From patchwork Sun May 30 08:58:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93550 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3F649A0524; Sun, 30 May 2021 11:00:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 57EF240E01; Sun, 30 May 2021 11:00:29 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 93CCE40DFB for ; Sun, 30 May 2021 11:00:27 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id AB5387DC2; Sun, 30 May 2021 02:00:25 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com AB5387DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365227; bh=OqtPpkxyU4mSMDSEMtVlCAOWrPrtK6kml+9jr5yFTRg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IPn/ycyWsPgtmM2OEKWaDDOS0wZofTd2JVbU4z4P0GtUVRm+CgaXLWRfyFo99Ilk9 c4BF8vNrydS/QhS03N0or8WAq4iJDDc1t0YepPDIu/GjnE5aIjy0qBED6lU7M0Y4cl ug7eBuJGyQkgUQeRbv9sEoAXR8lKeQA5CYCkwhL8= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jeffrey Huang , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:32 +0530 Message-Id: <20210530085929.29695-2-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 01/58] net/bnxt: add CFA folder to HCAPI directory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jeffrey Huang Before introducing more HCAPI components to DPDK, the CFA code needs to be organized into a dedicated folder so it is separated from other new HCAPI components Signed-off-by: Jeffrey Huang Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith --- drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa.h | 14 - .../net/bnxt/hcapi/{ => cfa}/hcapi_cfa_defs.h | 8 +- .../net/bnxt/hcapi/{ => cfa}/hcapi_cfa_p4.c | 0 .../net/bnxt/hcapi/{ => cfa}/hcapi_cfa_p4.h | 2 - drivers/net/bnxt/hcapi/cfa/meson.build | 10 + drivers/net/bnxt/hcapi/cfa_p40_hw.h | 781 ------------------ drivers/net/bnxt/hcapi/cfa_p40_tbl.h | 303 ------- drivers/net/bnxt/meson.build | 65 +- drivers/net/bnxt/tf_core/meson.build | 33 + drivers/net/bnxt/tf_core/tf_core.h | 2 +- drivers/net/bnxt/tf_core/tf_em.h | 2 +- drivers/net/bnxt/tf_ulp/meson.build | 28 + 12 files changed, 89 insertions(+), 1159 deletions(-) rename drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa.h (96%) rename drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa_defs.h (98%) rename drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa_p4.c (100%) rename drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa_p4.h (99%) create mode 100644 drivers/net/bnxt/hcapi/cfa/meson.build delete mode 100644 drivers/net/bnxt/hcapi/cfa_p40_hw.h delete mode 100644 drivers/net/bnxt/hcapi/cfa_p40_tbl.h create mode 100644 drivers/net/bnxt/tf_core/meson.build create mode 100644 drivers/net/bnxt/tf_ulp/meson.build diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h similarity index 96% rename from drivers/net/bnxt/hcapi/hcapi_cfa.h rename to drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h index c58092e72d..b8c85a0fca 100644 --- a/drivers/net/bnxt/hcapi/hcapi_cfa.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h @@ -14,20 +14,6 @@ #include "hcapi_cfa_defs.h" -#if CHIP_CFG == SR_A -#define SUPPORT_CFA_HW_P45 1 -#undef SUPPORT_CFA_HW_P4 -#define SUPPORT_CFA_HW_P4 0 -#elif CHIP_CFG == CMB_A -#define SUPPORT_CFA_HW_P4 1 -#else -#error "Chip not supported" -#endif - -#if SUPPORT_CFA_HW_P4 && SUPPORT_CFA_HW_P58 && SUPPORT_CFA_HW_P59 -#define SUPPORT_CFA_HW_ALL 1 -#endif - /** * Index used for the sram_entries field */ diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa_defs.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h similarity index 98% rename from drivers/net/bnxt/hcapi/hcapi_cfa_defs.h rename to drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h index b3d6892b0b..08f098ec86 100644 --- a/drivers/net/bnxt/hcapi/hcapi_cfa_defs.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h @@ -17,11 +17,6 @@ #include #include -#define SUPPORT_CFA_HW_ALL 0 -#define SUPPORT_CFA_HW_P4 1 -#define SUPPORT_CFA_HW_P58 0 -#define SUPPORT_CFA_HW_P59 0 - #define CFA_BITS_PER_BYTE (8) #define __CFA_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) #define CFA_ALIGN(x, a) __CFA_ALIGN_MASK(x, (a) - 1) @@ -49,8 +44,7 @@ enum hcapi_cfa_ver { HCAPI_CFA_P40 = 0, /**< CFA phase 4.0 */ HCAPI_CFA_P45 = 1, /**< CFA phase 4.5 */ HCAPI_CFA_P58 = 2, /**< CFA phase 5.8 */ - HCAPI_CFA_P59 = 3, /**< CFA phase 5.9 */ - HCAPI_CFA_PMAX = 4 + HCAPI_CFA_PMAX = 3 }; /** diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa_p4.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c similarity index 100% rename from drivers/net/bnxt/hcapi/hcapi_cfa_p4.c rename to drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa_p4.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h similarity index 99% rename from drivers/net/bnxt/hcapi/hcapi_cfa_p4.h rename to drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h index 305c83bc9f..74a5483c0b 100644 --- a/drivers/net/bnxt/hcapi/hcapi_cfa_p4.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h @@ -6,8 +6,6 @@ #ifndef _HCAPI_CFA_P4_H_ #define _HCAPI_CFA_P4_H_ -#include "cfa_p40_hw.h" - /** CFA phase 4 fix formatted table(layout) ID definition * */ diff --git a/drivers/net/bnxt/hcapi/cfa/meson.build b/drivers/net/bnxt/hcapi/cfa/meson.build new file mode 100644 index 0000000000..8b70d273f4 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa/meson.build @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Intel Corporation +# Copyright(c) 2021 Broadcom + +#Include the folder for headers +includes += include_directories('.') + +#Add the source files +sources += files( + 'hcapi_cfa_p4.c') diff --git a/drivers/net/bnxt/hcapi/cfa_p40_hw.h b/drivers/net/bnxt/hcapi/cfa_p40_hw.h deleted file mode 100644 index 5e32529886..0000000000 --- a/drivers/net/bnxt/hcapi/cfa_p40_hw.h +++ /dev/null @@ -1,781 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ -/* - * Name: cfa_p40_hw.h - * - * Description: header for SWE based on Truflow - * - * Date: taken from 12/16/19 17:18:12 - * - * Note: This file was first generated using tflib_decode.py. - * - * Changes have been made due to lack of availability of xml for - * additional tables at this time (EEM Record and union table fields) - * Changes not autogenerated are noted in comments. - */ - -#ifndef _CFA_P40_HW_H_ -#define _CFA_P40_HW_H_ - -/** - * Valid TCAM entry. (for idx 5 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_VALID_BITPOS 166 -#define CFA_P40_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1 -/** - * Key type (pass). (for idx 5 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_BITPOS 164 -#define CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_NUM_BITS 2 -/** - * Tunnel HDR type. (for idx 5 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_BITPOS 160 -#define CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_NUM_BITS 4 -/** - * Number of VLAN tags in tunnel l2 header. (for idx 4 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_BITPOS 158 -#define CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_NUM_BITS 2 -/** - * Number of VLAN tags in l2 header. (for idx 4 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_BITPOS 156 -#define CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_NUM_BITS 2 -/** - * Tunnel/Inner Source/Dest. MAC Address. - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_MAC1_BITPOS 108 -#define CFA_P40_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS 48 -/** - * Tunnel Outer VLAN Tag ID. (for idx 3 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_BITPOS 96 -#define CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_NUM_BITS 12 -/** - * Tunnel Inner VLAN Tag ID. (for idx 2 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_BITPOS 84 -#define CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_NUM_BITS 12 -/** - * Source Partition. (for idx 2 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_BITPOS 80 -#define CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS 4 -/** - * Source Virtual I/F. (for idx 2 ...) - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_SVIF_BITPOS 72 -#define CFA_P40_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS 8 -/** - * Tunnel/Inner Source/Dest. MAC Address. - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_MAC0_BITPOS 24 -#define CFA_P40_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS 48 -/** - * Outer VLAN Tag ID. - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_OVID_BITPOS 12 -#define CFA_P40_PROF_L2_CTXT_TCAM_OVID_NUM_BITS 12 -/** - * Inner VLAN Tag ID. - */ -#define CFA_P40_PROF_L2_CTXT_TCAM_IVID_BITPOS 0 -#define CFA_P40_PROF_L2_CTXT_TCAM_IVID_NUM_BITS 12 - -enum cfa_p40_prof_l2_ctxt_tcam_flds { - CFA_P40_PROF_L2_CTXT_TCAM_VALID_FLD = 0, - CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_FLD = 1, - CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_FLD = 2, - CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_FLD = 3, - CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_FLD = 4, - CFA_P40_PROF_L2_CTXT_TCAM_MAC1_FLD = 5, - CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_FLD = 6, - CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_FLD = 7, - CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_FLD = 8, - CFA_P40_PROF_L2_CTXT_TCAM_SVIF_FLD = 9, - CFA_P40_PROF_L2_CTXT_TCAM_MAC0_FLD = 10, - CFA_P40_PROF_L2_CTXT_TCAM_OVID_FLD = 11, - CFA_P40_PROF_L2_CTXT_TCAM_IVID_FLD = 12, - CFA_P40_PROF_L2_CTXT_TCAM_MAX_FLD -}; - -#define CFA_P40_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 167 - -/** - * Valid entry. (for idx 2 ...) - */ -#define CFA_P40_ACT_VEB_TCAM_VALID_BITPOS 79 -#define CFA_P40_ACT_VEB_TCAM_VALID_NUM_BITS 1 -/** - * reserved program to 0. (for idx 2 ...) - */ -#define CFA_P40_ACT_VEB_TCAM_RESERVED_BITPOS 78 -#define CFA_P40_ACT_VEB_TCAM_RESERVED_NUM_BITS 1 -/** - * PF Parif Number. (for idx 2 ...) - */ -#define CFA_P40_ACT_VEB_TCAM_PARIF_IN_BITPOS 74 -#define CFA_P40_ACT_VEB_TCAM_PARIF_IN_NUM_BITS 4 -/** - * Number of VLAN Tags. (for idx 2 ...) - */ -#define CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_BITPOS 72 -#define CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_NUM_BITS 2 -/** - * Dest. MAC Address. - */ -#define CFA_P40_ACT_VEB_TCAM_MAC_BITPOS 24 -#define CFA_P40_ACT_VEB_TCAM_MAC_NUM_BITS 48 -/** - * Outer VLAN Tag ID. - */ -#define CFA_P40_ACT_VEB_TCAM_OVID_BITPOS 12 -#define CFA_P40_ACT_VEB_TCAM_OVID_NUM_BITS 12 -/** - * Inner VLAN Tag ID. - */ -#define CFA_P40_ACT_VEB_TCAM_IVID_BITPOS 0 -#define CFA_P40_ACT_VEB_TCAM_IVID_NUM_BITS 12 - -enum cfa_p40_act_veb_tcam_flds { - CFA_P40_ACT_VEB_TCAM_VALID_FLD = 0, - CFA_P40_ACT_VEB_TCAM_RESERVED_FLD = 1, - CFA_P40_ACT_VEB_TCAM_PARIF_IN_FLD = 2, - CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_FLD = 3, - CFA_P40_ACT_VEB_TCAM_MAC_FLD = 4, - CFA_P40_ACT_VEB_TCAM_OVID_FLD = 5, - CFA_P40_ACT_VEB_TCAM_IVID_FLD = 6, - CFA_P40_ACT_VEB_TCAM_MAX_FLD -}; - -#define CFA_P40_ACT_VEB_TCAM_TOTAL_NUM_BITS 80 - -/** - * Entry is valid. - */ -#define CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_BITPOS 18 -#define CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_NUM_BITS 1 -/** - * Action Record Pointer - */ -#define CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_BITPOS 2 -#define CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_NUM_BITS 16 -/** - * for resolving TCAM/EM conflicts - */ -#define CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_BITPOS 0 -#define CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_NUM_BITS 2 - -enum cfa_p40_lkup_tcam_record_mem_flds { - CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_FLD = 0, - CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_FLD = 1, - CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_FLD = 2, - CFA_P40_LKUP_TCAM_RECORD_MEM_MAX_FLD -}; - -#define CFA_P40_LKUP_TCAM_RECORD_MEM_TOTAL_NUM_BITS 19 - -/** - * (for idx 1 ...) - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_BITPOS 62 -#define CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_NUM_BITS 2 -enum cfa_p40_prof_ctxt_remap_mem_tpid_anti_spoof_ctl { - CFA_P40_PROF_CTXT_REMAP_MEM_TPID_IGNORE = 0x0UL, - - CFA_P40_PROF_CTXT_REMAP_MEM_TPID_DROP = 0x1UL, - - CFA_P40_PROF_CTXT_REMAP_MEM_TPID_DEFAULT = 0x2UL, - - CFA_P40_PROF_CTXT_REMAP_MEM_TPID_SPIF = 0x3UL, - CFA_P40_PROF_CTXT_REMAP_MEM_TPID_MAX = 0x3UL -}; -/** - * (for idx 1 ...) - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_BITPOS 60 -#define CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_NUM_BITS 2 -enum cfa_p40_prof_ctxt_remap_mem_pri_anti_spoof_ctl { - CFA_P40_PROF_CTXT_REMAP_MEM_PRI_IGNORE = 0x0UL, - - CFA_P40_PROF_CTXT_REMAP_MEM_PRI_DROP = 0x1UL, - - CFA_P40_PROF_CTXT_REMAP_MEM_PRI_DEFAULT = 0x2UL, - - CFA_P40_PROF_CTXT_REMAP_MEM_PRI_SPIF = 0x3UL, - CFA_P40_PROF_CTXT_REMAP_MEM_PRI_MAX = 0x3UL -}; -/** - * Bypass Source Properties Lookup. (for idx 1 ...) - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_BITPOS 59 -#define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_NUM_BITS 1 -/** - * SP Record Pointer. (for idx 1 ...) - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_BITPOS 43 -#define CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_NUM_BITS 16 -/** - * BD Action pointer passing enable. (for idx 1 ...) - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_BITPOS 42 -#define CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_NUM_BITS 1 -/** - * Default VLAN TPID. (for idx 1 ...) - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_BITPOS 39 -#define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_NUM_BITS 3 -/** - * Allowed VLAN TPIDs. (for idx 1 ...) - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_BITPOS 33 -#define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_NUM_BITS 6 -/** - * Default VLAN PRI. - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_BITPOS 30 -#define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_NUM_BITS 3 -/** - * Allowed VLAN PRIs. - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_BITPOS 22 -#define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_NUM_BITS 8 -/** - * Partition. - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_BITPOS 18 -#define CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_NUM_BITS 4 -/** - * Bypass Lookup. - */ -#define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_BITPOS 17 -#define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_NUM_BITS 1 - -/** - * L2 Context Remap Data. Action bypass mode (1) {7'd0,prof_vnic[9:0]} Note: - * should also set byp_lkup_en. Action bypass mode (0) byp_lkup_en(0) - - * {prof_func[6:0],l2_context[9:0]} byp_lkup_en(1) - {1'b0,act_rec_ptr[15:0]} - */ - -#define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_BITPOS 0 -#define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_NUM_BITS 12 - -#define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_BITPOS 10 -#define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_NUM_BITS 7 - -#define CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_BITPOS 0 -#define CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_NUM_BITS 10 - -#define CFA_P40_PROF_CTXT_REMAP_MEM_ARP_BITPOS 0 -#define CFA_P40_PROF_CTXT_REMAP_MEM_ARP_NUM_BITS 16 - -enum cfa_p40_prof_ctxt_remap_mem_flds { - CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_FLD = 0, - CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_FLD = 1, - CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_FLD = 2, - CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_FLD = 3, - CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_FLD = 4, - CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_FLD = 5, - CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_FLD = 6, - CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_FLD = 7, - CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_FLD = 8, - CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_FLD = 9, - CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_FLD = 10, - CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_FLD = 11, - CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_FLD = 12, - CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_FLD = 13, - CFA_P40_PROF_CTXT_REMAP_MEM_ARP_FLD = 14, - CFA_P40_PROF_CTXT_REMAP_MEM_MAX_FLD -}; - -#define CFA_P40_PROF_CTXT_REMAP_MEM_TOTAL_NUM_BITS 64 - -/** - * Bypass action pointer look up (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_BITPOS 37 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_NUM_BITS 1 -/** - * Exact match search enable (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_BITPOS 36 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_NUM_BITS 1 -/** - * Exact match profile - */ -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_BITPOS 28 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_NUM_BITS 8 -/** - * Exact match key format - */ -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_BITPOS 23 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_NUM_BITS 5 -/** - * Exact match key mask - */ -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_BITPOS 13 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_NUM_BITS 10 -/** - * TCAM search enable - */ -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_BITPOS 12 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_NUM_BITS 1 -/** - * TCAM profile - */ -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_BITPOS 4 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_NUM_BITS 8 -/** - * TCAM key format - */ -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_BITPOS 0 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_NUM_BITS 4 - -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_BITPOS 16 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_NUM_BITS 2 - -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_BITPOS 0 -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_NUM_BITS 16 - -enum cfa_p40_prof_profile_tcam_remap_mem_flds { - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_FLD = 0, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_FLD = 1, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_FLD = 2, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_FLD = 3, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_FLD = 4, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_FLD = 5, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_FLD = 6, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_FLD = 7, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_FLD = 8, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_FLD = 9, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_MAX_FLD -}; - -#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TOTAL_NUM_BITS 38 - -/** - * Valid TCAM entry (for idx 2 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_VALID_BITPOS 80 -#define CFA_P40_PROF_PROFILE_TCAM_VALID_NUM_BITS 1 -/** - * Packet type (for idx 2 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_BITPOS 76 -#define CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_NUM_BITS 4 -/** - * Pass through CFA (for idx 2 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_BITPOS 74 -#define CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_NUM_BITS 2 -/** - * Aggregate error (for idx 2 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_BITPOS 73 -#define CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_NUM_BITS 1 -/** - * Profile function (for idx 2 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_BITPOS 66 -#define CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_NUM_BITS 7 -/** - * Reserved for future use. Set to 0. - */ -#define CFA_P40_PROF_PROFILE_TCAM_RESERVED_BITPOS 57 -#define CFA_P40_PROF_PROFILE_TCAM_RESERVED_NUM_BITS 9 -/** - * non-tunnel(0)/tunneled(1) packet (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_BITPOS 56 -#define CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_NUM_BITS 1 -/** - * Tunnel L2 tunnel valid (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_BITPOS 55 -#define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_NUM_BITS 1 -/** - * Tunnel L2 header type (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_BITPOS 53 -#define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_NUM_BITS 2 -/** - * Remapped tunnel L2 dest_type UC(0)/MC(2)/BC(3) (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_BITPOS 51 -#define CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_NUM_BITS 2 -/** - * Tunnel L2 1+ VLAN tags present (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_BITPOS 50 -#define CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_NUM_BITS 1 -/** - * Tunnel L2 2 VLAN tags present (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_BITPOS 49 -#define CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_NUM_BITS 1 -/** - * Tunnel L3 valid (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_BITPOS 48 -#define CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_NUM_BITS 1 -/** - * Tunnel L3 error (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_BITPOS 47 -#define CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_NUM_BITS 1 -/** - * Tunnel L3 header type (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_BITPOS 43 -#define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_NUM_BITS 4 -/** - * Tunnel L3 header is IPV4 or IPV6. (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_BITPOS 42 -#define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_NUM_BITS 1 -/** - * Tunnel L3 IPV6 src address is compressed (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_BITPOS 41 -#define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_NUM_BITS 1 -/** - * Tunnel L3 IPV6 dest address is compressed (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_BITPOS 40 -#define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_NUM_BITS 1 -/** - * Tunnel L4 valid (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_BITPOS 39 -#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_NUM_BITS 1 -/** - * Tunnel L4 error (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_BITPOS 38 -#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_NUM_BITS 1 -/** - * Tunnel L4 header type (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_BITPOS 34 -#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_NUM_BITS 4 -/** - * Tunnel L4 header is UDP or TCP (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_BITPOS 33 -#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_NUM_BITS 1 -/** - * Tunnel valid (for idx 1 ...) - */ -#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_BITPOS 32 -#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_NUM_BITS 1 -/** - * Tunnel error - */ -#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_BITPOS 31 -#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_NUM_BITS 1 -/** - * Tunnel header type - */ -#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_BITPOS 27 -#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_NUM_BITS 4 -/** - * Tunnel header flags - */ -#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_BITPOS 24 -#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_NUM_BITS 3 -/** - * L2 header valid - */ -#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_BITPOS 23 -#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_NUM_BITS 1 -/** - * L2 header error - */ -#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_BITPOS 22 -#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_NUM_BITS 1 -/** - * L2 header type - */ -#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_BITPOS 20 -#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_NUM_BITS 2 -/** - * Remapped L2 dest_type UC(0)/MC(2)/BC(3) - */ -#define CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_BITPOS 18 -#define CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_NUM_BITS 2 -/** - * L2 header 1+ VLAN tags present - */ -#define CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_BITPOS 17 -#define CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_NUM_BITS 1 -/** - * L2 header 2 VLAN tags present - */ -#define CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_BITPOS 16 -#define CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_NUM_BITS 1 -/** - * L3 header valid - */ -#define CFA_P40_PROF_PROFILE_TCAM_L3_VALID_BITPOS 15 -#define CFA_P40_PROF_PROFILE_TCAM_L3_VALID_NUM_BITS 1 -/** - * L3 header error - */ -#define CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_BITPOS 14 -#define CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_NUM_BITS 1 -/** - * L3 header type - */ -#define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_BITPOS 10 -#define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_NUM_BITS 4 -/** - * L3 header is IPV4 or IPV6. - */ -#define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_BITPOS 9 -#define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_NUM_BITS 1 -/** - * L3 header IPV6 src address is compressed - */ -#define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_BITPOS 8 -#define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_NUM_BITS 1 -/** - * L3 header IPV6 dest address is compressed - */ -#define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_BITPOS 7 -#define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_NUM_BITS 1 -/** - * L4 header valid - */ -#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_BITPOS 6 -#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_NUM_BITS 1 -/** - * L4 header error - */ -#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_BITPOS 5 -#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_NUM_BITS 1 -/** - * L4 header type - */ -#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_BITPOS 1 -#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_NUM_BITS 4 -/** - * L4 header is UDP or TCP - */ -#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_BITPOS 0 -#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_NUM_BITS 1 - -enum cfa_p40_prof_profile_tcam_flds { - CFA_P40_PROF_PROFILE_TCAM_VALID_FLD = 0, - CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 1, - CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_FLD = 2, - CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 3, - CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 4, - CFA_P40_PROF_PROFILE_TCAM_RESERVED_FLD = 5, - CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 6, - CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 7, - CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 8, - CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 9, - CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 10, - CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 11, - CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_FLD = 12, - CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_FLD = 13, - CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 14, - CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 15, - CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_FLD = 16, - CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_FLD = 17, - CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 18, - CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 19, - CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 20, - CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 21, - CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 22, - CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_FLD = 23, - CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 24, - CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 25, - CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 26, - CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 27, - CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 28, - CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 29, - CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 30, - CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 31, - CFA_P40_PROF_PROFILE_TCAM_L3_VALID_FLD = 32, - CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_FLD = 33, - CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 34, - CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 35, - CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_FLD = 36, - CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_FLD = 37, - CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 38, - CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 39, - CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 40, - CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 41, - CFA_P40_PROF_PROFILE_TCAM_MAX_FLD -}; - -#define CFA_P40_PROF_PROFILE_TCAM_TOTAL_NUM_BITS 81 - -/** - * CFA flexible key layout definition - */ -enum cfa_p40_key_fld_id { - CFA_P40_KEY_FLD_ID_MAX -}; - -/**************************************************************************/ -/** - * Non-autogenerated fields - */ - -/** - * Valid - */ -#define CFA_P40_EEM_KEY_TBL_VALID_BITPOS 0 -#define CFA_P40_EEM_KEY_TBL_VALID_NUM_BITS 1 - -/** - * L1 Cacheable - */ -#define CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_BITPOS 1 -#define CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_NUM_BITS 1 - -/** - * Strength - */ -#define CFA_P40_EEM_KEY_TBL_STRENGTH_BITPOS 2 -#define CFA_P40_EEM_KEY_TBL_STRENGTH_NUM_BITS 2 - -/** - * Key Size - */ -#define CFA_P40_EEM_KEY_TBL_KEY_SZ_BITPOS 15 -#define CFA_P40_EEM_KEY_TBL_KEY_SZ_NUM_BITS 9 - -/** - * Record Size - */ -#define CFA_P40_EEM_KEY_TBL_REC_SZ_BITPOS 24 -#define CFA_P40_EEM_KEY_TBL_REC_SZ_NUM_BITS 5 - -/** - * Action Record Internal - */ -#define CFA_P40_EEM_KEY_TBL_ACT_REC_INT_BITPOS 29 -#define CFA_P40_EEM_KEY_TBL_ACT_REC_INT_NUM_BITS 1 - -/** - * External Flow Counter - */ -#define CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_BITPOS 30 -#define CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_NUM_BITS 1 - -/** - * Action Record Pointer - */ -#define CFA_P40_EEM_KEY_TBL_AR_PTR_BITPOS 31 -#define CFA_P40_EEM_KEY_TBL_AR_PTR_NUM_BITS 33 - -/** - * EEM Key omitted - create using keybuilder - * Fields here cannot be larger than a uint64_t - */ - -#define CFA_P40_EEM_KEY_TBL_TOTAL_NUM_BITS 64 - -enum cfa_p40_eem_key_tbl_flds { - CFA_P40_EEM_KEY_TBL_VALID_FLD = 0, - CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_FLD = 1, - CFA_P40_EEM_KEY_TBL_STRENGTH_FLD = 2, - CFA_P40_EEM_KEY_TBL_KEY_SZ_FLD = 3, - CFA_P40_EEM_KEY_TBL_REC_SZ_FLD = 4, - CFA_P40_EEM_KEY_TBL_ACT_REC_INT_FLD = 5, - CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_FLD = 6, - CFA_P40_EEM_KEY_TBL_AR_PTR_FLD = 7, - CFA_P40_EEM_KEY_TBL_MAX_FLD -}; - -/** - * Mirror Destination 0 Source Property Record Pointer - */ -#define CFA_P40_MIRROR_TBL_SP_PTR_BITPOS 0 -#define CFA_P40_MIRROR_TBL_SP_PTR_NUM_BITS 11 - -/** - * ignore or honor drop - */ -#define CFA_P40_MIRROR_TBL_IGN_DROP_BITPOS 13 -#define CFA_P40_MIRROR_TBL_IGN_DROP_NUM_BITS 1 - -/** - * ingress or egress copy - */ -#define CFA_P40_MIRROR_TBL_COPY_BITPOS 14 -#define CFA_P40_MIRROR_TBL_COPY_NUM_BITS 1 - -/** - * Mirror Destination enable. - */ -#define CFA_P40_MIRROR_TBL_EN_BITPOS 15 -#define CFA_P40_MIRROR_TBL_EN_NUM_BITS 1 - -/** - * Action Record Pointer - */ -#define CFA_P40_MIRROR_TBL_AR_PTR_BITPOS 16 -#define CFA_P40_MIRROR_TBL_AR_PTR_NUM_BITS 16 - -#define CFA_P40_MIRROR_TBL_TOTAL_NUM_BITS 32 - -enum cfa_p40_mirror_tbl_flds { - CFA_P40_MIRROR_TBL_SP_PTR_FLD = 0, - CFA_P40_MIRROR_TBL_IGN_DROP_FLD = 1, - CFA_P40_MIRROR_TBL_COPY_FLD = 2, - CFA_P40_MIRROR_TBL_EN_FLD = 3, - CFA_P40_MIRROR_TBL_AR_PTR_FLD = 4, - CFA_P40_MIRROR_TBL_MAX_FLD -}; - -/** - * P45 Specific Updates (SR) - Non-autogenerated - */ -/** - * Valid TCAM entry. - */ -#define CFA_P45_PROF_L2_CTXT_TCAM_VALID_BITPOS 166 -#define CFA_P45_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1 -/** - * Source Partition. - */ -#define CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_BITPOS 166 -#define CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS 4 - -/** - * Source Virtual I/F. - */ -#define CFA_P45_PROF_L2_CTXT_TCAM_SVIF_BITPOS 72 -#define CFA_P45_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS 12 - - -/* The SR layout of the l2 ctxt key is different from the Wh+. Switch to - * cfa_p45_hw.h definition when available. - */ -enum cfa_p45_prof_l2_ctxt_tcam_flds { - CFA_P45_PROF_L2_CTXT_TCAM_VALID_FLD = 0, - CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_FLD = 1, - CFA_P45_PROF_L2_CTXT_TCAM_KEY_TYPE_FLD = 2, - CFA_P45_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_FLD = 3, - CFA_P45_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_FLD = 4, - CFA_P45_PROF_L2_CTXT_TCAM_L2_NUMTAGS_FLD = 5, - CFA_P45_PROF_L2_CTXT_TCAM_MAC1_FLD = 6, - CFA_P45_PROF_L2_CTXT_TCAM_T_OVID_FLD = 7, - CFA_P45_PROF_L2_CTXT_TCAM_T_IVID_FLD = 8, - CFA_P45_PROF_L2_CTXT_TCAM_SVIF_FLD = 9, - CFA_P45_PROF_L2_CTXT_TCAM_MAC0_FLD = 10, - CFA_P45_PROF_L2_CTXT_TCAM_OVID_FLD = 11, - CFA_P45_PROF_L2_CTXT_TCAM_IVID_FLD = 12, - CFA_P45_PROF_L2_CTXT_TCAM_MAX_FLD -}; - -#define CFA_P45_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 171 - -#endif /* _CFA_P40_HW_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_p40_tbl.h b/drivers/net/bnxt/hcapi/cfa_p40_tbl.h deleted file mode 100644 index 539241ad0e..0000000000 --- a/drivers/net/bnxt/hcapi/cfa_p40_tbl.h +++ /dev/null @@ -1,303 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ -/* - * Name: cfa_p40_tbl.h - * - * Description: header for SWE based on Truflow - * - * Date: 12/16/19 17:18:12 - * - * Note: This file was originally generated by tflib_decode.py. - * Remainder is hand coded due to lack of availability of xml for - * additional tables at this time (EEM Record and union fields) - * - **/ -#ifndef _CFA_P40_TBL_H_ -#define _CFA_P40_TBL_H_ - -#include "cfa_p40_hw.h" - -#include "hcapi_cfa_defs.h" - -const struct hcapi_cfa_field cfa_p40_prof_l2_ctxt_tcam_layout[] = { - {CFA_P40_PROF_L2_CTXT_TCAM_VALID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_VALID_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_MAC1_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_SVIF_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_MAC0_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_OVID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_OVID_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_IVID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_IVID_NUM_BITS}, -}; - -const struct hcapi_cfa_field cfa_p40_act_veb_tcam_layout[] = { - {CFA_P40_ACT_VEB_TCAM_VALID_BITPOS, - CFA_P40_ACT_VEB_TCAM_VALID_NUM_BITS}, - {CFA_P40_ACT_VEB_TCAM_RESERVED_BITPOS, - CFA_P40_ACT_VEB_TCAM_RESERVED_NUM_BITS}, - {CFA_P40_ACT_VEB_TCAM_PARIF_IN_BITPOS, - CFA_P40_ACT_VEB_TCAM_PARIF_IN_NUM_BITS}, - {CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_BITPOS, - CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_NUM_BITS}, - {CFA_P40_ACT_VEB_TCAM_MAC_BITPOS, - CFA_P40_ACT_VEB_TCAM_MAC_NUM_BITS}, - {CFA_P40_ACT_VEB_TCAM_OVID_BITPOS, - CFA_P40_ACT_VEB_TCAM_OVID_NUM_BITS}, - {CFA_P40_ACT_VEB_TCAM_IVID_BITPOS, - CFA_P40_ACT_VEB_TCAM_IVID_NUM_BITS}, -}; - -const struct hcapi_cfa_field cfa_p40_lkup_tcam_record_mem_layout[] = { - {CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_BITPOS, - CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_NUM_BITS}, - {CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_BITPOS, - CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_NUM_BITS}, - {CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_BITPOS, - CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_NUM_BITS}, -}; - -const struct hcapi_cfa_field cfa_p40_prof_ctxt_remap_mem_layout[] = { - {CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_NUM_BITS}, - /* Fields below not generated through automation */ - {CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_NUM_BITS}, - {CFA_P40_PROF_CTXT_REMAP_MEM_ARP_BITPOS, - CFA_P40_PROF_CTXT_REMAP_MEM_ARP_NUM_BITS}, -}; - -const struct hcapi_cfa_field cfa_p40_prof_profile_tcam_remap_mem_layout[] = { - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_NUM_BITS}, - /* Fields below not generated through automation */ - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_NUM_BITS}, -}; - -const struct hcapi_cfa_field cfa_p40_prof_profile_tcam_layout[] = { - {CFA_P40_PROF_PROFILE_TCAM_VALID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_VALID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_RESERVED_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_RESERVED_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L3_VALID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L3_VALID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_BITPOS, - CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_NUM_BITS}, -}; - -/**************************************************************************/ -/** - * Non-autogenerated fields - */ - -const struct hcapi_cfa_field cfa_p40_eem_key_tbl_layout[] = { - {CFA_P40_EEM_KEY_TBL_VALID_BITPOS, - CFA_P40_EEM_KEY_TBL_VALID_NUM_BITS}, - - {CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_BITPOS, - CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_NUM_BITS}, - - {CFA_P40_EEM_KEY_TBL_STRENGTH_BITPOS, - CFA_P40_EEM_KEY_TBL_STRENGTH_NUM_BITS}, - - {CFA_P40_EEM_KEY_TBL_KEY_SZ_BITPOS, - CFA_P40_EEM_KEY_TBL_KEY_SZ_NUM_BITS}, - - {CFA_P40_EEM_KEY_TBL_REC_SZ_BITPOS, - CFA_P40_EEM_KEY_TBL_REC_SZ_NUM_BITS}, - - {CFA_P40_EEM_KEY_TBL_ACT_REC_INT_BITPOS, - CFA_P40_EEM_KEY_TBL_ACT_REC_INT_NUM_BITS}, - - {CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_BITPOS, - CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_NUM_BITS}, - - {CFA_P40_EEM_KEY_TBL_AR_PTR_BITPOS, - CFA_P40_EEM_KEY_TBL_AR_PTR_NUM_BITS}, - -}; - -const struct hcapi_cfa_field cfa_p40_mirror_tbl_layout[] = { - {CFA_P40_MIRROR_TBL_SP_PTR_BITPOS, - CFA_P40_MIRROR_TBL_SP_PTR_NUM_BITS}, - - {CFA_P40_MIRROR_TBL_IGN_DROP_BITPOS, - CFA_P40_MIRROR_TBL_IGN_DROP_NUM_BITS}, - - {CFA_P40_MIRROR_TBL_COPY_BITPOS, - CFA_P40_MIRROR_TBL_COPY_NUM_BITS}, - - {CFA_P40_MIRROR_TBL_EN_BITPOS, - CFA_P40_MIRROR_TBL_EN_NUM_BITS}, - - {CFA_P40_MIRROR_TBL_AR_PTR_BITPOS, - CFA_P40_MIRROR_TBL_AR_PTR_NUM_BITS}, -}; - -/* P45 Defines */ - -const struct hcapi_cfa_field cfa_p45_prof_l2_ctxt_tcam_layout[] = { - {CFA_P45_PROF_L2_CTXT_TCAM_VALID_BITPOS, - CFA_P45_PROF_L2_CTXT_TCAM_VALID_NUM_BITS}, - {CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_BITPOS, - CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_MAC1_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_NUM_BITS}, - {CFA_P45_PROF_L2_CTXT_TCAM_SVIF_BITPOS, - CFA_P45_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_MAC0_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_OVID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_OVID_NUM_BITS}, - {CFA_P40_PROF_L2_CTXT_TCAM_IVID_BITPOS, - CFA_P40_PROF_L2_CTXT_TCAM_IVID_NUM_BITS}, -}; -#endif /* _CFA_P40_TBL_H_ */ diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build index 117c753489..f7a4e7a013 100644 --- a/drivers/net/bnxt/meson.build +++ b/drivers/net/bnxt/meson.build @@ -8,10 +8,17 @@ if is_windows subdir_done() endif -headers = files('rte_pmd_bnxt.h') +cflags_options = [ + '-DSUPPORT_CFA_HW_ALL=1', +] + +foreach option:cflags_options + if cc.has_argument(option) + cflags += option + endif +endforeach -includes += include_directories('tf_ulp') -includes += include_directories('tf_core') +headers = files('rte_pmd_bnxt.h') sources = files( 'bnxt_cpr.c', @@ -30,53 +37,6 @@ sources = files( 'bnxt_vnic.c', 'bnxt_reps.c', - 'tf_core/tf_core.c', - 'tf_core/bitalloc.c', - 'tf_core/tf_msg.c', - 'tf_core/rand.c', - 'tf_core/stack.c', - 'tf_core/tf_em_common.c', - 'tf_core/tf_em_internal.c', - 'tf_core/tf_rm.c', - 'tf_core/tf_tbl.c', - 'tf_core/tfp.c', - 'tf_core/tf_session.c', - 'tf_core/tf_device.c', - 'tf_core/tf_device_p4.c', - 'tf_core/tf_identifier.c', - 'tf_core/tf_shadow_tbl.c', - 'tf_core/tf_shadow_tcam.c', - 'tf_core/tf_tcam.c', - 'tf_core/tf_util.c', - 'tf_core/tf_if_tbl.c', - 'tf_core/ll.c', - 'tf_core/tf_global_cfg.c', - 'tf_core/tf_em_host.c', - 'tf_core/tf_shadow_identifier.c', - 'tf_core/tf_hash.c', - - 'hcapi/hcapi_cfa_p4.c', - - 'tf_ulp/bnxt_ulp.c', - 'tf_ulp/ulp_mark_mgr.c', - 'tf_ulp/ulp_flow_db.c', - 'tf_ulp/ulp_template_db_tbl.c', - 'tf_ulp/ulp_template_db_class.c', - 'tf_ulp/ulp_template_db_act.c', - 'tf_ulp/ulp_utils.c', - 'tf_ulp/ulp_mapper.c', - 'tf_ulp/ulp_matcher.c', - 'tf_ulp/ulp_rte_parser.c', - 'tf_ulp/bnxt_ulp_flow.c', - 'tf_ulp/ulp_port_db.c', - 'tf_ulp/ulp_def_rules.c', - 'tf_ulp/ulp_fc_mgr.c', - 'tf_ulp/ulp_tun.c', - 'tf_ulp/ulp_template_db_wh_plus_act.c', - 'tf_ulp/ulp_template_db_wh_plus_class.c', - 'tf_ulp/ulp_template_db_stingray_act.c', - 'tf_ulp/ulp_template_db_stingray_class.c', - 'rte_pmd_bnxt.c', ) @@ -85,3 +45,8 @@ if arch_subdir == 'x86' elif arch_subdir == 'arm' and host_machine.cpu_family().startswith('aarch64') sources += files('bnxt_rxtx_vec_neon.c') endif + +#Add the subdirectories that need to be compiled +subdir('tf_ulp') +subdir('tf_core') +subdir('hcapi/cfa') diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build new file mode 100644 index 0000000000..b23e0fbe70 --- /dev/null +++ b/drivers/net/bnxt/tf_core/meson.build @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Intel Corporation +# Copyright(c) 2021 Broadcom + +#Include the folder for headers +includes += include_directories('.') + +#Add the source files +sources += files( + 'tf_core.c', + 'bitalloc.c', + 'tf_msg.c', + 'rand.c', + 'stack.c', + 'tf_em_common.c', + 'tf_em_internal.c', + 'tf_rm.c', + 'tf_tbl.c', + 'tfp.c', + 'tf_session.c', + 'tf_device.c', + 'tf_device_p4.c', + 'tf_identifier.c', + 'tf_shadow_tbl.c', + 'tf_shadow_tcam.c', + 'tf_tcam.c', + 'tf_util.c', + 'tf_if_tbl.c', + 'll.c', + 'tf_global_cfg.c', + 'tf_em_host.c', + 'tf_shadow_identifier.c', + 'tf_hash.c') diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index a47edff1e3..5e458c58fb 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -10,7 +10,7 @@ #include #include #include -#include "hcapi/hcapi_cfa_defs.h" +#include "hcapi/cfa/hcapi_cfa_defs.h" #include "tf_project.h" /** diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 23591272bd..b5c3acb09a 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -9,7 +9,7 @@ #include "tf_core.h" #include "tf_session.h" -#include "hcapi/hcapi_cfa_defs.h" +#include "hcapi/cfa/hcapi_cfa_defs.h" #define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */ #define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */ diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build new file mode 100644 index 0000000000..98cbdf3177 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/meson.build @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Intel Corporation +# Copyright(c) 2021 Broadcom + +#Include the folder for headers +includes += include_directories('.') + +#Add the source files +sources += files( + 'bnxt_ulp.c', + 'ulp_mark_mgr.c', + 'ulp_flow_db.c', + 'ulp_template_db_tbl.c', + 'ulp_template_db_class.c', + 'ulp_template_db_act.c', + 'ulp_utils.c', + 'ulp_mapper.c', + 'ulp_matcher.c', + 'ulp_rte_parser.c', + 'bnxt_ulp_flow.c', + 'ulp_port_db.c', + 'ulp_def_rules.c', + 'ulp_fc_mgr.c', + 'ulp_tun.c', + 'ulp_template_db_wh_plus_act.c', + 'ulp_template_db_wh_plus_class.c', + 'ulp_template_db_stingray_act.c', + 'ulp_template_db_stingray_class.c') From patchwork Sun May 30 08:58:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93551 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 255C7A0524; Sun, 30 May 2021 11:00:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D0AD640E64; Sun, 30 May 2021 11:00:32 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 8311040E0F for ; Sun, 30 May 2021 11:00:29 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 990407DAF; Sun, 30 May 2021 02:00:27 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 990407DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365229; bh=Pw4UWVJklp28XXqHfOp1ofjZDwuWjoy2zP4l1XAO+pU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W6aeyaYz9glQwRsoLNtFuPUk8IsYRr57cGx8ktyNE2SXwuNlVUXgudPHQTeysZeP/ y7CwJ8THSZb/dYpi0v4fwogK4BCbccHpy4Mbn0IzWRQ6zdzbiLxWRTVkHf6iGEVeg1 /6GPVkzrungANlqkqkAEotXGSPr+1TkXEAh8qKo0= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Peter Spreadborough , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:33 +0530 Message-Id: <20210530085929.29695-3-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 02/58] net/bnxt: add base TRUFLOW support for Thor X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith Add infrastructure code to support TRUFLOW on Thor NICs. Also update meson.build Signed-off-by: Farah Smith Signed-off-by: Peter Spreadborough Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_core/cfa_resource_types.h | 1 - drivers/net/bnxt/tf_core/meson.build | 1 + drivers/net/bnxt/tf_core/tf_core.c | 1 + drivers/net/bnxt/tf_core/tf_device.c | 207 +++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 24 ++ drivers/net/bnxt/tf_core/tf_device_p4.c | 111 ++++++- drivers/net/bnxt/tf_core/tf_device_p4.h | 3 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 284 ++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.h | 79 +++++ drivers/net/bnxt/tf_core/tf_em_common.c | 4 +- drivers/net/bnxt/tf_core/tf_msg.c | 33 -- drivers/net/bnxt/tf_core/tf_rm.c | 8 +- drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 4 +- 13 files changed, 711 insertions(+), 49 deletions(-) create mode 100644 drivers/net/bnxt/tf_core/tf_device_p58.c create mode 100644 drivers/net/bnxt/tf_core/tf_device_p58.h diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h index f55a98a388..b63b87bcf3 100644 --- a/drivers/net/bnxt/tf_core/cfa_resource_types.h +++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h @@ -254,5 +254,4 @@ #define CFA_RESOURCE_TYPE_P4_TBL_SCOPE 0x22UL #define CFA_RESOURCE_TYPE_P4_LAST CFA_RESOURCE_TYPE_P4_TBL_SCOPE - #endif /* _CFA_RESOURCE_TYPES_H_ */ diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index b23e0fbe70..d7e8f664fd 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -20,6 +20,7 @@ sources += files( 'tf_session.c', 'tf_device.c', 'tf_device_p4.c', + 'tf_device_p58.c', 'tf_identifier.c', 'tf_shadow_tbl.c', 'tf_shadow_tcam.c', diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index feec3cf459..b1ce4e721c 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -35,6 +35,7 @@ tf_open_session(struct tf *tfp, * firmware open session succeeds. */ if (parms->device_type != TF_DEVICE_TYPE_WH && + parms->device_type != TF_DEVICE_TYPE_THOR && parms->device_type != TF_DEVICE_TYPE_SR) { TFP_DRV_LOG(ERR, "Unsupported device type %d\n", diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index f68eb723fe..9c63f6d5d4 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -5,6 +5,7 @@ #include "tf_device.h" #include "tf_device_p4.h" +#include "tf_device_p58.h" #include "tfp.h" #include "tf_em.h" @@ -12,6 +13,7 @@ struct tf; /* Forward declarations */ static int tf_dev_unbind_p4(struct tf *tfp); +static int tf_dev_unbind_p58(struct tf *tfp); /** * Device specific bind function, WH+ @@ -234,6 +236,203 @@ tf_dev_unbind_p4(struct tf *tfp) return rc; } +/** + * Device specific bind function, THOR + * + * [in] tfp + * Pointer to TF handle + * + * [in] shadow_copy + * Flag controlling shadow copy DB creation + * + * [in] resources + * Pointer to resource allocation information + * + * [out] dev_handle + * Device handle + * + * Returns + * - (0) if successful. + * - (-EINVAL) on parameter or internal failure. + */ +static int +tf_dev_bind_p58(struct tf *tfp, + bool shadow_copy, + struct tf_session_resources *resources, + struct tf_dev_info *dev_handle) +{ + int rc; + int frc; + struct tf_ident_cfg_parms ident_cfg; + struct tf_tbl_cfg_parms tbl_cfg; + struct tf_tcam_cfg_parms tcam_cfg; + struct tf_em_cfg_parms em_cfg; + struct tf_if_tbl_cfg_parms if_tbl_cfg; + struct tf_global_cfg_cfg_parms global_cfg; + + /* Initial function initialization */ + dev_handle->ops = &tf_dev_ops_p58_init; + + /* Initialize the modules */ + + ident_cfg.num_elements = TF_IDENT_TYPE_MAX; + ident_cfg.cfg = tf_ident_p58; + ident_cfg.shadow_copy = shadow_copy; + ident_cfg.resources = resources; + rc = tf_ident_bind(tfp, &ident_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Identifier initialization failure\n"); + goto fail; + } + + tbl_cfg.num_elements = TF_TBL_TYPE_MAX; + tbl_cfg.cfg = tf_tbl_p58; + tbl_cfg.shadow_copy = shadow_copy; + tbl_cfg.resources = resources; + rc = tf_tbl_bind(tfp, &tbl_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Table initialization failure\n"); + goto fail; + } + + tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX; + tcam_cfg.cfg = tf_tcam_p58; + tcam_cfg.shadow_copy = shadow_copy; + tcam_cfg.resources = resources; + rc = tf_tcam_bind(tfp, &tcam_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "TCAM initialization failure\n"); + goto fail; + } + + /* + * EM + */ + em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; + em_cfg.cfg = tf_em_int_p58; + em_cfg.resources = resources; + em_cfg.mem_type = 0; /* Not used by EM */ + + rc = tf_em_int_bind(tfp, &em_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "EM initialization failure\n"); + goto fail; + } + + /* + * IF_TBL + */ + if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; + if_tbl_cfg.cfg = tf_if_tbl_p58; + if_tbl_cfg.shadow_copy = shadow_copy; + rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "IF Table initialization failure\n"); + goto fail; + } + + /* + * GLOBAL_CFG + */ + global_cfg.num_elements = TF_GLOBAL_CFG_TYPE_MAX; + global_cfg.cfg = tf_global_cfg_p58; + rc = tf_global_cfg_bind(tfp, &global_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Global Cfg initialization failure\n"); + goto fail; + } + + /* Final function initialization */ + dev_handle->ops = &tf_dev_ops_p58; + + return 0; + + fail: + /* Cleanup of already created modules */ + frc = tf_dev_unbind_p58(tfp); + if (frc) + return frc; + + return rc; +} + +/** + * Device specific unbind function, THOR + * + * [in] tfp + * Pointer to TF handle + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int + tf_dev_unbind_p58(struct tf *tfp) +{ + int rc = 0; + bool fail = false; + + /* Unbind all the support modules. As this is only done on + * close we only report errors as everything has to be cleaned + * up regardless. + * + * In case of residuals TCAMs are cleaned up first as to + * invalidate the pipeline in a clean manner. + */ + rc = tf_tcam_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, TCAM\n"); + fail = true; + } + + rc = tf_ident_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, Identifier\n"); + fail = true; + } + + rc = tf_tbl_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, Table Type\n"); + fail = true; + } + + rc = tf_em_int_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, EM\n"); + fail = true; + } + + rc = tf_if_tbl_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, IF Table Type\n"); + fail = true; + } + + rc = tf_global_cfg_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, Global Cfg Type\n"); + fail = true; + } + + if (fail) + return -1; + + return rc; +} + int tf_dev_bind(struct tf *tfp __rte_unused, enum tf_device_type type, @@ -249,6 +448,12 @@ tf_dev_bind(struct tf *tfp __rte_unused, shadow_copy, resources, dev_handle); + case TF_DEVICE_TYPE_THOR: + dev_handle->type = type; + return tf_dev_bind_p58(tfp, + shadow_copy, + resources, + dev_handle); default: TFP_DRV_LOG(ERR, "No such device\n"); @@ -264,6 +469,8 @@ tf_dev_unbind(struct tf *tfp, case TF_DEVICE_TYPE_WH: case TF_DEVICE_TYPE_SR: return tf_dev_unbind_p4(tfp); + case TF_DEVICE_TYPE_THOR: + return tf_dev_unbind_p58(tfp); default: TFP_DRV_LOG(ERR, "No such device\n"); diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index d0c4ec80d0..d5ef72309f 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -134,6 +134,28 @@ struct tf_dev_ops { int (*tf_dev_get_max_types)(struct tf *tfp, uint16_t *max_types); + /** + * Retrieves the string description for the CFA resource + * type + * + * [in] tfp + * Pointer to TF handle + * + * [in] resource_id + * HCAPI cfa resource type id + * + * [out] resource_str + * Pointer to a string + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_resource_str)(struct tf *tfp, + uint16_t resource_id, + const char **resource_str); + + /** * Retrieves the WC TCAM slice information that the device * supports. @@ -709,5 +731,7 @@ struct tf_dev_ops { */ extern const struct tf_dev_ops tf_dev_ops_p4_init; extern const struct tf_dev_ops tf_dev_ops_p4; +extern const struct tf_dev_ops tf_dev_ops_p58_init; +extern const struct tf_dev_ops tf_dev_ops_p58; #endif /* _TF_DEVICE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 17d2f05bcc..257a0fb2d0 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -4,8 +4,8 @@ */ #include -#include +#include "cfa_resource_types.h" #include "tf_device.h" #include "tf_identifier.h" #include "tf_tbl.h" @@ -17,6 +17,79 @@ #define TF_DEV_P4_PARIF_MAX 16 #define TF_DEV_P4_PF_MASK 0xfUL +const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { + /* CFA_RESOURCE_TYPE_P4_MCG */ + "mc_group", + /* CFA_RESOURCE_TYPE_P4_ENCAP_8B */ + "encap_8 ", + /* CFA_RESOURCE_TYPE_P4_ENCAP_16B */ + "encap_16", + /* CFA_RESOURCE_TYPE_P4_ENCAP_64B */ + "encap_64", + /* CFA_RESOURCE_TYPE_P4_SP_MAC */ + "sp_mac ", + /* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 */ + "sp_macv4", + /* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 */ + "sp_macv6", + /* CFA_RESOURCE_TYPE_P4_COUNTER_64B */ + "ctr_64b ", + /* CFA_RESOURCE_TYPE_P4_NAT_PORT */ + "nat_port", + /* CFA_RESOURCE_TYPE_P4_NAT_IPV4 */ + "nat_ipv4", + /* CFA_RESOURCE_TYPE_P4_METER */ + "meter ", + /* CFA_RESOURCE_TYPE_P4_FLOW_STATE */ + "flow_st ", + /* CFA_RESOURCE_TYPE_P4_FULL_ACTION */ + "full_act", + /* CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION */ + "fmt0_act", + /* CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION */ + "ext0_act", + /* CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION */ + "fmt1_act", + /* CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION */ + "fmt2_act", + /* CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION */ + "fmt3_act", + /* CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION */ + "fmt4_act", + /* CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION */ + "fmt5_act", + /* CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION */ + "fmt6_act", + /* CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH */ + "l2ctx_hi", + /* CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW */ + "l2ctx_lo", + /* CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH */ + "l2ctr_hi", + /* CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW */ + "l2ctr_lo", + /* CFA_RESOURCE_TYPE_P4_PROF_FUNC */ + "prf_func", + /* CFA_RESOURCE_TYPE_P4_PROF_TCAM */ + "prf_tcam", + /* CFA_RESOURCE_TYPE_P4_EM_PROF_ID */ + "em_prof ", + /* CFA_RESOURCE_TYPE_P4_EM_REC */ + "em_rec ", + /* CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID */ + "wc_prof ", + /* CFA_RESOURCE_TYPE_P4_WC_TCAM */ + "wc_tcam ", + /* CFA_RESOURCE_TYPE_P4_METER_PROF */ + "mtr_prof", + /* CFA_RESOURCE_TYPE_P4_MIRROR */ + "mirror ", + /* CFA_RESOURCE_TYPE_P4_SP_TCAM */ + "sp_tcam ", + /* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */ + "tb_scope", +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. @@ -25,7 +98,7 @@ * Pointer to TF handle * * [out] max_types - * Pointer to the MAX number of HCAPI types supported + * Pointer to the MAX number of CFA resource types supported * * Returns * - (0) if successful. @@ -61,6 +134,38 @@ tf_dev_p4_get_max_types(struct tf *tfp, return 0; } +/** + * Device specific function that retrieves a human readable + * string to identify a CFA resource type. + * + * [in] tfp + * Pointer to TF handle + * + * [in] resource_id + * HCAPI CFA resource id + * + * [out] resource_str + * Resource string + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int +tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused, + uint16_t resource_id, + const char **resource_str) +{ + if (resource_str == NULL) + return -EINVAL; + + if (resource_id > CFA_RESOURCE_TYPE_P4_LAST) + return -EINVAL; + + *resource_str = tf_resource_str_p4[resource_id]; + + return 0; +} /** * Device specific function that retrieves the WC TCAM slices the @@ -142,6 +247,7 @@ tf_dev_p4_map_parif(struct tf *tfp __rte_unused, */ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_max_types = tf_dev_p4_get_max_types, + .tf_dev_get_resource_str = tf_dev_p4_get_resource_str, .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info, .tf_dev_alloc_ident = NULL, .tf_dev_free_ident = NULL, @@ -179,6 +285,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { */ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_max_types = tf_dev_p4_get_max_types, + .tf_dev_get_resource_str = tf_dev_p4_get_resource_str, .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info, .tf_dev_alloc_ident = tf_ident_alloc, .tf_dev_free_ident = tf_ident_free, diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index 81ed2322d1..bfad02a0b8 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -6,8 +6,7 @@ #ifndef _TF_DEVICE_P4_H_ #define _TF_DEVICE_P4_H_ -#include - +#include "cfa_resource_types.h" #include "tf_core.h" #include "tf_rm.h" #include "tf_if_tbl.h" diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c new file mode 100644 index 0000000000..fb5ad29a5c --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#include + +#include "cfa_resource_types.h" +#include "tf_device.h" +#include "tf_identifier.h" +#include "tf_tbl.h" +#include "tf_tcam.h" +#include "tf_em.h" +#include "tf_if_tbl.h" +#include "tfp.h" + +#define TF_DEV_P58_PARIF_MAX 16 +#define TF_DEV_P58_PF_MASK 0xfUL + +const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { + /* CFA_RESOURCE_TYPE_P58_METER */ + "meter ", + /* CFA_RESOURCE_TYPE_P58_SRAM_BANK_0 */ + "sram_bk0", + /* CFA_RESOURCE_TYPE_P58_SRAM_BANK_1 */ + "sram_bk1", + /* CFA_RESOURCE_TYPE_P58_SRAM_BANK_2 */ + "sram_bk2", + /* CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 */ + "sram_bk3", + /* CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH */ + "l2ctx_hi", + /* CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW */ + "l2ctx_lo", + /* CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH */ + "l2ctr_hi", + /* CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW */ + "l2ctr_lo", + /* CFA_RESOURCE_TYPE_P58_PROF_FUNC */ + "prf_func", + /* CFA_RESOURCE_TYPE_P58_PROF_TCAM */ + "prf_tcam", + /* CFA_RESOURCE_TYPE_P58_EM_PROF_ID */ + "em_prof ", + /* CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID */ + "wc_prof ", + /* CFA_RESOURCE_TYPE_P58_EM_REC */ + "em_rec ", + /* CFA_RESOURCE_TYPE_P58_WC_TCAM */ + "wc_tcam ", + /* CFA_RESOURCE_TYPE_P58_METER_PROF */ + "mtr_prof", + /* CFA_RESOURCE_TYPE_P58_MIRROR */ + "mirror ", + /* CFA_RESOURCE_TYPE_P58_EM_FKB */ + "em_fkb ", + /* CFA_RESOURCE_TYPE_P58_WC_FKB */ + "wc_fkb ", + /* CFA_RESOURCE_TYPE_P58_VEB_TCAM */ + "veb ", +}; + +/** + * Device specific function that retrieves the MAX number of HCAPI + * types the device supports. + * + * [in] tfp + * Pointer to TF handle + * + * [out] max_types + * Pointer to the MAX number of HCAPI types supported + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int +tf_dev_p58_get_max_types(struct tf *tfp, + uint16_t *max_types) +{ + struct tf_session *tfs; + struct tf_dev_info *dev; + int rc; + + if (max_types == NULL || tfp == NULL) + return -EINVAL; + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + *max_types = CFA_RESOURCE_TYPE_P58_LAST + 1; + + return 0; +} +/** + * Device specific function that retrieves a human readable + * string to identify a CFA resource type. + * + * [in] tfp + * Pointer to TF handle + * + * [in] resource_id + * HCAPI CFA resource id + * + * [out] resource_str + * Resource string + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int +tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused, + uint16_t resource_id, + const char **resource_str) +{ + if (resource_str == NULL) + return -EINVAL; + + if (resource_id > CFA_RESOURCE_TYPE_P58_LAST) + return -EINVAL; + + *resource_str = tf_resource_str_p58[resource_id]; + + return 0; +} + +/** + * Device specific function that retrieves the WC TCAM slices the + * device supports. + * + * [in] tfp + * Pointer to TF handle + * + * [out] slice_size + * Pointer to the WC TCAM slice size + * + * [out] num_slices_per_row + * Pointer to the WC TCAM row slice configuration + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int +tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused, + enum tf_tcam_tbl_type type, + uint16_t key_sz, + uint16_t *num_slices_per_row) +{ +#define CFA_P58_WC_TCAM_SLICES_PER_ROW 2 +#define CFA_P58_WC_TCAM_SLICE_SIZE 12 + + if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { + *num_slices_per_row = CFA_P58_WC_TCAM_SLICES_PER_ROW; + if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE) + return -ENOTSUP; + + *num_slices_per_row = 1; + } else { /* for other type of tcam */ + *num_slices_per_row = 1; + } + + return 0; +} + +static int +tf_dev_p58_map_parif(struct tf *tfp __rte_unused, + uint16_t parif_bitmask, + uint16_t pf, + uint8_t *data, + uint8_t *mask, + uint16_t sz_in_bytes) +{ + uint32_t parif_pf[2] = { 0 }; + uint32_t parif_pf_mask[2] = { 0 }; + uint32_t parif; + uint32_t shift; + + if (sz_in_bytes != sizeof(uint64_t)) + return -ENOTSUP; + + for (parif = 0; parif < TF_DEV_P58_PARIF_MAX; parif++) { + if (parif_bitmask & (1UL << parif)) { + if (parif < 8) { + shift = 4 * parif; + parif_pf_mask[0] |= TF_DEV_P58_PF_MASK << shift; + parif_pf[0] |= pf << shift; + } else { + shift = 4 * (parif - 8); + parif_pf_mask[1] |= TF_DEV_P58_PF_MASK << shift; + parif_pf[1] |= pf << shift; + } + } + } + tfp_memcpy(data, parif_pf, sz_in_bytes); + tfp_memcpy(mask, parif_pf_mask, sz_in_bytes); + + return 0; +} + + +/** + * Truflow P58 device specific functions + */ +const struct tf_dev_ops tf_dev_ops_p58_init = { + .tf_dev_get_max_types = tf_dev_p58_get_max_types, + .tf_dev_get_resource_str = tf_dev_p58_get_resource_str, + .tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info, + .tf_dev_alloc_ident = NULL, + .tf_dev_free_ident = NULL, + .tf_dev_search_ident = NULL, + .tf_dev_alloc_ext_tbl = NULL, + .tf_dev_alloc_tbl = NULL, + .tf_dev_free_ext_tbl = NULL, + .tf_dev_free_tbl = NULL, + .tf_dev_alloc_search_tbl = NULL, + .tf_dev_set_tbl = NULL, + .tf_dev_set_ext_tbl = NULL, + .tf_dev_get_tbl = NULL, + .tf_dev_get_bulk_tbl = NULL, + .tf_dev_alloc_tcam = NULL, + .tf_dev_free_tcam = NULL, + .tf_dev_alloc_search_tcam = NULL, + .tf_dev_set_tcam = NULL, + .tf_dev_get_tcam = NULL, + .tf_dev_insert_int_em_entry = NULL, + .tf_dev_delete_int_em_entry = NULL, + .tf_dev_insert_ext_em_entry = NULL, + .tf_dev_delete_ext_em_entry = NULL, + .tf_dev_alloc_tbl_scope = NULL, + .tf_dev_map_tbl_scope = NULL, + .tf_dev_map_parif = NULL, + .tf_dev_free_tbl_scope = NULL, + .tf_dev_set_if_tbl = NULL, + .tf_dev_get_if_tbl = NULL, + .tf_dev_set_global_cfg = NULL, + .tf_dev_get_global_cfg = NULL, +}; + +/** + * Truflow P58 device specific functions + */ +const struct tf_dev_ops tf_dev_ops_p58 = { + .tf_dev_get_max_types = tf_dev_p58_get_max_types, + .tf_dev_get_resource_str = tf_dev_p58_get_resource_str, + .tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info, + .tf_dev_alloc_ident = tf_ident_alloc, + .tf_dev_free_ident = tf_ident_free, + .tf_dev_search_ident = tf_ident_search, + .tf_dev_alloc_tbl = tf_tbl_alloc, + .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, + .tf_dev_free_tbl = tf_tbl_free, + .tf_dev_free_ext_tbl = tf_tbl_ext_free, + .tf_dev_alloc_search_tbl = tf_tbl_alloc_search, + .tf_dev_set_tbl = tf_tbl_set, + .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, + .tf_dev_get_tbl = tf_tbl_get, + .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, + .tf_dev_alloc_tcam = tf_tcam_alloc, + .tf_dev_free_tcam = tf_tcam_free, + .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, + .tf_dev_set_tcam = tf_tcam_set, + .tf_dev_get_tcam = NULL, + .tf_dev_insert_int_em_entry = tf_em_insert_int_entry, + .tf_dev_delete_int_em_entry = tf_em_delete_int_entry, + .tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry, + .tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry, + .tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc, + .tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope, + .tf_dev_map_parif = tf_dev_p58_map_parif, + .tf_dev_free_tbl_scope = tf_em_ext_common_free, + .tf_dev_set_if_tbl = tf_if_tbl_set, + .tf_dev_get_if_tbl = tf_if_tbl_get, + .tf_dev_set_global_cfg = tf_global_cfg_set, + .tf_dev_get_global_cfg = tf_global_cfg_get, +}; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h new file mode 100644 index 0000000000..3d6e3240bf --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#ifndef _TF_DEVICE_P58_H_ +#define _TF_DEVICE_P58_H_ + +#include "cfa_resource_types.h" +#include "tf_core.h" +#include "tf_rm.h" +#include "tf_if_tbl.h" +#include "tf_global_cfg.h" + +struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = { + [TF_IDENT_TYPE_L2_CTXT_HIGH] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH + }, + [TF_IDENT_TYPE_L2_CTXT_LOW] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW + }, + [TF_IDENT_TYPE_PROF_FUNC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC + }, + [TF_IDENT_TYPE_WC_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID + }, + [TF_IDENT_TYPE_EM_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID + }, +}; + +struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = { + [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH + }, + [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW + }, + [TF_TCAM_TBL_TYPE_PROF_TCAM] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM + }, + [TF_TCAM_TBL_TYPE_WC_TCAM] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM + }, + [TF_TCAM_TBL_TYPE_VEB_TCAM] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM + }, +}; + +struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { + [TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF + }, + [TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER + }, + [TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR + }, +}; + +struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { + [TF_EM_TBL_TYPE_EM_RECORD] = { + TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC + }, +}; + +struct tf_if_tbl_cfg tf_if_tbl_p58[TF_IF_TBL_TYPE_MAX]; + +struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { + [TF_TUNNEL_ENCAP] = { + TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP + }, + [TF_ACTION_BLOCK] = { + TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK + }, +}; +#endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index c4137af2bd..ddc6b3c4dd 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -1115,8 +1115,8 @@ int tf_em_ext_map_tbl_scope(struct tf *tfp, goto cleaner; } - gcfg_parms.type = - (enum tf_global_config_type)TF_GLOBAL_CFG_INTERNAL_PARIF_2_PF; + /* Note that TF_GLOBAL_CFG_INTERNAL_PARIF_2_PF is same as below enum */ + gcfg_parms.type = TF_GLOBAL_CFG_TYPE_MAX; gcfg_parms.offset = 0; gcfg_parms.config = (uint8_t *)data; gcfg_parms.config_mask = (uint8_t *)mask; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 46fc6288b2..f20a5113bf 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -19,9 +19,6 @@ #include "hwrm_tf.h" #include "tf_em.h" -/* Logging defines */ -#define TF_RM_MSG_DEBUG 0 - /* Specific msg size defines as we cannot use defines in tf.yaml. This * means we have to manually sync hwrm with these defines if the * tf.yaml changes. @@ -361,29 +358,13 @@ tf_msg_session_resc_qcaps(struct tf *tfp, goto cleanup; } -#if (TF_RM_MSG_DEBUG == 1) - printf("size: %d\n", tfp_le_to_cpu_32(resp.size)); -#endif /* (TF_RM_MSG_DEBUG == 1) */ - /* Post process the response */ data = (struct tf_rm_resc_req_entry *)qcaps_buf.va_addr; -#if (TF_RM_MSG_DEBUG == 1) - printf("\nQCAPS\n"); -#endif /* (TF_RM_MSG_DEBUG == 1) */ for (i = 0; i < size; i++) { query[i].type = tfp_le_to_cpu_32(data[i].type); query[i].min = tfp_le_to_cpu_16(data[i].min); query[i].max = tfp_le_to_cpu_16(data[i].max); - -#if (TF_RM_MSG_DEBUG == 1) - printf("type: %d(0x%x) %d %d\n", - query[i].type, - query[i].type, - query[i].min, - query[i].max); -#endif /* (TF_RM_MSG_DEBUG == 1) */ - } *resv_strategy = resp.flags & @@ -476,26 +457,12 @@ tf_msg_session_resc_alloc(struct tf *tfp, goto cleanup; } -#if (TF_RM_MSG_DEBUG == 1) - printf("\nRESV\n"); - printf("size: %d\n", tfp_le_to_cpu_32(resp.size)); -#endif /* (TF_RM_MSG_DEBUG == 1) */ - /* Post process the response */ resv_data = (struct tf_rm_resc_entry *)resv_buf.va_addr; for (i = 0; i < size; i++) { resv[i].type = tfp_le_to_cpu_32(resv_data[i].type); resv[i].start = tfp_le_to_cpu_16(resv_data[i].start); resv[i].stride = tfp_le_to_cpu_16(resv_data[i].stride); - -#if (TF_RM_MSG_DEBUG == 1) - printf("%d type: %d(0x%x) %d %d\n", - i, - resv[i].type, - resv[i].type, - resv[i].start, - resv[i].stride); -#endif /* (TF_RM_MSG_DEBUG == 1) */ } cleanup: diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index 887a3dccf8..f93a6d9018 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -6,6 +6,7 @@ #include #include +#include #include @@ -596,13 +597,6 @@ tf_rm_create_db(struct tf *tfp, rm_db->type = parms->type; *parms->rm_db = (void *)rm_db; -#if (TF_RM_DEBUG == 1) - printf("%s: type:%d num_entries:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - i); -#endif /* (TF_RM_DEBUG == 1) */ - tfp_free((void *)req); tfp_free((void *)resv); diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c b/drivers/net/bnxt/tf_core/tf_shadow_tcam.c index 38b1e7687b..523261f189 100644 --- a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_shadow_tcam.c @@ -6,6 +6,7 @@ #include "tf_common.h" #include "tf_util.h" #include "tfp.h" +#include "tf_tcam.h" #include "tf_shadow_tcam.h" #include "tf_hash.h" @@ -634,8 +635,7 @@ tf_shadow_tcam_search(struct tf_shadow_tcam_search_parms *parms) * requested allocation and return the info */ if (sparms->alloc) - ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt = - ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt + 1; + ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt++; sparms->hit = 1; sparms->search_status = HIT; From patchwork Sun May 30 08:58:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93552 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41A68A0524; Sun, 30 May 2021 11:00:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DE4AD410E0; Sun, 30 May 2021 11:00:33 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 27A6B40E28 for ; Sun, 30 May 2021 11:00:31 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 8734E7DC0; Sun, 30 May 2021 02:00:29 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 8734E7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365230; bh=KNVQC4OANG2Q/PLaz9fXON/OdDRoyCLL6mb1HG7ZHsc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ug3zoM226cZbt7EOELMST/91NFamsSF2mafIjVoyyGDxIQpvMgDeMXsNU7lYax8YB gq2pn9EnhwHtehNMRG3aMnagB72uc9IijuI9VrmuVCYk7IncgWsk9yJ2aYsvEdTf6S KdEj4+IeZ1OLNM1qjeDwFzkDyUZ7w+QOD5TcW+Yo= From: Venkat Duvvuru To: dev@dpdk.org Cc: Peter Spreadborough , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:34 +0530 Message-Id: <20210530085929.29695-4-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 03/58] net/bnxt: add mailbox selection via dev op X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Peter Spreadborough Add get mailbox dev op so that mailbox offset is based on device rather than hard coded. Signed-off-by: Peter Spreadborough Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_core/tf_device.c | 21 ++ drivers/net/bnxt/tf_core/tf_device.h | 12 + drivers/net/bnxt/tf_core/tf_device_p4.c | 8 + drivers/net/bnxt/tf_core/tf_device_p58.c | 7 + drivers/net/bnxt/tf_core/tf_msg.c | 410 +++++++++++++++++++++-- drivers/net/bnxt/tf_core/tf_msg.h | 12 +- drivers/net/bnxt/tf_core/tf_rm.c | 2 + drivers/net/bnxt/tf_core/tf_session.c | 22 +- drivers/net/bnxt/tf_core/tf_tcam.c | 4 +- 9 files changed, 463 insertions(+), 35 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 9c63f6d5d4..5116601a69 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -461,6 +461,27 @@ tf_dev_bind(struct tf *tfp __rte_unused, } } +int +tf_dev_bind_ops(enum tf_device_type type, + struct tf_dev_info *dev_handle) +{ + switch (type) { + case TF_DEVICE_TYPE_WH: + case TF_DEVICE_TYPE_SR: + dev_handle->ops = &tf_dev_ops_p4; + break; + case TF_DEVICE_TYPE_THOR: + dev_handle->ops = &tf_dev_ops_p58; + break; + default: + TFP_DRV_LOG(ERR, + "No such device\n"); + return -ENODEV; + } + + return 0; +} + int tf_dev_unbind(struct tf *tfp, struct tf_dev_info *dev_handle) diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index d5ef72309f..cbacc09ea5 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -108,6 +108,10 @@ int tf_dev_bind(struct tf *tfp, int tf_dev_unbind(struct tf *tfp, struct tf_dev_info *dev_handle); +int +tf_dev_bind_ops(enum tf_device_type type, + struct tf_dev_info *dev_handle); + /** * Truflow device specific function hooks structure * @@ -724,6 +728,14 @@ struct tf_dev_ops { */ int (*tf_dev_get_global_cfg)(struct tf *tfp, struct tf_global_cfg_parms *parms); + + /** + * Get mailbox + * + * returns: + * mailbox + */ + int (*tf_dev_get_mailbox)(void); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 257a0fb2d0..6b28f6ce59 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -13,6 +13,7 @@ #include "tf_em.h" #include "tf_if_tbl.h" #include "tfp.h" +#include "tf_msg_common.h" #define TF_DEV_P4_PARIF_MAX 16 #define TF_DEV_P4_PF_MASK 0xfUL @@ -241,6 +242,11 @@ tf_dev_p4_map_parif(struct tf *tfp __rte_unused, return 0; } +static int tf_dev_p4_get_mailbox(void) +{ + return TF_KONG_MB; +} + /** * Truflow P4 device specific functions @@ -278,6 +284,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_if_tbl = NULL, .tf_dev_set_global_cfg = NULL, .tf_dev_get_global_cfg = NULL, + .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, }; /** @@ -316,4 +323,5 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_if_tbl = tf_if_tbl_get, .tf_dev_set_global_cfg = tf_global_cfg_set, .tf_dev_get_global_cfg = tf_global_cfg_get, + .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index fb5ad29a5c..b4530f8762 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -13,6 +13,7 @@ #include "tf_em.h" #include "tf_if_tbl.h" #include "tfp.h" +#include "tf_msg_common.h" #define TF_DEV_P58_PARIF_MAX 16 #define TF_DEV_P58_PF_MASK 0xfUL @@ -206,6 +207,10 @@ tf_dev_p58_map_parif(struct tf *tfp __rte_unused, return 0; } +static int tf_dev_p58_get_mailbox(void) +{ + return TF_CHIMP_MB; +} /** * Truflow P58 device specific functions @@ -243,6 +248,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_if_tbl = NULL, .tf_dev_set_global_cfg = NULL, .tf_dev_get_global_cfg = NULL, + .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, }; /** @@ -281,4 +287,5 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_if_tbl = tf_if_tbl_get, .tf_dev_set_global_cfg = tf_global_cfg_set, .tf_dev_get_global_cfg = tf_global_cfg_get, + .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, }; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index f20a5113bf..1007211363 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -116,7 +116,8 @@ int tf_msg_session_open(struct tf *tfp, char *ctrl_chan_name, uint8_t *fw_session_id, - uint8_t *fw_session_client_id) + uint8_t *fw_session_client_id, + struct tf_dev_info *dev) { int rc; struct hwrm_tf_session_open_input req = { 0 }; @@ -131,7 +132,7 @@ tf_msg_session_open(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -155,6 +156,7 @@ tf_msg_session_attach(struct tf *tfp __rte_unused, int tf_msg_session_client_register(struct tf *tfp, + struct tf_session *tfs, char *ctrl_channel_name, uint8_t *fw_session_client_id) { @@ -163,6 +165,16 @@ tf_msg_session_client_register(struct tf *tfp, struct hwrm_tf_session_register_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; + struct tf_dev_info *dev; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -183,7 +195,7 @@ tf_msg_session_client_register(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -198,6 +210,7 @@ tf_msg_session_client_register(struct tf *tfp, int tf_msg_session_client_unregister(struct tf *tfp, + struct tf_session *tfs, uint8_t fw_session_client_id) { int rc; @@ -205,6 +218,16 @@ tf_msg_session_client_unregister(struct tf *tfp, struct hwrm_tf_session_unregister_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; + struct tf_dev_info *dev; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -223,7 +246,7 @@ tf_msg_session_client_unregister(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -232,13 +255,24 @@ tf_msg_session_client_unregister(struct tf *tfp, } int -tf_msg_session_close(struct tf *tfp) +tf_msg_session_close(struct tf *tfp, + struct tf_session *tfs) { int rc; struct hwrm_tf_session_close_input req = { 0 }; struct hwrm_tf_session_close_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; + struct tf_dev_info *dev; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -256,7 +290,7 @@ tf_msg_session_close(struct tf *tfp) parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -271,6 +305,26 @@ tf_msg_session_qcfg(struct tf *tfp) struct hwrm_tf_session_qcfg_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -288,7 +342,7 @@ tf_msg_session_qcfg(struct tf *tfp) parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -297,6 +351,7 @@ tf_msg_session_qcfg(struct tf *tfp) int tf_msg_session_resc_qcaps(struct tf *tfp, + struct tf_dev_info *dev, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, @@ -340,7 +395,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); if (rc) @@ -378,6 +433,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, int tf_msg_session_resc_alloc(struct tf *tfp, + struct tf_dev_info *dev, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *request, @@ -439,7 +495,7 @@ tf_msg_session_resc_alloc(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); if (rc) @@ -487,9 +543,31 @@ tf_msg_session_resc_flush(struct tf *tfp, struct tf_msg_dma_buf resv_buf = { 0 }; struct tf_rm_resc_entry *resv_data; int dma_size; + struct tf_dev_info *dev; + struct tf_session *tfs; TF_CHECK_PARMS2(tfp, resv); + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { TFP_DRV_LOG(ERR, @@ -524,7 +602,7 @@ tf_msg_session_resc_flush(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -549,6 +627,28 @@ tf_msg_insert_em_internal_entry(struct tf *tfp, uint16_t flags; uint8_t fw_session_id; uint8_t msg_key_size; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -593,7 +693,7 @@ tf_msg_insert_em_internal_entry(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -617,6 +717,28 @@ tf_msg_delete_em_entry(struct tf *tfp, struct hwrm_tf_em_delete_output resp = { 0 }; uint16_t flags; uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -641,7 +763,7 @@ tf_msg_delete_em_entry(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -664,6 +786,26 @@ tf_msg_em_mem_rgtr(struct tf *tfp, struct hwrm_tf_ctxt_mem_rgtr_input req = { 0 }; struct hwrm_tf_ctxt_mem_rgtr_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } req.page_level = page_lvl; req.page_size = page_size; @@ -674,7 +816,7 @@ tf_msg_em_mem_rgtr(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -694,6 +836,26 @@ tf_msg_em_mem_unrgtr(struct tf *tfp, struct hwrm_tf_ctxt_mem_unrgtr_input req = {0}; struct hwrm_tf_ctxt_mem_unrgtr_output resp = {0}; struct tfp_send_msg_parms parms = { 0 }; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } req.ctx_id = tfp_cpu_to_le_32(*ctx_id); @@ -702,7 +864,7 @@ tf_msg_em_mem_unrgtr(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -719,6 +881,28 @@ tf_msg_em_qcaps(struct tf *tfp, struct hwrm_tf_ext_em_qcaps_output resp = { 0 }; uint32_t flags; struct tfp_send_msg_parms parms = { 0 }; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } flags = (dir == TF_DIR_TX ? HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX : HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX); @@ -729,7 +913,7 @@ tf_msg_em_qcaps(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -762,6 +946,28 @@ tf_msg_em_cfg(struct tf *tfp, struct hwrm_tf_ext_em_cfg_output resp = {0}; uint32_t flags; struct tfp_send_msg_parms parms = { 0 }; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } flags = (dir == TF_DIR_TX ? HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX : HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX); @@ -782,7 +988,7 @@ tf_msg_em_cfg(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -799,6 +1005,28 @@ tf_msg_em_op(struct tf *tfp, struct hwrm_tf_ext_em_op_output resp = {0}; uint32_t flags; struct tfp_send_msg_parms parms = { 0 }; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } flags = (dir == TF_DIR_TX ? HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX : HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX); @@ -810,7 +1038,7 @@ tf_msg_em_op(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -819,6 +1047,7 @@ tf_msg_em_op(struct tf *tfp, int tf_msg_tcam_entry_set(struct tf *tfp, + struct tf_dev_info *dev, struct tf_tcam_set_parms *parms) { int rc; @@ -877,7 +1106,7 @@ tf_msg_tcam_entry_set(struct tf *tfp, mparms.req_size = sizeof(req); mparms.resp_data = (uint32_t *)&resp; mparms.resp_size = sizeof(resp); - mparms.mailbox = TF_KONG_MB; + mparms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &mparms); @@ -890,6 +1119,7 @@ tf_msg_tcam_entry_set(struct tf *tfp, int tf_msg_tcam_entry_free(struct tf *tfp, + struct tf_dev_info *dev, struct tf_tcam_free_parms *in_parms) { int rc; @@ -920,7 +1150,7 @@ tf_msg_tcam_entry_free(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -940,6 +1170,28 @@ tf_msg_set_tbl_entry(struct tf *tfp, struct hwrm_tf_tbl_type_set_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -976,7 +1228,7 @@ tf_msg_set_tbl_entry(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -999,6 +1251,28 @@ tf_msg_get_tbl_entry(struct tf *tfp, struct hwrm_tf_tbl_type_get_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -1020,7 +1294,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -1051,6 +1325,28 @@ tf_msg_get_global_cfg(struct tf *tfp, uint32_t flags = 0; uint8_t fw_session_id; uint16_t resp_size = 0; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(params->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(params->dir), + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -1077,7 +1373,7 @@ tf_msg_get_global_cfg(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); if (rc != 0) @@ -1108,6 +1404,28 @@ tf_msg_set_global_cfg(struct tf *tfp, struct hwrm_tf_global_cfg_set_output resp = { 0 }; uint32_t flags = 0; uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(params->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(params->dir), + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -1156,7 +1474,7 @@ tf_msg_set_global_cfg(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -1181,6 +1499,28 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, struct tf_tbl_type_bulk_get_output resp = { 0 }; int data_size = 0; uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -1203,7 +1543,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, req.host_addr = tfp_cpu_to_le_64(physical_mem_addr); MSG_PREP(parms, - TF_KONG_MB, + dev->ops->tf_dev_get_mailbox(), HWRM_TF, HWRM_TFT_TBL_TYPE_BULK_GET, req, @@ -1229,6 +1569,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp, struct hwrm_tf_if_tbl_get_input req = { 0 }; struct hwrm_tf_if_tbl_get_output resp = { 0 }; uint32_t flags = 0; + struct tf_dev_info *dev; struct tf_session *tfs; /* Retrieve the session information */ @@ -1241,6 +1582,16 @@ tf_msg_get_if_tbl_entry(struct tf *tfp, return rc; } + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(params->dir), + strerror(-rc)); + return rc; + } + flags = (params->dir == TF_DIR_TX ? HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX : HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX); @@ -1258,7 +1609,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); @@ -1268,7 +1619,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp, if (parms.tf_resp_code != 0) return tfp_le_to_cpu_32(parms.tf_resp_code); - tfp_memcpy(¶ms->data[0], resp.data, req.size); + tfp_memcpy(params->data, resp.data, req.size); return tfp_le_to_cpu_32(parms.tf_resp_code); } @@ -1282,6 +1633,7 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, struct hwrm_tf_if_tbl_set_input req = { 0 }; struct hwrm_tf_if_tbl_get_output resp = { 0 }; uint32_t flags = 0; + struct tf_dev_info *dev; struct tf_session *tfs; /* Retrieve the session information */ @@ -1294,6 +1646,10 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, return rc; } + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; flags = (params->dir == TF_DIR_TX ? HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX : @@ -1313,7 +1669,7 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = TF_KONG_MB; + parms.mailbox = dev->ops->tf_dev_get_mailbox(); rc = tfp_send_msg_direct(tfp, &parms); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 0a2566010c..25e29a554f 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -36,7 +36,8 @@ struct tf; int tf_msg_session_open(struct tf *tfp, char *ctrl_chan_name, uint8_t *fw_session_id, - uint8_t *fw_session_client_id); + uint8_t *fw_session_client_id, + struct tf_dev_info *dev); /** * Sends session close request to Firmware @@ -75,6 +76,7 @@ int tf_msg_session_attach(struct tf *tfp, * 0 on Success else internal Truflow error */ int tf_msg_session_client_register(struct tf *tfp, + struct tf_session *tfs, char *ctrl_channel_name, uint8_t *fw_session_client_id); @@ -92,6 +94,7 @@ int tf_msg_session_client_register(struct tf *tfp, * 0 on Success else internal Truflow error */ int tf_msg_session_client_unregister(struct tf *tfp, + struct tf_session *tfs, uint8_t fw_session_client_id); /** @@ -103,7 +106,8 @@ int tf_msg_session_client_unregister(struct tf *tfp, * Returns: * 0 on Success else internal Truflow error */ -int tf_msg_session_close(struct tf *tfp); +int tf_msg_session_close(struct tf *tfp, + struct tf_session *tfs); /** * Sends session query config request to TF Firmware @@ -139,6 +143,7 @@ int tf_msg_session_qcfg(struct tf *tfp); * 0 on Success else internal Truflow error */ int tf_msg_session_resc_qcaps(struct tf *tfp, + struct tf_dev_info *dev, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, @@ -166,6 +171,7 @@ int tf_msg_session_resc_qcaps(struct tf *tfp, * 0 on Success else internal Truflow error */ int tf_msg_session_resc_alloc(struct tf *tfp, + struct tf_dev_info *dev, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *request, @@ -368,6 +374,7 @@ int tf_msg_em_op(struct tf *tfp, * 0 on Success else internal Truflow error */ int tf_msg_tcam_entry_set(struct tf *tfp, + struct tf_dev_info *dev, struct tf_tcam_set_parms *parms); /** @@ -383,6 +390,7 @@ int tf_msg_tcam_entry_set(struct tf *tfp, * 0 on Success else internal Truflow error */ int tf_msg_tcam_entry_free(struct tf *tfp, + struct tf_dev_info *dev, struct tf_tcam_free_parms *parms); /** diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index f93a6d9018..2c08fb80fe 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -415,6 +415,7 @@ tf_rm_create_db(struct tf *tfp, /* Get Firmware Capabilities */ rc = tf_msg_session_resc_qcaps(tfp, + dev, parms->dir, max_types, query, @@ -499,6 +500,7 @@ tf_rm_create_db(struct tf *tfp, } rc = tf_msg_session_resc_alloc(tfp, + dev, parms->dir, hcapi_items, req, diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index 6335ad358c..b3fa7e13ff 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -56,14 +56,19 @@ tf_session_create(struct tf *tfp, uint8_t fw_session_id; uint8_t fw_session_client_id; union tf_session_id *session_id; + struct tf_dev_info dev; TF_CHECK_PARMS2(tfp, parms); + tf_dev_bind_ops(parms->open_cfg->device_type, + &dev); + /* Open FW session and get a new session_id */ rc = tf_msg_session_open(tfp, parms->open_cfg->ctrl_chan_name, &fw_session_id, - &fw_session_client_id); + &fw_session_client_id, + &dev); if (rc) { /* Log error */ if (rc == -EEXIST) @@ -177,6 +182,13 @@ tf_session_create(struct tf *tfp, if (rc) return rc; + if (session->dev.ops->tf_dev_get_mailbox == NULL) { + /* Log error */ + TFP_DRV_LOG(ERR, + "No tf_dev_get_mailbox() defined for device\n"); + goto cleanup; + } + session->dev_init = true; return 0; @@ -234,8 +246,9 @@ tf_session_client_create(struct tf *tfp, rc = tf_msg_session_client_register (tfp, - parms->ctrl_chan_name, - &session_client_id.internal.fw_session_client_id); + session, + parms->ctrl_chan_name, + &session_client_id.internal.fw_session_client_id); if (rc) { TFP_DRV_LOG(ERR, "Failed to create client on session, rc:%s\n", @@ -346,6 +359,7 @@ tf_session_client_destroy(struct tf *tfp, rc = tf_msg_session_client_unregister (tfp, + tfs, parms->session_client_id.internal.fw_session_client_id); /* Log error, but continue. If FW fails we do not really have @@ -534,7 +548,7 @@ tf_session_close_session(struct tf *tfp, strerror(-rc)); } - rc = tf_msg_session_close(tfp); + rc = tf_msg_session_close(tfp, tfs); if (rc) { /* Log error */ TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 22bc01c95d..038aa40e92 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -428,7 +428,7 @@ tf_tcam_free(struct tf *tfp, if (rc) return rc; - rc = tf_msg_tcam_entry_free(tfp, parms); + rc = tf_msg_tcam_entry_free(tfp, dev, parms); if (rc) { /* Log error */ TFP_DRV_LOG(ERR, @@ -652,7 +652,7 @@ tf_tcam_set(struct tf *tfp __rte_unused, if (rc) return rc; - rc = tf_msg_tcam_entry_set(tfp, parms); + rc = tf_msg_tcam_entry_set(tfp, dev, parms); if (rc) { /* Log error */ TFP_DRV_LOG(ERR, From patchwork Sun May 30 08:58:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93553 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 517A1A0524; Sun, 30 May 2021 11:01:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 58BF9410F8; Sun, 30 May 2021 11:00:35 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id DAF0540E78 for ; Sun, 30 May 2021 11:00:32 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 420007DAF; Sun, 30 May 2021 02:00:31 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 420007DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365232; bh=A1e6vLUuzQDuJBTnyBuxC3EGpFX0mtmAJma+GXcA7Ow=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a9gtrSxwssaLJgGh3hK5ZCZztZVEyijUFuBZOtlhmD8U57And3BaydXgJEKllgOfV IqxDjv8T/KNGBFCnzanvuz273S8c+8bis4XVPim73gv8YjuPH1WVfGH0f4bD5pRU8k bSNuzNfdG4VmOYFgHq3kG16hgcIIsxeNLFSnafsk= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:35 +0530 Message-Id: <20210530085929.29695-5-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 04/58] net/bnxt: check resource reservation in TRUFLOW X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding - Allow tf_open to continue if no resource is allocated for some table type. - Close the session if binding fails for any table. - Close the session if no resource is allocated for all tables. Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Peter Spreadborough --- drivers/net/bnxt/tf_core/tf_device.c | 284 +++++++++++++++++++------- drivers/net/bnxt/tf_core/tf_session.c | 2 +- 2 files changed, 207 insertions(+), 79 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 5116601a69..d4c93439ec 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -15,6 +15,44 @@ struct tf; static int tf_dev_unbind_p4(struct tf *tfp); static int tf_dev_unbind_p58(struct tf *tfp); +/** + * Resource Reservation Check function + * + * [in] tfp + * Pointer to TF handle + * + * [in] cfg + * Pointer to rm element config + * + * [in] reservations + * Pointer to resource reservation array + * + * Returns + * - (n) number of tables that have non-zero reservation count. + */ +static int +tf_dev_reservation_check(struct tf *tfp __rte_unused, + uint16_t count, + struct tf_rm_element_cfg *cfg, + uint16_t *reservations) +{ + uint16_t cnt = 0; + uint16_t *rm_num; + int i, j; + + for (i = 0; i < TF_DIR_MAX; i++) { + rm_num = (uint16_t *)reservations + i * count; + for (j = 0; j < count; j++) { + if ((cfg[j].cfg_type == TF_RM_ELEM_CFG_HCAPI || + cfg[j].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA) && + rm_num[j] > 0) + cnt++; + } + } + + return cnt; +} + /** * Device specific bind function, WH+ * @@ -42,6 +80,8 @@ tf_dev_bind_p4(struct tf *tfp, { int rc; int frc; + int rsv_cnt; + bool no_rsv_flag = true; struct tf_ident_cfg_parms ident_cfg; struct tf_tbl_cfg_parms tbl_cfg; struct tf_tcam_cfg_parms tcam_cfg; @@ -54,69 +94,117 @@ tf_dev_bind_p4(struct tf *tfp, /* Initialize the modules */ - ident_cfg.num_elements = TF_IDENT_TYPE_MAX; - ident_cfg.cfg = tf_ident_p4; - ident_cfg.shadow_copy = shadow_copy; - ident_cfg.resources = resources; - rc = tf_ident_bind(tfp, &ident_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "Identifier initialization failure\n"); - goto fail; + rsv_cnt = tf_dev_reservation_check(tfp, + TF_IDENT_TYPE_MAX, + tf_ident_p4, + (uint16_t *)resources->ident_cnt); + if (rsv_cnt) { + ident_cfg.num_elements = TF_IDENT_TYPE_MAX; + ident_cfg.cfg = tf_ident_p4; + ident_cfg.shadow_copy = shadow_copy; + ident_cfg.resources = resources; + rc = tf_ident_bind(tfp, &ident_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Identifier initialization failure\n"); + goto fail; + } + + no_rsv_flag = false; } - tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p4; - tbl_cfg.shadow_copy = shadow_copy; - tbl_cfg.resources = resources; - rc = tf_tbl_bind(tfp, &tbl_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "Table initialization failure\n"); - goto fail; + rsv_cnt = tf_dev_reservation_check(tfp, + TF_TBL_TYPE_MAX, + tf_tbl_p4, + (uint16_t *)resources->tbl_cnt); + if (rsv_cnt) { + tbl_cfg.num_elements = TF_TBL_TYPE_MAX; + tbl_cfg.cfg = tf_tbl_p4; + tbl_cfg.shadow_copy = shadow_copy; + tbl_cfg.resources = resources; + rc = tf_tbl_bind(tfp, &tbl_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Table initialization failure\n"); + goto fail; + } + + no_rsv_flag = false; } - tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX; - tcam_cfg.cfg = tf_tcam_p4; - tcam_cfg.shadow_copy = shadow_copy; - tcam_cfg.resources = resources; - rc = tf_tcam_bind(tfp, &tcam_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "TCAM initialization failure\n"); - goto fail; + rsv_cnt = tf_dev_reservation_check(tfp, + TF_TCAM_TBL_TYPE_MAX, + tf_tcam_p4, + (uint16_t *)resources->tcam_cnt); + if (rsv_cnt) { + tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX; + tcam_cfg.cfg = tf_tcam_p4; + tcam_cfg.shadow_copy = shadow_copy; + tcam_cfg.resources = resources; + rc = tf_tcam_bind(tfp, &tcam_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "TCAM initialization failure\n"); + goto fail; + } + no_rsv_flag = false; } /* * EEM */ - em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; if (dev_handle->type == TF_DEVICE_TYPE_WH) em_cfg.cfg = tf_em_ext_p4; else em_cfg.cfg = tf_em_ext_p45; - em_cfg.resources = resources; - em_cfg.mem_type = TF_EEM_MEM_TYPE_HOST; - rc = tf_em_ext_common_bind(tfp, &em_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "EEM initialization failure\n"); - goto fail; + + rsv_cnt = tf_dev_reservation_check(tfp, + TF_EM_TBL_TYPE_MAX, + em_cfg.cfg, + (uint16_t *)resources->em_cnt); + if (rsv_cnt) { + em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; + em_cfg.resources = resources; + em_cfg.mem_type = TF_EEM_MEM_TYPE_HOST; + rc = tf_em_ext_common_bind(tfp, &em_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "EEM initialization failure\n"); + goto fail; + } + no_rsv_flag = false; } /* * EM */ - em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; - em_cfg.cfg = tf_em_int_p4; - em_cfg.resources = resources; - em_cfg.mem_type = 0; /* Not used by EM */ + rsv_cnt = tf_dev_reservation_check(tfp, + TF_EM_TBL_TYPE_MAX, + tf_em_int_p4, + (uint16_t *)resources->em_cnt); + if (rsv_cnt) { + em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; + em_cfg.cfg = tf_em_int_p4; + em_cfg.resources = resources; + em_cfg.mem_type = 0; /* Not used by EM */ + + rc = tf_em_int_bind(tfp, &em_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "EM initialization failure\n"); + goto fail; + } + no_rsv_flag = false; + } - rc = tf_em_int_bind(tfp, &em_cfg); - if (rc) { + /* + * There is no rm reserved for any tables + * + */ + if (no_rsv_flag) { TFP_DRV_LOG(ERR, - "EM initialization failure\n"); - goto fail; + "No rm reserved for any tables\n"); + return -ENOMEM; } /* @@ -263,6 +351,8 @@ tf_dev_bind_p58(struct tf *tfp, { int rc; int frc; + int rsv_cnt; + bool no_rsv_flag = true; struct tf_ident_cfg_parms ident_cfg; struct tf_tbl_cfg_parms tbl_cfg; struct tf_tcam_cfg_parms tcam_cfg; @@ -275,52 +365,90 @@ tf_dev_bind_p58(struct tf *tfp, /* Initialize the modules */ - ident_cfg.num_elements = TF_IDENT_TYPE_MAX; - ident_cfg.cfg = tf_ident_p58; - ident_cfg.shadow_copy = shadow_copy; - ident_cfg.resources = resources; - rc = tf_ident_bind(tfp, &ident_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "Identifier initialization failure\n"); - goto fail; + rsv_cnt = tf_dev_reservation_check(tfp, + TF_IDENT_TYPE_MAX, + tf_ident_p58, + (uint16_t *)resources->ident_cnt); + if (rsv_cnt) { + ident_cfg.num_elements = TF_IDENT_TYPE_MAX; + ident_cfg.cfg = tf_ident_p58; + ident_cfg.shadow_copy = shadow_copy; + ident_cfg.resources = resources; + rc = tf_ident_bind(tfp, &ident_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Identifier initialization failure\n"); + goto fail; + } + no_rsv_flag = false; } - tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p58; - tbl_cfg.shadow_copy = shadow_copy; - tbl_cfg.resources = resources; - rc = tf_tbl_bind(tfp, &tbl_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "Table initialization failure\n"); - goto fail; + rsv_cnt = tf_dev_reservation_check(tfp, + TF_TBL_TYPE_MAX, + tf_tbl_p58, + (uint16_t *)resources->tbl_cnt); + if (rsv_cnt) { + tbl_cfg.num_elements = TF_TBL_TYPE_MAX; + tbl_cfg.cfg = tf_tbl_p58; + tbl_cfg.shadow_copy = shadow_copy; + tbl_cfg.resources = resources; + rc = tf_tbl_bind(tfp, &tbl_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Table initialization failure\n"); + goto fail; + } + no_rsv_flag = false; } - tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX; - tcam_cfg.cfg = tf_tcam_p58; - tcam_cfg.shadow_copy = shadow_copy; - tcam_cfg.resources = resources; - rc = tf_tcam_bind(tfp, &tcam_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "TCAM initialization failure\n"); - goto fail; + rsv_cnt = tf_dev_reservation_check(tfp, + TF_TCAM_TBL_TYPE_MAX, + tf_tcam_p58, + (uint16_t *)resources->tcam_cnt); + if (rsv_cnt) { + tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX; + tcam_cfg.cfg = tf_tcam_p58; + tcam_cfg.shadow_copy = shadow_copy; + tcam_cfg.resources = resources; + rc = tf_tcam_bind(tfp, &tcam_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "TCAM initialization failure\n"); + goto fail; + } + no_rsv_flag = false; } /* * EM */ - em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; - em_cfg.cfg = tf_em_int_p58; - em_cfg.resources = resources; - em_cfg.mem_type = 0; /* Not used by EM */ + rsv_cnt = tf_dev_reservation_check(tfp, + TF_EM_TBL_TYPE_MAX, + tf_em_int_p58, + (uint16_t *)resources->em_cnt); + if (rsv_cnt) { + em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; + em_cfg.cfg = tf_em_int_p58; + em_cfg.resources = resources; + em_cfg.mem_type = 0; /* Not used by EM */ + + rc = tf_em_int_bind(tfp, &em_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "EM initialization failure\n"); + goto fail; + } + no_rsv_flag = false; + } - rc = tf_em_int_bind(tfp, &em_cfg); - if (rc) { + /* + * There is no rm reserved for any tables + * + */ + if (no_rsv_flag) { TFP_DRV_LOG(ERR, - "EM initialization failure\n"); - goto fail; + "No rm reserved for any tables\n"); + return -ENOMEM; } /* diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index b3fa7e13ff..d2b24f5e20 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -180,7 +180,7 @@ tf_session_create(struct tf *tfp, &session->dev); /* Logging handled by dev_bind */ if (rc) - return rc; + goto cleanup; if (session->dev.ops->tf_dev_get_mailbox == NULL) { /* Log error */ From patchwork Sun May 30 08:58:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93554 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B18A0A0524; Sun, 30 May 2021 11:01:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 94BB141102; Sun, 30 May 2021 11:00:36 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 919DD410EE for ; Sun, 30 May 2021 11:00:34 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id F0E847DC0; Sun, 30 May 2021 02:00:32 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com F0E847DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365234; bh=zmyu0e5BJAkMIAGlzg2qT1bFC+NI8YafdOs+3e+cDKQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hE1rv8wmO9v3p13CklLJbw0KLY9vclCoBTKSvwSnHLqKrIca2t/7RqQtJyqKy+u07 m9WnHjbpaELj3kMyvdAsU+iUULZCeXIKCNn7fA80JcOv9bWvGqiJxFP0F6zHMSMZFl RRg7Q4GT2wdNQOdcXdlAXgdg1fH3S6uvoiuL2GXg= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:36 +0530 Message-Id: <20210530085929.29695-6-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 05/58] net/bnxt: update TRUFLOW resources X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith - Remove unused tables from tf_tbl_type - Encode flow type into flow handle (internal or external) - Clean up Whitney resource tables - Clean up Truflow CLI open tables and update Thor resources - Add Thor SRAM and external pool types to core API - Remove unneeded Stingray table reference Signed-off-by: Farah Smith Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Jay Ding Reviewed-by: Peter Spreadborough --- drivers/net/bnxt/tf_core/tf_core.c | 9 +- drivers/net/bnxt/tf_core/tf_core.h | 83 +++++---- drivers/net/bnxt/tf_core/tf_device.c | 5 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 105 ++++------- drivers/net/bnxt/tf_core/tf_device_p4.h | 175 ++++++++++-------- drivers/net/bnxt/tf_core/tf_device_p45.h | 105 ----------- drivers/net/bnxt/tf_core/tf_device_p58.c | 61 +++--- drivers/net/bnxt/tf_core/tf_device_p58.h | 6 + drivers/net/bnxt/tf_core/tf_em_common.c | 2 +- drivers/net/bnxt/tf_core/tf_em_internal.c | 2 +- drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 15 +- drivers/net/bnxt/tf_core/tf_msg.c | 3 +- drivers/net/bnxt/tf_core/tf_rm.c | 14 +- drivers/net/bnxt/tf_core/tf_shadow_tbl.c | 2 - drivers/net/bnxt/tf_core/tf_util.c | 8 +- 15 files changed, 246 insertions(+), 349 deletions(-) delete mode 100644 drivers/net/bnxt/tf_core/tf_device_p45.h diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index b1ce4e721c..ebe0fc34aa 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -19,6 +19,7 @@ #include "rand.h" #include "tf_common.h" #include "hwrm_tf.h" +#include "tf_ext_flow_handle.h" int tf_open_session(struct tf *tfp, @@ -251,6 +252,7 @@ int tf_delete_em_entry(struct tf *tfp, struct tf_session *tfs; struct tf_dev_info *dev; int rc; + unsigned int flag = 0; TF_CHECK_PARMS2(tfp, parms); @@ -274,12 +276,11 @@ int tf_delete_em_entry(struct tf *tfp, return rc; } - if (parms->mem == TF_MEM_EXTERNAL) - rc = dev->ops->tf_dev_delete_ext_em_entry(tfp, parms); - else if (parms->mem == TF_MEM_INTERNAL) + TF_GET_FLAG_FROM_FLOW_HANDLE(parms->flow_handle, flag); + if ((flag & TF_FLAGS_FLOW_HANDLE_INTERNAL)) rc = dev->ops->tf_dev_delete_int_em_entry(tfp, parms); else - return -EINVAL; + rc = dev->ops->tf_dev_delete_ext_em_entry(tfp, parms); if (rc) { TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 5e458c58fb..4fe0590569 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -158,34 +158,40 @@ enum tf_device_type { */ enum tf_identifier_type { /** + * WH/SR/TH/SR2 * The L2 Context is returned from the L2 Ctxt TCAM lookup * and can be used in WC TCAM or EM keys to virtualize further * lookups. */ TF_IDENT_TYPE_L2_CTXT_HIGH, /** + * WH/SR/TH/SR2 * The L2 Context is returned from the L2 Ctxt TCAM lookup * and can be used in WC TCAM or EM keys to virtualize further * lookups. */ TF_IDENT_TYPE_L2_CTXT_LOW, /** + * WH/SR/TH/SR2 * The WC profile func is returned from the L2 Ctxt TCAM lookup * to enable virtualization of the profile TCAM. */ TF_IDENT_TYPE_PROF_FUNC, /** + * WH/SR/TH/SR2 * The WC profile ID is included in the WC lookup key * to enable virtualization of the WC TCAM hardware. */ TF_IDENT_TYPE_WC_PROF, /** + * WH/SR/TH/SR2 * The EM profile ID is included in the EM lookup key * to enable virtualization of the EM hardware. (not required for SR2 * as it has table scope) */ TF_IDENT_TYPE_EM_PROF, /** + * TH/SR2 * The L2 func is included in the ILT result and from recycling to * enable virtualization of further lookups. */ @@ -203,59 +209,63 @@ enum tf_identifier_type { enum tf_tbl_type { /* Internal */ - /** Wh+/SR Action Record */ + /** Wh+/SR/TH Action Record */ TF_TBL_TYPE_FULL_ACT_RECORD, - /** Wh+/SR/Th Multicast Groups */ + /** TH Compact Action Record */ + TF_TBL_TYPE_COMPACT_ACT_RECORD, + /** (Future) Multicast Groups */ TF_TBL_TYPE_MCAST_GROUPS, - /** Wh+/SR Action Encap 8 Bytes */ + /** Wh+/SR/TH Action Encap 8 Bytes */ TF_TBL_TYPE_ACT_ENCAP_8B, - /** Wh+/SR Action Encap 16 Bytes */ + /** Wh+/SR/TH Action Encap 16 Bytes */ TF_TBL_TYPE_ACT_ENCAP_16B, - /** Action Encap 32 Bytes */ + /** WH+/SR/TH Action Encap 32 Bytes */ TF_TBL_TYPE_ACT_ENCAP_32B, - /** Wh+/SR Action Encap 64 Bytes */ + /** Wh+/SR/TH Action Encap 64 Bytes */ TF_TBL_TYPE_ACT_ENCAP_64B, - /** Action Source Properties SMAC */ + /** WH+/SR/TH Action Source Properties SMAC */ TF_TBL_TYPE_ACT_SP_SMAC, - /** Wh+/SR Action Source Properties SMAC IPv4 */ + /** Wh+/SR/TH Action Source Properties SMAC IPv4 */ TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - /** Action Source Properties SMAC IPv6 */ + /** WH+/SR/TH Action Source Properties SMAC IPv6 */ TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - /** Wh+/SR Action Statistics 64 Bits */ + /** Wh+/SR/TH Action Statistics 64 Bits */ TF_TBL_TYPE_ACT_STATS_64, - /** Wh+/SR Action Modify L4 Src Port */ - TF_TBL_TYPE_ACT_MODIFY_SPORT, - /** Wh+/SR Action Modify L4 Dest Port */ - TF_TBL_TYPE_ACT_MODIFY_DPORT, /** Wh+/SR Action Modify IPv4 Source */ TF_TBL_TYPE_ACT_MODIFY_IPV4, - /** Meter Profiles */ + /** TH 8B Modify Record */ + TF_TBL_TYPE_ACT_MODIFY_8B, + /** TH 16B Modify Record */ + TF_TBL_TYPE_ACT_MODIFY_16B, + /** TH 32B Modify Record */ + TF_TBL_TYPE_ACT_MODIFY_32B, + /** TH 64B Modify Record */ + TF_TBL_TYPE_ACT_MODIFY_64B, + /** (Future) Meter Profiles */ TF_TBL_TYPE_METER_PROF, - /** Meter Instance */ + /** (Future) Meter Instance */ TF_TBL_TYPE_METER_INST, - /** Mirror Config */ + /** Wh+/SR/Th Mirror Config */ TF_TBL_TYPE_MIRROR_CONFIG, - /** UPAR */ + /** (Future) UPAR */ TF_TBL_TYPE_UPAR, - /** SR2 Epoch 0 table */ + /** (Future) SR2 Epoch 0 table */ TF_TBL_TYPE_EPOCH0, - /** SR2 Epoch 1 table */ + /** (Future) SR2 Epoch 1 table */ TF_TBL_TYPE_EPOCH1, - /** SR2 Metadata */ + /** (Future) TH/SR2 Metadata */ TF_TBL_TYPE_METADATA, - /** SR2 CT State */ + /** (Future) TH/SR2 CT State */ TF_TBL_TYPE_CT_STATE, - /** SR2 Range Profile */ + /** (Future) TH/SR2 Range Profile */ TF_TBL_TYPE_RANGE_PROF, - /** SR2 Range Entry */ + /** (Future) SR2 Range Entry */ TF_TBL_TYPE_RANGE_ENTRY, - /** SR2 LAG Entry */ + /** (Future) SR2 LAG Entry */ TF_TBL_TYPE_LAG, - /** SR2 VNIC/SVIF Table */ - TF_TBL_TYPE_VNIC_SVIF, - /** Th/SR2 EM Flexible Key builder */ + /** TH/SR2 EM Flexible Key builder */ TF_TBL_TYPE_EM_FKB, - /** Th/SR2 WC Flexible Key builder */ + /** TH/SR2 WC Flexible Key builder */ TF_TBL_TYPE_WC_FKB, /* External */ @@ -263,9 +273,18 @@ enum tf_tbl_type { /** * External table type - initially 1 poolsize entries. * All External table types are associated with a table - * scope. Internal types are not. + * scope. Internal types are not. Currently this is + * a pool of 64B entries. */ TF_TBL_TYPE_EXT, + /* (Future) SR2 32B External EM Action 32B Pool */ + TF_TBL_TYPE_EXT_32B, + /* (Future) SR2 64B External EM Action 64B Pool */ + TF_TBL_TYPE_EXT_64B, + /* (Future) SR2 96B External EM Action 96B Pool */ + TF_TBL_TYPE_EXT_96B, + /* (Future) SR2 128B External EM Action 128B Pool */ + TF_TBL_TYPE_EXT_128B, TF_TBL_TYPE_MAX }; @@ -1998,8 +2017,8 @@ enum tf_if_tbl_type { TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, /** SR2 Ingress lookup table */ TF_IF_TBL_TYPE_ILT, - /** SR2 VNIC/SVIF Table */ - TF_IF_TBL_TYPE_VNIC_SVIF, + /** SR2 VNIC/SVIF Properties Table */ + TF_IF_TBL_TYPE_VSPT, TF_IF_TBL_TYPE_MAX }; diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index d4c93439ec..d072b9877c 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -153,11 +153,8 @@ tf_dev_bind_p4(struct tf *tfp, /* * EEM */ - if (dev_handle->type == TF_DEVICE_TYPE_WH) - em_cfg.cfg = tf_em_ext_p4; - else - em_cfg.cfg = tf_em_ext_p45; + em_cfg.cfg = tf_em_ext_p4; rsv_cnt = tf_dev_reservation_check(tfp, TF_EM_TBL_TYPE_MAX, em_cfg.cfg, diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 6b28f6ce59..f6c8f5efd0 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -19,76 +19,41 @@ #define TF_DEV_P4_PF_MASK 0xfUL const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { - /* CFA_RESOURCE_TYPE_P4_MCG */ - "mc_group", - /* CFA_RESOURCE_TYPE_P4_ENCAP_8B */ - "encap_8 ", - /* CFA_RESOURCE_TYPE_P4_ENCAP_16B */ - "encap_16", - /* CFA_RESOURCE_TYPE_P4_ENCAP_64B */ - "encap_64", - /* CFA_RESOURCE_TYPE_P4_SP_MAC */ - "sp_mac ", - /* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 */ - "sp_macv4", - /* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 */ - "sp_macv6", - /* CFA_RESOURCE_TYPE_P4_COUNTER_64B */ - "ctr_64b ", - /* CFA_RESOURCE_TYPE_P4_NAT_PORT */ - "nat_port", - /* CFA_RESOURCE_TYPE_P4_NAT_IPV4 */ - "nat_ipv4", - /* CFA_RESOURCE_TYPE_P4_METER */ - "meter ", - /* CFA_RESOURCE_TYPE_P4_FLOW_STATE */ - "flow_st ", - /* CFA_RESOURCE_TYPE_P4_FULL_ACTION */ - "full_act", - /* CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION */ - "fmt0_act", - /* CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION */ - "ext0_act", - /* CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION */ - "fmt1_act", - /* CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION */ - "fmt2_act", - /* CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION */ - "fmt3_act", - /* CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION */ - "fmt4_act", - /* CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION */ - "fmt5_act", - /* CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION */ - "fmt6_act", - /* CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH */ - "l2ctx_hi", - /* CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW */ - "l2ctx_lo", - /* CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH */ - "l2ctr_hi", - /* CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW */ - "l2ctr_lo", - /* CFA_RESOURCE_TYPE_P4_PROF_FUNC */ - "prf_func", - /* CFA_RESOURCE_TYPE_P4_PROF_TCAM */ - "prf_tcam", - /* CFA_RESOURCE_TYPE_P4_EM_PROF_ID */ - "em_prof ", - /* CFA_RESOURCE_TYPE_P4_EM_REC */ - "em_rec ", - /* CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID */ - "wc_prof ", - /* CFA_RESOURCE_TYPE_P4_WC_TCAM */ - "wc_tcam ", - /* CFA_RESOURCE_TYPE_P4_METER_PROF */ - "mtr_prof", - /* CFA_RESOURCE_TYPE_P4_MIRROR */ - "mirror ", - /* CFA_RESOURCE_TYPE_P4_SP_TCAM */ - "sp_tcam ", - /* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */ - "tb_scope", + [CFA_RESOURCE_TYPE_P4_MCG] = "mc_group", + [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = "encap_8 ", + [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = "encap_16", + [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = "encap_64", + [CFA_RESOURCE_TYPE_P4_SP_MAC] = "sp_mac ", + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = "sp_macv4", + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = "sp_macv6", + [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = "ctr_64b ", + [CFA_RESOURCE_TYPE_P4_NAT_PORT] = "nat_port", + [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = "nat_ipv4", + [CFA_RESOURCE_TYPE_P4_METER] = "meter ", + [CFA_RESOURCE_TYPE_P4_FLOW_STATE] = "flow_st ", + [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = "full_act", + [CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION] = "fmt0_act", + [CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION] = "ext0_act", + [CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION] = "fmt1_act", + [CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION] = "fmt2_act", + [CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION] = "fmt3_act", + [CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION] = "fmt4_act", + [CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION] = "fmt5_act", + [CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION] = "fmt6_act", + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = "l2ctx_hi", + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = "l2ctx_lo", + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = "l2ctr_hi", + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = "l2ctr_lo", + [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = "prf_func", + [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = "prf_tcam", + [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = "em_prof ", + [CFA_RESOURCE_TYPE_P4_EM_REC] = "em_rec ", + [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = "wc_prof ", + [CFA_RESOURCE_TYPE_P4_WC_TCAM] = "wc_tcam ", + [CFA_RESOURCE_TYPE_P4_METER_PROF] = "mtr_prof", + [CFA_RESOURCE_TYPE_P4_MIRROR] = "mirror ", + [CFA_RESOURCE_TYPE_P4_SP_TCAM] = "sp_tcam ", + [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope", }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index bfad02a0b8..ee283ce29d 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -13,98 +13,123 @@ #include "tf_global_cfg.h" struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID }, - /* CFA_RESOURCE_TYPE_P4_L2_FUNC */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } + [TF_IDENT_TYPE_L2_CTXT_HIGH] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH + }, + [TF_IDENT_TYPE_L2_CTXT_LOW] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW + }, + [TF_IDENT_TYPE_PROF_FUNC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC + }, + [TF_IDENT_TYPE_WC_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID + }, + [TF_IDENT_TYPE_EM_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID + }, }; struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM }, - /* CFA_RESOURCE_TYPE_P4_CT_RULE_TCAM */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_VEB_TCAM */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } + [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH + }, + [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW + }, + [TF_TCAM_TBL_TYPE_PROF_TCAM] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM + }, + [TF_TCAM_TBL_TYPE_WC_TCAM] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM + }, + [TF_TCAM_TBL_TYPE_SP_TCAM] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM + }, }; struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B }, - /* CFA_RESOURCE_TYPE_P4_ENCAP_32B */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR }, - /* CFA_RESOURCE_TYPE_P4_UPAR */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_EPOC */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_METADATA */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_CT_STATE */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_RANGE_PROF */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_RANGE_ENTRY */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_LAG */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_VNIC_SVIF */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_EM_FBK */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_WC_FKB */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P4_EXT */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } -}; + [TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION + }, + [TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG + }, + [TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B + }, + [TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B + }, + [TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B + }, + [TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC + }, + [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 + }, + [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 + }, + [TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B + }, + [TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 + }, + [TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF + }, + [TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER + }, + [TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR + }, -struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { - /* CFA_RESOURCE_TYPE_P4_EM_REC */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE }, }; -struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = { - /* CFA_RESOURCE_TYPE_P4_EM_REC */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE }, +struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { + [TF_EM_TBL_TYPE_TBL_SCOPE] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE + }, }; struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC }, - /* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + [TF_EM_TBL_TYPE_EM_RECORD] = { + TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC + }, }; +/* Note that hcapi_types from this table are from hcapi_cfa_p4.h + * These are not CFA resource types because they are not allocated + * CFA resources - they are identifiers for the interface tables + * shared between the firmware and the host. It may make sense to + * move these types to cfa_resource_types.h. + */ struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = { - { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT }, - { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR }, - { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR }, - { TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR }, - { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }, - { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID } + [TF_IF_TBL_TYPE_PROF_SPIF_DFLT_L2_CTXT] = { + TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT + }, + [TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = { + TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR + }, + [TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = { + TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR + }, + [TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR] = { + TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR + }, }; struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { - { TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP }, - { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, + [TF_TUNNEL_ENCAP] = { + TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP + }, + [TF_ACTION_BLOCK] = { + TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK + }, }; #endif /* _TF_DEVICE_P4_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h b/drivers/net/bnxt/tf_core/tf_device_p45.h deleted file mode 100644 index 13e04c63fc..0000000000 --- a/drivers/net/bnxt/tf_core/tf_device_p45.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ - -#ifndef _TF_DEVICE_P45_H_ -#define _TF_DEVICE_P45_H_ - -#include - -#include "tf_core.h" -#include "tf_rm.h" -#include "tf_if_tbl.h" -#include "tf_global_cfg.h" - -struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID }, - /* CFA_RESOURCE_TYPE_P45_L2_FUNC */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } -}; - -struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM }, - /* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_VEB_TCAM */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } -}; - -struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B }, - /* CFA_RESOURCE_TYPE_P45_ENCAP_32B */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR }, - /* CFA_RESOURCE_TYPE_P45_UPAR */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_EPOC */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_METADATA */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_CT_STATE */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_RANGE_PROF */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_LAG */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_EM_FBK */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_WC_FKB */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - /* CFA_RESOURCE_TYPE_P45_EXT */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } -}; - -struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { - /* CFA_RESOURCE_TYPE_P45_EM_REC */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE }, -}; - -struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC }, - /* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */ - { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, -}; - -struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = { - { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT }, - { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR }, - { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR }, - { TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR }, - { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }, - { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID } -}; - -struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { - { TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP }, - { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, -}; -#endif /* _TF_DEVICE_P45_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index b4530f8762..7dd806000c 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -18,47 +18,28 @@ #define TF_DEV_P58_PARIF_MAX 16 #define TF_DEV_P58_PF_MASK 0xfUL +/* For print alignment, make all entries 8 chars in this table */ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { - /* CFA_RESOURCE_TYPE_P58_METER */ - "meter ", - /* CFA_RESOURCE_TYPE_P58_SRAM_BANK_0 */ - "sram_bk0", - /* CFA_RESOURCE_TYPE_P58_SRAM_BANK_1 */ - "sram_bk1", - /* CFA_RESOURCE_TYPE_P58_SRAM_BANK_2 */ - "sram_bk2", - /* CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 */ - "sram_bk3", - /* CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH */ - "l2ctx_hi", - /* CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW */ - "l2ctx_lo", - /* CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH */ - "l2ctr_hi", - /* CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW */ - "l2ctr_lo", - /* CFA_RESOURCE_TYPE_P58_PROF_FUNC */ - "prf_func", - /* CFA_RESOURCE_TYPE_P58_PROF_TCAM */ - "prf_tcam", - /* CFA_RESOURCE_TYPE_P58_EM_PROF_ID */ - "em_prof ", - /* CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID */ - "wc_prof ", - /* CFA_RESOURCE_TYPE_P58_EM_REC */ - "em_rec ", - /* CFA_RESOURCE_TYPE_P58_WC_TCAM */ - "wc_tcam ", - /* CFA_RESOURCE_TYPE_P58_METER_PROF */ - "mtr_prof", - /* CFA_RESOURCE_TYPE_P58_MIRROR */ - "mirror ", - /* CFA_RESOURCE_TYPE_P58_EM_FKB */ - "em_fkb ", - /* CFA_RESOURCE_TYPE_P58_WC_FKB */ - "wc_fkb ", - /* CFA_RESOURCE_TYPE_P58_VEB_TCAM */ - "veb ", + [CFA_RESOURCE_TYPE_P58_METER] = "meter ", + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = "sram_bk0", + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = "sram_bk1", + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = "sram_bk2", + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = "sram_bk3", + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = "l2ctx_hi", + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = "l2ctx_lo", + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = "l2ctr_hi", + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = "l2ctr_lo", + [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = "prf_func", + [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = "prf_tcam", + [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = "em_prof ", + [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = "wc_prof ", + [CFA_RESOURCE_TYPE_P58_EM_REC] = "em_rec ", + [CFA_RESOURCE_TYPE_P58_WC_TCAM] = "wc_tcam ", + [CFA_RESOURCE_TYPE_P58_METER_PROF] = "mtr_prof", + [CFA_RESOURCE_TYPE_P58_MIRROR] = "mirror ", + [CFA_RESOURCE_TYPE_P58_EM_FKB] = "em_fkb ", + [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", + [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 3d6e3240bf..de7bb1cd76 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -49,6 +49,12 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = { }; struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { + [TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB + }, + [TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB + }, [TF_TBL_TYPE_METER_PROF] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF }, diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index ddc6b3c4dd..6cd6086685 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -777,7 +777,7 @@ tf_insert_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, TF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle, 0, 0, - 0, + TF_FLAGS_FLOW_HANDLE_EXTERNAL, index, 0, table_type); diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 62ccd7b78f..bdffd801b3 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -203,7 +203,7 @@ tf_em_insert_int_entry(struct tf *tfp, TF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle, (uint32_t)num_of_entries, 0, - 0, + TF_FLAGS_FLOW_HANDLE_INTERNAL, rptr_index, rptr_entry, 0); diff --git a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h index 9eb5aeb771..bf6dbcd238 100644 --- a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h +++ b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h @@ -19,6 +19,9 @@ #define TF_HASH_TYPE_FLOW_HANDLE_MASK 0x0000000100000000ULL #define TF_HASH_TYPE_FLOW_HANDLE_SFT 32 +#define TF_FLAGS_FLOW_HANDLE_INTERNAL 0x2 +#define TF_FLAGS_FLOW_HANDLE_EXTERNAL 0x0 + #define TF_FLOW_HANDLE_MASK (TF_NUM_KEY_ENTRIES_FLOW_HANDLE_MASK | \ TF_FLOW_TYPE_FLOW_HANDLE_MASK | \ TF_FLAGS_FLOW_HANDLE_MASK | \ @@ -92,15 +95,23 @@ do { \ #define TF_GET_NUM_KEY_ENTRIES_FROM_FLOW_HANDLE(flow_handle, \ num_key_entries) \ +do { \ (num_key_entries = \ (((flow_handle) & TF_NUM_KEY_ENTRIES_FLOW_HANDLE_MASK) >> \ - TF_NUM_KEY_ENTRIES_FLOW_HANDLE_SFT)) \ + TF_NUM_KEY_ENTRIES_FLOW_HANDLE_SFT)); \ +} while (0) #define TF_GET_ENTRY_NUM_FROM_FLOW_HANDLE(flow_handle, \ entry_num) \ +do { \ (entry_num = \ (((flow_handle) & TF_ENTRY_NUM_FLOW_HANDLE_MASK) >> \ - TF_ENTRY_NUM_FLOW_HANDLE_SFT)) \ + TF_ENTRY_NUM_FLOW_HANDLE_SFT)); \ +} while (0) + +#define TF_GET_FLAG_FROM_FLOW_HANDLE(flow_handle, flag) \ + (flag = (((flow_handle) & TF_FLAGS_FLOW_HANDLE_MASK) >>\ + TF_FLAGS_FLOW_HANDLE_SFT)) /* * 32 bit Flow ID handlers diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 1007211363..be30d4a09f 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -415,7 +415,6 @@ tf_msg_session_resc_qcaps(struct tf *tfp, /* Post process the response */ data = (struct tf_rm_resc_req_entry *)qcaps_buf.va_addr; - for (i = 0; i < size; i++) { query[i].type = tfp_le_to_cpu_32(data[i].type); query[i].min = tfp_le_to_cpu_16(data[i].min); @@ -1462,7 +1461,7 @@ tf_msg_set_global_cfg(struct tf *tfp, /* Only set mask if pointer is provided */ if (params->config_mask) { - tfp_memcpy(req.data + params->config_sz_in_bytes, + tfp_memcpy(req.mask, params->config_mask, params->config_sz_in_bytes); } diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index 2c08fb80fe..19de6e4c63 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -486,14 +486,20 @@ tf_rm_create_db(struct tf *tfp, req[j].max = parms->alloc_cnt[i]; j++; } else { + const char *type_str; + uint16_t hcapi_type = parms->cfg[i].hcapi_type; + + dev->ops->tf_dev_get_resource_str(tfp, + hcapi_type, + &type_str); TFP_DRV_LOG(ERR, - "%s: Resource failure, type:%d\n", - tf_dir_2_str(parms->dir), - parms->cfg[i].hcapi_type); + "%s: Resource failure, type:%d:%s\n", + tf_dir_2_str(parms->dir), + hcapi_type, type_str); TFP_DRV_LOG(ERR, "req:%d, avail:%d\n", parms->alloc_cnt[i], - query[parms->cfg[i].hcapi_type].max); + query[hcapi_type].max); return -EINVAL; } } diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tbl.c b/drivers/net/bnxt/tf_core/tf_shadow_tbl.c index 014e4f3c83..396ebdb0a9 100644 --- a/drivers/net/bnxt/tf_core/tf_shadow_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_shadow_tbl.c @@ -177,8 +177,6 @@ static int tf_shadow_tbl_is_searchable(enum tf_tbl_type type) case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: case TF_TBL_TYPE_ACT_MODIFY_IPV4: - case TF_TBL_TYPE_ACT_MODIFY_SPORT: - case TF_TBL_TYPE_ACT_MODIFY_DPORT: rc = 1; break; default: diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index ca37df5102..74c8f26204 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -88,12 +88,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type) return "Source Properties SMAC IPv6"; case TF_TBL_TYPE_ACT_STATS_64: return "Stats 64B"; - case TF_TBL_TYPE_ACT_MODIFY_SPORT: - return "NAT Source Port"; - case TF_TBL_TYPE_ACT_MODIFY_DPORT: - return "NAT Destination Port"; case TF_TBL_TYPE_ACT_MODIFY_IPV4: - return "NAT IPv4"; + return "Modify IPv4"; case TF_TBL_TYPE_METER_PROF: return "Meter Profile"; case TF_TBL_TYPE_METER_INST: @@ -116,8 +112,6 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type) return "Range"; case TF_TBL_TYPE_LAG: return "Link Aggregation"; - case TF_TBL_TYPE_VNIC_SVIF: - return "VNIC SVIF"; case TF_TBL_TYPE_EM_FKB: return "EM Flexible Key Builder"; case TF_TBL_TYPE_WC_FKB: From patchwork Sun May 30 08:58:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93555 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E0415A0524; Sun, 30 May 2021 11:01:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0CCEA410EF; Sun, 30 May 2021 11:00:39 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 4D40C40395 for ; Sun, 30 May 2021 11:00:36 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id ABEFE7DC2; Sun, 30 May 2021 02:00:34 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com ABEFE7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365235; bh=Nk/8Qth0QhEqihjsXL/84mhNxjMhggbsksolIErIvjE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=khIex4Y4q3+doNAsIsPS+ib57xYxk8DsNZAOfR9TnP2LZgIhlTtouKZv7GHmwFW8M DGfGCfBnqVn09WXaXu5PkNgxEsta7JvBUHQ3P2XqmIJWuz4MZYbuQVdV3ccZnY39H4 qZ3ws87iTUbYEY8xulHvOMuAs6LTN25zvUhEqgpM= From: Venkat Duvvuru To: dev@dpdk.org Cc: Peter Spreadborough , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:37 +0530 Message-Id: <20210530085929.29695-7-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 06/58] net/bnxt: add support for EM with FKB X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Peter Spreadborough Main TF changes to support EM insert with FKB. Flexible Key builder is required to create Wild Card and Exact Match keys for TCAM lookups. Signed-off-by: Peter Spreadborough Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_core/meson.build | 1 + drivers/net/bnxt/tf_core/tf_device_p58.c | 14 +- drivers/net/bnxt/tf_core/tf_em.h | 32 +++++ .../net/bnxt/tf_core/tf_em_hash_internal.c | 123 ++++++++++++++++++ drivers/net/bnxt/tf_core/tf_em_internal.c | 3 +- drivers/net/bnxt/tf_core/tf_msg.c | 96 ++++++++++++++ drivers/net/bnxt/tf_core/tf_msg.h | 35 +++++ 7 files changed, 295 insertions(+), 9 deletions(-) create mode 100644 drivers/net/bnxt/tf_core/tf_em_hash_internal.c diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index d7e8f664fd..373ee0413b 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -30,5 +30,6 @@ sources += files( 'll.c', 'tf_global_cfg.c', 'tf_em_host.c', + 'tf_em_hash_internal.c', 'tf_shadow_identifier.c', 'tf_hash.c') diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 7dd806000c..6cef1d5ba5 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -256,14 +256,14 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_set_tcam = tf_tcam_set, .tf_dev_get_tcam = NULL, - .tf_dev_insert_int_em_entry = tf_em_insert_int_entry, - .tf_dev_delete_int_em_entry = tf_em_delete_int_entry, - .tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry, - .tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry, - .tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc, - .tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope, + .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, + .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, + .tf_dev_insert_ext_em_entry = NULL, + .tf_dev_delete_ext_em_entry = NULL, + .tf_dev_alloc_tbl_scope = NULL, + .tf_dev_map_tbl_scope = NULL, .tf_dev_map_parif = tf_dev_p58_map_parif, - .tf_dev_free_tbl_scope = tf_em_ext_common_free, + .tf_dev_free_tbl_scope = NULL, .tf_dev_set_if_tbl = tf_if_tbl_set, .tf_dev_get_if_tbl = tf_if_tbl_get, .tf_dev_set_global_cfg = tf_global_cfg_set, diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index b5c3acb09a..5a67ca3509 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -197,6 +197,38 @@ int tf_em_insert_int_entry(struct tf *tfp, int tf_em_delete_int_entry(struct tf *tfp, struct tf_delete_em_entry_parms *parms); +/** + * Insert record in to internal EM table + * + * [in] tfp + * Pointer to TruFlow handle + * + * [in] parms + * Pointer to input parameters + * + * Returns: + * 0 - Success + * -EINVAL - Parameter error + */ +int tf_em_hash_insert_int_entry(struct tf *tfp, + struct tf_insert_em_entry_parms *parms); + +/** + * Delete record from internal EM table + * + * [in] tfp + * Pointer to TruFlow handle + * + * [in] parms + * Pointer to input parameters + * + * Returns: + * 0 - Success + * -EINVAL - Parameter error + */ +int tf_em_hash_delete_int_entry(struct tf *tfp, + struct tf_delete_em_entry_parms *parms); + /** * Insert record in to external EEM table * diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c new file mode 100644 index 0000000000..09183b42f0 --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#include +#include +#include +#include + +#include "tf_core.h" +#include "tf_util.h" +#include "tf_common.h" +#include "tf_em.h" +#include "tf_msg.h" +#include "tfp.h" +#include "tf_ext_flow_handle.h" + +#include "bnxt.h" + +/** + * EM Pool + */ +extern struct stack em_pool[TF_DIR_MAX]; + +/** + * Insert EM internal entry API + * + * returns: + * 0 - Success + */ +int +tf_em_hash_insert_int_entry(struct tf *tfp, + struct tf_insert_em_entry_parms *parms) +{ + int rc; + uint32_t gfid; + uint16_t rptr_index = 0; + uint8_t rptr_entry = 0; + uint8_t num_of_entries = 0; + struct stack *pool = &em_pool[parms->dir]; + uint32_t index; + uint32_t key0_hash; + uint32_t key1_hash; + uint64_t big_hash; + + rc = stack_pop(pool, &index); + if (rc) { + PMD_DRV_LOG(ERR, + "%s, EM entry index allocation failed\n", + tf_dir_2_str(parms->dir)); + return rc; + } + + big_hash = hcapi_cfa_key_hash((uint64_t *)parms->key, + (TF_HW_EM_KEY_MAX_SIZE + 4) * 8); + key0_hash = (uint32_t)(big_hash >> 32); + key1_hash = (uint32_t)(big_hash & 0xFFFFFFFF); + + rptr_index = index; + rc = tf_msg_hash_insert_em_internal_entry(tfp, + parms, + key0_hash, + key1_hash, + &rptr_index, + &rptr_entry, + &num_of_entries); + if (rc) { + /* Free the allocated index before returning */ + stack_push(pool, index); + return -1; + } + + PMD_DRV_LOG + (DEBUG, + "%s, Internal entry @ Index:%d rptr_index:0x%x rptr_entry:0x%x num_of_entries:%d\n", + tf_dir_2_str(parms->dir), + index, + rptr_index, + rptr_entry, + num_of_entries); + + TF_SET_GFID(gfid, + ((rptr_index << TF_EM_INTERNAL_INDEX_SHIFT) | + rptr_entry), + 0); /* N/A for internal table */ + + TF_SET_FLOW_ID(parms->flow_id, + gfid, + TF_GFID_TABLE_INTERNAL, + parms->dir); + + TF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle, + (uint32_t)num_of_entries, + 0, + 0, + rptr_index, + rptr_entry, + 0); + return 0; +} + +/** Delete EM internal entry API + * + * returns: + * 0 + * -EINVAL + */ +int +tf_em_hash_delete_int_entry(struct tf *tfp, + struct tf_delete_em_entry_parms *parms) +{ + int rc = 0; + struct stack *pool = &em_pool[parms->dir]; + + rc = tf_msg_delete_em_entry(tfp, parms); + + /* Return resource to pool */ + if (rc == 0) + stack_push(pool, parms->index); + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index bdffd801b3..0864218469 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -30,11 +30,10 @@ static void *em_db[TF_DIR_MAX]; */ static uint8_t init; - /** * EM Pool */ -static struct stack em_pool[TF_DIR_MAX]; +struct stack em_pool[TF_DIR_MAX]; /** * Create EM Tbl pool of memory indexes. diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index be30d4a09f..39d7e3eace 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -25,6 +25,7 @@ */ #define TF_MSG_SET_GLOBAL_CFG_DATA_SIZE 16 #define TF_MSG_EM_INSERT_KEY_SIZE 64 +#define TF_MSG_EM_INSERT_RECORD_SIZE 80 #define TF_MSG_TBL_TYPE_SET_DATA_SIZE 88 /* Compile check - Catch any msg changes that we depend on, like the @@ -706,6 +707,101 @@ tf_msg_insert_em_internal_entry(struct tf *tfp, return 0; } +int +tf_msg_hash_insert_em_internal_entry(struct tf *tfp, + struct tf_insert_em_entry_parms *em_parms, + uint32_t key0_hash, + uint32_t key1_hash, + uint16_t *rptr_index, + uint8_t *rptr_entry, + uint8_t *num_of_entries) +{ + int rc; + struct tfp_send_msg_parms parms = { 0 }; + struct hwrm_tf_em_hash_insert_input req = { 0 }; + struct hwrm_tf_em_hash_insert_output resp = { 0 }; + uint16_t flags; + uint8_t fw_session_id; + uint8_t msg_record_size; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Unable to lookup FW id, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + /* Populate the request */ + req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + + /* Check for key size conformity */ + msg_record_size = (em_parms->em_record_sz_in_bits + 7) / 8; + + if (msg_record_size > TF_MSG_EM_INSERT_RECORD_SIZE) { + rc = -EINVAL; + TFP_DRV_LOG(ERR, + "%s: Record size to large, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + tfp_memcpy((char *)req.em_record, + em_parms->em_record, + msg_record_size); + + flags = (em_parms->dir == TF_DIR_TX ? + HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX : + HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX); + req.flags = tfp_cpu_to_le_16(flags); + req.em_record_size_bits = em_parms->em_record_sz_in_bits; + req.em_record_idx = *rptr_index; + req.key0_hash = key0_hash; + req.key1_hash = key1_hash; + + parms.tf_type = HWRM_TF_EM_HASH_INSERT; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tfp, + &parms); + if (rc) + return rc; + + *rptr_entry = resp.rptr_entry; + *rptr_index = resp.rptr_index; + *num_of_entries = resp.num_of_entries; + + return 0; +} + int tf_msg_delete_em_entry(struct tf *tfp, struct tf_delete_em_entry_parms *em_parms) diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 25e29a554f..1d82ce5049 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -225,6 +225,41 @@ int tf_msg_insert_em_internal_entry(struct tf *tfp, uint16_t *rptr_index, uint8_t *rptr_entry, uint8_t *num_of_entries); +/** + * Sends EM hash internal insert request to Firmware + * + * [in] tfp + * Pointer to TF handle + * + * [in] params + * Pointer to em insert parameter list + * + * [in] key0_hash + * CRC32 hash of key + * + * [in] key1_hash + * Lookup3 hash of key + * + * [in] rptr_index + * Record ptr index + * + * [in] rptr_entry + * Record ptr entry + * + * [in] num_of_entries + * Number of entries to insert + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_hash_insert_em_internal_entry(struct tf *tfp, + struct tf_insert_em_entry_parms *em_parms, + uint32_t key0_hash, + uint32_t key1_hash, + uint16_t *rptr_index, + uint8_t *rptr_entry, + uint8_t *num_of_entries); /** * Sends EM internal delete request to Firmware * From patchwork Sun May 30 08:58:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93556 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2DDDDA0524; Sun, 30 May 2021 11:01:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 27CCA41124; Sun, 30 May 2021 11:00:40 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 08BB54111E for ; Sun, 30 May 2021 11:00:38 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 676537DAF; Sun, 30 May 2021 02:00:36 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 676537DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365237; bh=3SvcjBIqnljYBe0eQooSp4YaYghY+KdPl06ToNwaoVI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nL/yzprUN7hV9V7/1HyoxJ4nkunWWgelTwfi4U5PlUx93mKFRibE6zd6ue93bStRK HT06vWzLfNg6+WQ9RFMKnBAZfHMWepQyzf8PrLeIgmhLGRTOo42RU+gNM/LzZQ4wzm gQIvMzibRRz0xG2krStQW8UAre+rv65wH/7ETaX0= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:38 +0530 Message-Id: <20210530085929.29695-8-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 07/58] net/bnxt: add L2 Context TCAM get support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding - Implement TCAM get in host - Add Thor support for TCAM set/free Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Peter Spreadborough Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_core/hwrm_tf.h | 1 + drivers/net/bnxt/tf_core/tf_core.c | 65 +++++++++++++++-- drivers/net/bnxt/tf_core/tf_device.h | 12 ++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 6 ++ drivers/net/bnxt/tf_core/tf_device_p58.c | 9 ++- drivers/net/bnxt/tf_core/tf_msg.c | 52 ++++++++++++++ drivers/net/bnxt/tf_core/tf_msg.h | 16 +++++ drivers/net/bnxt/tf_core/tf_tcam.c | 89 +++++++++++++++++++++++- drivers/net/bnxt/tf_core/tf_tcam.h | 4 ++ 9 files changed, 248 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/tf_core/hwrm_tf.h b/drivers/net/bnxt/tf_core/hwrm_tf.h index a707cd2758..9cc9a1435c 100644 --- a/drivers/net/bnxt/tf_core/hwrm_tf.h +++ b/drivers/net/bnxt/tf_core/hwrm_tf.h @@ -65,6 +65,7 @@ typedef enum tf_subtype { #define TF_BITS2BYTES(x) (((x) + 7) >> 3) #define TF_BITS2BYTES_WORD_ALIGN(x) ((((x) + 31) >> 5) * 4) +#define TF_BITS2BYTES_64B_WORD_ALIGN(x) ((((x) + 63) >> 6) * 8) struct tf_set_global_cfg_input; struct tf_get_global_cfg_input; diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index ebe0fc34aa..a3b6afbc88 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -764,7 +764,8 @@ tf_set_tcam_entry(struct tf *tfp, return rc; } - if (dev->ops->tf_dev_set_tcam == NULL) { + if (dev->ops->tf_dev_set_tcam == NULL || + dev->ops->tf_dev_word_align == NULL) { rc = -EOPNOTSUPP; TFP_DRV_LOG(ERR, "%s: Operation not supported, rc:%s\n", @@ -778,7 +779,7 @@ tf_set_tcam_entry(struct tf *tfp, sparms.idx = parms->idx; sparms.key = parms->key; sparms.mask = parms->mask; - sparms.key_size = TF_BITS2BYTES_WORD_ALIGN(parms->key_sz_in_bits); + sparms.key_size = dev->ops->tf_dev_word_align(parms->key_sz_in_bits); sparms.result = parms->result; sparms.result_size = TF_BITS2BYTES_WORD_ALIGN(parms->result_sz_in_bits); @@ -796,10 +797,66 @@ tf_set_tcam_entry(struct tf *tfp, int tf_get_tcam_entry(struct tf *tfp __rte_unused, - struct tf_get_tcam_entry_parms *parms __rte_unused) + struct tf_get_tcam_entry_parms *parms) { + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + struct tf_tcam_get_parms gparms; + TF_CHECK_PARMS2(tfp, parms); - return -EOPNOTSUPP; + + memset(&gparms, 0, sizeof(struct tf_tcam_get_parms)); + + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + if (dev->ops->tf_dev_get_tcam == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + gparms.dir = parms->dir; + gparms.type = parms->tcam_tbl_type; + gparms.idx = parms->idx; + gparms.key = parms->key; + gparms.mask = parms->mask; + gparms.result = parms->result; + + rc = dev->ops->tf_dev_get_tcam(tfp, &gparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM get failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + parms->key_sz_in_bits = gparms.key_size * 8; + parms->result_sz_in_bits = gparms.result_size * 8; + + return 0; } int diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index cbacc09ea5..4f4120c603 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -736,6 +736,18 @@ struct tf_dev_ops { * mailbox */ int (*tf_dev_get_mailbox)(void); + + /** + * Convert length in bit to length in byte and align to word. + * The word length depends on device type. + * + * [in] size + * Size in bit + * + * Returns + * Size in byte + */ + int (*tf_dev_word_align)(uint16_t size); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index f6c8f5efd0..fbe92b7733 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -212,6 +212,10 @@ static int tf_dev_p4_get_mailbox(void) return TF_KONG_MB; } +static int tf_dev_p4_word_align(uint16_t size) +{ + return ((((size) + 31) >> 5) * 4); +} /** * Truflow P4 device specific functions @@ -250,6 +254,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_set_global_cfg = NULL, .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, + .tf_dev_word_align = NULL, }; /** @@ -289,4 +294,5 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_set_global_cfg = tf_global_cfg_set, .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, + .tf_dev_word_align = tf_dev_p4_word_align, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 6cef1d5ba5..688d987cb7 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -193,6 +193,11 @@ static int tf_dev_p58_get_mailbox(void) return TF_CHIMP_MB; } +static int tf_dev_p58_word_align(uint16_t size) +{ + return ((((size) + 63) >> 6) * 8); +} + /** * Truflow P58 device specific functions */ @@ -230,6 +235,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_set_global_cfg = NULL, .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, + .tf_dev_word_align = NULL, }; /** @@ -255,7 +261,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_free_tcam = tf_tcam_free, .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_set_tcam = tf_tcam_set, - .tf_dev_get_tcam = NULL, + .tf_dev_get_tcam = tf_tcam_get, .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, .tf_dev_insert_ext_em_entry = NULL, @@ -269,4 +275,5 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_set_global_cfg = tf_global_cfg_set, .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, + .tf_dev_word_align = tf_dev_p58_word_align, }; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 39d7e3eace..1af5c6d11c 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1212,6 +1212,58 @@ tf_msg_tcam_entry_set(struct tf *tfp, return rc; } +int +tf_msg_tcam_entry_get(struct tf *tfp, + struct tf_dev_info *dev, + struct tf_tcam_get_parms *parms) +{ + int rc; + struct tfp_send_msg_parms mparms = { 0 }; + struct hwrm_tf_tcam_get_input req = { 0 }; + struct hwrm_tf_tcam_get_output resp = { 0 }; + uint8_t fw_session_id; + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Unable to lookup FW id, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Populate the request */ + req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.type = parms->hcapi_type; + req.idx = tfp_cpu_to_le_16(parms->idx); + if (parms->dir == TF_DIR_TX) + req.flags |= HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX; + + mparms.tf_type = HWRM_TF_TCAM_GET; + mparms.req_data = (uint32_t *)&req; + mparms.req_size = sizeof(req); + mparms.resp_data = (uint32_t *)&resp; + mparms.resp_size = sizeof(resp); + mparms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tfp, + &mparms); + + if (rc != 0) + return rc; + + if (mparms.tf_resp_code != 0) + return tfp_le_to_cpu_32(mparms.tf_resp_code); + + parms->key_size = resp.key_size; + parms->result_size = resp.result_size; + tfp_memcpy(parms->key, resp.dev_data, resp.key_size); + tfp_memcpy(parms->mask, &resp.dev_data[resp.key_size], resp.key_size); + tfp_memcpy(parms->result, &resp.dev_data[resp.result_offset], resp.result_size); + + return tfp_le_to_cpu_32(mparms.tf_resp_code); +} + int tf_msg_tcam_entry_free(struct tf *tfp, struct tf_dev_info *dev, diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 1d82ce5049..a14bcd3927 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -412,6 +412,22 @@ int tf_msg_tcam_entry_set(struct tf *tfp, struct tf_dev_info *dev, struct tf_tcam_set_parms *parms); +/** + * Sends tcam entry 'get' to the Firmware. + * + * [in] tfp + * Pointer to session handle + * + * [in] parms + * Pointer to get parameters + * + * Returns: + * 0 on Success else internal Truflow error + */ +int tf_msg_tcam_entry_get(struct tf *tfp, + struct tf_dev_info *dev, + struct tf_tcam_get_parms *parms); + /** * Sends tcam entry 'free' to the Firmware. * diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 038aa40e92..a18d0e1e19 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -686,7 +686,94 @@ tf_tcam_set(struct tf *tfp __rte_unused, int tf_tcam_get(struct tf *tfp __rte_unused, - struct tf_tcam_get_parms *parms __rte_unused) + struct tf_tcam_get_parms *parms) { + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + struct tf_rm_is_allocated_parms aparms; + struct tf_rm_get_hcapi_parms hparms; + uint16_t num_slice_per_row = 1; + int allocated = 0; + + TF_CHECK_PARMS2(tfp, parms); + + if (!init) { + TFP_DRV_LOG(ERR, + "%s: No TCAM DBs created\n", + tf_dir_2_str(parms->dir)); + return -EINVAL; + } + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + if (dev->ops->tf_dev_get_tcam_slice_info == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Need to retrieve row size etc */ + rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, + parms->type, + parms->key_size, + &num_slice_per_row); + if (rc) + return rc; + + /* Check if element is in use */ + memset(&aparms, 0, sizeof(aparms)); + + aparms.rm_db = tcam_db[parms->dir]; + aparms.db_index = parms->type; + aparms.index = parms->idx / num_slice_per_row; + aparms.allocated = &allocated; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; + + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s: Entry is not allocated, type:%d, index:%d\n", + tf_dir_2_str(parms->dir), + parms->type, + parms->idx); + return -EINVAL; + } + + /* Convert TF type to HCAPI RM type */ + memset(&hparms, 0, sizeof(hparms)); + + hparms.rm_db = tcam_db[parms->dir]; + hparms.db_index = parms->type; + hparms.hcapi_type = &parms->hcapi_type; + + rc = tf_rm_get_hcapi_type(&hparms); + if (rc) + return rc; + + rc = tf_msg_tcam_entry_get(tfp, dev, parms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: %s: Entry %d set failed, rc:%s", + tf_dir_2_str(parms->dir), + tf_tcam_tbl_2_str(parms->type), + parms->idx, + strerror(-rc)); + return rc; + } + return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h index 40d010b09a..b550fa43ca 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.h +++ b/drivers/net/bnxt/tf_core/tf_tcam.h @@ -207,6 +207,10 @@ struct tf_tcam_get_parms { * [in] Type of object to get */ enum tf_tcam_tbl_type type; + /** + * [in] Type of HCAPI + */ + uint16_t hcapi_type; /** * [in] Entry index to read */ From patchwork Sun May 30 08:58:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93557 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 34B61A0524; Sun, 30 May 2021 11:01:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5E80A41134; Sun, 30 May 2021 11:00:41 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 0482B41121 for ; Sun, 30 May 2021 11:00:39 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 2348C7DC0; Sun, 30 May 2021 02:00:37 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 2348C7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365239; bh=y6OqARXqoPN+fYgTBkmDx6VNQSB9drG99EzX350/uow=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=babuijz6joW92rporaXFYT78iHReLnAim7FhbnFtvAr5nkjAOl0yWl2it4aN+mzHD /FGulWEnXVjnan5caeAbhZbeBmoS1RNdIkIy2osdqtknx2DdJFt0KFO76wT/u9H3bp 9+pLlwzUC1B1KabClmgvG6VwMtY4cbK+W1qe7rrs= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:39 +0530 Message-Id: <20210530085929.29695-9-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 08/58] net/bnxt: add action SRAM Translation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith - Translate Truflow action types for Thor to HCAPI RM resource defined SRAM banks. - move module type enum definitions to tf_core API - Switch to subtype concept for RM. - alloc/free working for Thor SRAM table type for full AR. Signed-off-by: Farah Smith Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Peter Spreadborough Reviewed-by: Randy Schacher --- drivers/net/bnxt/bnxt_util.h | 3 + drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h | 339 +++------ drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h | 387 +--------- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h | 411 ++++++++++ drivers/net/bnxt/tf_core/meson.build | 1 - drivers/net/bnxt/tf_core/tf_core.h | 24 + drivers/net/bnxt/tf_core/tf_device.c | 43 +- drivers/net/bnxt/tf_core/tf_device.h | 23 - drivers/net/bnxt/tf_core/tf_device_p4.c | 21 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 53 +- drivers/net/bnxt/tf_core/tf_device_p58.h | 110 ++- drivers/net/bnxt/tf_core/tf_em_common.c | 4 +- drivers/net/bnxt/tf_core/tf_em_host.c | 6 +- drivers/net/bnxt/tf_core/tf_em_internal.c | 4 +- drivers/net/bnxt/tf_core/tf_identifier.c | 10 +- drivers/net/bnxt/tf_core/tf_if_tbl.c | 2 +- drivers/net/bnxt/tf_core/tf_rm.c | 508 ++++++++----- drivers/net/bnxt/tf_core/tf_rm.h | 109 ++- drivers/net/bnxt/tf_core/tf_shadow_tbl.c | 783 -------------------- drivers/net/bnxt/tf_core/tf_shadow_tbl.h | 256 ------- drivers/net/bnxt/tf_core/tf_tbl.c | 238 +----- drivers/net/bnxt/tf_core/tf_tcam.c | 20 +- drivers/net/bnxt/tf_core/tf_util.c | 36 +- drivers/net/bnxt/tf_core/tf_util.h | 26 +- 24 files changed, 1130 insertions(+), 2287 deletions(-) create mode 100644 drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tbl.c delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tbl.h diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h index 64e97eed15..b243c21ec2 100644 --- a/drivers/net/bnxt/bnxt_util.h +++ b/drivers/net/bnxt/bnxt_util.h @@ -9,6 +9,9 @@ #ifndef BIT #define BIT(n) (1UL << (n)) #endif /* BIT */ +#ifndef BIT_MASK +#define BIT_MASK(len) (BIT(len) - 1) +#endif /* BIT_MASK */ #define PCI_SUBSYSTEM_ID_OFFSET 0x2e diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h index b8c85a0fca..c67aa29ad0 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h @@ -1,281 +1,126 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. +/* + * Copyright(c) Broadcom Limited. + * All rights reserved. */ +/*! + * \file + * \brief Exported functions for CFA HW programming + */ #ifndef _HCAPI_CFA_H_ #define _HCAPI_CFA_H_ #include +#include #include #include #include #include +#include #include "hcapi_cfa_defs.h" -/** - * Index used for the sram_entries field - */ -enum hcapi_cfa_resc_type_sram { - HCAPI_CFA_RESC_TYPE_SRAM_FULL_ACTION, - HCAPI_CFA_RESC_TYPE_SRAM_MCG, - HCAPI_CFA_RESC_TYPE_SRAM_ENCAP_8B, - HCAPI_CFA_RESC_TYPE_SRAM_ENCAP_16B, - HCAPI_CFA_RESC_TYPE_SRAM_ENCAP_64B, - HCAPI_CFA_RESC_TYPE_SRAM_SP_SMAC, - HCAPI_CFA_RESC_TYPE_SRAM_SP_SMAC_IPV4, - HCAPI_CFA_RESC_TYPE_SRAM_SP_SMAC_IPV6, - HCAPI_CFA_RESC_TYPE_SRAM_COUNTER_64B, - HCAPI_CFA_RESC_TYPE_SRAM_NAT_SPORT, - HCAPI_CFA_RESC_TYPE_SRAM_NAT_DPORT, - HCAPI_CFA_RESC_TYPE_SRAM_NAT_S_IPV4, - HCAPI_CFA_RESC_TYPE_SRAM_NAT_D_IPV4, - HCAPI_CFA_RESC_TYPE_SRAM_MAX -}; - -/** - * Index used for the hw_entries field in struct cfa_rm_db - */ -enum hcapi_cfa_resc_type_hw { - /* common HW resources for all chip variants */ - HCAPI_CFA_RESC_TYPE_HW_L2_CTXT_TCAM, - HCAPI_CFA_RESC_TYPE_HW_PROF_FUNC, - HCAPI_CFA_RESC_TYPE_HW_PROF_TCAM, - HCAPI_CFA_RESC_TYPE_HW_EM_PROF_ID, - HCAPI_CFA_RESC_TYPE_HW_EM_REC, - HCAPI_CFA_RESC_TYPE_HW_WC_TCAM_PROF_ID, - HCAPI_CFA_RESC_TYPE_HW_WC_TCAM, - HCAPI_CFA_RESC_TYPE_HW_METER_PROF, - HCAPI_CFA_RESC_TYPE_HW_METER_INST, - HCAPI_CFA_RESC_TYPE_HW_MIRROR, - HCAPI_CFA_RESC_TYPE_HW_UPAR, - /* Wh+/SR specific HW resources */ - HCAPI_CFA_RESC_TYPE_HW_SP_TCAM, - /* Thor, SR2 common HW resources */ - HCAPI_CFA_RESC_TYPE_HW_FKB, - /* SR specific HW resources */ - HCAPI_CFA_RESC_TYPE_HW_TBL_SCOPE, - HCAPI_CFA_RESC_TYPE_HW_L2_FUNC, - HCAPI_CFA_RESC_TYPE_HW_EPOCH0, - HCAPI_CFA_RESC_TYPE_HW_EPOCH1, - HCAPI_CFA_RESC_TYPE_HW_METADATA, - HCAPI_CFA_RESC_TYPE_HW_CT_STATE, - HCAPI_CFA_RESC_TYPE_HW_RANGE_PROF, - HCAPI_CFA_RESC_TYPE_HW_RANGE_ENTRY, - HCAPI_CFA_RESC_TYPE_HW_LAG_ENTRY, - HCAPI_CFA_RESC_TYPE_HW_MAX -}; - -struct hcapi_cfa_key_result { - uint64_t bucket_mem_ptr; - uint8_t bucket_idx; -}; - -/* common CFA register access macros */ -#define CFA_REG(x) OFFSETOF(cfa_reg_t, cfa_##x) - -#ifndef TF_REG_WR -#define TF_REG_WR(_p, x, y) (*((uint32_t volatile *)(x)) = (y)) -#endif -#ifndef TF_REG_RD -#define TF_REG_RD(_p, x) (*((uint32_t volatile *)(x))) -#endif -#ifndef TF_CFA_REG_RD -#define TF_CFA_REG_RD(_p, x) \ - TF_REG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x)) -#endif -#ifndef TF_CFA_REG_WR -#define TF_CFA_REG_WR(_p, x, y) \ - TF_REG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y) -#endif +#define INVALID_U64 (0xFFFFFFFFFFFFFFFFULL) +#define INVALID_U32 (0xFFFFFFFFUL) +#define INVALID_U16 (0xFFFFUL) +#define INVALID_U8 (0xFFUL) -/* Constants used by Resource Manager Registration*/ -#define RM_CLIENT_NAME_MAX_LEN 32 +struct hcapi_cfa_devops; /** - * Resource Manager Data Structures used for resource requests + * CFA device information */ -struct hcapi_cfa_resc_req_entry { - uint16_t min; - uint16_t max; -}; - -struct hcapi_cfa_resc_req { - /* Wh+/SR specific onchip Action SRAM resources */ - /* Validity of each sram type is indicated by the - * corresponding sram type bit in the sram_resc_flags. When - * set to 1, the CFA sram resource type is valid and amount of - * resources for this type is reserved. Each sram resource - * pool is identified by the starting index and number of - * resources in the pool. - */ - uint32_t sram_resc_flags; - struct hcapi_cfa_resc_req_entry sram_resc[HCAPI_CFA_RESC_TYPE_SRAM_MAX]; - - /* Validity of each resource type is indicated by the - * corresponding resource type bit in the hw_resc_flags. When - * set to 1, the CFA resource type is valid and amount of - * resource of this type is reserved. Each resource pool is - * identified by the starting index and the number of - * resources in the pool. - */ - uint32_t hw_resc_flags; - struct hcapi_cfa_resc_req_entry hw_resc[HCAPI_CFA_RESC_TYPE_HW_MAX]; -}; - -struct hcapi_cfa_resc_req_db { - struct hcapi_cfa_resc_req rx; - struct hcapi_cfa_resc_req tx; -}; - -struct hcapi_cfa_resc_entry { - uint16_t start; - uint16_t stride; - uint16_t tag; -}; - -struct hcapi_cfa_resc { - /* Wh+/SR specific onchip Action SRAM resources */ - /* Validity of each sram type is indicated by the - * corresponding sram type bit in the sram_resc_flags. When - * set to 1, the CFA sram resource type is valid and amount of - * resources for this type is reserved. Each sram resource - * pool is identified by the starting index and number of - * resources in the pool. - */ - uint32_t sram_resc_flags; - struct hcapi_cfa_resc_entry sram_resc[HCAPI_CFA_RESC_TYPE_SRAM_MAX]; - - /* Validity of each resource type is indicated by the - * corresponding resource type bit in the hw_resc_flags. When - * set to 1, the CFA resource type is valid and amount of - * resource of this type is reserved. Each resource pool is - * identified by the starting index and the number of resources - * in the pool. - */ - uint32_t hw_resc_flags; - struct hcapi_cfa_resc_entry hw_resc[HCAPI_CFA_RESC_TYPE_HW_MAX]; -}; - -struct hcapi_cfa_resc_db { - struct hcapi_cfa_resc rx; - struct hcapi_cfa_resc tx; +struct hcapi_cfa_devinfo { + /** [out] CFA device ops function pointer table */ + const struct hcapi_cfa_devops *devops; }; /** - * This is the main data structure used by the CFA Resource - * Manager. This data structure holds all the state and table - * management information. + * \defgroup CFA_HCAPI_DEVICE_API + * HCAPI used for writing to the hardware + * @{ */ -typedef struct hcapi_cfa_rm_data { - uint32_t dummy_data; -} hcapi_cfa_rm_data_t; - -/* End RM support */ - -struct hcapi_cfa_devops; - -struct hcapi_cfa_devinfo { - uint8_t global_cfg_data[CFA_GLOBAL_CFG_DATA_SZ]; - struct hcapi_cfa_layout_tbl layouts; - struct hcapi_cfa_devops *devops; -}; - -int hcapi_cfa_dev_bind(enum hcapi_cfa_ver hw_ver, - struct hcapi_cfa_devinfo *dev_info); - -int hcapi_cfa_key_compile_layout(struct hcapi_cfa_key_template *key_template, - struct hcapi_cfa_key_layout *key_layout); -uint64_t hcapi_cfa_key_hash(uint64_t *key_data, uint16_t bitlen); -int -hcapi_cfa_action_compile_layout(struct hcapi_cfa_action_template *act_template, - struct hcapi_cfa_action_layout *act_layout); -int hcapi_cfa_action_init_obj(uint64_t *act_obj, - struct hcapi_cfa_action_layout *act_layout); -int hcapi_cfa_action_compute_ptr(uint64_t *act_obj, - struct hcapi_cfa_action_layout *act_layout, - uint32_t base_ptr); - -int hcapi_cfa_action_hw_op(struct hcapi_cfa_hwop *op, - uint8_t *act_tbl, - struct hcapi_cfa_data *act_obj); -int hcapi_cfa_dev_hw_op(struct hcapi_cfa_hwop *op, uint16_t tbl_id, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_rm_register_client(hcapi_cfa_rm_data_t *data, - const char *client_name, - int *client_id); -int hcapi_cfa_rm_unregister_client(hcapi_cfa_rm_data_t *data, - int client_id); -int hcapi_cfa_rm_query_resources(hcapi_cfa_rm_data_t *data, - int client_id, - uint16_t chnl_id, - struct hcapi_cfa_resc_req_db *req_db); -int hcapi_cfa_rm_query_resources_one(hcapi_cfa_rm_data_t *data, - int clien_id, - struct hcapi_cfa_resc_db *resc_db); -int hcapi_cfa_rm_reserve_resources(hcapi_cfa_rm_data_t *data, - int client_id, - struct hcapi_cfa_resc_req_db *resc_req, - struct hcapi_cfa_resc_db *resc_db); -int hcapi_cfa_rm_release_resources(hcapi_cfa_rm_data_t *data, - int client_id, - struct hcapi_cfa_resc_req_db *resc_req, - struct hcapi_cfa_resc_db *resc_db); -int hcapi_cfa_rm_initialize(hcapi_cfa_rm_data_t *data); -#if SUPPORT_CFA_HW_P4 - -int hcapi_cfa_p4_dev_hw_op(struct hcapi_cfa_hwop *op, uint16_t tbl_id, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_prof_l2ctxt_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_prof_l2ctxtrmp_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_prof_tcam_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_prof_tcamrmp_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_wc_tcam_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_wc_tcam_rec_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_mirror_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *mirror); -int hcapi_cfa_p4_global_cfg_hwop(struct hcapi_cfa_hwop *op, - uint32_t type, - struct hcapi_cfa_data *config); -/* SUPPORT_CFA_HW_P4 */ -#elif SUPPORT_CFA_HW_P45 -int hcapi_cfa_p45_mirror_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *mirror); -int hcapi_cfa_p45_global_cfg_hwop(struct hcapi_cfa_hwop *op, - uint32_t type, - struct hcapi_cfa_data *config); -/* SUPPORT_CFA_HW_P45 */ -#endif -/** - * HCAPI CFA device HW operation function callback definition - * This is standardized function callback hook to install different - * CFA HW table programming function callback. +/** CFA device specific function hooks structure + * + * The following device hooks can be defined; unless noted otherwise, they are + * optional and can be filled with a null pointer. The pupose of these hooks + * to support CFA device operations for different device variants. */ +struct hcapi_cfa_devops { + /** calculate a key hash for the provided key_data + * + * This API computes hash for a key. + * + * @param[in] key_data + * A pointer of the key data buffer + * + * @param[in] bitlen + * Number of bits of the key data + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + uint64_t (*hcapi_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); -struct hcapi_cfa_tbl_cb { - /** - * This function callback provides the functionality to read/write - * HW table entry from a HW table. + /** hardware operation on the CFA EM key + * + * This API provides the functionality to program the exact match and + * key data to exact match record memory. * * @param[in] op * A pointer to the Hardware operation parameter * - * @param[in] obj_data - * A pointer to the HW data object for the hardware operation + * @param[in] key_tbl + * A pointer to the off-chip EM key table (applicable to EEM and + * SR2 EM only), set to NULL for on-chip EM key table or WC + * TCAM table. * + * @param[in/out] key_obj + * A pointer to the key data object for the hardware operation which + * has the following contents: + * 1. key record memory offset (index to WC TCAM or EM key hash + * value) + * 2. key data + * When using the HWOP PUT, the key_obj holds the LREC and key to + * be written. + * When using the HWOP GET, the key_obj be populated with the LREC + * and key which was specified by the key location object. + * + * @param[in/out] key_loc + * When using the HWOP PUT, this is a pointer to the key location + * data structure which holds the information of where the EM key + * is stored. It holds the bucket index and the data pointer of + * a dynamic bucket that is chained to static bucket + * When using the HWOP GET, this is a pointer to the key location + * which should be retreved. + * + * (valid for SR2 only). * @return * 0 for SUCCESS, negative value for FAILURE */ - int (*hwop_cb)(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); + int (*hcapi_cfa_key_hw_op)(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_key_tbl *key_tbl, + struct hcapi_cfa_key_data *key_data, + struct hcapi_cfa_key_loc *key_loc); }; -#endif /* HCAPI_CFA_H_ */ +/*@}*/ + +extern const size_t CFA_RM_HANDLE_DATA_SIZE; + +#if SUPPORT_CFA_HW_ALL +extern const struct hcapi_cfa_devops cfa_p4_devops; +extern const struct hcapi_cfa_devops cfa_p58_devops; + +#elif defined(SUPPORT_CFA_HW_P4) && SUPPORT_CFA_HW_P4 +extern const struct hcapi_cfa_devops cfa_p4_devops; +uint64_t hcapi_cfa_p4_key_hash(uint64_t *key_data, uint16_t bitlen); +/* SUPPORT_CFA_HW_P4 */ +#elif defined(SUPPORT_CFA_HW_P58) && SUPPORT_CFA_HW_P58 +extern const struct hcapi_cfa_devops cfa_p58_devops; +uint64_t hcapi_cfa_p58_key_hash(uint64_t *key_data, uint16_t bitlen); +/* SUPPORT_CFA_HW_P58 */ +#endif + +#endif /* HCAPI_CFA_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h index 08f098ec86..8e5095a6ef 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h @@ -30,12 +30,10 @@ #define CFA_GLOBAL_CFG_DATA_SZ (100) +#if SUPPORT_CFA_HW_ALL #include "hcapi_cfa_p4.h" -#define CFA_PROF_L2CTXT_TCAM_MAX_FIELD_CNT CFA_P40_PROF_L2_CTXT_TCAM_MAX_FLD -#define CFA_PROF_L2CTXT_REMAP_MAX_FIELD_CNT CFA_P40_PROF_L2_CTXT_RMP_DR_MAX_FLD -#define CFA_PROF_MAX_KEY_CFG_SZ sizeof(struct cfa_p4_prof_key_cfg) -#define CFA_KEY_MAX_FIELD_CNT 41 -#define CFA_ACT_MAX_TEMPLATE_SZ sizeof(struct cfa_p4_action_template) +#include "hcapi_cfa_p58.h" +#endif /* SUPPORT_CFA_HW_ALL */ /** * CFA HW version definition @@ -87,43 +85,6 @@ enum hcapi_cfa_key_ctrlops { HCAPI_CFA_KEY_CTRLOPS_MAX }; -/** - * CFA HW field structure definition - */ -struct hcapi_cfa_field { - /** [in] Starting bit position pf the HW field within a HW table - * entry. - */ - uint16_t bitpos; - /** [in] Number of bits for the HW field. */ - uint8_t bitlen; -}; - -/** - * CFA HW table entry layout structure definition - */ -struct hcapi_cfa_layout { - /** [out] Bit order of layout */ - bool is_msb_order; - /** [out] Size in bits of entry */ - uint32_t total_sz_in_bits; - /** [out] data pointer of the HW layout fields array */ - const struct hcapi_cfa_field *field_array; - /** [out] number of HW field entries in the HW layout field array */ - uint32_t array_sz; - /** [out] layout_id - layout id associated with the layout */ - uint16_t layout_id; -}; - -/** - * CFA HW data object definition - */ -struct hcapi_cfa_data_obj { - /** [in] HW field identifier. Used as an index to a HW table layout */ - uint16_t field_id; - /** [in] Value of the HW field */ - uint64_t val; -}; /** * CFA HW definition @@ -280,348 +241,6 @@ struct hcapi_cfa_key_loc { uint8_t bucket_idx; }; -/** - * CFA HW layout table definition - */ -struct hcapi_cfa_layout_tbl { - /** [out] data pointer to an array of fix formatted layouts supported. - * The index to the array is the CFA HW table ID - */ - const struct hcapi_cfa_layout *tbl; - /** [out] number of fix formatted layouts in the layout array */ - uint16_t num_layouts; -}; - -/** - * Key template consists of key fields that can be enabled/disabled - * individually. - */ -struct hcapi_cfa_key_template { - /** [in] key field enable field array, set 1 to the correspeonding - * field enable to make a field valid - */ - uint8_t field_en[CFA_KEY_MAX_FIELD_CNT]; - /** [in] Identified if the key template is for TCAM. If false, the - * the key template is for EM. This field is mandantory for device that - * only support fix key formats. - */ - bool is_wc_tcam_key; -}; - -/** - * key layout consist of field array, key bitlen, key ID, and other meta data - * pertain to a key - */ -struct hcapi_cfa_key_layout { - /** [out] key layout data */ - struct hcapi_cfa_layout *layout; - /** [out] actual key size in number of bits */ - uint16_t bitlen; - /** [out] key identifier and this field is only valid for device - * that supports fix key formats - */ - uint16_t id; - /** [out] Identified the key layout is WC TCAM key */ - bool is_wc_tcam_key; - /** [out] total slices size, valid for WC TCAM key only. It can be - * used by the user to determine the total size of WC TCAM key slices - * in bytes. - */ - uint16_t slices_size; -}; - -/** - * key layout memory contents - */ -struct hcapi_cfa_key_layout_contents { - /** key layouts */ - struct hcapi_cfa_key_layout key_layout; - - /** layout */ - struct hcapi_cfa_layout layout; - - /** fields */ - struct hcapi_cfa_field field_array[CFA_KEY_MAX_FIELD_CNT]; -}; - -/** - * Action template consists of action fields that can be enabled/disabled - * individually. - */ -struct hcapi_cfa_action_template { - /** [in] CFA version for the action template */ - enum hcapi_cfa_ver hw_ver; - /** [in] action field enable field array, set 1 to the correspeonding - * field enable to make a field valid - */ - uint8_t data[CFA_ACT_MAX_TEMPLATE_SZ]; -}; - -/** - * action layout consist of field array, action wordlen and action format ID - */ -struct hcapi_cfa_action_layout { - /** [in] action identifier */ - uint16_t id; - /** [out] action layout data */ - struct hcapi_cfa_layout *layout; - /** [out] actual action record size in number of bits */ - uint16_t wordlen; -}; - -/** - * \defgroup CFA_HCAPI_PUT_API - * HCAPI used for writing to the hardware - * @{ - */ - -/** - * This API provides the functionality to program a specified value to a - * HW field based on the provided programming layout. - * - * @param[in,out] obj_data - * A data pointer to a CFA HW key/mask data - * - * @param[in] layout - * A pointer to CFA HW programming layout - * - * @param[in] field_id - * ID of the HW field to be programmed - * - * @param[in] val - * Value of the HW field to be programmed - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int hcapi_cfa_put_field(uint64_t *data_buf, - const struct hcapi_cfa_layout *layout, - uint16_t field_id, uint64_t val); - -/** - * This API provides the functionality to program an array of field values - * with corresponding field IDs to a number of profiler sub-block fields - * based on the fixed profiler sub-block hardware programming layout. - * - * @param[in, out] obj_data - * A pointer to a CFA profiler key/mask object data - * - * @param[in] layout - * A pointer to CFA HW programming layout - * - * @param[in] field_tbl - * A pointer to an array that consists of the object field - * ID/value pairs - * - * @param[in] field_tbl_sz - * Number of entries in the table - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int hcapi_cfa_put_fields(uint64_t *obj_data, - const struct hcapi_cfa_layout *layout, - struct hcapi_cfa_data_obj *field_tbl, - uint16_t field_tbl_sz); - -/** - * This API provides the functionality to write a value to a - * field within the bit position and bit length of a HW data - * object based on a provided programming layout. - * - * @param[in, out] act_obj - * A pointer of the action object to be initialized - * - * @param[in] layout - * A pointer of the programming layout - * - * @param field_id - * [in] Identifier of the HW field - * - * @param[in] bitpos_adj - * Bit position adjustment value - * - * @param[in] bitlen_adj - * Bit length adjustment value - * - * @param[in] val - * HW field value to be programmed - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int hcapi_cfa_put_field_rel(uint64_t *obj_data, - const struct hcapi_cfa_layout *layout, - uint16_t field_id, int16_t bitpos_adj, - int16_t bitlen_adj, uint64_t val); - -/*@}*/ - -/** - * \defgroup CFA_HCAPI_GET_API - * HCAPI used for writing to the hardware - * @{ - */ - -/** - * This API provides the functionality to get the word length of - * a layout object. - * - * @param[in] layout - * A pointer of the HW layout - * - * @return - * Word length of the layout object - */ -uint16_t hcapi_cfa_get_wordlen(const struct hcapi_cfa_layout *layout); - -/** - * The API provides the functionality to get bit offset and bit - * length information of a field from a programming layout. - * - * @param[in] layout - * A pointer of the action layout - * - * @param[out] slice - * A pointer to the action offset info data structure - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int hcapi_cfa_get_slice(const struct hcapi_cfa_layout *layout, - uint16_t field_id, struct hcapi_cfa_field *slice); - -/** - * This API provides the functionality to read the value of a - * CFA HW field from CFA HW data object based on the hardware - * programming layout. - * - * @param[in] obj_data - * A pointer to a CFA HW key/mask object data - * - * @param[in] layout - * A pointer to CFA HW programming layout - * - * @param[in] field_id - * ID of the HW field to be programmed - * - * @param[out] val - * Value of the HW field - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int hcapi_cfa_get_field(uint64_t *obj_data, - const struct hcapi_cfa_layout *layout, - uint16_t field_id, uint64_t *val); - -/** - * This API provides the functionality to read a number of - * HW fields from a CFA HW data object based on the hardware - * programming layout. - * - * @param[in] obj_data - * A pointer to a CFA profiler key/mask object data - * - * @param[in] layout - * A pointer to CFA HW programming layout - * - * @param[in, out] field_tbl - * A pointer to an array that consists of the object field - * ID/value pairs - * - * @param[in] field_tbl_sz - * Number of entries in the table - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int hcapi_cfa_get_fields(uint64_t *obj_data, - const struct hcapi_cfa_layout *layout, - struct hcapi_cfa_data_obj *field_tbl, - uint16_t field_tbl_sz); - -/** - * Get a value to a specific location relative to a HW field - * - * This API provides the functionality to read HW field from - * a section of a HW data object identified by the bit position - * and bit length from a given programming layout in order to avoid - * reading the entire HW data object. - * - * @param[in] obj_data - * A pointer of the data object to read from - * - * @param[in] layout - * A pointer of the programming layout - * - * @param[in] field_id - * Identifier of the HW field - * - * @param[in] bitpos_adj - * Bit position adjustment value - * - * @param[in] bitlen_adj - * Bit length adjustment value - * - * @param[out] val - * Value of the HW field - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int hcapi_cfa_get_field_rel(uint64_t *obj_data, - const struct hcapi_cfa_layout *layout, - uint16_t field_id, int16_t bitpos_adj, - int16_t bitlen_adj, uint64_t *val); - -/** - * This function is used to initialize a layout_contents structure - * - * The struct hcapi_cfa_key_layout is complex as there are three - * layers of abstraction. Each of those layer need to be properly - * initialized. - * - * @param[in] layout_contents - * A pointer of the layout contents to initialize - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int -hcapi_cfa_init_key_layout_contents(struct hcapi_cfa_key_layout_contents *cont); - -/** - * This function is used to validate a key template - * - * The struct hcapi_cfa_key_template is complex as there are three - * layers of abstraction. Each of those layer need to be properly - * validated. - * - * @param[in] key_template - * A pointer of the key template contents to validate - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int -hcapi_cfa_is_valid_key_template(struct hcapi_cfa_key_template *key_template); - -/** - * This function is used to validate a key layout - * - * The struct hcapi_cfa_key_layout is complex as there are three - * layers of abstraction. Each of those layer need to be properly - * validated. - * - * @param[in] key_layout - * A pointer of the key layout contents to validate - * - * @return - * 0 for SUCCESS, negative value for FAILURE - */ -int hcapi_cfa_is_valid_key_layout(struct hcapi_cfa_key_layout *key_layout); - /** * This function is used to hash E/EM keys * diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h new file mode 100644 index 0000000000..b2535098d2 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h @@ -0,0 +1,411 @@ +/* + * Copyright(c) Broadcom Limited. + * All rights reserved. + */ + +#ifndef _HCAPI_CFA_P58_H_ +#define _HCAPI_CFA_P58_H_ + +/** CFA phase 5.8 fix formatted table(layout) ID definition + * + */ +enum cfa_p58_tbl_id { + CFA_P58_TBL_ILT = 0, + CFA_P58_TBL_L2CTXT_TCAM, + CFA_P58_TBL_L2CTXT_REMAP, + CFA_P58_TBL_PROF_TCAM, + CFA_P58_TBL_PROF_TCAM_REMAP, + CFA_P58_TBL_WC_TCAM, + CFA_P58_TBL_WC_TCAM_REC, + CFA_P58_TBL_VEB_TCAM, + CFA_P58_TBL_SP_TCAM, + /** Default Profile TCAM/Lookup Action Record Pointer Table */ + CFA_P58_TBL_PROF_PARIF_DFLT_ACT_REC_PTR, + /** Error Profile TCAM Miss Action Record Pointer Table */ + CFA_P58_TBL_PROF_PARIF_ERR_ACT_REC_PTR, + /** SR2 VNIC/SVIF Properties Table */ + CFA_P58_TBL_VSPT, + CFA_P58_TBL_MAX +}; + +#define CFA_P58_PROF_MAX_KEYS 4 +enum cfa_p58_mac_sel_mode { + CFA_P58_MAC_SEL_MODE_FIRST = 0, + CFA_P58_MAC_SEL_MODE_LOWEST = 1, +}; + +struct cfa_p58_prof_key_cfg { + uint8_t mac_sel[CFA_P58_PROF_MAX_KEYS]; +#define CFA_P58_PROF_MAC_SEL_DMAC0 (1 << 0) +#define CFA_P58_PROF_MAC_SEL_T_MAC0 (1 << 1) +#define CFA_P58_PROF_MAC_SEL_OUTERMOST_MAC0 (1 << 2) +#define CFA_P58_PROF_MAC_SEL_DMAC1 (1 << 3) +#define CFA_P58_PROF_MAC_SEL_T_MAC1 (1 << 4) +#define CFA_P58_PROF_MAC_OUTERMOST_MAC1 (1 << 5) + uint8_t vlan_sel[CFA_P58_PROF_MAX_KEYS]; +#define CFA_P58_PROFILER_VLAN_SEL_INNER_HDR 0 +#define CFA_P58_PROFILER_VLAN_SEL_TUNNEL_HDR 1 +#define CFA_P58_PROFILER_VLAN_SEL_OUTERMOST_HDR 2 + uint8_t pass_cnt; + enum cfa_p58_mac_sel_mode mode; +}; + +/** + * CFA action layout definition + */ + +#define CFA_P58_ACTION_MAX_LAYOUT_SIZE 184 + +/** + * Action object template structure + * + * Template structure presents data fields that are necessary to know + * at the beginning of Action Builder (AB) processing. Like before the + * AB compilation. One such example could be a template that is + * flexible in size (Encap Record) and the presence of these fields + * allows for determining the template size as well as where the + * fields are located in the record. + * + * The template may also present fields that are not made visible to + * the caller by way of the action fields. + * + * Template fields also allow for additional checking on user visible + * fields. One such example could be the encap pointer behavior on a + * CFA_P58_ACT_OBJ_TYPE_ACT or CFA_P58_ACT_OBJ_TYPE_ACT_SRAM. + */ +struct cfa_p58_action_template { + /** Action Object type + * + * Controls the type of the Action Template + */ + enum { + /** Select this type to build an Action Record Object + */ + CFA_P58_ACT_OBJ_TYPE_ACT, + /** Select this type to build an Action Statistics + * Object + */ + CFA_P58_ACT_OBJ_TYPE_STAT, + /** Select this type to build a SRAM Action Record + * Object. + */ + CFA_P58_ACT_OBJ_TYPE_ACT_SRAM, + /** Select this type to build a SRAM Action + * Encapsulation Object. + */ + CFA_P58_ACT_OBJ_TYPE_ENCAP_SRAM, + /** Select this type to build a SRAM Action Modify + * Object, with IPv4 capability. + */ + /* In case of Stingray the term Modify is used for the 'NAT + * action'. Action builder is leveraged to fill in the NAT + * object which then can be referenced by the action + * record. + */ + CFA_P58_ACT_OBJ_TYPE_MODIFY_IPV4_SRAM, + /** Select this type to build a SRAM Action Source + * Property Object. + */ + /* In case of Stingray this is not a 'pure' action record. + * Action builder is leveraged to full in the Source Property + * object which can then be referenced by the action + * record. + */ + CFA_P58_ACT_OBJ_TYPE_SRC_PROP_SRAM, + /** Select this type to build a SRAM Action Statistics + * Object + */ + CFA_P58_ACT_OBJ_TYPE_STAT_SRAM, + } obj_type; + + /** Action Control + * + * Controls the internals of the Action Template + * + * act is valid when: + * (obj_type == CFA_P58_ACT_OBJ_TYPE_ACT) + */ + /* + * Stat and encap are always inline for EEM as table scope + * allocation does not allow for separate Stats allocation, + * but has the xx_inline flags as to be forward compatible + * with Stingray 2, always treated as TRUE. + */ + struct { + /** Set to CFA_HCAPI_TRUE to enable statistics + */ + uint8_t stat_enable; + /** Set to CFA_HCAPI_TRUE to enable statistics to be inlined + */ + uint8_t stat_inline; + + /** Set to CFA_HCAPI_TRUE to enable encapsulation + */ + uint8_t encap_enable; + /** Set to CFA_HCAPI_TRUE to enable encapsulation to be inlined + */ + uint8_t encap_inline; + } act; + + /** Modify Setting + * + * Controls the type of the Modify Action the template is + * describing + * + * modify is valid when: + * (obj_type == CFA_P58_ACT_OBJ_TYPE_MODIFY_SRAM) + */ + enum { + /** Set to enable Modify of Source IPv4 Address + */ + CFA_P58_MR_REPLACE_SOURCE_IPV4 = 0, + /** Set to enable Modify of Destination IPv4 Address + */ + CFA_P58_MR_REPLACE_DEST_IPV4 + } modify; + + /** Encap Control + * Controls the type of encapsulation the template is + * describing + * + * encap is valid when: + * ((obj_type == CFA_P58_ACT_OBJ_TYPE_ACT) && + * act.encap_enable) || + * ((obj_type == CFA_P58_ACT_OBJ_TYPE_SRC_PROP_SRAM) + */ + struct { + /* Direction is required as Stingray Encap on RX is + * limited to l2 and VTAG only. + */ + /** Receive or Transmit direction + */ + uint8_t direction; + /** Set to CFA_HCAPI_TRUE to enable L2 capability in the + * template + */ + uint8_t l2_enable; + /** vtag controls the Encap Vector - VTAG Encoding, 4 bits + * + *
    + *
  • CFA_P58_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN + * Tags applied + *
  • CFA_P58_ACT_ENCAP_VTAGS_PUSH_1, adds capability to + * set 1 VLAN Tag. Action Template compile adds + * the following field to the action object + * ::TF_ER_VLAN1 + *
  • CFA_P58_ACT_ENCAP_VTAGS_PUSH_2, adds capability to + * set 2 VLAN Tags. Action Template compile adds + * the following fields to the action object + * ::TF_ER_VLAN1 and ::TF_ER_VLAN2 + *
+ */ + enum { CFA_P58_ACT_ENCAP_VTAGS_PUSH_0 = 0, + CFA_P58_ACT_ENCAP_VTAGS_PUSH_1, + CFA_P58_ACT_ENCAP_VTAGS_PUSH_2 } vtag; + + /* + * The remaining fields are NOT supported when + * direction is RX and ((obj_type == + * CFA_P58_ACT_OBJ_TYPE_ACT) && act.encap_enable). + * ab_compile_layout will perform the checking and + * skip remaining fields. + */ + /** L3 Encap controls the Encap Vector - L3 Encoding, + * 3 bits. Defines the type of L3 Encapsulation the + * template is describing. + *
    + *
  • CFA_P58_ACT_ENCAP_L3_NONE, default, no L3 + * Encapsulation processing. + *
  • CFA_P58_ACT_ENCAP_L3_IPV4, enables L3 IPv4 + * Encapsulation. + *
  • CFA_P58_ACT_ENCAP_L3_IPV6, enables L3 IPv6 + * Encapsulation. + *
  • CFA_P58_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS + * 8847 Encapsulation. + *
  • CFA_P58_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS + * 8848 Encapsulation. + *
+ */ + enum { + /** Set to disable any L3 encapsulation + * processing, default + */ + CFA_P58_ACT_ENCAP_L3_NONE = 0, + /** Set to enable L3 IPv4 encapsulation + */ + CFA_P58_ACT_ENCAP_L3_IPV4 = 4, + /** Set to enable L3 IPv6 encapsulation + */ + CFA_P58_ACT_ENCAP_L3_IPV6 = 5, + /** Set to enable L3 MPLS 8847 encapsulation + */ + CFA_P58_ACT_ENCAP_L3_MPLS_8847 = 6, + /** Set to enable L3 MPLS 8848 encapsulation + */ + CFA_P58_ACT_ENCAP_L3_MPLS_8848 = 7 + } l3; + +#define CFA_P58_ACT_ENCAP_MAX_MPLS_LABELS 8 + /** 1-8 labels, valid when + * (l3 == CFA_P58_ACT_ENCAP_L3_MPLS_8847) || + * (l3 == CFA_P58_ACT_ENCAP_L3_MPLS_8848) + * + * MAX number of MPLS Labels 8. + */ + uint8_t l3_num_mpls_labels; + + /** Set to CFA_HCAPI_TRUE to enable L4 capability in the + * template. + * + * CFA_HCAPI_TRUE adds ::TF_EN_UDP_SRC_PORT and + * ::TF_EN_UDP_DST_PORT to the template. + */ + uint8_t l4_enable; + + /** Tunnel Encap controls the Encap Vector - Tunnel + * Encap, 3 bits. Defines the type of Tunnel + * encapsulation the template is describing + *
    + *
  • CFA_P58_ACT_ENCAP_TNL_NONE, default, no Tunnel + * Encapsulation processing. + *
  • CFA_P58_ACT_ENCAP_TNL_GENERIC_FULL + *
  • CFA_P58_ACT_ENCAP_TNL_VXLAN. NOTE: Expects + * l4_enable set to CFA_P58_TRUE; + *
  • CFA_P58_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable + * set to CFA_P58_TRUE; + *
  • CFA_P58_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if + * l4_enable set to CFA_HCAPI_FALSE. + *
  • CFA_P58_ACT_ENCAP_TNL_GRE.NOTE: only valid if + * l4_enable set to CFA_HCAPI_FALSE. + *
  • CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TL4 + *
  • CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TNL + *
+ */ + enum { + /** Set to disable Tunnel header encapsulation + * processing, default + */ + CFA_P58_ACT_ENCAP_TNL_NONE = 0, + /** Set to enable Tunnel Generic Full header + * encapsulation + */ + CFA_P58_ACT_ENCAP_TNL_GENERIC_FULL, + /** Set to enable VXLAN header encapsulation + */ + CFA_P58_ACT_ENCAP_TNL_VXLAN, + /** Set to enable NGE (VXLAN2) header encapsulation + */ + CFA_P58_ACT_ENCAP_TNL_NGE, + /** Set to enable NVGRE header encapsulation + */ + CFA_P58_ACT_ENCAP_TNL_NVGRE, + /** Set to enable GRE header encapsulation + */ + CFA_P58_ACT_ENCAP_TNL_GRE, + /** Set to enable Generic header after Tunnel + * L4 encapsulation + */ + CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TL4, + /** Set to enable Generic header after Tunnel + * encapsulation + */ + CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TNL + } tnl; + + /** Number of bytes of generic tunnel header, + * valid when + * (tnl == CFA_P58_ACT_ENCAP_TNL_GENERIC_FULL) || + * (tnl == CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) || + * (tnl == CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TNL) + */ + uint8_t tnl_generic_size; + /** Number of 32b words of nge options, + * valid when + * (tnl == CFA_P58_ACT_ENCAP_TNL_NGE) + */ + uint8_t tnl_nge_op_len; + /* Currently not planned */ + /* Custom Header */ + /* uint8_t custom_enable; */ + } encap; +}; + +/** + * Enumeration of SRAM entry types, used for allocation of + * fixed SRAM entities. The memory model for CFA HCAPI + * determines if an SRAM entry type is supported. + */ +enum cfa_p58_action_sram_entry_type { + /* NOTE: Any additions to this enum must be reflected on FW + * side as well. + */ + + /** SRAM Action Record */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_ACT, + /** SRAM Action Encap 8 Bytes */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_ENCAP_8B, + /** SRAM Action Encap 16 Bytes */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_ENCAP_16B, + /** SRAM Action Encap 64 Bytes */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_ENCAP_64B, + /** SRAM Action Modify IPv4 Source */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_MODIFY_IPV4_SRC, + /** SRAM Action Modify IPv4 Destination */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_MODIFY_IPV4_DEST, + /** SRAM Action Source Properties SMAC */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_SP_SMAC, + /** SRAM Action Source Properties SMAC IPv4 */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_SP_SMAC_IPV4, + /** SRAM Action Source Properties SMAC IPv6 */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_SP_SMAC_IPV6, + /** SRAM Action Statistics 64 Bits */ + CFA_P58_ACTION_SRAM_ENTRY_TYPE_STATS_64, + CFA_P58_ACTION_SRAM_ENTRY_TYPE_MAX +}; + +/** + * SRAM Action Record structure holding either an action index or an + * action ptr. + */ +union cfa_p58_action_sram_act_record { + /** SRAM Action idx specifies the offset of the SRAM + * element within its SRAM Entry Type block. This + * index can be written into i.e. an L2 Context. Use + * this type for all SRAM Action Record types except + * SRAM Full Action records. Use act_ptr instead. + */ + uint16_t act_idx; + /** SRAM Full Action is special in that it needs an + * action record pointer. This pointer can be written + * into i.e. a Wildcard TCAM entry. + */ + uint32_t act_ptr; +}; + +/** + * cfa_p58_action_param parameter definition + */ +struct cfa_p58_action_param { + /** + * [in] receive or transmit direction + */ + uint8_t dir; + /** + * [in] type of the sram allocation type + */ + enum cfa_p58_action_sram_entry_type type; + /** + * [in] action record to set. The 'type' specified lists the + * record definition to use in the passed in record. + */ + union cfa_p58_action_sram_act_record record; + /** + * [in] number of elements in act_data + */ + uint32_t act_size; + /** + * [in] ptr to array of action data + */ + uint64_t *act_data; +}; +#endif /* _CFA_HW_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index 373ee0413b..2c02214d83 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -22,7 +22,6 @@ sources += files( 'tf_device_p4.c', 'tf_device_p58.c', 'tf_identifier.c', - 'tf_shadow_tbl.c', 'tf_shadow_tcam.c', 'tf_tcam.c', 'tf_util.c', diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 4fe0590569..0cc3719a1b 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -153,6 +153,30 @@ enum tf_device_type { TF_DEVICE_TYPE_MAX /**< Maximum */ }; +/** + * Module types + */ +enum tf_module_type { + /** + * Identifier module + */ + TF_MODULE_TYPE_IDENTIFIER, + /** + * Table type module + */ + TF_MODULE_TYPE_TABLE, + /** + * TCAM module + */ + TF_MODULE_TYPE_TCAM, + /** + * EM module + */ + TF_MODULE_TYPE_EM, + TF_MODULE_TYPE_MAX +}; + + /** * Identifier resource types */ diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index d072b9877c..61b3746d8b 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -8,6 +8,7 @@ #include "tf_device_p58.h" #include "tfp.h" #include "tf_em.h" +#include "tf_rm.h" struct tf; @@ -18,8 +19,8 @@ static int tf_dev_unbind_p58(struct tf *tfp); /** * Resource Reservation Check function * - * [in] tfp - * Pointer to TF handle + * [in] count + * Number of module subtypes * * [in] cfg * Pointer to rm element config @@ -28,11 +29,10 @@ static int tf_dev_unbind_p58(struct tf *tfp); * Pointer to resource reservation array * * Returns - * - (n) number of tables that have non-zero reservation count. + * - (n) number of tables in module that have non-zero reservation count. */ static int -tf_dev_reservation_check(struct tf *tfp __rte_unused, - uint16_t count, +tf_dev_reservation_check(uint16_t count, struct tf_rm_element_cfg *cfg, uint16_t *reservations) { @@ -94,8 +94,7 @@ tf_dev_bind_p4(struct tf *tfp, /* Initialize the modules */ - rsv_cnt = tf_dev_reservation_check(tfp, - TF_IDENT_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_IDENT_TYPE_MAX, tf_ident_p4, (uint16_t *)resources->ident_cnt); if (rsv_cnt) { @@ -113,8 +112,7 @@ tf_dev_bind_p4(struct tf *tfp, no_rsv_flag = false; } - rsv_cnt = tf_dev_reservation_check(tfp, - TF_TBL_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, tf_tbl_p4, (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { @@ -132,8 +130,7 @@ tf_dev_bind_p4(struct tf *tfp, no_rsv_flag = false; } - rsv_cnt = tf_dev_reservation_check(tfp, - TF_TCAM_TBL_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_TCAM_TBL_TYPE_MAX, tf_tcam_p4, (uint16_t *)resources->tcam_cnt); if (rsv_cnt) { @@ -155,8 +152,7 @@ tf_dev_bind_p4(struct tf *tfp, */ em_cfg.cfg = tf_em_ext_p4; - rsv_cnt = tf_dev_reservation_check(tfp, - TF_EM_TBL_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_EM_TBL_TYPE_MAX, em_cfg.cfg, (uint16_t *)resources->em_cnt); if (rsv_cnt) { @@ -175,8 +171,7 @@ tf_dev_bind_p4(struct tf *tfp, /* * EM */ - rsv_cnt = tf_dev_reservation_check(tfp, - TF_EM_TBL_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_EM_TBL_TYPE_MAX, tf_em_int_p4, (uint16_t *)resources->em_cnt); if (rsv_cnt) { @@ -360,10 +355,7 @@ tf_dev_bind_p58(struct tf *tfp, /* Initial function initialization */ dev_handle->ops = &tf_dev_ops_p58_init; - /* Initialize the modules */ - - rsv_cnt = tf_dev_reservation_check(tfp, - TF_IDENT_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_IDENT_TYPE_MAX, tf_ident_p58, (uint16_t *)resources->ident_cnt); if (rsv_cnt) { @@ -380,8 +372,7 @@ tf_dev_bind_p58(struct tf *tfp, no_rsv_flag = false; } - rsv_cnt = tf_dev_reservation_check(tfp, - TF_TBL_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, tf_tbl_p58, (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { @@ -398,8 +389,7 @@ tf_dev_bind_p58(struct tf *tfp, no_rsv_flag = false; } - rsv_cnt = tf_dev_reservation_check(tfp, - TF_TCAM_TBL_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_TCAM_TBL_TYPE_MAX, tf_tcam_p58, (uint16_t *)resources->tcam_cnt); if (rsv_cnt) { @@ -419,8 +409,7 @@ tf_dev_bind_p58(struct tf *tfp, /* * EM */ - rsv_cnt = tf_dev_reservation_check(tfp, - TF_EM_TBL_TYPE_MAX, + rsv_cnt = tf_dev_reservation_check(TF_EM_TBL_TYPE_MAX, tf_em_int_p58, (uint16_t *)resources->em_cnt); if (rsv_cnt) { @@ -593,10 +582,10 @@ tf_dev_bind_ops(enum tf_device_type type, switch (type) { case TF_DEVICE_TYPE_WH: case TF_DEVICE_TYPE_SR: - dev_handle->ops = &tf_dev_ops_p4; + dev_handle->ops = &tf_dev_ops_p4_init; break; case TF_DEVICE_TYPE_THOR: - dev_handle->ops = &tf_dev_ops_p58; + dev_handle->ops = &tf_dev_ops_p58_init; break; default: TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 4f4120c603..2cbb42fe2a 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -16,29 +16,6 @@ struct tf; struct tf_session; -/** - * Device module types - */ -enum tf_device_module_type { - /** - * Identifier module - */ - TF_DEVICE_MODULE_TYPE_IDENTIFIER, - /** - * Table type module - */ - TF_DEVICE_MODULE_TYPE_TABLE, - /** - * TCAM module - */ - TF_DEVICE_MODULE_TYPE_TCAM, - /** - * EM module - */ - TF_DEVICE_MODULE_TYPE_EM, - TF_DEVICE_MODULE_TYPE_MAX -}; - /** * The Device module provides a general device template. A supported * device type should implement one or more of the listed function diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index fbe92b7733..d0bede89e3 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -74,29 +74,10 @@ static int tf_dev_p4_get_max_types(struct tf *tfp, uint16_t *max_types) { - struct tf_session *tfs; - struct tf_dev_info *dev; - int rc; - if (max_types == NULL || tfp == NULL) return -EINVAL; - /* Retrieve the session information */ - rc = tf_session_get_session(tfp, &tfs); - if (rc) - return rc; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - if (dev->type == TF_DEVICE_TYPE_WH) - *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1; - else if (dev->type == TF_DEVICE_TYPE_SR) - *max_types = CFA_RESOURCE_TYPE_P45_LAST + 1; - else - return -ENODEV; + *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1; return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 688d987cb7..50a8d82074 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -58,25 +58,11 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { */ static int tf_dev_p58_get_max_types(struct tf *tfp, - uint16_t *max_types) + uint16_t *max_types) { - struct tf_session *tfs; - struct tf_dev_info *dev; - int rc; - if (max_types == NULL || tfp == NULL) return -EINVAL; - /* Retrieve the session information */ - rc = tf_session_get_session(tfp, &tfs); - if (rc) - return rc; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - *max_types = CFA_RESOURCE_TYPE_P58_LAST + 1; return 0; @@ -153,41 +139,6 @@ tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused, return 0; } -static int -tf_dev_p58_map_parif(struct tf *tfp __rte_unused, - uint16_t parif_bitmask, - uint16_t pf, - uint8_t *data, - uint8_t *mask, - uint16_t sz_in_bytes) -{ - uint32_t parif_pf[2] = { 0 }; - uint32_t parif_pf_mask[2] = { 0 }; - uint32_t parif; - uint32_t shift; - - if (sz_in_bytes != sizeof(uint64_t)) - return -ENOTSUP; - - for (parif = 0; parif < TF_DEV_P58_PARIF_MAX; parif++) { - if (parif_bitmask & (1UL << parif)) { - if (parif < 8) { - shift = 4 * parif; - parif_pf_mask[0] |= TF_DEV_P58_PF_MASK << shift; - parif_pf[0] |= pf << shift; - } else { - shift = 4 * (parif - 8); - parif_pf_mask[1] |= TF_DEV_P58_PF_MASK << shift; - parif_pf[1] |= pf << shift; - } - } - } - tfp_memcpy(data, parif_pf, sz_in_bytes); - tfp_memcpy(mask, parif_pf_mask, sz_in_bytes); - - return 0; -} - static int tf_dev_p58_get_mailbox(void) { return TF_CHIMP_MB; @@ -268,7 +219,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_delete_ext_em_entry = NULL, .tf_dev_alloc_tbl_scope = NULL, .tf_dev_map_tbl_scope = NULL, - .tf_dev_map_parif = tf_dev_p58_map_parif, + .tf_dev_map_parif = NULL, .tf_dev_free_tbl_scope = NULL, .tf_dev_set_if_tbl = tf_if_tbl_set, .tf_dev_get_if_tbl = tf_if_tbl_get, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index de7bb1cd76..abd916985e 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -64,6 +64,105 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { [TF_TBL_TYPE_MIRROR_CONFIG] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR }, + /* Policy - ARs in bank 1 */ + [TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + .divider = 8, + }, + [TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + .divider = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + .divider = 8, + }, + [TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + .divider = 8, + }, + [TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + .divider = 8, + }, + [TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + .divider = 8, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + .divider = 8, + }, + [TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + .divider = 8, + }, + [TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + .divider = 8, + }, + [TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + .divider = 8, + }, + /* Policy - SP in bank 0 */ + [TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + .divider = 8, + }, + [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + .divider = 8, + }, + [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + .divider = 8, + }, + /* Policy - Stats in bank 3 */ + [TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + .divider = 8, + }, }; struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { @@ -72,7 +171,16 @@ struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { }, }; -struct tf_if_tbl_cfg tf_if_tbl_p58[TF_IF_TBL_TYPE_MAX]; +struct tf_if_tbl_cfg tf_if_tbl_p58[TF_IF_TBL_TYPE_MAX] = { + [TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = { + TF_IF_TBL_CFG, CFA_P58_TBL_PROF_PARIF_DFLT_ACT_REC_PTR}, + [TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = { + TF_IF_TBL_CFG, CFA_P58_TBL_PROF_PARIF_ERR_ACT_REC_PTR}, + [TF_IF_TBL_TYPE_ILT] = { + TF_IF_TBL_CFG, CFA_P58_TBL_ILT}, + [TF_IF_TBL_TYPE_VSPT] = { + TF_IF_TBL_CFG, CFA_P58_TBL_VSPT}, +}; struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { [TF_TUNNEL_ENCAP] = { diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index 6cd6086685..589df60041 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -54,7 +54,7 @@ tbl_scope_cb_find(uint32_t tbl_scope_id) /* Check that id is valid */ parms.rm_db = eem_db[TF_DIR_RX]; - parms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE; + parms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; parms.index = tbl_scope_id; parms.allocated = &allocated; @@ -895,7 +895,7 @@ tf_em_ext_common_bind(struct tf *tfp, return -EINVAL; } - db_cfg.type = TF_DEVICE_MODULE_TYPE_EM; + db_cfg.module = TF_MODULE_TYPE_EM; db_cfg.num_elements = parms->num_elements; db_cfg.cfg = parms->cfg; diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c index 69f7e5bddd..166f397935 100644 --- a/drivers/net/bnxt/tf_core/tf_em_host.c +++ b/drivers/net/bnxt/tf_core/tf_em_host.c @@ -379,7 +379,7 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) /* Get Table Scope control block from the session pool */ aparms.rm_db = eem_db[TF_DIR_RX]; - aparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE; + aparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; aparms.index = (uint32_t *)&parms->tbl_scope_id; rc = tf_rm_allocate(&aparms); if (rc) { @@ -488,7 +488,7 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) cleanup: /* Free Table control block */ fparms.rm_db = eem_db[TF_DIR_RX]; - fparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE; + fparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; fparms.index = parms->tbl_scope_id; tf_rm_free(&fparms); return -EINVAL; @@ -512,7 +512,7 @@ tf_em_ext_free(struct tf *tfp, /* Free Table control block */ aparms.rm_db = eem_db[TF_DIR_RX]; - aparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE; + aparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; aparms.index = parms->tbl_scope_id; rc = tf_rm_free(&aparms); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 0864218469..043f9be4da 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -251,7 +251,7 @@ tf_em_int_bind(struct tf *tfp, return -EINVAL; } - db_cfg.type = TF_DEVICE_MODULE_TYPE_EM; + db_cfg.module = TF_MODULE_TYPE_EM; db_cfg.num_elements = parms->num_elements; db_cfg.cfg = parms->cfg; @@ -294,7 +294,7 @@ tf_em_int_bind(struct tf *tfp, for (i = 0; i < TF_DIR_MAX; i++) { iparms.rm_db = em_db[i]; - iparms.db_index = TF_EM_DB_EM_REC; + iparms.subtype = TF_EM_DB_EM_REC; iparms.info = &info; rc = tf_rm_get_info(&iparms); diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index 41ab13c132..9d0a578085 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -52,7 +52,7 @@ tf_ident_bind(struct tf *tfp, return -EINVAL; } - db_cfg.type = TF_DEVICE_MODULE_TYPE_IDENTIFIER; + db_cfg.module = TF_MODULE_TYPE_IDENTIFIER; db_cfg.num_elements = parms->num_elements; db_cfg.cfg = parms->cfg; @@ -161,7 +161,7 @@ tf_ident_alloc(struct tf *tfp __rte_unused, /* Allocate requested element */ aparms.rm_db = ident_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = &id; aparms.base_index = &base_id; rc = tf_rm_allocate(&aparms); @@ -215,7 +215,7 @@ tf_ident_free(struct tf *tfp __rte_unused, /* Check if element is in use */ aparms.rm_db = ident_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = parms->id; aparms.base_index = &base_id; aparms.allocated = &allocated; @@ -255,7 +255,7 @@ tf_ident_free(struct tf *tfp __rte_unused, /* Free requested element */ fparms.rm_db = ident_db[parms->dir]; - fparms.db_index = parms->type; + fparms.subtype = parms->type; fparms.index = parms->id; rc = tf_rm_free(&fparms); if (rc) { @@ -298,7 +298,7 @@ tf_ident_search(struct tf *tfp __rte_unused, /* Check if element is in use */ aparms.rm_db = ident_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = parms->search_id; aparms.base_index = &base_id; aparms.allocated = &allocated; diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.c b/drivers/net/bnxt/tf_core/tf_if_tbl.c index 16afa95e38..f58fa79b63 100644 --- a/drivers/net/bnxt/tf_core/tf_if_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_if_tbl.c @@ -144,7 +144,7 @@ int tf_if_tbl_get(struct tf *tfp, struct tf_if_tbl_get_parms *parms) { - int rc; + int rc = 0; struct tf_if_tbl_get_hcapi_parms hparms; TF_CHECK_PARMS3(tfp, parms, parms->data); diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index 19de6e4c63..9fd660543c 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -42,10 +42,18 @@ struct tf_rm_element { */ struct tf_rm_alloc_info alloc; + /** + * If cfg_type == HCAPI_BA_CHILD, this field indicates + * the parent module subtype for look up into the parent pool. + * An example subtype is TF_TBL_TYPE_FULL_ACT_RECORD which is a + * module subtype of TF_MODULE_TYPE_TABLE. + */ + uint16_t parent_subtype; + /** * Bit allocator pool for the element. Pool size is controlled * by the struct tf_session_resources at time of session creation. - * Null indicates that the element is not used for the device. + * Null indicates that the pool is not used for the element. */ struct bitalloc *pool; }; @@ -67,7 +75,7 @@ struct tf_rm_new_db { /** * Module type, used for logging purposes. */ - enum tf_device_module_type type; + enum tf_module_type module; /** * The DB consists of an array of elements @@ -100,7 +108,7 @@ struct tf_rm_new_db { */ static void tf_rm_count_hcapi_reservations(enum tf_dir dir, - enum tf_device_module_type type, + enum tf_module_type module, struct tf_rm_element_cfg *cfg, uint16_t *reservations, uint16_t count, @@ -110,8 +118,7 @@ tf_rm_count_hcapi_reservations(enum tf_dir dir, uint16_t cnt = 0; for (i = 0; i < count; i++) { - if ((cfg[i].cfg_type == TF_RM_ELEM_CFG_HCAPI || - cfg[i].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA) && + if (cfg[i].cfg_type != TF_RM_ELEM_CFG_NULL && reservations[i] > 0) cnt++; @@ -120,14 +127,14 @@ tf_rm_count_hcapi_reservations(enum tf_dir dir, * split configuration array thus it would fail for * this type of check. */ - if (type != TF_DEVICE_MODULE_TYPE_EM && + if (module != TF_MODULE_TYPE_EM && cfg[i].cfg_type == TF_RM_ELEM_CFG_NULL && reservations[i] > 0) { TFP_DRV_LOG(ERR, "%s, %s, %s allocation of %d not supported\n", - tf_device_module_type_2_str(type), + tf_module_2_str(module), tf_dir_2_str(dir), - tf_device_module_type_subtype_2_str(type, i), + tf_module_subtype_2_str(module, i), reservations[i]); } } @@ -156,8 +163,10 @@ enum tf_rm_adjust_type { * [in] action * Adjust action * - * [in] db_index - * DB index for the element type + * [in] subtype + * TF module subtype used as an index into the database. + * An example subtype is TF_TBL_TYPE_FULL_ACT_RECORD which is a + * module subtype of TF_MODULE_TYPE_TABLE. * * [in] index * Index to convert @@ -172,14 +181,14 @@ enum tf_rm_adjust_type { static int tf_rm_adjust_index(struct tf_rm_element *db, enum tf_rm_adjust_type action, - uint32_t db_index, + uint32_t subtype, uint32_t index, uint32_t *adj_index) { int rc = 0; uint32_t base_index; - base_index = db[db_index].alloc.entry.start; + base_index = db[subtype].alloc.entry.start; switch (action) { case TF_RM_ADJUST_RM_BASE: @@ -201,7 +210,7 @@ tf_rm_adjust_index(struct tf_rm_element *db, * [in] dir * Receive or transmit direction * - * [in] type + * [in] module * Type of Device Module * * [in] count @@ -214,7 +223,7 @@ tf_rm_adjust_index(struct tf_rm_element *db, */ static void tf_rm_log_residuals(enum tf_dir dir, - enum tf_device_module_type type, + enum tf_module_type module, uint16_t count, uint16_t *residuals) { @@ -228,7 +237,7 @@ tf_rm_log_residuals(enum tf_dir dir, TFP_DRV_LOG(ERR, "%s, %s was not cleaned up, %d outstanding\n", tf_dir_2_str(dir), - tf_device_module_type_subtype_2_str(type, i), + tf_module_subtype_2_str(module, i), residuals[i]); } } @@ -295,7 +304,7 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db, iparms.rm_db = rm_db; iparms.count = &count; for (i = 0, found = 0; i < rm_db->num_entries; i++) { - iparms.db_index = i; + iparms.subtype = i; rc = tf_rm_get_inuse_count(&iparms); /* Not a device supported entry, just skip */ if (rc == -ENOTSUP) @@ -329,13 +338,13 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db, for (i = 0, f = 0; i < rm_db->num_entries; i++) { if (residuals[i] == 0) continue; - aparms.db_index = i; + aparms.subtype = i; aparms.info = &info; rc = tf_rm_get_info(&aparms); if (rc) goto cleanup_all; - hparms.db_index = i; + hparms.subtype = i; rc = tf_rm_get_hcapi_type(&hparms); if (rc) goto cleanup_all; @@ -349,7 +358,7 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db, } tf_rm_log_residuals(rm_db->dir, - rm_db->type, + rm_db->module, rm_db->num_entries, residuals); @@ -367,16 +376,93 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db, return rc; } +/** + * Some resources do not have a 1:1 mapping between the Truflow type and the cfa + * resource type (HCAPI RM). These resources have multiple Truflow types which + * map to a single HCAPI RM type. In order to support this, one Truflow type + * sharing the HCAPI resources is designated the parent. All other Truflow + * types associated with that HCAPI RM type are designated the children. + * + * This function updates the resource counts of any HCAPI_BA_PARENT with the + * counts of the HCAPI_BA_CHILDREN. These are read from the alloc_cnt and + * written back to the req_cnt. + * + * [in] cfg + * Pointer to an array of module specific Truflow type indexed RM cfg items + * + * [in] alloc_cnt + * Pointer to the tf_open_session() configured array of module specific + * Truflow type indexed requested counts. + * + * [in/out] req_cnt + * Pointer to the location to put the updated resource counts. + * + * Returns: + * 0 - Success + * - - Failure if negative + */ +static int +tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg, + uint16_t *alloc_cnt, + uint16_t num_elements, + uint16_t *req_cnt) +{ + int parent, child; + + /* Search through all the elements */ + for (parent = 0; parent < num_elements; parent++) { + uint16_t combined_cnt = 0; + + /* If I am a parent */ + if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) { + /* start with my own count */ + RTE_ASSERT(cfg[parent].slices); + combined_cnt = + alloc_cnt[parent] / cfg[parent].slices; + + if (alloc_cnt[parent] % cfg[parent].slices) + combined_cnt++; + + /* Search again through all the elements */ + for (child = 0; child < num_elements; child++) { + /* If this is one of my children */ + if (cfg[child].cfg_type == + TF_RM_ELEM_CFG_HCAPI_BA_CHILD && + cfg[child].parent_subtype == parent) { + uint16_t cnt = 0; + RTE_ASSERT(cfg[child].slices); + + /* Increment the parents combined count + * with each child's count adjusted for + * number of slices per RM alloced item. + */ + cnt = + alloc_cnt[child] / cfg[child].slices; + + if (alloc_cnt[child] % cfg[child].slices) + cnt++; + + combined_cnt += cnt; + /* Clear the requested child count */ + req_cnt[child] = 0; + } + } + /* Save the parent count to be requested */ + req_cnt[parent] = combined_cnt; + } + } + return 0; +} + int tf_rm_create_db(struct tf *tfp, struct tf_rm_create_db_parms *parms) { int rc; - int i; - int j; struct tf_session *tfs; struct tf_dev_info *dev; - uint16_t max_types; + int i, j; + uint16_t max_types, hcapi_items, *req_cnt; struct tfp_calloc_parms cparms; struct tf_rm_resc_req_entry *query; enum tf_rm_resc_resv_strategy resv_strategy; @@ -385,7 +471,6 @@ tf_rm_create_db(struct tf *tfp, struct tf_rm_new_db *rm_db; struct tf_rm_element *db; uint32_t pool_size; - uint16_t hcapi_items; TF_CHECK_PARMS2(tfp, parms); @@ -401,9 +486,9 @@ tf_rm_create_db(struct tf *tfp, /* Need device max number of elements for the RM QCAPS */ rc = dev->ops->tf_dev_get_max_types(tfp, &max_types); - if (rc) - return rc; + + /* Allocate memory for RM QCAPS request */ cparms.nitems = max_types; cparms.size = sizeof(struct tf_rm_resc_req_entry); cparms.alignment = 0; @@ -423,6 +508,28 @@ tf_rm_create_db(struct tf *tfp, if (rc) return rc; + /* Copy requested counts (alloc_cnt) from tf_open_session() to local + * copy (req_cnt) so that it can be updated if required. + */ + + cparms.nitems = parms->num_elements; + cparms.size = sizeof(uint16_t); + rc = tfp_calloc(&cparms); + if (rc) + return rc; + + req_cnt = (uint16_t *)cparms.mem_va; + + tfp_memcpy(req_cnt, parms->alloc_cnt, + parms->num_elements * sizeof(uint16_t)); + + /* Update the req_cnt based upon the element configuration + */ + tf_rm_update_parent_reservations(parms->cfg, + parms->alloc_cnt, + parms->num_elements, + req_cnt); + /* Process capabilities against DB requirements. However, as a * DB can hold elements that are not HCAPI we can reduce the * req msg content by removing those out of the request yet @@ -430,21 +537,17 @@ tf_rm_create_db(struct tf *tfp, * remove entries where there are no request for elements. */ tf_rm_count_hcapi_reservations(parms->dir, - parms->type, + parms->module, parms->cfg, - parms->alloc_cnt, + req_cnt, parms->num_elements, &hcapi_items); - /* Handle the case where a DB create request really ends up - * being empty. Unsupported (if not rare) case but possible - * that no resources are necessary for a 'direction'. - */ if (hcapi_items == 0) { TFP_DRV_LOG(ERR, - "%s: DB create request for Zero elements, DB Type:%s\n", - tf_dir_2_str(parms->dir), - tf_device_module_type_2_str(parms->type)); + "%s: module:%s Empty RM DB create request\n", + tf_dir_2_str(parms->dir), + tf_module_2_str(parms->module)); parms->rm_db = NULL; return -ENOMEM; @@ -467,44 +570,45 @@ tf_rm_create_db(struct tf *tfp, /* Build the request */ for (i = 0, j = 0; i < parms->num_elements; i++) { - /* Skip any non HCAPI cfg elements */ - if (parms->cfg[i].cfg_type == TF_RM_ELEM_CFG_HCAPI || - parms->cfg[i].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA) { - /* Only perform reservation for entries that - * has been requested - */ - if (parms->alloc_cnt[i] == 0) - continue; + struct tf_rm_element_cfg *cfg = &parms->cfg[i]; + uint16_t hcapi_type = cfg->hcapi_type; + + /* Only perform reservation for requested entries + */ + if (req_cnt[i] == 0) + continue; + + /* Skip any children in the request */ + if (cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI || + cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA || + cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) { - /* Verify that we can get the full amount - * allocated per the qcaps availability. + /* Verify that we can get the full amount per qcaps. */ - if (parms->alloc_cnt[i] <= - query[parms->cfg[i].hcapi_type].max) { - req[j].type = parms->cfg[i].hcapi_type; - req[j].min = parms->alloc_cnt[i]; - req[j].max = parms->alloc_cnt[i]; + if (req_cnt[i] <= query[hcapi_type].max) { + req[j].type = hcapi_type; + req[j].min = req_cnt[i]; + req[j].max = req_cnt[i]; j++; } else { const char *type_str; - uint16_t hcapi_type = parms->cfg[i].hcapi_type; dev->ops->tf_dev_get_resource_str(tfp, - hcapi_type, - &type_str); + hcapi_type, + &type_str); TFP_DRV_LOG(ERR, - "%s: Resource failure, type:%d:%s\n", - tf_dir_2_str(parms->dir), - hcapi_type, type_str); - TFP_DRV_LOG(ERR, - "req:%d, avail:%d\n", - parms->alloc_cnt[i], - query[hcapi_type].max); + "Failure, %s:%d:%s req:%d avail:%d\n", + tf_dir_2_str(parms->dir), + hcapi_type, type_str, + req_cnt[i], + query[hcapi_type].max); return -EINVAL; } } } + /* Allocate all resources for the module type + */ rc = tf_msg_session_resc_alloc(tfp, dev, parms->dir, @@ -532,32 +636,56 @@ tf_rm_create_db(struct tf *tfp, db = rm_db->db; for (i = 0, j = 0; i < parms->num_elements; i++) { - db[i].cfg_type = parms->cfg[i].cfg_type; - db[i].hcapi_type = parms->cfg[i].hcapi_type; + struct tf_rm_element_cfg *cfg = &parms->cfg[i]; + const char *type_str; + + dev->ops->tf_dev_get_resource_str(tfp, + cfg->hcapi_type, + &type_str); - /* Skip any non HCAPI types as we didn't include them - * in the reservation request. + db[i].cfg_type = cfg->cfg_type; + db[i].hcapi_type = cfg->hcapi_type; + + /* Save the parent subtype for later use to find the pool */ - if (parms->cfg[i].cfg_type != TF_RM_ELEM_CFG_HCAPI && - parms->cfg[i].cfg_type != TF_RM_ELEM_CFG_HCAPI_BA) - continue; + if (cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD) + db[i].parent_subtype = cfg->parent_subtype; /* If the element didn't request an allocation no need * to create a pool nor verify if we got a reservation. */ - if (parms->alloc_cnt[i] == 0) + if (req_cnt[i] == 0) + continue; + + /* Skip any children or invalid + */ + if (cfg->cfg_type != TF_RM_ELEM_CFG_HCAPI && + cfg->cfg_type != TF_RM_ELEM_CFG_HCAPI_BA && + cfg->cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT) continue; /* If the element had requested an allocation and that * allocation was a success (full amount) then * allocate the pool. */ - if (parms->alloc_cnt[i] == resv[j].stride) { + if (req_cnt[i] == resv[j].stride) { db[i].alloc.entry.start = resv[j].start; db[i].alloc.entry.stride = resv[j].stride; - /* Only allocate BA pool if so requested */ - if (parms->cfg[i].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA) { + /* Only allocate BA pool if a BA type not a child */ + if (cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA || + cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) { + if (cfg->divider) { + resv[j].stride = + resv[j].stride / cfg->divider; + if (resv[j].stride <= 0) { + TFP_DRV_LOG(ERR, + "%s:Divide fails:%d:%s\n", + tf_dir_2_str(parms->dir), + cfg->hcapi_type, type_str); + goto fail; + } + } /* Create pool */ pool_size = (BITALLOC_SIZEOF(resv[j].stride) / sizeof(struct bitalloc)); @@ -567,9 +695,9 @@ tf_rm_create_db(struct tf *tfp, rc = tfp_calloc(&cparms); if (rc) { TFP_DRV_LOG(ERR, - "%s: Pool alloc failed, type:%d\n", - tf_dir_2_str(parms->dir), - db[i].cfg_type); + "%s: Pool alloc failed, type:%d:%s\n", + tf_dir_2_str(parms->dir), + cfg->hcapi_type, type_str); goto fail; } db[i].pool = (struct bitalloc *)cparms.mem_va; @@ -577,9 +705,9 @@ tf_rm_create_db(struct tf *tfp, rc = ba_init(db[i].pool, resv[j].stride); if (rc) { TFP_DRV_LOG(ERR, - "%s: Pool init failed, type:%d\n", - tf_dir_2_str(parms->dir), - db[i].cfg_type); + "%s: Pool init failed, type:%d:%s\n", + tf_dir_2_str(parms->dir), + cfg->hcapi_type, type_str); goto fail; } } @@ -589,25 +717,21 @@ tf_rm_create_db(struct tf *tfp, * all elements, not any less. */ TFP_DRV_LOG(ERR, - "%s: Alloc failed, type:%d\n", - tf_dir_2_str(parms->dir), - db[i].cfg_type); - TFP_DRV_LOG(ERR, - "req:%d, alloc:%d\n", - parms->alloc_cnt[i], - resv[j].stride); + "%s: Alloc failed %d:%s req:%d, alloc:%d\n", + tf_dir_2_str(parms->dir), cfg->hcapi_type, + type_str, req_cnt[i], resv[j].stride); goto fail; } } rm_db->num_entries = parms->num_elements; rm_db->dir = parms->dir; - rm_db->type = parms->type; + rm_db->module = parms->module; *parms->rm_db = (void *)rm_db; tfp_free((void *)req); tfp_free((void *)resv); - + tfp_free((void *)req_cnt); return 0; fail: @@ -616,6 +740,7 @@ tf_rm_create_db(struct tf *tfp, tfp_free((void *)db->pool); tfp_free((void *)db); tfp_free((void *)rm_db); + tfp_free((void *)req_cnt); parms->rm_db = NULL; return -EINVAL; @@ -682,7 +807,7 @@ tf_rm_free_db(struct tf *tfp, TFP_DRV_LOG(ERR, "%s: Internal Flush error, module:%s\n", tf_dir_2_str(parms->dir), - tf_device_module_type_2_str(rm_db->type)); + tf_module_2_str(rm_db->module)); } /* No need to check for configuration type, even if we do not @@ -695,6 +820,54 @@ tf_rm_free_db(struct tf *tfp, return rc; } +/** + * Get the bit allocator pool associated with the subtype and the db + * + * [in] rm_db + * Pointer to the DB + * + * [in] subtype + * Module subtype used to index into the module specific database. + * An example subtype is TF_TBL_TYPE_FULL_ACT_RECORD which is a + * module subtype of TF_MODULE_TYPE_TABLE. + * + * [in/out] pool + * Pointer to the bit allocator pool used + * + * [in/out] new_subtype + * Pointer to the subtype of the actual pool used + * Returns: + * 0 - Success + * - ENOTSUP - Operation not supported + */ +static int +tf_rm_get_pool(struct tf_rm_new_db *rm_db, + uint16_t subtype, + struct bitalloc **pool, + uint16_t *new_subtype) +{ + int rc = 0; + uint16_t tmp_subtype = subtype; + + /* If we are a child, get the parent table index */ + if (rm_db->db[subtype].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD) + tmp_subtype = rm_db->db[subtype].parent_subtype; + + *pool = rm_db->db[tmp_subtype].pool; + + /* Bail out if the pool is not valid, should never happen */ + if (rm_db->db[tmp_subtype].pool == NULL) { + rc = -ENOTSUP; + TFP_DRV_LOG(ERR, + "%s: Invalid pool for this type:%d, rc:%s\n", + tf_dir_2_str(rm_db->dir), + tmp_subtype, + strerror(-rc)); + return rc; + } + *new_subtype = tmp_subtype; + return rc; +} int tf_rm_allocate(struct tf_rm_allocate_parms *parms) @@ -704,37 +877,33 @@ tf_rm_allocate(struct tf_rm_allocate_parms *parms) uint32_t index; struct tf_rm_new_db *rm_db; enum tf_rm_elem_cfg_type cfg_type; + struct bitalloc *pool; + uint16_t subtype; TF_CHECK_PARMS2(parms, parms->rm_db); rm_db = (struct tf_rm_new_db *)parms->rm_db; - if (!rm_db->db) - return -EINVAL; - cfg_type = rm_db->db[parms->db_index].cfg_type; + TF_CHECK_PARMS1(rm_db->db); + + cfg_type = rm_db->db[parms->subtype].cfg_type; /* Bail out if not controlled by RM */ - if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA) + if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_CHILD) return -ENOTSUP; - /* Bail out if the pool is not valid, should never happen */ - if (rm_db->db[parms->db_index].pool == NULL) { - rc = -ENOTSUP; - TFP_DRV_LOG(ERR, - "%s: Invalid pool for this type:%d, rc:%s\n", - tf_dir_2_str(rm_db->dir), - parms->db_index, - strerror(-rc)); + rc = tf_rm_get_pool(rm_db, parms->subtype, &pool, &subtype); + if (rc) return rc; - } - /* * priority 0: allocate from top of the tcam i.e. high * priority !0: allocate index from bottom i.e lowest */ if (parms->priority) - id = ba_alloc_reverse(rm_db->db[parms->db_index].pool); + id = ba_alloc_reverse(pool); else - id = ba_alloc(rm_db->db[parms->db_index].pool); + id = ba_alloc(pool); if (id == BA_FAIL) { rc = -ENOMEM; TFP_DRV_LOG(ERR, @@ -747,7 +916,7 @@ tf_rm_allocate(struct tf_rm_allocate_parms *parms) /* Adjust for any non zero start value */ rc = tf_rm_adjust_index(rm_db->db, TF_RM_ADJUST_ADD_BASE, - parms->db_index, + subtype, id, &index); if (rc) { @@ -772,39 +941,35 @@ tf_rm_free(struct tf_rm_free_parms *parms) uint32_t adj_index; struct tf_rm_new_db *rm_db; enum tf_rm_elem_cfg_type cfg_type; + struct bitalloc *pool; + uint16_t subtype; TF_CHECK_PARMS2(parms, parms->rm_db); - rm_db = (struct tf_rm_new_db *)parms->rm_db; - if (!rm_db->db) - return -EINVAL; - cfg_type = rm_db->db[parms->db_index].cfg_type; + TF_CHECK_PARMS1(rm_db->db); + + cfg_type = rm_db->db[parms->subtype].cfg_type; /* Bail out if not controlled by RM */ - if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA) + if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_CHILD) return -ENOTSUP; - /* Bail out if the pool is not valid, should never happen */ - if (rm_db->db[parms->db_index].pool == NULL) { - rc = -ENOTSUP; - TFP_DRV_LOG(ERR, - "%s: Invalid pool for this type:%d, rc:%s\n", - tf_dir_2_str(rm_db->dir), - parms->db_index, - strerror(-rc)); + rc = tf_rm_get_pool(rm_db, parms->subtype, &pool, &subtype); + if (rc) return rc; - } /* Adjust for any non zero start value */ rc = tf_rm_adjust_index(rm_db->db, TF_RM_ADJUST_RM_BASE, - parms->db_index, + subtype, parms->index, &adj_index); if (rc) return rc; - rc = ba_free(rm_db->db[parms->db_index].pool, adj_index); + rc = ba_free(pool, adj_index); /* No logging direction matters and that is not available here */ if (rc) return rc; @@ -819,33 +984,30 @@ tf_rm_is_allocated(struct tf_rm_is_allocated_parms *parms) uint32_t adj_index; struct tf_rm_new_db *rm_db; enum tf_rm_elem_cfg_type cfg_type; + struct bitalloc *pool; + uint16_t subtype; TF_CHECK_PARMS2(parms, parms->rm_db); - rm_db = (struct tf_rm_new_db *)parms->rm_db; - if (!rm_db->db) - return -EINVAL; - cfg_type = rm_db->db[parms->db_index].cfg_type; + TF_CHECK_PARMS1(rm_db->db); + + cfg_type = rm_db->db[parms->subtype].cfg_type; + /* Bail out if not controlled by RM */ - if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA) + if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_CHILD) return -ENOTSUP; - /* Bail out if the pool is not valid, should never happen */ - if (rm_db->db[parms->db_index].pool == NULL) { - rc = -ENOTSUP; - TFP_DRV_LOG(ERR, - "%s: Invalid pool for this type:%d, rc:%s\n", - tf_dir_2_str(rm_db->dir), - parms->db_index, - strerror(-rc)); + rc = tf_rm_get_pool(rm_db, parms->subtype, &pool, &subtype); + if (rc) return rc; - } /* Adjust for any non zero start value */ rc = tf_rm_adjust_index(rm_db->db, TF_RM_ADJUST_RM_BASE, - parms->db_index, + subtype, parms->index, &adj_index); if (rc) @@ -853,8 +1015,7 @@ tf_rm_is_allocated(struct tf_rm_is_allocated_parms *parms) if (parms->base_index) *parms->base_index = adj_index; - *parms->allocated = ba_inuse(rm_db->db[parms->db_index].pool, - adj_index); + *parms->allocated = ba_inuse(pool, adj_index); return rc; } @@ -866,19 +1027,17 @@ tf_rm_get_info(struct tf_rm_get_alloc_info_parms *parms) enum tf_rm_elem_cfg_type cfg_type; TF_CHECK_PARMS2(parms, parms->rm_db); - rm_db = (struct tf_rm_new_db *)parms->rm_db; - if (!rm_db->db) - return -EINVAL; - cfg_type = rm_db->db[parms->db_index].cfg_type; + TF_CHECK_PARMS1(rm_db->db); + + cfg_type = rm_db->db[parms->subtype].cfg_type; /* Bail out if not controlled by HCAPI */ - if (cfg_type != TF_RM_ELEM_CFG_HCAPI && - cfg_type != TF_RM_ELEM_CFG_HCAPI_BA) + if (cfg_type == TF_RM_ELEM_CFG_NULL) return -ENOTSUP; memcpy(parms->info, - &rm_db->db[parms->db_index].alloc, + &rm_db->db[parms->subtype].alloc, sizeof(struct tf_rm_alloc_info)); return 0; @@ -891,18 +1050,16 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms) enum tf_rm_elem_cfg_type cfg_type; TF_CHECK_PARMS2(parms, parms->rm_db); - rm_db = (struct tf_rm_new_db *)parms->rm_db; - if (!rm_db->db) - return -EINVAL; - cfg_type = rm_db->db[parms->db_index].cfg_type; + TF_CHECK_PARMS1(rm_db->db); + + cfg_type = rm_db->db[parms->subtype].cfg_type; /* Bail out if not controlled by HCAPI */ - if (cfg_type != TF_RM_ELEM_CFG_HCAPI && - cfg_type != TF_RM_ELEM_CFG_HCAPI_BA) + if (cfg_type == TF_RM_ELEM_CFG_NULL) return -ENOTSUP; - *parms->hcapi_type = rm_db->db[parms->db_index].hcapi_type; + *parms->hcapi_type = rm_db->db[parms->subtype].hcapi_type; return 0; } @@ -915,30 +1072,31 @@ tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms) enum tf_rm_elem_cfg_type cfg_type; TF_CHECK_PARMS2(parms, parms->rm_db); - rm_db = (struct tf_rm_new_db *)parms->rm_db; - if (!rm_db->db) - return -EINVAL; - cfg_type = rm_db->db[parms->db_index].cfg_type; + TF_CHECK_PARMS1(rm_db->db); - /* Bail out if not controlled by RM */ - if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA) + cfg_type = rm_db->db[parms->subtype].cfg_type; + + /* Bail out if not a BA pool */ + if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_CHILD) return -ENOTSUP; /* Bail silently (no logging), if the pool is not valid there * was no elements allocated for it. */ - if (rm_db->db[parms->db_index].pool == NULL) { + if (rm_db->db[parms->subtype].pool == NULL) { *parms->count = 0; return 0; } - *parms->count = ba_inuse_count(rm_db->db[parms->db_index].pool); + *parms->count = ba_inuse_count(rm_db->db[parms->subtype].pool); return rc; - } - +/* Only used for table bulk get at this time + */ int tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms) { @@ -947,31 +1105,27 @@ tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms) uint32_t base_index; uint32_t stride; int rc = 0; + struct bitalloc *pool; + uint16_t subtype; TF_CHECK_PARMS2(parms, parms->rm_db); - rm_db = (struct tf_rm_new_db *)parms->rm_db; - if (!rm_db->db) - return -EINVAL; - cfg_type = rm_db->db[parms->db_index].cfg_type; + TF_CHECK_PARMS1(rm_db->db); - /* Bail out if not controlled by RM */ - if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA) + cfg_type = rm_db->db[parms->subtype].cfg_type; + + /* Bail out if not a BA pool */ + if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT && + cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_CHILD) return -ENOTSUP; - /* Bail out if the pool is not valid, should never happen */ - if (rm_db->db[parms->db_index].pool == NULL) { - rc = -ENOTSUP; - TFP_DRV_LOG(ERR, - "%s: Invalid pool for this type:%d, rc:%s\n", - tf_dir_2_str(rm_db->dir), - parms->db_index, - strerror(-rc)); + rc = tf_rm_get_pool(rm_db, parms->subtype, &pool, &subtype); + if (rc) return rc; - } - base_index = rm_db->db[parms->db_index].alloc.entry.start; - stride = rm_db->db[parms->db_index].alloc.entry.stride; + base_index = rm_db->db[subtype].alloc.entry.start; + stride = rm_db->db[subtype].alloc.entry.stride; if (parms->starting_index < base_index || parms->starting_index + parms->num_entries > base_index + stride) diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h index 291086c7c7..407c7d5bf9 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.h +++ b/drivers/net/bnxt/tf_core/tf_rm.h @@ -35,11 +35,11 @@ struct tf; * The RM DB will work on its initial allocated sizes so the * capability of dynamically growing a particular resource is not * possible. If this capability later becomes a requirement then the - * MAX pool size of the Chip œneeds to be added to the tf_rm_elem_info + * MAX pool size of the chip needs to be added to the tf_rm_elem_info * structure and several new APIs would need to be added to allow for * growth of a single TF resource type. * - * The access functions does not check for NULL pointers as it's a + * The access functions do not check for NULL pointers as they are a * support module, not called directly. */ @@ -65,19 +65,28 @@ enum tf_rm_elem_cfg_type { * No configuration */ TF_RM_ELEM_CFG_NULL, - /** HCAPI 'controlled', no RM storage thus the Device Module + /** HCAPI 'controlled', no RM storage so the module * using the RM can chose to handle storage locally. */ TF_RM_ELEM_CFG_HCAPI, - /** HCAPI 'controlled', uses a Bit Allocator Pool for internal + /** HCAPI 'controlled', uses a bit allocator pool for internal * storage in the RM. */ TF_RM_ELEM_CFG_HCAPI_BA, /** - * Shared element thus it belongs to a shared FW Session and - * is not controlled by the Host. + * HCAPI 'controlled', uses a bit allocator pool for internal + * storage in the RM but multiple TF types map to a single + * HCAPI type. Parent manages the table. */ - TF_RM_ELEM_CFG_SHARED, + TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + /** + * HCAPI 'controlled', uses a bit allocator pool for internal + * storage in the RM but multiple TF types map to a single + * HCAPI type. Child accesses the parent db. + */ + TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + + TF_RM_TYPE_MAX }; @@ -114,6 +123,30 @@ struct tf_rm_element_cfg { * conversion. */ uint16_t hcapi_type; + + /** + * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD + * + * Parent Truflow module subtype associated with this resource type. + */ + uint16_t parent_subtype; + + /** + * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD + * + * Resource slices. How many slices will fit in the + * resource pool chunk size. + */ + uint8_t slices; + /** + * Pool element divider count + * If 0 or 1, there is 1:1 correspondence between the RM + * BA pool resource element and the HCAPI RM firmware + * resource. If > 1, the RM BA pool element has a 1:n + * correspondence to the HCAPI RM firmware resource. + */ + uint8_t divider; + }; /** @@ -135,9 +168,9 @@ struct tf_rm_alloc_info { */ struct tf_rm_create_db_parms { /** - * [in] Device module type. Used for logging purposes. + * [in] Module type. Used for logging purposes. */ - enum tf_device_module_type type; + enum tf_module_type module; /** * [in] Receive or transmit direction. */ @@ -153,8 +186,7 @@ struct tf_rm_create_db_parms { /** * Resource allocation count array. This array content * originates from the tf_session_resources that is passed in - * on session open. - * Array size is num_elements. + * on session open. Array size is num_elements. */ uint16_t *alloc_cnt; /** @@ -186,10 +218,11 @@ struct tf_rm_allocate_parms { */ void *rm_db; /** - * [in] DB Index, indicates which DB entry to perform the - * action on. + * [in] Module subtype indicates which DB entry to perform the + * action on. (e.g. TF_TCAM_TBL_TYPE_L2_CTXT subtype of module + * TF_MODULE_TYPE_TCAM) */ - uint16_t db_index; + uint16_t subtype; /** * [in] Pointer to the allocated index in normalized * form. Normalized means the index has been adjusted, @@ -219,10 +252,11 @@ struct tf_rm_free_parms { */ void *rm_db; /** - * [in] DB Index, indicates which DB entry to perform the - * action on. + * [in] TF subtype indicates which DB entry to perform the + * action on. (e.g. TF_TCAM_TBL_TYPE_L2_CTXT subtype of module + * TF_MODULE_TYPE_TCAM) */ - uint16_t db_index; + uint16_t subtype; /** * [in] Index to free */ @@ -238,10 +272,11 @@ struct tf_rm_is_allocated_parms { */ void *rm_db; /** - * [in] DB Index, indicates which DB entry to perform the - * action on. + * [in] TF subtype indicates which DB entry to perform the + * action on. (e.g. TF_TCAM_TBL_TYPE_L2_CTXT subtype of module + * TF_MODULE_TYPE_TCAM) */ - uint16_t db_index; + uint16_t subtype; /** * [in] Index to free */ @@ -265,13 +300,14 @@ struct tf_rm_get_alloc_info_parms { */ void *rm_db; /** - * [in] DB Index, indicates which DB entry to perform the - * action on. + * [in] TF subtype indicates which DB entry to perform the + * action on. (e.g. TF_TCAM_TBL_TYPE_L2_CTXT subtype of module + * TF_MODULE_TYPE_TCAM) */ - uint16_t db_index; + uint16_t subtype; /** * [out] Pointer to the requested allocation information for - * the specified db_index + * the specified subtype */ struct tf_rm_alloc_info *info; }; @@ -285,12 +321,13 @@ struct tf_rm_get_hcapi_parms { */ void *rm_db; /** - * [in] DB Index, indicates which DB entry to perform the - * action on. + * [in] TF subtype indicates which DB entry to perform the + * action on. (e.g. TF_TCAM_TBL_TYPE_L2_CTXT subtype of module + * TF_MODULE_TYPE_TCAM) */ - uint16_t db_index; + uint16_t subtype; /** - * [out] Pointer to the hcapi type for the specified db_index + * [out] Pointer to the hcapi type for the specified subtype */ uint16_t *hcapi_type; }; @@ -304,12 +341,13 @@ struct tf_rm_get_inuse_count_parms { */ void *rm_db; /** - * [in] DB Index, indicates which DB entry to perform the - * action on. + * [in] TF subtype indicates which DB entry to perform the + * action on. (e.g. TF_TCAM_TBL_TYPE_L2_CTXT subtype of module + * TF_MODULE_TYPE_TCAM) */ - uint16_t db_index; + uint16_t subtype; /** - * [out] Pointer to the inuse count for the specified db_index + * [out] Pointer to the inuse count for the specified subtype */ uint16_t *count; }; @@ -323,10 +361,11 @@ struct tf_rm_check_indexes_in_range_parms { */ void *rm_db; /** - * [in] DB Index, indicates which DB entry to perform the - * action on. + * [in] TF subtype indicates which DB entry to perform the + * action on. (e.g. TF_TCAM_TBL_TYPE_L2_CTXT subtype of module + * TF_MODULE_TYPE_TCAM) */ - uint16_t db_index; + uint16_t subtype; /** * [in] Starting index */ diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tbl.c b/drivers/net/bnxt/tf_core/tf_shadow_tbl.c deleted file mode 100644 index 396ebdb0a9..0000000000 --- a/drivers/net/bnxt/tf_core/tf_shadow_tbl.c +++ /dev/null @@ -1,783 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ - -#include "tf_common.h" -#include "tf_util.h" -#include "tfp.h" -#include "tf_core.h" -#include "tf_shadow_tbl.h" -#include "tf_hash.h" - -/** - * The implementation includes 3 tables per table table type. - * - hash table - * - sized so that a minimum of 4 slots per shadow entry are available to - * minimize the likelihood of collisions. - * - shadow key table - * - sized to the number of entries requested and is directly indexed - * - the index is zero based and is the table index - the base address - * - the data associated with the entry is stored in the key table. - * - The stored key is actually the data associated with the entry. - * - shadow result table - * - the result table is stored separately since it only needs to be accessed - * when the key matches. - * - the result has a back pointer to the hash table via the hb handle. The - * hb handle is a 32 bit represention of the hash with a valid bit, bucket - * element index, and the hash index. It is necessary to store the hb handle - * with the result since subsequent removes only provide the table index. - * - * - Max entries is limited in the current implementation since bit 15 is the - * valid bit in the hash table. - * - A 16bit hash is calculated and masked based on the number of entries - * - 64b wide bucket is used and broken into 4x16bit elements. - * This decision is based on quicker bucket scanning to determine if any - * elements are in use. - * - bit 15 of each bucket element is the valid, this is done to prevent having - * to read the larger key/result data for determining VALID. It also aids - * in the more efficient scanning of the bucket for slot usage. - */ - -/* - * The maximum number of shadow entries supported. The value also doubles as - * the maximum number of hash buckets. There are only 15 bits of data per - * bucket to point to the shadow tables. - */ -#define TF_SHADOW_ENTRIES_MAX (1 << 15) - -/* The number of elements(BE) per hash bucket (HB) */ -#define TF_SHADOW_HB_NUM_ELEM (4) -#define TF_SHADOW_BE_VALID (1 << 15) -#define TF_SHADOW_BE_IS_VALID(be) (((be) & TF_SHADOW_BE_VALID) != 0) - -/** - * The hash bucket handle is 32b - * - bit 31, the Valid bit - * - bit 29-30, the element - * - bits 0-15, the hash idx (is masked based on the allocated size) - */ -#define TF_SHADOW_HB_HANDLE_IS_VALID(hndl) (((hndl) & (1 << 31)) != 0) -#define TF_SHADOW_HB_HANDLE_CREATE(idx, be) ((1 << 31) | \ - ((be) << 29) | (idx)) - -#define TF_SHADOW_HB_HANDLE_BE_GET(hdl) (((hdl) >> 29) & \ - (TF_SHADOW_HB_NUM_ELEM - 1)) - -#define TF_SHADOW_HB_HANDLE_HASH_GET(ctxt, hdl)((hdl) & \ - (ctxt)->hash_ctxt.hid_mask) - -/** - * The idx provided by the caller is within a region, so currently the base is - * either added or subtracted from the idx to ensure it can be used as a - * compressed index - */ - -/* Convert the table index to a shadow index */ -#define TF_SHADOW_IDX_TO_SHIDX(ctxt, idx) ((idx) - \ - (ctxt)->shadow_ctxt.base_addr) - -/* Convert the shadow index to a tbl index */ -#define TF_SHADOW_SHIDX_TO_IDX(ctxt, idx) ((idx) + \ - (ctxt)->shadow_ctxt.base_addr) - -/* Simple helper masks for clearing en element from the bucket */ -#define TF_SHADOW_BE0_MASK_CLEAR(hb) ((hb) & 0xffffffffffff0000ull) -#define TF_SHADOW_BE1_MASK_CLEAR(hb) ((hb) & 0xffffffff0000ffffull) -#define TF_SHADOW_BE2_MASK_CLEAR(hb) ((hb) & 0xffff0000ffffffffull) -#define TF_SHADOW_BE3_MASK_CLEAR(hb) ((hb) & 0x0000ffffffffffffull) - -/** - * This should be coming from external, but for now it is assumed that no key - * is greater than 512 bits (64B). This makes allocation of the key table - * easier without having to allocate on the fly. - */ -#define TF_SHADOW_MAX_KEY_SZ 64 - -/* - * Local only defines for the internal data. - */ - -/** - * tf_shadow_tbl_shadow_key_entry is the key entry of the key table. - * The key stored in the table is the result data of the index table. - */ -struct tf_shadow_tbl_shadow_key_entry { - uint8_t key[TF_SHADOW_MAX_KEY_SZ]; -}; - -/** - * tf_shadow_tbl_shadow_result_entry is the result table entry. - * The result table writes are broken into two phases: - * - The search phase, which stores the hb_handle and key size and - * - The set phase, which writes the refcnt - */ -struct tf_shadow_tbl_shadow_result_entry { - uint16_t key_size; - uint32_t refcnt; - uint32_t hb_handle; -}; - -/** - * tf_shadow_tbl_shadow_ctxt holds all information for accessing the key and - * result tables. - */ -struct tf_shadow_tbl_shadow_ctxt { - struct tf_shadow_tbl_shadow_key_entry *sh_key_tbl; - struct tf_shadow_tbl_shadow_result_entry *sh_res_tbl; - uint32_t base_addr; - uint16_t num_entries; - uint16_t alloc_idx; -}; - -/** - * tf_shadow_tbl_hash_ctxt holds all information related to accessing the hash - * table. - */ -struct tf_shadow_tbl_hash_ctxt { - uint64_t *hashtbl; - uint16_t hid_mask; - uint16_t hash_entries; -}; - -/** - * tf_shadow_tbl_ctxt holds the hash and shadow tables for the current shadow - * table db. This structure is per table table type as each table table has - * it's own shadow and hash table. - */ -struct tf_shadow_tbl_ctxt { - struct tf_shadow_tbl_shadow_ctxt shadow_ctxt; - struct tf_shadow_tbl_hash_ctxt hash_ctxt; -}; - -/** - * tf_shadow_tbl_db is the allocated db structure returned as an opaque - * void * pointer to the caller during create db. It holds the pointers for - * each table associated with the db. - */ -struct tf_shadow_tbl_db { - /* Each context holds the shadow and hash table information */ - struct tf_shadow_tbl_ctxt *ctxt[TF_TBL_TYPE_MAX]; -}; - -/** - * Simple routine that decides what table types can be searchable. - * - */ -static int tf_shadow_tbl_is_searchable(enum tf_tbl_type type) -{ - int rc = 0; - - switch (type) { - case TF_TBL_TYPE_ACT_ENCAP_8B: - case TF_TBL_TYPE_ACT_ENCAP_16B: - case TF_TBL_TYPE_ACT_ENCAP_32B: - case TF_TBL_TYPE_ACT_ENCAP_64B: - case TF_TBL_TYPE_ACT_SP_SMAC: - case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: - case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: - case TF_TBL_TYPE_ACT_MODIFY_IPV4: - rc = 1; - break; - default: - rc = 0; - break; - }; - - return rc; -} - -/** - * Returns the number of entries in the contexts shadow table. - */ -static inline uint16_t -tf_shadow_tbl_sh_num_entries_get(struct tf_shadow_tbl_ctxt *ctxt) -{ - return ctxt->shadow_ctxt.num_entries; -} - -/** - * Compare the give key with the key in the shadow table. - * - * Returns 0 if the keys match - */ -static int -tf_shadow_tbl_key_cmp(struct tf_shadow_tbl_ctxt *ctxt, - uint8_t *key, - uint16_t sh_idx, - uint16_t size) -{ - if (size != ctxt->shadow_ctxt.sh_res_tbl[sh_idx].key_size || - sh_idx >= tf_shadow_tbl_sh_num_entries_get(ctxt) || !key) - return -1; - - return memcmp(key, ctxt->shadow_ctxt.sh_key_tbl[sh_idx].key, size); -} - -/** - * Free the memory associated with the context. - */ -static void -tf_shadow_tbl_ctxt_delete(struct tf_shadow_tbl_ctxt *ctxt) -{ - if (!ctxt) - return; - - tfp_free(ctxt->hash_ctxt.hashtbl); - tfp_free(ctxt->shadow_ctxt.sh_key_tbl); - tfp_free(ctxt->shadow_ctxt.sh_res_tbl); -} - -/** - * The TF Shadow TBL context is per TBL and holds all information relating to - * managing the shadow and search capability. This routine allocated data that - * needs to be deallocated by the tf_shadow_tbl_ctxt_delete prior when deleting - * the shadow db. - */ -static int -tf_shadow_tbl_ctxt_create(struct tf_shadow_tbl_ctxt *ctxt, - uint16_t num_entries, - uint16_t base_addr) -{ - struct tfp_calloc_parms cparms; - uint16_t hash_size = 1; - uint16_t hash_mask; - int rc; - - /* Hash table is a power of two that holds the number of entries */ - if (num_entries > TF_SHADOW_ENTRIES_MAX) { - TFP_DRV_LOG(ERR, "Too many entries for shadow %d > %d\n", - num_entries, - TF_SHADOW_ENTRIES_MAX); - return -ENOMEM; - } - - while (hash_size < num_entries) - hash_size = hash_size << 1; - - hash_mask = hash_size - 1; - - /* Allocate the hash table */ - cparms.nitems = hash_size; - cparms.size = sizeof(uint64_t); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - goto error; - ctxt->hash_ctxt.hashtbl = cparms.mem_va; - ctxt->hash_ctxt.hid_mask = hash_mask; - ctxt->hash_ctxt.hash_entries = hash_size; - - /* allocate the shadow tables */ - /* allocate the shadow key table */ - cparms.nitems = num_entries; - cparms.size = sizeof(struct tf_shadow_tbl_shadow_key_entry); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - goto error; - ctxt->shadow_ctxt.sh_key_tbl = cparms.mem_va; - - /* allocate the shadow result table */ - cparms.nitems = num_entries; - cparms.size = sizeof(struct tf_shadow_tbl_shadow_result_entry); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - goto error; - ctxt->shadow_ctxt.sh_res_tbl = cparms.mem_va; - - ctxt->shadow_ctxt.num_entries = num_entries; - ctxt->shadow_ctxt.base_addr = base_addr; - - return 0; -error: - tf_shadow_tbl_ctxt_delete(ctxt); - - return -ENOMEM; -} - -/** - * Get a shadow table context given the db and the table type - */ -static struct tf_shadow_tbl_ctxt * -tf_shadow_tbl_ctxt_get(struct tf_shadow_tbl_db *shadow_db, - enum tf_tbl_type type) -{ - if (type >= TF_TBL_TYPE_MAX || - !shadow_db || - !shadow_db->ctxt[type]) - return NULL; - - return shadow_db->ctxt[type]; -} - -/** - * Sets the hash entry into the table given the table context, hash bucket - * handle, and shadow index. - */ -static inline int -tf_shadow_tbl_set_hash_entry(struct tf_shadow_tbl_ctxt *ctxt, - uint32_t hb_handle, - uint16_t sh_idx) -{ - uint16_t hid = TF_SHADOW_HB_HANDLE_HASH_GET(ctxt, hb_handle); - uint16_t be = TF_SHADOW_HB_HANDLE_BE_GET(hb_handle); - uint64_t entry = sh_idx | TF_SHADOW_BE_VALID; - - if (hid >= ctxt->hash_ctxt.hash_entries) - return -EINVAL; - - ctxt->hash_ctxt.hashtbl[hid] |= entry << (be * 16); - return 0; -} - -/** - * Clears the hash entry given the TBL context and hash bucket handle. - */ -static inline void -tf_shadow_tbl_clear_hash_entry(struct tf_shadow_tbl_ctxt *ctxt, - uint32_t hb_handle) -{ - uint16_t hid, be; - uint64_t *bucket; - - if (!TF_SHADOW_HB_HANDLE_IS_VALID(hb_handle)) - return; - - hid = TF_SHADOW_HB_HANDLE_HASH_GET(ctxt, hb_handle); - be = TF_SHADOW_HB_HANDLE_BE_GET(hb_handle); - bucket = &ctxt->hash_ctxt.hashtbl[hid]; - - switch (be) { - case 0: - *bucket = TF_SHADOW_BE0_MASK_CLEAR(*bucket); - break; - case 1: - *bucket = TF_SHADOW_BE1_MASK_CLEAR(*bucket); - break; - case 2: - *bucket = TF_SHADOW_BE2_MASK_CLEAR(*bucket); - break; - case 3: - *bucket = TF_SHADOW_BE2_MASK_CLEAR(*bucket); - break; - default: - /* - * Since the BE_GET masks non-inclusive bits, this will not - * happen. - */ - break; - } -} - -/** - * Clears the shadow key and result entries given the table context and - * shadow index. - */ -static void -tf_shadow_tbl_clear_sh_entry(struct tf_shadow_tbl_ctxt *ctxt, - uint16_t sh_idx) -{ - struct tf_shadow_tbl_shadow_key_entry *sk_entry; - struct tf_shadow_tbl_shadow_result_entry *sr_entry; - - if (sh_idx >= tf_shadow_tbl_sh_num_entries_get(ctxt)) - return; - - sk_entry = &ctxt->shadow_ctxt.sh_key_tbl[sh_idx]; - sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[sh_idx]; - - /* - * memset key/result to zero for now, possibly leave the data alone - * in the future and rely on the valid bit in the hash table. - */ - memset(sk_entry, 0, sizeof(struct tf_shadow_tbl_shadow_key_entry)); - memset(sr_entry, 0, sizeof(struct tf_shadow_tbl_shadow_result_entry)); -} - -/** - * Binds the allocated tbl index with the hash and shadow tables. - * The entry will be incomplete until the set has happened with the result - * data. - */ -int -tf_shadow_tbl_bind_index(struct tf_shadow_tbl_bind_index_parms *parms) -{ - int rc; - uint16_t idx, len; - struct tf_shadow_tbl_ctxt *ctxt; - struct tf_shadow_tbl_db *shadow_db; - struct tf_shadow_tbl_shadow_key_entry *sk_entry; - struct tf_shadow_tbl_shadow_result_entry *sr_entry; - - if (!parms || !TF_SHADOW_HB_HANDLE_IS_VALID(parms->hb_handle) || - !parms->data) { - TFP_DRV_LOG(ERR, "Invalid parms\n"); - return -EINVAL; - } - - shadow_db = (struct tf_shadow_tbl_db *)parms->shadow_db; - ctxt = tf_shadow_tbl_ctxt_get(shadow_db, parms->type); - if (!ctxt) { - TFP_DRV_LOG(DEBUG, "%s no ctxt for table\n", - tf_tbl_type_2_str(parms->type)); - return -EINVAL; - } - - idx = TF_SHADOW_IDX_TO_SHIDX(ctxt, parms->idx); - len = parms->data_sz_in_bytes; - if (idx >= tf_shadow_tbl_sh_num_entries_get(ctxt) || - len > TF_SHADOW_MAX_KEY_SZ) { - TFP_DRV_LOG(ERR, "%s:%s Invalid len (%d) > %d || oob idx %d\n", - tf_dir_2_str(parms->dir), - tf_tbl_type_2_str(parms->type), - len, - TF_SHADOW_MAX_KEY_SZ, idx); - - return -EINVAL; - } - - rc = tf_shadow_tbl_set_hash_entry(ctxt, parms->hb_handle, idx); - if (rc) - return -EINVAL; - - sk_entry = &ctxt->shadow_ctxt.sh_key_tbl[idx]; - sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx]; - - /* For tables, the data is the key */ - memcpy(sk_entry->key, parms->data, len); - - /* Write the result table */ - sr_entry->key_size = len; - sr_entry->hb_handle = parms->hb_handle; - sr_entry->refcnt = 1; - - return 0; -} - -/** - * Deletes hash/shadow information if no more references. - * - * Returns 0 - The caller should delete the table entry in hardware. - * Returns non-zero - The number of references to the entry - */ -int -tf_shadow_tbl_remove(struct tf_shadow_tbl_remove_parms *parms) -{ - uint16_t idx; - uint32_t hb_handle; - struct tf_shadow_tbl_ctxt *ctxt; - struct tf_shadow_tbl_db *shadow_db; - struct tf_tbl_free_parms *fparms; - struct tf_shadow_tbl_shadow_result_entry *sr_entry; - - if (!parms || !parms->fparms) { - TFP_DRV_LOG(ERR, "Invalid parms\n"); - return -EINVAL; - } - - fparms = parms->fparms; - if (!tf_shadow_tbl_is_searchable(fparms->type)) - return 0; - /* - * Initialize the ref count to zero. The default would be to remove - * the entry. - */ - fparms->ref_cnt = 0; - - shadow_db = (struct tf_shadow_tbl_db *)parms->shadow_db; - ctxt = tf_shadow_tbl_ctxt_get(shadow_db, fparms->type); - if (!ctxt) { - TFP_DRV_LOG(DEBUG, "%s no ctxt for table\n", - tf_tbl_type_2_str(fparms->type)); - return 0; - } - - idx = TF_SHADOW_IDX_TO_SHIDX(ctxt, fparms->idx); - if (idx >= tf_shadow_tbl_sh_num_entries_get(ctxt)) { - TFP_DRV_LOG(DEBUG, "%s %d >= %d\n", - tf_tbl_type_2_str(fparms->type), - fparms->idx, - tf_shadow_tbl_sh_num_entries_get(ctxt)); - return 0; - } - - sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx]; - if (sr_entry->refcnt <= 1) { - hb_handle = sr_entry->hb_handle; - tf_shadow_tbl_clear_hash_entry(ctxt, hb_handle); - tf_shadow_tbl_clear_sh_entry(ctxt, idx); - } else { - sr_entry->refcnt--; - fparms->ref_cnt = sr_entry->refcnt; - } - - return 0; -} - -int -tf_shadow_tbl_search(struct tf_shadow_tbl_search_parms *parms) -{ - uint16_t len; - uint64_t bucket; - uint32_t i, hid32; - struct tf_shadow_tbl_ctxt *ctxt; - struct tf_shadow_tbl_db *shadow_db; - uint16_t hid16, hb_idx, hid_mask, shtbl_idx, shtbl_key, be_valid; - struct tf_tbl_alloc_search_parms *sparms; - uint32_t be_avail = TF_SHADOW_HB_NUM_ELEM; - - if (!parms || !parms->sparms) { - TFP_DRV_LOG(ERR, "tbl search with invalid parms\n"); - return -EINVAL; - } - - sparms = parms->sparms; - /* Check that caller was supposed to call search */ - if (!tf_shadow_tbl_is_searchable(sparms->type)) - return -EINVAL; - - /* Initialize return values to invalid */ - sparms->hit = 0; - sparms->search_status = REJECT; - parms->hb_handle = 0; - sparms->ref_cnt = 0; - - shadow_db = (struct tf_shadow_tbl_db *)parms->shadow_db; - ctxt = tf_shadow_tbl_ctxt_get(shadow_db, sparms->type); - if (!ctxt) { - TFP_DRV_LOG(ERR, "%s Unable to get tbl mgr context\n", - tf_tbl_type_2_str(sparms->type)); - return -EINVAL; - } - - len = sparms->result_sz_in_bytes; - if (len > TF_SHADOW_MAX_KEY_SZ || !sparms->result || !len) { - TFP_DRV_LOG(ERR, "%s:%s Invalid parms %d : %p\n", - tf_dir_2_str(sparms->dir), - tf_tbl_type_2_str(sparms->type), - len, - sparms->result); - return -EINVAL; - } - - /* - * Calculate the crc32 - * Fold it to create a 16b value - * Reduce it to fit the table - */ - hid32 = tf_hash_calc_crc32(sparms->result, len); - hid16 = (uint16_t)(((hid32 >> 16) & 0xffff) ^ (hid32 & 0xffff)); - hid_mask = ctxt->hash_ctxt.hid_mask; - hb_idx = hid16 & hid_mask; - - bucket = ctxt->hash_ctxt.hashtbl[hb_idx]; - if (!bucket) { - /* empty bucket means a miss and available entry */ - sparms->search_status = MISS; - parms->hb_handle = TF_SHADOW_HB_HANDLE_CREATE(hb_idx, 0); - sparms->idx = 0; - return 0; - } - - /* Set the avail to max so we can detect when there is an avail entry */ - be_avail = TF_SHADOW_HB_NUM_ELEM; - for (i = 0; i < TF_SHADOW_HB_NUM_ELEM; i++) { - shtbl_idx = (uint16_t)((bucket >> (i * 16)) & 0xffff); - be_valid = TF_SHADOW_BE_IS_VALID(shtbl_idx); - if (!be_valid) { - /* The element is avail, keep going */ - be_avail = i; - continue; - } - /* There is a valid entry, compare it */ - shtbl_key = shtbl_idx & ~TF_SHADOW_BE_VALID; - if (!tf_shadow_tbl_key_cmp(ctxt, - sparms->result, - shtbl_key, - len)) { - /* - * It matches, increment the ref count if the caller - * requested allocation and return the info - */ - if (sparms->alloc) - ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt = - ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt + 1; - - sparms->hit = 1; - sparms->search_status = HIT; - parms->hb_handle = - TF_SHADOW_HB_HANDLE_CREATE(hb_idx, i); - sparms->idx = TF_SHADOW_SHIDX_TO_IDX(ctxt, shtbl_key); - sparms->ref_cnt = - ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt; - - return 0; - } - } - - /* No hits, return avail entry if exists */ - if (be_avail < TF_SHADOW_HB_NUM_ELEM) { - /* - * There is an available hash entry, so return MISS and the - * hash handle for the subsequent bind. - */ - parms->hb_handle = TF_SHADOW_HB_HANDLE_CREATE(hb_idx, be_avail); - sparms->search_status = MISS; - sparms->hit = 0; - sparms->idx = 0; - } else { - /* No room for the entry in the hash table, must REJECT */ - sparms->search_status = REJECT; - } - - return 0; -} - -int -tf_shadow_tbl_insert(struct tf_shadow_tbl_insert_parms *parms) -{ - uint16_t idx; - struct tf_shadow_tbl_ctxt *ctxt; - struct tf_tbl_set_parms *sparms; - struct tf_shadow_tbl_db *shadow_db; - struct tf_shadow_tbl_shadow_result_entry *sr_entry; - - if (!parms || !parms->sparms) { - TFP_DRV_LOG(ERR, "Null parms\n"); - return -EINVAL; - } - - sparms = parms->sparms; - if (!sparms->data || !sparms->data_sz_in_bytes) { - TFP_DRV_LOG(ERR, "%s:%s No result to set.\n", - tf_dir_2_str(sparms->dir), - tf_tbl_type_2_str(sparms->type)); - return -EINVAL; - } - - shadow_db = (struct tf_shadow_tbl_db *)parms->shadow_db; - ctxt = tf_shadow_tbl_ctxt_get(shadow_db, sparms->type); - if (!ctxt) { - /* We aren't tracking this table, so return success */ - TFP_DRV_LOG(DEBUG, "%s Unable to get tbl mgr context\n", - tf_tbl_type_2_str(sparms->type)); - return 0; - } - - idx = TF_SHADOW_IDX_TO_SHIDX(ctxt, sparms->idx); - if (idx >= tf_shadow_tbl_sh_num_entries_get(ctxt)) { - TFP_DRV_LOG(ERR, "%s:%s Invalid idx(0x%x)\n", - tf_dir_2_str(sparms->dir), - tf_tbl_type_2_str(sparms->type), - sparms->idx); - return -EINVAL; - } - - /* Write the result table, the key/hash has been written already */ - sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx]; - - /* - * If the handle is not valid, the bind was never called. We aren't - * tracking this entry. - */ - if (!TF_SHADOW_HB_HANDLE_IS_VALID(sr_entry->hb_handle)) - return 0; - - return 0; -} - -int -tf_shadow_tbl_free_db(struct tf_shadow_tbl_free_db_parms *parms) -{ - struct tf_shadow_tbl_db *shadow_db; - int i; - - TF_CHECK_PARMS1(parms); - - shadow_db = (struct tf_shadow_tbl_db *)parms->shadow_db; - if (!shadow_db) { - TFP_DRV_LOG(DEBUG, "Shadow db is NULL cannot be freed\n"); - return -EINVAL; - } - - for (i = 0; i < TF_TBL_TYPE_MAX; i++) { - if (shadow_db->ctxt[i]) { - tf_shadow_tbl_ctxt_delete(shadow_db->ctxt[i]); - tfp_free(shadow_db->ctxt[i]); - } - } - - tfp_free(shadow_db); - - return 0; -} - -/** - * Allocate the table resources for search and allocate - * - */ -int tf_shadow_tbl_create_db(struct tf_shadow_tbl_create_db_parms *parms) -{ - int rc; - int i; - uint16_t base; - struct tfp_calloc_parms cparms; - struct tf_shadow_tbl_db *shadow_db = NULL; - - TF_CHECK_PARMS1(parms); - - /* Build the shadow DB per the request */ - cparms.nitems = 1; - cparms.size = sizeof(struct tf_shadow_tbl_db); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - return rc; - shadow_db = (void *)cparms.mem_va; - - for (i = 0; i < TF_TBL_TYPE_MAX; i++) { - /* If the element didn't request an allocation no need - * to create a pool nor verify if we got a reservation. - */ - if (!parms->cfg->alloc_cnt[i] || - !tf_shadow_tbl_is_searchable(i)) { - shadow_db->ctxt[i] = NULL; - continue; - } - - cparms.nitems = 1; - cparms.size = sizeof(struct tf_shadow_tbl_ctxt); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - goto error; - - shadow_db->ctxt[i] = cparms.mem_va; - base = parms->cfg->base_addr[i]; - rc = tf_shadow_tbl_ctxt_create(shadow_db->ctxt[i], - parms->cfg->alloc_cnt[i], - base); - if (rc) - goto error; - } - - *parms->shadow_db = (void *)shadow_db; - - TFP_DRV_LOG(INFO, - "TF SHADOW TABLE - initialized\n"); - - return 0; -error: - for (i = 0; i < TF_TBL_TYPE_MAX; i++) { - if (shadow_db->ctxt[i]) { - tf_shadow_tbl_ctxt_delete(shadow_db->ctxt[i]); - tfp_free(shadow_db->ctxt[i]); - } - } - - tfp_free(shadow_db); - - return -ENOMEM; -} diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tbl.h b/drivers/net/bnxt/tf_core/tf_shadow_tbl.h deleted file mode 100644 index 354240efce..0000000000 --- a/drivers/net/bnxt/tf_core/tf_shadow_tbl.h +++ /dev/null @@ -1,256 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ - -#ifndef _TF_SHADOW_TBL_H_ -#define _TF_SHADOW_TBL_H_ - -#include "tf_core.h" - -/** - * The Shadow Table module provides shadow DB handling for table based - * TF types. A shadow DB provides the capability that allows for reuse - * of TF resources. - * - * A Shadow table DB is intended to be used by the Table Type module - * only. - */ - -/** - * Shadow DB configuration information for a single table type. - * - * During Device initialization the HCAPI device specifics are learned - * and as well as the RM DB creation. From that those initial steps - * this structure can be populated. - * - * NOTE: - * If used in an array of table types then such array must be ordered - * by the TF type is represents. - */ -struct tf_shadow_tbl_cfg_parms { - /** - * [in] The number of elements in the alloc_cnt and base_addr - * For now, it should always be equal to TF_TBL_TYPE_MAX - */ - int num_entries; - - /** - * [in] Resource allocation count array - * This array content originates from the tf_session_resources - * that is passed in on session open - * Array size is TF_TBL_TYPE_MAX - */ - uint16_t *alloc_cnt; - /** - * [in] The base index for each table - */ - uint16_t base_addr[TF_TBL_TYPE_MAX]; -}; - -/** - * Shadow table DB creation parameters - */ -struct tf_shadow_tbl_create_db_parms { - /** - * [in] Receive or transmit direction - */ - enum tf_dir dir; - /** - * [in] Configuration information for the shadow db - */ - struct tf_shadow_tbl_cfg_parms *cfg; - /** - * [out] Shadow table DB handle - */ - void **shadow_db; -}; - -/** - * Shadow table DB free parameters - */ -struct tf_shadow_tbl_free_db_parms { - /** - * [in] Shadow table DB handle - */ - void *shadow_db; -}; - -/** - * Shadow table search parameters - */ -struct tf_shadow_tbl_search_parms { - /** - * [in] Shadow table DB handle - */ - void *shadow_db; - /** - * [in,out] The search parms from tf core - */ - struct tf_tbl_alloc_search_parms *sparms; - /** - * [out] Reference count incremented if hit - */ - uint32_t hb_handle; -}; - -/** - * Shadow Table bind index parameters - */ -struct tf_shadow_tbl_bind_index_parms { - /** - * [in] Shadow tcam DB handle - */ - void *shadow_db; - /** - * [in] receive or transmit direction - */ - enum tf_dir dir; - /** - * [in] TCAM table type - */ - enum tf_tbl_type type; - /** - * [in] index of the entry to program - */ - uint16_t idx; - /** - * [in] struct containing key - */ - uint8_t *data; - /** - * [in] data size in bytes - */ - uint16_t data_sz_in_bytes; - /** - * [in] The hash bucket handled returned from the search - */ - uint32_t hb_handle; -}; - -/** - * Shadow table insert parameters - */ -struct tf_shadow_tbl_insert_parms { - /** - * [in] Shadow table DB handle - */ - void *shadow_db; - /** - * [in] The insert parms from tf core - */ - struct tf_tbl_set_parms *sparms; -}; - -/** - * Shadow table remove parameters - */ -struct tf_shadow_tbl_remove_parms { - /** - * [in] Shadow table DB handle - */ - void *shadow_db; - /** - * [in] The free parms from tf core - */ - struct tf_tbl_free_parms *fparms; -}; - -/** - * @page shadow_tbl Shadow table DB - * - * @ref tf_shadow_tbl_create_db - * - * @ref tf_shadow_tbl_free_db - * - * @reg tf_shadow_tbl_search - * - * @reg tf_shadow_tbl_insert - * - * @reg tf_shadow_tbl_remove - */ - -/** - * Creates and fills a Shadow table DB. The DB is indexed per the - * parms structure. - * - * [in] parms - * Pointer to create db parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_shadow_tbl_create_db(struct tf_shadow_tbl_create_db_parms *parms); - -/** - * Closes the Shadow table DB and frees all allocated - * resources per the associated database. - * - * [in] parms - * Pointer to the free DB parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_shadow_tbl_free_db(struct tf_shadow_tbl_free_db_parms *parms); - -/** - * Search Shadow table db for matching result - * - * [in] parms - * Pointer to the search parameters - * - * Returns - * - (0) if successful, element was found. - * - (-EINVAL) on failure. - * - * If there is a miss, but there is room for insertion, the hb_handle returned - * is used for insertion during the bind index API - */ -int tf_shadow_tbl_search(struct tf_shadow_tbl_search_parms *parms); - -/** - * Bind Shadow table db hash and result tables with result from search/alloc - * - * [in] parms - * Pointer to the search parameters - * - * Returns - * - (0) if successful - * - (-EINVAL) on failure. - * - * This is only called after a MISS in the search returns a hb_handle - */ -int tf_shadow_tbl_bind_index(struct tf_shadow_tbl_bind_index_parms *parms); - -/** - * Inserts an element into the Shadow table DB. Will fail if the - * elements ref_count is different from 0. Ref_count after insert will - * be incremented. - * - * [in] parms - * Pointer to insert parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_shadow_tbl_insert(struct tf_shadow_tbl_insert_parms *parms); - -/** - * Removes an element from the Shadow table DB. Will fail if the - * elements ref_count is 0. Ref_count after removal will be - * decremented. - * - * [in] parms - * Pointer to remove parameter - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_shadow_tbl_remove(struct tf_shadow_tbl_remove_parms *parms); - -#endif /* _TF_SHADOW_TBL_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 67a43311cc..7d15c3c5d4 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -13,11 +13,9 @@ #include "tf_util.h" #include "tf_msg.h" #include "tfp.h" -#include "tf_shadow_tbl.h" #include "tf_session.h" #include "tf_device.h" - struct tf; /** @@ -44,13 +42,7 @@ int tf_tbl_bind(struct tf *tfp, struct tf_tbl_cfg_parms *parms) { - int rc, d, i; - struct tf_rm_alloc_info info; - struct tf_rm_free_db_parms fparms; - struct tf_shadow_tbl_free_db_parms fshadow; - struct tf_rm_get_alloc_info_parms ainfo; - struct tf_shadow_tbl_cfg_parms shadow_cfg; - struct tf_shadow_tbl_create_db_parms shadow_cdb; + int rc, d; struct tf_rm_create_db_parms db_cfg = { 0 }; TF_CHECK_PARMS2(tfp, parms); @@ -62,7 +54,7 @@ tf_tbl_bind(struct tf *tfp, } db_cfg.num_elements = parms->num_elements; - db_cfg.type = TF_DEVICE_MODULE_TYPE_TABLE; + db_cfg.module = TF_MODULE_TYPE_TABLE; db_cfg.num_elements = parms->num_elements; db_cfg.cfg = parms->cfg; @@ -80,72 +72,12 @@ tf_tbl_bind(struct tf *tfp, } } - /* Initialize the Shadow Table. */ - if (parms->shadow_copy) { - for (d = 0; d < TF_DIR_MAX; d++) { - memset(&shadow_cfg, 0, sizeof(shadow_cfg)); - memset(&shadow_cdb, 0, sizeof(shadow_cdb)); - /* Get the base addresses of the tables */ - for (i = 0; i < TF_TBL_TYPE_MAX; i++) { - memset(&info, 0, sizeof(info)); - - if (!parms->resources->tbl_cnt[d].cnt[i]) - continue; - ainfo.rm_db = tbl_db[d]; - ainfo.db_index = i; - ainfo.info = &info; - rc = tf_rm_get_info(&ainfo); - if (rc) - goto error; - - shadow_cfg.base_addr[i] = info.entry.start; - } - - /* Create the shadow db */ - shadow_cfg.alloc_cnt = - parms->resources->tbl_cnt[d].cnt; - shadow_cfg.num_entries = parms->num_elements; - - shadow_cdb.shadow_db = &shadow_tbl_db[d]; - shadow_cdb.cfg = &shadow_cfg; - rc = tf_shadow_tbl_create_db(&shadow_cdb); - if (rc) { - TFP_DRV_LOG(ERR, - "Shadow TBL DB creation failed " - "rc=%d\n", rc); - goto error; - } - } - shadow_init = 1; - } - init = 1; TFP_DRV_LOG(INFO, "Table Type - initialized\n"); return 0; -error: - for (d = 0; d < TF_DIR_MAX; d++) { - memset(&fparms, 0, sizeof(fparms)); - fparms.dir = d; - fparms.rm_db = tbl_db[d]; - /* Ignoring return here since we are in the error case */ - (void)tf_rm_free_db(tfp, &fparms); - - if (parms->shadow_copy) { - fshadow.shadow_db = shadow_tbl_db[d]; - tf_shadow_tbl_free_db(&fshadow); - shadow_tbl_db[d] = NULL; - } - - tbl_db[d] = NULL; - } - - shadow_init = 0; - init = 0; - - return rc; } int @@ -154,8 +86,6 @@ tf_tbl_unbind(struct tf *tfp) int rc; int i; struct tf_rm_free_db_parms fparms = { 0 }; - struct tf_shadow_tbl_free_db_parms fshadow; - TF_CHECK_PARMS1(tfp); /* Bail if nothing has been initialized */ @@ -173,13 +103,6 @@ tf_tbl_unbind(struct tf *tfp) return rc; tbl_db[i] = NULL; - - if (shadow_init) { - memset(&fshadow, 0, sizeof(fshadow)); - fshadow.shadow_db = shadow_tbl_db[i]; - tf_shadow_tbl_free_db(&fshadow); - shadow_tbl_db[i] = NULL; - } } init = 0; @@ -207,7 +130,7 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, /* Allocate requested element */ aparms.rm_db = tbl_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = &idx; rc = tf_rm_allocate(&aparms); if (rc) { @@ -230,7 +153,6 @@ tf_tbl_free(struct tf *tfp __rte_unused, int rc; struct tf_rm_is_allocated_parms aparms = { 0 }; struct tf_rm_free_parms fparms = { 0 }; - struct tf_shadow_tbl_remove_parms shparms; int allocated = 0; TF_CHECK_PARMS2(tfp, parms); @@ -244,7 +166,7 @@ tf_tbl_free(struct tf *tfp __rte_unused, /* Check if element is in use */ aparms.rm_db = tbl_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = parms->idx; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); @@ -259,40 +181,9 @@ tf_tbl_free(struct tf *tfp __rte_unused, parms->idx); return -EINVAL; } - - /* - * The Shadow mgmt, if enabled, determines if the entry needs - * to be deleted. - */ - if (shadow_init) { - memset(&shparms, 0, sizeof(shparms)); - shparms.shadow_db = shadow_tbl_db[parms->dir]; - shparms.fparms = parms; - rc = tf_shadow_tbl_remove(&shparms); - if (rc) { - /* - * Should not get here, log it and let the entry be - * deleted. - */ - TFP_DRV_LOG(ERR, "%s: Shadow free fail, " - "type:%d index:%d deleting the entry.\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - } else { - /* - * If the entry still has references, just return the - * ref count to the caller. No need to remove entry - * from rm. - */ - if (parms->ref_cnt >= 1) - return rc; - } - } - /* Free requested element */ fparms.rm_db = tbl_db[parms->dir]; - fparms.db_index = parms->type; + fparms.subtype = parms->type; fparms.index = parms->idx; rc = tf_rm_free(&fparms); if (rc) { @@ -311,15 +202,7 @@ int tf_tbl_alloc_search(struct tf *tfp, struct tf_tbl_alloc_search_parms *parms) { - int rc, frc; - uint32_t idx; - struct tf_session *tfs; - struct tf_dev_info *dev; - struct tf_tbl_alloc_parms aparms; - struct tf_shadow_tbl_search_parms sparms; - struct tf_shadow_tbl_bind_index_parms bparms; - struct tf_tbl_free_parms fparms; - + int rc = 0; TF_CHECK_PARMS2(tfp, parms); if (!shadow_init || !shadow_tbl_db[parms->dir]) { @@ -328,103 +211,6 @@ tf_tbl_alloc_search(struct tf *tfp, return -EINVAL; } - memset(&sparms, 0, sizeof(sparms)); - sparms.sparms = parms; - sparms.shadow_db = shadow_tbl_db[parms->dir]; - rc = tf_shadow_tbl_search(&sparms); - if (rc) - return rc; - - /* - * The app didn't request us to alloc the entry, so return now. - * The hit should have been updated in the original search parm. - */ - if (!parms->alloc || parms->search_status != MISS) - return rc; - - /* Retrieve the session information */ - rc = tf_session_get_session(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup session, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup device, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - /* Allocate the index */ - if (dev->ops->tf_dev_alloc_tbl == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return -EOPNOTSUPP; - } - - memset(&aparms, 0, sizeof(aparms)); - aparms.dir = parms->dir; - aparms.type = parms->type; - aparms.tbl_scope_id = parms->tbl_scope_id; - aparms.idx = &idx; - rc = dev->ops->tf_dev_alloc_tbl(tfp, &aparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Table allocation failed, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - /* Bind the allocated index to the data */ - memset(&bparms, 0, sizeof(bparms)); - bparms.shadow_db = shadow_tbl_db[parms->dir]; - bparms.dir = parms->dir; - bparms.type = parms->type; - bparms.idx = idx; - bparms.data = parms->result; - bparms.data_sz_in_bytes = parms->result_sz_in_bytes; - bparms.hb_handle = sparms.hb_handle; - rc = tf_shadow_tbl_bind_index(&bparms); - if (rc) { - /* Error binding entry, need to free the allocated idx */ - if (dev->ops->tf_dev_free_tbl == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - memset(&fparms, 0, sizeof(fparms)); - fparms.dir = parms->dir; - fparms.type = parms->type; - fparms.idx = idx; - frc = dev->ops->tf_dev_free_tbl(tfp, &fparms); - if (frc) { - TFP_DRV_LOG(ERR, - "%s: Failed free index allocated during " - "search. rc=%s\n", - tf_dir_2_str(parms->dir), - strerror(-frc)); - /* return the original failure. */ - return rc; - } - } - - parms->idx = idx; - return rc; } @@ -449,7 +235,7 @@ tf_tbl_set(struct tf *tfp, /* Verify that the entry has been previously allocated */ aparms.rm_db = tbl_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = parms->idx; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); @@ -467,7 +253,7 @@ tf_tbl_set(struct tf *tfp, /* Set the entry */ hparms.rm_db = tbl_db[parms->dir]; - hparms.db_index = parms->type; + hparms.subtype = parms->type; hparms.hcapi_type = &hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); if (rc) { @@ -518,7 +304,7 @@ tf_tbl_get(struct tf *tfp, /* Verify that the entry has been previously allocated */ aparms.rm_db = tbl_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = parms->idx; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); @@ -536,7 +322,7 @@ tf_tbl_get(struct tf *tfp, /* Set the entry */ hparms.rm_db = tbl_db[parms->dir]; - hparms.db_index = parms->type; + hparms.subtype = parms->type; hparms.hcapi_type = &hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); if (rc) { @@ -588,7 +374,7 @@ tf_tbl_bulk_get(struct tf *tfp, /* Verify that the entries are in the range of reserved resources. */ cparms.rm_db = tbl_db[parms->dir]; - cparms.db_index = parms->type; + cparms.subtype = parms->type; cparms.starting_index = parms->starting_idx; cparms.num_entries = parms->num_entries; @@ -605,7 +391,7 @@ tf_tbl_bulk_get(struct tf *tfp, } hparms.rm_db = tbl_db[parms->dir]; - hparms.db_index = parms->type; + hparms.subtype = parms->type; hparms.hcapi_type = &hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index a18d0e1e19..42d503f500 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -71,7 +71,7 @@ tf_tcam_bind(struct tf *tfp, memset(&db_cfg, 0, sizeof(db_cfg)); - db_cfg.type = TF_DEVICE_MODULE_TYPE_TCAM; + db_cfg.module = TF_MODULE_TYPE_TCAM; db_cfg.num_elements = parms->num_elements; db_cfg.cfg = parms->cfg; @@ -100,7 +100,7 @@ tf_tcam_bind(struct tf *tfp, if (!parms->resources->tcam_cnt[d].cnt[i]) continue; ainfo.rm_db = tcam_db[d]; - ainfo.db_index = i; + ainfo.subtype = i; ainfo.info = &info; rc = tf_rm_get_info(&ainfo); if (rc) @@ -248,7 +248,7 @@ tf_tcam_alloc(struct tf *tfp, memset(&aparms, 0, sizeof(aparms)); aparms.rm_db = tcam_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.priority = parms->priority; aparms.index = (uint32_t *)&parms->idx; rc = tf_rm_allocate(&aparms); @@ -331,7 +331,7 @@ tf_tcam_free(struct tf *tfp, memset(&aparms, 0, sizeof(aparms)); aparms.rm_db = tcam_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = parms->idx / num_slice_per_row; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); @@ -379,7 +379,7 @@ tf_tcam_free(struct tf *tfp, /* Free requested element */ memset(&fparms, 0, sizeof(fparms)); fparms.rm_db = tcam_db[parms->dir]; - fparms.db_index = parms->type; + fparms.subtype = parms->type; fparms.index = parms->idx / num_slice_per_row; rc = tf_rm_free(&fparms); if (rc) { @@ -421,7 +421,7 @@ tf_tcam_free(struct tf *tfp, memset(&hparms, 0, sizeof(hparms)); hparms.rm_db = tcam_db[parms->dir]; - hparms.db_index = parms->type; + hparms.subtype = parms->type; hparms.hcapi_type = &parms->hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); @@ -625,7 +625,7 @@ tf_tcam_set(struct tf *tfp __rte_unused, memset(&aparms, 0, sizeof(aparms)); aparms.rm_db = tcam_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = parms->idx / num_slice_per_row; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); @@ -645,7 +645,7 @@ tf_tcam_set(struct tf *tfp __rte_unused, memset(&hparms, 0, sizeof(hparms)); hparms.rm_db = tcam_db[parms->dir]; - hparms.db_index = parms->type; + hparms.subtype = parms->type; hparms.hcapi_type = &parms->hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); @@ -736,7 +736,7 @@ tf_tcam_get(struct tf *tfp __rte_unused, memset(&aparms, 0, sizeof(aparms)); aparms.rm_db = tcam_db[parms->dir]; - aparms.db_index = parms->type; + aparms.subtype = parms->type; aparms.index = parms->idx / num_slice_per_row; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); @@ -756,7 +756,7 @@ tf_tcam_get(struct tf *tfp __rte_unused, memset(&hparms, 0, sizeof(hparms)); hparms.rm_db = tcam_db[parms->dir]; - hparms.db_index = parms->type; + hparms.subtype = parms->type; hparms.hcapi_type = &parms->hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index 74c8f26204..b4d47d5a8c 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -137,34 +137,34 @@ tf_em_tbl_type_2_str(enum tf_em_tbl_type em_type) } const char * -tf_device_module_type_subtype_2_str(enum tf_device_module_type dm_type, - uint16_t mod_type) +tf_module_subtype_2_str(enum tf_module_type module, + uint16_t subtype) { - switch (dm_type) { - case TF_DEVICE_MODULE_TYPE_IDENTIFIER: - return tf_ident_2_str(mod_type); - case TF_DEVICE_MODULE_TYPE_TABLE: - return tf_tbl_type_2_str(mod_type); - case TF_DEVICE_MODULE_TYPE_TCAM: - return tf_tcam_tbl_2_str(mod_type); - case TF_DEVICE_MODULE_TYPE_EM: - return tf_em_tbl_type_2_str(mod_type); + switch (module) { + case TF_MODULE_TYPE_IDENTIFIER: + return tf_ident_2_str(subtype); + case TF_MODULE_TYPE_TABLE: + return tf_tbl_type_2_str(subtype); + case TF_MODULE_TYPE_TCAM: + return tf_tcam_tbl_2_str(subtype); + case TF_MODULE_TYPE_EM: + return tf_em_tbl_type_2_str(subtype); default: - return "Invalid Device Module type"; + return "Invalid Module type"; } } const char * -tf_device_module_type_2_str(enum tf_device_module_type dm_type) +tf_module_2_str(enum tf_module_type module) { - switch (dm_type) { - case TF_DEVICE_MODULE_TYPE_IDENTIFIER: + switch (module) { + case TF_MODULE_TYPE_IDENTIFIER: return "Identifier"; - case TF_DEVICE_MODULE_TYPE_TABLE: + case TF_MODULE_TYPE_TABLE: return "Table"; - case TF_DEVICE_MODULE_TYPE_TCAM: + case TF_MODULE_TYPE_TCAM: return "TCAM"; - case TF_DEVICE_MODULE_TYPE_EM: + case TF_MODULE_TYPE_EM: return "EM"; default: return "Invalid Device Module type"; diff --git a/drivers/net/bnxt/tf_core/tf_util.h b/drivers/net/bnxt/tf_core/tf_util.h index 4225c756f6..1aa35b6b82 100644 --- a/drivers/net/bnxt/tf_core/tf_util.h +++ b/drivers/net/bnxt/tf_core/tf_util.h @@ -65,34 +65,30 @@ const char *tf_tbl_type_2_str(enum tf_tbl_type tbl_type); const char *tf_em_tbl_type_2_str(enum tf_em_tbl_type em_type); /** - * Helper function converting device module type and module type to + * Helper function converting module and submodule type to * text string. * - * [in] dm_type - * Device Module type + * [in] module + * Module type * - * [in] mod_type - * Module specific type + * [in] submodule + * Module specific subtype * * Returns: * Pointer to a char string holding the string for the EM type */ -const char *tf_device_module_type_subtype_2_str - (enum tf_device_module_type dm_type, - uint16_t mod_type); +const char *tf_module_subtype_2_str(enum tf_module_type module, + uint16_t subtype); /** - * Helper function converting device module type to text string + * Helper function converting module type to text string * - * [in] dm_type - * Device Module type - * - * [in] mod_type - * Module specific type + * [in] module + * Module type * * Returns: * Pointer to a char string holding the string for the EM type */ -const char *tf_device_module_type_2_str(enum tf_device_module_type dm_type); +const char *tf_module_2_str(enum tf_module_type module); #endif /* _TF_UTIL_H_ */ From patchwork Sun May 30 08:58:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93558 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1EB91A0524; Sun, 30 May 2021 11:01:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0685940E5A; Sun, 30 May 2021 11:00:45 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id A690941137 for ; Sun, 30 May 2021 11:00:41 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 11B7C7DC2; Sun, 30 May 2021 02:00:39 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 11B7C7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365241; bh=Mxc/WgjYPnx6GLR01eXzxvJo/bd7YYyVPFl6+2x7De0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mbm+swOdQBT3uIx33XzFSqpULkoi/yFAwTQVp2A1tfV+r7Cl7wiTvXfijDUueWfb0 QjoqTIMduXnRXDt2zioElIeieX6ZPbc6wdO5xhMJx9VpmfkxpH3hgAZzPcWWEs1rr7 gA6eOS4tKAby0yyYdsnUaV7tgBc03SM77LUxv31M= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:40 +0530 Message-Id: <20210530085929.29695-10-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 09/58] net/bnxt: add Thor WC TCAM support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding 1. Add set/get/free/alloc for WC TCAM 2. Rework the key size in slice management. 3. Add 3 FKB WC keys for WC TCAM set cli cmd 4. Add transform key function for WC TCAM FKB key 5. Add checking for key buffer length for get_tcam Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_core/tf_core.c | 2 + drivers/net/bnxt/tf_core/tf_core.h | 5 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 2 - drivers/net/bnxt/tf_core/tf_device_p58.c | 7 +- drivers/net/bnxt/tf_core/tf_device_p58.h | 3 + drivers/net/bnxt/tf_core/tf_msg.c | 31 ++-- drivers/net/bnxt/tf_core/tf_tcam.c | 192 ++++++++++++----------- 7 files changed, 132 insertions(+), 110 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index a3b6afbc88..573fa0b1ed 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -842,8 +842,10 @@ tf_get_tcam_entry(struct tf *tfp __rte_unused, gparms.type = parms->tcam_tbl_type; gparms.idx = parms->idx; gparms.key = parms->key; + gparms.key_size = dev->ops->tf_dev_word_align(parms->key_sz_in_bits); gparms.mask = parms->mask; gparms.result = parms->result; + gparms.result_size = TF_BITS2BYTES_WORD_ALIGN(parms->result_sz_in_bits); rc = dev->ops->tf_dev_get_tcam(tfp, &gparms); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 0cc3719a1b..fcba492dc5 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -1286,7 +1286,7 @@ struct tf_get_tcam_entry_parms { */ uint8_t *mask; /** - * [out] key size in bits + * [in/out] key size in bits */ uint16_t key_sz_in_bits; /** @@ -1294,7 +1294,7 @@ struct tf_get_tcam_entry_parms { */ uint8_t *result; /** - * [out] struct containing result size in bits + * [in/out] struct containing result size in bits */ uint16_t result_sz_in_bits; }; @@ -1961,6 +1961,7 @@ enum tf_tunnel_encap_offsets { enum tf_global_config_type { TF_TUNNEL_ENCAP, /**< Tunnel Encap Config(TECT) */ TF_ACTION_BLOCK, /**< Action Block Config(ABCR) */ + TF_COUNTER_CFG, /**< Counter Configuration (CNTRS_CTRL) */ TF_GLOBAL_CFG_TYPE_MAX }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index d0bede89e3..e5aaaac9a0 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -144,8 +144,6 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused, *num_slices_per_row = CFA_P4_WC_TCAM_SLICES_PER_ROW; if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE) return -ENOTSUP; - - *num_slices_per_row = 1; } else { /* for other type of tcam */ *num_slices_per_row = 1; } diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 50a8d82074..65e283ed11 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -123,15 +123,14 @@ tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused, uint16_t key_sz, uint16_t *num_slices_per_row) { -#define CFA_P58_WC_TCAM_SLICES_PER_ROW 2 -#define CFA_P58_WC_TCAM_SLICE_SIZE 12 +#define CFA_P58_WC_TCAM_SLICES_PER_ROW 1 +#define CFA_P58_WC_TCAM_SLICE_SIZE 24 if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { + /* only support single slice key size now */ *num_slices_per_row = CFA_P58_WC_TCAM_SLICES_PER_ROW; if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE) return -ENOTSUP; - - *num_slices_per_row = 1; } else { /* for other type of tcam */ *num_slices_per_row = 1; } diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index abd916985e..07f022769b 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -189,5 +189,8 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { [TF_ACTION_BLOCK] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, + [TF_COUNTER_CFG] = { + TF_GLOBAL_CFG_CFG_HCAPI, TF_COUNTER_CFG + }, }; #endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 1af5c6d11c..ec4c7890c3 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -39,19 +39,8 @@ * array size (define above) should be checked and compared. */ #define TF_MSG_SIZE_HWRM_TF_GLOBAL_CFG_SET 56 -static_assert(sizeof(struct hwrm_tf_global_cfg_set_input) == - TF_MSG_SIZE_HWRM_TF_GLOBAL_CFG_SET, - "HWRM message size changed: hwrm_tf_global_cfg_set_input"); - #define TF_MSG_SIZE_HWRM_TF_EM_INSERT 104 -static_assert(sizeof(struct hwrm_tf_em_insert_input) == - TF_MSG_SIZE_HWRM_TF_EM_INSERT, - "HWRM message size changed: hwrm_tf_em_insert_input"); - #define TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET 128 -static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) == - TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET, - "HWRM message size changed: hwrm_tf_tbl_type_set_input"); /** * This is the MAX data we can transport across regular HWRM @@ -630,6 +619,9 @@ tf_msg_insert_em_internal_entry(struct tf *tfp, struct tf_dev_info *dev; struct tf_session *tfs; + RTE_BUILD_BUG_ON(sizeof(struct hwrm_tf_em_insert_input) != + TF_MSG_SIZE_HWRM_TF_EM_INSERT); + /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) { @@ -1255,6 +1247,17 @@ tf_msg_tcam_entry_get(struct tf *tfp, if (mparms.tf_resp_code != 0) return tfp_le_to_cpu_32(mparms.tf_resp_code); + if (parms->key_size < resp.key_size || + parms->result_size < resp.result_size) { + rc = -EINVAL; + TFP_DRV_LOG(ERR, + "%s: Key buffer(%d) is smaller than the key(%d), rc:%s\n", + tf_dir_2_str(parms->dir), + parms->key_size, + resp.key_size, + strerror(-rc)); + return rc; + } parms->key_size = resp.key_size; parms->result_size = resp.result_size; tfp_memcpy(parms->key, resp.dev_data, resp.key_size); @@ -1320,6 +1323,9 @@ tf_msg_set_tbl_entry(struct tf *tfp, struct tf_dev_info *dev; struct tf_session *tfs; + RTE_BUILD_BUG_ON(sizeof(struct hwrm_tf_tbl_type_set_input) != + TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET); + /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) { @@ -1554,6 +1560,9 @@ tf_msg_set_global_cfg(struct tf *tfp, struct tf_dev_info *dev; struct tf_session *tfs; + RTE_BUILD_BUG_ON(sizeof(struct hwrm_tf_global_cfg_set_input) != + TF_MSG_SIZE_HWRM_TF_GLOBAL_CFG_SET); + /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 42d503f500..1b5c29815d 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -48,10 +48,13 @@ tf_tcam_bind(struct tf *tfp, struct tf_rm_free_db_parms fparms; struct tf_rm_create_db_parms db_cfg; struct tf_tcam_resources *tcam_cnt; - struct tf_shadow_tcam_free_db_parms fshadow; struct tf_rm_get_alloc_info_parms ainfo; + struct tf_shadow_tcam_free_db_parms fshadow; struct tf_shadow_tcam_cfg_parms shadow_cfg; struct tf_shadow_tcam_create_db_parms shadow_cdb; + uint16_t num_slices = 1; + struct tf_session *tfs; + struct tf_dev_info *dev; TF_CHECK_PARMS2(tfp, parms); @@ -61,11 +64,37 @@ tf_tcam_bind(struct tf *tfp, return -EINVAL; } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + if (dev->ops->tf_dev_get_tcam_slice_info == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "Operation not supported, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, + TF_TCAM_TBL_TYPE_WC_TCAM, + 0, + &num_slices); + if (rc) + return rc; + tcam_cnt = parms->resources->tcam_cnt; - if ((tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % 2) || - (tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % 2)) { + if ((tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % num_slices) || + (tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % num_slices)) { TFP_DRV_LOG(ERR, - "Number of WC TCAM entries cannot be odd num\n"); + "Requested num of WC TCAM entries has to be multiple %d\n", + num_slices); return -EINVAL; } @@ -88,6 +117,26 @@ tf_tcam_bind(struct tf *tfp, } } + /* check if reserved resource for WC is multiple of num_slices */ + for (d = 0; d < TF_DIR_MAX; d++) { + memset(&info, 0, sizeof(info)); + ainfo.rm_db = tcam_db[d]; + ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM; + ainfo.info = &info; + rc = tf_rm_get_info(&ainfo); + if (rc) + goto error; + + if (info.entry.start % num_slices != 0 || + info.entry.stride % num_slices != 0) { + TFP_DRV_LOG(ERR, + "%s: TCAM reserved resource is not multiple of %d\n", + tf_dir_2_str(d), + num_slices); + return -EINVAL; + } + } + /* Initialize the TCAM manager. */ if (parms->shadow_copy) { for (d = 0; d < TF_DIR_MAX; d++) { @@ -163,7 +212,6 @@ tf_tcam_unbind(struct tf *tfp) int i; struct tf_rm_free_db_parms fparms; struct tf_shadow_tcam_free_db_parms fshadow; - TF_CHECK_PARMS1(tfp); /* Bail if nothing has been initialized */ @@ -202,11 +250,12 @@ int tf_tcam_alloc(struct tf *tfp, struct tf_tcam_alloc_parms *parms) { - int rc; + int rc, i; struct tf_session *tfs; struct tf_dev_info *dev; struct tf_rm_allocate_parms aparms; - uint16_t num_slice_per_row = 1; + uint16_t num_slices = 1; + uint32_t index; TF_CHECK_PARMS2(tfp, parms); @@ -236,32 +285,24 @@ tf_tcam_alloc(struct tf *tfp, return rc; } - /* Need to retrieve row size etc */ + /* Need to retrieve number of slices based on the key_size */ rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, parms->type, parms->key_size, - &num_slice_per_row); + &num_slices); if (rc) return rc; - /* Allocate requested element */ - memset(&aparms, 0, sizeof(aparms)); - - aparms.rm_db = tcam_db[parms->dir]; - aparms.subtype = parms->type; - aparms.priority = parms->priority; - aparms.index = (uint32_t *)&parms->idx; - rc = tf_rm_allocate(&aparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed tcam, type:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - - if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM && - (parms->idx % 2) != 0) { + /* + * For WC TCAM, number of slices could be 4, 2, 1 based on + * the key_size. For other TCAM, it is always 1 + */ + for (i = 0; i < num_slices; i++) { + memset(&aparms, 0, sizeof(aparms)); + aparms.rm_db = tcam_db[parms->dir]; + aparms.subtype = parms->type; + aparms.priority = parms->priority; + aparms.index = &index; rc = tf_rm_allocate(&aparms); if (rc) { TFP_DRV_LOG(ERR, @@ -270,9 +311,11 @@ tf_tcam_alloc(struct tf *tfp, parms->type); return rc; } - } - parms->idx *= num_slice_per_row; + /* return the start index of each row */ + if (i == 0) + parms->idx = index; + } return 0; } @@ -287,9 +330,10 @@ tf_tcam_free(struct tf *tfp, struct tf_rm_is_allocated_parms aparms; struct tf_rm_free_parms fparms; struct tf_rm_get_hcapi_parms hparms; - uint16_t num_slice_per_row = 1; + uint16_t num_slices = 1; int allocated = 0; struct tf_shadow_tcam_remove_parms shparms; + int i; TF_CHECK_PARMS2(tfp, parms); @@ -323,16 +367,24 @@ tf_tcam_free(struct tf *tfp, rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, parms->type, 0, - &num_slice_per_row); + &num_slices); if (rc) return rc; + if (parms->idx % num_slices) { + TFP_DRV_LOG(ERR, + "%s: TCAM reserved resource is not multiple of %d\n", + tf_dir_2_str(parms->dir), + num_slices); + return -EINVAL; + } + /* Check if element is in use */ memset(&aparms, 0, sizeof(aparms)); aparms.rm_db = tcam_db[parms->dir]; aparms.subtype = parms->type; - aparms.index = parms->idx / num_slice_per_row; + aparms.index = parms->idx; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); if (rc) @@ -376,44 +428,20 @@ tf_tcam_free(struct tf *tfp, } } - /* Free requested element */ - memset(&fparms, 0, sizeof(fparms)); - fparms.rm_db = tcam_db[parms->dir]; - fparms.subtype = parms->type; - fparms.index = parms->idx / num_slice_per_row; - rc = tf_rm_free(&fparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Free failed, type:%d, index:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - return rc; - } - - if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM) { - int i; - - for (i = -1; i < 3; i += 3) { - aparms.index += i; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; - - if (allocated == TF_RM_ALLOCATED_ENTRY_IN_USE) { - /* Free requested element */ - fparms.index = aparms.index; - rc = tf_rm_free(&fparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Free failed, type:%d, " - "index:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - fparms.index); - return rc; - } - } + for (i = 0; i < num_slices; i++) { + /* Free requested element */ + memset(&fparms, 0, sizeof(fparms)); + fparms.rm_db = tcam_db[parms->dir]; + fparms.subtype = parms->type; + fparms.index = parms->idx + i; + rc = tf_rm_free(&fparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Free failed, type:%d, index:%d\n", + tf_dir_2_str(parms->dir), + parms->type, + parms->idx); + return rc; } } @@ -449,8 +477,8 @@ tf_tcam_alloc_search(struct tf *tfp, { struct tf_shadow_tcam_search_parms sparms; struct tf_shadow_tcam_bind_index_parms bparms; - struct tf_tcam_alloc_parms aparms; struct tf_tcam_free_parms fparms; + struct tf_tcam_alloc_parms aparms; uint16_t num_slice_per_row = 1; struct tf_session *tfs; struct tf_dev_info *dev; @@ -626,7 +654,7 @@ tf_tcam_set(struct tf *tfp __rte_unused, aparms.rm_db = tcam_db[parms->dir]; aparms.subtype = parms->type; - aparms.index = parms->idx / num_slice_per_row; + aparms.index = parms->idx; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); if (rc) @@ -693,7 +721,6 @@ tf_tcam_get(struct tf *tfp __rte_unused, struct tf_dev_info *dev; struct tf_rm_is_allocated_parms aparms; struct tf_rm_get_hcapi_parms hparms; - uint16_t num_slice_per_row = 1; int allocated = 0; TF_CHECK_PARMS2(tfp, parms); @@ -715,29 +742,12 @@ tf_tcam_get(struct tf *tfp __rte_unused, if (rc) return rc; - if (dev->ops->tf_dev_get_tcam_slice_info == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - /* Need to retrieve row size etc */ - rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, - parms->type, - parms->key_size, - &num_slice_per_row); - if (rc) - return rc; - /* Check if element is in use */ memset(&aparms, 0, sizeof(aparms)); aparms.rm_db = tcam_db[parms->dir]; aparms.subtype = parms->type; - aparms.index = parms->idx / num_slice_per_row; + aparms.index = parms->idx; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); if (rc) From patchwork Sun May 30 08:58:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93559 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2F759A0524; Sun, 30 May 2021 11:02:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1CEC441147; Sun, 30 May 2021 11:00:46 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 61C534113F for ; Sun, 30 May 2021 11:00:43 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id C11E77DAF; Sun, 30 May 2021 02:00:41 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com C11E77DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365243; bh=1JGgTkaH7EQPFI3hDpr7d9aFGvJWZIvciB02iz7293o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ca1W6hc5PrTAuW2MYtA7DbQhGQKUZ7QPCmSARvM1vy+O/OcgyiHKuhlstJ9osTOUO kUxvqbgBKBwbNVzEIlNqIa4HPmIcbhoEJ+sC/ktDLoU2iBiXhha6dsTcjWV7K9OJ7T CnCNGpZAvMVfps4W4YLzVW4iU/zA7+MJ5wDlKIzE= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:41 +0530 Message-Id: <20210530085929.29695-11-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 10/58] net/bnxt: add 64B SRAM record management with RM X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith HCAPI RM now manages 64B records instead of 8B. Truflow core RM will manage the same. The tf_tbl core APIs now return 8B pointer addresses. These can be used directly as SRAM pointers in Action Records. When communicating with the firmware 8B addresses will be used. Signed-off-by: Farah Smith Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_core/tf_device.h | 29 ++++- drivers/net/bnxt/tf_core/tf_device_p4.c | 2 + drivers/net/bnxt/tf_core/tf_device_p58.c | 71 ++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.h | 24 ++-- drivers/net/bnxt/tf_core/tf_rm.h | 2 +- drivers/net/bnxt/tf_core/tf_tbl.c | 158 ++++++++++++++++++++++- 6 files changed, 267 insertions(+), 19 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 2cbb42fe2a..a18d59660b 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -220,9 +220,36 @@ struct tf_dev_ops { */ int (*tf_dev_search_ident)(struct tf *tfp, struct tf_ident_search_parms *parms); + /** + * Get SRAM table information. + * + * Converts an internal RM allocated element offset to + * a user address and vice versa. + * + * [in] tfp + * Pointer to TF handle + * + * [in] type + * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD + * + * [in/out] base + * Pointer to the base address of the associated table type. + * + * [in/out] shift + * Pointer to any shift required for the associated table type. + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_tbl_info)(struct tf *tfp, + void *tbl_db, + enum tf_tbl_type type, + uint16_t *base, + uint16_t *shift); /** - * Allocation of a table type element. + * Allocation of an index table type element. * * This API allocates the specified table type element from a * device specific table type DB. The allocated element is diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index e5aaaac9a0..8274978bfe 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -206,6 +206,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_alloc_ident = NULL, .tf_dev_free_ident = NULL, .tf_dev_search_ident = NULL, + .tf_dev_get_tbl_info = NULL, .tf_dev_alloc_ext_tbl = NULL, .tf_dev_alloc_tbl = NULL, .tf_dev_free_ext_tbl = NULL, @@ -246,6 +247,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_alloc_ident = tf_ident_alloc, .tf_dev_free_ident = tf_ident_free, .tf_dev_search_ident = tf_ident_search, + .tf_dev_get_tbl_info = NULL, .tf_dev_alloc_tbl = tf_tbl_alloc, .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, .tf_dev_free_tbl = tf_tbl_free, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 65e283ed11..b61c58e41b 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -148,6 +148,75 @@ static int tf_dev_p58_word_align(uint16_t size) return ((((size) + 63) >> 6) * 8); } + +#define TF_DEV_P58_BANK_SZ_64B 2048 +/** + * Get SRAM table information. + * + * Converts an internal RM allocated element offset to + * a user address and vice versa. + * + * [in] tfp + * Pointer to TF handle + * + * [in] type + * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD + * + * [in/out] base + * Pointer to the Base address of the associated SRAM bank used for + * the type of record allocated. + * + * [in/out] shift + * Pointer to the factor to be used as a multiplier to translate + * between the RM units to the user address. SRAM manages 64B entries + * Addresses must be shifted to an 8B address. + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, + void *db, + enum tf_tbl_type type, + uint16_t *base, + uint16_t *shift) +{ + uint16_t hcapi_type; + struct tf_rm_get_hcapi_parms parms; + int rc; + + parms.rm_db = db; + parms.subtype = type; + parms.hcapi_type = &hcapi_type; + + rc = tf_rm_get_hcapi_type(&parms); + if (rc) + return rc; + + switch (hcapi_type) { + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: + *base = 0; + *shift = 3; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1: + *base = TF_DEV_P58_BANK_SZ_64B; + *shift = 3; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2: + *base = TF_DEV_P58_BANK_SZ_64B * 2; + *shift = 3; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3: + *base = TF_DEV_P58_BANK_SZ_64B * 3; + *shift = 3; + break; + default: + *base = 0; + *shift = 0; + break; + } + return 0; +} /** * Truflow P58 device specific functions */ @@ -158,6 +227,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_alloc_ident = NULL, .tf_dev_free_ident = NULL, .tf_dev_search_ident = NULL, + .tf_dev_get_tbl_info = NULL, .tf_dev_alloc_ext_tbl = NULL, .tf_dev_alloc_tbl = NULL, .tf_dev_free_ext_tbl = NULL, @@ -198,6 +268,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_alloc_ident = tf_ident_alloc, .tf_dev_free_ident = tf_ident_free, .tf_dev_search_ident = tf_ident_search, + .tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info, .tf_dev_alloc_tbl = tf_tbl_alloc, .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, .tf_dev_free_tbl = tf_tbl_free, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 07f022769b..4d7a78e52c 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -68,35 +68,35 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { [TF_TBL_TYPE_FULL_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 4, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_COMPACT_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 8, + .slices = 1, .divider = 8, }, /* Policy - Encaps in bank 2 */ [TF_TBL_TYPE_ACT_ENCAP_8B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_ACT_ENCAP_16B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_ACT_ENCAP_32B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_ACT_ENCAP_64B] = { @@ -111,21 +111,21 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_ACT_MODIFY_16B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_ACT_MODIFY_32B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_ACT_MODIFY_64B] = { @@ -139,28 +139,28 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { [TF_TBL_TYPE_ACT_SP_SMAC] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 8, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 4, + .slices = 1, .divider = 8, }, [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 2, + .slices = 1, .divider = 8, }, /* Policy - Stats in bank 3 */ [TF_TBL_TYPE_ACT_STATS_64] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, - .slices = 8, + .slices = 1, .divider = 8, }, }; diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h index 407c7d5bf9..6eb6865dac 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.h +++ b/drivers/net/bnxt/tf_core/tf_rm.h @@ -138,6 +138,7 @@ struct tf_rm_element_cfg { * resource pool chunk size. */ uint8_t slices; + /** * Pool element divider count * If 0 or 1, there is 1:1 correspondence between the RM @@ -146,7 +147,6 @@ struct tf_rm_element_cfg { * correspondence to the HCAPI RM firmware resource. */ uint8_t divider; - }; /** diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 7d15c3c5d4..75dbe2066f 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -16,6 +16,14 @@ #include "tf_session.h" #include "tf_device.h" +#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \ + *(new_idx) = (((idx) + (base)) << (shift)); \ +} + +#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \ + *(new_idx) = (((idx) >> (shift)) - (base)); \ +} + struct tf; /** @@ -118,6 +126,9 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, int rc; uint32_t idx; struct tf_rm_allocate_parms aparms = { 0 }; + struct tf_session *tfs; + struct tf_dev_info *dev; + uint16_t base = 0, shift = 0; TF_CHECK_PARMS2(tfp, parms); @@ -128,6 +139,29 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, return -EINVAL; } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + /* Only get table info if required for the device */ + if (dev->ops->tf_dev_get_tbl_info) { + rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], + parms->type, &base, &shift); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%d\n", + tf_dir_2_str(parms->dir), + parms->type); + return rc; + } + } + /* Allocate requested element */ aparms.rm_db = tbl_db[parms->dir]; aparms.subtype = parms->type; @@ -141,6 +175,7 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, return rc; } + TF_TBL_RM_TO_PTR(&idx, idx, base, shift); *parms->idx = idx; return 0; @@ -154,6 +189,9 @@ tf_tbl_free(struct tf *tfp __rte_unused, struct tf_rm_is_allocated_parms aparms = { 0 }; struct tf_rm_free_parms fparms = { 0 }; int allocated = 0; + struct tf_session *tfs; + struct tf_dev_info *dev; + uint16_t base = 0, shift = 0; TF_CHECK_PARMS2(tfp, parms); @@ -163,11 +201,35 @@ tf_tbl_free(struct tf *tfp __rte_unused, tf_dir_2_str(parms->dir)); return -EINVAL; } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + /* Only get table info if required for the device */ + if (dev->ops->tf_dev_get_tbl_info) { + rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], + parms->type, &base, &shift); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%d\n", + tf_dir_2_str(parms->dir), + parms->type); + return rc; + } + } /* Check if element is in use */ aparms.rm_db = tbl_db[parms->dir]; aparms.subtype = parms->type; - aparms.index = parms->idx; + + TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); + aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); if (rc) @@ -184,7 +246,9 @@ tf_tbl_free(struct tf *tfp __rte_unused, /* Free requested element */ fparms.rm_db = tbl_db[parms->dir]; fparms.subtype = parms->type; - fparms.index = parms->idx; + + TF_TBL_PTR_TO_RM(&fparms.index, parms->idx, base, shift); + rc = tf_rm_free(&fparms); if (rc) { TFP_DRV_LOG(ERR, @@ -223,6 +287,9 @@ tf_tbl_set(struct tf *tfp, uint16_t hcapi_type; struct tf_rm_is_allocated_parms aparms = { 0 }; struct tf_rm_get_hcapi_parms hparms = { 0 }; + struct tf_session *tfs; + struct tf_dev_info *dev; + uint16_t base = 0, shift = 0; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -233,10 +300,34 @@ tf_tbl_set(struct tf *tfp, return -EINVAL; } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + /* Only get table info if required for the device */ + if (dev->ops->tf_dev_get_tbl_info) { + rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], + parms->type, &base, &shift); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%d\n", + tf_dir_2_str(parms->dir), + parms->type); + return rc; + } + } + /* Verify that the entry has been previously allocated */ aparms.rm_db = tbl_db[parms->dir]; aparms.subtype = parms->type; - aparms.index = parms->idx; + TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); + aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); if (rc) @@ -292,6 +383,9 @@ tf_tbl_get(struct tf *tfp, int allocated = 0; struct tf_rm_is_allocated_parms aparms = { 0 }; struct tf_rm_get_hcapi_parms hparms = { 0 }; + struct tf_session *tfs; + struct tf_dev_info *dev; + uint16_t base = 0, shift = 0; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -302,10 +396,35 @@ tf_tbl_get(struct tf *tfp, return -EINVAL; } + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + /* Only get table info if required for the device */ + if (dev->ops->tf_dev_get_tbl_info) { + rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], + parms->type, &base, &shift); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%d\n", + tf_dir_2_str(parms->dir), + parms->type); + return rc; + } + } + /* Verify that the entry has been previously allocated */ aparms.rm_db = tbl_db[parms->dir]; aparms.subtype = parms->type; - aparms.index = parms->idx; + TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); + aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); if (rc) @@ -361,6 +480,9 @@ tf_tbl_bulk_get(struct tf *tfp, uint16_t hcapi_type; struct tf_rm_get_hcapi_parms hparms = { 0 }; struct tf_rm_check_indexes_in_range_parms cparms = { 0 }; + struct tf_session *tfs; + struct tf_dev_info *dev; + uint16_t base = 0, shift = 0; TF_CHECK_PARMS2(tfp, parms); @@ -372,10 +494,36 @@ tf_tbl_bulk_get(struct tf *tfp, return -EINVAL; } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + /* Only get table info if required for the device */ + if (dev->ops->tf_dev_get_tbl_info) { + rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], + parms->type, &base, &shift); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%d\n", + tf_dir_2_str(parms->dir), + parms->type); + return rc; + } + } + /* Verify that the entries are in the range of reserved resources. */ cparms.rm_db = tbl_db[parms->dir]; cparms.subtype = parms->type; - cparms.starting_index = parms->starting_idx; + + TF_TBL_PTR_TO_RM(&cparms.starting_index, parms->starting_idx, + base, shift); + cparms.num_entries = parms->num_entries; rc = tf_rm_check_indexes_in_range(&cparms); From patchwork Sun May 30 08:58:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93560 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 71B47A0524; Sun, 30 May 2021 11:02:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA22E4114F; Sun, 30 May 2021 11:00:47 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 1C91D41141 for ; Sun, 30 May 2021 11:00:45 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 7BE1A7DC0; Sun, 30 May 2021 02:00:43 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 7BE1A7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365244; bh=poFGy9dl4blUDoP7iIICmABxLIuPpXMKqp6qV6UZQRQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KSQSNQsvPNPBX9o8+vzWHeDpcRuPoIX9o2lvlMZByB6qTefntYtsHVN3rFc+mFzSD O8iYvYHZly9cLmXSDM2T7+2cgXVqoVKMDmuFp+6s62DdzibuSzlJBvUkld3NWLh/8F xPUbUOdX1usKH9IdP6uXJ8yVbqtRGYaBqMqDKnS0= From: Venkat Duvvuru To: dev@dpdk.org Cc: Peter Spreadborough , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:42 +0530 Message-Id: <20210530085929.29695-12-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 11/58] net/bnxt: add hashing changes for Thor X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Peter Spreadborough - Move HCAPI hashing code to common file and add Thor support. - Change DPDK EM insert for FKB to use limited size Type 3 key. - Update FKB builder to be able to tell between EM and WC keys during transform. Signed-off-by: Peter Spreadborough Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher Reviewed-by: Farah Smith --- drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h | 72 ++++++++++- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c | 85 ++++++++++++ drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h | 15 +++ drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c | 109 +--------------- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c | 122 ++++++++++++++++++ drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h | 6 + drivers/net/bnxt/hcapi/cfa/meson.build | 4 +- drivers/net/bnxt/tf_core/tf_device.h | 15 +++ drivers/net/bnxt/tf_core/tf_device_p4.c | 4 + drivers/net/bnxt/tf_core/tf_device_p58.c | 4 + drivers/net/bnxt/tf_core/tf_em.h | 8 +- drivers/net/bnxt/tf_core/tf_em_common.c | 42 ++++-- .../net/bnxt/tf_core/tf_em_hash_internal.c | 22 +++- 13 files changed, 383 insertions(+), 125 deletions(-) create mode 100644 drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c create mode 100644 drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h index c67aa29ad0..0580e07c45 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h @@ -63,10 +63,74 @@ struct hcapi_cfa_devops { */ uint64_t (*hcapi_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); - /** hardware operation on the CFA EM key - * - * This API provides the functionality to program the exact match and - * key data to exact match record memory. +int hcapi_cfa_action_hw_op(struct hcapi_cfa_hwop *op, + uint8_t *act_tbl, + struct hcapi_cfa_data *act_obj); +int hcapi_cfa_dev_hw_op(struct hcapi_cfa_hwop *op, uint16_t tbl_id, + struct hcapi_cfa_data *obj_data); +int hcapi_cfa_rm_register_client(hcapi_cfa_rm_data_t *data, + const char *client_name, + int *client_id); +int hcapi_cfa_rm_unregister_client(hcapi_cfa_rm_data_t *data, + int client_id); +int hcapi_cfa_rm_query_resources(hcapi_cfa_rm_data_t *data, + int client_id, + uint16_t chnl_id, + struct hcapi_cfa_resc_req_db *req_db); +int hcapi_cfa_rm_query_resources_one(hcapi_cfa_rm_data_t *data, + int clien_id, + struct hcapi_cfa_resc_db *resc_db); +int hcapi_cfa_rm_reserve_resources(hcapi_cfa_rm_data_t *data, + int client_id, + struct hcapi_cfa_resc_req_db *resc_req, + struct hcapi_cfa_resc_db *resc_db); +int hcapi_cfa_rm_release_resources(hcapi_cfa_rm_data_t *data, + int client_id, + struct hcapi_cfa_resc_req_db *resc_req, + struct hcapi_cfa_resc_db *resc_db); +int hcapi_cfa_rm_initialize(hcapi_cfa_rm_data_t *data); + +#if SUPPORT_CFA_HW_P4 + +int hcapi_cfa_p4_dev_hw_op(struct hcapi_cfa_hwop *op, uint16_t tbl_id, + struct hcapi_cfa_data *obj_data); +int hcapi_cfa_p4_prof_l2ctxt_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *obj_data); +int hcapi_cfa_p4_prof_l2ctxtrmp_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *obj_data); +int hcapi_cfa_p4_prof_tcam_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *obj_data); +int hcapi_cfa_p4_prof_tcamrmp_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *obj_data); +int hcapi_cfa_p4_wc_tcam_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *obj_data); +int hcapi_cfa_p4_wc_tcam_rec_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *obj_data); +int hcapi_cfa_p4_mirror_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *mirror); +int hcapi_cfa_p4_global_cfg_hwop(struct hcapi_cfa_hwop *op, + uint32_t type, + struct hcapi_cfa_data *config); +/* SUPPORT_CFA_HW_P4 */ +#elif SUPPORT_CFA_HW_P45 +int hcapi_cfa_p45_mirror_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *mirror); +int hcapi_cfa_p45_global_cfg_hwop(struct hcapi_cfa_hwop *op, + uint32_t type, + struct hcapi_cfa_data *config); +/* SUPPORT_CFA_HW_P45 */ +#endif + +/** + * HCAPI CFA device HW operation function callback definition + * This is standardized function callback hook to install different + * CFA HW table programming function callback. + */ + +struct hcapi_cfa_tbl_cb { + /** + * This function callback provides the functionality to read/write + * HW table entry from a HW table. * * @param[in] op * A pointer to the Hardware operation parameter diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c new file mode 100644 index 0000000000..fc96e3bff7 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c @@ -0,0 +1,85 @@ +/* + * Copyright(c) 2019-2021 Broadcom Limited. + * All rights reserved. + */ + +#include "hcapi_cfa_defs.h" +#include +#include "assert.h" + +const uint32_t crc32tbl[] = { /* CRC polynomial 0xedb88320 */ +0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, +0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, +0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, +0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, +0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, +0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, +0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, +0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, +0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, +0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, +0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, +0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, +0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, +0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, +0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, +0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, +0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, +0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, +0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, +0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, +0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, +0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, +0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, +0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, +0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, +0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, +0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, +0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, +0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, +0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, +0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, +0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, +0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, +0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, +0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, +0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, +0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, +0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, +0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, +0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, +0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, +0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, +0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, +0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, +0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, +0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, +0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, +0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, +0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, +0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, +0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, +0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, +0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, +0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, +0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, +0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, +0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, +0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, +0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, +0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, +0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, +0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, +0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, +0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +uint32_t hcapi_cfa_crc32i(uint32_t crc, const uint8_t *buf, size_t len) +{ + int l; + + for (l = (len - 1); l >= 0; l--) + crc = ucrc32(buf[l], crc); + + return ~crc; +} diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h index 8e5095a6ef..579f1d5693 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h @@ -54,6 +54,16 @@ enum hcapi_cfa_dir { HCAPI_CFA_DIR_MAX = 2 }; +/* + * Hashing defines + */ +#define HCAPI_CFA_LKUP_SEED_MEM_SIZE 512 + +/* CRC32i support for Key0 hash */ +#define ucrc32(ch, crc) (crc32tbl[((crc) ^ (ch)) & 0xff] ^ ((crc) >> 8)) +#define crc32(x, y) crc32i(~0, x, y) + + /** * CFA HW OPCODE definition */ @@ -282,4 +292,9 @@ int hcapi_cfa_key_hw_op(struct hcapi_cfa_hwop *op, uint64_t hcapi_get_table_page(struct hcapi_cfa_em_table *mem, uint32_t page); +uint32_t hcapi_cfa_crc32i(uint32_t crc, const uint8_t *buf, size_t len); +uint64_t hcapi_cfa_p4_key_hash(uint64_t *key_data, + uint16_t bitlen); +uint64_t hcapi_cfa_p58_key_hash(uint64_t *key_data, + uint16_t bitlen); #endif /* HCAPI_CFA_DEFS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c index 3a0476a33d..0544b667dd 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c @@ -12,10 +12,11 @@ #include "hcapi_cfa_defs.h" -#define HCAPI_CFA_LKUP_SEED_MEM_SIZE 512 -uint32_t hcapi_cfa_lkup_lkup3_init_cfg; -uint32_t hcapi_cfa_lkup_em_seed_mem[HCAPI_CFA_LKUP_SEED_MEM_SIZE]; -bool hcapi_cfa_lkup_init; +static uint32_t hcapi_cfa_lkup_lkup3_init_cfg; +static uint32_t hcapi_cfa_lkup_em_seed_mem[HCAPI_CFA_LKUP_SEED_MEM_SIZE]; +static bool hcapi_cfa_lkup_init; + +extern const uint32_t crc32tbl[]; static inline uint32_t SWAP_WORDS32(uint32_t val32) { @@ -47,102 +48,6 @@ static void hcapi_cfa_seeds_init(void) } } -/* CRC32i support for Key0 hash */ -#define ucrc32(ch, crc) (crc32tbl[((crc) ^ (ch)) & 0xff] ^ ((crc) >> 8)) -#define crc32(x, y) crc32i(~0, x, y) - -static const uint32_t crc32tbl[] = { /* CRC polynomial 0xedb88320 */ -0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, -0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, -0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, -0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, -0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, -0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, -0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, -0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, -0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, -0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, -0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, -0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, -0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, -0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, -0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, -0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, -0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, -0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, -0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, -0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, -0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, -0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, -0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, -0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, -0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, -0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, -0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, -0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, -0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, -0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, -0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, -0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, -0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, -0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, -0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, -0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, -0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, -0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, -0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, -0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, -0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, -0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, -0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, -0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, -0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, -0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, -0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, -0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, -0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, -0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, -0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, -0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, -0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, -0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, -0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, -0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, -0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, -0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, -0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, -0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, -0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, -0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, -0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, -0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d -}; - -static uint32_t hcapi_cfa_crc32i(uint32_t crc, const uint8_t *buf, size_t len) -{ - int l; - -#ifdef TF_EEM_DEBUG - TFP_DRV_LOG(DEBUG, "CRC2:"); -#endif - for (l = (len - 1); l >= 0; l--) { - crc = ucrc32(buf[l], crc); -#ifdef TF_EEM_DEBUG - TFP_DRV_LOG(DEBUG, - "%02X %08X %08X\n", - (buf[l] & 0xff), - crc, - ~crc); -#endif - } - -#ifdef TF_EEM_DEBUG - TFP_DRV_LOG(DEBUG, "\n"); -#endif - - return ~crc; -} - static uint32_t hcapi_cfa_crc32_hash(uint8_t *key) { int i; @@ -221,8 +126,8 @@ uint64_t hcapi_get_table_page(struct hcapi_cfa_em_table *mem, * Return: * */ -uint64_t hcapi_cfa_key_hash(uint64_t *key_data, - uint16_t bitlen) +uint64_t hcapi_cfa_p4_key_hash(uint64_t *key_data, + uint16_t bitlen) { uint32_t key0_hash; uint32_t key1_hash; diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c new file mode 100644 index 0000000000..723b8393b9 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#include +#include +#include +#include +#include "lookup3.h" +#include "rand.h" + +#include "hcapi_cfa_defs.h" + +static uint32_t hcapi_cfa_lkup_lkup3_init_cfg; +static uint32_t hcapi_cfa_lkup_em_seed_mem[HCAPI_CFA_LKUP_SEED_MEM_SIZE]; +static bool hcapi_cfa_lkup_init; + +extern const uint32_t crc32tbl[]; + +static void hcapi_cfa_seeds_init(void) +{ + int i; + uint32_t r; + + if (hcapi_cfa_lkup_init) + return; + + hcapi_cfa_lkup_init = true; + + /* Initialize the lfsr */ + rand_init(); + + /* RX and TX use the same seed values */ + hcapi_cfa_lkup_lkup3_init_cfg = rand32(); + + for (i = 0; i < HCAPI_CFA_LKUP_SEED_MEM_SIZE / 2; i++) { + r = rand32(); + hcapi_cfa_lkup_em_seed_mem[i * 2] = r; + r = rand32(); + hcapi_cfa_lkup_em_seed_mem[i * 2 + 1] = (r & 0x1); + } +} + +static uint32_t hcapi_cfa_crc32_hash(uint8_t *key) +{ + int i; + uint32_t index; + uint32_t val1, val2; + uint8_t temp[4]; + uint8_t *kptr = key; + + /* Do byte-wise XOR of the 52-byte HASH key first. */ + index = *key; + kptr--; + + for (i = CFA_P58_EEM_KEY_MAX_SIZE - 2; i >= 0; i--) { + index = index ^ *kptr; + kptr--; + } + + /* Get seeds */ + val1 = hcapi_cfa_lkup_em_seed_mem[index * 2]; + val2 = hcapi_cfa_lkup_em_seed_mem[index * 2 + 1]; + + temp[3] = (uint8_t)(val1 >> 24); + temp[2] = (uint8_t)(val1 >> 16); + temp[1] = (uint8_t)(val1 >> 8); + temp[0] = (uint8_t)(val1 & 0xff); + val1 = 0; + + /* Start with seed */ + if (!(val2 & 0x1)) + val1 = hcapi_cfa_crc32i(~val1, temp, 4); + + val1 = hcapi_cfa_crc32i(~val1, + (key - (CFA_P58_EEM_KEY_MAX_SIZE - 1)), + CFA_P58_EEM_KEY_MAX_SIZE); + + /* End with seed */ + if (val2 & 0x1) + val1 = hcapi_cfa_crc32i(~val1, temp, 4); + + return val1; +} + +static uint32_t hcapi_cfa_lookup3_hash(uint8_t *in_key) +{ + uint32_t val1; + + val1 = hashword(((uint32_t *)in_key) + 1, + CFA_P58_EEM_KEY_MAX_SIZE / (sizeof(uint32_t)), + hcapi_cfa_lkup_lkup3_init_cfg); + + return val1; +} + + +/** Approximation of HCAPI hcapi_cfa_key_hash() + * + * Return: + * + */ +uint64_t hcapi_cfa_p58_key_hash(uint64_t *key_data, + uint16_t bitlen) +{ + uint32_t key0_hash; + uint32_t key1_hash; + + /* + * Init the seeds if needed + */ + if (!hcapi_cfa_lkup_init) + hcapi_cfa_seeds_init(); + + key0_hash = hcapi_cfa_crc32_hash(((uint8_t *)key_data) + + (bitlen / 8) - 1); + + key1_hash = hcapi_cfa_lookup3_hash((uint8_t *)key_data); + + return ((uint64_t)key0_hash) << 32 | (uint64_t)key1_hash; +} diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h index b2535098d2..27796b1b2f 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h @@ -6,6 +6,12 @@ #ifndef _HCAPI_CFA_P58_H_ #define _HCAPI_CFA_P58_H_ +/** + * EEM Key entry sizes + */ +#define CFA_P58_EEM_KEY_MAX_SIZE 80 +#define CFA_P58_EEM_KEY_RECORD_SIZE 80 + /** CFA phase 5.8 fix formatted table(layout) ID definition * */ diff --git a/drivers/net/bnxt/hcapi/cfa/meson.build b/drivers/net/bnxt/hcapi/cfa/meson.build index 8b70d273f4..5cdb1862f3 100644 --- a/drivers/net/bnxt/hcapi/cfa/meson.build +++ b/drivers/net/bnxt/hcapi/cfa/meson.build @@ -7,4 +7,6 @@ includes += include_directories('.') #Add the source files sources += files( - 'hcapi_cfa_p4.c') + 'hcapi_cfa_p4.c', + 'hcapi_cfa_p58.c', + 'hcapi_cfa_common.c') diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index a18d59660b..3f2c24a0c6 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -752,6 +752,21 @@ struct tf_dev_ops { * Size in byte */ int (*tf_dev_word_align)(uint16_t size); + + /** + * Hash key using crc32 and lookup3 + * + * [in] key_data + * Pointer to key + * + * [in] bitlen + * Number of key bits + * + * Returns + * Hashes + */ + uint64_t (*tf_dev_cfa_key_hash)(uint64_t *key_data, + uint16_t bitlen); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 8274978bfe..2fb8fadb56 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -18,6 +18,9 @@ #define TF_DEV_P4_PARIF_MAX 16 #define TF_DEV_P4_PF_MASK 0xfUL +uint64_t hcapi_cfa_key_hash_p4(uint64_t *key_data, + uint16_t bitlen); + const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { [CFA_RESOURCE_TYPE_P4_MCG] = "mc_group", [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = "encap_8 ", @@ -276,4 +279,5 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, + .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index b61c58e41b..517ffc811b 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -18,6 +18,9 @@ #define TF_DEV_P58_PARIF_MAX 16 #define TF_DEV_P58_PF_MASK 0xfUL +uint64_t hcapi_cfa_key_hash_p58(uint64_t *key_data, + uint16_t bitlen); + /* For print alignment, make all entries 8 chars in this table */ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_METER] = "meter ", @@ -297,4 +300,5 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, + .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash }; diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 5a67ca3509..4de9e42cbc 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -14,8 +14,10 @@ #define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */ #define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */ -#define TF_HW_EM_KEY_MAX_SIZE 52 -#define TF_EM_KEY_RECORD_SIZE 64 +#define TF_P4_HW_EM_KEY_MAX_SIZE 52 +#define TF_P4_EM_KEY_RECORD_SIZE 64 + +#define TF_P58_HW_EM_KEY_MAX_SIZE 80 #define TF_EM_MAX_MASK 0x7FFF #define TF_EM_MAX_ENTRY (128 * 1024 * 1024) @@ -95,7 +97,7 @@ struct tf_em_64b_entry { /** Header is 8 bytes long */ struct cfa_p4_eem_entry_hdr hdr; /** Key is 448 bits - 56 bytes */ - uint8_t key[TF_EM_KEY_RECORD_SIZE - sizeof(struct cfa_p4_eem_entry_hdr)]; + uint8_t key[TF_P4_EM_KEY_RECORD_SIZE - sizeof(struct cfa_p4_eem_entry_hdr)]; }; /** EEM Memory Type diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index 589df60041..d8278f1ce1 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -284,7 +284,7 @@ tf_em_create_key_entry(struct cfa_p4_eem_entry_hdr *result, { key_entry->hdr.word1 = result->word1; key_entry->hdr.pointer = result->pointer; - memcpy(key_entry->key, in_key, TF_HW_EM_KEY_MAX_SIZE + 4); + memcpy(key_entry->key, in_key, TF_P4_HW_EM_KEY_MAX_SIZE + 4); } @@ -680,7 +680,8 @@ tf_em_validate_num_entries(struct tf_tbl_scope_cb *tbl_scope_cb, * TF_ERR_EM_DUP - key is already in table */ static int -tf_insert_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, +tf_insert_eem_entry(struct tf_dev_info *dev, + struct tf_tbl_scope_cb *tbl_scope_cb, struct tf_insert_em_entry_parms *parms) { uint32_t mask; @@ -706,11 +707,14 @@ tf_insert_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, return -EINVAL; #ifdef TF_EEM_DEBUG - dump_raw((uint8_t *)parms->key, TF_HW_EM_KEY_MAX_SIZE + 4, "In Key"); + dump_raw((uint8_t *)parms->key, TF_P4_HW_EM_KEY_MAX_SIZE + 4, "In Key"); #endif - big_hash = hcapi_cfa_key_hash((uint64_t *)parms->key, - (TF_HW_EM_KEY_MAX_SIZE + 4) * 8); + if (dev->ops->tf_dev_cfa_key_hash == NULL) + return -EINVAL; + + big_hash = dev->ops->tf_dev_cfa_key_hash((uint64_t *)parms->key, + (TF_P4_HW_EM_KEY_MAX_SIZE + 4) * 8); key0_hash = (uint32_t)(big_hash >> 32); key1_hash = (uint32_t)(big_hash & 0xFFFFFFFF); @@ -739,9 +743,9 @@ tf_insert_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, key_tbl.base0 = (uint8_t *)&tbl_scope_cb->em_ctx_info[parms->dir].em_tables[TF_KEY0_TABLE]; key_tbl.page_size = TF_EM_PAGE_SIZE; - key_obj.offset = index * TF_EM_KEY_RECORD_SIZE; + key_obj.offset = index * TF_P4_EM_KEY_RECORD_SIZE; key_obj.data = (uint8_t *)&key_entry; - key_obj.size = TF_EM_KEY_RECORD_SIZE; + key_obj.size = TF_P4_EM_KEY_RECORD_SIZE; rc = hcapi_cfa_key_hw_op(&op, &key_tbl, @@ -755,7 +759,7 @@ tf_insert_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, key_tbl.base0 = (uint8_t *)&tbl_scope_cb->em_ctx_info[parms->dir].em_tables[TF_KEY1_TABLE]; - key_obj.offset = index * TF_EM_KEY_RECORD_SIZE; + key_obj.offset = index * TF_P4_EM_KEY_RECORD_SIZE; rc = hcapi_cfa_key_hw_op(&op, &key_tbl, @@ -818,9 +822,9 @@ tf_delete_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, (uint8_t *)&tbl_scope_cb->em_ctx_info[parms->dir].em_tables [(hash_type == 0 ? TF_KEY0_TABLE : TF_KEY1_TABLE)]; key_tbl.page_size = TF_EM_PAGE_SIZE; - key_obj.offset = index * TF_EM_KEY_RECORD_SIZE; + key_obj.offset = index * TF_P4_EM_KEY_RECORD_SIZE; key_obj.data = NULL; - key_obj.size = TF_EM_KEY_RECORD_SIZE; + key_obj.size = TF_P4_EM_KEY_RECORD_SIZE; rc = hcapi_cfa_key_hw_op(&op, &key_tbl, @@ -843,7 +847,10 @@ int tf_em_insert_ext_entry(struct tf *tfp __rte_unused, struct tf_insert_em_entry_parms *parms) { + int rc; struct tf_tbl_scope_cb *tbl_scope_cb; + struct tf_session *tfs; + struct tf_dev_info *dev; tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id); if (tbl_scope_cb == NULL) { @@ -851,9 +858,20 @@ tf_em_insert_ext_entry(struct tf *tfp __rte_unused, return -EINVAL; } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + return tf_insert_eem_entry - (tbl_scope_cb, - parms); + (dev, + tbl_scope_cb, + parms); } /** Delete EM hash entry API diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c index 09183b42f0..f6c9772b44 100644 --- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c @@ -15,6 +15,7 @@ #include "tf_msg.h" #include "tfp.h" #include "tf_ext_flow_handle.h" +#include "tf_device.h" #include "bnxt.h" @@ -43,6 +44,18 @@ tf_em_hash_insert_int_entry(struct tf *tfp, uint32_t key0_hash; uint32_t key1_hash; uint64_t big_hash; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; rc = stack_pop(pool, &index); if (rc) { @@ -52,8 +65,11 @@ tf_em_hash_insert_int_entry(struct tf *tfp, return rc; } - big_hash = hcapi_cfa_key_hash((uint64_t *)parms->key, - (TF_HW_EM_KEY_MAX_SIZE + 4) * 8); + if (dev->ops->tf_dev_cfa_key_hash == NULL) + return -EINVAL; + + big_hash = dev->ops->tf_dev_cfa_key_hash((uint64_t *)parms->key, + TF_P58_HW_EM_KEY_MAX_SIZE * 8); key0_hash = (uint32_t)(big_hash >> 32); key1_hash = (uint32_t)(big_hash & 0xFFFFFFFF); @@ -93,7 +109,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp, TF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle, (uint32_t)num_of_entries, 0, - 0, + TF_FLAGS_FLOW_HANDLE_INTERNAL, rptr_index, rptr_entry, 0); From patchwork Sun May 30 08:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93561 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22D6BA0524; Sun, 30 May 2021 11:02:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 03C3341154; Sun, 30 May 2021 11:00:49 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 0BF1D41145 for ; Sun, 30 May 2021 11:00:47 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 382BE7DC2; Sun, 30 May 2021 02:00:45 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 382BE7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365246; bh=xjAQpWerWAqffuXbm+zIu9VOPDHAoiZdt20ZRgfwmKg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HHisbRxkEYfy8jwbFiJoUudZDkCjkTtCW7mFNiqp/Fc/Y+o6QWpN6YApd1ZTY5yHC +1tkH/wG+DkLF4eG0ujEfcYfO2VC7jffAs5CIx6gx9U1z21z9sTeCA0syebB5NeqpX Uj/xmBF/67wuXOGYSNTZRMFCNu+8B3wQ05us1siI= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Peter Spreadborough , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:43 +0530 Message-Id: <20210530085929.29695-13-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 12/58] net/bnxt: modify TRUFLOW HWRM messages X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith - Move Bulk get to a direct HWRM message - Deprecate code based on HCAPI changes Signed-off-by: Farah Smith Signed-off-by: Peter Spreadborough Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h | 72 +---- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c | 4 +- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h | 197 ++++++++---- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c | 116 ++++--- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h | 282 +---------------- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c | 2 +- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h | 287 +----------------- drivers/net/bnxt/tf_core/hwrm_tf.h | 196 ------------ drivers/net/bnxt/tf_core/lookup3.h | 2 +- drivers/net/bnxt/tf_core/tf_core.c | 1 - drivers/net/bnxt/tf_core/tf_core.h | 127 ++++---- drivers/net/bnxt/tf_core/tf_device.c | 2 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 75 +++-- drivers/net/bnxt/tf_core/tf_device_p58.h | 48 ++- drivers/net/bnxt/tf_core/tf_em.h | 4 +- drivers/net/bnxt/tf_core/tf_em_common.c | 250 ++++++++++----- drivers/net/bnxt/tf_core/tf_em_common.h | 68 ++++- drivers/net/bnxt/tf_core/tf_em_host.c | 109 +++++-- drivers/net/bnxt/tf_core/tf_msg.c | 263 ++++++++++++++-- drivers/net/bnxt/tf_core/tf_msg.h | 87 ++++++ drivers/net/bnxt/tf_core/tf_msg_common.h | 3 - drivers/net/bnxt/tf_core/tf_session.c | 115 +++++++ drivers/net/bnxt/tf_core/tf_session.h | 90 ++++++ drivers/net/bnxt/tf_core/tf_tbl.h | 30 -- drivers/net/bnxt/tf_core/tf_util.c | 12 - drivers/net/bnxt/tf_core/tf_util.h | 4 + drivers/net/bnxt/tf_core/tfp.c | 34 --- drivers/net/bnxt/tf_core/tfp.h | 52 ---- 28 files changed, 1202 insertions(+), 1330 deletions(-) delete mode 100644 drivers/net/bnxt/tf_core/hwrm_tf.h diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h index 0580e07c45..c67aa29ad0 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h @@ -63,74 +63,10 @@ struct hcapi_cfa_devops { */ uint64_t (*hcapi_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); -int hcapi_cfa_action_hw_op(struct hcapi_cfa_hwop *op, - uint8_t *act_tbl, - struct hcapi_cfa_data *act_obj); -int hcapi_cfa_dev_hw_op(struct hcapi_cfa_hwop *op, uint16_t tbl_id, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_rm_register_client(hcapi_cfa_rm_data_t *data, - const char *client_name, - int *client_id); -int hcapi_cfa_rm_unregister_client(hcapi_cfa_rm_data_t *data, - int client_id); -int hcapi_cfa_rm_query_resources(hcapi_cfa_rm_data_t *data, - int client_id, - uint16_t chnl_id, - struct hcapi_cfa_resc_req_db *req_db); -int hcapi_cfa_rm_query_resources_one(hcapi_cfa_rm_data_t *data, - int clien_id, - struct hcapi_cfa_resc_db *resc_db); -int hcapi_cfa_rm_reserve_resources(hcapi_cfa_rm_data_t *data, - int client_id, - struct hcapi_cfa_resc_req_db *resc_req, - struct hcapi_cfa_resc_db *resc_db); -int hcapi_cfa_rm_release_resources(hcapi_cfa_rm_data_t *data, - int client_id, - struct hcapi_cfa_resc_req_db *resc_req, - struct hcapi_cfa_resc_db *resc_db); -int hcapi_cfa_rm_initialize(hcapi_cfa_rm_data_t *data); - -#if SUPPORT_CFA_HW_P4 - -int hcapi_cfa_p4_dev_hw_op(struct hcapi_cfa_hwop *op, uint16_t tbl_id, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_prof_l2ctxt_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_prof_l2ctxtrmp_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_prof_tcam_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_prof_tcamrmp_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_wc_tcam_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_wc_tcam_rec_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *obj_data); -int hcapi_cfa_p4_mirror_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *mirror); -int hcapi_cfa_p4_global_cfg_hwop(struct hcapi_cfa_hwop *op, - uint32_t type, - struct hcapi_cfa_data *config); -/* SUPPORT_CFA_HW_P4 */ -#elif SUPPORT_CFA_HW_P45 -int hcapi_cfa_p45_mirror_hwop(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_data *mirror); -int hcapi_cfa_p45_global_cfg_hwop(struct hcapi_cfa_hwop *op, - uint32_t type, - struct hcapi_cfa_data *config); -/* SUPPORT_CFA_HW_P45 */ -#endif - -/** - * HCAPI CFA device HW operation function callback definition - * This is standardized function callback hook to install different - * CFA HW table programming function callback. - */ - -struct hcapi_cfa_tbl_cb { - /** - * This function callback provides the functionality to read/write - * HW table entry from a HW table. + /** hardware operation on the CFA EM key + * + * This API provides the functionality to program the exact match and + * key data to exact match record memory. * * @param[in] op * A pointer to the Hardware operation parameter diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c index fc96e3bff7..93a9f555df 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_common.c @@ -3,9 +3,7 @@ * All rights reserved. */ -#include "hcapi_cfa_defs.h" -#include -#include "assert.h" +#include "hcapi_cfa.h" const uint32_t crc32tbl[] = { /* CRC polynomial 0xedb88320 */ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h index 579f1d5693..5135a857e1 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h @@ -1,7 +1,6 @@ - -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom - * All rights reserved. +/* + * Copyright(c) Broadcom Limited. + * All rights reserved. */ /*! @@ -14,27 +13,54 @@ #include #include #include -#include #include +#include + +#if !defined(__GNUC__) +#pragma anon_unions +#endif #define CFA_BITS_PER_BYTE (8) +#define CFA_BITS_PER_WORD (sizeof(uint32_t) * CFA_BITS_PER_BYTE) #define __CFA_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) -#define CFA_ALIGN(x, a) __CFA_ALIGN_MASK(x, (a) - 1) +#define CFA_ALIGN(x, a) __CFA_ALIGN_MASK((x), (a) - 1) +#define CFA_ALIGN_256(x) CFA_ALIGN(x, 256) #define CFA_ALIGN_128(x) CFA_ALIGN(x, 128) #define CFA_ALIGN_32(x) CFA_ALIGN(x, 32) -#define NUM_WORDS_ALIGN_32BIT(x) \ - (CFA_ALIGN_32(x) / (sizeof(uint32_t) * CFA_BITS_PER_BYTE)) -#define NUM_WORDS_ALIGN_128BIT(x) \ - (CFA_ALIGN_128(x) / (sizeof(uint32_t) * CFA_BITS_PER_BYTE)) +#define NUM_WORDS_ALIGN_32BIT(x) (CFA_ALIGN_32(x) / CFA_BITS_PER_WORD) +#define NUM_WORDS_ALIGN_128BIT(x) (CFA_ALIGN_128(x) / CFA_BITS_PER_WORD) +#define NUM_WORDS_ALIGN_256BIT(x) (CFA_ALIGN_256(x) / CFA_BITS_PER_WORD) +/* TODO: redefine according to chip variant */ #define CFA_GLOBAL_CFG_DATA_SZ (100) +#ifndef SUPPORT_CFA_HW_P4 +#define SUPPORT_CFA_HW_P4 (0) +#endif + +#ifndef SUPPORT_CFA_HW_P45 +#define SUPPORT_CFA_HW_P45 (0) +#endif + +#ifndef SUPPORT_CFA_HW_P58 +#define SUPPORT_CFA_HW_P58 (0) +#endif + #if SUPPORT_CFA_HW_ALL #include "hcapi_cfa_p4.h" #include "hcapi_cfa_p58.h" #endif /* SUPPORT_CFA_HW_ALL */ +/* + * Hashing defines + */ +#define HCAPI_CFA_LKUP_SEED_MEM_SIZE 512 + +/* CRC32i support for Key0 hash */ +#define ucrc32(ch, crc) (crc32tbl[((crc) ^ (ch)) & 0xff] ^ ((crc) >> 8)) +#define crc32(x, y) crc32i(~0, x, y) + /** * CFA HW version definition */ @@ -54,35 +80,30 @@ enum hcapi_cfa_dir { HCAPI_CFA_DIR_MAX = 2 }; -/* - * Hashing defines - */ -#define HCAPI_CFA_LKUP_SEED_MEM_SIZE 512 - -/* CRC32i support for Key0 hash */ -#define ucrc32(ch, crc) (crc32tbl[((crc) ^ (ch)) & 0xff] ^ ((crc) >> 8)) -#define crc32(x, y) crc32i(~0, x, y) - - /** * CFA HW OPCODE definition */ enum hcapi_cfa_hwops { - HCAPI_CFA_HWOPS_PUT, /**< Write to HW operation */ - HCAPI_CFA_HWOPS_GET, /**< Read from HW operation */ - HCAPI_CFA_HWOPS_ADD, /**< For operations which require more than simple - * writes to HW, this operation is used. The - * distinction with this operation when compared - * to the PUT ops is that this operation is used - * in conjunction with the HCAPI_CFA_HWOPS_DEL - * op to remove the operations issued by the - * ADD OP. - */ - HCAPI_CFA_HWOPS_DEL, /**< This issues operations to clear the hardware. - * This operation is used in conjunction - * with the HCAPI_CFA_HWOPS_ADD op and is the - * way to undo/clear the ADD op. - */ + HCAPI_CFA_HWOPS_PUT, /**< Write to HW operation */ + HCAPI_CFA_HWOPS_GET, /**< Read from HW operation */ + HCAPI_CFA_HWOPS_ADD, /*< + * For operations which require more then + * simple writes to HW, this operation is + * used. The distinction with this operation + * when compared to the PUT ops is that this + * operation is used in conjunction with + * the HCAPI_CFA_HWOPS_DEL op to remove + * the operations issued by the ADD OP. + */ + HCAPI_CFA_HWOPS_DEL, /*< + * Beside to delete from the hardware, this + * operation is also undo the add operation + * performed by the HCAPI_CFA_HWOPS_ADD op. + */ + HCAPI_CFA_HWOPS_EVICT, /*< This operaton is used to evit entries from + * CFA cache memories. This operation is only + * applicable to tables that use CFA caches. + */ HCAPI_CFA_HWOPS_MAX }; @@ -91,11 +112,10 @@ enum hcapi_cfa_hwops { */ enum hcapi_cfa_key_ctrlops { HCAPI_CFA_KEY_CTRLOPS_INSERT, /**< insert control bits */ - HCAPI_CFA_KEY_CTRLOPS_STRIP, /**< strip control bits */ + HCAPI_CFA_KEY_CTRLOPS_STRIP, /**< strip control bits */ HCAPI_CFA_KEY_CTRLOPS_MAX }; - /** * CFA HW definition */ @@ -132,18 +152,23 @@ struct hcapi_cfa_data { /** [in] physical offset to the HW table for the data to be * written to. If this is an array of registers, this is the * index into the array of registers. For writing keys, this - * is the byte offset into the memory where the key should be + * is the byte pointer into the memory where the key should be * written. */ union { uint32_t index; uint32_t byte_offset; - } u; + }; /** [in] HW data buffer pointer */ uint8_t *data; - /** [in] HW data mask buffer pointer */ + /** [in] HW data mask buffer pointer. + * When the CFA data is a FKB and data_mask pointer + * is NULL, then the default mask to enable all bit will + * be used. + */ uint8_t *data_mask; - /** [in] size of the HW data buffer in bytes */ + /** [in/out] size of the HW data buffer in bytes + */ uint16_t data_sz; }; @@ -160,35 +185,36 @@ enum hcapi_cfa_em_table_type { TF_KEY1_TABLE, TF_RECORD_TABLE, TF_EFC_TABLE, + TF_ACTION_TABLE, + TF_EM_LKUP_TABLE, TF_MAX_TABLE }; struct hcapi_cfa_em_page_tbl { - uint32_t pg_count; - uint32_t pg_size; - void **pg_va_tbl; - uint64_t *pg_pa_tbl; + uint32_t pg_count; + uint32_t pg_size; + void **pg_va_tbl; + uint64_t *pg_pa_tbl; }; struct hcapi_cfa_em_table { - int type; - uint32_t num_entries; - uint16_t ctx_id; - uint32_t entry_size; - int num_lvl; - uint32_t page_cnt[TF_PT_LVL_MAX]; - uint64_t num_data_pages; - void *l0_addr; - uint64_t l0_dma_addr; - struct hcapi_cfa_em_page_tbl pg_tbl[TF_PT_LVL_MAX]; + int type; + uint32_t num_entries; + uint16_t ctx_id; + uint32_t entry_size; + int num_lvl; + uint32_t page_cnt[TF_PT_LVL_MAX]; + uint64_t num_data_pages; + void *l0_addr; + uint64_t l0_dma_addr; + struct hcapi_cfa_em_page_tbl pg_tbl[TF_PT_LVL_MAX]; }; struct hcapi_cfa_em_ctx_mem_info { - struct hcapi_cfa_em_table em_tables[TF_MAX_TABLE]; + struct hcapi_cfa_em_table em_tables[TF_MAX_TABLE]; }; /*********************** Truflow end ****************************/ - /** * CFA HW key table definition * @@ -210,6 +236,10 @@ struct hcapi_cfa_key_tbl { * applicable for newer chip */ uint8_t *base1; + /** [in] Optional - If the table is managed by a Backing Store + * database, then this object can be use to configure the EM Key. + */ + struct hcapi_cfa_bs_db *bs_db; /** [in] Page size for EEM tables */ uint32_t page_size; }; @@ -220,7 +250,7 @@ struct hcapi_cfa_key_tbl { struct hcapi_cfa_key_obj { /** [in] pointer to the key data buffer */ uint32_t *data; - /** [in] buffer len in bits */ + /** [in] buffer len in bytes */ uint32_t len; /** [in] Pointer to the key layout */ struct hcapi_cfa_key_layout *layout; @@ -239,6 +269,13 @@ struct hcapi_cfa_key_data { uint8_t *data; /** [in] size of the key in bytes */ uint16_t size; + /** [in] optional table scope ID */ + uint8_t tbl_scope; + /** [in] the fid owner of the key */ + uint64_t metadata; + /** [in] stored with the bucket which can be used to by + * the caller to retreved later via the GET HW OP. + */ }; /** @@ -247,8 +284,52 @@ struct hcapi_cfa_key_data { struct hcapi_cfa_key_loc { /** [out] on-chip EM bucket offset or off-chip EM bucket mem pointer */ uint64_t bucket_mem_ptr; + /** [out] off-chip EM key offset mem pointer */ + uint64_t mem_ptr; + /** [out] index within the array of the EM buckets */ + uint32_t bucket_mem_idx; /** [out] index within the EM bucket */ uint8_t bucket_idx; + /** [out] index within the EM records */ + uint32_t mem_idx; +}; + +/** + * Action record info + */ +struct hcapi_cfa_action_addr { + /** [in] action SRAM block ID for on-chip action records or table + * scope of the action backing store + */ + uint16_t blk_id; + /** [in] ar_id or cache line aligned address offset for the action + * record + */ + uint32_t offset; +}; + +/** + * Action data definition + */ +struct hcapi_cfa_action_data { + /** [in] action record addr info for on-chip action records */ + struct hcapi_cfa_action_addr addr; + /** [in/out] pointer to the action data buffer */ + uint32_t *data; + /** [in] action data buffer len in bytes */ + uint32_t len; +}; + +/** + * Action object definition + */ +struct hcapi_cfa_action_obj { + /** [in] pointer to the action data buffer */ + uint32_t *data; + /** [in] buffer len in bytes */ + uint32_t len; + /** [in] pointer to the action layout */ + struct hcapi_cfa_action_layout *layout; }; /** diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c index 0544b667dd..79bc569989 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c @@ -1,8 +1,9 @@ + /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2019-2021 Broadcom * All rights reserved. */ -#include + #include #include #include @@ -10,6 +11,7 @@ #include "lookup3.h" #include "rand.h" +#include "hcapi_cfa.h" #include "hcapi_cfa_defs.h" static uint32_t hcapi_cfa_lkup_lkup3_init_cfg; @@ -18,10 +20,9 @@ static bool hcapi_cfa_lkup_init; extern const uint32_t crc32tbl[]; -static inline uint32_t SWAP_WORDS32(uint32_t val32) +static __inline uint32_t SWAP_WORDS32(uint32_t val32) { - return (((val32 & 0x0000ffff) << 16) | - ((val32 & 0xffff0000) >> 16)); + return (((val32 & 0x0000ffff) << 16) | ((val32 & 0xffff0000) >> 16)); } static void hcapi_cfa_seeds_init(void) @@ -79,9 +80,8 @@ static uint32_t hcapi_cfa_crc32_hash(uint8_t *key) if (!(val2 & 0x1)) val1 = hcapi_cfa_crc32i(~val1, temp, 4); - val1 = hcapi_cfa_crc32i(~val1, - (key - (CFA_P4_EEM_KEY_MAX_SIZE - 1)), - CFA_P4_EEM_KEY_MAX_SIZE); + val1 = hcapi_cfa_crc32i(~val1, (key - (CFA_P4_EEM_KEY_MAX_SIZE - 1)), + CFA_P4_EEM_KEY_MAX_SIZE); /* End with seed */ if (val2 & 0x1) @@ -94,16 +94,14 @@ static uint32_t hcapi_cfa_lookup3_hash(uint8_t *in_key) { uint32_t val1; - val1 = hashword(((const uint32_t *)(uintptr_t *)in_key) + 1, - CFA_P4_EEM_KEY_MAX_SIZE / (sizeof(uint32_t)), - hcapi_cfa_lkup_lkup3_init_cfg); + val1 = hashword(((uint32_t *)in_key) + 1, + CFA_P4_EEM_KEY_MAX_SIZE / (sizeof(uint32_t)), + hcapi_cfa_lkup_lkup3_init_cfg); return val1; } - -uint64_t hcapi_get_table_page(struct hcapi_cfa_em_table *mem, - uint32_t page) +uint64_t hcapi_get_table_page(struct hcapi_cfa_em_table *mem, uint32_t page) { int level = 0; uint64_t addr; @@ -116,7 +114,7 @@ uint64_t hcapi_get_table_page(struct hcapi_cfa_em_table *mem, */ level = mem->num_lvl - 1; - addr = (uintptr_t)mem->pg_tbl[level].pg_va_tbl[page]; + addr = (uint64_t)mem->pg_tbl[level].pg_va_tbl[page]; return addr; } @@ -138,42 +136,39 @@ uint64_t hcapi_cfa_p4_key_hash(uint64_t *key_data, if (!hcapi_cfa_lkup_init) hcapi_cfa_seeds_init(); - key0_hash = hcapi_cfa_crc32_hash(((uint8_t *)key_data) + - (bitlen / 8) - 1); + key0_hash = + hcapi_cfa_crc32_hash(((uint8_t *)key_data) + (bitlen / 8) - 1); key1_hash = hcapi_cfa_lookup3_hash((uint8_t *)key_data); return ((uint64_t)key0_hash) << 32 | (uint64_t)key1_hash; } -static int hcapi_cfa_key_hw_op_put(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_key_data *key_obj) +static int hcapi_cfa_p4_key_hw_op_put(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_key_data *key_obj) { int rc = 0; - memcpy((uint8_t *)(uintptr_t)op->hw.base_addr + - key_obj->offset, - key_obj->data, - key_obj->size); + memcpy((uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, + key_obj->data, key_obj->size); return rc; } -static int hcapi_cfa_key_hw_op_get(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_key_data *key_obj) +static int hcapi_cfa_p4_key_hw_op_get(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_key_data *key_obj) { int rc = 0; memcpy(key_obj->data, - (uint8_t *)(uintptr_t)op->hw.base_addr + - key_obj->offset, + (uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, key_obj->size); return rc; } -static int hcapi_cfa_key_hw_op_add(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_key_data *key_obj) +static int hcapi_cfa_p4_key_hw_op_add(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_key_data *key_obj) { int rc = 0; struct cfa_p4_eem_64b_entry table_entry; @@ -182,8 +177,7 @@ static int hcapi_cfa_key_hw_op_add(struct hcapi_cfa_hwop *op, * Is entry free? */ memcpy(&table_entry, - (uint8_t *)(uintptr_t)op->hw.base_addr + - key_obj->offset, + (uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, key_obj->size); /* @@ -192,16 +186,14 @@ static int hcapi_cfa_key_hw_op_add(struct hcapi_cfa_hwop *op, if (table_entry.hdr.word1 & (1 << CFA_P4_EEM_ENTRY_VALID_SHIFT)) return -1; - memcpy((uint8_t *)(uintptr_t)op->hw.base_addr + - key_obj->offset, - key_obj->data, - key_obj->size); + memcpy((uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, + key_obj->data, key_obj->size); return rc; } -static int hcapi_cfa_key_hw_op_del(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_key_data *key_obj) +static int hcapi_cfa_p4_key_hw_op_del(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_key_data *key_obj) { int rc = 0; struct cfa_p4_eem_64b_entry table_entry; @@ -210,8 +202,7 @@ static int hcapi_cfa_key_hw_op_del(struct hcapi_cfa_hwop *op, * Read entry */ memcpy(&table_entry, - (uint8_t *)(uintptr_t)op->hw.base_addr + - key_obj->offset, + (uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, key_obj->size); /* @@ -223,8 +214,7 @@ static int hcapi_cfa_key_hw_op_del(struct hcapi_cfa_hwop *op, * before deleting the entry. */ if (key_obj->data != NULL) { - if (memcmp(&table_entry, - key_obj->data, + if (memcmp(&table_entry, key_obj->data, key_obj->size) != 0) return -1; } @@ -232,40 +222,33 @@ static int hcapi_cfa_key_hw_op_del(struct hcapi_cfa_hwop *op, return -1; } - /* * Delete entry */ - memset((uint8_t *)(uintptr_t)op->hw.base_addr + - key_obj->offset, - 0, - key_obj->size); + memset((uint8_t *)(uintptr_t)op->hw.base_addr + key_obj->offset, 0, key_obj->size); return rc; } - /** Apporiximation of hcapi_cfa_key_hw_op() * * */ -int hcapi_cfa_key_hw_op(struct hcapi_cfa_hwop *op, - struct hcapi_cfa_key_tbl *key_tbl, - struct hcapi_cfa_key_data *key_obj, - struct hcapi_cfa_key_loc *key_loc) +static int hcapi_cfa_p4_key_hw_op(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_key_tbl *key_tbl, + struct hcapi_cfa_key_data *key_obj, + struct hcapi_cfa_key_loc *key_loc) { int rc = 0; + struct hcapi_cfa_em_table *em_tbl; + uint32_t page; - if (op == NULL || - key_tbl == NULL || - key_obj == NULL || - key_loc == NULL) + if (op == NULL || key_tbl == NULL || key_obj == NULL || key_loc == NULL) return -1; - op->hw.base_addr = - hcapi_get_table_page((struct hcapi_cfa_em_table *) - key_tbl->base0, - key_obj->offset / key_tbl->page_size); + page = key_obj->offset / key_tbl->page_size; + em_tbl = (struct hcapi_cfa_em_table *)key_tbl->base0; + op->hw.base_addr = hcapi_get_table_page(em_tbl, page); /* Offset is adjusted to be the offset into the page */ key_obj->offset = key_obj->offset % key_tbl->page_size; @@ -274,14 +257,14 @@ int hcapi_cfa_key_hw_op(struct hcapi_cfa_hwop *op, switch (op->opcode) { case HCAPI_CFA_HWOPS_PUT: /**< Write to HW operation */ - rc = hcapi_cfa_key_hw_op_put(op, key_obj); + rc = hcapi_cfa_p4_key_hw_op_put(op, key_obj); break; case HCAPI_CFA_HWOPS_GET: /**< Read from HW operation */ - rc = hcapi_cfa_key_hw_op_get(op, key_obj); + rc = hcapi_cfa_p4_key_hw_op_get(op, key_obj); break; case HCAPI_CFA_HWOPS_ADD: - /**< For operations which require more than - * simple writes to HW, this operation is used. The + /**< For operations which require more then simple + * writes to HW, this operation is used. The * distinction with this operation when compared * to the PUT ops is that this operation is used * in conjunction with the HCAPI_CFA_HWOPS_DEL @@ -289,11 +272,11 @@ int hcapi_cfa_key_hw_op(struct hcapi_cfa_hwop *op, * ADD OP. */ - rc = hcapi_cfa_key_hw_op_add(op, key_obj); + rc = hcapi_cfa_p4_key_hw_op_add(op, key_obj); break; case HCAPI_CFA_HWOPS_DEL: - rc = hcapi_cfa_key_hw_op_del(op, key_obj); + rc = hcapi_cfa_p4_key_hw_op_del(op, key_obj); break; default: rc = -1; @@ -302,3 +285,8 @@ int hcapi_cfa_key_hw_op(struct hcapi_cfa_hwop *op, return rc; } + +const struct hcapi_cfa_devops cfa_p4_devops = { + .hcapi_cfa_key_hash = hcapi_cfa_p4_key_hash, + .hcapi_cfa_key_hw_op = hcapi_cfa_p4_key_hw_op, +}; diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h index 74a5483c0b..363ffcd57c 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2019-2021 Broadcom * All rights reserved. */ @@ -44,286 +44,6 @@ struct cfa_p4_prof_key_cfg { enum cfa_p4_mac_sel_mode mode; }; -/** - * CFA action layout definition - */ - -#define CFA_P4_ACTION_MAX_LAYOUT_SIZE 184 - -/** - * Action object template structure - * - * Template structure presents data fields that are necessary to know - * at the beginning of Action Builder (AB) processing. Like before the - * AB compilation. One such example could be a template that is - * flexible in size (Encap Record) and the presence of these fields - * allows for determining the template size as well as where the - * fields are located in the record. - * - * The template may also present fields that are not made visible to - * the caller by way of the action fields. - * - * Template fields also allow for additional checking on user visible - * fields. One such example could be the encap pointer behavior on a - * CFA_P4_ACT_OBJ_TYPE_ACT or CFA_P4_ACT_OBJ_TYPE_ACT_SRAM. - */ -struct cfa_p4_action_template { - /** Action Object type - * - * Controls the type of the Action Template - */ - enum { - /** Select this type to build an Action Record Object - */ - CFA_P4_ACT_OBJ_TYPE_ACT, - /** Select this type to build an Action Statistics - * Object - */ - CFA_P4_ACT_OBJ_TYPE_STAT, - /** Select this type to build a SRAM Action Record - * Object. - */ - CFA_P4_ACT_OBJ_TYPE_ACT_SRAM, - /** Select this type to build a SRAM Action - * Encapsulation Object. - */ - CFA_P4_ACT_OBJ_TYPE_ENCAP_SRAM, - /** Select this type to build a SRAM Action Modify - * Object, with IPv4 capability. - */ - /* In case of Stingray the term Modify is used for the 'NAT - * action'. Action builder is leveraged to fill in the NAT - * object which then can be referenced by the action - * record. - */ - CFA_P4_ACT_OBJ_TYPE_MODIFY_IPV4_SRAM, - /** Select this type to build a SRAM Action Source - * Property Object. - */ - /* In case of Stingray this is not a 'pure' action record. - * Action builder is leveraged to full in the Source Property - * object which can then be referenced by the action - * record. - */ - CFA_P4_ACT_OBJ_TYPE_SRC_PROP_SRAM, - /** Select this type to build a SRAM Action Statistics - * Object - */ - CFA_P4_ACT_OBJ_TYPE_STAT_SRAM, - } obj_type; - - /** Action Control - * - * Controls the internals of the Action Template - * - * act is valid when: - * (obj_type == CFA_P4_ACT_OBJ_TYPE_ACT) - */ - /* - * Stat and encap are always inline for EEM as table scope - * allocation does not allow for separate Stats allocation, - * but has the xx_inline flags as to be forward compatible - * with Stingray 2, always treated as TRUE. - */ - struct { - /** Set to CFA_HCAPI_TRUE to enable statistics - */ - uint8_t stat_enable; - /** Set to CFA_HCAPI_TRUE to enable statistics to be inlined - */ - uint8_t stat_inline; - - /** Set to CFA_HCAPI_TRUE to enable encapsulation - */ - uint8_t encap_enable; - /** Set to CFA_HCAPI_TRUE to enable encapsulation to be inlined - */ - uint8_t encap_inline; - } act; - - /** Modify Setting - * - * Controls the type of the Modify Action the template is - * describing - * - * modify is valid when: - * (obj_type == CFA_P4_ACT_OBJ_TYPE_MODIFY_SRAM) - */ - enum { - /** Set to enable Modify of Source IPv4 Address - */ - CFA_P4_MR_REPLACE_SOURCE_IPV4 = 0, - /** Set to enable Modify of Destination IPv4 Address - */ - CFA_P4_MR_REPLACE_DEST_IPV4 - } modify; - - /** Encap Control - * Controls the type of encapsulation the template is - * describing - * - * encap is valid when: - * ((obj_type == CFA_P4_ACT_OBJ_TYPE_ACT) && - * act.encap_enable) || - * ((obj_type == CFA_P4_ACT_OBJ_TYPE_SRC_PROP_SRAM) - */ - struct { - /* Direction is required as Stingray Encap on RX is - * limited to l2 and VTAG only. - */ - /** Receive or Transmit direction - */ - uint8_t direction; - /** Set to CFA_HCAPI_TRUE to enable L2 capability in the - * template - */ - uint8_t l2_enable; - /** vtag controls the Encap Vector - VTAG Encoding, 4 bits - * - *
    - *
  • CFA_P4_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN - * Tags applied - *
  • CFA_P4_ACT_ENCAP_VTAGS_PUSH_1, adds capability to - * set 1 VLAN Tag. Action Template compile adds - * the following field to the action object - * ::TF_ER_VLAN1 - *
  • CFA_P4_ACT_ENCAP_VTAGS_PUSH_2, adds capability to - * set 2 VLAN Tags. Action Template compile adds - * the following fields to the action object - * ::TF_ER_VLAN1 and ::TF_ER_VLAN2 - *
- */ - enum { CFA_P4_ACT_ENCAP_VTAGS_PUSH_0 = 0, - CFA_P4_ACT_ENCAP_VTAGS_PUSH_1, - CFA_P4_ACT_ENCAP_VTAGS_PUSH_2 } vtag; - - /* - * The remaining fields are NOT supported when - * direction is RX and ((obj_type == - * CFA_P4_ACT_OBJ_TYPE_ACT) && act.encap_enable). - * ab_compile_layout will perform the checking and - * skip remaining fields. - */ - /** L3 Encap controls the Encap Vector - L3 Encoding, - * 3 bits. Defines the type of L3 Encapsulation the - * template is describing. - *
    - *
  • CFA_P4_ACT_ENCAP_L3_NONE, default, no L3 - * Encapsulation processing. - *
  • CFA_P4_ACT_ENCAP_L3_IPV4, enables L3 IPv4 - * Encapsulation. - *
  • CFA_P4_ACT_ENCAP_L3_IPV6, enables L3 IPv6 - * Encapsulation. - *
  • CFA_P4_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS - * 8847 Encapsulation. - *
  • CFA_P4_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS - * 8848 Encapsulation. - *
- */ - enum { - /** Set to disable any L3 encapsulation - * processing, default - */ - CFA_P4_ACT_ENCAP_L3_NONE = 0, - /** Set to enable L3 IPv4 encapsulation - */ - CFA_P4_ACT_ENCAP_L3_IPV4 = 4, - /** Set to enable L3 IPv6 encapsulation - */ - CFA_P4_ACT_ENCAP_L3_IPV6 = 5, - /** Set to enable L3 MPLS 8847 encapsulation - */ - CFA_P4_ACT_ENCAP_L3_MPLS_8847 = 6, - /** Set to enable L3 MPLS 8848 encapsulation - */ - CFA_P4_ACT_ENCAP_L3_MPLS_8848 = 7 - } l3; - -#define CFA_P4_ACT_ENCAP_MAX_MPLS_LABELS 8 - /** 1-8 labels, valid when - * (l3 == CFA_P4_ACT_ENCAP_L3_MPLS_8847) || - * (l3 == CFA_P4_ACT_ENCAP_L3_MPLS_8848) - * - * MAX number of MPLS Labels 8. - */ - uint8_t l3_num_mpls_labels; - - /** Set to CFA_HCAPI_TRUE to enable L4 capability in the - * template. - * - * CFA_HCAPI_TRUE adds ::TF_EN_UDP_SRC_PORT and - * ::TF_EN_UDP_DST_PORT to the template. - */ - uint8_t l4_enable; - - /** Tunnel Encap controls the Encap Vector - Tunnel - * Encap, 3 bits. Defines the type of Tunnel - * encapsulation the template is describing - *
    - *
  • CFA_P4_ACT_ENCAP_TNL_NONE, default, no Tunnel - * Encapsulation processing. - *
  • CFA_P4_ACT_ENCAP_TNL_GENERIC_FULL - *
  • CFA_P4_ACT_ENCAP_TNL_VXLAN. NOTE: Expects - * l4_enable set to CFA_P4_TRUE; - *
  • CFA_P4_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable - * set to CFA_P4_TRUE; - *
  • CFA_P4_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if - * l4_enable set to CFA_HCAPI_FALSE. - *
  • CFA_P4_ACT_ENCAP_TNL_GRE.NOTE: only valid if - * l4_enable set to CFA_HCAPI_FALSE. - *
  • CFA_P4_ACT_ENCAP_TNL_GENERIC_AFTER_TL4 - *
  • CFA_P4_ACT_ENCAP_TNL_GENERIC_AFTER_TNL - *
- */ - enum { - /** Set to disable Tunnel header encapsulation - * processing, default - */ - CFA_P4_ACT_ENCAP_TNL_NONE = 0, - /** Set to enable Tunnel Generic Full header - * encapsulation - */ - CFA_P4_ACT_ENCAP_TNL_GENERIC_FULL, - /** Set to enable VXLAN header encapsulation - */ - CFA_P4_ACT_ENCAP_TNL_VXLAN, - /** Set to enable NGE (VXLAN2) header encapsulation - */ - CFA_P4_ACT_ENCAP_TNL_NGE, - /** Set to enable NVGRE header encapsulation - */ - CFA_P4_ACT_ENCAP_TNL_NVGRE, - /** Set to enable GRE header encapsulation - */ - CFA_P4_ACT_ENCAP_TNL_GRE, - /** Set to enable Generic header after Tunnel - * L4 encapsulation - */ - CFA_P4_ACT_ENCAP_TNL_GENERIC_AFTER_TL4, - /** Set to enable Generic header after Tunnel - * encapsulation - */ - CFA_P4_ACT_ENCAP_TNL_GENERIC_AFTER_TNL - } tnl; - - /** Number of bytes of generic tunnel header, - * valid when - * (tnl == CFA_P4_ACT_ENCAP_TNL_GENERIC_FULL) || - * (tnl == CFA_P4_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) || - * (tnl == CFA_P4_ACT_ENCAP_TNL_GENERIC_AFTER_TNL) - */ - uint8_t tnl_generic_size; - /** Number of 32b words of nge options, - * valid when - * (tnl == CFA_P4_ACT_ENCAP_TNL_NGE) - */ - uint8_t tnl_nge_op_len; - /* Currently not planned */ - /* Custom Header */ - /* uint8_t custom_enable; */ - } encap; -}; - /** * Enumeration of SRAM entry types, used for allocation of * fixed SRAM entities. The memory model for CFA HCAPI diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c index 723b8393b9..a70c6f4eaa 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.c @@ -88,7 +88,7 @@ static uint32_t hcapi_cfa_lookup3_hash(uint8_t *in_key) { uint32_t val1; - val1 = hashword(((uint32_t *)in_key) + 1, + val1 = hashword(((uint32_t *)in_key), CFA_P58_EEM_KEY_MAX_SIZE / (sizeof(uint32_t)), hcapi_cfa_lkup_lkup3_init_cfg); diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h index 27796b1b2f..d272d3ffec 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p58.h @@ -12,6 +12,11 @@ #define CFA_P58_EEM_KEY_MAX_SIZE 80 #define CFA_P58_EEM_KEY_RECORD_SIZE 80 +#define CFA_P58_EM_FKB_NUM_WORDS 4 +#define CFA_P58_EM_FKB_NUM_ENTRIES 64 +#define CFA_P58_WC_TCAM_FKB_NUM_WORDS 4 +#define CFA_P58_WC_TCAM_FKB_NUM_ENTRIES 64 + /** CFA phase 5.8 fix formatted table(layout) ID definition * */ @@ -29,7 +34,7 @@ enum cfa_p58_tbl_id { CFA_P58_TBL_PROF_PARIF_DFLT_ACT_REC_PTR, /** Error Profile TCAM Miss Action Record Pointer Table */ CFA_P58_TBL_PROF_PARIF_ERR_ACT_REC_PTR, - /** SR2 VNIC/SVIF Properties Table */ + /** VNIC/SVIF Properties Table */ CFA_P58_TBL_VSPT, CFA_P58_TBL_MAX }; @@ -56,286 +61,6 @@ struct cfa_p58_prof_key_cfg { enum cfa_p58_mac_sel_mode mode; }; -/** - * CFA action layout definition - */ - -#define CFA_P58_ACTION_MAX_LAYOUT_SIZE 184 - -/** - * Action object template structure - * - * Template structure presents data fields that are necessary to know - * at the beginning of Action Builder (AB) processing. Like before the - * AB compilation. One such example could be a template that is - * flexible in size (Encap Record) and the presence of these fields - * allows for determining the template size as well as where the - * fields are located in the record. - * - * The template may also present fields that are not made visible to - * the caller by way of the action fields. - * - * Template fields also allow for additional checking on user visible - * fields. One such example could be the encap pointer behavior on a - * CFA_P58_ACT_OBJ_TYPE_ACT or CFA_P58_ACT_OBJ_TYPE_ACT_SRAM. - */ -struct cfa_p58_action_template { - /** Action Object type - * - * Controls the type of the Action Template - */ - enum { - /** Select this type to build an Action Record Object - */ - CFA_P58_ACT_OBJ_TYPE_ACT, - /** Select this type to build an Action Statistics - * Object - */ - CFA_P58_ACT_OBJ_TYPE_STAT, - /** Select this type to build a SRAM Action Record - * Object. - */ - CFA_P58_ACT_OBJ_TYPE_ACT_SRAM, - /** Select this type to build a SRAM Action - * Encapsulation Object. - */ - CFA_P58_ACT_OBJ_TYPE_ENCAP_SRAM, - /** Select this type to build a SRAM Action Modify - * Object, with IPv4 capability. - */ - /* In case of Stingray the term Modify is used for the 'NAT - * action'. Action builder is leveraged to fill in the NAT - * object which then can be referenced by the action - * record. - */ - CFA_P58_ACT_OBJ_TYPE_MODIFY_IPV4_SRAM, - /** Select this type to build a SRAM Action Source - * Property Object. - */ - /* In case of Stingray this is not a 'pure' action record. - * Action builder is leveraged to full in the Source Property - * object which can then be referenced by the action - * record. - */ - CFA_P58_ACT_OBJ_TYPE_SRC_PROP_SRAM, - /** Select this type to build a SRAM Action Statistics - * Object - */ - CFA_P58_ACT_OBJ_TYPE_STAT_SRAM, - } obj_type; - - /** Action Control - * - * Controls the internals of the Action Template - * - * act is valid when: - * (obj_type == CFA_P58_ACT_OBJ_TYPE_ACT) - */ - /* - * Stat and encap are always inline for EEM as table scope - * allocation does not allow for separate Stats allocation, - * but has the xx_inline flags as to be forward compatible - * with Stingray 2, always treated as TRUE. - */ - struct { - /** Set to CFA_HCAPI_TRUE to enable statistics - */ - uint8_t stat_enable; - /** Set to CFA_HCAPI_TRUE to enable statistics to be inlined - */ - uint8_t stat_inline; - - /** Set to CFA_HCAPI_TRUE to enable encapsulation - */ - uint8_t encap_enable; - /** Set to CFA_HCAPI_TRUE to enable encapsulation to be inlined - */ - uint8_t encap_inline; - } act; - - /** Modify Setting - * - * Controls the type of the Modify Action the template is - * describing - * - * modify is valid when: - * (obj_type == CFA_P58_ACT_OBJ_TYPE_MODIFY_SRAM) - */ - enum { - /** Set to enable Modify of Source IPv4 Address - */ - CFA_P58_MR_REPLACE_SOURCE_IPV4 = 0, - /** Set to enable Modify of Destination IPv4 Address - */ - CFA_P58_MR_REPLACE_DEST_IPV4 - } modify; - - /** Encap Control - * Controls the type of encapsulation the template is - * describing - * - * encap is valid when: - * ((obj_type == CFA_P58_ACT_OBJ_TYPE_ACT) && - * act.encap_enable) || - * ((obj_type == CFA_P58_ACT_OBJ_TYPE_SRC_PROP_SRAM) - */ - struct { - /* Direction is required as Stingray Encap on RX is - * limited to l2 and VTAG only. - */ - /** Receive or Transmit direction - */ - uint8_t direction; - /** Set to CFA_HCAPI_TRUE to enable L2 capability in the - * template - */ - uint8_t l2_enable; - /** vtag controls the Encap Vector - VTAG Encoding, 4 bits - * - *
    - *
  • CFA_P58_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN - * Tags applied - *
  • CFA_P58_ACT_ENCAP_VTAGS_PUSH_1, adds capability to - * set 1 VLAN Tag. Action Template compile adds - * the following field to the action object - * ::TF_ER_VLAN1 - *
  • CFA_P58_ACT_ENCAP_VTAGS_PUSH_2, adds capability to - * set 2 VLAN Tags. Action Template compile adds - * the following fields to the action object - * ::TF_ER_VLAN1 and ::TF_ER_VLAN2 - *
- */ - enum { CFA_P58_ACT_ENCAP_VTAGS_PUSH_0 = 0, - CFA_P58_ACT_ENCAP_VTAGS_PUSH_1, - CFA_P58_ACT_ENCAP_VTAGS_PUSH_2 } vtag; - - /* - * The remaining fields are NOT supported when - * direction is RX and ((obj_type == - * CFA_P58_ACT_OBJ_TYPE_ACT) && act.encap_enable). - * ab_compile_layout will perform the checking and - * skip remaining fields. - */ - /** L3 Encap controls the Encap Vector - L3 Encoding, - * 3 bits. Defines the type of L3 Encapsulation the - * template is describing. - *
    - *
  • CFA_P58_ACT_ENCAP_L3_NONE, default, no L3 - * Encapsulation processing. - *
  • CFA_P58_ACT_ENCAP_L3_IPV4, enables L3 IPv4 - * Encapsulation. - *
  • CFA_P58_ACT_ENCAP_L3_IPV6, enables L3 IPv6 - * Encapsulation. - *
  • CFA_P58_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS - * 8847 Encapsulation. - *
  • CFA_P58_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS - * 8848 Encapsulation. - *
- */ - enum { - /** Set to disable any L3 encapsulation - * processing, default - */ - CFA_P58_ACT_ENCAP_L3_NONE = 0, - /** Set to enable L3 IPv4 encapsulation - */ - CFA_P58_ACT_ENCAP_L3_IPV4 = 4, - /** Set to enable L3 IPv6 encapsulation - */ - CFA_P58_ACT_ENCAP_L3_IPV6 = 5, - /** Set to enable L3 MPLS 8847 encapsulation - */ - CFA_P58_ACT_ENCAP_L3_MPLS_8847 = 6, - /** Set to enable L3 MPLS 8848 encapsulation - */ - CFA_P58_ACT_ENCAP_L3_MPLS_8848 = 7 - } l3; - -#define CFA_P58_ACT_ENCAP_MAX_MPLS_LABELS 8 - /** 1-8 labels, valid when - * (l3 == CFA_P58_ACT_ENCAP_L3_MPLS_8847) || - * (l3 == CFA_P58_ACT_ENCAP_L3_MPLS_8848) - * - * MAX number of MPLS Labels 8. - */ - uint8_t l3_num_mpls_labels; - - /** Set to CFA_HCAPI_TRUE to enable L4 capability in the - * template. - * - * CFA_HCAPI_TRUE adds ::TF_EN_UDP_SRC_PORT and - * ::TF_EN_UDP_DST_PORT to the template. - */ - uint8_t l4_enable; - - /** Tunnel Encap controls the Encap Vector - Tunnel - * Encap, 3 bits. Defines the type of Tunnel - * encapsulation the template is describing - *
    - *
  • CFA_P58_ACT_ENCAP_TNL_NONE, default, no Tunnel - * Encapsulation processing. - *
  • CFA_P58_ACT_ENCAP_TNL_GENERIC_FULL - *
  • CFA_P58_ACT_ENCAP_TNL_VXLAN. NOTE: Expects - * l4_enable set to CFA_P58_TRUE; - *
  • CFA_P58_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable - * set to CFA_P58_TRUE; - *
  • CFA_P58_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if - * l4_enable set to CFA_HCAPI_FALSE. - *
  • CFA_P58_ACT_ENCAP_TNL_GRE.NOTE: only valid if - * l4_enable set to CFA_HCAPI_FALSE. - *
  • CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TL4 - *
  • CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TNL - *
- */ - enum { - /** Set to disable Tunnel header encapsulation - * processing, default - */ - CFA_P58_ACT_ENCAP_TNL_NONE = 0, - /** Set to enable Tunnel Generic Full header - * encapsulation - */ - CFA_P58_ACT_ENCAP_TNL_GENERIC_FULL, - /** Set to enable VXLAN header encapsulation - */ - CFA_P58_ACT_ENCAP_TNL_VXLAN, - /** Set to enable NGE (VXLAN2) header encapsulation - */ - CFA_P58_ACT_ENCAP_TNL_NGE, - /** Set to enable NVGRE header encapsulation - */ - CFA_P58_ACT_ENCAP_TNL_NVGRE, - /** Set to enable GRE header encapsulation - */ - CFA_P58_ACT_ENCAP_TNL_GRE, - /** Set to enable Generic header after Tunnel - * L4 encapsulation - */ - CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TL4, - /** Set to enable Generic header after Tunnel - * encapsulation - */ - CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TNL - } tnl; - - /** Number of bytes of generic tunnel header, - * valid when - * (tnl == CFA_P58_ACT_ENCAP_TNL_GENERIC_FULL) || - * (tnl == CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) || - * (tnl == CFA_P58_ACT_ENCAP_TNL_GENERIC_AFTER_TNL) - */ - uint8_t tnl_generic_size; - /** Number of 32b words of nge options, - * valid when - * (tnl == CFA_P58_ACT_ENCAP_TNL_NGE) - */ - uint8_t tnl_nge_op_len; - /* Currently not planned */ - /* Custom Header */ - /* uint8_t custom_enable; */ - } encap; -}; - /** * Enumeration of SRAM entry types, used for allocation of * fixed SRAM entities. The memory model for CFA HCAPI diff --git a/drivers/net/bnxt/tf_core/hwrm_tf.h b/drivers/net/bnxt/tf_core/hwrm_tf.h deleted file mode 100644 index 9cc9a1435c..0000000000 --- a/drivers/net/bnxt/tf_core/hwrm_tf.h +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ -#ifndef _HWRM_TF_H_ -#define _HWRM_TF_H_ - -#include "tf_core.h" - -typedef enum tf_type { - TF_TYPE_TRUFLOW, - TF_TYPE_LAST = TF_TYPE_TRUFLOW, -} tf_type_t; - -typedef enum tf_subtype { - HWRM_TFT_GET_GLOBAL_CFG = 821, - HWRM_TFT_SET_GLOBAL_CFG = 822, - HWRM_TFT_TBL_TYPE_BULK_GET = 825, - HWRM_TFT_IF_TBL_SET = 827, - HWRM_TFT_IF_TBL_GET = 828, - TF_SUBTYPE_LAST = HWRM_TFT_IF_TBL_GET, -} tf_subtype_t; - -/* Request and Response compile time checking */ -/* u32_t tlv_req_value[26]; */ -#define TF_MAX_REQ_SIZE 104 -/* u32_t tlv_resp_value[170]; */ -#define TF_MAX_RESP_SIZE 680 - -/* Use this to allocate/free any kind of - * indexes over HWRM and fill the parms pointer - */ -#define TF_BULK_RECV 128 -#define TF_BULK_SEND 16 - -/* EM Key value */ -#define TF_DEV_DATA_TYPE_TF_EM_RULE_INSERT_KEY_DATA 0x2e30UL -/* EM Key value */ -#define TF_DEV_DATA_TYPE_TF_EM_RULE_DELETE_KEY_DATA 0x2e40UL -/* L2 Context DMA Address Type */ -#define TF_DEV_DATA_TYPE_TF_L2_CTX_DMA_ADDR 0x2fe0UL -/* L2 Context Entry */ -#define TF_DEV_DATA_TYPE_TF_L2_CTX_ENTRY 0x2fe1UL -/* Prof tcam DMA Address Type */ -#define TF_DEV_DATA_TYPE_TF_PROF_TCAM_DMA_ADDR 0x3030UL -/* Prof tcam Entry */ -#define TF_DEV_DATA_TYPE_TF_PROF_TCAM_ENTRY 0x3031UL -/* WC DMA Address Type */ -#define TF_DEV_DATA_TYPE_TF_WC_DMA_ADDR 0x30d0UL -/* WC Entry */ -#define TF_DEV_DATA_TYPE_TF_WC_ENTRY 0x30d1UL -/* SPIF DFLT L2 CTXT Entry */ -#define TF_DEV_DATA_TYPE_SPIF_DFLT_L2_CTXT 0x3131UL -/* PARIF DFLT ACT REC PTR Entry */ -#define TF_DEV_DATA_TYPE_PARIF_DFLT_ACT_REC 0x3132UL -/* PARIF ERR DFLT ACT REC PTR Entry */ -#define TF_DEV_DATA_TYPE_PARIF_ERR_DFLT_ACT_REC 0x3133UL -/* ILT Entry */ -#define TF_DEV_DATA_TYPE_ILT 0x3134UL -/* VNIC SVIF entry */ -#define TF_DEV_DATA_TYPE_VNIC_SVIF 0x3135UL -/* Action Data */ -#define TF_DEV_DATA_TYPE_TF_ACTION_DATA 0x3170UL -#define TF_DEV_DATA_TYPE_LAST TF_DEV_DATA_TYPE_TF_ACTION_DATA - -#define TF_BITS2BYTES(x) (((x) + 7) >> 3) -#define TF_BITS2BYTES_WORD_ALIGN(x) ((((x) + 31) >> 5) * 4) -#define TF_BITS2BYTES_64B_WORD_ALIGN(x) ((((x) + 63) >> 6) * 8) - -struct tf_set_global_cfg_input; -struct tf_get_global_cfg_input; -struct tf_get_global_cfg_output; -struct tf_tbl_type_bulk_get_input; -struct tf_tbl_type_bulk_get_output; -struct tf_if_tbl_set_input; -struct tf_if_tbl_get_input; -struct tf_if_tbl_get_output; -/* Input params for global config set */ -typedef struct tf_set_global_cfg_input { - /* Session Id */ - uint32_t fw_session_id; - /* flags */ - uint32_t flags; - /* When set to 0, indicates the query apply to RX */ -#define TF_SET_GLOBAL_CFG_INPUT_FLAGS_DIR_RX (0x0) - /* When set to 1, indicates the query apply to TX */ -#define TF_SET_GLOBAL_CFG_INPUT_FLAGS_DIR_TX (0x1) - /* Config type */ - uint32_t type; - /* Offset of the type */ - uint32_t offset; - /* Size of the data to set in bytes */ - uint16_t size; - /* Data to set */ - uint8_t data[TF_BULK_SEND]; -} tf_set_global_cfg_input_t, *ptf_set_global_cfg_input_t; - -/* Input params for global config to get */ -typedef struct tf_get_global_cfg_input { - /* Session Id */ - uint32_t fw_session_id; - /* flags */ - uint32_t flags; - /* When set to 0, indicates the query apply to RX */ -#define TF_GET_GLOBAL_CFG_INPUT_FLAGS_DIR_RX (0x0) - /* When set to 1, indicates the query apply to TX */ -#define TF_GET_GLOBAL_CFG_INPUT_FLAGS_DIR_TX (0x1) - /* Config to retrieve */ - uint32_t type; - /* Offset to retrieve */ - uint32_t offset; - /* Size of the data to set in bytes */ - uint16_t size; -} tf_get_global_cfg_input_t, *ptf_get_global_cfg_input_t; - -/* Output params for global config */ -typedef struct tf_get_global_cfg_output { - /* Size of the total data read in bytes */ - uint16_t size; - /* Data to get */ - uint8_t data[TF_BULK_SEND]; -} tf_get_global_cfg_output_t, *ptf_get_global_cfg_output_t; - -/* Input params for table type get */ -typedef struct tf_tbl_type_bulk_get_input { - /* Session Id */ - uint32_t fw_session_id; - /* flags */ - uint32_t flags; - /* When set to 0, indicates the get apply to RX */ -#define TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX (0x0) - /* When set to 1, indicates the get apply to TX */ -#define TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX (0x1) - /* When set to 1, indicates the clear entry on read */ -#define TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ (0x2) - /* Type of the object to set */ - uint32_t type; - /* Starting index to get from */ - uint32_t start_index; - /* Number of entries to get */ - uint32_t num_entries; - /* Host memory where data will be stored */ - uint64_t host_addr; -} tf_tbl_type_bulk_get_input_t, *ptf_tbl_type_bulk_get_input_t; - -/* Output params for table type get */ -typedef struct tf_tbl_type_bulk_get_output { - /* Size of the total data read in bytes */ - uint16_t size; -} tf_tbl_type_bulk_get_output_t, *ptf_tbl_type_bulk_get_output_t; - -/* Input params for if tbl set */ -typedef struct tf_if_tbl_set_input { - /* Session Id */ - uint32_t fw_session_id; - /* flags */ - uint16_t flags; - /* When set to 0, indicates the query apply to RX */ -#define TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX (0x0) - /* When set to 1, indicates the query apply to TX */ -#define TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX (0x1) - /* if table type */ - uint16_t tf_if_tbl_type; - /* index of table entry */ - uint16_t idx; - /* size of the data write to table entry */ - uint32_t data_sz_in_bytes; - /* data to write into table entry */ - uint32_t data[2]; -} tf_if_tbl_set_input_t, *ptf_if_tbl_set_input_t; - -/* Input params for if tbl get */ -typedef struct tf_if_tbl_get_input { - /* Session Id */ - uint32_t fw_session_id; - /* flags */ - uint16_t flags; - /* When set to 0, indicates the query apply to RX */ -#define TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX (0x0) - /* When set to 1, indicates the query apply to TX */ -#define TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX (0x1) - /* if table type */ - uint16_t tf_if_tbl_type; - /* size of the data get from table entry */ - uint32_t data_sz_in_bytes; - /* index of table entry */ - uint16_t idx; -} tf_if_tbl_get_input_t, *ptf_if_tbl_get_input_t; - -/* output params for if tbl get */ -typedef struct tf_if_tbl_get_output { - /* Value read from table entry */ - uint32_t data[2]; -} tf_if_tbl_get_output_t, *ptf_if_tbl_get_output_t; - -#endif /* _HWRM_TF_H_ */ diff --git a/drivers/net/bnxt/tf_core/lookup3.h b/drivers/net/bnxt/tf_core/lookup3.h index b1fd2cd436..743c4d9c4f 100644 --- a/drivers/net/bnxt/tf_core/lookup3.h +++ b/drivers/net/bnxt/tf_core/lookup3.h @@ -122,7 +122,7 @@ static inline uint32_t hashword(const uint32_t *k, size_t length, uint32_t initval) { uint32_t a, b, c; - int index = 12; + int index = length - 1; /* Set up the internal state */ a = 0xdeadbeef + (((uint32_t)length) << 2) + initval; diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 573fa0b1ed..9b8677caac 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -18,7 +18,6 @@ #include "bnxt.h" #include "rand.h" #include "tf_common.h" -#include "hwrm_tf.h" #include "tf_ext_flow_handle.h" int diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index fcba492dc5..7b26b58000 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -10,7 +10,7 @@ #include #include #include -#include "hcapi/cfa/hcapi_cfa_defs.h" +#include "hcapi_cfa_defs.h" #include "tf_project.h" /** @@ -43,6 +43,29 @@ enum tf_mem { TF_MEM_MAX }; +/** + * External memory control channel type + */ +enum tf_ext_mem_chan_type { + /** + * Direct memory write(Wh+/SR) + */ + TF_EXT_MEM_CHAN_TYPE_DIRECT = 0, + /** + * Ring interface MPC + */ + TF_EXT_MEM_CHAN_TYPE_RING_IF, + /** + * Use HWRM message to firmware + */ + TF_EXT_MEM_CHAN_TYPE_FW, + /** + * Use ring_if message to firmware + */ + TF_EXT_MEM_CHAN_TYPE_RING_IF_FW, + TF_EXT_MEM_CHAN_TYPE_MAX +}; + /** * EEM record AR helper * @@ -149,7 +172,6 @@ enum tf_device_type { TF_DEVICE_TYPE_WH = 0, /**< Whitney+ */ TF_DEVICE_TYPE_SR, /**< Stingray */ TF_DEVICE_TYPE_THOR, /**< Thor */ - TF_DEVICE_TYPE_SR2, /**< Stingray2 */ TF_DEVICE_TYPE_MAX /**< Maximum */ }; @@ -182,40 +204,39 @@ enum tf_module_type { */ enum tf_identifier_type { /** - * WH/SR/TH/SR2 + * WH/SR/TH * The L2 Context is returned from the L2 Ctxt TCAM lookup * and can be used in WC TCAM or EM keys to virtualize further * lookups. */ TF_IDENT_TYPE_L2_CTXT_HIGH, /** - * WH/SR/TH/SR2 + * WH/SR/TH * The L2 Context is returned from the L2 Ctxt TCAM lookup * and can be used in WC TCAM or EM keys to virtualize further * lookups. */ TF_IDENT_TYPE_L2_CTXT_LOW, /** - * WH/SR/TH/SR2 + * WH/SR/TH * The WC profile func is returned from the L2 Ctxt TCAM lookup * to enable virtualization of the profile TCAM. */ TF_IDENT_TYPE_PROF_FUNC, /** - * WH/SR/TH/SR2 + * WH/SR/TH * The WC profile ID is included in the WC lookup key * to enable virtualization of the WC TCAM hardware. */ TF_IDENT_TYPE_WC_PROF, /** - * WH/SR/TH/SR2 + * WH/SR/TH * The EM profile ID is included in the EM lookup key - * to enable virtualization of the EM hardware. (not required for SR2 - * as it has table scope) + * to enable virtualization of the EM hardware. */ TF_IDENT_TYPE_EM_PROF, /** - * TH/SR2 + * TH * The L2 func is included in the ILT result and from recycling to * enable virtualization of further lookups. */ @@ -273,23 +294,15 @@ enum tf_tbl_type { TF_TBL_TYPE_MIRROR_CONFIG, /** (Future) UPAR */ TF_TBL_TYPE_UPAR, - /** (Future) SR2 Epoch 0 table */ - TF_TBL_TYPE_EPOCH0, - /** (Future) SR2 Epoch 1 table */ - TF_TBL_TYPE_EPOCH1, - /** (Future) TH/SR2 Metadata */ + /** (Future) TH Metadata */ TF_TBL_TYPE_METADATA, - /** (Future) TH/SR2 CT State */ + /** (Future) TH CT State */ TF_TBL_TYPE_CT_STATE, - /** (Future) TH/SR2 Range Profile */ + /** (Future) TH Range Profile */ TF_TBL_TYPE_RANGE_PROF, - /** (Future) SR2 Range Entry */ - TF_TBL_TYPE_RANGE_ENTRY, - /** (Future) SR2 LAG Entry */ - TF_TBL_TYPE_LAG, - /** TH/SR2 EM Flexible Key builder */ + /** TH EM Flexible Key builder */ TF_TBL_TYPE_EM_FKB, - /** TH/SR2 WC Flexible Key builder */ + /** TH WC Flexible Key builder */ TF_TBL_TYPE_WC_FKB, /* External */ @@ -301,14 +314,6 @@ enum tf_tbl_type { * a pool of 64B entries. */ TF_TBL_TYPE_EXT, - /* (Future) SR2 32B External EM Action 32B Pool */ - TF_TBL_TYPE_EXT_32B, - /* (Future) SR2 64B External EM Action 64B Pool */ - TF_TBL_TYPE_EXT_64B, - /* (Future) SR2 96B External EM Action 96B Pool */ - TF_TBL_TYPE_EXT_96B, - /* (Future) SR2 128B External EM Action 128B Pool */ - TF_TBL_TYPE_EXT_128B, TF_TBL_TYPE_MAX }; @@ -969,20 +974,13 @@ struct tf_map_tbl_scope_parms { /** * allocate a table scope * - * On SR2 Firmware will allocate a scope ID. On other devices, the scope - * is a software construct to identify an EEM table. This function will + * The scope is a software construct to identify an EEM table. This function will * divide the hash memory/buckets and records according to the device * device constraints based upon calculations using either the number of flows * requested or the size of memory indicated. Other parameters passed in * determine the configuration (maximum key size, maximum external action record * size). * - * This API will allocate the table region in DRAM, program the PTU page table - * entries, and program the number of static buckets (if SR2) in the RX and TX - * CFAs. Buckets are assumed to start at 0 in the EM memory for the scope. - * Upon successful completion of this API, hash tables are fully initialized and - * ready for entries to be inserted. - * * A single API is used to allocate a common table scope identifier in both * receive and transmit CFA. The scope identifier is common due to nature of * connection tracking sending notifications between RX and TX direction. @@ -1028,7 +1026,7 @@ int tf_map_tbl_scope(struct tf *tfp, * * Firmware checks that the table scope ID is owned by the TruFlow * session, verifies that no references to this table scope remains - * (SR2 ILT) or Profile TCAM entries for either CFA (RX/TX) direction, + * or Profile TCAM entries for either CFA (RX/TX) direction, * then frees the table scope ID. * * Returns success or failure code. @@ -1589,6 +1587,10 @@ struct tf_set_tbl_entry_parms { * [in] Entry size */ uint16_t data_sz_in_bytes; + /** + * [in] External memory channel type to use + */ + enum tf_ext_mem_chan_type chan_type; /** * [in] Entry index to write to */ @@ -1627,6 +1629,10 @@ struct tf_get_tbl_entry_parms { * [in] Entry size */ uint16_t data_sz_in_bytes; + /** + * [in] External memory channel type to use + */ + enum tf_ext_mem_chan_type chan_type; /** * [in] Entry index to read */ @@ -1679,6 +1685,10 @@ struct tf_bulk_get_tbl_entry_parms { * structure for the physical address. */ uint64_t physical_mem_addr; + /** + * [in] External memory channel type to use + */ + enum tf_ext_mem_chan_type chan_type; }; /** @@ -1723,10 +1733,6 @@ struct tf_insert_em_entry_parms { * [in] ID of table scope to use (external only) */ uint32_t tbl_scope_id; - /** - * [in] ID of table interface to use (SR2 only) - */ - uint32_t tbl_if_id; /** * [in] ptr to structure containing key fields */ @@ -1747,6 +1753,10 @@ struct tf_insert_em_entry_parms { * [in] duplicate check flag */ uint8_t dup_check; + /** + * [in] External memory channel type to use + */ + enum tf_ext_mem_chan_type chan_type; /** * [out] Flow handle value for the inserted entry. This is encoded * as the entries[4]:bucket[2]:hashId[1]:hash[14] @@ -1775,19 +1785,14 @@ struct tf_delete_em_entry_parms { * [in] ID of table scope to use (external only) */ uint32_t tbl_scope_id; - /** - * [in] ID of table interface to use (SR2 only) - */ - uint32_t tbl_if_id; - /** - * [in] epoch group IDs of entry to delete - * 2 element array with 2 ids. (SR2 only) - */ - uint16_t *epochs; /** * [out] The index of the entry */ uint16_t index; + /** + * [in] External memory channel type to use + */ + enum tf_ext_mem_chan_type chan_type; /** * [in] structure containing flow delete handle information */ @@ -1809,10 +1814,6 @@ struct tf_search_em_entry_parms { * [in] ID of table scope to use (external only) */ uint32_t tbl_scope_id; - /** - * [in] ID of table interface to use (SR2 only) - */ - uint32_t tbl_if_id; /** * [in] ptr to structure containing key fields */ @@ -1830,10 +1831,9 @@ struct tf_search_em_entry_parms { */ uint16_t em_record_sz_in_bits; /** - * [in] epoch group IDs of entry to lookup - * 2 element array with 2 ids. (SR2 only) + * [in] External memory channel type to use */ - uint16_t *epochs; + enum tf_ext_mem_chan_type chan_type; /** * [in] ptr to structure containing flow delete handle */ @@ -1858,9 +1858,6 @@ struct tf_search_em_entry_parms { * This API inserts an exact match entry into DRAM EM table memory of the * specified direction and table scope. * - * When inserting an entry into an exact match table, the TruFlow library may - * need to allocate a dynamic bucket for the entry (SR2 only). - * * The insertion of duplicate entries in an EM table is not permitted. If a * TruFlow application can guarantee that it will never insert duplicates, it * can disable duplicate checking by passing a zero value in the dup_check @@ -2040,9 +2037,9 @@ enum tf_if_tbl_type { TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, /** Default Error Profile TCAM Miss Action Record Pointer Table */ TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - /** SR2 Ingress lookup table */ + /** Ingress lookup table */ TF_IF_TBL_TYPE_ILT, - /** SR2 VNIC/SVIF Properties Table */ + /** VNIC/SVIF Properties Table */ TF_IF_TBL_TYPE_VSPT, TF_IF_TBL_TYPE_MAX }; diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 61b3746d8b..9e71c04bf2 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -487,7 +487,7 @@ tf_dev_bind_p58(struct tf *tfp, * - (-EINVAL) on failure. */ static int - tf_dev_unbind_p58(struct tf *tfp) +tf_dev_unbind_p58(struct tf *tfp) { int rc = 0; bool fail = false; diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index ee283ce29d..a73ba3cd70 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -14,92 +14,117 @@ struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, + 0, 0, 0 }, [TF_IDENT_TYPE_L2_CTXT_LOW] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW, + 0, 0, 0 }, [TF_IDENT_TYPE_PROF_FUNC] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC, + 0, 0, 0 }, [TF_IDENT_TYPE_WC_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID, + 0, 0, 0 }, [TF_IDENT_TYPE_EM_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID, + 0, 0, 0 }, }; struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, + 0, 0, 0 }, [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, + 0, 0, 0 }, [TF_TCAM_TBL_TYPE_PROF_TCAM] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM, + 0, 0, 0 }, [TF_TCAM_TBL_TYPE_WC_TCAM] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM, + 0, 0, 0 }, [TF_TCAM_TBL_TYPE_SP_TCAM] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM, + 0, 0, 0 }, }; struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { [TF_TBL_TYPE_FULL_ACT_RECORD] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0, 0 }, [TF_TBL_TYPE_MCAST_GROUPS] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0, 0 }, [TF_TBL_TYPE_ACT_ENCAP_8B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0, 0 }, [TF_TBL_TYPE_ACT_ENCAP_16B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0, 0 }, [TF_TBL_TYPE_ACT_ENCAP_64B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0, 0 }, [TF_TBL_TYPE_ACT_SP_SMAC] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0, 0 }, [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0, 0 }, [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0, 0 }, [TF_TBL_TYPE_ACT_STATS_64] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0, 0 }, [TF_TBL_TYPE_ACT_MODIFY_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0, 0 }, [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0, 0 }, [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0, 0 }, [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0, 0 }, }; struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_TBL_SCOPE] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE, + 0, 0, 0 }, }; struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_EM_RECORD] = { - TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC + TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC, + 0, 0, 0 }, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 4d7a78e52c..b5e2598cb6 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -14,55 +14,70 @@ struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH, + 0, 0, 0 }, [TF_IDENT_TYPE_L2_CTXT_LOW] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW, + 0, 0, 0 }, [TF_IDENT_TYPE_PROF_FUNC] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC, + 0, 0, 0 }, [TF_IDENT_TYPE_WC_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID, + 0, 0, 0 }, [TF_IDENT_TYPE_EM_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID, + 0, 0, 0 }, }; struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = { [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, + 0, 0, 0 }, [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, + 0, 0, 0 }, [TF_TCAM_TBL_TYPE_PROF_TCAM] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM, + 0, 0, 0 }, [TF_TCAM_TBL_TYPE_WC_TCAM] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM, + 0, 0, 0 }, [TF_TCAM_TBL_TYPE_VEB_TCAM] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM, + 0, 0, 0 }, }; struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { [TF_TBL_TYPE_EM_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0, 0 }, [TF_TBL_TYPE_WC_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0, 0 }, [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0, 0 }, [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0, 0 }, [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0, 0 }, /* Policy - ARs in bank 1 */ [TF_TBL_TYPE_FULL_ACT_RECORD] = { @@ -167,7 +182,8 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_EM_RECORD] = { - TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC + TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC, + 0, 0, 0 }, }; diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 4de9e42cbc..2de1862cd9 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -9,7 +9,9 @@ #include "tf_core.h" #include "tf_session.h" -#include "hcapi/cfa/hcapi_cfa_defs.h" +#include "tf_em_common.h" + +#include "hcapi_cfa_defs.h" #define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */ #define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */ diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index d8278f1ce1..4dc3c86b57 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -19,18 +19,13 @@ #include "tfp.h" #include "tf_device.h" #include "tf_ext_flow_handle.h" -#include "cfa_resource_types.h" +#include "hcapi_cfa.h" #include "bnxt.h" /* Number of pointers per page_size */ #define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *)) -/** - * EM DBs. - */ -void *eem_db[TF_DIR_MAX]; - /** * Init flag, set on bind and cleared on unbind */ @@ -41,36 +36,7 @@ static uint8_t init; */ static enum tf_mem_type mem_type; -/** Table scope array */ -struct tf_tbl_scope_cb tbl_scopes[TF_NUM_TBL_SCOPE]; - /* API defined in tf_em.h */ -struct tf_tbl_scope_cb * -tbl_scope_cb_find(uint32_t tbl_scope_id) -{ - int i; - struct tf_rm_is_allocated_parms parms = { 0 }; - int allocated; - - /* Check that id is valid */ - parms.rm_db = eem_db[TF_DIR_RX]; - parms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; - parms.index = tbl_scope_id; - parms.allocated = &allocated; - - i = tf_rm_is_allocated(&parms); - - if (i < 0 || allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) - return NULL; - - for (i = 0; i < TF_NUM_TBL_SCOPE; i++) { - if (tbl_scopes[i].tbl_scope_id == tbl_scope_id) - return &tbl_scopes[i]; - } - - return NULL; -} - int tf_create_tbl_pool_external(enum tf_dir dir, struct tf_tbl_scope_cb *tbl_scope_cb, @@ -158,6 +124,44 @@ tf_destroy_tbl_pool_external(enum tf_dir dir, tfp_free(ext_act_pool_mem); } +/** + * Looks up table scope control block using tbl_scope_id from tf_session. + * + * [in] tfp + * Pointer to Truflow Handle + * [in] tbl_scope_id + * table scope id + * + * Return: + * - Pointer to the tf_tbl_scope_cb, if found. + * - (NULL) on failure, not found. + */ +struct tf_tbl_scope_cb * +tf_em_ext_common_tbl_scope_find(struct tf *tfp, + uint32_t tbl_scope_id) +{ + int rc; + struct em_ext_db *ext_db; + void *ext_ptr = NULL; + struct tf_tbl_scope_cb *tbl_scope_cb = NULL; + struct ll_entry *entry; + + rc = tf_session_get_em_ext_db(tfp, &ext_ptr); + if (rc) + return NULL; + + ext_db = (struct em_ext_db *)ext_ptr; + + for (entry = ext_db->tbl_scope_ll.head; entry != NULL; + entry = entry->next) { + tbl_scope_cb = (struct tf_tbl_scope_cb *)entry; + if (tbl_scope_cb->tbl_scope_id == tbl_scope_id) + return tbl_scope_cb; + } + + return NULL; +} + /** * Allocate External Tbl entry from the scope pool. * @@ -182,16 +186,14 @@ tf_tbl_ext_alloc(struct tf *tfp, TF_CHECK_PARMS2(tfp, parms); - /* Get the pool info from the table scope - */ - tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id); - + tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); if (tbl_scope_cb == NULL) { TFP_DRV_LOG(ERR, "%s, table scope not allocated\n", tf_dir_2_str(parms->dir)); return -EINVAL; } + pool = &tbl_scope_cb->ext_act_pool[parms->dir]; /* Allocate an element @@ -237,10 +239,7 @@ tf_tbl_ext_free(struct tf *tfp, TF_CHECK_PARMS2(tfp, parms); - /* Get the pool info from the table scope - */ - tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id); - + tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); if (tbl_scope_cb == NULL) { TFP_DRV_LOG(ERR, "%s, table scope error\n", @@ -646,7 +645,18 @@ tf_em_validate_num_entries(struct tf_tbl_scope_cb *tbl_scope_cb, tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_RECORD_TABLE].entry_size = parms->rx_max_action_entry_sz_in_bits / 8; - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_EFC_TABLE].num_entries = 0; + tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_EFC_TABLE].num_entries = + 0; + + tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_ACTION_TABLE].num_entries = + parms->rx_num_flows_in_k * TF_KILOBYTE; + tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_ACTION_TABLE].entry_size = + parms->rx_max_action_entry_sz_in_bits / 8; + + tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_EM_LKUP_TABLE].num_entries = + parms->rx_num_flows_in_k * TF_KILOBYTE; + tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_EM_LKUP_TABLE].entry_size = + parms->rx_max_key_sz_in_bits / 8; /* Tx */ tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_KEY0_TABLE].num_entries = @@ -664,7 +674,18 @@ tf_em_validate_num_entries(struct tf_tbl_scope_cb *tbl_scope_cb, tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_RECORD_TABLE].entry_size = parms->tx_max_action_entry_sz_in_bits / 8; - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_EFC_TABLE].num_entries = 0; + tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_EFC_TABLE].num_entries = + 0; + + tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_ACTION_TABLE].num_entries = + parms->rx_num_flows_in_k * TF_KILOBYTE; + tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_ACTION_TABLE].entry_size = + parms->tx_max_action_entry_sz_in_bits / 8; + + tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_EM_LKUP_TABLE].num_entries = + parms->rx_num_flows_in_k * TF_KILOBYTE; + tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_EM_LKUP_TABLE].entry_size = + parms->tx_max_key_sz_in_bits / 8; return 0; } @@ -747,10 +768,10 @@ tf_insert_eem_entry(struct tf_dev_info *dev, key_obj.data = (uint8_t *)&key_entry; key_obj.size = TF_P4_EM_KEY_RECORD_SIZE; - rc = hcapi_cfa_key_hw_op(&op, - &key_tbl, - &key_obj, - &key_loc); + rc = cfa_p4_devops.hcapi_cfa_key_hw_op(&op, + &key_tbl, + &key_obj, + &key_loc); if (rc == 0) { table_type = TF_KEY0_TABLE; @@ -761,10 +782,10 @@ tf_insert_eem_entry(struct tf_dev_info *dev, (uint8_t *)&tbl_scope_cb->em_ctx_info[parms->dir].em_tables[TF_KEY1_TABLE]; key_obj.offset = index * TF_P4_EM_KEY_RECORD_SIZE; - rc = hcapi_cfa_key_hw_op(&op, - &key_tbl, - &key_obj, - &key_loc); + rc = cfa_p4_devops.hcapi_cfa_key_hw_op(&op, + &key_tbl, + &key_obj, + &key_loc); if (rc != 0) return rc; @@ -781,7 +802,7 @@ tf_insert_eem_entry(struct tf_dev_info *dev, TF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle, 0, 0, - TF_FLAGS_FLOW_HANDLE_EXTERNAL, + 0, index, 0, table_type); @@ -826,10 +847,10 @@ tf_delete_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, key_obj.data = NULL; key_obj.size = TF_P4_EM_KEY_RECORD_SIZE; - rc = hcapi_cfa_key_hw_op(&op, - &key_tbl, - &key_obj, - &key_loc); + rc = cfa_p4_devops.hcapi_cfa_key_hw_op(&op, + &key_tbl, + &key_obj, + &key_loc); if (!rc) return rc; @@ -844,7 +865,7 @@ tf_delete_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, * -EINVAL - Error */ int -tf_em_insert_ext_entry(struct tf *tfp __rte_unused, +tf_em_insert_ext_entry(struct tf *tfp, struct tf_insert_em_entry_parms *parms) { int rc; @@ -852,7 +873,7 @@ tf_em_insert_ext_entry(struct tf *tfp __rte_unused, struct tf_session *tfs; struct tf_dev_info *dev; - tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id); + tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); if (tbl_scope_cb == NULL) { TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb\n"); return -EINVAL; @@ -881,12 +902,12 @@ tf_em_insert_ext_entry(struct tf *tfp __rte_unused, * -EINVAL - Error */ int -tf_em_delete_ext_entry(struct tf *tfp __rte_unused, +tf_em_delete_ext_entry(struct tf *tfp, struct tf_delete_em_entry_parms *parms) { struct tf_tbl_scope_cb *tbl_scope_cb; - tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id); + tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); if (tbl_scope_cb == NULL) { TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb\n"); return -EINVAL; @@ -904,6 +925,8 @@ tf_em_ext_common_bind(struct tf *tfp, int i; struct tf_rm_create_db_parms db_cfg = { 0 }; uint8_t db_exists = 0; + struct em_ext_db *ext_db; + struct tfp_calloc_parms cparms; TF_CHECK_PARMS2(tfp, parms); @@ -913,6 +936,21 @@ tf_em_ext_common_bind(struct tf *tfp, return -EINVAL; } + cparms.nitems = 1; + cparms.size = sizeof(struct em_ext_db); + cparms.alignment = 0; + if (tfp_calloc(&cparms) != 0) { + TFP_DRV_LOG(ERR, "em_ext_db alloc error %s\n", + strerror(ENOMEM)); + return -ENOMEM; + } + + ext_db = cparms.mem_va; + ll_init(&ext_db->tbl_scope_ll); + for (i = 0; i < TF_DIR_MAX; i++) + ext_db->eem_db[i] = NULL; + tf_session_set_em_ext_db(tfp, ext_db); + db_cfg.module = TF_MODULE_TYPE_EM; db_cfg.num_elements = parms->num_elements; db_cfg.cfg = parms->cfg; @@ -927,7 +965,7 @@ tf_em_ext_common_bind(struct tf *tfp, if (db_cfg.alloc_cnt[TF_EM_TBL_TYPE_TBL_SCOPE] == 0) continue; - db_cfg.rm_db = &eem_db[i]; + db_cfg.rm_db = (void *)&ext_db->eem_db[i]; rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, @@ -953,6 +991,13 @@ tf_em_ext_common_unbind(struct tf *tfp) int rc; int i; struct tf_rm_free_db_parms fparms = { 0 }; + struct em_ext_db *ext_db = NULL; + struct tf_session *tfs = NULL; + struct tf_dev_info *dev; + struct ll_entry *entry; + struct tf_tbl_scope_cb *tbl_scope_cb = NULL; + void *ext_ptr = NULL; + struct tf_free_tbl_scope_parms tparms = { 0 }; TF_CHECK_PARMS1(tfp); @@ -963,16 +1008,62 @@ tf_em_ext_common_unbind(struct tf *tfp) return 0; } + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = tf_session_get_em_ext_db(tfp, &ext_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + ext_db = (struct em_ext_db *)ext_ptr; + + entry = ext_db->tbl_scope_ll.head; + while (entry != NULL) { + tbl_scope_cb = (struct tf_tbl_scope_cb *)entry; + entry = entry->next; + tparms.tbl_scope_id = tbl_scope_cb->tbl_scope_id; + + if (dev->ops->tf_dev_free_tbl_scope) { + dev->ops->tf_dev_free_tbl_scope(tfp, &tparms); + } else { + /* should not reach here */ + ll_delete(&ext_db->tbl_scope_ll, &tbl_scope_cb->ll_entry); + tfp_free(tbl_scope_cb); + } + } + for (i = 0; i < TF_DIR_MAX; i++) { + if (ext_db->eem_db[i] == NULL) + continue; + fparms.dir = i; - fparms.rm_db = eem_db[i]; + fparms.rm_db = ext_db->eem_db[i]; rc = tf_rm_free_db(tfp, &fparms); if (rc) return rc; - eem_db[i] = NULL; + ext_db->eem_db[i] = NULL; } + tfp_free(ext_db); + tf_session_set_em_ext_db(tfp, NULL); + init = 0; return 0; @@ -1022,11 +1113,7 @@ int tf_tbl_ext_common_set(struct tf *tfp, return -EINVAL; } - /* Get the table scope control block associated with the - * external pool - */ - tbl_scope_cb = tbl_scope_cb_find(tbl_scope_id); - + tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, tbl_scope_id); if (tbl_scope_cb == NULL) { TFP_DRV_LOG(ERR, "%s, table scope error\n", @@ -1042,10 +1129,10 @@ int tf_tbl_ext_common_set(struct tf *tfp, key_obj.data = parms->data; key_obj.size = parms->data_sz_in_bytes; - rc = hcapi_cfa_key_hw_op(&op, - &key_tbl, - &key_obj, - &key_loc); + rc = cfa_p4_devops.hcapi_cfa_key_hw_op(&op, + &key_tbl, + &key_obj, + &key_loc); return rc; } @@ -1076,14 +1163,6 @@ int tf_em_ext_map_tbl_scope(struct tf *tfp, uint32_t sz_in_bytes = 8; struct tf_dev_info *dev; - tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id); - - if (tbl_scope_cb == NULL) { - TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb tbl_scope_id(%d)\n", - parms->tbl_scope_id); - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -1094,6 +1173,13 @@ int tf_em_ext_map_tbl_scope(struct tf *tfp, if (rc) return rc; + tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); + if (tbl_scope_cb == NULL) { + TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb tbl_scope_id(%d)\n", + parms->tbl_scope_id); + return -EINVAL; + } + if (dev->ops->tf_dev_map_tbl_scope == NULL) { rc = -EOPNOTSUPP; TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_em_common.h b/drivers/net/bnxt/tf_core/tf_em_common.h index 5e55f4e968..7f215adef2 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.h +++ b/drivers/net/bnxt/tf_core/tf_em_common.h @@ -8,7 +8,7 @@ #include "tf_core.h" #include "tf_session.h" - +#include "ll.h" /** * Function to search for table scope control block structure @@ -23,6 +23,53 @@ */ struct tf_tbl_scope_cb *tbl_scope_cb_find(uint32_t tbl_scope_id); +/** + * Table scope control block content + */ +struct tf_em_caps { + uint32_t flags; + uint32_t supported; + uint32_t max_entries_supported; + uint16_t key_entry_size; + uint16_t record_entry_size; + uint16_t efc_entry_size; +}; + +/** + * EEM data + * + * Link list of ext em data allocated and managed by EEM module + * for a TruFlow session. + */ +struct em_ext_db { + struct ll tbl_scope_ll; + struct rm_db *eem_db[TF_DIR_MAX]; +}; + +/** + * Table Scope Control Block + * + * Holds private data for a table scope. + */ +struct tf_tbl_scope_cb { + /** + * Linked list of tbl_scope + */ + struct ll_entry ll_entry; /* For inserting in link list, must be + * first field of struct. + */ + + uint32_t tbl_scope_id; + + /** The pf or parent pf of the vf used for table scope creation + */ + uint16_t pf; + struct hcapi_cfa_em_ctx_mem_info em_ctx_info[TF_DIR_MAX]; + struct tf_em_caps em_caps[TF_DIR_MAX]; + struct stack ext_act_pool[TF_DIR_MAX]; + uint32_t *ext_act_pool_mem[TF_DIR_MAX]; +}; + /** * Create and initialize a stack to use for action entries * @@ -131,4 +178,23 @@ int tf_em_validate_num_entries(struct tf_tbl_scope_cb *tbl_scope_cb, int tf_em_size_table(struct hcapi_cfa_em_table *tbl, uint32_t page_size); + +/** + * Look up table scope control block using tbl_scope_id from + * tf_session + * + * [in] tbl_scope_cb + * Pointer to Truflow Handle + * + * [in] tbl_scope_id + * table scope id + * + * Returns: + * - Pointer to the tf_tbl_scope_cb, if found. + * - (NULL) on failure, not found. + */ +struct tf_tbl_scope_cb * +tf_em_ext_common_tbl_scope_find(struct tf *tfp, + uint32_t tbl_scope_id); + #endif /* _TF_EM_COMMON_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c index 166f397935..869a78e904 100644 --- a/drivers/net/bnxt/tf_core/tf_em_host.c +++ b/drivers/net/bnxt/tf_core/tf_em_host.c @@ -29,13 +29,6 @@ /* Number of pointers per page_size */ #define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *)) -/** - * EM DBs. - */ -extern void *eem_db[TF_DIR_MAX]; - -extern struct tf_tbl_scope_cb tbl_scopes[TF_NUM_TBL_SCOPE]; - /** * Function to free a page table * @@ -367,7 +360,8 @@ tf_em_ctx_reg(struct tf *tfp, } int -tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) +tf_em_ext_alloc(struct tf *tfp, + struct tf_alloc_tbl_scope_parms *parms) { int rc; enum tf_dir dir; @@ -376,30 +370,65 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) struct tf_free_tbl_scope_parms free_parms; struct tf_rm_allocate_parms aparms = { 0 }; struct tf_rm_free_parms fparms = { 0 }; + struct tfp_calloc_parms cparms; + struct tf_session *tfs = NULL; + struct em_ext_db *ext_db = NULL; + void *ext_ptr = NULL; + uint16_t pf; + + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = tf_session_get_em_ext_db(tfp, &ext_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + ext_db = (struct em_ext_db *)ext_ptr; + + rc = tfp_get_pf(tfp, &pf); + if (rc) { + TFP_DRV_LOG(ERR, + "EEM: PF query error rc:%s\n", + strerror(-rc)); + goto cleanup; + } /* Get Table Scope control block from the session pool */ - aparms.rm_db = eem_db[TF_DIR_RX]; + aparms.rm_db = ext_db->eem_db[TF_DIR_RX]; aparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; aparms.index = (uint32_t *)&parms->tbl_scope_id; rc = tf_rm_allocate(&aparms); if (rc) { TFP_DRV_LOG(ERR, "Failed to allocate table scope\n"); - return rc; + goto cleanup; } - tbl_scope_cb = &tbl_scopes[parms->tbl_scope_id]; - tbl_scope_cb->index = parms->tbl_scope_id; - tbl_scope_cb->tbl_scope_id = parms->tbl_scope_id; - - rc = tfp_get_pf(tfp, &tbl_scope_cb->pf); + /* Create tbl_scope, initialize and attach to the session */ + cparms.nitems = 1; + cparms.size = sizeof(struct tf_tbl_scope_cb); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); if (rc) { + /* Log error */ TFP_DRV_LOG(ERR, - "EEM: PF query error rc:%s\n", - strerror(-rc)); + "Failed to allocate session table scope, rc:%s\n", + strerror(-rc)); goto cleanup; } + tbl_scope_cb = cparms.mem_va; + tbl_scope_cb->tbl_scope_id = parms->tbl_scope_id; + tbl_scope_cb->pf = pf; + for (dir = 0; dir < TF_DIR_MAX; dir++) { rc = tf_msg_em_qcaps(tfp, dir, @@ -409,7 +438,7 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) "EEM: Unable to query for EEM capability," " rc:%s\n", strerror(-rc)); - goto cleanup; + goto cleanup_ts; } } @@ -417,7 +446,7 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) * Validate and setup table sizes */ if (tf_em_validate_num_entries(tbl_scope_cb, parms)) - goto cleanup; + goto cleanup_ts; for (dir = 0; dir < TF_DIR_MAX; dir++) { /* @@ -429,7 +458,7 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) "EEM: Unable to register for EEM ctx," " rc:%s\n", strerror(-rc)); - goto cleanup; + goto cleanup_ts; } em_tables = tbl_scope_cb->em_ctx_info[dir].em_tables; @@ -478,19 +507,29 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) } } + /* Insert into session tbl_scope list */ + ll_insert(&ext_db->tbl_scope_ll, &tbl_scope_cb->ll_entry); return 0; cleanup_full: free_parms.tbl_scope_id = parms->tbl_scope_id; + /* Insert into session list prior to ext_free */ + ll_insert(&ext_db->tbl_scope_ll, &tbl_scope_cb->ll_entry); tf_em_ext_free(tfp, &free_parms); return -EINVAL; +cleanup_ts: + tfp_free(tbl_scope_cb); + cleanup: /* Free Table control block */ - fparms.rm_db = eem_db[TF_DIR_RX]; + fparms.rm_db = ext_db->eem_db[TF_DIR_RX]; fparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; fparms.index = parms->tbl_scope_id; - tf_rm_free(&fparms); + rc = tf_rm_free(&fparms); + if (rc) + TFP_DRV_LOG(ERR, "Failed to free table scope\n"); + return -EINVAL; } @@ -501,17 +540,35 @@ tf_em_ext_free(struct tf *tfp, int rc = 0; enum tf_dir dir; struct tf_tbl_scope_cb *tbl_scope_cb; + struct tf_session *tfs; + struct em_ext_db *ext_db = NULL; + void *ext_ptr = NULL; struct tf_rm_free_parms aparms = { 0 }; - tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id); + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n", + strerror(-rc)); + return -EINVAL; + } + + rc = tf_session_get_em_ext_db(tfp, &ext_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + ext_db = (struct em_ext_db *)ext_ptr; + tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); if (tbl_scope_cb == NULL) { TFP_DRV_LOG(ERR, "Table scope error\n"); return -EINVAL; } /* Free Table control block */ - aparms.rm_db = eem_db[TF_DIR_RX]; + aparms.rm_db = ext_db->eem_db[TF_DIR_RX]; aparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; aparms.index = parms->tbl_scope_id; rc = tf_rm_free(&aparms); @@ -534,6 +591,8 @@ tf_em_ext_free(struct tf *tfp, tf_em_ctx_unreg(tfp, tbl_scope_cb, dir); } - tbl_scopes[parms->tbl_scope_id].tbl_scope_id = TF_TBL_SCOPE_INVALID; + /* remove from session list and free tbl_scope */ + ll_delete(&ext_db->tbl_scope_ll, &tbl_scope_cb->ll_entry); + tfp_free(tbl_scope_cb); return rc; } diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index ec4c7890c3..c6eb94bee0 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -9,6 +9,7 @@ #include #include +#include "tf_em_common.h" #include "tf_msg_common.h" #include "tf_device.h" #include "tf_msg.h" @@ -16,7 +17,6 @@ #include "tf_common.h" #include "tf_session.h" #include "tfp.h" -#include "hwrm_tf.h" #include "tf_em.h" /* Specific msg size defines as we cannot use defines in tf.yaml. This @@ -39,8 +39,19 @@ * array size (define above) should be checked and compared. */ #define TF_MSG_SIZE_HWRM_TF_GLOBAL_CFG_SET 56 +static_assert(sizeof(struct hwrm_tf_global_cfg_set_input) == + TF_MSG_SIZE_HWRM_TF_GLOBAL_CFG_SET, + "HWRM message size changed: hwrm_tf_global_cfg_set_input"); + #define TF_MSG_SIZE_HWRM_TF_EM_INSERT 104 +static_assert(sizeof(struct hwrm_tf_em_insert_input) == + TF_MSG_SIZE_HWRM_TF_EM_INSERT, + "HWRM message size changed: hwrm_tf_em_insert_input"); + #define TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET 128 +static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) == + TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET, + "HWRM message size changed: hwrm_tf_tbl_type_set_input"); /** * This is the MAX data we can transport across regular HWRM @@ -862,6 +873,117 @@ tf_msg_delete_em_entry(struct tf *tfp, return 0; } +int tf_msg_ext_em_ctxt_mem_alloc(struct tf *tfp, + struct hcapi_cfa_em_table *tbl, + uint64_t *dma_addr, + uint32_t *page_lvl, + uint32_t *page_size) +{ + struct tfp_send_msg_parms parms = { 0 }; + struct hwrm_tf_ctxt_mem_alloc_input req = {0}; + struct hwrm_tf_ctxt_mem_alloc_output resp = {0}; + uint32_t mem_size_k; + int rc = 0; + struct tf_dev_info *dev; + struct tf_session *tfs; + uint32_t fw_se_id; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } + /* Retrieve the session information */ + fw_se_id = tfs->session_id.internal.fw_session_id; + + if (tbl->num_entries && tbl->entry_size) { + /* unit: kbytes */ + mem_size_k = (tbl->num_entries / TF_KILOBYTE) * tbl->entry_size; + req.mem_size = tfp_cpu_to_le_32(mem_size_k); + req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); + parms.tf_type = HWRM_TF_CTXT_MEM_ALLOC; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + rc = tfp_send_msg_direct(tfp, &parms); + if (rc) { + TFP_DRV_LOG(ERR, "Failed ext_em_alloc error rc:%s\n", + strerror(-rc)); + return rc; + } + + *dma_addr = tfp_le_to_cpu_64(resp.page_dir); + *page_lvl = resp.page_level; + *page_size = resp.page_size; + } + + return rc; +} + +int tf_msg_ext_em_ctxt_mem_free(struct tf *tfp, + uint32_t mem_size_k, + uint64_t dma_addr, + uint8_t page_level, + uint8_t page_size) +{ + struct tfp_send_msg_parms parms = { 0 }; + struct hwrm_tf_ctxt_mem_free_input req = {0}; + struct hwrm_tf_ctxt_mem_free_output resp = {0}; + int rc = 0; + struct tf_dev_info *dev; + struct tf_session *tfs; + uint32_t fw_se_id; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } + /* Retrieve the session information */ + fw_se_id = tfs->session_id.internal.fw_session_id; + + req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); + req.mem_size = tfp_cpu_to_le_32(mem_size_k); + req.page_dir = tfp_cpu_to_le_64(dma_addr); + req.page_level = page_level; + req.page_size = page_size; + parms.tf_type = HWRM_TF_CTXT_MEM_FREE; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + rc = tfp_send_msg_direct(tfp, &parms); + + return rc; +} + int tf_msg_em_mem_rgtr(struct tf *tfp, int page_lvl, @@ -875,6 +997,7 @@ tf_msg_em_mem_rgtr(struct tf *tfp, struct tfp_send_msg_parms parms = { 0 }; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t fw_se_id; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -893,7 +1016,9 @@ tf_msg_em_mem_rgtr(struct tf *tfp, strerror(-rc)); return rc; } + fw_se_id = tfs->session_id.internal.fw_session_id; + req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); req.page_level = page_lvl; req.page_size = page_size; req.page_dir = tfp_cpu_to_le_64(dma_addr); @@ -925,6 +1050,7 @@ tf_msg_em_mem_unrgtr(struct tf *tfp, struct tfp_send_msg_parms parms = { 0 }; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t fw_se_id; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -944,6 +1070,9 @@ tf_msg_em_mem_unrgtr(struct tf *tfp, return rc; } + fw_se_id = tfs->session_id.internal.fw_session_id; + req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); + req.ctx_id = tfp_cpu_to_le_32(*ctx_id); parms.tf_type = HWRM_TF_CTXT_MEM_UNRGTR; @@ -970,6 +1099,7 @@ tf_msg_em_qcaps(struct tf *tfp, struct tfp_send_msg_parms parms = { 0 }; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t fw_se_id; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -980,6 +1110,7 @@ tf_msg_em_qcaps(struct tf *tfp, strerror(-rc)); return rc; } + fw_se_id = tfs->session_id.internal.fw_session_id; /* Retrieve the device information */ rc = tf_session_get_device(tfs, &dev); @@ -996,6 +1127,7 @@ tf_msg_em_qcaps(struct tf *tfp, req.flags = tfp_cpu_to_le_32(flags); parms.tf_type = HWRM_TF_EXT_EM_QCAPS; + req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); parms.req_data = (uint32_t *)&req; parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; @@ -1082,6 +1214,80 @@ tf_msg_em_cfg(struct tf *tfp, return rc; } +int +tf_msg_ext_em_cfg(struct tf *tfp, + struct tf_tbl_scope_cb *tbl_scope_cb, + uint32_t st_buckets, + uint8_t flush_interval, + enum tf_dir dir) +{ + struct hcapi_cfa_em_ctx_mem_info *ctxp = &tbl_scope_cb->em_ctx_info[dir]; + struct hcapi_cfa_em_table *lkup_tbl, *act_tbl; + struct hwrm_tf_ext_em_cfg_input req = {0}; + struct hwrm_tf_ext_em_cfg_output resp = {0}; + struct tfp_send_msg_parms parms = { 0 }; + uint32_t flags; + struct tf_dev_info *dev; + struct tf_session *tfs; + uint32_t fw_se_id; + int rc; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + fw_se_id = tfs->session_id.internal.fw_session_id; + + lkup_tbl = &ctxp->em_tables[TF_EM_LKUP_TABLE]; + act_tbl = &ctxp->em_tables[TF_ACTION_TABLE]; + flags = (dir == TF_DIR_TX ? HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX : + HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX); + flags |= HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD; + + req.flags = tfp_cpu_to_le_32(flags); + req.num_entries = tfp_cpu_to_le_32(act_tbl->num_entries); + req.lkup_static_buckets = tfp_cpu_to_le_32(st_buckets); + req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); + req.flush_interval = flush_interval; + req.action_ctx_id = tfp_cpu_to_le_16(act_tbl->ctx_id); + req.action_tbl_scope = tfp_cpu_to_le_16(tbl_scope_cb->tbl_scope_id); + req.lkup_ctx_id = tfp_cpu_to_le_16(lkup_tbl->ctx_id); + req.lkup_tbl_scope = tfp_cpu_to_le_16(tbl_scope_cb->tbl_scope_id); + + req.enables = (HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID | + HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE | + HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID | + HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE | + HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS | + HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES); + + parms.tf_type = HWRM_TF_EXT_EM_CFG; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tfp, + &parms); + return rc; +} + int tf_msg_em_op(struct tf *tfp, int dir, @@ -1244,9 +1450,6 @@ tf_msg_tcam_entry_get(struct tf *tfp, if (rc != 0) return rc; - if (mparms.tf_resp_code != 0) - return tfp_le_to_cpu_32(mparms.tf_resp_code); - if (parms->key_size < resp.key_size || parms->result_size < resp.result_size) { rc = -EINVAL; @@ -1264,7 +1467,7 @@ tf_msg_tcam_entry_get(struct tf *tfp, tfp_memcpy(parms->mask, &resp.dev_data[resp.key_size], resp.key_size); tfp_memcpy(parms->result, &resp.dev_data[resp.result_offset], resp.result_size); - return tfp_le_to_cpu_32(mparms.tf_resp_code); + return 0; } int @@ -1388,7 +1591,7 @@ tf_msg_set_tbl_entry(struct tf *tfp, if (rc) return rc; - return tfp_le_to_cpu_32(parms.tf_resp_code); + return 0; } int @@ -1454,15 +1657,22 @@ tf_msg_get_tbl_entry(struct tf *tfp, if (rc) return rc; - /* Verify that we got enough buffer to return the requested data */ - if (tfp_le_to_cpu_32(resp.size) != size) + /* + * The response will be 64 bytes long, the response size will + * be in words (16). All we can test for is that the response + * size is < to the requested size. + */ + if ((tfp_le_to_cpu_32(resp.size) * 4) < size) return -EINVAL; + /* + * Copy the requested number of bytes + */ tfp_memcpy(data, &resp.data, size); - return tfp_le_to_cpu_32(parms.tf_resp_code); + return 0; } /* HWRM Tunneled messages */ @@ -1544,7 +1754,7 @@ tf_msg_get_global_cfg(struct tf *tfp, else return -EFAULT; - return tfp_le_to_cpu_32(parms.tf_resp_code); + return 0; } int @@ -1560,9 +1770,6 @@ tf_msg_set_global_cfg(struct tf *tfp, struct tf_dev_info *dev; struct tf_session *tfs; - RTE_BUILD_BUG_ON(sizeof(struct hwrm_tf_global_cfg_set_input) != - TF_MSG_SIZE_HWRM_TF_GLOBAL_CFG_SET); - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) { @@ -1637,7 +1844,7 @@ tf_msg_set_global_cfg(struct tf *tfp, if (rc != 0) return rc; - return tfp_le_to_cpu_32(parms.tf_resp_code); + return 0; } int @@ -1651,8 +1858,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, { int rc; struct tfp_send_msg_parms parms = { 0 }; - struct tf_tbl_type_bulk_get_input req = { 0 }; - struct tf_tbl_type_bulk_get_output resp = { 0 }; + struct hwrm_tf_tbl_type_bulk_get_input req = { 0 }; + struct hwrm_tf_tbl_type_bulk_get_output resp = { 0 }; int data_size = 0; uint8_t fw_session_id; struct tf_dev_info *dev; @@ -1698,14 +1905,15 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, req.host_addr = tfp_cpu_to_le_64(physical_mem_addr); - MSG_PREP(parms, - dev->ops->tf_dev_get_mailbox(), - HWRM_TF, - HWRM_TFT_TBL_TYPE_BULK_GET, - req, - resp); + parms.tf_type = HWRM_TF_TBL_TYPE_BULK_GET; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_tunneled(tfp, &parms); + rc = tfp_send_msg_direct(tfp, + &parms); if (rc) return rc; @@ -1713,7 +1921,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, if (tfp_le_to_cpu_32(resp.size) != data_size) return -EINVAL; - return tfp_le_to_cpu_32(parms.tf_resp_code); + return 0; } int @@ -1772,12 +1980,9 @@ tf_msg_get_if_tbl_entry(struct tf *tfp, if (rc != 0) return rc; - if (parms.tf_resp_code != 0) - return tfp_le_to_cpu_32(parms.tf_resp_code); - tfp_memcpy(params->data, resp.data, req.size); - return tfp_le_to_cpu_32(parms.tf_resp_code); + return 0; } int @@ -1832,5 +2037,5 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, if (rc != 0) return rc; - return tfp_le_to_cpu_32(parms.tf_resp_code); + return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index a14bcd3927..7b4a6a3d92 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -9,6 +9,7 @@ #include #include +#include "tf_em_common.h" #include "tf_tbl.h" #include "tf_rm.h" #include "tf_tcam.h" @@ -275,6 +276,60 @@ tf_msg_hash_insert_em_internal_entry(struct tf *tfp, int tf_msg_delete_em_entry(struct tf *tfp, struct tf_delete_em_entry_parms *em_parms); +/** + * Sends Ext EM mem allocation request to Firmware + * + * [in] tfp + * Pointer to TF handle + * + * [in] tbl + * memory allocation details + * + * [out] dma_addr + * memory address + * + * [out] page_lvl + * page level + * + * [out] page_size + * page size + * + * Returns: + * 0 on Success else internal Truflow error + */ +int tf_msg_ext_em_ctxt_mem_alloc(struct tf *tfp, + struct hcapi_cfa_em_table *tbl, + uint64_t *dma_addr, + uint32_t *page_lvl, + uint32_t *page_size); + +/** + * Sends Ext EM mem allocation request to Firmware + * + * [in] tfp + * Pointer to TF handle + * + * [in] mem_size_k + * memory size in KB + * + * [in] page_dir + * Pointer to the PBL or PDL depending on number of levels + * + * [in] page_level + * PBL indirect levels + * + * [in] page_size + * page size + * + * Returns: + * 0 on Success else internal Truflow error + */ +int tf_msg_ext_em_ctxt_mem_free(struct tf *tfp, + uint32_t mem_size_k, + uint64_t dma_addr, + uint8_t page_level, + uint8_t page_size); + /** * Sends EM mem register request to Firmware * @@ -377,6 +432,38 @@ int tf_msg_em_cfg(struct tf *tfp, uint8_t flush_interval, int dir); +/** + * Sends Ext EM config request to Firmware + * + * [in] tfp + * Pointer to TF handle + * + * [in] fw_se_id + * FW session id + * + * [in] tbl_scope_cb + * Table scope parameters + * + * [in] st_buckets + * static bucket size + * + * [in] flush_interval + * Flush pending HW cached flows every 1/10th of value set in + * seconds, both idle and active flows are flushed from the HW + * cache. If set to 0, this feature will be disabled. + * + * [in] dir + * Receive or Transmit direction + * + * Returns: + * 0 on Success else internal Truflow error + */ +int tf_msg_ext_em_cfg(struct tf *tfp, + struct tf_tbl_scope_cb *tbl_scope_cb, + uint32_t st_buckets, + uint8_t flush_interval, + enum tf_dir dir); + /** * Sends EM operation request to Firmware * diff --git a/drivers/net/bnxt/tf_core/tf_msg_common.h b/drivers/net/bnxt/tf_core/tf_msg_common.h index 0c5c21fd68..49f334717d 100644 --- a/drivers/net/bnxt/tf_core/tf_msg_common.h +++ b/drivers/net/bnxt/tf_core/tf_msg_common.h @@ -15,7 +15,6 @@ parms.mailbox = mb; \ parms.tf_type = type; \ parms.tf_subtype = subtype; \ - parms.tf_resp_code = 0; \ parms.req_size = sizeof(req); \ parms.req_data = (uint32_t *)&(req); \ parms.resp_size = sizeof(resp); \ @@ -26,7 +25,6 @@ parms.mailbox = mb; \ parms.tf_type = type; \ parms.tf_subtype = subtype; \ - parms.tf_resp_code = 0; \ parms.req_size = 0; \ parms.req_data = NULL; \ parms.resp_size = sizeof(resp); \ @@ -37,7 +35,6 @@ parms.mailbox = mb; \ parms.tf_type = type; \ parms.tf_subtype = subtype; \ - parms.tf_resp_code = 0; \ parms.req_size = sizeof(req); \ parms.req_data = (uint32_t *)&(req); \ parms.resp_size = 0; \ diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index d2b24f5e20..f591fbe3f5 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -173,6 +173,9 @@ tf_session_create(struct tf *tfp, ll_insert(&session->client_ll, &client->ll_entry); session->ref_count++; + /* Init session em_ext_db */ + session->em_ext_db_handle = NULL; + rc = tf_dev_bind(tfp, parms->open_cfg->device_type, session->shadow_copy, @@ -796,3 +799,115 @@ tf_session_get_session_id(struct tf *tfp, return 0; } + +int +tf_session_get_em_ext_db(struct tf *tfp, + void **em_ext_db_handle) +{ + struct tf_session *tfs = NULL; + int rc = 0; + + *em_ext_db_handle = NULL; + + if (tfp == NULL) + return (-EINVAL); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + *em_ext_db_handle = tfs->em_ext_db_handle; + return rc; +} + +int +tf_session_set_em_ext_db(struct tf *tfp, + void *em_ext_db_handle) +{ + struct tf_session *tfs = NULL; + int rc = 0; + + if (tfp == NULL) + return (-EINVAL); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + tfs->em_ext_db_handle = em_ext_db_handle; + return rc; +} + +int +tf_session_get_db(struct tf *tfp, + enum tf_module_type type, + void **db_handle) +{ + struct tf_session *tfs = NULL; + int rc = 0; + + *db_handle = NULL; + + if (tfp == NULL) + return (-EINVAL); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + switch (type) { + case TF_MODULE_TYPE_IDENTIFIER: + *db_handle = tfs->id_db_handle; + break; + case TF_MODULE_TYPE_TABLE: + *db_handle = tfs->tbl_db_handle; + break; + case TF_MODULE_TYPE_TCAM: + *db_handle = tfs->tcam_db_handle; + break; + case TF_MODULE_TYPE_EM: + *db_handle = tfs->em_db_handle; + break; + default: + rc = -EINVAL; + break; + } + + return rc; +} + +int +tf_session_set_db(struct tf *tfp, + enum tf_module_type type, + void *db_handle) +{ + struct tf_session *tfs = NULL; + int rc = 0; + + if (tfp == NULL) + return (-EINVAL); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + switch (type) { + case TF_MODULE_TYPE_IDENTIFIER: + tfs->id_db_handle = db_handle; + break; + case TF_MODULE_TYPE_TABLE: + tfs->tbl_db_handle = db_handle; + break; + case TF_MODULE_TYPE_TCAM: + tfs->tcam_db_handle = db_handle; + break; + case TF_MODULE_TYPE_EM: + tfs->em_db_handle = db_handle; + break; + default: + rc = -EINVAL; + break; + } + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index 1d51fa12f8..e5c7a07daf 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -112,6 +112,31 @@ struct tf_session { * Linked list of clients registered for this session */ struct ll client_ll; + + /** + * em ext db reference for the session + */ + void *em_ext_db_handle; + + /** + * tcam db reference for the session + */ + void *tcam_db_handle; + + /** + * table db reference for the session + */ + void *tbl_db_handle; + + /** + * identifier db reference for the session + */ + void *id_db_handle; + + /** + * em db reference for the session + */ + void *em_db_handle; }; /** @@ -410,4 +435,69 @@ int tf_session_get_fw_session_id(struct tf *tfp, int tf_session_get_session_id(struct tf *tfp, union tf_session_id *session_id); +/** + * API to get the em_ext_db from tf_session. + * + * [in] tfp + * Pointer to TF handle + * + * [out] em_ext_db_handle, pointer to eem handle + * + * Returns: + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int +tf_session_get_em_ext_db(struct tf *tfp, + void **em_ext_db_handle); + +/** + * API to set the em_ext_db in tf_session. + * + * [in] tfp + * Pointer to TF handle + * + * [in] em_ext_db_handle, pointer to eem handle + * + * Returns: + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int +tf_session_set_em_ext_db(struct tf *tfp, + void *em_ext_db_handle); + +/** + * API to get the db from tf_session. + * + * [in] tfp + * Pointer to TF handle + * + * [out] db_handle, pointer to db handle + * + * Returns: + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int +tf_session_get_db(struct tf *tfp, + enum tf_module_type type, + void **db_handle); + +/** + * API to set the db in tf_session. + * + * [in] tfp + * Pointer to TF handle + * + * [in] db_handle, pointer to db handle + * + * Returns: + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int +tf_session_set_db(struct tf *tfp, + enum tf_module_type type, + void *db_handle); #endif /* _TF_SESSION_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h index f0d8e94f7e..9271cf28eb 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.h +++ b/drivers/net/bnxt/tf_core/tf_tbl.h @@ -15,39 +15,9 @@ struct tf; * The Table module provides processing of Internal TF table types. */ -/** - * Table scope control block content - */ -struct tf_em_caps { - uint32_t flags; - uint32_t supported; - uint32_t max_entries_supported; - uint16_t key_entry_size; - uint16_t record_entry_size; - uint16_t efc_entry_size; -}; - /** Invalid table scope id */ #define TF_TBL_SCOPE_INVALID 0xffffffff -/** - * Table Scope Control Block - * - * Holds private data for a table scope. Only one instance of a table - * scope with Internal EM is supported. - */ -struct tf_tbl_scope_cb { - uint32_t tbl_scope_id; - /** The pf or parent pf of the vf used for table scope creation - */ - uint16_t pf; - int index; - struct hcapi_cfa_em_ctx_mem_info em_ctx_info[TF_DIR_MAX]; - struct tf_em_caps em_caps[TF_DIR_MAX]; - struct stack ext_act_pool[TF_DIR_MAX]; - uint32_t *ext_act_pool_mem[TF_DIR_MAX]; -}; - /** * Table configuration parameters */ diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index b4d47d5a8c..25f5c152d2 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -98,20 +98,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type) return "Mirror"; case TF_TBL_TYPE_UPAR: return "UPAR"; - case TF_TBL_TYPE_EPOCH0: - return "EPOCH0"; - case TF_TBL_TYPE_EPOCH1: - return "EPOCH1"; case TF_TBL_TYPE_METADATA: return "Metadata"; - case TF_TBL_TYPE_CT_STATE: - return "Connection State"; - case TF_TBL_TYPE_RANGE_PROF: - return "Range Profile"; - case TF_TBL_TYPE_RANGE_ENTRY: - return "Range"; - case TF_TBL_TYPE_LAG: - return "Link Aggregation"; case TF_TBL_TYPE_EM_FKB: return "EM Flexible Key Builder"; case TF_TBL_TYPE_WC_FKB: diff --git a/drivers/net/bnxt/tf_core/tf_util.h b/drivers/net/bnxt/tf_core/tf_util.h index 1aa35b6b82..4caf50349d 100644 --- a/drivers/net/bnxt/tf_core/tf_util.h +++ b/drivers/net/bnxt/tf_core/tf_util.h @@ -9,6 +9,10 @@ #include "tf_core.h" #include "tf_device.h" +#define TF_BITS2BYTES(x) (((x) + 7) >> 3) +#define TF_BITS2BYTES_WORD_ALIGN(x) ((((x) + 31) >> 5) * 4) +#define TF_BITS2BYTES_64B_WORD_ALIGN(x) ((((x) + 63) >> 6) * 8) + /** * Helper function converting direction to text string * diff --git a/drivers/net/bnxt/tf_core/tfp.c b/drivers/net/bnxt/tf_core/tfp.c index b88affcf1e..37c49b587d 100644 --- a/drivers/net/bnxt/tf_core/tfp.c +++ b/drivers/net/bnxt/tf_core/tfp.c @@ -53,40 +53,6 @@ tfp_send_msg_direct(struct tf *tfp, return rc; } -/** - * Sends preformatted TruFlow msg to the TruFlow Firmware using - * the Truflow tunnel HWRM message type. - * - * Returns success or failure code. - */ -int -tfp_send_msg_tunneled(struct tf *tfp, - struct tfp_send_msg_parms *parms) -{ - int rc = 0; - uint8_t use_kong_mb = 1; - - if (parms == NULL) - return -EINVAL; - - if (parms->mailbox == TF_CHIMP_MB) - use_kong_mb = 0; - - rc = bnxt_hwrm_tf_message_tunneled(container_of(tfp, - struct bnxt, - tfp), - use_kong_mb, - parms->tf_type, - parms->tf_subtype, - &parms->tf_resp_code, - parms->req_data, - parms->req_size, - parms->resp_data, - parms->resp_size); - - return rc; -} - /** * Allocates zero'ed memory from the heap. * diff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h index 2e4ca7ac44..bcc56b0a54 100644 --- a/drivers/net/bnxt/tf_core/tfp.h +++ b/drivers/net/bnxt/tf_core/tfp.h @@ -56,11 +56,6 @@ struct tfp_send_msg_parms { * [in] tlv_subtype, specifies the tlv_subtype. */ uint16_t tf_subtype; - /** - * [out] tf_resp_code, response code from the internal tlv - * message. Only supported on tunneled messages. - */ - uint32_t tf_resp_code; /** * [out] size, number specifying the request size of the data in bytes */ @@ -111,7 +106,6 @@ struct tfp_calloc_parms { * @page Portability * * @ref tfp_send_direct - * @ref tfp_send_msg_tunneled * * @ref tfp_calloc * @ref tfp_memcpy @@ -139,37 +133,6 @@ struct tfp_calloc_parms { int tfp_send_msg_direct(struct tf *tfp, struct tfp_send_msg_parms *parms); -/** - * Provides communication capability from the TrueFlow API layer to - * the TrueFlow firmware. The portability layer internally provides - * the transport to the firmware. - * - * [in] session, pointer to session handle - * [in] parms, parameter structure - * - * Returns: - * 0 - Success - * -1 - Global error like not supported - * -EINVAL - Parameter Error - */ -int tfp_send_msg_tunneled(struct tf *tfp, - struct tfp_send_msg_parms *parms); - -/** - * Sends OEM command message to Chimp - * - * [in] session, pointer to session handle - * [in] max_flows, max number of flows requested - * - * Returns: - * 0 - Success - * -1 - Global error like not supported - * -EINVAL - Parameter Error - */ -int -tfp_msg_hwrm_oem_cmd(struct tf *tfp, - uint32_t max_flows); - /** * Sends OEM command message to Chimp * @@ -253,21 +216,6 @@ int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid); #define tfp_bswap_32(val) rte_bswap32(val) #define tfp_bswap_64(val) rte_bswap64(val) -/** - * Lookup of the FID in the platform specific structure. - * - * [in] session - * Pointer to session handle - * - * [out] fw_fid - * Pointer to the fw_fid - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid); - /** * Get the PF associated with the fw communications channel. * From patchwork Sun May 30 08:58:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93562 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1B590A0524; Sun, 30 May 2021 11:02:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9803D4115E; Sun, 30 May 2021 11:00:50 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id BAEA34114A for ; Sun, 30 May 2021 11:00:48 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 268D47DAF; Sun, 30 May 2021 02:00:46 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 268D47DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365248; bh=A69ce6vAYTVg8qnMpnBdZ9ErGv3cKOL1yEFhhOfP2Ps=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lnzc4NlTZzBsHqqpOvKWgAC4cWBssCGtWtNvuFKSs6dFLVunU8ch8wEESl1QEbxJT I+OAduxJbnAcOLROfH2RYk8aIymJLNeJwiUl6zLNgnp2Ef+uUCk43I59qLNUQSiIGV 8QyRLq7iJwHJOS/boMnd/iaEIVHpXstuQ2eiY+00= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:44 +0530 Message-Id: <20210530085929.29695-14-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 13/58] net/bnxt: change RM database type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding RM databases are statically defined in each module. New static database needs to be defined in the code when multiple sessions are added. Add dynamic alloc database and associate it to each session. Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_core/tf_em.h | 10 ++ drivers/net/bnxt/tf_core/tf_em_internal.c | 44 +++++-- drivers/net/bnxt/tf_core/tf_identifier.c | 82 ++++++++++-- drivers/net/bnxt/tf_core/tf_identifier.h | 10 ++ drivers/net/bnxt/tf_core/tf_tbl.c | 151 +++++++++++++++++----- drivers/net/bnxt/tf_core/tf_tbl.h | 10 ++ drivers/net/bnxt/tf_core/tf_tcam.c | 107 ++++++++++++--- drivers/net/bnxt/tf_core/tf_tcam.h | 10 ++ 8 files changed, 351 insertions(+), 73 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 2de1862cd9..19ad7f12be 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -133,6 +133,16 @@ struct tf_em_cfg_parms { enum tf_mem_type mem_type; }; +/** + * EM database + * + * EM rm database + * + */ +struct em_rm_db { + struct rm_db *em_db[TF_DIR_MAX]; +}; + /** * @page em EM * diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 043f9be4da..5a100ef1de 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -18,11 +18,6 @@ #include "bnxt.h" -/** - * EM DBs. - */ -static void *em_db[TF_DIR_MAX]; - #define TF_EM_DB_EM_REC 0 /** @@ -242,6 +237,8 @@ tf_em_int_bind(struct tf *tfp, uint8_t db_exists = 0; struct tf_rm_get_alloc_info_parms iparms; struct tf_rm_alloc_info info; + struct em_rm_db *em_db; + struct tfp_calloc_parms cparms; TF_CHECK_PARMS2(tfp, parms); @@ -251,6 +248,21 @@ tf_em_int_bind(struct tf *tfp, return -EINVAL; } + memset(&db_cfg, 0, sizeof(db_cfg)); + cparms.nitems = 1; + cparms.size = sizeof(struct em_rm_db); + cparms.alignment = 0; + if (tfp_calloc(&cparms) != 0) { + TFP_DRV_LOG(ERR, "em_rm_db alloc error %s\n", + strerror(ENOMEM)); + return -ENOMEM; + } + + em_db = cparms.mem_va; + for (i = 0; i < TF_DIR_MAX; i++) + em_db->em_db[i] = NULL; + tf_session_set_db(tfp, TF_MODULE_TYPE_EM, em_db); + db_cfg.module = TF_MODULE_TYPE_EM; db_cfg.num_elements = parms->num_elements; db_cfg.cfg = parms->cfg; @@ -277,7 +289,8 @@ tf_em_int_bind(struct tf *tfp, return rc; } - db_cfg.rm_db = &em_db[i]; + db_cfg.rm_db = (void *)&em_db->em_db[i]; + rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, @@ -293,7 +306,7 @@ tf_em_int_bind(struct tf *tfp, init = 1; for (i = 0; i < TF_DIR_MAX; i++) { - iparms.rm_db = em_db[i]; + iparms.rm_db = em_db->em_db[i]; iparms.subtype = TF_EM_DB_EM_REC; iparms.info = &info; @@ -323,6 +336,8 @@ tf_em_int_unbind(struct tf *tfp) int rc; int i; struct tf_rm_free_db_parms fparms = { 0 }; + struct em_rm_db *em_db; + void *em_db_ptr = NULL; TF_CHECK_PARMS1(tfp); @@ -336,16 +351,25 @@ tf_em_int_unbind(struct tf *tfp) for (i = 0; i < TF_DIR_MAX; i++) tf_free_em_pool(i); + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + em_db = (struct em_rm_db *)em_db_ptr; + for (i = 0; i < TF_DIR_MAX; i++) { fparms.dir = i; - fparms.rm_db = em_db[i]; - if (em_db[i] != NULL) { + fparms.rm_db = em_db->em_db[i]; + if (em_db->em_db[i] != NULL) { rc = tf_rm_free_db(tfp, &fparms); if (rc) return rc; } - em_db[i] = NULL; + em_db->em_db[i] = NULL; } init = 0; diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index 9d0a578085..ee68b6ca58 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -11,14 +11,10 @@ #include "tf_rm.h" #include "tf_util.h" #include "tfp.h" +#include "tf_session.h" struct tf; -/** - * Identifier DBs. - */ -static void *ident_db[TF_DIR_MAX]; - /** * Init flag, set on bind and cleared on unbind */ @@ -43,6 +39,8 @@ tf_ident_bind(struct tf *tfp, struct tf_rm_create_db_parms db_cfg = { 0 }; struct tf_shadow_ident_cfg_parms shadow_cfg = { 0 }; struct tf_shadow_ident_create_db_parms shadow_cdb = { 0 }; + struct ident_rm_db *ident_db; + struct tfp_calloc_parms cparms; TF_CHECK_PARMS2(tfp, parms); @@ -52,14 +50,29 @@ tf_ident_bind(struct tf *tfp, return -EINVAL; } + memset(&db_cfg, 0, sizeof(db_cfg)); + cparms.nitems = 1; + cparms.size = sizeof(struct ident_rm_db); + cparms.alignment = 0; + if (tfp_calloc(&cparms) != 0) { + TFP_DRV_LOG(ERR, "ident_rm_db alloc error %s\n", + strerror(ENOMEM)); + return -ENOMEM; + } + + ident_db = cparms.mem_va; + for (i = 0; i < TF_DIR_MAX; i++) + ident_db->ident_db[i] = NULL; + tf_session_set_db(tfp, TF_MODULE_TYPE_IDENTIFIER, ident_db); + db_cfg.module = TF_MODULE_TYPE_IDENTIFIER; db_cfg.num_elements = parms->num_elements; db_cfg.cfg = parms->cfg; for (i = 0; i < TF_DIR_MAX; i++) { + db_cfg.rm_db = (void *)&ident_db->ident_db[i]; db_cfg.dir = i; db_cfg.alloc_cnt = parms->resources->ident_cnt[i].cnt; - db_cfg.rm_db = &ident_db[i]; rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, @@ -102,6 +115,8 @@ tf_ident_unbind(struct tf *tfp) int i; struct tf_rm_free_db_parms fparms = { 0 }; struct tf_shadow_ident_free_db_parms sparms = { 0 }; + struct ident_rm_db *ident_db; + void *ident_db_ptr = NULL; TF_CHECK_PARMS1(tfp); @@ -112,9 +127,18 @@ tf_ident_unbind(struct tf *tfp) return 0; } + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get ident_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + ident_db = (struct ident_rm_db *)ident_db_ptr; + for (i = 0; i < TF_DIR_MAX; i++) { + fparms.rm_db = ident_db->ident_db[i]; fparms.dir = i; - fparms.rm_db = ident_db[i]; rc = tf_rm_free_db(tfp, &fparms); if (rc) { TFP_DRV_LOG(ERR, @@ -131,7 +155,7 @@ tf_ident_unbind(struct tf *tfp) } ident_shadow_db[i] = NULL; } - ident_db[i] = NULL; + ident_db->ident_db[i] = NULL; } init = 0; @@ -149,6 +173,8 @@ tf_ident_alloc(struct tf *tfp __rte_unused, uint32_t base_id; struct tf_rm_allocate_parms aparms = { 0 }; struct tf_shadow_ident_insert_parms iparms = { 0 }; + struct ident_rm_db *ident_db; + void *ident_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -159,8 +185,16 @@ tf_ident_alloc(struct tf *tfp __rte_unused, return -EINVAL; } - /* Allocate requested element */ - aparms.rm_db = ident_db[parms->dir]; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get ident_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + ident_db = (struct ident_rm_db *)ident_db_ptr; + + aparms.rm_db = ident_db->ident_db[parms->dir]; aparms.subtype = parms->type; aparms.index = &id; aparms.base_index = &base_id; @@ -203,6 +237,8 @@ tf_ident_free(struct tf *tfp __rte_unused, struct tf_shadow_ident_remove_parms rparms = { 0 }; int allocated = 0; uint32_t base_id; + struct ident_rm_db *ident_db; + void *ident_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -213,8 +249,17 @@ tf_ident_free(struct tf *tfp __rte_unused, return -EINVAL; } + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get ident_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + ident_db = (struct ident_rm_db *)ident_db_ptr; + /* Check if element is in use */ - aparms.rm_db = ident_db[parms->dir]; + aparms.rm_db = ident_db->ident_db[parms->dir]; aparms.subtype = parms->type; aparms.index = parms->id; aparms.base_index = &base_id; @@ -254,7 +299,7 @@ tf_ident_free(struct tf *tfp __rte_unused, } /* Free requested element */ - fparms.rm_db = ident_db[parms->dir]; + fparms.rm_db = ident_db->ident_db[parms->dir]; fparms.subtype = parms->type; fparms.index = parms->id; rc = tf_rm_free(&fparms); @@ -279,6 +324,8 @@ tf_ident_search(struct tf *tfp __rte_unused, struct tf_shadow_ident_search_parms sparms = { 0 }; int allocated = 0; uint32_t base_id; + struct ident_rm_db *ident_db; + void *ident_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -296,8 +343,17 @@ tf_ident_search(struct tf *tfp __rte_unused, return -EINVAL; } + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get ident_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + ident_db = (struct ident_rm_db *)ident_db_ptr; + /* Check if element is in use */ - aparms.rm_db = ident_db[parms->dir]; + aparms.rm_db = ident_db->ident_db[parms->dir]; aparms.subtype = parms->type; aparms.index = parms->search_id; aparms.base_index = &base_id; diff --git a/drivers/net/bnxt/tf_core/tf_identifier.h b/drivers/net/bnxt/tf_core/tf_identifier.h index 2700416c71..54cecbfd4c 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.h +++ b/drivers/net/bnxt/tf_core/tf_identifier.h @@ -99,6 +99,16 @@ struct tf_ident_search_parms { uint32_t *ref_cnt; }; +/** + * Identifier database + * + * Identifier rm database + * + */ +struct ident_rm_db { + struct rm_db *ident_db[TF_DIR_MAX]; +}; + /** * @page ident Identity Management * diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 75dbe2066f..2d0dda18c9 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -26,11 +26,6 @@ struct tf; -/** - * Table DBs. - */ -static void *tbl_db[TF_DIR_MAX]; - /** * Table Shadow DBs */ @@ -50,8 +45,10 @@ int tf_tbl_bind(struct tf *tfp, struct tf_tbl_cfg_parms *parms) { - int rc, d; + int rc, d, i; struct tf_rm_create_db_parms db_cfg = { 0 }; + struct tbl_rm_db *tbl_db; + struct tfp_calloc_parms cparms; TF_CHECK_PARMS2(tfp, parms); @@ -61,6 +58,21 @@ tf_tbl_bind(struct tf *tfp, return -EINVAL; } + memset(&db_cfg, 0, sizeof(db_cfg)); + cparms.nitems = 1; + cparms.size = sizeof(struct tbl_rm_db); + cparms.alignment = 0; + if (tfp_calloc(&cparms) != 0) { + TFP_DRV_LOG(ERR, "tbl_rm_db alloc error %s\n", + strerror(ENOMEM)); + return -ENOMEM; + } + + tbl_db = cparms.mem_va; + for (i = 0; i < TF_DIR_MAX; i++) + tbl_db->tbl_db[i] = NULL; + tf_session_set_db(tfp, TF_MODULE_TYPE_TABLE, tbl_db); + db_cfg.num_elements = parms->num_elements; db_cfg.module = TF_MODULE_TYPE_TABLE; db_cfg.num_elements = parms->num_elements; @@ -69,7 +81,8 @@ tf_tbl_bind(struct tf *tfp, for (d = 0; d < TF_DIR_MAX; d++) { db_cfg.dir = d; db_cfg.alloc_cnt = parms->resources->tbl_cnt[d].cnt; - db_cfg.rm_db = &tbl_db[d]; + db_cfg.rm_db = (void *)&tbl_db->tbl_db[d]; + rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, @@ -79,7 +92,6 @@ tf_tbl_bind(struct tf *tfp, return rc; } } - init = 1; TFP_DRV_LOG(INFO, @@ -94,6 +106,8 @@ tf_tbl_unbind(struct tf *tfp) int rc; int i; struct tf_rm_free_db_parms fparms = { 0 }; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; TF_CHECK_PARMS1(tfp); /* Bail if nothing has been initialized */ @@ -103,14 +117,23 @@ tf_tbl_unbind(struct tf *tfp) return 0; } + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + for (i = 0; i < TF_DIR_MAX; i++) { fparms.dir = i; - fparms.rm_db = tbl_db[i]; + fparms.rm_db = tbl_db->tbl_db[i]; rc = tf_rm_free_db(tfp, &fparms); if (rc) return rc; - tbl_db[i] = NULL; + tbl_db->tbl_db[i] = NULL; } init = 0; @@ -129,6 +152,8 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, struct tf_session *tfs; struct tf_dev_info *dev; uint16_t base = 0, shift = 0; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -149,10 +174,22 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, if (rc) return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + /* Only get table info if required for the device */ if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], - parms->type, &base, &shift); + rc = dev->ops->tf_dev_get_tbl_info(tfp, + tbl_db->tbl_db[parms->dir], + parms->type, + &base, + &shift); if (rc) { TFP_DRV_LOG(ERR, "%s: Failed to get table info:%d\n", @@ -163,7 +200,7 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, } /* Allocate requested element */ - aparms.rm_db = tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; aparms.subtype = parms->type; aparms.index = &idx; rc = tf_rm_allocate(&aparms); @@ -192,6 +229,8 @@ tf_tbl_free(struct tf *tfp __rte_unused, struct tf_session *tfs; struct tf_dev_info *dev; uint16_t base = 0, shift = 0; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -211,10 +250,22 @@ tf_tbl_free(struct tf *tfp __rte_unused, if (rc) return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + /* Only get table info if required for the device */ if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], - parms->type, &base, &shift); + rc = dev->ops->tf_dev_get_tbl_info(tfp, + tbl_db->tbl_db[parms->dir], + parms->type, + &base, + &shift); if (rc) { TFP_DRV_LOG(ERR, "%s: Failed to get table info:%d\n", @@ -225,7 +276,7 @@ tf_tbl_free(struct tf *tfp __rte_unused, } /* Check if element is in use */ - aparms.rm_db = tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; aparms.subtype = parms->type; TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); @@ -244,7 +295,7 @@ tf_tbl_free(struct tf *tfp __rte_unused, return -EINVAL; } /* Free requested element */ - fparms.rm_db = tbl_db[parms->dir]; + fparms.rm_db = tbl_db->tbl_db[parms->dir]; fparms.subtype = parms->type; TF_TBL_PTR_TO_RM(&fparms.index, parms->idx, base, shift); @@ -290,6 +341,8 @@ tf_tbl_set(struct tf *tfp, struct tf_session *tfs; struct tf_dev_info *dev; uint16_t base = 0, shift = 0; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -310,10 +363,22 @@ tf_tbl_set(struct tf *tfp, if (rc) return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + /* Only get table info if required for the device */ if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], - parms->type, &base, &shift); + rc = dev->ops->tf_dev_get_tbl_info(tfp, + tbl_db->tbl_db[parms->dir], + parms->type, + &base, + &shift); if (rc) { TFP_DRV_LOG(ERR, "%s: Failed to get table info:%d\n", @@ -324,7 +389,7 @@ tf_tbl_set(struct tf *tfp, } /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; aparms.subtype = parms->type; TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); @@ -343,7 +408,7 @@ tf_tbl_set(struct tf *tfp, } /* Set the entry */ - hparms.rm_db = tbl_db[parms->dir]; + hparms.rm_db = tbl_db->tbl_db[parms->dir]; hparms.subtype = parms->type; hparms.hcapi_type = &hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); @@ -386,6 +451,8 @@ tf_tbl_get(struct tf *tfp, struct tf_session *tfs; struct tf_dev_info *dev; uint16_t base = 0, shift = 0; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -407,10 +474,22 @@ tf_tbl_get(struct tf *tfp, if (rc) return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + /* Only get table info if required for the device */ if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], - parms->type, &base, &shift); + rc = dev->ops->tf_dev_get_tbl_info(tfp, + tbl_db->tbl_db[parms->dir], + parms->type, + &base, + &shift); if (rc) { TFP_DRV_LOG(ERR, "%s: Failed to get table info:%d\n", @@ -421,7 +500,7 @@ tf_tbl_get(struct tf *tfp, } /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; aparms.subtype = parms->type; TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); @@ -440,7 +519,7 @@ tf_tbl_get(struct tf *tfp, } /* Set the entry */ - hparms.rm_db = tbl_db[parms->dir]; + hparms.rm_db = tbl_db->tbl_db[parms->dir]; hparms.subtype = parms->type; hparms.hcapi_type = &hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); @@ -483,6 +562,8 @@ tf_tbl_bulk_get(struct tf *tfp, struct tf_session *tfs; struct tf_dev_info *dev; uint16_t base = 0, shift = 0; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -504,10 +585,22 @@ tf_tbl_bulk_get(struct tf *tfp, if (rc) return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + /* Only get table info if required for the device */ if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, tbl_db[parms->dir], - parms->type, &base, &shift); + rc = dev->ops->tf_dev_get_tbl_info(tfp, + tbl_db->tbl_db[parms->dir], + parms->type, + &base, + &shift); if (rc) { TFP_DRV_LOG(ERR, "%s: Failed to get table info:%d\n", @@ -518,7 +611,7 @@ tf_tbl_bulk_get(struct tf *tfp, } /* Verify that the entries are in the range of reserved resources. */ - cparms.rm_db = tbl_db[parms->dir]; + cparms.rm_db = tbl_db->tbl_db[parms->dir]; cparms.subtype = parms->type; TF_TBL_PTR_TO_RM(&cparms.starting_index, parms->starting_idx, @@ -538,7 +631,7 @@ tf_tbl_bulk_get(struct tf *tfp, return rc; } - hparms.rm_db = tbl_db[parms->dir]; + hparms.rm_db = tbl_db->tbl_db[parms->dir]; hparms.subtype = parms->type; hparms.hcapi_type = &hcapi_type; rc = tf_rm_get_hcapi_type(&hparms); diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h index 9271cf28eb..83b72d1b3f 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.h +++ b/drivers/net/bnxt/tf_core/tf_tbl.h @@ -229,6 +229,16 @@ struct tf_tbl_get_bulk_parms { uint64_t physical_mem_addr; }; +/** + * Table RM database + * + * Table rm database + * + */ +struct tbl_rm_db { + struct rm_db *tbl_db[TF_DIR_MAX]; +}; + /** * @page tbl Table * diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 1b5c29815d..c2eef26dbb 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -18,11 +18,6 @@ struct tf; -/** - * TCAM DBs. - */ -static void *tcam_db[TF_DIR_MAX]; - /** * TCAM Shadow DBs */ @@ -55,6 +50,8 @@ tf_tcam_bind(struct tf *tfp, uint16_t num_slices = 1; struct tf_session *tfs; struct tf_dev_info *dev; + struct tcam_rm_db *tcam_db; + struct tfp_calloc_parms cparms; TF_CHECK_PARMS2(tfp, parms); @@ -99,6 +96,19 @@ tf_tcam_bind(struct tf *tfp, } memset(&db_cfg, 0, sizeof(db_cfg)); + cparms.nitems = 1; + cparms.size = sizeof(struct tcam_rm_db); + cparms.alignment = 0; + if (tfp_calloc(&cparms) != 0) { + TFP_DRV_LOG(ERR, "tcam_rm_db alloc error %s\n", + strerror(ENOMEM)); + return -ENOMEM; + } + + tcam_db = cparms.mem_va; + for (i = 0; i < TF_DIR_MAX; i++) + tcam_db->tcam_db[i] = NULL; + tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, tcam_db); db_cfg.module = TF_MODULE_TYPE_TCAM; db_cfg.num_elements = parms->num_elements; @@ -107,7 +117,7 @@ tf_tcam_bind(struct tf *tfp, for (d = 0; d < TF_DIR_MAX; d++) { db_cfg.dir = d; db_cfg.alloc_cnt = parms->resources->tcam_cnt[d].cnt; - db_cfg.rm_db = &tcam_db[d]; + db_cfg.rm_db = (void *)&tcam_db->tcam_db[d]; rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, @@ -120,7 +130,7 @@ tf_tcam_bind(struct tf *tfp, /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { memset(&info, 0, sizeof(info)); - ainfo.rm_db = tcam_db[d]; + ainfo.rm_db = tcam_db->tcam_db[d]; ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM; ainfo.info = &info; rc = tf_rm_get_info(&ainfo); @@ -148,7 +158,7 @@ tf_tcam_bind(struct tf *tfp, if (!parms->resources->tcam_cnt[d].cnt[i]) continue; - ainfo.rm_db = tcam_db[d]; + ainfo.rm_db = tcam_db->tcam_db[d]; ainfo.subtype = i; ainfo.info = &info; rc = tf_rm_get_info(&ainfo); @@ -186,7 +196,7 @@ tf_tcam_bind(struct tf *tfp, for (i = 0; i < TF_DIR_MAX; i++) { memset(&fparms, 0, sizeof(fparms)); fparms.dir = i; - fparms.rm_db = tcam_db[i]; + fparms.rm_db = tcam_db->tcam_db[i]; /* Ignoring return here since we are in the error case */ (void)tf_rm_free_db(tfp, &fparms); @@ -196,7 +206,8 @@ tf_tcam_bind(struct tf *tfp, shadow_tcam_db[i] = NULL; } - tcam_db[i] = NULL; + tcam_db->tcam_db[i] = NULL; + tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, NULL); } shadow_init = 0; @@ -211,6 +222,8 @@ tf_tcam_unbind(struct tf *tfp) int rc; int i; struct tf_rm_free_db_parms fparms; + struct tcam_rm_db *tcam_db; + void *tcam_db_ptr = NULL; struct tf_shadow_tcam_free_db_parms fshadow; TF_CHECK_PARMS1(tfp); @@ -221,15 +234,24 @@ tf_tcam_unbind(struct tf *tfp) return 0; } + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; + for (i = 0; i < TF_DIR_MAX; i++) { memset(&fparms, 0, sizeof(fparms)); fparms.dir = i; - fparms.rm_db = tcam_db[i]; + fparms.rm_db = tcam_db->tcam_db[i]; rc = tf_rm_free_db(tfp, &fparms); if (rc) return rc; - tcam_db[i] = NULL; + tcam_db->tcam_db[i] = NULL; if (shadow_init) { memset(&fshadow, 0, sizeof(fshadow)); @@ -256,6 +278,8 @@ tf_tcam_alloc(struct tf *tfp, struct tf_rm_allocate_parms aparms; uint16_t num_slices = 1; uint32_t index; + struct tcam_rm_db *tcam_db; + void *tcam_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -293,13 +317,22 @@ tf_tcam_alloc(struct tf *tfp, if (rc) return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; + /* * For WC TCAM, number of slices could be 4, 2, 1 based on * the key_size. For other TCAM, it is always 1 */ for (i = 0; i < num_slices; i++) { memset(&aparms, 0, sizeof(aparms)); - aparms.rm_db = tcam_db[parms->dir]; + aparms.rm_db = tcam_db->tcam_db[parms->dir]; aparms.subtype = parms->type; aparms.priority = parms->priority; aparms.index = &index; @@ -334,6 +367,8 @@ tf_tcam_free(struct tf *tfp, int allocated = 0; struct tf_shadow_tcam_remove_parms shparms; int i; + struct tcam_rm_db *tcam_db; + void *tcam_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -379,10 +414,18 @@ tf_tcam_free(struct tf *tfp, return -EINVAL; } + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; + /* Check if element is in use */ memset(&aparms, 0, sizeof(aparms)); - - aparms.rm_db = tcam_db[parms->dir]; + aparms.rm_db = tcam_db->tcam_db[parms->dir]; aparms.subtype = parms->type; aparms.index = parms->idx; aparms.allocated = &allocated; @@ -431,7 +474,7 @@ tf_tcam_free(struct tf *tfp, for (i = 0; i < num_slices; i++) { /* Free requested element */ memset(&fparms, 0, sizeof(fparms)); - fparms.rm_db = tcam_db[parms->dir]; + fparms.rm_db = tcam_db->tcam_db[parms->dir]; fparms.subtype = parms->type; fparms.index = parms->idx + i; rc = tf_rm_free(&fparms); @@ -448,7 +491,7 @@ tf_tcam_free(struct tf *tfp, /* Convert TF type to HCAPI RM type */ memset(&hparms, 0, sizeof(hparms)); - hparms.rm_db = tcam_db[parms->dir]; + hparms.rm_db = tcam_db->tcam_db[parms->dir]; hparms.subtype = parms->type; hparms.hcapi_type = &parms->hcapi_type; @@ -612,6 +655,8 @@ tf_tcam_set(struct tf *tfp __rte_unused, struct tf_shadow_tcam_insert_parms iparms; uint16_t num_slice_per_row = 1; int allocated = 0; + struct tcam_rm_db *tcam_db; + void *tcam_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -649,10 +694,19 @@ tf_tcam_set(struct tf *tfp __rte_unused, if (rc) return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; + /* Check if element is in use */ memset(&aparms, 0, sizeof(aparms)); - aparms.rm_db = tcam_db[parms->dir]; + aparms.rm_db = tcam_db->tcam_db[parms->dir]; aparms.subtype = parms->type; aparms.index = parms->idx; aparms.allocated = &allocated; @@ -672,7 +726,7 @@ tf_tcam_set(struct tf *tfp __rte_unused, /* Convert TF type to HCAPI RM type */ memset(&hparms, 0, sizeof(hparms)); - hparms.rm_db = tcam_db[parms->dir]; + hparms.rm_db = tcam_db->tcam_db[parms->dir]; hparms.subtype = parms->type; hparms.hcapi_type = &parms->hcapi_type; @@ -722,6 +776,8 @@ tf_tcam_get(struct tf *tfp __rte_unused, struct tf_rm_is_allocated_parms aparms; struct tf_rm_get_hcapi_parms hparms; int allocated = 0; + struct tcam_rm_db *tcam_db; + void *tcam_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -742,10 +798,19 @@ tf_tcam_get(struct tf *tfp __rte_unused, if (rc) return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; + /* Check if element is in use */ memset(&aparms, 0, sizeof(aparms)); - aparms.rm_db = tcam_db[parms->dir]; + aparms.rm_db = tcam_db->tcam_db[parms->dir]; aparms.subtype = parms->type; aparms.index = parms->idx; aparms.allocated = &allocated; @@ -765,7 +830,7 @@ tf_tcam_get(struct tf *tfp __rte_unused, /* Convert TF type to HCAPI RM type */ memset(&hparms, 0, sizeof(hparms)); - hparms.rm_db = tcam_db[parms->dir]; + hparms.rm_db = tcam_db->tcam_db[parms->dir]; hparms.subtype = parms->type; hparms.hcapi_type = &parms->hcapi_type; diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h index b550fa43ca..acab223532 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.h +++ b/drivers/net/bnxt/tf_core/tf_tcam.h @@ -237,6 +237,16 @@ struct tf_tcam_get_parms { uint16_t result_size; }; +/** + * TCAM database + * + * Tcam rm database + * + */ +struct tcam_rm_db { + struct rm_db *tcam_db[TF_DIR_MAX]; +}; + /** * @page tcam TCAM * From patchwork Sun May 30 08:58:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93563 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4D71AA0524; Sun, 30 May 2021 11:02:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CFAFD41162; Sun, 30 May 2021 11:00:52 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 791BF4115B for ; Sun, 30 May 2021 11:00:50 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id D61287DC2; Sun, 30 May 2021 02:00:48 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com D61287DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365250; bh=wMtnh9gRE505tqsMk1uaLGUYRKoHNRqY5pJN4tdcnsY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sDvRgGlSn4DPyh8PwirB4gkR2pOEPIwPO5gq1PIeF6bMhcYvj1YpEqmPzg0ku7bsd KJSipEh0YsEJ6dhwHXmJvcik4ZjmVQp61FxONGSR3/Lbx1QHr7vfoAx6ybjwNzAHLC zbzIrlxVrYPv/qPKCbKMlIYZ9829jArdCh85imfA= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:45 +0530 Message-Id: <20210530085929.29695-15-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 14/58] net/bnxt: add shared session support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding There are 2 types of sessions - shared and non-shared. For non-shared all the allocated resources are owned and managed by a single session instance. No other applications have access to the resources owned by the non-shared session. For a shared session, resources are shared between 2 applications. The FW shared session can only be created by one application and shared by other apps. The host session that creates the FW shared session is the creator. Applications can retrieve the reserved resources through a new API tf_get_session_resc_info. Each module supports two sessions, one is shared session, the other is non-shared session. Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 281 +++++++++++++++++----- drivers/net/bnxt/tf_core/bitalloc.c | 10 +- drivers/net/bnxt/tf_core/bitalloc.h | 3 +- drivers/net/bnxt/tf_core/tf_core.c | 105 ++++++++ drivers/net/bnxt/tf_core/tf_core.h | 177 +++++++++++++- drivers/net/bnxt/tf_core/tf_device.c | 76 +++--- drivers/net/bnxt/tf_core/tf_device.h | 73 ++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 8 + drivers/net/bnxt/tf_core/tf_device_p58.c | 8 + drivers/net/bnxt/tf_core/tf_em.h | 17 ++ drivers/net/bnxt/tf_core/tf_em_common.c | 25 -- drivers/net/bnxt/tf_core/tf_em_internal.c | 118 +++++---- drivers/net/bnxt/tf_core/tf_identifier.c | 89 +++---- drivers/net/bnxt/tf_core/tf_identifier.h | 16 ++ drivers/net/bnxt/tf_core/tf_msg.c | 223 ++++++++++++++--- drivers/net/bnxt/tf_core/tf_msg.h | 47 +++- drivers/net/bnxt/tf_core/tf_rm.c | 277 ++++++++++++++++++++- drivers/net/bnxt/tf_core/tf_rm.h | 34 +++ drivers/net/bnxt/tf_core/tf_session.c | 37 ++- drivers/net/bnxt/tf_core/tf_session.h | 66 +++++ drivers/net/bnxt/tf_core/tf_tbl.c | 104 ++++---- drivers/net/bnxt/tf_core/tf_tbl.h | 17 ++ drivers/net/bnxt/tf_core/tf_tcam.c | 103 ++++---- drivers/net/bnxt/tf_core/tf_tcam.h | 16 ++ drivers/net/bnxt/tf_core/tfp.c | 6 +- drivers/net/bnxt/tf_core/tfp.h | 3 +- 26 files changed, 1560 insertions(+), 379 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index aea9305486..046acb8de2 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -699,6 +699,8 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf) /* Experimental */ + #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0) + /* Experimental */ #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) /* Experimental */ #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) @@ -727,6 +729,8 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec) /* Experimental */ + #define HWRM_TF_EM_MOVE UINT32_C(0x2ed) + /* Experimental */ #define HWRM_TF_TCAM_SET UINT32_C(0x2f8) /* Experimental */ #define HWRM_TF_TCAM_GET UINT32_C(0x2f9) @@ -986,8 +990,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 15 -#define HWRM_VERSION_STR "1.10.2.15" +#define HWRM_VERSION_RSVD 22 +#define HWRM_VERSION_STR "1.10.2.22" /**************** * hwrm_ver_get * @@ -11971,7 +11975,7 @@ struct hwrm_func_cfg_input { /* * Function ID of the function that is being * configured. - * If set to 0xFF... (All Fs), then the configuration is + * If set to 0xFF... (All Fs), then the the configuration is * for the requesting function. */ uint16_t fid; @@ -12671,7 +12675,7 @@ struct hwrm_func_cfg_input { /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block block. When this bit is ‘0’, this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \ UINT32_C(0x20) @@ -12685,7 +12689,7 @@ struct hwrm_func_cfg_input { /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block block. When this bit is ‘0’, this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \ UINT32_C(0x80) @@ -18041,7 +18045,7 @@ struct hwrm_func_spd_cfg_input { UINT32_C(0x10) /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -18300,7 +18304,7 @@ struct hwrm_func_spd_qcfg_output { uint8_t unused_1; /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -29815,7 +29819,7 @@ struct hwrm_vnic_cfg_input { * queue ID will be arriving on this VNIC. Packet priority to CoS mapping * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, * ntuple filters with VNIC destination specified are invalid since they - * conflict with the CoS to VNIC steering rules in this mode. + * conflict with the the CoS to VNIC steering rules in this mode. * * If this field is not specified, packet to VNIC steering will be * subject to the standard L2 filter rules and any additional ntuple @@ -41312,14 +41316,14 @@ struct hwrm_cfa_eem_qcaps_output { #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \ UINT32_C(0x2) /* - * When set to 1, indicates the FW supports the Centralized + * When set to 1, indicates the the FW supports the Centralized * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x4) /* - * When set to 1, indicates the FW supports the Detached + * When set to 1, indicates the the FW supports the Detached * Centralized Memory Model. The memory is allocated and managed * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of @@ -42143,8 +42147,24 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; - /* unused. */ - uint32_t unused0; + uint32_t flags; + /* Indicates if the shared session has been created. */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ + UINT32_C(0x1) + /* + * If this bit set to 0, then it indicates the shared session + * has been created by another session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \ + UINT32_C(0x0) + /* + * If this bit is set to 1, then it indicates the shared session + * is created by this session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \ + UINT32_C(0x1) + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \ + HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR /* unused. */ uint8_t unused1[3]; /* @@ -42948,6 +42968,105 @@ struct hwrm_tf_session_resc_flush_output { uint8_t valid; } __rte_packed; +/***************************** + * hwrm_tf_session_resc_info * + *****************************/ + + +/* hwrm_tf_session_resc_info_input (size:320b/40B) */ +struct hwrm_tf_session_resc_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_info_output (size:128b/16B) */ +struct hwrm_tf_session_resc_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /* TruFlow RM capability of a resource. */ /* tf_rm_resc_req_entry (size:64b/8B) */ struct tf_rm_resc_req_entry { @@ -43608,14 +43727,14 @@ struct hwrm_tf_ext_em_qcaps_output { uint16_t resp_len; uint32_t flags; /* - * When set to 1, indicates the FW supports the Centralized + * When set to 1, indicates the the FW supports the Centralized * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x1) /* - * When set to 1, indicates the FW supports the Detached + * When set to 1, indicates the the FW supports the Detached * Centralized Memory Model. The memory is allocated and managed * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of @@ -44434,6 +44553,79 @@ struct hwrm_tf_em_delete_output { uint16_t unused0[3]; } __rte_packed; +/******************* + * hwrm_tf_em_move * + *******************/ + + +/* hwrm_tf_em_move_input (size:320b/40B) */ +struct hwrm_tf_em_move_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Session Id. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX + /* Number of EM entry blocks */ + uint16_t num_blocks; + /* New index for entry */ + uint32_t new_index; + /* Unused */ + uint32_t unused0; + /* EM internal flow handle. */ + uint64_t flow_handle; +} __rte_packed; + +/* hwrm_tf_em_move_output (size:128b/16B) */ +struct hwrm_tf_em_move_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Index of old entry. */ + uint16_t em_index; + /* unused. */ + uint16_t unused0[3]; +} __rte_packed; + /******************** * hwrm_tf_tcam_set * ********************/ @@ -46988,10 +47180,7 @@ struct hwrm_nvm_write_input { * This is where the source data is. */ uint64_t host_src_addr; - /* - * The Directory Entry Type (valid values are defined in the bnxnvm - * directory_type enum defined in the file bnxnvm_defs.h). - */ + /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ uint16_t dir_type; /* * Directory ordinal. @@ -47003,10 +47192,8 @@ struct hwrm_nvm_write_input { /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ uint16_t dir_attr; /* - * Length of data to write, in bytes. May be less than or equal to the allocated - * size for the directory entry. - * The data length stored in the directory entry will be updated to reflect - * this value once the write is complete. + * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. + * The data length stored in the directory entry will be updated to reflect this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -47019,15 +47206,11 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. This - * value may be greater than or equal to the specified data length (dir_data_length). + * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may be - * greater than the requested item length. - * The purpose for allocating more than the required number of bytes for - * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with a - * size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate + * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; uint32_t unused_0; @@ -47044,11 +47227,8 @@ struct hwrm_nvm_write_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested - * item length. - * The actual item length used when creating a new directory entry will be - * a multiple of an NVM block size. + * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. + * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -47392,10 +47572,7 @@ struct hwrm_nvm_get_dev_info_output { /* Total size, in bytes of the NVRAM device. */ uint32_t nvram_size; uint32_t reserved_size; - /* - * Available size that can be used, in bytes. Available size is the - * NVRAM size take away the used size and reserved size. - */ + /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */ uint32_t available_size; /* This field represents the major version of NVM cfg */ uint8_t nvm_cfg_ver_maj; @@ -47537,15 +47714,9 @@ struct hwrm_nvm_mod_dir_entry_input { * The (0-based) instance of this Directory Type. */ uint16_t dir_ordinal; - /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension - * flag definitions). - */ + /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */ uint16_t dir_ext; - /* - * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag - * definitions). - */ + /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ uint16_t dir_attr; /* * If valid, then this field updates the checksum @@ -47712,10 +47883,8 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, - * will be safely deleted. - * When combined with erase_unused_space then unspecified images will be - * securely erased. + * If set to 1, then unspecified images, images not in the package file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) @@ -48100,10 +48269,7 @@ struct hwrm_nvm_set_variable_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t flags; - /* - * When this bit is 1, flush internal cache after this write operation - * (see hwrm_nvm_flush command.) - */ + /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) /* encryption method */ @@ -48405,10 +48571,7 @@ struct hwrm_fw_reset_input { */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \ UINT32_C(0x4) - /* - * AP processor complex (in multi-host environment). Use host_idx to - * control which core is reset - */ + /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \ UINT32_C(0x5) /* Reset all blocks of the chip (including all processors) */ diff --git a/drivers/net/bnxt/tf_core/bitalloc.c b/drivers/net/bnxt/tf_core/bitalloc.c index af1397071b..e253cfc3a6 100644 --- a/drivers/net/bnxt/tf_core/bitalloc.c +++ b/drivers/net/bnxt/tf_core/bitalloc.c @@ -65,7 +65,7 @@ ba_ffs(bitalloc_word_t v) } int -ba_init(struct bitalloc *pool, int size) +ba_init(struct bitalloc *pool, int size, bool free) { bitalloc_word_t *mem = (bitalloc_word_t *)pool; int i; @@ -101,9 +101,11 @@ ba_init(struct bitalloc *pool, int size) pool->storage[offset++] = words[--lev]; } - /* Free the entire pool */ - for (i = 0; i < size; i++) - ba_free(pool, i); + /* Free the entire pool if it is required*/ + if (free) { + for (i = 0; i < size; i++) + ba_free(pool, i); + } return 0; } diff --git a/drivers/net/bnxt/tf_core/bitalloc.h b/drivers/net/bnxt/tf_core/bitalloc.h index 7244b86e95..e3b389e68d 100644 --- a/drivers/net/bnxt/tf_core/bitalloc.h +++ b/drivers/net/bnxt/tf_core/bitalloc.h @@ -7,6 +7,7 @@ #define _BITALLOC_H_ #include +#include /* Bitalloc works on uint32_t as its word size */ typedef uint32_t bitalloc_word_t; @@ -64,7 +65,7 @@ struct bitalloc { * Returns 0 on success, -1 on failure. Size is arbitrary up to * BITALLOC_MAX_SIZE */ -int ba_init(struct bitalloc *pool, int size); +int ba_init(struct bitalloc *pool, int size, bool free); /** * Returns -1 on failure, or index of allocated entry diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 9b8677caac..69f5c10293 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -27,6 +27,8 @@ tf_open_session(struct tf *tfp, int rc; unsigned int domain, bus, slot, device; struct tf_session_open_session_parms oparms; + int name_len; + char *name; TF_CHECK_PARMS2(tfp, parms); @@ -69,6 +71,13 @@ tf_open_session(struct tf *tfp, } } + name_len = strlen(parms->ctrl_chan_name); + name = &parms->ctrl_chan_name[name_len - strlen("tf_shared")]; + if (!strncmp(name, "tf_shared", strlen("tf_shared"))) { + memset(parms->ctrl_chan_name, 0, strlen(parms->ctrl_chan_name)); + strcpy(parms->ctrl_chan_name, "tf_share"); + } + parms->session_id.internal.domain = domain; parms->session_id.internal.bus = bus; parms->session_id.internal.device = device; @@ -1593,3 +1602,99 @@ tf_get_if_tbl_entry(struct tf *tfp, return 0; } + +int tf_get_session_info(struct tf *tfp, + struct tf_get_session_info_parms *parms) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } + + TF_CHECK_PARMS2(tfp, parms); + + if (dev->ops->tf_dev_get_ident_resc_info == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "Operation not supported, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_get_ident_resc_info(tfp, parms->session_info.ident); + if (rc) { + TFP_DRV_LOG(ERR, + "Ident get resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + if (dev->ops->tf_dev_get_tbl_resc_info == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "Operation not supported, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_get_tbl_resc_info(tfp, parms->session_info.tbl); + if (rc) { + TFP_DRV_LOG(ERR, + "Tbl get resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + if (dev->ops->tf_dev_get_tcam_resc_info == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "Operation not supported, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_get_tcam_resc_info(tfp, parms->session_info.tcam); + if (rc) { + TFP_DRV_LOG(ERR, + "TCAM get resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + if (dev->ops->tf_dev_get_em_resc_info == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "Operation not supported, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_get_em_resc_info(tfp, parms->session_info.em); + if (rc) { + TFP_DRV_LOG(ERR, + "EM get resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 7b26b58000..4440d60fe5 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -557,7 +557,8 @@ struct tf_open_session_parms { * rte_eth_dev_get_name_by_port() within the ULP. * * ctrl_chan_name will be used as part of a name for any - * shared memory allocation. + * shared memory allocation. The ctrl_chan_name is usually in format + * 0000:02:00.0. The name for shared session is 0000:02:00.0-tf_shared. */ char ctrl_chan_name[TF_SESSION_NAME_MAX]; /** @@ -616,29 +617,63 @@ struct tf_open_session_parms { * Resource allocation for the session. */ struct tf_session_resources resources; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /** + * [out] shared_session_creator + * + * Indicates whether the application created the session if set. + * Otherwise the shared session already existed. Just for information + * purposes. + */ + int shared_session_creator; }; /** * Opens a new TruFlow Session or session client. * - * What gets created depends on the passed in tfp content. If the tfp - * does not have prior session data a new session with associated - * session client. If tfp has a session already a session client will - * be created. In both cases the session client is created using the - * provided ctrl_chan_name. + * What gets created depends on the passed in tfp content. If the tfp does not + * have prior session data a new session with associated session client. If tfp + * has a session already a session client will be created. In both cases the + * session client is created using the provided ctrl_chan_name. * - * In case of session creation TruFlow will allocate session specific - * memory, shared memory, to hold its session data. This data is - * private to TruFlow. + * In case of session creation TruFlow will allocate session specific memory to + * hold its session data. This data is private to TruFlow. * * No other TruFlow APIs will succeed unless this API is first called * and succeeds. * - * tf_open_session() returns a session id and session client id that - * is used on all other TF APIs. + * tf_open_session() returns a session id and session client id. These are + * also stored within the tfp structure passed in to all other APIs. * * A Session or session client can be closed using tf_close_session(). * + * There are 2 types of sessions - shared and not. For non-shared all + * the allocated resources are owned and managed by a single session instance. + * No other applications have access to the resources owned by the non-shared + * session. For a shared session, resources are shared between 2 applications. + * + * When the caller of tf_open_session() sets the ctrl_chan_name[] to a name + * like "0000:02:00.0-tf_shared", it is a request to create a new "shared" + * session in the firmware or access the existing shared session. There is + * only 1 shared session that can be created. If the shared session has + * already been created in the firmware, this API will return this indication + * by clearing the shared_session_creator flag. Only the first shared session + * create will have the shared_session_creator flag set. + * + * The shared session should always be the first session to be created by + * application and the last session closed due to RM management preference. + * + * Sessions remain open in the firmware until the last client of the session + * closes the session (tf_close_session()). + * * [in] tfp * Pointer to TF handle * @@ -652,6 +687,126 @@ struct tf_open_session_parms { int tf_open_session(struct tf *tfp, struct tf_open_session_parms *parms); +/** + * General internal resource info + * + * TODO: remove tf_rm_new_entry structure and use this structure + * internally. + */ +struct tf_resource_info { + uint16_t start; + uint16_t stride; +}; + +/** + * Identifier resource definition + */ +struct tf_identifier_resource_info { + /** + * Array of TF Identifiers. The index used is tf_identifier_type. + */ + struct tf_resource_info info[TF_IDENT_TYPE_MAX]; +}; + +/** + * Table type resource info definition + */ +struct tf_tbl_resource_info { + /** + * Array of TF Table types. The index used is tf_tbl_type. + */ + struct tf_resource_info info[TF_TBL_TYPE_MAX]; +}; + +/** + * TCAM type resource definition + */ +struct tf_tcam_resource_info { + /** + * Array of TF TCAM types. The index used is tf_tcam_tbl_type. + */ + struct tf_resource_info info[TF_TCAM_TBL_TYPE_MAX]; +}; + +/** + * EM type resource definition + */ +struct tf_em_resource_info { + /** + * Array of TF EM table types. The index used is tf_em_tbl_type. + */ + struct tf_resource_info info[TF_EM_TBL_TYPE_MAX]; +}; + +/** + * tf_session_resources parameter definition. + */ +struct tf_session_resource_info { + /** + * [in] Requested Identifier Resources + * + * Number of identifier resources requested for the + * session. + */ + struct tf_identifier_resource_info ident[TF_DIR_MAX]; + /** + * [in] Requested Index Table resource counts + * + * The number of index table resources requested for the + * session. + */ + struct tf_tbl_resource_info tbl[TF_DIR_MAX]; + /** + * [in] Requested TCAM Table resource counts + * + * The number of TCAM table resources requested for the + * session. + */ + + struct tf_tcam_resource_info tcam[TF_DIR_MAX]; + /** + * [in] Requested EM resource counts + * + * The number of internal EM table resources requested for the + * session. + */ + struct tf_em_resource_info em[TF_DIR_MAX]; +}; + +/** + * tf_get_session_resources parameter definition. + */ +struct tf_get_session_info_parms { + /** + * [out] the structure is used to return the information of + * allocated resources. + * + */ + struct tf_session_resource_info session_info; +}; + +/** (experimental) + * Gets info about a TruFlow Session + * + * Get info about the session which has been created. Whether it exists and + * what resource start and stride offsets are in use. This API is primarily + * intended to be used by an application which has created a shared session + * This application needs to obtain the resources which have already been + * allocated for the shared session. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to get parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_get_session_info(struct tf *tfp, + struct tf_get_session_info_parms *parms); + /** * Experimental * diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 9e71c04bf2..fed4156200 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -351,10 +351,16 @@ tf_dev_bind_p58(struct tf *tfp, struct tf_em_cfg_parms em_cfg; struct tf_if_tbl_cfg_parms if_tbl_cfg; struct tf_global_cfg_cfg_parms global_cfg; + struct tf_session *tfs; /* Initial function initialization */ dev_handle->ops = &tf_dev_ops_p58_init; + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + rsv_cnt = tf_dev_reservation_check(TF_IDENT_TYPE_MAX, tf_ident_p58, (uint16_t *)resources->ident_cnt); @@ -440,26 +446,28 @@ tf_dev_bind_p58(struct tf *tfp, /* * IF_TBL */ - if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; - if_tbl_cfg.cfg = tf_if_tbl_p58; - if_tbl_cfg.shadow_copy = shadow_copy; - rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "IF Table initialization failure\n"); - goto fail; - } + if (!tf_session_is_shared_session(tfs)) { + if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; + if_tbl_cfg.cfg = tf_if_tbl_p58; + if_tbl_cfg.shadow_copy = shadow_copy; + rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "IF Table initialization failure\n"); + goto fail; + } - /* - * GLOBAL_CFG - */ - global_cfg.num_elements = TF_GLOBAL_CFG_TYPE_MAX; - global_cfg.cfg = tf_global_cfg_p58; - rc = tf_global_cfg_bind(tfp, &global_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "Global Cfg initialization failure\n"); - goto fail; + /* + * GLOBAL_CFG + */ + global_cfg.num_elements = TF_GLOBAL_CFG_TYPE_MAX; + global_cfg.cfg = tf_global_cfg_p58; + rc = tf_global_cfg_bind(tfp, &global_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Global Cfg initialization failure\n"); + goto fail; + } } /* Final function initialization */ @@ -491,6 +499,12 @@ tf_dev_unbind_p58(struct tf *tfp) { int rc = 0; bool fail = false; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; /* Unbind all the support modules. As this is only done on * close we only report errors as everything has to be cleaned @@ -527,18 +541,20 @@ tf_dev_unbind_p58(struct tf *tfp) fail = true; } - rc = tf_if_tbl_unbind(tfp); - if (rc) { - TFP_DRV_LOG(ERR, - "Device unbind failed, IF Table Type\n"); - fail = true; - } + if (!tf_session_is_shared_session(tfs)) { + rc = tf_if_tbl_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, IF Table Type\n"); + fail = true; + } - rc = tf_global_cfg_unbind(tfp); - if (rc) { - TFP_DRV_LOG(ERR, - "Device unbind failed, Global Cfg Type\n"); - fail = true; + rc = tf_global_cfg_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, Global Cfg Type\n"); + fail = true; + } } if (fail) diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 3f2c24a0c6..16c2fe0f64 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -220,6 +220,25 @@ struct tf_dev_ops { */ int (*tf_dev_search_ident)(struct tf *tfp, struct tf_ident_search_parms *parms); + + /** + * Retrieves the identifier resource info. + * + * This API retrieves the identifier resource info from the rm db. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to identifier info + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_ident_resc_info)(struct tf *tfp, + struct tf_identifier_resource_info *parms); + /** * Get SRAM table information. * @@ -425,6 +444,24 @@ struct tf_dev_ops { int (*tf_dev_get_bulk_tbl)(struct tf *tfp, struct tf_tbl_get_bulk_parms *parms); + /** + * Retrieves the table resource info. + * + * This API retrieves the table resource info from the rm db. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to tbl info + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_tbl_resc_info)(struct tf *tfp, + struct tf_tbl_resource_info *parms); + /** * Allocation of a tcam element. * @@ -524,6 +561,24 @@ struct tf_dev_ops { int (*tf_dev_get_tcam)(struct tf *tfp, struct tf_tcam_get_parms *parms); + /** + * Retrieves the tcam resource info. + * + * This API retrieves the tcam resource info from the rm db. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to tcam info + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_tcam_resc_info)(struct tf *tfp, + struct tf_tcam_resource_info *parms); + /** * Insert EM hash entry API * @@ -588,6 +643,24 @@ struct tf_dev_ops { int (*tf_dev_delete_ext_em_entry)(struct tf *tfp, struct tf_delete_em_entry_parms *parms); + /** + * Retrieves the em resource info. + * + * This API retrieves the em resource info from the rm db. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to em info + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_em_resc_info)(struct tf *tfp, + struct tf_em_resource_info *parms); + /** * Allocate EEM table scope * diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 2fb8fadb56..3f788638c1 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -209,6 +209,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_alloc_ident = NULL, .tf_dev_free_ident = NULL, .tf_dev_search_ident = NULL, + .tf_dev_get_ident_resc_info = NULL, .tf_dev_get_tbl_info = NULL, .tf_dev_alloc_ext_tbl = NULL, .tf_dev_alloc_tbl = NULL, @@ -219,15 +220,18 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_set_ext_tbl = NULL, .tf_dev_get_tbl = NULL, .tf_dev_get_bulk_tbl = NULL, + .tf_dev_get_tbl_resc_info = NULL, .tf_dev_alloc_tcam = NULL, .tf_dev_free_tcam = NULL, .tf_dev_alloc_search_tcam = NULL, .tf_dev_set_tcam = NULL, .tf_dev_get_tcam = NULL, + .tf_dev_get_tcam_resc_info = NULL, .tf_dev_insert_int_em_entry = NULL, .tf_dev_delete_int_em_entry = NULL, .tf_dev_insert_ext_em_entry = NULL, .tf_dev_delete_ext_em_entry = NULL, + .tf_dev_get_em_resc_info = NULL, .tf_dev_alloc_tbl_scope = NULL, .tf_dev_map_tbl_scope = NULL, .tf_dev_map_parif = NULL, @@ -250,6 +254,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_alloc_ident = tf_ident_alloc, .tf_dev_free_ident = tf_ident_free, .tf_dev_search_ident = tf_ident_search, + .tf_dev_get_ident_resc_info = tf_ident_get_resc_info, .tf_dev_get_tbl_info = NULL, .tf_dev_alloc_tbl = tf_tbl_alloc, .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, @@ -260,15 +265,18 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, + .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_set_tcam = tf_tcam_set, .tf_dev_get_tcam = NULL, + .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_delete_int_entry, .tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry, .tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry, + .tf_dev_get_em_resc_info = tf_em_get_resc_info, .tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc, .tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope, .tf_dev_map_parif = tf_dev_p4_map_parif, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 517ffc811b..c2bc283220 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -230,6 +230,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_alloc_ident = NULL, .tf_dev_free_ident = NULL, .tf_dev_search_ident = NULL, + .tf_dev_get_ident_resc_info = NULL, .tf_dev_get_tbl_info = NULL, .tf_dev_alloc_ext_tbl = NULL, .tf_dev_alloc_tbl = NULL, @@ -240,15 +241,18 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_set_ext_tbl = NULL, .tf_dev_get_tbl = NULL, .tf_dev_get_bulk_tbl = NULL, + .tf_dev_get_tbl_resc_info = NULL, .tf_dev_alloc_tcam = NULL, .tf_dev_free_tcam = NULL, .tf_dev_alloc_search_tcam = NULL, .tf_dev_set_tcam = NULL, .tf_dev_get_tcam = NULL, + .tf_dev_get_tcam_resc_info = NULL, .tf_dev_insert_int_em_entry = NULL, .tf_dev_delete_int_em_entry = NULL, .tf_dev_insert_ext_em_entry = NULL, .tf_dev_delete_ext_em_entry = NULL, + .tf_dev_get_em_resc_info = NULL, .tf_dev_alloc_tbl_scope = NULL, .tf_dev_map_tbl_scope = NULL, .tf_dev_map_parif = NULL, @@ -271,6 +275,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_alloc_ident = tf_ident_alloc, .tf_dev_free_ident = tf_ident_free, .tf_dev_search_ident = tf_ident_search, + .tf_dev_get_ident_resc_info = tf_ident_get_resc_info, .tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info, .tf_dev_alloc_tbl = tf_tbl_alloc, .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, @@ -281,15 +286,18 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, + .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_set_tcam = tf_tcam_set, .tf_dev_get_tcam = tf_tcam_get, + .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, .tf_dev_insert_ext_em_entry = NULL, .tf_dev_delete_ext_em_entry = NULL, + .tf_dev_get_em_resc_info = tf_em_get_resc_info, .tf_dev_alloc_tbl_scope = NULL, .tf_dev_map_tbl_scope = NULL, .tf_dev_map_parif = NULL, diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 19ad7f12be..60d90e28de 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -530,4 +530,21 @@ tf_em_ext_system_bind(struct tf *tfp, struct tf_em_cfg_parms *parms); int offload_system_mmap(struct tf_tbl_scope_cb *tbl_scope_cb); + +/** + * Retrieves the allocated resource info + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int +tf_em_get_resc_info(struct tf *tfp, + struct tf_em_resource_info *em); #endif /* _TF_EM_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index 4dc3c86b57..ed8f6db58c 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -26,11 +26,6 @@ /* Number of pointers per page_size */ #define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *)) -/** - * Init flag, set on bind and cleared on unbind - */ -static uint8_t init; - /** * Host or system */ @@ -924,18 +919,11 @@ tf_em_ext_common_bind(struct tf *tfp, int rc; int i; struct tf_rm_create_db_parms db_cfg = { 0 }; - uint8_t db_exists = 0; struct em_ext_db *ext_db; struct tfp_calloc_parms cparms; TF_CHECK_PARMS2(tfp, parms); - if (init) { - TFP_DRV_LOG(ERR, - "EM Ext DB already initialized\n"); - return -EINVAL; - } - cparms.nitems = 1; cparms.size = sizeof(struct em_ext_db); cparms.alignment = 0; @@ -974,12 +962,8 @@ tf_em_ext_common_bind(struct tf *tfp, return rc; } - db_exists = 1; } - if (db_exists) - init = 1; - mem_type = parms->mem_type; return 0; @@ -1001,13 +985,6 @@ tf_em_ext_common_unbind(struct tf *tfp) TF_CHECK_PARMS1(tfp); - /* Bail if nothing has been initialized */ - if (!init) { - TFP_DRV_LOG(INFO, - "No EM Ext DBs created\n"); - return 0; - } - rc = tf_session_get_session_internal(tfp, &tfs); if (rc) { TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n", @@ -1064,8 +1041,6 @@ tf_em_ext_common_unbind(struct tf *tfp) tfp_free(ext_db); tf_session_set_em_ext_db(tfp, NULL); - init = 0; - return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 5a100ef1de..e373a9b029 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -20,11 +20,6 @@ #define TF_EM_DB_EM_REC 0 -/** - * Init flag, set on bind and cleared on unbind - */ -static uint8_t init; - /** * EM Pool */ @@ -234,19 +229,18 @@ tf_em_int_bind(struct tf *tfp, int rc; int i; struct tf_rm_create_db_parms db_cfg = { 0 }; - uint8_t db_exists = 0; struct tf_rm_get_alloc_info_parms iparms; struct tf_rm_alloc_info info; struct em_rm_db *em_db; struct tfp_calloc_parms cparms; + struct tf_session *tfs; TF_CHECK_PARMS2(tfp, parms); - if (init) { - TFP_DRV_LOG(ERR, - "EM Int DB already initialized\n"); - return -EINVAL; - } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; memset(&db_cfg, 0, sizeof(db_cfg)); cparms.nitems = 1; @@ -290,8 +284,11 @@ tf_em_int_bind(struct tf *tfp, } db_cfg.rm_db = (void *)&em_db->em_db[i]; - - rc = tf_rm_create_db(tfp, &db_cfg); + if (tf_session_is_shared_session(tfs) && + (!tf_session_is_shared_session_creator(tfs))) + rc = tf_rm_create_db_no_reservation(tfp, &db_cfg); + else + rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, "%s: EM Int DB creation failed\n", @@ -299,34 +296,31 @@ tf_em_int_bind(struct tf *tfp, return rc; } - db_exists = 1; } - if (db_exists) - init = 1; - - for (i = 0; i < TF_DIR_MAX; i++) { - iparms.rm_db = em_db->em_db[i]; - iparms.subtype = TF_EM_DB_EM_REC; - iparms.info = &info; + if (!tf_session_is_shared_session(tfs)) { + for (i = 0; i < TF_DIR_MAX; i++) { + iparms.rm_db = em_db->em_db[i]; + iparms.subtype = TF_EM_DB_EM_REC; + iparms.info = &info; + + rc = tf_rm_get_info(&iparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: EM DB get info failed\n", + tf_dir_2_str(i)); + return rc; + } - rc = tf_rm_get_info(&iparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: EM DB get info failed\n", - tf_dir_2_str(i)); - return rc; + rc = tf_create_em_pool(i, + iparms.info->entry.stride, + iparms.info->entry.start); + /* Logging handled in tf_create_em_pool */ + if (rc) + return rc; } - - rc = tf_create_em_pool(i, - iparms.info->entry.stride, - iparms.info->entry.start); - /* Logging handled in tf_create_em_pool */ - if (rc) - return rc; } - return 0; } @@ -338,18 +332,19 @@ tf_em_int_unbind(struct tf *tfp) struct tf_rm_free_db_parms fparms = { 0 }; struct em_rm_db *em_db; void *em_db_ptr = NULL; + struct tf_session *tfs; TF_CHECK_PARMS1(tfp); - /* Bail if nothing has been initialized */ - if (!init) { - TFP_DRV_LOG(INFO, - "No EM Int DBs created\n"); - return 0; - } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; - for (i = 0; i < TF_DIR_MAX; i++) - tf_free_em_pool(i); + if (!tf_session_is_shared_session(tfs)) { + for (i = 0; i < TF_DIR_MAX; i++) + tf_free_em_pool(i); + } rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); if (rc) { @@ -372,7 +367,42 @@ tf_em_int_unbind(struct tf *tfp) em_db->em_db[i] = NULL; } - init = 0; + return 0; +} + +int +tf_em_get_resc_info(struct tf *tfp, + struct tf_em_resource_info *em) +{ + int rc; + int d; + struct tf_resource_info *dinfo; + struct tf_rm_get_alloc_info_parms ainfo; + void *em_db_ptr = NULL; + struct em_rm_db *em_db; + + TF_CHECK_PARMS2(tfp, em); + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + em_db = (struct em_rm_db *)em_db_ptr; + + /* check if reserved resource for WC is multiple of num_slices */ + for (d = 0; d < TF_DIR_MAX; d++) { + ainfo.rm_db = em_db->em_db[d]; + dinfo = em[d].info; + + ainfo.info = (struct tf_rm_alloc_info *)dinfo; + ainfo.subtype = 0; + rc = tf_rm_get_all_info(&ainfo, TF_EM_TBL_TYPE_MAX); + if (rc && rc != -ENOTSUP) + return rc; + } return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index ee68b6ca58..4063f3ba17 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -15,11 +15,6 @@ struct tf; -/** - * Init flag, set on bind and cleared on unbind - */ -static uint8_t init; - /** * Identifier shadow DBs. */ @@ -41,14 +36,14 @@ tf_ident_bind(struct tf *tfp, struct tf_shadow_ident_create_db_parms shadow_cdb = { 0 }; struct ident_rm_db *ident_db; struct tfp_calloc_parms cparms; + struct tf_session *tfs; TF_CHECK_PARMS2(tfp, parms); - if (init) { - TFP_DRV_LOG(ERR, - "Identifier DB already initialized\n"); - return -EINVAL; - } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; memset(&db_cfg, 0, sizeof(db_cfg)); cparms.nitems = 1; @@ -73,7 +68,11 @@ tf_ident_bind(struct tf *tfp, db_cfg.rm_db = (void *)&ident_db->ident_db[i]; db_cfg.dir = i; db_cfg.alloc_cnt = parms->resources->ident_cnt[i].cnt; - rc = tf_rm_create_db(tfp, &db_cfg); + if (tf_session_is_shared_session(tfs) && + (!tf_session_is_shared_session_creator(tfs))) + rc = tf_rm_create_db_no_reservation(tfp, &db_cfg); + else + rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, "%s: Identifier DB creation failed\n", @@ -100,8 +99,6 @@ tf_ident_bind(struct tf *tfp, } } - init = 1; - TFP_DRV_LOG(INFO, "Identifier - initialized\n"); @@ -120,13 +117,6 @@ tf_ident_unbind(struct tf *tfp) TF_CHECK_PARMS1(tfp); - /* Bail if nothing has been initialized */ - if (!init) { - TFP_DRV_LOG(INFO, - "No Identifier DBs created\n"); - return 0; - } - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); if (rc) { TFP_DRV_LOG(ERR, @@ -158,7 +148,6 @@ tf_ident_unbind(struct tf *tfp) ident_db->ident_db[i] = NULL; } - init = 0; shadow_init = 0; return 0; @@ -178,13 +167,6 @@ tf_ident_alloc(struct tf *tfp __rte_unused, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Identifier DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); if (rc) { TFP_DRV_LOG(ERR, @@ -242,13 +224,6 @@ tf_ident_free(struct tf *tfp __rte_unused, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Identifier DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); if (rc) { TFP_DRV_LOG(ERR, @@ -329,13 +304,6 @@ tf_ident_search(struct tf *tfp __rte_unused, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Identifier DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - if (!shadow_init) { TFP_DRV_LOG(ERR, "%s: Identifier Shadow copy is not enabled\n", @@ -388,3 +356,40 @@ tf_ident_search(struct tf *tfp __rte_unused, return 0; } + +int +tf_ident_get_resc_info(struct tf *tfp, + struct tf_identifier_resource_info *ident) +{ + int rc; + int d; + struct tf_resource_info *dinfo; + struct tf_rm_get_alloc_info_parms ainfo; + void *ident_db_ptr = NULL; + struct ident_rm_db *ident_db; + + TF_CHECK_PARMS2(tfp, ident); + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get ident_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + ident_db = (struct ident_rm_db *)ident_db_ptr; + + /* check if reserved resource for WC is multiple of num_slices */ + for (d = 0; d < TF_DIR_MAX; d++) { + ainfo.rm_db = ident_db->ident_db[d]; + dinfo = ident[d].info; + + ainfo.info = (struct tf_rm_alloc_info *)dinfo; + ainfo.subtype = 0; + rc = tf_rm_get_all_info(&ainfo, TF_IDENT_TYPE_MAX); + if (rc) + return rc; + } + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_identifier.h b/drivers/net/bnxt/tf_core/tf_identifier.h index 54cecbfd4c..55c093802e 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.h +++ b/drivers/net/bnxt/tf_core/tf_identifier.h @@ -201,4 +201,20 @@ int tf_ident_free(struct tf *tfp, int tf_ident_search(struct tf *tfp, struct tf_ident_search_parms *parms); +/** + * Retrieves the allocated resource info + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_ident_get_resc_info(struct tf *tfp, + struct tf_identifier_resource_info *parms); + #endif /* _TF_IDENTIFIER_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index c6eb94bee0..4a840f3473 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -114,11 +114,12 @@ tf_msg_free_dma_buf(struct tf_msg_dma_buf *buf) /* HWRM Direct messages */ int -tf_msg_session_open(struct tf *tfp, +tf_msg_session_open(struct bnxt *bp, char *ctrl_chan_name, uint8_t *fw_session_id, uint8_t *fw_session_client_id, - struct tf_dev_info *dev) + struct tf_dev_info *dev, + bool *shared_session_creator) { int rc; struct hwrm_tf_session_open_input req = { 0 }; @@ -135,7 +136,7 @@ tf_msg_session_open(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(bp, &parms); if (rc) return rc; @@ -143,6 +144,8 @@ tf_msg_session_open(struct tf *tfp, *fw_session_id = (uint8_t)tfp_le_to_cpu_32(resp.fw_session_id); *fw_session_client_id = (uint8_t)tfp_le_to_cpu_32(resp.fw_session_client_id); + *shared_session_creator = (bool)tfp_le_to_cpu_32(resp.flags + & HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR); return rc; } @@ -198,7 +201,7 @@ tf_msg_session_client_register(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -249,7 +252,7 @@ tf_msg_session_client_unregister(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; @@ -293,7 +296,7 @@ tf_msg_session_close(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; } @@ -345,7 +348,7 @@ tf_msg_session_qcfg(struct tf *tfp) parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; } @@ -367,6 +370,16 @@ tf_msg_session_resc_qcaps(struct tf *tfp, struct tf_msg_dma_buf qcaps_buf = { 0 }; struct tf_rm_resc_req_entry *data; int dma_size; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } TF_CHECK_PARMS3(tfp, query, resv_strategy); @@ -398,7 +411,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) goto cleanup; @@ -416,6 +429,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, /* Post process the response */ data = (struct tf_rm_resc_req_entry *)qcaps_buf.va_addr; + for (i = 0; i < size; i++) { query[i].type = tfp_le_to_cpu_32(data[i].type); query[i].min = tfp_le_to_cpu_16(data[i].min); @@ -450,6 +464,16 @@ tf_msg_session_resc_alloc(struct tf *tfp, struct tf_rm_resc_req_entry *req_data; struct tf_rm_resc_entry *resv_data; int dma_size; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } TF_CHECK_PARMS3(tfp, request, resv); @@ -497,7 +521,114 @@ tf_msg_session_resc_alloc(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + if (rc) + goto cleanup; + + /* Process the response + * Should always get expected number of entries + */ + if (tfp_le_to_cpu_32(resp.size) != size) { + TFP_DRV_LOG(ERR, + "%s: Alloc message size error, rc:%s\n", + tf_dir_2_str(dir), + strerror(EINVAL)); + rc = -EINVAL; + goto cleanup; + } + + /* Post process the response */ + resv_data = (struct tf_rm_resc_entry *)resv_buf.va_addr; + for (i = 0; i < size; i++) { + resv[i].type = tfp_le_to_cpu_32(resv_data[i].type); + resv[i].start = tfp_le_to_cpu_16(resv_data[i].start); + resv[i].stride = tfp_le_to_cpu_16(resv_data[i].stride); + } + +cleanup: + tf_msg_free_dma_buf(&req_buf); + tf_msg_free_dma_buf(&resv_buf); + + return rc; +} + +int +tf_msg_session_resc_info(struct tf *tfp, + struct tf_dev_info *dev, + enum tf_dir dir, + uint16_t size, + struct tf_rm_resc_req_entry *request, + struct tf_rm_resc_entry *resv) +{ + int rc; + int i; + struct tfp_send_msg_parms parms = { 0 }; + struct hwrm_tf_session_resc_info_input req = { 0 }; + struct hwrm_tf_session_resc_info_output resp = { 0 }; + uint8_t fw_session_id; + struct tf_msg_dma_buf req_buf = { 0 }; + struct tf_msg_dma_buf resv_buf = { 0 }; + struct tf_rm_resc_req_entry *req_data; + struct tf_rm_resc_entry *resv_data; + int dma_size; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + TF_CHECK_PARMS3(tfp, request, resv); + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Unable to lookup FW id, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Prepare DMA buffers */ + dma_size = size * sizeof(struct tf_rm_resc_req_entry); + rc = tf_msg_alloc_dma_buf(&req_buf, dma_size); + if (rc) + return rc; + + dma_size = size * sizeof(struct tf_rm_resc_entry); + rc = tf_msg_alloc_dma_buf(&resv_buf, dma_size); + if (rc) { + tf_msg_free_dma_buf(&req_buf); + return rc; + } + + /* Populate the request */ + req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.flags = tfp_cpu_to_le_16(dir); + req.req_size = size; + + req_data = (struct tf_rm_resc_req_entry *)req_buf.va_addr; + for (i = 0; i < size; i++) { + req_data[i].type = tfp_cpu_to_le_32(request[i].type); + req_data[i].min = tfp_cpu_to_le_16(request[i].min); + req_data[i].max = tfp_cpu_to_le_16(request[i].max); + } + + req.req_addr = tfp_cpu_to_le_64(req_buf.pa_addr); + req.resc_addr = tfp_cpu_to_le_64(resv_buf.pa_addr); + + parms.tf_type = HWRM_TF_SESSION_RESC_INFO; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) goto cleanup; @@ -604,7 +735,7 @@ tf_msg_session_resc_flush(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); tf_msg_free_dma_buf(&resv_buf); @@ -698,7 +829,7 @@ tf_msg_insert_em_internal_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -793,7 +924,7 @@ tf_msg_hash_insert_em_internal_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -863,7 +994,7 @@ tf_msg_delete_em_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -919,7 +1050,7 @@ int tf_msg_ext_em_ctxt_mem_alloc(struct tf *tfp, parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) { TFP_DRV_LOG(ERR, "Failed ext_em_alloc error rc:%s\n", strerror(-rc)); @@ -979,7 +1110,7 @@ int tf_msg_ext_em_ctxt_mem_free(struct tf *tfp, parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; } @@ -1030,7 +1161,7 @@ tf_msg_em_mem_rgtr(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -1082,7 +1213,7 @@ tf_msg_em_mem_unrgtr(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; } @@ -1134,7 +1265,7 @@ tf_msg_em_qcaps(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -1209,7 +1340,7 @@ tf_msg_em_cfg(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; } @@ -1283,7 +1414,7 @@ tf_msg_ext_em_cfg(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; } @@ -1333,7 +1464,7 @@ tf_msg_em_op(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; } @@ -1351,6 +1482,16 @@ tf_msg_tcam_entry_set(struct tf *tfp, uint8_t *data = NULL; int data_size = 0; uint8_t fw_session_id; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -1401,7 +1542,7 @@ tf_msg_tcam_entry_set(struct tf *tfp, mparms.resp_size = sizeof(resp); mparms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &mparms); cleanup: @@ -1420,6 +1561,16 @@ tf_msg_tcam_entry_get(struct tf *tfp, struct hwrm_tf_tcam_get_input req = { 0 }; struct hwrm_tf_tcam_get_output resp = { 0 }; uint8_t fw_session_id; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -1444,7 +1595,7 @@ tf_msg_tcam_entry_get(struct tf *tfp, mparms.resp_size = sizeof(resp); mparms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &mparms); if (rc != 0) @@ -1480,6 +1631,16 @@ tf_msg_tcam_entry_free(struct tf *tfp, struct hwrm_tf_tcam_free_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } rc = tf_session_get_fw_session_id(tfp, &fw_session_id); if (rc) { @@ -1505,7 +1666,7 @@ tf_msg_tcam_entry_free(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); return rc; } @@ -1586,7 +1747,7 @@ tf_msg_set_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -1652,7 +1813,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -1738,7 +1899,7 @@ tf_msg_get_global_cfg(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc != 0) return rc; @@ -1839,7 +2000,7 @@ tf_msg_set_global_cfg(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc != 0) return rc; @@ -1912,7 +2073,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc) return rc; @@ -1975,7 +2136,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc != 0) return rc; @@ -2032,7 +2193,7 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tfp, &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); if (rc != 0) return rc; diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 7b4a6a3d92..5ecaf9e7e7 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -14,6 +14,7 @@ #include "tf_rm.h" #include "tf_tcam.h" #include "tf_global_cfg.h" +#include "bnxt.h" struct tf; @@ -22,8 +23,8 @@ struct tf; /** * Sends session open request to Firmware * - * [in] session - * Pointer to session handle + * [in] bp + * Pointer to bnxt handle * * [in] ctrl_chan_name * PCI name of the control channel @@ -31,14 +32,24 @@ struct tf; * [in/out] fw_session_id * Pointer to the fw_session_id that is allocated on firmware side * + * [in/out] fw_session_client_id + * Pointer to the fw_session_client_id that is allocated on firmware side + * + * [in/out] dev + * Pointer to the associated device + * + * [out] shared_session_creator + * Pointer to the shared_session_creator + * * Returns: * 0 on Success else internal Truflow error */ -int tf_msg_session_open(struct tf *tfp, +int tf_msg_session_open(struct bnxt *bp, char *ctrl_chan_name, uint8_t *fw_session_id, uint8_t *fw_session_client_id, - struct tf_dev_info *dev); + struct tf_dev_info *dev, + bool *shared_session_creator); /** * Sends session close request to Firmware @@ -178,6 +189,34 @@ int tf_msg_session_resc_alloc(struct tf *tfp, struct tf_rm_resc_req_entry *request, struct tf_rm_resc_entry *resv); +/** + * Sends session HW resource allocation request to TF Firmware + * + * [in] tfp + * Pointer to TF handle + * + * [in] dir + * Receive or Transmit direction + * + * [in] size + * Number of elements in the req and resv arrays + * + * [in] req + * Pointer to an array of request elements + * + * [in] resv + * Pointer to an array of reserved elements + * + * Returns: + * 0 on Success else internal Truflow error + */ +int tf_msg_session_resc_info(struct tf *tfp, + struct tf_dev_info *dev, + enum tf_dir dir, + uint16_t size, + struct tf_rm_resc_req_entry *request, + struct tf_rm_resc_entry *resv); + /** * Sends session resource flush request to TF Firmware * diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index 9fd660543c..761d18413b 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -702,7 +702,9 @@ tf_rm_create_db(struct tf *tfp, } db[i].pool = (struct bitalloc *)cparms.mem_va; - rc = ba_init(db[i].pool, resv[j].stride); + rc = ba_init(db[i].pool, + resv[j].stride, + !tf_session_is_shared_session(tfs)); if (rc) { TFP_DRV_LOG(ERR, "%s: Pool init failed, type:%d:%s\n", @@ -746,6 +748,249 @@ tf_rm_create_db(struct tf *tfp, return -EINVAL; } +int +tf_rm_create_db_no_reservation(struct tf *tfp, + struct tf_rm_create_db_parms *parms) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + int i, j; + uint16_t hcapi_items, *req_cnt; + struct tfp_calloc_parms cparms; + struct tf_rm_resc_req_entry *req; + struct tf_rm_resc_entry *resv; + struct tf_rm_new_db *rm_db; + struct tf_rm_element *db; + uint32_t pool_size; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + /* Copy requested counts (alloc_cnt) from tf_open_session() to local + * copy (req_cnt) so that it can be updated if required. + */ + + cparms.nitems = parms->num_elements; + cparms.size = sizeof(uint16_t); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) + return rc; + + req_cnt = (uint16_t *)cparms.mem_va; + + tfp_memcpy(req_cnt, parms->alloc_cnt, + parms->num_elements * sizeof(uint16_t)); + + /* Process capabilities against DB requirements. However, as a + * DB can hold elements that are not HCAPI we can reduce the + * req msg content by removing those out of the request yet + * the DB holds them all as to give a fast lookup. We can also + * remove entries where there are no request for elements. + */ + tf_rm_count_hcapi_reservations(parms->dir, + parms->module, + parms->cfg, + req_cnt, + parms->num_elements, + &hcapi_items); + + if (hcapi_items == 0) { + TFP_DRV_LOG(ERR, + "%s: module:%s Empty RM DB create request\n", + tf_dir_2_str(parms->dir), + tf_module_2_str(parms->module)); + + parms->rm_db = NULL; + return -ENOMEM; + } + + /* Alloc request, alignment already set */ + cparms.nitems = (size_t)hcapi_items; + cparms.size = sizeof(struct tf_rm_resc_req_entry); + rc = tfp_calloc(&cparms); + if (rc) + return rc; + req = (struct tf_rm_resc_req_entry *)cparms.mem_va; + + /* Alloc reservation, alignment and nitems already set */ + cparms.size = sizeof(struct tf_rm_resc_entry); + rc = tfp_calloc(&cparms); + if (rc) + return rc; + resv = (struct tf_rm_resc_entry *)cparms.mem_va; + + /* Build the request */ + for (i = 0, j = 0; i < parms->num_elements; i++) { + struct tf_rm_element_cfg *cfg = &parms->cfg[i]; + uint16_t hcapi_type = cfg->hcapi_type; + + /* Only perform reservation for requested entries + */ + if (req_cnt[i] == 0) + continue; + + /* Skip any children in the request */ + if (cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI || + cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA || + cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) { + req[j].type = hcapi_type; + req[j].min = req_cnt[i]; + req[j].max = req_cnt[i]; + j++; + } + } + + /* Get all resources info for the module type + */ + rc = tf_msg_session_resc_info(tfp, + dev, + parms->dir, + hcapi_items, + req, + resv); + if (rc) + return rc; + + /* Build the RM DB per the request */ + cparms.nitems = 1; + cparms.size = sizeof(struct tf_rm_new_db); + rc = tfp_calloc(&cparms); + if (rc) + return rc; + rm_db = (void *)cparms.mem_va; + + /* Build the DB within RM DB */ + cparms.nitems = parms->num_elements; + cparms.size = sizeof(struct tf_rm_element); + rc = tfp_calloc(&cparms); + if (rc) + return rc; + rm_db->db = (struct tf_rm_element *)cparms.mem_va; + + db = rm_db->db; + for (i = 0, j = 0; i < parms->num_elements; i++) { + struct tf_rm_element_cfg *cfg = &parms->cfg[i]; + const char *type_str; + + dev->ops->tf_dev_get_resource_str(tfp, + cfg->hcapi_type, + &type_str); + + db[i].cfg_type = cfg->cfg_type; + db[i].hcapi_type = cfg->hcapi_type; + + /* Save the parent subtype for later use to find the pool + */ + if (cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD) + db[i].parent_subtype = cfg->parent_subtype; + + /* If the element didn't request an allocation no need + * to create a pool nor verify if we got a reservation. + */ + if (req_cnt[i] == 0) + continue; + + /* Skip any children or invalid + */ + if (cfg->cfg_type != TF_RM_ELEM_CFG_HCAPI && + cfg->cfg_type != TF_RM_ELEM_CFG_HCAPI_BA && + cfg->cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT) + continue; + + /* If the element had requested an allocation and that + * allocation was a success (full amount) then + * allocate the pool. + */ + if (req_cnt[i] == resv[j].stride) { + db[i].alloc.entry.start = resv[j].start; + db[i].alloc.entry.stride = resv[j].stride; + + /* Only allocate BA pool if a BA type not a child */ + if (cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA || + cfg->cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) { + if (cfg->divider) { + resv[j].stride = + resv[j].stride / cfg->divider; + if (resv[j].stride <= 0) { + TFP_DRV_LOG(ERR, + "%s:Divide fails:%d:%s\n", + tf_dir_2_str(parms->dir), + cfg->hcapi_type, type_str); + goto fail; + } + } + /* Create pool */ + pool_size = (BITALLOC_SIZEOF(resv[j].stride) / + sizeof(struct bitalloc)); + /* Alloc request, alignment already set */ + cparms.nitems = pool_size; + cparms.size = sizeof(struct bitalloc); + rc = tfp_calloc(&cparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Pool alloc failed, type:%d:%s\n", + tf_dir_2_str(parms->dir), + cfg->hcapi_type, type_str); + goto fail; + } + db[i].pool = (struct bitalloc *)cparms.mem_va; + + rc = ba_init(db[i].pool, + resv[j].stride, + !tf_session_is_shared_session(tfs)); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Pool init failed, type:%d:%s\n", + tf_dir_2_str(parms->dir), + cfg->hcapi_type, type_str); + goto fail; + } + } + j++; + } else { + /* Bail out as we want what we requested for + * all elements, not any less. + */ + TFP_DRV_LOG(ERR, + "%s: Alloc failed %d:%s req:%d, alloc:%d\n", + tf_dir_2_str(parms->dir), cfg->hcapi_type, + type_str, req_cnt[i], resv[j].stride); + goto fail; + } + } + + rm_db->num_entries = parms->num_elements; + rm_db->dir = parms->dir; + rm_db->module = parms->module; + *parms->rm_db = (void *)rm_db; + + tfp_free((void *)req); + tfp_free((void *)resv); + tfp_free((void *)req_cnt); + return 0; + + fail: + tfp_free((void *)req); + tfp_free((void *)resv); + tfp_free((void *)db->pool); + tfp_free((void *)db); + tfp_free((void *)rm_db); + tfp_free((void *)req_cnt); + parms->rm_db = NULL; + + return -EINVAL; +} int tf_rm_free_db(struct tf *tfp, struct tf_rm_free_db_parms *parms) @@ -1043,6 +1288,36 @@ tf_rm_get_info(struct tf_rm_get_alloc_info_parms *parms) return 0; } +int +tf_rm_get_all_info(struct tf_rm_get_alloc_info_parms *parms, int size) +{ + struct tf_rm_new_db *rm_db; + enum tf_rm_elem_cfg_type cfg_type; + struct tf_rm_alloc_info *info = parms->info; + int i; + + TF_CHECK_PARMS2(parms, parms->rm_db); + rm_db = (struct tf_rm_new_db *)parms->rm_db; + TF_CHECK_PARMS1(rm_db->db); + + for (i = 0; i < size; i++) { + cfg_type = rm_db->db[i].cfg_type; + + /* Bail out if not controlled by HCAPI */ + if (cfg_type == TF_RM_ELEM_CFG_NULL) { + info++; + continue; + } + + memcpy(info, + &rm_db->db[i].alloc, + sizeof(struct tf_rm_alloc_info)); + info++; + } + + return 0; +} + int tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms) { diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h index 6eb6865dac..8b984112e8 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.h +++ b/drivers/net/bnxt/tf_core/tf_rm.h @@ -425,6 +425,24 @@ struct tf_rm_check_indexes_in_range_parms { int tf_rm_create_db(struct tf *tfp, struct tf_rm_create_db_parms *parms); +/** + * Creates and fills a Resource Manager (RM) DB with requested + * elements. The DB is indexed per the parms structure. It only retrieve + * allocated resource information for a exist session. + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to create parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_rm_create_db_no_reservation(struct tf *tfp, + struct tf_rm_create_db_parms *parms); + /** * Closes the Resource Manager (RM) DB and frees all allocated * resources per the associated database. @@ -498,6 +516,22 @@ int tf_rm_is_allocated(struct tf_rm_is_allocated_parms *parms); */ int tf_rm_get_info(struct tf_rm_get_alloc_info_parms *parms); +/** + * Retrieves all elements allocation information from the Resource + * Manager (RM) DB. + * + * [in] parms + * Pointer to get info parameters + * + * [in] size + * number of the elements for the specific module + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_rm_get_all_info(struct tf_rm_get_alloc_info_parms *parms, int size); + /** * Performs a lookup in the Resource Manager DB and retrieves the * requested HCAPI RM type. diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index f591fbe3f5..391d8786ab 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -11,6 +11,7 @@ #include "tf_common.h" #include "tf_msg.h" #include "tfp.h" +#include "bnxt.h" struct tf_session_client_create_parms { /** @@ -57,6 +58,7 @@ tf_session_create(struct tf *tfp, uint8_t fw_session_client_id; union tf_session_id *session_id; struct tf_dev_info dev; + bool shared_session_creator; TF_CHECK_PARMS2(tfp, parms); @@ -64,11 +66,12 @@ tf_session_create(struct tf *tfp, &dev); /* Open FW session and get a new session_id */ - rc = tf_msg_session_open(tfp, + rc = tf_msg_session_open(parms->open_cfg->bp, parms->open_cfg->ctrl_chan_name, &fw_session_id, &fw_session_client_id, - &dev); + &dev, + &shared_session_creator); if (rc) { /* Log error */ if (rc == -EEXIST) @@ -137,6 +140,7 @@ tf_session_create(struct tf *tfp, session_id->id = session->session_id.id; session->shadow_copy = parms->open_cfg->shadow_copy; + session->bp = parms->open_cfg->bp; /* Init session client list */ ll_init(&session->client_ll); @@ -175,12 +179,20 @@ tf_session_create(struct tf *tfp, /* Init session em_ext_db */ session->em_ext_db_handle = NULL; + if (!strcmp(parms->open_cfg->ctrl_chan_name, "tf_share")) + session->shared_session = true; + + if (session->shared_session && shared_session_creator) { + session->shared_session_creator = true; + parms->open_cfg->shared_session_creator = true; + } rc = tf_dev_bind(tfp, parms->open_cfg->device_type, session->shadow_copy, &parms->open_cfg->resources, &session->dev); + /* Logging handled by dev_bind */ if (rc) goto cleanup; @@ -857,16 +869,29 @@ tf_session_get_db(struct tf *tfp, switch (type) { case TF_MODULE_TYPE_IDENTIFIER: - *db_handle = tfs->id_db_handle; + if (tfs->id_db_handle) + *db_handle = tfs->id_db_handle; + else + rc = -EINVAL; break; case TF_MODULE_TYPE_TABLE: - *db_handle = tfs->tbl_db_handle; + if (tfs->tbl_db_handle) + *db_handle = tfs->tbl_db_handle; + else + rc = -EINVAL; + break; case TF_MODULE_TYPE_TCAM: - *db_handle = tfs->tcam_db_handle; + if (tfs->tcam_db_handle) + *db_handle = tfs->tcam_db_handle; + else + rc = -EINVAL; break; case TF_MODULE_TYPE_EM: - *db_handle = tfs->em_db_handle; + if (tfs->em_db_handle) + *db_handle = tfs->em_db_handle; + else + rc = -EINVAL; break; default: rc = -EINVAL; diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index e5c7a07daf..0b8f63c374 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -70,6 +70,23 @@ struct tf_session { */ union tf_session_id session_id; + /** + * Boolean controlling the use and availability of shared session. + * Shared session will allow the application to share resources + * on the firmware side without having to allocate them on firmware. + * Additional private session core_data will be allocated if this + * boolean is set to 'true', default 'false'. + * + */ + bool shared_session; + + /** + * This flag indicates the shared session on firmware side is created + * by this session. Some privileges may be assigned to this session. + * + */ + bool shared_session_creator; + /** * Boolean controlling the use and availability of shadow * copy. Shadow copy will allow the TruFlow Core to keep track @@ -137,6 +154,11 @@ struct tf_session { * em db reference for the session */ void *em_db_handle; + + /** + * the pointer to the parent bp struct + */ + void *bp; }; /** @@ -500,4 +522,48 @@ int tf_session_set_db(struct tf *tfp, enum tf_module_type type, void *db_handle); + +/** + * Check if the session is shared session. + * + * [in] session, pointer to the session + * + * Returns: + * - true if it is shared session + * - false if it is not shared session + */ +static inline bool +tf_session_is_shared_session(struct tf_session *tfs) +{ + return tfs->shared_session; +} + +/** + * Check if the session is the shared session creator + * + * [in] session, pointer to the session + * + * Returns: + * - true if it is the shared session creator + * - false if it is not the shared session creator + */ +static inline bool +tf_session_is_shared_session_creator(struct tf_session *tfs) +{ + return tfs->shared_session_creator; +} + +/** + * Get the pointer to the parent bnxt struct + * + * [in] session, pointer to the session + * + * Returns: + * - the pointer to the parent bnxt struct + */ +static inline struct bnxt* +tf_session_get_bp(struct tf_session *tfs) +{ + return tfs->bp; +} #endif /* _TF_SESSION_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 2d0dda18c9..17fb550917 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -31,11 +31,6 @@ struct tf; */ static void *shadow_tbl_db[TF_DIR_MAX]; -/** - * Init flag, set on bind and cleared on unbind - */ -static uint8_t init; - /** * Shadow init flag, set on bind and cleared on unbind */ @@ -49,14 +44,14 @@ tf_tbl_bind(struct tf *tfp, struct tf_rm_create_db_parms db_cfg = { 0 }; struct tbl_rm_db *tbl_db; struct tfp_calloc_parms cparms; + struct tf_session *tfs; TF_CHECK_PARMS2(tfp, parms); - if (init) { - TFP_DRV_LOG(ERR, - "Table DB already initialized\n"); - return -EINVAL; - } + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; memset(&db_cfg, 0, sizeof(db_cfg)); cparms.nitems = 1; @@ -82,8 +77,11 @@ tf_tbl_bind(struct tf *tfp, db_cfg.dir = d; db_cfg.alloc_cnt = parms->resources->tbl_cnt[d].cnt; db_cfg.rm_db = (void *)&tbl_db->tbl_db[d]; - - rc = tf_rm_create_db(tfp, &db_cfg); + if (tf_session_is_shared_session(tfs) && + (!tf_session_is_shared_session_creator(tfs))) + rc = tf_rm_create_db_no_reservation(tfp, &db_cfg); + else + rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, "%s: Table DB creation failed\n", @@ -92,7 +90,6 @@ tf_tbl_bind(struct tf *tfp, return rc; } } - init = 1; TFP_DRV_LOG(INFO, "Table Type - initialized\n"); @@ -110,13 +107,6 @@ tf_tbl_unbind(struct tf *tfp) void *tbl_db_ptr = NULL; TF_CHECK_PARMS1(tfp); - /* Bail if nothing has been initialized */ - if (!init) { - TFP_DRV_LOG(INFO, - "No Table DBs created\n"); - return 0; - } - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); if (rc) { TFP_DRV_LOG(ERR, @@ -136,7 +126,6 @@ tf_tbl_unbind(struct tf *tfp) tbl_db->tbl_db[i] = NULL; } - init = 0; shadow_init = 0; return 0; @@ -157,13 +146,6 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Table DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -234,12 +216,6 @@ tf_tbl_free(struct tf *tfp __rte_unused, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Table DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -346,13 +322,6 @@ tf_tbl_set(struct tf *tfp, TF_CHECK_PARMS3(tfp, parms, parms->data); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Table DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -456,14 +425,6 @@ tf_tbl_get(struct tf *tfp, TF_CHECK_PARMS3(tfp, parms, parms->data); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Table DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -567,14 +528,6 @@ tf_tbl_bulk_get(struct tf *tfp, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Table DBs created\n", - tf_dir_2_str(parms->dir)); - - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -662,3 +615,40 @@ tf_tbl_bulk_get(struct tf *tfp, return rc; } + +int +tf_tbl_get_resc_info(struct tf *tfp, + struct tf_tbl_resource_info *tbl) +{ + int rc; + int d; + struct tf_resource_info *dinfo; + struct tf_rm_get_alloc_info_parms ainfo; + void *tbl_db_ptr = NULL; + struct tbl_rm_db *tbl_db; + + TF_CHECK_PARMS2(tfp, tbl); + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + + /* check if reserved resource for WC is multiple of num_slices */ + for (d = 0; d < TF_DIR_MAX; d++) { + ainfo.rm_db = tbl_db->tbl_db[d]; + dinfo = tbl[d].info; + + ainfo.info = (struct tf_rm_alloc_info *)dinfo; + ainfo.subtype = 0; + rc = tf_rm_get_all_info(&ainfo, TF_TBL_TYPE_MAX); + if (rc) + return rc; + } + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h index 83b72d1b3f..aba46fd161 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.h +++ b/drivers/net/bnxt/tf_core/tf_tbl.h @@ -396,4 +396,21 @@ int tf_tbl_get(struct tf *tfp, int tf_tbl_bulk_get(struct tf *tfp, struct tf_tbl_get_bulk_parms *parms); +/** + * Retrieves the allocated resource info + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to Table resource info parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int +tf_tbl_get_resc_info(struct tf *tfp, + struct tf_tbl_resource_info *tbl); + #endif /* TF_TBL_TYPE_H */ diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index c2eef26dbb..70dc539f15 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -23,11 +23,6 @@ struct tf; */ static void *shadow_tcam_db[TF_DIR_MAX]; -/** - * Init flag, set on bind and cleared on unbind - */ -static uint8_t init; - /** * Shadow init flag, set on bind and cleared on unbind */ @@ -55,12 +50,6 @@ tf_tcam_bind(struct tf *tfp, TF_CHECK_PARMS2(tfp, parms); - if (init) { - TFP_DRV_LOG(ERR, - "TCAM DB already initialized\n"); - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -118,7 +107,11 @@ tf_tcam_bind(struct tf *tfp, db_cfg.dir = d; db_cfg.alloc_cnt = parms->resources->tcam_cnt[d].cnt; db_cfg.rm_db = (void *)&tcam_db->tcam_db[d]; - rc = tf_rm_create_db(tfp, &db_cfg); + if (tf_session_is_shared_session(tfs) && + (!tf_session_is_shared_session_creator(tfs))) + rc = tf_rm_create_db_no_reservation(tfp, &db_cfg); + else + rc = tf_rm_create_db(tfp, &db_cfg); if (rc) { TFP_DRV_LOG(ERR, "%s: TCAM DB creation failed\n", @@ -143,7 +136,8 @@ tf_tcam_bind(struct tf *tfp, "%s: TCAM reserved resource is not multiple of %d\n", tf_dir_2_str(d), num_slices); - return -EINVAL; + rc = -EINVAL; + goto error; } } @@ -186,8 +180,6 @@ tf_tcam_bind(struct tf *tfp, shadow_init = 1; } - init = 1; - TFP_DRV_LOG(INFO, "TCAM - initialized\n"); @@ -211,7 +203,6 @@ tf_tcam_bind(struct tf *tfp, } shadow_init = 0; - init = 0; return rc; } @@ -227,13 +218,6 @@ tf_tcam_unbind(struct tf *tfp) struct tf_shadow_tcam_free_db_parms fshadow; TF_CHECK_PARMS1(tfp); - /* Bail if nothing has been initialized */ - if (!init) { - TFP_DRV_LOG(INFO, - "No TCAM DBs created\n"); - return 0; - } - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); if (rc) { TFP_DRV_LOG(ERR, @@ -263,7 +247,6 @@ tf_tcam_unbind(struct tf *tfp) } shadow_init = 0; - init = 0; return 0; } @@ -283,13 +266,6 @@ tf_tcam_alloc(struct tf *tfp, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No TCAM DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -372,13 +348,6 @@ tf_tcam_free(struct tf *tfp, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No TCAM DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -529,13 +498,6 @@ tf_tcam_alloc_search(struct tf *tfp, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No TCAM DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - if (!shadow_init || !shadow_tcam_db[parms->dir]) { TFP_DRV_LOG(ERR, "%s: TCAM Shadow not initialized for %s\n", tf_dir_2_str(parms->dir), @@ -660,13 +622,6 @@ tf_tcam_set(struct tf *tfp __rte_unused, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No TCAM DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -781,13 +736,6 @@ tf_tcam_get(struct tf *tfp __rte_unused, TF_CHECK_PARMS2(tfp, parms); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No TCAM DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) @@ -852,3 +800,40 @@ tf_tcam_get(struct tf *tfp __rte_unused, return 0; } + +int +tf_tcam_get_resc_info(struct tf *tfp, + struct tf_tcam_resource_info *tcam) +{ + int rc; + int d; + struct tf_resource_info *dinfo; + struct tf_rm_get_alloc_info_parms ainfo; + void *tcam_db_ptr = NULL; + struct tcam_rm_db *tcam_db; + + TF_CHECK_PARMS2(tfp, tcam); + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; + + /* check if reserved resource for WC is multiple of num_slices */ + for (d = 0; d < TF_DIR_MAX; d++) { + ainfo.rm_db = tcam_db->tcam_db[d]; + dinfo = tcam[d].info; + + ainfo.info = (struct tf_rm_alloc_info *)dinfo; + ainfo.subtype = 0; + rc = tf_rm_get_all_info(&ainfo, TF_TCAM_TBL_TYPE_MAX); + if (rc && rc != -ENOTSUP) + return rc; + } + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h index acab223532..bed17af6ae 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.h +++ b/drivers/net/bnxt/tf_core/tf_tcam.h @@ -386,4 +386,20 @@ int tf_tcam_set(struct tf *tfp, int tf_tcam_get(struct tf *tfp, struct tf_tcam_get_parms *parms); +/** + * Retrieves the allocated resource info + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_get_resc_info(struct tf *tfp, + struct tf_tcam_resource_info *parms); + #endif /* _TF_TCAM_H */ diff --git a/drivers/net/bnxt/tf_core/tfp.c b/drivers/net/bnxt/tf_core/tfp.c index 37c49b587d..4d9b37f749 100644 --- a/drivers/net/bnxt/tf_core/tfp.c +++ b/drivers/net/bnxt/tf_core/tfp.c @@ -28,7 +28,7 @@ * Returns success or failure code. */ int -tfp_send_msg_direct(struct tf *tfp, +tfp_send_msg_direct(struct bnxt *bp, struct tfp_send_msg_parms *parms) { int rc = 0; @@ -40,9 +40,7 @@ tfp_send_msg_direct(struct tf *tfp, if (parms->mailbox == TF_CHIMP_MB) use_kong_mb = 0; - rc = bnxt_hwrm_tf_message_direct(container_of(tfp, - struct bnxt, - tfp), + rc = bnxt_hwrm_tf_message_direct(bp, use_kong_mb, parms->tf_type, parms->req_data, diff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h index bcc56b0a54..58f34bbcab 100644 --- a/drivers/net/bnxt/tf_core/tfp.h +++ b/drivers/net/bnxt/tf_core/tfp.h @@ -15,6 +15,7 @@ #include #include #include +#include /** * DPDK/Driver specific log level for the BNXT Eth driver. @@ -130,7 +131,7 @@ struct tfp_calloc_parms { * -1 - Global error like not supported * -EINVAL - Parameter Error */ -int tfp_send_msg_direct(struct tf *tfp, +int tfp_send_msg_direct(struct bnxt *bp, struct tfp_send_msg_parms *parms); /** From patchwork Sun May 30 08:58:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93564 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4221A0524; Sun, 30 May 2021 11:02:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 658EB4116A; Sun, 30 May 2021 11:00:54 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 35CCB41161 for ; Sun, 30 May 2021 11:00:52 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 916067DC0; Sun, 30 May 2021 02:00:50 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 916067DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365251; bh=PL8jHtTSSTgaBwoMdYogLaWsSAM/oHudA5U92VpWXAA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FETg3lMKO0cV95rMtmCoOi41SXPcXGeDe4TsOZyBqvPn6bdkuiARN8wJl+j44QMJP JuaD9y9ffvsZcjdnvh6OcOSqRcO9+qIrwhmNy6Wk0Lu0/Si1n/AolSKnk4waOCJWm5 BzHHLOn/1i7nezI8kuZvIfysGH6Be69CuuBCJMhA= From: Venkat Duvvuru To: dev@dpdk.org Cc: Peter Spreadborough , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:46 +0530 Message-Id: <20210530085929.29695-16-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 15/58] net/bnxt: add dpool allocator for EM allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Peter Spreadborough The dpool allocator supports variable size entries and also supports defragmentation of the allocation space. EM will by default use the fixed size stack allocator. The dynamic allocator may be selected at build time. The dpool allocator supports variable size entries and also supports defragmentation of the allocation space. Signed-off-by: Peter Spreadborough Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_core/dpool.c | 373 ++++++++++++++++++ drivers/net/bnxt/tf_core/dpool.h | 309 +++++++++++++++ drivers/net/bnxt/tf_core/meson.build | 1 + drivers/net/bnxt/tf_core/tf_core.h | 42 ++ drivers/net/bnxt/tf_core/tf_device.h | 34 ++ drivers/net/bnxt/tf_core/tf_device_p58.c | 5 + drivers/net/bnxt/tf_core/tf_em.h | 26 ++ .../net/bnxt/tf_core/tf_em_hash_internal.c | 102 ++++- drivers/net/bnxt/tf_core/tf_em_internal.c | 215 ++++++++-- drivers/net/bnxt/tf_core/tf_msg.c | 69 ++++ drivers/net/bnxt/tf_core/tf_msg.h | 15 + drivers/net/bnxt/tf_core/tf_session.h | 5 + 12 files changed, 1156 insertions(+), 40 deletions(-) create mode 100644 drivers/net/bnxt/tf_core/dpool.c create mode 100644 drivers/net/bnxt/tf_core/dpool.h diff --git a/drivers/net/bnxt/tf_core/dpool.c b/drivers/net/bnxt/tf_core/dpool.c new file mode 100644 index 0000000000..a5f9f866b7 --- /dev/null +++ b/drivers/net/bnxt/tf_core/dpool.c @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ +#include +#include +#include +#include +#include + +#include + +#include "tfp.h" +#include "dpool.h" + +int dpool_init(struct dpool *dpool, + uint32_t start_index, + uint32_t size, + uint8_t max_alloc_size, + void *user_data, + int (*move_callback)(void *, uint64_t, uint32_t)) +{ + uint32_t i; + int rc; + struct tfp_calloc_parms parms; + + parms.nitems = size; + parms.size = sizeof(struct dpool_entry); + parms.alignment = 0; + + rc = tfp_calloc(&parms); + + if (rc) + return rc; + + dpool->entry = parms.mem_va; + dpool->start_index = start_index; + dpool->size = size; + dpool->max_alloc_size = max_alloc_size; + dpool->user_data = user_data; + dpool->move_callback = move_callback; + /* + * Init entries + */ + for (i = 0; i < size; i++) { + dpool->entry[i].flags = 0; + dpool->entry[i].index = start_index; + dpool->entry[i].entry_data = 0UL; + start_index++; + } + + return 0; +} + +static int dpool_move(struct dpool *dpool, + uint32_t dst_index, + uint32_t src_index) +{ + uint32_t size; + uint32_t i; + if (DP_IS_FREE(dpool->entry[dst_index].flags)) { + size = DP_FLAGS_SIZE(dpool->entry[src_index].flags); + + dpool->entry[dst_index].flags = dpool->entry[src_index].flags; + dpool->entry[dst_index].entry_data = dpool->entry[src_index].entry_data; + + if (dpool->move_callback != NULL) { + dpool->move_callback(dpool->user_data, + dpool->entry[src_index].entry_data, + dst_index + dpool->start_index); + } + + dpool->entry[src_index].flags = 0; + dpool->entry[src_index].entry_data = 0UL; + + for (i = 1; i < size; i++) { + dpool->entry[dst_index + i].flags = size; + dpool->entry[src_index + i].flags = 0; + } + } else { + return -1; + } + + return 0; +} + + +int dpool_defrag(struct dpool *dpool, + uint32_t entry_size, + uint8_t defrag) +{ + struct dpool_free_list *free_list; + struct dpool_adj_list *adj_list; + uint32_t count; + uint32_t index; + uint32_t used; + uint32_t i; + uint32_t size; + uint32_t largest_free_index = 0; + uint32_t largest_free_size; + uint32_t max; + uint32_t max_index; + uint32_t max_size = 0; + int rc; + + free_list = rte_zmalloc("dpool_free_list", + sizeof(struct dpool_free_list), 0); + if (free_list == NULL) { + TFP_DRV_LOG(ERR, "dpool free list allocation failed\n"); + return -ENOMEM; + } + + adj_list = rte_zmalloc("dpool_adjacent_list", + sizeof(struct dpool_adj_list), 0); + if (adj_list == NULL) { + TFP_DRV_LOG(ERR, "dpool adjacent list allocation failed\n"); + return -ENOMEM; + } + + while (1) { + /* + * Create list of free entries + */ + free_list->size = 0; + largest_free_size = 0; + largest_free_index = 0; + count = 0; + + for (i = 0; i < dpool->size; i++) { + if (DP_IS_FREE(dpool->entry[i].flags)) { + if (count == 0) + index = i; + count++; + } else if (count > 0) { + free_list->entry[free_list->size].index = index; + free_list->entry[free_list->size].size = count; + + if (count > largest_free_size) { + largest_free_index = free_list->size; + largest_free_size = count; + } + + free_list->size++; + count = 0; + } + } + + if (free_list->size == 0) + largest_free_size = count; + + /* + * If using defrag to fit and there's a large enough + * space then we are done. + */ + if (defrag == DP_DEFRAG_TO_FIT && + largest_free_size >= entry_size) + goto done; + + /* + * Create list of entries adjacent to free entries + */ + count = 0; + adj_list->size = 0; + used = 0; + + for (i = 0; i < dpool->size; ) { + if (DP_IS_USED(dpool->entry[i].flags)) { + used++; + + if (count > 0) { + adj_list->entry[adj_list->size].index = i; + adj_list->entry[adj_list->size].size = + DP_FLAGS_SIZE(dpool->entry[i].flags); + adj_list->entry[adj_list->size].left = count; + + if (adj_list->size > 0 && used == 1) + adj_list->entry[adj_list->size - 1].right = count; + + adj_list->size++; + } + + count = 0; + i += DP_FLAGS_SIZE(dpool->entry[i].flags); + } else { + used = 0; + count++; + i++; + } + } + + /* + * Using the size of the largest free space available + * select the adjacency list entry of that size with + * the largest left + right + size count. If there + * are no entries of that size then decrement the size + * and try again. + */ + max = 0; + max_index = 0; + max_size = 0; + + for (size = largest_free_size; size > 0; size--) { + for (i = 0; i < adj_list->size; i++) { + if (adj_list->entry[i].size == size && + ((size + + adj_list->entry[i].left + + adj_list->entry[i].right) > max)) { + max = size + + adj_list->entry[i].left + + adj_list->entry[i].right; + max_size = size; + max_index = adj_list->entry[i].index; + } + } + + if (max) + break; + } + + /* + * If the max entry is smaller than the largest_free_size + * find the first entry in the free list that it cn fit in to. + */ + if (max_size < largest_free_size) { + for (i = 0; i < free_list->size; i++) { + if (free_list->entry[i].size >= max_size) { + largest_free_index = i; + break; + } + } + } + + /* + * If we have a contender then move it to the new spot. + */ + if (max) { + rc = dpool_move(dpool, + free_list->entry[largest_free_index].index, + max_index); + if (rc) { + rte_free(free_list); + rte_free(adj_list); + return rc; + } + } else { + break; + } + } + +done: + rte_free(free_list); + rte_free(adj_list); + return largest_free_size; +} + + +uint32_t dpool_alloc(struct dpool *dpool, + uint32_t size, + uint8_t defrag) +{ + uint32_t i; + uint32_t j; + uint32_t count = 0; + uint32_t first_entry_index; + int rc; + + if (size > dpool->max_alloc_size || size == 0) + return DP_INVALID_INDEX; + + /* + * Defrag requires EM move support. + */ + if (defrag != DP_DEFRAG_NONE && + dpool->move_callback == NULL) + return DP_INVALID_INDEX; + + while (1) { + /* + * find consecutive free entries + */ + for (i = 0; i < dpool->size; i++) { + if (DP_IS_FREE(dpool->entry[i].flags)) { + if (count == 0) + first_entry_index = i; + + count++; + + if (count == size) { + for (j = 0; j < size; j++) { + dpool->entry[j + first_entry_index].flags = size; + if (j == 0) + dpool->entry[j + first_entry_index].flags |= DP_FLAGS_START; + } + + dpool->entry[i].entry_data = 0UL; + return (first_entry_index + dpool->start_index); + } + } else { + count = 0; + } + } + + /* + * If defragging then do it to it + */ + if (defrag != DP_DEFRAG_NONE) { + rc = dpool_defrag(dpool, size, defrag); + + if (rc < 0) + return DP_INVALID_INDEX; + } else { + break; + } + + /* + * If the defrag created enough space then try the + * alloc again else quit. + */ + if ((uint32_t)rc < size) + break; + } + + return DP_INVALID_INDEX; +} + +int dpool_free(struct dpool *dpool, + uint32_t index) +{ + uint32_t i; + int start = (index - dpool->start_index); + uint32_t size; + + if (start < 0) + return -1; + + if (DP_IS_START(dpool->entry[start].flags)) { + size = DP_FLAGS_SIZE(dpool->entry[start].flags); + if (size > dpool->max_alloc_size || size == 0) + return -1; + + for (i = start; i < (start + size); i++) + dpool->entry[i].flags = 0; + + return 0; + } + + return -1; +} + +void dpool_free_all(struct dpool *dpool) +{ + uint32_t i; + + for (i = 0; i < dpool->size; i++) + dpool_free(dpool, dpool->entry[i].index); +} + +int dpool_set_entry_data(struct dpool *dpool, + uint32_t index, + uint64_t entry_data) +{ + int start = (index - dpool->start_index); + + if (start < 0) + return -1; + + if (DP_IS_START(dpool->entry[start].flags)) { + dpool->entry[start].entry_data = entry_data; + return 0; + } + + return -1; +} diff --git a/drivers/net/bnxt/tf_core/dpool.h b/drivers/net/bnxt/tf_core/dpool.h new file mode 100644 index 0000000000..db9d53f01f --- /dev/null +++ b/drivers/net/bnxt/tf_core/dpool.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#ifndef _DPOOL_H_ +#define _DPOOL_H_ + +#include +#include + +#define DP_MAX_FREE_SIZE 0x8000 /* 32K */ + +#define DP_INVALID_INDEX 0xffffffff + +#define DP_FLAGS_START 0x80000000 +#define DP_IS_START(flags) ((flags) & DP_FLAGS_START) + +#define DP_FLAGS_SIZE_SHIFT 0 +#define DP_FLAGS_SIZE_MASK 0x07 + +#define DP_FLAGS_SIZE(flags) (((flags) >> DP_FLAGS_SIZE_SHIFT) & DP_FLAGS_SIZE_MASK) + +#define DP_IS_FREE(flags) (((flags) & DP_FLAGS_SIZE_MASK) == 0) +#define DP_IS_USED(flags) ((flags) & DP_FLAGS_SIZE_MASK) + +#define DP_DEFRAG_NONE 0x0 +#define DP_DEFRAG_ALL 0x1 +#define DP_DEFRAG_TO_FIT 0x2 + +/** + * Free list entry + * + * Each entry includes an index in to the dpool entry array + * and the size of dpool array entry. + */ +struct dpool_free_list_entry { + /* + * Index in to dpool entry array + */ + uint32_t index; + /* + * The size of the entry in the dpool entry array + */ + uint32_t size; +}; + +/** + * Free list + * + * Used internally to record free entries in the dpool entry array. + * Each entry represents a single or multiple contiguious entries + * in the dpool entry array. + * + * Used only during the defrag operation. + */ +struct dpool_free_list { + /* + * Number of entries in the free list + */ + uint32_t size; + /* + * List of unused entries in the dpool entry array + */ + struct dpool_free_list_entry entry[DP_MAX_FREE_SIZE]; +}; + +/** + * Adjacent list entry + * + * Each entry includes and index in to the dpool entry array, + * the size of the entry and the counts of free entries to the + * right and left off that entry. + */ +struct dpool_adj_list_entry { + /* + * Index in to dpool entry array + */ + uint32_t index; + /* + * The size of the entry in the dpool entry array + */ + uint32_t size; + /* + * Number of free entries directly to the left of + * this entry + */ + uint32_t left; + /* + * Number of free entries directly to the right of + * this entry + */ + uint32_t right; +}; + +/** + * Adjacent list + * + * A list of references to entries in the dpool entry array that + * have free entries to the left and right. Since we pack to the + * left entries will always have a non zero left cout. + * + * Used only during the defrag operation. + */ +struct dpool_adj_list { + /* + * Number of entries in the adj list + */ + uint32_t size; + /* + * List of entries in the dpool entry array that have + * free entries directly to their left and right. + */ + struct dpool_adj_list_entry entry[DP_MAX_FREE_SIZE]; +}; + +/** + * Dpool entry + * + * Each entry includes flags and the FW index. + */ +struct dpool_entry { + uint32_t flags; + uint32_t index; + uint64_t entry_data; +}; + +/** + * Dpool + * + * Used to manage resource pool. Includes the start FW index, the + * size of the entry array and the entry array it's self. + */ +struct dpool { + uint32_t start_index; + uint32_t size; + uint8_t max_alloc_size; + void *user_data; + int (*move_callback)(void *user_data, + uint64_t entry_data, + uint32_t new_index); + struct dpool_entry *entry; +}; + +/** + * dpool_init + * + * Initialize the dpool + * + * [in] dpool + * Pointer to a dpool structure that includes an entry field + * that points to the entry array. The user is responsible for + * allocating memory for the dpool struct and the entry array. + * + * [in] start_index + * The base index to use. + * + * [in] size + * The number of entries + * + * [in] max_alloc_size + * The number of entries + * + * [in] user_data + * Pointer to user data. Will be passed in callbacks. + * + * [in] move_callback + * Pointer to move EM entry callback. + * + * Return + * - 0 on success + * - -1 on failure + * + */ +int dpool_init(struct dpool *dpool, + uint32_t start_index, + uint32_t size, + uint8_t max_alloc_size, + void *user_data, + int (*move_callback)(void *, uint64_t, uint32_t)); + +/** + * dpool_alloc + * + * Request a FW index of size and if necessary de-fragment the dpool + * array. + * + * [i] dpool + * The dpool + * + * [i] size + * The size of the requested allocation. + * + * [i] defrag + * Operation to apply when there is insufficient space: + * + * DP_DEFRAG_NONE (0x0) - Don't do anything. + * DP_DEFRAG_ALL (0x1) - Defrag until there is nothing left + * to defrag. + * DP_DEFRAG_TO_FIT (0x2) - Defrag until there is just enough space + * to insert the requested allocation. + * + * Return + * - FW index on success + * - DP_INVALID_INDEX on failure + * + */ +uint32_t dpool_alloc(struct dpool *dpool, + uint32_t size, + uint8_t defrag); + +/** + * dpool_set_entry_data + * + * Set the entry data field. This will be passed to callbacks. + * + * [i] dpool + * The dpool + * + * [i] index + * FW index + * + * [i] entry_data + * Entry data value + * + * Return + * - FW index on success + * - DP_INVALID_INDEX on failure + * + */ +int dpool_set_entry_data(struct dpool *dpool, + uint32_t index, + uint64_t entry_data); + +/** + * dpool_free + * + * Free allocated entry. The is responsible for the dpool and dpool + * entry array memory. + * + * [in] dpool + * The pool + * + * [in] index + * FW index to free up. + * + * Result + * - 0 on success + * - -1 on failure + * + */ +int dpool_free(struct dpool *dpool, + uint32_t index); + +/** + * dpool_free_all + * + * Free all entries. + * + * [in] dpool + * The pool + * + * Result + * - 0 on success + * - -1 on failure + * + */ +void dpool_free_all(struct dpool *dpool); + +/** + * dpool_dump + * + * Debug/util function to dump the dpool array. + * + * [in] dpool + * The pool + * + */ +void dpool_dump(struct dpool *dpool); + +/** + * dpool_defrag + * + * De-fragment the dpool array and apply the specified defrag stratagy. + * + * [in] dpool + * The dpool + * + * [in] entry_size + * If using the DP_DEFRAG_TO_FIT stratagy defrag will stop when there's + * at least entry_size space available. + * + * [i] defrag + * Defrag stratagy: + * + * DP_DEFRAG_ALL (0x1) - Defrag until there is nothing left + * to defrag. + * DP_DEFRAG_TO_FIT (0x2) - Defrag until there is just enough space + * to insert the requested allocation. + * + * Return + * < 0 - on failure + * > 0 - The size of the largest free space + */ +int dpool_defrag(struct dpool *dpool, + uint32_t entry_size, + uint8_t defrag); + +#endif /* _DPOOL_H_ */ diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index 2c02214d83..3a91f04bc0 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -10,6 +10,7 @@ sources += files( 'tf_core.c', 'bitalloc.c', 'tf_msg.c', + 'dpool.c', 'rand.c', 'stack.c', 'tf_em_common.c', diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 4440d60fe5..08a083077c 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -1953,6 +1953,48 @@ struct tf_delete_em_entry_parms { */ uint64_t flow_handle; }; +/** + * tf_move_em_entry parameter definition + */ +struct tf_move_em_entry_parms { + /** + * [in] receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] internal or external + */ + enum tf_mem mem; + /** + * [in] ID of table scope to use (external only) + */ + uint32_t tbl_scope_id; + /** + * [in] ID of table interface to use (SR2 only) + */ + uint32_t tbl_if_id; + /** + * [in] epoch group IDs of entry to delete + * 2 element array with 2 ids. (SR2 only) + */ + uint16_t *epochs; + /** + * [out] The index of the entry + */ + uint16_t index; + /** + * [in] External memory channel type to use + */ + enum tf_ext_mem_chan_type chan_type; + /** + * [in] The index of the new EM record + */ + uint32_t new_index; + /** + * [in] structure containing flow delete handle information + */ + uint64_t flow_handle; +}; /** * tf_search_em_entry parameter definition */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 16c2fe0f64..31806bb289 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -611,6 +611,22 @@ struct tf_dev_ops { int (*tf_dev_delete_int_em_entry)(struct tf *tfp, struct tf_delete_em_entry_parms *parms); + /** + * Move EM hash entry API + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to E/EM move parameters + * + * returns: + * 0 - Success + * -EINVAL - Error + */ + int (*tf_dev_move_int_em_entry)(struct tf *tfp, + struct tf_move_em_entry_parms *parms); + /** * Insert EEM hash entry API * @@ -661,6 +677,24 @@ struct tf_dev_ops { int (*tf_dev_get_em_resc_info)(struct tf *tfp, struct tf_em_resource_info *parms); + /** + * Move EEM hash entry API + * + * Pointer to E/EM move parameters + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to em info + * + * returns: + * 0 - Success + * -EINVAL - Error + */ + int (*tf_dev_move_ext_em_entry)(struct tf *tfp, + struct tf_move_em_entry_parms *parms); + /** * Allocate EEM table scope * diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index c2bc283220..7917c9613a 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -295,6 +295,11 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, +#if (TF_EM_ALLOC == 1) + .tf_dev_move_int_em_entry = tf_em_move_int_entry, +#else + .tf_dev_move_int_em_entry = NULL, +#endif .tf_dev_insert_ext_em_entry = NULL, .tf_dev_delete_ext_em_entry = NULL, .tf_dev_get_em_resc_info = tf_em_get_resc_info, diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 60d90e28de..9d168c3c7f 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -13,6 +13,16 @@ #include "hcapi_cfa_defs.h" +/** + * TF_EM_ALLOC + * + * 0: Use stack allocator with fixed sized entries + * (default). + * 1: Use dpool allocator with variable size + * entries. + */ +#define TF_EM_ALLOC 0 + #define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */ #define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */ @@ -243,6 +253,22 @@ int tf_em_hash_insert_int_entry(struct tf *tfp, int tf_em_hash_delete_int_entry(struct tf *tfp, struct tf_delete_em_entry_parms *parms); +/** + * Move record from internal EM table + * + * [in] tfp + * Pointer to TruFlow handle + * + * [in] parms + * Pointer to input parameters + * + * Returns: + * 0 - Success + * -EINVAL - Parameter error + */ +int tf_em_move_int_entry(struct tf *tfp, + struct tf_move_em_entry_parms *parms); + /** * Insert record in to external EEM table * diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c index f6c9772b44..098e8af07e 100644 --- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c @@ -22,7 +22,9 @@ /** * EM Pool */ -extern struct stack em_pool[TF_DIR_MAX]; +#if (TF_EM_ALLOC == 1) +#include "dpool.h" +#endif /** * Insert EM internal entry API @@ -39,7 +41,11 @@ tf_em_hash_insert_int_entry(struct tf *tfp, uint16_t rptr_index = 0; uint8_t rptr_entry = 0; uint8_t num_of_entries = 0; - struct stack *pool = &em_pool[parms->dir]; +#if (TF_EM_ALLOC == 1) + struct dpool *pool; +#else + struct stack *pool; +#endif uint32_t index; uint32_t key0_hash; uint32_t key1_hash; @@ -56,7 +62,20 @@ tf_em_hash_insert_int_entry(struct tf *tfp, rc = tf_session_get_device(tfs, &dev); if (rc) return rc; +#if (TF_EM_ALLOC == 1) + pool = (struct dpool *)tfs->em_pool[parms->dir]; + index = dpool_alloc(pool, + parms->em_record_sz_in_bits / 128, + DP_DEFRAG_TO_FIT); + if (index == DP_INVALID_INDEX) { + PMD_DRV_LOG(ERR, + "%s, EM entry index allocation failed\n", + tf_dir_2_str(parms->dir)); + return -1; + } +#else + pool = (struct stack *)tfs->em_pool[parms->dir]; rc = stack_pop(pool, &index); if (rc) { PMD_DRV_LOG(ERR, @@ -64,6 +83,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp, tf_dir_2_str(parms->dir)); return rc; } +#endif if (dev->ops->tf_dev_cfa_key_hash == NULL) return -EINVAL; @@ -83,19 +103,14 @@ tf_em_hash_insert_int_entry(struct tf *tfp, &num_of_entries); if (rc) { /* Free the allocated index before returning */ +#if (TF_EM_ALLOC == 1) + dpool_free(pool, index); +#else stack_push(pool, index); +#endif return -1; } - PMD_DRV_LOG - (DEBUG, - "%s, Internal entry @ Index:%d rptr_index:0x%x rptr_entry:0x%x num_of_entries:%d\n", - tf_dir_2_str(parms->dir), - index, - rptr_index, - rptr_entry, - num_of_entries); - TF_SET_GFID(gfid, ((rptr_index << TF_EM_INTERNAL_INDEX_SHIFT) | rptr_entry), @@ -113,6 +128,9 @@ tf_em_hash_insert_int_entry(struct tf *tfp, rptr_index, rptr_entry, 0); +#if (TF_EM_ALLOC == 1) + dpool_set_entry_data(pool, index, parms->flow_handle); +#endif return 0; } @@ -127,13 +145,71 @@ tf_em_hash_delete_int_entry(struct tf *tfp, struct tf_delete_em_entry_parms *parms) { int rc = 0; - struct stack *pool = &em_pool[parms->dir]; + struct tf_session *tfs; +#if (TF_EM_ALLOC == 1) + struct dpool *pool; +#else + struct stack *pool; +#endif + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } rc = tf_msg_delete_em_entry(tfp, parms); /* Return resource to pool */ - if (rc == 0) + if (rc == 0) { +#if (TF_EM_ALLOC == 1) + pool = (struct dpool *)tfs->em_pool[parms->dir]; + dpool_free(pool, parms->index); +#else + pool = (struct stack *)tfs->em_pool[parms->dir]; stack_push(pool, parms->index); +#endif + } + + return rc; +} + +#if (TF_EM_ALLOC == 1) +/** Move EM internal entry API + * + * returns: + * 0 + * -EINVAL + */ +int +tf_em_move_int_entry(struct tf *tfp, + struct tf_move_em_entry_parms *parms) +{ + int rc = 0; + struct dpool *pool; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = tf_msg_move_em_entry(tfp, parms); + + /* Return resource to pool */ + if (rc == 0) { + pool = (struct dpool *)tfs->em_pool[parms->dir]; + dpool_free(pool, parms->index); + } return rc; } +#endif diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index e373a9b029..eec15b89bc 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -15,7 +15,6 @@ #include "tf_msg.h" #include "tfp.h" #include "tf_ext_flow_handle.h" - #include "bnxt.h" #define TF_EM_DB_EM_REC 0 @@ -23,7 +22,9 @@ /** * EM Pool */ -struct stack em_pool[TF_DIR_MAX]; +#if (TF_EM_ALLOC == 1) +#include "dpool.h" +#else /** * Create EM Tbl pool of memory indexes. @@ -41,14 +42,35 @@ struct stack em_pool[TF_DIR_MAX]; * - Failure, entry not allocated, out of resources */ static int -tf_create_em_pool(enum tf_dir dir, +tf_create_em_pool(struct tf_session *tfs, + enum tf_dir dir, uint32_t num_entries, uint32_t start) { struct tfp_calloc_parms parms; uint32_t i, j; int rc = 0; - struct stack *pool = &em_pool[dir]; + struct stack *pool; + + /* + * Allocate stack pool + */ + parms.nitems = 1; + parms.size = sizeof(struct stack); + parms.alignment = 0; + + rc = tfp_calloc(&parms); + + if (rc) { + TFP_DRV_LOG(ERR, + "%s, EM stack allocation failure %s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + pool = (struct stack *)parms.mem_va; + tfs->em_pool[dir] = (void *)pool; /* Assumes that num_entries has been checked before we get here */ parms.nitems = num_entries / TF_SESSION_EM_ENTRY_SIZE; @@ -108,6 +130,8 @@ tf_create_em_pool(enum tf_dir dir, return 0; cleanup: tfp_free((void *)parms.mem_va); + tfp_free((void *)tfs->em_pool[dir]); + tfs->em_pool[dir] = NULL; return rc; } @@ -120,16 +144,23 @@ tf_create_em_pool(enum tf_dir dir, * Return: */ static void -tf_free_em_pool(enum tf_dir dir) +tf_free_em_pool(struct tf_session *tfs, + enum tf_dir dir) { - struct stack *pool = &em_pool[dir]; + struct stack *pool = (struct stack *)tfs->em_pool[dir]; uint32_t *ptr; - ptr = stack_items(pool); + if (pool != NULL) { + ptr = stack_items(pool); + + if (ptr != NULL) + tfp_free(ptr); - if (ptr != NULL) - tfp_free(ptr); + tfp_free(pool); + tfs->em_pool[dir] = NULL; + } } +#endif /* TF_EM_ALLOC != 1 */ /** * Insert EM internal entry API @@ -146,17 +177,44 @@ tf_em_insert_int_entry(struct tf *tfp, uint16_t rptr_index = 0; uint8_t rptr_entry = 0; uint8_t num_of_entries = 0; - struct stack *pool = &em_pool[parms->dir]; + struct tf_session *tfs; +#if (TF_EM_ALLOC == 1) + struct dpool *pool; +#else + struct stack *pool; +#endif uint32_t index; - rc = stack_pop(pool, &index); + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } +#if (TF_EM_ALLOC == 1) + pool = (struct dpool *)tfs->em_pool[parms->dir]; + index = dpool_alloc(pool, TF_SESSION_EM_ENTRY_SIZE, 0); + if (index == DP_INVALID_INDEX) { + PMD_DRV_LOG(ERR, + "%s, EM entry index allocation failed\n", + tf_dir_2_str(parms->dir)); + return -1; + } +#else + pool = (struct stack *)tfs->em_pool[parms->dir]; + rc = stack_pop(pool, &index); if (rc) { PMD_DRV_LOG(ERR, "%s, EM entry index allocation failed\n", tf_dir_2_str(parms->dir)); return rc; } +#endif + rptr_index = index; rc = tf_msg_insert_em_internal_entry(tfp, @@ -166,19 +224,13 @@ tf_em_insert_int_entry(struct tf *tfp, &num_of_entries); if (rc) { /* Free the allocated index before returning */ +#if (TF_EM_ALLOC == 1) + dpool_free(pool, index); +#else stack_push(pool, index); +#endif return -1; } - - PMD_DRV_LOG - (DEBUG, - "%s, Internal entry @ Index:%d rptr_index:0x%x rptr_entry:0x%x num_of_entries:%d\n", - tf_dir_2_str(parms->dir), - index, - rptr_index, - rptr_entry, - num_of_entries); - TF_SET_GFID(gfid, ((rptr_index << TF_EM_INTERNAL_INDEX_SHIFT) | rptr_entry), @@ -211,16 +263,86 @@ tf_em_delete_int_entry(struct tf *tfp, struct tf_delete_em_entry_parms *parms) { int rc = 0; - struct stack *pool = &em_pool[parms->dir]; + struct tf_session *tfs; +#if (TF_EM_ALLOC == 1) + struct dpool *pool; +#else + struct stack *pool; +#endif + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } rc = tf_msg_delete_em_entry(tfp, parms); /* Return resource to pool */ - if (rc == 0) + if (rc == 0) { +#if (TF_EM_ALLOC == 1) + pool = (struct dpool *)tfs->em_pool[parms->dir]; + dpool_free(pool, parms->index); +#else + pool = (struct stack *)tfs->em_pool[parms->dir]; stack_push(pool, parms->index); +#endif + } + + return rc; +} + +#if (TF_EM_ALLOC == 1) +static int +tf_em_move_callback(void *user_data, + uint64_t entry_data, + uint32_t new_index) +{ + int rc; + struct tf *tfp = (struct tf *)user_data; + struct tf_move_em_entry_parms parms; + struct tf_dev_info *dev; + struct tf_session *tfs; + + memset(&parms, 0, sizeof(parms)); + + parms.tbl_scope_id = 0; + parms.flow_handle = entry_data; + parms.new_index = new_index; + TF_GET_DIR_FROM_FLOW_ID(entry_data, parms.dir); + parms.mem = TF_MEM_INTERNAL; + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms.dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(parms.dir), + strerror(-rc)); + return rc; + } + + if (dev->ops->tf_dev_move_int_em_entry != NULL) + rc = dev->ops->tf_dev_move_int_em_entry(tfp, &parms); + else + rc = -EOPNOTSUPP; return rc; } +#endif int tf_em_int_bind(struct tf *tfp, @@ -311,14 +433,49 @@ tf_em_int_bind(struct tf *tfp, tf_dir_2_str(i)); return rc; } +#if (TF_EM_ALLOC == 1) + /* + * Allocate stack pool + */ + cparms.nitems = 1; + cparms.size = sizeof(struct dpool); + cparms.alignment = 0; + + rc = tfp_calloc(&cparms); - rc = tf_create_em_pool(i, - iparms.info->entry.stride, - iparms.info->entry.start); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, EM stack allocation failure %s\n", + tf_dir_2_str(i), + strerror(-rc)); + return rc; + } + + tfs->em_pool[i] = (struct dpool *)cparms.mem_va; + + rc = dpool_init(tfs->em_pool[i], + iparms.info->entry.start, + iparms.info->entry.stride, + 7, + (void *)tfp, + tf_em_move_callback); +#else + rc = tf_create_em_pool(tfs, + i, + iparms.info->entry.stride, + iparms.info->entry.start); +#endif /* Logging handled in tf_create_em_pool */ if (rc) return rc; } + + if (rc) { + TFP_DRV_LOG(ERR, + "%s: EM pool init failed\n", + tf_dir_2_str(i)); + return rc; + } } return 0; @@ -343,7 +500,11 @@ tf_em_int_unbind(struct tf *tfp) if (!tf_session_is_shared_session(tfs)) { for (i = 0; i < TF_DIR_MAX; i++) - tf_free_em_pool(i); +#if (TF_EM_ALLOC == 1) + dpool_free_all(tfs->em_pool[i]); +#else + tf_free_em_pool(tfs, i); +#endif } rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 4a840f3473..2ee8a1e8a9 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1004,6 +1004,75 @@ tf_msg_delete_em_entry(struct tf *tfp, return 0; } +int +tf_msg_move_em_entry(struct tf *tfp, + struct tf_move_em_entry_parms *em_parms) +{ + int rc; + struct tfp_send_msg_parms parms = { 0 }; + struct hwrm_tf_em_move_input req = { 0 }; + struct hwrm_tf_em_move_output resp = { 0 }; + uint16_t flags; + uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Unable to lookup FW id, rc:%s\n", + tf_dir_2_str(em_parms->dir), + strerror(-rc)); + return rc; + } + + /* Populate the request */ + req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + + flags = (em_parms->dir == TF_DIR_TX ? + HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX : + HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX); + req.flags = tfp_cpu_to_le_16(flags); + req.flow_handle = tfp_cpu_to_le_64(em_parms->flow_handle); + req.new_index = tfp_cpu_to_le_32(em_parms->new_index); + + parms.tf_type = HWRM_TF_EM_MOVE; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + &parms); + if (rc) + return rc; + + em_parms->index = tfp_le_to_cpu_16(resp.em_index); + + return 0; +} + int tf_msg_ext_em_ctxt_mem_alloc(struct tf *tfp, struct hcapi_cfa_em_table *tbl, uint64_t *dma_addr, diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 5ecaf9e7e7..e8662fef0e 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -315,6 +315,21 @@ tf_msg_hash_insert_em_internal_entry(struct tf *tfp, int tf_msg_delete_em_entry(struct tf *tfp, struct tf_delete_em_entry_parms *em_parms); +/** + * Sends EM internal move request to Firmware + * + * [in] tfp + * Pointer to TF handle + * + * [in] em_parms + * Pointer to em move parameters + * + * Returns: + * 0 on Success else internal Truflow error + */ +int tf_msg_move_em_entry(struct tf *tfp, + struct tf_move_em_entry_parms *em_parms); + /** * Sends Ext EM mem allocation request to Firmware * diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index 0b8f63c374..e2cebd20a1 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -159,6 +159,11 @@ struct tf_session { * the pointer to the parent bp struct */ void *bp; + + /** + * EM allocator for session + */ + void *em_pool[TF_DIR_MAX]; }; /** From patchwork Sun May 30 08:58:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93565 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C33A3A0524; Sun, 30 May 2021 11:02:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DE45441176; Sun, 30 May 2021 11:00:55 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id E10EA4113A for ; Sun, 30 May 2021 11:00:53 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 4C7F97DAF; Sun, 30 May 2021 02:00:52 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 4C7F97DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365253; bh=I+FF1tWpHWt1ID9vmEhGoO6WHMt4QBoje4JKy62qx40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tyRuE3lHFBVEzx4UnF/D/3yTsbSRbN33MS6Ks1ZEdeQbxqpXMwN2fxRfSKBZwEi3K 77n9Z54XyndZj5HoTZ5ZMVPuXIFcRACWro9GNppuN0JJN3+YfCGhGHWR6BU6V1iSz7 UhEGT1k3RjkoIs2Ja9nCEJgZFYhOVYAF0QjCjxqM= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:47 +0530 Message-Id: <20210530085929.29695-17-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 16/58] net/bnxt: update shared session functionality X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding - Distinguish the shared session on host side using PCI address - One session could be shared by multiple interfaces. Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_core/tf_core.c | 9 --- drivers/net/bnxt/tf_core/tf_core.h | 4 ++ drivers/net/bnxt/tf_core/tf_device.c | 28 +++++---- drivers/net/bnxt/tf_core/tf_device_p58.c | 7 ++- drivers/net/bnxt/tf_core/tf_em_internal.c | 23 ++++---- drivers/net/bnxt/tf_core/tf_identifier.c | 15 ++--- drivers/net/bnxt/tf_core/tf_msg.c | 69 +++++++++++++---------- drivers/net/bnxt/tf_core/tf_session.c | 13 ++++- drivers/net/bnxt/tf_core/tf_session.h | 9 +-- drivers/net/bnxt/tf_core/tf_tbl.c | 57 ++++++++++++++++--- drivers/net/bnxt/tf_core/tf_tcam.c | 15 ++--- drivers/net/bnxt/tf_core/tfp.c | 4 +- 12 files changed, 153 insertions(+), 100 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 69f5c10293..945e54bfdd 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -27,8 +27,6 @@ tf_open_session(struct tf *tfp, int rc; unsigned int domain, bus, slot, device; struct tf_session_open_session_parms oparms; - int name_len; - char *name; TF_CHECK_PARMS2(tfp, parms); @@ -71,13 +69,6 @@ tf_open_session(struct tf *tfp, } } - name_len = strlen(parms->ctrl_chan_name); - name = &parms->ctrl_chan_name[name_len - strlen("tf_shared")]; - if (!strncmp(name, "tf_shared", strlen("tf_shared"))) { - memset(parms->ctrl_chan_name, 0, strlen(parms->ctrl_chan_name)); - strcpy(parms->ctrl_chan_name, "tf_share"); - } - parms->session_id.internal.domain = domain; parms->session_id.internal.bus = bus; parms->session_id.internal.device = device; diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 08a083077c..3d14dc5391 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -458,6 +458,10 @@ struct tf_session_info { */ struct tf { struct tf_session_info *session; + /** + * the pointer to the parent bp struct + */ + void *bp; }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index fed4156200..97ae73fa5a 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -44,7 +44,11 @@ tf_dev_reservation_check(uint16_t count, rm_num = (uint16_t *)reservations + i * count; for (j = 0; j < count; j++) { if ((cfg[j].cfg_type == TF_RM_ELEM_CFG_HCAPI || - cfg[j].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA) && + cfg[j].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA || + cfg[j].cfg_type == + TF_RM_ELEM_CFG_HCAPI_BA_PARENT || + cfg[j].cfg_type == + TF_RM_ELEM_CFG_HCAPI_BA_CHILD) && rm_num[j] > 0) cnt++; } @@ -263,49 +267,49 @@ tf_dev_unbind_p4(struct tf *tfp) */ rc = tf_tcam_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, TCAM\n"); fail = true; } rc = tf_ident_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, Identifier\n"); fail = true; } rc = tf_tbl_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, Table Type\n"); fail = true; } rc = tf_em_ext_common_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, EEM\n"); fail = true; } rc = tf_em_int_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, EM\n"); fail = true; } rc = tf_if_tbl_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, IF Table Type\n"); fail = true; } rc = tf_global_cfg_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, Global Cfg Type\n"); fail = true; } @@ -515,28 +519,28 @@ tf_dev_unbind_p58(struct tf *tfp) */ rc = tf_tcam_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, TCAM\n"); fail = true; } rc = tf_ident_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, Identifier\n"); fail = true; } rc = tf_tbl_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, Table Type\n"); fail = true; } rc = tf_em_int_unbind(tfp); if (rc) { - TFP_DRV_LOG(ERR, + TFP_DRV_LOG(INFO, "Device unbind failed, EM\n"); fail = true; } diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 7917c9613a..ba82efdfe2 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -193,8 +193,11 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, parms.hcapi_type = &hcapi_type; rc = tf_rm_get_hcapi_type(&parms); - if (rc) - return rc; + if (rc) { + *base = 0; + *shift = 0; + return 0; + } switch (hcapi_type) { case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index eec15b89bc..3b1e4e385d 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -509,21 +509,21 @@ tf_em_int_unbind(struct tf *tfp) rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", + TFP_DRV_LOG(INFO, + "Em_db is not initialized, rc:%s\n", strerror(-rc)); - return rc; + return 0; } em_db = (struct em_rm_db *)em_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { + if (em_db->em_db[i] == NULL) + continue; fparms.dir = i; fparms.rm_db = em_db->em_db[i]; - if (em_db->em_db[i] != NULL) { - rc = tf_rm_free_db(tfp, &fparms); - if (rc) - return rc; - } + rc = tf_rm_free_db(tfp, &fparms); + if (rc) + return rc; em_db->em_db[i] = NULL; } @@ -546,10 +546,9 @@ tf_em_get_resc_info(struct tf *tfp, rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; + TFP_DRV_LOG(INFO, + "No resource allocated for em from session\n"); + return 0; } em_db = (struct em_rm_db *)em_db_ptr; diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index 4063f3ba17..ebb975562d 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -119,14 +119,16 @@ tf_ident_unbind(struct tf *tfp) rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get ident_db from session, rc:%s\n", + TFP_DRV_LOG(INFO, + "Ident_db is not initialized, rc:%s\n", strerror(-rc)); - return rc; + return 0; } ident_db = (struct ident_rm_db *)ident_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { + if (ident_db->ident_db[i] == NULL) + continue; fparms.rm_db = ident_db->ident_db[i]; fparms.dir = i; rc = tf_rm_free_db(tfp, &fparms); @@ -372,10 +374,9 @@ tf_ident_get_resc_info(struct tf *tfp, rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get ident_db from session, rc:%s\n", - strerror(-rc)); - return rc; + TFP_DRV_LOG(INFO, + "No resource allocated for ident from session\n"); + return 0; } ident_db = (struct ident_rm_db *)ident_db_ptr; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 2ee8a1e8a9..18eea8338a 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -125,9 +125,16 @@ tf_msg_session_open(struct bnxt *bp, struct hwrm_tf_session_open_input req = { 0 }; struct hwrm_tf_session_open_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; + int name_len; + char *name; /* Populate the request */ - tfp_memcpy(&req.session_name, ctrl_chan_name, TF_SESSION_NAME_MAX); + name_len = strnlen(ctrl_chan_name, TF_SESSION_NAME_MAX); + name = &ctrl_chan_name[name_len - strlen("tf_shared")]; + if (!strncmp(name, "tf_shared", strlen("tf_shared"))) + tfp_memcpy(&req.session_name, name, strlen("tf_share")); + else + tfp_memcpy(&req.session_name, ctrl_chan_name, TF_SESSION_NAME_MAX); parms.tf_type = HWRM_TF_SESSION_OPEN; parms.req_data = (uint32_t *)&req; @@ -201,7 +208,7 @@ tf_msg_session_client_register(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -252,7 +259,7 @@ tf_msg_session_client_unregister(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; @@ -296,7 +303,7 @@ tf_msg_session_close(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; } @@ -348,7 +355,7 @@ tf_msg_session_qcfg(struct tf *tfp) parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; } @@ -411,7 +418,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) goto cleanup; @@ -521,7 +528,7 @@ tf_msg_session_resc_alloc(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) goto cleanup; @@ -628,7 +635,7 @@ tf_msg_session_resc_info(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) goto cleanup; @@ -735,7 +742,7 @@ tf_msg_session_resc_flush(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); tf_msg_free_dma_buf(&resv_buf); @@ -829,7 +836,7 @@ tf_msg_insert_em_internal_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -924,7 +931,7 @@ tf_msg_hash_insert_em_internal_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -994,7 +1001,7 @@ tf_msg_delete_em_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -1063,7 +1070,7 @@ tf_msg_move_em_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -1119,7 +1126,7 @@ int tf_msg_ext_em_ctxt_mem_alloc(struct tf *tfp, parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) { TFP_DRV_LOG(ERR, "Failed ext_em_alloc error rc:%s\n", strerror(-rc)); @@ -1179,7 +1186,7 @@ int tf_msg_ext_em_ctxt_mem_free(struct tf *tfp, parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; } @@ -1230,7 +1237,7 @@ tf_msg_em_mem_rgtr(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -1282,7 +1289,7 @@ tf_msg_em_mem_unrgtr(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; } @@ -1334,7 +1341,7 @@ tf_msg_em_qcaps(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -1409,7 +1416,7 @@ tf_msg_em_cfg(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; } @@ -1483,7 +1490,7 @@ tf_msg_ext_em_cfg(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; } @@ -1533,7 +1540,7 @@ tf_msg_em_op(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; } @@ -1611,7 +1618,7 @@ tf_msg_tcam_entry_set(struct tf *tfp, mparms.resp_size = sizeof(resp); mparms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &mparms); cleanup: @@ -1664,7 +1671,7 @@ tf_msg_tcam_entry_get(struct tf *tfp, mparms.resp_size = sizeof(resp); mparms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &mparms); if (rc != 0) @@ -1735,7 +1742,7 @@ tf_msg_tcam_entry_free(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); return rc; } @@ -1816,7 +1823,7 @@ tf_msg_set_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -1882,7 +1889,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -1968,7 +1975,7 @@ tf_msg_get_global_cfg(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc != 0) return rc; @@ -2069,7 +2076,7 @@ tf_msg_set_global_cfg(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc != 0) return rc; @@ -2142,7 +2149,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc) return rc; @@ -2205,7 +2212,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc != 0) return rc; @@ -2262,7 +2269,7 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, parms.resp_size = sizeof(resp); parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfs), &parms); + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); if (rc != 0) return rc; diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index 391d8786ab..93876d8e5d 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -59,6 +59,8 @@ tf_session_create(struct tf *tfp, union tf_session_id *session_id; struct tf_dev_info dev; bool shared_session_creator; + int name_len; + char *name; TF_CHECK_PARMS2(tfp, parms); @@ -140,7 +142,6 @@ tf_session_create(struct tf *tfp, session_id->id = session->session_id.id; session->shadow_copy = parms->open_cfg->shadow_copy; - session->bp = parms->open_cfg->bp; /* Init session client list */ ll_init(&session->client_ll); @@ -179,7 +180,12 @@ tf_session_create(struct tf *tfp, /* Init session em_ext_db */ session->em_ext_db_handle = NULL; - if (!strcmp(parms->open_cfg->ctrl_chan_name, "tf_share")) + + /* Populate the request */ + name_len = strnlen(parms->open_cfg->ctrl_chan_name, + TF_SESSION_NAME_MAX); + name = &parms->open_cfg->ctrl_chan_name[name_len - strlen("tf_shared")]; + if (!strncmp(name, "tf_shared", strlen("tf_shared"))) session->shared_session = true; if (session->shared_session && shared_session_creator) { @@ -404,8 +410,9 @@ tf_session_open_session(struct tf *tfp, int rc; struct tf_session_client_create_parms scparms; - TF_CHECK_PARMS2(tfp, parms); + TF_CHECK_PARMS3(tfp, parms, parms->open_cfg->bp); + tfp->bp = parms->open_cfg->bp; /* Decide if we're creating a new session or session client */ if (tfp->session == NULL) { rc = tf_session_create(tfp, parms); diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index e2cebd20a1..034a2213a4 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -155,11 +155,6 @@ struct tf_session { */ void *em_db_handle; - /** - * the pointer to the parent bp struct - */ - void *bp; - /** * EM allocator for session */ @@ -567,8 +562,8 @@ tf_session_is_shared_session_creator(struct tf_session *tfs) * - the pointer to the parent bnxt struct */ static inline struct bnxt* -tf_session_get_bp(struct tf_session *tfs) +tf_session_get_bp(struct tf *tfp) { - return tfs->bp; + return tfp->bp; } #endif /* _TF_SESSION_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 17fb550917..ca1aef8ebf 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -109,14 +109,16 @@ tf_tbl_unbind(struct tf *tfp) rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", + TFP_DRV_LOG(INFO, + "Tbl_db is not initialized, rc:%s\n", strerror(-rc)); - return rc; + return 0; } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { + if (tbl_db->tbl_db[i] == NULL) + continue; fparms.dir = i; fparms.rm_db = tbl_db->tbl_db[i]; rc = tf_rm_free_db(tfp, &fparms); @@ -621,23 +623,36 @@ tf_tbl_get_resc_info(struct tf *tfp, struct tf_tbl_resource_info *tbl) { int rc; - int d; + int d, i; struct tf_resource_info *dinfo; struct tf_rm_get_alloc_info_parms ainfo; void *tbl_db_ptr = NULL; struct tbl_rm_db *tbl_db; + uint16_t base = 0, shift = 0; + struct tf_dev_info *dev; + struct tf_session *tfs; TF_CHECK_PARMS2(tfp, tbl); + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; + TFP_DRV_LOG(INFO, + "No resource allocated for table from session\n"); + return 0; } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { ainfo.rm_db = tbl_db->tbl_db[d]; @@ -648,7 +663,33 @@ tf_tbl_get_resc_info(struct tf *tfp, rc = tf_rm_get_all_info(&ainfo, TF_TBL_TYPE_MAX); if (rc) return rc; + + if (dev->ops->tf_dev_get_tbl_info) { + /* Adjust all */ + for (i = 0; i < TF_TBL_TYPE_MAX; i++) { + /* Only get table info if required for the device */ + rc = dev->ops->tf_dev_get_tbl_info(tfp, + tbl_db->tbl_db[d], + i, + &base, + &shift); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%d\n", + tf_dir_2_str(d), + i); + return rc; + } + if (dinfo[i].stride) + TF_TBL_RM_TO_PTR(&dinfo[i].start, + dinfo[i].start, + base, + shift); + } + } } + + return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 70dc539f15..0f05af87f1 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -220,14 +220,16 @@ tf_tcam_unbind(struct tf *tfp) rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", + TFP_DRV_LOG(INFO, + "Tcam_db is not initialized, rc:%s\n", strerror(-rc)); - return rc; + return 0; } tcam_db = (struct tcam_rm_db *)tcam_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { + if (tcam_db->tcam_db[i] == NULL) + continue; memset(&fparms, 0, sizeof(fparms)); fparms.dir = i; fparms.rm_db = tcam_db->tcam_db[i]; @@ -816,10 +818,9 @@ tf_tcam_get_resc_info(struct tf *tfp, rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; + TFP_DRV_LOG(INFO, + "No resource allocated for tcam from session\n"); + return 0; } tcam_db = (struct tcam_rm_db *)tcam_db_ptr; diff --git a/drivers/net/bnxt/tf_core/tfp.c b/drivers/net/bnxt/tf_core/tfp.c index 4d9b37f749..a4b0934610 100644 --- a/drivers/net/bnxt/tf_core/tfp.c +++ b/drivers/net/bnxt/tf_core/tfp.c @@ -134,7 +134,7 @@ tfp_get_fid(struct tf *tfp, uint16_t *fw_fid) if (tfp == NULL || fw_fid == NULL) return -EINVAL; - bp = container_of(tfp, struct bnxt, tfp); + bp = (struct bnxt *)tfp->bp; if (bp == NULL) return -EINVAL; @@ -151,7 +151,7 @@ tfp_get_pf(struct tf *tfp, uint16_t *pf) if (tfp == NULL || pf == NULL) return -EINVAL; - bp = container_of(tfp, struct bnxt, tfp); + bp = (struct bnxt *)tfp->bp; if (BNXT_VF(bp) && bp->parent) { *pf = bp->parent->fid - 1; return 0; From patchwork Sun May 30 08:58:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93566 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3F5CCA0524; Sun, 30 May 2021 11:03:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09C084114C; Sun, 30 May 2021 11:00:58 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 9BB7B41173 for ; Sun, 30 May 2021 11:00:55 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 071DB7DC2; Sun, 30 May 2021 02:00:53 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 071DB7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365255; bh=uA2O/P0U+PSYH8+GGRx1EjFi2LVS9aT5spICAk4FVfs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u0Awy55ZD7THGQ7xh3fGSyzWe4Jw4cvWEQAYvQfuDiNrBo7z5MWdqIQFj9oeKniMr 4/igqFBLKSQoWEid9V+i7xWkbYZfmnTm3lJn1teWK8S7bAgx2i7nRGySX2lAoyMlmt ahblXZ847T2V2Gor9qraBy1rdkTZHoBGj3qC68yM= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:48 +0530 Message-Id: <20210530085929.29695-18-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 17/58] net/bnxt: modify resource reservation strategy X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding Allow an application to only reserve resources for one direction. Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Ajit Kumar Khaparde Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_core/tf_core.c | 4 -- drivers/net/bnxt/tf_core/tf_em_common.c | 61 +++++++++++------------ drivers/net/bnxt/tf_core/tf_em_internal.c | 13 +++-- drivers/net/bnxt/tf_core/tf_identifier.c | 15 +++--- drivers/net/bnxt/tf_core/tf_tbl.c | 12 +++-- drivers/net/bnxt/tf_core/tf_tcam.c | 14 ++++-- 6 files changed, 65 insertions(+), 54 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 945e54bfdd..de2a93646f 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1636,7 +1636,6 @@ int tf_get_session_info(struct tf *tfp, TFP_DRV_LOG(ERR, "Ident get resc info failed, rc:%s\n", strerror(-rc)); - return rc; } if (dev->ops->tf_dev_get_tbl_resc_info == NULL) { @@ -1652,7 +1651,6 @@ int tf_get_session_info(struct tf *tfp, TFP_DRV_LOG(ERR, "Tbl get resc info failed, rc:%s\n", strerror(-rc)); - return rc; } if (dev->ops->tf_dev_get_tcam_resc_info == NULL) { @@ -1668,7 +1666,6 @@ int tf_get_session_info(struct tf *tfp, TFP_DRV_LOG(ERR, "TCAM get resc info failed, rc:%s\n", strerror(-rc)); - return rc; } if (dev->ops->tf_dev_get_em_resc_info == NULL) { @@ -1684,7 +1681,6 @@ int tf_get_session_info(struct tf *tfp, TFP_DRV_LOG(ERR, "EM get resc info failed, rc:%s\n", strerror(-rc)); - return rc; } return 0; diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index ed8f6db58c..812ccb0d29 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -301,6 +301,7 @@ tf_em_page_tbl_pgcnt(uint32_t num_pages, { return roundup(num_pages, MAX_PAGE_PTRS(page_size)) / MAX_PAGE_PTRS(page_size); + return 0; } /** @@ -722,10 +723,6 @@ tf_insert_eem_entry(struct tf_dev_info *dev, if (!mask) return -EINVAL; -#ifdef TF_EEM_DEBUG - dump_raw((uint8_t *)parms->key, TF_P4_HW_EM_KEY_MAX_SIZE + 4, "In Key"); -#endif - if (dev->ops->tf_dev_cfa_key_hash == NULL) return -EINVAL; @@ -737,10 +734,6 @@ tf_insert_eem_entry(struct tf_dev_info *dev, key0_index = key0_hash & mask; key1_index = key1_hash & mask; -#ifdef TF_EEM_DEBUG - TFP_DRV_LOG(DEBUG, "Key0 hash:0x%08x\n", key0_hash); - TFP_DRV_LOG(DEBUG, "Key1 hash:0x%08x\n", key1_hash); -#endif /* * Use the "result" arg to populate all of the key entry then * store the byte swapped "raw" entry in a local copy ready @@ -1010,35 +1003,41 @@ tf_em_ext_common_unbind(struct tf *tfp) } ext_db = (struct em_ext_db *)ext_ptr; - entry = ext_db->tbl_scope_ll.head; - while (entry != NULL) { - tbl_scope_cb = (struct tf_tbl_scope_cb *)entry; - entry = entry->next; - tparms.tbl_scope_id = tbl_scope_cb->tbl_scope_id; - - if (dev->ops->tf_dev_free_tbl_scope) { - dev->ops->tf_dev_free_tbl_scope(tfp, &tparms); - } else { - /* should not reach here */ - ll_delete(&ext_db->tbl_scope_ll, &tbl_scope_cb->ll_entry); - tfp_free(tbl_scope_cb); + if (ext_db != NULL) { + entry = ext_db->tbl_scope_ll.head; + while (entry != NULL) { + tbl_scope_cb = (struct tf_tbl_scope_cb *)entry; + entry = entry->next; + tparms.tbl_scope_id = + tbl_scope_cb->tbl_scope_id; + + if (dev->ops->tf_dev_free_tbl_scope) { + dev->ops->tf_dev_free_tbl_scope(tfp, + &tparms); + } else { + /* should not reach here */ + ll_delete(&ext_db->tbl_scope_ll, + &tbl_scope_cb->ll_entry); + tfp_free(tbl_scope_cb); + } } - } - for (i = 0; i < TF_DIR_MAX; i++) { - if (ext_db->eem_db[i] == NULL) - continue; + for (i = 0; i < TF_DIR_MAX; i++) { + if (ext_db->eem_db[i] == NULL) + continue; - fparms.dir = i; - fparms.rm_db = ext_db->eem_db[i]; - rc = tf_rm_free_db(tfp, &fparms); - if (rc) - return rc; + fparms.dir = i; + fparms.rm_db = ext_db->eem_db[i]; + rc = tf_rm_free_db(tfp, &fparms); + if (rc) + return rc; - ext_db->eem_db[i] = NULL; + ext_db->eem_db[i] = NULL; + } + + tfp_free(ext_db); } - tfp_free(ext_db); tf_session_set_em_ext_db(tfp, NULL); return 0; diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 3b1e4e385d..93de513989 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -349,6 +349,7 @@ tf_em_int_bind(struct tf *tfp, struct tf_em_cfg_parms *parms) { int rc; + int db_rc[TF_DIR_MAX] = { 0 }; int i; struct tf_rm_create_db_parms db_cfg = { 0 }; struct tf_rm_get_alloc_info_parms iparms; @@ -408,18 +409,22 @@ tf_em_int_bind(struct tf *tfp, db_cfg.rm_db = (void *)&em_db->em_db[i]; if (tf_session_is_shared_session(tfs) && (!tf_session_is_shared_session_creator(tfs))) - rc = tf_rm_create_db_no_reservation(tfp, &db_cfg); + db_rc[i] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else - rc = tf_rm_create_db(tfp, &db_cfg); - if (rc) { + db_rc[i] = tf_rm_create_db(tfp, &db_cfg); + if (db_rc[i]) { TFP_DRV_LOG(ERR, "%s: EM Int DB creation failed\n", tf_dir_2_str(i)); - return rc; } } + /* No db created */ + if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) + return db_rc[TF_DIR_RX]; + + if (!tf_session_is_shared_session(tfs)) { for (i = 0; i < TF_DIR_MAX; i++) { iparms.rm_db = em_db->em_db[i]; diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index ebb975562d..3cc87de4ef 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -30,6 +30,7 @@ tf_ident_bind(struct tf *tfp, struct tf_ident_cfg_parms *parms) { int rc; + int db_rc[TF_DIR_MAX] = { 0 }; int i; struct tf_rm_create_db_parms db_cfg = { 0 }; struct tf_shadow_ident_cfg_parms shadow_cfg = { 0 }; @@ -70,15 +71,13 @@ tf_ident_bind(struct tf *tfp, db_cfg.alloc_cnt = parms->resources->ident_cnt[i].cnt; if (tf_session_is_shared_session(tfs) && (!tf_session_is_shared_session_creator(tfs))) - rc = tf_rm_create_db_no_reservation(tfp, &db_cfg); + db_rc[i] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else - rc = tf_rm_create_db(tfp, &db_cfg); - if (rc) { - TFP_DRV_LOG(ERR, + db_rc[i] = tf_rm_create_db(tfp, &db_cfg); + if (db_rc[i]) { + TFP_DRV_LOG(INFO, "%s: Identifier DB creation failed\n", tf_dir_2_str(i)); - - return rc; } if (parms->shadow_copy) { @@ -99,6 +98,10 @@ tf_ident_bind(struct tf *tfp, } } + /* No db created */ + if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) + return db_rc[TF_DIR_RX]; + TFP_DRV_LOG(INFO, "Identifier - initialized\n"); diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index ca1aef8ebf..192115183b 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -41,6 +41,7 @@ tf_tbl_bind(struct tf *tfp, struct tf_tbl_cfg_parms *parms) { int rc, d, i; + int db_rc[TF_DIR_MAX] = { 0 }; struct tf_rm_create_db_parms db_cfg = { 0 }; struct tbl_rm_db *tbl_db; struct tfp_calloc_parms cparms; @@ -79,18 +80,21 @@ tf_tbl_bind(struct tf *tfp, db_cfg.rm_db = (void *)&tbl_db->tbl_db[d]; if (tf_session_is_shared_session(tfs) && (!tf_session_is_shared_session_creator(tfs))) - rc = tf_rm_create_db_no_reservation(tfp, &db_cfg); + db_rc[d] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else - rc = tf_rm_create_db(tfp, &db_cfg); - if (rc) { + db_rc[d] = tf_rm_create_db(tfp, &db_cfg); + if (db_rc[d]) { TFP_DRV_LOG(ERR, "%s: Table DB creation failed\n", tf_dir_2_str(d)); - return rc; } } + /* No db created */ + if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) + return db_rc[TF_DIR_RX]; + TFP_DRV_LOG(INFO, "Table Type - initialized\n"); diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 0f05af87f1..ce959e3923 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -33,6 +33,7 @@ tf_tcam_bind(struct tf *tfp, struct tf_tcam_cfg_parms *parms) { int rc; + int db_rc[TF_DIR_MAX] = { 0 }; int i, d; struct tf_rm_alloc_info info; struct tf_rm_free_db_parms fparms; @@ -109,17 +110,20 @@ tf_tcam_bind(struct tf *tfp, db_cfg.rm_db = (void *)&tcam_db->tcam_db[d]; if (tf_session_is_shared_session(tfs) && (!tf_session_is_shared_session_creator(tfs))) - rc = tf_rm_create_db_no_reservation(tfp, &db_cfg); + db_rc[d] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else - rc = tf_rm_create_db(tfp, &db_cfg); - if (rc) { - TFP_DRV_LOG(ERR, + db_rc[d] = tf_rm_create_db(tfp, &db_cfg); + if (db_rc[d]) { + TFP_DRV_LOG(INFO, "%s: TCAM DB creation failed\n", tf_dir_2_str(d)); - return rc; } } + /* No db created */ + if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) + return db_rc[TF_DIR_RX]; + /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { memset(&info, 0, sizeof(info)); From patchwork Sun May 30 08:58:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93567 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F643A0524; Sun, 30 May 2021 11:03:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 92D69410E3; Sun, 30 May 2021 11:01:00 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 89E764111D for ; Sun, 30 May 2021 11:00:57 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id B6C877DC0; Sun, 30 May 2021 02:00:55 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com B6C877DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365257; bh=rouVU/HeVQkDPJNpV6jQVEKNvOM420FenXNDQRH1LpI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=inHXST2dl2YZdiYOIj4fPvlScDer02JxiR1o1RMygCgelC8R0SDi15lJ75fVdXun4 sVa6kw3tFMPrQa+hvgpIaUPvNt+X9sQT+/3dd8ppUNG1EMi1t57Lyp/V3TZG57iLe4 PXIj9ARs9/8wDU0Dk0cdFW61C9scGkZ4XWskl5Lo= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:49 +0530 Message-Id: <20210530085929.29695-19-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 18/58] net/bnxt: shared TCAM region support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith - switch to single slice management on Wh+ - Support of shared session WC_TCAM_HIGH and WC_TCAM_LOW regions - Enable/disable using TF_TCAM_SHARED flag in tf_core.h - Fix empty session module DBs in the case that none are allocated for a given module type Signed-off-by: Farah Smith Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_core/meson.build | 25 +- drivers/net/bnxt/tf_core/tf_core.h | 45 +- drivers/net/bnxt/tf_core/tf_device.c | 72 ++- drivers/net/bnxt/tf_core/tf_device.h | 4 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 17 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 13 +- drivers/net/bnxt/tf_core/tf_identifier.c | 2 +- drivers/net/bnxt/tf_core/tf_tbl.c | 5 +- drivers/net/bnxt/tf_core/tf_tcam.c | 5 +- drivers/net/bnxt/tf_core/tf_tcam_shared.c | 744 ++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_tcam_shared.h | 127 ++++ drivers/net/bnxt/tf_core/tf_util.c | 6 + 12 files changed, 1014 insertions(+), 51 deletions(-) create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_shared.c create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_shared.h diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index 3a91f04bc0..f28e77ec2e 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -10,26 +10,27 @@ sources += files( 'tf_core.c', 'bitalloc.c', 'tf_msg.c', - 'dpool.c', + 'll.c', + 'dpool.c', 'rand.c', 'stack.c', - 'tf_em_common.c', - 'tf_em_internal.c', 'tf_rm.c', 'tf_tbl.c', + 'tf_em_common.c', + 'tf_em_host.c', + 'tf_em_internal.c', + 'tf_em_hash_internal.c', 'tfp.c', - 'tf_session.c', + 'tf_util.c', 'tf_device.c', 'tf_device_p4.c', - 'tf_device_p58.c', + 'tf_global_cfg.c', 'tf_identifier.c', + 'tf_if_tbl.c', + 'tf_session.c', 'tf_shadow_tcam.c', 'tf_tcam.c', - 'tf_util.c', - 'tf_if_tbl.c', - 'll.c', - 'tf_global_cfg.c', - 'tf_em_host.c', - 'tf_em_hash_internal.c', + 'tf_tcam_shared.c', 'tf_shadow_identifier.c', - 'tf_hash.c') + 'tf_hash.c', + 'tf_device_p58.c') diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 3d14dc5391..39a498122b 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -21,7 +21,6 @@ /********** BEGIN Truflow Core DEFINITIONS **********/ - #define TF_KILOBYTE 1024 #define TF_MEGABYTE (1024 * 1024) @@ -77,7 +76,6 @@ enum tf_ext_mem_chan_type { #define TF_ACT_REC_OFFSET_2_PTR(offset) ((offset) >> 4) #define TF_ACT_REC_PTR_2_OFFSET(offset) ((offset) << 4) - /* * Helper Macros */ @@ -198,7 +196,6 @@ enum tf_module_type { TF_MODULE_TYPE_MAX }; - /** * Identifier resource types */ @@ -317,6 +314,41 @@ enum tf_tbl_type { TF_TBL_TYPE_MAX }; +/** Enable Shared TCAM Management + * + * This feature allows for management of high and low pools within + * the WC TCAM. These pools are only valid when this feature is enabled. + * + * For normal OVS-DPDK operation, this feature is not required and can + * be disabled by commenting out TF_TCAM_SHARED in this header file. + * + * Operation: + * + * When a shared session is created with WC TCAM entries allocated during + * tf_open_session(), the TF_TCAM_TBL_TYPE_WC_TCAM pool entries will be divided + * into 2 equal pools - TF_TCAM_TBL_TYPE_WC_TCAM_HIGH and + * TF_TCAM_TBL_TYPE_WC_TCAM_LOW. + * + * The user will allocate and free entries from either of these pools to obtain + * WC_TCAM entry offsets. For the WC_TCAM_HI/LO management, alloc/free is done + * using the tf_alloc_tcam_entry()/tf_free_tcam_entry() APIs for the shared + * session. + * + * The use case for this feature is so that applications can have a shared + * session and use the TF core to allocate/set/free entries within a given + * region of the WC_TCAM within the shared session. Application A only writes + * to the LOW region for example and Application B only writes to the HIGH + * region during normal operation. After Application A goes down, Application + * B may decide to overwrite the LOW region with the HIGH region's entries + * and switch to the low region. + * + * For other TCAM types in the shared session, no alloc/free operations are + * permitted. Only set should be used for other TCAM table types after getting + * the range as provided by the tf_get_resource_info() API. + * + */ +#define TF_TCAM_SHARED 1 + /** * TCAM table type */ @@ -335,6 +367,12 @@ enum tf_tcam_tbl_type { TF_TCAM_TBL_TYPE_CT_RULE_TCAM, /** Virtual Edge Bridge TCAM */ TF_TCAM_TBL_TYPE_VEB_TCAM, +#ifdef TF_TCAM_SHARED + /** Wildcard TCAM HI Priority */ + TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + /** Wildcard TCAM Low Priority */ + TF_TCAM_TBL_TYPE_WC_TCAM_LOW, +#endif /* TF_TCAM_SHARED */ TF_TCAM_TBL_TYPE_MAX }; @@ -1044,7 +1082,6 @@ int tf_search_identifier(struct tf *tfp, * Current thought is that memory is allocated within core. */ - /** * tf_alloc_tbl_scope_parms definition */ diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 97ae73fa5a..55cf55886a 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -9,6 +9,9 @@ #include "tfp.h" #include "tf_em.h" #include "tf_rm.h" +#ifdef TF_TCAM_SHARED +#include "tf_tcam_shared.h" +#endif /* TF_TCAM_SHARED */ struct tf; @@ -92,6 +95,12 @@ tf_dev_bind_p4(struct tf *tfp, struct tf_em_cfg_parms em_cfg; struct tf_if_tbl_cfg_parms if_tbl_cfg; struct tf_global_cfg_cfg_parms global_cfg; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; /* Initial function initialization */ dev_handle->ops = &tf_dev_ops_p4_init; @@ -142,7 +151,11 @@ tf_dev_bind_p4(struct tf *tfp, tcam_cfg.cfg = tf_tcam_p4; tcam_cfg.shadow_copy = shadow_copy; tcam_cfg.resources = resources; +#ifdef TF_TCAM_SHARED + rc = tf_tcam_shared_bind(tfp, &tcam_cfg); +#else /* !TF_TCAM_SHARED */ rc = tf_tcam_bind(tfp, &tcam_cfg); +#endif if (rc) { TFP_DRV_LOG(ERR, "TCAM initialization failure\n"); @@ -203,31 +216,32 @@ tf_dev_bind_p4(struct tf *tfp, return -ENOMEM; } - /* - * IF_TBL - */ - if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; - if_tbl_cfg.cfg = tf_if_tbl_p4; - if_tbl_cfg.shadow_copy = shadow_copy; - rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "IF Table initialization failure\n"); - goto fail; - } + if (!tf_session_is_shared_session(tfs)) { + /* + * IF_TBL + */ + if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; + if_tbl_cfg.cfg = tf_if_tbl_p4; + if_tbl_cfg.shadow_copy = shadow_copy; + rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "IF Table initialization failure\n"); + goto fail; + } - /* - * GLOBAL_CFG - */ - global_cfg.num_elements = TF_GLOBAL_CFG_TYPE_MAX; - global_cfg.cfg = tf_global_cfg_p4; - rc = tf_global_cfg_bind(tfp, &global_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "Global Cfg initialization failure\n"); - goto fail; + /* + * GLOBAL_CFG + */ + global_cfg.num_elements = TF_GLOBAL_CFG_TYPE_MAX; + global_cfg.cfg = tf_global_cfg_p4; + rc = tf_global_cfg_bind(tfp, &global_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "Global Cfg initialization failure\n"); + goto fail; + } } - /* Final function initialization */ dev_handle->ops = &tf_dev_ops_p4; @@ -265,7 +279,11 @@ tf_dev_unbind_p4(struct tf *tfp) * In case of residuals TCAMs are cleaned up first as to * invalidate the pipeline in a clean manner. */ +#ifdef TF_TCAM_SHARED + rc = tf_tcam_shared_unbind(tfp); +#else /* !TF_TCAM_SHARED */ rc = tf_tcam_unbind(tfp); +#endif /* TF_TCAM_SHARED */ if (rc) { TFP_DRV_LOG(INFO, "Device unbind failed, TCAM\n"); @@ -407,7 +425,11 @@ tf_dev_bind_p58(struct tf *tfp, tcam_cfg.cfg = tf_tcam_p58; tcam_cfg.shadow_copy = shadow_copy; tcam_cfg.resources = resources; +#ifdef TF_TCAM_SHARED + rc = tf_tcam_shared_bind(tfp, &tcam_cfg); +#else /* !TF_TCAM_SHARED */ rc = tf_tcam_bind(tfp, &tcam_cfg); +#endif if (rc) { TFP_DRV_LOG(ERR, "TCAM initialization failure\n"); @@ -517,7 +539,11 @@ tf_dev_unbind_p58(struct tf *tfp) * In case of residuals TCAMs are cleaned up first as to * invalidate the pipeline in a clean manner. */ +#ifdef TF_TCAM_SHARED + rc = tf_tcam_shared_unbind(tfp); +#else /* !TF_TCAM_SHARED */ rc = tf_tcam_unbind(tfp); +#endif /* TF_TCAM_SHARED */ if (rc) { TFP_DRV_LOG(INFO, "Device unbind failed, TCAM\n"); diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 31806bb289..ea4dcfb8e2 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -10,6 +10,9 @@ #include "tf_identifier.h" #include "tf_tbl.h" #include "tf_tcam.h" +#ifdef TF_TCAM_SHARED +#include "tf_tcam_shared.h" +#endif #include "tf_if_tbl.h" #include "tf_global_cfg.h" @@ -136,7 +139,6 @@ struct tf_dev_ops { uint16_t resource_id, const char **resource_str); - /** * Retrieves the WC TCAM slice information that the device * supports. diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 3f788638c1..fccbccc2d8 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -10,6 +10,9 @@ #include "tf_identifier.h" #include "tf_tbl.h" #include "tf_tcam.h" +#ifdef TF_TCAM_SHARED +#include "tf_tcam_shared.h" +#endif /* TF_TCAM_SHARED */ #include "tf_em.h" #include "tf_if_tbl.h" #include "tfp.h" @@ -140,7 +143,8 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused, uint16_t key_sz, uint16_t *num_slices_per_row) { -#define CFA_P4_WC_TCAM_SLICES_PER_ROW 2 +/* Single slice support */ +#define CFA_P4_WC_TCAM_SLICES_PER_ROW 1 #define CFA_P4_WC_TCAM_SLICE_SIZE 12 if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { @@ -266,11 +270,18 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, +#ifdef TF_TCAM_SHARED + .tf_dev_alloc_tcam = tf_tcam_shared_alloc, + .tf_dev_free_tcam = tf_tcam_shared_free, + .tf_dev_set_tcam = tf_tcam_shared_set, + .tf_dev_get_tcam = tf_tcam_shared_get, +#else /* !TF_TCAM_SHARED */ .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, - .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_set_tcam = tf_tcam_set, - .tf_dev_get_tcam = NULL, + .tf_dev_get_tcam = tf_tcam_get, +#endif + .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_delete_int_entry, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index ba82efdfe2..b25c5acf94 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -10,6 +10,9 @@ #include "tf_identifier.h" #include "tf_tbl.h" #include "tf_tcam.h" +#ifdef TF_TCAM_SHARED +#include "tf_tcam_shared.h" +#endif /* TF_TCAM_SHARED */ #include "tf_em.h" #include "tf_if_tbl.h" #include "tfp.h" @@ -151,7 +154,6 @@ static int tf_dev_p58_word_align(uint16_t size) return ((((size) + 63) >> 6) * 8); } - #define TF_DEV_P58_BANK_SZ_64B 2048 /** * Get SRAM table information. @@ -290,11 +292,18 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, +#ifdef TF_TCAM_SHARED + .tf_dev_alloc_tcam = tf_tcam_shared_alloc, + .tf_dev_free_tcam = tf_tcam_shared_free, + .tf_dev_set_tcam = tf_tcam_set, + .tf_dev_get_tcam = tf_tcam_get, +#else /* !TF_TCAM_SHARED */ .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, - .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_set_tcam = tf_tcam_set, .tf_dev_get_tcam = tf_tcam_get, +#endif + .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index 3cc87de4ef..3575c3e1a0 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -76,7 +76,7 @@ tf_ident_bind(struct tf *tfp, db_rc[i] = tf_rm_create_db(tfp, &db_cfg); if (db_rc[i]) { TFP_DRV_LOG(INFO, - "%s: Identifier DB creation failed\n", + "%s: No Identifier DB required\n", tf_dir_2_str(i)); } diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 192115183b..295204ac87 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -85,7 +85,7 @@ tf_tbl_bind(struct tf *tfp, db_rc[d] = tf_rm_create_db(tfp, &db_cfg); if (db_rc[d]) { TFP_DRV_LOG(ERR, - "%s: Table DB creation failed\n", + "%s: No Table DB creation required\n", tf_dir_2_str(d)); } @@ -656,7 +656,6 @@ tf_tbl_get_resc_info(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { ainfo.rm_db = tbl_db->tbl_db[d]; @@ -693,7 +692,5 @@ tf_tbl_get_resc_info(struct tf *tfp, } } - - return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index ce959e3923..5c018f7003 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -115,7 +115,7 @@ tf_tcam_bind(struct tf *tfp, db_rc[d] = tf_rm_create_db(tfp, &db_cfg); if (db_rc[d]) { TFP_DRV_LOG(INFO, - "%s: TCAM DB creation failed\n", + "%s: no TCAM DB required\n", tf_dir_2_str(d)); } } @@ -126,6 +126,9 @@ tf_tcam_bind(struct tf *tfp, /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { + if (!tcam_db->tcam_db[d]) + continue; + memset(&info, 0, sizeof(info)); ainfo.rm_db = tcam_db->tcam_db[d]; ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM; diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c new file mode 100644 index 0000000000..17d7fee7a8 --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c @@ -0,0 +1,744 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#include +#include + +#include "tf_tcam_shared.h" +#include "tf_tcam.h" +#include "tf_common.h" +#include "tf_util.h" +#include "tf_rm.h" +#include "tf_device.h" +#include "tfp.h" +#include "tf_session.h" +#include "tf_msg.h" +#include "bitalloc.h" +#include "tf_core.h" +#include "tf_rm.h" + +struct tf; + +/** Shared WC TCAM pool identifiers + */ +enum tf_tcam_shared_wc_pool_id { + TF_TCAM_SHARED_WC_POOL_HI = 0, + TF_TCAM_SHARED_WC_POOL_LO = 1, + TF_TCAM_SHARED_WC_POOL_MAX = 2 +}; + +/** Get string representation of a WC TCAM shared pool id + */ +static const char * +tf_pool_2_str(enum tf_tcam_shared_wc_pool_id id) +{ + switch (id) { + case TF_TCAM_SHARED_WC_POOL_HI: + return "TCAM_SHARED_WC_POOL_HI"; + case TF_TCAM_SHARED_WC_POOL_LO: + return "TCAM_SHARED_WC_POOL_LO"; + default: + return "Invalid TCAM_SHARED_WC_POOL"; + } +} + +/** The WC TCAM shared pool datastructure + */ +struct tf_tcam_shared_wc_pool { + /** Start and stride data */ + struct tf_resource_info info; + /** bitalloc pool */ + struct bitalloc *pool; +}; + +/** The WC TCAM shared pool declarations + * TODO: add tcam_shared_wc_db + */ +struct tf_tcam_shared_wc_pool tcam_shared_wc[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX]; + +/** Create a WC TCAM shared pool + */ +static int +tf_tcam_shared_create_wc_pool(int dir, + enum tf_tcam_shared_wc_pool_id id, + int start, + int stride) +{ + int rc = 0; + bool free = true; + struct tfp_calloc_parms cparms; + uint32_t pool_size; + + /* Create pool */ + pool_size = (BITALLOC_SIZEOF(stride) / sizeof(struct bitalloc)); + cparms.nitems = pool_size; + cparms.alignment = 0; + cparms.size = sizeof(struct bitalloc); + rc = tfp_calloc(&cparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: pool memory alloc failed %s:%s\n", + tf_dir_2_str(dir), tf_pool_2_str(id), + strerror(-rc)); + return rc; + } + tcam_shared_wc[dir][id].pool = (struct bitalloc *)cparms.mem_va; + + rc = ba_init(tcam_shared_wc[dir][id].pool, + stride, + free); + + if (rc) { + TFP_DRV_LOG(ERR, + "%s: pool bitalloc failed %s\n", + tf_dir_2_str(dir), tf_pool_2_str(id)); + return rc; + } + + tcam_shared_wc[dir][id].info.start = start; + tcam_shared_wc[dir][id].info.stride = stride; + return rc; +} +/** Free a WC TCAM shared pool + */ +static void +tf_tcam_shared_free_wc_pool(int dir, + enum tf_tcam_shared_wc_pool_id id) +{ + tcam_shared_wc[dir][id].info.start = 0; + tcam_shared_wc[dir][id].info.stride = 0; + + if (tcam_shared_wc[dir][id].pool) + tfp_free((void *)tcam_shared_wc[dir][id].pool); +} + +/** Get the number of WC TCAM slices allocated during 1 allocation/free + */ +static int +tf_tcam_shared_get_slices(struct tf *tfp, + struct tf_dev_info *dev, + uint16_t *num_slices) +{ + int rc; + + if (dev->ops->tf_dev_get_tcam_slice_info == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "Operation not supported, rc:%s\n", strerror(-rc)); + return rc; + } + rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, + TF_TCAM_TBL_TYPE_WC_TCAM, + 0, + num_slices); + return rc; +} + +static bool +tf_tcam_shared_db_valid(struct tf *tfp, + enum tf_dir dir) +{ + struct tcam_rm_db *tcam_db; + void *tcam_db_ptr = NULL; + int rc; + + TF_CHECK_PARMS1(tfp); + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); + if (rc) + return false; + + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; + + if (tcam_db->tcam_db[dir]) + return true; + + return false; +} + +static int +tf_tcam_shared_get_rm_info(struct tf *tfp, + enum tf_dir dir, + uint16_t *hcapi_type, + struct tf_rm_alloc_info *info) +{ + int rc; + struct tcam_rm_db *tcam_db; + void *tcam_db_ptr = NULL; + struct tf_rm_get_alloc_info_parms ainfo; + struct tf_rm_get_hcapi_parms hparms; + + TF_CHECK_PARMS3(tfp, hcapi_type, info); + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); + if (rc) { + TFP_DRV_LOG(INFO, + "Tcam_db is not initialized, rc:%s\n", + strerror(-rc)); + return 0; + } + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; + + /* Convert TF type to HCAPI RM type */ + memset(&hparms, 0, sizeof(hparms)); + hparms.rm_db = tcam_db->tcam_db[dir]; + hparms.subtype = TF_TCAM_TBL_TYPE_WC_TCAM; + hparms.hcapi_type = hcapi_type; + + rc = tf_rm_get_hcapi_type(&hparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Get RM hcapi type failed %s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + memset(info, 0, sizeof(struct tf_rm_alloc_info)); + ainfo.rm_db = tcam_db->tcam_db[dir]; + ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM; + ainfo.info = info; + + rc = tf_rm_get_info(&ainfo); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM rm info get failed %s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + return rc; +} + +/** + * tf_tcam_shared_bind + */ +int +tf_tcam_shared_bind(struct tf *tfp, + struct tf_tcam_cfg_parms *parms) +{ + int rc, dir; + struct tf_session *tfs; + struct tf_dev_info *dev; + struct tf_rm_alloc_info info; + uint16_t start, stride; + uint16_t num_slices; + uint16_t hcapi_type; + + TF_CHECK_PARMS2(tfp, parms); + + /* Perform normal bind + */ + rc = tf_tcam_bind(tfp, parms); + if (rc) + return rc; + + /* After the normal TCAM bind, if this is a shared session + * create all required databases for the WC_HI and WC_LO pools + */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Session access failure: %s\n", strerror(-rc)); + return rc; + } + if (tf_session_is_shared_session(tfs)) { + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + rc = tf_tcam_shared_get_slices(tfp, + dev, + &num_slices); + if (rc) + return rc; + + /* If there are WC TCAM entries, create 2 pools each with 1/2 + * the total number of entries + */ + for (dir = 0; dir < TF_DIR_MAX; dir++) { + if (!tf_tcam_shared_db_valid(tfp, dir)) + continue; + + rc = tf_tcam_shared_get_rm_info(tfp, + dir, + &hcapi_type, + &info); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM rm info get failed\n", + tf_dir_2_str(dir)); + goto done; + } + + start = info.entry.start; + stride = info.entry.stride / 2; + + tf_tcam_shared_create_wc_pool(dir, + TF_TCAM_SHARED_WC_POOL_HI, + start, + stride); + + start += stride; + tf_tcam_shared_create_wc_pool(dir, + TF_TCAM_SHARED_WC_POOL_LO, + start, + stride); + } + } +done: + return rc; +} +/** + * tf_tcam_shared_unbind + */ +int +tf_tcam_shared_unbind(struct tf *tfp) +{ + int rc, dir; + struct tf_session *tfs; + + TF_CHECK_PARMS1(tfp); + + /* Perform normal unbind, this will write all the + * allocated TCAM entries in the shared session. + */ + rc = tf_tcam_unbind(tfp); + if (rc) + return rc; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* If we are the shared session + */ + if (tf_session_is_shared_session(tfs)) { + /* If there are WC TCAM entries allocated, free them + */ + for (dir = 0; dir < TF_DIR_MAX; dir++) { + tf_tcam_shared_free_wc_pool(dir, + TF_TCAM_SHARED_WC_POOL_HI); + tf_tcam_shared_free_wc_pool(dir, + TF_TCAM_SHARED_WC_POOL_LO); + } + } + return 0; +} +/** + * tf_tcam_shared_alloc + */ +int +tf_tcam_shared_alloc(struct tf *tfp, + struct tf_tcam_alloc_parms *parms) +{ + int rc, i; + struct tf_session *tfs; + struct tf_dev_info *dev; + int log_idx; + struct bitalloc *pool; + enum tf_tcam_shared_wc_pool_id id; + uint16_t num_slices; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* If we aren't the shared session or the type is + * not one of the special WC TCAM types, call the normal + * allocation. + */ + if (!tf_session_is_shared_session(tfs) || + (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && + parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { + /* Perform normal alloc + */ + rc = tf_tcam_alloc(tfp, parms); + return rc; + } + + if (!tf_tcam_shared_db_valid(tfp, parms->dir)) { + TFP_DRV_LOG(ERR, + "%s: tcam shared pool doesn't exist\n", + tf_dir_2_str(parms->dir)); + return -ENOMEM; + } + + if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) + id = TF_TCAM_SHARED_WC_POOL_HI; + else + id = TF_TCAM_SHARED_WC_POOL_LO; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); + if (rc) + return rc; + + pool = tcam_shared_wc[parms->dir][id].pool; + + for (i = 0; i < num_slices; i++) { + /* + * priority 0: allocate from top of the tcam i.e. high + * priority !0: allocate index from bottom i.e lowest + */ + if (parms->priority) + log_idx = ba_alloc_reverse(pool); + else + log_idx = ba_alloc(pool); + if (log_idx == BA_FAIL) { + TFP_DRV_LOG(ERR, + "%s: Allocation failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(ENOMEM)); + return -ENOMEM; + } + /* return the index without the start of each row */ + if (i == 0) + parms->idx = log_idx; + } + return 0; +} + +int +tf_tcam_shared_free(struct tf *tfp, + struct tf_tcam_free_parms *parms) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + int allocated = 0; + int i; + uint16_t start; + int phy_idx; + struct bitalloc *pool; + enum tf_tcam_shared_wc_pool_id id; + struct tf_tcam_free_parms nparms; + uint16_t num_slices; + uint16_t hcapi_type; + struct tf_rm_alloc_info info; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* If we aren't the shared session or the type is + * not one of the special WC TCAM types, call the normal + * allocation. + */ + if (!tf_session_is_shared_session(tfs) || + (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && + parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { + /* Perform normal free + */ + rc = tf_tcam_free(tfp, parms); + return rc; + } + + if (!tf_tcam_shared_db_valid(tfp, parms->dir)) { + TFP_DRV_LOG(ERR, + "%s: tcam shared pool doesn't exist\n", + tf_dir_2_str(parms->dir)); + return -ENOMEM; + } + + if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) + id = TF_TCAM_SHARED_WC_POOL_HI; + else + id = TF_TCAM_SHARED_WC_POOL_LO; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); + if (rc) + return rc; + + rc = tf_tcam_shared_get_rm_info(tfp, + parms->dir, + &hcapi_type, + &info); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM rm info get failed\n", + tf_dir_2_str(parms->dir)); + return rc; + } + + pool = tcam_shared_wc[parms->dir][id].pool; + start = tcam_shared_wc[parms->dir][id].info.start; + + if (parms->idx % num_slices) { + TFP_DRV_LOG(ERR, + "%s: TCAM reserved resource is not multiple of %d\n", + tf_dir_2_str(parms->dir), num_slices); + return -EINVAL; + } + + phy_idx = parms->idx + start; + allocated = ba_inuse(pool, parms->idx); + + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s: Entry already free, type:%d, idx:%d\n", + tf_dir_2_str(parms->dir), parms->type, parms->idx); + return -EINVAL; + } + + for (i = 0; i < num_slices; i++) { + rc = ba_free(pool, parms->idx + i); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Free failed, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tcam_tbl_2_str(parms->type), + parms->idx); + return rc; + } + } + + /* Override HI/LO type with parent WC TCAM type */ + nparms = *parms; + nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; + nparms.hcapi_type = hcapi_type; + nparms.idx = phy_idx; + + rc = tf_msg_tcam_entry_free(tfp, dev, &nparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: %s: log%d free failed, rc:%s\n", + tf_dir_2_str(nparms.dir), + tf_tcam_tbl_2_str(nparms.type), + phy_idx, + strerror(-rc)); + return rc; + } + return 0; +} + +int +tf_tcam_shared_set(struct tf *tfp __rte_unused, + struct tf_tcam_set_parms *parms __rte_unused) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + int allocated = 0; + int phy_idx, log_idx; + uint16_t num_slices; + struct tf_tcam_set_parms nparms; + struct bitalloc *pool; + uint16_t start; + enum tf_tcam_shared_wc_pool_id id; + uint16_t hcapi_type; + struct tf_rm_alloc_info info; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* If we aren't the shared session or one of our + * special types + */ + if (!tf_session_is_shared_session(tfs) || + (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && + parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { + /* Perform normal set and exit + */ + rc = tf_tcam_set(tfp, parms); + return rc; + } + + if (!tf_tcam_shared_db_valid(tfp, parms->dir)) { + TFP_DRV_LOG(ERR, + "%s: tcam shared pool doesn't exist\n", + tf_dir_2_str(parms->dir)); + return -ENOMEM; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) + id = TF_TCAM_SHARED_WC_POOL_HI; + else + id = TF_TCAM_SHARED_WC_POOL_LO; + + pool = tcam_shared_wc[parms->dir][id].pool; + start = tcam_shared_wc[parms->dir][id].info.start; + + log_idx = parms->idx; + phy_idx = parms->idx + start; + allocated = ba_inuse(pool, parms->idx); + + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s: Entry is not allocated, type:%d, logid:%d\n", + tf_dir_2_str(parms->dir), parms->type, log_idx); + return -EINVAL; + } + rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); + if (rc) + return rc; + + if (parms->idx % num_slices) { + TFP_DRV_LOG(ERR, + "%s: TCAM reserved resource is not multiple of %d\n", + tf_dir_2_str(parms->dir), num_slices); + return -EINVAL; + } + rc = tf_tcam_shared_get_rm_info(tfp, + parms->dir, + &hcapi_type, + &info); + if (rc) + return rc; + + /* Override HI/LO type with parent WC TCAM type */ + nparms.hcapi_type = hcapi_type; + nparms.dir = parms->dir; + nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; + nparms.idx = phy_idx; + nparms.key = parms->key; + nparms.mask = parms->mask; + nparms.key_size = parms->key_size; + nparms.result = parms->result; + nparms.result_size = parms->result_size; + + rc = tf_msg_tcam_entry_set(tfp, dev, &nparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: %s: phy entry %d set failed, rc:%s", + tf_dir_2_str(parms->dir), + tf_tcam_tbl_2_str(nparms.type), + phy_idx, + strerror(-rc)); + return rc; + } + return 0; +} + +int +tf_tcam_shared_get(struct tf *tfp __rte_unused, + struct tf_tcam_get_parms *parms) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + int allocated = 0; + int phy_idx, log_idx; + uint16_t num_slices; + struct tf_tcam_get_parms nparms; + struct bitalloc *pool; + uint16_t start; + enum tf_tcam_shared_wc_pool_id id; + uint16_t hcapi_type; + struct tf_rm_alloc_info info; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* If we aren't the shared session or one of our + * special types + */ + if (!tf_session_is_shared_session(tfs) || + (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && + parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { + /* Perform normal get and exit + */ + rc = tf_tcam_get(tfp, parms); + return rc; + } + + if (!tf_tcam_shared_db_valid(tfp, parms->dir)) { + TFP_DRV_LOG(ERR, + "%s: tcam shared pool doesn't exist\n", + tf_dir_2_str(parms->dir)); + return -ENOMEM; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) + id = TF_TCAM_SHARED_WC_POOL_HI; + else + id = TF_TCAM_SHARED_WC_POOL_LO; + + pool = tcam_shared_wc[parms->dir][id].pool; + start = tcam_shared_wc[parms->dir][id].info.start; + + rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); + if (rc) + return rc; + + if (parms->idx % num_slices) { + TFP_DRV_LOG(ERR, + "%s: TCAM reserved resource is not multiple of %d\n", + tf_dir_2_str(parms->dir), num_slices); + return -EINVAL; + } + log_idx = parms->idx; + phy_idx = parms->idx + start; + allocated = ba_inuse(pool, parms->idx); + + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s: Entry is not allocated, type:%d, logid:%d\n", + tf_dir_2_str(parms->dir), parms->type, log_idx); + return -EINVAL; + } + + rc = tf_tcam_shared_get_rm_info(tfp, + parms->dir, + &hcapi_type, + &info); + if (rc) + return rc; + + /* Override HI/LO type with parent WC TCAM type */ + nparms = *parms; + nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; + nparms.hcapi_type = hcapi_type; + nparms.idx = phy_idx; + + rc = tf_msg_tcam_entry_get(tfp, dev, &nparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: %s: Entry %d set failed, rc:%s", + tf_dir_2_str(nparms.dir), + tf_tcam_tbl_2_str(nparms.type), + nparms.idx, + strerror(-rc)); + return rc; + } + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h new file mode 100644 index 0000000000..fad6e23b4c --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#ifndef _TF_TCAM_SHARED_H_ +#define _TF_TCAM_SHARED_H_ + +#include "tf_core.h" +#include "tf_tcam.h" + +/** + * @page tcam_shared TCAM SHARED + * + * @ref tf_tcam_shared_bind + * + * @ref tf_tcam_shared_unbind + * + * @ref tf_tcam_shared_alloc + * + * @ref tf_tcam_shared_free + * + * @ref tf_tcam_shared_set + * + * @ref tf_tcam_shared_get + * + */ + +/** + * Initializes the TCAM shared module with the requested DBs. Must be + * invoked as the first thing before any of the access functions. + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_bind(struct tf *tfp, + struct tf_tcam_cfg_parms *parms); + +/** + * Cleans up the private DBs and releases all the data. + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_unbind(struct tf *tfp); + +/** + * Allocates the requested tcam type from the internal RM DB. + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_alloc(struct tf *tfp, + struct tf_tcam_alloc_parms *parms); + +/** + * Free's the requested table type and returns it to the DB. + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_free(struct tf *tfp, + struct tf_tcam_free_parms *parms); + +/** + * Configures the requested element by sending a firmware request which + * then installs it into the device internal structures. + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_set(struct tf *tfp, + struct tf_tcam_set_parms *parms); + +/** + * Retrieves the requested element by sending a firmware request to get + * the element. + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_get(struct tf *tfp, + struct tf_tcam_get_parms *parms); + +#endif /* _TF_TCAM_SHARED_H */ diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index 25f5c152d2..e712816209 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -59,6 +59,12 @@ tf_tcam_tbl_2_str(enum tf_tcam_tbl_type tcam_type) return "sp_tcam"; case TF_TCAM_TBL_TYPE_CT_RULE_TCAM: return "ct_rule_tcam"; +#ifdef TF_TCAM_SHARED + case TF_TCAM_TBL_TYPE_WC_TCAM_HIGH: + return "wc_tcam_hi"; + case TF_TCAM_TBL_TYPE_WC_TCAM_LOW: + return "wc_tcam_lo"; +#endif default: return "Invalid tcam table type"; } From patchwork Sun May 30 08:58:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93568 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 21C83A0524; Sun, 30 May 2021 11:03:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F3CD941188; Sun, 30 May 2021 11:01:01 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 77C294117F for ; Sun, 30 May 2021 11:00:59 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id A46F97DAF; Sun, 30 May 2021 02:00:57 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com A46F97DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365259; bh=GJbcgc9IdUXP6WZmnvGVv0fECjfJVpfVvhKVV5Hw09s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RG7L/Y6JrORWpurWkSa3UeuyqId5S9gw2TaW1XyMCFKBO3gjMrxUOK5YUH/DBfgDo ShXlrb+osg80x8sCZ2LbGcCk7WS5EwUHp62TjFQcimxokhyiVNW5Rq/kndEKJEsa9q HZ2P5TqiLLw7vE03BuVGMeGOBwo4hKsEznkXCo3Y= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:50 +0530 Message-Id: <20210530085929.29695-20-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 19/58] net/bnxt: cleanup session open/close messages X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith Add profile_id to set_prof_tcam. Signed-off-by: Farah Smith Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher Reviewed-by: Peter Spreadborough --- drivers/net/bnxt/tf_core/tf_device.c | 90 ++++++++++++----------- drivers/net/bnxt/tf_core/tf_em_internal.c | 13 +--- drivers/net/bnxt/tf_core/tf_identifier.c | 15 +--- drivers/net/bnxt/tf_core/tf_if_tbl.c | 18 +---- drivers/net/bnxt/tf_core/tf_session.c | 18 +++-- drivers/net/bnxt/tf_core/tf_tbl.c | 18 ++--- drivers/net/bnxt/tf_core/tf_tcam.c | 12 +-- 7 files changed, 77 insertions(+), 107 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 55cf55886a..498e668b16 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -216,20 +216,20 @@ tf_dev_bind_p4(struct tf *tfp, return -ENOMEM; } - if (!tf_session_is_shared_session(tfs)) { - /* - * IF_TBL - */ - if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; - if_tbl_cfg.cfg = tf_if_tbl_p4; - if_tbl_cfg.shadow_copy = shadow_copy; - rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "IF Table initialization failure\n"); - goto fail; - } + /* + * IF_TBL + */ + if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; + if_tbl_cfg.cfg = tf_if_tbl_p4; + if_tbl_cfg.shadow_copy = shadow_copy; + rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "IF Table initialization failure\n"); + goto fail; + } + if (!tf_session_is_shared_session(tfs)) { /* * GLOBAL_CFG */ @@ -271,6 +271,12 @@ tf_dev_unbind_p4(struct tf *tfp) { int rc = 0; bool fail = false; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; /* Unbind all the support modules. As this is only done on * close we only report errors as everything has to be cleaned @@ -318,18 +324,20 @@ tf_dev_unbind_p4(struct tf *tfp) fail = true; } - rc = tf_if_tbl_unbind(tfp); - if (rc) { - TFP_DRV_LOG(INFO, - "Device unbind failed, IF Table Type\n"); - fail = true; - } + if (!tf_session_is_shared_session(tfs)) { + rc = tf_if_tbl_unbind(tfp); + if (rc) { + TFP_DRV_LOG(INFO, + "Device unbind failed, IF Table Type\n"); + fail = true; + } - rc = tf_global_cfg_unbind(tfp); - if (rc) { - TFP_DRV_LOG(INFO, - "Device unbind failed, Global Cfg Type\n"); - fail = true; + rc = tf_global_cfg_unbind(tfp); + if (rc) { + TFP_DRV_LOG(INFO, + "Device unbind failed, Global Cfg Type\n"); + fail = true; + } } if (fail) @@ -472,17 +480,17 @@ tf_dev_bind_p58(struct tf *tfp, /* * IF_TBL */ - if (!tf_session_is_shared_session(tfs)) { - if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; - if_tbl_cfg.cfg = tf_if_tbl_p58; - if_tbl_cfg.shadow_copy = shadow_copy; - rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "IF Table initialization failure\n"); - goto fail; - } + if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; + if_tbl_cfg.cfg = tf_if_tbl_p58; + if_tbl_cfg.shadow_copy = shadow_copy; + rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); + if (rc) { + TFP_DRV_LOG(ERR, + "IF Table initialization failure\n"); + goto fail; + } + if (!tf_session_is_shared_session(tfs)) { /* * GLOBAL_CFG */ @@ -571,14 +579,14 @@ tf_dev_unbind_p58(struct tf *tfp) fail = true; } - if (!tf_session_is_shared_session(tfs)) { - rc = tf_if_tbl_unbind(tfp); - if (rc) { - TFP_DRV_LOG(ERR, - "Device unbind failed, IF Table Type\n"); - fail = true; - } + rc = tf_if_tbl_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, IF Table Type\n"); + fail = true; + } + if (!tf_session_is_shared_session(tfs)) { rc = tf_global_cfg_unbind(tfp); if (rc) { TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 93de513989..28ffbd5876 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -412,17 +412,13 @@ tf_em_int_bind(struct tf *tfp, db_rc[i] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else db_rc[i] = tf_rm_create_db(tfp, &db_cfg); - if (db_rc[i]) { - TFP_DRV_LOG(ERR, - "%s: EM Int DB creation failed\n", - tf_dir_2_str(i)); - - } } /* No db created */ - if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) + if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) { + TFP_DRV_LOG(ERR, "EM Int DB creation failed\n"); return db_rc[TF_DIR_RX]; + } if (!tf_session_is_shared_session(tfs)) { @@ -514,9 +510,6 @@ tf_em_int_unbind(struct tf *tfp) rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); if (rc) { - TFP_DRV_LOG(INFO, - "Em_db is not initialized, rc:%s\n", - strerror(-rc)); return 0; } em_db = (struct em_rm_db *)em_db_ptr; diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index 3575c3e1a0..9f27a41fcf 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -74,11 +74,6 @@ tf_ident_bind(struct tf *tfp, db_rc[i] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else db_rc[i] = tf_rm_create_db(tfp, &db_cfg); - if (db_rc[i]) { - TFP_DRV_LOG(INFO, - "%s: No Identifier DB required\n", - tf_dir_2_str(i)); - } if (parms->shadow_copy) { shadow_cfg.alloc_cnt = @@ -99,8 +94,10 @@ tf_ident_bind(struct tf *tfp, } /* No db created */ - if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) + if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) { + TFP_DRV_LOG(ERR, "No Identifier DB created\n"); return db_rc[TF_DIR_RX]; + } TFP_DRV_LOG(INFO, "Identifier - initialized\n"); @@ -121,12 +118,8 @@ tf_ident_unbind(struct tf *tfp) TF_CHECK_PARMS1(tfp); rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); - if (rc) { - TFP_DRV_LOG(INFO, - "Ident_db is not initialized, rc:%s\n", - strerror(-rc)); + if (rc) return 0; - } ident_db = (struct ident_rm_db *)ident_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.c b/drivers/net/bnxt/tf_core/tf_if_tbl.c index f58fa79b63..762dac0473 100644 --- a/drivers/net/bnxt/tf_core/tf_if_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_if_tbl.c @@ -16,24 +16,16 @@ struct tf; /** * IF Table DBs. + * TODO: Store this data in session db */ static void *if_tbl_db[TF_DIR_MAX]; -/** - * IF Table Shadow DBs - */ -/* static void *shadow_if_tbl_db[TF_DIR_MAX]; */ - /** * Init flag, set on bind and cleared on unbind + * TODO: Store this data in session db */ static uint8_t init; -/** - * Shadow init flag, set on bind and cleared on unbind - */ -/* static uint8_t shadow_init; */ - /** * Convert if_tbl_type to hwrm type. * @@ -70,12 +62,6 @@ tf_if_tbl_bind(struct tf *tfp __rte_unused, { TF_CHECK_PARMS2(tfp, parms); - if (init) { - TFP_DRV_LOG(ERR, - "IF TBL DB already initialized\n"); - return -EINVAL; - } - if_tbl_db[TF_DIR_RX] = parms->cfg; if_tbl_db[TF_DIR_TX] = parms->cfg; diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index 93876d8e5d..e6ab518121 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -425,9 +425,11 @@ tf_session_open_session(struct tf *tfp, } TFP_DRV_LOG(INFO, - "Session created, session_client_id:%d, session_id:%d\n", + "Session created, session_client_id:%d," + "session_id:0x%08x, fw_session_id:%d\n", parms->open_cfg->session_client_id.id, - parms->open_cfg->session_id.id); + parms->open_cfg->session_id.id, + parms->open_cfg->session_id.internal.fw_session_id); } else { scparms.ctrl_chan_name = parms->open_cfg->ctrl_chan_name; scparms.session_client_id = &parms->open_cfg->session_client_id; @@ -438,16 +440,16 @@ tf_session_open_session(struct tf *tfp, rc = tf_session_client_create(tfp, &scparms); if (rc) { TFP_DRV_LOG(ERR, - "Failed to create client on session %d, rc:%s\n", + "Failed to create client on session 0x%x, rc:%s\n", parms->open_cfg->session_id.id, strerror(-rc)); return rc; } TFP_DRV_LOG(INFO, - "Session Client:%d created on session:%d\n", - parms->open_cfg->session_client_id.id, - parms->open_cfg->session_id.id); + "Session Client:%d registered on session:0x%8x\n", + scparms.session_client_id->internal.fw_session_client_id, + tfp->session->session_id.id); } return 0; @@ -541,7 +543,7 @@ tf_session_close_session(struct tf *tfp, client->session_client_id.id); TFP_DRV_LOG(INFO, - "session_id:%d, ref_count:%d\n", + "session_id:0x%08x, ref_count:%d\n", tfs->session_id.id, tfs->ref_count); @@ -587,7 +589,7 @@ tf_session_close_session(struct tf *tfp, tfs->ref_count--; TFP_DRV_LOG(INFO, - "Closed session, session_id:%d, ref_count:%d\n", + "Closed session, session_id:0x%08x, ref_count:%d\n", tfs->session_id.id, tfs->ref_count); diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 295204ac87..6842291adf 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -83,17 +83,15 @@ tf_tbl_bind(struct tf *tfp, db_rc[d] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else db_rc[d] = tf_rm_create_db(tfp, &db_cfg); - if (db_rc[d]) { - TFP_DRV_LOG(ERR, - "%s: No Table DB creation required\n", - tf_dir_2_str(d)); - - } } /* No db created */ - if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) + if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) { + TFP_DRV_LOG(ERR, + "%s: No Table DB created\n", + tf_dir_2_str(d)); return db_rc[TF_DIR_RX]; + } TFP_DRV_LOG(INFO, "Table Type - initialized\n"); @@ -112,12 +110,8 @@ tf_tbl_unbind(struct tf *tfp) TF_CHECK_PARMS1(tfp); rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); - if (rc) { - TFP_DRV_LOG(INFO, - "Tbl_db is not initialized, rc:%s\n", - strerror(-rc)); + if (rc) return 0; - } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 5c018f7003..7878f8727a 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -113,16 +113,13 @@ tf_tcam_bind(struct tf *tfp, db_rc[d] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else db_rc[d] = tf_rm_create_db(tfp, &db_cfg); - if (db_rc[d]) { - TFP_DRV_LOG(INFO, - "%s: no TCAM DB required\n", - tf_dir_2_str(d)); - } } /* No db created */ - if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) + if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) { + TFP_DRV_LOG(ERR, "No TCAM DB created\n"); return db_rc[TF_DIR_RX]; + } /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { @@ -227,9 +224,6 @@ tf_tcam_unbind(struct tf *tfp) rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); if (rc) { - TFP_DRV_LOG(INFO, - "Tcam_db is not initialized, rc:%s\n", - strerror(-rc)); return 0; } tcam_db = (struct tcam_rm_db *)tcam_db_ptr; From patchwork Sun May 30 08:58:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93569 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 558DFA0524; Sun, 30 May 2021 11:03:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 202704116F; Sun, 30 May 2021 11:01:05 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 332F441158 for ; Sun, 30 May 2021 11:01:01 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 926AE7DC0; Sun, 30 May 2021 02:00:59 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 926AE7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365260; bh=FEo+JbhHDy4XlIacvctl+HORwXxGACXENao6p8l7nCQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B3m4liOON8Bim3eo7xUm3pNMIyDNzLkahcd/lCr6j3NqO82LfqDtWJ46S36xGSdeO ioceOntN6gRufXNczyKJV1VSRY53SoSFJpiS2C9bgNM3tS7tJzVZCCIC1qhhVXXPyP Ksdys5Z4RREjNNFB2RSngaJDpGH1YSCvwBFYCbps= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:51 +0530 Message-Id: <20210530085929.29695-21-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 20/58] net/bnxt: add WC TCAM hi/lo move support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith - Add new API to move wc tcam regions from the hi pool to the low pool. - Enable shared tcam get/set functions on Thor. Signed-off-by: Farah Smith Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_core/tf_core.c | 53 +++ drivers/net/bnxt/tf_core/tf_core.h | 39 ++ drivers/net/bnxt/tf_core/tf_device.h | 18 + drivers/net/bnxt/tf_core/tf_device_p4.c | 1 + drivers/net/bnxt/tf_core/tf_device_p58.c | 5 +- drivers/net/bnxt/tf_core/tf_session.c | 41 ++ drivers/net/bnxt/tf_core/tf_session.h | 48 +++ drivers/net/bnxt/tf_core/tf_tcam.c | 2 +- drivers/net/bnxt/tf_core/tf_tcam_shared.c | 468 ++++++++++++++++++++-- drivers/net/bnxt/tf_core/tf_tcam_shared.h | 35 ++ 10 files changed, 673 insertions(+), 37 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index de2a93646f..73dbee2940 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -917,6 +917,59 @@ tf_free_tcam_entry(struct tf *tfp, return 0; } +#ifdef TF_TCAM_SHARED +int +tf_move_tcam_shared_entries(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + if (dev->ops->tf_dev_move_tcam == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_move_tcam(tfp, parms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM shared entries move failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return 0; +} +#endif /* TF_TCAM_SHARED */ + int tf_alloc_tbl_entry(struct tf *tfp, struct tf_alloc_tbl_entry_parms *parms) diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 39a498122b..95cde2e8eb 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -1242,6 +1242,10 @@ int tf_free_tbl_scope(struct tf *tfp, * @ref tf_get_tcam_entry * * @ref tf_free_tcam_entry + * +#ifdef TF_TCAM_SHARED + * @ref tf_move_tcam_shared_entries +#endif */ /** @@ -1543,6 +1547,41 @@ struct tf_free_tcam_entry_parms { int tf_free_tcam_entry(struct tf *tfp, struct tf_free_tcam_entry_parms *parms); +#ifdef TF_TCAM_SHARED +/** + * tf_move_tcam_shared_entries parameter definition + */ +struct tf_move_tcam_shared_entries_parms { + /** + * [in] receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] TCAM table type + */ + enum tf_tcam_tbl_type tcam_tbl_type; +}; + +/** + * Move TCAM entries + * + * This API only affects the following TCAM pools within a shared session: + * + * TF_TCAM_TBL_TYPE_WC_TCAM_HIGH + * TF_TCAM_TBL_TYPE_WC_TCAM_LOW + * + * When called, all allocated entries from the high pool will be moved to + * the low pool. Then the allocated entries in the high pool will be + * cleared and freed. + * + * This API is not supported on a non-shared session. + * + * Returns success or failure code. + */ +int tf_move_tcam_shared_entries(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms); + +#endif /* TF_TCAM_SHARED */ /** * @page table Table Access * diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index ea4dcfb8e2..48ab17d56b 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -563,6 +563,24 @@ struct tf_dev_ops { int (*tf_dev_get_tcam)(struct tf *tfp, struct tf_tcam_get_parms *parms); +#ifdef TF_TCAM_SHARED + /** + * Move TCAM shared entries + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to parameters + * + * returns: + * 0 - Success + * -EINVAL - Error + */ + int (*tf_dev_move_tcam)(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms); +#endif /* TF_TCAM_SHARED */ + /** * Retrieves the tcam resource info. * diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index fccbccc2d8..c870f45ff0 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -275,6 +275,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_free_tcam = tf_tcam_shared_free, .tf_dev_set_tcam = tf_tcam_shared_set, .tf_dev_get_tcam = tf_tcam_shared_get, + .tf_dev_move_tcam = tf_tcam_shared_move_p4, #else /* !TF_TCAM_SHARED */ .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index b25c5acf94..14b9d28b13 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -295,8 +295,9 @@ const struct tf_dev_ops tf_dev_ops_p58 = { #ifdef TF_TCAM_SHARED .tf_dev_alloc_tcam = tf_tcam_shared_alloc, .tf_dev_free_tcam = tf_tcam_shared_free, - .tf_dev_set_tcam = tf_tcam_set, - .tf_dev_get_tcam = tf_tcam_get, + .tf_dev_set_tcam = tf_tcam_shared_set, + .tf_dev_get_tcam = tf_tcam_shared_get, + .tf_dev_move_tcam = tf_tcam_shared_move_p58, #else /* !TF_TCAM_SHARED */ .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index e6ab518121..70844edb50 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -945,3 +945,44 @@ tf_session_set_db(struct tf *tfp, return rc; } + +#ifdef TF_TCAM_SHARED + +int +tf_session_get_tcam_shared_db(struct tf *tfp, + void **tcam_shared_db_handle) +{ + struct tf_session *tfs = NULL; + int rc = 0; + + *tcam_shared_db_handle = NULL; + + if (tfp == NULL) + return (-EINVAL); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + *tcam_shared_db_handle = tfs->tcam_shared_db_handle; + return rc; +} + +int +tf_session_set_tcam_shared_db(struct tf *tfp, + void *tcam_shared_db_handle) +{ + struct tf_session *tfs = NULL; + int rc = 0; + + if (tfp == NULL) + return (-EINVAL); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + tfs->tcam_shared_db_handle = tcam_shared_db_handle; + return rc; +} +#endif /* TF_TCAM_SHARED */ diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index 034a2213a4..c2875f9fa1 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -159,6 +159,13 @@ struct tf_session { * EM allocator for session */ void *em_pool[TF_DIR_MAX]; + +#ifdef TF_TCAM_SHARED + /** + * tcam db reference for the session + */ + void *tcam_shared_db_handle; +#endif /* TF_TCAM_SHARED */ }; /** @@ -255,6 +262,22 @@ struct tf_session_close_session_parms { * @ref tf_session_get_fw_session_id * * @ref tf_session_get_session_id + * + * @ref tf_session_is_shared_session_creator + * + * @ref tf_session_get_db + * + * @ref tf_session_set_db + * + * @ref tf_session_get_bp + * + * @ref tf_session_is_shared_session + * + * #define TF_SHARED + * @ref tf_session_get_tcam_shared_db + * + * @ref tf_session_set_tcam_shared_db + * #endif */ /** @@ -566,4 +589,29 @@ tf_session_get_bp(struct tf *tfp) { return tfp->bp; } + +/** + * Set the pointer to the tcam shared database + * + * [in] session, pointer to the session + * + * Returns: + * - the pointer to the parent bnxt struct + */ +int +tf_session_set_tcam_shared_db(struct tf *tfp, + void *tcam_shared_db_handle); + +/** + * Get the pointer to the tcam shared database + * + * [in] session, pointer to the session + * + * Returns: + * - the pointer to the parent bnxt struct + */ +int +tf_session_get_tcam_shared_db(struct tf *tfp, + void **tcam_shared_db_handle); + #endif /* _TF_SESSION_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 7878f8727a..d7e12e00ef 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -299,7 +299,7 @@ tf_tcam_alloc(struct tf *tfp, rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); if (rc) { TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", + "Failed to get tcam_db from session, rc:%s\n", strerror(-rc)); return rc; } diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c index 17d7fee7a8..0e8cb78f8d 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c @@ -53,10 +53,34 @@ struct tf_tcam_shared_wc_pool { struct bitalloc *pool; }; +struct tf_tcam_shared_wc_pools { + struct tf_tcam_shared_wc_pool db[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX]; +}; + /** The WC TCAM shared pool declarations - * TODO: add tcam_shared_wc_db */ -struct tf_tcam_shared_wc_pool tcam_shared_wc[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX]; +/* struct tf_tcam_shared_wc_pool tcam_shared_wc[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX]; */ + +static int +tf_tcam_shared_create_db(struct tf_tcam_shared_wc_pools **db) +{ + struct tfp_calloc_parms cparms; + int rc = 0; + + cparms.nitems = 1; + cparms.alignment = 0; + cparms.size = sizeof(struct tf_tcam_shared_wc_pools); + rc = tfp_calloc(&cparms); + if (rc) { + TFP_DRV_LOG(ERR, + "TCAM shared db allocation failed (%s)\n", + strerror(-rc)); + return rc; + } + *db = cparms.mem_va; + + return rc; +} /** Create a WC TCAM shared pool */ @@ -64,7 +88,8 @@ static int tf_tcam_shared_create_wc_pool(int dir, enum tf_tcam_shared_wc_pool_id id, int start, - int stride) + int stride, + struct tf_tcam_shared_wc_pools *tcam_shared_wc) { int rc = 0; bool free = true; @@ -84,9 +109,9 @@ tf_tcam_shared_create_wc_pool(int dir, strerror(-rc)); return rc; } - tcam_shared_wc[dir][id].pool = (struct bitalloc *)cparms.mem_va; + tcam_shared_wc->db[dir][id].pool = (struct bitalloc *)cparms.mem_va; - rc = ba_init(tcam_shared_wc[dir][id].pool, + rc = ba_init(tcam_shared_wc->db[dir][id].pool, stride, free); @@ -97,21 +122,27 @@ tf_tcam_shared_create_wc_pool(int dir, return rc; } - tcam_shared_wc[dir][id].info.start = start; - tcam_shared_wc[dir][id].info.stride = stride; + tcam_shared_wc->db[dir][id].info.start = start; + tcam_shared_wc->db[dir][id].info.stride = stride; + return rc; } /** Free a WC TCAM shared pool */ -static void +static int tf_tcam_shared_free_wc_pool(int dir, - enum tf_tcam_shared_wc_pool_id id) + enum tf_tcam_shared_wc_pool_id id, + struct tf_tcam_shared_wc_pools *tcam_shared_wc) { - tcam_shared_wc[dir][id].info.start = 0; - tcam_shared_wc[dir][id].info.stride = 0; + int rc = 0; + TF_CHECK_PARMS1(tcam_shared_wc); + + tcam_shared_wc->db[dir][id].info.start = 0; + tcam_shared_wc->db[dir][id].info.stride = 0; - if (tcam_shared_wc[dir][id].pool) - tfp_free((void *)tcam_shared_wc[dir][id].pool); + if (tcam_shared_wc->db[dir][id].pool) + tfp_free((void *)tcam_shared_wc->db[dir][id].pool); + return rc; } /** Get the number of WC TCAM slices allocated during 1 allocation/free @@ -137,7 +168,7 @@ tf_tcam_shared_get_slices(struct tf *tfp, } static bool -tf_tcam_shared_db_valid(struct tf *tfp, +tf_tcam_db_valid(struct tf *tfp, enum tf_dir dir) { struct tcam_rm_db *tcam_db; @@ -226,6 +257,7 @@ tf_tcam_shared_bind(struct tf *tfp, uint16_t start, stride; uint16_t num_slices; uint16_t hcapi_type; + struct tf_tcam_shared_wc_pools *tcam_shared_wc = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -256,11 +288,14 @@ tf_tcam_shared_bind(struct tf *tfp, if (rc) return rc; + tf_tcam_shared_create_db(&tcam_shared_wc); + + /* If there are WC TCAM entries, create 2 pools each with 1/2 * the total number of entries */ for (dir = 0; dir < TF_DIR_MAX; dir++) { - if (!tf_tcam_shared_db_valid(tfp, dir)) + if (!tf_tcam_db_valid(tfp, dir)) continue; rc = tf_tcam_shared_get_rm_info(tfp, @@ -278,15 +313,19 @@ tf_tcam_shared_bind(struct tf *tfp, stride = info.entry.stride / 2; tf_tcam_shared_create_wc_pool(dir, - TF_TCAM_SHARED_WC_POOL_HI, - start, - stride); + TF_TCAM_SHARED_WC_POOL_HI, + start, + stride, + tcam_shared_wc); start += stride; tf_tcam_shared_create_wc_pool(dir, - TF_TCAM_SHARED_WC_POOL_LO, - start, - stride); + TF_TCAM_SHARED_WC_POOL_LO, + start, + stride, + tcam_shared_wc); + + tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc); } } done: @@ -300,6 +339,8 @@ tf_tcam_shared_unbind(struct tf *tfp) { int rc, dir; struct tf_session *tfs; + void *tcam_shared_db_ptr = NULL; + struct tf_tcam_shared_wc_pools *tcam_shared_wc; TF_CHECK_PARMS1(tfp); @@ -315,6 +356,15 @@ tf_tcam_shared_unbind(struct tf *tfp) if (rc) return rc; + rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get tcam_shared_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; + /* If we are the shared session */ if (tf_session_is_shared_session(tfs)) { @@ -322,9 +372,11 @@ tf_tcam_shared_unbind(struct tf *tfp) */ for (dir = 0; dir < TF_DIR_MAX; dir++) { tf_tcam_shared_free_wc_pool(dir, - TF_TCAM_SHARED_WC_POOL_HI); + TF_TCAM_SHARED_WC_POOL_HI, + tcam_shared_wc); tf_tcam_shared_free_wc_pool(dir, - TF_TCAM_SHARED_WC_POOL_LO); + TF_TCAM_SHARED_WC_POOL_LO, + tcam_shared_wc); } } return 0; @@ -343,6 +395,8 @@ tf_tcam_shared_alloc(struct tf *tfp, struct bitalloc *pool; enum tf_tcam_shared_wc_pool_id id; uint16_t num_slices; + struct tf_tcam_shared_wc_pools *tcam_shared_wc; + void *tcam_shared_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -364,13 +418,22 @@ tf_tcam_shared_alloc(struct tf *tfp, return rc; } - if (!tf_tcam_shared_db_valid(tfp, parms->dir)) { + if (!tf_tcam_db_valid(tfp, parms->dir)) { TFP_DRV_LOG(ERR, "%s: tcam shared pool doesn't exist\n", tf_dir_2_str(parms->dir)); return -ENOMEM; } + rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get tcam_shared_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; + if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) id = TF_TCAM_SHARED_WC_POOL_HI; else @@ -385,7 +448,7 @@ tf_tcam_shared_alloc(struct tf *tfp, if (rc) return rc; - pool = tcam_shared_wc[parms->dir][id].pool; + pool = tcam_shared_wc->db[parms->dir][id].pool; for (i = 0; i < num_slices; i++) { /* @@ -427,6 +490,8 @@ tf_tcam_shared_free(struct tf *tfp, uint16_t num_slices; uint16_t hcapi_type; struct tf_rm_alloc_info info; + void *tcam_shared_db_ptr = NULL; + struct tf_tcam_shared_wc_pools *tcam_shared_wc; TF_CHECK_PARMS2(tfp, parms); @@ -448,13 +513,23 @@ tf_tcam_shared_free(struct tf *tfp, return rc; } - if (!tf_tcam_shared_db_valid(tfp, parms->dir)) { + if (!tf_tcam_db_valid(tfp, parms->dir)) { TFP_DRV_LOG(ERR, "%s: tcam shared pool doesn't exist\n", tf_dir_2_str(parms->dir)); return -ENOMEM; } + rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get tcam_shared_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; + + if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) id = TF_TCAM_SHARED_WC_POOL_HI; else @@ -480,8 +555,8 @@ tf_tcam_shared_free(struct tf *tfp, return rc; } - pool = tcam_shared_wc[parms->dir][id].pool; - start = tcam_shared_wc[parms->dir][id].info.start; + pool = tcam_shared_wc->db[parms->dir][id].pool; + start = tcam_shared_wc->db[parms->dir][id].info.start; if (parms->idx % num_slices) { TFP_DRV_LOG(ERR, @@ -548,6 +623,9 @@ tf_tcam_shared_set(struct tf *tfp __rte_unused, enum tf_tcam_shared_wc_pool_id id; uint16_t hcapi_type; struct tf_rm_alloc_info info; + struct tf_tcam_shared_wc_pools *tcam_shared_wc; + void *tcam_shared_db_ptr = NULL; + TF_CHECK_PARMS2(tfp, parms); @@ -568,7 +646,7 @@ tf_tcam_shared_set(struct tf *tfp __rte_unused, return rc; } - if (!tf_tcam_shared_db_valid(tfp, parms->dir)) { + if (!tf_tcam_db_valid(tfp, parms->dir)) { TFP_DRV_LOG(ERR, "%s: tcam shared pool doesn't exist\n", tf_dir_2_str(parms->dir)); @@ -585,8 +663,17 @@ tf_tcam_shared_set(struct tf *tfp __rte_unused, else id = TF_TCAM_SHARED_WC_POOL_LO; - pool = tcam_shared_wc[parms->dir][id].pool; - start = tcam_shared_wc[parms->dir][id].info.start; + rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get tcam_shared_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; + + pool = tcam_shared_wc->db[parms->dir][id].pool; + start = tcam_shared_wc->db[parms->dir][id].info.start; log_idx = parms->idx; phy_idx = parms->idx + start; @@ -656,6 +743,8 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused, enum tf_tcam_shared_wc_pool_id id; uint16_t hcapi_type; struct tf_rm_alloc_info info; + struct tf_tcam_shared_wc_pools *tcam_shared_wc; + void *tcam_shared_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -676,7 +765,7 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused, return rc; } - if (!tf_tcam_shared_db_valid(tfp, parms->dir)) { + if (!tf_tcam_db_valid(tfp, parms->dir)) { TFP_DRV_LOG(ERR, "%s: tcam shared pool doesn't exist\n", tf_dir_2_str(parms->dir)); @@ -692,8 +781,18 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused, else id = TF_TCAM_SHARED_WC_POOL_LO; - pool = tcam_shared_wc[parms->dir][id].pool; - start = tcam_shared_wc[parms->dir][id].info.start; + + rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get tcam_shared_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; + + pool = tcam_shared_wc->db[parms->dir][id].pool; + start = tcam_shared_wc->db[parms->dir][id].info.start; rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); if (rc) @@ -742,3 +841,304 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused, } return 0; } + +/* Temporary builder defines pulled in here and renamed + */ +#define TF_TMP_MAX_FIELD_BITLEN 512 + +union tf_tmp_field_obj { + uint8_t bytes[(TF_TMP_MAX_FIELD_BITLEN + 7) / 8]; +}; + +#define TF_TMP_MAX_KEY_BITLEN 768 +#define TF_TMP_MAX_KEY_WORDLEN ((TF_TMP_MAX_KEY_BITLEN + 63) / 64) + +union tf_tmp_key { + uint32_t words[(TF_TMP_MAX_KEY_BITLEN + 31) / 32]; + uint8_t bytes[(TF_TMP_MAX_KEY_BITLEN + 7) / 8]; +}; + +/** Move a WC TCAM entry from the high offset to the same low offset + */ +static int +tf_tcam_shared_move_entry(struct tf *tfp, + struct tf_dev_info *dev, + uint16_t hcapi_type, + enum tf_dir dir, + int sphy_idx, + int dphy_idx, + int key_sz_bytes, + int remap_sz_bytes, + uint16_t num_slices) +{ + int rc = 0; + struct tf_tcam_get_parms gparms; + struct tf_tcam_set_parms sparms; + struct tf_tcam_free_parms fparms; + union tf_tmp_key tcam_key_obj; + union tf_tmp_key tcam_key_msk_obj; + union tf_tmp_field_obj tcam_remap_obj; + + memset(&tcam_key_obj, 0, sizeof(tcam_key_obj)); + memset(&tcam_key_msk_obj, 0, sizeof(tcam_key_msk_obj)); + memset(&tcam_remap_obj, 0, sizeof(tcam_remap_obj)); + memset(&gparms, 0, sizeof(gparms)); + + if (num_slices > 1) { + TFP_DRV_LOG(ERR, + "Only single slice supported"); + return -EOPNOTSUPP; + } + + gparms.hcapi_type = hcapi_type; + gparms.dir = dir; + gparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; + gparms.idx = sphy_idx; + gparms.key = (uint8_t *)&tcam_key_obj; + gparms.key_size = key_sz_bytes; + gparms.mask = (uint8_t *)&tcam_key_msk_obj; + gparms.result = (uint8_t *)&tcam_remap_obj; + gparms.result_size = remap_sz_bytes; + + rc = tf_msg_tcam_entry_get(tfp, dev, &gparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: WC_TCAM_HIGH: phyid(%d) get failed, rc:%s", + tf_dir_2_str(dir), + gparms.idx, + strerror(-rc)); + return rc; + } + + /* Override HI/LO type with parent WC TCAM type */ + sparms.hcapi_type = hcapi_type; + sparms.dir = dir; + sparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; + sparms.idx = dphy_idx; + sparms.key = gparms.key; + sparms.mask = gparms.mask; + sparms.key_size = gparms.key_size; + sparms.result = gparms.result; + sparms.result_size = gparms.result_size; + + rc = tf_msg_tcam_entry_set(tfp, dev, &sparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: WC_TCAM_LOW phyid(%d) set failed, rc:%s", + tf_dir_2_str(dir), + sparms.idx, + strerror(-rc)); + return rc; + } + + /* Override HI/LO type with parent WC TCAM type */ + fparms.dir = dir; + fparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; + fparms.hcapi_type = hcapi_type; + fparms.idx = sphy_idx; + + rc = tf_msg_tcam_entry_free(tfp, dev, &fparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: %s: phyid(%d) free failed, rc:%s\n", + tf_dir_2_str(dir), + tf_tcam_tbl_2_str(fparms.type), + sphy_idx, + strerror(-rc)); + return rc; + } + return rc; +} + +/** Move all shared WC TCAM entries from the high pool into the low pool + * and clear out the high pool entries. + */ +static +int tf_tcam_shared_move(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms, + int key_sz_bytes, + int remap_sz_bytes) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + int log_idx; + uint16_t num_slices; + struct bitalloc *hi_pool, *lo_pool; + uint16_t hi_start, lo_start; + enum tf_tcam_shared_wc_pool_id hi_id, lo_id; + uint16_t hcapi_type; + struct tf_rm_alloc_info info; + int hi_cnt, i, j; + struct tf_tcam_shared_wc_pools *tcam_shared_wc; + void *tcam_shared_db_ptr = NULL; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* If we aren't the shared session or one of our + * special types + */ + if (!tf_session_is_shared_session(tfs) || + (parms->tcam_tbl_type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && + parms->tcam_tbl_type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { + TFP_DRV_LOG(ERR, + "%s: Session must be shared with HI/LO type\n", + tf_dir_2_str(parms->dir)); + return -EOPNOTSUPP; + } + + if (!tf_tcam_db_valid(tfp, parms->dir)) { + TFP_DRV_LOG(ERR, + "%s: tcam shared pool doesn't exist\n", + tf_dir_2_str(parms->dir)); + return -ENOMEM; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + /* TODO print amazing error */ + return rc; + } + rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); + if (rc) + return rc; + + rc = tf_tcam_shared_get_rm_info(tfp, + parms->dir, + &hcapi_type, + &info); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM rm info get failed\n", + tf_dir_2_str(parms->dir)); + return rc; + } + + rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get tcam_shared_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; + + hi_id = TF_TCAM_SHARED_WC_POOL_HI; + hi_pool = tcam_shared_wc->db[parms->dir][hi_id].pool; + hi_start = tcam_shared_wc->db[parms->dir][hi_id].info.start; + + lo_id = TF_TCAM_SHARED_WC_POOL_LO; + lo_pool = tcam_shared_wc->db[parms->dir][lo_id].pool; + lo_start = tcam_shared_wc->db[parms->dir][lo_id].info.start; + + if (hi_pool == NULL || lo_pool == NULL) + return -ENOMEM; + + /* Get the total count of in use entries in the high pool + */ + hi_cnt = ba_inuse_count(hi_pool); + + /* Copy each valid entry to the same low pool logical offset + */ + for (i = 0; i < hi_cnt; i++) { + /* Go through all the slices + */ + for (j = 0; j < num_slices; j++) { + /* Find next free starting from where we left off + */ + log_idx = ba_find_next_inuse(hi_pool, i); + + if (log_idx < 0) { + TFP_DRV_LOG(ERR, + "Expected a found %s entry %d\n", + tf_pool_2_str(hi_id), + i); + goto done; + } + /* The user should have never allocated from the low + * pool because the move only happens when switching + * from the high to the low pool + */ + if (ba_alloc_index(lo_pool, log_idx) < 0) { + TFP_DRV_LOG(ERR, + "Cannot allocate %s index %d\n", + tf_pool_2_str(lo_id), + i); + goto done; + } + + if (j == 0) { + rc = tf_tcam_shared_move_entry(tfp, dev, + hcapi_type, + parms->dir, + hi_start + log_idx, + lo_start + log_idx, + key_sz_bytes, + remap_sz_bytes, + num_slices); + if (rc) { + TFP_DRV_LOG(ERR, + "Cannot allocate %s index %d\n", + tf_pool_2_str(hi_id), + i); + goto done; + } + ba_free(hi_pool, log_idx); + TFP_DRV_LOG(DEBUG, + "%s: TCAM shared move pool(%s) phyid(%d)\n", + tf_dir_2_str(parms->dir), + tf_pool_2_str(hi_id), + hi_start + log_idx); + TFP_DRV_LOG(DEBUG, + "to pool(%s) phyid(%d)\n", + tf_pool_2_str(lo_id), + lo_start + log_idx); + } + } + } +done: + return rc; +} + +/* Normally, device specific code wouldn't reside here, it belongs + * in a separate device specific function in tf_device_pxx.c. + * But this code is placed here as it is not a long term solution + * and we would like to have this code centrally located for easy + * removal + */ +#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4 12 +#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P4 4 + +int tf_tcam_shared_move_p4(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms) +{ + int rc = 0; + rc = tf_tcam_shared_move(tfp, + parms, + TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4, + TF_TCAM_SHARED_REMAP_SZ_BYTES_P4); + return rc; +} + +#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 24 +#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 8 + +int tf_tcam_shared_move_p58(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms) +{ + int rc = 0; + rc = tf_tcam_shared_move(tfp, + parms, + TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58, + TF_TCAM_SHARED_REMAP_SZ_BYTES_P58); + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h index fad6e23b4c..5588125470 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.h +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h @@ -124,4 +124,39 @@ int tf_tcam_shared_set(struct tf *tfp, int tf_tcam_shared_get(struct tf *tfp, struct tf_tcam_get_parms *parms); + +/** + * Moves entries from the WC_TCAM_HI to the WC_TCAM_LO shared pools + * for the P4 device. + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_move_p4(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms); + +/** + * Moves entries from the WC_TCAM_HI to the WC_TCAM_LO shared pools + * for the P58 device. + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_move_p58(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms); + #endif /* _TF_TCAM_SHARED_H */ From patchwork Sun May 30 08:58:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93570 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E425EA0524; Sun, 30 May 2021 11:03:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3235C41190; Sun, 30 May 2021 11:01:06 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id E27394118C for ; Sun, 30 May 2021 11:01:02 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 4D9FE7DC2; Sun, 30 May 2021 02:01:01 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 4D9FE7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365262; bh=UH4m8pxnu5FEqervG+mLEoEkMUuykm1gnQarsZsjY8c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r9EywzJn4wbI1u6ehfK7QV+rHFh08wDQg5UvYAhL72onBsEbD8NeuxDrmblfaKpLt zZ0R1OF+LE3SOpxVX0KipTYL15fiThhknmo7I5YXlMGWAGOBbWzEOjjHPzHw+nFr7+ PWXg5vhBvp/ZKRgt68lU+XpcSt6Mh9jdTF8mV0qY= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:52 +0530 Message-Id: <20210530085929.29695-22-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 21/58] net/bnxt: add API to get shared table increments X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith Provide tf API to get the shared table increment value for a given TF table type. Signed-off-by: Farah Smith Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_core/tf_core.c | 52 +++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_core.h | 34 ++++++++++++++- drivers/net/bnxt/tf_core/tf_device.h | 17 ++++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 25 +++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.c | 44 +++++++++++++++++++ drivers/net/bnxt/tf_core/tf_tcam_shared.c | 22 +++++++--- 6 files changed, 188 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 73dbee2940..0fbbd40252 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1415,6 +1415,58 @@ tf_bulk_get_tbl_entry(struct tf *tfp, return rc; } +int tf_get_shared_tbl_increment(struct tf *tfp, + struct tf_get_shared_tbl_increment_parms *parms) +{ + int rc = 0; + struct tf_session *tfs; + struct tf_dev_info *dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Internal table type processing */ + + if (dev->ops->tf_dev_get_shared_tbl_increment == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + rc = dev->ops->tf_dev_get_shared_tbl_increment(tfp, parms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Get table increment not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} + int tf_alloc_tbl_scope(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms) diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 95cde2e8eb..44c30fa904 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -848,7 +848,6 @@ struct tf_get_session_info_parms { */ int tf_get_session_info(struct tf *tfp, struct tf_get_session_info_parms *parms); - /** * Experimental * @@ -1594,6 +1593,8 @@ int tf_move_tcam_shared_entries(struct tf *tfp, * @ref tf_get_tbl_entry * * @ref tf_bulk_get_tbl_entry + * + * @ref tf_get_shared_tbl_increment */ /** @@ -1844,6 +1845,37 @@ struct tf_set_tbl_entry_parms { int tf_set_tbl_entry(struct tf *tfp, struct tf_set_tbl_entry_parms *parms); +/** + * tf_get_shared_tbl_increment parameter definition + */ +struct tf_get_shared_tbl_increment_parms { + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] Type of object to set + */ + enum tf_tbl_type type; + /** + * [out] Value to increment by for resource type + */ + uint32_t increment_cnt; +}; + +/** + * tf_get_shared_tbl_increment + * + * This API is currently only required for use in the shared + * session for Thor (p58) actions. An increment count is returned per + * type to indicate how much to increment the start by for each + * entry (see tf_resource_info) + * + * Returns success or failure code. + */ +int tf_get_shared_tbl_increment(struct tf *tfp, + struct tf_get_shared_tbl_increment_parms *parms); + /** * tf_get_tbl_entry parameter definition */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 48ab17d56b..1893f630e7 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -446,6 +446,23 @@ struct tf_dev_ops { int (*tf_dev_get_bulk_tbl)(struct tf *tfp, struct tf_tbl_get_bulk_parms *parms); + /** + * Gets the increment value to add to the shared session resource + * start offset by for each count in the "stride" + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to get shared tbl increment parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_shared_tbl_increment)(struct tf *tfp, + struct tf_get_shared_tbl_increment_parms *parms); + /** * Retrieves the table resource info. * diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index c870f45ff0..28a6e41906 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -193,6 +193,26 @@ tf_dev_p4_map_parif(struct tf *tfp __rte_unused, return 0; } +/** + * Device specific function that retrieves the increment + * required for certain table types in a shared session + * + * [in] tfp + * tf handle + * + * [in/out] parms + * pointer to parms structure + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p4_get_shared_tbl_increment(struct tf *tfp __rte_unused, + struct tf_get_shared_tbl_increment_parms *parms) +{ + parms->increment_cnt = 1; + return 0; +} static int tf_dev_p4_get_mailbox(void) { return TF_KONG_MB; @@ -224,12 +244,16 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_set_ext_tbl = NULL, .tf_dev_get_tbl = NULL, .tf_dev_get_bulk_tbl = NULL, + .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = NULL, .tf_dev_alloc_tcam = NULL, .tf_dev_free_tcam = NULL, .tf_dev_alloc_search_tcam = NULL, .tf_dev_set_tcam = NULL, .tf_dev_get_tcam = NULL, +#ifdef TF_TCAM_SHARED + .tf_dev_move_tcam = NULL, +#endif /* TF_TCAM_SHARED */ .tf_dev_get_tcam_resc_info = NULL, .tf_dev_insert_int_em_entry = NULL, .tf_dev_delete_int_em_entry = NULL, @@ -269,6 +293,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, + .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, #ifdef TF_TCAM_SHARED .tf_dev_alloc_tcam = tf_tcam_shared_alloc, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 14b9d28b13..bd6813beef 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -154,6 +154,48 @@ static int tf_dev_p58_word_align(uint16_t size) return ((((size) + 63) >> 6) * 8); } +/** + * Device specific function that retrieves the increment + * required for certain table types in a shared session + * + * [in] tfp + * tf handle + * + * [in/out] parms + * pointer to parms structure + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused, + struct tf_get_shared_tbl_increment_parms *parms) +{ + switch (parms->type) { + case TF_TBL_TYPE_FULL_ACT_RECORD: + case TF_TBL_TYPE_COMPACT_ACT_RECORD: + case TF_TBL_TYPE_ACT_ENCAP_8B: + case TF_TBL_TYPE_ACT_ENCAP_16B: + case TF_TBL_TYPE_ACT_ENCAP_32B: + case TF_TBL_TYPE_ACT_ENCAP_64B: + case TF_TBL_TYPE_ACT_SP_SMAC: + case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: + case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: + case TF_TBL_TYPE_ACT_STATS_64: + case TF_TBL_TYPE_ACT_MODIFY_IPV4: + case TF_TBL_TYPE_ACT_MODIFY_8B: + case TF_TBL_TYPE_ACT_MODIFY_16B: + case TF_TBL_TYPE_ACT_MODIFY_32B: + case TF_TBL_TYPE_ACT_MODIFY_64B: + parms->increment_cnt = 8; + break; + default: + parms->increment_cnt = 1; + break; + } + return 0; +} + #define TF_DEV_P58_BANK_SZ_64B 2048 /** * Get SRAM table information. @@ -246,6 +288,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_set_ext_tbl = NULL, .tf_dev_get_tbl = NULL, .tf_dev_get_bulk_tbl = NULL, + .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = NULL, .tf_dev_alloc_tcam = NULL, .tf_dev_free_tcam = NULL, @@ -291,6 +334,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, + .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, #ifdef TF_TCAM_SHARED .tf_dev_alloc_tcam = tf_tcam_shared_alloc, diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c index 0e8cb78f8d..f0727cea80 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c @@ -858,6 +858,10 @@ union tf_tmp_key { uint8_t bytes[(TF_TMP_MAX_KEY_BITLEN + 7) / 8]; }; +/** p58 has an enable bit, p4 does not + */ +#define TF_TCAM_SHARED_ENTRY_ENABLE 0x8 + /** Move a WC TCAM entry from the high offset to the same low offset */ static int @@ -869,7 +873,8 @@ tf_tcam_shared_move_entry(struct tf *tfp, int dphy_idx, int key_sz_bytes, int remap_sz_bytes, - uint16_t num_slices) + uint16_t num_slices, + bool set_enable_bit) { int rc = 0; struct tf_tcam_get_parms gparms; @@ -911,6 +916,9 @@ tf_tcam_shared_move_entry(struct tf *tfp, return rc; } + if (set_enable_bit) + tcam_key_obj.bytes[0] |= TF_TCAM_SHARED_ENTRY_ENABLE; + /* Override HI/LO type with parent WC TCAM type */ sparms.hcapi_type = hcapi_type; sparms.dir = dir; @@ -960,7 +968,8 @@ static int tf_tcam_shared_move(struct tf *tfp, struct tf_move_tcam_shared_entries_parms *parms, int key_sz_bytes, - int remap_sz_bytes) + int remap_sz_bytes, + bool set_enable_bit) { int rc; struct tf_session *tfs; @@ -1084,7 +1093,8 @@ int tf_tcam_shared_move(struct tf *tfp, lo_start + log_idx, key_sz_bytes, remap_sz_bytes, - num_slices); + num_slices, + set_enable_bit); if (rc) { TFP_DRV_LOG(ERR, "Cannot allocate %s index %d\n", @@ -1125,7 +1135,8 @@ int tf_tcam_shared_move_p4(struct tf *tfp, rc = tf_tcam_shared_move(tfp, parms, TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4, - TF_TCAM_SHARED_REMAP_SZ_BYTES_P4); + TF_TCAM_SHARED_REMAP_SZ_BYTES_P4, + false); /* no enable bit */ return rc; } @@ -1139,6 +1150,7 @@ int tf_tcam_shared_move_p58(struct tf *tfp, rc = tf_tcam_shared_move(tfp, parms, TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58, - TF_TCAM_SHARED_REMAP_SZ_BYTES_P58); + TF_TCAM_SHARED_REMAP_SZ_BYTES_P58, + true); /* set enable bit */ return rc; } From patchwork Sun May 30 08:58:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93571 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 903FFA0524; Sun, 30 May 2021 11:03:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A3C5A41196; Sun, 30 May 2021 11:01:07 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id D08F341158 for ; Sun, 30 May 2021 11:01:04 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 08B397DAF; Sun, 30 May 2021 02:01:02 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 08B397DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365264; bh=Ys7x9aSzmDrCibh3+lAEEt4Icmwtv1Kdhlmz/OIwrFk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uaZJMryZpLw8WuTIQBS6Q3gLAtfiDcyX/YTknXnhWOLbQbwAnj0nXmvqCCXoVvWl7 qgATAP9Qbf6Loxq6jfCKAqDx+Cj1GJ4M96hdoX5HcMFIVY/tl/YQ0GvB9ac337rQ+C V6PchrzDEXbBfx5xqu2femHtHkRkz3ziNNqGmfQU= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Farah Smith , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:53 +0530 Message-Id: <20210530085929.29695-23-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 22/58] net/bnxt: modify host session failure cleanup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding - Close fw session if session open fails after fw session open. - Additional WC TCAM debug info to help in future debug - Reduce key/mask buffer sizes for performance - When a 64b counter is freed, clear the entry Signed-off-by: Jay Ding Signed-off-by: Farah Smith Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_core/tf_em_internal.c | 15 +++--- drivers/net/bnxt/tf_core/tf_identifier.c | 14 ++++-- drivers/net/bnxt/tf_core/tf_msg.c | 24 ++------- drivers/net/bnxt/tf_core/tf_msg.h | 9 +++- drivers/net/bnxt/tf_core/tf_rm.c | 59 +++-------------------- drivers/net/bnxt/tf_core/tf_session.c | 32 ++++++++++-- drivers/net/bnxt/tf_core/tf_tbl.c | 51 ++++++++++++++++++-- drivers/net/bnxt/tf_core/tf_tcam.c | 14 ++++-- drivers/net/bnxt/tf_core/tf_tcam_shared.c | 41 ++++++++-------- 9 files changed, 138 insertions(+), 121 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 28ffbd5876..0720bb905d 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -543,18 +543,21 @@ tf_em_get_resc_info(struct tf *tfp, TF_CHECK_PARMS2(tfp, em); rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); - if (rc) { - TFP_DRV_LOG(INFO, - "No resource allocated for em from session\n"); - return 0; - } + if (rc == -ENOMEM) + return 0; /* db does not exist */ + else if (rc) + return rc; /* db error */ + em_db = (struct em_rm_db *)em_db_ptr; - /* check if reserved resource for WC is multiple of num_slices */ + /* check if reserved resource for EM is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { ainfo.rm_db = em_db->em_db[d]; dinfo = em[d].info; + if (!ainfo.rm_db) + continue; + ainfo.info = (struct tf_rm_alloc_info *)dinfo; ainfo.subtype = 0; rc = tf_rm_get_all_info(&ainfo, TF_EM_TBL_TYPE_MAX); diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index 9f27a41fcf..c491f77a2b 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -369,16 +369,20 @@ tf_ident_get_resc_info(struct tf *tfp, TF_CHECK_PARMS2(tfp, ident); rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); - if (rc) { - TFP_DRV_LOG(INFO, - "No resource allocated for ident from session\n"); - return 0; - } + if (rc == -ENOMEM) + return 0; /* db doesn't exist */ + else if (rc) + return rc; /* error getting db */ + ident_db = (struct ident_rm_db *)ident_db_ptr; /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { ainfo.rm_db = ident_db->ident_db[d]; + + if (!ainfo.rm_db) + continue; + dinfo = ident[d].info; ainfo.info = (struct tf_rm_alloc_info *)dinfo; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 18eea8338a..fbd4b1d910 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -267,31 +267,13 @@ tf_msg_session_client_unregister(struct tf *tfp, int tf_msg_session_close(struct tf *tfp, - struct tf_session *tfs) + uint8_t fw_session_id, + int mailbox) { int rc; struct hwrm_tf_session_close_input req = { 0 }; struct hwrm_tf_session_close_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; - uint8_t fw_session_id; - struct tf_dev_info *dev; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup device, rc:%s\n", - strerror(-rc)); - return rc; - } - - rc = tf_session_get_fw_session_id(tfp, &fw_session_id); - if (rc) { - TFP_DRV_LOG(ERR, - "Unable to lookup FW id, rc:%s\n", - strerror(-rc)); - return rc; - } /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); @@ -301,7 +283,7 @@ tf_msg_session_close(struct tf *tfp, parms.req_size = sizeof(req); parms.resp_data = (uint32_t *)&resp; parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); + parms.mailbox = mailbox; rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index e8662fef0e..b26b15bfa3 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -115,11 +115,18 @@ int tf_msg_session_client_unregister(struct tf *tfp, * [in] session * Pointer to session handle * + * [in] fw_session_id + * fw session id + * + * [in] mailbox + * mailbox + * * Returns: * 0 on Success else internal Truflow error */ int tf_msg_session_close(struct tf *tfp, - struct tf_session *tfs); + uint8_t fw_session_id, + int mailbox); /** * Sends session query config request to TF Firmware diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index 761d18413b..b57f200edf 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -18,9 +18,6 @@ #include "tfp.h" #include "tf_msg.h" -/* Logging defines */ -#define TF_RM_DEBUG 0 - /** * Generic RM Element data type that an RM DB is build upon. */ @@ -204,44 +201,6 @@ tf_rm_adjust_index(struct tf_rm_element *db, return rc; } -/** - * Logs an array of found residual entries to the console. - * - * [in] dir - * Receive or transmit direction - * - * [in] module - * Type of Device Module - * - * [in] count - * Number of entries in the residual array - * - * [in] residuals - * Pointer to an array of residual entries. Array is index same as - * the DB in which this function is used. Each entry holds residual - * value for that entry. - */ -static void -tf_rm_log_residuals(enum tf_dir dir, - enum tf_module_type module, - uint16_t count, - uint16_t *residuals) -{ - int i; - - /* Walk the residual array and log the types that wasn't - * cleaned up to the console. - */ - for (i = 0; i < count; i++) { - if (residuals[i] != 0) - TFP_DRV_LOG(ERR, - "%s, %s was not cleaned up, %d outstanding\n", - tf_dir_2_str(dir), - tf_module_subtype_2_str(module, i), - residuals[i]); - } -} - /** * Performs a check of the passed in DB for any lingering elements. If * a resource type was found to not have been cleaned up by the caller @@ -357,11 +316,6 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db, *resv_size = found; } - tf_rm_log_residuals(rm_db->dir, - rm_db->module, - rm_db->num_entries, - residuals); - tfp_free((void *)residuals); *resv = local_resv; @@ -544,11 +498,6 @@ tf_rm_create_db(struct tf *tfp, &hcapi_items); if (hcapi_items == 0) { - TFP_DRV_LOG(ERR, - "%s: module:%s Empty RM DB create request\n", - tf_dir_2_str(parms->dir), - tf_module_2_str(parms->module)); - parms->rm_db = NULL; return -ENOMEM; } @@ -1296,7 +1245,13 @@ tf_rm_get_all_info(struct tf_rm_get_alloc_info_parms *parms, int size) struct tf_rm_alloc_info *info = parms->info; int i; - TF_CHECK_PARMS2(parms, parms->rm_db); + TF_CHECK_PARMS1(parms); + + /* No rm info available for this module type + */ + if (!parms->rm_db) + return -ENOMEM; + rm_db = (struct tf_rm_new_db *)parms->rm_db; TF_CHECK_PARMS1(rm_db->db); diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index 70844edb50..71ccb2e3e7 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -215,6 +215,16 @@ tf_session_create(struct tf *tfp, return 0; cleanup: + rc = tf_msg_session_close(tfp, + fw_session_id, + dev.ops->tf_dev_get_mailbox()); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "FW Session close failed, rc:%s\n", + strerror(-rc)); + } + tfp_free(tfp->session->core_data); tfp_free(tfp->session); tfp->session = NULL; @@ -479,6 +489,8 @@ tf_session_close_session(struct tf *tfp, struct tf_dev_info *tfd = NULL; struct tf_session_client_destroy_parms scdparms; uint16_t fid; + uint8_t fw_session_id = 1; + int mailbox = 0; TF_CHECK_PARMS2(tfp, parms); @@ -563,6 +575,16 @@ tf_session_close_session(struct tf *tfp, return rc; } + mailbox = tfd->ops->tf_dev_get_mailbox(); + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "Unable to lookup FW id, rc:%s\n", + strerror(-rc)); + return rc; + } + /* Unbind the device */ rc = tf_dev_unbind(tfp, tfd); if (rc) { @@ -572,7 +594,7 @@ tf_session_close_session(struct tf *tfp, strerror(-rc)); } - rc = tf_msg_session_close(tfp, tfs); + rc = tf_msg_session_close(tfp, fw_session_id, mailbox); if (rc) { /* Log error */ TFP_DRV_LOG(ERR, @@ -881,26 +903,26 @@ tf_session_get_db(struct tf *tfp, if (tfs->id_db_handle) *db_handle = tfs->id_db_handle; else - rc = -EINVAL; + rc = -ENOMEM; break; case TF_MODULE_TYPE_TABLE: if (tfs->tbl_db_handle) *db_handle = tfs->tbl_db_handle; else - rc = -EINVAL; + rc = -ENOMEM; break; case TF_MODULE_TYPE_TCAM: if (tfs->tcam_db_handle) *db_handle = tfs->tcam_db_handle; else - rc = -EINVAL; + rc = -ENOMEM; break; case TF_MODULE_TYPE_EM: if (tfs->em_db_handle) *db_handle = tfs->em_db_handle; else - rc = -EINVAL; + rc = -ENOMEM; break; default: rc = -EINVAL; diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 6842291adf..ced59130b2 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -270,6 +270,44 @@ tf_tbl_free(struct tf *tfp __rte_unused, parms->idx); return -EINVAL; } + + /* If this is counter table, clear the entry on free */ + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) { + uint8_t data[8] = { 0 }; + uint16_t hcapi_type = 0; + struct tf_rm_get_hcapi_parms hparms = { 0 }; + + /* Get the hcapi type */ + hparms.rm_db = tbl_db->tbl_db[parms->dir]; + hparms.subtype = parms->type; + hparms.hcapi_type = &hcapi_type; + rc = tf_rm_get_hcapi_type(&hparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Failed type lookup, type:%d, rc:%s\n", + tf_dir_2_str(parms->dir), + parms->type, + strerror(-rc)); + return rc; + } + /* Clear the counter + */ + rc = tf_msg_set_tbl_entry(tfp, + parms->dir, + hcapi_type, + sizeof(data), + data, + parms->idx); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Set failed, type:%d, rc:%s\n", + tf_dir_2_str(parms->dir), + parms->type, + strerror(-rc)); + return rc; + } + } + /* Free requested element */ fparms.rm_db = tbl_db->tbl_db[parms->dir]; fparms.subtype = parms->type; @@ -643,11 +681,11 @@ tf_tbl_get_resc_info(struct tf *tfp, return rc; rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); - if (rc) { - TFP_DRV_LOG(INFO, - "No resource allocated for table from session\n"); - return 0; - } + if (rc == -ENOMEM) + return 0; /* db doesn't exist */ + else if (rc) + return rc; /* error getting db */ + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; /* check if reserved resource for WC is multiple of num_slices */ @@ -655,6 +693,9 @@ tf_tbl_get_resc_info(struct tf *tfp, ainfo.rm_db = tbl_db->tbl_db[d]; dinfo = tbl[d].info; + if (!ainfo.rm_db) + continue; + ainfo.info = (struct tf_rm_alloc_info *)dinfo; ainfo.subtype = 0; rc = tf_rm_get_all_info(&ainfo, TF_TBL_TYPE_MAX); diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index d7e12e00ef..45206c5992 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -818,16 +818,20 @@ tf_tcam_get_resc_info(struct tf *tfp, TF_CHECK_PARMS2(tfp, tcam); rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); - if (rc) { - TFP_DRV_LOG(INFO, - "No resource allocated for tcam from session\n"); - return 0; - } + if (rc == -ENOMEM) + return 0; /* db doesn't exist */ + else if (rc) + return rc; /* error getting db */ + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { ainfo.rm_db = tcam_db->tcam_db[d]; + + if (!ainfo.rm_db) + continue; + dinfo = tcam[d].info; ainfo.info = (struct tf_rm_alloc_info *)dinfo; diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c index f0727cea80..5139b28537 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c @@ -842,20 +842,28 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused, return 0; } -/* Temporary builder defines pulled in here and renamed +/* Normally, device specific code wouldn't reside here, it belongs + * in a separate device specific function in tf_device_pxx.c. + * But this code is placed here as it is not a long term solution + * and we would like to have this code centrally located for easy + * removal */ -#define TF_TMP_MAX_FIELD_BITLEN 512 +#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4 12 +#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P4 4 +#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 24 +#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 8 +/* Temporary builder defines pulled in here and adjusted + * for max WC TCAM values + */ union tf_tmp_field_obj { - uint8_t bytes[(TF_TMP_MAX_FIELD_BITLEN + 7) / 8]; + uint32_t words[(TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 + 3) / 4]; + uint8_t bytes[TF_TCAM_SHARED_REMAP_SZ_BYTES_P58]; }; -#define TF_TMP_MAX_KEY_BITLEN 768 -#define TF_TMP_MAX_KEY_WORDLEN ((TF_TMP_MAX_KEY_BITLEN + 63) / 64) - union tf_tmp_key { - uint32_t words[(TF_TMP_MAX_KEY_BITLEN + 31) / 32]; - uint8_t bytes[(TF_TMP_MAX_KEY_BITLEN + 7) / 8]; + uint32_t words[(TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 + 3) / 4]; + uint8_t bytes[TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58]; }; /** p58 has an enable bit, p4 does not @@ -934,9 +942,10 @@ tf_tcam_shared_move_entry(struct tf *tfp, if (rc) { /* Log error */ TFP_DRV_LOG(ERR, - "%s: WC_TCAM_LOW phyid(%d) set failed, rc:%s", + "%s: WC_TCAM_LOW phyid(%d/0x%x) set failed, rc:%s", tf_dir_2_str(dir), sparms.idx, + sparms.idx, strerror(-rc)); return rc; } @@ -951,10 +960,11 @@ tf_tcam_shared_move_entry(struct tf *tfp, if (rc) { /* Log error */ TFP_DRV_LOG(ERR, - "%s: %s: phyid(%d) free failed, rc:%s\n", + "%s: %s: phyid(%d/0x%x) free failed, rc:%s\n", tf_dir_2_str(dir), tf_tcam_tbl_2_str(fparms.type), sphy_idx, + sphy_idx, strerror(-rc)); return rc; } @@ -1119,15 +1129,6 @@ int tf_tcam_shared_move(struct tf *tfp, return rc; } -/* Normally, device specific code wouldn't reside here, it belongs - * in a separate device specific function in tf_device_pxx.c. - * But this code is placed here as it is not a long term solution - * and we would like to have this code centrally located for easy - * removal - */ -#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4 12 -#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P4 4 - int tf_tcam_shared_move_p4(struct tf *tfp, struct tf_move_tcam_shared_entries_parms *parms) { @@ -1140,8 +1141,6 @@ int tf_tcam_shared_move_p4(struct tf *tfp, return rc; } -#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 24 -#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 8 int tf_tcam_shared_move_p58(struct tf *tfp, struct tf_move_tcam_shared_entries_parms *parms) From patchwork Sun May 30 08:58:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93572 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EDDDFA0524; Sun, 30 May 2021 11:03:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BDA640E46; Sun, 30 May 2021 11:01:10 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 8B2A941123 for ; Sun, 30 May 2021 11:01:06 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id EAC2C7DC0; Sun, 30 May 2021 02:01:04 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com EAC2C7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365266; bh=vwX/v+Ce3tfe/JFaBysj2Imim4Dg/s+j/7cp1a7sKSs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DGsOnfKxMV8eUGR+5ofd+nlVsPYOCvCxadYV7eiSWU78VjLANn3NM6cZUWUCHgZqW o+3L6VlM+ilA34OM1Cj5Q4U54Yv5a2Tb5PfIfAB0pHn92EV2qW+TZpyWzAWwx4wmU3 ECBRWyt9ja/Y91JejT1pCXyBUIe03dZUdxbk+ZMU= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:54 +0530 Message-Id: <20210530085929.29695-24-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 23/58] net/bnxt: cleanup of WC TCAM shared unbind X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith - clean up all allocated hi or lo pool tcam regions on close - message cleanup - remove unsupported multi-slice - find next free entry should start from 0 first time - update reserved resources so cli open session can come up Signed-off-by: Farah Smith Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_core/tf_tcam_shared.c | 333 ++++++++++++---------- 1 file changed, 179 insertions(+), 154 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c index 5139b28537..b96d9ca9dd 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c @@ -19,8 +19,6 @@ #include "tf_core.h" #include "tf_rm.h" -struct tf; - /** Shared WC TCAM pool identifiers */ enum tf_tcam_shared_wc_pool_id { @@ -288,6 +286,12 @@ tf_tcam_shared_bind(struct tf *tfp, if (rc) return rc; + if (num_slices > 1) { + TFP_DRV_LOG(ERR, + "Only single slice supported\n"); + return -EOPNOTSUPP; + } + tf_tcam_shared_create_db(&tcam_shared_wc); @@ -338,49 +342,135 @@ int tf_tcam_shared_unbind(struct tf *tfp) { int rc, dir; + struct tf_dev_info *dev; struct tf_session *tfs; void *tcam_shared_db_ptr = NULL; struct tf_tcam_shared_wc_pools *tcam_shared_wc; + enum tf_tcam_shared_wc_pool_id pool_id; + struct tf_tcam_free_parms parms; + struct bitalloc *pool; + uint16_t start; + int log_idx, phy_idx; + uint16_t hcapi_type; + struct tf_rm_alloc_info info; + int i, pool_cnt; TF_CHECK_PARMS1(tfp); - /* Perform normal unbind, this will write all the - * allocated TCAM entries in the shared session. - */ - rc = tf_tcam_unbind(tfp); - if (rc) - return rc; - /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); if (rc) return rc; - rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); + /* If not the shared session, call the normal + * tcam unbind and exit + */ + if (!tf_session_is_shared_session(tfs)) { + rc = tf_tcam_unbind(tfp); + return rc; + } + + /* We must be a shared session, get the database + */ + rc = tf_session_get_tcam_shared_db(tfp, + (void *)&tcam_shared_db_ptr); if (rc) { TFP_DRV_LOG(ERR, - "Failed to get tcam_shared_db from session, rc:%s\n", + "Failed to get tcam_shared_db, rc:%s\n", strerror(-rc)); return rc; } - tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; - /* If we are the shared session + tcam_shared_wc = + (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; + + + /* Get the device */ - if (tf_session_is_shared_session(tfs)) { - /* If there are WC TCAM entries allocated, free them + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + + /* If there are WC TCAM entries allocated, free them + */ + for (dir = 0; dir < TF_DIR_MAX; dir++) { + /* If the database is invalid, skip */ - for (dir = 0; dir < TF_DIR_MAX; dir++) { - tf_tcam_shared_free_wc_pool(dir, - TF_TCAM_SHARED_WC_POOL_HI, - tcam_shared_wc); + if (!tf_tcam_db_valid(tfp, dir)) + continue; + + rc = tf_tcam_shared_get_rm_info(tfp, + dir, + &hcapi_type, + &info); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM shared rm info get failed\n", + tf_dir_2_str(dir)); + return rc; + } + + for (pool_id = TF_TCAM_SHARED_WC_POOL_HI; + pool_id < TF_TCAM_SHARED_WC_POOL_MAX; + pool_id++) { + pool = tcam_shared_wc->db[dir][pool_id].pool; + start = tcam_shared_wc->db[dir][pool_id].info.start; + pool_cnt = ba_inuse_count(pool); + + if (pool_cnt) { + TFP_DRV_LOG(INFO, + "%s: %s: %d residuals found, freeing\n", + tf_dir_2_str(dir), + tf_pool_2_str(pool_id), + pool_cnt); + } + + log_idx = 0; + + for (i = 0; i < pool_cnt; i++) { + log_idx = ba_find_next_inuse(pool, log_idx); + + if (log_idx < 0) { + TFP_DRV_LOG(ERR, + "Expected a found %s entry %d\n", + tf_pool_2_str(pool_id), + i); + /* attempt normal unbind + */ + goto done; + } + phy_idx = start + log_idx; + + parms.type = TF_TCAM_TBL_TYPE_WC_TCAM; + parms.hcapi_type = hcapi_type; + parms.idx = phy_idx; + parms.dir = dir; + rc = tf_msg_tcam_entry_free(tfp, dev, &parms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: %s: %d free failed, rc:%s\n", + tf_dir_2_str(parms.dir), + tf_tcam_tbl_2_str(parms.type), + phy_idx, + strerror(-rc)); + return rc; + } + } + /* Free the pool once all the entries + * have been cleared + */ tf_tcam_shared_free_wc_pool(dir, - TF_TCAM_SHARED_WC_POOL_LO, + pool_id, tcam_shared_wc); } } - return 0; +done: + rc = tf_tcam_unbind(tfp); + return rc; } + /** * tf_tcam_shared_alloc */ @@ -388,13 +478,12 @@ int tf_tcam_shared_alloc(struct tf *tfp, struct tf_tcam_alloc_parms *parms) { - int rc, i; + int rc; struct tf_session *tfs; struct tf_dev_info *dev; int log_idx; struct bitalloc *pool; enum tf_tcam_shared_wc_pool_id id; - uint16_t num_slices; struct tf_tcam_shared_wc_pools *tcam_shared_wc; void *tcam_shared_db_ptr = NULL; @@ -444,32 +533,24 @@ tf_tcam_shared_alloc(struct tf *tfp, if (rc) return rc; - rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); - if (rc) - return rc; - pool = tcam_shared_wc->db[parms->dir][id].pool; - for (i = 0; i < num_slices; i++) { - /* - * priority 0: allocate from top of the tcam i.e. high - * priority !0: allocate index from bottom i.e lowest - */ - if (parms->priority) - log_idx = ba_alloc_reverse(pool); - else - log_idx = ba_alloc(pool); - if (log_idx == BA_FAIL) { - TFP_DRV_LOG(ERR, - "%s: Allocation failed, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(ENOMEM)); - return -ENOMEM; - } - /* return the index without the start of each row */ - if (i == 0) - parms->idx = log_idx; + /* + * priority 0: allocate from top of the tcam i.e. high + * priority !0: allocate index from bottom i.e lowest + */ + if (parms->priority) + log_idx = ba_alloc_reverse(pool); + else + log_idx = ba_alloc(pool); + if (log_idx == BA_FAIL) { + TFP_DRV_LOG(ERR, + "%s: Allocation failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(ENOMEM)); + return -ENOMEM; } + parms->idx = log_idx; return 0; } @@ -481,13 +562,11 @@ tf_tcam_shared_free(struct tf *tfp, struct tf_session *tfs; struct tf_dev_info *dev; int allocated = 0; - int i; uint16_t start; int phy_idx; struct bitalloc *pool; enum tf_tcam_shared_wc_pool_id id; struct tf_tcam_free_parms nparms; - uint16_t num_slices; uint16_t hcapi_type; struct tf_rm_alloc_info info; void *tcam_shared_db_ptr = NULL; @@ -540,10 +619,6 @@ tf_tcam_shared_free(struct tf *tfp, if (rc) return rc; - rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); - if (rc) - return rc; - rc = tf_tcam_shared_get_rm_info(tfp, parms->dir, &hcapi_type, @@ -558,13 +633,6 @@ tf_tcam_shared_free(struct tf *tfp, pool = tcam_shared_wc->db[parms->dir][id].pool; start = tcam_shared_wc->db[parms->dir][id].info.start; - if (parms->idx % num_slices) { - TFP_DRV_LOG(ERR, - "%s: TCAM reserved resource is not multiple of %d\n", - tf_dir_2_str(parms->dir), num_slices); - return -EINVAL; - } - phy_idx = parms->idx + start; allocated = ba_inuse(pool, parms->idx); @@ -575,16 +643,14 @@ tf_tcam_shared_free(struct tf *tfp, return -EINVAL; } - for (i = 0; i < num_slices; i++) { - rc = ba_free(pool, parms->idx + i); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Free failed, type:%s, idx:%d\n", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(parms->type), - parms->idx); - return rc; - } + rc = ba_free(pool, parms->idx); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Free failed, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tcam_tbl_2_str(parms->type), + parms->idx); + return rc; } /* Override HI/LO type with parent WC TCAM type */ @@ -616,7 +682,6 @@ tf_tcam_shared_set(struct tf *tfp __rte_unused, struct tf_dev_info *dev; int allocated = 0; int phy_idx, log_idx; - uint16_t num_slices; struct tf_tcam_set_parms nparms; struct bitalloc *pool; uint16_t start; @@ -685,16 +750,7 @@ tf_tcam_shared_set(struct tf *tfp __rte_unused, tf_dir_2_str(parms->dir), parms->type, log_idx); return -EINVAL; } - rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); - if (rc) - return rc; - if (parms->idx % num_slices) { - TFP_DRV_LOG(ERR, - "%s: TCAM reserved resource is not multiple of %d\n", - tf_dir_2_str(parms->dir), num_slices); - return -EINVAL; - } rc = tf_tcam_shared_get_rm_info(tfp, parms->dir, &hcapi_type, @@ -736,7 +792,6 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused, struct tf_dev_info *dev; int allocated = 0; int phy_idx, log_idx; - uint16_t num_slices; struct tf_tcam_get_parms nparms; struct bitalloc *pool; uint16_t start; @@ -794,16 +849,6 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused, pool = tcam_shared_wc->db[parms->dir][id].pool; start = tcam_shared_wc->db[parms->dir][id].info.start; - rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); - if (rc) - return rc; - - if (parms->idx % num_slices) { - TFP_DRV_LOG(ERR, - "%s: TCAM reserved resource is not multiple of %d\n", - tf_dir_2_str(parms->dir), num_slices); - return -EINVAL; - } log_idx = parms->idx; phy_idx = parms->idx + start; allocated = ba_inuse(pool, parms->idx); @@ -881,7 +926,6 @@ tf_tcam_shared_move_entry(struct tf *tfp, int dphy_idx, int key_sz_bytes, int remap_sz_bytes, - uint16_t num_slices, bool set_enable_bit) { int rc = 0; @@ -897,12 +941,6 @@ tf_tcam_shared_move_entry(struct tf *tfp, memset(&tcam_remap_obj, 0, sizeof(tcam_remap_obj)); memset(&gparms, 0, sizeof(gparms)); - if (num_slices > 1) { - TFP_DRV_LOG(ERR, - "Only single slice supported"); - return -EOPNOTSUPP; - } - gparms.hcapi_type = hcapi_type; gparms.dir = dir; gparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; @@ -917,7 +955,8 @@ tf_tcam_shared_move_entry(struct tf *tfp, if (rc) { /* Log error */ TFP_DRV_LOG(ERR, - "%s: WC_TCAM_HIGH: phyid(%d) get failed, rc:%s", + "%s: %s: phyid(%d) get failed, rc:%s\n", + tf_tcam_tbl_2_str(gparms.type), tf_dir_2_str(dir), gparms.idx, strerror(-rc)); @@ -942,7 +981,8 @@ tf_tcam_shared_move_entry(struct tf *tfp, if (rc) { /* Log error */ TFP_DRV_LOG(ERR, - "%s: WC_TCAM_LOW phyid(%d/0x%x) set failed, rc:%s", + "%s: %s phyid(%d/0x%x) set failed, rc:%s\n", + tf_tcam_tbl_2_str(sparms.type), tf_dir_2_str(dir), sparms.idx, sparms.idx, @@ -985,13 +1025,12 @@ int tf_tcam_shared_move(struct tf *tfp, struct tf_session *tfs; struct tf_dev_info *dev; int log_idx; - uint16_t num_slices; struct bitalloc *hi_pool, *lo_pool; uint16_t hi_start, lo_start; enum tf_tcam_shared_wc_pool_id hi_id, lo_id; uint16_t hcapi_type; struct tf_rm_alloc_info info; - int hi_cnt, i, j; + int hi_cnt, i; struct tf_tcam_shared_wc_pools *tcam_shared_wc; void *tcam_shared_db_ptr = NULL; @@ -1027,9 +1066,6 @@ int tf_tcam_shared_move(struct tf *tfp, /* TODO print amazing error */ return rc; } - rc = tf_tcam_shared_get_slices(tfp, dev, &num_slices); - if (rc) - return rc; rc = tf_tcam_shared_get_rm_info(tfp, parms->dir, @@ -1068,62 +1104,51 @@ int tf_tcam_shared_move(struct tf *tfp, /* Copy each valid entry to the same low pool logical offset */ + log_idx = 0; + for (i = 0; i < hi_cnt; i++) { - /* Go through all the slices + /* Find next free index starting from where we left off */ - for (j = 0; j < num_slices; j++) { - /* Find next free starting from where we left off - */ - log_idx = ba_find_next_inuse(hi_pool, i); + log_idx = ba_find_next_inuse(hi_pool, log_idx); + if (log_idx < 0) { + TFP_DRV_LOG(ERR, + "Expected a found %s entry %d\n", + tf_pool_2_str(hi_id), + i); + goto done; + } + /* The user should have never allocated from the low + * pool because the move only happens when switching + * from the high to the low pool + */ + if (ba_alloc_index(lo_pool, log_idx) < 0) { + TFP_DRV_LOG(ERR, + "Warning %s index %d already allocated\n", + tf_pool_2_str(lo_id), + i); - if (log_idx < 0) { - TFP_DRV_LOG(ERR, - "Expected a found %s entry %d\n", - tf_pool_2_str(hi_id), - i); - goto done; - } - /* The user should have never allocated from the low - * pool because the move only happens when switching - * from the high to the low pool + /* Since already allocated, continue with move */ - if (ba_alloc_index(lo_pool, log_idx) < 0) { - TFP_DRV_LOG(ERR, - "Cannot allocate %s index %d\n", - tf_pool_2_str(lo_id), - i); - goto done; - } + } - if (j == 0) { - rc = tf_tcam_shared_move_entry(tfp, dev, - hcapi_type, - parms->dir, - hi_start + log_idx, - lo_start + log_idx, - key_sz_bytes, - remap_sz_bytes, - num_slices, - set_enable_bit); - if (rc) { - TFP_DRV_LOG(ERR, - "Cannot allocate %s index %d\n", - tf_pool_2_str(hi_id), - i); - goto done; - } - ba_free(hi_pool, log_idx); - TFP_DRV_LOG(DEBUG, - "%s: TCAM shared move pool(%s) phyid(%d)\n", - tf_dir_2_str(parms->dir), - tf_pool_2_str(hi_id), - hi_start + log_idx); - TFP_DRV_LOG(DEBUG, - "to pool(%s) phyid(%d)\n", - tf_pool_2_str(lo_id), - lo_start + log_idx); - } + rc = tf_tcam_shared_move_entry(tfp, dev, + hcapi_type, + parms->dir, + hi_start + log_idx, + lo_start + log_idx, + key_sz_bytes, + remap_sz_bytes, + set_enable_bit); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Move error %s to %s index %d\n", + tf_dir_2_str(parms->dir), + tf_pool_2_str(hi_id), + tf_pool_2_str(lo_id), + i); + goto done; } + ba_free(hi_pool, log_idx); } done: return rc; From patchwork Sun May 30 08:58:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93573 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 36180A0524; Sun, 30 May 2021 11:04:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 52294411A3; Sun, 30 May 2021 11:01:11 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 45B3041199 for ; Sun, 30 May 2021 11:01:08 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id A57B47DC2; Sun, 30 May 2021 02:01:06 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com A57B47DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365267; bh=h1rbBpPaBLCE1RR6Mz6iecb+hRhdZiZF29IiSvw2zuI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NTa1ALwK1VDBGpG+xvByNsQiOlXIsRujx6dcWvE/Pq6fcIjwDuOpb5zloYwStQSau ByAIWoGBdALGjcxFWemd4sCwTTBlLg7XP1o3JYUIxvEGiX5TUiB7IpsKu630gNgxbN cu7JqjRVV1y0tI7t7MsNp+egU9Kkpl9WC7UjJ6qk= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:55 +0530 Message-Id: <20210530085929.29695-25-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 24/58] net/bnxt: add support for WC TCAM shared session X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding If the session shares WC TCAM entries with others, specify it in the session name by attach "-wc_tcam". Firmware will flush the shared WC TCAM entries if the last shared session using them is closed. Signed-off-by: Jay Ding Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_core/tf_msg.c | 46 +++++++++++++++++++++++---- drivers/net/bnxt/tf_core/tf_session.c | 5 +++ 2 files changed, 44 insertions(+), 7 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index fbd4b1d910..6717710dbd 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -58,6 +58,16 @@ static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) == */ #define TF_PCI_BUF_SIZE_MAX 88 +/** + * This is the length of shared session name "tf_share" + */ +#define TF_SHARED_SESSION_NAME_LEN 8 + +/** + * This is the length of tcam shared session name "tf_shared-wc_tcam" + */ +#define TF_TCAM_SHARED_SESSION_NAME_LEN 17 + /** * If data bigger than TF_PCI_BUF_SIZE_MAX then use DMA method */ @@ -126,13 +136,17 @@ tf_msg_session_open(struct bnxt *bp, struct hwrm_tf_session_open_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; int name_len; - char *name; + char *session_name; + char *tcam_session_name; /* Populate the request */ name_len = strnlen(ctrl_chan_name, TF_SESSION_NAME_MAX); - name = &ctrl_chan_name[name_len - strlen("tf_shared")]; - if (!strncmp(name, "tf_shared", strlen("tf_shared"))) - tfp_memcpy(&req.session_name, name, strlen("tf_share")); + session_name = &ctrl_chan_name[name_len - strlen("tf_shared")]; + tcam_session_name = &ctrl_chan_name[name_len - strlen("tf_shared-wc_tcam")]; + if (!strncmp(tcam_session_name, "tf_shared-wc_tcam", strlen("tf_shared-wc_tcam"))) + tfp_memcpy(&req.session_name, tcam_session_name, TF_TCAM_SHARED_SESSION_NAME_LEN); + else if (!strncmp(session_name, "tf_shared", strlen("tf_shared"))) + tfp_memcpy(&req.session_name, session_name, TF_SHARED_SESSION_NAME_LEN); else tfp_memcpy(&req.session_name, ctrl_chan_name, TF_SESSION_NAME_MAX); @@ -177,6 +191,9 @@ tf_msg_session_client_register(struct tf *tfp, struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; struct tf_dev_info *dev; + int name_len; + char *session_name; + char *tcam_session_name; /* Retrieve the device information */ rc = tf_session_get_device(tfs, &dev); @@ -197,9 +214,24 @@ tf_msg_session_client_register(struct tf *tfp, /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - tfp_memcpy(&req.session_client_name, - ctrl_channel_name, - TF_SESSION_NAME_MAX); + name_len = strnlen(ctrl_channel_name, TF_SESSION_NAME_MAX); + session_name = &ctrl_channel_name[name_len - strlen("tf_shared")]; + tcam_session_name = &ctrl_channel_name[name_len - + strlen("tf_shared-wc_tcam")]; + if (!strncmp(tcam_session_name, + "tf_shared-wc_tcam", + strlen("tf_shared-wc_tcam"))) + tfp_memcpy(&req.session_client_name, + tcam_session_name, + TF_TCAM_SHARED_SESSION_NAME_LEN); + else if (!strncmp(session_name, "tf_shared", strlen("tf_shared"))) + tfp_memcpy(&req.session_client_name, + session_name, + TF_SHARED_SESSION_NAME_LEN); + else + tfp_memcpy(&req.session_client_name, + ctrl_channel_name, + TF_SESSION_NAME_MAX); parms.tf_type = HWRM_TF_SESSION_REGISTER; parms.req_data = (uint32_t *)&req; diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index 71ccb2e3e7..90b65c59e6 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -188,6 +188,11 @@ tf_session_create(struct tf *tfp, if (!strncmp(name, "tf_shared", strlen("tf_shared"))) session->shared_session = true; + name = &parms->open_cfg->ctrl_chan_name[name_len - + strlen("tf_shared-wc_tcam")]; + if (!strncmp(name, "tf_shared-wc_tcam", strlen("tf_shared-wc_tcam"))) + session->shared_session = true; + if (session->shared_session && shared_session_creator) { session->shared_session_creator = true; parms->open_cfg->shared_session_creator = true; From patchwork Sun May 30 08:58:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93574 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5CF6DA0524; Sun, 30 May 2021 11:04:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5FE04411A9; Sun, 30 May 2021 11:01:12 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 00DF340DFD for ; Sun, 30 May 2021 11:01:10 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 601CC7DAF; Sun, 30 May 2021 02:01:08 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 601CC7DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365269; bh=SsHE0PtF9mbQIeas9gEG7guy5+1hcIhEoeFQi0YsdIk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KmXOY7PwDNRW5/ub8E1d1IOmiGzlA+XYgaodWRcIX4WtaCKjXNjoixKbHpMVxz4nr L3/w6U8SB04btp7q3dKQ76arZFm63d7443SfpfMSdDpnpZ+080v530jwW7DoXD+8gZ jK0gChZtKGD9Ni84xLS3B9cS/G9xRpvzLnoF/WeM= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Randy Schacher , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:56 +0530 Message-Id: <20210530085929.29695-26-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 25/58] net/bnxt: add API to clear hi/lo WC region X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith Provide TRUFLOW API to clear either the hi or the low region for ungraceful exit cleanup. Signed-off-by: Farah Smith Signed-off-by: Randy Schacher Signed-off-by: Venkat Duvvuru Reviewed-by: Jay Ding Reviewed-by: Peter Spreadborough --- drivers/net/bnxt/tf_core/tf_core.c | 51 ++++++++++ drivers/net/bnxt/tf_core/tf_core.h | 39 +++++++- drivers/net/bnxt/tf_core/tf_device.h | 19 +++- drivers/net/bnxt/tf_core/tf_device_p4.c | 4 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 1 + drivers/net/bnxt/tf_core/tf_tcam_shared.c | 111 +++++++++++++++++++++- drivers/net/bnxt/tf_core/tf_tcam_shared.h | 21 ++++ drivers/net/bnxt/tf_core/tf_util.h | 1 - 8 files changed, 235 insertions(+), 12 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 0fbbd40252..97e6165e92 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -968,6 +968,57 @@ tf_move_tcam_shared_entries(struct tf *tfp, return 0; } + +int +tf_clear_tcam_shared_entries(struct tf *tfp, + struct tf_clear_tcam_shared_entries_parms *parms) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + if (dev->ops->tf_dev_clear_tcam == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_clear_tcam(tfp, parms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM shared entries clear failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return 0; +} #endif /* TF_TCAM_SHARED */ int diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 44c30fa904..0b06bb2bb5 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -233,7 +233,7 @@ enum tf_identifier_type { */ TF_IDENT_TYPE_EM_PROF, /** - * TH + * (Future) * The L2 func is included in the ILT result and from recycling to * enable virtualization of further lookups. */ @@ -1244,6 +1244,8 @@ int tf_free_tbl_scope(struct tf *tfp, * #ifdef TF_TCAM_SHARED * @ref tf_move_tcam_shared_entries + * + * @ref tf_clear_tcam_shared_entries #endif */ @@ -1580,6 +1582,37 @@ struct tf_move_tcam_shared_entries_parms { int tf_move_tcam_shared_entries(struct tf *tfp, struct tf_move_tcam_shared_entries_parms *parms); +/** + * tf_clear_tcam_shared_entries parameter definition + */ +struct tf_clear_tcam_shared_entries_parms { + /** + * [in] receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] TCAM table type + */ + enum tf_tcam_tbl_type tcam_tbl_type; +}; + +/** + * Clear TCAM shared entries pool + * + * This API only affects the following TCAM pools within a shared session: + * + * TF_TCAM_TBL_TYPE_WC_TCAM_HIGH + * TF_TCAM_TBL_TYPE_WC_TCAM_LOW + * + * When called, the indicated WC TCAM high or low pool will be cleared. + * + * This API is not supported on a non-shared session. + * + * Returns success or failure code. + */ +int tf_clear_tcam_shared_entries(struct tf *tfp, + struct tf_clear_tcam_shared_entries_parms *parms); + #endif /* TF_TCAM_SHARED */ /** * @page table Table Access @@ -2108,7 +2141,7 @@ struct tf_move_em_entry_parms { uint64_t flow_handle; }; /** - * tf_search_em_entry parameter definition + * tf_search_em_entry parameter definition (Future) */ struct tf_search_em_entry_parms { /** @@ -2211,7 +2244,7 @@ int tf_delete_em_entry(struct tf *tfp, struct tf_delete_em_entry_parms *parms); /** - * search em hash entry table memory + * search em hash entry table memory (Future) * * Internal: diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 1893f630e7..da3f541685 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -595,7 +595,24 @@ struct tf_dev_ops { * -EINVAL - Error */ int (*tf_dev_move_tcam)(struct tf *tfp, - struct tf_move_tcam_shared_entries_parms *parms); + struct tf_move_tcam_shared_entries_parms *parms); + + /** + * Move TCAM shared entries + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to parameters + * + * returns: + * 0 - Success + * -EINVAL - Error + */ + int (*tf_dev_clear_tcam)(struct tf *tfp, + struct tf_clear_tcam_shared_entries_parms *parms); + #endif /* TF_TCAM_SHARED */ /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 28a6e41906..c340098cde 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -251,9 +251,6 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_alloc_search_tcam = NULL, .tf_dev_set_tcam = NULL, .tf_dev_get_tcam = NULL, -#ifdef TF_TCAM_SHARED - .tf_dev_move_tcam = NULL, -#endif /* TF_TCAM_SHARED */ .tf_dev_get_tcam_resc_info = NULL, .tf_dev_insert_int_em_entry = NULL, .tf_dev_delete_int_em_entry = NULL, @@ -301,6 +298,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_set_tcam = tf_tcam_shared_set, .tf_dev_get_tcam = tf_tcam_shared_get, .tf_dev_move_tcam = tf_tcam_shared_move_p4, + .tf_dev_clear_tcam = tf_tcam_shared_clear, #else /* !TF_TCAM_SHARED */ .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index bd6813beef..77a884f645 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -342,6 +342,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_set_tcam = tf_tcam_shared_set, .tf_dev_get_tcam = tf_tcam_shared_get, .tf_dev_move_tcam = tf_tcam_shared_move_p58, + .tf_dev_clear_tcam = tf_tcam_shared_clear, #else /* !TF_TCAM_SHARED */ .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c index b96d9ca9dd..c1c94829d7 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c @@ -1154,8 +1154,9 @@ int tf_tcam_shared_move(struct tf *tfp, return rc; } -int tf_tcam_shared_move_p4(struct tf *tfp, - struct tf_move_tcam_shared_entries_parms *parms) +int +tf_tcam_shared_move_p4(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms) { int rc = 0; rc = tf_tcam_shared_move(tfp, @@ -1167,8 +1168,9 @@ int tf_tcam_shared_move_p4(struct tf *tfp, } -int tf_tcam_shared_move_p58(struct tf *tfp, - struct tf_move_tcam_shared_entries_parms *parms) +int +tf_tcam_shared_move_p58(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms) { int rc = 0; rc = tf_tcam_shared_move(tfp, @@ -1178,3 +1180,104 @@ int tf_tcam_shared_move_p58(struct tf *tfp, true); /* set enable bit */ return rc; } + +int +tf_tcam_shared_clear(struct tf *tfp, + struct tf_clear_tcam_shared_entries_parms *parms) +{ + int rc = 0; + struct tf_session *tfs; + struct tf_dev_info *dev; + uint16_t start; + int phy_idx; + enum tf_tcam_shared_wc_pool_id id; + struct tf_tcam_free_parms nparms; + uint16_t hcapi_type; + struct tf_rm_alloc_info info; + void *tcam_shared_db_ptr = NULL; + struct tf_tcam_shared_wc_pools *tcam_shared_wc; + int i, cnt; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + if (!tf_session_is_shared_session(tfs) || + (parms->tcam_tbl_type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && + parms->tcam_tbl_type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) + return -EOPNOTSUPP; + + if (!tf_tcam_db_valid(tfp, parms->dir)) { + TFP_DRV_LOG(ERR, + "%s: tcam shared pool doesn't exist\n", + tf_dir_2_str(parms->dir)); + return -ENOMEM; + } + + rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get tcam_shared_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; + + + if (parms->tcam_tbl_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) + id = TF_TCAM_SHARED_WC_POOL_HI; + else + id = TF_TCAM_SHARED_WC_POOL_LO; + + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + rc = tf_tcam_shared_get_rm_info(tfp, + parms->dir, + &hcapi_type, + &info); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: TCAM rm info get failed\n", + tf_dir_2_str(parms->dir)); + return rc; + } + + start = tcam_shared_wc->db[parms->dir][id].info.start; + cnt = tcam_shared_wc->db[parms->dir][id].info.stride; + + /* Override HI/LO type with parent WC TCAM type */ + nparms.dir = parms->dir; + nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; + nparms.hcapi_type = hcapi_type; + + for (i = 0; i < cnt; i++) { + phy_idx = start + i; + nparms.idx = phy_idx; + + /* Clear entry */ + rc = tf_msg_tcam_entry_free(tfp, dev, &nparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "%s: %s: log%d free failed, rc:%s\n", + tf_dir_2_str(nparms.dir), + tf_tcam_tbl_2_str(nparms.type), + phy_idx, + strerror(-rc)); + return rc; + } + } + + TFP_DRV_LOG(DEBUG, + "%s: TCAM shared clear pool(%s)\n", + tf_dir_2_str(nparms.dir), + tf_pool_2_str(id)); + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h index 5588125470..020763af6b 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.h +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h @@ -24,6 +24,11 @@ * * @ref tf_tcam_shared_get * + * @ref tf_tcam_shared_move_p4 + * + * @ref tf_tcam_shared_move_p58 + * + * @ref tf_tcam_shared_clear */ /** @@ -159,4 +164,20 @@ int tf_tcam_shared_move_p4(struct tf *tfp, int tf_tcam_shared_move_p58(struct tf *tfp, struct tf_move_tcam_shared_entries_parms *parms); +/** + * Allocates and clears the entire WC_TCAM_HI or WC_TCAM_LO shared pools + * + * [in] tfp + * Pointer to the truflow handle + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tcam_shared_clear(struct tf *tfp, + struct tf_clear_tcam_shared_entries_parms *parms); + #endif /* _TF_TCAM_SHARED_H */ diff --git a/drivers/net/bnxt/tf_core/tf_util.h b/drivers/net/bnxt/tf_core/tf_util.h index 4caf50349d..854c51931a 100644 --- a/drivers/net/bnxt/tf_core/tf_util.h +++ b/drivers/net/bnxt/tf_core/tf_util.h @@ -7,7 +7,6 @@ #define _TF_UTIL_H_ #include "tf_core.h" -#include "tf_device.h" #define TF_BITS2BYTES(x) (((x) + 7) >> 3) #define TF_BITS2BYTES_WORD_ALIGN(x) ((((x) + 31) >> 5) * 4) From patchwork Sun May 30 08:58:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93575 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 567E0A0524; Sun, 30 May 2021 11:04:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E2209411B3; Sun, 30 May 2021 11:01:13 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 492B941182 for ; Sun, 30 May 2021 11:01:11 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 1A8917DC0; Sun, 30 May 2021 02:01:09 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 1A8917DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365270; bh=mEkhBn1frOpWb3HnSczl9m7cO6Eno/itFvl+53DmQ40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T+GFk3MMq7yAwIcut7I2eXAcsvNCytDPza5Nzl+iwdO9Btc50XZo1tq6yVFkAorLr iQPT2OLyU+agOers+jVq7Lv4A3JtxL+scA/smpvg+zP8TuRiuwBSDCD8suldT4eVVj hdo4c1oHYHFy9R2lHAsYL0KWrw6pxNfZ5Rs5Hlzg= From: Venkat Duvvuru To: dev@dpdk.org Cc: Venkat Duvvuru Date: Sun, 30 May 2021 14:28:57 +0530 Message-Id: <20210530085929.29695-27-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 26/58] net/bnxt: check FW capability to support TRUFLOW X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, a devarg (host-based-truflow) is passed while launching the app to enable truflow feature. However, this mechanism doesn't give a seamless experience when flow offloads has to work with firmware that doesn't/does support truflow feature. Also, it's likely that customers may not want to use devarg to enable flow offloads. This patch fixes it by checking for truflow feature support in device's capabilities and configurations field of the hwrm_ver_get's response. Signed-off-by: Venkat Duvvuru Reviewed-by: Kalesh Anakkur Purayil Reviewed-by: Somnath Kotur --- doc/guides/nics/bnxt.rst | 3 +- drivers/net/bnxt/bnxt.h | 10 +++--- drivers/net/bnxt/bnxt_ethdev.c | 56 ---------------------------------- drivers/net/bnxt/bnxt_hwrm.c | 7 ++++- 4 files changed, 12 insertions(+), 64 deletions(-) diff --git a/doc/guides/nics/bnxt.rst b/doc/guides/nics/bnxt.rst index 0fb2032447..fef8a7fac9 100644 --- a/doc/guides/nics/bnxt.rst +++ b/doc/guides/nics/bnxt.rst @@ -658,8 +658,7 @@ which currently supports basic packet classification in the receive path. The feature uses a newly implemented control-plane firmware interface which optimizes flow insertions and deletions. -This is a tech preview feature, and is disabled by default. It can be enabled -using bnxt devargs. For ex: "-a 0000:0d:00.0,host-based-truflow=1”. +This is a tech preview feature. This feature is currently supported on Whitney+ and Stingray devices. diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index db67bff127..882f577848 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -645,10 +645,9 @@ struct bnxt { #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) #define BNXT_FLAG_DFLT_MAC_SET BIT(26) -#define BNXT_FLAG_TRUFLOW_EN BIT(27) -#define BNXT_FLAG_GFID_ENABLE BIT(28) -#define BNXT_FLAG_RFS_NEEDS_VNIC BIT(29) -#define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(30) +#define BNXT_FLAG_GFID_ENABLE BIT(27) +#define BNXT_FLAG_RFS_NEEDS_VNIC BIT(28) +#define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(29) #define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) @@ -664,7 +663,6 @@ struct bnxt { #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5(bp)) #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) -#define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN) #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) uint32_t flags2; @@ -686,6 +684,8 @@ struct bnxt { #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) #define BNXT_FW_CAP_LINK_ADMIN BIT(7) +#define BNXT_FW_CAP_TRUFLOW_EN BIT(8) +#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) pthread_mutex_t flow_lock; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 3778e28cca..a0e0ba5884 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -87,7 +87,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { { .vendor_id = 0, /* sentinel */ }, }; -#define BNXT_DEVARG_TRUFLOW "host-based-truflow" #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" #define BNXT_DEVARG_REPRESENTOR "representor" @@ -100,7 +99,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, - BNXT_DEVARG_TRUFLOW, BNXT_DEVARG_FLOW_XSTAT, BNXT_DEVARG_MAX_NUM_KFLOWS, BNXT_DEVARG_REP_BASED_PF, @@ -112,12 +110,6 @@ static const char *const bnxt_dev_args[] = { NULL }; -/* - * truflow == false to disable the feature - * truflow == true to enable the feature - */ -#define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) - /* * flow_xstat == false to disable the feature * flow_xstat == true to enable the feature @@ -5182,45 +5174,6 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) return 0; } -static int -bnxt_parse_devarg_truflow(__rte_unused const char *key, - const char *value, void *opaque_arg) -{ - struct bnxt *bp = opaque_arg; - unsigned long truflow; - char *end = NULL; - - if (!value || !opaque_arg) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to truflow devargs.\n"); - return -EINVAL; - } - - truflow = strtoul(value, &end, 10); - if (end == NULL || *end != '\0' || - (truflow == ULONG_MAX && errno == ERANGE)) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to truflow devargs.\n"); - return -EINVAL; - } - - if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { - PMD_DRV_LOG(ERR, - "Invalid value passed to truflow devargs.\n"); - return -EINVAL; - } - - if (truflow) { - bp->flags |= BNXT_FLAG_TRUFLOW_EN; - PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); - } else { - bp->flags &= ~BNXT_FLAG_TRUFLOW_EN; - PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n"); - } - - return 0; -} - static int bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -5528,15 +5481,6 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) if (kvlist == NULL) return -EINVAL; - /* - * Handler for "truflow" devarg. - * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1" - */ - ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, - bnxt_parse_devarg_truflow, bp); - if (ret) - goto err; - /* * Handler for "flow_xstat" devarg. * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 931ecea77c..4505321778 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -1345,6 +1345,12 @@ int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout) bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS; } + if (dev_caps_cfg & + HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) { + PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n"); + bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN; + } + error: HWRM_UNLOCK(); return rc; @@ -4561,7 +4567,6 @@ int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index) return rc; } - int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type, uint16_t dir_ordinal, uint16_t dir_ext, uint16_t dir_attr, const uint8_t *data, From patchwork Sun May 30 08:58:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93691 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 246BDA0524; Tue, 1 Jun 2021 09:39:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 988B7410E2; Tue, 1 Jun 2021 09:39:56 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id B3AFA411B0 for ; Sun, 30 May 2021 11:01:13 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 678437DAF; Sun, 30 May 2021 02:01:11 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 678437DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365273; bh=xmro2rObpnoiTYXI6DWtI4ijwl5Y1N0mP3OAm27qLzI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LKSdU8h8uHRT1RsbPACYxgBfYrLQwGWXDd+2KqTQE6VMhI33D4xl/HOxIguS7owDf TrCxAbXzkKpR2BJcF/HatJ3Ee2dcLQjzmsXZAdBQqIHTIeigvBabOPKpbGvfOsNlUW 3NqpwT1DVCPCaiNGLqVKQqVmFuaYrUvUzIc6cLSE= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:58 +0530 Message-Id: <20210530085929.29695-28-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:53 +0200 Subject: [dpdk-dev] [PATCH 27/58] net/bnxt: add support for generic table processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Added support for generic table processing, this feature shall enable support for shared resource like mirror and tcam cache tables. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Ajit Kumar Khaparde Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/meson.build | 1 + drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 311 ++ drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 142 + drivers/net/bnxt/tf_ulp/ulp_mapper.c | 643 ++- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 15 +- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 65 +- .../tf_ulp/ulp_template_db_stingray_class.c | 3509 +++++++++++++++- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 43 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 3511 ++++++++++++++++- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 14 + drivers/net/bnxt/tf_ulp/ulp_utils.c | 112 +- drivers/net/bnxt/tf_ulp/ulp_utils.h | 68 + 12 files changed, 7670 insertions(+), 764 deletions(-) create mode 100644 drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build index 98cbdf3177..611d7ab58e 100644 --- a/drivers/net/bnxt/tf_ulp/meson.build +++ b/drivers/net/bnxt/tf_ulp/meson.build @@ -22,6 +22,7 @@ sources += files( 'ulp_def_rules.c', 'ulp_fc_mgr.c', 'ulp_tun.c', + 'ulp_gen_tbl.c', 'ulp_template_db_wh_plus_act.c', 'ulp_template_db_wh_plus_class.c', 'ulp_template_db_stingray_act.c', diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c new file mode 100644 index 0000000000..0edbe77a96 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2020 Broadcom + * All rights reserved. + */ + +#include +#include +#include "ulp_mapper.h" +#include "ulp_flow_db.h" + +/* Retrieve the generic table initialization parameters for the tbl_idx */ +static struct bnxt_ulp_generic_tbl_params* +ulp_mapper_gen_tbl_params_get(uint32_t tbl_idx) +{ + if (tbl_idx >= BNXT_ULP_GEN_TBL_MAX_SZ) + return NULL; + + return &ulp_generic_tbl_params[tbl_idx]; +} + +/* + * Initialize the generic table list + * + * mapper_data [in] Pointer to the mapper data and the generic table is + * part of it + * + * returns 0 on success + */ +int32_t +ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data) +{ + struct bnxt_ulp_generic_tbl_params *tbl; + struct ulp_mapper_gen_tbl_list *entry; + uint32_t idx, size; + + /* Allocate the generic tables. */ + for (idx = 0; idx < BNXT_ULP_GEN_TBL_MAX_SZ; idx++) { + tbl = ulp_mapper_gen_tbl_params_get(idx); + if (!tbl) { + BNXT_TF_DBG(ERR, "Failed to get gen table parms %d\n", + idx); + return -EINVAL; + } + entry = &mapper_data->gen_tbl_list[idx]; + if (tbl->result_num_entries != 0) { + /* add 4 bytes for reference count */ + entry->mem_data_size = (tbl->result_num_entries + 1) * + (tbl->result_byte_size + sizeof(uint32_t)); + + /* allocate the big chunk of memory */ + entry->mem_data = rte_zmalloc("ulp mapper gen tbl", + entry->mem_data_size, 0); + if (!entry->mem_data) { + BNXT_TF_DBG(ERR, + "Failed to allocate gen table %d\n", + idx); + return -ENOMEM; + } + /* Populate the generic table container */ + entry->container.num_elem = tbl->result_num_entries; + entry->container.byte_data_size = tbl->result_byte_size; + entry->container.ref_count = + (uint32_t *)entry->mem_data; + size = sizeof(uint32_t) * (tbl->result_num_entries + 1); + entry->container.byte_data = &entry->mem_data[size]; + entry->container.byte_order = tbl->result_byte_order; + } + } + /* success */ + return 0; +} + +/* + * Free the generic table list + * + * mapper_data [in] Pointer to the mapper data and the generic table is + * part of it + * + * returns 0 on success + */ +int32_t +ulp_mapper_generic_tbl_list_deinit(struct bnxt_ulp_mapper_data *mapper_data) +{ + struct ulp_mapper_gen_tbl_list *tbl_list; + uint32_t idx; + + /* iterate the generic table. */ + for (idx = 0; idx < BNXT_ULP_GEN_TBL_MAX_SZ; idx++) { + tbl_list = &mapper_data->gen_tbl_list[idx]; + if (tbl_list->mem_data) { + rte_free(tbl_list->mem_data); + tbl_list->mem_data = NULL; + } + } + /* success */ + return 0; +} + +/* + * Get the generic table list entry + * + * ulp_ctxt [in] - Ptr to ulp_context + * tbl_idx [in] - Table index to the generic table list + * key [in] - Key index to the table + * entry [out] - output will include the entry if found + * + * returns 0 on success. + */ +int32_t +ulp_mapper_gen_tbl_entry_get(struct bnxt_ulp_context *ulp, + uint32_t tbl_idx, + uint32_t key, + struct ulp_mapper_gen_tbl_entry *entry) +{ + struct bnxt_ulp_mapper_data *mapper_data; + struct ulp_mapper_gen_tbl_list *tbl_list; + + mapper_data = bnxt_ulp_cntxt_ptr2_mapper_data_get(ulp); + if (!mapper_data || tbl_idx >= BNXT_ULP_GEN_TBL_MAX_SZ || + !entry) { + BNXT_TF_DBG(ERR, "invalid arguments %x:%x\n", tbl_idx, key); + return -EINVAL; + } + /* populate the output and return the values */ + tbl_list = &mapper_data->gen_tbl_list[tbl_idx]; + if (key > tbl_list->container.num_elem) { + BNXT_TF_DBG(ERR, "invalid key %x:%x\n", key, + tbl_list->container.num_elem); + return -EINVAL; + } + entry->ref_count = &tbl_list->container.ref_count[key]; + entry->byte_data_size = tbl_list->container.byte_data_size; + entry->byte_data = &tbl_list->container.byte_data[key * + entry->byte_data_size]; + entry->byte_order = tbl_list->container.byte_order; + return 0; +} + +/* + * utility function to calculate the table idx + * + * res_sub_type [in] - Resource sub type + * dir [in] - Direction + * + * returns None + */ +int32_t +ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir) +{ + int32_t tbl_idx; + + /* Validate for direction */ + if (dir >= TF_DIR_MAX) { + BNXT_TF_DBG(ERR, "invalid argument %x\n", dir); + return -EINVAL; + } + tbl_idx = (res_sub_type << 1) | (dir & 0x1); + if (tbl_idx >= BNXT_ULP_GEN_TBL_MAX_SZ) { + BNXT_TF_DBG(ERR, "invalid table index %x\n", tbl_idx); + return -EINVAL; + } + return tbl_idx; +} + +/* + * Set the data in the generic table entry + * + * entry [in] - generic table entry + * offset [in] - The offset in bits where the data has to be set + * len [in] - The length of the data in bits to be set + * data [in] - pointer to the data to be used for setting the value. + * + * returns 0 on success + */ +int32_t +ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, + uint32_t offset, uint32_t len, uint8_t *data) +{ + /* validate the null arguments */ + if (!entry || !data) { + BNXT_TF_DBG(ERR, "invalid argument\n"); + return -EINVAL; + } + + /* check the size of the buffer for validation */ + if ((offset + len) > ULP_BYTE_2_BITS(entry->byte_data_size)) { + BNXT_TF_DBG(ERR, "invalid offset or length %x:%x:%x\n", + offset, len, entry->byte_data_size); + return -EINVAL; + } + + if (entry->byte_order == BNXT_ULP_BYTE_ORDER_LE) { + if (ulp_bs_push_lsb(entry->byte_data, offset, len, data) != + len) { + BNXT_TF_DBG(ERR, "write failed offset = %x, len =%x\n", + offset, len); + return -EIO; + } + } else { + if (ulp_bs_push_msb(entry->byte_data, offset, len, data) != + len) { + BNXT_TF_DBG(ERR, "write failed offset = %x, len =%x\n", + offset, len); + return -EIO; + } + } + return 0; +} + +/* + * Get the data in the generic table entry + * + * entry [in] - generic table entry + * offset [in] - The offset in bits where the data has to get + * len [in] - The length of the data in bits to be get + * data [out] - pointer to the data to be used for setting the value. + * data_size [in] - The size of data in bytes + * + * returns 0 on success + */ +int32_t +ulp_mapper_gen_tbl_entry_data_get(struct ulp_mapper_gen_tbl_entry *entry, + uint32_t offset, uint32_t len, uint8_t *data, + uint32_t data_size) +{ + /* validate the null arguments */ + if (!entry || !data) { + BNXT_TF_DBG(ERR, "invalid argument\n"); + return -EINVAL; + } + + /* check the size of the buffer for validation */ + if ((offset + len) > ULP_BYTE_2_BITS(entry->byte_data_size) || + len > ULP_BYTE_2_BITS(data_size)) { + BNXT_TF_DBG(ERR, "invalid offset or length %x:%x:%x\n", + offset, len, entry->byte_data_size); + return -EINVAL; + } + if (entry->byte_order == BNXT_ULP_BYTE_ORDER_LE) + ulp_bs_pull_lsb(entry->byte_data, data, data_size, offset, len); + else + ulp_bs_pull_msb(entry->byte_data, data, offset, len); + + return 0; +} + +/* + * Free the generic table list entry + * + * ulp_ctx [in] - Pointer to the ulp context + * res [in] - Pointer to flow db resource entry + * + * returns 0 on success + */ +int32_t +ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, + struct ulp_flow_db_res_params *res) +{ + struct ulp_mapper_gen_tbl_entry entry; + int32_t tbl_idx; + uint32_t fid; + + /* Extract the resource sub type and direction */ + tbl_idx = ulp_mapper_gen_tbl_idx_calculate(res->resource_sub_type, + res->direction); + if (tbl_idx < 0) { + BNXT_TF_DBG(ERR, "invalid argument %x:%x\n", + res->resource_sub_type, res->direction); + return -EINVAL; + } + + /* Get the generic table entry*/ + if (ulp_mapper_gen_tbl_entry_get(ulp_ctx, tbl_idx, res->resource_hndl, + &entry)) { + BNXT_TF_DBG(ERR, "Gen tbl entry get failed %x:%" PRIX64 "\n", + tbl_idx, res->resource_hndl); + return -EINVAL; + } + + /* Decrement the reference count */ + if (!ULP_GEN_TBL_REF_CNT(&entry)) { + BNXT_TF_DBG(ERR, "generic table corrupt %x:%" PRIX64 "\n", + tbl_idx, res->resource_hndl); + return -EINVAL; + } + ULP_GEN_TBL_REF_CNT_DEC(&entry); + + /* retain the details since there are other users */ + if (ULP_GEN_TBL_REF_CNT(&entry)) + return 0; + + /* Delete the generic table entry. First extract the fid */ + if (ulp_mapper_gen_tbl_entry_data_get(&entry, ULP_GEN_TBL_FID_OFFSET, + ULP_GEN_TBL_FID_SIZE_BITS, + (uint8_t *)&fid, + sizeof(fid))) { + BNXT_TF_DBG(ERR, "Unable to get fid %x:%" PRIX64 "\n", + tbl_idx, res->resource_hndl); + return -EINVAL; + } + + /* Destroy the flow associated with the shared flow id */ + if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, + fid)) + BNXT_TF_DBG(ERR, "Error in deleting shared flow id %x\n", fid); + + /* clear the byte data of the generic table entry */ + memset(entry.byte_data, 0, entry.byte_data_size); + + return 0; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h new file mode 100644 index 0000000000..c8a1112af4 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2021 Broadcom + * All rights reserved. + */ + +#ifndef _ULP_GEN_TBL_H_ +#define _ULP_GEN_TBL_H_ + +/* Macros for reference count manipulation */ +#define ULP_GEN_TBL_REF_CNT_INC(entry) {*(entry)->ref_count += 1; } +#define ULP_GEN_TBL_REF_CNT_DEC(entry) {*(entry)->ref_count -= 1; } +#define ULP_GEN_TBL_REF_CNT(entry) (*(entry)->ref_count) + +#define ULP_GEN_TBL_FID_OFFSET 0 +#define ULP_GEN_TBL_FID_SIZE_BITS 32 + +/* Structure to pass the generic table values across APIs */ +struct ulp_mapper_gen_tbl_entry { + uint32_t *ref_count; + uint32_t byte_data_size; + uint8_t *byte_data; + enum bnxt_ulp_byte_order byte_order; +}; + +/* + * Structure to store the generic tbl container + * The ref count and byte data contain list of "num_elem" elements. + * The size of each entry in byte_data is of size byte_data_size. + */ +struct ulp_mapper_gen_tbl_cont { + uint32_t num_elem; + uint32_t byte_data_size; + enum bnxt_ulp_byte_order byte_order; + /* Reference count to track number of users*/ + uint32_t *ref_count; + /* First 4 bytes is either tcam_idx or fid and rest are identities */ + uint8_t *byte_data; +}; + +/* Structure to store the generic tbl container */ +struct ulp_mapper_gen_tbl_list { + struct ulp_mapper_gen_tbl_cont container; + uint32_t mem_data_size; + uint8_t *mem_data; +}; + +/* Forward declaration */ +struct bnxt_ulp_mapper_data; +struct ulp_flow_db_res_params; + +/* + * Initialize the generic table list + * + * mapper_data [in] Pointer to the mapper data and the generic table is + * part of it + * + * returns 0 on success + */ +int32_t +ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data); + +/* + * Free the generic table list + * + * mapper_data [in] Pointer to the mapper data and the generic table is + * part of it + * + * returns 0 on success + */ +int32_t +ulp_mapper_generic_tbl_list_deinit(struct bnxt_ulp_mapper_data *mapper_data); + +/* + * Get the generic table list entry + * + * ulp_ctxt [in] - Ptr to ulp_context + * tbl_idx [in] - Table index to the generic table list + * key [in] - Key index to the table + * entry [out] - output will include the entry if found + * + * returns 0 on success. + */ +int32_t +ulp_mapper_gen_tbl_entry_get(struct bnxt_ulp_context *ulp, + uint32_t tbl_idx, + uint32_t key, + struct ulp_mapper_gen_tbl_entry *entry); + +/* + * utility function to calculate the table idx + * + * res_sub_type [in] - Resource sub type + * dir [in] - direction + * + * returns None + */ +int32_t +ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir); + +/* + * Set the data in the generic table entry + * + * entry [in] - generic table entry + * offset [in] - The offset in bits where the data has to be set + * len [in] - The length of the data in bits to be set + * data [in] - pointer to the data to be used for setting the value. + * + * returns 0 on success + */ +int32_t +ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, + uint32_t offset, uint32_t len, uint8_t *data); + +/* + * Get the data in the generic table entry + * + * entry [in] - generic table entry + * offset [in] - The offset in bits where the data has to get + * len [in] - The length of the data in bits to be get + * data [out] - pointer to the data to be used for setting the value. + * data_size [in] - The size of data in bytes + * + * returns 0 on success + */ +int32_t +ulp_mapper_gen_tbl_entry_data_get(struct ulp_mapper_gen_tbl_entry *entry, + uint32_t offset, uint32_t len, uint8_t *data, + uint32_t data_size); + +/* + * Free the generic table list entry + * + * ulp_ctx [in] - Pointer to the ulp context + * res [in] - Pointer to flow db resource entry + * + * returns 0 on success + */ +int32_t +ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, + struct ulp_flow_db_res_params *res); + +#endif /* _ULP_EN_TBL_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 4e06ae9ca1..2bb8d08699 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -102,7 +102,7 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx, rc = tf_alloc_identifier(tfp, &iparms); if (rc) { BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n", - (iparms.dir == TF_DIR_RX) ? "RX" : "TX", + tf_dir_2_str(iparms.dir), iparms.ident_type); return rc; } @@ -113,7 +113,7 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx, rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval); if (rc) { BNXT_TF_DBG(ERR, "Failed to write to global resource id\n"); - /* Free the identifier when update failed */ + /* Free the identifer when update failed */ fparms.dir = iparms.dir; fparms.ident_type = iparms.ident_type; fparms.id = iparms.id; @@ -160,8 +160,7 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, rc = tf_alloc_tbl_entry(tfp, &aparms); if (rc) { BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n", - (aparms.dir == TF_DIR_RX) ? "RX" : "TX", - aparms.type); + tf_dir_2_str(aparms.dir), aparms.type); return rc; } @@ -171,7 +170,7 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval); if (rc) { BNXT_TF_DBG(ERR, "Failed to write to global resource id\n"); - /* Free the identifier when update failed */ + /* Free the identifer when update failed */ free_parms.dir = aparms.dir; free_parms.type = aparms.type; free_parms.idx = aparms.idx; @@ -181,16 +180,6 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, return rc; } -/* Retrieve the cache initialization parameters for the tbl_idx */ -static struct bnxt_ulp_cache_tbl_params * -ulp_mapper_cache_tbl_params_get(uint32_t tbl_idx) -{ - if (tbl_idx >= BNXT_ULP_CACHE_TBL_MAX_SZ) - return NULL; - - return &ulp_cache_tbl_params[tbl_idx]; -} - /* Retrieve the global template table */ static uint32_t * ulp_mapper_glb_template_table_get(uint32_t *num_entries) @@ -341,121 +330,6 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_parms *mparms, return &dev_tbls->ident_list[idx]; } -static struct bnxt_ulp_mapper_cache_entry * -ulp_mapper_cache_entry_get(struct bnxt_ulp_context *ulp, - uint32_t id, - uint16_t key) -{ - struct bnxt_ulp_mapper_data *mapper_data; - - mapper_data = bnxt_ulp_cntxt_ptr2_mapper_data_get(ulp); - if (!mapper_data || id >= BNXT_ULP_CACHE_TBL_MAX_SZ || - !mapper_data->cache_tbl[id]) { - BNXT_TF_DBG(ERR, "Unable to acquire the cache tbl (%d)\n", id); - return NULL; - } - - return &mapper_data->cache_tbl[id][key]; -} - -/* - * Concatenates the tbl_type and tbl_id into a 32bit value for storing in the - * resource_type. This is done to conserve memory since both the tbl_type and - * tbl_id are 16bit. - */ -static inline void -ulp_mapper_cache_res_type_set(struct ulp_flow_db_res_params *res, - uint16_t tbl_type, - uint16_t tbl_id) -{ - res->resource_type = tbl_type; - res->resource_sub_type = tbl_id; -} - -/* Extracts the tbl_type and tbl_id from the 32bit resource type. */ -static inline void -ulp_mapper_cache_res_type_get(struct ulp_flow_db_res_params *res, - uint16_t *tbl_type, - uint16_t *tbl_id) -{ - *tbl_type = res->resource_type; - *tbl_id = res->resource_sub_type; -} - -static int32_t -ulp_mapper_cache_entry_free(struct bnxt_ulp_context *ulp, - struct tf *tfp, - struct ulp_flow_db_res_params *res) -{ - struct bnxt_ulp_mapper_cache_entry *cache_entry; - struct tf_free_identifier_parms ident_parms; - struct tf_free_tcam_entry_parms tcam_parms; - uint16_t table_id, table_type; - int32_t rc, trc, i; - - /* - * The table id, used for cache, and table_type, used for tcam, are - * both encoded within the resource. We must first extract them to - * formulate the args for tf calls. - */ - ulp_mapper_cache_res_type_get(res, &table_type, &table_id); - cache_entry = ulp_mapper_cache_entry_get(ulp, table_id, - (uint16_t)res->resource_hndl); - if (!cache_entry || !cache_entry->ref_count) { - BNXT_TF_DBG(ERR, "Cache entry (%d:%d) not valid on free.\n", - table_id, (uint16_t)res->resource_hndl); - return -EINVAL; - } - - /* - * See if we need to delete the entry. The tcam and identifiers are all - * tracked by the cached entries reference count. All are deleted when - * the reference count hit zero. - */ - cache_entry->ref_count--; - if (cache_entry->ref_count) - return 0; - - /* - * Need to delete the tcam entry and the allocated identifiers. - * In the event of a failure, need to try to delete the remaining - * resources before returning error. - */ - tcam_parms.dir = res->direction; - tcam_parms.tcam_tbl_type = table_type; - tcam_parms.idx = cache_entry->tcam_idx; - rc = tf_free_tcam_entry(tfp, &tcam_parms); - if (rc) - BNXT_TF_DBG(ERR, "Failed to free tcam [%d][%s][0x%04x] rc=%d\n", - table_type, - (res->direction == TF_DIR_RX) ? "RX" : "TX", - tcam_parms.idx, rc); - - /* - * Free the identifiers associated with the tcam entry. Entries with - * negative one are considered uninitialized. - */ - for (i = 0; i < BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM; i++) { - if (cache_entry->idents[i] == ULP_IDENTS_INVALID) - continue; - - ident_parms.dir = res->direction; - ident_parms.ident_type = cache_entry->ident_types[i]; - ident_parms.id = cache_entry->idents[i]; - trc = tf_free_identifier(tfp, &ident_parms); - if (trc) { - BNXT_TF_DBG(ERR, "Failed to free identifier " - "[%d][%s][0x%04x] rc=%d\n", - ident_parms.ident_type, - (res->direction == TF_DIR_RX) ? "RX" : "TX", - ident_parms.id, trc); - rc = trc; - } - } - - return rc; -} - static inline int32_t ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp __rte_unused, struct tf *tfp, @@ -537,7 +411,6 @@ ulp_mapper_mark_free(struct bnxt_ulp_context *ulp, res->resource_hndl); } - static inline int32_t ulp_mapper_parent_flow_free(struct bnxt_ulp_context *ulp, uint32_t parent_fid, @@ -628,9 +501,9 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_alloc_identifier(tfp, &iparms); if (rc) { - BNXT_TF_DBG(ERR, "Alloc ident %s:%d failed.\n", - (iparms.dir == TF_DIR_RX) ? "RX" : "TX", - iparms.ident_type); + BNXT_TF_DBG(ERR, "Alloc ident %s:%s failed.\n", + tf_dir_2_str(iparms.dir), + tf_ident_2_str(iparms.ident_type)); return rc; } @@ -664,7 +537,6 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, } else { *val = iparms.id; } - return 0; error: @@ -677,7 +549,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, BNXT_TF_DBG(ERR, "Ident process failed for %s:%s\n", ident->description, - (tbl->direction == TF_DIR_RX) ? "RX" : "TX"); + tf_dir_2_str(tbl->direction)); return rc; } @@ -723,14 +595,12 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, /* Search identifier also increase the reference count */ rc = tf_search_identifier(tfp, &sparms); if (rc) { - BNXT_TF_DBG(ERR, "Search ident %s:%x failed.\n", + BNXT_TF_DBG(ERR, "Search ident %s:%s:%x failed.\n", tf_dir_2_str(sparms.dir), + tf_ident_2_str(sparms.ident_type), sparms.search_id); return rc; } - BNXT_TF_DBG(INFO, "Search ident %s:%x.success.\n", - tf_dir_2_str(sparms.dir), - sparms.search_id); /* Write it to the regfile */ id = (uint64_t)tfp_cpu_to_be_64(sparms.search_id); @@ -782,6 +652,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, { uint16_t idx, size_idx; uint8_t *val = NULL; + uint16_t write_idx = blob->write_idx; uint64_t regval; uint32_t val_size = 0, field_size = 0; uint64_t act_bit; @@ -1057,8 +928,8 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, } break; default: - BNXT_TF_DBG(ERR, "invalid result mapper opcode 0x%x\n", - fld->result_opcode); + BNXT_TF_DBG(ERR, "invalid result mapper opcode 0x%x at %d\n", + fld->result_opcode, write_idx); return -EINVAL; } return 0; @@ -1193,9 +1064,7 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms, BNXT_TF_DBG(ERR, "invalid keymask mapper opcode 0x%x\n", opcode); return -EINVAL; - break; } - return 0; } @@ -1204,15 +1073,15 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl, uint64_t flow_id) { - enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode; struct ulp_flow_db_res_params fid_parms; uint32_t mark, gfid, mark_flag; + enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode; int32_t rc = 0; if (mark_op == BNXT_ULP_MARK_DB_OPCODE_NOP || !(mark_op == BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION && - ULP_BITMAP_ISSET(parms->act_bitmap->bits, - BNXT_ULP_ACTION_BIT_MARK))) + ULP_BITMAP_ISSET(parms->act_bitmap->bits, + BNXT_ULP_ACTION_BIT_MARK))) return rc; /* no need to perform gfid process */ /* Get the mark id details from action property */ @@ -1222,6 +1091,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms, TF_GET_GFID_FROM_FLOW_ID(flow_id, gfid); mark_flag = BNXT_ULP_MARK_GLOBAL_HW_FID; + rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag, gfid, mark); if (rc) { @@ -1246,16 +1116,16 @@ static int32_t ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { - enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode; struct ulp_flow_db_res_params fid_parms; uint32_t act_idx, mark, mark_flag; uint64_t val64; + enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode; int32_t rc = 0; if (mark_op == BNXT_ULP_MARK_DB_OPCODE_NOP || !(mark_op == BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION && - ULP_BITMAP_ISSET(parms->act_bitmap->bits, - BNXT_ULP_ACTION_BIT_MARK))) + ULP_BITMAP_ISSET(parms->act_bitmap->bits, + BNXT_ULP_ACTION_BIT_MARK))) return rc; /* no need to perform mark action process */ /* Get the mark id details from action property */ @@ -1473,19 +1343,6 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, tf_dir_2_str(sparms.dir), sparms.idx); return -EIO; } - BNXT_TF_DBG(INFO, "tcam[%s][%s][%x] write success.\n", - tf_tcam_tbl_2_str(sparms.tcam_tbl_type), - tf_dir_2_str(sparms.dir), sparms.idx); - - /* Update cache with TCAM index if the was cache allocated. */ - if (parms->tcam_tbl_opc == - BNXT_ULP_MAPPER_TCAM_TBL_OPC_CACHE_ALLOC) { - if (!parms->cache_ptr) { - BNXT_TF_DBG(ERR, "Unable to update cache"); - return -EINVAL; - } - parms->cache_ptr->tcam_idx = idx; - } /* Mark action */ rc = ulp_mapper_mark_act_ptr_process(parms, tbl); @@ -1713,7 +1570,6 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, } if (rc) goto error; - /* * Only link the entry to the flow db in the event that cache was not * used. @@ -1741,7 +1597,6 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, * entry does not use cache. */ parms->tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL; - parms->cache_ptr = NULL; } return 0; @@ -1837,7 +1692,6 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } } - /* do the transpose for the internal EM keys */ if (tbl->resource_func == BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) ulp_blob_perform_byte_reverse(&key); @@ -1964,7 +1818,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, for (i = 0; i < (num_flds + encap_flds); i++) { /* set the swap index if encap swap bit is enabled */ if (parms->device_params->encap_byte_swap && encap_flds && - (i == num_flds)) + i == num_flds) ulp_blob_encap_swap_idx_set(&data); /* Process the result fields */ @@ -2011,11 +1865,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_set_tbl_entry(tfp, &sparms); if (rc) { BNXT_TF_DBG(ERR, - "Glbl Set table[%d][%s][%d] failed rc=%d\n", - sparms.type, - (sparms.dir == TF_DIR_RX) ? "RX" : "TX", - sparms.idx, - rc); + "Glbl Index table[%s][%s][%x] failed rc=%d\n", + tf_tbl_type_2_str(sparms.type), + tf_dir_2_str(sparms.dir), + sparms.idx, rc); return rc; } return 0; /* success */ @@ -2065,6 +1918,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, } index = aparms.idx; } + /* * calculate the idx for the result record, for external EM the offset * needs to be shifted accordingly. If external non-inline table types @@ -2097,11 +1951,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_set_tbl_entry(tfp, &sparms); if (rc) { - BNXT_TF_DBG(ERR, "Set table[%d][%s][%d] failed rc=%d\n", - sparms.type, - (sparms.dir == TF_DIR_RX) ? "RX" : "TX", - sparms.idx, - rc); + BNXT_TF_DBG(ERR, "Set table[%s][%s][%x] failed rc=%d\n", + tf_tbl_type_2_str(sparms.type), + tf_dir_2_str(sparms.dir), + sparms.idx, rc); goto error; } } @@ -2149,162 +2002,6 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } -static int32_t -ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms, - struct bnxt_ulp_mapper_tbl_info *tbl) -{ - struct bnxt_ulp_mapper_key_field_info *kflds; - struct bnxt_ulp_mapper_cache_entry *cache_entry; - struct bnxt_ulp_mapper_ident_info *idents; - uint32_t i, num_kflds = 0, num_idents = 0; - struct ulp_flow_db_res_params fid_parms; - struct tf_free_identifier_parms fparms; - uint16_t tmplen, tmp_ident; - struct ulp_blob key; - uint8_t *cache_key; - uint64_t regval; - uint16_t *ckey; - int32_t rc; - - /* Get the key fields list and build the key. */ - kflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds); - if (!kflds || !num_kflds) { - BNXT_TF_DBG(ERR, "Failed to get key fields\n"); - return -EINVAL; - } - if (!ulp_blob_init(&key, tbl->key_bit_size, - parms->device_params->byte_order)) { - BNXT_TF_DBG(ERR, "Failed to alloc blob\n"); - return -EINVAL; - } - for (i = 0; i < num_kflds; i++) { - /* Setup the key */ - rc = ulp_mapper_keymask_field_process(parms, tbl->direction, - &kflds[i], - &key, 1, "Cache Key"); - if (rc) { - BNXT_TF_DBG(ERR, - "Failed to create key for Cache rc=%d\n", - rc); - return -EINVAL; - } - } - - /* - * Perform the lookup in the cache table with constructed key. The - * cache_key is a byte array of tmplen, it needs to be converted to a - * index for the cache table. - */ - cache_key = ulp_blob_data_get(&key, &tmplen); - ckey = (uint16_t *)cache_key; - - /* - * The id computed based on resource sub type and direction where - * dir is the bit0 and rest of the bits come from resource - * sub type. - */ - cache_entry = ulp_mapper_cache_entry_get(parms->ulp_ctx, - (tbl->resource_sub_type << 1 | - (tbl->direction & 0x1)), - *ckey); - - /* - * Get the identifier list for processing by both the hit and miss - * processing. - */ - idents = ulp_mapper_ident_fields_get(parms, tbl, &num_idents); - - if (!cache_entry->ref_count) { - /* Initialize the cache entry */ - cache_entry->tcam_idx = 0; - cache_entry->ref_count = 0; - for (i = 0; i < BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM; i++) - cache_entry->idents[i] = ULP_IDENTS_INVALID; - - /* Need to allocate identifiers for storing in the cache. */ - for (i = 0; i < num_idents; i++) { - /* - * Since we are using the cache, the identifier does not - * get added to the flow db. Pass in the pointer to the - * tmp_ident. - */ - rc = ulp_mapper_ident_process(parms, tbl, - &idents[i], &tmp_ident); - if (rc) - goto error; - - cache_entry->ident_types[i] = idents[i].ident_type; - cache_entry->idents[i] = tmp_ident; - } - - /* Tell the TCAM processor to alloc an entry */ - parms->tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_CACHE_ALLOC; - /* Store the cache key for use by the tcam process code */ - parms->cache_ptr = cache_entry; - } else { - /* Cache hit, get values from result. */ - for (i = 0; i < num_idents; i++) { - regval = (uint64_t)cache_entry->idents[i]; - if (!ulp_regfile_write(parms->regfile, - idents[i].regfile_idx, - tfp_cpu_to_be_64(regval))) { - BNXT_TF_DBG(ERR, - "Failed to write to regfile\n"); - return -EINVAL; - } - } - /* - * The cached entry is being used, so let the tcam processing - * know not to process this table. - */ - parms->tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_CACHE_SKIP; - } - - /* Made through the cache processing, increment the reference count. */ - cache_entry->ref_count++; - - /* Link the cache to the flow db. */ - memset(&fid_parms, 0, sizeof(fid_parms)); - fid_parms.direction = tbl->direction; - fid_parms.resource_func = tbl->resource_func; - - /* - * Cache resource type is composed of table_type, resource - * sub type and direction, it needs to set appropriately via setter. - */ - ulp_mapper_cache_res_type_set(&fid_parms, - tbl->resource_type, - (tbl->resource_sub_type << 1 | - (tbl->direction & 0x1))); - fid_parms.resource_hndl = (uint64_t)*ckey; - fid_parms.critical_resource = tbl->critical_resource; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); - if (rc) - BNXT_TF_DBG(ERR, "Failed to add cache to flow db.\n"); - - return rc; -error: - /* - * This error handling only gets called when the idents are being - * allocated for the cache on misses. Using the num_idents that was - * previously set. - */ - for (i = 0; i < num_idents; i++) { - if (cache_entry->idents[i] == ULP_IDENTS_INVALID) - continue; - - fparms.dir = tbl->direction; - fparms.ident_type = idents[i].ident_type; - fparms.id = cache_entry->idents[i]; - tf_free_identifier(parms->tfp, &fparms); - } - - return rc; -} - static int32_t ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) @@ -2367,21 +2064,232 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_set_if_tbl_entry(tfp, &iftbl_params); if (rc) { - BNXT_TF_DBG(ERR, "Set table[%d][%s][%d] failed rc=%d\n", - iftbl_params.type, - (iftbl_params.dir == TF_DIR_RX) ? "RX" : "TX", - iftbl_params.idx, - rc); + BNXT_TF_DBG(ERR, "Set table[%d][%s][%x] failed rc=%d\n", + iftbl_params.type,/* TBD: add tf_if_tbl_2_str */ + tf_dir_2_str(iftbl_params.dir), + iftbl_params.idx, rc); return rc; } /* * TBD: Need to look at the need to store idx in flow db for restore - * the table to its original state on deletion of this entry. + * the table to its orginial state on deletion of this entry. */ return rc; } +/* + * Process the identifier list in the generic table. + * Extract the ident from the generic table entry and + * write it to the reg file. + */ +static int32_t +ulp_mapper_gen_tbl_ident_scan(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_mapper_gen_tbl_entry *gen_tbl_ent) +{ + struct bnxt_ulp_mapper_ident_info *idents; + uint32_t i, idx, num_idents = 0; + int32_t rc = 0; + + /* Get the ident list */ + idents = ulp_mapper_ident_fields_get(parms, tbl, &num_idents); + + for (i = 0; i < num_idents; i++) { + /* Extract the index from the result byte data array */ + rc = ulp_mapper_gen_tbl_entry_data_get(gen_tbl_ent, + idents[i].ident_bit_pos, + idents[i].ident_bit_size, + (uint8_t *)&idx, + sizeof(idx)); + + /* validate the extraction */ + if (rc) { + BNXT_TF_DBG(ERR, "failed to read %s:%x:%x\n", + idents[i].description, + idents[i].ident_bit_pos, + idents[i].ident_bit_size); + return -EINVAL; + } + + /* Write it to the regfile */ + if (!ulp_regfile_write(parms->regfile, + idents[i].regfile_idx, idx)) { + BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", + idents[i].regfile_idx); + return -EINVAL; + } + } + return 0; +} + +/* + * Process the identifier list in the generic table. + * Write the ident to the generic table entry + */ +static int32_t +ulp_mapper_gen_tbl_ident_write(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_mapper_gen_tbl_entry *gen_tbl_ent) +{ + struct bnxt_ulp_mapper_ident_info *idents; + uint32_t i, num_idents = 0; + uint64_t idx; + + /* Get the ident list */ + idents = ulp_mapper_ident_fields_get(parms, tbl, &num_idents); + + for (i = 0; i < num_idents; i++) { + /* read from the regfile */ + if (!ulp_regfile_read(parms->regfile, idents[i].regfile_idx, + &idx)) { + BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", + idents[i].regfile_idx); + return -EINVAL; + } + + /* Update the gen tbl entry with the new data */ + ulp_mapper_gen_tbl_entry_data_set(gen_tbl_ent, + idents[i].ident_bit_pos, + idents[i].ident_bit_size, + (uint8_t *)&idx); + } + return 0; +} + +static int32_t +ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl) +{ + struct bnxt_ulp_mapper_key_field_info *kflds; + struct ulp_flow_db_res_params fid_parms; + struct ulp_mapper_gen_tbl_entry gen_tbl_ent; + uint16_t tmplen; + struct ulp_blob key; + uint8_t *cache_key; + int32_t tbl_idx; + uint32_t i, ckey, num_kflds = 0; + uint32_t gen_tbl_hit = 0, fdb_write = 0; + int32_t rc = 0; + + /* Get the key fields list and build the key. */ + kflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds); + if (!kflds || !num_kflds) { + BNXT_TF_DBG(ERR, "Failed to get key fields\n"); + return -EINVAL; + } + if (!ulp_blob_init(&key, tbl->key_bit_size, + parms->device_params->byte_order)) { + BNXT_TF_DBG(ERR, "Failed to alloc blob\n"); + return -EINVAL; + } + for (i = 0; i < num_kflds; i++) { + /* Setup the key */ + rc = ulp_mapper_keymask_field_process(parms, tbl->direction, + &kflds[i], + &key, 1, "Gen Tbl Key"); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed to create key for Gen tbl rc=%d\n", + rc); + return -EINVAL; + } + } + + /* Calculate the table index for the generic table*/ + tbl_idx = ulp_mapper_gen_tbl_idx_calculate(tbl->resource_sub_type, + tbl->direction); + if (tbl_idx < 0) { + BNXT_TF_DBG(ERR, "Invalid table index %x:%x\n", + tbl->resource_sub_type, tbl->direction); + return -EINVAL; + } + + /* The_key is a byte array convert it to a search index */ + cache_key = ulp_blob_data_get(&key, &tmplen); + memcpy(&ckey, cache_key, sizeof(ckey)); + /* Get the generic table entry */ + rc = ulp_mapper_gen_tbl_entry_get(parms->ulp_ctx, + tbl_idx, ckey, &gen_tbl_ent); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed to create key for Gen tbl rc=%d\n", rc); + return -EINVAL; + } + switch (tbl->tbl_opcode) { + case BNXT_ULP_GENERIC_TBL_OPC_READ: + /* check the reference count */ + if (ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) { + /* Scan ident list and create the result blob*/ + rc = ulp_mapper_gen_tbl_ident_scan(parms, tbl, + &gen_tbl_ent); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed to scan ident list\n"); + return -EINVAL; + } + /* increment the reference count */ + ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent); + + /* it is a hit */ + gen_tbl_hit = 1; + fdb_write = 1; + } + break; + case BNXT_ULP_GENERIC_TBL_OPC_WRITE: + /* check the reference count */ + if (ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) { + /* a hit then error */ + BNXT_TF_DBG(ERR, "generic entry already present %x\n", + ckey); + return -EINVAL; /* success */ + } + + /* Create the result blob from the ident list */ + rc = ulp_mapper_gen_tbl_ident_write(parms, tbl, &gen_tbl_ent); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed to write ident list\n"); + return -EINVAL; + } + + /* increment the reference count */ + ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent); + fdb_write = 1; + break; + default: + BNXT_TF_DBG(ERR, "Invalid table opcode %x\n", tbl->tbl_opcode); + return -EINVAL; + } + + /* Set the generic entry hit */ + rc = ulp_regfile_write(parms->regfile, + BNXT_ULP_REGFILE_INDEX_GENERIC_TBL_HIT, + gen_tbl_hit); + if (!rc) { + BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", + tbl->index_operand); + return -EIO; + } + + /* add the entry to the flow database */ + if (fdb_write) { + memset(&fid_parms, 0, sizeof(fid_parms)); + fid_parms.direction = tbl->direction; + fid_parms.resource_func = tbl->resource_func; + fid_parms.resource_sub_type = tbl->resource_sub_type; + fid_parms.resource_hndl = ckey; + fid_parms.critical_resource = tbl->critical_resource; + rc = ulp_flow_db_resource_add(parms->ulp_ctx, + parms->flow_type, + parms->fid, + &fid_parms); + if (rc) + BNXT_TF_DBG(ERR, "Fail to add gen ent flowdb %d\n", rc); + } + return rc; +} + static int32_t ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_mapper_data *mapper_data) @@ -2522,7 +2430,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) tbls = ulp_mapper_tbl_list_get(parms, tid, &num_tbls); if (!tbls || !num_tbls) { BNXT_TF_DBG(ERR, "No %s tables for %d:%d\n", - (parms->tmpl_type == BNXT_ULP_TEMPLATE_TYPE_CLASS) ? + (parms->tmpl_type = BNXT_ULP_TEMPLATE_TYPE_CLASS) ? "class" : "action", parms->dev_id, tid); return -EINVAL; } @@ -2546,12 +2454,15 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: rc = ulp_mapper_index_tbl_process(parms, tbl); break; - case BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE: - rc = ulp_mapper_cache_tbl_process(parms, tbl); - break; case BNXT_ULP_RESOURCE_FUNC_IF_TABLE: rc = ulp_mapper_if_tbl_process(parms, tbl); break; + case BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE: + rc = ulp_mapper_gen_tbl_process(parms, tbl); + break; + case BNXT_ULP_RESOURCE_FUNC_INVALID: + rc = 0; + break; default: BNXT_TF_DBG(ERR, "Unexpected mapper resource %d\n", tbl->resource_func); @@ -2569,7 +2480,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) return rc; error: BNXT_TF_DBG(ERR, "%s tables failed creation for %d:%d\n", - (parms->tmpl_type == BNXT_ULP_TEMPLATE_TYPE_CLASS) ? + (parms->tmpl_type = BNXT_ULP_TEMPLATE_TYPE_CLASS) ? "class" : "action", parms->dev_id, tid); return rc; } @@ -2594,9 +2505,6 @@ ulp_mapper_resource_free(struct bnxt_ulp_context *ulp, } switch (res->resource_func) { - case BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE: - rc = ulp_mapper_cache_entry_free(ulp, tfp, res); - break; case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: rc = ulp_mapper_tcam_entry_free(ulp, tfp, res); break; @@ -2619,6 +2527,9 @@ ulp_mapper_resource_free(struct bnxt_ulp_context *ulp, case BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW: rc = ulp_mapper_child_flow_free(ulp, fid, res); break; + case BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE: + rc = ulp_mapper_gen_tbl_res_free(ulp, res); + break; default: break; } @@ -2902,11 +2813,9 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, int32_t ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx) { - struct bnxt_ulp_cache_tbl_params *tbl; struct bnxt_ulp_mapper_data *data; - uint32_t i; struct tf *tfp; - int32_t rc, csize; + int32_t rc; if (!ulp_ctx) return -EINVAL; @@ -2936,28 +2845,14 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx) goto error; } - /* Allocate the ulp cache tables. */ - for (i = 0; i < BNXT_ULP_CACHE_TBL_MAX_SZ; i++) { - tbl = ulp_mapper_cache_tbl_params_get(i); - if (!tbl) { - BNXT_TF_DBG(ERR, "Failed to get cache table parms (%d)", - i); - goto error; - } - if (tbl->num_entries != 0) { - csize = sizeof(struct bnxt_ulp_mapper_cache_entry) * - tbl->num_entries; - data->cache_tbl[i] = rte_zmalloc("ulp mapper cache tbl", - csize, 0); - if (!data->cache_tbl[i]) { - BNXT_TF_DBG(ERR, "Failed to allocate Cache " - "table %d.\n", i); - rc = -ENOMEM; - goto error; - } - } + /* Allocate the generic table list */ + rc = ulp_mapper_generic_tbl_list_init(data); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to initialize generic tbl list\n"); + goto error; } + /* Allocate global template table entries */ rc = ulp_mapper_glb_template_table_init(ulp_ctx); if (rc) { BNXT_TF_DBG(ERR, "Failed to initialize global templates\n"); @@ -2975,7 +2870,6 @@ void ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx) { struct bnxt_ulp_mapper_data *data; - uint32_t i; struct tf *tfp; if (!ulp_ctx) { @@ -3004,11 +2898,8 @@ ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx) ulp_mapper_glb_resource_info_deinit(ulp_ctx, data); free_mapper_data: - /* Free the ulp cache tables */ - for (i = 0; i < BNXT_ULP_CACHE_TBL_MAX_SZ; i++) { - rte_free(data->cache_tbl[i]); - data->cache_tbl[i] = NULL; - } + /* Free the generic table */ + (void)ulp_mapper_generic_tbl_list_deinit(data); rte_free(data); /* Reset the data pointer within the ulp_ctx. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 4ce19cc88d..8422f44026 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -14,6 +14,7 @@ #include "ulp_template_struct.h" #include "bnxt_ulp.h" #include "ulp_utils.h" +#include "ulp_gen_tbl.h" #define ULP_IDENTS_INVALID ((uint16_t)0xffff) @@ -31,13 +32,6 @@ enum bnxt_ulp_cache_table_opc { BNXT_ULP_MAPPER_TCAM_TBL_OPC_CACHE_ALLOC }; -struct bnxt_ulp_mapper_cache_entry { - uint32_t ref_count; - uint16_t tcam_idx; - uint16_t idents[BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM]; - uint8_t ident_types[BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM]; -}; - struct bnxt_ulp_mapper_glb_resource_entry { enum bnxt_ulp_resource_func resource_func; uint32_t resource_type; /* TF_ enum type */ @@ -47,8 +41,7 @@ struct bnxt_ulp_mapper_glb_resource_entry { struct bnxt_ulp_mapper_data { struct bnxt_ulp_mapper_glb_resource_entry glb_res_tbl[TF_DIR_MAX][BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ]; - struct bnxt_ulp_mapper_cache_entry - *cache_tbl[BNXT_ULP_CACHE_TBL_MAX_SZ]; + struct ulp_mapper_gen_tbl_list gen_tbl_list[BNXT_ULP_GEN_TBL_MAX_SZ]; }; /* Internal Structure for passing the arguments around */ @@ -69,13 +62,11 @@ struct bnxt_ulp_mapper_parms { struct ulp_regfile *regfile; struct tf *tfp; struct bnxt_ulp_context *ulp_ctx; - uint8_t encap_byte_swap; uint32_t fid; enum bnxt_ulp_fdb_type flow_type; struct bnxt_ulp_mapper_data *mapper_data; enum bnxt_ulp_cache_table_opc tcam_tbl_opc; - struct bnxt_ulp_mapper_cache_entry *cache_ptr; - struct bnxt_ulp_device_params *device_params; + struct bnxt_ulp_device_params *device_params; uint32_t parent_fid; uint32_t parent_flow; uint8_t tun_idx; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 5deb7b9236..2a9a290eea 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -9,7 +9,7 @@ #define BNXT_ULP_REGFILE_MAX_SZ 19 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_CACHE_TBL_MAX_SZ 4 +#define BNXT_ULP_GEN_TBL_MAX_SZ 4 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 217 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919 @@ -53,7 +53,10 @@ enum bnxt_ulp_action_bit { BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000000200000, BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000000400000, BNXT_ULP_ACTION_BIT_JUMP = 0x0000000000800000, - BNXT_ULP_ACTION_BIT_LAST = 0x0000000001000000 + BNXT_ULP_ACTION_BIT_SHARED = 0x0000000001000000, + BNXT_ULP_ACTION_BIT_SAMPLE = 0x0000000002000000, + BNXT_ULP_ACTION_BIT_SHARED_SAMPLE = 0x0000000004000000, + BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000 }; enum bnxt_ulp_hdr_bit { @@ -183,6 +186,13 @@ enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_LAST = 3 }; +enum bnxt_ulp_generic_tbl_opc { + BNXT_ULP_GENERIC_TBL_OPC_NOT_USED = 0, + BNXT_ULP_GENERIC_TBL_OPC_READ = 1, + BNXT_ULP_GENERIC_TBL_OPC_WRITE = 2, + BNXT_ULP_GENERIC_TBL_OPC_LAST = 3 +}; + enum bnxt_ulp_glb_regfile_index { BNXT_ULP_GLB_REGFILE_INDEX_NOT_USED = 0, BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 1, @@ -261,25 +271,36 @@ enum bnxt_ulp_priority { enum bnxt_ulp_regfile_index { BNXT_ULP_REGFILE_INDEX_NOT_USED = 0, - BNXT_ULP_REGFILE_INDEX_CLASS_TID = 1, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 2, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 3, - BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 4, - BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 5, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 6, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 7, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 8, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 9, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 10, - BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 11, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 12, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 13, - BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 14, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 15, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR = 16, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 = 17, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 = 18, - BNXT_ULP_REGFILE_INDEX_LAST = 19 + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2, + BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3, + BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6, + BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7, + BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9, + BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10, + BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11, + BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12, + BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13, + BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 14, + BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR = 15, + BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 = 16, + BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 = 17, + BNXT_ULP_REGFILE_INDEX_ACTION_REC_SIZE = 18, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0 = 19, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_1 = 20, + BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0 = 21, + BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_1 = 22, + BNXT_ULP_REGFILE_INDEX_WC_TCAM_INDEX_0 = 23, + BNXT_ULP_REGFILE_INDEX_WC_TCAM_INDEX_1 = 24, + BNXT_ULP_REGFILE_INDEX_SRC_PROPERTY_PTR = 25, + BNXT_ULP_REGFILE_INDEX_GENERIC_TBL_HIT = 26, + BNXT_ULP_REGFILE_INDEX_MIRROR_PTR_0 = 27, + BNXT_ULP_REGFILE_INDEX_CLASS_TID = 28, + BNXT_ULP_REGFILE_INDEX_FID = 29, + BNXT_ULP_REGFILE_INDEX_LAST = 30 }; enum bnxt_ulp_search_before_alloc { @@ -322,7 +343,7 @@ enum bnxt_ulp_resource_func { BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60, BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80, BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81, - BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82, + BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE = 0x82, BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83, BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84, BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c index 3c868fdf00..a8f26e8c51 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c @@ -3,132 +3,185 @@ * All rights reserved. */ +/* date: Thu Oct 15 17:28:37 2020 */ + #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" #include "ulp_rte_parser.h" +/* Mapper templates for header class list */ struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_class_tmpl_list[] = { + /* default-vfr-[port_to_vs]:1 */ + /* class_tid: 1, stingray, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 0 }, + /* default-vfr-[vs_to_port]:2 */ + /* class_tid: 2, stingray, egress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 7, .start_tbl_idx = 6 }, + /* default-vfr-[vfrep_to_vf]:3 */ + /* class_tid: 3, stingray, egress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 7, .start_tbl_idx = 13 }, + /* default-vfr-[vf_to_vfrep]:4 */ + /* class_tid: 4, stingray, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 7, .start_tbl_idx = 20 }, + /* default-egr-[loopback_action_rec]:5 */ + /* class_tid: 5, stingray, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 1, .start_tbl_idx = 27 }, + /* class-ing-em-[eth, (vlan), ipv4]-[smac, dmac, (vid)]:6 */ + /* class_tid: 6, stingray, ingress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 28 }, + /* class-ing-em-[eth, (vlan), ipv6]-[smac, dmac, (vid)]:7 */ + /* class_tid: 7, stingray, ingress */ [7] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 33 }, + /* class-ing-em-[eth, ipv4, udp]-[sip, dip, sp, dp]:8 */ + /* class_tid: 8, stingray, ingress */ [8] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 38 }, + /* class-ing-em-[eth, ipv4, tcp]-[sip, dip, sp, dp]:9 */ + /* class_tid: 9, stingray, ingress */ [9] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 44 }, + /* class-ing-em-[eth,ipv6, udp]-[sip, dip, sp, dp]:10 */ + /* class_tid: 10, stingray, ingress */ [10] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 50 }, + /* class-ing-em-[eth, ipv6, tcp]-[sip, dip, sp, dp]:11 */ + /* class_tid: 11, stingray, ingress */ [11] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 56 }, + /* class-ing-em-[eth, (vlan), ipv4, udp]-[dmac, (vid), sip, dip, sp, dp]:12 */ + /* class_tid: 12, stingray, ingress */ [12] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 62 }, + /* class-ing-em-[eth, (vlan), ipv4, tcp]-[dmac, (vid), sip, dip, sp, dp]:13 */ + /* class_tid: 13, stingray, ingress */ [13] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 67 }, + /* class-ing-em-[eth, (vlan), ipv6, udp]-[dmac, (vid), sip, dip, sp, dp]:14 */ + /* class_tid: 14, stingray, ingress */ [14] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 72 }, + /* class-ing-em-[eth, (vlan), ipv6, tcp]-[dmac, (vid), sip, dip, sp, dp]:15 */ + /* class_tid: 15, stingray, ingress */ [15] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 77 }, + /* class-ing-em-[eth, (vlan), ipv4, udp, vxlan]-[dmac, (vid), dip, dp]:16 */ + /* class_tid: 16, stingray, ingress */ [16] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 82 }, + /* class-ing-em-[eth, (vlan), ipv6, udp, vxlan]-[t_dmac, (vid), t_dip, t_dp]:17 */ + /* class_tid: 17, stingray, ingress */ [17] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 87 }, + /* class-ing-em-f1-[eth, ipv4, udp, vxlan]-[t_dmac]:18 */ + /* class_tid: 18, stingray, ingress */ [18] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 92 }, + /* class-ing-em-f2-[ipv4, udp, vxlan]-[vni, i_dmac]:19 */ + /* class_tid: 19, stingray, ingress */ [19] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 97 }, + /* class-egr-em-[eth, ipv4, udp]-[sip, dip, sp, dp]:20 */ + /* class_tid: 20, stingray, egress */ [20] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 102 }, + /* class-egr-em-[eth, ipv4, tcp]-[sip, dip, sp, dp]:21 */ + /* class_tid: 21, stingray, egress */ [21] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 108 }, + /* class-egr-em-[eth-ipv6-udp]-[sip-dip-sp-dp]:22 */ + /* class_tid: 22, stingray, egress */ [22] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 114 }, + /* class-egr-em-[eth, ipv6, tcp]-[sip, dip, sp, dp]:23 */ + /* class_tid: 23, stingray, egress */ [23] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 120 }, + /* class-egr-em-[eth, (vlan), ipv4]-[smac, dmac, type]:24 */ + /* class_tid: 24, stingray, egress */ [24] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, .start_tbl_idx = 126 }, + /* class-egr-em-[eth, (vlan), ipv6]-[smac, dmac, type]:25 */ + /* class_tid: 25, stingray, egress */ [25] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, @@ -137,7 +190,7 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_class_tmpl_list[] = { }; struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { - { + { /* class_tid: 1, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -152,8 +205,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -169,7 +222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 0, .ident_nums = 1 }, - { + { /* class_tid: 1, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -188,7 +241,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 1, stingray, table: parif_def_lkup_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -199,7 +252,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, - { + { /* class_tid: 1, stingray, table: parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -210,7 +263,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, - { + { /* class_tid: 1, stingray, table: parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -221,7 +274,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, - { + { /* class_tid: 2, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -236,7 +289,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* class_tid: 2, stingray, table: l2_cntxt_tcam_vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, @@ -257,8 +310,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -276,7 +329,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 1, .ident_nums = 1 }, - { + { /* class_tid: 2, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET, @@ -297,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -308,7 +361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, - { + { /* class_tid: 2, stingray, table: parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -319,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, - { + { /* class_tid: 2, stingray, table: parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -330,7 +383,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, - { + { /* class_tid: 3, stingray, table: egr_int_vtag_encap_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = @@ -345,7 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, - { + { /* class_tid: 3, stingray, table: egr_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -360,8 +413,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 3, stingray, table: egr_l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -377,7 +430,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 2, .ident_nums = 0 }, - { + { /* class_tid: 3, stingray, table: egr_l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -396,7 +449,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 3, stingray, table: ing_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -411,7 +464,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* class_tid: 3, stingray, table: ing_l2_cntxt_dtagged_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -430,7 +483,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 3, stingray, table: ing_l2_cntxt_stagged_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -449,8 +502,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -466,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 2, .ident_nums = 1 }, - { + { /* class_tid: 4, stingray, table: egr_l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -485,7 +538,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 4, stingray, table: egr_parif_def_lkup_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -496,7 +549,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, - { + { /* class_tid: 4, stingray, table: egr_parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -507,7 +560,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, - { + { /* class_tid: 4, stingray, table: egr_parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -518,7 +571,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, - { + { /* class_tid: 4, stingray, table: ing_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -533,7 +586,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* class_tid: 4, stingray, table: ing_l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -552,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 5, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -567,7 +620,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR }, - { + { /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -586,8 +639,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -603,7 +656,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 4, .ident_nums = 1 }, - { + { /* class_tid: 6, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -622,7 +675,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 6, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -640,7 +693,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 6, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -658,7 +711,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -677,8 +730,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -694,7 +747,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 6, .ident_nums = 1 }, - { + { /* class_tid: 7, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -713,7 +766,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 7, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -731,7 +784,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 7, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -749,8 +802,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -766,7 +819,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 7, .ident_nums = 1 }, - { + { /* class_tid: 8, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -785,8 +838,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -802,7 +855,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 8, .ident_nums = 1 }, - { + { /* class_tid: 8, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -821,7 +874,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 8, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -839,7 +892,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 8, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -857,8 +910,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -874,7 +927,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 9, .ident_nums = 1 }, - { + { /* class_tid: 9, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -893,8 +946,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -910,7 +963,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 10, .ident_nums = 1 }, - { + { /* class_tid: 9, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -929,7 +982,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 9, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -947,7 +1000,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 9, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -965,8 +1018,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -982,7 +1035,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 11, .ident_nums = 1 }, - { + { /* class_tid: 10, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -1001,8 +1054,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1018,7 +1071,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 12, .ident_nums = 1 }, - { + { /* class_tid: 10, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1037,7 +1090,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 10, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1055,7 +1108,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 10, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1073,8 +1126,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -1090,7 +1143,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 13, .ident_nums = 1 }, - { + { /* class_tid: 11, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -1109,8 +1162,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1126,7 +1179,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 14, .ident_nums = 1 }, - { + { /* class_tid: 11, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1145,7 +1198,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 11, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1163,7 +1216,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 11, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1181,7 +1234,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1200,8 +1253,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1217,7 +1270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 16, .ident_nums = 1 }, - { + { /* class_tid: 12, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1236,7 +1289,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 12, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1254,7 +1307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 12, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1272,7 +1325,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1291,8 +1344,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1308,7 +1361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 18, .ident_nums = 1 }, - { + { /* class_tid: 13, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1327,7 +1380,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 13, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1345,7 +1398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 13, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1363,7 +1416,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1382,8 +1435,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1399,7 +1452,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 20, .ident_nums = 1 }, - { + { /* class_tid: 14, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1418,7 +1471,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 14, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1436,7 +1489,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 14, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1454,7 +1507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1473,8 +1526,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1490,7 +1543,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 22, .ident_nums = 1 }, - { + { /* class_tid: 15, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1509,7 +1562,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 15, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1527,7 +1580,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 15, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1545,7 +1598,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1564,8 +1617,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1581,7 +1634,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 24, .ident_nums = 1 }, - { + { /* class_tid: 16, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1600,7 +1653,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 16, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1618,7 +1671,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 16, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1636,7 +1689,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1655,8 +1708,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1672,7 +1725,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 26, .ident_nums = 1 }, - { + { /* class_tid: 17, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1691,7 +1744,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 17, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1709,7 +1762,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 17, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1727,7 +1780,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 18, stingray, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -1744,7 +1797,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1763,8 +1816,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1780,7 +1833,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 28, .ident_nums = 2 }, - { + { /* class_tid: 18, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1799,7 +1852,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 18, stingray, table: wm_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .direction = TF_DIR_RX, @@ -1818,7 +1871,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1837,8 +1890,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1854,7 +1907,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 31, .ident_nums = 2 }, - { + { /* class_tid: 19, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1873,7 +1926,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 19, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1891,7 +1944,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 19, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1909,8 +1962,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -1926,7 +1979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 33, .ident_nums = 1 }, - { + { /* class_tid: 20, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1945,8 +1998,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1962,7 +2015,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 34, .ident_nums = 1 }, - { + { /* class_tid: 20, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -1981,7 +2034,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 20, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1999,7 +2052,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 20, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2017,8 +2070,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -2034,7 +2087,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 35, .ident_nums = 1 }, - { + { /* class_tid: 21, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -2053,8 +2106,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2070,7 +2123,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 36, .ident_nums = 1 }, - { + { /* class_tid: 21, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2089,7 +2142,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 21, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2107,7 +2160,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 21, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2125,8 +2178,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -2142,7 +2195,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 37, .ident_nums = 1 }, - { + { /* class_tid: 22, stingray, table: l2_cntxt_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -2161,8 +2214,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2178,7 +2231,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 38, .ident_nums = 1 }, - { + { /* class_tid: 22, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2197,7 +2250,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 22, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2215,7 +2268,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 22, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2233,8 +2286,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -2250,7 +2303,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 39, .ident_nums = 1 }, - { + { /* class_tid: 23, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -2269,8 +2322,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2286,7 +2339,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 40, .ident_nums = 1 }, - { + { /* class_tid: 23, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2305,7 +2358,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 23, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2323,7 +2376,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 23, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2341,7 +2394,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, @@ -2360,8 +2413,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2377,7 +2430,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 42, .ident_nums = 1 }, - { + { /* class_tid: 24, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2396,7 +2449,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 24, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2414,7 +2467,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 24, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2432,7 +2485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, @@ -2451,8 +2504,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2468,7 +2521,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_start_idx = 44, .ident_nums = 1 }, - { + { /* class_tid: 25, stingray, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2487,7 +2540,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 25, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2505,7 +2558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 25, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2526,7 +2579,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { }; struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { + /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, @@ -2536,22 +2591,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 1, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2564,46 +2624,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2612,22 +2681,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, stingray, table: l2_cntxt_tcam_vfr_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2640,46 +2714,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2688,7 +2771,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, @@ -2698,22 +2783,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2726,46 +2816,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2774,7 +2873,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, stingray, table: egr_l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, @@ -2784,22 +2885,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, stingray, table: egr_l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2812,46 +2918,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2860,12 +2975,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, stingray, table: ing_l2_cntxt_dtagged_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2878,11 +2996,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2895,21 +3015,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2919,11 +3043,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2935,16 +3061,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2953,7 +3082,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, stingray, table: ing_l2_cntxt_stagged_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2966,16 +3097,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2988,21 +3122,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3012,11 +3150,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3028,16 +3168,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3046,7 +3189,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, @@ -3056,22 +3201,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: egr_l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3084,46 +3234,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3132,22 +3291,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: ing_l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3160,46 +3324,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3208,7 +3381,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3224,11 +3399,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3244,6 +3421,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3259,21 +3437,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3286,16 +3468,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3303,11 +3488,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3316,12 +3503,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -3332,6 +3522,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3341,42 +3532,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3384,6 +3584,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3391,6 +3592,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3402,16 +3604,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3419,6 +3624,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3426,6 +3632,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3433,6 +3640,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3444,21 +3652,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3466,21 +3678,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3488,31 +3704,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3520,26 +3742,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3547,16 +3774,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3569,11 +3799,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3581,11 +3813,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3593,6 +3827,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3601,42 +3836,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -3647,11 +3891,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3662,6 +3908,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3671,42 +3918,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -3717,11 +3973,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3732,6 +3990,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3741,7 +4000,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3757,11 +4018,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3777,6 +4040,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3792,21 +4056,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3819,16 +4087,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3836,11 +4107,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3849,12 +4122,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -3865,6 +4141,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3874,42 +4151,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3921,6 +4207,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3928,6 +4215,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3939,16 +4227,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3956,6 +4247,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3963,6 +4255,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3970,6 +4263,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3981,21 +4275,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4003,21 +4301,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4025,31 +4327,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4057,26 +4365,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4084,16 +4397,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4106,11 +4422,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4118,11 +4436,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4130,6 +4450,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4138,42 +4459,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4184,11 +4514,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4199,6 +4531,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4208,42 +4541,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4254,11 +4596,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4269,6 +4613,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4278,7 +4623,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4288,22 +4635,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -4319,46 +4671,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4367,12 +4728,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -4383,6 +4747,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4392,12 +4757,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4409,6 +4777,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4416,6 +4785,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4427,21 +4797,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4449,6 +4823,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4456,6 +4831,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4467,16 +4843,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4484,6 +4863,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4491,6 +4871,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4498,6 +4879,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4509,21 +4891,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4531,21 +4917,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4553,31 +4943,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4585,26 +4981,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4612,16 +5013,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4634,11 +5038,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4646,11 +5052,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4658,6 +5066,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4666,17 +5075,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4687,6 +5100,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4697,6 +5111,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -4706,6 +5121,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4716,6 +5132,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4726,16 +5143,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4746,6 +5166,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4755,17 +5176,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4776,6 +5201,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4786,6 +5212,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -4795,6 +5222,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4805,6 +5233,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4815,16 +5244,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4835,6 +5267,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4844,7 +5277,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4854,22 +5289,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -4885,46 +5325,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4933,12 +5382,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -4949,6 +5401,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4958,12 +5411,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4971,6 +5427,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4978,6 +5435,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4989,21 +5447,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5011,6 +5473,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5018,6 +5481,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5029,16 +5493,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5046,6 +5513,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5053,6 +5521,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5060,6 +5529,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5071,21 +5541,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5093,21 +5567,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5115,31 +5593,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5147,26 +5631,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5174,16 +5663,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5196,11 +5688,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5208,11 +5702,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5220,6 +5716,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5228,17 +5725,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5249,6 +5750,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5259,6 +5761,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -5268,6 +5771,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5278,6 +5782,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5288,16 +5793,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5308,6 +5816,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5317,17 +5826,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5338,6 +5851,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5348,6 +5862,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -5357,6 +5872,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5367,6 +5883,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5377,16 +5894,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5397,6 +5917,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5406,7 +5927,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5416,22 +5939,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -5447,46 +5975,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5495,12 +6032,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -5511,6 +6051,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5520,12 +6061,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5537,6 +6081,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5544,6 +6089,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5555,21 +6101,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5581,6 +6131,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5588,6 +6139,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5599,16 +6151,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5616,6 +6171,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5623,6 +6179,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5630,6 +6187,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5641,21 +6199,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5663,21 +6225,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5685,31 +6251,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5717,26 +6289,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5744,16 +6321,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5766,11 +6346,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5778,11 +6360,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5790,6 +6374,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5798,17 +6383,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5819,6 +6408,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5829,6 +6419,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -5838,6 +6429,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5848,6 +6440,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5858,16 +6451,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5878,6 +6474,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5887,17 +6484,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5908,6 +6509,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5918,6 +6520,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -5927,6 +6530,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5937,6 +6541,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5947,16 +6552,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5967,6 +6575,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5976,7 +6585,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5986,22 +6597,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -6017,46 +6633,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6065,12 +6690,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -6081,6 +6709,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6090,12 +6719,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6103,6 +6735,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6110,6 +6743,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6121,21 +6755,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6147,6 +6785,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6154,6 +6793,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6165,16 +6805,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6182,6 +6825,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6189,6 +6833,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6196,6 +6841,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6207,21 +6853,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6229,21 +6879,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6251,31 +6905,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6283,26 +6943,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6310,16 +6975,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6332,11 +7000,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6344,11 +7014,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6356,6 +7028,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6364,17 +7037,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6385,6 +7062,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6395,6 +7073,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -6404,6 +7083,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6414,6 +7094,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6424,16 +7105,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6444,6 +7128,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6453,17 +7138,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6474,6 +7163,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6484,6 +7174,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -6493,6 +7184,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6503,6 +7195,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6513,16 +7206,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6533,6 +7229,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6542,7 +7239,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -6558,11 +7257,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -6578,6 +7279,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -6593,21 +7295,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6620,16 +7326,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6637,11 +7346,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6650,12 +7361,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -6666,6 +7380,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6675,12 +7390,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6692,6 +7410,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6699,6 +7418,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6710,21 +7430,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6732,6 +7456,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6739,6 +7464,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6750,16 +7476,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6767,6 +7496,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6774,6 +7504,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6781,6 +7512,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6792,21 +7524,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6814,21 +7550,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6836,31 +7576,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6868,26 +7614,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6895,16 +7646,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6917,11 +7671,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6929,11 +7685,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6941,6 +7699,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6949,17 +7708,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6970,6 +7733,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6980,6 +7744,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -6989,6 +7754,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6999,6 +7765,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7009,16 +7776,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7029,6 +7799,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7038,17 +7809,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7059,6 +7834,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7069,6 +7845,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -7078,6 +7855,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7088,6 +7866,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7098,16 +7877,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7118,6 +7900,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7127,7 +7910,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7143,11 +7928,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7163,6 +7950,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7178,21 +7966,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7205,16 +7997,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7222,11 +8017,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7235,12 +8032,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -7251,6 +8051,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7260,12 +8061,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7273,6 +8077,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7280,6 +8085,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7291,21 +8097,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7313,6 +8123,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7320,6 +8131,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7331,16 +8143,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7348,6 +8163,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7355,6 +8171,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7362,6 +8179,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7373,21 +8191,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7395,21 +8217,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7417,31 +8243,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7449,26 +8281,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7476,16 +8313,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7498,11 +8338,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7510,11 +8352,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7522,6 +8366,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7530,17 +8375,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7551,6 +8400,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7561,6 +8411,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -7570,6 +8421,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7580,6 +8432,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7590,16 +8443,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7610,6 +8466,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7619,17 +8476,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7640,6 +8501,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7650,6 +8512,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -7659,6 +8522,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7669,6 +8533,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7679,16 +8544,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7699,6 +8567,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7708,7 +8577,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7724,11 +8595,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7744,6 +8617,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7759,21 +8633,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7786,16 +8664,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7803,11 +8684,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7816,12 +8699,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -7832,6 +8718,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7841,12 +8728,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7858,6 +8748,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7865,6 +8756,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7876,21 +8768,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7902,6 +8798,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7909,6 +8806,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7920,16 +8818,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7937,6 +8838,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7944,6 +8846,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7951,6 +8854,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7962,21 +8866,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7984,21 +8892,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8006,31 +8918,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8038,26 +8956,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8065,16 +8988,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8087,11 +9013,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8099,11 +9027,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8111,6 +9041,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8119,17 +9050,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8140,6 +9075,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8150,6 +9086,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -8159,6 +9096,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8169,6 +9107,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8179,16 +9118,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8199,6 +9141,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8208,17 +9151,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8229,6 +9176,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8239,6 +9187,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -8248,6 +9197,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8258,6 +9208,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8268,16 +9219,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8288,6 +9242,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8297,7 +9252,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8313,11 +9270,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8333,6 +9292,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8348,21 +9308,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8375,16 +9339,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8392,11 +9359,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8405,12 +9374,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -8421,6 +9393,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8430,12 +9403,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8443,6 +9419,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8450,6 +9427,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8461,21 +9439,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8487,6 +9469,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8494,6 +9477,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8505,16 +9489,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8522,6 +9509,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8529,6 +9517,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8536,6 +9525,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8547,21 +9537,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8569,21 +9563,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8591,31 +9589,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8623,26 +9627,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8650,16 +9659,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8672,11 +9684,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8684,11 +9698,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8696,6 +9712,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8704,17 +9721,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8725,6 +9746,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8735,6 +9757,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -8744,6 +9767,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8754,6 +9778,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8764,16 +9789,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8784,6 +9812,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8793,17 +9822,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8814,6 +9847,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8824,6 +9858,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -8833,6 +9868,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8843,6 +9879,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8853,16 +9890,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8873,6 +9913,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8882,17 +9923,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8905,6 +9950,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8920,6 +9966,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8935,21 +9982,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8962,6 +10013,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8969,16 +10021,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8987,12 +10042,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -9003,6 +10061,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9012,92 +10071,111 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9105,6 +10183,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9112,6 +10191,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9123,11 +10203,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9139,6 +10221,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9146,6 +10229,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9157,21 +10241,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9179,6 +10267,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9186,6 +10275,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9197,16 +10287,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9214,6 +10307,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9221,6 +10315,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9232,16 +10327,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9254,11 +10352,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9266,11 +10366,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9278,6 +10380,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9286,27 +10389,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -9316,6 +10425,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "t_ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -9326,21 +10436,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "t_ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9351,6 +10465,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9360,27 +10475,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -9390,6 +10511,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "t_ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -9400,21 +10522,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "t_ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9425,6 +10551,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9434,17 +10561,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9457,6 +10588,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -9472,6 +10604,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -9487,21 +10620,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9514,6 +10651,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9521,16 +10659,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9539,12 +10680,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -9555,6 +10699,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9564,92 +10709,111 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9657,6 +10821,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9664,6 +10829,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9675,11 +10841,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9691,6 +10859,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9698,6 +10867,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9709,21 +10879,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9735,6 +10909,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9742,6 +10917,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9753,16 +10929,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9770,6 +10949,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9777,6 +10957,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9788,16 +10969,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9810,11 +10994,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9822,11 +11008,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9834,6 +11022,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9842,27 +11031,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -9872,6 +11067,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -9882,21 +11078,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9907,6 +11107,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9916,27 +11117,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -9946,6 +11153,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -9956,21 +11164,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9981,6 +11193,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9990,17 +11203,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10013,6 +11230,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -10028,26 +11246,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10055,6 +11278,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10062,16 +11286,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10080,12 +11307,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -10096,96 +11326,116 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 18, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10193,6 +11443,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10200,6 +11451,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10211,11 +11463,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10227,6 +11481,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10234,6 +11489,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10245,21 +11501,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10267,6 +11527,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10274,6 +11535,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10285,16 +11547,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10302,6 +11567,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10309,6 +11575,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10320,16 +11587,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10342,11 +11612,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10354,11 +11626,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10366,6 +11640,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10374,7 +11649,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, stingray, table: wm_0 */ { + .description = "wc_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10387,11 +11664,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "spare", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10404,6 +11683,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10411,21 +11691,26 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "others", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10438,6 +11723,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -10453,31 +11739,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10485,6 +11777,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10492,11 +11785,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10505,12 +11800,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -10521,96 +11819,116 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 19, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10618,6 +11936,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10625,6 +11944,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10636,11 +11956,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10652,6 +11974,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10659,6 +11982,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10670,21 +11994,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10692,6 +12020,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10699,6 +12028,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10710,16 +12040,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10727,6 +12060,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10734,6 +12068,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10745,16 +12080,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10767,11 +12105,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10779,11 +12119,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10791,6 +12133,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10799,17 +12142,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dst_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10820,6 +12167,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10830,16 +12178,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -10850,6 +12201,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -10859,17 +12211,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 339, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dst_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10880,6 +12236,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10890,16 +12247,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -10910,6 +12270,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -10919,7 +12280,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10929,22 +12292,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -10960,31 +12328,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10996,16 +12370,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11014,12 +12391,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -11030,6 +12410,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11039,12 +12420,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11056,6 +12440,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11063,6 +12448,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11074,21 +12460,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11096,6 +12486,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11103,6 +12494,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11114,21 +12506,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11136,6 +12532,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11143,6 +12540,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11154,111 +12552,133 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11271,11 +12691,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11283,11 +12705,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11295,6 +12719,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11303,17 +12728,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11324,6 +12753,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11334,6 +12764,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -11343,6 +12774,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11353,6 +12785,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11363,16 +12796,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11383,6 +12819,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11392,17 +12829,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11413,6 +12854,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11423,6 +12865,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -11432,6 +12875,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11442,6 +12886,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11452,16 +12897,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11472,6 +12920,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11481,7 +12930,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11491,22 +12942,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -11522,31 +12978,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11558,16 +13020,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11576,12 +13041,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -11592,6 +13060,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11601,12 +13070,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11614,6 +13086,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11621,6 +13094,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11632,21 +13106,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11654,6 +13132,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11661,6 +13140,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11672,21 +13152,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11694,6 +13178,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11701,6 +13186,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11712,111 +13198,133 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11829,11 +13337,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11841,11 +13351,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11853,6 +13365,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11861,17 +13374,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11882,6 +13399,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11892,6 +13410,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -11901,6 +13420,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11911,6 +13431,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11921,16 +13442,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11941,6 +13465,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11950,17 +13475,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11971,6 +13500,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11981,6 +13511,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -11990,6 +13521,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12000,6 +13532,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12010,16 +13543,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12030,6 +13566,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12039,7 +13576,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12049,22 +13588,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: l2_cntxt_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -12080,31 +13624,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12116,16 +13666,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12134,12 +13687,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -12150,6 +13706,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12159,12 +13716,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12176,6 +13736,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12183,6 +13744,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12194,21 +13756,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12220,6 +13786,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12227,6 +13794,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12238,21 +13806,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12260,6 +13832,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12267,6 +13840,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12278,111 +13852,133 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12395,11 +13991,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12407,11 +14005,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12419,6 +14019,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12427,17 +14028,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12448,6 +14053,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12458,6 +14064,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -12467,6 +14074,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12477,6 +14085,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12487,16 +14096,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12507,6 +14119,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12516,17 +14129,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12537,6 +14154,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12547,6 +14165,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -12556,6 +14175,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12566,6 +14186,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12576,16 +14197,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12596,6 +14220,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12605,7 +14230,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12615,22 +14242,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -12646,31 +14278,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12682,16 +14320,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12700,12 +14341,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -12716,6 +14360,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12725,12 +14370,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12738,6 +14386,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12745,6 +14394,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12756,21 +14406,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12782,6 +14436,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12789,6 +14444,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12800,21 +14456,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12822,6 +14482,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12829,6 +14490,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12840,111 +14502,133 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12957,11 +14641,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12969,11 +14655,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12981,6 +14669,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12989,17 +14678,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13010,6 +14703,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13020,6 +14714,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -13029,6 +14724,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13039,6 +14735,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13049,16 +14746,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13069,6 +14769,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13078,17 +14779,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13099,6 +14804,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13109,6 +14815,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -13118,6 +14825,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13128,6 +14836,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13138,16 +14847,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13158,6 +14870,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13167,7 +14880,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13183,11 +14898,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13203,6 +14920,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13218,21 +14936,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13245,11 +14967,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13261,6 +14985,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13270,11 +14995,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13283,12 +15010,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -13299,6 +15029,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13308,42 +15039,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13351,6 +15091,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13358,6 +15099,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13369,16 +15111,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13386,6 +15131,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13393,6 +15139,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13400,6 +15147,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13411,21 +15159,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13433,21 +15185,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13455,31 +15211,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13487,26 +15249,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13514,16 +15281,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13536,11 +15306,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13548,11 +15320,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13560,6 +15334,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13568,27 +15343,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 351, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_eth_type", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dmac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13599,6 +15380,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13609,6 +15391,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13618,27 +15401,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_eth_type", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dmac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13649,6 +15438,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13659,6 +15449,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13668,7 +15459,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13684,11 +15477,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13704,6 +15499,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13719,21 +15515,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13746,11 +15546,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13762,6 +15564,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13771,11 +15574,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13784,12 +15589,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -13800,6 +15608,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13809,42 +15618,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, stingray, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13856,6 +15674,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13863,6 +15682,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13874,16 +15694,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13891,6 +15714,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13898,6 +15722,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13905,6 +15730,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13916,21 +15742,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13938,21 +15768,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13960,31 +15794,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13992,26 +15832,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14019,16 +15864,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14041,11 +15889,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14053,11 +15903,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14065,6 +15917,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14073,27 +15926,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, stingray, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 351, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_eth_type", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dmac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -14104,6 +15963,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -14114,6 +15974,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -14123,27 +15984,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, stingray, table: int_em_0 */ { + .description = "spare", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_eth_type", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dmac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -14154,6 +16021,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -14164,6 +16032,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -14176,83 +16045,104 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { }; struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] = { + /* class_tid: 1, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14262,30 +16152,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14294,7 +16192,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 1, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14304,6 +16204,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -14313,10 +16214,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14326,44 +16229,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 1, stingray, table: parif_def_lkup_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14372,7 +16286,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 1, stingray, table: parif_def_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14381,7 +16297,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 1, stingray, table: parif_def_err_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14390,83 +16308,104 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14476,44 +16415,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 2, stingray, table: l2_cntxt_tcam_vfr_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14523,46 +16473,57 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14571,7 +16532,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14581,6 +16544,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -14590,10 +16554,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14603,44 +16569,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14649,7 +16626,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, stingray, table: parif_def_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14658,7 +16637,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, stingray, table: parif_def_err_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14667,23 +16648,29 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, stingray, table: egr_int_vtag_encap_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -14692,21 +16679,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x81, 0x00} }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14716,50 +16707,63 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "spare", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, stingray, table: egr_int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14769,46 +16773,57 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -14818,164 +16833,206 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, stingray, table: egr_l2_cntxt_cache_0 */ + /* class_tid: 3, stingray, table: egr_l2_cntxt_tcam_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, stingray, table: ing_int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14985,32 +17042,40 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, stingray, table: ing_l2_cntxt_dtagged_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15020,58 +17085,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, stingray, table: ing_l2_cntxt_stagged_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15081,58 +17160,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15141,7 +17234,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: egr_l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15151,6 +17246,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15160,10 +17256,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15172,44 +17270,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 4, stingray, table: egr_parif_def_lkup_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15218,7 +17327,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: egr_parif_def_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15227,7 +17338,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: egr_parif_def_err_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15236,83 +17349,104 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: ing_int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -15322,30 +17456,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 4, stingray, table: ing_l2_cntxt_tcam_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15355,134 +17497,167 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 5, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15492,30 +17667,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15525,6 +17708,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15534,10 +17718,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -15547,44 +17733,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15593,19 +17790,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15615,12 +17817,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15630,16 +17834,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 6, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15649,22 +17857,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15674,26 +17886,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15703,22 +17921,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15728,26 +17950,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15757,6 +17985,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15766,10 +17995,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -15779,44 +18010,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15825,19 +18067,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15847,12 +18094,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15862,16 +18111,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 7, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15881,22 +18134,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15906,26 +18163,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15935,22 +18198,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15960,26 +18227,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15988,7 +18261,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15998,6 +18273,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16007,10 +18283,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16020,44 +18298,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16066,19 +18355,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16088,12 +18382,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16103,16 +18399,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 8, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16122,22 +18422,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16147,26 +18451,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16176,22 +18486,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16201,26 +18515,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16229,7 +18549,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16239,6 +18561,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16248,10 +18571,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16261,44 +18586,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16307,19 +18643,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16329,12 +18670,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16344,16 +18687,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 9, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16363,22 +18710,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16388,26 +18739,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16417,22 +18774,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16442,26 +18803,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16470,7 +18837,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16480,6 +18849,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16489,10 +18859,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16502,44 +18874,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16548,19 +18931,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16570,12 +18958,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16585,16 +18975,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 10, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16604,22 +18998,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16629,26 +19027,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16658,22 +19062,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16683,26 +19091,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16711,7 +19125,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16721,6 +19137,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16730,10 +19147,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16743,44 +19162,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16789,19 +19219,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16811,12 +19246,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16826,16 +19263,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 11, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16845,22 +19286,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16870,26 +19315,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16899,22 +19350,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16924,26 +19379,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16953,6 +19414,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16962,10 +19424,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16975,44 +19439,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17021,19 +19496,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17043,12 +19523,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17058,16 +19540,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 12, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17077,22 +19563,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17102,26 +19592,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17131,22 +19627,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17156,26 +19656,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17185,6 +19691,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -17194,10 +19701,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -17207,44 +19716,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17253,19 +19773,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17275,12 +19800,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17290,16 +19817,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 13, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17309,22 +19840,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17334,26 +19869,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17363,22 +19904,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17388,26 +19933,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17417,6 +19968,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -17426,10 +19978,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -17439,44 +19993,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17485,19 +20050,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17507,12 +20077,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17522,16 +20094,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 14, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17541,22 +20117,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17566,26 +20146,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17595,22 +20181,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17620,26 +20210,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17649,6 +20245,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -17658,10 +20255,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -17671,44 +20270,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17717,19 +20327,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17739,12 +20354,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17754,16 +20371,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 15, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17773,22 +20394,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17798,26 +20423,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17827,22 +20458,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17852,26 +20487,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17881,6 +20522,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -17890,10 +20532,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -17903,44 +20547,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17949,19 +20604,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17971,12 +20631,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17986,16 +20648,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 16, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18005,22 +20671,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18030,26 +20700,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18059,22 +20735,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18084,26 +20764,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18113,6 +20799,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -18122,10 +20809,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -18135,44 +20824,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18181,19 +20881,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18203,12 +20908,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18218,16 +20925,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 17, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18237,22 +20948,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18262,26 +20977,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18291,22 +21012,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18316,30 +21041,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, stingray, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18349,6 +21082,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -18358,10 +21092,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -18371,44 +21107,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18418,6 +21165,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "wc_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18426,11 +21174,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18440,12 +21191,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18455,12 +21208,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18470,22 +21225,27 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 18, stingray, table: wm_0 */ { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18495,12 +21255,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18510,6 +21273,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -18519,10 +21283,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -18532,44 +21298,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18579,6 +21356,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "wc_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18587,39 +21365,50 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 19, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18629,22 +21418,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18654,26 +21447,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18683,22 +21482,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18708,26 +21511,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18736,7 +21545,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18746,6 +21557,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -18755,10 +21567,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -18778,26 +21592,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18807,20 +21627,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18829,19 +21654,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18851,12 +21681,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18866,16 +21698,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 20, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18885,22 +21721,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18910,26 +21750,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18939,22 +21785,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18964,26 +21814,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18992,7 +21848,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19002,6 +21860,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -19011,10 +21870,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -19034,26 +21895,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19063,20 +21930,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19085,19 +21957,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19107,12 +21984,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19122,16 +22001,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 21, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19141,22 +22024,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19166,26 +22053,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19195,22 +22088,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19220,26 +22117,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19248,7 +22151,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: l2_cntxt_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19258,6 +22163,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -19267,10 +22173,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -19290,26 +22198,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19319,20 +22233,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19341,19 +22260,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19363,12 +22287,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19378,16 +22304,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 22, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19397,22 +22327,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19422,26 +22356,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19451,22 +22391,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19476,26 +22420,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19504,7 +22454,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19514,6 +22466,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -19523,10 +22476,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -19546,26 +22501,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19575,20 +22536,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19597,19 +22563,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19619,12 +22590,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19634,16 +22607,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 23, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19653,22 +22630,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19678,26 +22659,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19707,22 +22694,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19732,26 +22723,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19761,6 +22758,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -19770,10 +22768,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -19793,26 +22793,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19822,20 +22828,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19844,19 +22855,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19866,12 +22882,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19881,16 +22899,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 24, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19900,22 +22922,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19925,26 +22951,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19954,22 +22986,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19979,26 +23015,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20008,6 +23050,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -20017,10 +23060,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -20040,26 +23085,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20069,20 +23120,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20091,19 +23147,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, stingray, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -20113,12 +23174,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20128,16 +23191,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 25, stingray, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20147,22 +23214,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -20172,26 +23243,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, stingray, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20201,22 +23278,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -20226,20 +23307,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -20248,203 +23333,261 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] }; struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { + /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, @@ -20452,20 +23595,25 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { .ident_bit_pos = 0 }, { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, @@ -20473,90 +23621,115 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { .ident_bit_pos = 0 }, { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index c65b6dc159..3a66d59b5d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,6 +3,8 @@ * All rights reserved. */ +/* date: Thu Oct 15 17:28:37 2020 */ + #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" @@ -96,6 +98,11 @@ uint32_t ulp_act_prop_map_table[] = { BNXT_ULP_ACT_PROP_SZ_LAST }; +/* + * This structure has to be indexed based on the rte_flow_action_type that is + * part of DPDK. The below array is list of parsing functions for each of the + * flow actions that are supported. + */ struct bnxt_ulp_rte_act_info ulp_act_info[] = { [RTE_FLOW_ACTION_TYPE_END] = { .act_type = BNXT_ULP_ACT_TYPE_END, @@ -295,25 +302,36 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = { } }; -struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = { +/* Specifies parameters for the generic tables */ +struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 | TF_DIR_RX] = { - .num_entries = 16384 + .result_num_entries = 16384, + .result_byte_size = 6, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 | TF_DIR_TX] = { - .num_entries = 16384 + .result_num_entries = 16384, + .result_byte_size = 6, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 | TF_DIR_RX] = { - .num_entries = 16384 + .result_num_entries = 16384, + .result_byte_size = 6, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 | TF_DIR_TX] = { - .num_entries = 16384 + .result_num_entries = 16384, + .result_byte_size = 6, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; +/* device tables */ const struct ulp_template_device_tbls ulp_template_stingray_tbls[] = { [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { .tmpl_list = ulp_stingray_class_tmpl_list, @@ -329,6 +347,7 @@ const struct ulp_template_device_tbls ulp_template_stingray_tbls[] = { } }; +/* device tables */ const struct ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { .tmpl_list = ulp_wh_plus_class_tmpl_list, @@ -344,8 +363,10 @@ const struct ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { } }; +/* List of device specific parameters */ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { [BNXT_ULP_DEVICE_ID_WH_PLUS] = { + .description = "Whitney_Plus", .byte_order = BNXT_ULP_BYTE_ORDER_LE, .encap_byte_swap = 1, .int_flow_db_num_entries = 16384, @@ -364,6 +385,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { .dev_tbls = ulp_template_wh_plus_tbls }, [BNXT_ULP_DEVICE_ID_STINGRAY] = { + .description = "Stingray", .byte_order = BNXT_ULP_BYTE_ORDER_LE, .encap_byte_swap = 1, .int_flow_db_num_entries = 16384, @@ -383,6 +405,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { } }; +/* List of device specific parameters */ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { [0] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -434,6 +457,11 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { } }; +/* + * This table has to be indexed based on the rte_flow_item_type that is part of + * DPDK. The below array is list of parsing functions for each of the flow items + * that are supported. + */ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { [RTE_FLOW_ITEM_TYPE_END] = { .hdr_type = BNXT_ULP_HDR_TYPE_END, @@ -629,12 +657,17 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { } }; +/* + * The parser uses this table to map vtags_num to CFA encapsulation VTAG + * encoding. It then takes the result and stores it in act_prop[encap_vtag_type] + */ uint32_t bnxt_ulp_encap_vtag_map[] = { BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP, BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI }; +/* Lists global action records */ uint32_t ulp_glb_template_tbl[] = { BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index d9266abd3a..89f1bef75f 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -1,134 +1,187 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ +/* date: Thu Oct 15 17:28:37 2020 */ + #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" #include "ulp_rte_parser.h" +/* Mapper templates for header class list */ struct bnxt_ulp_mapper_tbl_list_info ulp_wh_plus_class_tmpl_list[] = { + /* default-vfr-[port_to_vs]:1 */ + /* class_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 0 }, + /* default-vfr-[vs_to_port]:2 */ + /* class_tid: 2, wh_plus, egress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 7, .start_tbl_idx = 6 }, + /* default-vfr-[vfrep_to_vf]:3 */ + /* class_tid: 3, wh_plus, egress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 7, .start_tbl_idx = 13 }, + /* default-vfr-[vf_to_vfrep]:4 */ + /* class_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 7, .start_tbl_idx = 20 }, + /* default-egr-[loopback_action_rec]:5 */ + /* class_tid: 5, wh_plus, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 1, .start_tbl_idx = 27 }, + /* class-ing-em-[eth, (vlan), ipv4]-[smac, dmac, (vid)]:6 */ + /* class_tid: 6, wh_plus, ingress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 28 }, + /* class-ing-em-[eth, (vlan), ipv6]-[smac, dmac, (vid)]:7 */ + /* class_tid: 7, wh_plus, ingress */ [7] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 33 }, + /* class-ing-em-[eth, ipv4, udp]-[sip, dip, sp, dp]:8 */ + /* class_tid: 8, wh_plus, ingress */ [8] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 38 }, + /* class-ing-em-[eth, ipv4, tcp]-[sip, dip, sp, dp]:9 */ + /* class_tid: 9, wh_plus, ingress */ [9] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 44 }, + /* class-ing-em-[eth,ipv6, udp]-[sip, dip, sp, dp]:10 */ + /* class_tid: 10, wh_plus, ingress */ [10] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 50 }, + /* class-ing-em-[eth, ipv6, tcp]-[sip, dip, sp, dp]:11 */ + /* class_tid: 11, wh_plus, ingress */ [11] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 56 }, + /* class-ing-em-[eth, (vlan), ipv4, udp]-[dmac, (vid), sip, dip, sp, dp]:12 */ + /* class_tid: 12, wh_plus, ingress */ [12] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 62 }, + /* class-ing-em-[eth, (vlan), ipv4, tcp]-[dmac, (vid), sip, dip, sp, dp]:13 */ + /* class_tid: 13, wh_plus, ingress */ [13] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 67 }, + /* class-ing-em-[eth, (vlan), ipv6, udp]-[dmac, (vid), sip, dip, sp, dp]:14 */ + /* class_tid: 14, wh_plus, ingress */ [14] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 72 }, + /* class-ing-em-[eth, (vlan), ipv6, tcp]-[dmac, (vid), sip, dip, sp, dp]:15 */ + /* class_tid: 15, wh_plus, ingress */ [15] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 77 }, + /* class-ing-em-[eth, (vlan), ipv4, udp, vxlan]-[dmac, (vid), dip, dp]:16 */ + /* class_tid: 16, wh_plus, ingress */ [16] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 82 }, + /* class-ing-em-[eth, (vlan), ipv6, udp, vxlan]-[t_dmac, (vid), t_dip, t_dp]:17 */ + /* class_tid: 17, wh_plus, ingress */ [17] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 87 }, + /* class-ing-em-f1-[eth, ipv4, udp, vxlan]-[t_dmac]:18 */ + /* class_tid: 18, wh_plus, ingress */ [18] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 92 }, + /* class-ing-em-f2-[ipv4, udp, vxlan]-[vni, i_dmac]:19 */ + /* class_tid: 19, wh_plus, ingress */ [19] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 97 }, + /* class-egr-em-[eth, ipv4, udp]-[sip, dip, sp, dp]:20 */ + /* class_tid: 20, wh_plus, egress */ [20] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 102 }, + /* class-egr-em-[eth, ipv4, tcp]-[sip, dip, sp, dp]:21 */ + /* class_tid: 21, wh_plus, egress */ [21] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 108 }, + /* class-egr-em-[eth-ipv6-udp]-[sip-dip-sp-dp]:22 */ + /* class_tid: 22, wh_plus, egress */ [22] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 114 }, + /* class-egr-em-[eth, ipv6, tcp]-[sip, dip, sp, dp]:23 */ + /* class_tid: 23, wh_plus, egress */ [23] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 120 }, + /* class-egr-em-[eth, (vlan), ipv4]-[smac, dmac, type]:24 */ + /* class_tid: 24, wh_plus, egress */ [24] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, .start_tbl_idx = 126 }, + /* class-egr-em-[eth, (vlan), ipv6]-[smac, dmac, type]:25 */ + /* class_tid: 25, wh_plus, egress */ [25] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, @@ -137,7 +190,7 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_wh_plus_class_tmpl_list[] = { }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { - { + { /* class_tid: 1, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -152,8 +205,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -169,7 +222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 0, .ident_nums = 1 }, - { + { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -188,7 +241,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 1, wh_plus, table: parif_def_lkup_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -199,7 +252,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, - { + { /* class_tid: 1, wh_plus, table: parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -210,7 +263,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, - { + { /* class_tid: 1, wh_plus, table: parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -221,7 +274,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, - { + { /* class_tid: 2, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -236,7 +289,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, @@ -257,8 +310,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -276,7 +329,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 1, .ident_nums = 1 }, - { + { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET, @@ -297,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -308,7 +361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, - { + { /* class_tid: 2, wh_plus, table: parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -319,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, - { + { /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -330,7 +383,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, - { + { /* class_tid: 3, wh_plus, table: egr_int_vtag_encap_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = @@ -345,7 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, - { + { /* class_tid: 3, wh_plus, table: egr_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -360,8 +413,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 3, wh_plus, table: egr_l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -377,7 +430,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 2, .ident_nums = 0 }, - { + { /* class_tid: 3, wh_plus, table: egr_l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -396,7 +449,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 3, wh_plus, table: ing_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -411,7 +464,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* class_tid: 3, wh_plus, table: ing_l2_cntxt_dtagged_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -430,7 +483,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 3, wh_plus, table: ing_l2_cntxt_stagged_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -449,8 +502,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -466,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 2, .ident_nums = 1 }, - { + { /* class_tid: 4, wh_plus, table: egr_l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -485,7 +538,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 4, wh_plus, table: egr_parif_def_lkup_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -496,7 +549,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, - { + { /* class_tid: 4, wh_plus, table: egr_parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -507,7 +560,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, - { + { /* class_tid: 4, wh_plus, table: egr_parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -518,7 +571,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, - { + { /* class_tid: 4, wh_plus, table: ing_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -533,7 +586,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* class_tid: 4, wh_plus, table: ing_l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -552,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 5, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -567,7 +620,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR }, - { + { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -586,8 +639,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -603,7 +656,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 4, .ident_nums = 1 }, - { + { /* class_tid: 6, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -622,7 +675,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 6, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -640,7 +693,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 6, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -658,7 +711,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -677,8 +730,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -694,7 +747,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 6, .ident_nums = 1 }, - { + { /* class_tid: 7, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -713,7 +766,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 7, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -731,7 +784,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 7, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -749,8 +802,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -766,7 +819,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 7, .ident_nums = 1 }, - { + { /* class_tid: 8, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -785,8 +838,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -802,7 +855,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 8, .ident_nums = 1 }, - { + { /* class_tid: 8, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -821,7 +874,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 8, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -839,7 +892,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 8, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -857,8 +910,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -874,7 +927,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 9, .ident_nums = 1 }, - { + { /* class_tid: 9, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -893,8 +946,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -910,7 +963,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 10, .ident_nums = 1 }, - { + { /* class_tid: 9, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -929,7 +982,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 9, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -947,7 +1000,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 9, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -965,8 +1018,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -982,7 +1035,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 11, .ident_nums = 1 }, - { + { /* class_tid: 10, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -1001,8 +1054,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1018,7 +1071,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 12, .ident_nums = 1 }, - { + { /* class_tid: 10, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1037,7 +1090,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 10, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1055,7 +1108,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 10, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1073,8 +1126,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -1090,7 +1143,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 13, .ident_nums = 1 }, - { + { /* class_tid: 11, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -1109,8 +1162,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1126,7 +1179,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 14, .ident_nums = 1 }, - { + { /* class_tid: 11, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1145,7 +1198,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 11, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1163,7 +1216,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 11, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1181,7 +1234,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1200,8 +1253,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1217,7 +1270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 16, .ident_nums = 1 }, - { + { /* class_tid: 12, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1236,7 +1289,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 12, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1254,7 +1307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 12, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1272,7 +1325,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1291,8 +1344,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1308,7 +1361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 18, .ident_nums = 1 }, - { + { /* class_tid: 13, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1327,7 +1380,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 13, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1345,7 +1398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 13, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1363,7 +1416,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1382,8 +1435,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1399,7 +1452,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 20, .ident_nums = 1 }, - { + { /* class_tid: 14, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1418,7 +1471,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 14, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1436,7 +1489,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 14, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1454,7 +1507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1473,8 +1526,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1490,7 +1543,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 22, .ident_nums = 1 }, - { + { /* class_tid: 15, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1509,7 +1562,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 15, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1527,7 +1580,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 15, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1545,7 +1598,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1564,8 +1617,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1581,7 +1634,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 24, .ident_nums = 1 }, - { + { /* class_tid: 16, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1600,7 +1653,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 16, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1618,7 +1671,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 16, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1636,7 +1689,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1655,8 +1708,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1672,7 +1725,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 26, .ident_nums = 1 }, - { + { /* class_tid: 17, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1691,7 +1744,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 17, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1709,7 +1762,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 17, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1727,7 +1780,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 18, wh_plus, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -1744,7 +1797,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1763,8 +1816,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1780,7 +1833,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 28, .ident_nums = 2 }, - { + { /* class_tid: 18, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1799,7 +1852,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 18, wh_plus, table: wm_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .direction = TF_DIR_RX, @@ -1818,7 +1871,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1837,8 +1890,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1854,7 +1907,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 31, .ident_nums = 2 }, - { + { /* class_tid: 19, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -1873,7 +1926,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 19, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -1891,7 +1944,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 19, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1909,8 +1962,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -1926,7 +1979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 33, .ident_nums = 1 }, - { + { /* class_tid: 20, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1945,8 +1998,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -1962,7 +2015,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 34, .ident_nums = 1 }, - { + { /* class_tid: 20, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -1981,7 +2034,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 20, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -1999,7 +2052,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 20, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2017,8 +2070,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -2034,7 +2087,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 35, .ident_nums = 1 }, - { + { /* class_tid: 21, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -2053,8 +2106,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2070,7 +2123,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 36, .ident_nums = 1 }, - { + { /* class_tid: 21, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2089,7 +2142,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 21, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2107,7 +2160,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 21, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2125,8 +2178,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -2142,7 +2195,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 37, .ident_nums = 1 }, - { + { /* class_tid: 22, wh_plus, table: l2_cntxt_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -2161,8 +2214,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2178,7 +2231,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 38, .ident_nums = 1 }, - { + { /* class_tid: 22, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2197,7 +2250,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 22, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2215,7 +2268,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 22, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2233,8 +2286,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, @@ -2250,7 +2303,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 39, .ident_nums = 1 }, - { + { /* class_tid: 23, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -2269,8 +2322,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2286,7 +2339,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 40, .ident_nums = 1 }, - { + { /* class_tid: 23, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2305,7 +2358,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 23, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2323,7 +2376,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 23, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2341,7 +2394,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, @@ -2360,8 +2413,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2377,7 +2430,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 42, .ident_nums = 1 }, - { + { /* class_tid: 24, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2396,7 +2449,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 24, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2414,7 +2467,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 24, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2432,7 +2485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, @@ -2451,8 +2504,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + { /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, @@ -2468,7 +2521,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 44, .ident_nums = 1 }, - { + { /* class_tid: 25, wh_plus, table: profile_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -2487,7 +2540,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, - { + { /* class_tid: 25, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, @@ -2505,7 +2558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, - { + { /* class_tid: 25, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, @@ -2526,7 +2579,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }; struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, @@ -2536,22 +2591,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2564,46 +2624,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2612,22 +2681,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_vfr_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2640,46 +2714,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2688,7 +2771,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, @@ -2698,22 +2783,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2726,46 +2816,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2774,7 +2873,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, wh_plus, table: egr_l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, @@ -2784,22 +2885,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, wh_plus, table: egr_l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2812,46 +2918,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2860,12 +2975,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, wh_plus, table: ing_l2_cntxt_dtagged_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2878,11 +2996,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2895,26 +3015,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2924,11 +3049,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2940,11 +3067,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2953,7 +3082,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, wh_plus, table: ing_l2_cntxt_stagged_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2966,16 +3097,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2988,26 +3122,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3017,11 +3156,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3033,11 +3174,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3046,7 +3189,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, @@ -3056,22 +3201,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: egr_l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3084,46 +3234,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3132,22 +3291,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: ing_l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3160,46 +3324,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3208,7 +3381,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3224,11 +3399,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3244,6 +3421,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3259,26 +3437,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3291,16 +3474,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3308,6 +3494,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3316,12 +3503,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -3332,6 +3522,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3341,42 +3532,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3384,6 +3584,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3391,6 +3592,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3402,16 +3604,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3419,6 +3624,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3426,6 +3632,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3433,6 +3640,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3444,21 +3652,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3466,21 +3678,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3488,31 +3704,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3520,26 +3742,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3547,16 +3774,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3569,11 +3799,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3581,11 +3813,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3593,6 +3827,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3601,42 +3836,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -3647,11 +3891,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3662,6 +3908,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3671,42 +3918,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -3717,11 +3973,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3732,6 +3990,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3741,7 +4000,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3757,11 +4018,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3777,6 +4040,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -3792,26 +4056,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3824,16 +4093,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3841,6 +4113,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3849,12 +4122,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -3865,6 +4141,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -3874,42 +4151,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3921,6 +4207,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3928,6 +4215,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3939,16 +4227,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3956,6 +4247,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3963,6 +4255,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3970,6 +4263,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -3981,21 +4275,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4003,21 +4301,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4025,31 +4327,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4057,26 +4365,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4084,16 +4397,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4106,11 +4422,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4118,11 +4436,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4130,6 +4450,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4138,42 +4459,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4184,11 +4514,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4199,6 +4531,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4208,42 +4541,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4254,11 +4596,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4269,6 +4613,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4278,7 +4623,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4288,22 +4635,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -4319,46 +4671,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4367,12 +4728,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -4383,6 +4747,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4392,12 +4757,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4409,6 +4777,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4416,6 +4785,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4427,21 +4797,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4449,6 +4823,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4456,6 +4831,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4467,16 +4843,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4484,6 +4863,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4491,6 +4871,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4498,6 +4879,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4509,21 +4891,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4531,21 +4917,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4553,31 +4943,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4585,26 +4981,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4612,16 +5013,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4634,11 +5038,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4646,11 +5052,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4658,6 +5066,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4666,17 +5075,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4687,6 +5100,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4697,6 +5111,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -4706,6 +5121,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4716,6 +5132,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4726,16 +5143,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4746,6 +5166,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4755,17 +5176,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4776,6 +5201,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4786,6 +5212,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -4795,6 +5222,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4805,6 +5233,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4815,16 +5244,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4835,6 +5267,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4844,7 +5277,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -4854,22 +5289,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -4885,46 +5325,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4933,12 +5382,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -4949,6 +5401,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -4958,12 +5411,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4971,6 +5427,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4978,6 +5435,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -4989,21 +5447,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5011,6 +5473,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5018,6 +5481,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5029,16 +5493,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5046,6 +5513,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5053,6 +5521,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5060,6 +5529,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5071,21 +5541,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5093,21 +5567,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5115,31 +5593,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5147,26 +5631,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5174,16 +5663,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5196,11 +5688,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5208,11 +5702,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5220,6 +5716,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5228,17 +5725,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5249,6 +5750,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5259,6 +5761,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -5268,6 +5771,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5278,6 +5782,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5288,16 +5793,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5308,6 +5816,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5317,17 +5826,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5338,6 +5851,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5348,6 +5862,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -5357,6 +5872,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5367,6 +5883,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5377,16 +5894,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5397,6 +5917,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5406,7 +5927,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5416,22 +5939,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -5447,46 +5975,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5495,12 +6032,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -5511,6 +6051,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5520,12 +6061,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5537,6 +6081,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5544,6 +6089,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5555,21 +6101,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5581,6 +6131,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5588,6 +6139,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5599,16 +6151,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5616,6 +6171,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5623,6 +6179,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5630,6 +6187,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5641,21 +6199,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5663,21 +6225,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5685,31 +6251,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5717,26 +6289,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5744,16 +6321,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5766,11 +6346,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5778,11 +6360,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5790,6 +6374,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -5798,17 +6383,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5819,6 +6408,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5829,6 +6419,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -5838,6 +6429,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5848,6 +6440,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5858,16 +6451,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5878,6 +6474,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5887,17 +6484,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5908,6 +6509,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5918,6 +6520,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -5927,6 +6530,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5937,6 +6541,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5947,16 +6552,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5967,6 +6575,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -5976,7 +6585,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -5986,22 +6597,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -6017,46 +6633,55 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6065,12 +6690,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -6081,6 +6709,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6090,12 +6719,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6103,6 +6735,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6110,6 +6743,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6121,21 +6755,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6147,6 +6785,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6154,6 +6793,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6165,16 +6805,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6182,6 +6825,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6189,6 +6833,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6196,6 +6841,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6207,21 +6853,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6229,21 +6879,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6251,31 +6905,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6283,26 +6943,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6310,16 +6975,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6332,11 +7000,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6344,11 +7014,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6356,6 +7028,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6364,17 +7037,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6385,6 +7062,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6395,6 +7073,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -6404,6 +7083,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6414,6 +7094,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6424,16 +7105,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6444,6 +7128,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6453,17 +7138,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6474,6 +7163,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6484,6 +7174,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -6493,6 +7184,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6503,6 +7195,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6513,16 +7206,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6533,6 +7229,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6542,7 +7239,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -6558,11 +7257,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -6578,6 +7279,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -6593,26 +7295,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6625,16 +7332,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6642,6 +7352,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6650,12 +7361,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -6666,6 +7380,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -6675,12 +7390,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6692,6 +7410,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6699,6 +7418,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6710,21 +7430,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6732,6 +7456,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6739,6 +7464,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6750,16 +7476,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6767,6 +7496,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6774,6 +7504,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6781,6 +7512,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6792,21 +7524,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6814,21 +7550,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6836,31 +7576,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6868,26 +7614,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6895,16 +7646,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6917,11 +7671,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6929,11 +7685,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6941,6 +7699,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -6949,17 +7708,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6970,6 +7733,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6980,6 +7744,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -6989,6 +7754,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -6999,6 +7765,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7009,16 +7776,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7029,6 +7799,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7038,17 +7809,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7059,6 +7834,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7069,6 +7845,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -7078,6 +7855,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7088,6 +7866,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7098,16 +7877,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7118,6 +7900,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7127,7 +7910,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7143,11 +7928,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7163,6 +7950,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7178,26 +7966,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7210,16 +8003,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7227,6 +8023,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7235,12 +8032,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -7251,6 +8051,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7260,12 +8061,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7273,6 +8077,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7280,6 +8085,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7291,21 +8097,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7313,6 +8123,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7320,6 +8131,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7331,16 +8143,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7348,6 +8163,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7355,6 +8171,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7362,6 +8179,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7373,21 +8191,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7395,21 +8217,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7417,31 +8243,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7449,26 +8281,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7476,16 +8313,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7498,11 +8338,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7510,11 +8352,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7522,6 +8366,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7530,17 +8375,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7551,6 +8400,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7561,6 +8411,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -7570,6 +8421,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7580,6 +8432,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7590,16 +8443,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7610,6 +8466,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7619,17 +8476,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7640,6 +8501,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7650,6 +8512,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -7659,6 +8522,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7669,6 +8533,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -7679,16 +8544,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7699,6 +8567,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7708,7 +8577,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7724,11 +8595,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7744,6 +8617,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -7759,26 +8633,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7791,16 +8670,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7808,6 +8690,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7816,12 +8699,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -7832,6 +8718,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -7841,12 +8728,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7858,6 +8748,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7865,6 +8756,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7876,21 +8768,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7902,6 +8798,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7909,6 +8806,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7920,16 +8818,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7937,6 +8838,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7944,6 +8846,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7951,6 +8854,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7962,21 +8866,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -7984,21 +8892,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8006,31 +8918,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8038,26 +8956,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8065,16 +8988,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8087,11 +9013,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8099,11 +9027,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8111,6 +9041,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8119,17 +9050,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8140,6 +9075,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8150,6 +9086,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -8159,6 +9096,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8169,6 +9107,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8179,16 +9118,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8199,6 +9141,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8208,17 +9151,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8229,6 +9176,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8239,6 +9187,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -8248,6 +9197,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8258,6 +9208,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8268,16 +9219,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8288,6 +9242,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8297,7 +9252,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8313,11 +9270,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8333,6 +9292,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8348,26 +9308,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8380,16 +9345,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8397,6 +9365,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8405,12 +9374,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -8421,6 +9393,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8430,12 +9403,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8443,6 +9419,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8450,6 +9427,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8461,21 +9439,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8487,6 +9469,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8494,6 +9477,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8505,16 +9489,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8522,6 +9509,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8529,6 +9517,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8536,6 +9525,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8547,21 +9537,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8569,21 +9563,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8591,31 +9589,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8623,26 +9627,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8650,16 +9659,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8672,11 +9684,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8684,11 +9698,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8696,6 +9712,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8704,17 +9721,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8725,6 +9746,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8735,6 +9757,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -8744,6 +9767,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8754,6 +9778,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8764,16 +9789,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8784,6 +9812,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8793,17 +9822,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8814,6 +9847,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8824,6 +9858,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -8833,6 +9868,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8843,6 +9879,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -8853,16 +9890,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8873,6 +9913,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -8882,17 +9923,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8905,6 +9950,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8920,11 +9966,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -8940,21 +9988,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8967,6 +10019,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8974,11 +10027,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -8987,12 +10042,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -9003,6 +10061,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9012,92 +10071,111 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9105,6 +10183,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9112,6 +10191,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9123,11 +10203,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9139,6 +10221,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9146,6 +10229,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9157,21 +10241,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9179,6 +10267,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9186,6 +10275,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9197,16 +10287,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9214,6 +10307,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9221,6 +10315,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9232,16 +10327,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9254,11 +10352,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9266,11 +10366,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9278,6 +10380,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9286,27 +10389,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -9316,6 +10425,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "t_ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -9326,21 +10436,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "t_ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9351,6 +10465,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9360,27 +10475,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -9390,6 +10511,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "t_ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -9400,21 +10522,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "t_ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "t_l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9425,6 +10551,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9434,17 +10561,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9457,6 +10588,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -9472,11 +10604,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -9492,21 +10626,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9519,6 +10657,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9526,11 +10665,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9539,12 +10680,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -9555,6 +10699,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9564,92 +10709,111 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9657,6 +10821,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9664,6 +10829,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9675,11 +10841,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9691,6 +10859,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9698,6 +10867,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9709,21 +10879,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9735,6 +10909,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9742,6 +10917,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9753,16 +10929,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9770,6 +10949,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9777,6 +10957,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9788,16 +10969,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9810,11 +10994,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9822,11 +11008,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9834,6 +11022,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -9842,27 +11031,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -9872,6 +11067,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -9882,21 +11078,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9907,6 +11107,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9916,27 +11117,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -9946,6 +11153,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -9956,21 +11164,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9981,6 +11193,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -9990,17 +11203,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10013,6 +11230,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -10028,31 +11246,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10060,6 +11284,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10067,11 +11292,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10080,12 +11307,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -10096,96 +11326,116 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 18, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10193,6 +11443,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10200,6 +11451,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10211,11 +11463,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10227,6 +11481,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10234,6 +11489,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10245,21 +11501,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10267,6 +11527,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10274,6 +11535,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10285,16 +11547,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10302,6 +11567,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10309,6 +11575,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10320,16 +11587,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10342,11 +11612,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10354,11 +11626,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10366,6 +11640,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10374,7 +11649,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, wh_plus, table: wm_0 */ { + .description = "wc_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10387,11 +11664,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "spare", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10404,6 +11683,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10411,21 +11691,26 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "others", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10438,6 +11723,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -10453,31 +11739,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10485,6 +11777,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10492,11 +11785,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10505,12 +11800,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -10521,96 +11819,116 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 19, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10618,6 +11936,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10625,6 +11944,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10636,11 +11956,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10652,6 +11974,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10659,6 +11982,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10670,21 +11994,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10692,6 +12020,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10699,6 +12028,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10710,16 +12040,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10727,6 +12060,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10734,6 +12068,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10745,16 +12080,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10767,11 +12105,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10779,11 +12119,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10791,6 +12133,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -10799,17 +12142,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dst_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10820,6 +12167,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10830,16 +12178,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -10850,6 +12201,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -10859,17 +12211,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 339, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dst_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10880,6 +12236,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10890,16 +12247,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -10910,6 +12270,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -10919,7 +12280,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -10929,22 +12292,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -10960,36 +12328,43 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11001,11 +12376,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11014,12 +12391,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -11030,6 +12410,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11039,12 +12420,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11056,6 +12440,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11063,6 +12448,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11074,21 +12460,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11096,6 +12486,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11103,6 +12494,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11114,21 +12506,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11136,6 +12532,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11143,6 +12540,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11154,111 +12552,133 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11271,11 +12691,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11283,11 +12705,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11295,6 +12719,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11303,17 +12728,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11324,6 +12753,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11334,6 +12764,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -11343,6 +12774,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11353,6 +12785,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11363,16 +12796,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11383,6 +12819,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11392,17 +12829,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11413,6 +12854,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11423,6 +12865,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -11432,6 +12875,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11442,6 +12886,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11452,16 +12897,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11472,6 +12920,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11481,7 +12930,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11491,22 +12942,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -11522,36 +12978,43 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11563,11 +13026,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11576,12 +13041,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -11592,6 +13060,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11601,12 +13070,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11614,6 +13086,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11621,6 +13094,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11632,21 +13106,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11654,6 +13132,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11661,6 +13140,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11672,21 +13152,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11694,6 +13178,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11701,6 +13186,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11712,111 +13198,133 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11829,11 +13337,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11841,11 +13351,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11853,6 +13365,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -11861,17 +13374,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 251, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11882,6 +13399,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11892,6 +13410,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -11901,6 +13420,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11911,6 +13431,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11921,16 +13442,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11941,6 +13465,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -11950,17 +13475,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11971,6 +13500,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -11981,6 +13511,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -11990,6 +13521,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_dst_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12000,6 +13532,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12010,16 +13543,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12030,6 +13566,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12039,7 +13576,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12049,22 +13588,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: l2_cntxt_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -12080,36 +13624,43 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12121,11 +13672,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12134,12 +13687,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -12150,6 +13706,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12159,12 +13716,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12176,6 +13736,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12183,6 +13744,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12194,21 +13756,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12220,6 +13786,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12227,6 +13794,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12238,21 +13806,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12260,6 +13832,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12267,6 +13840,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12278,111 +13852,133 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12395,11 +13991,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12407,11 +14005,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12419,6 +14019,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12427,17 +14028,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12448,6 +14053,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12458,6 +14064,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -12467,6 +14074,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12477,6 +14085,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12487,16 +14096,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12507,6 +14119,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12516,17 +14129,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12537,6 +14154,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12547,6 +14165,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -12556,6 +14175,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12566,6 +14186,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12576,16 +14197,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12596,6 +14220,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12605,7 +14230,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -12615,22 +14242,27 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -12646,36 +14278,43 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_tl2_dst", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12687,11 +14326,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12700,12 +14341,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -12716,6 +14360,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -12725,12 +14370,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12738,6 +14386,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12745,6 +14394,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12756,21 +14406,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12782,6 +14436,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12789,6 +14444,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12800,21 +14456,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12822,6 +14482,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12829,6 +14490,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12840,111 +14502,133 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12957,11 +14641,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12969,11 +14655,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12981,6 +14669,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -12989,17 +14678,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 59, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13010,6 +14703,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13020,6 +14714,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -13029,6 +14724,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13039,6 +14735,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13049,16 +14746,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13069,6 +14769,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13078,17 +14779,21 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_dst_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13099,6 +14804,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l4_src_port", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13109,6 +14815,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ip_proto", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, @@ -13118,6 +14825,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_dst_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13128,6 +14836,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13138,16 +14847,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_src_mac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_id", .field_bit_size = 24, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13158,6 +14870,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13167,7 +14880,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13183,11 +14898,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13203,6 +14920,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13218,26 +14936,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13250,11 +14973,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13266,6 +14991,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13275,6 +15001,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13283,12 +15010,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -13299,6 +15029,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13308,42 +15039,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13351,6 +15091,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13358,6 +15099,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13369,16 +15111,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13386,6 +15131,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13393,6 +15139,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13400,6 +15147,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13411,21 +15159,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13433,21 +15185,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13455,31 +15211,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13487,26 +15249,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13514,16 +15281,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13536,11 +15306,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13548,11 +15320,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13560,6 +15334,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13568,27 +15343,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 351, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_eth_type", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dmac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13599,6 +15380,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13609,6 +15391,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13618,27 +15401,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_eth_type", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dmac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -13649,6 +15438,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13659,6 +15449,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13668,7 +15459,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13684,11 +15477,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac0_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13704,6 +15499,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "svif", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, .mask_operand = { @@ -13719,26 +15515,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sparif", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ivlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_ovlan_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mac1_l2_addr", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13751,11 +15552,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl2_num_vtags", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13767,6 +15570,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13776,6 +15580,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13784,12 +15589,15 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ { + .description = "recycle", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, @@ -13800,6 +15608,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "class_tid", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -13809,42 +15618,51 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, wh_plus, table: profile_tcam_0 */ { + .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13856,6 +15674,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13863,6 +15682,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13874,16 +15694,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13891,6 +15714,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13898,6 +15722,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13905,6 +15730,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13916,21 +15742,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tun_hdr_flags", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tun_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13938,21 +15768,25 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl4_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13960,31 +15794,37 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_isIP", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_type", .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -13992,26 +15832,31 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_two_vtags", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_vtag_present", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_uc_mc_bc", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_type", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl2_hdr_valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14019,16 +15864,19 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hrec_next", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "prof_func_id", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14041,11 +15889,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "agg_error", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "recycle_cnt", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14053,11 +15903,13 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_0", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pkt_type_1", .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14065,6 +15917,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -14073,27 +15926,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, wh_plus, table: ext_em_0 */ { + .description = "spare", .field_bit_size = 351, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_eth_type", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dmac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -14104,6 +15963,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -14114,6 +15974,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -14123,27 +15984,33 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, wh_plus, table: int_em_0 */ { + .description = "spare", .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "local_cos", .field_bit_size = 3, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_eth_type", .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_inner_vid", .field_bit_size = 12, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_dmac", .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, @@ -14154,6 +16021,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_cntxt_id", .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -14164,6 +16032,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, @@ -14176,83 +16045,104 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { }; struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = { + /* class_tid: 1, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14262,30 +16152,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14294,7 +16192,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14304,6 +16204,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -14313,10 +16214,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14326,44 +16229,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 1, wh_plus, table: parif_def_lkup_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14372,7 +16286,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 1, wh_plus, table: parif_def_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14381,7 +16297,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 1, wh_plus, table: parif_def_err_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14390,83 +16308,104 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14476,44 +16415,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_vfr_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14523,46 +16473,57 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14571,7 +16532,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14581,6 +16544,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -14590,10 +16554,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14603,44 +16569,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14649,7 +16626,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, wh_plus, table: parif_def_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14658,7 +16637,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14667,23 +16648,29 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 3, wh_plus, table: egr_int_vtag_encap_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -14692,21 +16679,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x81, 0x00} }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14716,50 +16707,63 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "spare", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, wh_plus, table: egr_int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -14769,46 +16773,57 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -14818,164 +16833,206 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, wh_plus, table: egr_l2_cntxt_cache_0 */ + /* class_tid: 3, wh_plus, table: egr_l2_cntxt_tcam_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, wh_plus, table: ing_int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -14985,32 +17042,40 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, wh_plus, table: ing_l2_cntxt_dtagged_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15020,58 +17085,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 3, wh_plus, table: ing_l2_cntxt_stagged_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15081,58 +17160,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15141,7 +17234,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: egr_l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15151,6 +17246,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15160,10 +17256,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15172,44 +17270,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 4, wh_plus, table: egr_parif_def_lkup_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15218,7 +17327,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: egr_parif_def_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15227,7 +17338,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: egr_parif_def_err_arec_ptr_0 */ { + .description = "act_rec_ptr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15236,83 +17349,104 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: ing_int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -15322,30 +17456,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 4, wh_plus, table: ing_l2_cntxt_tcam_0 */ { + .description = "act_record_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15355,134 +17497,167 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 5, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15492,30 +17667,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15525,6 +17708,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15534,10 +17718,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -15547,44 +17733,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15593,19 +17790,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15615,12 +17817,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15630,16 +17834,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 6, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15649,22 +17857,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15674,26 +17886,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15703,22 +17921,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15728,26 +17950,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15757,6 +17985,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -15766,10 +17995,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -15779,44 +18010,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15825,19 +18067,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15847,12 +18094,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15862,16 +18111,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 7, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15881,22 +18134,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15906,26 +18163,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 7, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15935,22 +18198,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -15960,26 +18227,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15988,7 +18261,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -15998,6 +18273,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16007,10 +18283,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16020,44 +18298,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16066,19 +18355,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16088,12 +18382,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16103,16 +18399,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 8, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16122,22 +18422,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16147,26 +18451,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 8, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16176,22 +18486,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16201,26 +18515,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16229,7 +18549,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16239,6 +18561,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16248,10 +18571,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16261,44 +18586,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16307,19 +18643,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16329,12 +18670,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16344,16 +18687,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 9, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16363,22 +18710,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16388,26 +18739,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 9, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16417,22 +18774,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16442,26 +18803,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16470,7 +18837,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16480,6 +18849,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16489,10 +18859,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16502,44 +18874,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16548,19 +18931,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16570,12 +18958,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16585,16 +18975,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 10, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16604,22 +18998,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16629,26 +19027,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 10, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16658,22 +19062,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16683,26 +19091,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16711,7 +19125,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16721,6 +19137,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16730,10 +19147,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16743,44 +19162,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16789,19 +19219,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16811,12 +19246,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16826,16 +19263,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 11, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16845,22 +19286,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16870,26 +19315,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 11, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16899,22 +19350,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -16924,26 +19379,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -16953,6 +19414,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -16962,10 +19424,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -16975,44 +19439,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17021,19 +19496,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17043,12 +19523,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17058,16 +19540,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 12, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17077,22 +19563,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17102,26 +19592,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 12, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17131,22 +19627,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17156,26 +19656,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17185,6 +19691,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -17194,10 +19701,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -17207,44 +19716,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17253,19 +19773,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17275,12 +19800,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17290,16 +19817,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 13, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17309,22 +19840,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17334,26 +19869,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 13, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17363,22 +19904,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17388,26 +19933,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17417,6 +19968,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -17426,10 +19978,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -17439,44 +19993,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17485,19 +20050,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17507,12 +20077,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17522,16 +20094,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 14, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17541,22 +20117,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17566,26 +20146,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 14, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17595,22 +20181,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17620,26 +20210,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17649,6 +20245,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -17658,10 +20255,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -17671,44 +20270,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17717,19 +20327,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17739,12 +20354,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17754,16 +20371,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 15, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17773,22 +20394,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17798,26 +20423,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 15, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17827,22 +20458,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17852,26 +20487,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17881,6 +20522,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -17890,10 +20532,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -17903,44 +20547,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17949,19 +20604,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -17971,12 +20631,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -17986,16 +20648,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 16, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18005,22 +20671,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18030,26 +20700,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 16, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18059,22 +20735,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18084,26 +20764,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18113,6 +20799,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -18122,10 +20809,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -18135,44 +20824,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18181,19 +20881,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18203,12 +20908,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18218,16 +20925,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 17, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18237,22 +20948,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18262,26 +20977,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 17, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18291,22 +21012,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18316,30 +21041,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, wh_plus, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18349,6 +21082,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -18358,10 +21092,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -18371,44 +21107,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18418,6 +21165,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "wc_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18426,11 +21174,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 18, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18440,12 +21191,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18455,12 +21208,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18470,22 +21225,27 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 18, wh_plus, table: wm_0 */ { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18495,12 +21255,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18510,6 +21273,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -18519,10 +21283,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -18532,44 +21298,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18579,6 +21356,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "wc_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18587,39 +21365,50 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 19, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18629,22 +21418,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18654,26 +21447,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 19, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18683,22 +21482,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18708,26 +21511,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18736,7 +21545,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18746,6 +21557,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -18755,10 +21567,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -18778,26 +21592,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18807,20 +21627,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18829,19 +21654,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18851,12 +21681,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18866,16 +21698,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 20, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18885,22 +21721,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18910,26 +21750,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 20, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18939,22 +21785,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -18964,26 +21814,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -18992,7 +21848,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19002,6 +21860,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -19011,10 +21870,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -19034,26 +21895,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19063,20 +21930,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19085,19 +21957,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19107,12 +21984,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19122,16 +22001,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 21, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19141,22 +22024,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19166,26 +22053,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 21, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19195,22 +22088,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19220,26 +22117,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19248,7 +22151,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: l2_cntxt_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19258,6 +22163,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -19267,10 +22173,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -19290,26 +22198,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19319,20 +22233,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19341,19 +22260,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19363,12 +22287,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19378,16 +22304,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 22, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19397,22 +22327,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19422,26 +22356,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 22, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19451,22 +22391,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19476,26 +22420,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19504,7 +22454,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19514,6 +22466,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -19523,10 +22476,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -19546,26 +22501,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19575,20 +22536,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19597,19 +22563,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19619,12 +22590,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19634,16 +22607,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 23, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19653,22 +22630,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19678,26 +22659,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 23, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19707,22 +22694,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19732,26 +22723,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19761,6 +22758,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -19770,10 +22768,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -19793,26 +22793,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19822,20 +22828,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19844,19 +22855,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19866,12 +22882,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19881,16 +22899,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 24, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19900,22 +22922,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19925,26 +22951,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 24, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -19954,22 +22986,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -19979,26 +23015,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20008,6 +23050,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "prof_func_id", .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -20017,10 +23060,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l2_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "parif", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, .result_operand = { @@ -20040,26 +23085,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "allowed_pri", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_pri", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "allowed_tpid", .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "default_tpid", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "bd_act_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "sp_rec_ptr", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20069,20 +23120,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "byp_sp_lkup", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20091,19 +23147,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, wh_plus, table: profile_tcam_0 */ { + .description = "wc_key_id", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "wc_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "em_key_mask", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -20113,12 +23174,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_key_id", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_profile_id", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20128,16 +23191,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "em_search_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pl_byp_lkup_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* class_tid: 25, wh_plus, table: ext_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20147,22 +23214,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -20172,26 +23243,32 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 25, wh_plus, table: int_em_0 */ { + .description = "act_rec_ptr", .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -20201,22 +23278,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ext_flow_ctr", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "act_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "act_rec_size", .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "key_size", .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -20226,20 +23307,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "strength", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "l1_cacheable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -20248,203 +23333,261 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = }; struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, @@ -20452,20 +23595,25 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_pos = 0 }, { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, @@ -20473,90 +23621,115 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_pos = 0 }, { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ { + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ { + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index a539ec0c84..67308f1cf1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -217,6 +217,9 @@ struct bnxt_ulp_mapper_tbl_info { enum bnxt_ulp_mark_db_opcode mark_db_opcode; enum bnxt_ulp_index_opcode index_opcode; uint32_t index_operand; + + /* Table opcode for table operations */ + uint32_t tbl_opcode; }; struct bnxt_ulp_mapper_key_field_info { @@ -258,6 +261,12 @@ struct bnxt_ulp_cache_tbl_params { uint16_t num_entries; }; +struct bnxt_ulp_generic_tbl_params { + uint16_t result_num_entries; + uint16_t result_byte_size; + enum bnxt_ulp_byte_order result_byte_order; +}; + /* * Flow Mapper Static Data Externs: * Access to the below static data should be done through access functions and @@ -288,6 +297,11 @@ extern struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[]; */ extern struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[]; +/* + * The ulp_generic_tbl_parms table provides the sizes of the generic tables the + * mapper must dynamically allocate during initialization. + */ +extern struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[]; /* * The ulp_global template table is used to initialize default entries * that could be reused by other templates. diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index 7214e9c889..ff8eabd3f3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -146,8 +146,20 @@ ulp_bs_put_lsb(uint8_t *bs, uint16_t bitpos, uint8_t bitlen, uint8_t val) } } -/* Assuming that val is in Big-Endian Format */ -static uint32_t +/* + * Add data to the byte array in Little endian format. + * + * bs [in] The byte array where data is pushed + * + * pos [in] The offset where data is pushed + * + * len [in] The number of bits to be added to the data array. + * + * val [in] The data to be added to the data array. + * + * returns the number of bits pushed. + */ +uint32_t ulp_bs_push_lsb(uint8_t *bs, uint16_t pos, uint8_t len, uint8_t *val) { int i; @@ -169,8 +181,20 @@ ulp_bs_push_lsb(uint8_t *bs, uint16_t pos, uint8_t len, uint8_t *val) return len; } -/* Assuming that val is in Big-Endian Format */ -static uint32_t +/* + * Add data to the byte array in Big endian format. + * + * bs [in] The byte array where data is pushed + * + * pos [in] The offset where data is pushed + * + * len [in] The number of bits to be added to the data array. + * + * val [in] The data to be added to the data array. + * + * returns the number of bits pushed. + */ +uint32_t ulp_bs_push_msb(uint8_t *bs, uint16_t pos, uint8_t len, uint8_t *val) { int i; @@ -474,7 +498,7 @@ ulp_blob_pad_push(struct ulp_blob *blob, { if (datalen > (uint32_t)(blob->bitlen - blob->write_idx)) { BNXT_TF_DBG(ERR, "Pad too large for blob\n"); - return 0; + return -1; } blob->write_idx += datalen; @@ -504,8 +528,22 @@ ulp_bs_get_lsb(uint8_t *src, uint16_t bitpos, uint8_t bitlen, uint8_t *dst) } } -/* Assuming that src is in little-Endian Format */ -static void +/* + * Get data from the byte array in Little endian format. + * + * src [in] The byte array where data is extracted from + * + * dst [out] The byte array where data is pulled into + * + * size [in] The size of dst array in bytes + * + * offset [in] The offset where data is pulled + * + * len [in] The number of bits to be extracted from the data array + * + * returns None. + */ +void ulp_bs_pull_lsb(uint8_t *src, uint8_t *dst, uint32_t size, uint32_t offset, uint32_t len) { @@ -525,6 +563,57 @@ ulp_bs_pull_lsb(uint8_t *src, uint8_t *dst, uint32_t size, ulp_bs_get_lsb(src, offset, len, &dst[size - 1 - idx]); } +/* Get data from src and put into dst using big-endian format */ +static void +ulp_bs_get_msb(uint8_t *src, uint16_t bitpos, uint8_t bitlen, uint8_t *dst) +{ + uint8_t bitoffs = bitpos % ULP_BLOB_BYTE; + uint16_t index = ULP_BITS_2_BYTE_NR(bitpos); + uint8_t mask; + int32_t shift; + + shift = ULP_BLOB_BYTE - bitoffs - bitlen; + if (shift >= 0) { + mask = 0xFF >> -bitlen; + *dst = (src[index] >> shift) & mask; + } else { + *dst = (src[index] & (0xFF >> bitoffs)) << -shift; + *dst |= src[index + 1] >> -shift; + } +} + +/* + * Get data from the byte array in Big endian format. + * + * src [in] The byte array where data is extracted from + * + * dst [out] The byte array where data is pulled into + * + * offset [in] The offset where data is pulled + * + * len [in] The number of bits to be extracted from the data array + * + * returns None. + */ +void +ulp_bs_pull_msb(uint8_t *src, uint8_t *dst, + uint32_t offset, uint32_t len) +{ + uint32_t idx; + uint32_t cnt = ULP_BITS_2_BYTE_NR(len); + + /* iterate bytewise to get data */ + for (idx = 0; idx < cnt; idx++) { + ulp_bs_get_msb(src, offset, ULP_BLOB_BYTE, &dst[idx]); + offset += ULP_BLOB_BYTE; + len -= ULP_BLOB_BYTE; + } + + /* Extract the last reminder data that is not 8 byte boundary */ + if (len) + ulp_bs_get_msb(src, offset, len, &dst[idx]); +} + /* * Extract data from the binary blob using given offset. * @@ -549,11 +638,10 @@ ulp_blob_pull(struct ulp_blob *blob, uint8_t *data, uint32_t data_size, return -1; /* failure */ } - if (blob->byte_order == BNXT_ULP_BYTE_ORDER_BE) { - BNXT_TF_DBG(ERR, "Big endian pull not implemented\n"); - return -1; /* failure */ - } - ulp_bs_pull_lsb(blob->data, data, data_size, offset, len); + if (blob->byte_order == BNXT_ULP_BYTE_ORDER_BE) + ulp_bs_pull_msb(blob->data, data, offset, len); + else + ulp_bs_pull_lsb(blob->data, data, data_size, offset, len); return 0; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h index d3f0da049b..bbd8c16407 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.h +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h @@ -135,6 +135,38 @@ ulp_regfile_write(struct ulp_regfile *regfile, enum bnxt_ulp_regfile_index field, uint64_t data); +/* + * Add data to the byte array in Little endian format. + * + * bs [in] The byte array where data is pushed + * + * pos [in] The offset where data is pushed + * + * len [in] The number of bits to be added to the data array. + * + * val [in] The data to be added to the data array. + * + * returns the number of bits pushed. + */ +uint32_t +ulp_bs_push_lsb(uint8_t *bs, uint16_t pos, uint8_t len, uint8_t *val); + +/* + * Add data to the byte array in Big endian format. + * + * bs [in] The byte array where data is pushed + * + * pos [in] The offset where data is pushed + * + * len [in] The number of bits to be added to the data array. + * + * val [in] The data to be added to the data array. + * + * returns the number of bits pushed. + */ +uint32_t +ulp_bs_push_msb(uint8_t *bs, uint16_t pos, uint8_t len, uint8_t *val); + /* * Initializes the blob structure for creating binary blob * @@ -257,6 +289,42 @@ uint8_t * ulp_blob_data_get(struct ulp_blob *blob, uint16_t *datalen); +/* + * Get data from the byte array in Little endian format. + * + * src [in] The byte array where data is extracted from + * + * dst [out] The byte array where data is pulled into + * + * size [in] The size of dst array in bytes + * + * offset [in] The offset where data is pulled + * + * len [in] The number of bits to be extracted from the data array + * + * returns None. + */ +void +ulp_bs_pull_lsb(uint8_t *src, uint8_t *dst, uint32_t size, + uint32_t offset, uint32_t len); + +/* + * Get data from the byte array in Big endian format. + * + * src [in] The byte array where data is extracted from + * + * dst [out] The byte array where data is pulled into + * + * offset [in] The offset where data is pulled + * + * len [in] The number of bits to be extracted from the data array + * + * returns None. + */ +void +ulp_bs_pull_msb(uint8_t *src, uint8_t *dst, + uint32_t offset, uint32_t len); + /* * Extract data from the binary blob using given offset. * From patchwork Sun May 30 08:58:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93576 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B4FFA0524; Sun, 30 May 2021 11:04:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 625D4410F9; Sun, 30 May 2021 11:01:17 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 3BD4540E01 for ; Sun, 30 May 2021 11:01:15 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id CE94E7DC0; Sun, 30 May 2021 02:01:13 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com CE94E7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365274; bh=cPCwC6QrZComzBuVXBBNPIHxDuxFxTn3EUkazHZP2+A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ECzxhh8c/6c+La8MMZed9/tAklqXmzGlEF5s1SwVF2tA9MgYcpY5USKXA5xE/j4Y0 mH9EGFp6yC4GAjqw5zNEMnABti7QvZQsq6ND9HzbvD0Kxx/GQn//kIW+rBnYOcPt5X UXcS8F0lpOxtlp5AwgoEShsjF03gMMNPcyp9I9OI= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:28:59 +0530 Message-Id: <20210530085929.29695-29-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 28/58] net/bnxt: add support for mapper flow database opcodes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Added support for mapper flow database opcode to enable shared resources like mirror action. This allows mapper to conditionally populate flow database based on template content. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 119 ++++++++++++------ .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 8 ++ drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 4 + 3 files changed, 95 insertions(+), 36 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 2bb8d08699..4e9211a7ab 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -469,6 +469,80 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp, return 0; } +/* + * Process the flow database opcode action. + * returns 0 on success. + */ +static int32_t +ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_flow_db_res_params *fid_parms) +{ + uint32_t push_fid, fid = 0; + uint64_t val64; + int32_t rc = 0; + + switch (tbl->fdb_opcode) { + case BNXT_ULP_FDB_OPC_PUSH: + push_fid = parms->fid; + break; + case BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE: + /* allocate a new fid */ + rc = ulp_flow_db_fid_alloc(parms->ulp_ctx, + BNXT_ULP_FDB_TYPE_REGULAR, + tbl->resource_func, &fid); + if (rc) { + BNXT_TF_DBG(ERR, + "Unable to allocate flow table entry\n"); + return rc; + } + /* Store the allocated fid in regfile*/ + val64 = fid; + rc = ulp_regfile_write(parms->regfile, tbl->flow_db_operand, + val64); + if (!rc) { + BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", + tbl->flow_db_operand); + rc = -EINVAL; + goto error; + } + /* Use the allocated fid to update the flow resource */ + push_fid = fid; + break; + case BNXT_ULP_FDB_OPC_PUSH_REGFILE: + /* get the fid from the regfile */ + rc = ulp_regfile_read(parms->regfile, tbl->flow_db_operand, + &val64); + if (!rc) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", + tbl->flow_db_operand); + return -EINVAL; + } + /* Use the extracted fid to update the flow resource */ + push_fid = (uint32_t)val64; + break; + default: + return rc; /* Nothing to be done */ + } + + /* Add the resource to the flow database */ + rc = ulp_flow_db_resource_add(parms->ulp_ctx, parms->flow_type, + push_fid, fid_parms); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to add res to flow %x rc = %d\n", + push_fid, rc); + goto error; + } + return rc; + +error: + /* free the allocated fid */ + if (fid) + ulp_flow_db_fid_free(parms->ulp_ctx, + BNXT_ULP_FDB_TYPE_REGULAR, fid); + return rc; +} + /* * Process the identifier instruction and either store it in the flow database * or return it in the val (if not NULL) on success. If val is NULL, the @@ -524,10 +598,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_hndl = iparms.id; fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to link res to flow rc = %d\n", rc); @@ -618,10 +689,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_type = ident->ident_type; fid_parms.resource_hndl = sparms.search_id; fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to link res to flow rc = %d\n", rc); @@ -1103,10 +1171,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = gfid; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc); return rc; @@ -1152,10 +1217,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = act_idx; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc); return rc; @@ -1201,10 +1263,7 @@ ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = act_idx; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc); return rc; @@ -1580,10 +1639,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_type = tbl->resource_type; fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_hndl = idx; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n", @@ -1741,10 +1797,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_hndl = iparms.flow_handle; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc); @@ -1968,10 +2021,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_hndl = index; fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n", rc); @@ -2280,10 +2330,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_sub_type = tbl->resource_sub_type; fid_parms.resource_hndl = ckey; fid_parms.critical_resource = tbl->critical_resource; - rc = ulp_flow_db_resource_add(parms->ulp_ctx, - parms->flow_type, - parms->fid, - &fid_parms); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) BNXT_TF_DBG(ERR, "Fail to add gen ent flowdb %d\n", rc); } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 2a9a290eea..f16651a821 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -179,6 +179,14 @@ enum bnxt_ulp_direction { BNXT_ULP_DIRECTION_LAST = 2 }; +enum bnxt_ulp_fdb_opc { + BNXT_ULP_FDB_OPC_PUSH = 0, + BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE = 1, + BNXT_ULP_FDB_OPC_PUSH_REGFILE = 2, + BNXT_ULP_FDB_OPC_NOP = 3, + BNXT_ULP_FDB_OPC_LAST = 4 +}; + enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, BNXT_ULP_FLOW_MEM_TYPE_EXT = 1, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 67308f1cf1..167116a2f4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -220,6 +220,10 @@ struct bnxt_ulp_mapper_tbl_info { /* Table opcode for table operations */ uint32_t tbl_opcode; + + /* FDB table opcode */ + enum bnxt_ulp_fdb_opc fdb_opcode; + uint32_t flow_db_operand; }; struct bnxt_ulp_mapper_key_field_info { From patchwork Sun May 30 08:59:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93577 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 46C27A0524; Sun, 30 May 2021 11:04:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C4F23411B8; Sun, 30 May 2021 11:01:18 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id B8AAC40E3C for ; Sun, 30 May 2021 11:01:16 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 5650B7DAF; Sun, 30 May 2021 02:01:15 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 5650B7DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365276; bh=YY315HyyptdNxG1U0Xpr3bwsEtEG/qEGsYEU32tKuDc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Qsuoy5N+3Nq1eI/dIXaXU8NtfNeva/P1r2oUt8SeB37vfyMwa4bo2faLRiht1qWXD 03kmzcy/JDC0AovkeRiKiKkcEyhA9t48OYC0i1UbVY8d15DpN63AbhD/dXYb44zGlc N8ZY0EQUVKTSUid0dqp2IcKKMbT60x73uIbXakTY= From: Venkat Duvvuru To: dev@dpdk.org Cc: Mike Baucom , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:00 +0530 Message-Id: <20210530085929.29695-30-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 29/58] net/bnxt: add conditional execution and rejection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Mike Baucom Conditional execution and rejection processing added for templates and tables. This allows the mapper to skip tables and reject templates based on the content without having to hard code rules. Signed-off-by: Mike Baucom Signed-off-by: Venkat Duvvuru Reviewed-by: Kishore Padmanabha --- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 1 + drivers/net/bnxt/tf_ulp/ulp_mapper.c | 330 ++++++++++++++---- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 2 + .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 30 +- .../tf_ulp/ulp_template_db_stingray_act.c | 30 +- .../tf_ulp/ulp_template_db_stingray_class.c | 8 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 243 +++++++++++++ drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h | 2 + .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 30 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 8 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 18 +- 11 files changed, 593 insertions(+), 109 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 777a6badd9..ddf38ed931 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -93,6 +93,7 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, mapper_cparms->flow_id = params->fid; mapper_cparms->parent_flow = params->parent_flow; mapper_cparms->parent_fid = params->parent_fid; + mapper_cparms->fld_bitmap = ¶ms->fld_bitmap; } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 4e9211a7ab..d84614fcd1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -17,6 +17,7 @@ #include "ulp_mapper.h" #include "ulp_flow_db.h" #include "tf_util.h" +#include "ulp_template_db_tbl.h" static struct bnxt_ulp_glb_resource_info * ulp_mapper_glb_resource_info_list_get(uint32_t *num_entries) @@ -190,6 +191,12 @@ ulp_mapper_glb_template_table_get(uint32_t *num_entries) return ulp_glb_template_tbl; } +static uint8_t * +ulp_mapper_glb_field_tbl_get(uint32_t idx) +{ + return &ulp_glb_field_tbl[idx]; +} + /* * Get the size of the action property for a given index. * @@ -205,6 +212,40 @@ ulp_mapper_act_prop_size_get(uint32_t idx) return ulp_act_prop_map_table[idx]; } +static struct bnxt_ulp_mapper_cond_info * +ulp_mapper_tmpl_reject_list_get(struct bnxt_ulp_mapper_parms *mparms, + uint32_t tid, + uint32_t *num_tbls, + enum bnxt_ulp_cond_list_opc *opc) +{ + uint32_t idx; + const struct ulp_template_device_tbls *dev_tbls; + + dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; + *num_tbls = dev_tbls->tmpl_list[tid].reject_info.cond_nums; + *opc = dev_tbls->tmpl_list[tid].reject_info.cond_list_opcode; + idx = dev_tbls->tmpl_list[tid].reject_info.cond_start_idx; + + return &dev_tbls->cond_list[idx]; +} + +static struct bnxt_ulp_mapper_cond_info * +ulp_mapper_tbl_execute_list_get(struct bnxt_ulp_mapper_parms *mparms, + struct bnxt_ulp_mapper_tbl_info *tbl, + uint32_t *num_tbls, + enum bnxt_ulp_cond_list_opc *opc) +{ + uint32_t idx; + const struct ulp_template_device_tbls *dev_tbls; + + dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; + *num_tbls = tbl->execute_info.cond_nums; + *opc = tbl->execute_info.cond_list_opcode; + idx = tbl->execute_info.cond_start_idx; + + return &dev_tbls->cond_list[idx]; +} + /* * Get a list of classifier tables that implement the flow * Gets a device dependent list of tables that implement the class template id @@ -2376,61 +2417,6 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, return rc; } -/* - * Function to process the conditional opcode of the mapper table. - * returns 1 to skip the table. - * return 0 to continue processing the table. - * - * defaults to skip - */ -static int32_t -ulp_mapper_tbl_cond_opcode_process(struct bnxt_ulp_mapper_parms *parms, - struct bnxt_ulp_mapper_tbl_info *tbl) -{ - int32_t rc = 1; - - switch (tbl->cond_opcode) { - case BNXT_ULP_COND_OPCODE_NOP: - rc = 0; - break; - case BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET: - if (tbl->cond_operand < BNXT_ULP_CF_IDX_LAST && - ULP_COMP_FLD_IDX_RD(parms, tbl->cond_operand)) - rc = 0; - break; - case BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET: - if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, - tbl->cond_operand)) - rc = 0; - break; - case BNXT_ULP_COND_OPCODE_HDR_BIT_IS_SET: - if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, - tbl->cond_operand)) - rc = 0; - break; - case BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET: - if (tbl->cond_operand < BNXT_ULP_CF_IDX_LAST && - !ULP_COMP_FLD_IDX_RD(parms, tbl->cond_operand)) - rc = 0; - break; - case BNXT_ULP_COND_OPCODE_ACTION_BIT_NOT_SET: - if (!ULP_BITMAP_ISSET(parms->act_bitmap->bits, - tbl->cond_operand)) - rc = 0; - break; - case BNXT_ULP_COND_OPCODE_HDR_BIT_NOT_SET: - if (!ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, - tbl->cond_operand)) - rc = 0; - break; - default: - BNXT_TF_DBG(ERR, - "Invalid arg in mapper tbl for cond opcode\n"); - break; - } - return rc; -} - /* * Function to process the memtype opcode of the mapper table. * returns 1 to skip the table. @@ -2467,27 +2453,251 @@ ulp_mapper_tbl_memtype_opcode_process(struct bnxt_ulp_mapper_parms *parms, return rc; } +/* + * Common conditional opcode process routine that is used for both the template + * rejection and table conditional execution. + */ +static int32_t +ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, + enum bnxt_ulp_cond_opc opc, + uint32_t operand, + int32_t *res) +{ + int32_t rc = 0; + uint8_t *bit; + uint32_t idx; + uint64_t regval; + + switch (opc) { + case BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET: + if (operand < BNXT_ULP_CF_IDX_LAST) { + *res = ULP_COMP_FLD_IDX_RD(parms, operand); + } else { + BNXT_TF_DBG(ERR, "comp field out of bounds %d\n", + operand); + rc = -EINVAL; + } + break; + case BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET: + if (operand < BNXT_ULP_CF_IDX_LAST) { + *res = !ULP_COMP_FLD_IDX_RD(parms, operand); + } else { + BNXT_TF_DBG(ERR, "comp field out of bounds %d\n", + operand); + rc = -EINVAL; + } + break; + case BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET: + if (operand < BNXT_ULP_ACTION_BIT_LAST) { + *res = ULP_BITMAP_ISSET(parms->act_bitmap->bits, + operand); + } else { + BNXT_TF_DBG(ERR, "action bit out of bounds %d\n", + operand); + rc = -EINVAL; + } + break; + case BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET: + if (operand < BNXT_ULP_ACTION_BIT_LAST) { + *res = !ULP_BITMAP_ISSET(parms->act_bitmap->bits, + operand); + } else { + BNXT_TF_DBG(ERR, "action bit out of bounds %d\n", + operand); + rc = -EINVAL; + } + break; + case BNXT_ULP_COND_OPC_HDR_BIT_IS_SET: + if (operand < BNXT_ULP_HDR_BIT_LAST) { + *res = ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, + operand); + } else { + BNXT_TF_DBG(ERR, "header bit out of bounds %d\n", + operand); + rc = -EINVAL; + } + break; + case BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET: + if (operand < BNXT_ULP_HDR_BIT_LAST) { + *res = !ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, + operand); + } else { + BNXT_TF_DBG(ERR, "header bit out of bounds %d\n", + operand); + rc = -EINVAL; + } + break; + case BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET: + idx = (parms->class_tid << BNXT_ULP_GLB_FIELD_TBL_SHIFT) | + operand; + bit = ulp_mapper_glb_field_tbl_get(idx); + if (!bit) { + BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", + idx); + return -EINVAL; + } + *res = ULP_BITMAP_ISSET(parms->fld_bitmap->bits, (1 << *bit)); + break; + case BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET: + idx = (parms->class_tid << BNXT_ULP_GLB_FIELD_TBL_SHIFT) | + operand; + bit = ulp_mapper_glb_field_tbl_get(idx); + if (!bit) { + BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", + idx); + return -EINVAL; + } + *res = !ULP_BITMAP_ISSET(parms->fld_bitmap->bits, (1 << *bit)); + break; + case BNXT_ULP_COND_OPC_REGFILE_IS_SET: + if (!ulp_regfile_read(parms->regfile, operand, ®val)) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand); + return -EINVAL; + } + *res = regval != 0; + break; + case BNXT_ULP_COND_OPC_REGFILE_NOT_SET: + if (!ulp_regfile_read(parms->regfile, operand, ®val)) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand); + return -EINVAL; + } + *res = regval == 0; + break; + default: + BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc); + rc = -EINVAL; + break; + } + return (rc); +} + +/* + * Processes a list of conditions and returns both a status and result of the + * list. The status must be checked prior to verifying the result. + * + * returns 0 for success, negative on failure + * returns res = 1 for true, res = 0 for false. + */ +static int32_t +ulp_mapper_cond_opc_list_process(struct bnxt_ulp_mapper_parms *parms, + enum bnxt_ulp_cond_list_opc list_opc, + struct bnxt_ulp_mapper_cond_info *list, + uint32_t num, + int32_t *res) +{ + uint32_t i; + int32_t rc = 0, trc; + + switch (list_opc) { + case BNXT_ULP_COND_LIST_OPC_AND: + /* AND Defaults to true. */ + *res = 1; + break; + case BNXT_ULP_COND_LIST_OPC_OR: + /* OR Defaults to false. */ + *res = 0; + break; + case BNXT_ULP_COND_LIST_OPC_TRUE: + *res = 1; + return rc; + case BNXT_ULP_COND_LIST_OPC_FALSE: + *res = 0; + return rc; + default: + BNXT_TF_DBG(ERR, "Invalid conditional list opcode %d\n", + list_opc); + return -EINVAL; + } + + for (i = 0; i < num; i++) { + rc = ulp_mapper_cond_opc_process(parms, + list[i].cond_opcode, + list[i].cond_operand, + &trc); + if (rc) + return rc; + + if (list_opc == BNXT_ULP_COND_LIST_OPC_AND) { + /* early return if result is ever zero */ + if (!trc) { + *res = trc; + return rc; + } + } else { + /* early return if result is ever non-zero */ + if (trc) { + *res = trc; + return rc; + } + } + } + + return rc; +} + static int32_t ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) { + struct bnxt_ulp_mapper_cond_info *cond_tbls = NULL; + enum bnxt_ulp_cond_list_opc cond_opc; struct bnxt_ulp_mapper_tbl_info *tbls; - uint32_t num_tbls, i; - int32_t rc = -EINVAL; + struct bnxt_ulp_mapper_tbl_info *tbl; + uint32_t num_tbls, i, num_cond_tbls; + int32_t rc = -EINVAL, cond_rc = 0; + + cond_tbls = ulp_mapper_tmpl_reject_list_get(parms, tid, + &num_cond_tbls, + &cond_opc); + /* + * Process the reject list if exists, otherwise assume that the + * template is allowed. + */ + if (cond_tbls && num_cond_tbls) { + rc = ulp_mapper_cond_opc_list_process(parms, + cond_opc, + cond_tbls, + num_cond_tbls, + &cond_rc); + if (rc) + return rc; + + /* Reject the template if True */ + if (cond_rc) { + BNXT_TF_DBG(ERR, "%s Template %d rejected.\n", + (parms->tmpl_type == + BNXT_ULP_TEMPLATE_TYPE_CLASS) ? + "class" : "action", tid); + return -EINVAL; + } + } tbls = ulp_mapper_tbl_list_get(parms, tid, &num_tbls); if (!tbls || !num_tbls) { BNXT_TF_DBG(ERR, "No %s tables for %d:%d\n", - (parms->tmpl_type = BNXT_ULP_TEMPLATE_TYPE_CLASS) ? + (parms->tmpl_type == BNXT_ULP_TEMPLATE_TYPE_CLASS) ? "class" : "action", parms->dev_id, tid); return -EINVAL; } for (i = 0; i < num_tbls; i++) { - struct bnxt_ulp_mapper_tbl_info *tbl = &tbls[i]; + tbl = &tbls[i]; + /* Handle the table level opcodes to determine if required. */ if (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) continue; - if (ulp_mapper_tbl_cond_opcode_process(parms, tbl)) + cond_tbls = ulp_mapper_tbl_execute_list_get(parms, tbl, + &num_cond_tbls, + &cond_opc); + rc = ulp_mapper_cond_opc_list_process(parms, cond_opc, + cond_tbls, num_cond_tbls, + &cond_rc); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to process cond opc list " + "(%d)\n", rc); + return rc; + } + /* Skip the table if False */ + if (!cond_rc) continue; switch (tbl->resource_func) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 8422f44026..8bc6cdbdd5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -58,6 +58,7 @@ struct bnxt_ulp_mapper_parms { struct ulp_rte_act_bitmap *act_bitmap; struct ulp_rte_hdr_bitmap *hdr_bitmap; struct ulp_rte_hdr_field *hdr_field; + struct ulp_rte_field_bitmap *fld_bitmap; uint32_t *comp_fld; struct ulp_regfile *regfile; struct tf *tfp; @@ -79,6 +80,7 @@ struct bnxt_ulp_mapper_create_parms { uint32_t *comp_fld; struct ulp_rte_act_bitmap *act; struct ulp_rte_act_prop *act_prop; + struct ulp_rte_field_bitmap *fld_bitmap; uint32_t class_tid; uint32_t act_tid; uint16_t func_id; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index f16651a821..e4b8c56472 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -27,6 +27,7 @@ #define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 +#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 enum bnxt_ulp_action_bit { BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001, @@ -143,15 +144,26 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_LAST = 46 }; -enum bnxt_ulp_cond_opcode { - BNXT_ULP_COND_OPCODE_NOP = 0, - BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET = 1, - BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET = 2, - BNXT_ULP_COND_OPCODE_HDR_BIT_IS_SET = 3, - BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET = 4, - BNXT_ULP_COND_OPCODE_ACTION_BIT_NOT_SET = 5, - BNXT_ULP_COND_OPCODE_HDR_BIT_NOT_SET = 6, - BNXT_ULP_COND_OPCODE_LAST = 7 +enum bnxt_ulp_cond_list_opc { + BNXT_ULP_COND_LIST_OPC_TRUE = 0, + BNXT_ULP_COND_LIST_OPC_FALSE = 1, + BNXT_ULP_COND_LIST_OPC_OR = 2, + BNXT_ULP_COND_LIST_OPC_AND = 3, + BNXT_ULP_COND_LIST_OPC_LAST = 4 +}; + +enum bnxt_ulp_cond_opc { + BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET = 0, + BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET = 1, + BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET = 2, + BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET = 3, + BNXT_ULP_COND_OPC_HDR_BIT_IS_SET = 4, + BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET = 5, + BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET = 6, + BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7, + BNXT_ULP_COND_OPC_REGFILE_IS_SET = 8, + BNXT_ULP_COND_OPC_REGFILE_NOT_SET = 9, + BNXT_ULP_COND_OPC_LAST = 10 }; enum bnxt_ulp_critical_resource { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c index b370da22f7..6ad6263183 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c @@ -47,7 +47,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -64,7 +64,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -81,7 +81,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -146,7 +146,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -195,7 +195,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -244,7 +244,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -261,7 +261,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, @@ -278,7 +278,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, @@ -342,7 +342,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -359,7 +359,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -376,7 +376,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -441,7 +441,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -459,7 +459,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -493,7 +493,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -511,7 +511,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c index a8f26e8c51..c11d1ad96d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c @@ -292,7 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { { /* class_tid: 2, stingray, table: l2_cntxt_tcam_vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -315,7 +315,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, .key_start_idx = 27, @@ -332,7 +332,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { { /* class_tid: 2, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -1785,7 +1785,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 3a66d59b5d..4fe90d8bb9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -98,6 +98,249 @@ uint32_t ulp_act_prop_map_table[] = { BNXT_ULP_ACT_PROP_SZ_LAST }; +uint8_t ulp_glb_field_tbl[211] = { + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0, + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0, + [16] = 0, + [17] = 0, + [18] = 0, + [19] = 0, + [20] = 0, + [21] = 0, + [22] = 0, + [23] = 0, + [24] = 0, + [25] = 0, + [26] = 0, + [27] = 0, + [28] = 0, + [29] = 0, + [30] = 0, + [31] = 0, + [32] = 0, + [33] = 0, + [34] = 0, + [35] = 0, + [36] = 0, + [37] = 0, + [38] = 0, + [39] = 0, + [40] = 0, + [41] = 0, + [42] = 0, + [43] = 0, + [44] = 0, + [45] = 0, + [46] = 0, + [47] = 0, + [48] = 0, + [49] = 0, + [50] = 0, + [51] = 0, + [52] = 0, + [53] = 0, + [54] = 0, + [55] = 0, + [56] = 0, + [57] = 0, + [58] = 0, + [59] = 0, + [60] = 0, + [61] = 0, + [62] = 0, + [63] = 0, + [64] = 0, + [65] = 0, + [66] = 0, + [67] = 0, + [68] = 0, + [69] = 0, + [70] = 0, + [71] = 0, + [72] = 0, + [73] = 0, + [74] = 0, + [75] = 0, + [76] = 0, + [77] = 0, + [78] = 0, + [79] = 0, + [80] = 0, + [81] = 0, + [82] = 0, + [83] = 0, + [84] = 0, + [85] = 0, + [86] = 0, + [87] = 0, + [88] = 0, + [89] = 0, + [90] = 0, + [91] = 0, + [92] = 0, + [93] = 0, + [94] = 0, + [95] = 0, + [96] = 0, + [97] = 0, + [98] = 0, + [99] = 0, + [100] = 0, + [101] = 0, + [102] = 0, + [103] = 0, + [104] = 0, + [105] = 0, + [106] = 0, + [107] = 0, + [108] = 0, + [109] = 0, + [110] = 0, + [111] = 0, + [112] = 0, + [113] = 0, + [114] = 0, + [115] = 0, + [116] = 0, + [117] = 0, + [118] = 0, + [119] = 0, + [120] = 0, + [121] = 0, + [122] = 0, + [123] = 0, + [124] = 0, + [125] = 0, + [126] = 0, + [127] = 0, + /* svif.index */ + [128] = 1, + /* o_eth.dmac */ + [129] = 2, + [130] = 0, + /* o_eth.smac */ + [131] = 3, + [132] = 0, + /* o_eth.type */ + [133] = 4, + [134] = 0, + /* o_ipv4.ver */ + [135] = 11, + [136] = 0, + /* o_ipv4.tos */ + [137] = 12, + [138] = 0, + /* o_ipv4.len */ + [139] = 13, + [140] = 0, + /* o_ipv4.frag_id */ + [141] = 14, + [142] = 0, + /* o_ipv4.frag_off */ + [143] = 15, + [144] = 0, + /* o_ipv4.ttl */ + [145] = 16, + [146] = 0, + /* o_ipv4.proto_id */ + [147] = 17, + [148] = 0, + /* o_ipv4.csum */ + [149] = 18, + [150] = 0, + /* o_ipv4.src_addr */ + [151] = 19, + [152] = 0, + /* o_ipv4.dst_addr */ + [153] = 20, + [154] = 0, + [155] = 0, + [156] = 0, + [157] = 0, + [158] = 0, + [159] = 0, + [160] = 0, + [161] = 0, + [162] = 0, + [163] = 0, + [164] = 0, + [165] = 0, + [166] = 0, + [167] = 0, + [168] = 0, + [169] = 0, + [170] = 0, + [171] = 0, + [172] = 0, + [173] = 0, + [174] = 0, + /* o_tcp.src_port */ + [175] = 21, + [176] = 0, + /* o_tcp.dst_port */ + [177] = 22, + [178] = 0, + /* o_tcp.sent_seq */ + [179] = 23, + [180] = 0, + /* o_tcp.recv_ack */ + [181] = 24, + [182] = 0, + /* o_tcp.data_off */ + [183] = 25, + [184] = 0, + /* o_tcp.tcp_flags */ + [185] = 26, + [186] = 0, + /* o_tcp.rx_win */ + [187] = 27, + [188] = 0, + /* o_tcp.csum */ + [189] = 28, + [190] = 0, + /* o_tcp.urp */ + [191] = 29, + [192] = 0, + [193] = 0, + [194] = 0, + [195] = 0, + [196] = 0, + [197] = 0, + [198] = 0, + [199] = 0, + [200] = 0, + /* oo_vlan.cfi_pri */ + [201] = 5, + /* oi_vlan.cfi_pri */ + [202] = 8, + [203] = 0, + [204] = 0, + /* oo_vlan.vid */ + [205] = 6, + /* oi_vlan.vid */ + [206] = 9, + [207] = 0, + [208] = 0, + /* oo_vlan.type */ + [209] = 7, + /* oi_vlan.type */ + [210] = 10 +}; + /* * This structure has to be indexed based on the rte_flow_action_type that is * part of DPDK. The below array is list of parsing functions for each of the diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h index 684e93f557..a656f3da52 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h @@ -45,4 +45,6 @@ extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[]; extern struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[]; + +extern uint8_t ulp_glb_field_tbl[]; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 26eba56516..be6149b9ce 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -47,7 +47,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -64,7 +64,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -81,7 +81,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -145,7 +145,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -194,7 +194,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -243,7 +243,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -260,7 +260,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, @@ -277,7 +277,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, @@ -341,7 +341,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -358,7 +358,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -375,7 +375,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -440,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -458,7 +458,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -492,7 +492,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -510,7 +510,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 89f1bef75f..f248d33203 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -292,7 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -315,7 +315,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, .key_start_idx = 27, @@ -332,7 +332,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -1785,7 +1785,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 167116a2f4..9a15968ea8 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -149,12 +149,24 @@ extern uint16_t ulp_act_sig_tbl[]; extern struct bnxt_ulp_act_match_info ulp_act_match_list[]; /* Device Specific Tables for mapper */ +struct bnxt_ulp_mapper_cond_info { + enum bnxt_ulp_cond_opc cond_opcode; + uint32_t cond_operand; +}; + +struct bnxt_ulp_mapper_cond_list_info { + enum bnxt_ulp_cond_list_opc cond_list_opcode; + uint32_t cond_start_idx; + uint32_t cond_nums; +}; + struct ulp_template_device_tbls { struct bnxt_ulp_mapper_tbl_list_info *tmpl_list; struct bnxt_ulp_mapper_tbl_info *tbl_list; struct bnxt_ulp_mapper_key_field_info *key_field_list; struct bnxt_ulp_mapper_result_field_info *result_field_list; struct bnxt_ulp_mapper_ident_info *ident_list; + struct bnxt_ulp_mapper_cond_info *cond_list; }; /* Device specific parameters */ @@ -183,14 +195,16 @@ struct bnxt_ulp_mapper_tbl_list_info { uint32_t device_name; uint32_t start_tbl_idx; uint32_t num_tbls; + struct bnxt_ulp_mapper_cond_list_info reject_info; }; struct bnxt_ulp_mapper_tbl_info { enum bnxt_ulp_resource_func resource_func; uint32_t resource_type; /* TF_ enum type */ enum bnxt_ulp_resource_sub_type resource_sub_type; - enum bnxt_ulp_cond_opcode cond_opcode; - uint32_t cond_operand; + struct bnxt_ulp_mapper_cond_list_info execute_info; + enum bnxt_ulp_cond_opc cond_opcode; + uint32_t cond_operand; enum bnxt_ulp_mem_type_opcode mem_type_opcode; uint8_t direction; uint32_t priority; From patchwork Sun May 30 08:59:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93578 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4DC4CA0524; Sun, 30 May 2021 11:04:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3EBE4411BE; Sun, 30 May 2021 11:01:20 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 400C94119A for ; Sun, 30 May 2021 11:01:18 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id D275D7DC2; Sun, 30 May 2021 02:01:16 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com D275D7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365277; bh=/lcjhXVHzUsYjRtfhgmyY1YHXX8nPu9xQIxIAID8IXM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K+1ZChGA8ecKpzXnZxC1jb7w3IORStVyhAQAAi3sdpph9kT47bn8JsRiuvV//SJQ1 tv41sTpZd6JZDt0FUjjVkPJ0RMMASWAPCVf0mDUQp/QuFeMQSnZLCJmn2iUScz7jdr cC+rKRiUU7ybGn7kfgYTEa8YInb/rjSlL1MPC+50= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:01 +0530 Message-Id: <20210530085929.29695-31-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 30/58] net/bnxt: modify TCAM opcode processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Added TCAM table specific opcode to process TCAM entry creation and reuse. This change removes the TCAM cache mechanism and uses the generic table mechanism for reuse of TCAM entries. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 135 ++++++----------- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 15 -- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 7 + .../tf_ulp/ulp_template_db_wh_plus_class.c | 138 ++++++++++++------ drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 + 5 files changed, 144 insertions(+), 152 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index d84614fcd1..c511f835ff 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -1356,20 +1356,11 @@ ulp_mapper_tcam_tbl_scan_ident_alloc(struct bnxt_ulp_mapper_parms *parms, uint32_t num_idents; uint32_t i; - /* - * Since the cache entry is responsible for allocating - * identifiers when in use, allocate the identifiers only - * during normal processing. - */ - if (parms->tcam_tbl_opc == - BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL) { - idents = ulp_mapper_ident_fields_get(parms, tbl, &num_idents); - - for (i = 0; i < num_idents; i++) { - if (ulp_mapper_ident_process(parms, tbl, - &idents[i], NULL)) - return -EINVAL; - } + idents = ulp_mapper_ident_fields_get(parms, tbl, &num_idents); + for (i = 0; i < num_idents; i++) { + if (ulp_mapper_ident_process(parms, tbl, + &idents[i], NULL)) + return -EINVAL; } return 0; } @@ -1490,14 +1481,15 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct tf_search_tcam_entry_parms searchparms = { 0 }; struct ulp_flow_db_res_params fid_parms = { 0 }; struct tf_free_tcam_entry_parms free_parms = { 0 }; - enum bnxt_ulp_search_before_alloc search_flag; uint32_t hit = 0; uint16_t tmplen = 0; uint16_t idx; - /* Skip this if was handled by the cache. */ - if (parms->tcam_tbl_opc == BNXT_ULP_MAPPER_TCAM_TBL_OPC_CACHE_SKIP) { - parms->tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL; + /* Skip this if table opcode is NOP */ + if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_NOT_USED || + tbl->tbl_opcode >= BNXT_ULP_TCAM_TBL_OPC_LAST) { + BNXT_TF_DBG(ERR, "Invalid tcam table opcode %d\n", + tbl->tbl_opcode); return 0; } @@ -1555,41 +1547,31 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, } } + /* For wild card tcam perform the post process to swap the blob */ if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) { ulp_mapper_wc_tcam_tbl_post_process(&key, tbl->key_bit_size); ulp_mapper_wc_tcam_tbl_post_process(&mask, tbl->key_bit_size); } - if (tbl->srch_b4_alloc == BNXT_ULP_SEARCH_BEFORE_ALLOC_NO) { - /* - * No search for re-use is requested, so simply allocate the - * tcam index. - */ - aparms.dir = tbl->direction; - aparms.tcam_tbl_type = tbl->resource_type; - aparms.search_enable = tbl->srch_b4_alloc; - aparms.key = ulp_blob_data_get(&key, &tmplen); - aparms.key_sz_in_bits = tmplen; + if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE) { + /* allocate the tcam index */ + aparms.dir = tbl->direction; + aparms.tcam_tbl_type = tbl->resource_type; + aparms.key = ulp_blob_data_get(&key, &tmplen); + aparms.key_sz_in_bits = tmplen; if (tbl->blob_key_bit_size != tmplen) { BNXT_TF_DBG(ERR, "Key len (%d) != Expected (%d)\n", tmplen, tbl->blob_key_bit_size); return -EINVAL; } - aparms.mask = ulp_blob_data_get(&mask, &tmplen); + aparms.mask = ulp_blob_data_get(&mask, &tmplen); if (tbl->blob_key_bit_size != tmplen) { BNXT_TF_DBG(ERR, "Mask len (%d) != Expected (%d)\n", tmplen, tbl->blob_key_bit_size); return -EINVAL; } - - aparms.priority = tbl->priority; - - /* - * All failures after this succeeds require the entry to be - * freed. cannot return directly on failure, but needs to goto - * error. - */ + aparms.priority = tbl->priority; rc = tf_alloc_tcam_entry(tfp, &aparms); if (rc) { BNXT_TF_DBG(ERR, "tcam alloc failed rc=%d.\n", rc); @@ -1627,14 +1609,18 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, hit = searchparms.hit; } - /* if it is miss then it is same as no search before alloc */ - if (!hit) - search_flag = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO; - else - search_flag = tbl->srch_b4_alloc; + /* Write the tcam index into the regfile*/ + if (!ulp_regfile_write(parms->regfile, tbl->tbl_operand, + (uint64_t)tfp_cpu_to_be_64(idx))) { + BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", + tbl->tbl_operand); + rc = -EINVAL; + /* Need to free the tcam idx, so goto error */ + goto error; + } - switch (search_flag) { - case BNXT_ULP_SEARCH_BEFORE_ALLOC_NO: + /* if it is miss then it is same as no search before alloc */ + if (!hit || tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE) { /*Scan identifier list, allocate identifier and update regfile*/ rc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl); /* Create the result blob */ @@ -1645,60 +1631,29 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, if (!rc) rc = ulp_mapper_tcam_tbl_entry_write(parms, tbl, &key, &mask, &data, idx); - break; - case BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP: - /*Scan identifier list, extract identifier and update regfile*/ - rc = ulp_mapper_tcam_tbl_scan_ident_extract(parms, tbl, &data); - break; - case BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE: + } else { /*Scan identifier list, extract identifier and update regfile*/ rc = ulp_mapper_tcam_tbl_scan_ident_extract(parms, tbl, &data); - /* Create the result blob */ - if (!rc) - rc = ulp_mapper_tcam_tbl_result_create(parms, tbl, - &update_data); - /* Update/overwrite the tcam entry */ - if (!rc) - rc = ulp_mapper_tcam_tbl_entry_write(parms, tbl, &key, - &mask, - &update_data, idx); - break; - default: - BNXT_TF_DBG(ERR, "invalid search opcode\n"); - rc = -EINVAL; - break; } if (rc) goto error; - /* - * Only link the entry to the flow db in the event that cache was not - * used. - */ - if (parms->tcam_tbl_opc == BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL) { - fid_parms.direction = tbl->direction; - fid_parms.resource_func = tbl->resource_func; - fid_parms.resource_type = tbl->resource_type; - fid_parms.critical_resource = tbl->critical_resource; - fid_parms.resource_hndl = idx; - rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); - if (rc) { - BNXT_TF_DBG(ERR, - "Failed to link resource to flow rc = %d\n", - rc); - /* Need to free the identifier, so goto error */ - goto error; - } - } else { - /* - * Reset the tcam table opcode to normal in case the next tcam - * entry does not use cache. - */ - parms->tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL; + + /* Add the tcam index to the flow database */ + fid_parms.direction = tbl->direction; + fid_parms.resource_func = tbl->resource_func; + fid_parms.resource_type = tbl->resource_type; + fid_parms.critical_resource = tbl->critical_resource; + fid_parms.resource_hndl = idx; + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n", + rc); + /* Need to free the identifier, so goto error */ + goto error; } return 0; error: - parms->tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL; free_parms.dir = tbl->direction; free_parms.tcam_tbl_type = tbl->resource_type; free_parms.idx = idx; @@ -1706,7 +1661,6 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, if (trc) BNXT_TF_DBG(ERR, "Failed to free tcam[%d][%d][%d] on failure\n", tbl->resource_type, tbl->direction, idx); - return rc; } @@ -2976,7 +2930,6 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, parms.comp_fld = cparms->comp_fld; parms.tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); parms.ulp_ctx = ulp_ctx; - parms.tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL; parms.act_tid = cparms->act_tid; parms.class_tid = cparms->class_tid; parms.flow_type = cparms->flow_type; diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 8bc6cdbdd5..4c423d2374 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -18,20 +18,6 @@ #define ULP_IDENTS_INVALID ((uint16_t)0xffff) -/* - * The cache table opcode is used to convey informat from the cache handler - * to the tcam handler. The opcodes do the following: - * NORMAL - tcam should process all instructions as normal - * SKIP - tcam is using the cached entry and doesn't need to process the - * instruction. - * ALLOC - tcam needs to allocate the tcam index and store in the cache entry - */ -enum bnxt_ulp_cache_table_opc { - BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL, - BNXT_ULP_MAPPER_TCAM_TBL_OPC_CACHE_SKIP, - BNXT_ULP_MAPPER_TCAM_TBL_OPC_CACHE_ALLOC -}; - struct bnxt_ulp_mapper_glb_resource_entry { enum bnxt_ulp_resource_func resource_func; uint32_t resource_type; /* TF_ enum type */ @@ -66,7 +52,6 @@ struct bnxt_ulp_mapper_parms { uint32_t fid; enum bnxt_ulp_fdb_type flow_type; struct bnxt_ulp_mapper_data *mapper_data; - enum bnxt_ulp_cache_table_opc tcam_tbl_opc; struct bnxt_ulp_device_params *device_params; uint32_t parent_fid; uint32_t parent_flow; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index e4b8c56472..ddc396b3f9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -323,6 +323,13 @@ enum bnxt_ulp_regfile_index { BNXT_ULP_REGFILE_INDEX_LAST = 30 }; +enum bnxt_ulp_tcam_tbl_opc { + BNXT_ULP_TCAM_TBL_OPC_NOT_USED = 0, + BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE = 1, + BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2, + BNXT_ULP_TCAM_TBL_OPC_LAST = 3 +}; + enum bnxt_ulp_search_before_alloc { BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0, BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP = 1, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index f248d33203..a505337bb2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -226,7 +226,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1, .blob_key_bit_size = 167, @@ -295,7 +296,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 14, .blob_key_bit_size = 167, @@ -335,7 +337,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 28, .blob_key_bit_size = 167, @@ -434,7 +437,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 42, .blob_key_bit_size = 167, @@ -523,7 +527,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 82, .blob_key_bit_size = 167, @@ -590,7 +595,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 95, .blob_key_bit_size = 167, @@ -624,7 +630,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 108, .blob_key_bit_size = 167, @@ -660,7 +667,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_1, .key_start_idx = 124, .blob_key_bit_size = 81, @@ -715,7 +723,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 189, .blob_key_bit_size = 167, @@ -751,7 +760,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_1, .key_start_idx = 205, .blob_key_bit_size = 81, @@ -823,7 +833,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 271, .blob_key_bit_size = 167, @@ -859,7 +870,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 287, .blob_key_bit_size = 81, @@ -931,7 +943,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 353, .blob_key_bit_size = 167, @@ -967,7 +980,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 369, .blob_key_bit_size = 81, @@ -1039,7 +1053,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 435, .blob_key_bit_size = 167, @@ -1075,7 +1090,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 451, .blob_key_bit_size = 81, @@ -1147,7 +1163,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 517, .blob_key_bit_size = 167, @@ -1183,7 +1200,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 533, .blob_key_bit_size = 81, @@ -1238,7 +1256,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 598, .blob_key_bit_size = 167, @@ -1274,7 +1293,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 614, .blob_key_bit_size = 81, @@ -1329,7 +1349,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 679, .blob_key_bit_size = 167, @@ -1365,7 +1386,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 695, .blob_key_bit_size = 81, @@ -1420,7 +1442,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 760, .blob_key_bit_size = 167, @@ -1456,7 +1479,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 776, .blob_key_bit_size = 81, @@ -1511,7 +1535,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 841, .blob_key_bit_size = 167, @@ -1547,7 +1572,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 857, .blob_key_bit_size = 81, @@ -1602,7 +1628,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 922, .blob_key_bit_size = 167, @@ -1638,7 +1665,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 938, .blob_key_bit_size = 81, @@ -1693,7 +1721,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1003, .blob_key_bit_size = 167, @@ -1729,7 +1758,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1019, .blob_key_bit_size = 81, @@ -1801,7 +1831,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1084, .blob_key_bit_size = 167, @@ -1837,7 +1868,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1100, .blob_key_bit_size = 81, @@ -1875,7 +1907,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1148, .blob_key_bit_size = 167, @@ -1911,7 +1944,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1164, .blob_key_bit_size = 81, @@ -1983,7 +2017,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1224, .blob_key_bit_size = 167, @@ -2019,7 +2054,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1240, .blob_key_bit_size = 81, @@ -2091,7 +2127,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1306, .blob_key_bit_size = 167, @@ -2127,7 +2164,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1322, .blob_key_bit_size = 81, @@ -2199,7 +2237,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1388, .blob_key_bit_size = 167, @@ -2235,7 +2274,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1404, .blob_key_bit_size = 81, @@ -2307,7 +2347,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1470, .blob_key_bit_size = 167, @@ -2343,7 +2384,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1486, .blob_key_bit_size = 81, @@ -2398,7 +2440,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1551, .blob_key_bit_size = 167, @@ -2434,7 +2477,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1567, .blob_key_bit_size = 81, @@ -2489,7 +2533,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1624, .blob_key_bit_size = 167, @@ -2525,7 +2570,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .key_start_idx = 1640, .blob_key_bit_size = 81, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 9a15968ea8..ee17390358 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -234,6 +234,7 @@ struct bnxt_ulp_mapper_tbl_info { /* Table opcode for table operations */ uint32_t tbl_opcode; + uint32_t tbl_operand; /* FDB table opcode */ enum bnxt_ulp_fdb_opc fdb_opcode; From patchwork Sun May 30 08:59:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93579 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FD9DA0524; Sun, 30 May 2021 11:04:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D354A4118D; Sun, 30 May 2021 11:01:21 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 891AC41100 for ; Sun, 30 May 2021 11:01:19 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 5A4CC7DC0; Sun, 30 May 2021 02:01:18 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 5A4CC7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365279; bh=OETjWCWlPYGaxqq5FJzF1nJ2k5R/rE+3Wx8axnPj/TM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X1NiukazuaX/OoM90WiWl8GaCNMNCUhx3ugNUf6Pk07Waqj8fB01RUgmBTgvpR0Nr qjaFpNnIyGyYC70NQu52AhUWNm6HlLC1zQxWXKwJrJ/pjU+Hf0hzlF3bFxpzDSOGyh uWolJAQqeNXlkatouM2RWBoA+sAOhNKzspnjys+8= From: Venkat Duvvuru To: dev@dpdk.org Cc: Venkat Duvvuru Date: Sun, 30 May 2021 14:29:02 +0530 Message-Id: <20210530085929.29695-32-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 31/58] net/bnxt: modify VXLAN decap for multichannel mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The driver is using physical port id as the index into the tunnel inner flow table. However, this will not work in case of multichannel mode where multiple physical functions are going to share the same physical port id. When tunnel inner flow offload request comes before tunnel outer flow offload request, the driver caches the tunnel inner flow details and programs it in the hardware after installing the tunnel outer flow in the hardware. If more than one tunnel inner flow arrives before tunnel outer flow is offloaded, the driver rejects any such tunnel inner flow offload requests. This patch fixes the above two problems by 1. Using dpdk port id as the index to store tunnel inner info. 2. Caching any number of tunnel inner flow offload requests that come before offloading tunnel outer flow offload request Signed-off-by: Venkat Duvvuru Reviewed-by: Shahaji Bhosle --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 + drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 3 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 + drivers/net/bnxt/tf_ulp/ulp_tun.c | 192 ++++++++++++------ drivers/net/bnxt/tf_ulp/ulp_tun.h | 30 ++- 5 files changed, 150 insertions(+), 79 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 5c805eef97..59fb530fb1 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -22,6 +22,7 @@ #include "ulp_flow_db.h" #include "ulp_mapper.h" #include "ulp_port_db.h" +#include "ulp_tun.h" /* Linked list of all TF sessions. */ STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list = @@ -533,6 +534,8 @@ ulp_ctx_init(struct bnxt *bp, if (rc) goto error_deinit; + ulp_tun_tbl_init(ulp_data->tun_tbl); + bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp); return rc; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index ddf38ed931..836e94bc60 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -79,6 +79,7 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, struct ulp_rte_parser_params *params, enum bnxt_ulp_fdb_type flow_type) { + memset(mapper_cparms, 0, sizeof(*mapper_cparms)); mapper_cparms->flow_type = flow_type; mapper_cparms->app_priority = params->priority; mapper_cparms->dir_attr = params->dir_attr; @@ -176,7 +177,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, params.fid = fid; params.func_id = func_id; params.priority = attr->priority; - params.port_id = bnxt_get_phy_port_id(dev->data->port_id); + params.port_id = dev->data->port_id; /* Perform the rte flow post process */ ret = bnxt_ulp_rte_parser_post_process(¶ms); if (ret == BNXT_TF_RC_ERROR) diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index ee17390358..b253aefe8d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -62,6 +62,7 @@ struct ulp_rte_act_prop { /* Structure to be used for passing all the parser functions */ struct ulp_rte_parser_params { + STAILQ_ENTRY(ulp_rte_parser_params) next; struct ulp_rte_hdr_bitmap hdr_bitmap; struct ulp_rte_hdr_bitmap hdr_fp_bit; struct ulp_rte_field_bitmap fld_bitmap; diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c index 884692947a..6c1ae3ced2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.c +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c @@ -3,6 +3,8 @@ * All rights reserved. */ +#include + #include #include "ulp_tun.h" @@ -48,19 +50,18 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params, goto err; /* Store the tunnel dmac in the tunnel cache table and use it while - * programming tunnel flow F2. + * programming tunnel inner flow. */ memcpy(tun_entry->t_dmac, ¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec, RTE_ETHER_ADDR_LEN); - tun_entry->valid = true; tun_entry->tun_flow_info[params->port_id].state = BNXT_ULP_FLOW_STATE_TUN_O_OFFLD; tun_entry->outer_tun_flow_id = params->fid; - /* F1 and it's related F2s are correlated based on - * Tunnel Destination IP Address. + /* Tunnel outer flow and it's related inner flows are correlated + * based on Tunnel Destination IP Address. */ if (tun_entry->t_dst_ip_valid) goto done; @@ -89,25 +90,27 @@ ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry, { struct bnxt_ulp_mapper_create_parms mparms = { 0 }; struct ulp_per_port_flow_info *flow_info; - struct ulp_rte_parser_params *params; + struct ulp_rte_parser_params *inner_params; int ret; - /* F2 doesn't have tunnel dmac, use the tunnel dmac that was - * stored during F1 programming. + /* Tunnel inner flow doesn't have tunnel dmac, use the tunnel + * dmac that was stored during F1 programming. */ flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id]; - params = &flow_info->first_inner_tun_params; - memcpy(¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX], - tun_entry->t_dmac, RTE_ETHER_ADDR_LEN); - params->parent_fid = tun_entry->outer_tun_flow_id; - params->fid = flow_info->first_tun_i_fid; - - bnxt_ulp_init_mapper_params(&mparms, params, - BNXT_ULP_FDB_TYPE_REGULAR); - - ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms); - if (ret) - PMD_DRV_LOG(ERR, "Failed to create F2 flow."); + STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) { + memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX], + tun_entry->t_dmac, RTE_ETHER_ADDR_LEN); + inner_params->parent_fid = tun_entry->outer_tun_flow_id; + + bnxt_ulp_init_mapper_params(&mparms, inner_params, + BNXT_ULP_FDB_TYPE_REGULAR); + + ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms); + if (ret) + PMD_DRV_LOG(ERR, + "Failed to create inner tun flow, FID:%u.", + inner_params->fid); + } } /* This function either install outer tunnel flow & inner tunnel flow @@ -118,21 +121,18 @@ ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params, struct bnxt_tun_cache_entry *tun_entry, uint16_t tun_idx) { - enum bnxt_ulp_tun_flow_state flow_state; int ret; - flow_state = tun_entry->tun_flow_info[params->port_id].state; ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx); if (ret == BNXT_TF_RC_ERROR) { PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow."); return ret; } - /* If flow_state == BNXT_ULP_FLOW_STATE_NORMAL before installing - * F1, that means F2 is not deferred. Hence, no need to install F2. + /* Install any cached tunnel inner flows that came before tunnel + * outer flow. */ - if (flow_state != BNXT_ULP_FLOW_STATE_NORMAL) - ulp_install_inner_tun_flow(tun_entry, params); + ulp_install_inner_tun_flow(tun_entry, params); return BNXT_TF_RC_FID; } @@ -141,9 +141,10 @@ ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params, * outer tunnel flow request. */ static int32_t -ulp_post_process_first_inner_tun_flow(struct ulp_rte_parser_params *params, +ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params, struct bnxt_tun_cache_entry *tun_entry) { + struct ulp_rte_parser_params *inner_tun_params; struct ulp_per_port_flow_info *flow_info; int ret; @@ -155,19 +156,22 @@ ulp_post_process_first_inner_tun_flow(struct ulp_rte_parser_params *params, if (ret != BNXT_TF_RC_SUCCESS) return BNXT_TF_RC_ERROR; - /* If Tunnel F2 flow comes first then we can't install it in the - * hardware, because, F2 flow will not have L2 context information. - * So, just cache the F2 information and program it in the context - * of F1 flow installation. + /* If Tunnel inner flow comes first then we can't install it in the + * hardware, because, Tunnel inner flow will not have L2 context + * information. So, just cache the Tunnel inner flow information + * and program it in the context of F1 flow installation. */ flow_info = &tun_entry->tun_flow_info[params->port_id]; - memcpy(&flow_info->first_inner_tun_params, params, - sizeof(struct ulp_rte_parser_params)); - - flow_info->first_tun_i_fid = params->fid; - flow_info->state = BNXT_ULP_FLOW_STATE_TUN_I_CACHED; + inner_tun_params = rte_zmalloc("ulp_inner_tun_params", + sizeof(struct ulp_rte_parser_params), 0); + if (!inner_tun_params) + return BNXT_TF_RC_ERROR; + memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params)); + STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params, + next); + flow_info->tun_i_cnt++; - /* F1 and it's related F2s are correlated based on + /* F1 and it's related Tunnel inner flows are correlated based on * Tunnel Destination IP Address. It could be already set, if * the inner flow got offloaded first. */ @@ -248,8 +252,8 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params, int32_t ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) { - bool outer_tun_sig, inner_tun_sig, first_inner_tun_flow; - bool outer_tun_reject, inner_tun_reject, outer_tun_flow, inner_tun_flow; + bool inner_tun_sig, cache_inner_tun_flow; + bool outer_tun_reject, outer_tun_flow, inner_tun_flow; enum bnxt_ulp_tun_flow_state flow_state; struct bnxt_tun_cache_entry *tun_entry; uint32_t l3_tun, l3_tun_decap; @@ -267,40 +271,31 @@ ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) if (rc == BNXT_TF_RC_ERROR) return rc; + if (params->port_id >= RTE_MAX_ETHPORTS) + return BNXT_TF_RC_ERROR; flow_state = tun_entry->tun_flow_info[params->port_id].state; /* Outer tunnel flow validation */ - outer_tun_sig = BNXT_OUTER_TUN_SIGNATURE(l3_tun, params); - outer_tun_flow = BNXT_OUTER_TUN_FLOW(outer_tun_sig); + outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params); outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state, - outer_tun_sig); + outer_tun_flow); /* Inner tunnel flow validation */ inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params); - first_inner_tun_flow = BNXT_FIRST_INNER_TUN_FLOW(flow_state, + cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state, inner_tun_sig); inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig); - inner_tun_reject = BNXT_REJECT_INNER_TUN_FLOW(flow_state, - inner_tun_sig); if (outer_tun_reject) { tun_entry->outer_tun_rej_cnt++; BNXT_TF_DBG(ERR, "Tunnel F1 flow rejected, COUNT: %d\n", tun_entry->outer_tun_rej_cnt); - /* Inner tunnel flow is rejected if it comes between first inner - * tunnel flow and outer flow requests. - */ - } else if (inner_tun_reject) { - tun_entry->inner_tun_rej_cnt++; - BNXT_TF_DBG(ERR, - "Tunnel F2 flow rejected, COUNT: %d\n", - tun_entry->inner_tun_rej_cnt); } - if (outer_tun_reject || inner_tun_reject) + if (outer_tun_reject) return BNXT_TF_RC_ERROR; - else if (first_inner_tun_flow) - return ulp_post_process_first_inner_tun_flow(params, tun_entry); + else if (cache_inner_tun_flow) + return ulp_post_process_cache_inner_tun_flow(params, tun_entry); else if (outer_tun_flow) return ulp_post_process_outer_tun_flow(params, tun_entry, tun_idx); @@ -310,11 +305,86 @@ ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) return BNXT_TF_RC_NORMAL; } +void +ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl) +{ + struct ulp_per_port_flow_info *flow_info; + int i, j; + + for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { + for (j = 0; j < RTE_MAX_ETHPORTS; j++) { + flow_info = &tun_tbl[i].tun_flow_info[j]; + STAILQ_INIT(&flow_info->tun_i_prms_list); + } + } +} + void ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx) { + struct ulp_rte_parser_params *inner_params; + struct ulp_per_port_flow_info *flow_info; + int j; + + for (j = 0; j < RTE_MAX_ETHPORTS; j++) { + flow_info = &tun_tbl[tun_idx].tun_flow_info[j]; + STAILQ_FOREACH(inner_params, + &flow_info->tun_i_prms_list, + next) { + STAILQ_REMOVE(&flow_info->tun_i_prms_list, + inner_params, + ulp_rte_parser_params, next); + rte_free(inner_params); + } + } + memset(&tun_tbl[tun_idx], 0, - sizeof(struct bnxt_tun_cache_entry)); + sizeof(struct bnxt_tun_cache_entry)); + + for (j = 0; j < RTE_MAX_ETHPORTS; j++) { + flow_info = &tun_tbl[tun_idx].tun_flow_info[j]; + STAILQ_INIT(&flow_info->tun_i_prms_list); + } +} + +static bool +ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry, + struct ulp_per_port_flow_info *flow_info, + uint32_t fid) +{ + struct ulp_rte_parser_params *inner_params; + int j; + + STAILQ_FOREACH(inner_params, + &flow_info->tun_i_prms_list, + next) { + if (inner_params->fid == fid) { + STAILQ_REMOVE(&flow_info->tun_i_prms_list, + inner_params, + ulp_rte_parser_params, + next); + rte_free(inner_params); + flow_info->tun_i_cnt--; + /* When a dpdk application offloads a duplicate + * tunnel inner flow on a port that it is not + * destined to, there won't be a tunnel outer flow + * associated with these duplicate tunnel inner flows. + * So, when the last tunnel inner flow ages out, the + * driver has to clear the tunnel entry, otherwise + * the tunnel entry cannot be reused. + */ + if (!flow_info->tun_i_cnt && + flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) { + memset(tun_entry, 0, + sizeof(struct bnxt_tun_cache_entry)); + for (j = 0; j < RTE_MAX_ETHPORTS; j++) + STAILQ_INIT(&flow_info->tun_i_prms_list); + } + return true; + } + } + + return false; } /* When a dpdk application offloads the same tunnel inner flow @@ -330,12 +400,14 @@ ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid) struct ulp_per_port_flow_info *flow_info; int i, j; - for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES ; i++) { + for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { + if (!tun_tbl[i].t_dst_ip_valid) + continue; for (j = 0; j < RTE_MAX_ETHPORTS; j++) { flow_info = &tun_tbl[i].tun_flow_info[j]; - if (flow_info->first_tun_i_fid == fid && - flow_info->state == BNXT_ULP_FLOW_STATE_TUN_I_CACHED) - memset(flow_info, 0, sizeof(*flow_info)); + if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i], + flow_info, fid) == true) + return; } } } diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h index af6926f0e4..7e31f81f13 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.h +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h @@ -15,7 +15,7 @@ #include "ulp_template_db_enum.h" #include "ulp_template_struct.h" -#define BNXT_OUTER_TUN_SIGNATURE(l3_tun, params) \ +#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \ ((l3_tun) && \ ULP_BITMAP_ISSET((params)->act_bitmap.bits, \ BNXT_ULP_ACTION_BIT_JUMP)) @@ -24,22 +24,16 @@ !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \ BNXT_ULP_HDR_BIT_O_ETH)) -#define BNXT_FIRST_INNER_TUN_FLOW(state, inner_tun_sig) \ +#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig)) #define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig)) -#define BNXT_OUTER_TUN_FLOW(outer_tun_sig) ((outer_tun_sig)) /* It is invalid to get another outer flow offload request * for the same tunnel, while the outer flow is already offloaded. */ #define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig)) -/* It is invalid to get another inner flow offload request - * for the same tunnel, while the outer flow is not yet offloaded. - */ -#define BNXT_REJECT_INNER_TUN_FLOW(state, inner_tun_sig) \ - ((state) == BNXT_ULP_FLOW_STATE_TUN_I_CACHED && (inner_tun_sig)) #define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1 #define ULP_TUN_O_IPV4_DIP_INDEX 19 @@ -50,10 +44,10 @@ * requests arrive. * * If inner tunnel flow offload request arrives first then the flow - * state will change from BNXT_ULP_FLOW_STATE_NORMAL to - * BNXT_ULP_FLOW_STATE_TUN_I_CACHED and the following outer tunnel - * flow offload request will change the state of the flow to - * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from BNXT_ULP_FLOW_STATE_TUN_I_CACHED. + * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state. + * The following outer tunnel flow offload request will change the + * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from + * BNXT_ULP_FLOW_STATE_NORMAL. * * If outer tunnel flow offload request arrives first then the flow state * will change from BNXT_ULP_FLOW_STATE_NORMAL to @@ -67,17 +61,15 @@ enum bnxt_ulp_tun_flow_state { BNXT_ULP_FLOW_STATE_NORMAL = 0, BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, - BNXT_ULP_FLOW_STATE_TUN_I_CACHED }; struct ulp_per_port_flow_info { - enum bnxt_ulp_tun_flow_state state; - uint32_t first_tun_i_fid; - struct ulp_rte_parser_params first_inner_tun_params; + enum bnxt_ulp_tun_flow_state state; + uint32_t tun_i_cnt; + STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list; }; struct bnxt_tun_cache_entry { - bool valid; bool t_dst_ip_valid; uint8_t t_dmac[RTE_ETHER_ADDR_LEN]; union { @@ -86,10 +78,12 @@ struct bnxt_tun_cache_entry { }; uint32_t outer_tun_flow_id; uint16_t outer_tun_rej_cnt; - uint16_t inner_tun_rej_cnt; struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS]; }; +void +ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl); + void ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx); From patchwork Sun May 30 08:59:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93580 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ECD10A0524; Sun, 30 May 2021 11:04:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E5A684111B; Sun, 30 May 2021 11:01:24 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 448EE4118D for ; Sun, 30 May 2021 11:01:21 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id A3EE97DAF; Sun, 30 May 2021 02:01:19 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com A3EE97DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365280; bh=ISxKrnsjwpg5wZNzh6DJFdcc/8AW2lB3Vfwfc5uX2AQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cy39IsjVbG2QT5rkDCQ5Gid7eaD2dF+5FEU2e6WUcgjtt4ogmkYcfq1htu6sXxAbA gVipu49VlPjP9vYto3Re1HNnm+FhWvbqzfuRA+6WO6OM6wCuSewgcT9wKhZzbPvFnG rff0FjBaRjpNzA+tmHfd3jDr847nHScAHL8m8Z4U= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Michael Baucom , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:03 +0530 Message-Id: <20210530085929.29695-33-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 32/58] net/bnxt: modify table processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha 1. Added interface table specific opcode to process interface table entry creation and reuse. This allows reuse of the interface table entry for multiple flows. Changed the regfile apis to store the data in big endian format. 2. The result blob creation being done in tcam, interface, index tables are consolidate to a common method. 3. Added result blob processing for generic table write 4. Modified the index table opcode processing to support new opcodes. 5. The driver was setting key size that did not take into account the word alignment. 6. The hard coded values for critical resource is replaced with template defined values. Signed-off-by: Kishore Padmanabha Signed-off-by: Michael Baucom Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 18 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 4 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 674 ++++++++++-------- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 22 + .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 108 +-- .../tf_ulp/ulp_template_db_wh_plus_class.c | 69 +- 6 files changed, 512 insertions(+), 383 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c index 0edbe77a96..dd2b799b30 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c @@ -5,6 +5,8 @@ #include #include +#include "tf_core.h" +#include "tfp.h" #include "ulp_mapper.h" #include "ulp_flow_db.h" @@ -163,18 +165,20 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir) } /* - * Set the data in the generic table entry + * Set the data in the generic table entry, Data is in Big endian format * * entry [in] - generic table entry * offset [in] - The offset in bits where the data has to be set * len [in] - The length of the data in bits to be set * data [in] - pointer to the data to be used for setting the value. + * data_size [in] - length of the data pointer in bytes. * * returns 0 on success */ int32_t ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, - uint32_t offset, uint32_t len, uint8_t *data) + uint32_t offset, uint32_t len, uint8_t *data, + uint32_t data_size) { /* validate the null arguments */ if (!entry || !data) { @@ -183,12 +187,17 @@ ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, } /* check the size of the buffer for validation */ - if ((offset + len) > ULP_BYTE_2_BITS(entry->byte_data_size)) { + if ((offset + len) > ULP_BYTE_2_BITS(entry->byte_data_size) || + data_size < ULP_BITS_2_BYTE(len)) { BNXT_TF_DBG(ERR, "invalid offset or length %x:%x:%x\n", offset, len, entry->byte_data_size); return -EINVAL; } + /* adjust the data pointer */ + data = data + (data_size - ULP_BITS_2_BYTE(len)); + + /* Push the data into the byte data array */ if (entry->byte_order == BNXT_ULP_BYTE_ORDER_LE) { if (ulp_bs_push_lsb(entry->byte_data, offset, len, data) != len) { @@ -208,7 +217,7 @@ ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, } /* - * Get the data in the generic table entry + * Get the data in the generic table entry, Data is in Big endian format * * entry [in] - generic table entry * offset [in] - The offset in bits where the data has to get @@ -298,6 +307,7 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, tbl_idx, res->resource_hndl); return -EINVAL; } + fid = tfp_be_to_cpu_32(fid); /* Destroy the flow associated with the shared flow id */ if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h index c8a1112af4..701a8d10e5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h @@ -104,12 +104,14 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir); * offset [in] - The offset in bits where the data has to be set * len [in] - The length of the data in bits to be set * data [in] - pointer to the data to be used for setting the value. + * data_size [in] - length of the data pointer in bytes. * * returns 0 on success */ int32_t ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, - uint32_t offset, uint32_t len, uint8_t *data); + uint32_t offset, uint32_t len, uint8_t *data, + uint32_t data_size); /* * Get the data in the generic table entry diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index c511f835ff..eb57ec8ba3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -530,7 +530,7 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms, case BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE: /* allocate a new fid */ rc = ulp_flow_db_fid_alloc(parms->ulp_ctx, - BNXT_ULP_FDB_TYPE_REGULAR, + parms->flow_type, tbl->resource_func, &fid); if (rc) { BNXT_TF_DBG(ERR, @@ -540,7 +540,7 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms, /* Store the allocated fid in regfile*/ val64 = fid; rc = ulp_regfile_write(parms->regfile, tbl->flow_db_operand, - val64); + tfp_cpu_to_be_64(val64)); if (!rc) { BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", tbl->flow_db_operand); @@ -560,7 +560,7 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } /* Use the extracted fid to update the flow resource */ - push_fid = (uint32_t)val64; + push_fid = tfp_be_to_cpu_64((uint32_t)val64); break; default: return rc; /* Nothing to be done */ @@ -584,6 +584,65 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms, return rc; } +/* + * Process the identifier list in the given table. + * Extract the ident from the table entry and + * write it to the reg file. + * returns 0 on success. + */ +static int32_t +ulp_mapper_tbl_ident_scan_ext(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl, + uint8_t *byte_data, + uint32_t byte_data_size, + enum bnxt_ulp_byte_order byte_order) +{ + struct bnxt_ulp_mapper_ident_info *idents; + uint32_t i, num_idents = 0; + uint64_t val64; + + /* validate the null arguments */ + if (!byte_data) { + BNXT_TF_DBG(ERR, "invalid argument\n"); + return -EINVAL; + } + + /* Get the ident list and process each one */ + idents = ulp_mapper_ident_fields_get(parms, tbl, &num_idents); + + for (i = 0; i < num_idents; i++) { + /* check the size of the buffer for validation */ + if ((idents[i].ident_bit_pos + idents[i].ident_bit_size) > + ULP_BYTE_2_BITS(byte_data_size) || + idents[i].ident_bit_size > ULP_BYTE_2_BITS(sizeof(val64))) { + BNXT_TF_DBG(ERR, "invalid offset or length %x:%x:%x\n", + idents[i].ident_bit_pos, + idents[i].ident_bit_size, + byte_data_size); + return -EINVAL; + } + if (byte_order == BNXT_ULP_BYTE_ORDER_LE) + ulp_bs_pull_lsb(byte_data, (uint8_t *)&val64, + sizeof(val64), + idents[i].ident_bit_pos, + idents[i].ident_bit_size); + else + ulp_bs_pull_msb(byte_data, (uint8_t *)&val64, + idents[i].ident_bit_pos, + idents[i].ident_bit_size); + + /* Write it to the regfile, val64 is already in big-endian*/ + if (!ulp_regfile_write(parms->regfile, + idents[i].regfile_idx, + val64)) { + BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", + idents[i].regfile_idx); + return -EINVAL; + } + } + return 0; +} + /* * Process the identifier instruction and either store it in the flow database * or return it in the val (if not NULL) on success. If val is NULL, the @@ -637,7 +696,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_func = ident->resource_func; fid_parms.resource_type = ident->ident_type; fid_parms.resource_hndl = iparms.id; - fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; + fid_parms.critical_resource = tbl->critical_resource; rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { @@ -729,7 +788,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_func = ident->resource_func; fid_parms.resource_type = ident->ident_type; fid_parms.resource_hndl = sparms.search_id; - fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; + fid_parms.critical_resource = tbl->critical_resource; rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to link res to flow rc = %d\n", @@ -1044,6 +1103,57 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, return 0; } +/* + * Result table process and fill the result blob. + * data [out] - the result blob data + */ +static int32_t +ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_blob *data, + const char *name) +{ + struct bnxt_ulp_mapper_result_field_info *dflds; + uint32_t i, num_flds = 0, encap_flds = 0; + int32_t rc = 0; + + /* Get the result field list */ + dflds = ulp_mapper_result_fields_get(parms, tbl, &num_flds, + &encap_flds); + + /* validate the result field list counts */ + if ((tbl->resource_func == BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE && + (!num_flds && !encap_flds)) || !dflds || + (tbl->resource_func != BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE && + (!num_flds || encap_flds))) { + BNXT_TF_DBG(ERR, "Failed to get data fields %x:%x\n", + num_flds, encap_flds); + return -EINVAL; + } + + /* process the result fields, loop through them */ + for (i = 0; i < (num_flds + encap_flds); i++) { + /* set the swap index if encap swap bit is enabled */ + if (parms->device_params->encap_byte_swap && encap_flds && + i == num_flds) + ulp_blob_encap_swap_idx_set(data); + + /* Process the result fields */ + rc = ulp_mapper_result_field_process(parms, tbl->direction, + &dflds[i], data, name); + if (rc) { + BNXT_TF_DBG(ERR, "data field failed\n"); + return rc; + } + } + + /* if encap bit swap is enabled perform the bit swap */ + if (parms->device_params->encap_byte_swap && encap_flds) + ulp_blob_perform_encap_swap(data); + + return rc; +} + /* Function to alloc action record and set the table. */ static int32_t ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms, @@ -1209,7 +1319,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms, } fid_parms.direction = tbl->direction; fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID; - fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; + fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = gfid; rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); @@ -1255,7 +1365,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms, } fid_parms.direction = tbl->direction; fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID; - fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; + fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = act_idx; rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); @@ -1301,7 +1411,7 @@ ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms, } fid_parms.direction = tbl->direction; fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID; - fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; + fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = act_idx; rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); @@ -1310,43 +1420,6 @@ ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms, return rc; } -/* - * Tcam table - create the result blob. - * data [out] - the result blob data - */ -static int32_t -ulp_mapper_tcam_tbl_result_create(struct bnxt_ulp_mapper_parms *parms, - struct bnxt_ulp_mapper_tbl_info *tbl, - struct ulp_blob *data) -{ - struct bnxt_ulp_mapper_result_field_info *dflds; - uint32_t num_dflds; - uint32_t encap_flds = 0; - uint32_t i; - int32_t rc = 0; - - /* Create the result data blob */ - dflds = ulp_mapper_result_fields_get(parms, tbl, &num_dflds, - &encap_flds); - if (!dflds || !num_dflds || encap_flds) { - BNXT_TF_DBG(ERR, "Failed to get data fields.\n"); - return -EINVAL; - } - - for (i = 0; i < num_dflds; i++) { - rc = ulp_mapper_result_field_process(parms, - tbl->direction, - &dflds[i], - data, - "TCAM Result"); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to set data fields\n"); - return -EINVAL; - } - } - return rc; -} - /* Tcam table scan the identifier list and allocate each identifier */ static int32_t ulp_mapper_tcam_tbl_scan_ident_alloc(struct bnxt_ulp_mapper_parms *parms, @@ -1418,8 +1491,8 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, sparms.idx = idx; /* Already verified the key/mask lengths */ sparms.key = ulp_blob_data_get(key, &tmplen); + sparms.key_sz_in_bits = tmplen; sparms.mask = ulp_blob_data_get(mask, &tmplen); - sparms.key_sz_in_bits = tbl->key_bit_size; sparms.result = ulp_blob_data_get(data, &tmplen); if (tbl->result_bit_size != tmplen) { @@ -1625,8 +1698,8 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl); /* Create the result blob */ if (!rc) - rc = ulp_mapper_tcam_tbl_result_create(parms, tbl, - &data); + rc = ulp_mapper_tbl_result_build(parms, tbl, &data, + "TCAM Result"); /* write the tcam entry */ if (!rc) rc = ulp_mapper_tcam_tbl_entry_write(parms, tbl, &key, @@ -1669,9 +1742,8 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { struct bnxt_ulp_mapper_key_field_info *kflds; - struct bnxt_ulp_mapper_result_field_info *dflds; struct ulp_blob key, data; - uint32_t i, num_kflds, num_dflds; + uint32_t i, num_kflds; uint16_t tmplen; struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); struct ulp_flow_db_res_params fid_parms = { 0 }; @@ -1680,7 +1752,6 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, enum bnxt_ulp_flow_mem_type mtype; int32_t trc; int32_t rc = 0; - uint32_t encap_flds = 0; rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype); if (rc) { @@ -1721,27 +1792,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, */ /* Create the result data blob */ - dflds = ulp_mapper_result_fields_get(parms, tbl, - &num_dflds, &encap_flds); - if (!dflds || !num_dflds || encap_flds) { - BNXT_TF_DBG(ERR, "Failed to get data fields.\n"); - return -EINVAL; - } - - for (i = 0; i < num_dflds; i++) { - struct bnxt_ulp_mapper_result_field_info *fld; - - fld = &dflds[i]; - - rc = ulp_mapper_result_field_process(parms, - tbl->direction, - fld, - &data, - "EM Result"); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to set data fields.\n"); - return rc; - } + rc = ulp_mapper_tbl_result_build(parms, tbl, &data, "EM Result"); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to build the result blob\n"); + return rc; } /* do the transpose for the internal EM keys */ if (tbl->resource_func == BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) @@ -1818,28 +1872,23 @@ static int32_t ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { - struct bnxt_ulp_mapper_result_field_info *flds; - struct ulp_flow_db_res_params fid_parms; + struct ulp_flow_db_res_params fid_parms; struct ulp_blob data; - uint64_t idx = 0; + uint64_t regval = 0; uint16_t tmplen; - uint32_t i, num_flds, index, hit; + uint32_t index, hit; int32_t rc = 0, trc = 0; - struct tf_alloc_tbl_entry_parms aparms = { 0 }; + struct tf_alloc_tbl_entry_parms aparms = { 0 }; struct tf_search_tbl_entry_parms srchparms = { 0 }; - struct tf_set_tbl_entry_parms sparms = { 0 }; - struct tf_free_tbl_entry_parms free_parms = { 0 }; + struct tf_set_tbl_entry_parms sparms = { 0 }; + struct tf_get_tbl_entry_parms gparms = { 0 }; + struct tf_free_tbl_entry_parms free_parms = { 0 }; uint32_t tbl_scope_id; struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); uint16_t bit_size; - uint32_t encap_flds = 0; - - /* Get the scope id first */ - rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, &tbl_scope_id); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to get table scope rc=%d\n", rc); - return rc; - } + bool alloc = false; + bool write = false; + bool search = false; /* use the max size if encap is enabled */ if (tbl->encap_num_fields) @@ -1850,82 +1899,150 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* Initialize the blob data */ if (!ulp_blob_init(&data, bit_size, parms->device_params->byte_order)) { - BNXT_TF_DBG(ERR, "Failed initial index table blob\n"); + BNXT_TF_DBG(ERR, "Failed to initialize index table blob\n"); return -EINVAL; } - /* Get the result fields list */ - flds = ulp_mapper_result_fields_get(parms, tbl, &num_flds, &encap_flds); - - if (!flds || (!num_flds && !encap_flds)) { - BNXT_TF_DBG(ERR, "template undefined for the index table\n"); - return -EINVAL; + /* Get the scope id first */ + rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, &tbl_scope_id); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to get table scope rc=%d\n", rc); + return rc; } - /* process the result fields, loop through them */ - for (i = 0; i < (num_flds + encap_flds); i++) { - /* set the swap index if encap swap bit is enabled */ - if (parms->device_params->encap_byte_swap && encap_flds && - i == num_flds) - ulp_blob_encap_swap_idx_set(&data); - - /* Process the result fields */ - rc = ulp_mapper_result_field_process(parms, - tbl->direction, - &flds[i], - &data, - "Indexed Result"); - if (rc) { - BNXT_TF_DBG(ERR, "data field failed\n"); - return rc; + switch (tbl->tbl_opcode) { + case BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE: + alloc = true; + break; + case BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE: + /* + * Build the entry, alloc an index, write the table, and store + * the data in the regfile. + */ + alloc = true; + write = true; + break; + case BNXT_ULP_INDEX_TBL_OPC_SRCH_ALLOC_WR_REGFILE: + if (tbl->resource_type == TF_TBL_TYPE_EXT) { + /* Not currently supporting with EXT */ + BNXT_TF_DBG(ERR, + "Ext Table Search Opcode not supported.\n"); + return -EINVAL; } - } - - /* if encap bit swap is enabled perform the bit swap */ - if (parms->device_params->encap_byte_swap && encap_flds) { - ulp_blob_perform_encap_swap(&data); - } + /* + * Search for the entry in the tf core. If it is hit, save the + * index in the regfile. If it is a miss, Build the entry, + * alloc an index, write the table, and store the data in the + * regfile (same as ALLOC_WR). + */ + search = true; + break; + case BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE: + /* + * get the index to write to from the regfile and then write + * the table entry. + */ + if (!ulp_regfile_read(parms->regfile, + tbl->tbl_operand, + ®val)) { + BNXT_TF_DBG(ERR, + "Failed to get tbl idx from regfile[%d].\n", + tbl->tbl_operand); + return -EINVAL; + } + index = tfp_be_to_cpu_64(regval); + /* For external, we need to reverse shift */ + if (tbl->resource_type == TF_TBL_TYPE_EXT) + index = TF_ACT_REC_PTR_2_OFFSET(index); - /* - * Check for index opcode, if it is Global then - * no need to allocate the table, just set the table - * and exit since it is not maintained in the flow db. - */ - if (tbl->index_opcode == BNXT_ULP_INDEX_OPCODE_GLOBAL) { - /* get the index from index operand */ - if (tbl->index_operand < BNXT_ULP_GLB_REGFILE_INDEX_LAST && - ulp_mapper_glb_resource_read(parms->mapper_data, + write = true; + break; + case BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE: + /* + * get the index to write to from the global regfile and then + * write the table. + */ + if (ulp_mapper_glb_resource_read(parms->mapper_data, tbl->direction, - tbl->index_operand, - &idx)) { - BNXT_TF_DBG(ERR, "Glbl regfile[%d] read failed.\n", + tbl->tbl_operand, + ®val)) { + BNXT_TF_DBG(ERR, + "Failed to get tbl idx from Global " + "regfile[%d].\n", tbl->index_operand); return -EINVAL; } - /* set the Tf index table */ - sparms.dir = tbl->direction; - sparms.type = tbl->resource_type; - sparms.data = ulp_blob_data_get(&data, &tmplen); - sparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen); - sparms.idx = tfp_be_to_cpu_64(idx); - sparms.tbl_scope_id = tbl_scope_id; + index = tfp_be_to_cpu_64(regval); + /* For external, we need to reverse shift */ + if (tbl->resource_type == TF_TBL_TYPE_EXT) + index = TF_ACT_REC_PTR_2_OFFSET(index); + write = true; + break; + case BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE: + /* + * The read is different from the rest and can be handled here + * instead of trying to use common code. Simply read the table + * with the index from the regfile, scan and store the + * identifiers, and return. + */ + if (tbl->resource_type == TF_TBL_TYPE_EXT) { + /* Not currently supporting with EXT */ + BNXT_TF_DBG(ERR, + "Ext Table Read Opcode not supported.\n"); + return -EINVAL; + } + if (!ulp_regfile_read(parms->regfile, + tbl->tbl_operand, ®val)) { + BNXT_TF_DBG(ERR, + "Failed to get tbl idx from regfile[%d]\n", + tbl->tbl_operand); + return -EINVAL; + } + index = tfp_be_to_cpu_64(regval); + gparms.dir = tbl->direction; + gparms.type = tbl->resource_type; + gparms.data = ulp_blob_data_get(&data, &tmplen); + gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tbl->result_bit_size); + gparms.idx = index; + rc = tf_get_tbl_entry(tfp, &gparms); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to read the tbl entry %d:%d\n", + tbl->resource_type, index); + return rc; + } + /* + * Scan the fields in the entry and push them into the regfile. + */ + rc = ulp_mapper_tbl_ident_scan_ext(parms, tbl, + gparms.data, + gparms.data_sz_in_bytes, + data.byte_order); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to read fields on tbl read " + "rc=%d\n", rc); + return rc; + } + return 0; + default: + BNXT_TF_DBG(ERR, "Invalid index table opcode %d\n", + tbl->tbl_opcode); + return -EINVAL; + } - rc = tf_set_tbl_entry(tfp, &sparms); + if (write || search) { + /* Get the result fields list */ + rc = ulp_mapper_tbl_result_build(parms, + tbl, + &data, + "Indexed Result"); if (rc) { - BNXT_TF_DBG(ERR, - "Glbl Index table[%s][%s][%x] failed rc=%d\n", - tf_tbl_type_2_str(sparms.type), - tf_dir_2_str(sparms.dir), - sparms.idx, rc); + BNXT_TF_DBG(ERR, "Failed to build the result blob\n"); return rc; } - return 0; /* success */ } - index = 0; - hit = 0; - /* Perform the tf table allocation by filling the alloc params */ - if (tbl->srch_b4_alloc) { + if (search) { + /* Use the result blob to perform a search */ memset(&srchparms, 0, sizeof(srchparms)); srchparms.dir = tbl->direction; srchparms.type = tbl->resource_type; @@ -1948,12 +2065,15 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, } index = srchparms.idx; hit = srchparms.hit; - } else { + if (hit) + write = false; + else + write = true; + } + + if (alloc) { aparms.dir = tbl->direction; aparms.type = tbl->resource_type; - aparms.search_enable = tbl->srch_b4_alloc; - aparms.result = ulp_blob_data_get(&data, &tmplen); - aparms.result_sz_in_bytes = ULP_BITS_2_BYTE(tmplen); aparms.tbl_scope_id = tbl_scope_id; /* All failures after the alloc succeeds require a free */ @@ -1967,39 +2087,43 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, index = aparms.idx; } - /* - * calculate the idx for the result record, for external EM the offset - * needs to be shifted accordingly. If external non-inline table types - * are used then need to revisit this logic. - */ - if (tbl->resource_type == TF_TBL_TYPE_EXT) - idx = TF_ACT_REC_OFFSET_2_PTR(index); - else - idx = index; + if (search || alloc) { + /* + * Store the index in the regfile since we either allocated it + * or it was a hit. + * + * Calculate the idx for the result record, for external EM the + * offset needs to be shifted accordingly. + * If external non-inline table types are used then need to + * revisit this logic. + */ + if (tbl->resource_type == TF_TBL_TYPE_EXT) + regval = TF_ACT_REC_OFFSET_2_PTR(index); + else + regval = index; - /* Always storing values in Regfile in BE */ - idx = tfp_cpu_to_be_64(idx); - if (tbl->index_opcode == BNXT_ULP_INDEX_OPCODE_ALLOCATE) { - rc = ulp_regfile_write(parms->regfile, tbl->index_operand, idx); + rc = ulp_regfile_write(parms->regfile, + tbl->tbl_operand, + tfp_cpu_to_be_64(regval)); if (!rc) { - BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", - tbl->index_operand); + BNXT_TF_DBG(ERR, "Failed to write regfile[%d] rc=%d\n", + tbl->tbl_operand, rc); goto error; } } - /* Perform the tf table set by filling the set params */ - if (!tbl->srch_b4_alloc || !hit) { - sparms.dir = tbl->direction; - sparms.type = tbl->resource_type; - sparms.data = ulp_blob_data_get(&data, &tmplen); + if (write) { + sparms.dir = tbl->direction; + sparms.type = tbl->resource_type; + sparms.data = ulp_blob_data_get(&data, &tmplen); sparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen); - sparms.idx = index; - sparms.tbl_scope_id = tbl_scope_id; - + sparms.idx = index; + sparms.tbl_scope_id = tbl_scope_id; rc = tf_set_tbl_entry(tfp, &sparms); if (rc) { - BNXT_TF_DBG(ERR, "Set table[%s][%s][%x] failed rc=%d\n", + BNXT_TF_DBG(ERR, + "Index table[%s][%s][%x] write failed " + "rc=%d\n", tf_tbl_type_2_str(sparms.type), tf_dir_2_str(sparms.dir), sparms.idx, rc); @@ -2014,7 +2138,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_type = tbl->resource_type; fid_parms.resource_sub_type = tbl->resource_sub_type; fid_parms.resource_hndl = index; - fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; + fid_parms.critical_resource = tbl->critical_resource; rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { @@ -2051,15 +2175,15 @@ static int32_t ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { - struct bnxt_ulp_mapper_result_field_info *flds; - struct ulp_blob data; + struct ulp_blob data, res_blob; uint64_t idx; uint16_t tmplen; - uint32_t i, num_flds; int32_t rc = 0; struct tf_set_if_tbl_entry_parms iftbl_params = { 0 }; + struct tf_get_if_tbl_entry_parms get_parms = { 0 }; struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); - uint32_t encap_flds; + enum bnxt_ulp_if_tbl_opc if_opc = tbl->tbl_opcode; + uint32_t res_size; /* Initialize the blob data */ if (!ulp_blob_init(&data, tbl->result_bit_size, @@ -2068,34 +2192,64 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } - /* Get the result fields list */ - flds = ulp_mapper_result_fields_get(parms, tbl, &num_flds, &encap_flds); - - if (!flds || !num_flds || encap_flds) { - BNXT_TF_DBG(ERR, "template undefined for the IF table\n"); - return -EINVAL; + /* create the result blob */ + rc = ulp_mapper_tbl_result_build(parms, tbl, &data, "IFtable Result"); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to build the result blob\n"); + return rc; } - /* process the result fields, loop through them */ - for (i = 0; i < num_flds; i++) { - /* Process the result fields */ - rc = ulp_mapper_result_field_process(parms, - tbl->direction, - &flds[i], - &data, - "IFtable Result"); + /* Get the index details */ + switch (if_opc) { + case BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD: + idx = ULP_COMP_FLD_IDX_RD(parms, tbl->tbl_operand); + break; + case BNXT_ULP_IF_TBL_OPC_WR_REGFILE: + if (!ulp_regfile_read(parms->regfile, tbl->tbl_operand, &idx)) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", + tbl->tbl_operand); + return -EINVAL; + } + idx = tfp_be_to_cpu_64(idx); + break; + case BNXT_ULP_IF_TBL_OPC_WR_CONST: + idx = tbl->tbl_operand; + break; + case BNXT_ULP_IF_TBL_OPC_RD_COMP_FIELD: + /* Initialize the result blob */ + if (!ulp_blob_init(&res_blob, tbl->result_bit_size, + parms->device_params->byte_order)) { + BNXT_TF_DBG(ERR, "Failed initial result blob\n"); + return -EINVAL; + } + + /* read the interface table */ + idx = ULP_COMP_FLD_IDX_RD(parms, tbl->tbl_operand); + res_size = ULP_BITS_2_BYTE(tbl->result_bit_size); + get_parms.dir = tbl->direction; + get_parms.type = tbl->resource_type; + get_parms.idx = idx; + get_parms.data = ulp_blob_data_get(&res_blob, &tmplen); + get_parms.data_sz_in_bytes = res_size; + + rc = tf_get_if_tbl_entry(tfp, &get_parms); if (rc) { - BNXT_TF_DBG(ERR, "data field failed\n"); + BNXT_TF_DBG(ERR, "Get table[%d][%s][%x] failed rc=%d\n", + get_parms.type, + tf_dir_2_str(get_parms.dir), + get_parms.idx, rc); return rc; } - } - - /* Get the index details from computed field */ - if (tbl->index_opcode == BNXT_ULP_INDEX_OPCODE_COMP_FIELD) { - idx = ULP_COMP_FLD_IDX_RD(parms, tbl->index_operand); - } else if (tbl->index_opcode == BNXT_ULP_INDEX_OPCODE_CONSTANT) { - idx = tbl->index_operand; - } else { + rc = ulp_mapper_tbl_ident_scan_ext(parms, tbl, + res_blob.data, + res_size, + res_blob.byte_order); + if (rc) + BNXT_TF_DBG(ERR, "Scan and extract failed rc=%d\n", rc); + return rc; + case BNXT_ULP_IF_TBL_OPC_NOT_USED: + return rc; /* skip it */ + default: BNXT_TF_DBG(ERR, "Invalid tbl index opcode\n"); return -EINVAL; } @@ -2123,98 +2277,20 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } -/* - * Process the identifier list in the generic table. - * Extract the ident from the generic table entry and - * write it to the reg file. - */ -static int32_t -ulp_mapper_gen_tbl_ident_scan(struct bnxt_ulp_mapper_parms *parms, - struct bnxt_ulp_mapper_tbl_info *tbl, - struct ulp_mapper_gen_tbl_entry *gen_tbl_ent) -{ - struct bnxt_ulp_mapper_ident_info *idents; - uint32_t i, idx, num_idents = 0; - int32_t rc = 0; - - /* Get the ident list */ - idents = ulp_mapper_ident_fields_get(parms, tbl, &num_idents); - - for (i = 0; i < num_idents; i++) { - /* Extract the index from the result byte data array */ - rc = ulp_mapper_gen_tbl_entry_data_get(gen_tbl_ent, - idents[i].ident_bit_pos, - idents[i].ident_bit_size, - (uint8_t *)&idx, - sizeof(idx)); - - /* validate the extraction */ - if (rc) { - BNXT_TF_DBG(ERR, "failed to read %s:%x:%x\n", - idents[i].description, - idents[i].ident_bit_pos, - idents[i].ident_bit_size); - return -EINVAL; - } - - /* Write it to the regfile */ - if (!ulp_regfile_write(parms->regfile, - idents[i].regfile_idx, idx)) { - BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", - idents[i].regfile_idx); - return -EINVAL; - } - } - return 0; -} - -/* - * Process the identifier list in the generic table. - * Write the ident to the generic table entry - */ -static int32_t -ulp_mapper_gen_tbl_ident_write(struct bnxt_ulp_mapper_parms *parms, - struct bnxt_ulp_mapper_tbl_info *tbl, - struct ulp_mapper_gen_tbl_entry *gen_tbl_ent) -{ - struct bnxt_ulp_mapper_ident_info *idents; - uint32_t i, num_idents = 0; - uint64_t idx; - - /* Get the ident list */ - idents = ulp_mapper_ident_fields_get(parms, tbl, &num_idents); - - for (i = 0; i < num_idents; i++) { - /* read from the regfile */ - if (!ulp_regfile_read(parms->regfile, idents[i].regfile_idx, - &idx)) { - BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", - idents[i].regfile_idx); - return -EINVAL; - } - - /* Update the gen tbl entry with the new data */ - ulp_mapper_gen_tbl_entry_data_set(gen_tbl_ent, - idents[i].ident_bit_pos, - idents[i].ident_bit_size, - (uint8_t *)&idx); - } - return 0; -} - static int32_t ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { struct bnxt_ulp_mapper_key_field_info *kflds; struct ulp_flow_db_res_params fid_parms; - struct ulp_mapper_gen_tbl_entry gen_tbl_ent; + struct ulp_mapper_gen_tbl_entry gen_tbl_ent, *g; uint16_t tmplen; - struct ulp_blob key; + struct ulp_blob key, data; uint8_t *cache_key; int32_t tbl_idx; uint32_t i, ckey, num_kflds = 0; uint32_t gen_tbl_hit = 0, fdb_write = 0; + uint8_t *byte_data; int32_t rc = 0; /* Get the key fields list and build the key. */ @@ -2265,9 +2341,12 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, case BNXT_ULP_GENERIC_TBL_OPC_READ: /* check the reference count */ if (ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) { + g = &gen_tbl_ent; /* Scan ident list and create the result blob*/ - rc = ulp_mapper_gen_tbl_ident_scan(parms, tbl, - &gen_tbl_ent); + rc = ulp_mapper_tbl_ident_scan_ext(parms, tbl, + g->byte_data, + g->byte_data_size, + g->byte_order); if (rc) { BNXT_TF_DBG(ERR, "Failed to scan ident list\n"); @@ -2290,11 +2369,26 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; /* success */ } - /* Create the result blob from the ident list */ - rc = ulp_mapper_gen_tbl_ident_write(parms, tbl, &gen_tbl_ent); + /* Initialize the blob data */ + if (!ulp_blob_init(&data, tbl->result_bit_size, + BNXT_ULP_BYTE_ORDER_BE)) { + BNXT_TF_DBG(ERR, "Failed initial index table blob\n"); + return -EINVAL; + } + + /* Get the result fields list */ + rc = ulp_mapper_tbl_result_build(parms, tbl, &data, + "Gen tbl Result"); if (rc) { - BNXT_TF_DBG(ERR, - "Failed to write ident list\n"); + BNXT_TF_DBG(ERR, "Failed to build the result blob\n"); + return rc; + } + byte_data = ulp_blob_data_get(&data, &tmplen); + rc = ulp_mapper_gen_tbl_entry_data_set(&gen_tbl_ent, 0, + tmplen, byte_data, + ULP_BITS_2_BYTE(tmplen)); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to write generic table\n"); return -EINVAL; } @@ -2310,7 +2404,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* Set the generic entry hit */ rc = ulp_regfile_write(parms->regfile, BNXT_ULP_REGFILE_INDEX_GENERIC_TBL_HIT, - gen_tbl_hit); + tfp_cpu_to_be_64(gen_tbl_hit)); if (!rc) { BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", tbl->index_operand); diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index ddc396b3f9..b9a81d881b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,6 +3,8 @@ * All rights reserved. */ +/* date: Thu Oct 15 17:28:37 2020 */ + #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -230,6 +232,26 @@ enum bnxt_ulp_hdr_type { BNXT_ULP_HDR_TYPE_LAST = 3 }; +enum bnxt_ulp_if_tbl_opc { + BNXT_ULP_IF_TBL_OPC_NOT_USED = 0, + BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD = 1, + BNXT_ULP_IF_TBL_OPC_WR_REGFILE = 2, + BNXT_ULP_IF_TBL_OPC_WR_CONST = 3, + BNXT_ULP_IF_TBL_OPC_RD_COMP_FIELD = 4, + BNXT_ULP_IF_TBL_OPC_LAST = 5 +}; + +enum bnxt_ulp_index_tbl_opc { + BNXT_ULP_INDEX_TBL_OPC_NOT_USED = 0, + BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE = 1, + BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE = 2, + BNXT_ULP_INDEX_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 3, + BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE = 4, + BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE = 5, + BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE = 6, + BNXT_ULP_INDEX_TBL_OPC_LAST = 7 +}; + enum bnxt_ulp_index_opcode { BNXT_ULP_INDEX_OPCODE_NOT_USED = 0, BNXT_ULP_INDEX_OPCODE_ALLOCATE = 1, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index be6149b9ce..73f57409a9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -56,8 +56,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -73,7 +73,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 }, { @@ -90,8 +90,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -105,8 +105,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, - .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -121,8 +121,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -137,8 +137,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -154,8 +154,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -170,8 +170,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -186,8 +186,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -203,8 +203,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -219,8 +219,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -235,8 +235,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -252,8 +252,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -269,7 +269,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 3, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR }, { @@ -286,8 +286,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 3, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -301,8 +301,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -317,8 +317,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 12, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -333,8 +333,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -350,8 +350,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -367,8 +367,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -384,7 +384,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 }, { @@ -400,8 +400,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, - .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -416,8 +416,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -432,8 +432,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 11, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -449,8 +449,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -467,7 +467,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, { @@ -483,8 +483,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -501,8 +501,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -519,8 +519,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 11, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index a505337bb2..0cd9518e2a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -202,8 +202,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, @@ -250,8 +250,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, }, { /* class_tid: 1, wh_plus, table: parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -261,8 +261,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, { /* class_tid: 1, wh_plus, table: parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -272,8 +272,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, { /* class_tid: 2, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -287,8 +287,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -361,8 +361,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, { /* class_tid: 2, wh_plus, table: parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -372,8 +372,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, { /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -383,8 +383,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, { /* class_tid: 3, wh_plus, table: egr_int_vtag_encap_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -398,8 +398,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, { /* class_tid: 3, wh_plus, table: egr_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -413,8 +413,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 3, wh_plus, table: egr_l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, @@ -465,8 +465,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 3, wh_plus, table: ing_l2_cntxt_dtagged_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -551,8 +551,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, - .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, { /* class_tid: 4, wh_plus, table: egr_parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -562,8 +562,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, - .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, { /* class_tid: 4, wh_plus, table: egr_parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -573,8 +573,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, - .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, { /* class_tid: 4, wh_plus, table: ing_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -588,8 +588,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 4, wh_plus, table: ing_l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -623,8 +623,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, - .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -1824,8 +1825,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 1, .encap_num_fields = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, { /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, From patchwork Sun May 30 08:59:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93581 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7B478A0524; Sun, 30 May 2021 11:05:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 23D8B40E64; Sun, 30 May 2021 11:01:26 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 01BFE411CB for ; Sun, 30 May 2021 11:01:23 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 5F5AB7DC2; Sun, 30 May 2021 02:01:21 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 5F5AB7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365282; bh=6pLhWM2jy4KrBVLVzAocQAbygn2R3XVcY4dQfuPYlJw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m1ridYKaka5FUJrCSs/CzLBNFD/LU68/HA5Jilyxb2vDz/ZgIAdV54Q+37lOeuQp+ 10hhBzhmFaDPrlPIlsMuqfPwGqTIvg4lV1eYKINvkAiQnCfnraTT6yQEcNcsBtVka1 sb5JVm3lghAo8Hp6gV+Zgpp2snXTP2jU4RA/zjTU= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:04 +0530 Message-Id: <20210530085929.29695-34-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 33/58] net/bnxt: modify ULP priority opcode processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Added ulp priority opcode to enable flexibility to the usage of the flow priority. New opcodes help template specify the flow priority accordingly. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Douglas Flint Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 7 + drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 27 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 23 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 3 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 92 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 1 + .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 75 +- .../tf_ulp/ulp_template_db_stingray_act.c | 835 ++++++++++++++---- .../tf_ulp/ulp_template_db_stingray_class.c | 620 +++++++------ drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 12 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h | 14 +- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 725 ++++++++++++--- .../tf_ulp/ulp_template_db_wh_plus_class.c | 506 ++++++----- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 18 +- 14 files changed, 1959 insertions(+), 999 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 330965061a..96aef28b92 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -30,6 +30,13 @@ #define BNXT_ULP_VF_REP_ENABLED 0x1 #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) +enum bnxt_ulp_flow_mem_type { + BNXT_ULP_FLOW_MEM_TYPE_INT = 0, + BNXT_ULP_FLOW_MEM_TYPE_EXT = 1, + BNXT_ULP_FLOW_MEM_TYPE_BOTH = 2, + BNXT_ULP_FLOW_MEM_TYPE_LAST = 3 +}; + struct bnxt_ulp_df_rule_info { uint32_t port_to_app_flow_id; uint32_t app_to_port_flow_id; diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 3eddbd6831..054a76b5ee 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ @@ -251,7 +251,8 @@ ulp_bulk_get_flow_stats(struct tf *tfp, */ parms.entry_sz_in_bytes = sizeof(uint64_t); stats = (uint64_t *)fc_info->shadow_hw_tbl[dir].mem_va; - parms.physical_mem_addr = (uintptr_t)fc_info->shadow_hw_tbl[dir].mem_pa; + parms.physical_mem_addr = (uint64_t) + ((uintptr_t)(fc_info->shadow_hw_tbl[dir].mem_pa)); if (!stats) { PMD_DRV_LOG(ERR, @@ -588,11 +589,11 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, if (params.resource_func == BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE && (params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT || + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT || params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT || + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT || params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC)) { + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) { found_cntr_resource = true; break; } @@ -606,7 +607,10 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, dir = params.direction; hw_cntr_id = params.resource_hndl; if (params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT) { + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { + /* TODO: + * Think about optimizing with try_lock later + */ pthread_mutex_lock(&ulp_fc_info->fc_lock); sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx; @@ -623,11 +627,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, } pthread_mutex_unlock(&ulp_fc_info->fc_lock); } else if (params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC) { - /* Get stats from the parent child table */ - ulp_flow_db_parent_flow_count_get(ctxt, flow_id, - &count->hits, &count->bytes, - count->reset); + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) { + /* Get the stats from the parent child table */ + ulp_flow_db_parent_flow_count_get(ctxt, + flow_id, + &count->hits, + &count->bytes); count->hits_set = 1; count->bytes_set = 1; } else { diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 8669edfeba..c599e0c7e1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -720,7 +720,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, if (params->resource_type == TF_TBL_TYPE_ACT_STATS_64 && params->resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT) { + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { /* Store the first HW counter ID for this table */ if (!ulp_fc_mgr_start_idx_isset(ulp_ctxt, params->direction)) ulp_fc_mgr_start_idx_set(ulp_ctxt, params->direction, @@ -833,7 +833,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, */ if (params->resource_type == TF_TBL_TYPE_ACT_STATS_64 && params->resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT) { + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { ulp_fc_mgr_cntr_reset(ulp_ctxt, params->direction, params->resource_hndl); } @@ -1259,7 +1259,7 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx, uint32_t flow_id, uint16_t *cfa_action) { - uint8_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION; + uint8_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION; struct ulp_flow_db_res_params params; int32_t rc; @@ -1267,7 +1267,7 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT, flow_id, BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - sub_type, ¶ms); + sub_typ, ¶ms); if (rc) { BNXT_TF_DBG(ERR, "CFA Action ptr not found for flow id %u\n", flow_id); @@ -1647,7 +1647,7 @@ int32_t ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms) { struct ulp_flow_db_res_params fid_parms; - uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC; + uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC; struct ulp_flow_db_res_params res_params; int32_t fid_idx, rc; @@ -1676,7 +1676,7 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms) BNXT_ULP_FDB_TYPE_REGULAR, parms->fid, BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - sub_type, + sub_typ, &res_params)) { /* Enable the counter accumulation in parent entry */ if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx, @@ -1708,7 +1708,7 @@ int32_t ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms) { struct ulp_flow_db_res_params fid_parms; - uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT; + uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT; enum bnxt_ulp_resource_func res_fun; struct ulp_flow_db_res_params res_p; uint32_t parent_fid = parms->parent_fid; @@ -1819,8 +1819,9 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt, */ int32_t ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, uint64_t *packet_count, - uint64_t *byte_count, uint8_t count_reset) + uint32_t parent_fid, + uint64_t *packet_count, + uint64_t *byte_count) { struct bnxt_ulp_flow_db *flow_db; struct ulp_fdb_parent_child_db *p_pdb; @@ -1841,10 +1842,6 @@ ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, p_pdb->parent_flow_tbl[idx].pkt_count; *byte_count = p_pdb->parent_flow_tbl[idx].byte_count; - if (count_reset) { - p_pdb->parent_flow_tbl[idx].pkt_count = 0; - p_pdb->parent_flow_tbl[idx].byte_count = 0; - } } return 0; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h index 62c914833b..14369271ff 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h @@ -390,8 +390,7 @@ int32_t ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t parent_fid, uint64_t *packet_count, - uint64_t *byte_count, - uint8_t count_reset); + uint64_t *byte_count); /* * reset the parent accumulation counters diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index eb57ec8ba3..bf68155410 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -154,7 +154,7 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, aparms.type = glb_res->resource_type; aparms.dir = glb_res->direction; - aparms.search_enable = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO; + aparms.search_enable = 0; aparms.tbl_scope_id = tbl_scope_id; /* Allocate the index tbl using tf api */ @@ -219,7 +219,7 @@ ulp_mapper_tmpl_reject_list_get(struct bnxt_ulp_mapper_parms *mparms, enum bnxt_ulp_cond_list_opc *opc) { uint32_t idx; - const struct ulp_template_device_tbls *dev_tbls; + const struct bnxt_ulp_template_device_tbls *dev_tbls; dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; *num_tbls = dev_tbls->tmpl_list[tid].reject_info.cond_nums; @@ -236,7 +236,7 @@ ulp_mapper_tbl_execute_list_get(struct bnxt_ulp_mapper_parms *mparms, enum bnxt_ulp_cond_list_opc *opc) { uint32_t idx; - const struct ulp_template_device_tbls *dev_tbls; + const struct bnxt_ulp_template_device_tbls *dev_tbls; dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; *num_tbls = tbl->execute_info.cond_nums; @@ -265,7 +265,7 @@ ulp_mapper_tbl_list_get(struct bnxt_ulp_mapper_parms *mparms, uint32_t *num_tbls) { uint32_t idx; - const struct ulp_template_device_tbls *dev_tbls; + const struct bnxt_ulp_template_device_tbls *dev_tbls; dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; @@ -292,7 +292,7 @@ ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_parms *mparms, uint32_t *num_flds) { uint32_t idx; - const struct ulp_template_device_tbls *dev_tbls; + const struct bnxt_ulp_template_device_tbls *dev_tbls; dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; if (!dev_tbls->key_field_list) { @@ -326,7 +326,7 @@ ulp_mapper_result_fields_get(struct bnxt_ulp_mapper_parms *mparms, uint32_t *num_encap_flds) { uint32_t idx; - const struct ulp_template_device_tbls *dev_tbls; + const struct bnxt_ulp_template_device_tbls *dev_tbls; dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; if (!dev_tbls->result_field_list) { @@ -357,7 +357,7 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_parms *mparms, uint32_t *num_flds) { uint32_t idx; - const struct ulp_template_device_tbls *dev_tbls; + const struct bnxt_ulp_template_device_tbls *dev_tbls; dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; if (!dev_tbls->ident_list) { @@ -584,6 +584,36 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms, return rc; } +/* + * Process the flow database opcode action. + * returns 0 on success. + */ +static int32_t +ulp_mapper_priority_opc_process(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl, + uint32_t *priority) +{ + int32_t rc = 0; + + switch (tbl->pri_opcode) { + case BNXT_ULP_PRI_OPC_NOT_USED: + *priority = 0; + break; + case BNXT_ULP_PRI_OPC_CONST: + *priority = tbl->pri_operand; + break; + case BNXT_ULP_PRI_OPC_APP_PRI: + *priority = parms->app_priority; + break; + default: + BNXT_TF_DBG(ERR, "Priority opcode not supported %d\n", + tbl->pri_opcode); + rc = -EINVAL; + break; + } + return rc; +} + /* * Process the identifier list in the given table. * Extract the ident from the table entry and @@ -1294,11 +1324,11 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms, { struct ulp_flow_db_res_params fid_parms; uint32_t mark, gfid, mark_flag; - enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode; + enum bnxt_ulp_mark_db_opc mark_op = tbl->mark_db_opcode; int32_t rc = 0; - if (mark_op == BNXT_ULP_MARK_DB_OPCODE_NOP || - !(mark_op == BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION && + if (mark_op == BNXT_ULP_MARK_DB_OPC_NOP || + !(mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION && ULP_BITMAP_ISSET(parms->act_bitmap->bits, BNXT_ULP_ACTION_BIT_MARK))) return rc; /* no need to perform gfid process */ @@ -1335,11 +1365,11 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms, struct ulp_flow_db_res_params fid_parms; uint32_t act_idx, mark, mark_flag; uint64_t val64; - enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode; + enum bnxt_ulp_mark_db_opc mark_op = tbl->mark_db_opcode; int32_t rc = 0; - if (mark_op == BNXT_ULP_MARK_DB_OPCODE_NOP || - !(mark_op == BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION && + if (mark_op == BNXT_ULP_MARK_DB_OPC_NOP || + !(mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION && ULP_BITMAP_ISSET(parms->act_bitmap->bits, BNXT_ULP_ACTION_BIT_MARK))) return rc; /* no need to perform mark action process */ @@ -1381,11 +1411,11 @@ ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms, struct ulp_flow_db_res_params fid_parms; uint32_t act_idx, mark, mark_flag; uint64_t val64; - enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode; + enum bnxt_ulp_mark_db_opc mark_op = tbl->mark_db_opcode; int32_t rc = 0; - if (mark_op == BNXT_ULP_MARK_DB_OPCODE_NOP || - mark_op == BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION) + if (mark_op == BNXT_ULP_MARK_DB_OPC_NOP || + mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION) return rc; /* no need to perform mark action process */ /* Get the mark id details from the computed field of dev port id */ @@ -1644,7 +1674,15 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, tmplen, tbl->blob_key_bit_size); return -EINVAL; } - aparms.priority = tbl->priority; + + /* calculate the entry priority */ + rc = ulp_mapper_priority_opc_process(parms, tbl, + &aparms.priority); + if (rc) { + BNXT_TF_DBG(ERR, "entry priority process failed\n"); + return rc; + } + rc = tf_alloc_tcam_entry(tfp, &aparms); if (rc) { BNXT_TF_DBG(ERR, "tcam alloc failed rc=%d.\n", rc); @@ -1662,11 +1700,18 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, searchparms.key = ulp_blob_data_get(&key, &tmplen); searchparms.key_sz_in_bits = tbl->key_bit_size; searchparms.mask = ulp_blob_data_get(&mask, &tmplen); - searchparms.priority = tbl->priority; searchparms.alloc = 1; searchparms.result = ulp_blob_data_get(&data, &tmplen); searchparms.result_sz_in_bits = tbl->result_bit_size; + /* calculate the entry priority */ + rc = ulp_mapper_priority_opc_process(parms, tbl, + &searchparms.priority); + if (rc) { + BNXT_TF_DBG(ERR, "entry priority process failed\n"); + return rc; + } + rc = tf_search_tcam_entry(tfp, &searchparms); if (rc) { BNXT_TF_DBG(ERR, "tcam search failed rc=%d\n", rc); @@ -1969,7 +2014,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, BNXT_TF_DBG(ERR, "Failed to get tbl idx from Global " "regfile[%d].\n", - tbl->index_operand); + tbl->tbl_operand); return -EINVAL; } index = tfp_be_to_cpu_64(regval); @@ -2407,7 +2452,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, tfp_cpu_to_be_64(gen_tbl_hit)); if (!rc) { BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", - tbl->index_operand); + BNXT_ULP_REGFILE_INDEX_GENERIC_TBL_HIT); return -EIO; } @@ -2482,15 +2527,15 @@ ulp_mapper_tbl_memtype_opcode_process(struct bnxt_ulp_mapper_parms *parms, bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype); switch (tbl->mem_type_opcode) { - case BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT: + case BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT: if (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) rc = 0; break; - case BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT: + case BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT: if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT) rc = 0; break; - case BNXT_ULP_MEM_TYPE_OPCODE_NOP: + case BNXT_ULP_MEM_TYPE_OPC_NOP: rc = 0; break; default: @@ -3031,6 +3076,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, parms.parent_fid = cparms->parent_fid; parms.fid = cparms->flow_id; parms.tun_idx = cparms->tun_idx; + parms.app_priority = cparms->app_priority; /* Get the device id from the ulp context */ if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 4c423d2374..bef72696d3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -56,6 +56,7 @@ struct bnxt_ulp_mapper_parms { uint32_t parent_fid; uint32_t parent_flow; uint8_t tun_idx; + uint32_t app_priority; }; struct bnxt_ulp_mapper_create_parms { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index b9a81d881b..6bb26f0ad5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -26,7 +26,6 @@ #define BNXT_ULP_ACT_HID_SHFTR 23 #define BNXT_ULP_ACT_HID_SHFTL 23 #define BNXT_ULP_ACT_HID_MASK 4095 -#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 @@ -201,13 +200,6 @@ enum bnxt_ulp_fdb_opc { BNXT_ULP_FDB_OPC_LAST = 4 }; -enum bnxt_ulp_flow_mem_type { - BNXT_ULP_FLOW_MEM_TYPE_INT = 0, - BNXT_ULP_FLOW_MEM_TYPE_EXT = 1, - BNXT_ULP_FLOW_MEM_TYPE_BOTH = 2, - BNXT_ULP_FLOW_MEM_TYPE_LAST = 3 -}; - enum bnxt_ulp_generic_tbl_opc { BNXT_ULP_GENERIC_TBL_OPC_NOT_USED = 0, BNXT_ULP_GENERIC_TBL_OPC_READ = 1, @@ -252,15 +244,6 @@ enum bnxt_ulp_index_tbl_opc { BNXT_ULP_INDEX_TBL_OPC_LAST = 7 }; -enum bnxt_ulp_index_opcode { - BNXT_ULP_INDEX_OPCODE_NOT_USED = 0, - BNXT_ULP_INDEX_OPCODE_ALLOCATE = 1, - BNXT_ULP_INDEX_OPCODE_GLOBAL = 2, - BNXT_ULP_INDEX_OPCODE_COMP_FIELD = 3, - BNXT_ULP_INDEX_OPCODE_CONSTANT = 4, - BNXT_ULP_INDEX_OPCODE_LAST = 5 -}; - enum bnxt_ulp_mapper_opc { BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT = 0, BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD = 1, @@ -278,11 +261,11 @@ enum bnxt_ulp_mapper_opc { BNXT_ULP_MAPPER_OPC_LAST = 13 }; -enum bnxt_ulp_mark_db_opcode { - BNXT_ULP_MARK_DB_OPCODE_NOP = 0, - BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION = 1, - BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG = 2, - BNXT_ULP_MARK_DB_OPCODE_LAST = 3 +enum bnxt_ulp_mark_db_opc { + BNXT_ULP_MARK_DB_OPC_NOP = 0, + BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION = 1, + BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG = 2, + BNXT_ULP_MARK_DB_OPC_LAST = 3 }; enum bnxt_ulp_match_type { @@ -291,24 +274,18 @@ enum bnxt_ulp_match_type { BNXT_ULP_MATCH_TYPE_LAST = 2 }; -enum bnxt_ulp_mem_type_opcode { - BNXT_ULP_MEM_TYPE_OPCODE_NOP = 0, - BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT = 1, - BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT = 2, - BNXT_ULP_MEM_TYPE_OPCODE_LAST = 3 +enum bnxt_ulp_mem_type_opc { + BNXT_ULP_MEM_TYPE_OPC_NOP = 0, + BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT = 1, + BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT = 2, + BNXT_ULP_MEM_TYPE_OPC_LAST = 3 }; -enum bnxt_ulp_priority { - BNXT_ULP_PRIORITY_LEVEL_0 = 0, - BNXT_ULP_PRIORITY_LEVEL_1 = 1, - BNXT_ULP_PRIORITY_LEVEL_2 = 2, - BNXT_ULP_PRIORITY_LEVEL_3 = 3, - BNXT_ULP_PRIORITY_LEVEL_4 = 4, - BNXT_ULP_PRIORITY_LEVEL_5 = 5, - BNXT_ULP_PRIORITY_LEVEL_6 = 6, - BNXT_ULP_PRIORITY_LEVEL_7 = 7, - BNXT_ULP_PRIORITY_NOT_USED = 8, - BNXT_ULP_PRIORITY_LAST = 9 +enum bnxt_ulp_pri_opc { + BNXT_ULP_PRI_OPC_NOT_USED = 0, + BNXT_ULP_PRI_OPC_CONST = 1, + BNXT_ULP_PRI_OPC_APP_PRI = 2, + BNXT_ULP_PRI_OPC_LAST = 3 }; enum bnxt_ulp_regfile_index { @@ -352,13 +329,6 @@ enum bnxt_ulp_tcam_tbl_opc { BNXT_ULP_TCAM_TBL_OPC_LAST = 3 }; -enum bnxt_ulp_search_before_alloc { - BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0, - BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP = 1, - BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE = 2, - BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 3 -}; - enum bnxt_ulp_template_type { BNXT_ULP_TEMPLATE_TYPE_CLASS = 0, BNXT_ULP_TEMPLATE_TYPE_ACTION = 1, @@ -403,13 +373,14 @@ enum bnxt_ulp_resource_func { enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION = 1, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC = 3, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 4, - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0, - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1 + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL = 0, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION = 1, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT = 2, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC = 3, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT = 4, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM = 0, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL = 2 }; enum bnxt_ulp_sym { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c index 6ad6263183..1381f0a0ee 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c @@ -1,39 +1,54 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ +/* date: Thu Oct 15 17:28:37 2020 */ + #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" #include "ulp_rte_parser.h" -struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_act_tmpl_list[] = { +/* Mapper templates for header act list */ +struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[] = { + /* act-ing-[dec_ttl, count, nat]:1 */ + /* act_tid: 1, stingray, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 0 }, + /* act-ing-[drop, pop_vlan, push_vlan, dec_ttl, count, vxlan_decap]:2 */ + /* act_tid: 2, stingray, ingress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 3, .start_tbl_idx = 6 }, + /* act-ing-[mark, rss, count, pop_vlan, vxlan_decap]:3 */ + /* act_tid: 3, stingray, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 3, .start_tbl_idx = 9 }, + /* act_egr-[vxlan_encap, count]:4 */ + /* act_tid: 4, stingray, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 12 }, + /* act-egr-[dec_ttl, count, nat]:5 */ + /* act_tid: 5, stingray, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, .start_tbl_idx = 18 }, + /* act-egr-[drop, push_vlan, dec_ttl, count]:6 */ + /* act_tid: 6, stingray, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 5, @@ -42,495 +57,470 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_act_tmpl_list[] = { }; struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { - { + { /* act_tid: 1, stingray, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 0, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 1, stingray, table: int_act_modify_ipv4_src_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 1, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 }, - { + { /* act_tid: 1, stingray, table: int_act_modify_ipv4_dst_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 2, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 }, - { + { /* act_tid: 1, stingray, table: int_encap_mac_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 3, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, - .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR }, - { + { /* act_tid: 1, stingray, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 15, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 1, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 41, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 2, stingray, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 67, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 2, stingray, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 68, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 2, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 94, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 3, stingray, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 120, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 3, stingray, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 121, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 3, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 147, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 4, stingray, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 173, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 4, stingray, table: int_sp_smac_ipv4_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, .result_start_idx = 174, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 3, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR }, - { + { /* act_tid: 4, stingray, table: int_sp_smac_ipv6_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, .result_start_idx = 177, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 3, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR }, - { + { /* act_tid: 4, stingray, table: int_tun_encap_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, .result_start_idx = 180, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, - { + { /* act_tid: 4, stingray, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 192, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 4, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 230, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 5, stingray, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 256, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 5, stingray, table: int_act_modify_ipv4_src_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 257, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 }, - { + { /* act_tid: 5, stingray, table: int_act_modify_ipv4_dst_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 258, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 }, - { + { /* act_tid: 5, stingray, table: int_encap_mac_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 259, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, - .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR }, - { + { /* act_tid: 5, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 271, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 5, stingray, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 297, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 11, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 6, stingray, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 334, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 6, stingray, table: int_vtag_encap_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 335, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, - { + { /* act_tid: 6, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 347, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 6, stingray, table: ext_full_act_record_no_tag_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 373, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 6, stingray, table: ext_full_act_record_one_tag_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 399, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 11, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR } }; struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = { + /* act_tid: 1, stingray, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 1, stingray, table: int_act_modify_ipv4_src_0 */ { + .description = "ipv4_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -539,7 +529,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 1, stingray, table: int_act_modify_ipv4_dst_0 */ { + .description = "ipv4_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -548,19 +540,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 1, stingray, table: int_encap_mac_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -569,40 +566,50 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "spare", .field_bit_size = 80, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 1, stingray, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -612,18 +619,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -638,22 +649,27 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -663,12 +679,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -678,6 +696,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -697,6 +716,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -706,6 +726,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -725,18 +746,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -746,6 +771,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -755,6 +781,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -773,6 +800,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -782,22 +810,28 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 1, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -807,18 +841,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -833,18 +871,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -854,6 +896,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -863,6 +906,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -882,6 +926,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -891,6 +936,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -910,18 +956,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -931,6 +981,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -940,6 +991,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -958,6 +1010,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -967,34 +1020,44 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 2, stingray, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 2, stingray, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1004,18 +1067,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1030,30 +1097,37 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1063,6 +1137,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -1082,6 +1157,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1091,6 +1167,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -1110,18 +1187,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -1131,6 +1212,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -1140,6 +1222,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -1156,6 +1239,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1165,6 +1249,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1179,14 +1264,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1200,7 +1288,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 2, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1210,18 +1300,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1236,18 +1330,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1257,6 +1355,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1266,6 +1365,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -1285,6 +1385,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1294,6 +1395,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -1313,18 +1415,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -1334,6 +1440,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -1343,6 +1450,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -1359,6 +1467,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1368,6 +1477,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1382,14 +1492,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1404,18 +1517,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 3, stingray, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 3, stingray, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1425,18 +1544,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1451,66 +1574,82 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -1527,6 +1666,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1536,6 +1676,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1550,18 +1691,23 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 3, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1571,18 +1717,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1597,58 +1747,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -1665,6 +1829,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1674,6 +1839,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1688,30 +1854,39 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 4, stingray, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 4, stingray, table: int_sp_smac_ipv4_0 */ { + .description = "smac", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1721,6 +1896,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1730,10 +1906,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 4, stingray, table: int_sp_smac_ipv6_0 */ { + .description = "smac", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1743,6 +1922,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1752,10 +1932,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 4, stingray, table: int_tun_encap_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -1764,6 +1947,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -1772,6 +1956,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1781,12 +1966,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1796,16 +1983,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_l2_dmac", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1815,6 +2005,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_vtag", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -1826,6 +2017,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_ip", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -1837,6 +2029,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_udp", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1846,6 +2039,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_tun", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -1856,7 +2050,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 4, stingray, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1866,18 +2062,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1892,70 +2092,87 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1965,22 +2182,27 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -1989,6 +2211,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -1997,6 +2220,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2006,12 +2230,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2021,16 +2247,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_l2_dmac", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2040,6 +2269,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_vtag", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -2051,6 +2281,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_ip", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -2062,6 +2293,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_udp", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2071,6 +2303,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_tun", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -2081,7 +2314,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 4, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2091,18 +2326,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2117,18 +2356,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2138,46 +2381,57 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2187,34 +2441,44 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 5, stingray, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 5, stingray, table: int_act_modify_ipv4_src_0 */ { + .description = "ipv4_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2223,7 +2487,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 5, stingray, table: int_act_modify_ipv4_dst_0 */ { + .description = "ipv4_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2232,19 +2498,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 5, stingray, table: int_encap_mac_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -2253,40 +2524,50 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "spare", .field_bit_size = 80, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 5, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2296,18 +2577,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2322,18 +2607,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -2343,6 +2632,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2352,6 +2642,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -2371,6 +2662,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2380,6 +2672,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -2399,18 +2692,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2420,6 +2717,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2429,6 +2727,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -2447,6 +2746,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2456,30 +2756,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 5, stingray, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2489,18 +2797,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2515,30 +2827,37 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2548,6 +2867,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -2567,6 +2887,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2576,6 +2897,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -2595,18 +2917,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2616,6 +2942,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2625,6 +2952,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -2643,6 +2971,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2652,34 +2981,42 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -2688,56 +3025,71 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 6, stingray, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 6, stingray, table: int_vtag_encap_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -2746,16 +3098,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2765,6 +3120,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2774,10 +3130,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2787,10 +3145,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "spare", .field_bit_size = 80, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 6, stingray, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2800,18 +3161,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2826,18 +3191,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2847,34 +3216,42 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2884,6 +3261,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2893,10 +3271,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2906,18 +3286,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2932,14 +3316,18 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 6, stingray, table: ext_full_act_record_no_tag_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2949,18 +3337,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2975,58 +3367,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -3036,6 +3442,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -3045,10 +3452,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -3058,18 +3467,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -3083,7 +3496,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 6, stingray, table: ext_full_act_record_one_tag_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -3093,18 +3508,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -3119,58 +3538,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -3180,6 +3613,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -3189,10 +3623,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -3202,6 +3638,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -3216,14 +3653,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -3238,22 +3678,27 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -3262,16 +3707,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -3281,6 +3729,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -3290,10 +3739,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c index c11d1ad96d..53ba637d4e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c @@ -11,7 +11,7 @@ #include "ulp_rte_parser.h" /* Mapper templates for header class list */ -struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_class_tmpl_list[] = { +struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = { /* default-vfr-[port_to_vs]:1 */ /* class_tid: 1, stingray, ingress */ [1] = { @@ -194,22 +194,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 0, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .key_start_idx = 0, .blob_key_bit_size = 12, @@ -226,8 +225,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -238,7 +237,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 1, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 1, stingray, table: parif_def_lkup_arec_ptr_0 */ @@ -249,8 +248,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, { /* class_tid: 1, stingray, table: parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -260,8 +259,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, { /* class_tid: 1, stingray, table: parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -271,23 +270,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF }, { /* class_tid: 2, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 43, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 2, stingray, table: l2_cntxt_tcam_vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -295,8 +293,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 14, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -307,14 +305,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 1, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, @@ -335,8 +333,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 28, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -347,7 +345,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 2, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr_0 */ @@ -358,8 +356,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, { /* class_tid: 2, stingray, table: parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -369,8 +367,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, { /* class_tid: 2, stingray, table: parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -380,44 +378,42 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF }, { /* class_tid: 3, stingray, table: egr_int_vtag_encap_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 99, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, { /* class_tid: 3, stingray, table: egr_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 111, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 3, stingray, table: egr_l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .key_start_idx = 41, .blob_key_bit_size = 12, @@ -434,8 +430,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 42, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -446,30 +442,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 2, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 3, stingray, table: ing_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 150, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 3, stingray, table: ing_l2_cntxt_dtagged_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 55, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -480,15 +475,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 2, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 3, stingray, table: ing_l2_cntxt_stagged_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 68, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -499,14 +494,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 2, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .key_start_idx = 81, .blob_key_bit_size = 12, @@ -523,8 +518,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 82, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -535,7 +530,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 3, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 4, stingray, table: egr_parif_def_lkup_arec_ptr_0 */ @@ -546,8 +541,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, - .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, { /* class_tid: 4, stingray, table: egr_parif_def_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -557,8 +552,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, - .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, { /* class_tid: 4, stingray, table: egr_parif_def_err_arec_ptr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -568,30 +563,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, - .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF }, { /* class_tid: 4, stingray, table: ing_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 219, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, { /* class_tid: 4, stingray, table: ing_l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 95, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -602,30 +596,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 3, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 5, stingray, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 258, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, - .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR }, { /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 108, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -636,14 +629,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 3, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 121, .blob_key_bit_size = 16, @@ -660,8 +653,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_1, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 1, .key_start_idx = 124, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -672,13 +665,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 6, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 167, .blob_key_bit_size = 448, @@ -690,13 +683,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 6, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 178, .blob_key_bit_size = 200, @@ -708,15 +701,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 189, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -727,14 +720,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 202, .blob_key_bit_size = 16, @@ -751,8 +744,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_1, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 1, .key_start_idx = 205, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -763,13 +756,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 7, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 7, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 248, .blob_key_bit_size = 448, @@ -781,13 +774,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 7, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 7, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 259, .blob_key_bit_size = 200, @@ -799,14 +792,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 7, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .key_start_idx = 270, .blob_key_bit_size = 12, @@ -823,8 +816,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 271, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -835,14 +828,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 8, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 284, .blob_key_bit_size = 16, @@ -859,8 +852,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 287, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -871,13 +864,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 9, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 8, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 330, .blob_key_bit_size = 448, @@ -889,13 +882,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 9, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 8, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 341, .blob_key_bit_size = 200, @@ -907,14 +900,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 9, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .key_start_idx = 352, .blob_key_bit_size = 12, @@ -931,8 +924,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 353, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -943,14 +936,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 10, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 366, .blob_key_bit_size = 16, @@ -967,8 +960,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 369, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -979,13 +972,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 11, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 9, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 412, .blob_key_bit_size = 448, @@ -997,13 +990,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 11, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 9, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 423, .blob_key_bit_size = 200, @@ -1015,14 +1008,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 11, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .key_start_idx = 434, .blob_key_bit_size = 12, @@ -1039,8 +1032,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 435, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1051,14 +1044,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 12, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 448, .blob_key_bit_size = 16, @@ -1075,8 +1068,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 451, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1087,13 +1080,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 13, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 10, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 494, .blob_key_bit_size = 448, @@ -1105,13 +1098,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 13, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 10, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 505, .blob_key_bit_size = 392, @@ -1123,14 +1116,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 13, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .key_start_idx = 516, .blob_key_bit_size = 12, @@ -1147,8 +1140,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 517, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1159,14 +1152,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 14, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 530, .blob_key_bit_size = 16, @@ -1183,8 +1176,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 533, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1195,13 +1188,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 15, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 11, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 576, .blob_key_bit_size = 448, @@ -1213,13 +1206,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 15, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 11, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 587, .blob_key_bit_size = 392, @@ -1231,15 +1224,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 15, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 598, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1250,14 +1243,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 15, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 611, .blob_key_bit_size = 16, @@ -1274,8 +1267,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 614, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1286,13 +1279,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 17, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 12, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 657, .blob_key_bit_size = 448, @@ -1304,13 +1297,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 17, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 12, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 668, .blob_key_bit_size = 200, @@ -1322,15 +1315,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 17, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 679, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1341,14 +1334,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 17, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 692, .blob_key_bit_size = 16, @@ -1365,8 +1358,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 695, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1377,13 +1370,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 19, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 13, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 738, .blob_key_bit_size = 448, @@ -1395,13 +1388,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 19, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 13, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 749, .blob_key_bit_size = 200, @@ -1413,15 +1406,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 19, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 760, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1432,14 +1425,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 19, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 773, .blob_key_bit_size = 16, @@ -1456,8 +1449,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 776, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1468,13 +1461,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 21, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 14, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 819, .blob_key_bit_size = 448, @@ -1486,13 +1479,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 21, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 14, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 830, .blob_key_bit_size = 392, @@ -1504,15 +1497,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 21, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 841, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1523,14 +1516,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 21, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 854, .blob_key_bit_size = 16, @@ -1547,8 +1540,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 857, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1559,13 +1552,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 23, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 15, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 900, .blob_key_bit_size = 448, @@ -1577,13 +1570,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 23, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 15, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 911, .blob_key_bit_size = 392, @@ -1595,15 +1588,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 23, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 922, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1614,14 +1607,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 23, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 935, .blob_key_bit_size = 16, @@ -1638,8 +1631,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 938, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1650,13 +1643,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 25, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 16, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 981, .blob_key_bit_size = 448, @@ -1668,13 +1661,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 25, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 16, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 992, .blob_key_bit_size = 200, @@ -1686,15 +1679,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 25, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1003, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1705,14 +1698,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 25, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 1016, .blob_key_bit_size = 16, @@ -1729,8 +1722,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1019, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1741,13 +1734,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 27, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 17, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 1062, .blob_key_bit_size = 448, @@ -1759,13 +1752,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 27, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 17, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 1073, .blob_key_bit_size = 392, @@ -1777,32 +1770,31 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 27, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 18, stingray, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 768, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, { /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1084, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1813,14 +1805,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 27, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 1097, .blob_key_bit_size = 16, @@ -1837,8 +1829,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1100, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1849,15 +1841,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 30, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 18, stingray, table: wm_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1143, .blob_key_bit_size = 192, .key_bit_size = 160, @@ -1868,15 +1860,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 30, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1148, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1887,14 +1879,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 30, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 1161, .blob_key_bit_size = 16, @@ -1911,8 +1903,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1164, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1923,13 +1915,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 33, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 19, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 1207, .blob_key_bit_size = 112, @@ -1941,13 +1933,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 33, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 19, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 1215, .blob_key_bit_size = 448, @@ -1959,14 +1951,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 33, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1223, .blob_key_bit_size = 12, @@ -1983,8 +1975,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1224, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -1995,14 +1987,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 34, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1237, .blob_key_bit_size = 16, @@ -2019,8 +2011,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1240, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2031,13 +2023,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 35, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 20, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1283, .blob_key_bit_size = 448, @@ -2049,13 +2041,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 35, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 20, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1294, .blob_key_bit_size = 200, @@ -2067,14 +2059,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 35, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1305, .blob_key_bit_size = 12, @@ -2091,8 +2083,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1306, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -2103,14 +2095,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 36, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1319, .blob_key_bit_size = 16, @@ -2127,8 +2119,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1322, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2139,13 +2131,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 37, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 21, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1365, .blob_key_bit_size = 448, @@ -2157,13 +2149,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 37, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 21, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1376, .blob_key_bit_size = 200, @@ -2175,14 +2167,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 37, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1387, .blob_key_bit_size = 12, @@ -2199,8 +2191,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1388, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -2211,14 +2203,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 38, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1401, .blob_key_bit_size = 16, @@ -2235,8 +2227,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1404, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2247,13 +2239,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 39, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 22, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1447, .blob_key_bit_size = 448, @@ -2265,13 +2257,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 39, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 22, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1458, .blob_key_bit_size = 392, @@ -2283,14 +2275,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 39, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1469, .blob_key_bit_size = 12, @@ -2307,8 +2299,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1470, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -2319,14 +2311,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 40, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1483, .blob_key_bit_size = 16, @@ -2343,8 +2335,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1486, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2355,13 +2347,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 41, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 23, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1529, .blob_key_bit_size = 448, @@ -2373,13 +2365,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 41, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 23, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1540, .blob_key_bit_size = 392, @@ -2391,15 +2383,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 41, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1551, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -2410,14 +2402,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 41, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1564, .blob_key_bit_size = 16, @@ -2434,8 +2426,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1567, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2446,13 +2438,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 43, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 24, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1610, .blob_key_bit_size = 448, @@ -2464,13 +2456,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 43, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 24, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1617, .blob_key_bit_size = 104, @@ -2482,15 +2474,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 43, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1624, .blob_key_bit_size = 171, .key_bit_size = 171, @@ -2501,14 +2493,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 43, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1637, .blob_key_bit_size = 16, @@ -2525,8 +2517,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1640, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2537,13 +2529,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 45, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 25, stingray, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1683, .blob_key_bit_size = 448, @@ -2555,13 +2547,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 45, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 25, stingray, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1690, .blob_key_bit_size = 104, @@ -2573,7 +2565,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 45, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 4fe90d8bb9..bb48ad284a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -547,26 +547,26 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = { /* Specifies parameters for the generic tables */ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { - [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | TF_DIR_RX] = { .result_num_entries = 16384, .result_byte_size = 6, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | TF_DIR_TX] = { .result_num_entries = 16384, .result_byte_size = 6, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | TF_DIR_RX] = { .result_num_entries = 16384, .result_byte_size = 6, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | TF_DIR_TX] = { .result_num_entries = 16384, .result_byte_size = 6, @@ -575,7 +575,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { }; /* device tables */ -const struct ulp_template_device_tbls ulp_template_stingray_tbls[] = { +const struct bnxt_ulp_template_device_tbls ulp_template_stingray_tbls[] = { [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { .tmpl_list = ulp_stingray_class_tmpl_list, .tbl_list = ulp_stingray_class_tbl_list, @@ -591,7 +591,7 @@ const struct ulp_template_device_tbls ulp_template_stingray_tbls[] = { }; /* device tables */ -const struct ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { +const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { .tmpl_list = ulp_wh_plus_class_tmpl_list, .tbl_list = ulp_wh_plus_class_tbl_list, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h index a656f3da52..dbfcc46164 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h @@ -1,14 +1,17 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ +/* date: Mon Sep 21 14:21:33 2020 */ + #ifndef ULP_TEMPLATE_DB_TBL_H_ #define ULP_TEMPLATE_DB_TBL_H_ #include "ulp_template_struct.h" -extern struct bnxt_ulp_mapper_tbl_list_info ulp_wh_plus_class_tmpl_list[]; +/* WH_PLUS template table declarations */ +extern struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[]; @@ -20,14 +23,15 @@ bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[]; extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[]; -extern struct bnxt_ulp_mapper_tbl_list_info ulp_wh_plus_act_tmpl_list[]; +extern struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[]; extern struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[]; -extern struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_class_tmpl_list[]; +/* STINGRAY template table declarations */ +extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[]; @@ -39,7 +43,7 @@ bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]; extern struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[]; -extern struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_act_tmpl_list[]; +extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[]; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 73f57409a9..3c16d8177d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -1,39 +1,54 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ +/* date: Thu Oct 15 17:28:37 2020 */ + #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" #include "ulp_rte_parser.h" -struct bnxt_ulp_mapper_tbl_list_info ulp_wh_plus_act_tmpl_list[] = { +/* Mapper templates for header act list */ +struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { + /* act-ing-[dec_ttl, count, nat]:1 */ + /* act_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 0 }, + /* act-ing-[drop, pop_vlan, push_vlan, dec_ttl, count, vxlan_decap]:2 */ + /* act_tid: 2, wh_plus, ingress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 3, .start_tbl_idx = 6 }, + /* act-ing-[mark, rss, count, pop_vlan, vxlan_decap]:3 */ + /* act_tid: 3, wh_plus, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 3, .start_tbl_idx = 9 }, + /* act_egr-[vxlan_encap, count]:4 */ + /* act_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 12 }, + /* act-egr-[dec_ttl, count, nat]:5 */ + /* act_tid: 5, wh_plus, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, .start_tbl_idx = 18 }, + /* act-egr-[drop, push_vlan, dec_ttl, count]:6 */ + /* act_tid: 6, wh_plus, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, @@ -42,494 +57,469 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_wh_plus_act_tmpl_list[] = { }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { - { + { /* act_tid: 1, wh_plus, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 0, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 1, wh_plus, table: int_act_modify_ipv4_src_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 1, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 }, - { + { /* act_tid: 1, wh_plus, table: int_act_modify_ipv4_dst_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 2, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 }, - { + { /* act_tid: 1, wh_plus, table: int_encap_mac_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 3, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR }, - { + { /* act_tid: 1, wh_plus, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 15, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 1, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 41, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 2, wh_plus, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 67, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 2, wh_plus, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 68, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 2, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 94, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 3, wh_plus, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 120, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 3, wh_plus, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 121, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 3, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 147, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 4, wh_plus, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 173, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 4, wh_plus, table: int_sp_smac_ipv4_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, .result_start_idx = 174, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 3, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR }, - { + { /* act_tid: 4, wh_plus, table: int_sp_smac_ipv6_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, .result_start_idx = 177, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 3, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR }, - { + { /* act_tid: 4, wh_plus, table: int_tun_encap_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP, .result_start_idx = 180, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, - { + { /* act_tid: 4, wh_plus, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 192, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 4, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 230, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 5, wh_plus, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 256, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 5, wh_plus, table: int_act_modify_ipv4_src_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 257, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 }, - { + { /* act_tid: 5, wh_plus, table: int_act_modify_ipv4_dst_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 258, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 + .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 }, - { + { /* act_tid: 5, wh_plus, table: int_encap_mac_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 259, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR }, - { + { /* act_tid: 5, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 271, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 5, wh_plus, table: ext_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 297, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 11, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 6, wh_plus, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 334, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, - { + { /* act_tid: 6, wh_plus, table: int_vtag_encap_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 335, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, - { + { /* act_tid: 6, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 347, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 6, wh_plus, table: ext_full_act_record_no_tag_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 373, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, - { + { /* act_tid: 6, wh_plus, table: ext_full_act_record_one_tag_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 399, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 11, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR } }; struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { + /* act_tid: 1, wh_plus, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 1, wh_plus, table: int_act_modify_ipv4_src_0 */ { + .description = "ipv4_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -538,7 +528,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 1, wh_plus, table: int_act_modify_ipv4_dst_0 */ { + .description = "ipv4_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -547,19 +539,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 1, wh_plus, table: int_encap_mac_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -568,40 +565,50 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "spare", .field_bit_size = 80, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 1, wh_plus, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -611,18 +618,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -637,22 +648,27 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -662,12 +678,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -677,6 +695,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -696,6 +715,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -705,6 +725,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -724,18 +745,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -745,6 +770,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -754,6 +780,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -772,6 +799,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -781,22 +809,28 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 1, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -806,18 +840,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -832,18 +870,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -853,6 +895,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -862,6 +905,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -881,6 +925,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -890,6 +935,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -909,18 +955,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -930,6 +980,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -939,6 +990,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -957,6 +1009,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -966,34 +1019,44 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 2, wh_plus, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 2, wh_plus, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1003,18 +1066,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1029,30 +1096,37 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1062,6 +1136,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -1081,6 +1156,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1090,6 +1166,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -1109,18 +1186,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -1130,6 +1211,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -1139,6 +1221,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -1155,6 +1238,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1164,6 +1248,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1178,14 +1263,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1199,7 +1287,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 2, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1209,18 +1299,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1235,18 +1329,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1256,6 +1354,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1265,6 +1364,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -1284,6 +1384,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1293,6 +1394,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -1312,18 +1414,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -1333,6 +1439,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -1342,6 +1449,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -1358,6 +1466,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1367,6 +1476,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1381,14 +1491,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1403,18 +1516,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 3, wh_plus, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 3, wh_plus, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1424,18 +1543,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1450,66 +1573,82 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -1526,6 +1665,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1535,6 +1675,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1549,18 +1690,23 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 3, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1570,18 +1716,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1596,58 +1746,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -1664,6 +1828,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1673,6 +1838,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1687,30 +1853,39 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 4, wh_plus, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 4, wh_plus, table: int_sp_smac_ipv4_0 */ { + .description = "smac", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1720,6 +1895,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv4_src_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1729,10 +1905,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 4, wh_plus, table: int_sp_smac_ipv6_0 */ { + .description = "smac", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1742,6 +1921,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ipv6_src_addr", .field_bit_size = 128, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1751,10 +1931,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 4, wh_plus, table: int_tun_encap_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -1763,6 +1946,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -1771,6 +1955,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1780,12 +1965,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1795,16 +1982,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_l2_dmac", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1814,6 +2004,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_vtag", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -1825,6 +2016,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_ip", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -1836,6 +2028,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_udp", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1845,6 +2038,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_tun", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -1855,7 +2049,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 4, wh_plus, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -1865,18 +2061,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -1891,70 +2091,87 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -1964,22 +2181,27 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -1988,6 +2210,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -1996,6 +2219,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2005,12 +2229,14 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2020,16 +2246,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_l2_dmac", .field_bit_size = 48, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2039,6 +2268,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_vtag", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -2050,6 +2280,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_ip", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -2061,6 +2292,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_udp", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2070,6 +2302,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "encap_tun", .field_bit_size = 0, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, .result_operand = { @@ -2080,7 +2313,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 4, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2090,18 +2325,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2116,18 +2355,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2137,46 +2380,57 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2186,34 +2440,44 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 5, wh_plus, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 5, wh_plus, table: int_act_modify_ipv4_src_0 */ { + .description = "ipv4_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2222,7 +2486,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 5, wh_plus, table: int_act_modify_ipv4_dst_0 */ { + .description = "ipv4_addr", .field_bit_size = 32, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2231,19 +2497,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 5, wh_plus, table: int_encap_mac_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -2252,40 +2523,50 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "spare", .field_bit_size = 80, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 5, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2295,18 +2576,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2321,18 +2606,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { @@ -2342,6 +2631,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2351,6 +2641,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -2370,6 +2661,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2379,6 +2671,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -2398,18 +2691,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2419,6 +2716,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2428,6 +2726,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -2446,6 +2745,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2455,30 +2755,38 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 5, wh_plus, table: ext_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2488,18 +2796,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2514,30 +2826,37 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2547,6 +2866,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -2566,6 +2886,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2575,6 +2896,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, .result_operand = { @@ -2594,18 +2916,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2615,6 +2941,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2624,6 +2951,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, .result_operand = { @@ -2642,6 +2970,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2651,34 +2980,42 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -2687,56 +3024,71 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 6, wh_plus, table: int_flow_counter_tbl_0 */ { + .description = "count", .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 6, wh_plus, table: int_vtag_encap_record_0 */ { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -2745,16 +3097,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2764,6 +3119,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2773,10 +3129,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2786,10 +3144,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "spare", .field_bit_size = 80, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 6, wh_plus, table: int_full_act_record_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2799,18 +3160,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2825,18 +3190,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2846,34 +3215,42 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2883,6 +3260,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -2892,10 +3270,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -2905,18 +3285,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2931,14 +3315,18 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "hit", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "type", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, + /* act_tid: 6, wh_plus, table: ext_full_act_record_no_tag_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -2948,18 +3336,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -2974,58 +3366,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -3035,6 +3441,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -3044,10 +3451,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -3057,18 +3466,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -3082,7 +3495,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* act_tid: 6, wh_plus, table: ext_full_act_record_one_tag_0 */ { + .description = "flow_cntr_ptr", .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { @@ -3092,18 +3507,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "age_enable", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "agg_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "rate_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "flow_cntr_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -3118,58 +3537,72 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "flow_cntr_ext", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_key", .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_mir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcpflags_match", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_ptr", .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "encap_rec_int", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "dst_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_dst_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "src_ip_ptr", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tcp_src_port", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "meter_id", .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "tl3_rdir", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "l3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -3179,6 +3612,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "tl3_ttl_dec", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { @@ -3188,10 +3622,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "decap_func", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vnic_or_vport", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -3201,6 +3637,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "pop_vlan", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -3215,14 +3652,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "meter", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "mirror", .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "drop", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { @@ -3237,22 +3677,27 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_tun_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l4_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l3_type", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_l2_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_vtag_type", .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { @@ -3261,16 +3706,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "ecv_custom_en", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "ecv_valid", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_tpid", .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -3280,6 +3728,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_vid", .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { @@ -3289,10 +3738,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "vtag_de", .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .description = "vtag_pcp", .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 0cd9518e2a..d1a9a7e092 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -11,7 +11,7 @@ #include "ulp_rte_parser.h" /* Mapper templates for header class list */ -struct bnxt_ulp_mapper_tbl_list_info ulp_wh_plus_class_tmpl_list[] = { +struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* default-vfr-[port_to_vs]:1 */ /* class_tid: 1, wh_plus, ingress */ [1] = { @@ -194,14 +194,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 0, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, @@ -209,7 +208,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 0, .blob_key_bit_size = 8, @@ -228,7 +227,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -239,7 +239,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 1, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 1, wh_plus, table: parif_def_lkup_arec_ptr_0 */ @@ -279,14 +279,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 43, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, @@ -298,7 +297,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 14, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -309,14 +309,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 1, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, @@ -339,7 +339,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 28, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -350,7 +351,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 2, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr_0 */ @@ -390,14 +391,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 99, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 }, @@ -405,14 +405,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 111, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, @@ -420,7 +419,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 41, .blob_key_bit_size = 8, @@ -439,7 +438,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 42, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -450,21 +450,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 2, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 3, wh_plus, table: ing_int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 150, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, @@ -472,8 +471,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 55, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -484,15 +483,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 2, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 3, wh_plus, table: ing_l2_cntxt_stagged_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 68, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -503,14 +502,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 2, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 81, .blob_key_bit_size = 8, @@ -529,7 +528,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 82, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -540,7 +540,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 3, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 4, wh_plus, table: egr_parif_def_lkup_arec_ptr_0 */ @@ -580,14 +580,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 219, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR }, @@ -597,7 +596,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 95, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -608,21 +608,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 3, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 5, wh_plus, table: int_full_act_record_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 258, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP @@ -633,7 +632,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 108, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -644,14 +644,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 3, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 121, .blob_key_bit_size = 16, @@ -670,7 +670,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_1, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 1, .key_start_idx = 124, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -681,13 +682,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 6, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 167, .blob_key_bit_size = 448, @@ -699,13 +700,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 6, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 178, .blob_key_bit_size = 200, @@ -717,7 +718,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ @@ -726,7 +727,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 189, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -737,14 +739,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 202, .blob_key_bit_size = 16, @@ -763,7 +765,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_1, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 1, .key_start_idx = 205, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -774,13 +777,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 7, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 7, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 248, .blob_key_bit_size = 448, @@ -792,13 +795,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 7, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 7, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 259, .blob_key_bit_size = 200, @@ -810,14 +813,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 7, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 270, .blob_key_bit_size = 8, @@ -836,7 +839,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 271, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -847,14 +851,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 8, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 284, .blob_key_bit_size = 16, @@ -873,7 +877,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 287, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -884,13 +889,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 9, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 8, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 330, .blob_key_bit_size = 448, @@ -902,13 +907,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 9, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 8, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 341, .blob_key_bit_size = 200, @@ -920,14 +925,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 9, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 352, .blob_key_bit_size = 8, @@ -946,7 +951,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 353, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -957,14 +963,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 10, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 366, .blob_key_bit_size = 16, @@ -983,7 +989,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 369, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -994,13 +1001,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 11, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 9, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 412, .blob_key_bit_size = 448, @@ -1012,13 +1019,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 11, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 9, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 423, .blob_key_bit_size = 200, @@ -1030,14 +1037,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 11, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 434, .blob_key_bit_size = 8, @@ -1056,7 +1063,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 435, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1067,14 +1075,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 12, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 448, .blob_key_bit_size = 16, @@ -1093,7 +1101,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 451, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1104,13 +1113,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 13, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 10, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 494, .blob_key_bit_size = 448, @@ -1122,13 +1131,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 13, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 10, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 505, .blob_key_bit_size = 392, @@ -1140,14 +1149,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 13, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 516, .blob_key_bit_size = 8, @@ -1166,7 +1175,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 517, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1177,14 +1187,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 14, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 530, .blob_key_bit_size = 16, @@ -1203,7 +1213,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 533, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1214,13 +1225,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 15, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 11, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 576, .blob_key_bit_size = 448, @@ -1232,13 +1243,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 15, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 11, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 587, .blob_key_bit_size = 392, @@ -1250,7 +1261,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 15, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ @@ -1259,7 +1270,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 598, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1270,14 +1282,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 15, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 611, .blob_key_bit_size = 16, @@ -1296,7 +1308,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 614, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1307,13 +1320,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 17, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 12, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 657, .blob_key_bit_size = 448, @@ -1325,13 +1338,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 17, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 12, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 668, .blob_key_bit_size = 200, @@ -1343,7 +1356,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 17, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ @@ -1352,7 +1365,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 679, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1363,14 +1377,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 17, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 692, .blob_key_bit_size = 16, @@ -1389,7 +1403,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 695, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1400,13 +1415,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 19, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 13, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 738, .blob_key_bit_size = 448, @@ -1418,13 +1433,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 19, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 13, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 749, .blob_key_bit_size = 200, @@ -1436,7 +1451,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 19, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ @@ -1445,7 +1460,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 760, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1456,14 +1472,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 19, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 773, .blob_key_bit_size = 16, @@ -1482,7 +1498,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 776, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1493,13 +1510,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 21, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 14, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 819, .blob_key_bit_size = 448, @@ -1511,13 +1528,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 21, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 14, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 830, .blob_key_bit_size = 392, @@ -1529,7 +1546,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 21, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ @@ -1538,7 +1555,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 841, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1549,14 +1567,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 21, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 854, .blob_key_bit_size = 16, @@ -1575,7 +1593,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 857, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1586,13 +1605,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 23, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 15, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 900, .blob_key_bit_size = 448, @@ -1604,13 +1623,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 23, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 15, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 911, .blob_key_bit_size = 392, @@ -1622,7 +1641,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 23, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ @@ -1631,7 +1650,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 922, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1642,14 +1662,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 23, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 935, .blob_key_bit_size = 16, @@ -1668,7 +1688,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 938, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1679,13 +1700,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 25, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 16, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 981, .blob_key_bit_size = 448, @@ -1697,13 +1718,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 25, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 16, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 992, .blob_key_bit_size = 200, @@ -1715,7 +1736,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 25, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ @@ -1724,7 +1745,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1003, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1735,14 +1757,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 25, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 1016, .blob_key_bit_size = 16, @@ -1761,7 +1783,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1019, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1772,13 +1795,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 27, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 17, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 1062, .blob_key_bit_size = 448, @@ -1790,13 +1813,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 27, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 17, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 1073, .blob_key_bit_size = 392, @@ -1808,23 +1831,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 27, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 18, wh_plus, table: int_flow_counter_tbl_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC, .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, .result_start_idx = 768, .result_bit_size = 64, .result_num_fields = 1, .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 }, @@ -1834,7 +1856,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1084, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1845,14 +1868,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 27, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 1097, .blob_key_bit_size = 16, @@ -1871,7 +1894,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1100, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1882,15 +1906,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 30, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 18, wh_plus, table: wm_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1143, .blob_key_bit_size = 192, .key_bit_size = 160, @@ -1901,7 +1925,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 30, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ @@ -1910,7 +1934,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1148, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -1921,14 +1946,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 30, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .key_start_idx = 1161, .blob_key_bit_size = 16, @@ -1947,7 +1972,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1164, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -1958,13 +1984,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 33, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 19, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_RX, .key_start_idx = 1207, .blob_key_bit_size = 112, @@ -1976,13 +2002,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 33, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 19, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, .key_start_idx = 1215, .blob_key_bit_size = 448, @@ -1994,14 +2020,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 33, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1223, .blob_key_bit_size = 8, @@ -2020,7 +2046,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1224, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -2031,14 +2058,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 34, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1237, .blob_key_bit_size = 16, @@ -2057,7 +2084,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1240, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2068,13 +2096,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 35, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 20, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1283, .blob_key_bit_size = 448, @@ -2086,13 +2114,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 35, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 20, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1294, .blob_key_bit_size = 200, @@ -2104,14 +2132,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 35, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1305, .blob_key_bit_size = 8, @@ -2130,7 +2158,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1306, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -2141,14 +2170,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 36, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1319, .blob_key_bit_size = 16, @@ -2167,7 +2196,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1322, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2178,13 +2208,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 37, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 21, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1365, .blob_key_bit_size = 448, @@ -2196,13 +2226,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 37, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 21, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1376, .blob_key_bit_size = 200, @@ -2214,14 +2244,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 37, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1387, .blob_key_bit_size = 8, @@ -2240,7 +2270,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1388, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -2251,14 +2282,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 38, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1401, .blob_key_bit_size = 16, @@ -2277,7 +2308,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1404, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2288,13 +2320,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 39, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 22, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1447, .blob_key_bit_size = 448, @@ -2306,13 +2338,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 39, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 22, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1458, .blob_key_bit_size = 392, @@ -2324,14 +2356,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 39, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1469, .blob_key_bit_size = 8, @@ -2350,7 +2382,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1470, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -2361,14 +2394,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 40, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1483, .blob_key_bit_size = 16, @@ -2387,7 +2420,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1486, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2398,13 +2432,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 41, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 23, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1529, .blob_key_bit_size = 448, @@ -2416,13 +2450,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 41, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 23, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1540, .blob_key_bit_size = 392, @@ -2434,7 +2468,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 41, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ @@ -2443,7 +2477,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1551, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -2454,14 +2489,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 41, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1564, .blob_key_bit_size = 16, @@ -2480,7 +2515,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1567, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2491,13 +2527,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 43, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 24, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1610, .blob_key_bit_size = 448, @@ -2509,13 +2545,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 43, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 24, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1617, .blob_key_bit_size = 104, @@ -2527,7 +2563,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 43, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ @@ -2536,7 +2572,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1624, .blob_key_bit_size = 167, .key_bit_size = 167, @@ -2547,14 +2584,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 43, .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .key_start_idx = 1637, .blob_key_bit_size = 16, @@ -2573,7 +2610,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .key_start_idx = 1640, .blob_key_bit_size = 81, .key_bit_size = 81, @@ -2584,13 +2622,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 45, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO }, { /* class_tid: 25, wh_plus, table: ext_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_TX, .key_start_idx = 1683, .blob_key_bit_size = 448, @@ -2602,13 +2640,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 45, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES }, { /* class_tid: 25, wh_plus, table: int_em_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .direction = TF_DIR_TX, .key_start_idx = 1690, .blob_key_bit_size = 104, @@ -2620,7 +2658,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .encap_num_fields = 0, .ident_start_idx = 45, .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index b253aefe8d..23b4c89896 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -161,8 +161,8 @@ struct bnxt_ulp_mapper_cond_list_info { uint32_t cond_nums; }; -struct ulp_template_device_tbls { - struct bnxt_ulp_mapper_tbl_list_info *tmpl_list; +struct bnxt_ulp_template_device_tbls { + struct bnxt_ulp_mapper_tmpl_info *tmpl_list; struct bnxt_ulp_mapper_tbl_info *tbl_list; struct bnxt_ulp_mapper_key_field_info *key_field_list; struct bnxt_ulp_mapper_result_field_info *result_field_list; @@ -188,11 +188,11 @@ struct bnxt_ulp_device_params { uint64_t packet_count_mask; uint32_t byte_count_shift; uint32_t packet_count_shift; - const struct ulp_template_device_tbls *dev_tbls; + const struct bnxt_ulp_template_device_tbls *dev_tbls; }; /* Flow Mapper */ -struct bnxt_ulp_mapper_tbl_list_info { +struct bnxt_ulp_mapper_tmpl_info { uint32_t device_name; uint32_t start_tbl_idx; uint32_t num_tbls; @@ -206,10 +206,10 @@ struct bnxt_ulp_mapper_tbl_info { struct bnxt_ulp_mapper_cond_list_info execute_info; enum bnxt_ulp_cond_opc cond_opcode; uint32_t cond_operand; - enum bnxt_ulp_mem_type_opcode mem_type_opcode; + enum bnxt_ulp_mem_type_opc mem_type_opcode; uint8_t direction; - uint32_t priority; - enum bnxt_ulp_search_before_alloc srch_b4_alloc; + enum bnxt_ulp_pri_opc pri_opcode; + uint32_t pri_operand; enum bnxt_ulp_critical_resource critical_resource; /* Information for accessing the ulp_key_field_list */ @@ -229,9 +229,7 @@ struct bnxt_ulp_mapper_tbl_info { uint32_t ident_start_idx; uint16_t ident_nums; - enum bnxt_ulp_mark_db_opcode mark_db_opcode; - enum bnxt_ulp_index_opcode index_opcode; - uint32_t index_operand; + enum bnxt_ulp_mark_db_opc mark_db_opcode; /* Table opcode for table operations */ uint32_t tbl_opcode; From patchwork Sun May 30 08:59:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93692 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1659A0524; Tue, 1 Jun 2021 09:40:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6A4F0410F2; Tue, 1 Jun 2021 09:39:58 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id C93AA411C1 for ; Sun, 30 May 2021 11:01:25 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 2142A7DAF; Sun, 30 May 2021 02:01:22 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 2142A7DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365285; bh=V/k5ScS8k+ZhJ4tbLhyThPYmf10CHwcOQnD9qQVbQM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kYEoCHXOfUxQlK1fbJ9YNId7E4l527EVFr74fHWuHaIipkA6ru/xC5t26gUfvxOf5 lVDPWq3sVfTJ8+hFphgj+Ls143fsksK7kazDMWZLoK5w74P9XYZNfSxkstL9mU1Rwc 7SvAAb6gccT6rryTxPTSBJq3awrG4F4DaR8gS70Q= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:05 +0530 Message-Id: <20210530085929.29695-35-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:53 +0200 Subject: [dpdk-dev] [PATCH 34/58] net/bnxt: add support for conflict resolution X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Conflict resolution feature allows rejection of flows based on the previously added flows that conflict. For instance, a five tuple flow is added and then you add a new flow with only 4 tuple instead having same layer2 details then it will be rejected. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 2 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 14 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 +- drivers/net/bnxt/tf_ulp/meson.build | 1 + drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 12 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 64 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 38 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 3 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 789 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_matcher.c | 4 +- drivers/net/bnxt/tf_ulp/ulp_matcher.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 6 +- drivers/net/bnxt/tf_ulp/ulp_port_db.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 412 + drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 55 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 768 +- .../net/bnxt/tf_ulp/ulp_template_db_class.c | 4146 +-- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 1235 +- .../net/bnxt/tf_ulp/ulp_template_db_field.h | 1396 +- .../tf_ulp/ulp_template_db_stingray_act.c | 3706 +- .../tf_ulp/ulp_template_db_stingray_class.c | 28599 ++++----------- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 1024 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h | 24 +- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 3705 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 28654 ++++------------ drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 63 +- drivers/net/bnxt/tf_ulp/ulp_tun.c | 227 +- drivers/net/bnxt/tf_ulp/ulp_tun.h | 39 +- drivers/net/bnxt/tf_ulp/ulp_utils.c | 16 +- drivers/net/bnxt/tf_ulp/ulp_utils.h | 12 +- 36 files changed, 15693 insertions(+), 59347 deletions(-) create mode 100644 drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h index 7b405f4dc3..b2629e47b6 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2019 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 59fb530fb1..458c37b4e9 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2020 Broadcom * All rights reserved. */ @@ -22,7 +22,6 @@ #include "ulp_flow_db.h" #include "ulp_mapper.h" #include "ulp_port_db.h" -#include "ulp_tun.h" /* Linked list of all TF sessions. */ STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list = @@ -55,14 +54,13 @@ bnxt_ulp_devid_get(struct bnxt *bp, { if (BNXT_CHIP_P5(bp)) return -EINVAL; - /* Assuming Whitney */ - *ulp_dev_id = BNXT_ULP_DEVICE_ID_WH_PLUS; if (BNXT_STINGRAY(bp)) *ulp_dev_id = BNXT_ULP_DEVICE_ID_STINGRAY; else /* Assuming Whitney */ *ulp_dev_id = BNXT_ULP_DEVICE_ID_WH_PLUS; + return 0; } @@ -400,21 +398,18 @@ ulp_eem_tbl_scope_init(struct bnxt *bp) if (bnxt_ulp_cntxt_mem_type_get(bp->ulp_ctx, &mtype)) return -EINVAL; - if (mtype != BNXT_ULP_FLOW_MEM_TYPE_EXT) { BNXT_TF_DBG(INFO, "Table Scope alloc is not required\n"); return 0; } bnxt_init_tbl_scope_parms(bp, ¶ms); - rc = tf_alloc_tbl_scope(&bp->tfp, ¶ms); if (rc) { BNXT_TF_DBG(ERR, "Unable to allocate eem table scope rc = %d\n", rc); return rc; } - rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to set table scope id\n"); @@ -534,8 +529,6 @@ ulp_ctx_init(struct bnxt *bp, if (rc) goto error_deinit; - ulp_tun_tbl_init(ulp_data->tun_tbl); - bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp); return rc; @@ -547,8 +540,7 @@ ulp_ctx_init(struct bnxt *bp, /* The function to initialize ulp dparms with devargs */ static int32_t -ulp_dparms_init(struct bnxt *bp, - struct bnxt_ulp_context *ulp_ctx) +ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) { struct bnxt_ulp_device_params *dparms; uint32_t dev_id; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 96aef28b92..c2e71430ec 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2020 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 836e94bc60..1655b0f29a 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ @@ -79,7 +79,6 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, struct ulp_rte_parser_params *params, enum bnxt_ulp_fdb_type flow_type) { - memset(mapper_cparms, 0, sizeof(*mapper_cparms)); mapper_cparms->flow_type = flow_type; mapper_cparms->app_priority = params->priority; mapper_cparms->dir_attr = params->dir_attr; @@ -95,6 +94,12 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, mapper_cparms->parent_flow = params->parent_flow; mapper_cparms->parent_fid = params->parent_fid; mapper_cparms->fld_bitmap = ¶ms->fld_bitmap; + + /* update the signature fields into the computed field list */ + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID, + params->hdr_sig_id); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, + params->flow_sig_id); } /* Function to create the rte flow. */ @@ -177,7 +182,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, params.fid = fid; params.func_id = func_id; params.priority = attr->priority; - params.port_id = dev->data->port_id; /* Perform the rte flow post process */ ret = bnxt_ulp_rte_parser_post_process(¶ms); if (ret == BNXT_TF_RC_ERROR) diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build index 611d7ab58e..701a510f27 100644 --- a/drivers/net/bnxt/tf_ulp/meson.build +++ b/drivers/net/bnxt/tf_ulp/meson.build @@ -23,6 +23,7 @@ sources += files( 'ulp_fc_mgr.c', 'ulp_tun.c', 'ulp_gen_tbl.c', + 'ulp_rte_handler_tbl.c', 'ulp_template_db_wh_plus_act.c', 'ulp_template_db_wh_plus_class.c', 'ulp_template_db_stingray_act.c', diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index 8a3c5ee8fb..5e9b12e4f5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2020 Broadcom * All rights reserved. */ @@ -366,7 +366,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, goto err1; } - rc = ulp_flow_db_fid_alloc(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT, + rc = ulp_flow_db_fid_alloc(ulp_ctx, mapper_params.flow_type, mapper_params.func_id, &fid); if (rc) { BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n"); @@ -383,7 +383,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, return 0; err3: - ulp_flow_db_fid_free(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT, fid); + ulp_flow_db_fid_free(ulp_ctx, mapper_params.flow_type, fid); err2: bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); err1: @@ -437,7 +437,7 @@ void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) { struct bnxt_ulp_df_rule_info *info; - uint16_t port_id; + uint8_t port_id; if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev)) @@ -501,7 +501,7 @@ int32_t bnxt_ulp_create_df_rules(struct bnxt *bp) { struct bnxt_ulp_df_rule_info *info; - uint16_t port_id; + uint8_t port_id; int rc; if (!BNXT_TRUFLOW_EN(bp) || @@ -575,7 +575,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) struct rte_eth_dev *parent_dev = vfr->parent_dev; struct bnxt *bp = parent_dev->data->dev_private; uint16_t vfr_port_id = vfr_ethdev->data->port_id; - uint16_t port_id; + uint8_t port_id; int rc; if (!bp || !BNXT_TRUFLOW_EN(bp)) diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h index 04cb86bea2..de4d3dfe95 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2019 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index c599e0c7e1..96398d8a01 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ @@ -48,17 +48,21 @@ ulp_flow_db_active_flows_bit_set(struct bnxt_ulp_flow_db *flow_db, uint32_t a_idx = idx / ULP_INDEX_BITMAP_SIZE; if (flag) { - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type == + BNXT_ULP_FDB_TYPE_RID) ULP_INDEX_BITMAP_SET(f_tbl->active_reg_flows[a_idx], idx); - else + if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type == + BNXT_ULP_FDB_TYPE_RID) ULP_INDEX_BITMAP_SET(f_tbl->active_dflt_flows[a_idx], idx); } else { - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type == + BNXT_ULP_FDB_TYPE_RID) ULP_INDEX_BITMAP_RESET(f_tbl->active_reg_flows[a_idx], idx); - else + if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type == + BNXT_ULP_FDB_TYPE_RID) ULP_INDEX_BITMAP_RESET(f_tbl->active_dflt_flows[a_idx], idx); } @@ -85,9 +89,15 @@ ulp_flow_db_active_flows_bit_is_set(struct bnxt_ulp_flow_db *flow_db, if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) return ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx], idx); - else + else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT) return ULP_INDEX_BITMAP_GET(f_tbl->active_dflt_flows[a_idx], idx); + else if (flow_type == BNXT_ULP_FDB_TYPE_RID) + return (ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx], + idx) && + ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx], + idx)); + return 0; } static inline enum tf_dir @@ -213,7 +223,7 @@ ulp_flow_db_alloc_resource(struct bnxt_ulp_flow_db *flow_db) return -ENOMEM; } size = (flow_tbl->num_flows / sizeof(uint64_t)) + 1; - size = ULP_BYTE_ROUND_OFF_8(size); + size = ULP_BYTE_ROUND_OFF_8(size); flow_tbl->active_reg_flows = rte_zmalloc("active reg flows", size, ULP_BUFFER_ALIGN_64_BYTE); if (!flow_tbl->active_reg_flows) { @@ -617,7 +627,7 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -674,7 +684,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -688,7 +698,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist\n"); + BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); return -EINVAL; } @@ -769,7 +779,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -783,7 +793,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist\n"); + BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); return -EINVAL; } @@ -868,9 +878,8 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, enum bnxt_ulp_fdb_type flow_type, uint32_t fid) { - struct bnxt_tun_cache_entry *tun_tbl; - struct bnxt_ulp_flow_tbl *flow_tbl; struct bnxt_ulp_flow_db *flow_db; + struct bnxt_ulp_flow_tbl *flow_tbl; flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); if (!flow_db) { @@ -878,7 +887,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -893,7 +902,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist\n"); + BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); return -EINVAL; } flow_tbl->head_index--; @@ -901,6 +910,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, BNXT_TF_DBG(ERR, "FlowDB: Head Ptr is zero\n"); return -ENOENT; } + flow_tbl->flow_tbl_stack[flow_tbl->head_index] = fid; /* Clear the flows bitmap */ @@ -909,18 +919,12 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) ulp_flow_db_func_id_set(flow_db, fid, 0); - tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt); - if (!tun_tbl) - return -EINVAL; - - ulp_clear_tun_inner_entry(tun_tbl, fid); - /* all good, return success */ return 0; } /* - * Get the flow database entry details + *Get the flow database entry details * * ulp_ctxt [in] Ptr to ulp_context * flow_type [in] - specify default or regular @@ -947,7 +951,7 @@ ulp_flow_db_resource_get(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -1003,10 +1007,14 @@ ulp_flow_db_next_entry_get(struct bnxt_ulp_flow_db *flow_db, uint64_t *active_flows; struct bnxt_ulp_flow_tbl *flowtbl = &flow_db->flow_tbl; - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) { active_flows = flowtbl->active_reg_flows; - else + } else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT) { active_flows = flowtbl->active_dflt_flows; + } else { + BNXT_TF_DBG(ERR, "Invalid flow type %x\n", flow_type); + return -EINVAL; + } do { /* increment the flow id to find the next valid flow id */ @@ -1199,7 +1207,7 @@ ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -1601,7 +1609,7 @@ ulp_flow_db_child_flow_reset(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h index 14369271ff..f7dfd67bed 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2019 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c index dd2b799b30..a762408d77 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c @@ -47,7 +47,7 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data) if (tbl->result_num_entries != 0) { /* add 4 bytes for reference count */ entry->mem_data_size = (tbl->result_num_entries + 1) * - (tbl->result_byte_size + sizeof(uint32_t)); + (tbl->result_num_bytes + sizeof(uint32_t)); /* allocate the big chunk of memory */ entry->mem_data = rte_zmalloc("ulp mapper gen tbl", @@ -60,7 +60,7 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data) } /* Populate the generic table container */ entry->container.num_elem = tbl->result_num_entries; - entry->container.byte_data_size = tbl->result_byte_size; + entry->container.byte_data_size = tbl->result_num_bytes; entry->container.ref_count = (uint32_t *)entry->mem_data; size = sizeof(uint32_t) * (tbl->result_num_entries + 1); @@ -168,7 +168,6 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir) * Set the data in the generic table entry, Data is in Big endian format * * entry [in] - generic table entry - * offset [in] - The offset in bits where the data has to be set * len [in] - The length of the data in bits to be set * data [in] - pointer to the data to be used for setting the value. * data_size [in] - length of the data pointer in bytes. @@ -177,7 +176,7 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir) */ int32_t ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, - uint32_t offset, uint32_t len, uint8_t *data, + uint32_t len, uint8_t *data, uint32_t data_size) { /* validate the null arguments */ @@ -187,32 +186,13 @@ ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, } /* check the size of the buffer for validation */ - if ((offset + len) > ULP_BYTE_2_BITS(entry->byte_data_size) || + if (len > ULP_BYTE_2_BITS(entry->byte_data_size) || data_size < ULP_BITS_2_BYTE(len)) { - BNXT_TF_DBG(ERR, "invalid offset or length %x:%x:%x\n", - offset, len, entry->byte_data_size); + BNXT_TF_DBG(ERR, "invalid offset or length %x:%x\n", + len, entry->byte_data_size); return -EINVAL; } - - /* adjust the data pointer */ - data = data + (data_size - ULP_BITS_2_BYTE(len)); - - /* Push the data into the byte data array */ - if (entry->byte_order == BNXT_ULP_BYTE_ORDER_LE) { - if (ulp_bs_push_lsb(entry->byte_data, offset, len, data) != - len) { - BNXT_TF_DBG(ERR, "write failed offset = %x, len =%x\n", - offset, len); - return -EIO; - } - } else { - if (ulp_bs_push_msb(entry->byte_data, offset, len, data) != - len) { - BNXT_TF_DBG(ERR, "write failed offset = %x, len =%x\n", - offset, len); - return -EIO; - } - } + memcpy(entry->byte_data, data, ULP_BITS_2_BYTE(len)); return 0; } @@ -267,7 +247,7 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, { struct ulp_mapper_gen_tbl_entry entry; int32_t tbl_idx; - uint32_t fid; + uint32_t fid = 0; /* Extract the resource sub type and direction */ tbl_idx = ulp_mapper_gen_tbl_idx_calculate(res->resource_sub_type, @@ -310,7 +290,7 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, fid = tfp_be_to_cpu_32(fid); /* Destroy the flow associated with the shared flow id */ - if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, + if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_RID, fid)) BNXT_TF_DBG(ERR, "Error in deleting shared flow id %x\n", fid); diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h index 701a8d10e5..6236dc3ca2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h @@ -101,7 +101,6 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir); * Set the data in the generic table entry * * entry [in] - generic table entry - * offset [in] - The offset in bits where the data has to be set * len [in] - The length of the data in bits to be set * data [in] - pointer to the data to be used for setting the value. * data_size [in] - length of the data pointer in bytes. @@ -110,7 +109,7 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir); */ int32_t ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry, - uint32_t offset, uint32_t len, uint8_t *data, + uint32_t len, uint8_t *data, uint32_t data_size); /* diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index bf68155410..ced446e189 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -19,6 +19,20 @@ #include "tf_util.h" #include "ulp_template_db_tbl.h" +static const char * +ulp_mapper_tmpl_name_str(enum bnxt_ulp_template_type tmpl_type) +{ + switch (tmpl_type) { + case BNXT_ULP_TEMPLATE_TYPE_CLASS: + return "class"; + case BNXT_ULP_TEMPLATE_TYPE_ACTION: + return "action"; + default: + return "invalid template type"; + } +} + + static struct bnxt_ulp_glb_resource_info * ulp_mapper_glb_resource_info_list_get(uint32_t *num_entries) { @@ -42,7 +56,7 @@ ulp_mapper_glb_resource_read(struct bnxt_ulp_mapper_data *mapper_data, uint64_t *regval) { if (!mapper_data || !regval || - dir >= TF_DIR_MAX || idx >= BNXT_ULP_GLB_REGFILE_INDEX_LAST) + dir >= TF_DIR_MAX || idx >= BNXT_ULP_GLB_RF_IDX_LAST) return -EINVAL; *regval = mapper_data->glb_res_tbl[dir][idx].resource_hndl; @@ -65,7 +79,7 @@ ulp_mapper_glb_resource_write(struct bnxt_ulp_mapper_data *data, /* validate the arguments */ if (!data || res->direction >= TF_DIR_MAX || - res->glb_regfile_index >= BNXT_ULP_GLB_REGFILE_INDEX_LAST) + res->glb_regfile_index >= BNXT_ULP_GLB_RF_IDX_LAST) return -EINVAL; /* write to the mapper data */ @@ -191,10 +205,27 @@ ulp_mapper_glb_template_table_get(uint32_t *num_entries) return ulp_glb_template_tbl; } -static uint8_t * -ulp_mapper_glb_field_tbl_get(uint32_t idx) +static int32_t +ulp_mapper_glb_field_tbl_get(struct bnxt_ulp_mapper_parms *parms, + uint32_t operand, + uint8_t *val) { - return &ulp_glb_field_tbl[idx]; + uint32_t t_idx; + + t_idx = parms->class_tid << (BNXT_ULP_HDR_SIG_ID_SHIFT + + BNXT_ULP_GLB_FIELD_TBL_SHIFT); + t_idx += ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_HDR_SIG_ID) << + BNXT_ULP_GLB_FIELD_TBL_SHIFT; + t_idx += operand; + + if (t_idx >= BNXT_ULP_GLB_FIELD_TBL_SIZE) { + BNXT_TF_DBG(ERR, "Invalid hdr field index %x:%x:%x\n", + parms->class_tid, t_idx, operand); + *val = 0; + return -EINVAL; /* error */ + } + *val = ulp_glb_field_tbl[t_idx]; + return 0; } /* @@ -286,7 +317,7 @@ ulp_mapper_tbl_list_get(struct bnxt_ulp_mapper_parms *mparms, * * Returns array of Key fields, or NULL on error. */ -static struct bnxt_ulp_mapper_key_field_info * +static struct bnxt_ulp_mapper_key_info * ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_parms *mparms, struct bnxt_ulp_mapper_tbl_info *tbl, uint32_t *num_flds) @@ -295,7 +326,7 @@ ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_parms *mparms, const struct bnxt_ulp_template_device_tbls *dev_tbls; dev_tbls = &mparms->device_params->dev_tbls[mparms->tmpl_type]; - if (!dev_tbls->key_field_list) { + if (!dev_tbls->key_info_list) { *num_flds = 0; return NULL; } @@ -303,7 +334,7 @@ ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_parms *mparms, idx = tbl->key_start_idx; *num_flds = tbl->key_num_fields; - return &dev_tbls->key_field_list[idx]; + return &dev_tbls->key_info_list[idx]; } /* @@ -319,7 +350,7 @@ ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_parms *mparms, * * Returns array of data fields, or NULL on error. */ -static struct bnxt_ulp_mapper_result_field_info * +static struct bnxt_ulp_mapper_field_info * ulp_mapper_result_fields_get(struct bnxt_ulp_mapper_parms *mparms, struct bnxt_ulp_mapper_tbl_info *tbl, uint32_t *num_flds, @@ -510,6 +541,41 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp, return 0; } +/* + * Process the flow database opcode alloc action. + * returns 0 on success + */ +static int32_t +ulp_mapper_fdb_opc_alloc_rid(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl) +{ + uint32_t rid = 0; + uint64_t val64; + int32_t rc = 0; + + /* allocate a new fid */ + rc = ulp_flow_db_fid_alloc(parms->ulp_ctx, + BNXT_ULP_FDB_TYPE_RID, + 0, &rid); + if (rc) { + BNXT_TF_DBG(ERR, + "Unable to allocate flow table entry\n"); + return -EINVAL; + } + /* Store the allocated fid in regfile*/ + val64 = rid; + rc = ulp_regfile_write(parms->regfile, tbl->fdb_operand, + tfp_cpu_to_be_64(val64)); + if (rc) { + BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", + tbl->fdb_operand); + ulp_flow_db_fid_free(parms->ulp_ctx, + BNXT_ULP_FDB_TYPE_RID, rid); + return -EINVAL; + } + return 0; +} + /* * Process the flow database opcode action. * returns 0 on success. @@ -519,68 +585,40 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl, struct ulp_flow_db_res_params *fid_parms) { - uint32_t push_fid, fid = 0; + uint32_t push_fid; uint64_t val64; + enum bnxt_ulp_fdb_type flow_type; int32_t rc = 0; switch (tbl->fdb_opcode) { case BNXT_ULP_FDB_OPC_PUSH: push_fid = parms->fid; + flow_type = parms->flow_type; break; case BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE: - /* allocate a new fid */ - rc = ulp_flow_db_fid_alloc(parms->ulp_ctx, - parms->flow_type, - tbl->resource_func, &fid); - if (rc) { - BNXT_TF_DBG(ERR, - "Unable to allocate flow table entry\n"); - return rc; - } - /* Store the allocated fid in regfile*/ - val64 = fid; - rc = ulp_regfile_write(parms->regfile, tbl->flow_db_operand, - tfp_cpu_to_be_64(val64)); - if (!rc) { - BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", - tbl->flow_db_operand); - rc = -EINVAL; - goto error; - } - /* Use the allocated fid to update the flow resource */ - push_fid = fid; - break; case BNXT_ULP_FDB_OPC_PUSH_REGFILE: /* get the fid from the regfile */ - rc = ulp_regfile_read(parms->regfile, tbl->flow_db_operand, + rc = ulp_regfile_read(parms->regfile, tbl->fdb_operand, &val64); if (!rc) { BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", - tbl->flow_db_operand); + tbl->fdb_operand); return -EINVAL; } /* Use the extracted fid to update the flow resource */ - push_fid = tfp_be_to_cpu_64((uint32_t)val64); + push_fid = (uint32_t)tfp_be_to_cpu_64(val64); + flow_type = BNXT_ULP_FDB_TYPE_RID; break; default: return rc; /* Nothing to be done */ } /* Add the resource to the flow database */ - rc = ulp_flow_db_resource_add(parms->ulp_ctx, parms->flow_type, + rc = ulp_flow_db_resource_add(parms->ulp_ctx, flow_type, push_fid, fid_parms); - if (rc) { + if (rc) BNXT_TF_DBG(ERR, "Failed to add res to flow %x rc = %d\n", push_fid, rc); - goto error; - } - return rc; - -error: - /* free the allocated fid */ - if (fid) - ulp_flow_db_fid_free(parms->ulp_ctx, - BNXT_ULP_FDB_TYPE_REGULAR, fid); return rc; } @@ -651,6 +689,7 @@ ulp_mapper_tbl_ident_scan_ext(struct bnxt_ulp_mapper_parms *parms, byte_data_size); return -EINVAL; } + val64 = 0; if (byte_order == BNXT_ULP_BYTE_ORDER_LE) ulp_bs_pull_lsb(byte_data, (uint8_t *)&val64, sizeof(val64), @@ -662,9 +701,8 @@ ulp_mapper_tbl_ident_scan_ext(struct bnxt_ulp_mapper_parms *parms, idents[i].ident_bit_size); /* Write it to the regfile, val64 is already in big-endian*/ - if (!ulp_regfile_write(parms->regfile, - idents[i].regfile_idx, - val64)) { + if (ulp_regfile_write(parms->regfile, + idents[i].regfile_idx, val64)) { BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", idents[i].regfile_idx); return -EINVAL; @@ -712,7 +750,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, } id = (uint64_t)tfp_cpu_to_be_64(iparms.id); - if (!ulp_regfile_write(parms->regfile, idx, id)) { + if (ulp_regfile_write(parms->regfile, idx, id)) { BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", idx); rc = -EINVAL; /* Need to free the identifier, so goto error */ @@ -805,7 +843,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, /* Write it to the regfile */ id = (uint64_t)tfp_cpu_to_be_64(sparms.search_id); - if (!ulp_regfile_write(parms->regfile, ident->regfile_idx, id)) { + if (ulp_regfile_write(parms->regfile, ident->regfile_idx, id)) { BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", idx); rc = -EINVAL; /* Need to free the identifier, so goto error */ @@ -842,107 +880,38 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, } static int32_t -ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, - enum tf_dir dir, - struct bnxt_ulp_mapper_result_field_info *fld, - struct ulp_blob *blob, - const char *name) +ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, + enum tf_dir dir, + struct bnxt_ulp_mapper_field_info *fld, + struct ulp_blob *blob, + uint8_t is_key, + const char *name) { - uint16_t idx, size_idx; - uint8_t *val = NULL; - uint16_t write_idx = blob->write_idx; - uint64_t regval; uint32_t val_size = 0, field_size = 0; - uint64_t act_bit; + uint64_t hdr_bit, act_bit, regval; + uint16_t write_idx = blob->write_idx; + uint16_t idx, size_idx, bitlen; + uint8_t *val = NULL; uint8_t act_val[16]; - uint64_t hdr_bit; - - switch (fld->result_opcode) { - case BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT: - val = fld->result_operand; - if (!ulp_blob_push(blob, val, fld->field_bit_size)) { - BNXT_TF_DBG(ERR, "%s failed to add field\n", name); - return -EINVAL; - } - break; - case BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP: - if (!ulp_operand_read(fld->result_operand, - (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); + uint8_t bit; - if (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s act_prop[%d] oob\n", name, idx); - return -EINVAL; - } - val = &parms->act_prop->act_details[idx]; - field_size = ulp_mapper_act_prop_size_get(idx); - if (fld->field_bit_size < ULP_BYTE_2_BITS(field_size)) { - field_size = field_size - - ((fld->field_bit_size + 7) / 8); - val += field_size; - } - if (!ulp_blob_push(blob, val, fld->field_bit_size)) { - BNXT_TF_DBG(ERR, "%s push field failed\n", name); - return -EINVAL; - } - break; - case BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT: - if (!ulp_operand_read(fld->result_operand, - (uint8_t *)&act_bit, sizeof(uint64_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - act_bit = tfp_be_to_cpu_64(act_bit); - memset(act_val, 0, sizeof(act_val)); - if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) - act_val[0] = 1; - if (fld->field_bit_size > ULP_BYTE_2_BITS(sizeof(act_val))) { - BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); - return -EINVAL; - } - if (!ulp_blob_push(blob, act_val, fld->field_bit_size)) { - BNXT_TF_DBG(ERR, "%s push field failed\n", name); + bitlen = fld->field_bit_size; + switch (fld->field_opcode) { + case BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT: + val = fld->field_operand; + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } - val = act_val; break; - case BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ: - if (!ulp_operand_read(fld->result_operand, - (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - - if (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s act_prop[%d] oob\n", name, idx); - return -EINVAL; - } - val = &parms->act_prop->act_details[idx]; - - /* get the size index next */ - if (!ulp_operand_read(&fld->result_operand[sizeof(uint16_t)], - (uint8_t *)&size_idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - size_idx = tfp_be_to_cpu_16(size_idx); - - if (size_idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { - BNXT_TF_DBG(ERR, "act_prop[%d] oob\n", size_idx); + case BNXT_ULP_FIELD_OPC_SET_TO_ZERO: + if (ulp_blob_pad_push(blob, bitlen) < 0) { + BNXT_TF_DBG(ERR, "%s too large for blob\n", name); return -EINVAL; } - memcpy(&val_size, &parms->act_prop->act_details[size_idx], - sizeof(uint32_t)); - val_size = tfp_be_to_cpu_32(val_size); - val_size = ULP_BYTE_2_BITS(val_size); - ulp_blob_push_encap(blob, val, val_size); break; - case BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE: - if (!ulp_operand_read(fld->result_operand, + case BNXT_ULP_FIELD_OPC_SET_TO_REGFILE: + if (!ulp_operand_read(fld->field_operand, (uint8_t *)&idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; @@ -956,58 +925,52 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } - val = ulp_blob_push_64(blob, ®val, fld->field_bit_size); + val = ulp_blob_push_64(blob, ®val, bitlen); if (!val) { - BNXT_TF_DBG(ERR, "%s push field failed\n", name); + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } break; - case BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE: - if (!ulp_operand_read(fld->result_operand, + case BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE: + if (!ulp_operand_read(fld->field_operand, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name); + BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); if (ulp_mapper_glb_resource_read(parms->mapper_data, dir, idx, ®val)) { - BNXT_TF_DBG(ERR, "%s regfile[%d] read failed.\n", + BNXT_TF_DBG(ERR, "%s global regfile[%d] read failed.\n", name, idx); return -EINVAL; } - val = ulp_blob_push_64(blob, ®val, fld->field_bit_size); + val = ulp_blob_push_64(blob, ®val, bitlen); if (!val) { - BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name); + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } break; - case BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD: - if (!ulp_operand_read(fld->result_operand, + case BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD: + if (!ulp_operand_read(fld->field_operand, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name); + BNXT_TF_DBG(ERR, "%s operand read failed.\n", + name); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); if (idx < BNXT_ULP_CF_IDX_LAST) val = ulp_blob_push_32(blob, &parms->comp_fld[idx], - fld->field_bit_size); + bitlen); if (!val) { - BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name); + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } break; - case BNXT_ULP_MAPPER_OPC_SET_TO_ZERO: - if (ulp_blob_pad_push(blob, fld->field_bit_size) < 0) { - BNXT_TF_DBG(ERR, "%s too large for blob\n", name); - return -EINVAL; - } - - break; - case BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST: - if (!ulp_operand_read(fld->result_operand, + case BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST: + if (!ulp_operand_read(fld->field_operand, (uint8_t *)&act_bit, sizeof(uint64_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; @@ -1015,10 +978,11 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, act_bit = tfp_be_to_cpu_64(act_bit); if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) { /* Action bit is set so consider operand_true */ - if (!ulp_operand_read(fld->result_operand_true, + if (!ulp_operand_read(fld->field_operand_true, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", + BNXT_TF_DBG(ERR, + "%s true operand read failed\n", name); return -EINVAL; } @@ -1030,28 +994,27 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, } val = &parms->act_prop->act_details[idx]; field_size = ulp_mapper_act_prop_size_get(idx); - if (fld->field_bit_size < ULP_BYTE_2_BITS(field_size)) { - field_size = field_size - - ((fld->field_bit_size + 7) / 8); + if (bitlen < ULP_BYTE_2_BITS(field_size)) { + field_size = field_size - ((bitlen + 7) / 8); val += field_size; } - if (!ulp_blob_push(blob, val, fld->field_bit_size)) { - BNXT_TF_DBG(ERR, "%s push field failed\n", + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } } else { /* action bit is not set, use the operand false */ - val = fld->result_operand_false; - if (!ulp_blob_push(blob, val, fld->field_bit_size)) { - BNXT_TF_DBG(ERR, "%s failed to add field\n", + val = fld->field_operand_false; + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } } break; - case BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST: - if (!ulp_operand_read(fld->result_operand, + case BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST: + if (!ulp_operand_read(fld->field_operand, (uint8_t *)&act_bit, sizeof(uint64_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; @@ -1059,22 +1022,22 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, act_bit = tfp_be_to_cpu_64(act_bit); if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) { /* Action bit is set so consider operand_true */ - val = fld->result_operand_true; + val = fld->field_operand_true; } else { /* action bit is not set, use the operand false */ - val = fld->result_operand_false; + val = fld->field_operand_false; } - if (!ulp_blob_push(blob, val, fld->field_bit_size)) { - BNXT_TF_DBG(ERR, "%s failed to add field\n", + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } break; - case BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF: - if (!ulp_operand_read(fld->result_operand, + case BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF: + if (!ulp_operand_read(fld->field_operand, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name); + BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); @@ -1084,9 +1047,9 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, } /* check if the computed field is set */ if (ULP_COMP_FLD_IDX_RD(parms, idx)) - val = fld->result_operand_true; + val = fld->field_operand_true; else - val = fld->result_operand_false; + val = fld->field_operand_false; /* read the appropriate computed field */ if (!ulp_operand_read(val, (uint8_t *)&idx, sizeof(uint16_t))) { @@ -1098,15 +1061,14 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, BNXT_TF_DBG(ERR, "%s invalid index %u\n", name, idx); return -EINVAL; } - val = ulp_blob_push_32(blob, &parms->comp_fld[idx], - fld->field_bit_size); + val = ulp_blob_push_32(blob, &parms->comp_fld[idx], bitlen); if (!val) { - BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name); + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } break; - case BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST: - if (!ulp_operand_read(fld->result_operand, + case BNXT_ULP_FIELD_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST: + if (!ulp_operand_read(fld->field_operand, (uint8_t *)&hdr_bit, sizeof(uint64_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; @@ -1114,20 +1076,128 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, hdr_bit = tfp_be_to_cpu_64(hdr_bit); if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) { /* Header bit is set so consider operand_true */ - val = fld->result_operand_true; + val = fld->field_operand_true; } else { /* Header bit is not set, use the operand false */ - val = fld->result_operand_false; + val = fld->field_operand_false; } - if (!ulp_blob_push(blob, val, fld->field_bit_size)) { - BNXT_TF_DBG(ERR, "%s failed to add field\n", + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } break; + case BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP: + if (!ulp_operand_read(fld->field_operand, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + idx = tfp_be_to_cpu_16(idx); + + if (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { + BNXT_TF_DBG(ERR, "%s act_prop[%d] oob\n", name, idx); + return -EINVAL; + } + val = &parms->act_prop->act_details[idx]; + field_size = ulp_mapper_act_prop_size_get(idx); + if (bitlen < ULP_BYTE_2_BITS(field_size)) { + field_size = field_size - ((bitlen + 7) / 8); + val += field_size; + } + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + break; + case BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT: + if (!ulp_operand_read(fld->field_operand, + (uint8_t *)&act_bit, sizeof(uint64_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + act_bit = tfp_be_to_cpu_64(act_bit); + memset(act_val, 0, sizeof(act_val)); + if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) + act_val[0] = 1; + if (bitlen > ULP_BYTE_2_BITS(sizeof(act_val))) { + BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); + return -EINVAL; + } + if (!ulp_blob_push(blob, act_val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + val = act_val; + break; + case BNXT_ULP_FIELD_OPC_SET_TO_ENCAP_ACT_PROP_SZ: + if (!ulp_operand_read(fld->field_operand, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + idx = tfp_be_to_cpu_16(idx); + + if (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { + BNXT_TF_DBG(ERR, "%s act_prop[%d] oob\n", name, idx); + return -EINVAL; + } + val = &parms->act_prop->act_details[idx]; + + /* get the size index next */ + if (!ulp_operand_read(&fld->field_operand[sizeof(uint16_t)], + (uint8_t *)&size_idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + size_idx = tfp_be_to_cpu_16(size_idx); + + if (size_idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { + BNXT_TF_DBG(ERR, "act_prop[%d] oob\n", size_idx); + return -EINVAL; + } + memcpy(&val_size, &parms->act_prop->act_details[size_idx], + sizeof(uint32_t)); + val_size = tfp_be_to_cpu_32(val_size); + val_size = ULP_BYTE_2_BITS(val_size); + ulp_blob_push_encap(blob, val, val_size); + break; + case BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD: + if (!ulp_operand_read(fld->field_operand, (uint8_t *)&idx, + sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); + return -EINVAL; + } + idx = tfp_be_to_cpu_16(idx); + /* get the index from the global field list */ + if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) { + BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", + idx); + return -EINVAL; + } + if (is_key) + val = parms->hdr_field[bit].spec; + else + val = parms->hdr_field[bit].mask; + + /* + * Need to account for how much data was pushed to the header + * field vs how much is to be inserted in the key/mask. + */ + field_size = parms->hdr_field[bit].size; + if (bitlen < ULP_BYTE_2_BITS(field_size)) { + field_size = field_size - ((bitlen + 7) / 8); + val += field_size; + } + + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + break; default: - BNXT_TF_DBG(ERR, "invalid result mapper opcode 0x%x at %d\n", - fld->result_opcode, write_idx); + BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n", + name, fld->field_opcode, write_idx); return -EINVAL; } return 0; @@ -1143,7 +1213,7 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms, struct ulp_blob *data, const char *name) { - struct bnxt_ulp_mapper_result_field_info *dflds; + struct bnxt_ulp_mapper_field_info *dflds; uint32_t i, num_flds = 0, encap_flds = 0; int32_t rc = 0; @@ -1169,8 +1239,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms, ulp_blob_encap_swap_idx_set(data); /* Process the result fields */ - rc = ulp_mapper_result_field_process(parms, tbl->direction, - &dflds[i], data, name); + rc = ulp_mapper_field_process(parms, tbl->direction, + &dflds[i], data, 0, name); if (rc) { BNXT_TF_DBG(ERR, "data field failed\n"); return rc; @@ -1184,139 +1254,6 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms, return rc; } -/* Function to alloc action record and set the table. */ -static int32_t -ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms, - enum tf_dir dir, - struct bnxt_ulp_mapper_key_field_info *f, - struct ulp_blob *blob, - uint8_t is_key, - const char *name) -{ - uint64_t val64; - uint16_t idx, bitlen; - uint32_t opcode; - uint8_t *operand; - struct ulp_regfile *regfile = parms->regfile; - uint8_t *val = NULL; - struct bnxt_ulp_mapper_key_field_info *fld = f; - uint32_t field_size; - - if (is_key) { - operand = fld->spec_operand; - opcode = fld->spec_opcode; - } else { - operand = fld->mask_operand; - opcode = fld->mask_opcode; - } - - bitlen = fld->field_bit_size; - - switch (opcode) { - case BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT: - val = operand; - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name); - return -EINVAL; - } - break; - case BNXT_ULP_MAPPER_OPC_SET_TO_ZERO: - if (ulp_blob_pad_push(blob, bitlen) < 0) { - BNXT_TF_DBG(ERR, "%s pad too large for blob\n", name); - return -EINVAL; - } - - break; - case BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD: - if (!ulp_operand_read(operand, (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - if (is_key) - val = parms->hdr_field[idx].spec; - else - val = parms->hdr_field[idx].mask; - - /* - * Need to account for how much data was pushed to the header - * field vs how much is to be inserted in the key/mask. - */ - field_size = parms->hdr_field[idx].size; - if (bitlen < ULP_BYTE_2_BITS(field_size)) { - field_size = field_size - ((bitlen + 7) / 8); - val += field_size; - } - - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name); - return -EINVAL; - } - break; - case BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD: - if (!ulp_operand_read(operand, (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - if (idx < BNXT_ULP_CF_IDX_LAST) - val = ulp_blob_push_32(blob, &parms->comp_fld[idx], - bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name); - return -EINVAL; - } - break; - case BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE: - if (!ulp_operand_read(operand, (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - - if (!ulp_regfile_read(regfile, idx, &val64)) { - BNXT_TF_DBG(ERR, "%s regfile[%d] read failed.\n", - name, idx); - return -EINVAL; - } - - val = ulp_blob_push_64(blob, &val64, bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name); - return -EINVAL; - } - break; - case BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE: - if (!ulp_operand_read(operand, (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - if (ulp_mapper_glb_resource_read(parms->mapper_data, - dir, - idx, &val64)) { - BNXT_TF_DBG(ERR, "%s regfile[%d] read failed.\n", - name, idx); - return -EINVAL; - } - val = ulp_blob_push_64(blob, &val64, bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name); - return -EINVAL; - } - break; - default: - BNXT_TF_DBG(ERR, "invalid keymask mapper opcode 0x%x\n", - opcode); - return -EINVAL; - } - return 0; -} - static int32_t ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl, @@ -1380,7 +1317,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms, mark = tfp_be_to_cpu_32(mark); if (!ulp_regfile_read(parms->regfile, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, &val64)) { BNXT_TF_DBG(ERR, "read action ptr main failed\n"); return -EINVAL; @@ -1423,7 +1360,7 @@ ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms, /* Get the main action pointer */ if (!ulp_regfile_read(parms->regfile, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, &val64)) { BNXT_TF_DBG(ERR, "read action ptr main failed\n"); return -EINVAL; @@ -1521,8 +1458,8 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, sparms.idx = idx; /* Already verified the key/mask lengths */ sparms.key = ulp_blob_data_get(key, &tmplen); - sparms.key_sz_in_bits = tmplen; sparms.mask = ulp_blob_data_get(mask, &tmplen); + sparms.key_sz_in_bits = tbl->key_bit_size; sparms.result = ulp_blob_data_get(data, &tmplen); if (tbl->result_bit_size != tmplen) { @@ -1575,7 +1512,7 @@ static int32_t ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { - struct bnxt_ulp_mapper_key_field_info *kflds; + struct bnxt_ulp_mapper_key_info *kflds; struct ulp_blob key, mask, data, update_data; uint32_t i, num_kflds; struct tf *tfp; @@ -1632,20 +1569,22 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, */ for (i = 0; i < num_kflds; i++) { /* Setup the key */ - rc = ulp_mapper_keymask_field_process(parms, tbl->direction, - &kflds[i], - &key, 1, "TCAM Key"); + rc = ulp_mapper_field_process(parms, tbl->direction, + &kflds[i].field_info_spec, + &key, 1, "TCAM Key"); if (rc) { - BNXT_TF_DBG(ERR, "Key field set failed.\n"); + BNXT_TF_DBG(ERR, "Key field set failed %s\n", + kflds[i].field_info_spec.description); return rc; } /* Setup the mask */ - rc = ulp_mapper_keymask_field_process(parms, tbl->direction, - &kflds[i], - &mask, 0, "TCAM Mask"); + rc = ulp_mapper_field_process(parms, tbl->direction, + &kflds[i].field_info_mask, + &mask, 0, "TCAM Mask"); if (rc) { - BNXT_TF_DBG(ERR, "Mask field set failed.\n"); + BNXT_TF_DBG(ERR, "Mask field set failed %s\n", + kflds[i].field_info_mask.description); return rc; } } @@ -1728,8 +1667,8 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, } /* Write the tcam index into the regfile*/ - if (!ulp_regfile_write(parms->regfile, tbl->tbl_operand, - (uint64_t)tfp_cpu_to_be_64(idx))) { + if (ulp_regfile_write(parms->regfile, tbl->tbl_operand, + (uint64_t)tfp_cpu_to_be_64(idx))) { BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", tbl->tbl_operand); rc = -EINVAL; @@ -1786,7 +1725,7 @@ static int32_t ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { - struct bnxt_ulp_mapper_key_field_info *kflds; + struct bnxt_ulp_mapper_key_info *kflds; struct ulp_blob key, data; uint32_t i, num_kflds; uint16_t tmplen; @@ -1822,9 +1761,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* create the key */ for (i = 0; i < num_kflds; i++) { /* Setup the key */ - rc = ulp_mapper_keymask_field_process(parms, tbl->direction, - &kflds[i], - &key, 1, "EM Key"); + rc = ulp_mapper_field_process(parms, tbl->direction, + &kflds[i].field_info_spec, + &key, 1, "EM Key"); if (rc) { BNXT_TF_DBG(ERR, "Key field set failed.\n"); return rc; @@ -2150,7 +2089,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = ulp_regfile_write(parms->regfile, tbl->tbl_operand, tfp_cpu_to_be_64(regval)); - if (!rc) { + if (rc) { BNXT_TF_DBG(ERR, "Failed to write regfile[%d] rc=%d\n", tbl->tbl_operand, rc); goto error; @@ -2326,7 +2265,7 @@ static int32_t ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { - struct bnxt_ulp_mapper_key_field_info *kflds; + struct bnxt_ulp_mapper_key_info *kflds; struct ulp_flow_db_res_params fid_parms; struct ulp_mapper_gen_tbl_entry gen_tbl_ent, *g; uint16_t tmplen; @@ -2351,9 +2290,9 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, } for (i = 0; i < num_kflds; i++) { /* Setup the key */ - rc = ulp_mapper_keymask_field_process(parms, tbl->direction, - &kflds[i], - &key, 1, "Gen Tbl Key"); + rc = ulp_mapper_field_process(parms, tbl->direction, + &kflds[i].field_info_spec, + &key, 1, "Gen Tbl Key"); if (rc) { BNXT_TF_DBG(ERR, "Failed to create key for Gen tbl rc=%d\n", @@ -2416,7 +2355,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* Initialize the blob data */ if (!ulp_blob_init(&data, tbl->result_bit_size, - BNXT_ULP_BYTE_ORDER_BE)) { + gen_tbl_ent.byte_order)) { BNXT_TF_DBG(ERR, "Failed initial index table blob\n"); return -EINVAL; } @@ -2429,7 +2368,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } byte_data = ulp_blob_data_get(&data, &tmplen); - rc = ulp_mapper_gen_tbl_entry_data_set(&gen_tbl_ent, 0, + rc = ulp_mapper_gen_tbl_entry_data_set(&gen_tbl_ent, tmplen, byte_data, ULP_BITS_2_BYTE(tmplen)); if (rc) { @@ -2448,11 +2387,11 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* Set the generic entry hit */ rc = ulp_regfile_write(parms->regfile, - BNXT_ULP_REGFILE_INDEX_GENERIC_TBL_HIT, + BNXT_ULP_RF_IDX_GENERIC_TBL_HIT, tfp_cpu_to_be_64(gen_tbl_hit)); - if (!rc) { + if (rc) { BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", - BNXT_ULP_REGFILE_INDEX_GENERIC_TBL_HIT); + BNXT_ULP_RF_IDX_GENERIC_TBL_HIT); return -EIO; } @@ -2557,8 +2496,7 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, int32_t *res) { int32_t rc = 0; - uint8_t *bit; - uint32_t idx; + uint8_t bit; uint64_t regval; switch (opc) { @@ -2621,26 +2559,22 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, } break; case BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET: - idx = (parms->class_tid << BNXT_ULP_GLB_FIELD_TBL_SHIFT) | - operand; - bit = ulp_mapper_glb_field_tbl_get(idx); - if (!bit) { + rc = ulp_mapper_glb_field_tbl_get(parms, operand, &bit); + if (rc) { BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", - idx); + operand); return -EINVAL; } - *res = ULP_BITMAP_ISSET(parms->fld_bitmap->bits, (1 << *bit)); + *res = ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit); break; case BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET: - idx = (parms->class_tid << BNXT_ULP_GLB_FIELD_TBL_SHIFT) | - operand; - bit = ulp_mapper_glb_field_tbl_get(idx); - if (!bit) { + rc = ulp_mapper_glb_field_tbl_get(parms, operand, &bit); + if (rc) { BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", - idx); + operand); return -EINVAL; } - *res = !ULP_BITMAP_ISSET(parms->fld_bitmap->bits, (1 << *bit)); + *res = !ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit); break; case BNXT_ULP_COND_OPC_REGFILE_IS_SET: if (!ulp_regfile_read(parms->regfile, operand, ®val)) { @@ -2728,6 +2662,70 @@ ulp_mapper_cond_opc_list_process(struct bnxt_ulp_mapper_parms *parms, return rc; } +/* + * Processes conflict resolution and returns both a status and result. + * The status must be checked prior to verifying the result. + * + * returns 0 for success, negative on failure + * returns res = 1 for true, res = 0 for false. + */ +static int32_t +ulp_mapper_conflict_resolution_process(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl, + int32_t *res) +{ + int32_t rc = 0; + uint64_t regval; + uint64_t comp_sig_id; + + *res = 0; + switch (tbl->accept_opcode) { + case BNXT_ULP_ACCEPT_OPC_ALWAYS: + *res = 1; + break; + case BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH: + /* perform the signature validation*/ + if (tbl->resource_func == + BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE) { + /* Perform the check that generic table is hit or not */ + if (!ulp_regfile_read(parms->regfile, + BNXT_ULP_RF_IDX_GENERIC_TBL_HIT, + ®val)) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", + BNXT_ULP_RF_IDX_GENERIC_TBL_HIT); + return -EINVAL; + } + if (!regval) { + /* not a hit so no need to check flow sign*/ + *res = 1; + return rc; + } + } + /* compare the new flow signature against stored one */ + if (!ulp_regfile_read(parms->regfile, + BNXT_ULP_RF_IDX_FLOW_SIG_ID, + ®val)) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", + BNXT_ULP_RF_IDX_FLOW_SIG_ID); + return -EINVAL; + } + comp_sig_id = ULP_COMP_FLD_IDX_RD(parms, + BNXT_ULP_CF_IDX_FLOW_SIG_ID); + regval = tfp_be_to_cpu_64(regval); + if (comp_sig_id == regval) + *res = 1; + else + BNXT_TF_DBG(ERR, "failed signature match %x:%x\n", + (uint32_t)comp_sig_id, (uint32_t)regval); + break; + default: + BNXT_TF_DBG(ERR, "Invalid accept opcode %d\n", + tbl->accept_opcode); + return -EINVAL; + } + return rc; +} + static int32_t ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) { @@ -2757,9 +2755,8 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) /* Reject the template if True */ if (cond_rc) { BNXT_TF_DBG(ERR, "%s Template %d rejected.\n", - (parms->tmpl_type == - BNXT_ULP_TEMPLATE_TYPE_CLASS) ? - "class" : "action", tid); + ulp_mapper_tmpl_name_str(parms->tmpl_type), + tid); return -EINVAL; } } @@ -2767,8 +2764,8 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) tbls = ulp_mapper_tbl_list_get(parms, tid, &num_tbls); if (!tbls || !num_tbls) { BNXT_TF_DBG(ERR, "No %s tables for %d:%d\n", - (parms->tmpl_type == BNXT_ULP_TEMPLATE_TYPE_CLASS) ? - "class" : "action", parms->dev_id, tid); + ulp_mapper_tmpl_name_str(parms->tmpl_type), + parms->dev_id, tid); return -EINVAL; } @@ -2793,6 +2790,15 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) if (!cond_rc) continue; + /* process the fdb opcode for alloc push */ + if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE) { + rc = ulp_mapper_fdb_opc_alloc_rid(parms, tbl); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to do fdb alloc\n"); + return rc; + } + } + switch (tbl->resource_func) { case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: rc = ulp_mapper_tcam_tbl_process(parms, tbl); @@ -2825,13 +2831,22 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) tbl->resource_func); goto error; } + + /* perform the post table process */ + rc = ulp_mapper_conflict_resolution_process(parms, tbl, + &cond_rc); + if (rc || !cond_rc) { + BNXT_TF_DBG(ERR, "Failed due to conflict resolution\n"); + rc = -EINVAL; + goto error; + } } return rc; error: BNXT_TF_DBG(ERR, "%s tables failed creation for %d:%d\n", - (parms->tmpl_type = BNXT_ULP_TEMPLATE_TYPE_CLASS) ? - "class" : "action", parms->dev_id, tid); + ulp_mapper_tmpl_name_str(parms->tmpl_type), + parms->dev_id, tid); return rc; } @@ -3054,7 +3069,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, { struct bnxt_ulp_mapper_parms parms; struct ulp_regfile regfile; - int32_t rc, trc; + int32_t rc = 0, trc; if (!ulp_ctx || !cparms) return -EINVAL; @@ -3109,14 +3124,6 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } - rc = ulp_regfile_write(parms.regfile, - BNXT_ULP_REGFILE_INDEX_CLASS_TID, - tfp_cpu_to_be_64((uint64_t)parms.class_tid)); - if (!rc) { - BNXT_TF_DBG(ERR, "Unable to write template ID to regfile\n"); - return -EINVAL; - } - /* Process the action template list from the selected action table*/ if (parms.act_tid) { parms.tmpl_type = BNXT_ULP_TEMPLATE_TYPE_ACTION; @@ -3152,7 +3159,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, flow_error: /* Free all resources that were allocated during flow creation */ - trc = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, + trc = ulp_mapper_flow_destroy(ulp_ctx, parms.flow_type, parms.fid); if (trc) BNXT_TF_DBG(ERR, "Failed to free all resources rc=%d\n", trc); diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c index 06ad5a94e2..8b8dccf9f1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h index d9d82d4644..9696730cc2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2019 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c index e23867f8b9..6e2506cfa3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ @@ -77,6 +77,8 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params, BNXT_TF_DBG(DEBUG, "Found matching pattern template %d\n", class_match->class_tid); *class_id = class_match->class_tid; + params->hdr_sig_id = class_match->hdr_sig_id; + params->flow_sig_id = class_match->flow_sig_id; return BNXT_TF_RC_SUCCESS; error: diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h index dc2487889c..a582188252 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.h +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index a11e6786c0..94075784d8 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ @@ -185,15 +185,13 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt, port_data = &port_db->phy_port_list[func->phy_port_id]; if (!port_data->port_valid) { port_data->port_svif = - bnxt_get_svif(port_id, false, - BNXT_ULP_INTF_TYPE_INVALID); + bnxt_get_svif(port_id, false, BNXT_ULP_INTF_TYPE_INVALID); port_data->port_spif = bnxt_get_phy_port_id(port_id); port_data->port_parif = bnxt_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID); port_data->port_vport = bnxt_get_vport(port_id); port_data->port_valid = true; } - return 0; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h index ae2b71df25..7b85987a0c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2019 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c new file mode 100644 index 0000000000..8e466255d9 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c @@ -0,0 +1,412 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2020 Broadcom + * All rights reserved. + */ + +#include "ulp_template_db_enum.h" +#include "ulp_template_struct.h" +#include "ulp_rte_parser.h" + +/* + * This structure has to be indexed based on the rte_flow_action_type that is + * part of DPDK. The below array is list of parsing functions for each of the + * flow actions that are supported. + */ +struct bnxt_ulp_rte_act_info ulp_act_info[] = { + [RTE_FLOW_ACTION_TYPE_END] = { + .act_type = BNXT_ULP_ACT_TYPE_END, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_VOID] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_void_act_handler + }, + [RTE_FLOW_ACTION_TYPE_PASSTHRU] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_JUMP] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_jump_act_handler + }, + [RTE_FLOW_ACTION_TYPE_MARK] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_mark_act_handler + }, + [RTE_FLOW_ACTION_TYPE_FLAG] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_QUEUE] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_DROP] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_drop_act_handler + }, + [RTE_FLOW_ACTION_TYPE_COUNT] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_count_act_handler + }, + [RTE_FLOW_ACTION_TYPE_RSS] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_rss_act_handler + }, + [RTE_FLOW_ACTION_TYPE_PF] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_pf_act_handler + }, + [RTE_FLOW_ACTION_TYPE_VF] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_vf_act_handler + }, + [RTE_FLOW_ACTION_TYPE_PHY_PORT] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_phy_port_act_handler + }, + [RTE_FLOW_ACTION_TYPE_PORT_ID] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_port_id_act_handler + }, + [RTE_FLOW_ACTION_TYPE_METER] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_SECURITY] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_of_pop_vlan_act_handler + }, + [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_of_push_vlan_act_handler + }, + [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_of_set_vlan_vid_act_handler + }, + [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_of_set_vlan_pcp_act_handler + }, + [RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_vxlan_encap_act_handler + }, + [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_vxlan_decap_act_handler + }, + [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_RAW_DECAP] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_set_ipv4_src_act_handler + }, + [RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_set_ipv4_dst_act_handler + }, + [RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_set_tp_src_act_handler + }, + [RTE_FLOW_ACTION_TYPE_SET_TP_DST] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_set_tp_dst_act_handler + }, + [RTE_FLOW_ACTION_TYPE_MAC_SWAP] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_DEC_TTL] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_dec_ttl_act_handler + }, + [RTE_FLOW_ACTION_TYPE_SET_TTL] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + } +}; + +/* + * This table has to be indexed based on the rte_flow_item_type that is part of + * DPDK. The below array is list of parsing functions for each of the flow items + * that are supported. + */ +struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { + [RTE_FLOW_ITEM_TYPE_END] = { + .hdr_type = BNXT_ULP_HDR_TYPE_END, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_VOID] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_void_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_INVERT] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ANY] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_PF] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_pf_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_VF] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_vf_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_PHY_PORT] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_phy_port_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_PORT_ID] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_port_id_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_RAW] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ETH] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_eth_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_VLAN] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_vlan_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_IPV4] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_ipv4_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_IPV6] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_ipv6_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_ICMP] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_UDP] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_udp_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_TCP] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_tcp_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_SCTP] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_VXLAN] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_vxlan_hdr_handler + }, + [RTE_FLOW_ITEM_TYPE_E_TAG] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_NVGRE] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_MPLS] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_GRE] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_FUZZY] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_GTP] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_GTPC] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_GTPU] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ESP] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_GENEVE] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_IPV6_EXT] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ICMP6] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_MARK] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_META] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_GRE_KEY] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_GTP_PSC] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_PPPOES] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_PPPOED] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_NSH] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_IGMP] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_AH] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + [RTE_FLOW_ITEM_TYPE_HIGIG2] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + } +}; diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 3fb29c0cb4..7c048a33a0 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1,9 +1,8 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ -#include #include "bnxt.h" #include "ulp_template_db_enum.h" #include "ulp_template_struct.h" @@ -228,11 +227,6 @@ bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params) BNXT_ULP_CF_IDX_VF_FUNC_PARIF, parif); - /* populate the loopback parif */ - ULP_COMP_FLD_IDX_WR(params, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF, - BNXT_ULP_SYM_VF_FUNC_PARIF); - } else { /* Set DRV func PARIF */ if (ulp_port_db_parif_get(params->ulp_ctx, ifindex, @@ -301,6 +295,9 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params) /* Merge the hdr_fp_bit into the proto header bit */ params->hdr_bitmap.bits |= params->hdr_fp_bit.bits; + /* Update the comp fld fid */ + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FID, params->fid); + /* Update the computed interface parameters */ bnxt_ulp_comp_fld_intf_update(params); @@ -626,7 +623,7 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param, } } -/* Internal Function to identify broadcast or multicast packets */ +/* Internal Function to indentify broadcast or multicast packets */ static int32_t ulp_rte_parser_is_bcmc_addr(const struct rte_ether_addr *eth_addr) { @@ -686,10 +683,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, ulp_rte_prsr_mask_copy(params, &idx, ð_mask->type, sizeof(eth_mask->type)); } - /* Add number of vlan header elements */ + /* Add number of Eth header elements */ params->field_idx += BNXT_ULP_PROTO_HDR_ETH_NUM; - params->vlan_idx = params->field_idx; - params->field_idx += BNXT_ULP_PROTO_HDR_VLAN_NUM; /* Update the protocol hdr bitmap */ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, @@ -722,7 +717,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, const struct rte_flow_item_vlan *vlan_mask = item->mask; struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bit; - uint32_t idx = params->vlan_idx; + uint32_t idx = params->field_idx; uint16_t vlan_tag, priority; uint32_t outer_vtag_num; uint32_t inner_vtag_num; @@ -769,7 +764,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, vlan_tag = htons(vlan_tag); /* - * The priority field is ignored since OVS is setting it as + * The priortiy field is ignored since OVS is seting it as * wild card match and it is not supported. This is a work * around and shall be addressed in the future. */ @@ -781,8 +776,8 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, ulp_rte_prsr_mask_copy(params, &idx, &vlan_mask->inner_type, sizeof(vlan_mask->inner_type)); } - /* Set the vlan index to new incremented value */ - params->vlan_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM; + /* Set the field index to new incremented value */ + params->field_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM; /* Get the outer tag and inner tag counts */ outer_vtag_num = ULP_COMP_FLD_IDX_RD(params, @@ -965,7 +960,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, &ipv4_mask->hdr.version_ihl, sizeof(ipv4_mask->hdr.version_ihl)); /* - * The tos field is ignored since OVS is setting it as wild card + * The tos field is ignored since OVS is seting it as wild card * match and it is not supported. This is a work around and * shall be addressed in the future. */ @@ -1013,13 +1008,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } - /* Some of the PMD applications may set the protocol field - * in the IPv4 spec but don't set the mask. So, consider - * the mask in the proto value calculation. - */ - if (ipv4_mask) - proto &= ipv4_mask->hdr.next_proto_id; - /* Update the field protocol hdr bitmap */ ulp_rte_l3_proto_type_update(params, proto, inner_flag); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); @@ -1117,8 +1105,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, &vtcf_mask, size); /* - * The TC and flow label field are ignored since OVS is - * setting it for match and it is not supported. + * The TC and flow lable field are ignored since OVS is seting + * it for match and it is not supported. * This is a work around and * shall be addressed in the future. */ @@ -1158,13 +1146,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } - /* Some of the PMD applications may set the protocol field - * in the IPv6 spec but don't set the mask. So, consider - * the mask in proto value calculation. - */ - if (ipv6_mask) - proto &= ipv6_mask->hdr.proto; - /* Update the field protocol hdr bitmap */ ulp_rte_l3_proto_type_update(params, proto, inner_flag); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); @@ -1549,7 +1530,7 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item, buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG]; ulp_encap_buffer_copy(buff, item->spec, - sizeof(struct rte_vlan_hdr), + sizeof(struct rte_flow_item_vlan), ULP_BUFFER_ALIGN_8_BYTE); if (!ulp_rte_item_skip_void(&item, 1)) @@ -1560,15 +1541,15 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item, if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) { vlan_num++; memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG + - sizeof(struct rte_vlan_hdr)], + sizeof(struct rte_flow_item_vlan)], item->spec, - sizeof(struct rte_vlan_hdr)); + sizeof(struct rte_flow_item_vlan)); if (!ulp_rte_item_skip_void(&item, 1)) return BNXT_TF_RC_ERROR; } /* Update the vlan count and size of more than one */ if (vlan_num) { - vlan_size = vlan_num * sizeof(struct rte_vlan_hdr); + vlan_size = vlan_num * sizeof(struct rte_flow_item_vlan); vlan_num = tfp_cpu_to_be_32(vlan_num); memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM], &vlan_num, @@ -1727,7 +1708,7 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item, BNXT_TF_DBG(ERR, "vxlan encap does not have vni\n"); return BNXT_TF_RC_ERROR; } - vxlan_size = sizeof(struct rte_vxlan_hdr); + vxlan_size = sizeof(struct rte_flow_item_vxlan); /* copy the vxlan details */ memcpy(&vxlan_spec, item->spec, vxlan_size); vxlan_spec.flags = 0x08; diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index 27a5131bb3..7996317903 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index 92d3c043ef..509cbd26a8 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -1,815 +1,143 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ +/* date: Mon Nov 23 17:33:02 2020 */ + #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" -#include "ulp_rte_parser.h" +#include "ulp_template_db_tbl.h" /* * Action signature table: * maps hash id to ulp_act_match_list[] index */ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_ACT_HID_015a] = 1, - [BNXT_ULP_ACT_HID_00eb] = 2, - [BNXT_ULP_ACT_HID_0043] = 3, - [BNXT_ULP_ACT_HID_03d8] = 4, - [BNXT_ULP_ACT_HID_02c1] = 5, - [BNXT_ULP_ACT_HID_015e] = 6, - [BNXT_ULP_ACT_HID_00ef] = 7, - [BNXT_ULP_ACT_HID_0047] = 8, - [BNXT_ULP_ACT_HID_03dc] = 9, - [BNXT_ULP_ACT_HID_02c5] = 10, - [BNXT_ULP_ACT_HID_025b] = 11, - [BNXT_ULP_ACT_HID_01ec] = 12, - [BNXT_ULP_ACT_HID_0144] = 13, - [BNXT_ULP_ACT_HID_04d9] = 14, - [BNXT_ULP_ACT_HID_03c2] = 15, - [BNXT_ULP_ACT_HID_025f] = 16, - [BNXT_ULP_ACT_HID_01f0] = 17, - [BNXT_ULP_ACT_HID_0148] = 18, - [BNXT_ULP_ACT_HID_04dd] = 19, - [BNXT_ULP_ACT_HID_03c6] = 20, - [BNXT_ULP_ACT_HID_0000] = 21, - [BNXT_ULP_ACT_HID_0002] = 22, - [BNXT_ULP_ACT_HID_0800] = 23, - [BNXT_ULP_ACT_HID_0101] = 24, - [BNXT_ULP_ACT_HID_0020] = 25, - [BNXT_ULP_ACT_HID_0901] = 26, - [BNXT_ULP_ACT_HID_0121] = 27, - [BNXT_ULP_ACT_HID_0004] = 28, - [BNXT_ULP_ACT_HID_0006] = 29, - [BNXT_ULP_ACT_HID_0804] = 30, - [BNXT_ULP_ACT_HID_0105] = 31, - [BNXT_ULP_ACT_HID_0024] = 32, - [BNXT_ULP_ACT_HID_0905] = 33, - [BNXT_ULP_ACT_HID_0125] = 34, - [BNXT_ULP_ACT_HID_0001] = 35, - [BNXT_ULP_ACT_HID_0005] = 36, - [BNXT_ULP_ACT_HID_0009] = 37, - [BNXT_ULP_ACT_HID_000d] = 38, - [BNXT_ULP_ACT_HID_0021] = 39, - [BNXT_ULP_ACT_HID_0029] = 40, - [BNXT_ULP_ACT_HID_0025] = 41, - [BNXT_ULP_ACT_HID_002d] = 42, - [BNXT_ULP_ACT_HID_0801] = 43, - [BNXT_ULP_ACT_HID_0809] = 44, - [BNXT_ULP_ACT_HID_0805] = 45, - [BNXT_ULP_ACT_HID_080d] = 46, - [BNXT_ULP_ACT_HID_0c15] = 47, - [BNXT_ULP_ACT_HID_0c19] = 48, - [BNXT_ULP_ACT_HID_02f6] = 49, - [BNXT_ULP_ACT_HID_04f8] = 50, - [BNXT_ULP_ACT_HID_01df] = 51, - [BNXT_ULP_ACT_HID_07e5] = 52, - [BNXT_ULP_ACT_HID_06ce] = 53, - [BNXT_ULP_ACT_HID_02fa] = 54, - [BNXT_ULP_ACT_HID_04fc] = 55, - [BNXT_ULP_ACT_HID_01e3] = 56, - [BNXT_ULP_ACT_HID_07e9] = 57, - [BNXT_ULP_ACT_HID_06d2] = 58, - [BNXT_ULP_ACT_HID_03f7] = 59, - [BNXT_ULP_ACT_HID_05f9] = 60, - [BNXT_ULP_ACT_HID_02e0] = 61, - [BNXT_ULP_ACT_HID_08e6] = 62, - [BNXT_ULP_ACT_HID_07cf] = 63, - [BNXT_ULP_ACT_HID_03fb] = 64, - [BNXT_ULP_ACT_HID_05fd] = 65, - [BNXT_ULP_ACT_HID_02e4] = 66, - [BNXT_ULP_ACT_HID_08ea] = 67, - [BNXT_ULP_ACT_HID_07d3] = 68, - [BNXT_ULP_ACT_HID_040d] = 69, - [BNXT_ULP_ACT_HID_040f] = 70, - [BNXT_ULP_ACT_HID_0413] = 71, - [BNXT_ULP_ACT_HID_0567] = 72, - [BNXT_ULP_ACT_HID_0a49] = 73, - [BNXT_ULP_ACT_HID_050e] = 74, - [BNXT_ULP_ACT_HID_0668] = 75, - [BNXT_ULP_ACT_HID_0b4a] = 76, - [BNXT_ULP_ACT_HID_0411] = 77, - [BNXT_ULP_ACT_HID_056b] = 78, - [BNXT_ULP_ACT_HID_0a4d] = 79, - [BNXT_ULP_ACT_HID_0512] = 80, - [BNXT_ULP_ACT_HID_066c] = 81, - [BNXT_ULP_ACT_HID_0b4e] = 82 + [BNXT_ULP_ACT_HID_0000] = 1, + [BNXT_ULP_ACT_HID_0001] = 2, + [BNXT_ULP_ACT_HID_0400] = 3, + [BNXT_ULP_ACT_HID_0331] = 4, + [BNXT_ULP_ACT_HID_0010] = 5, + [BNXT_ULP_ACT_HID_0731] = 6, + [BNXT_ULP_ACT_HID_0341] = 7, + [BNXT_ULP_ACT_HID_0002] = 8, + [BNXT_ULP_ACT_HID_0003] = 9, + [BNXT_ULP_ACT_HID_0402] = 10, + [BNXT_ULP_ACT_HID_0333] = 11, + [BNXT_ULP_ACT_HID_0012] = 12, + [BNXT_ULP_ACT_HID_0733] = 13, + [BNXT_ULP_ACT_HID_0343] = 14 }; /* Array for the act matcher list */ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [1] = { - .act_hid = BNXT_ULP_ACT_HID_015a, + .act_hid = BNXT_ULP_ACT_HID_0000, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [2] = { - .act_hid = BNXT_ULP_ACT_HID_00eb, + .act_hid = BNXT_ULP_ACT_HID_0001, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [3] = { - .act_hid = BNXT_ULP_ACT_HID_0043, + .act_hid = BNXT_ULP_ACT_HID_0400, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [4] = { - .act_hid = BNXT_ULP_ACT_HID_03d8, + .act_hid = BNXT_ULP_ACT_HID_0331, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [5] = { - .act_hid = BNXT_ULP_ACT_HID_02c1, + .act_hid = BNXT_ULP_ACT_HID_0010, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [6] = { - .act_hid = BNXT_ULP_ACT_HID_015e, + .act_hid = BNXT_ULP_ACT_HID_0731, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [7] = { - .act_hid = BNXT_ULP_ACT_HID_00ef, + .act_hid = BNXT_ULP_ACT_HID_0341, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [8] = { - .act_hid = BNXT_ULP_ACT_HID_0047, + .act_hid = BNXT_ULP_ACT_HID_0002, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [9] = { - .act_hid = BNXT_ULP_ACT_HID_03dc, + .act_hid = BNXT_ULP_ACT_HID_0003, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_ACTION_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [10] = { - .act_hid = BNXT_ULP_ACT_HID_02c5, + .act_hid = BNXT_ULP_ACT_HID_0402, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [11] = { - .act_hid = BNXT_ULP_ACT_HID_025b, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [12] = { - .act_hid = BNXT_ULP_ACT_HID_01ec, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [13] = { - .act_hid = BNXT_ULP_ACT_HID_0144, + .act_hid = BNXT_ULP_ACT_HID_0333, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [14] = { - .act_hid = BNXT_ULP_ACT_HID_04d9, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [15] = { - .act_hid = BNXT_ULP_ACT_HID_03c2, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [16] = { - .act_hid = BNXT_ULP_ACT_HID_025f, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [17] = { - .act_hid = BNXT_ULP_ACT_HID_01f0, - .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [18] = { - .act_hid = BNXT_ULP_ACT_HID_0148, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [19] = { - .act_hid = BNXT_ULP_ACT_HID_04dd, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [20] = { - .act_hid = BNXT_ULP_ACT_HID_03c6, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [21] = { - .act_hid = BNXT_ULP_ACT_HID_0000, - .act_sig = { .bits = - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [22] = { - .act_hid = BNXT_ULP_ACT_HID_0002, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [23] = { - .act_hid = BNXT_ULP_ACT_HID_0800, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [24] = { - .act_hid = BNXT_ULP_ACT_HID_0101, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [25] = { - .act_hid = BNXT_ULP_ACT_HID_0020, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [26] = { - .act_hid = BNXT_ULP_ACT_HID_0901, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [27] = { - .act_hid = BNXT_ULP_ACT_HID_0121, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [28] = { - .act_hid = BNXT_ULP_ACT_HID_0004, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [29] = { - .act_hid = BNXT_ULP_ACT_HID_0006, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [30] = { - .act_hid = BNXT_ULP_ACT_HID_0804, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [31] = { - .act_hid = BNXT_ULP_ACT_HID_0105, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [32] = { - .act_hid = BNXT_ULP_ACT_HID_0024, + [12] = { + .act_hid = BNXT_ULP_ACT_HID_0012, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_ACTION_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 + .act_tid = 1 }, - [33] = { - .act_hid = BNXT_ULP_ACT_HID_0905, + [13] = { + .act_hid = BNXT_ULP_ACT_HID_0733, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 + .act_tid = 1 }, - [34] = { - .act_hid = BNXT_ULP_ACT_HID_0125, + [14] = { + .act_hid = BNXT_ULP_ACT_HID_0343, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_ACTION_BIT_VXLAN_DECAP | BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [35] = { - .act_hid = BNXT_ULP_ACT_HID_0001, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [36] = { - .act_hid = BNXT_ULP_ACT_HID_0005, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [37] = { - .act_hid = BNXT_ULP_ACT_HID_0009, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [38] = { - .act_hid = BNXT_ULP_ACT_HID_000d, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [39] = { - .act_hid = BNXT_ULP_ACT_HID_0021, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [40] = { - .act_hid = BNXT_ULP_ACT_HID_0029, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [41] = { - .act_hid = BNXT_ULP_ACT_HID_0025, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [42] = { - .act_hid = BNXT_ULP_ACT_HID_002d, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [43] = { - .act_hid = BNXT_ULP_ACT_HID_0801, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [44] = { - .act_hid = BNXT_ULP_ACT_HID_0809, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [45] = { - .act_hid = BNXT_ULP_ACT_HID_0805, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [46] = { - .act_hid = BNXT_ULP_ACT_HID_080d, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [47] = { - .act_hid = BNXT_ULP_ACT_HID_0c15, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 - }, - [48] = { - .act_hid = BNXT_ULP_ACT_HID_0c19, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 - }, - [49] = { - .act_hid = BNXT_ULP_ACT_HID_02f6, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [50] = { - .act_hid = BNXT_ULP_ACT_HID_04f8, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [51] = { - .act_hid = BNXT_ULP_ACT_HID_01df, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [52] = { - .act_hid = BNXT_ULP_ACT_HID_07e5, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [53] = { - .act_hid = BNXT_ULP_ACT_HID_06ce, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [54] = { - .act_hid = BNXT_ULP_ACT_HID_02fa, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [55] = { - .act_hid = BNXT_ULP_ACT_HID_04fc, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [56] = { - .act_hid = BNXT_ULP_ACT_HID_01e3, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [57] = { - .act_hid = BNXT_ULP_ACT_HID_07e9, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [58] = { - .act_hid = BNXT_ULP_ACT_HID_06d2, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [59] = { - .act_hid = BNXT_ULP_ACT_HID_03f7, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [60] = { - .act_hid = BNXT_ULP_ACT_HID_05f9, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [61] = { - .act_hid = BNXT_ULP_ACT_HID_02e0, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [62] = { - .act_hid = BNXT_ULP_ACT_HID_08e6, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [63] = { - .act_hid = BNXT_ULP_ACT_HID_07cf, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [64] = { - .act_hid = BNXT_ULP_ACT_HID_03fb, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [65] = { - .act_hid = BNXT_ULP_ACT_HID_05fd, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [66] = { - .act_hid = BNXT_ULP_ACT_HID_02e4, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_08ea, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [68] = { - .act_hid = BNXT_ULP_ACT_HID_07d3, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | - BNXT_ULP_ACTION_BIT_SET_IPV4_DST | - BNXT_ULP_ACTION_BIT_SET_TP_SRC | - BNXT_ULP_ACTION_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 - }, - [69] = { - .act_hid = BNXT_ULP_ACT_HID_040d, - .act_sig = { .bits = - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [70] = { - .act_hid = BNXT_ULP_ACT_HID_040f, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [71] = { - .act_hid = BNXT_ULP_ACT_HID_0413, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DROP | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [72] = { - .act_hid = BNXT_ULP_ACT_HID_0567, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | - BNXT_ULP_ACTION_BIT_SET_VLAN_VID | - BNXT_ULP_ACTION_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [73] = { - .act_hid = BNXT_ULP_ACT_HID_0a49, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_SET_VLAN_VID | - BNXT_ULP_ACTION_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [74] = { - .act_hid = BNXT_ULP_ACT_HID_050e, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [75] = { - .act_hid = BNXT_ULP_ACT_HID_0668, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | - BNXT_ULP_ACTION_BIT_SET_VLAN_VID | - BNXT_ULP_ACTION_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [76] = { - .act_hid = BNXT_ULP_ACT_HID_0b4a, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_VLAN_VID | - BNXT_ULP_ACTION_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [77] = { - .act_hid = BNXT_ULP_ACT_HID_0411, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [78] = { - .act_hid = BNXT_ULP_ACT_HID_056b, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | - BNXT_ULP_ACTION_BIT_SET_VLAN_VID | - BNXT_ULP_ACTION_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [79] = { - .act_hid = BNXT_ULP_ACT_HID_0a4d, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_SET_VLAN_VID | - BNXT_ULP_ACTION_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [80] = { - .act_hid = BNXT_ULP_ACT_HID_0512, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [81] = { - .act_hid = BNXT_ULP_ACT_HID_066c, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | - BNXT_ULP_ACTION_BIT_SET_VLAN_VID | - BNXT_ULP_ACTION_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [82] = { - .act_hid = BNXT_ULP_ACT_HID_0b4e, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_SET_VLAN_VID | - BNXT_ULP_ACTION_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 + .act_tid = 1 } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index 5c3e714f48..38f523aa7a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ +/* date: Mon Nov 23 17:33:02 2020 */ + #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" -#include "ulp_rte_parser.h" +#include "ulp_template_db_tbl.h" /* Define the template structures */ /* @@ -14,437 +16,336 @@ * maps hash id to ulp_class_match_list[] index */ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_0138] = 1, - [BNXT_ULP_CLASS_HID_03f0] = 2, - [BNXT_ULP_CLASS_HID_0139] = 3, - [BNXT_ULP_CLASS_HID_03f1] = 4, - [BNXT_ULP_CLASS_HID_068b] = 5, - [BNXT_ULP_CLASS_HID_0143] = 6, - [BNXT_ULP_CLASS_HID_0118] = 7, - [BNXT_ULP_CLASS_HID_03d0] = 8, - [BNXT_ULP_CLASS_HID_0119] = 9, - [BNXT_ULP_CLASS_HID_03d1] = 10, - [BNXT_ULP_CLASS_HID_06ab] = 11, - [BNXT_ULP_CLASS_HID_0163] = 12, - [BNXT_ULP_CLASS_HID_0128] = 13, - [BNXT_ULP_CLASS_HID_03e0] = 14, - [BNXT_ULP_CLASS_HID_0129] = 15, - [BNXT_ULP_CLASS_HID_03e1] = 16, - [BNXT_ULP_CLASS_HID_069b] = 17, - [BNXT_ULP_CLASS_HID_0153] = 18, - [BNXT_ULP_CLASS_HID_0134] = 19, - [BNXT_ULP_CLASS_HID_03fc] = 20, - [BNXT_ULP_CLASS_HID_0135] = 21, - [BNXT_ULP_CLASS_HID_03fd] = 22, - [BNXT_ULP_CLASS_HID_0687] = 23, - [BNXT_ULP_CLASS_HID_014f] = 24, - [BNXT_ULP_CLASS_HID_0114] = 25, - [BNXT_ULP_CLASS_HID_03dc] = 26, - [BNXT_ULP_CLASS_HID_0115] = 27, - [BNXT_ULP_CLASS_HID_03dd] = 28, - [BNXT_ULP_CLASS_HID_06a7] = 29, - [BNXT_ULP_CLASS_HID_016f] = 30, - [BNXT_ULP_CLASS_HID_0124] = 31, - [BNXT_ULP_CLASS_HID_03ec] = 32, - [BNXT_ULP_CLASS_HID_0125] = 33, - [BNXT_ULP_CLASS_HID_03ed] = 34, - [BNXT_ULP_CLASS_HID_0697] = 35, - [BNXT_ULP_CLASS_HID_015f] = 36, - [BNXT_ULP_CLASS_HID_0452] = 37, - [BNXT_ULP_CLASS_HID_0528] = 38, - [BNXT_ULP_CLASS_HID_0790] = 39, - [BNXT_ULP_CLASS_HID_046e] = 40, - [BNXT_ULP_CLASS_HID_0462] = 41, - [BNXT_ULP_CLASS_HID_0518] = 42, - [BNXT_ULP_CLASS_HID_07a0] = 43, - [BNXT_ULP_CLASS_HID_045e] = 44, - [BNXT_ULP_CLASS_HID_0228] = 45, - [BNXT_ULP_CLASS_HID_06d0] = 46, - [BNXT_ULP_CLASS_HID_02be] = 47, - [BNXT_ULP_CLASS_HID_07a6] = 48, - [BNXT_ULP_CLASS_HID_0218] = 49, - [BNXT_ULP_CLASS_HID_06e0] = 50, - [BNXT_ULP_CLASS_HID_028e] = 51, - [BNXT_ULP_CLASS_HID_0796] = 52, - [BNXT_ULP_CLASS_HID_079c] = 53, - [BNXT_ULP_CLASS_HID_0654] = 54, - [BNXT_ULP_CLASS_HID_06d2] = 55, - [BNXT_ULP_CLASS_HID_058a] = 56, - [BNXT_ULP_CLASS_HID_052f] = 57, - [BNXT_ULP_CLASS_HID_07e7] = 58, - [BNXT_ULP_CLASS_HID_079d] = 59, - [BNXT_ULP_CLASS_HID_0655] = 60, - [BNXT_ULP_CLASS_HID_046d] = 61, - [BNXT_ULP_CLASS_HID_0725] = 62, - [BNXT_ULP_CLASS_HID_06d3] = 63, - [BNXT_ULP_CLASS_HID_058b] = 64, - [BNXT_ULP_CLASS_HID_07ac] = 65, - [BNXT_ULP_CLASS_HID_0664] = 66, - [BNXT_ULP_CLASS_HID_06e2] = 67, - [BNXT_ULP_CLASS_HID_05ba] = 68, - [BNXT_ULP_CLASS_HID_051f] = 69, - [BNXT_ULP_CLASS_HID_07d7] = 70, - [BNXT_ULP_CLASS_HID_07ad] = 71, - [BNXT_ULP_CLASS_HID_0665] = 72, - [BNXT_ULP_CLASS_HID_045d] = 73, - [BNXT_ULP_CLASS_HID_0715] = 74, - [BNXT_ULP_CLASS_HID_06e3] = 75, - [BNXT_ULP_CLASS_HID_05bb] = 76, - [BNXT_ULP_CLASS_HID_016a] = 77, - [BNXT_ULP_CLASS_HID_03d2] = 78, - [BNXT_ULP_CLASS_HID_0612] = 79, - [BNXT_ULP_CLASS_HID_00da] = 80, - [BNXT_ULP_CLASS_HID_06bd] = 81, - [BNXT_ULP_CLASS_HID_0165] = 82, - [BNXT_ULP_CLASS_HID_016b] = 83, - [BNXT_ULP_CLASS_HID_03d3] = 84, - [BNXT_ULP_CLASS_HID_03a5] = 85, - [BNXT_ULP_CLASS_HID_066d] = 86, - [BNXT_ULP_CLASS_HID_0613] = 87, - [BNXT_ULP_CLASS_HID_00db] = 88, - [BNXT_ULP_CLASS_HID_015a] = 89, - [BNXT_ULP_CLASS_HID_03e2] = 90, - [BNXT_ULP_CLASS_HID_0622] = 91, - [BNXT_ULP_CLASS_HID_00ea] = 92, - [BNXT_ULP_CLASS_HID_068d] = 93, - [BNXT_ULP_CLASS_HID_0155] = 94, - [BNXT_ULP_CLASS_HID_015b] = 95, - [BNXT_ULP_CLASS_HID_03e3] = 96, - [BNXT_ULP_CLASS_HID_0395] = 97, - [BNXT_ULP_CLASS_HID_065d] = 98, - [BNXT_ULP_CLASS_HID_0623] = 99, - [BNXT_ULP_CLASS_HID_00eb] = 100, - [BNXT_ULP_CLASS_HID_04bc] = 101, - [BNXT_ULP_CLASS_HID_0442] = 102, - [BNXT_ULP_CLASS_HID_050a] = 103, - [BNXT_ULP_CLASS_HID_06ba] = 104, - [BNXT_ULP_CLASS_HID_0472] = 105, - [BNXT_ULP_CLASS_HID_0700] = 106, - [BNXT_ULP_CLASS_HID_04c8] = 107, - [BNXT_ULP_CLASS_HID_0678] = 108, - [BNXT_ULP_CLASS_HID_061f] = 109, - [BNXT_ULP_CLASS_HID_05ad] = 110, - [BNXT_ULP_CLASS_HID_06a5] = 111, - [BNXT_ULP_CLASS_HID_0455] = 112, - [BNXT_ULP_CLASS_HID_05dd] = 113, - [BNXT_ULP_CLASS_HID_0563] = 114, - [BNXT_ULP_CLASS_HID_059b] = 115, - [BNXT_ULP_CLASS_HID_070b] = 116, - [BNXT_ULP_CLASS_HID_04bd] = 117, - [BNXT_ULP_CLASS_HID_0443] = 118, - [BNXT_ULP_CLASS_HID_050b] = 119, - [BNXT_ULP_CLASS_HID_06bb] = 120, - [BNXT_ULP_CLASS_HID_0473] = 121, - [BNXT_ULP_CLASS_HID_0701] = 122, - [BNXT_ULP_CLASS_HID_04c9] = 123, - [BNXT_ULP_CLASS_HID_0679] = 124, - [BNXT_ULP_CLASS_HID_05e2] = 125, - [BNXT_ULP_CLASS_HID_00b0] = 126, - [BNXT_ULP_CLASS_HID_0648] = 127, - [BNXT_ULP_CLASS_HID_03f8] = 128, - [BNXT_ULP_CLASS_HID_02ea] = 129, - [BNXT_ULP_CLASS_HID_05b8] = 130, - [BNXT_ULP_CLASS_HID_0370] = 131, - [BNXT_ULP_CLASS_HID_00e0] = 132, - [BNXT_ULP_CLASS_HID_0745] = 133, - [BNXT_ULP_CLASS_HID_0213] = 134, - [BNXT_ULP_CLASS_HID_031b] = 135, - [BNXT_ULP_CLASS_HID_008b] = 136, - [BNXT_ULP_CLASS_HID_044d] = 137, - [BNXT_ULP_CLASS_HID_071b] = 138, - [BNXT_ULP_CLASS_HID_0003] = 139, - [BNXT_ULP_CLASS_HID_05b3] = 140, - [BNXT_ULP_CLASS_HID_05e3] = 141, - [BNXT_ULP_CLASS_HID_00b1] = 142, - [BNXT_ULP_CLASS_HID_0649] = 143, - [BNXT_ULP_CLASS_HID_03f9] = 144, - [BNXT_ULP_CLASS_HID_02eb] = 145, - [BNXT_ULP_CLASS_HID_05b9] = 146, - [BNXT_ULP_CLASS_HID_0371] = 147, - [BNXT_ULP_CLASS_HID_00e1] = 148, - [BNXT_ULP_CLASS_HID_0000] = 149, - [BNXT_ULP_CLASS_HID_00ce] = 150, - [BNXT_ULP_CLASS_HID_01b6] = 151, - [BNXT_ULP_CLASS_HID_0074] = 152, - [BNXT_ULP_CLASS_HID_00fe] = 153, - [BNXT_ULP_CLASS_HID_03bc] = 154, - [BNXT_ULP_CLASS_HID_0206] = 155, - [BNXT_ULP_CLASS_HID_02c4] = 156, - [BNXT_ULP_CLASS_HID_055a] = 157, - [BNXT_ULP_CLASS_HID_045a] = 158, - [BNXT_ULP_CLASS_HID_061a] = 159, - [BNXT_ULP_CLASS_HID_051a] = 160, - [BNXT_ULP_CLASS_HID_074a] = 161, - [BNXT_ULP_CLASS_HID_004e] = 162, - [BNXT_ULP_CLASS_HID_040a] = 163, - [BNXT_ULP_CLASS_HID_010e] = 164, - [BNXT_ULP_CLASS_HID_048b] = 165, - [BNXT_ULP_CLASS_HID_0749] = 166, - [BNXT_ULP_CLASS_HID_05f1] = 167, - [BNXT_ULP_CLASS_HID_04b7] = 168, - [BNXT_ULP_CLASS_HID_049b] = 169, - [BNXT_ULP_CLASS_HID_0759] = 170, - [BNXT_ULP_CLASS_HID_05e1] = 171, - [BNXT_ULP_CLASS_HID_04a7] = 172, - [BNXT_ULP_CLASS_HID_0301] = 173, - [BNXT_ULP_CLASS_HID_07f9] = 174, - [BNXT_ULP_CLASS_HID_0397] = 175, - [BNXT_ULP_CLASS_HID_068f] = 176, - [BNXT_ULP_CLASS_HID_02f1] = 177, - [BNXT_ULP_CLASS_HID_0609] = 178, - [BNXT_ULP_CLASS_HID_0267] = 179, - [BNXT_ULP_CLASS_HID_077f] = 180, - [BNXT_ULP_CLASS_HID_01e1] = 181, - [BNXT_ULP_CLASS_HID_0329] = 182, - [BNXT_ULP_CLASS_HID_01c1] = 183, - [BNXT_ULP_CLASS_HID_0309] = 184, - [BNXT_ULP_CLASS_HID_01d1] = 185, - [BNXT_ULP_CLASS_HID_0319] = 186, - [BNXT_ULP_CLASS_HID_01e2] = 187, - [BNXT_ULP_CLASS_HID_032a] = 188, - [BNXT_ULP_CLASS_HID_0650] = 189, - [BNXT_ULP_CLASS_HID_0198] = 190, - [BNXT_ULP_CLASS_HID_01c2] = 191, - [BNXT_ULP_CLASS_HID_030a] = 192, - [BNXT_ULP_CLASS_HID_0670] = 193, - [BNXT_ULP_CLASS_HID_01b8] = 194, - [BNXT_ULP_CLASS_HID_01d2] = 195, - [BNXT_ULP_CLASS_HID_031a] = 196, - [BNXT_ULP_CLASS_HID_0660] = 197, - [BNXT_ULP_CLASS_HID_01a8] = 198, - [BNXT_ULP_CLASS_HID_01dd] = 199, - [BNXT_ULP_CLASS_HID_0315] = 200, - [BNXT_ULP_CLASS_HID_003d] = 201, - [BNXT_ULP_CLASS_HID_02f5] = 202, - [BNXT_ULP_CLASS_HID_01cd] = 203, - [BNXT_ULP_CLASS_HID_0305] = 204, - [BNXT_ULP_CLASS_HID_01de] = 205, - [BNXT_ULP_CLASS_HID_0316] = 206, - [BNXT_ULP_CLASS_HID_066c] = 207, - [BNXT_ULP_CLASS_HID_01a4] = 208, - [BNXT_ULP_CLASS_HID_003e] = 209, - [BNXT_ULP_CLASS_HID_02f6] = 210, - [BNXT_ULP_CLASS_HID_078c] = 211, - [BNXT_ULP_CLASS_HID_0044] = 212, - [BNXT_ULP_CLASS_HID_01ce] = 213, - [BNXT_ULP_CLASS_HID_0306] = 214, - [BNXT_ULP_CLASS_HID_067c] = 215, - [BNXT_ULP_CLASS_HID_01b4] = 216 + [BNXT_ULP_CLASS_HID_00fc] = 1, + [BNXT_ULP_CLASS_HID_0046] = 2, + [BNXT_ULP_CLASS_HID_0056] = 3, + [BNXT_ULP_CLASS_HID_00b8] = 4, + [BNXT_ULP_CLASS_HID_0041] = 5, + [BNXT_ULP_CLASS_HID_00ab] = 6, + [BNXT_ULP_CLASS_HID_0053] = 7, + [BNXT_ULP_CLASS_HID_00a5] = 8, + [BNXT_ULP_CLASS_HID_0069] = 9, + [BNXT_ULP_CLASS_HID_009d] = 10, + [BNXT_ULP_CLASS_HID_0005] = 11, + [BNXT_ULP_CLASS_HID_006f] = 12, + [BNXT_ULP_CLASS_HID_00af] = 13, + [BNXT_ULP_CLASS_HID_00d3] = 14, + [BNXT_ULP_CLASS_HID_005b] = 15, + [BNXT_ULP_CLASS_HID_00ad] = 16, + [BNXT_ULP_CLASS_HID_0091] = 17, + [BNXT_ULP_CLASS_HID_00fb] = 18, + [BNXT_ULP_CLASS_HID_0063] = 19, + [BNXT_ULP_CLASS_HID_0097] = 20, + [BNXT_ULP_CLASS_HID_00cc] = 21, + [BNXT_ULP_CLASS_HID_00f0] = 22, + [BNXT_ULP_CLASS_HID_00c0] = 23, + [BNXT_ULP_CLASS_HID_002a] = 24, + [BNXT_ULP_CLASS_HID_00c7] = 25, + [BNXT_ULP_CLASS_HID_0029] = 26, + [BNXT_ULP_CLASS_HID_00d1] = 27, + [BNXT_ULP_CLASS_HID_003b] = 28, + [BNXT_ULP_CLASS_HID_00ef] = 29, + [BNXT_ULP_CLASS_HID_0013] = 30, + [BNXT_ULP_CLASS_HID_009b] = 31, + [BNXT_ULP_CLASS_HID_00ed] = 32, + [BNXT_ULP_CLASS_HID_002d] = 33, + [BNXT_ULP_CLASS_HID_0051] = 34, + [BNXT_ULP_CLASS_HID_00d9] = 35, + [BNXT_ULP_CLASS_HID_0023] = 36, + [BNXT_ULP_CLASS_HID_0017] = 37, + [BNXT_ULP_CLASS_HID_0079] = 38, + [BNXT_ULP_CLASS_HID_00e1] = 39, + [BNXT_ULP_CLASS_HID_0015] = 40 }; /* Array for the proto matcher list */ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { [1] = { - .class_hid = BNXT_ULP_CLASS_HID_0138, + .class_hid = BNXT_ULP_CLASS_HID_00fc, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 0 }, [2] = { - .class_hid = BNXT_ULP_CLASS_HID_03f0, + .class_hid = BNXT_ULP_CLASS_HID_0046, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 1 }, [3] = { - .class_hid = BNXT_ULP_CLASS_HID_0139, + .class_hid = BNXT_ULP_CLASS_HID_0056, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 2 }, [4] = { - .class_hid = BNXT_ULP_CLASS_HID_03f1, + .class_hid = BNXT_ULP_CLASS_HID_00b8, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 3 }, [5] = { - .class_hid = BNXT_ULP_CLASS_HID_068b, + .class_hid = BNXT_ULP_CLASS_HID_0041, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 4 }, [6] = { - .class_hid = BNXT_ULP_CLASS_HID_0143, + .class_hid = BNXT_ULP_CLASS_HID_00ab, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 5 }, [7] = { - .class_hid = BNXT_ULP_CLASS_HID_0118, + .class_hid = BNXT_ULP_CLASS_HID_0053, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 6 }, [8] = { - .class_hid = BNXT_ULP_CLASS_HID_03d0, + .class_hid = BNXT_ULP_CLASS_HID_00a5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 7 }, [9] = { - .class_hid = BNXT_ULP_CLASS_HID_0119, + .class_hid = BNXT_ULP_CLASS_HID_0069, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 8 }, [10] = { - .class_hid = BNXT_ULP_CLASS_HID_03d1, + .class_hid = BNXT_ULP_CLASS_HID_009d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 9 }, [11] = { - .class_hid = BNXT_ULP_CLASS_HID_06ab, + .class_hid = BNXT_ULP_CLASS_HID_0005, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 10 }, [12] = { - .class_hid = BNXT_ULP_CLASS_HID_0163, + .class_hid = BNXT_ULP_CLASS_HID_006f, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 11 }, [13] = { - .class_hid = BNXT_ULP_CLASS_HID_0128, + .class_hid = BNXT_ULP_CLASS_HID_00af, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 12 }, [14] = { - .class_hid = BNXT_ULP_CLASS_HID_03e0, + .class_hid = BNXT_ULP_CLASS_HID_00d3, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 13 }, [15] = { - .class_hid = BNXT_ULP_CLASS_HID_0129, + .class_hid = BNXT_ULP_CLASS_HID_005b, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -452,15 +353,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 14 }, [16] = { - .class_hid = BNXT_ULP_CLASS_HID_03e1, + .class_hid = BNXT_ULP_CLASS_HID_00ad, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -468,14 +374,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 15 }, [17] = { - .class_hid = BNXT_ULP_CLASS_HID_069b, + .class_hid = BNXT_ULP_CLASS_HID_0091, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -483,16 +396,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 16 }, [18] = { - .class_hid = BNXT_ULP_CLASS_HID_0153, + .class_hid = BNXT_ULP_CLASS_HID_00fb, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -500,3486 +417,451 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 6, - .wc_pri = 17 }, [19] = { - .class_hid = BNXT_ULP_CLASS_HID_0134, + .class_hid = BNXT_ULP_CLASS_HID_0063, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 0 }, [20] = { - .class_hid = BNXT_ULP_CLASS_HID_03fc, + .class_hid = BNXT_ULP_CLASS_HID_0097, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 1 }, [21] = { - .class_hid = BNXT_ULP_CLASS_HID_0135, + .class_hid = BNXT_ULP_CLASS_HID_00cc, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 2 }, [22] = { - .class_hid = BNXT_ULP_CLASS_HID_03fd, + .class_hid = BNXT_ULP_CLASS_HID_00f0, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 3 }, [23] = { - .class_hid = BNXT_ULP_CLASS_HID_0687, + .class_hid = BNXT_ULP_CLASS_HID_00c0, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 4 }, [24] = { - .class_hid = BNXT_ULP_CLASS_HID_014f, + .class_hid = BNXT_ULP_CLASS_HID_002a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 5 }, [25] = { - .class_hid = BNXT_ULP_CLASS_HID_0114, + .class_hid = BNXT_ULP_CLASS_HID_00c7, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 6 }, [26] = { - .class_hid = BNXT_ULP_CLASS_HID_03dc, + .class_hid = BNXT_ULP_CLASS_HID_0029, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 7 }, [27] = { - .class_hid = BNXT_ULP_CLASS_HID_0115, + .class_hid = BNXT_ULP_CLASS_HID_00d1, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 8 }, [28] = { - .class_hid = BNXT_ULP_CLASS_HID_03dd, + .class_hid = BNXT_ULP_CLASS_HID_003b, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 9 }, [29] = { - .class_hid = BNXT_ULP_CLASS_HID_06a7, + .class_hid = BNXT_ULP_CLASS_HID_00ef, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 10 }, [30] = { - .class_hid = BNXT_ULP_CLASS_HID_016f, + .class_hid = BNXT_ULP_CLASS_HID_0013, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 11 }, [31] = { - .class_hid = BNXT_ULP_CLASS_HID_0124, + .class_hid = BNXT_ULP_CLASS_HID_009b, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 12 }, [32] = { - .class_hid = BNXT_ULP_CLASS_HID_03ec, + .class_hid = BNXT_ULP_CLASS_HID_00ed, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 13 }, [33] = { - .class_hid = BNXT_ULP_CLASS_HID_0125, + .class_hid = BNXT_ULP_CLASS_HID_002d, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 14 }, [34] = { - .class_hid = BNXT_ULP_CLASS_HID_03ed, + .class_hid = BNXT_ULP_CLASS_HID_0051, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 15 }, [35] = { - .class_hid = BNXT_ULP_CLASS_HID_0697, + .class_hid = BNXT_ULP_CLASS_HID_00d9, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 16 }, [36] = { - .class_hid = BNXT_ULP_CLASS_HID_015f, + .class_hid = BNXT_ULP_CLASS_HID_0023, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF7_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 7, - .wc_pri = 17 - }, - [37] = { - .class_hid = BNXT_ULP_CLASS_HID_0452, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 8, - .wc_pri = 0 - }, - [38] = { - .class_hid = BNXT_ULP_CLASS_HID_0528, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 8, - .wc_pri = 1 - }, - [39] = { - .class_hid = BNXT_ULP_CLASS_HID_0790, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 8, - .wc_pri = 2 - }, - [40] = { - .class_hid = BNXT_ULP_CLASS_HID_046e, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 8, - .wc_pri = 3 - }, - [41] = { - .class_hid = BNXT_ULP_CLASS_HID_0462, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 9, - .wc_pri = 0 - }, - [42] = { - .class_hid = BNXT_ULP_CLASS_HID_0518, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 9, - .wc_pri = 1 - }, - [43] = { - .class_hid = BNXT_ULP_CLASS_HID_07a0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 9, - .wc_pri = 2 - }, - [44] = { - .class_hid = BNXT_ULP_CLASS_HID_045e, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 9, - .wc_pri = 3 - }, - [45] = { - .class_hid = BNXT_ULP_CLASS_HID_0228, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 10, - .wc_pri = 0 - }, - [46] = { - .class_hid = BNXT_ULP_CLASS_HID_06d0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 10, - .wc_pri = 1 - }, - [47] = { - .class_hid = BNXT_ULP_CLASS_HID_02be, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 10, - .wc_pri = 2 - }, - [48] = { - .class_hid = BNXT_ULP_CLASS_HID_07a6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 10, - .wc_pri = 3 - }, - [49] = { - .class_hid = BNXT_ULP_CLASS_HID_0218, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 11, - .wc_pri = 0 - }, - [50] = { - .class_hid = BNXT_ULP_CLASS_HID_06e0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 11, - .wc_pri = 1 - }, - [51] = { - .class_hid = BNXT_ULP_CLASS_HID_028e, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 11, - .wc_pri = 2 - }, - [52] = { - .class_hid = BNXT_ULP_CLASS_HID_0796, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 11, - .wc_pri = 3 - }, - [53] = { - .class_hid = BNXT_ULP_CLASS_HID_079c, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 0 - }, - [54] = { - .class_hid = BNXT_ULP_CLASS_HID_0654, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 1 - }, - [55] = { - .class_hid = BNXT_ULP_CLASS_HID_06d2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 2 - }, - [56] = { - .class_hid = BNXT_ULP_CLASS_HID_058a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 3 - }, - [57] = { - .class_hid = BNXT_ULP_CLASS_HID_052f, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 4 - }, - [58] = { - .class_hid = BNXT_ULP_CLASS_HID_07e7, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 5 - }, - [59] = { - .class_hid = BNXT_ULP_CLASS_HID_079d, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 6 - }, - [60] = { - .class_hid = BNXT_ULP_CLASS_HID_0655, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 7 - }, - [61] = { - .class_hid = BNXT_ULP_CLASS_HID_046d, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 8 }, - [62] = { - .class_hid = BNXT_ULP_CLASS_HID_0725, + [37] = { + .class_hid = BNXT_ULP_CLASS_HID_0017, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 9 }, - [63] = { - .class_hid = BNXT_ULP_CLASS_HID_06d3, + [38] = { + .class_hid = BNXT_ULP_CLASS_HID_0079, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 10 }, - [64] = { - .class_hid = BNXT_ULP_CLASS_HID_058b, + [39] = { + .class_hid = BNXT_ULP_CLASS_HID_00e1, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 12, - .wc_pri = 11 - }, - [65] = { - .class_hid = BNXT_ULP_CLASS_HID_07ac, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 0 }, - [66] = { - .class_hid = BNXT_ULP_CLASS_HID_0664, + [40] = { + .class_hid = BNXT_ULP_CLASS_HID_0015, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 1 - }, - [67] = { - .class_hid = BNXT_ULP_CLASS_HID_06e2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 2 - }, - [68] = { - .class_hid = BNXT_ULP_CLASS_HID_05ba, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 3 - }, - [69] = { - .class_hid = BNXT_ULP_CLASS_HID_051f, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 4 - }, - [70] = { - .class_hid = BNXT_ULP_CLASS_HID_07d7, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 5 - }, - [71] = { - .class_hid = BNXT_ULP_CLASS_HID_07ad, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 6 - }, - [72] = { - .class_hid = BNXT_ULP_CLASS_HID_0665, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 7 - }, - [73] = { - .class_hid = BNXT_ULP_CLASS_HID_045d, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 8 - }, - [74] = { - .class_hid = BNXT_ULP_CLASS_HID_0715, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 9 - }, - [75] = { - .class_hid = BNXT_ULP_CLASS_HID_06e3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 10 - }, - [76] = { - .class_hid = BNXT_ULP_CLASS_HID_05bb, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 13, - .wc_pri = 11 - }, - [77] = { - .class_hid = BNXT_ULP_CLASS_HID_016a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 0 - }, - [78] = { - .class_hid = BNXT_ULP_CLASS_HID_03d2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 1 - }, - [79] = { - .class_hid = BNXT_ULP_CLASS_HID_0612, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 2 - }, - [80] = { - .class_hid = BNXT_ULP_CLASS_HID_00da, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 3 - }, - [81] = { - .class_hid = BNXT_ULP_CLASS_HID_06bd, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 4 - }, - [82] = { - .class_hid = BNXT_ULP_CLASS_HID_0165, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 5 - }, - [83] = { - .class_hid = BNXT_ULP_CLASS_HID_016b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 6 - }, - [84] = { - .class_hid = BNXT_ULP_CLASS_HID_03d3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 7 - }, - [85] = { - .class_hid = BNXT_ULP_CLASS_HID_03a5, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 8 - }, - [86] = { - .class_hid = BNXT_ULP_CLASS_HID_066d, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 9 - }, - [87] = { - .class_hid = BNXT_ULP_CLASS_HID_0613, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 10 - }, - [88] = { - .class_hid = BNXT_ULP_CLASS_HID_00db, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 14, - .wc_pri = 11 - }, - [89] = { - .class_hid = BNXT_ULP_CLASS_HID_015a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 0 - }, - [90] = { - .class_hid = BNXT_ULP_CLASS_HID_03e2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 1 - }, - [91] = { - .class_hid = BNXT_ULP_CLASS_HID_0622, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 2 - }, - [92] = { - .class_hid = BNXT_ULP_CLASS_HID_00ea, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 3 - }, - [93] = { - .class_hid = BNXT_ULP_CLASS_HID_068d, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 4 - }, - [94] = { - .class_hid = BNXT_ULP_CLASS_HID_0155, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 5 - }, - [95] = { - .class_hid = BNXT_ULP_CLASS_HID_015b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 6 - }, - [96] = { - .class_hid = BNXT_ULP_CLASS_HID_03e3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 7 - }, - [97] = { - .class_hid = BNXT_ULP_CLASS_HID_0395, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 8 - }, - [98] = { - .class_hid = BNXT_ULP_CLASS_HID_065d, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 9 - }, - [99] = { - .class_hid = BNXT_ULP_CLASS_HID_0623, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 10 - }, - [100] = { - .class_hid = BNXT_ULP_CLASS_HID_00eb, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 15, - .wc_pri = 11 - }, - [101] = { - .class_hid = BNXT_ULP_CLASS_HID_04bc, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 0 - }, - [102] = { - .class_hid = BNXT_ULP_CLASS_HID_0442, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 1 - }, - [103] = { - .class_hid = BNXT_ULP_CLASS_HID_050a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 2 - }, - [104] = { - .class_hid = BNXT_ULP_CLASS_HID_06ba, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 3 - }, - [105] = { - .class_hid = BNXT_ULP_CLASS_HID_0472, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 4 - }, - [106] = { - .class_hid = BNXT_ULP_CLASS_HID_0700, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 5 - }, - [107] = { - .class_hid = BNXT_ULP_CLASS_HID_04c8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 6 - }, - [108] = { - .class_hid = BNXT_ULP_CLASS_HID_0678, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 7 - }, - [109] = { - .class_hid = BNXT_ULP_CLASS_HID_061f, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 8 - }, - [110] = { - .class_hid = BNXT_ULP_CLASS_HID_05ad, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 9 - }, - [111] = { - .class_hid = BNXT_ULP_CLASS_HID_06a5, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 10 - }, - [112] = { - .class_hid = BNXT_ULP_CLASS_HID_0455, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 11 - }, - [113] = { - .class_hid = BNXT_ULP_CLASS_HID_05dd, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 12 - }, - [114] = { - .class_hid = BNXT_ULP_CLASS_HID_0563, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 13 - }, - [115] = { - .class_hid = BNXT_ULP_CLASS_HID_059b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 14 - }, - [116] = { - .class_hid = BNXT_ULP_CLASS_HID_070b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 15 - }, - [117] = { - .class_hid = BNXT_ULP_CLASS_HID_04bd, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 16 - }, - [118] = { - .class_hid = BNXT_ULP_CLASS_HID_0443, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 17 - }, - [119] = { - .class_hid = BNXT_ULP_CLASS_HID_050b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 18 - }, - [120] = { - .class_hid = BNXT_ULP_CLASS_HID_06bb, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 19 - }, - [121] = { - .class_hid = BNXT_ULP_CLASS_HID_0473, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 20 - }, - [122] = { - .class_hid = BNXT_ULP_CLASS_HID_0701, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 21 - }, - [123] = { - .class_hid = BNXT_ULP_CLASS_HID_04c9, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 22 - }, - [124] = { - .class_hid = BNXT_ULP_CLASS_HID_0679, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 16, - .wc_pri = 23 - }, - [125] = { - .class_hid = BNXT_ULP_CLASS_HID_05e2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 0 - }, - [126] = { - .class_hid = BNXT_ULP_CLASS_HID_00b0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 1 - }, - [127] = { - .class_hid = BNXT_ULP_CLASS_HID_0648, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 2 - }, - [128] = { - .class_hid = BNXT_ULP_CLASS_HID_03f8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 3 - }, - [129] = { - .class_hid = BNXT_ULP_CLASS_HID_02ea, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 4 - }, - [130] = { - .class_hid = BNXT_ULP_CLASS_HID_05b8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 5 - }, - [131] = { - .class_hid = BNXT_ULP_CLASS_HID_0370, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 6 - }, - [132] = { - .class_hid = BNXT_ULP_CLASS_HID_00e0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 7 - }, - [133] = { - .class_hid = BNXT_ULP_CLASS_HID_0745, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 8 - }, - [134] = { - .class_hid = BNXT_ULP_CLASS_HID_0213, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 9 - }, - [135] = { - .class_hid = BNXT_ULP_CLASS_HID_031b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 10 - }, - [136] = { - .class_hid = BNXT_ULP_CLASS_HID_008b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 11 - }, - [137] = { - .class_hid = BNXT_ULP_CLASS_HID_044d, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 12 - }, - [138] = { - .class_hid = BNXT_ULP_CLASS_HID_071b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 13 - }, - [139] = { - .class_hid = BNXT_ULP_CLASS_HID_0003, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 14 - }, - [140] = { - .class_hid = BNXT_ULP_CLASS_HID_05b3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 15 - }, - [141] = { - .class_hid = BNXT_ULP_CLASS_HID_05e3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 16 - }, - [142] = { - .class_hid = BNXT_ULP_CLASS_HID_00b1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 17 - }, - [143] = { - .class_hid = BNXT_ULP_CLASS_HID_0649, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 18 - }, - [144] = { - .class_hid = BNXT_ULP_CLASS_HID_03f9, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 19 - }, - [145] = { - .class_hid = BNXT_ULP_CLASS_HID_02eb, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 20 - }, - [146] = { - .class_hid = BNXT_ULP_CLASS_HID_05b9, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 21 - }, - [147] = { - .class_hid = BNXT_ULP_CLASS_HID_0371, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 22 - }, - [148] = { - .class_hid = BNXT_ULP_CLASS_HID_00e1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 17, - .wc_pri = 23 - }, - [149] = { - .class_hid = BNXT_ULP_CLASS_HID_0000, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF18_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF18_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 18, - .wc_pri = 0 - }, - [150] = { - .class_hid = BNXT_ULP_CLASS_HID_00ce, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF18_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF18_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 18, - .wc_pri = 1 - }, - [151] = { - .class_hid = BNXT_ULP_CLASS_HID_01b6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF18_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 18, - .wc_pri = 2 - }, - [152] = { - .class_hid = BNXT_ULP_CLASS_HID_0074, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF18_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 18, - .wc_pri = 3 - }, - [153] = { - .class_hid = BNXT_ULP_CLASS_HID_00fe, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF18_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 18, - .wc_pri = 4 - }, - [154] = { - .class_hid = BNXT_ULP_CLASS_HID_03bc, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF18_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 18, - .wc_pri = 5 - }, - [155] = { - .class_hid = BNXT_ULP_CLASS_HID_0206, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 18, - .wc_pri = 6 - }, - [156] = { - .class_hid = BNXT_ULP_CLASS_HID_02c4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 18, - .wc_pri = 7 - }, - [157] = { - .class_hid = BNXT_ULP_CLASS_HID_055a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 19, - .wc_pri = 0 - }, - [158] = { - .class_hid = BNXT_ULP_CLASS_HID_045a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 19, - .wc_pri = 1 - }, - [159] = { - .class_hid = BNXT_ULP_CLASS_HID_061a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 19, - .wc_pri = 2 - }, - [160] = { - .class_hid = BNXT_ULP_CLASS_HID_051a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 19, - .wc_pri = 3 - }, - [161] = { - .class_hid = BNXT_ULP_CLASS_HID_074a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 19, - .wc_pri = 4 - }, - [162] = { - .class_hid = BNXT_ULP_CLASS_HID_004e, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 19, - .wc_pri = 5 - }, - [163] = { - .class_hid = BNXT_ULP_CLASS_HID_040a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 19, - .wc_pri = 6 - }, - [164] = { - .class_hid = BNXT_ULP_CLASS_HID_010e, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 19, - .wc_pri = 7 - }, - [165] = { - .class_hid = BNXT_ULP_CLASS_HID_048b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF20_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 20, - .wc_pri = 0 - }, - [166] = { - .class_hid = BNXT_ULP_CLASS_HID_0749, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF20_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 20, - .wc_pri = 1 - }, - [167] = { - .class_hid = BNXT_ULP_CLASS_HID_05f1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 20, - .wc_pri = 2 - }, - [168] = { - .class_hid = BNXT_ULP_CLASS_HID_04b7, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 20, - .wc_pri = 3 - }, - [169] = { - .class_hid = BNXT_ULP_CLASS_HID_049b, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF21_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 21, - .wc_pri = 0 - }, - [170] = { - .class_hid = BNXT_ULP_CLASS_HID_0759, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF21_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 21, - .wc_pri = 1 - }, - [171] = { - .class_hid = BNXT_ULP_CLASS_HID_05e1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 21, - .wc_pri = 2 - }, - [172] = { - .class_hid = BNXT_ULP_CLASS_HID_04a7, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 21, - .wc_pri = 3 - }, - [173] = { - .class_hid = BNXT_ULP_CLASS_HID_0301, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF22_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 22, - .wc_pri = 0 - }, - [174] = { - .class_hid = BNXT_ULP_CLASS_HID_07f9, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF22_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 22, - .wc_pri = 1 - }, - [175] = { - .class_hid = BNXT_ULP_CLASS_HID_0397, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 22, - .wc_pri = 2 - }, - [176] = { - .class_hid = BNXT_ULP_CLASS_HID_068f, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 22, - .wc_pri = 3 - }, - [177] = { - .class_hid = BNXT_ULP_CLASS_HID_02f1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF23_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 23, - .wc_pri = 0 - }, - [178] = { - .class_hid = BNXT_ULP_CLASS_HID_0609, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF23_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 23, - .wc_pri = 1 - }, - [179] = { - .class_hid = BNXT_ULP_CLASS_HID_0267, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 23, - .wc_pri = 2 - }, - [180] = { - .class_hid = BNXT_ULP_CLASS_HID_077f, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 23, - .wc_pri = 3 - }, - [181] = { - .class_hid = BNXT_ULP_CLASS_HID_01e1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 0 - }, - [182] = { - .class_hid = BNXT_ULP_CLASS_HID_0329, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 1 - }, - [183] = { - .class_hid = BNXT_ULP_CLASS_HID_01c1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 2 - }, - [184] = { - .class_hid = BNXT_ULP_CLASS_HID_0309, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 3 - }, - [185] = { - .class_hid = BNXT_ULP_CLASS_HID_01d1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 4 - }, - [186] = { - .class_hid = BNXT_ULP_CLASS_HID_0319, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 5 - }, - [187] = { - .class_hid = BNXT_ULP_CLASS_HID_01e2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 6 - }, - [188] = { - .class_hid = BNXT_ULP_CLASS_HID_032a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 7 - }, - [189] = { - .class_hid = BNXT_ULP_CLASS_HID_0650, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF24_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 8 - }, - [190] = { - .class_hid = BNXT_ULP_CLASS_HID_0198, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 9 - }, - [191] = { - .class_hid = BNXT_ULP_CLASS_HID_01c2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 10 - }, - [192] = { - .class_hid = BNXT_ULP_CLASS_HID_030a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 11 - }, - [193] = { - .class_hid = BNXT_ULP_CLASS_HID_0670, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF24_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 12 - }, - [194] = { - .class_hid = BNXT_ULP_CLASS_HID_01b8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 13 - }, - [195] = { - .class_hid = BNXT_ULP_CLASS_HID_01d2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 14 - }, - [196] = { - .class_hid = BNXT_ULP_CLASS_HID_031a, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 15 - }, - [197] = { - .class_hid = BNXT_ULP_CLASS_HID_0660, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF24_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 16 - }, - [198] = { - .class_hid = BNXT_ULP_CLASS_HID_01a8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF24_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 24, - .wc_pri = 17 - }, - [199] = { - .class_hid = BNXT_ULP_CLASS_HID_01dd, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 0 - }, - [200] = { - .class_hid = BNXT_ULP_CLASS_HID_0315, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 1 - }, - [201] = { - .class_hid = BNXT_ULP_CLASS_HID_003d, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 2 - }, - [202] = { - .class_hid = BNXT_ULP_CLASS_HID_02f5, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 3 - }, - [203] = { - .class_hid = BNXT_ULP_CLASS_HID_01cd, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 4 - }, - [204] = { - .class_hid = BNXT_ULP_CLASS_HID_0305, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 5 - }, - [205] = { - .class_hid = BNXT_ULP_CLASS_HID_01de, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 6 - }, - [206] = { - .class_hid = BNXT_ULP_CLASS_HID_0316, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 7 - }, - [207] = { - .class_hid = BNXT_ULP_CLASS_HID_066c, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF25_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 8 - }, - [208] = { - .class_hid = BNXT_ULP_CLASS_HID_01a4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 9 - }, - [209] = { - .class_hid = BNXT_ULP_CLASS_HID_003e, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 10 - }, - [210] = { - .class_hid = BNXT_ULP_CLASS_HID_02f6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 11 - }, - [211] = { - .class_hid = BNXT_ULP_CLASS_HID_078c, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF25_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 12 - }, - [212] = { - .class_hid = BNXT_ULP_CLASS_HID_0044, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 13 - }, - [213] = { - .class_hid = BNXT_ULP_CLASS_HID_01ce, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 14 - }, - [214] = { - .class_hid = BNXT_ULP_CLASS_HID_0306, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 15 - }, - [215] = { - .class_hid = BNXT_ULP_CLASS_HID_067c, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF25_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 16 - }, - [216] = { - .class_hid = BNXT_ULP_CLASS_HID_01b4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF25_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 25, - .wc_pri = 17 } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 6bb26f0ad5..12d91e6aa4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -1,34 +1,60 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ -/* date: Thu Oct 15 17:28:37 2020 */ +/* date: Mon Nov 23 17:33:02 2020 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 19 +#define BNXT_ULP_REGFILE_MAX_SZ 31 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 4 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 217 -#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919 -#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907 -#define BNXT_ULP_CLASS_HID_SHFTR 32 -#define BNXT_ULP_CLASS_HID_SHFTL 31 -#define BNXT_ULP_CLASS_HID_MASK 2047 -#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 4096 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 83 +#define BNXT_ULP_GEN_TBL_MAX_SZ 6 +#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 41 +#define BNXT_ULP_CLASS_HID_LOW_PRIME 3793 +#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919 +#define BNXT_ULP_CLASS_HID_SHFTR 24 +#define BNXT_ULP_CLASS_HID_SHFTL 23 +#define BNXT_ULP_CLASS_HID_MASK 255 +#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 15 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 -#define BNXT_ULP_ACT_HID_HIGH_PRIME 4721 -#define BNXT_ULP_ACT_HID_SHFTR 23 +#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919 +#define BNXT_ULP_ACT_HID_SHFTR 24 #define BNXT_ULP_ACT_HID_SHFTL 23 -#define BNXT_ULP_ACT_HID_MASK 4095 +#define BNXT_ULP_ACT_HID_MASK 2047 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 +#define BNXT_ULP_HDR_SIG_ID_SHIFT 4 +#define BNXT_ULP_GLB_FIELD_TBL_SIZE 4441 +#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 273 +#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 14 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 385 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 10 +#define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 8 +#define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 41 +#define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 273 +#define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 14 +#define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 385 +#define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10 +#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 2 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 4 +#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 0 +#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 0 +#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 65 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 2 +#define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2 +#define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4 +#define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0 +#define ULP_STINGRAY_ACT_IDENT_LIST_SIZE 0 +#define ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE 65 +#define ULP_STINGRAY_ACT_COND_LIST_SIZE 2 enum bnxt_ulp_action_bit { BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001, @@ -82,6 +108,12 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_LAST = 0x0000000000020000 }; +enum bnxt_ulp_accept_opc { + BNXT_ULP_ACCEPT_OPC_ALWAYS = 0, + BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH = 1, + BNXT_ULP_ACCEPT_OPC_LAST = 2 +}; + enum bnxt_ulp_act_type { BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0, BNXT_ULP_ACT_TYPE_SUPPORTED = 1, @@ -139,10 +171,12 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_L3_HDR_CNT = 40, BNXT_ULP_CF_IDX_L4_HDR_CNT = 41, BNXT_ULP_CF_IDX_VFR_MODE = 42, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF = 43, - BNXT_ULP_CF_IDX_L3_TUN = 44, - BNXT_ULP_CF_IDX_L3_TUN_DECAP = 45, - BNXT_ULP_CF_IDX_LAST = 46 + BNXT_ULP_CF_IDX_L3_TUN = 43, + BNXT_ULP_CF_IDX_L3_TUN_DECAP = 44, + BNXT_ULP_CF_IDX_FID = 45, + BNXT_ULP_CF_IDX_HDR_SIG_ID = 46, + BNXT_ULP_CF_IDX_FLOW_SIG_ID = 47, + BNXT_ULP_CF_IDX_LAST = 48 }; enum bnxt_ulp_cond_list_opc { @@ -200,6 +234,35 @@ enum bnxt_ulp_fdb_opc { BNXT_ULP_FDB_OPC_LAST = 4 }; +enum bnxt_ulp_fdb_type { + BNXT_ULP_FDB_TYPE_REGULAR = 0, + BNXT_ULP_FDB_TYPE_DEFAULT = 1, + BNXT_ULP_FDB_TYPE_RID = 2, + BNXT_ULP_FDB_TYPE_LAST = 3 +}; + +enum bnxt_ulp_field_opc { + BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT = 0, + BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD = 1, + BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD = 2, + BNXT_ULP_FIELD_OPC_SET_TO_REGFILE = 3, + BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE = 4, + BNXT_ULP_FIELD_OPC_SET_TO_ZERO = 5, + BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT = 6, + BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP = 7, + BNXT_ULP_FIELD_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8, + BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9, + BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10, + BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11, + BNXT_ULP_FIELD_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12, + BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_ACT_PROP_ELSE_CONST = 13, + BNXT_ULP_FIELD_OPC_IF_NOT_COMP_FIELD_THEN_ACT_PROP_ELSE_CONST = 14, + BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CONST_ELSE_CF = 15, + BNXT_ULP_FIELD_OPC_IF_NOT_COMP_FIELD_THEN_CONST_ELSE_CF = 16, + BNXT_ULP_FIELD_OPC_IF_FIELD_BIT_THEN_ONES_ELSE_ZERO = 17, + BNXT_ULP_FIELD_OPC_LAST = 18 +}; + enum bnxt_ulp_generic_tbl_opc { BNXT_ULP_GENERIC_TBL_OPC_NOT_USED = 0, BNXT_ULP_GENERIC_TBL_OPC_READ = 1, @@ -207,14 +270,14 @@ enum bnxt_ulp_generic_tbl_opc { BNXT_ULP_GENERIC_TBL_OPC_LAST = 3 }; -enum bnxt_ulp_glb_regfile_index { - BNXT_ULP_GLB_REGFILE_INDEX_NOT_USED = 0, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 1, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR = 2, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID = 3, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID = 4, - BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR = 5, - BNXT_ULP_GLB_REGFILE_INDEX_LAST = 6 +enum bnxt_ulp_glb_rf_idx { + BNXT_ULP_GLB_RF_IDX_NOT_USED = 0, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID = 1, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR = 2, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 3, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5, + BNXT_ULP_GLB_RF_IDX_LAST = 6 }; enum bnxt_ulp_hdr_type { @@ -244,23 +307,6 @@ enum bnxt_ulp_index_tbl_opc { BNXT_ULP_INDEX_TBL_OPC_LAST = 7 }; -enum bnxt_ulp_mapper_opc { - BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT = 0, - BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD = 1, - BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD = 2, - BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE = 3, - BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE = 4, - BNXT_ULP_MAPPER_OPC_SET_TO_ZERO = 5, - BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT = 6, - BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP = 7, - BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8, - BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9, - BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10, - BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11, - BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12, - BNXT_ULP_MAPPER_OPC_LAST = 13 -}; - enum bnxt_ulp_mark_db_opc { BNXT_ULP_MARK_DB_OPC_NOP = 0, BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION = 1, @@ -288,38 +334,39 @@ enum bnxt_ulp_pri_opc { BNXT_ULP_PRI_OPC_LAST = 3 }; -enum bnxt_ulp_regfile_index { - BNXT_ULP_REGFILE_INDEX_NOT_USED = 0, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2, - BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3, - BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9, - BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12, - BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 14, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR = 15, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 = 16, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 = 17, - BNXT_ULP_REGFILE_INDEX_ACTION_REC_SIZE = 18, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0 = 19, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_1 = 20, - BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0 = 21, - BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_1 = 22, - BNXT_ULP_REGFILE_INDEX_WC_TCAM_INDEX_0 = 23, - BNXT_ULP_REGFILE_INDEX_WC_TCAM_INDEX_1 = 24, - BNXT_ULP_REGFILE_INDEX_SRC_PROPERTY_PTR = 25, - BNXT_ULP_REGFILE_INDEX_GENERIC_TBL_HIT = 26, - BNXT_ULP_REGFILE_INDEX_MIRROR_PTR_0 = 27, - BNXT_ULP_REGFILE_INDEX_CLASS_TID = 28, - BNXT_ULP_REGFILE_INDEX_FID = 29, - BNXT_ULP_REGFILE_INDEX_LAST = 30 +enum bnxt_ulp_rf_idx { + BNXT_ULP_RF_IDX_NOT_USED = 0, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 = 1, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_1 = 2, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 = 3, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_1 = 4, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 = 5, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_1 = 6, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 = 7, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_1 = 8, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR = 9, + BNXT_ULP_RF_IDX_ACTION_PTR_0 = 10, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 = 11, + BNXT_ULP_RF_IDX_ENCAP_PTR_1 = 12, + BNXT_ULP_RF_IDX_CRITICAL_RESOURCE = 13, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 = 14, + BNXT_ULP_RF_IDX_MAIN_SP_PTR = 15, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 = 16, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 = 17, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE = 18, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 = 19, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_1 = 20, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 = 21, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_1 = 22, + BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0 = 23, + BNXT_ULP_RF_IDX_WC_TCAM_INDEX_1 = 24, + BNXT_ULP_RF_IDX_SRC_PROPERTY_PTR = 25, + BNXT_ULP_RF_IDX_GENERIC_TBL_HIT = 26, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 = 27, + BNXT_ULP_RF_IDX_HDR_SIG_ID = 28, + BNXT_ULP_RF_IDX_FLOW_SIG_ID = 29, + BNXT_ULP_RF_IDX_RID = 30, + BNXT_ULP_RF_IDX_LAST = 31 }; enum bnxt_ulp_tcam_tbl_opc { @@ -340,11 +387,6 @@ enum bnxt_ulp_fdb_resource_flags { BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01 }; -enum bnxt_ulp_fdb_type { - BNXT_ULP_FDB_TYPE_REGULAR = 0, - BNXT_ULP_FDB_TYPE_DEFAULT = 1 -}; - enum bnxt_ulp_flow_dir_bitmask { BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000, BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000 @@ -352,7 +394,7 @@ enum bnxt_ulp_flow_dir_bitmask { enum bnxt_ulp_match_type_bitmask { BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000, - BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001 + BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x8000000000000000 }; enum bnxt_ulp_resource_func { @@ -366,9 +408,8 @@ enum bnxt_ulp_resource_func { BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83, BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84, BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85, - BNXT_ULP_RESOURCE_FUNC_SHARED_TABLE = 0x86, - BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x87, - BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x88 + BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86, + BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87 }; enum bnxt_ulp_resource_sub_type { @@ -383,232 +424,6 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL = 2 }; -enum bnxt_ulp_sym { - BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0, - BNXT_ULP_SYM_PKT_TYPE_L2 = 0, - BNXT_ULP_SYM_PKT_TYPE_0_IGNORE = 0, - BNXT_ULP_SYM_PKT_TYPE_0_L2 = 0, - BNXT_ULP_SYM_PKT_TYPE_1_IGNORE = 0, - BNXT_ULP_SYM_PKT_TYPE_1_L2 = 0, - BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0, - BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0, - BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1, - BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2, - BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3, - BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0, - BNXT_ULP_SYM_AGG_ERROR_NO = 0, - BNXT_ULP_SYM_AGG_ERROR_YES = 1, - BNXT_ULP_SYM_RESERVED_IGNORE = 0, - BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0, - BNXT_ULP_SYM_HREC_NEXT_NO = 0, - BNXT_ULP_SYM_HREC_NEXT_YES = 1, - BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0, - BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1, - BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0, - BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0, - BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0, - BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2, - BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3, - BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0, - BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0, - BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1, - BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0, - BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0, - BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1, - BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0, - BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1, - BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0, - BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1, - BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0, - BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0, - BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1, - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0, - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1, - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0, - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1, - BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0, - BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1, - BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, - BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0, - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1, - BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0, - BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1, - BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0, - BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1, - BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2, - BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3, - BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4, - BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5, - BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6, - BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7, - BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8, - BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9, - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15, - BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0, - BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_L2_HDR_VALID_NO = 0, - BNXT_ULP_SYM_L2_HDR_VALID_YES = 1, - BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0, - BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1, - BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2, - BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0, - BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0, - BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2, - BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3, - BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0, - BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0, - BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1, - BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0, - BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0, - BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1, - BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_L3_HDR_VALID_NO = 0, - BNXT_ULP_SYM_L3_HDR_VALID_YES = 1, - BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0, - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1, - BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2, - BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3, - BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4, - BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5, - BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6, - BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7, - BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8, - BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0, - BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0, - BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1, - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0, - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1, - BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0, - BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0, - BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1, - BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_L4_HDR_VALID_NO = 0, - BNXT_ULP_SYM_L4_HDR_VALID_YES = 1, - BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0, - BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1, - BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2, - BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3, - BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4, - BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5, - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0, - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1, - BNXT_ULP_SYM_POP_VLAN_NO = 0, - BNXT_ULP_SYM_POP_VLAN_YES = 1, - BNXT_ULP_SYM_DECAP_FUNC_NONE = 0, - BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3, - BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8, - BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9, - BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10, - BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11, - BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12, - BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13, - BNXT_ULP_SYM_ECV_VALID_NO = 0, - BNXT_ULP_SYM_ECV_VALID_YES = 1, - BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0, - BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1, - BNXT_ULP_SYM_ECV_L2_EN_NO = 0, - BNXT_ULP_SYM_ECV_L2_EN_YES = 1, - BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, - BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0, - BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4, - BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5, - BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6, - BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7, - BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0, - BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4, - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5, - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, - BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0, - BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1, - BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2, - BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3, - BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4, - BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5, - BNXT_ULP_SYM_WH_PLUS_INT_ACT_REC = 1, - BNXT_ULP_SYM_WH_PLUS_EXT_ACT_REC = 0, - BNXT_ULP_SYM_WH_PLUS_UC_ACT_REC = 0, - BNXT_ULP_SYM_WH_PLUS_MC_ACT_REC = 1, - BNXT_ULP_SYM_ACT_REC_DROP_YES = 1, - BNXT_ULP_SYM_ACT_REC_DROP_NO = 0, - BNXT_ULP_SYM_ACT_REC_POP_VLAN_YES = 1, - BNXT_ULP_SYM_ACT_REC_POP_VLAN_NO = 0, - BNXT_ULP_SYM_ACT_REC_METER_EN_YES = 1, - BNXT_ULP_SYM_ACT_REC_METER_EN_NO = 0, - BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 4, - BNXT_ULP_SYM_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448, - BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 16, - BNXT_ULP_SYM_STINGRAY_EXT_EM_MAX_KEY_SIZE = 448, - BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3, - BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3, - BNXT_ULP_SYM_MATCH_TYPE_EM = 0, - BNXT_ULP_SYM_MATCH_TYPE_WM = 1, - BNXT_ULP_SYM_IP_PROTO_ICMP = 1, - BNXT_ULP_SYM_IP_PROTO_IGMP = 2, - BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4, - BNXT_ULP_SYM_IP_PROTO_TCP = 6, - BNXT_ULP_SYM_IP_PROTO_UDP = 17, - BNXT_ULP_SYM_VF_FUNC_PARIF = 15, - BNXT_ULP_SYM_NO = 0, - BNXT_ULP_SYM_YES = 1, - BNXT_ULP_SYM_RECYCLE_DST = 0x800 -}; - -enum bnxt_ulp_wh_plus { - BNXT_ULP_WH_PLUS_LOOPBACK_PORT = 4, - BNXT_ULP_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448 -}; - enum bnxt_ulp_act_prop_sz { BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4, BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4, @@ -651,6 +466,7 @@ enum bnxt_ulp_act_prop_sz { BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4, BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32, BNXT_ULP_ACT_PROP_SZ_JUMP = 4, + BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE = 8, BNXT_ULP_ACT_PROP_SZ_LAST = 4 }; @@ -696,319 +512,512 @@ enum bnxt_ulp_act_prop_idx { BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221, BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225, BNXT_ULP_ACT_PROP_IDX_JUMP = 257, - BNXT_ULP_ACT_PROP_IDX_LAST = 261 + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 261, + BNXT_ULP_ACT_PROP_IDX_LAST = 269 +}; + +enum bnxt_ulp_wh_plus_sym { + BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_L2 = 0, + BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_0_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_0_L2 = 0, + BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_1_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_1_L2 = 0, + BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_ZERO = 0, + BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_ONE = 1, + BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_TWO = 2, + BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_THREE = 3, + BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_NO = 0, + BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_YES = 1, + BNXT_ULP_WH_PLUS_SYM_RESERVED_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_NO = 0, + BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL2_HDR_TYPE_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_HDR_TYPE_DIX = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_UC = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_MC = 2, + BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_BC = 3, + BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IPV4 = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IPV6 = 1, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_TCP = 0, + BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_UDP = 1, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_NO = 0, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_YES = 1, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_VXLAN = 0, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_GENEVE = 1, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NVGRE = 2, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_GRE = 3, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IPV4 = 4, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IPV6 = 5, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_PPPOE = 6, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_MPLS = 7, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_UPAR1 = 8, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_UPAR2 = 9, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE = 15, + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_FLAGS_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_DIX = 0, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_LLC_SNAP = 1, + BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_LLC = 2, + BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_UC = 0, + BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_MC = 2, + BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_BC = 3, + BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IPV4 = 0, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IPV6 = 1, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_ARP = 2, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_PTP = 3, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_EAPOL = 4, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_ROCE = 5, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_FCOE = 6, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_UPAR1 = 7, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_UPAR2 = 8, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_YES = 1, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_TCP = 0, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UDP = 1, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_ICMP = 2, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UPAR1 = 3, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UPAR2 = 4, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_BTH_V1 = 5, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_NO = 0, + BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_YES = 1, + BNXT_ULP_WH_PLUS_SYM_POP_VLAN_NO = 0, + BNXT_ULP_WH_PLUS_SYM_POP_VLAN_YES = 1, + BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_NONE = 0, + BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL2 = 3, + BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL3 = 8, + BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL4 = 9, + BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TUN = 10, + BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L2 = 11, + BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L3 = 12, + BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L4 = 13, + BNXT_ULP_WH_PLUS_SYM_ECV_VALID_NO = 0, + BNXT_ULP_WH_PLUS_SYM_ECV_VALID_YES = 1, + BNXT_ULP_WH_PLUS_SYM_ECV_CUSTOM_EN_NO = 0, + BNXT_ULP_WH_PLUS_SYM_ECV_CUSTOM_EN_YES = 1, + BNXT_ULP_WH_PLUS_SYM_ECV_L2_EN_NO = 0, + BNXT_ULP_WH_PLUS_SYM_ECV_L2_EN_YES = 1, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_NOP = 0, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, + BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_NONE = 0, + BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_IPV4 = 4, + BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_IPV6 = 5, + BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_MPLS_8847 = 6, + BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_MPLS_8848 = 7, + BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_NONE = 0, + BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP = 4, + BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_CSUM = 5, + BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, + BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, + BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NONE = 0, + BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_GENERIC = 1, + BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_VXLAN = 2, + BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NGE = 3, + BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NVGRE = 4, + BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_GRE = 5, + BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT = 1, + BNXT_ULP_WH_PLUS_SYM_EEM_EXT_FLOW_CNTR = 0, + BNXT_ULP_WH_PLUS_SYM_UC_ACT_REC = 0, + BNXT_ULP_WH_PLUS_SYM_MC_ACT_REC = 1, + BNXT_ULP_WH_PLUS_SYM_ACT_REC_DROP_YES = 1, + BNXT_ULP_WH_PLUS_SYM_ACT_REC_DROP_NO = 0, + BNXT_ULP_WH_PLUS_SYM_ACT_REC_POP_VLAN_YES = 1, + BNXT_ULP_WH_PLUS_SYM_ACT_REC_POP_VLAN_NO = 0, + BNXT_ULP_WH_PLUS_SYM_ACT_REC_METER_EN_YES = 1, + BNXT_ULP_WH_PLUS_SYM_ACT_REC_METER_EN_NO = 0, + BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT = 4, + BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PARIF = 15, + BNXT_ULP_WH_PLUS_SYM_EXT_EM_MAX_KEY_SIZE = 448, + BNXT_ULP_WH_PLUS_SYM_MATCH_TYPE_EM = 0, + BNXT_ULP_WH_PLUS_SYM_MATCH_TYPE_WM = 1, + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_ICMP = 1, + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_IGMP = 2, + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_IP_IN_IP = 4, + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP = 6, + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_UDP = 17, + BNXT_ULP_WH_PLUS_SYM_VF_FUNC_PARIF = 15, + BNXT_ULP_WH_PLUS_SYM_NO = 0, + BNXT_ULP_WH_PLUS_SYM_YES = 1, + BNXT_ULP_WH_PLUS_SYM_RECYCLE_DST = 0x800 +}; + +enum bnxt_ulp_stingray_sym { + BNXT_ULP_STINGRAY_SYM_PKT_TYPE_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_PKT_TYPE_L2 = 0, + BNXT_ULP_STINGRAY_SYM_PKT_TYPE_0_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_PKT_TYPE_0_L2 = 0, + BNXT_ULP_STINGRAY_SYM_PKT_TYPE_1_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_PKT_TYPE_1_L2 = 0, + BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_ZERO = 0, + BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_ONE = 1, + BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_TWO = 2, + BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_THREE = 3, + BNXT_ULP_STINGRAY_SYM_AGG_ERROR_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_AGG_ERROR_NO = 0, + BNXT_ULP_STINGRAY_SYM_AGG_ERROR_YES = 1, + BNXT_ULP_STINGRAY_SYM_RESERVED_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_HREC_NEXT_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_HREC_NEXT_NO = 0, + BNXT_ULP_STINGRAY_SYM_HREC_NEXT_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL2_HDR_TYPE_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL2_HDR_TYPE_DIX = 0, + BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_UC = 0, + BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_MC = 2, + BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_BC = 3, + BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IPV4 = 0, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IPV6 = 1, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_TCP = 0, + BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_UDP = 1, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_NO = 0, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_YES = 1, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_NO = 0, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_YES = 1, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_VXLAN = 0, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_GENEVE = 1, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NVGRE = 2, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_GRE = 3, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IPV4 = 4, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IPV6 = 5, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_PPPOE = 6, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_MPLS = 7, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_UPAR1 = 8, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_UPAR2 = 9, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE = 15, + BNXT_ULP_STINGRAY_SYM_TUN_HDR_FLAGS_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_NO = 0, + BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES = 1, + BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_NO = 0, + BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_YES = 1, + BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_DIX = 0, + BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_LLC_SNAP = 1, + BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_LLC = 2, + BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_UC = 0, + BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_MC = 2, + BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_BC = 3, + BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_NO = 0, + BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_YES = 1, + BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_NO = 0, + BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_YES = 1, + BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_NO = 0, + BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES = 1, + BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_NO = 0, + BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_YES = 1, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IPV4 = 0, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IPV6 = 1, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_ARP = 2, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_PTP = 3, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_EAPOL = 4, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_ROCE = 5, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_FCOE = 6, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_UPAR1 = 7, + BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_UPAR2 = 8, + BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_NO = 0, + BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_YES = 1, + BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_NO = 0, + BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_YES = 1, + BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_NO = 0, + BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_YES = 1, + BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_NO = 0, + BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES = 1, + BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_NO = 0, + BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_YES = 1, + BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_TCP = 0, + BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UDP = 1, + BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_ICMP = 2, + BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UPAR1 = 3, + BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UPAR2 = 4, + BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_BTH_V1 = 5, + BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, + BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_NO = 0, + BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_YES = 1, + BNXT_ULP_STINGRAY_SYM_POP_VLAN_NO = 0, + BNXT_ULP_STINGRAY_SYM_POP_VLAN_YES = 1, + BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_NONE = 0, + BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL2 = 3, + BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL3 = 8, + BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL4 = 9, + BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TUN = 10, + BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L2 = 11, + BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L3 = 12, + BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L4 = 13, + BNXT_ULP_STINGRAY_SYM_ECV_VALID_NO = 0, + BNXT_ULP_STINGRAY_SYM_ECV_VALID_YES = 1, + BNXT_ULP_STINGRAY_SYM_ECV_CUSTOM_EN_NO = 0, + BNXT_ULP_STINGRAY_SYM_ECV_CUSTOM_EN_YES = 1, + BNXT_ULP_STINGRAY_SYM_ECV_L2_EN_NO = 0, + BNXT_ULP_STINGRAY_SYM_ECV_L2_EN_YES = 1, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_NOP = 0, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, + BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_NONE = 0, + BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_IPV4 = 4, + BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_IPV6 = 5, + BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_MPLS_8847 = 6, + BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_MPLS_8848 = 7, + BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_NONE = 0, + BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP = 4, + BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_CSUM = 5, + BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, + BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, + BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NONE = 0, + BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_GENERIC = 1, + BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_VXLAN = 2, + BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NGE = 3, + BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NVGRE = 4, + BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_GRE = 5, + BNXT_ULP_STINGRAY_SYM_EEM_ACT_REC_INT = 0, + BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR = 1, + BNXT_ULP_STINGRAY_SYM_UC_ACT_REC = 0, + BNXT_ULP_STINGRAY_SYM_MC_ACT_REC = 1, + BNXT_ULP_STINGRAY_SYM_ACT_REC_DROP_YES = 1, + BNXT_ULP_STINGRAY_SYM_ACT_REC_DROP_NO = 0, + BNXT_ULP_STINGRAY_SYM_ACT_REC_POP_VLAN_YES = 1, + BNXT_ULP_STINGRAY_SYM_ACT_REC_POP_VLAN_NO = 0, + BNXT_ULP_STINGRAY_SYM_ACT_REC_METER_EN_YES = 1, + BNXT_ULP_STINGRAY_SYM_ACT_REC_METER_EN_NO = 0, + BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT = 16, + BNXT_ULP_STINGRAY_SYM_LOOPBACK_PARIF = 15, + BNXT_ULP_STINGRAY_SYM_EXT_EM_MAX_KEY_SIZE = 448, + BNXT_ULP_STINGRAY_SYM_MATCH_TYPE_EM = 0, + BNXT_ULP_STINGRAY_SYM_MATCH_TYPE_WM = 1, + BNXT_ULP_STINGRAY_SYM_IP_PROTO_ICMP = 1, + BNXT_ULP_STINGRAY_SYM_IP_PROTO_IGMP = 2, + BNXT_ULP_STINGRAY_SYM_IP_PROTO_IP_IN_IP = 4, + BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP = 6, + BNXT_ULP_STINGRAY_SYM_IP_PROTO_UDP = 17, + BNXT_ULP_STINGRAY_SYM_VF_FUNC_PARIF = 15, + BNXT_ULP_STINGRAY_SYM_NO = 0, + BNXT_ULP_STINGRAY_SYM_YES = 1, + BNXT_ULP_STINGRAY_SYM_RECYCLE_DST = 0x800 }; enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_0138 = 0x0138, - BNXT_ULP_CLASS_HID_03f0 = 0x03f0, - BNXT_ULP_CLASS_HID_0139 = 0x0139, - BNXT_ULP_CLASS_HID_03f1 = 0x03f1, - BNXT_ULP_CLASS_HID_068b = 0x068b, - BNXT_ULP_CLASS_HID_0143 = 0x0143, - BNXT_ULP_CLASS_HID_0118 = 0x0118, - BNXT_ULP_CLASS_HID_03d0 = 0x03d0, - BNXT_ULP_CLASS_HID_0119 = 0x0119, - BNXT_ULP_CLASS_HID_03d1 = 0x03d1, - BNXT_ULP_CLASS_HID_06ab = 0x06ab, - BNXT_ULP_CLASS_HID_0163 = 0x0163, - BNXT_ULP_CLASS_HID_0128 = 0x0128, - BNXT_ULP_CLASS_HID_03e0 = 0x03e0, - BNXT_ULP_CLASS_HID_0129 = 0x0129, - BNXT_ULP_CLASS_HID_03e1 = 0x03e1, - BNXT_ULP_CLASS_HID_069b = 0x069b, - BNXT_ULP_CLASS_HID_0153 = 0x0153, - BNXT_ULP_CLASS_HID_0134 = 0x0134, - BNXT_ULP_CLASS_HID_03fc = 0x03fc, - BNXT_ULP_CLASS_HID_0135 = 0x0135, - BNXT_ULP_CLASS_HID_03fd = 0x03fd, - BNXT_ULP_CLASS_HID_0687 = 0x0687, - BNXT_ULP_CLASS_HID_014f = 0x014f, - BNXT_ULP_CLASS_HID_0114 = 0x0114, - BNXT_ULP_CLASS_HID_03dc = 0x03dc, - BNXT_ULP_CLASS_HID_0115 = 0x0115, - BNXT_ULP_CLASS_HID_03dd = 0x03dd, - BNXT_ULP_CLASS_HID_06a7 = 0x06a7, - BNXT_ULP_CLASS_HID_016f = 0x016f, - BNXT_ULP_CLASS_HID_0124 = 0x0124, - BNXT_ULP_CLASS_HID_03ec = 0x03ec, - BNXT_ULP_CLASS_HID_0125 = 0x0125, - BNXT_ULP_CLASS_HID_03ed = 0x03ed, - BNXT_ULP_CLASS_HID_0697 = 0x0697, - BNXT_ULP_CLASS_HID_015f = 0x015f, - BNXT_ULP_CLASS_HID_0452 = 0x0452, - BNXT_ULP_CLASS_HID_0528 = 0x0528, - BNXT_ULP_CLASS_HID_0790 = 0x0790, - BNXT_ULP_CLASS_HID_046e = 0x046e, - BNXT_ULP_CLASS_HID_0462 = 0x0462, - BNXT_ULP_CLASS_HID_0518 = 0x0518, - BNXT_ULP_CLASS_HID_07a0 = 0x07a0, - BNXT_ULP_CLASS_HID_045e = 0x045e, - BNXT_ULP_CLASS_HID_0228 = 0x0228, - BNXT_ULP_CLASS_HID_06d0 = 0x06d0, - BNXT_ULP_CLASS_HID_02be = 0x02be, - BNXT_ULP_CLASS_HID_07a6 = 0x07a6, - BNXT_ULP_CLASS_HID_0218 = 0x0218, - BNXT_ULP_CLASS_HID_06e0 = 0x06e0, - BNXT_ULP_CLASS_HID_028e = 0x028e, - BNXT_ULP_CLASS_HID_0796 = 0x0796, - BNXT_ULP_CLASS_HID_079c = 0x079c, - BNXT_ULP_CLASS_HID_0654 = 0x0654, - BNXT_ULP_CLASS_HID_06d2 = 0x06d2, - BNXT_ULP_CLASS_HID_058a = 0x058a, - BNXT_ULP_CLASS_HID_052f = 0x052f, - BNXT_ULP_CLASS_HID_07e7 = 0x07e7, - BNXT_ULP_CLASS_HID_079d = 0x079d, - BNXT_ULP_CLASS_HID_0655 = 0x0655, - BNXT_ULP_CLASS_HID_046d = 0x046d, - BNXT_ULP_CLASS_HID_0725 = 0x0725, - BNXT_ULP_CLASS_HID_06d3 = 0x06d3, - BNXT_ULP_CLASS_HID_058b = 0x058b, - BNXT_ULP_CLASS_HID_07ac = 0x07ac, - BNXT_ULP_CLASS_HID_0664 = 0x0664, - BNXT_ULP_CLASS_HID_06e2 = 0x06e2, - BNXT_ULP_CLASS_HID_05ba = 0x05ba, - BNXT_ULP_CLASS_HID_051f = 0x051f, - BNXT_ULP_CLASS_HID_07d7 = 0x07d7, - BNXT_ULP_CLASS_HID_07ad = 0x07ad, - BNXT_ULP_CLASS_HID_0665 = 0x0665, - BNXT_ULP_CLASS_HID_045d = 0x045d, - BNXT_ULP_CLASS_HID_0715 = 0x0715, - BNXT_ULP_CLASS_HID_06e3 = 0x06e3, - BNXT_ULP_CLASS_HID_05bb = 0x05bb, - BNXT_ULP_CLASS_HID_016a = 0x016a, - BNXT_ULP_CLASS_HID_03d2 = 0x03d2, - BNXT_ULP_CLASS_HID_0612 = 0x0612, - BNXT_ULP_CLASS_HID_00da = 0x00da, - BNXT_ULP_CLASS_HID_06bd = 0x06bd, - BNXT_ULP_CLASS_HID_0165 = 0x0165, - BNXT_ULP_CLASS_HID_016b = 0x016b, - BNXT_ULP_CLASS_HID_03d3 = 0x03d3, - BNXT_ULP_CLASS_HID_03a5 = 0x03a5, - BNXT_ULP_CLASS_HID_066d = 0x066d, - BNXT_ULP_CLASS_HID_0613 = 0x0613, - BNXT_ULP_CLASS_HID_00db = 0x00db, - BNXT_ULP_CLASS_HID_015a = 0x015a, - BNXT_ULP_CLASS_HID_03e2 = 0x03e2, - BNXT_ULP_CLASS_HID_0622 = 0x0622, - BNXT_ULP_CLASS_HID_00ea = 0x00ea, - BNXT_ULP_CLASS_HID_068d = 0x068d, - BNXT_ULP_CLASS_HID_0155 = 0x0155, - BNXT_ULP_CLASS_HID_015b = 0x015b, - BNXT_ULP_CLASS_HID_03e3 = 0x03e3, - BNXT_ULP_CLASS_HID_0395 = 0x0395, - BNXT_ULP_CLASS_HID_065d = 0x065d, - BNXT_ULP_CLASS_HID_0623 = 0x0623, - BNXT_ULP_CLASS_HID_00eb = 0x00eb, - BNXT_ULP_CLASS_HID_04bc = 0x04bc, - BNXT_ULP_CLASS_HID_0442 = 0x0442, - BNXT_ULP_CLASS_HID_050a = 0x050a, - BNXT_ULP_CLASS_HID_06ba = 0x06ba, - BNXT_ULP_CLASS_HID_0472 = 0x0472, - BNXT_ULP_CLASS_HID_0700 = 0x0700, - BNXT_ULP_CLASS_HID_04c8 = 0x04c8, - BNXT_ULP_CLASS_HID_0678 = 0x0678, - BNXT_ULP_CLASS_HID_061f = 0x061f, - BNXT_ULP_CLASS_HID_05ad = 0x05ad, - BNXT_ULP_CLASS_HID_06a5 = 0x06a5, - BNXT_ULP_CLASS_HID_0455 = 0x0455, - BNXT_ULP_CLASS_HID_05dd = 0x05dd, - BNXT_ULP_CLASS_HID_0563 = 0x0563, - BNXT_ULP_CLASS_HID_059b = 0x059b, - BNXT_ULP_CLASS_HID_070b = 0x070b, - BNXT_ULP_CLASS_HID_04bd = 0x04bd, - BNXT_ULP_CLASS_HID_0443 = 0x0443, - BNXT_ULP_CLASS_HID_050b = 0x050b, - BNXT_ULP_CLASS_HID_06bb = 0x06bb, - BNXT_ULP_CLASS_HID_0473 = 0x0473, - BNXT_ULP_CLASS_HID_0701 = 0x0701, - BNXT_ULP_CLASS_HID_04c9 = 0x04c9, - BNXT_ULP_CLASS_HID_0679 = 0x0679, - BNXT_ULP_CLASS_HID_05e2 = 0x05e2, - BNXT_ULP_CLASS_HID_00b0 = 0x00b0, - BNXT_ULP_CLASS_HID_0648 = 0x0648, - BNXT_ULP_CLASS_HID_03f8 = 0x03f8, - BNXT_ULP_CLASS_HID_02ea = 0x02ea, - BNXT_ULP_CLASS_HID_05b8 = 0x05b8, - BNXT_ULP_CLASS_HID_0370 = 0x0370, - BNXT_ULP_CLASS_HID_00e0 = 0x00e0, - BNXT_ULP_CLASS_HID_0745 = 0x0745, - BNXT_ULP_CLASS_HID_0213 = 0x0213, - BNXT_ULP_CLASS_HID_031b = 0x031b, - BNXT_ULP_CLASS_HID_008b = 0x008b, - BNXT_ULP_CLASS_HID_044d = 0x044d, - BNXT_ULP_CLASS_HID_071b = 0x071b, - BNXT_ULP_CLASS_HID_0003 = 0x0003, - BNXT_ULP_CLASS_HID_05b3 = 0x05b3, - BNXT_ULP_CLASS_HID_05e3 = 0x05e3, - BNXT_ULP_CLASS_HID_00b1 = 0x00b1, - BNXT_ULP_CLASS_HID_0649 = 0x0649, - BNXT_ULP_CLASS_HID_03f9 = 0x03f9, - BNXT_ULP_CLASS_HID_02eb = 0x02eb, - BNXT_ULP_CLASS_HID_05b9 = 0x05b9, - BNXT_ULP_CLASS_HID_0371 = 0x0371, + BNXT_ULP_CLASS_HID_00fc = 0x00fc, + BNXT_ULP_CLASS_HID_0046 = 0x0046, + BNXT_ULP_CLASS_HID_0056 = 0x0056, + BNXT_ULP_CLASS_HID_00b8 = 0x00b8, + BNXT_ULP_CLASS_HID_0041 = 0x0041, + BNXT_ULP_CLASS_HID_00ab = 0x00ab, + BNXT_ULP_CLASS_HID_0053 = 0x0053, + BNXT_ULP_CLASS_HID_00a5 = 0x00a5, + BNXT_ULP_CLASS_HID_0069 = 0x0069, + BNXT_ULP_CLASS_HID_009d = 0x009d, + BNXT_ULP_CLASS_HID_0005 = 0x0005, + BNXT_ULP_CLASS_HID_006f = 0x006f, + BNXT_ULP_CLASS_HID_00af = 0x00af, + BNXT_ULP_CLASS_HID_00d3 = 0x00d3, + BNXT_ULP_CLASS_HID_005b = 0x005b, + BNXT_ULP_CLASS_HID_00ad = 0x00ad, + BNXT_ULP_CLASS_HID_0091 = 0x0091, + BNXT_ULP_CLASS_HID_00fb = 0x00fb, + BNXT_ULP_CLASS_HID_0063 = 0x0063, + BNXT_ULP_CLASS_HID_0097 = 0x0097, + BNXT_ULP_CLASS_HID_00cc = 0x00cc, + BNXT_ULP_CLASS_HID_00f0 = 0x00f0, + BNXT_ULP_CLASS_HID_00c0 = 0x00c0, + BNXT_ULP_CLASS_HID_002a = 0x002a, + BNXT_ULP_CLASS_HID_00c7 = 0x00c7, + BNXT_ULP_CLASS_HID_0029 = 0x0029, + BNXT_ULP_CLASS_HID_00d1 = 0x00d1, + BNXT_ULP_CLASS_HID_003b = 0x003b, + BNXT_ULP_CLASS_HID_00ef = 0x00ef, + BNXT_ULP_CLASS_HID_0013 = 0x0013, + BNXT_ULP_CLASS_HID_009b = 0x009b, + BNXT_ULP_CLASS_HID_00ed = 0x00ed, + BNXT_ULP_CLASS_HID_002d = 0x002d, + BNXT_ULP_CLASS_HID_0051 = 0x0051, + BNXT_ULP_CLASS_HID_00d9 = 0x00d9, + BNXT_ULP_CLASS_HID_0023 = 0x0023, + BNXT_ULP_CLASS_HID_0017 = 0x0017, + BNXT_ULP_CLASS_HID_0079 = 0x0079, BNXT_ULP_CLASS_HID_00e1 = 0x00e1, - BNXT_ULP_CLASS_HID_0000 = 0x0000, - BNXT_ULP_CLASS_HID_00ce = 0x00ce, - BNXT_ULP_CLASS_HID_01b6 = 0x01b6, - BNXT_ULP_CLASS_HID_0074 = 0x0074, - BNXT_ULP_CLASS_HID_00fe = 0x00fe, - BNXT_ULP_CLASS_HID_03bc = 0x03bc, - BNXT_ULP_CLASS_HID_0206 = 0x0206, - BNXT_ULP_CLASS_HID_02c4 = 0x02c4, - BNXT_ULP_CLASS_HID_055a = 0x055a, - BNXT_ULP_CLASS_HID_045a = 0x045a, - BNXT_ULP_CLASS_HID_061a = 0x061a, - BNXT_ULP_CLASS_HID_051a = 0x051a, - BNXT_ULP_CLASS_HID_074a = 0x074a, - BNXT_ULP_CLASS_HID_004e = 0x004e, - BNXT_ULP_CLASS_HID_040a = 0x040a, - BNXT_ULP_CLASS_HID_010e = 0x010e, - BNXT_ULP_CLASS_HID_048b = 0x048b, - BNXT_ULP_CLASS_HID_0749 = 0x0749, - BNXT_ULP_CLASS_HID_05f1 = 0x05f1, - BNXT_ULP_CLASS_HID_04b7 = 0x04b7, - BNXT_ULP_CLASS_HID_049b = 0x049b, - BNXT_ULP_CLASS_HID_0759 = 0x0759, - BNXT_ULP_CLASS_HID_05e1 = 0x05e1, - BNXT_ULP_CLASS_HID_04a7 = 0x04a7, - BNXT_ULP_CLASS_HID_0301 = 0x0301, - BNXT_ULP_CLASS_HID_07f9 = 0x07f9, - BNXT_ULP_CLASS_HID_0397 = 0x0397, - BNXT_ULP_CLASS_HID_068f = 0x068f, - BNXT_ULP_CLASS_HID_02f1 = 0x02f1, - BNXT_ULP_CLASS_HID_0609 = 0x0609, - BNXT_ULP_CLASS_HID_0267 = 0x0267, - BNXT_ULP_CLASS_HID_077f = 0x077f, - BNXT_ULP_CLASS_HID_01e1 = 0x01e1, - BNXT_ULP_CLASS_HID_0329 = 0x0329, - BNXT_ULP_CLASS_HID_01c1 = 0x01c1, - BNXT_ULP_CLASS_HID_0309 = 0x0309, - BNXT_ULP_CLASS_HID_01d1 = 0x01d1, - BNXT_ULP_CLASS_HID_0319 = 0x0319, - BNXT_ULP_CLASS_HID_01e2 = 0x01e2, - BNXT_ULP_CLASS_HID_032a = 0x032a, - BNXT_ULP_CLASS_HID_0650 = 0x0650, - BNXT_ULP_CLASS_HID_0198 = 0x0198, - BNXT_ULP_CLASS_HID_01c2 = 0x01c2, - BNXT_ULP_CLASS_HID_030a = 0x030a, - BNXT_ULP_CLASS_HID_0670 = 0x0670, - BNXT_ULP_CLASS_HID_01b8 = 0x01b8, - BNXT_ULP_CLASS_HID_01d2 = 0x01d2, - BNXT_ULP_CLASS_HID_031a = 0x031a, - BNXT_ULP_CLASS_HID_0660 = 0x0660, - BNXT_ULP_CLASS_HID_01a8 = 0x01a8, - BNXT_ULP_CLASS_HID_01dd = 0x01dd, - BNXT_ULP_CLASS_HID_0315 = 0x0315, - BNXT_ULP_CLASS_HID_003d = 0x003d, - BNXT_ULP_CLASS_HID_02f5 = 0x02f5, - BNXT_ULP_CLASS_HID_01cd = 0x01cd, - BNXT_ULP_CLASS_HID_0305 = 0x0305, - BNXT_ULP_CLASS_HID_01de = 0x01de, - BNXT_ULP_CLASS_HID_0316 = 0x0316, - BNXT_ULP_CLASS_HID_066c = 0x066c, - BNXT_ULP_CLASS_HID_01a4 = 0x01a4, - BNXT_ULP_CLASS_HID_003e = 0x003e, - BNXT_ULP_CLASS_HID_02f6 = 0x02f6, - BNXT_ULP_CLASS_HID_078c = 0x078c, - BNXT_ULP_CLASS_HID_0044 = 0x0044, - BNXT_ULP_CLASS_HID_01ce = 0x01ce, - BNXT_ULP_CLASS_HID_0306 = 0x0306, - BNXT_ULP_CLASS_HID_067c = 0x067c, - BNXT_ULP_CLASS_HID_01b4 = 0x01b4 + BNXT_ULP_CLASS_HID_0015 = 0x0015 }; enum bnxt_ulp_act_hid { - BNXT_ULP_ACT_HID_015a = 0x015a, - BNXT_ULP_ACT_HID_00eb = 0x00eb, - BNXT_ULP_ACT_HID_0043 = 0x0043, - BNXT_ULP_ACT_HID_03d8 = 0x03d8, - BNXT_ULP_ACT_HID_02c1 = 0x02c1, - BNXT_ULP_ACT_HID_015e = 0x015e, - BNXT_ULP_ACT_HID_00ef = 0x00ef, - BNXT_ULP_ACT_HID_0047 = 0x0047, - BNXT_ULP_ACT_HID_03dc = 0x03dc, - BNXT_ULP_ACT_HID_02c5 = 0x02c5, - BNXT_ULP_ACT_HID_025b = 0x025b, - BNXT_ULP_ACT_HID_01ec = 0x01ec, - BNXT_ULP_ACT_HID_0144 = 0x0144, - BNXT_ULP_ACT_HID_04d9 = 0x04d9, - BNXT_ULP_ACT_HID_03c2 = 0x03c2, - BNXT_ULP_ACT_HID_025f = 0x025f, - BNXT_ULP_ACT_HID_01f0 = 0x01f0, - BNXT_ULP_ACT_HID_0148 = 0x0148, - BNXT_ULP_ACT_HID_04dd = 0x04dd, - BNXT_ULP_ACT_HID_03c6 = 0x03c6, BNXT_ULP_ACT_HID_0000 = 0x0000, - BNXT_ULP_ACT_HID_0002 = 0x0002, - BNXT_ULP_ACT_HID_0800 = 0x0800, - BNXT_ULP_ACT_HID_0101 = 0x0101, - BNXT_ULP_ACT_HID_0020 = 0x0020, - BNXT_ULP_ACT_HID_0901 = 0x0901, - BNXT_ULP_ACT_HID_0121 = 0x0121, - BNXT_ULP_ACT_HID_0004 = 0x0004, - BNXT_ULP_ACT_HID_0006 = 0x0006, - BNXT_ULP_ACT_HID_0804 = 0x0804, - BNXT_ULP_ACT_HID_0105 = 0x0105, - BNXT_ULP_ACT_HID_0024 = 0x0024, - BNXT_ULP_ACT_HID_0905 = 0x0905, - BNXT_ULP_ACT_HID_0125 = 0x0125, BNXT_ULP_ACT_HID_0001 = 0x0001, - BNXT_ULP_ACT_HID_0005 = 0x0005, - BNXT_ULP_ACT_HID_0009 = 0x0009, - BNXT_ULP_ACT_HID_000d = 0x000d, - BNXT_ULP_ACT_HID_0021 = 0x0021, - BNXT_ULP_ACT_HID_0029 = 0x0029, - BNXT_ULP_ACT_HID_0025 = 0x0025, - BNXT_ULP_ACT_HID_002d = 0x002d, - BNXT_ULP_ACT_HID_0801 = 0x0801, - BNXT_ULP_ACT_HID_0809 = 0x0809, - BNXT_ULP_ACT_HID_0805 = 0x0805, - BNXT_ULP_ACT_HID_080d = 0x080d, - BNXT_ULP_ACT_HID_0c15 = 0x0c15, - BNXT_ULP_ACT_HID_0c19 = 0x0c19, - BNXT_ULP_ACT_HID_02f6 = 0x02f6, - BNXT_ULP_ACT_HID_04f8 = 0x04f8, - BNXT_ULP_ACT_HID_01df = 0x01df, - BNXT_ULP_ACT_HID_07e5 = 0x07e5, - BNXT_ULP_ACT_HID_06ce = 0x06ce, - BNXT_ULP_ACT_HID_02fa = 0x02fa, - BNXT_ULP_ACT_HID_04fc = 0x04fc, - BNXT_ULP_ACT_HID_01e3 = 0x01e3, - BNXT_ULP_ACT_HID_07e9 = 0x07e9, - BNXT_ULP_ACT_HID_06d2 = 0x06d2, - BNXT_ULP_ACT_HID_03f7 = 0x03f7, - BNXT_ULP_ACT_HID_05f9 = 0x05f9, - BNXT_ULP_ACT_HID_02e0 = 0x02e0, - BNXT_ULP_ACT_HID_08e6 = 0x08e6, - BNXT_ULP_ACT_HID_07cf = 0x07cf, - BNXT_ULP_ACT_HID_03fb = 0x03fb, - BNXT_ULP_ACT_HID_05fd = 0x05fd, - BNXT_ULP_ACT_HID_02e4 = 0x02e4, - BNXT_ULP_ACT_HID_08ea = 0x08ea, - BNXT_ULP_ACT_HID_07d3 = 0x07d3, - BNXT_ULP_ACT_HID_040d = 0x040d, - BNXT_ULP_ACT_HID_040f = 0x040f, - BNXT_ULP_ACT_HID_0413 = 0x0413, - BNXT_ULP_ACT_HID_0567 = 0x0567, - BNXT_ULP_ACT_HID_0a49 = 0x0a49, - BNXT_ULP_ACT_HID_050e = 0x050e, - BNXT_ULP_ACT_HID_0668 = 0x0668, - BNXT_ULP_ACT_HID_0b4a = 0x0b4a, - BNXT_ULP_ACT_HID_0411 = 0x0411, - BNXT_ULP_ACT_HID_056b = 0x056b, - BNXT_ULP_ACT_HID_0a4d = 0x0a4d, - BNXT_ULP_ACT_HID_0512 = 0x0512, - BNXT_ULP_ACT_HID_066c = 0x066c, - BNXT_ULP_ACT_HID_0b4e = 0x0b4e + BNXT_ULP_ACT_HID_0400 = 0x0400, + BNXT_ULP_ACT_HID_0331 = 0x0331, + BNXT_ULP_ACT_HID_0010 = 0x0010, + BNXT_ULP_ACT_HID_0731 = 0x0731, + BNXT_ULP_ACT_HID_0341 = 0x0341, + BNXT_ULP_ACT_HID_0002 = 0x0002, + BNXT_ULP_ACT_HID_0003 = 0x0003, + BNXT_ULP_ACT_HID_0402 = 0x0402, + BNXT_ULP_ACT_HID_0333 = 0x0333, + BNXT_ULP_ACT_HID_0012 = 0x0012, + BNXT_ULP_ACT_HID_0733 = 0x0733, + BNXT_ULP_ACT_HID_0343 = 0x0343 }; enum bnxt_ulp_df_tpl { - BNXT_ULP_DF_TPL_PORT_TO_VS = 1, - BNXT_ULP_DF_TPL_VS_TO_PORT = 2, - BNXT_ULP_DF_TPL_VFREP_TO_VF = 3, - BNXT_ULP_DF_TPL_VF_TO_VFREP = 4, - BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 5 + BNXT_ULP_DF_TPL_PORT_TO_VS = 3, + BNXT_ULP_DF_TPL_VS_TO_PORT = 4, + BNXT_ULP_DF_TPL_VFREP_TO_VF = 5, + BNXT_ULP_DF_TPL_VF_TO_VFREP = 6, + BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h index 6bfea8abc6..0e7278a38f 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h @@ -1,1191 +1,223 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ +/* date: Wed Nov 18 12:19:40 2020 */ + #ifndef ULP_HDR_FIELD_ENUMS_H_ #define ULP_HDR_FIELD_ENUMS_H_ -enum bnxt_ulp_hf1 { - BNXT_ULP_HF1_IDX_SVIF_INDEX = 0 -}; - -enum bnxt_ulp_hf2 { - BNXT_ULP_HF2_IDX_SVIF_INDEX = 0 -}; - -enum bnxt_ulp_hf3 { - BNXT_ULP_HF3_IDX_SVIF_INDEX = 0 -}; - -enum bnxt_ulp_hf4 { - BNXT_ULP_HF4_IDX_SVIF_INDEX = 0 -}; - -enum bnxt_ulp_hf5 { - BNXT_ULP_HF5_IDX_SVIF_INDEX = 0 -}; - -enum bnxt_ulp_hf6 { - BNXT_ULP_HF6_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF6_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF6_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF6_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF6_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF6_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF6_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF6_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF6_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF6_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF6_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF6_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF6_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF6_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF6_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF6_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF6_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF6_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF6_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF6_IDX_O_IPV4_DST_ADDR = 19 -}; - -enum bnxt_ulp_hf7 { - BNXT_ULP_HF7_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF7_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF7_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF7_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF7_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF7_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF7_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF7_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF7_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF7_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF7_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF7_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF7_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF7_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF7_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF7_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF7_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF7_IDX_O_IPV6_DST_ADDR = 17 -}; - -enum bnxt_ulp_hf8 { - BNXT_ULP_HF8_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF8_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF8_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF8_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF8_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF8_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF8_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF8_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF8_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF8_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF8_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF8_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF8_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF8_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF8_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF8_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF8_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF8_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF8_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF8_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF8_IDX_O_UDP_CSUM = 23 -}; - -enum bnxt_ulp_hf9 { - BNXT_ULP_HF9_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF9_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF9_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF9_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF9_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF9_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF9_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF9_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF9_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF9_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF9_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF9_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF9_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF9_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF9_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF9_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF9_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF9_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT = 20, - BNXT_ULP_HF9_IDX_O_TCP_DST_PORT = 21, - BNXT_ULP_HF9_IDX_O_TCP_SENT_SEQ = 22, - BNXT_ULP_HF9_IDX_O_TCP_RECV_ACK = 23, - BNXT_ULP_HF9_IDX_O_TCP_DATA_OFF = 24, - BNXT_ULP_HF9_IDX_O_TCP_TCP_FLAGS = 25, - BNXT_ULP_HF9_IDX_O_TCP_RX_WIN = 26, - BNXT_ULP_HF9_IDX_O_TCP_CSUM = 27, - BNXT_ULP_HF9_IDX_O_TCP_URP = 28 -}; - -enum bnxt_ulp_hf10 { - BNXT_ULP_HF10_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF10_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF10_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF10_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF10_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF10_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF10_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF10_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF10_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF10_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF10_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF10_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF10_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF10_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF10_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF10_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR = 17, - BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT = 18, - BNXT_ULP_HF10_IDX_O_UDP_DST_PORT = 19, - BNXT_ULP_HF10_IDX_O_UDP_LENGTH = 20, - BNXT_ULP_HF10_IDX_O_UDP_CSUM = 21 -}; - -enum bnxt_ulp_hf11 { - BNXT_ULP_HF11_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF11_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF11_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF11_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF11_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF11_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF11_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF11_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF11_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF11_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF11_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF11_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF11_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF11_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF11_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF11_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR = 17, - BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT = 18, - BNXT_ULP_HF11_IDX_O_TCP_DST_PORT = 19, - BNXT_ULP_HF11_IDX_O_TCP_SENT_SEQ = 20, - BNXT_ULP_HF11_IDX_O_TCP_RECV_ACK = 21, - BNXT_ULP_HF11_IDX_O_TCP_DATA_OFF = 22, - BNXT_ULP_HF11_IDX_O_TCP_TCP_FLAGS = 23, - BNXT_ULP_HF11_IDX_O_TCP_RX_WIN = 24, - BNXT_ULP_HF11_IDX_O_TCP_CSUM = 25, - BNXT_ULP_HF11_IDX_O_TCP_URP = 26 -}; - -enum bnxt_ulp_hf12 { - BNXT_ULP_HF12_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF12_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF12_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF12_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF12_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF12_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF12_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF12_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF12_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF12_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF12_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF12_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF12_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF12_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF12_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF12_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF12_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF12_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF12_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF12_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF12_IDX_O_UDP_CSUM = 23 -}; - -enum bnxt_ulp_hf13 { - BNXT_ULP_HF13_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF13_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF13_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF13_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF13_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF13_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF13_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF13_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF13_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF13_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF13_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF13_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF13_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF13_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF13_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF13_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF13_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF13_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT = 20, - BNXT_ULP_HF13_IDX_O_TCP_DST_PORT = 21, - BNXT_ULP_HF13_IDX_O_TCP_SENT_SEQ = 22, - BNXT_ULP_HF13_IDX_O_TCP_RECV_ACK = 23, - BNXT_ULP_HF13_IDX_O_TCP_DATA_OFF = 24, - BNXT_ULP_HF13_IDX_O_TCP_TCP_FLAGS = 25, - BNXT_ULP_HF13_IDX_O_TCP_RX_WIN = 26, - BNXT_ULP_HF13_IDX_O_TCP_CSUM = 27, - BNXT_ULP_HF13_IDX_O_TCP_URP = 28 -}; - -enum bnxt_ulp_hf14 { - BNXT_ULP_HF14_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF14_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF14_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF14_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF14_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF14_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF14_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF14_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF14_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF14_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF14_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF14_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF14_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF14_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF14_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF14_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR = 17, - BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT = 18, - BNXT_ULP_HF14_IDX_O_UDP_DST_PORT = 19, - BNXT_ULP_HF14_IDX_O_UDP_LENGTH = 20, - BNXT_ULP_HF14_IDX_O_UDP_CSUM = 21 -}; - -enum bnxt_ulp_hf15 { - BNXT_ULP_HF15_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF15_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF15_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF15_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF15_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF15_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF15_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF15_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF15_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF15_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF15_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF15_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF15_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF15_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF15_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF15_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR = 17, - BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT = 18, - BNXT_ULP_HF15_IDX_O_TCP_DST_PORT = 19, - BNXT_ULP_HF15_IDX_O_TCP_SENT_SEQ = 20, - BNXT_ULP_HF15_IDX_O_TCP_RECV_ACK = 21, - BNXT_ULP_HF15_IDX_O_TCP_DATA_OFF = 22, - BNXT_ULP_HF15_IDX_O_TCP_TCP_FLAGS = 23, - BNXT_ULP_HF15_IDX_O_TCP_RX_WIN = 24, - BNXT_ULP_HF15_IDX_O_TCP_CSUM = 25, - BNXT_ULP_HF15_IDX_O_TCP_URP = 26 -}; - -enum bnxt_ulp_hf16 { - BNXT_ULP_HF16_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF16_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF16_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF16_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF16_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF16_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF16_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF16_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF16_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF16_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF16_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF16_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF16_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF16_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF16_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF16_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF16_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF16_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF16_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF16_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF16_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF16_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF16_IDX_O_UDP_CSUM = 23, - BNXT_ULP_HF16_IDX_T_VXLAN_FLAGS = 24, - BNXT_ULP_HF16_IDX_T_VXLAN_RSVD0 = 25, - BNXT_ULP_HF16_IDX_T_VXLAN_VNI = 26, - BNXT_ULP_HF16_IDX_T_VXLAN_RSVD1 = 27 -}; - -enum bnxt_ulp_hf17 { - BNXT_ULP_HF17_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF17_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF17_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF17_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF17_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF17_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF17_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF17_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF17_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF17_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF17_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF17_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF17_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF17_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF17_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF17_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF17_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR = 17, - BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT = 18, - BNXT_ULP_HF17_IDX_O_UDP_DST_PORT = 19, - BNXT_ULP_HF17_IDX_O_UDP_LENGTH = 20, - BNXT_ULP_HF17_IDX_O_UDP_CSUM = 21, - BNXT_ULP_HF17_IDX_T_VXLAN_FLAGS = 22, - BNXT_ULP_HF17_IDX_T_VXLAN_RSVD0 = 23, - BNXT_ULP_HF17_IDX_T_VXLAN_VNI = 24, - BNXT_ULP_HF17_IDX_T_VXLAN_RSVD1 = 25 -}; - -enum bnxt_ulp_hf18 { - BNXT_ULP_HF18_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF18_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF18_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF18_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF18_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF18_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF18_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF18_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF18_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF18_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF18_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF18_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF18_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF18_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF18_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF18_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF18_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF18_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF18_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF18_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF18_IDX_O_UDP_CSUM = 23, - BNXT_ULP_HF18_IDX_T_VXLAN_FLAGS = 24, - BNXT_ULP_HF18_IDX_T_VXLAN_RSVD0 = 25, - BNXT_ULP_HF18_IDX_T_VXLAN_VNI = 26, - BNXT_ULP_HF18_IDX_T_VXLAN_RSVD1 = 27 -}; - -enum bnxt_ulp_hf19 { - BNXT_ULP_HF19_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF19_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF19_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF19_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF19_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF19_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF19_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF19_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF19_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF19_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF19_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF19_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF19_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF19_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF19_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF19_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF19_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF19_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF19_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF19_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF19_IDX_O_UDP_CSUM = 23, - BNXT_ULP_HF19_IDX_T_VXLAN_FLAGS = 24, - BNXT_ULP_HF19_IDX_T_VXLAN_RSVD0 = 25, - BNXT_ULP_HF19_IDX_T_VXLAN_VNI = 26, - BNXT_ULP_HF19_IDX_T_VXLAN_RSVD1 = 27, - BNXT_ULP_HF19_IDX_I_ETH_DMAC = 28, - BNXT_ULP_HF19_IDX_I_ETH_SMAC = 29, - BNXT_ULP_HF19_IDX_I_ETH_TYPE = 30, - BNXT_ULP_HF19_IDX_IO_VLAN_CFI_PRI = 31, - BNXT_ULP_HF19_IDX_IO_VLAN_VID = 32, - BNXT_ULP_HF19_IDX_IO_VLAN_TYPE = 33, - BNXT_ULP_HF19_IDX_II_VLAN_CFI_PRI = 34, - BNXT_ULP_HF19_IDX_II_VLAN_VID = 35, - BNXT_ULP_HF19_IDX_II_VLAN_TYPE = 36, - BNXT_ULP_HF19_IDX_I_IPV4_VER = 37, - BNXT_ULP_HF19_IDX_I_IPV4_TOS = 38, - BNXT_ULP_HF19_IDX_I_IPV4_LEN = 39, - BNXT_ULP_HF19_IDX_I_IPV4_FRAG_ID = 40, - BNXT_ULP_HF19_IDX_I_IPV4_FRAG_OFF = 41, - BNXT_ULP_HF19_IDX_I_IPV4_TTL = 42, - BNXT_ULP_HF19_IDX_I_IPV4_PROTO_ID = 43, - BNXT_ULP_HF19_IDX_I_IPV4_CSUM = 44, - BNXT_ULP_HF19_IDX_I_IPV4_SRC_ADDR = 45, - BNXT_ULP_HF19_IDX_I_IPV4_DST_ADDR = 46 -}; - -enum bnxt_ulp_hf20 { - BNXT_ULP_HF20_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF20_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF20_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF20_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF20_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF20_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF20_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF20_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF20_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF20_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF20_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF20_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF20_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF20_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF20_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF20_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF20_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF20_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF20_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF20_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF20_IDX_O_UDP_CSUM = 23 -}; - -enum bnxt_ulp_hf21 { - BNXT_ULP_HF21_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF21_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF21_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF21_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF21_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF21_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF21_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF21_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF21_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF21_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF21_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF21_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF21_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF21_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF21_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF21_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF21_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF21_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT = 20, - BNXT_ULP_HF21_IDX_O_TCP_DST_PORT = 21, - BNXT_ULP_HF21_IDX_O_TCP_SENT_SEQ = 22, - BNXT_ULP_HF21_IDX_O_TCP_RECV_ACK = 23, - BNXT_ULP_HF21_IDX_O_TCP_DATA_OFF = 24, - BNXT_ULP_HF21_IDX_O_TCP_TCP_FLAGS = 25, - BNXT_ULP_HF21_IDX_O_TCP_RX_WIN = 26, - BNXT_ULP_HF21_IDX_O_TCP_CSUM = 27, - BNXT_ULP_HF21_IDX_O_TCP_URP = 28 -}; - -enum bnxt_ulp_hf22 { - BNXT_ULP_HF22_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF22_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF22_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF22_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF22_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF22_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF22_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF22_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF22_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF22_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF22_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF22_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF22_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF22_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF22_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF22_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR = 17, - BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT = 18, - BNXT_ULP_HF22_IDX_O_UDP_DST_PORT = 19, - BNXT_ULP_HF22_IDX_O_UDP_LENGTH = 20, - BNXT_ULP_HF22_IDX_O_UDP_CSUM = 21 -}; - -enum bnxt_ulp_hf23 { - BNXT_ULP_HF23_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF23_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF23_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF23_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF23_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF23_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF23_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF23_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF23_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF23_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF23_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF23_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF23_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF23_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF23_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF23_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR = 17, - BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT = 18, - BNXT_ULP_HF23_IDX_O_TCP_DST_PORT = 19, - BNXT_ULP_HF23_IDX_O_TCP_SENT_SEQ = 20, - BNXT_ULP_HF23_IDX_O_TCP_RECV_ACK = 21, - BNXT_ULP_HF23_IDX_O_TCP_DATA_OFF = 22, - BNXT_ULP_HF23_IDX_O_TCP_TCP_FLAGS = 23, - BNXT_ULP_HF23_IDX_O_TCP_RX_WIN = 24, - BNXT_ULP_HF23_IDX_O_TCP_CSUM = 25, - BNXT_ULP_HF23_IDX_O_TCP_URP = 26 -}; - -enum bnxt_ulp_hf24 { - BNXT_ULP_HF24_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF24_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF24_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF24_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF24_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF24_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF24_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF24_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF24_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF24_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF24_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF24_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF24_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF24_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF24_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF24_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF24_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF24_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF24_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF24_IDX_O_IPV4_DST_ADDR = 19 -}; - -enum bnxt_ulp_hf25 { - BNXT_ULP_HF25_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF25_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF25_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF25_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF25_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF25_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF25_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF25_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF25_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF25_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF25_IDX_O_IPV6_VER = 10, - BNXT_ULP_HF25_IDX_O_IPV6_TC = 11, - BNXT_ULP_HF25_IDX_O_IPV6_FLOW_LABEL = 12, - BNXT_ULP_HF25_IDX_O_IPV6_PAYLOAD_LEN = 13, - BNXT_ULP_HF25_IDX_O_IPV6_PROTO_ID = 14, - BNXT_ULP_HF25_IDX_O_IPV6_TTL = 15, - BNXT_ULP_HF25_IDX_O_IPV6_SRC_ADDR = 16, - BNXT_ULP_HF25_IDX_O_IPV6_DST_ADDR = 17 -}; - -enum bnxt_ulp_hf_bitmask1 { - BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000 -}; - -enum bnxt_ulp_hf_bitmask2 { - BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000 -}; - -enum bnxt_ulp_hf_bitmask3 { - BNXT_ULP_HF3_BITMASK_SVIF_INDEX = 0x8000000000000000 -}; - -enum bnxt_ulp_hf_bitmask4 { - BNXT_ULP_HF4_BITMASK_SVIF_INDEX = 0x8000000000000000 -}; - -enum bnxt_ulp_hf_bitmask5 { - BNXT_ULP_HF5_BITMASK_SVIF_INDEX = 0x8000000000000000 -}; - -enum bnxt_ulp_hf_bitmask6 { - BNXT_ULP_HF6_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF6_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF6_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF6_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF6_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF6_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF6_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF6_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF6_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF6_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF6_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000 -}; - -enum bnxt_ulp_hf_bitmask7 { - BNXT_ULP_HF7_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF7_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF7_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF7_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF7_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF7_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF7_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF7_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF7_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF7_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF7_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF7_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF7_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF7_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF7_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF7_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF7_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF7_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000 -}; - -enum bnxt_ulp_hf_bitmask8 { - BNXT_ULP_HF8_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF8_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF8_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF8_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF8_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF8_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF8_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF8_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF8_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF8_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF8_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF8_BITMASK_O_UDP_CSUM = 0x0000010000000000 -}; - -enum bnxt_ulp_hf_bitmask9 { - BNXT_ULP_HF9_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF9_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF9_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF9_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF9_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF9_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF9_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF9_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF9_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF9_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_SENT_SEQ = 0x0000020000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_RECV_ACK = 0x0000010000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_DATA_OFF = 0x0000008000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_TCP_FLAGS = 0x0000004000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_RX_WIN = 0x0000002000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_CSUM = 0x0000001000000000, - BNXT_ULP_HF9_BITMASK_O_TCP_URP = 0x0000000800000000 -}; - -enum bnxt_ulp_hf_bitmask10 { - BNXT_ULP_HF10_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF10_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF10_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF10_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF10_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF10_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF10_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF10_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF10_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF10_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF10_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF10_BITMASK_O_UDP_CSUM = 0x0000040000000000 -}; - -enum bnxt_ulp_hf_bitmask11 { - BNXT_ULP_HF11_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF11_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF11_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF11_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF11_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF11_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF11_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF11_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF11_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF11_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF11_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF11_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF11_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF11_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF11_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF11_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF11_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF11_BITMASK_O_TCP_URP = 0x0000002000000000 -}; - -enum bnxt_ulp_hf_bitmask12 { - BNXT_ULP_HF12_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF12_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF12_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF12_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF12_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF12_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF12_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF12_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF12_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF12_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF12_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF12_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF12_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF12_BITMASK_O_UDP_CSUM = 0x0000010000000000 -}; - -enum bnxt_ulp_hf_bitmask13 { - BNXT_ULP_HF13_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF13_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF13_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF13_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF13_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF13_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF13_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF13_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF13_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF13_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF13_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_SENT_SEQ = 0x0000020000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_RECV_ACK = 0x0000010000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_DATA_OFF = 0x0000008000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_TCP_FLAGS = 0x0000004000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_RX_WIN = 0x0000002000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_CSUM = 0x0000001000000000, - BNXT_ULP_HF13_BITMASK_O_TCP_URP = 0x0000000800000000 +enum bnxt_ulp_glb_hf { + BNXT_ULP_GLB_HF_WM, + BNXT_ULP_GLB_HF_SVIF_INDEX, + BNXT_ULP_GLB_HF_O_ETH_DMAC, + BNXT_ULP_GLB_HF_I_ETH_DMAC, + BNXT_ULP_GLB_HF_O_ETH_SMAC, + BNXT_ULP_GLB_HF_I_ETH_SMAC, + BNXT_ULP_GLB_HF_O_ETH_TYPE, + BNXT_ULP_GLB_HF_I_ETH_TYPE, + BNXT_ULP_GLB_HF_O_IPV4_VER, + BNXT_ULP_GLB_HF_I_IPV4_VER, + BNXT_ULP_GLB_HF_O_IPV4_TOS, + BNXT_ULP_GLB_HF_I_IPV4_TOS, + BNXT_ULP_GLB_HF_O_IPV4_LEN, + BNXT_ULP_GLB_HF_I_IPV4_LEN, + BNXT_ULP_GLB_HF_O_IPV4_FRAG_ID, + BNXT_ULP_GLB_HF_I_IPV4_FRAG_ID, + BNXT_ULP_GLB_HF_O_IPV4_FRAG_OFF, + BNXT_ULP_GLB_HF_I_IPV4_FRAG_OFF, + BNXT_ULP_GLB_HF_O_IPV4_TTL, + BNXT_ULP_GLB_HF_I_IPV4_TTL, + BNXT_ULP_GLB_HF_O_IPV4_PROTO_ID, + BNXT_ULP_GLB_HF_I_IPV4_PROTO_ID, + BNXT_ULP_GLB_HF_O_IPV4_CSUM, + BNXT_ULP_GLB_HF_I_IPV4_CSUM, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR, + BNXT_ULP_GLB_HF_I_IPV4_SRC_ADDR, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR, + BNXT_ULP_GLB_HF_I_IPV4_DST_ADDR, + BNXT_ULP_GLB_HF_O_IPV6_VER, + BNXT_ULP_GLB_HF_I_IPV6_VER, + BNXT_ULP_GLB_HF_O_IPV6_TC, + BNXT_ULP_GLB_HF_I_IPV6_TC, + BNXT_ULP_GLB_HF_O_IPV6_FLOW_LABEL, + BNXT_ULP_GLB_HF_I_IPV6_FLOW_LABEL, + BNXT_ULP_GLB_HF_O_IPV6_PAYLOAD_LEN, + BNXT_ULP_GLB_HF_I_IPV6_PAYLOAD_LEN, + BNXT_ULP_GLB_HF_O_IPV6_PROTO_ID, + BNXT_ULP_GLB_HF_I_IPV6_PROTO_ID, + BNXT_ULP_GLB_HF_O_IPV6_TTL, + BNXT_ULP_GLB_HF_I_IPV6_TTL, + BNXT_ULP_GLB_HF_O_IPV6_SRC_ADDR, + BNXT_ULP_GLB_HF_I_IPV6_SRC_ADDR, + BNXT_ULP_GLB_HF_O_IPV6_DST_ADDR, + BNXT_ULP_GLB_HF_I_IPV6_DST_ADDR, + BNXT_ULP_GLB_HF_O_L3_PROTO_ID, + BNXT_ULP_GLB_HF_I_L3_PROTO_ID, + BNXT_ULP_GLB_HF_O_L3_SRC_ADDR, + BNXT_ULP_GLB_HF_I_L3_SRC_ADDR, + BNXT_ULP_GLB_HF_O_L3_DST_ADDR, + BNXT_ULP_GLB_HF_I_L3_DST_ADDR, + BNXT_ULP_GLB_HF_O_L4_SRC_PORT, + BNXT_ULP_GLB_HF_I_L4_SRC_PORT, + BNXT_ULP_GLB_HF_O_L4_DST_PORT, + BNXT_ULP_GLB_HF_I_L4_DST_PORT, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT, + BNXT_ULP_GLB_HF_I_TCP_SRC_PORT, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT, + BNXT_ULP_GLB_HF_I_TCP_DST_PORT, + BNXT_ULP_GLB_HF_O_TCP_SENT_SEQ, + BNXT_ULP_GLB_HF_I_TCP_SENT_SEQ, + BNXT_ULP_GLB_HF_O_TCP_RECV_ACK, + BNXT_ULP_GLB_HF_I_TCP_RECV_ACK, + BNXT_ULP_GLB_HF_O_TCP_DATA_OFF, + BNXT_ULP_GLB_HF_I_TCP_DATA_OFF, + BNXT_ULP_GLB_HF_O_TCP_TCP_FLAGS, + BNXT_ULP_GLB_HF_I_TCP_TCP_FLAGS, + BNXT_ULP_GLB_HF_O_TCP_RX_WIN, + BNXT_ULP_GLB_HF_I_TCP_RX_WIN, + BNXT_ULP_GLB_HF_O_TCP_CSUM, + BNXT_ULP_GLB_HF_I_TCP_CSUM, + BNXT_ULP_GLB_HF_O_TCP_URP, + BNXT_ULP_GLB_HF_I_TCP_URP, + BNXT_ULP_GLB_HF_O_UDP_SRC_PORT, + BNXT_ULP_GLB_HF_I_UDP_SRC_PORT, + BNXT_ULP_GLB_HF_O_UDP_DST_PORT, + BNXT_ULP_GLB_HF_I_UDP_DST_PORT, + BNXT_ULP_GLB_HF_O_UDP_LENGTH, + BNXT_ULP_GLB_HF_I_UDP_LENGTH, + BNXT_ULP_GLB_HF_O_UDP_CSUM, + BNXT_ULP_GLB_HF_I_UDP_CSUM, + BNXT_ULP_GLB_HF_OO_VLAN_CFI_PRI, + BNXT_ULP_GLB_HF_OI_VLAN_CFI_PRI, + BNXT_ULP_GLB_HF_IO_VLAN_CFI_PRI, + BNXT_ULP_GLB_HF_II_VLAN_CFI_PRI, + BNXT_ULP_GLB_HF_OO_VLAN_VID, + BNXT_ULP_GLB_HF_OI_VLAN_VID, + BNXT_ULP_GLB_HF_IO_VLAN_VID, + BNXT_ULP_GLB_HF_II_VLAN_VID, + BNXT_ULP_GLB_HF_OO_VLAN_TYPE, + BNXT_ULP_GLB_HF_OI_VLAN_TYPE, + BNXT_ULP_GLB_HF_IO_VLAN_TYPE, + BNXT_ULP_GLB_HF_II_VLAN_TYPE, + BNXT_ULP_GLB_HF_T_VXLAN_FLAGS, + BNXT_ULP_GLB_HF_T_VXLAN_RSVD0, + BNXT_ULP_GLB_HF_T_VXLAN_VNI, + BNXT_ULP_GLB_HF_T_VXLAN_RSVD1 +}; + +enum bnxt_ulp_hf1_0_bitmask { + BNXT_ULP_HF1_0_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_0_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_URP = 0x0000010000000000 +}; + +enum bnxt_ulp_hf1_1_bitmask { + BNXT_ULP_HF1_1_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_1_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_URP = 0x0000002000000000 +}; + +enum bnxt_ulp_hf2_0_bitmask { + BNXT_ULP_HF2_0_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_0_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF2_0_BITMASK_O_TCP_URP = 0x0000010000000000 +}; + +enum bnxt_ulp_hf2_1_bitmask { + BNXT_ULP_HF2_1_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_1_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_URP = 0x0000002000000000 }; - -enum bnxt_ulp_hf_bitmask14 { - BNXT_ULP_HF14_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF14_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF14_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF14_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF14_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF14_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF14_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF14_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF14_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF14_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF14_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF14_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF14_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF14_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF14_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF14_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF14_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF14_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF14_BITMASK_O_UDP_CSUM = 0x0000040000000000 -}; - -enum bnxt_ulp_hf_bitmask15 { - BNXT_ULP_HF15_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF15_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF15_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF15_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF15_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF15_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF15_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF15_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF15_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF15_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF15_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF15_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF15_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF15_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF15_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF15_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF15_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF15_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF15_BITMASK_O_TCP_URP = 0x0000002000000000 -}; - -enum bnxt_ulp_hf_bitmask16 { - BNXT_ULP_HF16_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF16_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF16_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF16_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF16_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF16_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF16_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF16_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF16_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF16_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF16_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF16_BITMASK_O_UDP_CSUM = 0x0000010000000000, - BNXT_ULP_HF16_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000, - BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000, - BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI = 0x0000002000000000, - BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000 -}; - -enum bnxt_ulp_hf_bitmask17 { - BNXT_ULP_HF17_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF17_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF17_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF17_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF17_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF17_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF17_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF17_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF17_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF17_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF17_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF17_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF17_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF17_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF17_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF17_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF17_BITMASK_O_UDP_CSUM = 0x0000040000000000, - BNXT_ULP_HF17_BITMASK_T_VXLAN_FLAGS = 0x0000020000000000, - BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD0 = 0x0000010000000000, - BNXT_ULP_HF17_BITMASK_T_VXLAN_VNI = 0x0000008000000000, - BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD1 = 0x0000004000000000 -}; - -enum bnxt_ulp_hf_bitmask18 { - BNXT_ULP_HF18_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF18_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF18_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF18_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF18_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF18_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF18_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF18_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF18_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF18_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF18_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF18_BITMASK_O_UDP_CSUM = 0x0000010000000000, - BNXT_ULP_HF18_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000, - BNXT_ULP_HF18_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000, - BNXT_ULP_HF18_BITMASK_T_VXLAN_VNI = 0x0000002000000000, - BNXT_ULP_HF18_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000 -}; - -enum bnxt_ulp_hf_bitmask19 { - BNXT_ULP_HF19_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF19_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF19_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF19_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF19_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF19_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF19_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF19_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF19_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF19_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF19_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF19_BITMASK_O_UDP_CSUM = 0x0000010000000000, - BNXT_ULP_HF19_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000, - BNXT_ULP_HF19_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000, - BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI = 0x0000002000000000, - BNXT_ULP_HF19_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000, - BNXT_ULP_HF19_BITMASK_I_ETH_DMAC = 0x0000000800000000, - BNXT_ULP_HF19_BITMASK_I_ETH_SMAC = 0x0000000400000000, - BNXT_ULP_HF19_BITMASK_I_ETH_TYPE = 0x0000000200000000, - BNXT_ULP_HF19_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000, - BNXT_ULP_HF19_BITMASK_IO_VLAN_VID = 0x0000000080000000, - BNXT_ULP_HF19_BITMASK_IO_VLAN_TYPE = 0x0000000040000000, - BNXT_ULP_HF19_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000, - BNXT_ULP_HF19_BITMASK_II_VLAN_VID = 0x0000000010000000, - BNXT_ULP_HF19_BITMASK_II_VLAN_TYPE = 0x0000000008000000, - BNXT_ULP_HF19_BITMASK_I_IPV4_VER = 0x0000000004000000, - BNXT_ULP_HF19_BITMASK_I_IPV4_TOS = 0x0000000002000000, - BNXT_ULP_HF19_BITMASK_I_IPV4_LEN = 0x0000000001000000, - BNXT_ULP_HF19_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000, - BNXT_ULP_HF19_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000, - BNXT_ULP_HF19_BITMASK_I_IPV4_TTL = 0x0000000000200000, - BNXT_ULP_HF19_BITMASK_I_IPV4_PROTO_ID = 0x0000000000100000, - BNXT_ULP_HF19_BITMASK_I_IPV4_CSUM = 0x0000000000080000, - BNXT_ULP_HF19_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000, - BNXT_ULP_HF19_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000 -}; - -enum bnxt_ulp_hf_bitmask20 { - BNXT_ULP_HF20_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF20_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF20_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF20_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF20_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF20_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF20_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF20_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF20_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF20_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF20_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF20_BITMASK_O_UDP_CSUM = 0x0000010000000000 -}; - -enum bnxt_ulp_hf_bitmask21 { - BNXT_ULP_HF21_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF21_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF21_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF21_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF21_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF21_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF21_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF21_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF21_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF21_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_SENT_SEQ = 0x0000020000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_RECV_ACK = 0x0000010000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_DATA_OFF = 0x0000008000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_TCP_FLAGS = 0x0000004000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_RX_WIN = 0x0000002000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_CSUM = 0x0000001000000000, - BNXT_ULP_HF21_BITMASK_O_TCP_URP = 0x0000000800000000 -}; - -enum bnxt_ulp_hf_bitmask22 { - BNXT_ULP_HF22_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF22_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF22_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF22_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF22_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF22_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF22_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF22_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF22_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF22_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF22_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF22_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF22_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF22_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF22_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF22_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF22_BITMASK_O_UDP_CSUM = 0x0000040000000000 -}; - -enum bnxt_ulp_hf_bitmask23 { - BNXT_ULP_HF23_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF23_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF23_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF23_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF23_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF23_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF23_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF23_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF23_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF23_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF23_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF23_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF23_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF23_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF23_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF23_BITMASK_O_TCP_URP = 0x0000002000000000 -}; - -enum bnxt_ulp_hf_bitmask24 { - BNXT_ULP_HF24_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF24_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF24_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF24_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF24_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF24_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF24_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF24_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF24_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF24_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF24_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000 -}; - -enum bnxt_ulp_hf_bitmask25 { - BNXT_ULP_HF25_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF25_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF25_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF25_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF25_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF25_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF25_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF25_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF25_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF25_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF25_BITMASK_O_IPV6_VER = 0x0020000000000000, - BNXT_ULP_HF25_BITMASK_O_IPV6_TC = 0x0010000000000000, - BNXT_ULP_HF25_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, - BNXT_ULP_HF25_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, - BNXT_ULP_HF25_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF25_BITMASK_O_IPV6_TTL = 0x0001000000000000, - BNXT_ULP_HF25_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF25_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000 -}; - #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c index 1381f0a0ee..87d6347196 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c @@ -3,3359 +3,244 @@ * All rights reserved. */ -/* date: Thu Oct 15 17:28:37 2020 */ +/* date: Mon Nov 23 17:33:02 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" -#include "ulp_rte_parser.h" +#include "ulp_template_db_tbl.h" /* Mapper templates for header act list */ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[] = { - /* act-ing-[dec_ttl, count, nat]:1 */ /* act_tid: 1, stingray, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 0 - }, - /* act-ing-[drop, pop_vlan, push_vlan, dec_ttl, count, vxlan_decap]:2 */ - /* act_tid: 2, stingray, ingress */ - [2] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 3, - .start_tbl_idx = 6 - }, - /* act-ing-[mark, rss, count, pop_vlan, vxlan_decap]:3 */ - /* act_tid: 3, stingray, ingress */ - [3] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 3, - .start_tbl_idx = 9 - }, - /* act_egr-[vxlan_encap, count]:4 */ - /* act_tid: 4, stingray, egress */ - [4] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 12 - }, - /* act-egr-[dec_ttl, count, nat]:5 */ - /* act_tid: 5, stingray, egress */ - [5] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 18 - }, - /* act-egr-[drop, push_vlan, dec_ttl, count]:6 */ - /* act_tid: 6, stingray, egress */ - [6] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 24 + .num_tbls = 4, + .start_tbl_idx = 0, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 0, + .cond_nums = 0 } } }; struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { - { /* act_tid: 1, stingray, table: int_flow_counter_tbl_0 */ + { /* act_tid: 1, stingray, table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 0, .result_bit_size = 64, .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .encap_num_fields = 0 }, - { /* act_tid: 1, stingray, table: int_act_modify_ipv4_src_0 */ + { /* act_tid: 1, stingray, table: int_vtag_encap_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_RX, - .result_start_idx = 1, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 1, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 - }, - { /* act_tid: 1, stingray, table: int_act_modify_ipv4_dst_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, - .direction = TF_DIR_RX, - .result_start_idx = 2, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 - }, - { /* act_tid: 1, stingray, table: int_encap_mac_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .result_start_idx = 3, + .result_start_idx = 1, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR - }, - { /* act_tid: 1, stingray, table: ext_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .result_start_idx = 15, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .encap_num_fields = 12 }, - { /* act_tid: 1, stingray, table: int_full_act_record_0 */ + { /* act_tid: 1, stingray, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .result_start_idx = 41, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 2, stingray, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_RX, - .result_start_idx = 67, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* act_tid: 2, stingray, table: ext_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, - .result_start_idx = 68, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 2, stingray, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .result_start_idx = 94, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 3, stingray, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_RX, - .result_start_idx = 120, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* act_tid: 3, stingray, table: ext_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .result_start_idx = 121, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 3, stingray, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .result_start_idx = 147, + .result_start_idx = 13, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 4, stingray, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_TX, - .result_start_idx = 173, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* act_tid: 4, stingray, table: int_sp_smac_ipv4_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG, - .direction = TF_DIR_TX, - .result_start_idx = 174, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 3, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR - }, - { /* act_tid: 4, stingray, table: int_sp_smac_ipv6_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG, - .direction = TF_DIR_TX, - .result_start_idx = 177, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 3, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR - }, - { /* act_tid: 4, stingray, table: int_tun_encap_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_TX, - .result_start_idx = 180, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .encap_num_fields = 0 }, - { /* act_tid: 4, stingray, table: ext_full_act_record_0 */ + { /* act_tid: 1, stingray, table: ext_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .result_start_idx = 192, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 4, stingray, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .result_start_idx = 230, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 5, stingray, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_TX, - .result_start_idx = 256, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* act_tid: 5, stingray, table: int_act_modify_ipv4_src_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, - .direction = TF_DIR_TX, - .result_start_idx = 257, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 - }, - { /* act_tid: 5, stingray, table: int_act_modify_ipv4_dst_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, - .direction = TF_DIR_TX, - .result_start_idx = 258, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 - }, - { /* act_tid: 5, stingray, table: int_encap_mac_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .result_start_idx = 259, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR - }, - { /* act_tid: 5, stingray, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .result_start_idx = 271, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 5, stingray, table: ext_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .result_start_idx = 297, + .result_start_idx = 39, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 11, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 6, stingray, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .encap_num_fields = 0 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[] = { + { .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_TX, - .result_start_idx = 334, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .cond_operand = BNXT_ULP_ACTION_BIT_COUNT }, - { /* act_tid: 6, stingray, table: int_vtag_encap_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + { .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, - .direction = TF_DIR_TX, - .result_start_idx = 335, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 - }, - { /* act_tid: 6, stingray, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .result_start_idx = 347, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 6, stingray, table: ext_full_act_record_no_tag_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, - .direction = TF_DIR_TX, - .result_start_idx = 373, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 6, stingray, table: ext_full_act_record_one_tag_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, - .direction = TF_DIR_TX, - .result_start_idx = 399, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 11, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN } }; -struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = { - /* act_tid: 1, stingray, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 1, stingray, table: int_act_modify_ipv4_src_0 */ - { - .description = "ipv4_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 1, stingray, table: int_act_modify_ipv4_dst_0 */ - { - .description = "ipv4_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 1, stingray, table: int_encap_mac_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L2_EN_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "spare", - .field_bit_size = 80, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 1, stingray, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 1, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 2, stingray, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 2, stingray, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 2, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 3, stingray, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 3, stingray, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 3, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 4, stingray, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 4, stingray, table: int_sp_smac_ipv4_0 */ - { - .description = "smac", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 4, stingray, table: int_sp_smac_ipv6_0 */ - { - .description = "smac", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 4, stingray, table: int_tun_encap_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_l2_dmac", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_vtag", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_ip", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_udp", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_tun", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 4, stingray, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_l2_dmac", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_vtag", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_ip", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_udp", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_tun", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 4, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 5, stingray, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 5, stingray, table: int_act_modify_ipv4_src_0 */ - { - .description = "ipv4_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 5, stingray, table: int_act_modify_ipv4_dst_0 */ - { - .description = "ipv4_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 5, stingray, table: int_encap_mac_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L2_EN_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "spare", - .field_bit_size = 80, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 5, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 5, stingray, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L2_EN_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 6, stingray, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 6, stingray, table: int_vtag_encap_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "spare", - .field_bit_size = 80, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 6, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, +struct bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[] = { + /* act_tid: 1, stingray, table: int_flow_counter_tbl.0 */ { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "count", + .field_bit_size = 64, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* act_tid: 1, stingray, table: int_vtag_encap_record.0 */ { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "tl3_rdir", + .description = "ecv_custom_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l3_ttl_dec", + .description = "ecv_valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", + .description = "vtag_vid", .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", + .description = "vtag_de", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "spare", + .field_bit_size = 80, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* act_tid: 6, stingray, table: ext_full_act_record_no_tag_0 */ + /* act_tid: 1, stingray, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "age_enable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, @@ -3367,75 +252,110 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .description = "tcpflags_key", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "tcp_dst_port", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "src_ip_ptr", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "tcp_src_port", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "meter_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3444,8 +364,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = { .description = "tl3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3454,38 +374,60 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = { .description = "decap_func", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pop_vlan", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "meter", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "mirror", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, @@ -3496,37 +438,47 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* act_tid: 6, stingray, table: ext_full_act_record_one_tag_0 */ + { + .description = "hit", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* act_tid: 1, stingray, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "age_enable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, @@ -3540,73 +492,113 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = { .description = "flow_cntr_ext", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "tcp_dst_port", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "src_ip_ptr", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "tcp_src_port", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "meter_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3615,8 +607,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = { .description = "tl3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3625,23 +617,35 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = { .description = "decap_func", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pop_vlan", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, @@ -3655,18 +659,18 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = { .description = "meter", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "mirror", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, @@ -3676,81 +680,5 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[] = ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c index 53ba637d4e..c836e2f8ed 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c @@ -3,21096 +3,5059 @@ * All rights reserved. */ -/* date: Thu Oct 15 17:28:37 2020 */ +/* date: Mon Nov 23 17:33:02 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" -#include "ulp_rte_parser.h" +#include "ulp_template_db_tbl.h" /* Mapper templates for header class list */ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = { - /* default-vfr-[port_to_vs]:1 */ /* class_tid: 1, stingray, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, - .start_tbl_idx = 0 + .start_tbl_idx = 0, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 0, + .cond_nums = 0 } }, - /* default-vfr-[vs_to_port]:2 */ - /* class_tid: 2, stingray, egress */ + /* class_tid: 2, stingray, ingress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 7, - .start_tbl_idx = 6 + .num_tbls = 6, + .start_tbl_idx = 6, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 2, + .cond_nums = 0 } }, - /* default-vfr-[vfrep_to_vf]:3 */ - /* class_tid: 3, stingray, egress */ + /* class_tid: 3, stingray, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 7, - .start_tbl_idx = 13 + .num_tbls = 6, + .start_tbl_idx = 12, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 4, + .cond_nums = 0 } }, - /* default-vfr-[vf_to_vfrep]:4 */ /* class_tid: 4, stingray, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 7, - .start_tbl_idx = 20 + .num_tbls = 8, + .start_tbl_idx = 18, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 4, + .cond_nums = 0 } }, - /* default-egr-[loopback_action_rec]:5 */ /* class_tid: 5, stingray, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 1, - .start_tbl_idx = 27 + .num_tbls = 7, + .start_tbl_idx = 26, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 10, + .cond_nums = 0 } }, - /* class-ing-em-[eth, (vlan), ipv4]-[smac, dmac, (vid)]:6 */ - /* class_tid: 6, stingray, ingress */ + /* class_tid: 6, stingray, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 28 + .num_tbls = 7, + .start_tbl_idx = 33, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 10, + .cond_nums = 0 } }, - /* class-ing-em-[eth, (vlan), ipv6]-[smac, dmac, (vid)]:7 */ - /* class_tid: 7, stingray, ingress */ + /* class_tid: 7, stingray, egress */ [7] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 33 - }, - /* class-ing-em-[eth, ipv4, udp]-[sip, dip, sp, dp]:8 */ - /* class_tid: 8, stingray, ingress */ - [8] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 38 - }, - /* class-ing-em-[eth, ipv4, tcp]-[sip, dip, sp, dp]:9 */ - /* class_tid: 9, stingray, ingress */ - [9] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 44 - }, - /* class-ing-em-[eth,ipv6, udp]-[sip, dip, sp, dp]:10 */ - /* class_tid: 10, stingray, ingress */ - [10] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 50 - }, - /* class-ing-em-[eth, ipv6, tcp]-[sip, dip, sp, dp]:11 */ - /* class_tid: 11, stingray, ingress */ - [11] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 56 - }, - /* class-ing-em-[eth, (vlan), ipv4, udp]-[dmac, (vid), sip, dip, sp, dp]:12 */ - /* class_tid: 12, stingray, ingress */ - [12] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 62 - }, - /* class-ing-em-[eth, (vlan), ipv4, tcp]-[dmac, (vid), sip, dip, sp, dp]:13 */ - /* class_tid: 13, stingray, ingress */ - [13] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 67 + .num_tbls = 1, + .start_tbl_idx = 40, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 10, + .cond_nums = 0 } + } +}; + +struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { + { /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 0, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 0, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 0, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 0, + .ident_nums = 1 }, - /* class-ing-em-[eth, (vlan), ipv6, udp]-[dmac, (vid), sip, dip, sp, dp]:14 */ - /* class_tid: 14, stingray, ingress */ - [14] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 72 + { /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 0, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 13, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 1, + .ident_nums = 3 }, - /* class-ing-em-[eth, (vlan), ipv6, tcp]-[dmac, (vid), sip, dip, sp, dp]:15 */ - /* class_tid: 15, stingray, ingress */ - [15] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 77 + { /* class_tid: 1, stingray, table: profile_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 16, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 13, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 4, + .ident_nums = 1 }, - /* class-ing-em-[eth, (vlan), ipv4, udp, vxlan]-[dmac, (vid), dip, dp]:16 */ - /* class_tid: 16, stingray, ingress */ - [16] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 82 + { /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 1, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 59, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 21, + .result_bit_size = 66, + .result_num_fields = 5, + .encap_num_fields = 0 }, - /* class-ing-em-[eth, (vlan), ipv6, udp, vxlan]-[t_dmac, (vid), t_dip, t_dp]:17 */ - /* class_tid: 17, stingray, ingress */ - [17] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 87 + { /* class_tid: 1, stingray, table: eem.ext_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 62, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 10, + .result_start_idx = 26, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 }, - /* class-ing-em-f1-[eth, ipv4, udp, vxlan]-[t_dmac]:18 */ - /* class_tid: 18, stingray, ingress */ - [18] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 92 + { /* class_tid: 1, stingray, table: em.int_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 72, + .blob_key_bit_size = 176, + .key_bit_size = 176, + .key_num_fields = 10, + .result_start_idx = 35, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 }, - /* class-ing-em-f2-[ipv4, udp, vxlan]-[vni, i_dmac]:19 */ - /* class_tid: 19, stingray, ingress */ - [19] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 97 + { /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 82, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 44, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 5, + .ident_nums = 1 }, - /* class-egr-em-[eth, ipv4, udp]-[sip, dip, sp, dp]:20 */ - /* class_tid: 20, stingray, egress */ - [20] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 102 + { /* class_tid: 2, stingray, table: profile_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 95, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 6, + .ident_nums = 3 }, - /* class-egr-em-[eth, ipv4, tcp]-[sip, dip, sp, dp]:21 */ - /* class_tid: 21, stingray, egress */ - [21] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 108 + { /* class_tid: 2, stingray, table: profile_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 2, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 98, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 57, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 9, + .ident_nums = 1 }, - /* class-egr-em-[eth-ipv6-udp]-[sip-dip-sp-dp]:22 */ - /* class_tid: 22, stingray, egress */ - [22] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 114 + { /* class_tid: 2, stingray, table: profile_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 3, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 141, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 65, + .result_bit_size = 66, + .result_num_fields = 5, + .encap_num_fields = 0 }, - /* class-egr-em-[eth, ipv6, tcp]-[sip, dip, sp, dp]:23 */ - /* class_tid: 23, stingray, egress */ - [23] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 120 + { /* class_tid: 2, stingray, table: eem.ext_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 144, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 10, + .result_start_idx = 70, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 }, - /* class-egr-em-[eth, (vlan), ipv4]-[smac, dmac, type]:24 */ - /* class_tid: 24, stingray, egress */ - [24] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 126 + { /* class_tid: 2, stingray, table: em.int_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 154, + .blob_key_bit_size = 176, + .key_bit_size = 176, + .key_num_fields = 10, + .result_start_idx = 79, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 }, - /* class-egr-em-[eth, (vlan), ipv6]-[smac, dmac, type]:25 */ - /* class_tid: 25, stingray, egress */ - [25] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 5, - .start_tbl_idx = 131 - } -}; - -struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { - { /* class_tid: 1, stingray, table: int_full_act_record_0 */ + { /* class_tid: 3, stingray, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .result_start_idx = 0, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 88, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 0, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 26, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 1 + .encap_num_fields = 0 }, - { /* class_tid: 1, stingray, table: l2_cntxt_tcam_0 */ + { /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 1, - .blob_key_bit_size = 171, - .key_bit_size = 171, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 164, + .blob_key_bit_size = 167, + .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 27, + .result_start_idx = 114, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 1, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .ident_start_idx = 10, + .ident_nums = 1 + }, + { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 177, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 127, + .result_bit_size = 62, + .result_num_fields = 4, + .encap_num_fields = 0 }, - { /* class_tid: 1, stingray, table: parif_def_lkup_arec_ptr_0 */ + { /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, - .result_start_idx = 40, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 131, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 1, stingray, table: parif_def_arec_ptr_0 */ + { /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, - .result_start_idx = 41, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 132, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 1, stingray, table: parif_def_err_arec_ptr_0 */ + { /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, - .result_start_idx = 42, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 133, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 2, stingray, table: int_full_act_record_0 */ + { /* class_tid: 4, stingray, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .result_start_idx = 43, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 134, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .encap_num_fields = 0 }, - { /* class_tid: 2, stingray, table: l2_cntxt_tcam_vfr_0 */ + { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 4, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 14, - .blob_key_bit_size = 171, - .key_bit_size = 171, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 178, + .blob_key_bit_size = 167, + .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 69, + .result_start_idx = 160, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 1, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .ident_start_idx = 11, + .ident_nums = 0 }, - { /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, + { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, - .key_start_idx = 27, - .blob_key_bit_size = 12, - .key_bit_size = 12, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 5, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 191, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 82, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 1, + .ident_start_idx = 11, .ident_nums = 1 }, - { /* class_tid: 2, stingray, table: l2_cntxt_tcam_0 */ + { /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 28, - .blob_key_bit_size = 171, - .key_bit_size = 171, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 6, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 192, + .blob_key_bit_size = 167, + .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 83, + .result_start_idx = 173, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .ident_start_idx = 12, + .ident_nums = 1 + }, + { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 8, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 205, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 186, + .result_bit_size = 62, + .result_num_fields = 4, + .encap_num_fields = 0 }, - { /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr_0 */ + { /* class_tid: 4, stingray, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, - .result_start_idx = 96, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 190, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 2, stingray, table: parif_def_arec_ptr_0 */ + { /* class_tid: 4, stingray, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, - .result_start_idx = 97, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 191, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 2, stingray, table: parif_def_err_arec_ptr_0 */ + { /* class_tid: 4, stingray, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, - .result_start_idx = 98, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 192, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 3, stingray, table: egr_int_vtag_encap_record_0 */ + { /* class_tid: 5, stingray, table: int_vtag_encap_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .result_start_idx = 99, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 193, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .encap_num_fields = 12 }, - { /* class_tid: 3, stingray, table: egr_int_full_act_record_0 */ + { /* class_tid: 5, stingray, table: int_full_act_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .result_start_idx = 111, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 205, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* class_tid: 3, stingray, table: egr_l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 41, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 137, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0 + .encap_num_fields = 0 }, - { /* class_tid: 3, stingray, table: egr_l2_cntxt_tcam_0 */ + { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 42, - .blob_key_bit_size = 171, - .key_bit_size = 171, + .key_start_idx = 206, + .blob_key_bit_size = 167, + .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 137, + .result_start_idx = 231, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .ident_start_idx = 13, + .ident_nums = 0 }, - { /* class_tid: 3, stingray, table: ing_int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .result_start_idx = 150, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* class_tid: 3, stingray, table: ing_l2_cntxt_dtagged_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 55, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 176, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 3, stingray, table: ing_l2_cntxt_stagged_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 68, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 189, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + { /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, - .key_start_idx = 81, - .blob_key_bit_size = 12, - .key_bit_size = 12, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 219, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 202, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 1 - }, - { /* class_tid: 4, stingray, table: egr_l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 82, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 203, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 4, stingray, table: egr_parif_def_lkup_arec_ptr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .result_start_idx = 216, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF - }, - { /* class_tid: 4, stingray, table: egr_parif_def_arec_ptr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .result_start_idx = 217, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF - }, - { /* class_tid: 4, stingray, table: egr_parif_def_err_arec_ptr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, - .result_start_idx = 218, - .result_bit_size = 32, - .result_num_fields = 1, + .result_start_idx = 244, + .result_bit_size = 62, + .result_num_fields = 4, .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + .ident_start_idx = 13, + .ident_nums = 0 }, - { /* class_tid: 4, stingray, table: ing_int_full_act_record_0 */ + { /* class_tid: 5, stingray, table: int_full_act_record.ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .result_start_idx = 219, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* class_tid: 4, stingray, table: ing_l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 95, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 245, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 0, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 5, stingray, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .result_start_idx = 258, + .result_start_idx = 248, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR + .encap_num_fields = 0 }, - { /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ + { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 108, - .blob_key_bit_size = 171, - .key_bit_size = 171, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 220, + .blob_key_bit_size = 167, + .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 284, + .result_start_idx = 274, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 121, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 297, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 4, - .ident_nums = 1 - }, - { /* class_tid: 6, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 1, - .key_start_idx = 124, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 298, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 6, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 167, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 306, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 6, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 178, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 315, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + .ident_start_idx = 13, + .ident_nums = 0 }, - { /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ + { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 189, - .blob_key_bit_size = 171, - .key_bit_size = 171, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 233, + .blob_key_bit_size = 167, + .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 324, + .result_start_idx = 287, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 202, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 337, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 6, - .ident_nums = 1 - }, - { /* class_tid: 7, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 1, - .key_start_idx = 205, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 338, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 7, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 248, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 346, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 7, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 259, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 355, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 270, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 364, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 1 + .ident_start_idx = 13, + .ident_nums = 0 }, - { /* class_tid: 8, stingray, table: l2_cntxt_tcam_0 */ + { /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 271, - .blob_key_bit_size = 171, - .key_bit_size = 171, + .key_start_idx = 246, + .blob_key_bit_size = 167, + .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 365, + .result_start_idx = 300, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 8, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 284, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 378, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 8, - .ident_nums = 1 - }, - { /* class_tid: 8, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 287, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 379, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 8, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 330, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 387, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 8, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 341, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 396, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 352, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 405, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 9, + .ident_start_idx = 13, .ident_nums = 1 }, - { /* class_tid: 9, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 353, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 406, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 10, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 366, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 419, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 10, - .ident_nums = 1 - }, - { /* class_tid: 9, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 369, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 420, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 11, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 9, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 412, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 428, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 11, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 9, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 423, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 437, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 11, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 434, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 446, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 11, - .ident_nums = 1 - }, - { /* class_tid: 10, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 435, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 447, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 12, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 448, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 460, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 12, - .ident_nums = 1 - }, - { /* class_tid: 10, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 451, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 461, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 13, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 10, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 494, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 469, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 13, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 10, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 505, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 478, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 13, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 516, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 487, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 13, - .ident_nums = 1 - }, - { /* class_tid: 11, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 517, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 488, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 14, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 530, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 501, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 14, - .ident_nums = 1 - }, - { /* class_tid: 11, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 533, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 502, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 15, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 11, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 576, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 510, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 15, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 11, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 587, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 519, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 15, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 598, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 528, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 15, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 611, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 541, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 16, - .ident_nums = 1 - }, - { /* class_tid: 12, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 614, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 542, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 17, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 12, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 657, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 550, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 17, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 12, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 668, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 559, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 17, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 679, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 568, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 17, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 692, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 581, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 18, - .ident_nums = 1 - }, - { /* class_tid: 13, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 695, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 582, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 19, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 13, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 738, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 590, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 19, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 13, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 749, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 599, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 19, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 760, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 608, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 19, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 773, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 621, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 20, - .ident_nums = 1 - }, - { /* class_tid: 14, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 776, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 622, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 21, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 14, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 819, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 630, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 21, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 14, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 830, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 639, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 21, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 841, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 648, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 21, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 854, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 661, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 22, - .ident_nums = 1 - }, - { /* class_tid: 15, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 857, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 662, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 23, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 15, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 900, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 670, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 23, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 15, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 911, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 679, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 23, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 922, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 688, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 23, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 935, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 701, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 24, - .ident_nums = 1 - }, - { /* class_tid: 16, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 938, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 702, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 25, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 16, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 981, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 710, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 25, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 16, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 992, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 719, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 25, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1003, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 728, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 25, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 1016, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 741, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 26, - .ident_nums = 1 - }, - { /* class_tid: 17, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1019, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 742, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 27, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 17, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 1062, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 750, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 27, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 17, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 1073, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 759, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 27, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 18, stingray, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_RX, - .result_start_idx = 768, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1084, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 769, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 27, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 1097, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 782, - .result_bit_size = 20, - .result_num_fields = 2, - .encap_num_fields = 0, - .ident_start_idx = 28, - .ident_nums = 2 - }, - { /* class_tid: 18, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1100, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 784, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 30, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 18, stingray, table: wm_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1143, - .blob_key_bit_size = 192, - .key_bit_size = 160, - .key_num_fields = 5, - .result_start_idx = 792, - .result_bit_size = 19, - .result_num_fields = 3, - .encap_num_fields = 0, - .ident_start_idx = 30, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1148, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 795, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 30, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 1161, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 808, - .result_bit_size = 20, - .result_num_fields = 2, - .encap_num_fields = 0, - .ident_start_idx = 31, - .ident_nums = 2 - }, - { /* class_tid: 19, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1164, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 810, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 33, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 19, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 1207, - .blob_key_bit_size = 112, - .key_bit_size = 112, - .key_num_fields = 8, - .result_start_idx = 818, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 33, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 19, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 1215, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 8, - .result_start_idx = 827, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 33, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1223, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 836, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 33, - .ident_nums = 1 - }, - { /* class_tid: 20, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1224, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 837, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 34, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1237, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 850, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 34, - .ident_nums = 1 - }, - { /* class_tid: 20, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1240, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 851, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 35, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 20, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1283, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 859, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 35, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 20, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1294, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 868, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 35, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1305, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 877, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 35, - .ident_nums = 1 - }, - { /* class_tid: 21, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1306, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 878, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 36, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1319, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 891, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 36, - .ident_nums = 1 - }, - { /* class_tid: 21, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1322, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 892, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 37, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 21, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1365, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 900, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 37, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 21, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1376, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 909, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 37, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1387, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 918, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 37, - .ident_nums = 1 - }, - { /* class_tid: 22, stingray, table: l2_cntxt_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1388, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 919, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 38, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1401, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 932, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 38, - .ident_nums = 1 - }, - { /* class_tid: 22, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1404, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 933, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 39, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 22, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1447, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 941, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 39, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 22, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1458, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 950, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 39, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1469, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 1, - .result_start_idx = 959, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 39, - .ident_nums = 1 - }, - { /* class_tid: 23, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1470, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 960, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 40, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1483, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 973, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 40, - .ident_nums = 1 - }, - { /* class_tid: 23, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1486, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 974, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 41, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 23, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1529, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 982, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 41, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 23, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1540, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 991, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 41, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1551, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 1000, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 41, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1564, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 1013, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 42, - .ident_nums = 1 - }, - { /* class_tid: 24, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1567, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 1014, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 43, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 24, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1610, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 7, - .result_start_idx = 1022, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 43, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 24, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1617, - .blob_key_bit_size = 104, - .key_bit_size = 104, - .key_num_fields = 7, - .result_start_idx = 1031, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 43, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1624, - .blob_key_bit_size = 171, - .key_bit_size = 171, - .key_num_fields = 13, - .result_start_idx = 1040, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 43, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1637, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 1053, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 44, - .ident_nums = 1 - }, - { /* class_tid: 25, stingray, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1640, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 1054, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 45, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 25, stingray, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1683, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 7, - .result_start_idx = 1062, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 45, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 25, stingray, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1690, - .blob_key_bit_size = 104, - .key_bit_size = 104, - .key_num_fields = 7, - .result_start_idx = 1071, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 45, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - } -}; - -struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = { - /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam_vfr_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, stingray, table: egr_l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, stingray, table: egr_l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, stingray, table: ing_l2_cntxt_dtagged_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, stingray, table: ing_l2_cntxt_stagged_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, stingray, table: egr_l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, stingray, table: ing_l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF6_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF6_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF6_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF6_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF6_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF6_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF6_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF6_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF6_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF6_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF6_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF7_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF7_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF7_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF7_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF7_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF7_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF7_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF7_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF15_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF15_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF15_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF16_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "t_ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "t_ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "t_ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "t_ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF17_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF18_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF18_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 18, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 18, stingray, table: wm_0 */ - { - .description = "wc_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "spare", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "others", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF19_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 19, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 19, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dst_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF19_IDX_I_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_HF19_IDX_T_VXLAN_VNI & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 19, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 339, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dst_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF19_IDX_I_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_HF19_IDX_T_VXLAN_VNI & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, stingray, table: l2_cntxt_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF24_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF24_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF24_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF24_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF24_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF24_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF24_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF24_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF24_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 351, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_eth_type", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF24_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_eth_type", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF24_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF25_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF25_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF25_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF25_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF25_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF25_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF25_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF25_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF25_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, stingray, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, stingray, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 351, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_eth_type", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF25_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, stingray, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_eth_type", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF25_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } -}; - -struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] = { - /* class_tid: 1, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 1, stingray, table: parif_def_lkup_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, stingray, table: parif_def_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, stingray, table: parif_def_err_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam_vfr_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: parif_def_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: parif_def_err_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, stingray, table: egr_int_vtag_encap_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x81, 0x00} - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "spare", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, stingray, table: egr_int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, stingray, table: egr_l2_cntxt_cache_0 */ - /* class_tid: 3, stingray, table: egr_l2_cntxt_tcam_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, stingray, table: ing_int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, stingray, table: ing_l2_cntxt_dtagged_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, stingray, table: ing_l2_cntxt_stagged_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, stingray, table: egr_l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_VF_FUNC_PARIF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 4, stingray, table: egr_parif_def_lkup_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, stingray, table: egr_parif_def_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, stingray, table: egr_parif_def_err_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, stingray, table: ing_int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 4, stingray, table: ing_l2_cntxt_tcam_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 5, stingray, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0005 >> 8) & 0xff, - 0x0005 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 6, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0005 >> 8) & 0xff, - 0x0005 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 7, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 8, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 9, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 10, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 11, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 12, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 13, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 14, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 15, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0031 >> 8) & 0xff, - 0x0031 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 16, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, stingray, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0031 >> 8) & 0xff, - 0x0031 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 17, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 259, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 313, + .result_bit_size = 62, + .result_num_fields = 4, + .encap_num_fields = 0 }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { /* class_tid: 6, stingray, table: parif_def_lkup_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 317, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0 }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + { /* class_tid: 6, stingray, table: parif_def_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 318, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0 }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { /* class_tid: 6, stingray, table: parif_def_err_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 319, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0 }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + { /* class_tid: 6, stingray, table: int_full_act_record.ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .result_start_idx = 320, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 260, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 346, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 14, + .ident_nums = 0 }, - /* class_tid: 17, stingray, table: int_em_0 */ + { /* class_tid: 7, stingray, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 359, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[] = { { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* class_tid: 18, stingray, table: int_flow_counter_tbl_0 */ { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + } +}; + +struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { + /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, stingray, table: profile_tcam.0 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, stingray, table: eem.ext_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 275, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 275, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, stingray, table: em.int_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, stingray, table: profile_tcam_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, stingray, table: profile_tcam.0 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, stingray, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, stingray, table: eem.ext_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 275, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 275, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, stingray, table: em.int_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[] = { + /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -21101,1089 +5064,1117 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "wc_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 18, stingray, table: profile_tcam_0 */ + /* class_tid: 1, stingray, table: profile_tcam.0 */ { .description = "wc_key_id", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "wc_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "em_key_mask", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x001b >> 8) & 0xff, - 0x001b & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (0x007d >> 8) & 0xff, + 0x007d & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_key_id", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_search_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 18, stingray, table: wm_0 */ - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ { - .description = "act_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", + .description = "profile_tcam_index", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ - { .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "wc_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff, + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 19, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, { - .description = "wc_profile_id", + .description = "wm_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_profile_id", + .description = "flow_sig_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 19, stingray, table: int_em_0 */ + /* class_tid: 1, stingray, table: eem.ext_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ext_flow_cntr", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "act_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "key_size", .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x006d >> 8) & 0xff, - 0x006d & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (0x00ad >> 8) & 0xff, + 0x00ad & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "reserved", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "strength", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 19, stingray, table: ext_em_0 */ + /* class_tid: 1, stingray, table: em.int_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ext_flow_cntr", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "key_size", .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x006d >> 8) & 0xff, - 0x006d & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "reserved", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "strength", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 20, stingray, table: l2_cntxt_tcam_0 */ + /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 20, stingray, table: profile_tcam_0 */ + /* class_tid: 2, stingray, table: profile_tcam.0 */ { .description = "wc_key_id", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "wc_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "em_key_mask", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (0x0079 >> 8) & 0xff, + 0x0079 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_key_id", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_search_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 2, stingray, table: profile_tcam_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .description = "wm_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "flow_sig_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 20, stingray, table: ext_em_0 */ + /* class_tid: 2, stingray, table: eem.ext_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ext_flow_cntr", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "act_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "key_size", .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (0x00ad >> 8) & 0xff, + 0x00ad & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "reserved", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "strength", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 20, stingray, table: int_em_0 */ + /* class_tid: 2, stingray, table: em.int_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ext_flow_cntr", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "key_size", .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "reserved", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "strength", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ + /* class_tid: 3, stingray, table: int_full_act_record.0 */ { - .description = "l2_cntxt_id", + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 21, stingray, table: l2_cntxt_tcam_0 */ + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ { - .description = "em_profile_id", + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 21, stingray, table: profile_tcam_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_profile_id", + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */ + { + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */ + { + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */ + { + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + /* class_tid: 4, stingray, table: int_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_key", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "wc_search_en", + .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "em_search_en", + .description = "pop_vlan", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "meter", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 21, stingray, table: ext_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "mirror", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "hit", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 21, stingray, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "parif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "allowed_pri", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "default_pri", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "default_tpid", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .description = "bd_act_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 22, stingray, table: l2_cntxt_0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -22192,1539 +6183,1323 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[] { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */ { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 22, stingray, table: profile_tcam_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 4, stingray, table: parif_def_lkup_arec_ptr.0 */ { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: parif_def_arec_ptr.0 */ { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, stingray, table: parif_def_err_arec_ptr.0 */ { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 5, stingray, table: int_vtag_encap_record.egr0 */ { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "ecv_l2_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 22, stingray, table: ext_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ecv_custom_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "ecv_valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x81, 0x00} }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, + .description = "vtag_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "vtag_de", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "spare", + .field_bit_size = 80, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 5, stingray, table: int_full_act_record.egr0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "age_enable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "agg_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 22, stingray, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "tl3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT >> 8) & 0xff, + BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "pop_vlan", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", + .description = "meter", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "mirror", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "hit", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, stingray, table: l2_cntxt_tcam_0 */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "reserved", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 23, stingray, table: profile_tcam_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 5, stingray, table: int_full_act_record.ing0 */ { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "age_enable", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_search_en", + .description = "rate_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "flow_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, stingray, table: ext_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "tcpflags_mir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "tcpflags_match", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, stingray, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "tl3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "pop_vlan", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "strength", + .description = "meter", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "mirror", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "hit", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, stingray, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0003 >> 8) & 0xff, - 0x0003 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 24, stingray, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0061 >> 8) & 0xff, - 0x0061 & 0xff, + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "parif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 24, stingray, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "allowed_pri", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "default_pri", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "default_tpid", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0061 >> 8) & 0xff, - 0x0061 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "bd_act_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .description = "byp_sp_lkup", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ + /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */ { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 25, stingray, table: profile_tcam_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 6, stingray, table: parif_def_lkup_arec_ptr.egr */ { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0003 >> 8) & 0xff, - 0x0003 & 0xff, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: parif_def_arec_ptr.egr */ { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: parif_def_err_arec_ptr.egr */ { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, stingray, table: int_full_act_record.ing */ { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "age_enable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 25, stingray, table: ext_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "rate_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "flow_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0061 >> 8) & 0xff, - 0x0061 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "reserved", + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "encap_ptr", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "tl3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 25, stingray, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "pop_vlan", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "meter", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "mirror", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0061 >> 8) & 0xff, - 0x0061 & 0xff, + .description = "drop", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */ + { + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "l2_byp_lkup_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "parif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } -}; - -struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { - /* class_tid: 1, stingray, table: l2_cntxt_cache_0 */ + .description = "allowed_pri", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "default_pri", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 2, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "default_tpid", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "bd_act_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 4, stingray, table: egr_l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "byp_sp_lkup", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 6, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 7, stingray, table: l2_cntxt_tcam_0 */ + /* class_tid: 7, stingray, table: int_full_act_record.0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 7, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "age_enable", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 8, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 8, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 9, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 9, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 10, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 10, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 11, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 11, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 12, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 12, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 13, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 13, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 14, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "l3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 14, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 15, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 15, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 16, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 16, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT >> 8) & 0xff, + BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 17, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "pop_vlan", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 17, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "meter", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 18, stingray, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "mirror", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 18, stingray, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "drop", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "hit", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 19, stingray, table: l2_cntxt_tcam_0 */ + { + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } +}; + +struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { + /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 19, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 8, + .ident_bit_pos = 58 }, { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0, + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_bit_pos = 32 }, - /* class_tid: 20, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "em_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 }, - /* class_tid: 20, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 1, stingray, table: profile_tcam.0 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 28 }, - /* class_tid: 21, stingray, table: l2_cntxt_cache_0 */ + /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 21, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 2, stingray, table: profile_tcam_cache.rd */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_bit_pos = 32 }, - /* class_tid: 22, stingray, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 8, + .ident_bit_pos = 58 }, - /* class_tid: 22, stingray, table: profile_tcam_cache_0 */ { .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - /* class_tid: 23, stingray, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 }, - /* class_tid: 23, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 2, stingray, table: profile_tcam.0 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 28 }, - /* class_tid: 24, stingray, table: l2_cntxt_tcam_0 */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 24, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_bit_pos = 42 }, - /* class_tid: 25, stingray, table: l2_cntxt_tcam_0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 25, stingray, table: profile_tcam_cache_0 */ + /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */ { - .description = "em_profile_id", + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index bb48ad284a..30a71def95 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,574 +3,50 @@ * All rights reserved. */ -/* date: Thu Oct 15 17:28:37 2020 */ +/* date: Mon Nov 23 17:33:02 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" -#include "ulp_rte_parser.h" #include "ulp_template_db_tbl.h" -uint32_t ulp_act_prop_map_table[] = { - [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE, - [BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM] = - BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM, - [BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] = - BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM, - [BNXT_ULP_ACT_PROP_IDX_PORT_ID] = - BNXT_ULP_ACT_PROP_SZ_PORT_ID, - [BNXT_ULP_ACT_PROP_IDX_VNIC] = - BNXT_ULP_ACT_PROP_SZ_VNIC, - [BNXT_ULP_ACT_PROP_IDX_VPORT] = - BNXT_ULP_ACT_PROP_SZ_VPORT, - [BNXT_ULP_ACT_PROP_IDX_MARK] = - BNXT_ULP_ACT_PROP_SZ_MARK, - [BNXT_ULP_ACT_PROP_IDX_COUNT] = - BNXT_ULP_ACT_PROP_SZ_COUNT, - [BNXT_ULP_ACT_PROP_IDX_METER] = - BNXT_ULP_ACT_PROP_SZ_METER, - [BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC] = - BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC, - [BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST] = - BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST, - [BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN] = - BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN, - [BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP] = - BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP, - [BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID] = - BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID, - [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC] = - BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC, - [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST] = - BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST, - [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC] = - BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC, - [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST] = - BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST, - [BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC] = - BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC, - [BNXT_ULP_ACT_PROP_IDX_SET_TP_DST] = - BNXT_ULP_ACT_PROP_SZ_SET_TP_DST, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN, - [BNXT_ULP_ACT_PROP_IDX_JUMP] = - BNXT_ULP_ACT_PROP_SZ_JUMP, - [BNXT_ULP_ACT_PROP_IDX_LAST] = - BNXT_ULP_ACT_PROP_SZ_LAST -}; - -uint8_t ulp_glb_field_tbl[211] = { - [0] = 0, - [1] = 0, - [2] = 0, - [3] = 0, - [4] = 0, - [5] = 0, - [6] = 0, - [7] = 0, - [8] = 0, - [9] = 0, - [10] = 0, - [11] = 0, - [12] = 0, - [13] = 0, - [14] = 0, - [15] = 0, - [16] = 0, - [17] = 0, - [18] = 0, - [19] = 0, - [20] = 0, - [21] = 0, - [22] = 0, - [23] = 0, - [24] = 0, - [25] = 0, - [26] = 0, - [27] = 0, - [28] = 0, - [29] = 0, - [30] = 0, - [31] = 0, - [32] = 0, - [33] = 0, - [34] = 0, - [35] = 0, - [36] = 0, - [37] = 0, - [38] = 0, - [39] = 0, - [40] = 0, - [41] = 0, - [42] = 0, - [43] = 0, - [44] = 0, - [45] = 0, - [46] = 0, - [47] = 0, - [48] = 0, - [49] = 0, - [50] = 0, - [51] = 0, - [52] = 0, - [53] = 0, - [54] = 0, - [55] = 0, - [56] = 0, - [57] = 0, - [58] = 0, - [59] = 0, - [60] = 0, - [61] = 0, - [62] = 0, - [63] = 0, - [64] = 0, - [65] = 0, - [66] = 0, - [67] = 0, - [68] = 0, - [69] = 0, - [70] = 0, - [71] = 0, - [72] = 0, - [73] = 0, - [74] = 0, - [75] = 0, - [76] = 0, - [77] = 0, - [78] = 0, - [79] = 0, - [80] = 0, - [81] = 0, - [82] = 0, - [83] = 0, - [84] = 0, - [85] = 0, - [86] = 0, - [87] = 0, - [88] = 0, - [89] = 0, - [90] = 0, - [91] = 0, - [92] = 0, - [93] = 0, - [94] = 0, - [95] = 0, - [96] = 0, - [97] = 0, - [98] = 0, - [99] = 0, - [100] = 0, - [101] = 0, - [102] = 0, - [103] = 0, - [104] = 0, - [105] = 0, - [106] = 0, - [107] = 0, - [108] = 0, - [109] = 0, - [110] = 0, - [111] = 0, - [112] = 0, - [113] = 0, - [114] = 0, - [115] = 0, - [116] = 0, - [117] = 0, - [118] = 0, - [119] = 0, - [120] = 0, - [121] = 0, - [122] = 0, - [123] = 0, - [124] = 0, - [125] = 0, - [126] = 0, - [127] = 0, - /* svif.index */ - [128] = 1, - /* o_eth.dmac */ - [129] = 2, - [130] = 0, - /* o_eth.smac */ - [131] = 3, - [132] = 0, - /* o_eth.type */ - [133] = 4, - [134] = 0, - /* o_ipv4.ver */ - [135] = 11, - [136] = 0, - /* o_ipv4.tos */ - [137] = 12, - [138] = 0, - /* o_ipv4.len */ - [139] = 13, - [140] = 0, - /* o_ipv4.frag_id */ - [141] = 14, - [142] = 0, - /* o_ipv4.frag_off */ - [143] = 15, - [144] = 0, - /* o_ipv4.ttl */ - [145] = 16, - [146] = 0, - /* o_ipv4.proto_id */ - [147] = 17, - [148] = 0, - /* o_ipv4.csum */ - [149] = 18, - [150] = 0, - /* o_ipv4.src_addr */ - [151] = 19, - [152] = 0, - /* o_ipv4.dst_addr */ - [153] = 20, - [154] = 0, - [155] = 0, - [156] = 0, - [157] = 0, - [158] = 0, - [159] = 0, - [160] = 0, - [161] = 0, - [162] = 0, - [163] = 0, - [164] = 0, - [165] = 0, - [166] = 0, - [167] = 0, - [168] = 0, - [169] = 0, - [170] = 0, - [171] = 0, - [172] = 0, - [173] = 0, - [174] = 0, - /* o_tcp.src_port */ - [175] = 21, - [176] = 0, - /* o_tcp.dst_port */ - [177] = 22, - [178] = 0, - /* o_tcp.sent_seq */ - [179] = 23, - [180] = 0, - /* o_tcp.recv_ack */ - [181] = 24, - [182] = 0, - /* o_tcp.data_off */ - [183] = 25, - [184] = 0, - /* o_tcp.tcp_flags */ - [185] = 26, - [186] = 0, - /* o_tcp.rx_win */ - [187] = 27, - [188] = 0, - /* o_tcp.csum */ - [189] = 28, - [190] = 0, - /* o_tcp.urp */ - [191] = 29, - [192] = 0, - [193] = 0, - [194] = 0, - [195] = 0, - [196] = 0, - [197] = 0, - [198] = 0, - [199] = 0, - [200] = 0, - /* oo_vlan.cfi_pri */ - [201] = 5, - /* oi_vlan.cfi_pri */ - [202] = 8, - [203] = 0, - [204] = 0, - /* oo_vlan.vid */ - [205] = 6, - /* oi_vlan.vid */ - [206] = 9, - [207] = 0, - [208] = 0, - /* oo_vlan.type */ - [209] = 7, - /* oi_vlan.type */ - [210] = 10 -}; - -/* - * This structure has to be indexed based on the rte_flow_action_type that is - * part of DPDK. The below array is list of parsing functions for each of the - * flow actions that are supported. - */ -struct bnxt_ulp_rte_act_info ulp_act_info[] = { - [RTE_FLOW_ACTION_TYPE_END] = { - .act_type = BNXT_ULP_ACT_TYPE_END, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_VOID] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_void_act_handler - }, - [RTE_FLOW_ACTION_TYPE_PASSTHRU] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_JUMP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_jump_act_handler - }, - [RTE_FLOW_ACTION_TYPE_MARK] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_mark_act_handler - }, - [RTE_FLOW_ACTION_TYPE_FLAG] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_QUEUE] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_DROP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_drop_act_handler - }, - [RTE_FLOW_ACTION_TYPE_COUNT] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_count_act_handler - }, - [RTE_FLOW_ACTION_TYPE_RSS] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_rss_act_handler - }, - [RTE_FLOW_ACTION_TYPE_PF] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_pf_act_handler - }, - [RTE_FLOW_ACTION_TYPE_VF] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vf_act_handler - }, - [RTE_FLOW_ACTION_TYPE_PHY_PORT] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_phy_port_act_handler - }, - [RTE_FLOW_ACTION_TYPE_PORT_ID] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_port_id_act_handler - }, - [RTE_FLOW_ACTION_TYPE_METER] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SECURITY] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_of_pop_vlan_act_handler - }, - [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_of_push_vlan_act_handler - }, - [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_of_set_vlan_vid_act_handler - }, - [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_of_set_vlan_pcp_act_handler - }, - [RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vxlan_encap_act_handler - }, - [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vxlan_decap_act_handler - }, - [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_RAW_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_set_ipv4_src_act_handler - }, - [RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_set_ipv4_dst_act_handler - }, - [RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_set_tp_src_act_handler - }, - [RTE_FLOW_ACTION_TYPE_SET_TP_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_set_tp_dst_act_handler - }, - [RTE_FLOW_ACTION_TYPE_MAC_SWAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_DEC_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_dec_ttl_act_handler - }, - [RTE_FLOW_ACTION_TYPE_SET_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - } -}; - -/* Specifies parameters for the generic tables */ +/* Specifies parameters for the cache and shared tables */ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | - TF_DIR_RX] = { - .result_num_entries = 16384, - .result_byte_size = 6, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + BNXT_ULP_DIRECTION_INGRESS] = { + .result_num_entries = 16384, + .result_num_bytes = 16, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | - TF_DIR_TX] = { - .result_num_entries = 16384, - .result_byte_size = 6, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE - + BNXT_ULP_DIRECTION_EGRESS] = { + .result_num_entries = 16384, + .result_num_bytes = 16, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | - TF_DIR_RX] = { - .result_num_entries = 16384, - .result_byte_size = 6, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + BNXT_ULP_DIRECTION_INGRESS] = { + .result_num_entries = 16384, + .result_num_bytes = 16, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | - TF_DIR_TX] = { - .result_num_entries = 16384, - .result_byte_size = 6, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + BNXT_ULP_DIRECTION_EGRESS] = { + .result_num_entries = 16384, + .result_num_bytes = 16, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .result_num_entries = 16, + .result_num_bytes = 16, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .result_num_entries = 16, + .result_num_bytes = 16, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; @@ -578,15 +54,27 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { const struct bnxt_ulp_template_device_tbls ulp_template_stingray_tbls[] = { [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { .tmpl_list = ulp_stingray_class_tmpl_list, + .tmpl_list_size = ULP_STINGRAY_CLASS_TMPL_LIST_SIZE, .tbl_list = ulp_stingray_class_tbl_list, - .key_field_list = ulp_stingray_class_key_field_list, + .tbl_list_size = ULP_STINGRAY_CLASS_TBL_LIST_SIZE, + .key_info_list = ulp_stingray_class_key_info_list, + .key_info_list_size = ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE, + .ident_list = ulp_stingray_class_ident_list, + .ident_list_size = ULP_STINGRAY_CLASS_IDENT_LIST_SIZE, + .cond_list = ulp_stingray_class_cond_list, + .cond_list_size = ULP_STINGRAY_CLASS_COND_LIST_SIZE, .result_field_list = ulp_stingray_class_result_field_list, - .ident_list = ulp_stingray_class_ident_list + .result_field_list_size = ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE }, [BNXT_ULP_TEMPLATE_TYPE_ACTION] = { .tmpl_list = ulp_stingray_act_tmpl_list, + .tmpl_list_size = ULP_STINGRAY_ACT_TMPL_LIST_SIZE, .tbl_list = ulp_stingray_act_tbl_list, - .result_field_list = ulp_stingray_act_result_field_list + .tbl_list_size = ULP_STINGRAY_ACT_TBL_LIST_SIZE, + .cond_list = ulp_stingray_act_cond_list, + .cond_list_size = ULP_STINGRAY_ACT_COND_LIST_SIZE, + .result_field_list = ulp_stingray_act_result_field_list, + .result_field_list_size = ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE } }; @@ -594,15 +82,27 @@ const struct bnxt_ulp_template_device_tbls ulp_template_stingray_tbls[] = { const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { .tmpl_list = ulp_wh_plus_class_tmpl_list, + .tmpl_list_size = ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE, .tbl_list = ulp_wh_plus_class_tbl_list, - .key_field_list = ulp_wh_plus_class_key_field_list, + .tbl_list_size = ULP_WH_PLUS_CLASS_TBL_LIST_SIZE, + .key_info_list = ulp_wh_plus_class_key_info_list, + .key_info_list_size = ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE, + .ident_list = ulp_wh_plus_class_ident_list, + .ident_list_size = ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE, + .cond_list = ulp_wh_plus_class_cond_list, + .cond_list_size = ULP_WH_PLUS_CLASS_COND_LIST_SIZE, .result_field_list = ulp_wh_plus_class_result_field_list, - .ident_list = ulp_wh_plus_class_ident_list + .result_field_list_size = ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE }, [BNXT_ULP_TEMPLATE_TYPE_ACTION] = { .tmpl_list = ulp_wh_plus_act_tmpl_list, + .tmpl_list_size = ULP_WH_PLUS_ACT_TMPL_LIST_SIZE, .tbl_list = ulp_wh_plus_act_tbl_list, - .result_field_list = ulp_wh_plus_act_result_field_list + .tbl_list_size = ULP_WH_PLUS_ACT_TBL_LIST_SIZE, + .cond_list = ulp_wh_plus_act_cond_list, + .cond_list_size = ULP_WH_PLUS_ACT_COND_LIST_SIZE, + .result_field_list = ulp_wh_plus_act_result_field_list, + .result_field_list_size = ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE } }; @@ -653,265 +153,237 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { [0] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, [1] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_TX }, [2] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .direction = TF_DIR_TX }, [3] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, [4] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_TX }, [5] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, .direction = TF_DIR_RX }, [6] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_RX }, [7] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_TX } }; -/* - * This table has to be indexed based on the rte_flow_item_type that is part of - * DPDK. The below array is list of parsing functions for each of the flow items - * that are supported. - */ -struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { - [RTE_FLOW_ITEM_TYPE_END] = { - .hdr_type = BNXT_ULP_HDR_TYPE_END, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_VOID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_void_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_INVERT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ANY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_PF] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_pf_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_VF] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vf_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_PHY_PORT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_phy_port_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_PORT_ID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_port_id_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_RAW] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_eth_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_VLAN] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vlan_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_IPV4] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_ipv4_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_IPV6] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_ipv6_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_ICMP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_UDP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_udp_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_TCP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_tcp_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_SCTP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_VXLAN] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vxlan_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_E_TAG] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_NVGRE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_MPLS] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GRE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_FUZZY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GTP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GTPC] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GTPU] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ESP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GENEVE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_IPV6_EXT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_MARK] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_META] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GRE_KEY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GTP_PSC] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_PPPOES] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_PPPOED] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_NSH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_IGMP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_AH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_HIGIG2] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL +/* Lists global action records */ +uint32_t ulp_glb_template_tbl[] = { + BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC +}; + +/* Provides act_bitmask */ +struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = { + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .act_bitmask = BNXT_ULP_ACTION_BIT_SHARED_SAMPLE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .act_bitmask = BNXT_ULP_ACTION_BIT_SHARED_SAMPLE } }; -/* - * The parser uses this table to map vtags_num to CFA encapsulation VTAG - * encoding. It then takes the result and stores it in act_prop[encap_vtag_type] - */ -uint32_t bnxt_ulp_encap_vtag_map[] = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI +uint32_t ulp_act_prop_map_table[] = { + [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE, + [BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM] = + BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM, + [BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] = + BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM, + [BNXT_ULP_ACT_PROP_IDX_PORT_ID] = + BNXT_ULP_ACT_PROP_SZ_PORT_ID, + [BNXT_ULP_ACT_PROP_IDX_VNIC] = + BNXT_ULP_ACT_PROP_SZ_VNIC, + [BNXT_ULP_ACT_PROP_IDX_VPORT] = + BNXT_ULP_ACT_PROP_SZ_VPORT, + [BNXT_ULP_ACT_PROP_IDX_MARK] = + BNXT_ULP_ACT_PROP_SZ_MARK, + [BNXT_ULP_ACT_PROP_IDX_COUNT] = + BNXT_ULP_ACT_PROP_SZ_COUNT, + [BNXT_ULP_ACT_PROP_IDX_METER] = + BNXT_ULP_ACT_PROP_SZ_METER, + [BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC] = + BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC, + [BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST] = + BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST, + [BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN] = + BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN, + [BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP] = + BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP, + [BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID] = + BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID, + [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC] = + BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC, + [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST] = + BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST, + [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC] = + BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC, + [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST] = + BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST, + [BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC] = + BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC, + [BNXT_ULP_ACT_PROP_IDX_SET_TP_DST] = + BNXT_ULP_ACT_PROP_SZ_SET_TP_DST, + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0] = + BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0, + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1] = + BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1, + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2] = + BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2, + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3] = + BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3, + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4] = + BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4, + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5] = + BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5, + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6] = + BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6, + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7] = + BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_IP, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP, + [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] = + BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN, + [BNXT_ULP_ACT_PROP_IDX_JUMP] = + BNXT_ULP_ACT_PROP_SZ_JUMP, + [BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE] = + BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE, + [BNXT_ULP_ACT_PROP_IDX_LAST] = + BNXT_ULP_ACT_PROP_SZ_LAST }; -/* Lists global action records */ -uint32_t ulp_glb_template_tbl[] = { - BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC +uint8_t ulp_glb_field_tbl[] = { + [2048] = 0, + [2049] = 1, + [2050] = 2, + [2052] = 3, + [2054] = 4, + [2056] = 5, + [2058] = 6, + [2060] = 7, + [2062] = 8, + [2064] = 9, + [2066] = 10, + [2068] = 11, + [2070] = 12, + [2072] = 13, + [2074] = 14, + [2102] = 15, + [2104] = 16, + [2106] = 17, + [2108] = 18, + [2110] = 19, + [2112] = 20, + [2114] = 21, + [2116] = 22, + [2118] = 23, + [2176] = 0, + [2177] = 1, + [2178] = 2, + [2180] = 3, + [2182] = 4, + [2184] = 8, + [2186] = 9, + [2188] = 10, + [2190] = 11, + [2192] = 12, + [2194] = 13, + [2196] = 14, + [2198] = 15, + [2200] = 16, + [2202] = 17, + [2230] = 18, + [2232] = 19, + [2234] = 20, + [2236] = 21, + [2238] = 22, + [2240] = 23, + [2242] = 24, + [2244] = 25, + [2246] = 26, + [2256] = 5, + [2260] = 6, + [2264] = 7, + [4352] = 0, + [4353] = 1, + [4354] = 2, + [4356] = 3, + [4358] = 4, + [4360] = 8, + [4362] = 9, + [4364] = 10, + [4366] = 11, + [4368] = 12, + [4370] = 13, + [4372] = 14, + [4374] = 15, + [4376] = 16, + [4378] = 17, + [4406] = 18, + [4408] = 19, + [4410] = 20, + [4412] = 21, + [4414] = 22, + [4416] = 23, + [4418] = 24, + [4420] = 25, + [4422] = 26, + [4432] = 5, + [4436] = 6, + [4440] = 7 }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h index dbfcc46164..93b0afbf25 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h @@ -16,10 +16,10 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[]; extern struct -bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[]; +bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[]; extern struct -bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[]; +bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[]; extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[]; @@ -28,7 +28,13 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[]; extern struct -bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[]; +bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[]; + +extern struct +bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[]; + +extern struct +bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[]; /* STINGRAY template table declarations */ extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[]; @@ -36,10 +42,10 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[]; extern struct -bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[]; +bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[]; extern struct -bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]; +bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[]; extern struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[]; @@ -48,7 +54,13 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[]; extern struct -bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[]; +bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[]; + +extern struct +bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[]; + +extern struct +bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[]; extern uint8_t ulp_glb_field_tbl[]; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 3c16d8177d..69cc7f33f9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,3358 +3,242 @@ * All rights reserved. */ -/* date: Thu Oct 15 17:28:37 2020 */ +/* date: Wed Nov 18 12:19:40 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" -#include "ulp_rte_parser.h" +#include "ulp_template_db_tbl.h" /* Mapper templates for header act list */ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { - /* act-ing-[dec_ttl, count, nat]:1 */ /* act_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 0 - }, - /* act-ing-[drop, pop_vlan, push_vlan, dec_ttl, count, vxlan_decap]:2 */ - /* act_tid: 2, wh_plus, ingress */ - [2] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 3, - .start_tbl_idx = 6 - }, - /* act-ing-[mark, rss, count, pop_vlan, vxlan_decap]:3 */ - /* act_tid: 3, wh_plus, ingress */ - [3] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 3, - .start_tbl_idx = 9 - }, - /* act_egr-[vxlan_encap, count]:4 */ - /* act_tid: 4, wh_plus, egress */ - [4] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 12 - }, - /* act-egr-[dec_ttl, count, nat]:5 */ - /* act_tid: 5, wh_plus, egress */ - [5] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 18 - }, - /* act-egr-[drop, push_vlan, dec_ttl, count]:6 */ - /* act_tid: 6, wh_plus, egress */ - [6] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 24 + .num_tbls = 4, + .start_tbl_idx = 0, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 0, + .cond_nums = 0 } } }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { - { /* act_tid: 1, wh_plus, table: int_flow_counter_tbl_0 */ + { /* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 0, .result_bit_size = 64, .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .encap_num_fields = 0 }, - { /* act_tid: 1, wh_plus, table: int_act_modify_ipv4_src_0 */ + { /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, .direction = TF_DIR_RX, - .result_start_idx = 1, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 1, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 - }, - { /* act_tid: 1, wh_plus, table: int_act_modify_ipv4_dst_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, - .direction = TF_DIR_RX, - .result_start_idx = 2, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 - }, - { /* act_tid: 1, wh_plus, table: int_encap_mac_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .result_start_idx = 3, + .result_start_idx = 1, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR - }, - { /* act_tid: 1, wh_plus, table: ext_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .result_start_idx = 15, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .encap_num_fields = 12 }, - { /* act_tid: 1, wh_plus, table: int_full_act_record_0 */ + { /* act_tid: 1, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .result_start_idx = 41, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 2, wh_plus, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_RX, - .result_start_idx = 67, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* act_tid: 2, wh_plus, table: ext_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .direction = TF_DIR_RX, - .result_start_idx = 68, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 2, wh_plus, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .result_start_idx = 94, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 3, wh_plus, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_RX, - .result_start_idx = 120, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* act_tid: 3, wh_plus, table: ext_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .result_start_idx = 121, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 3, wh_plus, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .result_start_idx = 147, + .result_start_idx = 13, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 4, wh_plus, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_TX, - .result_start_idx = 173, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* act_tid: 4, wh_plus, table: int_sp_smac_ipv4_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG, - .direction = TF_DIR_TX, - .result_start_idx = 174, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 3, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR - }, - { /* act_tid: 4, wh_plus, table: int_sp_smac_ipv6_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG, - .direction = TF_DIR_TX, - .result_start_idx = 177, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 3, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR - }, - { /* act_tid: 4, wh_plus, table: int_tun_encap_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_TX, - .result_start_idx = 180, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .encap_num_fields = 0 }, - { /* act_tid: 4, wh_plus, table: ext_full_act_record_0 */ + { /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .result_start_idx = 192, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 4, wh_plus, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .result_start_idx = 230, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 5, wh_plus, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_TX, - .result_start_idx = 256, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* act_tid: 5, wh_plus, table: int_act_modify_ipv4_src_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, - .direction = TF_DIR_TX, - .result_start_idx = 257, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 - }, - { /* act_tid: 5, wh_plus, table: int_act_modify_ipv4_dst_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, - .direction = TF_DIR_TX, - .result_start_idx = 258, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 - }, - { /* act_tid: 5, wh_plus, table: int_encap_mac_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .result_start_idx = 259, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR - }, - { /* act_tid: 5, wh_plus, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .result_start_idx = 271, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 5, wh_plus, table: ext_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .result_start_idx = 297, + .result_start_idx = 39, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 11, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 6, wh_plus, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .encap_num_fields = 0 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { + { .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_TX, - .result_start_idx = 334, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 + .cond_operand = BNXT_ULP_ACTION_BIT_COUNT }, - { /* act_tid: 6, wh_plus, table: int_vtag_encap_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + { .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, - .direction = TF_DIR_TX, - .result_start_idx = 335, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 - }, - { /* act_tid: 6, wh_plus, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .result_start_idx = 347, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 6, wh_plus, table: ext_full_act_record_no_tag_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, - .direction = TF_DIR_TX, - .result_start_idx = 373, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* act_tid: 6, wh_plus, table: ext_full_act_record_one_tag_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, - .direction = TF_DIR_TX, - .result_start_idx = 399, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 11, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN } }; - -struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { - /* act_tid: 1, wh_plus, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 1, wh_plus, table: int_act_modify_ipv4_src_0 */ - { - .description = "ipv4_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 1, wh_plus, table: int_act_modify_ipv4_dst_0 */ - { - .description = "ipv4_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 1, wh_plus, table: int_encap_mac_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L2_EN_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "spare", - .field_bit_size = 80, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 1, wh_plus, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 1, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 2, wh_plus, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 2, wh_plus, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 2, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 3, wh_plus, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 3, wh_plus, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 3, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 4, wh_plus, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 4, wh_plus, table: int_sp_smac_ipv4_0 */ - { - .description = "smac", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 4, wh_plus, table: int_sp_smac_ipv6_0 */ - { - .description = "smac", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 4, wh_plus, table: int_tun_encap_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_l2_dmac", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_vtag", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_ip", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_udp", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_tun", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 4, wh_plus, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_l2_dmac", - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_vtag", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_ip", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_udp", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "encap_tun", - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 4, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 5, wh_plus, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 5, wh_plus, table: int_act_modify_ipv4_src_0 */ - { - .description = "ipv4_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 5, wh_plus, table: int_act_modify_ipv4_dst_0 */ - { - .description = "ipv4_addr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* act_tid: 5, wh_plus, table: int_encap_mac_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L2_EN_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "spare", - .field_bit_size = 80, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 5, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 5, wh_plus, table: ext_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST, - .result_operand = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = {0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L2_EN_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 6, wh_plus, table: int_flow_counter_tbl_0 */ - { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 6, wh_plus, table: int_vtag_encap_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "spare", - .field_bit_size = 80, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* act_tid: 6, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, + +struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { + /* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */ { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "count", + .field_bit_size = 64, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "tl3_rdir", + .description = "ecv_custom_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l3_ttl_dec", + .description = "ecv_valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", + .description = "vtag_vid", .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", + .description = "vtag_de", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "spare", + .field_bit_size = 80, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* act_tid: 6, wh_plus, table: ext_full_act_record_no_tag_0 */ + /* act_tid: 1, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "age_enable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, @@ -3366,75 +250,110 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .description = "tcpflags_key", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "tcp_dst_port", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "src_ip_ptr", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "tcp_src_port", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "meter_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3443,8 +362,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3453,38 +372,60 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pop_vlan", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "meter", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "mirror", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, @@ -3495,37 +436,47 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* act_tid: 6, wh_plus, table: ext_full_act_record_one_tag_0 */ + { + .description = "hit", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "age_enable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, @@ -3539,73 +490,113 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "tcp_dst_port", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "src_ip_ptr", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "tcp_src_port", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "meter_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3614,8 +605,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3624,23 +615,35 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, + .field_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, + .field_operand = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pop_vlan", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, @@ -3654,18 +657,18 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "mirror", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, + .field_operand = { ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, @@ -3675,81 +678,5 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index d1a9a7e092..0bce60d4e3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,21189 +3,5059 @@ * All rights reserved. */ -/* date: Thu Oct 15 17:28:37 2020 */ +/* date: Mon Nov 23 17:33:02 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" -#include "ulp_rte_parser.h" +#include "ulp_template_db_tbl.h" /* Mapper templates for header class list */ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { - /* default-vfr-[port_to_vs]:1 */ /* class_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 0 + .start_tbl_idx = 0, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 0, + .cond_nums = 0 } }, - /* default-vfr-[vs_to_port]:2 */ - /* class_tid: 2, wh_plus, egress */ + /* class_tid: 2, wh_plus, ingress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 7, - .start_tbl_idx = 6 + .num_tbls = 6, + .start_tbl_idx = 6, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 2, + .cond_nums = 0 } }, - /* default-vfr-[vfrep_to_vf]:3 */ - /* class_tid: 3, wh_plus, egress */ + /* class_tid: 3, wh_plus, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 7, - .start_tbl_idx = 13 + .num_tbls = 6, + .start_tbl_idx = 12, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 4, + .cond_nums = 0 } }, - /* default-vfr-[vf_to_vfrep]:4 */ /* class_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 7, - .start_tbl_idx = 20 + .num_tbls = 8, + .start_tbl_idx = 18, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 4, + .cond_nums = 0 } }, - /* default-egr-[loopback_action_rec]:5 */ /* class_tid: 5, wh_plus, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 1, - .start_tbl_idx = 27 + .num_tbls = 7, + .start_tbl_idx = 26, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 10, + .cond_nums = 0 } }, - /* class-ing-em-[eth, (vlan), ipv4]-[smac, dmac, (vid)]:6 */ - /* class_tid: 6, wh_plus, ingress */ + /* class_tid: 6, wh_plus, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 28 + .num_tbls = 7, + .start_tbl_idx = 33, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 10, + .cond_nums = 0 } }, - /* class-ing-em-[eth, (vlan), ipv6]-[smac, dmac, (vid)]:7 */ - /* class_tid: 7, wh_plus, ingress */ + /* class_tid: 7, wh_plus, egress */ [7] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 33 - }, - /* class-ing-em-[eth, ipv4, udp]-[sip, dip, sp, dp]:8 */ - /* class_tid: 8, wh_plus, ingress */ - [8] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 38 - }, - /* class-ing-em-[eth, ipv4, tcp]-[sip, dip, sp, dp]:9 */ - /* class_tid: 9, wh_plus, ingress */ - [9] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 44 - }, - /* class-ing-em-[eth,ipv6, udp]-[sip, dip, sp, dp]:10 */ - /* class_tid: 10, wh_plus, ingress */ - [10] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 50 - }, - /* class-ing-em-[eth, ipv6, tcp]-[sip, dip, sp, dp]:11 */ - /* class_tid: 11, wh_plus, ingress */ - [11] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 56 - }, - /* class-ing-em-[eth, (vlan), ipv4, udp]-[dmac, (vid), sip, dip, sp, dp]:12 */ - /* class_tid: 12, wh_plus, ingress */ - [12] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 62 - }, - /* class-ing-em-[eth, (vlan), ipv4, tcp]-[dmac, (vid), sip, dip, sp, dp]:13 */ - /* class_tid: 13, wh_plus, ingress */ - [13] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 67 + .num_tbls = 1, + .start_tbl_idx = 40, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 10, + .cond_nums = 0 } + } +}; + +struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { + { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 0, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 0, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 0, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 0, + .ident_nums = 1 }, - /* class-ing-em-[eth, (vlan), ipv6, udp]-[dmac, (vid), sip, dip, sp, dp]:14 */ - /* class_tid: 14, wh_plus, ingress */ - [14] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 72 + { /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 0, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 13, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 1, + .ident_nums = 3 }, - /* class-ing-em-[eth, (vlan), ipv6, tcp]-[dmac, (vid), sip, dip, sp, dp]:15 */ - /* class_tid: 15, wh_plus, ingress */ - [15] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 77 + { /* class_tid: 1, wh_plus, table: profile_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 16, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 13, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 4, + .ident_nums = 1 }, - /* class-ing-em-[eth, (vlan), ipv4, udp, vxlan]-[dmac, (vid), dip, dp]:16 */ - /* class_tid: 16, wh_plus, ingress */ - [16] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 82 + { /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 1, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 59, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 21, + .result_bit_size = 66, + .result_num_fields = 5, + .encap_num_fields = 0 }, - /* class-ing-em-[eth, (vlan), ipv6, udp, vxlan]-[t_dmac, (vid), t_dip, t_dp]:17 */ - /* class_tid: 17, wh_plus, ingress */ - [17] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 87 + { /* class_tid: 1, wh_plus, table: eem.ext_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 62, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 10, + .result_start_idx = 26, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 }, - /* class-ing-em-f1-[eth, ipv4, udp, vxlan]-[t_dmac]:18 */ - /* class_tid: 18, wh_plus, ingress */ - [18] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 92 + { /* class_tid: 1, wh_plus, table: em.int_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 72, + .blob_key_bit_size = 176, + .key_bit_size = 176, + .key_num_fields = 10, + .result_start_idx = 35, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 }, - /* class-ing-em-f2-[ipv4, udp, vxlan]-[vni, i_dmac]:19 */ - /* class_tid: 19, wh_plus, ingress */ - [19] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 97 + { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 82, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 44, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 5, + .ident_nums = 1 }, - /* class-egr-em-[eth, ipv4, udp]-[sip, dip, sp, dp]:20 */ - /* class_tid: 20, wh_plus, egress */ - [20] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 102 + { /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 95, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 6, + .ident_nums = 3 }, - /* class-egr-em-[eth, ipv4, tcp]-[sip, dip, sp, dp]:21 */ - /* class_tid: 21, wh_plus, egress */ - [21] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 108 + { /* class_tid: 2, wh_plus, table: profile_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 2, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 98, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 57, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 9, + .ident_nums = 1 }, - /* class-egr-em-[eth-ipv6-udp]-[sip-dip-sp-dp]:22 */ - /* class_tid: 22, wh_plus, egress */ - [22] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 114 + { /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 3, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 141, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 65, + .result_bit_size = 66, + .result_num_fields = 5, + .encap_num_fields = 0 }, - /* class-egr-em-[eth, ipv6, tcp]-[sip, dip, sp, dp]:23 */ - /* class_tid: 23, wh_plus, egress */ - [23] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 120 + { /* class_tid: 2, wh_plus, table: eem.ext_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 144, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 10, + .result_start_idx = 70, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 }, - /* class-egr-em-[eth, (vlan), ipv4]-[smac, dmac, type]:24 */ - /* class_tid: 24, wh_plus, egress */ - [24] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 126 + { /* class_tid: 2, wh_plus, table: em.int_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 154, + .blob_key_bit_size = 176, + .key_bit_size = 176, + .key_num_fields = 10, + .result_start_idx = 79, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 }, - /* class-egr-em-[eth, (vlan), ipv6]-[smac, dmac, type]:25 */ - /* class_tid: 25, wh_plus, egress */ - [25] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 131 - } -}; - -struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { - { /* class_tid: 1, wh_plus, table: int_full_act_record_0 */ + { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .result_start_idx = 0, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 88, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 0, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 26, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 1 + .encap_num_fields = 0 }, - { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_0 */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 164, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 27, + .result_start_idx = 114, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 1, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .ident_start_idx = 10, + .ident_nums = 1 + }, + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 177, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 127, + .result_bit_size = 62, + .result_num_fields = 4, + .encap_num_fields = 0 }, - { /* class_tid: 1, wh_plus, table: parif_def_lkup_arec_ptr_0 */ + { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, - .result_start_idx = 40, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 131, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0 }, - { /* class_tid: 1, wh_plus, table: parif_def_arec_ptr_0 */ + { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, - .result_start_idx = 41, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 132, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 1, wh_plus, table: parif_def_err_arec_ptr_0 */ + { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, - .result_start_idx = 42, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 133, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 2, wh_plus, table: int_full_act_record_0 */ + { /* class_tid: 4, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .result_start_idx = 43, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 134, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .encap_num_fields = 0 }, - { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_vfr_0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 4, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 14, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 178, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 69, + .result_start_idx = 160, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 1, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .ident_start_idx = 11, + .ident_nums = 0 }, - { /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, - .key_start_idx = 27, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 5, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 191, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 82, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 1, + .ident_start_idx = 11, .ident_nums = 1 }, - { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 6, + .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 28, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 192, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 83, + .result_start_idx = 173, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .ident_start_idx = 12, + .ident_nums = 1 + }, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 8, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 205, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 186, + .result_bit_size = 62, + .result_num_fields = 4, + .encap_num_fields = 0 }, - { /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr_0 */ + { /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, - .result_start_idx = 96, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 190, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 2, wh_plus, table: parif_def_arec_ptr_0 */ + { /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, - .result_start_idx = 97, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 191, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr_0 */ + { /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, - .result_start_idx = 98, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 192, .result_bit_size = 32, .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + .encap_num_fields = 0 }, - { /* class_tid: 3, wh_plus, table: egr_int_vtag_encap_record_0 */ + { /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .result_start_idx = 99, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 193, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .encap_num_fields = 12 }, - { /* class_tid: 3, wh_plus, table: egr_int_full_act_record_0 */ + { /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, - .result_start_idx = 111, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 205, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .encap_num_fields = 0 }, - { /* class_tid: 3, wh_plus, table: egr_l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 41, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 137, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0 - }, - { /* class_tid: 3, wh_plus, table: egr_l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 42, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 137, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 3, wh_plus, table: ing_int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .result_start_idx = 150, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* class_tid: 3, wh_plus, table: ing_l2_cntxt_dtagged_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 55, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 176, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 3, wh_plus, table: ing_l2_cntxt_stagged_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 68, + .key_start_idx = 206, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 189, + .result_start_idx = 231, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .ident_start_idx = 13, + .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, - .key_start_idx = 81, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 219, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 202, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 1 - }, - { /* class_tid: 4, wh_plus, table: egr_l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 82, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 203, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 4, wh_plus, table: egr_parif_def_lkup_arec_ptr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .result_start_idx = 216, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF - }, - { /* class_tid: 4, wh_plus, table: egr_parif_def_arec_ptr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .result_start_idx = 217, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF - }, - { /* class_tid: 4, wh_plus, table: egr_parif_def_err_arec_ptr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, - .result_start_idx = 218, - .result_bit_size = 32, - .result_num_fields = 1, + .result_start_idx = 244, + .result_bit_size = 62, + .result_num_fields = 4, .encap_num_fields = 0, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + .ident_start_idx = 13, + .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: ing_int_full_act_record_0 */ + { /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .result_start_idx = 219, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { /* class_tid: 4, wh_plus, table: ing_l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 95, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 245, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 0, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 5, wh_plus, table: int_full_act_record_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .result_start_idx = 258, + .result_start_idx = 248, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + .encap_num_fields = 0 }, - { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 108, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 220, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 284, + .result_start_idx = 274, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 121, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 297, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 4, - .ident_nums = 1 - }, - { /* class_tid: 6, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 1, - .key_start_idx = 124, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 298, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 6, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 167, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 306, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 6, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 178, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 315, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + .ident_start_idx = 13, + .ident_nums = 0 }, - { /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 189, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 233, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 324, + .result_start_idx = 287, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 202, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 337, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 6, - .ident_nums = 1 - }, - { /* class_tid: 7, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 1, - .key_start_idx = 205, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 338, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 7, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 248, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 346, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 7, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 259, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 355, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 270, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 364, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 1 + .ident_start_idx = 13, + .ident_nums = 0 }, - { /* class_tid: 8, wh_plus, table: l2_cntxt_tcam_0 */ + { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 271, + .key_start_idx = 246, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 365, + .result_start_idx = 300, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 8, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 284, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 378, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 8, + .ident_start_idx = 13, .ident_nums = 1 }, - { /* class_tid: 8, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 287, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 379, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 8, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 330, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 387, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 8, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 341, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 396, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 352, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 405, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 1 - }, - { /* class_tid: 9, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 353, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 406, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 10, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 366, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 419, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 10, - .ident_nums = 1 - }, - { /* class_tid: 9, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 369, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 420, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 11, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 9, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 412, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 428, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 11, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 9, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 423, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 437, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 11, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 434, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 446, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 11, - .ident_nums = 1 - }, - { /* class_tid: 10, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 435, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 447, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 12, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 448, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 460, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 12, - .ident_nums = 1 - }, - { /* class_tid: 10, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 451, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 461, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 13, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 10, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 494, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 469, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 13, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 10, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 505, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 478, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 13, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 516, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 487, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 13, - .ident_nums = 1 - }, - { /* class_tid: 11, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 517, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 488, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 14, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 530, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 501, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 14, - .ident_nums = 1 - }, - { /* class_tid: 11, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 533, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 502, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 15, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 11, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 576, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 510, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 15, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 11, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 587, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 519, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 15, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 598, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 528, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 15, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 611, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 541, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 16, - .ident_nums = 1 - }, - { /* class_tid: 12, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 614, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 542, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 17, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 12, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 657, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 550, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 17, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 12, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 668, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 559, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 17, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 679, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 568, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 17, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 692, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 581, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 18, - .ident_nums = 1 - }, - { /* class_tid: 13, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 695, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 582, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 19, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 13, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 738, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 590, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 19, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 13, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 749, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 599, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 19, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 760, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 608, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 19, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 773, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 621, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 20, - .ident_nums = 1 - }, - { /* class_tid: 14, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 776, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 622, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 21, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 14, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 819, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 630, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 21, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 14, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 830, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 639, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 21, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 841, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 648, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 21, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 854, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 661, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 22, - .ident_nums = 1 - }, - { /* class_tid: 15, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 857, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 662, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 23, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 15, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 900, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 670, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 23, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 15, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 911, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 679, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 23, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 922, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 688, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 23, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 935, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 701, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 24, - .ident_nums = 1 - }, - { /* class_tid: 16, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 938, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 702, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 25, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 16, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 981, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 710, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 25, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 16, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 992, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 719, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 25, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1003, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 728, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 25, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 1016, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 741, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 26, - .ident_nums = 1 - }, - { /* class_tid: 17, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1019, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 742, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 27, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 17, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 1062, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 750, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 27, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 17, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 1073, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 759, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 27, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 18, wh_plus, table: int_flow_counter_tbl_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC, - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_RX, - .result_start_idx = 768, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 - }, - { /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1084, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 769, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 27, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 1097, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 782, - .result_bit_size = 20, - .result_num_fields = 2, - .encap_num_fields = 0, - .ident_start_idx = 28, - .ident_nums = 2 - }, - { /* class_tid: 18, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1100, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 784, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 30, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 18, wh_plus, table: wm_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .direction = TF_DIR_RX, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1143, - .blob_key_bit_size = 192, - .key_bit_size = 160, - .key_num_fields = 5, - .result_start_idx = 792, - .result_bit_size = 19, - .result_num_fields = 3, - .encap_num_fields = 0, - .ident_start_idx = 30, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1148, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 795, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 30, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 1161, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 808, - .result_bit_size = 20, - .result_num_fields = 2, - .encap_num_fields = 0, - .ident_start_idx = 31, - .ident_nums = 2 - }, - { /* class_tid: 19, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1164, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 810, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 33, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 19, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_RX, - .key_start_idx = 1207, - .blob_key_bit_size = 112, - .key_bit_size = 112, - .key_num_fields = 8, - .result_start_idx = 818, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 33, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 19, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_RX, - .key_start_idx = 1215, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 8, - .result_start_idx = 827, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 33, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1223, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 836, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 33, - .ident_nums = 1 - }, - { /* class_tid: 20, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1224, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 837, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 34, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1237, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 850, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 34, - .ident_nums = 1 - }, - { /* class_tid: 20, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1240, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 851, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 35, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 20, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1283, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 859, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 35, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 20, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1294, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 868, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 35, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1305, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 877, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 35, - .ident_nums = 1 - }, - { /* class_tid: 21, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1306, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 878, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 36, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1319, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 891, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 36, - .ident_nums = 1 - }, - { /* class_tid: 21, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1322, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 892, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 37, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 21, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1365, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 900, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 37, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 21, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1376, - .blob_key_bit_size = 200, - .key_bit_size = 200, - .key_num_fields = 11, - .result_start_idx = 909, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 37, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1387, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 918, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 37, - .ident_nums = 1 - }, - { /* class_tid: 22, wh_plus, table: l2_cntxt_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1388, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 919, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 38, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1401, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 932, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 38, - .ident_nums = 1 - }, - { /* class_tid: 22, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1404, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 933, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 39, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 22, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1447, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 941, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 39, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 22, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1458, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 950, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 39, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1469, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 959, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 39, - .ident_nums = 1 - }, - { /* class_tid: 23, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1470, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 960, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 40, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1483, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 973, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 40, - .ident_nums = 1 - }, - { /* class_tid: 23, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1486, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 974, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 41, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 23, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1529, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 982, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 41, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 23, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1540, - .blob_key_bit_size = 392, - .key_bit_size = 392, - .key_num_fields = 11, - .result_start_idx = 991, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 41, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1551, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 1000, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 41, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1564, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 1013, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 42, - .ident_nums = 1 - }, - { /* class_tid: 24, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1567, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 1014, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 43, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 24, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1610, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 7, - .result_start_idx = 1022, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 43, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 24, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1617, - .blob_key_bit_size = 104, - .key_bit_size = 104, - .key_num_fields = 7, - .result_start_idx = 1031, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 43, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1624, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 1040, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 43, - .ident_nums = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INVALID, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 1637, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 1053, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 44, - .ident_nums = 1 - }, - { /* class_tid: 25, wh_plus, table: profile_tcam_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1640, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 1054, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 45, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO - }, - { /* class_tid: 25, wh_plus, table: ext_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .direction = TF_DIR_TX, - .key_start_idx = 1683, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 7, - .result_start_idx = 1062, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 45, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - }, - { /* class_tid: 25, wh_plus, table: int_em_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .direction = TF_DIR_TX, - .key_start_idx = 1690, - .blob_key_bit_size = 104, - .key_bit_size = 104, - .key_num_fields = 7, - .result_start_idx = 1071, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 45, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - } -}; - -struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_vfr_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, wh_plus, table: egr_l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, wh_plus, table: egr_l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, wh_plus, table: ing_l2_cntxt_dtagged_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, wh_plus, table: ing_l2_cntxt_stagged_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, wh_plus, table: egr_l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, wh_plus, table: ing_l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF6_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF6_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF6_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF6_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF6_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF6_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF6_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF6_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF6_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF6_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF6_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF6_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF7_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF7_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF7_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF7_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF7_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF7_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF7_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF7_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF7_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF11_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF13_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF15_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF15_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF15_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF15_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF16_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "t_ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "t_ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "t_ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "t_ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "t_l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF17_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF18_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF18_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 18, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 18, wh_plus, table: wm_0 */ - { - .description = "wc_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "spare", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "others", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF19_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 19, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 19, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dst_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF19_IDX_I_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_HF19_IDX_T_VXLAN_VNI & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 19, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 339, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dst_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF19_IDX_I_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF19_IDX_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_HF19_IDX_T_VXLAN_VNI & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 20, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 21, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_dst_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv4_src_addr", - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, wh_plus, table: l2_cntxt_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 22, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_tl2_dst", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 59, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 23, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_dst_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l4_src_port", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ip_proto", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_dst_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ipv6_src_addr", - .field_bit_size = 128, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_src_mac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_id", - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF24_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF24_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF24_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF24_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF24_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF24_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF24_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF24_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF24_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 351, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_eth_type", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF24_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_eth_type", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF24_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF24_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF25_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF25_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_HF25_IDX_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac0_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF25_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF25_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_HF25_IDX_O_ETH_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "svif", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF25_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF25_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF25_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sparif", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mac1_l2_addr", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "recycle", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "class_tid", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, wh_plus, table: profile_tcam_0 */ - { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hrec_next", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "agg_error", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "recycle_cnt", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_0", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pkt_type_1", - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, wh_plus, table: ext_em_0 */ - { - .description = "spare", - .field_bit_size = 351, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_eth_type", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF25_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 25, wh_plus, table: int_em_0 */ - { - .description = "spare", - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "local_cos", - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_eth_type", - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_inner_vid", - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF25_IDX_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_HF25_IDX_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } -}; - -struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = { - /* class_tid: 1, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 1, wh_plus, table: parif_def_lkup_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, wh_plus, table: parif_def_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, wh_plus, table: parif_def_err_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_vfr_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: parif_def_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 3, wh_plus, table: egr_int_vtag_encap_record_0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x81, 0x00} - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "spare", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, wh_plus, table: egr_int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, wh_plus, table: egr_l2_cntxt_cache_0 */ - /* class_tid: 3, wh_plus, table: egr_l2_cntxt_tcam_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, wh_plus, table: ing_int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, wh_plus, table: ing_l2_cntxt_dtagged_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 3, wh_plus, table: ing_l2_cntxt_stagged_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, wh_plus, table: egr_l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_VF_FUNC_PARIF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 4, wh_plus, table: egr_parif_def_lkup_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, wh_plus, table: egr_parif_def_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, wh_plus, table: egr_parif_def_err_arec_ptr_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 4, wh_plus, table: ing_int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 4, wh_plus, table: ing_l2_cntxt_tcam_0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 5, wh_plus, table: int_full_act_record_0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0005 >> 8) & 0xff, - 0x0005 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 6, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 6, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0005 >> 8) & 0xff, - 0x0005 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 7, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 7, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 8, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 8, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 9, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 9, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 10, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 10, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 11, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 11, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 12, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 12, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 13, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 13, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 14, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 14, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 15, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 15, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0031 >> 8) & 0xff, - 0x0031 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 16, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 16, wh_plus, table: int_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 17, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0031 >> 8) & 0xff, - 0x0031 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 17, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 259, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 313, + .result_bit_size = 62, + .result_num_fields = 4, + .encap_num_fields = 0 }, - { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 317, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0 }, - { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + { /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 318, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0 }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .result_start_idx = 319, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0 }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + { /* class_tid: 6, wh_plus, table: int_full_act_record.ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .result_start_idx = 320, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 260, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 346, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 14, + .ident_nums = 0 }, - /* class_tid: 17, wh_plus, table: int_em_0 */ + { /* class_tid: 7, wh_plus, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 359, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* class_tid: 18, wh_plus, table: int_flow_counter_tbl_0 */ { - .description = "count", - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ + .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + } +}; + +struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam.0 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, wh_plus, table: eem.ext_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 275, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 275, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 1, wh_plus, table: em.int_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, wh_plus, table: profile_tcam.0 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, wh_plus, table: eem.ext_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 275, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 275, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 2, wh_plus, table: em.int_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, + .field_operand = { + (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -21194,1089 +5064,1119 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "wc_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 18, wh_plus, table: profile_tcam_0 */ + /* class_tid: 1, wh_plus, table: profile_tcam.0 */ { .description = "wc_key_id", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "wc_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "em_key_mask", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x001b >> 8) & 0xff, - 0x001b & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (0x007d >> 8) & 0xff, + 0x007d & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_key_id", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_search_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 18, wh_plus, table: wm_0 */ - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ { - .description = "act_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ - { - .description = "l2_cntxt_id", + .description = "profile_tcam_index", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "allowed_pri", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ - { .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "wc_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff, + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 19, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, { - .description = "wc_profile_id", + .description = "wm_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_profile_id", + .description = "flow_sig_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 19, wh_plus, table: int_em_0 */ + /* class_tid: 1, wh_plus, table: eem.ext_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ext_flow_cntr", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "act_rec_size", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "key_size", .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x006d >> 8) & 0xff, - 0x006d & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (0x00ad >> 8) & 0xff, + 0x00ad & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "reserved", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "strength", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 19, wh_plus, table: ext_em_0 */ + /* class_tid: 1, wh_plus, table: em.int_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ext_flow_cntr", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "key_size", .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x006d >> 8) & 0xff, - 0x006d & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "reserved", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "strength", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "valid", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 20, wh_plus, table: l2_cntxt_tcam_0 */ + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 20, wh_plus, table: profile_tcam_0 */ + /* class_tid: 2, wh_plus, table: profile_tcam.0 */ { .description = "wc_key_id", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "wc_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "em_key_mask", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (0x0079 >> 8) & 0xff, + 0x0079 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_key_id", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_profile_id", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "em_search_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .description = "wm_profile_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "flow_sig_id", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 20, wh_plus, table: ext_em_0 */ + /* class_tid: 2, wh_plus, table: eem.ext_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ext_flow_cntr", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "act_rec_size", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "key_size", .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (0x00ad >> 8) & 0xff, + 0x00ad & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "reserved", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "strength", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 20, wh_plus, table: int_em_0 */ + /* class_tid: 2, wh_plus, table: em.int_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ext_flow_cntr", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "key_size", .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "reserved", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "strength", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ + /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ { - .description = "l2_cntxt_id", + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 21, wh_plus, table: l2_cntxt_tcam_0 */ + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ { - .description = "em_profile_id", + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 21, wh_plus, table: profile_tcam_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_profile_id", + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + { + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ + { + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ + { + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + /* class_tid: 4, wh_plus, table: int_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_key", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "wc_search_en", + .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "em_search_en", + .description = "pop_vlan", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "meter", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 21, wh_plus, table: ext_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "mirror", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "hit", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 21, wh_plus, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "parif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "allowed_pri", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "default_pri", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "default_tpid", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .description = "bd_act_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 22, wh_plus, table: l2_cntxt_0 */ + { + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -22285,1539 +6185,1329 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] = { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 22, wh_plus, table: profile_tcam_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */ { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */ { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */ { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */ { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "ecv_l2_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 22, wh_plus, table: ext_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "ecv_custom_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "ecv_valid", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x81, 0x00} }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, + .description = "vtag_vid", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "vtag_de", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "spare", + .field_bit_size = 80, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "age_enable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "agg_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 22, wh_plus, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT >> 8) & 0xff, + BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "pop_vlan", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", + .description = "meter", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "mirror", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "hit", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, wh_plus, table: l2_cntxt_tcam_0 */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "reserved", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 23, wh_plus, table: profile_tcam_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */ { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "age_enable", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_search_en", + .description = "rate_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "flow_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, wh_plus, table: ext_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "tcpflags_mir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "tcpflags_match", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 23, wh_plus, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "l3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "tl3_ttl_dec", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0185 >> 8) & 0xff, - 0x0185 & 0xff, + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "pop_vlan", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "strength", + .description = "meter", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "mirror", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "drop", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "hit", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { - .description = "prof_func_id", - .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .description = "reserved", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ - { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 24, wh_plus, table: profile_tcam_0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0003 >> 8) & 0xff, - 0x0003 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - /* class_tid: 24, wh_plus, table: ext_em_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0061 >> 8) & 0xff, - 0x0061 & 0xff, + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 24, wh_plus, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "parif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "allowed_pri", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "default_pri", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0061 >> 8) & 0xff, - 0x0061 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "default_tpid", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "bd_act_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "prof_func_id", .field_bit_size = 7, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "parif", .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF, - .result_operand = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_true = { - (BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .result_operand_false = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "allowed_pri", .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { - .description = "em_profile_id", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "rid", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 25, wh_plus, table: profile_tcam_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "wc_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, + /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */ { - .description = "em_key_mask", - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0003 >> 8) & 0xff, - 0x0003 & 0xff, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */ { - .description = "em_key_id", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */ { - .description = "em_profile_id", - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, + .field_operand = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, + /* class_tid: 6, wh_plus, table: int_full_act_record.ing */ { - .description = "em_search_en", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "age_enable", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 25, wh_plus, table: ext_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "ext_flow_ctr", + .description = "rate_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "flow_cntr_en", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0061 >> 8) & 0xff, - 0x0061 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "reserved", + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "encap_ptr", .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "l1_cacheable", + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "l3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", + .description = "tl3_rdir", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 25, wh_plus, table: int_em_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, + .field_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "ext_flow_ctr", + .description = "pop_vlan", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_int", + .description = "meter", .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .description = "mirror", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "key_size", - .field_bit_size = 9, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x0061 >> 8) & 0xff, - 0x0061 & 0xff, + .description = "drop", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + { + .description = "act_record_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, + .field_operand = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .description = "reserved", - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "strength", - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + .description = "l2_byp_lkup_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .description = "l1_cacheable", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .description = "parif", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "valid", - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } -}; - -struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_cache_0 */ + .description = "allowed_pri", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "default_pri", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 2, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "default_tpid", + .field_bit_size = 3, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "bd_act_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + }, + { + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 4, wh_plus, table: egr_l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "byp_sp_lkup", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 6, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 7, wh_plus, table: l2_cntxt_tcam_0 */ + /* class_tid: 7, wh_plus, table: int_full_act_record.0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 7, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "age_enable", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 8, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 8, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 9, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 9, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 10, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 10, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 11, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "encap_ptr", + .field_bit_size = 11, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 11, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 12, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 12, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 13, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 13, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "meter_id", + .field_bit_size = 10, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 14, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "l3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 14, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 15, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 15, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 16, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "decap_func", + .field_bit_size = 4, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 16, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, + .field_operand = { + (BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT >> 8) & 0xff, + BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, - /* class_tid: 17, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "pop_vlan", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 17, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "meter", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 18, wh_plus, table: l2_cntxt_tcam_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "mirror", + .field_bit_size = 2, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 18, wh_plus, table: profile_tcam_cache_0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "drop", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "hit", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO }, - /* class_tid: 19, wh_plus, table: l2_cntxt_tcam_0 */ + { + .description = "type", + .field_bit_size = 1, + .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + } +}; + +struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 19, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 8, + .ident_bit_pos = 58 }, { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0, + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_bit_pos = 32 }, - /* class_tid: 20, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "em_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 }, - /* class_tid: 20, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 1, wh_plus, table: profile_tcam.0 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 28 }, - /* class_tid: 21, wh_plus, table: l2_cntxt_cache_0 */ + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 21, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_bit_pos = 32 }, - /* class_tid: 22, wh_plus, table: l2_cntxt_cache_0 */ { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 8, + .ident_bit_pos = 58 }, - /* class_tid: 22, wh_plus, table: profile_tcam_cache_0 */ { .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - /* class_tid: 23, wh_plus, table: l2_cntxt_cache_0 */ - { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 }, - /* class_tid: 23, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 2, wh_plus, table: profile_tcam.0 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 28 }, - /* class_tid: 24, wh_plus, table: l2_cntxt_tcam_0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 24, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_bit_pos = 42 }, - /* class_tid: 25, wh_plus, table: l2_cntxt_tcam_0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 25, wh_plus, table: profile_tcam_cache_0 */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ { - .description = "em_profile_id", + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 23b4c89896..b06b1b12d3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2019 Broadcom * All rights reserved. */ @@ -18,7 +18,7 @@ #include "tf_core.h" /* Number of fields for each protocol */ -#define BNXT_ULP_PROTO_HDR_SVIF_NUM 1 +#define BNXT_ULP_PROTO_HDR_SVIF_NUM 2 #define BNXT_ULP_PROTO_HDR_ETH_NUM 3 #define BNXT_ULP_PROTO_HDR_S_VLAN_NUM 3 #define BNXT_ULP_PROTO_HDR_VLAN_NUM 6 @@ -28,7 +28,7 @@ #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 #define BNXT_ULP_PROTO_HDR_MAX 128 -#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 0 +#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1 /* Direction attributes */ #define BNXT_ULP_FLOW_ATTR_TRANSFER 0x1 @@ -62,14 +62,12 @@ struct ulp_rte_act_prop { /* Structure to be used for passing all the parser functions */ struct ulp_rte_parser_params { - STAILQ_ENTRY(ulp_rte_parser_params) next; struct ulp_rte_hdr_bitmap hdr_bitmap; struct ulp_rte_hdr_bitmap hdr_fp_bit; struct ulp_rte_field_bitmap fld_bitmap; struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX]; uint32_t comp_fld[BNXT_ULP_CF_IDX_LAST]; uint32_t field_idx; - uint32_t vlan_idx; struct ulp_rte_act_bitmap act_bitmap; struct ulp_rte_act_prop act_prop; uint32_t dir_attr; @@ -78,10 +76,11 @@ struct ulp_rte_parser_params { uint32_t parent_flow; uint32_t parent_fid; uint16_t func_id; - uint16_t port_id; uint32_t class_id; uint32_t act_tmpl; struct bnxt_ulp_context *ulp_ctx; + uint32_t hdr_sig_id; + uint32_t flow_sig_id; }; /* Flow Parser Header Information Structure */ @@ -127,6 +126,8 @@ struct bnxt_ulp_class_match_info { uint32_t class_tid; uint8_t act_vnic; uint8_t wc_pri; + uint32_t hdr_sig_id; + uint32_t flow_sig_id; }; /* Flow Matcher templates Structure for class entries */ @@ -163,11 +164,17 @@ struct bnxt_ulp_mapper_cond_list_info { struct bnxt_ulp_template_device_tbls { struct bnxt_ulp_mapper_tmpl_info *tmpl_list; + uint32_t tmpl_list_size; struct bnxt_ulp_mapper_tbl_info *tbl_list; - struct bnxt_ulp_mapper_key_field_info *key_field_list; - struct bnxt_ulp_mapper_result_field_info *result_field_list; + uint32_t tbl_list_size; + struct bnxt_ulp_mapper_key_info *key_info_list; + uint32_t key_info_list_size; + struct bnxt_ulp_mapper_field_info *result_field_list; + uint32_t result_field_list_size; struct bnxt_ulp_mapper_ident_info *ident_list; + uint32_t ident_list_size; struct bnxt_ulp_mapper_cond_info *cond_list; + uint32_t cond_list_size; }; /* Device specific parameters */ @@ -210,6 +217,10 @@ struct bnxt_ulp_mapper_tbl_info { uint8_t direction; enum bnxt_ulp_pri_opc pri_opcode; uint32_t pri_operand; + + /* conflict resoution opcode */ + enum bnxt_ulp_accept_opc accept_opcode; + enum bnxt_ulp_critical_resource critical_resource; /* Information for accessing the ulp_key_field_list */ @@ -237,25 +248,21 @@ struct bnxt_ulp_mapper_tbl_info { /* FDB table opcode */ enum bnxt_ulp_fdb_opc fdb_opcode; - uint32_t flow_db_operand; + uint32_t fdb_operand; }; -struct bnxt_ulp_mapper_key_field_info { - uint8_t description[64]; - enum bnxt_ulp_mapper_opc mask_opcode; - enum bnxt_ulp_mapper_opc spec_opcode; - uint16_t field_bit_size; - uint8_t mask_operand[16]; - uint8_t spec_operand[16]; +struct bnxt_ulp_mapper_field_info { + uint8_t description[64]; + enum bnxt_ulp_field_opc field_opcode; + uint16_t field_bit_size; + uint8_t field_operand[16]; + uint8_t field_operand_true[16]; + uint8_t field_operand_false[16]; }; -struct bnxt_ulp_mapper_result_field_info { - uint8_t description[64]; - enum bnxt_ulp_mapper_opc result_opcode; - uint16_t field_bit_size; - uint8_t result_operand[16]; - uint8_t result_operand_true[16]; - uint8_t result_operand_false[16]; +struct bnxt_ulp_mapper_key_info { + struct bnxt_ulp_mapper_field_info field_info_spec; + struct bnxt_ulp_mapper_field_info field_info_mask; }; struct bnxt_ulp_mapper_ident_info { @@ -265,13 +272,13 @@ struct bnxt_ulp_mapper_ident_info { uint16_t ident_type; uint16_t ident_bit_size; uint16_t ident_bit_pos; - enum bnxt_ulp_regfile_index regfile_idx; + enum bnxt_ulp_rf_idx regfile_idx; }; struct bnxt_ulp_glb_resource_info { enum bnxt_ulp_resource_func resource_func; uint32_t resource_type; /* TF_ enum type */ - enum bnxt_ulp_glb_regfile_index glb_regfile_index; + enum bnxt_ulp_glb_rf_idx glb_regfile_index; enum tf_dir direction; }; @@ -281,10 +288,14 @@ struct bnxt_ulp_cache_tbl_params { struct bnxt_ulp_generic_tbl_params { uint16_t result_num_entries; - uint16_t result_byte_size; + uint16_t result_num_bytes; enum bnxt_ulp_byte_order result_byte_order; }; +struct bnxt_ulp_shared_act_info { + uint64_t act_bitmask; +}; + /* * Flow Mapper Static Data Externs: * Access to the below static data should be done through access functions and diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c index 6c1ae3ced2..e8d2861880 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.c +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ -#include - #include #include "ulp_tun.h" @@ -50,18 +48,18 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params, goto err; /* Store the tunnel dmac in the tunnel cache table and use it while - * programming tunnel inner flow. + * programming tunnel flow F2. */ memcpy(tun_entry->t_dmac, ¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec, RTE_ETHER_ADDR_LEN); - tun_entry->tun_flow_info[params->port_id].state = - BNXT_ULP_FLOW_STATE_TUN_O_OFFLD; + tun_entry->valid = true; + tun_entry->state = BNXT_ULP_FLOW_STATE_TUN_O_OFFLD; tun_entry->outer_tun_flow_id = params->fid; - /* Tunnel outer flow and it's related inner flows are correlated - * based on Tunnel Destination IP Address. + /* F1 and it's related F2s are correlated based on + * Tunnel Destination IP Address. */ if (tun_entry->t_dst_ip_valid) goto done; @@ -85,32 +83,27 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params, /* This function programs the inner tunnel flow in the hardware. */ static void -ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry, - struct ulp_rte_parser_params *tun_o_params) +ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry) { struct bnxt_ulp_mapper_create_parms mparms = { 0 }; - struct ulp_per_port_flow_info *flow_info; - struct ulp_rte_parser_params *inner_params; + struct ulp_rte_parser_params *params; int ret; - /* Tunnel inner flow doesn't have tunnel dmac, use the tunnel - * dmac that was stored during F1 programming. + /* F2 doesn't have tunnel dmac, use the tunnel dmac that was + * stored during F1 programming. */ - flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id]; - STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) { - memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX], - tun_entry->t_dmac, RTE_ETHER_ADDR_LEN); - inner_params->parent_fid = tun_entry->outer_tun_flow_id; - - bnxt_ulp_init_mapper_params(&mparms, inner_params, - BNXT_ULP_FDB_TYPE_REGULAR); - - ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms); - if (ret) - PMD_DRV_LOG(ERR, - "Failed to create inner tun flow, FID:%u.", - inner_params->fid); - } + params = &tun_entry->first_inner_tun_params; + memcpy(¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX], + tun_entry->t_dmac, RTE_ETHER_ADDR_LEN); + params->parent_fid = tun_entry->outer_tun_flow_id; + params->fid = tun_entry->first_inner_tun_flow_id; + + bnxt_ulp_init_mapper_params(&mparms, params, + BNXT_ULP_FDB_TYPE_REGULAR); + + ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms); + if (ret) + PMD_DRV_LOG(ERR, "Failed to create F2 flow."); } /* This function either install outer tunnel flow & inner tunnel flow @@ -121,31 +114,30 @@ ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params, struct bnxt_tun_cache_entry *tun_entry, uint16_t tun_idx) { + enum bnxt_ulp_tun_flow_state flow_state; int ret; + flow_state = tun_entry->state; ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx); - if (ret == BNXT_TF_RC_ERROR) { - PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow."); + if (ret) return ret; - } - /* Install any cached tunnel inner flows that came before tunnel - * outer flow. + /* If flow_state == BNXT_ULP_FLOW_STATE_NORMAL before installing + * F1, that means F2 is not deferred. Hence, no need to install F2. */ - ulp_install_inner_tun_flow(tun_entry, params); + if (flow_state != BNXT_ULP_FLOW_STATE_NORMAL) + ulp_install_inner_tun_flow(tun_entry); - return BNXT_TF_RC_FID; + return 0; } /* This function will be called if inner tunnel flow request comes before * outer tunnel flow request. */ static int32_t -ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params, +ulp_post_process_first_inner_tun_flow(struct ulp_rte_parser_params *params, struct bnxt_tun_cache_entry *tun_entry) { - struct ulp_rte_parser_params *inner_tun_params; - struct ulp_per_port_flow_info *flow_info; int ret; ret = ulp_matcher_pattern_match(params, ¶ms->class_id); @@ -156,22 +148,18 @@ ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params, if (ret != BNXT_TF_RC_SUCCESS) return BNXT_TF_RC_ERROR; - /* If Tunnel inner flow comes first then we can't install it in the - * hardware, because, Tunnel inner flow will not have L2 context - * information. So, just cache the Tunnel inner flow information - * and program it in the context of F1 flow installation. + /* If Tunnel F2 flow comes first then we can't install it in the + * hardware, because, F2 flow will not have L2 context information. + * So, just cache the F2 information and program it in the context + * of F1 flow installation. */ - flow_info = &tun_entry->tun_flow_info[params->port_id]; - inner_tun_params = rte_zmalloc("ulp_inner_tun_params", - sizeof(struct ulp_rte_parser_params), 0); - if (!inner_tun_params) - return BNXT_TF_RC_ERROR; - memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params)); - STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params, - next); - flow_info->tun_i_cnt++; + memcpy(&tun_entry->first_inner_tun_params, params, + sizeof(struct ulp_rte_parser_params)); + + tun_entry->first_inner_tun_flow_id = params->fid; + tun_entry->state = BNXT_ULP_FLOW_STATE_TUN_I_CACHED; - /* F1 and it's related Tunnel inner flows are correlated based on + /* F1 and it's related F2s are correlated based on * Tunnel Destination IP Address. It could be already set, if * the inner flow got offloaded first. */ @@ -252,8 +240,8 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params, int32_t ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) { - bool inner_tun_sig, cache_inner_tun_flow; - bool outer_tun_reject, outer_tun_flow, inner_tun_flow; + bool outer_tun_sig, inner_tun_sig, first_inner_tun_flow; + bool outer_tun_reject, inner_tun_reject, outer_tun_flow, inner_tun_flow; enum bnxt_ulp_tun_flow_state flow_state; struct bnxt_tun_cache_entry *tun_entry; uint32_t l3_tun, l3_tun_decap; @@ -271,31 +259,40 @@ ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) if (rc == BNXT_TF_RC_ERROR) return rc; - if (params->port_id >= RTE_MAX_ETHPORTS) - return BNXT_TF_RC_ERROR; - flow_state = tun_entry->tun_flow_info[params->port_id].state; + flow_state = tun_entry->state; /* Outer tunnel flow validation */ - outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params); + outer_tun_sig = BNXT_OUTER_TUN_SIGNATURE(l3_tun, params); + outer_tun_flow = BNXT_OUTER_TUN_FLOW(outer_tun_sig); outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state, - outer_tun_flow); + outer_tun_sig); /* Inner tunnel flow validation */ inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params); - cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state, + first_inner_tun_flow = BNXT_FIRST_INNER_TUN_FLOW(flow_state, inner_tun_sig); inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig); + inner_tun_reject = BNXT_REJECT_INNER_TUN_FLOW(flow_state, + inner_tun_sig); if (outer_tun_reject) { tun_entry->outer_tun_rej_cnt++; BNXT_TF_DBG(ERR, "Tunnel F1 flow rejected, COUNT: %d\n", tun_entry->outer_tun_rej_cnt); + /* Inner tunnel flow is rejected if it comes between first inner + * tunnel flow and outer flow requests. + */ + } else if (inner_tun_reject) { + tun_entry->inner_tun_rej_cnt++; + BNXT_TF_DBG(ERR, + "Tunnel F2 flow rejected, COUNT: %d\n", + tun_entry->inner_tun_rej_cnt); } - if (outer_tun_reject) + if (outer_tun_reject || inner_tun_reject) return BNXT_TF_RC_ERROR; - else if (cache_inner_tun_flow) - return ulp_post_process_cache_inner_tun_flow(params, tun_entry); + else if (first_inner_tun_flow) + return ulp_post_process_first_inner_tun_flow(params, tun_entry); else if (outer_tun_flow) return ulp_post_process_outer_tun_flow(params, tun_entry, tun_idx); @@ -305,109 +302,9 @@ ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) return BNXT_TF_RC_NORMAL; } -void -ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl) -{ - struct ulp_per_port_flow_info *flow_info; - int i, j; - - for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { - for (j = 0; j < RTE_MAX_ETHPORTS; j++) { - flow_info = &tun_tbl[i].tun_flow_info[j]; - STAILQ_INIT(&flow_info->tun_i_prms_list); - } - } -} - void ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx) { - struct ulp_rte_parser_params *inner_params; - struct ulp_per_port_flow_info *flow_info; - int j; - - for (j = 0; j < RTE_MAX_ETHPORTS; j++) { - flow_info = &tun_tbl[tun_idx].tun_flow_info[j]; - STAILQ_FOREACH(inner_params, - &flow_info->tun_i_prms_list, - next) { - STAILQ_REMOVE(&flow_info->tun_i_prms_list, - inner_params, - ulp_rte_parser_params, next); - rte_free(inner_params); - } - } - memset(&tun_tbl[tun_idx], 0, - sizeof(struct bnxt_tun_cache_entry)); - - for (j = 0; j < RTE_MAX_ETHPORTS; j++) { - flow_info = &tun_tbl[tun_idx].tun_flow_info[j]; - STAILQ_INIT(&flow_info->tun_i_prms_list); - } -} - -static bool -ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry, - struct ulp_per_port_flow_info *flow_info, - uint32_t fid) -{ - struct ulp_rte_parser_params *inner_params; - int j; - - STAILQ_FOREACH(inner_params, - &flow_info->tun_i_prms_list, - next) { - if (inner_params->fid == fid) { - STAILQ_REMOVE(&flow_info->tun_i_prms_list, - inner_params, - ulp_rte_parser_params, - next); - rte_free(inner_params); - flow_info->tun_i_cnt--; - /* When a dpdk application offloads a duplicate - * tunnel inner flow on a port that it is not - * destined to, there won't be a tunnel outer flow - * associated with these duplicate tunnel inner flows. - * So, when the last tunnel inner flow ages out, the - * driver has to clear the tunnel entry, otherwise - * the tunnel entry cannot be reused. - */ - if (!flow_info->tun_i_cnt && - flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) { - memset(tun_entry, 0, - sizeof(struct bnxt_tun_cache_entry)); - for (j = 0; j < RTE_MAX_ETHPORTS; j++) - STAILQ_INIT(&flow_info->tun_i_prms_list); - } - return true; - } - } - - return false; -} - -/* When a dpdk application offloads the same tunnel inner flow - * on all the uplink ports, a tunnel inner flow entry is cached - * even if it is not for the right uplink port. Such tunnel - * inner flows will eventually get aged out as there won't be - * any traffic on these ports. When such a flow destroy is - * called, cleanup the tunnel inner flow entry. - */ -void -ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid) -{ - struct ulp_per_port_flow_info *flow_info; - int i, j; - - for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { - if (!tun_tbl[i].t_dst_ip_valid) - continue; - for (j = 0; j < RTE_MAX_ETHPORTS; j++) { - flow_info = &tun_tbl[i].tun_flow_info[j]; - if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i], - flow_info, fid) == true) - return; - } - } + sizeof(struct bnxt_tun_cache_entry)); } diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h index 7e31f81f13..ad70ae6164 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.h +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2020 Broadcom * All rights reserved. */ @@ -15,7 +15,7 @@ #include "ulp_template_db_enum.h" #include "ulp_template_struct.h" -#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \ +#define BNXT_OUTER_TUN_SIGNATURE(l3_tun, params) \ ((l3_tun) && \ ULP_BITMAP_ISSET((params)->act_bitmap.bits, \ BNXT_ULP_ACTION_BIT_JUMP)) @@ -24,16 +24,22 @@ !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \ BNXT_ULP_HDR_BIT_O_ETH)) -#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \ +#define BNXT_FIRST_INNER_TUN_FLOW(state, inner_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig)) #define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig)) +#define BNXT_OUTER_TUN_FLOW(outer_tun_sig) ((outer_tun_sig)) /* It is invalid to get another outer flow offload request * for the same tunnel, while the outer flow is already offloaded. */ #define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig)) +/* It is invalid to get another inner flow offload request + * for the same tunnel, while the outer flow is not yet offloaded. + */ +#define BNXT_REJECT_INNER_TUN_FLOW(state, inner_tun_sig) \ + ((state) == BNXT_ULP_FLOW_STATE_TUN_I_CACHED && (inner_tun_sig)) #define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1 #define ULP_TUN_O_IPV4_DIP_INDEX 19 @@ -44,10 +50,10 @@ * requests arrive. * * If inner tunnel flow offload request arrives first then the flow - * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state. - * The following outer tunnel flow offload request will change the - * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from - * BNXT_ULP_FLOW_STATE_NORMAL. + * state will change from BNXT_ULP_FLOW_STATE_NORMAL to + * BNXT_ULP_FLOW_STATE_TUN_I_CACHED and the following outer tunnel + * flow offload request will change the state of the flow to + * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from BNXT_ULP_FLOW_STATE_TUN_I_CACHED. * * If outer tunnel flow offload request arrives first then the flow state * will change from BNXT_ULP_FLOW_STATE_NORMAL to @@ -61,15 +67,12 @@ enum bnxt_ulp_tun_flow_state { BNXT_ULP_FLOW_STATE_NORMAL = 0, BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, -}; - -struct ulp_per_port_flow_info { - enum bnxt_ulp_tun_flow_state state; - uint32_t tun_i_cnt; - STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list; + BNXT_ULP_FLOW_STATE_TUN_I_CACHED }; struct bnxt_tun_cache_entry { + enum bnxt_ulp_tun_flow_state state; + bool valid; bool t_dst_ip_valid; uint8_t t_dmac[RTE_ETHER_ADDR_LEN]; union { @@ -77,17 +80,13 @@ struct bnxt_tun_cache_entry { uint8_t t_dst_ip6[16]; }; uint32_t outer_tun_flow_id; + uint32_t first_inner_tun_flow_id; uint16_t outer_tun_rej_cnt; - struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS]; + uint16_t inner_tun_rej_cnt; + struct ulp_rte_parser_params first_inner_tun_params; }; -void -ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl); - void ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx); -void -ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid); - #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index ff8eabd3f3..8e3a920ab4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -38,11 +38,11 @@ ulp_regfile_init(struct ulp_regfile *regfile) */ uint32_t ulp_regfile_read(struct ulp_regfile *regfile, - enum bnxt_ulp_regfile_index field, + enum bnxt_ulp_rf_idx field, uint64_t *data) { /* validate the arguments */ - if (!regfile || field >= BNXT_ULP_REGFILE_INDEX_LAST) { + if (!regfile || field >= BNXT_ULP_RF_IDX_LAST) { BNXT_TF_DBG(ERR, "invalid argument\n"); return 0; /* failure */ } @@ -64,21 +64,21 @@ ulp_regfile_read(struct ulp_regfile *regfile, * size [in] The size in bytes of the value beingritten into this * variable. * - * returns 0 on fail + * returns 0 on success */ -uint32_t +int32_t ulp_regfile_write(struct ulp_regfile *regfile, - enum bnxt_ulp_regfile_index field, + enum bnxt_ulp_rf_idx field, uint64_t data) { /* validate the arguments */ - if (!regfile || field >= BNXT_ULP_REGFILE_INDEX_LAST) { + if (!regfile || field >= BNXT_ULP_RF_IDX_LAST) { BNXT_TF_DBG(ERR, "invalid argument\n"); - return 0; /* failure */ + return -EINVAL; /* failure */ } regfile->entry[field].data = data; - return sizeof(data); /* Success */ + return 0; /* Success */ } static void diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h index bbd8c16407..caad5628c9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.h +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2019 Broadcom * All rights reserved. */ @@ -91,7 +91,7 @@ struct ulp_regfile_entry { }; struct ulp_regfile { - struct ulp_regfile_entry entry[BNXT_ULP_REGFILE_INDEX_LAST]; + struct ulp_regfile_entry entry[BNXT_ULP_RF_IDX_LAST]; }; /* @@ -115,7 +115,7 @@ ulp_regfile_init(struct ulp_regfile *regfile); */ uint32_t ulp_regfile_read(struct ulp_regfile *regfile, - enum bnxt_ulp_regfile_index field, + enum bnxt_ulp_rf_idx field, uint64_t *data); /* @@ -128,11 +128,11 @@ ulp_regfile_read(struct ulp_regfile *regfile, * data [in] The value is written into this variable. It is going to be in the * same byte order as it was written. * - * returns zero on error + * returns zero on success */ -uint32_t +int32_t ulp_regfile_write(struct ulp_regfile *regfile, - enum bnxt_ulp_regfile_index field, + enum bnxt_ulp_rf_idx field, uint64_t data); /* From patchwork Sun May 30 08:59:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93693 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42F9EA0524; Tue, 1 Jun 2021 09:40:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 85367410FC; Tue, 1 Jun 2021 09:40:00 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id BD795411D5 for ; Sun, 30 May 2021 11:01:27 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id E62C67DC2; Sun, 30 May 2021 02:01:25 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com E62C67DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365287; bh=zvtt7fAYWJSARam8QP5J+HxOV7lewLfIDBQdRJFrm+E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Au6al9HJh8w/p5nyw5Qk99c9/X3mH3j/rwBx5+vYB1x8bqMwswGcdRr1MnUhPN0hq gINgn7OGn097N9ADGyKknSCOnlnwQctgwU2fpkGgIR3hI1tCEBcV/NO5oLb3ffH12w eiIO8A3RtsqcGJOBXb6l8XYFYKUAp6cix9a5GYpM= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:06 +0530 Message-Id: <20210530085929.29695-36-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:53 +0200 Subject: [dpdk-dev] [PATCH 35/58] net/bnxt: add support for conditional goto processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The condition execute of the mapper tables have goto field that defines the offset of the next table to be processed instead of sequential processing of the tables, this improving the performance. Also, modify key and mask field opcode processing Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 6 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 393 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 36 +- drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 48 +- .../net/bnxt/tf_ulp/ulp_template_db_class.c | 3286 ++++++++-- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 1222 ++-- .../net/bnxt/tf_ulp/ulp_template_db_field.h | 462 +- .../tf_ulp/ulp_template_db_stingray_act.c | 585 +- .../tf_ulp/ulp_template_db_stingray_class.c | 5638 +++++++--------- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 234 +- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 581 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 5656 +++++++---------- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 16 +- drivers/net/bnxt/tf_ulp/ulp_tun.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_tun.h | 2 +- 15 files changed, 9532 insertions(+), 8635 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index 5e9b12e4f5..6d6c22b157 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -139,7 +139,7 @@ ulp_set_vlan_in_act_prop(uint16_t port_id, struct ulp_rte_act_prop *act_prop = mapper_params->act_prop; if (ULP_BITMAP_ISSET(mapper_params->act->bits, - BNXT_ULP_ACTION_BIT_SET_VLAN_VID)) { + BNXT_ULP_ACT_BIT_SET_VLAN_VID)) { BNXT_TF_DBG(ERR, "VLAN already set, multiple VLANs unsupported\n"); return BNXT_TF_RC_ERROR; @@ -148,7 +148,7 @@ ulp_set_vlan_in_act_prop(uint16_t port_id, port_id = rte_cpu_to_be_16(port_id); ULP_BITMAP_SET(mapper_params->act->bits, - BNXT_ULP_ACTION_BIT_SET_VLAN_VID); + BNXT_ULP_ACT_BIT_SET_VLAN_VID); memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG], &port_id, sizeof(port_id)); @@ -161,7 +161,7 @@ ulp_set_mark_in_act_prop(uint16_t port_id, struct bnxt_ulp_mapper_create_parms *mapper_params) { if (ULP_BITMAP_ISSET(mapper_params->act->bits, - BNXT_ULP_ACTION_BIT_MARK)) { + BNXT_ULP_ACT_BIT_MARK)) { BNXT_TF_DBG(ERR, "MARK already set, multiple MARKs unsupported\n"); return BNXT_TF_RC_ERROR; diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index ced446e189..ad5fde9730 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -892,26 +892,35 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, uint16_t write_idx = blob->write_idx; uint16_t idx, size_idx, bitlen; uint8_t *val = NULL; - uint8_t act_val[16]; + uint8_t tmpval[16]; uint8_t bit; + uint32_t src1_sel = 0; + enum bnxt_ulp_field_src fld_src; + uint8_t *fld_src_oper; bitlen = fld->field_bit_size; - switch (fld->field_opcode) { - case BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT: - val = fld->field_operand; - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + /* Evaluate the condition */ + switch (fld->field_cond_src) { + case BNXT_ULP_FIELD_COND_SRC_TRUE: + src1_sel = 1; + break; + case BNXT_ULP_FIELD_COND_SRC_CF: + if (!ulp_operand_read(fld->field_cond_opr, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); return -EINVAL; } - break; - case BNXT_ULP_FIELD_OPC_SET_TO_ZERO: - if (ulp_blob_pad_push(blob, bitlen) < 0) { - BNXT_TF_DBG(ERR, "%s too large for blob\n", name); + idx = tfp_be_to_cpu_16(idx); + if (idx >= BNXT_ULP_CF_IDX_LAST) { + BNXT_TF_DBG(ERR, "%s invalid index %u\n", name, idx); return -EINVAL; } + /* check if the computed field is set */ + if (ULP_COMP_FLD_IDX_RD(parms, idx)) + src1_sel = 1; break; - case BNXT_ULP_FIELD_OPC_SET_TO_REGFILE: - if (!ulp_operand_read(fld->field_operand, + case BNXT_ULP_FIELD_COND_SRC_RF: + if (!ulp_operand_read(fld->field_cond_opr, (uint8_t *)&idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; @@ -924,38 +933,78 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, name, idx); return -EINVAL; } - - val = ulp_blob_push_64(blob, ®val, bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + if (regval) + src1_sel = 1; + break; + case BNXT_ULP_FIELD_COND_SRC_ACT_BIT: + if (!ulp_operand_read(fld->field_cond_opr, + (uint8_t *)&act_bit, sizeof(uint64_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; } + act_bit = tfp_be_to_cpu_64(act_bit); + if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) + src1_sel = 1; break; - case BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE: - if (!ulp_operand_read(fld->field_operand, - (uint8_t *)&idx, + case BNXT_ULP_FIELD_COND_SRC_HDR_BIT: + if (!ulp_operand_read(fld->field_cond_opr, + (uint8_t *)&hdr_bit, sizeof(uint64_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + hdr_bit = tfp_be_to_cpu_64(hdr_bit); + if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) + src1_sel = 1; + break; + case BNXT_ULP_FIELD_COND_SRC_FIELD_BIT: + if (!ulp_operand_read(fld->field_cond_opr, (uint8_t *)&idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); - if (ulp_mapper_glb_resource_read(parms->mapper_data, - dir, - idx, ®val)) { - BNXT_TF_DBG(ERR, "%s global regfile[%d] read failed.\n", - name, idx); + /* get the index from the global field list */ + if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) { + BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", + idx); return -EINVAL; } - val = ulp_blob_push_64(blob, ®val, bitlen); - if (!val) { + if (bit && (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit))) + src1_sel = 1; + break; + default: + BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n", + name, fld->field_cond_src, write_idx); + return -EINVAL; + } + + /* pick the selected source */ + if (src1_sel) { + fld_src = fld->field_src1; + fld_src_oper = fld->field_opr1; + } else { + fld_src = fld->field_src2; + fld_src_oper = fld->field_opr2; + } + + /* Perform the action */ + switch (fld_src) { + case BNXT_ULP_FIELD_SRC_ZERO: + if (ulp_blob_pad_push(blob, bitlen) < 0) { + BNXT_TF_DBG(ERR, "%s too large for blob\n", name); + return -EINVAL; + } + break; + case BNXT_ULP_FIELD_SRC_CONST: + val = fld_src_oper; + if (!ulp_blob_push(blob, val, bitlen)) { BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } break; - case BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD: - if (!ulp_operand_read(fld->field_operand, - (uint8_t *)&idx, - sizeof(uint16_t))) { + case BNXT_ULP_FIELD_SRC_CF: + if (!ulp_operand_read(fld_src_oper, + (uint8_t *)&idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); return -EINVAL; @@ -969,126 +1018,29 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } break; - case BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST: - if (!ulp_operand_read(fld->field_operand, - (uint8_t *)&act_bit, sizeof(uint64_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - act_bit = tfp_be_to_cpu_64(act_bit); - if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) { - /* Action bit is set so consider operand_true */ - if (!ulp_operand_read(fld->field_operand_true, - (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, - "%s true operand read failed\n", - name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - if (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s act_prop[%d] oob\n", - name, idx); - return -EINVAL; - } - val = &parms->act_prop->act_details[idx]; - field_size = ulp_mapper_act_prop_size_get(idx); - if (bitlen < ULP_BYTE_2_BITS(field_size)) { - field_size = field_size - ((bitlen + 7) / 8); - val += field_size; - } - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", - name); - return -EINVAL; - } - } else { - /* action bit is not set, use the operand false */ - val = fld->field_operand_false; - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", - name); - return -EINVAL; - } - } - break; - case BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST: - if (!ulp_operand_read(fld->field_operand, - (uint8_t *)&act_bit, sizeof(uint64_t))) { + case BNXT_ULP_FIELD_SRC_RF: + if (!ulp_operand_read(fld_src_oper, + (uint8_t *)&idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; } - act_bit = tfp_be_to_cpu_64(act_bit); - if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) { - /* Action bit is set so consider operand_true */ - val = fld->field_operand_true; - } else { - /* action bit is not set, use the operand false */ - val = fld->field_operand_false; - } - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", - name); - return -EINVAL; - } - break; - case BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF: - if (!ulp_operand_read(fld->field_operand, - (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - if (idx >= BNXT_ULP_CF_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s invalid index %u\n", name, idx); - return -EINVAL; - } - /* check if the computed field is set */ - if (ULP_COMP_FLD_IDX_RD(parms, idx)) - val = fld->field_operand_true; - else - val = fld->field_operand_false; - /* read the appropriate computed field */ - if (!ulp_operand_read(val, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s val operand read failed\n", name); - return -EINVAL; - } idx = tfp_be_to_cpu_16(idx); - if (idx >= BNXT_ULP_CF_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s invalid index %u\n", name, idx); + /* Uninitialized regfile entries return 0 */ + if (!ulp_regfile_read(parms->regfile, idx, ®val)) { + BNXT_TF_DBG(ERR, "%s regfile[%d] read oob\n", + name, idx); return -EINVAL; } - val = ulp_blob_push_32(blob, &parms->comp_fld[idx], bitlen); + + val = ulp_blob_push_64(blob, ®val, bitlen); if (!val) { BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); return -EINVAL; } break; - case BNXT_ULP_FIELD_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST: - if (!ulp_operand_read(fld->field_operand, - (uint8_t *)&hdr_bit, sizeof(uint64_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - hdr_bit = tfp_be_to_cpu_64(hdr_bit); - if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) { - /* Header bit is set so consider operand_true */ - val = fld->field_operand_true; - } else { - /* Header bit is not set, use the operand false */ - val = fld->field_operand_false; - } - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", - name); - return -EINVAL; - } - break; - case BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP: - if (!ulp_operand_read(fld->field_operand, + case BNXT_ULP_FIELD_SRC_ACT_PROP: + if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; @@ -1110,28 +1062,8 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } break; - case BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT: - if (!ulp_operand_read(fld->field_operand, - (uint8_t *)&act_bit, sizeof(uint64_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - act_bit = tfp_be_to_cpu_64(act_bit); - memset(act_val, 0, sizeof(act_val)); - if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) - act_val[0] = 1; - if (bitlen > ULP_BYTE_2_BITS(sizeof(act_val))) { - BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); - return -EINVAL; - } - if (!ulp_blob_push(blob, act_val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); - return -EINVAL; - } - val = act_val; - break; - case BNXT_ULP_FIELD_OPC_SET_TO_ENCAP_ACT_PROP_SZ: - if (!ulp_operand_read(fld->field_operand, + case BNXT_ULP_FIELD_SRC_ACT_PROP_SZ: + if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; @@ -1145,7 +1077,7 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, val = &parms->act_prop->act_details[idx]; /* get the size index next */ - if (!ulp_operand_read(&fld->field_operand[sizeof(uint16_t)], + if (!ulp_operand_read(&fld_src_oper[sizeof(uint16_t)], (uint8_t *)&size_idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed\n", name); return -EINVAL; @@ -1162,8 +1094,29 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, val_size = ULP_BYTE_2_BITS(val_size); ulp_blob_push_encap(blob, val, val_size); break; - case BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD: - if (!ulp_operand_read(fld->field_operand, (uint8_t *)&idx, + case BNXT_ULP_FIELD_SRC_GLB_RF: + if (!ulp_operand_read(fld_src_oper, + (uint8_t *)&idx, + sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); + return -EINVAL; + } + idx = tfp_be_to_cpu_16(idx); + if (ulp_mapper_glb_resource_read(parms->mapper_data, + dir, + idx, ®val)) { + BNXT_TF_DBG(ERR, "%s global regfile[%d] read failed.\n", + name, idx); + return -EINVAL; + } + val = ulp_blob_push_64(blob, ®val, bitlen); + if (!val) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + break; + case BNXT_ULP_FIELD_SRC_HF: + if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx, sizeof(uint16_t))) { BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); return -EINVAL; @@ -1195,9 +1148,80 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } break; + case BNXT_ULP_FIELD_SRC_HDR_BIT: + if (!ulp_operand_read(fld_src_oper, + (uint8_t *)&hdr_bit, sizeof(uint64_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + hdr_bit = tfp_be_to_cpu_64(hdr_bit); + memset(tmpval, 0, sizeof(tmpval)); + if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) + tmpval[0] = 1; + if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) { + BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); + return -EINVAL; + } + if (!ulp_blob_push(blob, tmpval, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + val = tmpval; + break; + case BNXT_ULP_FIELD_SRC_ACT_BIT: + if (!ulp_operand_read(fld_src_oper, + (uint8_t *)&act_bit, sizeof(uint64_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + act_bit = tfp_be_to_cpu_64(act_bit); + memset(tmpval, 0, sizeof(tmpval)); + if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) + tmpval[0] = 1; + if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) { + BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); + return -EINVAL; + } + if (!ulp_blob_push(blob, tmpval, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + val = tmpval; + break; + case BNXT_ULP_FIELD_SRC_FIELD_BIT: + if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx, + sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); + return -EINVAL; + } + idx = tfp_be_to_cpu_16(idx); + /* get the index from the global field list */ + if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) { + BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", + idx); + return -EINVAL; + } + memset(tmpval, 0, sizeof(tmpval)); + if (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit)) + tmpval[0] = 1; + if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) { + BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); + return -EINVAL; + } + if (!ulp_blob_push(blob, tmpval, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + val = tmpval; + break; + case BNXT_ULP_FIELD_SRC_SKIP: + /* do nothing */ + break; + case BNXT_ULP_FIELD_SRC_REJECT: + return -EINVAL; default: BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n", - name, fld->field_opcode, write_idx); + name, fld_src, write_idx); return -EINVAL; } return 0; @@ -1267,7 +1291,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms, if (mark_op == BNXT_ULP_MARK_DB_OPC_NOP || !(mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION && ULP_BITMAP_ISSET(parms->act_bitmap->bits, - BNXT_ULP_ACTION_BIT_MARK))) + BNXT_ULP_ACT_BIT_MARK))) return rc; /* no need to perform gfid process */ /* Get the mark id details from action property */ @@ -1308,7 +1332,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms, if (mark_op == BNXT_ULP_MARK_DB_OPC_NOP || !(mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION && ULP_BITMAP_ISSET(parms->act_bitmap->bits, - BNXT_ULP_ACTION_BIT_MARK))) + BNXT_ULP_ACT_BIT_MARK))) return rc; /* no need to perform mark action process */ /* Get the mark id details from action property */ @@ -2500,7 +2524,7 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, uint64_t regval; switch (opc) { - case BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET: + case BNXT_ULP_COND_OPC_CF_IS_SET: if (operand < BNXT_ULP_CF_IDX_LAST) { *res = ULP_COMP_FLD_IDX_RD(parms, operand); } else { @@ -2509,7 +2533,7 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, rc = -EINVAL; } break; - case BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET: + case BNXT_ULP_COND_OPC_CF_NOT_SET: if (operand < BNXT_ULP_CF_IDX_LAST) { *res = !ULP_COMP_FLD_IDX_RD(parms, operand); } else { @@ -2518,8 +2542,8 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, rc = -EINVAL; } break; - case BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET: - if (operand < BNXT_ULP_ACTION_BIT_LAST) { + case BNXT_ULP_COND_OPC_ACT_BIT_IS_SET: + if (operand < BNXT_ULP_ACT_BIT_LAST) { *res = ULP_BITMAP_ISSET(parms->act_bitmap->bits, operand); } else { @@ -2528,8 +2552,8 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, rc = -EINVAL; } break; - case BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET: - if (operand < BNXT_ULP_ACTION_BIT_LAST) { + case BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET: + if (operand < BNXT_ULP_ACT_BIT_LAST) { *res = !ULP_BITMAP_ISSET(parms->act_bitmap->bits, operand); } else { @@ -2576,14 +2600,14 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, } *res = !ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit); break; - case BNXT_ULP_COND_OPC_REGFILE_IS_SET: + case BNXT_ULP_COND_OPC_RF_IS_SET: if (!ulp_regfile_read(parms->regfile, operand, ®val)) { BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand); return -EINVAL; } *res = regval != 0; break; - case BNXT_ULP_COND_OPC_REGFILE_NOT_SET: + case BNXT_ULP_COND_OPC_RF_NOT_SET: if (!ulp_regfile_read(parms->regfile, operand, ®val)) { BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand); return -EINVAL; @@ -2733,8 +2757,9 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) enum bnxt_ulp_cond_list_opc cond_opc; struct bnxt_ulp_mapper_tbl_info *tbls; struct bnxt_ulp_mapper_tbl_info *tbl; - uint32_t num_tbls, i, num_cond_tbls; + uint32_t num_tbls, tbl_idx, num_cond_tbls; int32_t rc = -EINVAL, cond_rc = 0; + uint32_t cond_goto = 1; cond_tbls = ulp_mapper_tmpl_reject_list_get(parms, tid, &num_cond_tbls, @@ -2769,12 +2794,15 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) return -EINVAL; } - for (i = 0; i < num_tbls; i++) { - tbl = &tbls[i]; - + for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) { + tbl = &tbls[tbl_idx]; + cond_goto = tbl->execute_info.cond_goto; /* Handle the table level opcodes to determine if required. */ - if (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) + if (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) { + tbl_idx += 1; continue; + } + cond_tbls = ulp_mapper_tbl_execute_list_get(parms, tbl, &num_cond_tbls, &cond_opc); @@ -2787,8 +2815,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) return rc; } /* Skip the table if False */ - if (!cond_rc) + if (!cond_rc) { + tbl_idx += 1; continue; + } /* process the fdb opcode for alloc push */ if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE) { @@ -2817,6 +2847,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) rc = ulp_mapper_gen_tbl_process(parms, tbl); break; case BNXT_ULP_RESOURCE_FUNC_INVALID: + case BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE: rc = 0; break; default: @@ -2840,6 +2871,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) rc = -EINVAL; goto error; } + tbl_idx += cond_goto; } return rc; @@ -3081,6 +3113,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, parms.hdr_bitmap = cparms->hdr_bitmap; parms.regfile = ®file; parms.hdr_field = cparms->hdr_field; + parms.fld_bitmap = cparms->fld_bitmap; parms.comp_fld = cparms->comp_fld; parms.tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); parms.ulp_ctx = ulp_ctx; diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 7c048a33a0..02e2b7fdc0 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -274,7 +274,7 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params) /* Update the decrement ttl computational fields */ if (ULP_BITMAP_ISSET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_DEC_TTL)) { + BNXT_ULP_ACT_BIT_DEC_TTL)) { /* * Check that vxlan proto is included and vxlan decap * action is not set then decrement tunnel ttl. @@ -283,7 +283,7 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params) if ((ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_VXLAN) && !ULP_BITMAP_ISSET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_VXLAN_DECAP))) { + BNXT_ULP_ACT_BIT_VXLAN_DECAP))) { ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_T_DEC_TTL, 1); } else { @@ -1439,7 +1439,7 @@ ulp_rte_mark_act_handler(const struct rte_flow_action *action_item, &mark_id, BNXT_ULP_ACT_PROP_SZ_MARK); /* Update the hdr_bitmap with vxlan */ - ULP_BITMAP_SET(act->bits, BNXT_ULP_ACTION_BIT_MARK); + ULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_MARK); return BNXT_TF_RC_SUCCESS; } BNXT_TF_DBG(ERR, "Parse Error: Mark arg is invalid\n"); @@ -1455,7 +1455,7 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item, if (rss) { /* Update the hdr_bitmap with vxlan */ - ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACTION_BIT_RSS); + ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_RSS); return BNXT_TF_RC_SUCCESS; } BNXT_TF_DBG(ERR, "Parse Error: RSS arg is invalid\n"); @@ -1728,7 +1728,7 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item, &vxlan_size, sizeof(uint32_t)); /* update the hdr_bitmap with vxlan */ - ULP_BITMAP_SET(act->bits, BNXT_ULP_ACTION_BIT_VXLAN_ENCAP); + ULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_VXLAN_ENCAP); return BNXT_TF_RC_SUCCESS; } @@ -1740,7 +1740,7 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item { /* update the hdr_bitmap with vxlan */ ULP_BITMAP_SET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_VXLAN_DECAP); + BNXT_ULP_ACT_BIT_VXLAN_DECAP); /* Update computational field with tunnel decap info */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1); @@ -1753,7 +1753,7 @@ ulp_rte_drop_act_handler(const struct rte_flow_action *action_item __rte_unused, struct ulp_rte_parser_params *params) { /* Update the hdr_bitmap with drop */ - ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_DROP); + ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_DROP); return BNXT_TF_RC_SUCCESS; } @@ -1779,7 +1779,7 @@ ulp_rte_count_act_handler(const struct rte_flow_action *action_item, } /* Update the hdr_bitmap with count */ - ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_COUNT); + ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_COUNT); return BNXT_TF_RC_SUCCESS; } @@ -1992,7 +1992,7 @@ ulp_rte_of_pop_vlan_act_handler(const struct rte_flow_action *a __rte_unused, struct ulp_rte_parser_params *params) { /* Update the act_bitmap with pop */ - ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_POP_VLAN); + ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_POP_VLAN); return BNXT_TF_RC_SUCCESS; } @@ -2017,7 +2017,7 @@ ulp_rte_of_push_vlan_act_handler(const struct rte_flow_action *action_item, ðertype, BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN); /* Update the hdr_bitmap with push vlan */ ULP_BITMAP_SET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_PUSH_VLAN); + BNXT_ULP_ACT_BIT_PUSH_VLAN); return BNXT_TF_RC_SUCCESS; } BNXT_TF_DBG(ERR, "Parse Error: Push vlan arg is invalid\n"); @@ -2040,7 +2040,7 @@ ulp_rte_of_set_vlan_vid_act_handler(const struct rte_flow_action *action_item, &vid, BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID); /* Update the hdr_bitmap with vlan vid */ ULP_BITMAP_SET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_SET_VLAN_VID); + BNXT_ULP_ACT_BIT_SET_VLAN_VID); return BNXT_TF_RC_SUCCESS; } BNXT_TF_DBG(ERR, "Parse Error: Vlan vid arg is invalid\n"); @@ -2063,7 +2063,7 @@ ulp_rte_of_set_vlan_pcp_act_handler(const struct rte_flow_action *action_item, &pcp, BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP); /* Update the hdr_bitmap with vlan vid */ ULP_BITMAP_SET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_SET_VLAN_PCP); + BNXT_ULP_ACT_BIT_SET_VLAN_PCP); return BNXT_TF_RC_SUCCESS; } BNXT_TF_DBG(ERR, "Parse Error: Vlan pcp arg is invalid\n"); @@ -2084,7 +2084,7 @@ ulp_rte_set_ipv4_src_act_handler(const struct rte_flow_action *action_item, &set_ipv4->ipv4_addr, BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC); /* Update the hdr_bitmap with set ipv4 src */ ULP_BITMAP_SET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC); + BNXT_ULP_ACT_BIT_SET_IPV4_SRC); return BNXT_TF_RC_SUCCESS; } BNXT_TF_DBG(ERR, "Parse Error: set ipv4 src arg is invalid\n"); @@ -2105,7 +2105,7 @@ ulp_rte_set_ipv4_dst_act_handler(const struct rte_flow_action *action_item, &set_ipv4->ipv4_addr, BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST); /* Update the hdr_bitmap with set ipv4 dst */ ULP_BITMAP_SET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_SET_IPV4_DST); + BNXT_ULP_ACT_BIT_SET_IPV4_DST); return BNXT_TF_RC_SUCCESS; } BNXT_TF_DBG(ERR, "Parse Error: set ipv4 dst arg is invalid\n"); @@ -2126,7 +2126,7 @@ ulp_rte_set_tp_src_act_handler(const struct rte_flow_action *action_item, &set_tp->port, BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC); /* Update the hdr_bitmap with set tp src */ ULP_BITMAP_SET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_SET_TP_SRC); + BNXT_ULP_ACT_BIT_SET_TP_SRC); return BNXT_TF_RC_SUCCESS; } @@ -2148,7 +2148,7 @@ ulp_rte_set_tp_dst_act_handler(const struct rte_flow_action *action_item, &set_tp->port, BNXT_ULP_ACT_PROP_SZ_SET_TP_DST); /* Update the hdr_bitmap with set tp dst */ ULP_BITMAP_SET(params->act_bitmap.bits, - BNXT_ULP_ACTION_BIT_SET_TP_DST); + BNXT_ULP_ACT_BIT_SET_TP_DST); return BNXT_TF_RC_SUCCESS; } @@ -2162,7 +2162,7 @@ ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *act __rte_unused, struct ulp_rte_parser_params *params) { /* Update the act_bitmap with dec ttl */ - ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_DEC_TTL); + ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_DEC_TTL); return BNXT_TF_RC_SUCCESS; } @@ -2172,6 +2172,6 @@ ulp_rte_jump_act_handler(const struct rte_flow_action *action_item __rte_unused, struct ulp_rte_parser_params *params) { /* Update the act_bitmap with dec ttl */ - ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP); + ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP); return BNXT_TF_RC_SUCCESS; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index 509cbd26a8..fa7d67bcd0 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Nov 23 17:33:02 2020 */ +/* date: Tue Dec 1 11:40:24 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -42,101 +42,101 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [2] = { .act_hid = BNXT_ULP_ACT_HID_0001, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DROP | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [3] = { .act_hid = BNXT_ULP_ACT_HID_0400, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [4] = { .act_hid = BNXT_ULP_ACT_HID_0331, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [5] = { .act_hid = BNXT_ULP_ACT_HID_0010, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [6] = { .act_hid = BNXT_ULP_ACT_HID_0731, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [7] = { .act_hid = BNXT_ULP_ACT_HID_0341, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [8] = { .act_hid = BNXT_ULP_ACT_HID_0002, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [9] = { .act_hid = BNXT_ULP_ACT_HID_0003, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DROP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [10] = { .act_hid = BNXT_ULP_ACT_HID_0402, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [11] = { .act_hid = BNXT_ULP_ACT_HID_0333, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [12] = { .act_hid = BNXT_ULP_ACT_HID_0012, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [13] = { .act_hid = BNXT_ULP_ACT_HID_0733, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DEC_TTL | - BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [14] = { .act_hid = BNXT_ULP_ACT_HID_0343, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index 38f523aa7a..a5133f7caf 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Nov 23 17:33:02 2020 */ +/* date: Tue Dec 1 11:40:24 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -16,837 +16,1450 @@ * maps hash id to ulp_class_match_list[] index */ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_00fc] = 1, - [BNXT_ULP_CLASS_HID_0046] = 2, - [BNXT_ULP_CLASS_HID_0056] = 3, - [BNXT_ULP_CLASS_HID_00b8] = 4, - [BNXT_ULP_CLASS_HID_0041] = 5, - [BNXT_ULP_CLASS_HID_00ab] = 6, - [BNXT_ULP_CLASS_HID_0053] = 7, - [BNXT_ULP_CLASS_HID_00a5] = 8, - [BNXT_ULP_CLASS_HID_0069] = 9, - [BNXT_ULP_CLASS_HID_009d] = 10, - [BNXT_ULP_CLASS_HID_0005] = 11, - [BNXT_ULP_CLASS_HID_006f] = 12, - [BNXT_ULP_CLASS_HID_00af] = 13, - [BNXT_ULP_CLASS_HID_00d3] = 14, - [BNXT_ULP_CLASS_HID_005b] = 15, - [BNXT_ULP_CLASS_HID_00ad] = 16, - [BNXT_ULP_CLASS_HID_0091] = 17, - [BNXT_ULP_CLASS_HID_00fb] = 18, - [BNXT_ULP_CLASS_HID_0063] = 19, - [BNXT_ULP_CLASS_HID_0097] = 20, - [BNXT_ULP_CLASS_HID_00cc] = 21, - [BNXT_ULP_CLASS_HID_00f0] = 22, - [BNXT_ULP_CLASS_HID_00c0] = 23, - [BNXT_ULP_CLASS_HID_002a] = 24, - [BNXT_ULP_CLASS_HID_00c7] = 25, - [BNXT_ULP_CLASS_HID_0029] = 26, - [BNXT_ULP_CLASS_HID_00d1] = 27, - [BNXT_ULP_CLASS_HID_003b] = 28, - [BNXT_ULP_CLASS_HID_00ef] = 29, - [BNXT_ULP_CLASS_HID_0013] = 30, - [BNXT_ULP_CLASS_HID_009b] = 31, - [BNXT_ULP_CLASS_HID_00ed] = 32, - [BNXT_ULP_CLASS_HID_002d] = 33, - [BNXT_ULP_CLASS_HID_0051] = 34, - [BNXT_ULP_CLASS_HID_00d9] = 35, - [BNXT_ULP_CLASS_HID_0023] = 36, - [BNXT_ULP_CLASS_HID_0017] = 37, - [BNXT_ULP_CLASS_HID_0079] = 38, - [BNXT_ULP_CLASS_HID_00e1] = 39, - [BNXT_ULP_CLASS_HID_0015] = 40 + [BNXT_ULP_CLASS_HID_07e0] = 1, + [BNXT_ULP_CLASS_HID_01dc] = 2, + [BNXT_ULP_CLASS_HID_006e] = 3, + [BNXT_ULP_CLASS_HID_025a] = 4, + [BNXT_ULP_CLASS_HID_0146] = 5, + [BNXT_ULP_CLASS_HID_0332] = 6, + [BNXT_ULP_CLASS_HID_01c4] = 7, + [BNXT_ULP_CLASS_HID_078a] = 8, + [BNXT_ULP_CLASS_HID_02ed] = 9, + [BNXT_ULP_CLASS_HID_04d9] = 10, + [BNXT_ULP_CLASS_HID_036b] = 11, + [BNXT_ULP_CLASS_HID_0131] = 12, + [BNXT_ULP_CLASS_HID_0217] = 13, + [BNXT_ULP_CLASS_HID_03c3] = 14, + [BNXT_ULP_CLASS_HID_0295] = 15, + [BNXT_ULP_CLASS_HID_0441] = 16, + [BNXT_ULP_CLASS_HID_0095] = 17, + [BNXT_ULP_CLASS_HID_0241] = 18, + [BNXT_ULP_CLASS_HID_04ed] = 19, + [BNXT_ULP_CLASS_HID_06d9] = 20, + [BNXT_ULP_CLASS_HID_07bf] = 21, + [BNXT_ULP_CLASS_HID_016b] = 22, + [BNXT_ULP_CLASS_HID_0417] = 23, + [BNXT_ULP_CLASS_HID_05c3] = 24, + [BNXT_ULP_CLASS_HID_0187] = 25, + [BNXT_ULP_CLASS_HID_0373] = 26, + [BNXT_ULP_CLASS_HID_0205] = 27, + [BNXT_ULP_CLASS_HID_03f1] = 28, + [BNXT_ULP_CLASS_HID_00a1] = 29, + [BNXT_ULP_CLASS_HID_029d] = 30, + [BNXT_ULP_CLASS_HID_012f] = 31, + [BNXT_ULP_CLASS_HID_031b] = 32, + [BNXT_ULP_CLASS_HID_072f] = 33, + [BNXT_ULP_CLASS_HID_011b] = 34, + [BNXT_ULP_CLASS_HID_0387] = 35, + [BNXT_ULP_CLASS_HID_0573] = 36, + [BNXT_ULP_CLASS_HID_0649] = 37, + [BNXT_ULP_CLASS_HID_0005] = 38, + [BNXT_ULP_CLASS_HID_02a1] = 39, + [BNXT_ULP_CLASS_HID_049d] = 40, + [BNXT_ULP_CLASS_HID_01ea] = 41, + [BNXT_ULP_CLASS_HID_03de] = 42, + [BNXT_ULP_CLASS_HID_0672] = 43, + [BNXT_ULP_CLASS_HID_0026] = 44, + [BNXT_ULP_CLASS_HID_0746] = 45, + [BNXT_ULP_CLASS_HID_010a] = 46, + [BNXT_ULP_CLASS_HID_03ae] = 47, + [BNXT_ULP_CLASS_HID_0592] = 48, + [BNXT_ULP_CLASS_HID_07d0] = 49, + [BNXT_ULP_CLASS_HID_01ec] = 50, + [BNXT_ULP_CLASS_HID_005e] = 51, + [BNXT_ULP_CLASS_HID_026a] = 52, + [BNXT_ULP_CLASS_HID_0176] = 53, + [BNXT_ULP_CLASS_HID_0302] = 54, + [BNXT_ULP_CLASS_HID_01f4] = 55, + [BNXT_ULP_CLASS_HID_07ba] = 56, + [BNXT_ULP_CLASS_HID_06a7] = 57, + [BNXT_ULP_CLASS_HID_006b] = 58, + [BNXT_ULP_CLASS_HID_0725] = 59, + [BNXT_ULP_CLASS_HID_00e9] = 60, + [BNXT_ULP_CLASS_HID_05d9] = 61, + [BNXT_ULP_CLASS_HID_078d] = 62, + [BNXT_ULP_CLASS_HID_065f] = 63, + [BNXT_ULP_CLASS_HID_0003] = 64, + [BNXT_ULP_CLASS_HID_045f] = 65, + [BNXT_ULP_CLASS_HID_0603] = 66, + [BNXT_ULP_CLASS_HID_00a7] = 67, + [BNXT_ULP_CLASS_HID_026b] = 68, + [BNXT_ULP_CLASS_HID_0371] = 69, + [BNXT_ULP_CLASS_HID_0525] = 70, + [BNXT_ULP_CLASS_HID_07d9] = 71, + [BNXT_ULP_CLASS_HID_018d] = 72, + [BNXT_ULP_CLASS_HID_0177] = 73, + [BNXT_ULP_CLASS_HID_033b] = 74, + [BNXT_ULP_CLASS_HID_05df] = 75, + [BNXT_ULP_CLASS_HID_0783] = 76, + [BNXT_ULP_CLASS_HID_0069] = 77, + [BNXT_ULP_CLASS_HID_025d] = 78, + [BNXT_ULP_CLASS_HID_00ef] = 79, + [BNXT_ULP_CLASS_HID_06a5] = 80, + [BNXT_ULP_CLASS_HID_02f1] = 81, + [BNXT_ULP_CLASS_HID_04a5] = 82, + [BNXT_ULP_CLASS_HID_0377] = 83, + [BNXT_ULP_CLASS_HID_053b] = 84, + [BNXT_ULP_CLASS_HID_0601] = 85, + [BNXT_ULP_CLASS_HID_03df] = 86, + [BNXT_ULP_CLASS_HID_0269] = 87, + [BNXT_ULP_CLASS_HID_045d] = 88, + [BNXT_ULP_CLASS_HID_02dd] = 89, + [BNXT_ULP_CLASS_HID_04e9] = 90, + [BNXT_ULP_CLASS_HID_035b] = 91, + [BNXT_ULP_CLASS_HID_0101] = 92, + [BNXT_ULP_CLASS_HID_0227] = 93, + [BNXT_ULP_CLASS_HID_03f3] = 94, + [BNXT_ULP_CLASS_HID_02a5] = 95, + [BNXT_ULP_CLASS_HID_0471] = 96, + [BNXT_ULP_CLASS_HID_00a5] = 97, + [BNXT_ULP_CLASS_HID_0271] = 98, + [BNXT_ULP_CLASS_HID_04dd] = 99, + [BNXT_ULP_CLASS_HID_06e9] = 100, + [BNXT_ULP_CLASS_HID_078f] = 101, + [BNXT_ULP_CLASS_HID_015b] = 102, + [BNXT_ULP_CLASS_HID_0427] = 103, + [BNXT_ULP_CLASS_HID_05f3] = 104, + [BNXT_ULP_CLASS_HID_01b7] = 105, + [BNXT_ULP_CLASS_HID_0343] = 106, + [BNXT_ULP_CLASS_HID_0235] = 107, + [BNXT_ULP_CLASS_HID_03c1] = 108, + [BNXT_ULP_CLASS_HID_0091] = 109, + [BNXT_ULP_CLASS_HID_02ad] = 110, + [BNXT_ULP_CLASS_HID_011f] = 111, + [BNXT_ULP_CLASS_HID_032b] = 112, + [BNXT_ULP_CLASS_HID_071f] = 113, + [BNXT_ULP_CLASS_HID_012b] = 114, + [BNXT_ULP_CLASS_HID_03b7] = 115, + [BNXT_ULP_CLASS_HID_0543] = 116, + [BNXT_ULP_CLASS_HID_0679] = 117, + [BNXT_ULP_CLASS_HID_0035] = 118, + [BNXT_ULP_CLASS_HID_0291] = 119, + [BNXT_ULP_CLASS_HID_04ad] = 120, + [BNXT_ULP_CLASS_HID_01da] = 121, + [BNXT_ULP_CLASS_HID_03ee] = 122, + [BNXT_ULP_CLASS_HID_0642] = 123, + [BNXT_ULP_CLASS_HID_0016] = 124, + [BNXT_ULP_CLASS_HID_0776] = 125, + [BNXT_ULP_CLASS_HID_013a] = 126, + [BNXT_ULP_CLASS_HID_039e] = 127, + [BNXT_ULP_CLASS_HID_05a2] = 128, + [BNXT_ULP_CLASS_HID_0697] = 129, + [BNXT_ULP_CLASS_HID_005b] = 130, + [BNXT_ULP_CLASS_HID_0715] = 131, + [BNXT_ULP_CLASS_HID_00d9] = 132, + [BNXT_ULP_CLASS_HID_05e9] = 133, + [BNXT_ULP_CLASS_HID_07bd] = 134, + [BNXT_ULP_CLASS_HID_066f] = 135, + [BNXT_ULP_CLASS_HID_0033] = 136, + [BNXT_ULP_CLASS_HID_046f] = 137, + [BNXT_ULP_CLASS_HID_0633] = 138, + [BNXT_ULP_CLASS_HID_0097] = 139, + [BNXT_ULP_CLASS_HID_025b] = 140, + [BNXT_ULP_CLASS_HID_0341] = 141, + [BNXT_ULP_CLASS_HID_0515] = 142, + [BNXT_ULP_CLASS_HID_07e9] = 143, + [BNXT_ULP_CLASS_HID_01bd] = 144, + [BNXT_ULP_CLASS_HID_0147] = 145, + [BNXT_ULP_CLASS_HID_030b] = 146, + [BNXT_ULP_CLASS_HID_05ef] = 147, + [BNXT_ULP_CLASS_HID_07b3] = 148, + [BNXT_ULP_CLASS_HID_0059] = 149, + [BNXT_ULP_CLASS_HID_026d] = 150, + [BNXT_ULP_CLASS_HID_00df] = 151, + [BNXT_ULP_CLASS_HID_0695] = 152, + [BNXT_ULP_CLASS_HID_02c1] = 153, + [BNXT_ULP_CLASS_HID_0495] = 154, + [BNXT_ULP_CLASS_HID_0347] = 155, + [BNXT_ULP_CLASS_HID_050b] = 156, + [BNXT_ULP_CLASS_HID_0631] = 157, + [BNXT_ULP_CLASS_HID_03ef] = 158, + [BNXT_ULP_CLASS_HID_0259] = 159, + [BNXT_ULP_CLASS_HID_046d] = 160 }; /* Array for the proto matcher list */ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { [1] = { - .class_hid = BNXT_ULP_CLASS_HID_00fc, + .class_hid = BNXT_ULP_CLASS_HID_07e0, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2] = { - .class_hid = BNXT_ULP_CLASS_HID_0046, + .class_hid = BNXT_ULP_CLASS_HID_01dc, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [3] = { - .class_hid = BNXT_ULP_CLASS_HID_0056, + .class_hid = BNXT_ULP_CLASS_HID_006e, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [4] = { - .class_hid = BNXT_ULP_CLASS_HID_00b8, + .class_hid = BNXT_ULP_CLASS_HID_025a, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 1, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [5] = { - .class_hid = BNXT_ULP_CLASS_HID_0041, + .class_hid = BNXT_ULP_CLASS_HID_0146, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 1, + .hdr_sig_id = 0, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [6] = { - .class_hid = BNXT_ULP_CLASS_HID_00ab, + .class_hid = BNXT_ULP_CLASS_HID_0332, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 1, + .hdr_sig_id = 0, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [7] = { - .class_hid = BNXT_ULP_CLASS_HID_0053, + .class_hid = BNXT_ULP_CLASS_HID_01c4, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 1, + .hdr_sig_id = 0, + .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [8] = { - .class_hid = BNXT_ULP_CLASS_HID_00a5, + .class_hid = BNXT_ULP_CLASS_HID_078a, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 0, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [9] = { - .class_hid = BNXT_ULP_CLASS_HID_0069, + .class_hid = BNXT_ULP_CLASS_HID_02ed, .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [10] = { - .class_hid = BNXT_ULP_CLASS_HID_009d, + .class_hid = BNXT_ULP_CLASS_HID_04d9, .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [11] = { - .class_hid = BNXT_ULP_CLASS_HID_0005, + .class_hid = BNXT_ULP_CLASS_HID_036b, .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [12] = { - .class_hid = BNXT_ULP_CLASS_HID_006f, + .class_hid = BNXT_ULP_CLASS_HID_0131, .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [13] = { - .class_hid = BNXT_ULP_CLASS_HID_00af, + .class_hid = BNXT_ULP_CLASS_HID_0217, .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [14] = { - .class_hid = BNXT_ULP_CLASS_HID_00d3, + .class_hid = BNXT_ULP_CLASS_HID_03c3, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 2, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [15] = { - .class_hid = BNXT_ULP_CLASS_HID_005b, + .class_hid = BNXT_ULP_CLASS_HID_0295, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 2, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [16] = { - .class_hid = BNXT_ULP_CLASS_HID_00ad, + .class_hid = BNXT_ULP_CLASS_HID_0441, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 2, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [17] = { - .class_hid = BNXT_ULP_CLASS_HID_0091, + .class_hid = BNXT_ULP_CLASS_HID_0095, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 2, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [18] = { - .class_hid = BNXT_ULP_CLASS_HID_00fb, + .class_hid = BNXT_ULP_CLASS_HID_0241, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 2, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [19] = { - .class_hid = BNXT_ULP_CLASS_HID_0063, + .class_hid = BNXT_ULP_CLASS_HID_04ed, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 2, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [20] = { - .class_hid = BNXT_ULP_CLASS_HID_0097, + .class_hid = BNXT_ULP_CLASS_HID_06d9, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 2, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [21] = { - .class_hid = BNXT_ULP_CLASS_HID_00cc, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 2, + .class_hid = BNXT_ULP_CLASS_HID_07bf, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [22] = { - .class_hid = BNXT_ULP_CLASS_HID_00f0, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 3, + .class_hid = BNXT_ULP_CLASS_HID_016b, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [23] = { - .class_hid = BNXT_ULP_CLASS_HID_00c0, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 3, + .class_hid = BNXT_ULP_CLASS_HID_0417, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [24] = { - .class_hid = BNXT_ULP_CLASS_HID_002a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 3, + .class_hid = BNXT_ULP_CLASS_HID_05c3, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [25] = { - .class_hid = BNXT_ULP_CLASS_HID_00c7, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_0187, + .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 3, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [26] = { - .class_hid = BNXT_ULP_CLASS_HID_0029, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_0373, + .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 3, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [27] = { - .class_hid = BNXT_ULP_CLASS_HID_00d1, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_0205, + .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 3, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [28] = { - .class_hid = BNXT_ULP_CLASS_HID_003b, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_03f1, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [29] = { - .class_hid = BNXT_ULP_CLASS_HID_00ef, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_00a1, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [30] = { - .class_hid = BNXT_ULP_CLASS_HID_0013, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_029d, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [31] = { - .class_hid = BNXT_ULP_CLASS_HID_009b, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_012f, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [32] = { - .class_hid = BNXT_ULP_CLASS_HID_00ed, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_031b, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [33] = { - .class_hid = BNXT_ULP_CLASS_HID_002d, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_072f, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [34] = { - .class_hid = BNXT_ULP_CLASS_HID_0051, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_011b, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [35] = { - .class_hid = BNXT_ULP_CLASS_HID_00d9, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_0387, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [36] = { - .class_hid = BNXT_ULP_CLASS_HID_0023, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_0573, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [37] = { - .class_hid = BNXT_ULP_CLASS_HID_0017, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_0649, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [38] = { - .class_hid = BNXT_ULP_CLASS_HID_0079, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_0005, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [39] = { - .class_hid = BNXT_ULP_CLASS_HID_00e1, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_02a1, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [40] = { - .class_hid = BNXT_ULP_CLASS_HID_0015, - .class_tid = 2, + .class_hid = BNXT_ULP_CLASS_HID_049d, + .class_tid = 1, .hdr_sig_id = 1, .flow_sig_id = 4, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [41] = { + .class_hid = BNXT_ULP_CLASS_HID_01ea, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [42] = { + .class_hid = BNXT_ULP_CLASS_HID_03de, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 5, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [43] = { + .class_hid = BNXT_ULP_CLASS_HID_0672, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 6, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [44] = { + .class_hid = BNXT_ULP_CLASS_HID_0026, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 6, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [45] = { + .class_hid = BNXT_ULP_CLASS_HID_0746, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 6, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [46] = { + .class_hid = BNXT_ULP_CLASS_HID_010a, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 6, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [47] = { + .class_hid = BNXT_ULP_CLASS_HID_03ae, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 6, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [48] = { + .class_hid = BNXT_ULP_CLASS_HID_0592, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 6, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [49] = { + .class_hid = BNXT_ULP_CLASS_HID_07d0, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 6, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [50] = { + .class_hid = BNXT_ULP_CLASS_HID_01ec, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 7, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [51] = { + .class_hid = BNXT_ULP_CLASS_HID_005e, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [52] = { + .class_hid = BNXT_ULP_CLASS_HID_026a, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [53] = { + .class_hid = BNXT_ULP_CLASS_HID_0176, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [54] = { + .class_hid = BNXT_ULP_CLASS_HID_0302, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [55] = { + .class_hid = BNXT_ULP_CLASS_HID_01f4, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [56] = { + .class_hid = BNXT_ULP_CLASS_HID_07ba, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [57] = { + .class_hid = BNXT_ULP_CLASS_HID_06a7, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [58] = { + .class_hid = BNXT_ULP_CLASS_HID_006b, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [59] = { + .class_hid = BNXT_ULP_CLASS_HID_0725, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [60] = { + .class_hid = BNXT_ULP_CLASS_HID_00e9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [61] = { + .class_hid = BNXT_ULP_CLASS_HID_05d9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [62] = { + .class_hid = BNXT_ULP_CLASS_HID_078d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 9, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [63] = { + .class_hid = BNXT_ULP_CLASS_HID_065f, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [64] = { + .class_hid = BNXT_ULP_CLASS_HID_0003, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [65] = { + .class_hid = BNXT_ULP_CLASS_HID_045f, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [66] = { + .class_hid = BNXT_ULP_CLASS_HID_0603, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -854,14 +1467,1933 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [67] = { + .class_hid = BNXT_ULP_CLASS_HID_00a7, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [68] = { + .class_hid = BNXT_ULP_CLASS_HID_026b, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [69] = { + .class_hid = BNXT_ULP_CLASS_HID_0371, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [70] = { + .class_hid = BNXT_ULP_CLASS_HID_0525, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [71] = { + .class_hid = BNXT_ULP_CLASS_HID_07d9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [72] = { + .class_hid = BNXT_ULP_CLASS_HID_018d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [73] = { + .class_hid = BNXT_ULP_CLASS_HID_0177, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [74] = { + .class_hid = BNXT_ULP_CLASS_HID_033b, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [75] = { + .class_hid = BNXT_ULP_CLASS_HID_05df, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [76] = { + .class_hid = BNXT_ULP_CLASS_HID_0783, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [77] = { + .class_hid = BNXT_ULP_CLASS_HID_0069, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [78] = { + .class_hid = BNXT_ULP_CLASS_HID_025d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [79] = { + .class_hid = BNXT_ULP_CLASS_HID_00ef, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [80] = { + .class_hid = BNXT_ULP_CLASS_HID_06a5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [81] = { + .class_hid = BNXT_ULP_CLASS_HID_02f1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [82] = { + .class_hid = BNXT_ULP_CLASS_HID_04a5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [83] = { + .class_hid = BNXT_ULP_CLASS_HID_0377, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [84] = { + .class_hid = BNXT_ULP_CLASS_HID_053b, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [85] = { + .class_hid = BNXT_ULP_CLASS_HID_0601, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [86] = { + .class_hid = BNXT_ULP_CLASS_HID_03df, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [87] = { + .class_hid = BNXT_ULP_CLASS_HID_0269, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [88] = { + .class_hid = BNXT_ULP_CLASS_HID_045d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [89] = { + .class_hid = BNXT_ULP_CLASS_HID_02dd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [90] = { + .class_hid = BNXT_ULP_CLASS_HID_04e9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [91] = { + .class_hid = BNXT_ULP_CLASS_HID_035b, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [92] = { + .class_hid = BNXT_ULP_CLASS_HID_0101, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [93] = { + .class_hid = BNXT_ULP_CLASS_HID_0227, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 10, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [94] = { + .class_hid = BNXT_ULP_CLASS_HID_03f3, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 11, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [95] = { + .class_hid = BNXT_ULP_CLASS_HID_02a5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [96] = { + .class_hid = BNXT_ULP_CLASS_HID_0471, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [97] = { + .class_hid = BNXT_ULP_CLASS_HID_00a5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [98] = { + .class_hid = BNXT_ULP_CLASS_HID_0271, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [99] = { + .class_hid = BNXT_ULP_CLASS_HID_04dd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [100] = { + .class_hid = BNXT_ULP_CLASS_HID_06e9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [101] = { + .class_hid = BNXT_ULP_CLASS_HID_078f, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [102] = { + .class_hid = BNXT_ULP_CLASS_HID_015b, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [103] = { + .class_hid = BNXT_ULP_CLASS_HID_0427, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [104] = { + .class_hid = BNXT_ULP_CLASS_HID_05f3, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [105] = { + .class_hid = BNXT_ULP_CLASS_HID_01b7, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [106] = { + .class_hid = BNXT_ULP_CLASS_HID_0343, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [107] = { + .class_hid = BNXT_ULP_CLASS_HID_0235, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [108] = { + .class_hid = BNXT_ULP_CLASS_HID_03c1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [109] = { + .class_hid = BNXT_ULP_CLASS_HID_0091, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [110] = { + .class_hid = BNXT_ULP_CLASS_HID_02ad, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [111] = { + .class_hid = BNXT_ULP_CLASS_HID_011f, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [112] = { + .class_hid = BNXT_ULP_CLASS_HID_032b, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [113] = { + .class_hid = BNXT_ULP_CLASS_HID_071f, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [114] = { + .class_hid = BNXT_ULP_CLASS_HID_012b, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [115] = { + .class_hid = BNXT_ULP_CLASS_HID_03b7, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [116] = { + .class_hid = BNXT_ULP_CLASS_HID_0543, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [117] = { + .class_hid = BNXT_ULP_CLASS_HID_0679, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [118] = { + .class_hid = BNXT_ULP_CLASS_HID_0035, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [119] = { + .class_hid = BNXT_ULP_CLASS_HID_0291, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [120] = { + .class_hid = BNXT_ULP_CLASS_HID_04ad, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [121] = { + .class_hid = BNXT_ULP_CLASS_HID_01da, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 12, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [122] = { + .class_hid = BNXT_ULP_CLASS_HID_03ee, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 13, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [123] = { + .class_hid = BNXT_ULP_CLASS_HID_0642, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [124] = { + .class_hid = BNXT_ULP_CLASS_HID_0016, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [125] = { + .class_hid = BNXT_ULP_CLASS_HID_0776, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [126] = { + .class_hid = BNXT_ULP_CLASS_HID_013a, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [127] = { + .class_hid = BNXT_ULP_CLASS_HID_039e, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [128] = { + .class_hid = BNXT_ULP_CLASS_HID_05a2, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [129] = { + .class_hid = BNXT_ULP_CLASS_HID_0697, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [130] = { + .class_hid = BNXT_ULP_CLASS_HID_005b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [131] = { + .class_hid = BNXT_ULP_CLASS_HID_0715, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [132] = { + .class_hid = BNXT_ULP_CLASS_HID_00d9, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [133] = { + .class_hid = BNXT_ULP_CLASS_HID_05e9, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 14, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [134] = { + .class_hid = BNXT_ULP_CLASS_HID_07bd, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 15, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [135] = { + .class_hid = BNXT_ULP_CLASS_HID_066f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [136] = { + .class_hid = BNXT_ULP_CLASS_HID_0033, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [137] = { + .class_hid = BNXT_ULP_CLASS_HID_046f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [138] = { + .class_hid = BNXT_ULP_CLASS_HID_0633, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [139] = { + .class_hid = BNXT_ULP_CLASS_HID_0097, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [140] = { + .class_hid = BNXT_ULP_CLASS_HID_025b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [141] = { + .class_hid = BNXT_ULP_CLASS_HID_0341, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [142] = { + .class_hid = BNXT_ULP_CLASS_HID_0515, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [143] = { + .class_hid = BNXT_ULP_CLASS_HID_07e9, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [144] = { + .class_hid = BNXT_ULP_CLASS_HID_01bd, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [145] = { + .class_hid = BNXT_ULP_CLASS_HID_0147, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [146] = { + .class_hid = BNXT_ULP_CLASS_HID_030b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [147] = { + .class_hid = BNXT_ULP_CLASS_HID_05ef, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [148] = { + .class_hid = BNXT_ULP_CLASS_HID_07b3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [149] = { + .class_hid = BNXT_ULP_CLASS_HID_0059, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [150] = { + .class_hid = BNXT_ULP_CLASS_HID_026d, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [151] = { + .class_hid = BNXT_ULP_CLASS_HID_00df, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [152] = { + .class_hid = BNXT_ULP_CLASS_HID_0695, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [153] = { + .class_hid = BNXT_ULP_CLASS_HID_02c1, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [154] = { + .class_hid = BNXT_ULP_CLASS_HID_0495, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [155] = { + .class_hid = BNXT_ULP_CLASS_HID_0347, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [156] = { + .class_hid = BNXT_ULP_CLASS_HID_050b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [157] = { + .class_hid = BNXT_ULP_CLASS_HID_0631, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [158] = { + .class_hid = BNXT_ULP_CLASS_HID_03ef, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [159] = { + .class_hid = BNXT_ULP_CLASS_HID_0259, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [160] = { + .class_hid = BNXT_ULP_CLASS_HID_046d, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 12d91e6aa4..fc342bef0a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Nov 23 17:33:02 2020 */ +/* date: Tue Dec 1 10:17:11 2020 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -12,13 +12,13 @@ #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 #define BNXT_ULP_GEN_TBL_MAX_SZ 6 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 41 -#define BNXT_ULP_CLASS_HID_LOW_PRIME 3793 +#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 161 +#define BNXT_ULP_CLASS_HID_LOW_PRIME 7669 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919 #define BNXT_ULP_CLASS_HID_SHFTR 24 #define BNXT_ULP_CLASS_HID_SHFTL 23 -#define BNXT_ULP_CLASS_HID_MASK 255 +#define BNXT_ULP_CLASS_HID_MASK 2047 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 15 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 @@ -30,18 +30,18 @@ #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 -#define BNXT_ULP_GLB_FIELD_TBL_SIZE 4441 -#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 273 -#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 14 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 385 +#define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033 +#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 38 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 192 +#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 10 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 341 #define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 10 -#define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 8 -#define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 41 -#define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 273 -#define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 14 -#define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 385 +#define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7 +#define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38 +#define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192 +#define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10 +#define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341 #define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 4 @@ -56,35 +56,35 @@ #define ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE 65 #define ULP_STINGRAY_ACT_COND_LIST_SIZE 2 -enum bnxt_ulp_action_bit { - BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001, - BNXT_ULP_ACTION_BIT_DROP = 0x0000000000000002, - BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004, - BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008, - BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010, - BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000020, - BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000040, - BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000080, - BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000100, - BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000000200, - BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000000400, - BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000000800, - BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000001000, - BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000002000, - BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000004000, - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000008000, - BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000010000, - BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000020000, - BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000040000, - BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000080000, - BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000100000, - BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000000200000, - BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000000400000, - BNXT_ULP_ACTION_BIT_JUMP = 0x0000000000800000, - BNXT_ULP_ACTION_BIT_SHARED = 0x0000000001000000, - BNXT_ULP_ACTION_BIT_SAMPLE = 0x0000000002000000, - BNXT_ULP_ACTION_BIT_SHARED_SAMPLE = 0x0000000004000000, - BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000 +enum bnxt_ulp_act_bit { + BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001, + BNXT_ULP_ACT_BIT_DROP = 0x0000000000000002, + BNXT_ULP_ACT_BIT_COUNT = 0x0000000000000004, + BNXT_ULP_ACT_BIT_RSS = 0x0000000000000008, + BNXT_ULP_ACT_BIT_METER = 0x0000000000000010, + BNXT_ULP_ACT_BIT_VXLAN_DECAP = 0x0000000000000020, + BNXT_ULP_ACT_BIT_POP_MPLS = 0x0000000000000040, + BNXT_ULP_ACT_BIT_PUSH_MPLS = 0x0000000000000080, + BNXT_ULP_ACT_BIT_MAC_SWAP = 0x0000000000000100, + BNXT_ULP_ACT_BIT_SET_MAC_SRC = 0x0000000000000200, + BNXT_ULP_ACT_BIT_SET_MAC_DST = 0x0000000000000400, + BNXT_ULP_ACT_BIT_POP_VLAN = 0x0000000000000800, + BNXT_ULP_ACT_BIT_PUSH_VLAN = 0x0000000000001000, + BNXT_ULP_ACT_BIT_SET_VLAN_PCP = 0x0000000000002000, + BNXT_ULP_ACT_BIT_SET_VLAN_VID = 0x0000000000004000, + BNXT_ULP_ACT_BIT_SET_IPV4_SRC = 0x0000000000008000, + BNXT_ULP_ACT_BIT_SET_IPV4_DST = 0x0000000000010000, + BNXT_ULP_ACT_BIT_SET_IPV6_SRC = 0x0000000000020000, + BNXT_ULP_ACT_BIT_SET_IPV6_DST = 0x0000000000040000, + BNXT_ULP_ACT_BIT_DEC_TTL = 0x0000000000080000, + BNXT_ULP_ACT_BIT_SET_TP_SRC = 0x0000000000100000, + BNXT_ULP_ACT_BIT_SET_TP_DST = 0x0000000000200000, + BNXT_ULP_ACT_BIT_VXLAN_ENCAP = 0x0000000000400000, + BNXT_ULP_ACT_BIT_JUMP = 0x0000000000800000, + BNXT_ULP_ACT_BIT_SHARED = 0x0000000001000000, + BNXT_ULP_ACT_BIT_SAMPLE = 0x0000000002000000, + BNXT_ULP_ACT_BIT_SHARED_SAMPLE = 0x0000000004000000, + BNXT_ULP_ACT_BIT_LAST = 0x0000000008000000 }; enum bnxt_ulp_hdr_bit { @@ -188,16 +188,16 @@ enum bnxt_ulp_cond_list_opc { }; enum bnxt_ulp_cond_opc { - BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET = 0, - BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET = 1, - BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET = 2, - BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET = 3, + BNXT_ULP_COND_OPC_CF_IS_SET = 0, + BNXT_ULP_COND_OPC_CF_NOT_SET = 1, + BNXT_ULP_COND_OPC_ACT_BIT_IS_SET = 2, + BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET = 3, BNXT_ULP_COND_OPC_HDR_BIT_IS_SET = 4, BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET = 5, BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET = 6, BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7, - BNXT_ULP_COND_OPC_REGFILE_IS_SET = 8, - BNXT_ULP_COND_OPC_REGFILE_NOT_SET = 9, + BNXT_ULP_COND_OPC_RF_IS_SET = 8, + BNXT_ULP_COND_OPC_RF_NOT_SET = 9, BNXT_ULP_COND_OPC_LAST = 10 }; @@ -241,26 +241,31 @@ enum bnxt_ulp_fdb_type { BNXT_ULP_FDB_TYPE_LAST = 3 }; -enum bnxt_ulp_field_opc { - BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT = 0, - BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD = 1, - BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD = 2, - BNXT_ULP_FIELD_OPC_SET_TO_REGFILE = 3, - BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE = 4, - BNXT_ULP_FIELD_OPC_SET_TO_ZERO = 5, - BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT = 6, - BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP = 7, - BNXT_ULP_FIELD_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8, - BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9, - BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10, - BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11, - BNXT_ULP_FIELD_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12, - BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_ACT_PROP_ELSE_CONST = 13, - BNXT_ULP_FIELD_OPC_IF_NOT_COMP_FIELD_THEN_ACT_PROP_ELSE_CONST = 14, - BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CONST_ELSE_CF = 15, - BNXT_ULP_FIELD_OPC_IF_NOT_COMP_FIELD_THEN_CONST_ELSE_CF = 16, - BNXT_ULP_FIELD_OPC_IF_FIELD_BIT_THEN_ONES_ELSE_ZERO = 17, - BNXT_ULP_FIELD_OPC_LAST = 18 +enum bnxt_ulp_field_cond_src { + BNXT_ULP_FIELD_COND_SRC_TRUE = 0, + BNXT_ULP_FIELD_COND_SRC_CF = 1, + BNXT_ULP_FIELD_COND_SRC_RF = 2, + BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3, + BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4, + BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5, + BNXT_ULP_FIELD_COND_SRC_LAST = 6 +}; + +enum bnxt_ulp_field_src { + BNXT_ULP_FIELD_SRC_ZERO = 0, + BNXT_ULP_FIELD_SRC_CONST = 1, + BNXT_ULP_FIELD_SRC_CF = 2, + BNXT_ULP_FIELD_SRC_RF = 3, + BNXT_ULP_FIELD_SRC_ACT_PROP = 4, + BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 5, + BNXT_ULP_FIELD_SRC_GLB_RF = 6, + BNXT_ULP_FIELD_SRC_HF = 7, + BNXT_ULP_FIELD_SRC_HDR_BIT = 8, + BNXT_ULP_FIELD_SRC_ACT_BIT = 9, + BNXT_ULP_FIELD_SRC_FIELD_BIT = 10, + BNXT_ULP_FIELD_SRC_SKIP = 11, + BNXT_ULP_FIELD_SRC_REJECT = 12, + BNXT_ULP_FIELD_SRC_LAST = 13 }; enum bnxt_ulp_generic_tbl_opc { @@ -409,7 +414,8 @@ enum bnxt_ulp_resource_func { BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84, BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85, BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86, - BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87 + BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87, + BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE = 0x88 }; enum bnxt_ulp_resource_sub_type { @@ -516,483 +522,603 @@ enum bnxt_ulp_act_prop_idx { BNXT_ULP_ACT_PROP_IDX_LAST = 269 }; -enum bnxt_ulp_wh_plus_sym { - BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_L2 = 0, - BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_0_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_0_L2 = 0, - BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_1_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_1_L2 = 0, - BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_ZERO = 0, - BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_ONE = 1, - BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_TWO = 2, - BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_THREE = 3, - BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_NO = 0, - BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_YES = 1, - BNXT_ULP_WH_PLUS_SYM_RESERVED_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_NO = 0, - BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL2_HDR_TYPE_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_HDR_TYPE_DIX = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_UC = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_MC = 2, - BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_BC = 3, - BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IPV4 = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IPV6 = 1, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_TCP = 0, - BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_UDP = 1, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_NO = 0, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_YES = 1, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_VXLAN = 0, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_GENEVE = 1, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NVGRE = 2, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_GRE = 3, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IPV4 = 4, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IPV6 = 5, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_PPPOE = 6, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_MPLS = 7, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_UPAR1 = 8, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_UPAR2 = 9, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE = 15, - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_FLAGS_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_DIX = 0, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_LLC_SNAP = 1, - BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_LLC = 2, - BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_UC = 0, - BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_MC = 2, - BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_BC = 3, - BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IPV4 = 0, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IPV6 = 1, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_ARP = 2, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_PTP = 3, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_EAPOL = 4, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_ROCE = 5, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_FCOE = 6, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_UPAR1 = 7, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_UPAR2 = 8, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_YES = 1, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_TCP = 0, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UDP = 1, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_ICMP = 2, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UPAR1 = 3, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UPAR2 = 4, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_BTH_V1 = 5, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_NO = 0, - BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_YES = 1, - BNXT_ULP_WH_PLUS_SYM_POP_VLAN_NO = 0, - BNXT_ULP_WH_PLUS_SYM_POP_VLAN_YES = 1, - BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_NONE = 0, - BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL2 = 3, - BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL3 = 8, - BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL4 = 9, - BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TUN = 10, - BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L2 = 11, - BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L3 = 12, - BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L4 = 13, - BNXT_ULP_WH_PLUS_SYM_ECV_VALID_NO = 0, - BNXT_ULP_WH_PLUS_SYM_ECV_VALID_YES = 1, - BNXT_ULP_WH_PLUS_SYM_ECV_CUSTOM_EN_NO = 0, - BNXT_ULP_WH_PLUS_SYM_ECV_CUSTOM_EN_YES = 1, - BNXT_ULP_WH_PLUS_SYM_ECV_L2_EN_NO = 0, - BNXT_ULP_WH_PLUS_SYM_ECV_L2_EN_YES = 1, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_NOP = 0, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, - BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_NONE = 0, - BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_IPV4 = 4, - BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_IPV6 = 5, - BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_MPLS_8847 = 6, - BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_MPLS_8848 = 7, - BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_NONE = 0, - BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP = 4, - BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_CSUM = 5, - BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, - BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, - BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NONE = 0, - BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_GENERIC = 1, - BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_VXLAN = 2, - BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NGE = 3, - BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NVGRE = 4, - BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_GRE = 5, - BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT = 1, - BNXT_ULP_WH_PLUS_SYM_EEM_EXT_FLOW_CNTR = 0, - BNXT_ULP_WH_PLUS_SYM_UC_ACT_REC = 0, - BNXT_ULP_WH_PLUS_SYM_MC_ACT_REC = 1, - BNXT_ULP_WH_PLUS_SYM_ACT_REC_DROP_YES = 1, - BNXT_ULP_WH_PLUS_SYM_ACT_REC_DROP_NO = 0, - BNXT_ULP_WH_PLUS_SYM_ACT_REC_POP_VLAN_YES = 1, - BNXT_ULP_WH_PLUS_SYM_ACT_REC_POP_VLAN_NO = 0, - BNXT_ULP_WH_PLUS_SYM_ACT_REC_METER_EN_YES = 1, - BNXT_ULP_WH_PLUS_SYM_ACT_REC_METER_EN_NO = 0, - BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT = 4, - BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PARIF = 15, - BNXT_ULP_WH_PLUS_SYM_EXT_EM_MAX_KEY_SIZE = 448, - BNXT_ULP_WH_PLUS_SYM_MATCH_TYPE_EM = 0, - BNXT_ULP_WH_PLUS_SYM_MATCH_TYPE_WM = 1, - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_ICMP = 1, - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_IGMP = 2, - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_IP_IN_IP = 4, - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP = 6, - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_UDP = 17, - BNXT_ULP_WH_PLUS_SYM_VF_FUNC_PARIF = 15, - BNXT_ULP_WH_PLUS_SYM_NO = 0, - BNXT_ULP_WH_PLUS_SYM_YES = 1, - BNXT_ULP_WH_PLUS_SYM_RECYCLE_DST = 0x800 -}; - -enum bnxt_ulp_stingray_sym { - BNXT_ULP_STINGRAY_SYM_PKT_TYPE_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_PKT_TYPE_L2 = 0, - BNXT_ULP_STINGRAY_SYM_PKT_TYPE_0_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_PKT_TYPE_0_L2 = 0, - BNXT_ULP_STINGRAY_SYM_PKT_TYPE_1_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_PKT_TYPE_1_L2 = 0, - BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_ZERO = 0, - BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_ONE = 1, - BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_TWO = 2, - BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_THREE = 3, - BNXT_ULP_STINGRAY_SYM_AGG_ERROR_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_AGG_ERROR_NO = 0, - BNXT_ULP_STINGRAY_SYM_AGG_ERROR_YES = 1, - BNXT_ULP_STINGRAY_SYM_RESERVED_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_HREC_NEXT_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_HREC_NEXT_NO = 0, - BNXT_ULP_STINGRAY_SYM_HREC_NEXT_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL2_HDR_TYPE_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL2_HDR_TYPE_DIX = 0, - BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_UC = 0, - BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_MC = 2, - BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_BC = 3, - BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IPV4 = 0, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IPV6 = 1, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_TCP = 0, - BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_UDP = 1, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_NO = 0, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_YES = 1, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_NO = 0, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_YES = 1, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_VXLAN = 0, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_GENEVE = 1, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NVGRE = 2, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_GRE = 3, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IPV4 = 4, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IPV6 = 5, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_PPPOE = 6, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_MPLS = 7, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_UPAR1 = 8, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_UPAR2 = 9, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE = 15, - BNXT_ULP_STINGRAY_SYM_TUN_HDR_FLAGS_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_NO = 0, - BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES = 1, - BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_NO = 0, - BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_YES = 1, - BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_DIX = 0, - BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_LLC_SNAP = 1, - BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_LLC = 2, - BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_UC = 0, - BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_MC = 2, - BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_BC = 3, - BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_NO = 0, - BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_YES = 1, - BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_NO = 0, - BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_YES = 1, - BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_NO = 0, - BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES = 1, - BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_NO = 0, - BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_YES = 1, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IPV4 = 0, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IPV6 = 1, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_ARP = 2, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_PTP = 3, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_EAPOL = 4, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_ROCE = 5, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_FCOE = 6, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_UPAR1 = 7, - BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_UPAR2 = 8, - BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_NO = 0, - BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_YES = 1, - BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_NO = 0, - BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_YES = 1, - BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_NO = 0, - BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_YES = 1, - BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_NO = 0, - BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES = 1, - BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_NO = 0, - BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_YES = 1, - BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_TCP = 0, - BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UDP = 1, - BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_ICMP = 2, - BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UPAR1 = 3, - BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UPAR2 = 4, - BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_BTH_V1 = 5, - BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, - BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_NO = 0, - BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_YES = 1, - BNXT_ULP_STINGRAY_SYM_POP_VLAN_NO = 0, - BNXT_ULP_STINGRAY_SYM_POP_VLAN_YES = 1, - BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_NONE = 0, - BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL2 = 3, - BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL3 = 8, - BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL4 = 9, - BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TUN = 10, - BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L2 = 11, - BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L3 = 12, - BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L4 = 13, - BNXT_ULP_STINGRAY_SYM_ECV_VALID_NO = 0, - BNXT_ULP_STINGRAY_SYM_ECV_VALID_YES = 1, - BNXT_ULP_STINGRAY_SYM_ECV_CUSTOM_EN_NO = 0, - BNXT_ULP_STINGRAY_SYM_ECV_CUSTOM_EN_YES = 1, - BNXT_ULP_STINGRAY_SYM_ECV_L2_EN_NO = 0, - BNXT_ULP_STINGRAY_SYM_ECV_L2_EN_YES = 1, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_NOP = 0, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, - BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_NONE = 0, - BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_IPV4 = 4, - BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_IPV6 = 5, - BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_MPLS_8847 = 6, - BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_MPLS_8848 = 7, - BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_NONE = 0, - BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP = 4, - BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_CSUM = 5, - BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, - BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, - BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NONE = 0, - BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_GENERIC = 1, - BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_VXLAN = 2, - BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NGE = 3, - BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NVGRE = 4, - BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_GRE = 5, - BNXT_ULP_STINGRAY_SYM_EEM_ACT_REC_INT = 0, - BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR = 1, - BNXT_ULP_STINGRAY_SYM_UC_ACT_REC = 0, - BNXT_ULP_STINGRAY_SYM_MC_ACT_REC = 1, - BNXT_ULP_STINGRAY_SYM_ACT_REC_DROP_YES = 1, - BNXT_ULP_STINGRAY_SYM_ACT_REC_DROP_NO = 0, - BNXT_ULP_STINGRAY_SYM_ACT_REC_POP_VLAN_YES = 1, - BNXT_ULP_STINGRAY_SYM_ACT_REC_POP_VLAN_NO = 0, - BNXT_ULP_STINGRAY_SYM_ACT_REC_METER_EN_YES = 1, - BNXT_ULP_STINGRAY_SYM_ACT_REC_METER_EN_NO = 0, - BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT = 16, - BNXT_ULP_STINGRAY_SYM_LOOPBACK_PARIF = 15, - BNXT_ULP_STINGRAY_SYM_EXT_EM_MAX_KEY_SIZE = 448, - BNXT_ULP_STINGRAY_SYM_MATCH_TYPE_EM = 0, - BNXT_ULP_STINGRAY_SYM_MATCH_TYPE_WM = 1, - BNXT_ULP_STINGRAY_SYM_IP_PROTO_ICMP = 1, - BNXT_ULP_STINGRAY_SYM_IP_PROTO_IGMP = 2, - BNXT_ULP_STINGRAY_SYM_IP_PROTO_IP_IN_IP = 4, - BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP = 6, - BNXT_ULP_STINGRAY_SYM_IP_PROTO_UDP = 17, - BNXT_ULP_STINGRAY_SYM_VF_FUNC_PARIF = 15, - BNXT_ULP_STINGRAY_SYM_NO = 0, - BNXT_ULP_STINGRAY_SYM_YES = 1, - BNXT_ULP_STINGRAY_SYM_RECYCLE_DST = 0x800 +enum ulp_wp_sym { + ULP_WP_SYM_PKT_TYPE_IGNORE = 0, + ULP_WP_SYM_PKT_TYPE_L2 = 0, + ULP_WP_SYM_PKT_TYPE_0_IGNORE = 0, + ULP_WP_SYM_PKT_TYPE_0_L2 = 0, + ULP_WP_SYM_PKT_TYPE_1_IGNORE = 0, + ULP_WP_SYM_PKT_TYPE_1_L2 = 0, + ULP_WP_SYM_RECYCLE_CNT_IGNORE = 0, + ULP_WP_SYM_RECYCLE_CNT_ZERO = 0, + ULP_WP_SYM_RECYCLE_CNT_ONE = 1, + ULP_WP_SYM_RECYCLE_CNT_TWO = 2, + ULP_WP_SYM_RECYCLE_CNT_THREE = 3, + ULP_WP_SYM_AGG_ERROR_IGNORE = 0, + ULP_WP_SYM_AGG_ERROR_NO = 0, + ULP_WP_SYM_AGG_ERROR_YES = 1, + ULP_WP_SYM_RESERVED_IGNORE = 0, + ULP_WP_SYM_HREC_NEXT_IGNORE = 0, + ULP_WP_SYM_HREC_NEXT_NO = 0, + ULP_WP_SYM_HREC_NEXT_YES = 1, + ULP_WP_SYM_TL2_HDR_VALID_IGNORE = 0, + ULP_WP_SYM_TL2_HDR_VALID_NO = 0, + ULP_WP_SYM_TL2_HDR_VALID_YES = 1, + ULP_WP_SYM_TL2_HDR_TYPE_IGNORE = 0, + ULP_WP_SYM_TL2_HDR_TYPE_DIX = 0, + ULP_WP_SYM_TL2_UC_MC_BC_IGNORE = 0, + ULP_WP_SYM_TL2_UC_MC_BC_UC = 0, + ULP_WP_SYM_TL2_UC_MC_BC_MC = 2, + ULP_WP_SYM_TL2_UC_MC_BC_BC = 3, + ULP_WP_SYM_TL2_VTAG_PRESENT_IGNORE = 0, + ULP_WP_SYM_TL2_VTAG_PRESENT_NO = 0, + ULP_WP_SYM_TL2_VTAG_PRESENT_YES = 1, + ULP_WP_SYM_TL2_TWO_VTAGS_IGNORE = 0, + ULP_WP_SYM_TL2_TWO_VTAGS_NO = 0, + ULP_WP_SYM_TL2_TWO_VTAGS_YES = 1, + ULP_WP_SYM_TL3_HDR_VALID_IGNORE = 0, + ULP_WP_SYM_TL3_HDR_VALID_NO = 0, + ULP_WP_SYM_TL3_HDR_VALID_YES = 1, + ULP_WP_SYM_TL3_HDR_ERROR_IGNORE = 0, + ULP_WP_SYM_TL3_HDR_ERROR_NO = 0, + ULP_WP_SYM_TL3_HDR_ERROR_YES = 1, + ULP_WP_SYM_TL3_HDR_TYPE_IGNORE = 0, + ULP_WP_SYM_TL3_HDR_TYPE_IPV4 = 0, + ULP_WP_SYM_TL3_HDR_TYPE_IPV6 = 1, + ULP_WP_SYM_TL3_HDR_ISIP_IGNORE = 0, + ULP_WP_SYM_TL3_HDR_ISIP_NO = 0, + ULP_WP_SYM_TL3_HDR_ISIP_YES = 1, + ULP_WP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, + ULP_WP_SYM_TL3_IPV6_CMP_SRC_NO = 0, + ULP_WP_SYM_TL3_IPV6_CMP_SRC_YES = 1, + ULP_WP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, + ULP_WP_SYM_TL3_IPV6_CMP_DST_NO = 0, + ULP_WP_SYM_TL3_IPV6_CMP_DST_YES = 1, + ULP_WP_SYM_TL4_HDR_VALID_IGNORE = 0, + ULP_WP_SYM_TL4_HDR_VALID_NO = 0, + ULP_WP_SYM_TL4_HDR_VALID_YES = 1, + ULP_WP_SYM_TL4_HDR_ERROR_IGNORE = 0, + ULP_WP_SYM_TL4_HDR_ERROR_NO = 0, + ULP_WP_SYM_TL4_HDR_ERROR_YES = 1, + ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, + ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, + ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, + ULP_WP_SYM_TL4_HDR_TYPE_IGNORE = 0, + ULP_WP_SYM_TL4_HDR_TYPE_TCP = 0, + ULP_WP_SYM_TL4_HDR_TYPE_UDP = 1, + ULP_WP_SYM_TUN_HDR_VALID_IGNORE = 0, + ULP_WP_SYM_TUN_HDR_VALID_NO = 0, + ULP_WP_SYM_TUN_HDR_VALID_YES = 1, + ULP_WP_SYM_TUN_HDR_ERROR_IGNORE = 0, + ULP_WP_SYM_TUN_HDR_ERROR_NO = 0, + ULP_WP_SYM_TUN_HDR_ERROR_YES = 1, + ULP_WP_SYM_TUN_HDR_TYPE_IGNORE = 0, + ULP_WP_SYM_TUN_HDR_TYPE_VXLAN = 0, + ULP_WP_SYM_TUN_HDR_TYPE_GENEVE = 1, + ULP_WP_SYM_TUN_HDR_TYPE_NVGRE = 2, + ULP_WP_SYM_TUN_HDR_TYPE_GRE = 3, + ULP_WP_SYM_TUN_HDR_TYPE_IPV4 = 4, + ULP_WP_SYM_TUN_HDR_TYPE_IPV6 = 5, + ULP_WP_SYM_TUN_HDR_TYPE_PPPOE = 6, + ULP_WP_SYM_TUN_HDR_TYPE_MPLS = 7, + ULP_WP_SYM_TUN_HDR_TYPE_UPAR1 = 8, + ULP_WP_SYM_TUN_HDR_TYPE_UPAR2 = 9, + ULP_WP_SYM_TUN_HDR_TYPE_NONE = 15, + ULP_WP_SYM_TUN_HDR_FLAGS_IGNORE = 0, + ULP_WP_SYM_L2_HDR_VALID_IGNORE = 0, + ULP_WP_SYM_L2_HDR_VALID_NO = 0, + ULP_WP_SYM_L2_HDR_VALID_YES = 1, + ULP_WP_SYM_L2_HDR_ERROR_IGNORE = 0, + ULP_WP_SYM_L2_HDR_ERROR_NO = 0, + ULP_WP_SYM_L2_HDR_ERROR_YES = 1, + ULP_WP_SYM_L2_HDR_TYPE_IGNORE = 0, + ULP_WP_SYM_L2_HDR_TYPE_DIX = 0, + ULP_WP_SYM_L2_HDR_TYPE_LLC_SNAP = 1, + ULP_WP_SYM_L2_HDR_TYPE_LLC = 2, + ULP_WP_SYM_L2_UC_MC_BC_IGNORE = 0, + ULP_WP_SYM_L2_UC_MC_BC_UC = 0, + ULP_WP_SYM_L2_UC_MC_BC_MC = 2, + ULP_WP_SYM_L2_UC_MC_BC_BC = 3, + ULP_WP_SYM_L2_VTAG_PRESENT_IGNORE = 0, + ULP_WP_SYM_L2_VTAG_PRESENT_NO = 0, + ULP_WP_SYM_L2_VTAG_PRESENT_YES = 1, + ULP_WP_SYM_L2_TWO_VTAGS_IGNORE = 0, + ULP_WP_SYM_L2_TWO_VTAGS_NO = 0, + ULP_WP_SYM_L2_TWO_VTAGS_YES = 1, + ULP_WP_SYM_L3_HDR_VALID_IGNORE = 0, + ULP_WP_SYM_L3_HDR_VALID_NO = 0, + ULP_WP_SYM_L3_HDR_VALID_YES = 1, + ULP_WP_SYM_L3_HDR_ERROR_IGNORE = 0, + ULP_WP_SYM_L3_HDR_ERROR_NO = 0, + ULP_WP_SYM_L3_HDR_ERROR_YES = 1, + ULP_WP_SYM_L3_HDR_TYPE_IGNORE = 0, + ULP_WP_SYM_L3_HDR_TYPE_IPV4 = 0, + ULP_WP_SYM_L3_HDR_TYPE_IPV6 = 1, + ULP_WP_SYM_L3_HDR_TYPE_ARP = 2, + ULP_WP_SYM_L3_HDR_TYPE_PTP = 3, + ULP_WP_SYM_L3_HDR_TYPE_EAPOL = 4, + ULP_WP_SYM_L3_HDR_TYPE_ROCE = 5, + ULP_WP_SYM_L3_HDR_TYPE_FCOE = 6, + ULP_WP_SYM_L3_HDR_TYPE_UPAR1 = 7, + ULP_WP_SYM_L3_HDR_TYPE_UPAR2 = 8, + ULP_WP_SYM_L3_HDR_ISIP_IGNORE = 0, + ULP_WP_SYM_L3_HDR_ISIP_NO = 0, + ULP_WP_SYM_L3_HDR_ISIP_YES = 1, + ULP_WP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, + ULP_WP_SYM_L3_IPV6_CMP_SRC_NO = 0, + ULP_WP_SYM_L3_IPV6_CMP_SRC_YES = 1, + ULP_WP_SYM_L3_IPV6_CMP_DST_IGNORE = 0, + ULP_WP_SYM_L3_IPV6_CMP_DST_NO = 0, + ULP_WP_SYM_L3_IPV6_CMP_DST_YES = 1, + ULP_WP_SYM_L4_HDR_VALID_IGNORE = 0, + ULP_WP_SYM_L4_HDR_VALID_NO = 0, + ULP_WP_SYM_L4_HDR_VALID_YES = 1, + ULP_WP_SYM_L4_HDR_ERROR_IGNORE = 0, + ULP_WP_SYM_L4_HDR_ERROR_NO = 0, + ULP_WP_SYM_L4_HDR_ERROR_YES = 1, + ULP_WP_SYM_L4_HDR_TYPE_IGNORE = 0, + ULP_WP_SYM_L4_HDR_TYPE_TCP = 0, + ULP_WP_SYM_L4_HDR_TYPE_UDP = 1, + ULP_WP_SYM_L4_HDR_TYPE_ICMP = 2, + ULP_WP_SYM_L4_HDR_TYPE_UPAR1 = 3, + ULP_WP_SYM_L4_HDR_TYPE_UPAR2 = 4, + ULP_WP_SYM_L4_HDR_TYPE_BTH_V1 = 5, + ULP_WP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, + ULP_WP_SYM_L4_HDR_IS_UDP_TCP_NO = 0, + ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1, + ULP_WP_SYM_POP_VLAN_NO = 0, + ULP_WP_SYM_POP_VLAN_YES = 1, + ULP_WP_SYM_DECAP_FUNC_NONE = 0, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2 = 3, + ULP_WP_SYM_DECAP_FUNC_THRU_TL3 = 8, + ULP_WP_SYM_DECAP_FUNC_THRU_TL4 = 9, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN = 10, + ULP_WP_SYM_DECAP_FUNC_THRU_L2 = 11, + ULP_WP_SYM_DECAP_FUNC_THRU_L3 = 12, + ULP_WP_SYM_DECAP_FUNC_THRU_L4 = 13, + ULP_WP_SYM_ECV_VALID_NO = 0, + ULP_WP_SYM_ECV_VALID_YES = 1, + ULP_WP_SYM_ECV_CUSTOM_EN_NO = 0, + ULP_WP_SYM_ECV_CUSTOM_EN_YES = 1, + ULP_WP_SYM_ECV_L2_EN_NO = 0, + ULP_WP_SYM_ECV_L2_EN_YES = 1, + ULP_WP_SYM_ECV_VTAG_TYPE_NOP = 0, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, + ULP_WP_SYM_ECV_L3_TYPE_NONE = 0, + ULP_WP_SYM_ECV_L3_TYPE_IPV4 = 4, + ULP_WP_SYM_ECV_L3_TYPE_IPV6 = 5, + ULP_WP_SYM_ECV_L3_TYPE_MPLS_8847 = 6, + ULP_WP_SYM_ECV_L3_TYPE_MPLS_8848 = 7, + ULP_WP_SYM_ECV_L4_TYPE_NONE = 0, + ULP_WP_SYM_ECV_L4_TYPE_UDP = 4, + ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM = 5, + ULP_WP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, + ULP_WP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, + ULP_WP_SYM_ECV_TUN_TYPE_NONE = 0, + ULP_WP_SYM_ECV_TUN_TYPE_GENERIC = 1, + ULP_WP_SYM_ECV_TUN_TYPE_VXLAN = 2, + ULP_WP_SYM_ECV_TUN_TYPE_NGE = 3, + ULP_WP_SYM_ECV_TUN_TYPE_NVGRE = 4, + ULP_WP_SYM_ECV_TUN_TYPE_GRE = 5, + ULP_WP_SYM_EEM_ACT_REC_INT = 1, + ULP_WP_SYM_EEM_EXT_FLOW_CNTR = 0, + ULP_WP_SYM_UC_ACT_REC = 0, + ULP_WP_SYM_MC_ACT_REC = 1, + ULP_WP_SYM_ACT_REC_DROP_YES = 1, + ULP_WP_SYM_ACT_REC_DROP_NO = 0, + ULP_WP_SYM_ACT_REC_POP_VLAN_YES = 1, + ULP_WP_SYM_ACT_REC_POP_VLAN_NO = 0, + ULP_WP_SYM_ACT_REC_METER_EN_YES = 1, + ULP_WP_SYM_ACT_REC_METER_EN_NO = 0, + ULP_WP_SYM_LOOPBACK_PORT = 4, + ULP_WP_SYM_LOOPBACK_PARIF = 15, + ULP_WP_SYM_EXT_EM_MAX_KEY_SIZE = 448, + ULP_WP_SYM_MATCH_TYPE_EM = 0, + ULP_WP_SYM_MATCH_TYPE_WM = 1, + ULP_WP_SYM_IP_PROTO_ICMP = 1, + ULP_WP_SYM_IP_PROTO_IGMP = 2, + ULP_WP_SYM_IP_PROTO_IP_IN_IP = 4, + ULP_WP_SYM_IP_PROTO_TCP = 6, + ULP_WP_SYM_IP_PROTO_UDP = 17, + ULP_WP_SYM_VF_FUNC_PARIF = 15, + ULP_WP_SYM_NO = 0, + ULP_WP_SYM_YES = 1, + ULP_WP_SYM_RECYCLE_DST = 0x800 +}; + +enum ulp_sr_sym { + ULP_SR_SYM_PKT_TYPE_IGNORE = 0, + ULP_SR_SYM_PKT_TYPE_L2 = 0, + ULP_SR_SYM_PKT_TYPE_0_IGNORE = 0, + ULP_SR_SYM_PKT_TYPE_0_L2 = 0, + ULP_SR_SYM_PKT_TYPE_1_IGNORE = 0, + ULP_SR_SYM_PKT_TYPE_1_L2 = 0, + ULP_SR_SYM_RECYCLE_CNT_IGNORE = 0, + ULP_SR_SYM_RECYCLE_CNT_ZERO = 0, + ULP_SR_SYM_RECYCLE_CNT_ONE = 1, + ULP_SR_SYM_RECYCLE_CNT_TWO = 2, + ULP_SR_SYM_RECYCLE_CNT_THREE = 3, + ULP_SR_SYM_AGG_ERROR_IGNORE = 0, + ULP_SR_SYM_AGG_ERROR_NO = 0, + ULP_SR_SYM_AGG_ERROR_YES = 1, + ULP_SR_SYM_RESERVED_IGNORE = 0, + ULP_SR_SYM_HREC_NEXT_IGNORE = 0, + ULP_SR_SYM_HREC_NEXT_NO = 0, + ULP_SR_SYM_HREC_NEXT_YES = 1, + ULP_SR_SYM_TL2_HDR_VALID_IGNORE = 0, + ULP_SR_SYM_TL2_HDR_VALID_NO = 0, + ULP_SR_SYM_TL2_HDR_VALID_YES = 1, + ULP_SR_SYM_TL2_HDR_TYPE_IGNORE = 0, + ULP_SR_SYM_TL2_HDR_TYPE_DIX = 0, + ULP_SR_SYM_TL2_UC_MC_BC_IGNORE = 0, + ULP_SR_SYM_TL2_UC_MC_BC_UC = 0, + ULP_SR_SYM_TL2_UC_MC_BC_MC = 2, + ULP_SR_SYM_TL2_UC_MC_BC_BC = 3, + ULP_SR_SYM_TL2_VTAG_PRESENT_IGNORE = 0, + ULP_SR_SYM_TL2_VTAG_PRESENT_NO = 0, + ULP_SR_SYM_TL2_VTAG_PRESENT_YES = 1, + ULP_SR_SYM_TL2_TWO_VTAGS_IGNORE = 0, + ULP_SR_SYM_TL2_TWO_VTAGS_NO = 0, + ULP_SR_SYM_TL2_TWO_VTAGS_YES = 1, + ULP_SR_SYM_TL3_HDR_VALID_IGNORE = 0, + ULP_SR_SYM_TL3_HDR_VALID_NO = 0, + ULP_SR_SYM_TL3_HDR_VALID_YES = 1, + ULP_SR_SYM_TL3_HDR_ERROR_IGNORE = 0, + ULP_SR_SYM_TL3_HDR_ERROR_NO = 0, + ULP_SR_SYM_TL3_HDR_ERROR_YES = 1, + ULP_SR_SYM_TL3_HDR_TYPE_IGNORE = 0, + ULP_SR_SYM_TL3_HDR_TYPE_IPV4 = 0, + ULP_SR_SYM_TL3_HDR_TYPE_IPV6 = 1, + ULP_SR_SYM_TL3_HDR_ISIP_IGNORE = 0, + ULP_SR_SYM_TL3_HDR_ISIP_NO = 0, + ULP_SR_SYM_TL3_HDR_ISIP_YES = 1, + ULP_SR_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, + ULP_SR_SYM_TL3_IPV6_CMP_SRC_NO = 0, + ULP_SR_SYM_TL3_IPV6_CMP_SRC_YES = 1, + ULP_SR_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, + ULP_SR_SYM_TL3_IPV6_CMP_DST_NO = 0, + ULP_SR_SYM_TL3_IPV6_CMP_DST_YES = 1, + ULP_SR_SYM_TL4_HDR_VALID_IGNORE = 0, + ULP_SR_SYM_TL4_HDR_VALID_NO = 0, + ULP_SR_SYM_TL4_HDR_VALID_YES = 1, + ULP_SR_SYM_TL4_HDR_ERROR_IGNORE = 0, + ULP_SR_SYM_TL4_HDR_ERROR_NO = 0, + ULP_SR_SYM_TL4_HDR_ERROR_YES = 1, + ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, + ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, + ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, + ULP_SR_SYM_TL4_HDR_TYPE_IGNORE = 0, + ULP_SR_SYM_TL4_HDR_TYPE_TCP = 0, + ULP_SR_SYM_TL4_HDR_TYPE_UDP = 1, + ULP_SR_SYM_TUN_HDR_VALID_IGNORE = 0, + ULP_SR_SYM_TUN_HDR_VALID_NO = 0, + ULP_SR_SYM_TUN_HDR_VALID_YES = 1, + ULP_SR_SYM_TUN_HDR_ERROR_IGNORE = 0, + ULP_SR_SYM_TUN_HDR_ERROR_NO = 0, + ULP_SR_SYM_TUN_HDR_ERROR_YES = 1, + ULP_SR_SYM_TUN_HDR_TYPE_IGNORE = 0, + ULP_SR_SYM_TUN_HDR_TYPE_VXLAN = 0, + ULP_SR_SYM_TUN_HDR_TYPE_GENEVE = 1, + ULP_SR_SYM_TUN_HDR_TYPE_NVGRE = 2, + ULP_SR_SYM_TUN_HDR_TYPE_GRE = 3, + ULP_SR_SYM_TUN_HDR_TYPE_IPV4 = 4, + ULP_SR_SYM_TUN_HDR_TYPE_IPV6 = 5, + ULP_SR_SYM_TUN_HDR_TYPE_PPPOE = 6, + ULP_SR_SYM_TUN_HDR_TYPE_MPLS = 7, + ULP_SR_SYM_TUN_HDR_TYPE_UPAR1 = 8, + ULP_SR_SYM_TUN_HDR_TYPE_UPAR2 = 9, + ULP_SR_SYM_TUN_HDR_TYPE_NONE = 15, + ULP_SR_SYM_TUN_HDR_FLAGS_IGNORE = 0, + ULP_SR_SYM_L2_HDR_VALID_IGNORE = 0, + ULP_SR_SYM_L2_HDR_VALID_NO = 0, + ULP_SR_SYM_L2_HDR_VALID_YES = 1, + ULP_SR_SYM_L2_HDR_ERROR_IGNORE = 0, + ULP_SR_SYM_L2_HDR_ERROR_NO = 0, + ULP_SR_SYM_L2_HDR_ERROR_YES = 1, + ULP_SR_SYM_L2_HDR_TYPE_IGNORE = 0, + ULP_SR_SYM_L2_HDR_TYPE_DIX = 0, + ULP_SR_SYM_L2_HDR_TYPE_LLC_SNAP = 1, + ULP_SR_SYM_L2_HDR_TYPE_LLC = 2, + ULP_SR_SYM_L2_UC_MC_BC_IGNORE = 0, + ULP_SR_SYM_L2_UC_MC_BC_UC = 0, + ULP_SR_SYM_L2_UC_MC_BC_MC = 2, + ULP_SR_SYM_L2_UC_MC_BC_BC = 3, + ULP_SR_SYM_L2_VTAG_PRESENT_IGNORE = 0, + ULP_SR_SYM_L2_VTAG_PRESENT_NO = 0, + ULP_SR_SYM_L2_VTAG_PRESENT_YES = 1, + ULP_SR_SYM_L2_TWO_VTAGS_IGNORE = 0, + ULP_SR_SYM_L2_TWO_VTAGS_NO = 0, + ULP_SR_SYM_L2_TWO_VTAGS_YES = 1, + ULP_SR_SYM_L3_HDR_VALID_IGNORE = 0, + ULP_SR_SYM_L3_HDR_VALID_NO = 0, + ULP_SR_SYM_L3_HDR_VALID_YES = 1, + ULP_SR_SYM_L3_HDR_ERROR_IGNORE = 0, + ULP_SR_SYM_L3_HDR_ERROR_NO = 0, + ULP_SR_SYM_L3_HDR_ERROR_YES = 1, + ULP_SR_SYM_L3_HDR_TYPE_IGNORE = 0, + ULP_SR_SYM_L3_HDR_TYPE_IPV4 = 0, + ULP_SR_SYM_L3_HDR_TYPE_IPV6 = 1, + ULP_SR_SYM_L3_HDR_TYPE_ARP = 2, + ULP_SR_SYM_L3_HDR_TYPE_PTP = 3, + ULP_SR_SYM_L3_HDR_TYPE_EAPOL = 4, + ULP_SR_SYM_L3_HDR_TYPE_ROCE = 5, + ULP_SR_SYM_L3_HDR_TYPE_FCOE = 6, + ULP_SR_SYM_L3_HDR_TYPE_UPAR1 = 7, + ULP_SR_SYM_L3_HDR_TYPE_UPAR2 = 8, + ULP_SR_SYM_L3_HDR_ISIP_IGNORE = 0, + ULP_SR_SYM_L3_HDR_ISIP_NO = 0, + ULP_SR_SYM_L3_HDR_ISIP_YES = 1, + ULP_SR_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, + ULP_SR_SYM_L3_IPV6_CMP_SRC_NO = 0, + ULP_SR_SYM_L3_IPV6_CMP_SRC_YES = 1, + ULP_SR_SYM_L3_IPV6_CMP_DST_IGNORE = 0, + ULP_SR_SYM_L3_IPV6_CMP_DST_NO = 0, + ULP_SR_SYM_L3_IPV6_CMP_DST_YES = 1, + ULP_SR_SYM_L4_HDR_VALID_IGNORE = 0, + ULP_SR_SYM_L4_HDR_VALID_NO = 0, + ULP_SR_SYM_L4_HDR_VALID_YES = 1, + ULP_SR_SYM_L4_HDR_ERROR_IGNORE = 0, + ULP_SR_SYM_L4_HDR_ERROR_NO = 0, + ULP_SR_SYM_L4_HDR_ERROR_YES = 1, + ULP_SR_SYM_L4_HDR_TYPE_IGNORE = 0, + ULP_SR_SYM_L4_HDR_TYPE_TCP = 0, + ULP_SR_SYM_L4_HDR_TYPE_UDP = 1, + ULP_SR_SYM_L4_HDR_TYPE_ICMP = 2, + ULP_SR_SYM_L4_HDR_TYPE_UPAR1 = 3, + ULP_SR_SYM_L4_HDR_TYPE_UPAR2 = 4, + ULP_SR_SYM_L4_HDR_TYPE_BTH_V1 = 5, + ULP_SR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, + ULP_SR_SYM_L4_HDR_IS_UDP_TCP_NO = 0, + ULP_SR_SYM_L4_HDR_IS_UDP_TCP_YES = 1, + ULP_SR_SYM_POP_VLAN_NO = 0, + ULP_SR_SYM_POP_VLAN_YES = 1, + ULP_SR_SYM_DECAP_FUNC_NONE = 0, + ULP_SR_SYM_DECAP_FUNC_THRU_TL2 = 3, + ULP_SR_SYM_DECAP_FUNC_THRU_TL3 = 8, + ULP_SR_SYM_DECAP_FUNC_THRU_TL4 = 9, + ULP_SR_SYM_DECAP_FUNC_THRU_TUN = 10, + ULP_SR_SYM_DECAP_FUNC_THRU_L2 = 11, + ULP_SR_SYM_DECAP_FUNC_THRU_L3 = 12, + ULP_SR_SYM_DECAP_FUNC_THRU_L4 = 13, + ULP_SR_SYM_ECV_VALID_NO = 0, + ULP_SR_SYM_ECV_VALID_YES = 1, + ULP_SR_SYM_ECV_CUSTOM_EN_NO = 0, + ULP_SR_SYM_ECV_CUSTOM_EN_YES = 1, + ULP_SR_SYM_ECV_L2_EN_NO = 0, + ULP_SR_SYM_ECV_L2_EN_YES = 1, + ULP_SR_SYM_ECV_VTAG_TYPE_NOP = 0, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, + ULP_SR_SYM_ECV_L3_TYPE_NONE = 0, + ULP_SR_SYM_ECV_L3_TYPE_IPV4 = 4, + ULP_SR_SYM_ECV_L3_TYPE_IPV6 = 5, + ULP_SR_SYM_ECV_L3_TYPE_MPLS_8847 = 6, + ULP_SR_SYM_ECV_L3_TYPE_MPLS_8848 = 7, + ULP_SR_SYM_ECV_L4_TYPE_NONE = 0, + ULP_SR_SYM_ECV_L4_TYPE_UDP = 4, + ULP_SR_SYM_ECV_L4_TYPE_UDP_CSUM = 5, + ULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, + ULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, + ULP_SR_SYM_ECV_TUN_TYPE_NONE = 0, + ULP_SR_SYM_ECV_TUN_TYPE_GENERIC = 1, + ULP_SR_SYM_ECV_TUN_TYPE_VXLAN = 2, + ULP_SR_SYM_ECV_TUN_TYPE_NGE = 3, + ULP_SR_SYM_ECV_TUN_TYPE_NVGRE = 4, + ULP_SR_SYM_ECV_TUN_TYPE_GRE = 5, + ULP_SR_SYM_EEM_ACT_REC_INT = 0, + ULP_SR_SYM_EEM_EXT_FLOW_CNTR = 1, + ULP_SR_SYM_UC_ACT_REC = 0, + ULP_SR_SYM_MC_ACT_REC = 1, + ULP_SR_SYM_ACT_REC_DROP_YES = 1, + ULP_SR_SYM_ACT_REC_DROP_NO = 0, + ULP_SR_SYM_ACT_REC_POP_VLAN_YES = 1, + ULP_SR_SYM_ACT_REC_POP_VLAN_NO = 0, + ULP_SR_SYM_ACT_REC_METER_EN_YES = 1, + ULP_SR_SYM_ACT_REC_METER_EN_NO = 0, + ULP_SR_SYM_LOOPBACK_PORT = 16, + ULP_SR_SYM_LOOPBACK_PARIF = 15, + ULP_SR_SYM_EXT_EM_MAX_KEY_SIZE = 448, + ULP_SR_SYM_MATCH_TYPE_EM = 0, + ULP_SR_SYM_MATCH_TYPE_WM = 1, + ULP_SR_SYM_IP_PROTO_ICMP = 1, + ULP_SR_SYM_IP_PROTO_IGMP = 2, + ULP_SR_SYM_IP_PROTO_IP_IN_IP = 4, + ULP_SR_SYM_IP_PROTO_TCP = 6, + ULP_SR_SYM_IP_PROTO_UDP = 17, + ULP_SR_SYM_VF_FUNC_PARIF = 15, + ULP_SR_SYM_NO = 0, + ULP_SR_SYM_YES = 1, + ULP_SR_SYM_RECYCLE_DST = 0x800 }; enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_00fc = 0x00fc, - BNXT_ULP_CLASS_HID_0046 = 0x0046, - BNXT_ULP_CLASS_HID_0056 = 0x0056, - BNXT_ULP_CLASS_HID_00b8 = 0x00b8, - BNXT_ULP_CLASS_HID_0041 = 0x0041, - BNXT_ULP_CLASS_HID_00ab = 0x00ab, - BNXT_ULP_CLASS_HID_0053 = 0x0053, - BNXT_ULP_CLASS_HID_00a5 = 0x00a5, - BNXT_ULP_CLASS_HID_0069 = 0x0069, - BNXT_ULP_CLASS_HID_009d = 0x009d, + BNXT_ULP_CLASS_HID_07e0 = 0x07e0, + BNXT_ULP_CLASS_HID_01dc = 0x01dc, + BNXT_ULP_CLASS_HID_006e = 0x006e, + BNXT_ULP_CLASS_HID_025a = 0x025a, + BNXT_ULP_CLASS_HID_0146 = 0x0146, + BNXT_ULP_CLASS_HID_0332 = 0x0332, + BNXT_ULP_CLASS_HID_01c4 = 0x01c4, + BNXT_ULP_CLASS_HID_078a = 0x078a, + BNXT_ULP_CLASS_HID_02ed = 0x02ed, + BNXT_ULP_CLASS_HID_04d9 = 0x04d9, + BNXT_ULP_CLASS_HID_036b = 0x036b, + BNXT_ULP_CLASS_HID_0131 = 0x0131, + BNXT_ULP_CLASS_HID_0217 = 0x0217, + BNXT_ULP_CLASS_HID_03c3 = 0x03c3, + BNXT_ULP_CLASS_HID_0295 = 0x0295, + BNXT_ULP_CLASS_HID_0441 = 0x0441, + BNXT_ULP_CLASS_HID_0095 = 0x0095, + BNXT_ULP_CLASS_HID_0241 = 0x0241, + BNXT_ULP_CLASS_HID_04ed = 0x04ed, + BNXT_ULP_CLASS_HID_06d9 = 0x06d9, + BNXT_ULP_CLASS_HID_07bf = 0x07bf, + BNXT_ULP_CLASS_HID_016b = 0x016b, + BNXT_ULP_CLASS_HID_0417 = 0x0417, + BNXT_ULP_CLASS_HID_05c3 = 0x05c3, + BNXT_ULP_CLASS_HID_0187 = 0x0187, + BNXT_ULP_CLASS_HID_0373 = 0x0373, + BNXT_ULP_CLASS_HID_0205 = 0x0205, + BNXT_ULP_CLASS_HID_03f1 = 0x03f1, + BNXT_ULP_CLASS_HID_00a1 = 0x00a1, + BNXT_ULP_CLASS_HID_029d = 0x029d, + BNXT_ULP_CLASS_HID_012f = 0x012f, + BNXT_ULP_CLASS_HID_031b = 0x031b, + BNXT_ULP_CLASS_HID_072f = 0x072f, + BNXT_ULP_CLASS_HID_011b = 0x011b, + BNXT_ULP_CLASS_HID_0387 = 0x0387, + BNXT_ULP_CLASS_HID_0573 = 0x0573, + BNXT_ULP_CLASS_HID_0649 = 0x0649, BNXT_ULP_CLASS_HID_0005 = 0x0005, - BNXT_ULP_CLASS_HID_006f = 0x006f, - BNXT_ULP_CLASS_HID_00af = 0x00af, - BNXT_ULP_CLASS_HID_00d3 = 0x00d3, - BNXT_ULP_CLASS_HID_005b = 0x005b, - BNXT_ULP_CLASS_HID_00ad = 0x00ad, - BNXT_ULP_CLASS_HID_0091 = 0x0091, - BNXT_ULP_CLASS_HID_00fb = 0x00fb, - BNXT_ULP_CLASS_HID_0063 = 0x0063, - BNXT_ULP_CLASS_HID_0097 = 0x0097, - BNXT_ULP_CLASS_HID_00cc = 0x00cc, - BNXT_ULP_CLASS_HID_00f0 = 0x00f0, - BNXT_ULP_CLASS_HID_00c0 = 0x00c0, - BNXT_ULP_CLASS_HID_002a = 0x002a, - BNXT_ULP_CLASS_HID_00c7 = 0x00c7, - BNXT_ULP_CLASS_HID_0029 = 0x0029, - BNXT_ULP_CLASS_HID_00d1 = 0x00d1, - BNXT_ULP_CLASS_HID_003b = 0x003b, + BNXT_ULP_CLASS_HID_02a1 = 0x02a1, + BNXT_ULP_CLASS_HID_049d = 0x049d, + BNXT_ULP_CLASS_HID_01ea = 0x01ea, + BNXT_ULP_CLASS_HID_03de = 0x03de, + BNXT_ULP_CLASS_HID_0672 = 0x0672, + BNXT_ULP_CLASS_HID_0026 = 0x0026, + BNXT_ULP_CLASS_HID_0746 = 0x0746, + BNXT_ULP_CLASS_HID_010a = 0x010a, + BNXT_ULP_CLASS_HID_03ae = 0x03ae, + BNXT_ULP_CLASS_HID_0592 = 0x0592, + BNXT_ULP_CLASS_HID_07d0 = 0x07d0, + BNXT_ULP_CLASS_HID_01ec = 0x01ec, + BNXT_ULP_CLASS_HID_005e = 0x005e, + BNXT_ULP_CLASS_HID_026a = 0x026a, + BNXT_ULP_CLASS_HID_0176 = 0x0176, + BNXT_ULP_CLASS_HID_0302 = 0x0302, + BNXT_ULP_CLASS_HID_01f4 = 0x01f4, + BNXT_ULP_CLASS_HID_07ba = 0x07ba, + BNXT_ULP_CLASS_HID_06a7 = 0x06a7, + BNXT_ULP_CLASS_HID_006b = 0x006b, + BNXT_ULP_CLASS_HID_0725 = 0x0725, + BNXT_ULP_CLASS_HID_00e9 = 0x00e9, + BNXT_ULP_CLASS_HID_05d9 = 0x05d9, + BNXT_ULP_CLASS_HID_078d = 0x078d, + BNXT_ULP_CLASS_HID_065f = 0x065f, + BNXT_ULP_CLASS_HID_0003 = 0x0003, + BNXT_ULP_CLASS_HID_045f = 0x045f, + BNXT_ULP_CLASS_HID_0603 = 0x0603, + BNXT_ULP_CLASS_HID_00a7 = 0x00a7, + BNXT_ULP_CLASS_HID_026b = 0x026b, + BNXT_ULP_CLASS_HID_0371 = 0x0371, + BNXT_ULP_CLASS_HID_0525 = 0x0525, + BNXT_ULP_CLASS_HID_07d9 = 0x07d9, + BNXT_ULP_CLASS_HID_018d = 0x018d, + BNXT_ULP_CLASS_HID_0177 = 0x0177, + BNXT_ULP_CLASS_HID_033b = 0x033b, + BNXT_ULP_CLASS_HID_05df = 0x05df, + BNXT_ULP_CLASS_HID_0783 = 0x0783, + BNXT_ULP_CLASS_HID_0069 = 0x0069, + BNXT_ULP_CLASS_HID_025d = 0x025d, BNXT_ULP_CLASS_HID_00ef = 0x00ef, - BNXT_ULP_CLASS_HID_0013 = 0x0013, - BNXT_ULP_CLASS_HID_009b = 0x009b, - BNXT_ULP_CLASS_HID_00ed = 0x00ed, - BNXT_ULP_CLASS_HID_002d = 0x002d, - BNXT_ULP_CLASS_HID_0051 = 0x0051, + BNXT_ULP_CLASS_HID_06a5 = 0x06a5, + BNXT_ULP_CLASS_HID_02f1 = 0x02f1, + BNXT_ULP_CLASS_HID_04a5 = 0x04a5, + BNXT_ULP_CLASS_HID_0377 = 0x0377, + BNXT_ULP_CLASS_HID_053b = 0x053b, + BNXT_ULP_CLASS_HID_0601 = 0x0601, + BNXT_ULP_CLASS_HID_03df = 0x03df, + BNXT_ULP_CLASS_HID_0269 = 0x0269, + BNXT_ULP_CLASS_HID_045d = 0x045d, + BNXT_ULP_CLASS_HID_02dd = 0x02dd, + BNXT_ULP_CLASS_HID_04e9 = 0x04e9, + BNXT_ULP_CLASS_HID_035b = 0x035b, + BNXT_ULP_CLASS_HID_0101 = 0x0101, + BNXT_ULP_CLASS_HID_0227 = 0x0227, + BNXT_ULP_CLASS_HID_03f3 = 0x03f3, + BNXT_ULP_CLASS_HID_02a5 = 0x02a5, + BNXT_ULP_CLASS_HID_0471 = 0x0471, + BNXT_ULP_CLASS_HID_00a5 = 0x00a5, + BNXT_ULP_CLASS_HID_0271 = 0x0271, + BNXT_ULP_CLASS_HID_04dd = 0x04dd, + BNXT_ULP_CLASS_HID_06e9 = 0x06e9, + BNXT_ULP_CLASS_HID_078f = 0x078f, + BNXT_ULP_CLASS_HID_015b = 0x015b, + BNXT_ULP_CLASS_HID_0427 = 0x0427, + BNXT_ULP_CLASS_HID_05f3 = 0x05f3, + BNXT_ULP_CLASS_HID_01b7 = 0x01b7, + BNXT_ULP_CLASS_HID_0343 = 0x0343, + BNXT_ULP_CLASS_HID_0235 = 0x0235, + BNXT_ULP_CLASS_HID_03c1 = 0x03c1, + BNXT_ULP_CLASS_HID_0091 = 0x0091, + BNXT_ULP_CLASS_HID_02ad = 0x02ad, + BNXT_ULP_CLASS_HID_011f = 0x011f, + BNXT_ULP_CLASS_HID_032b = 0x032b, + BNXT_ULP_CLASS_HID_071f = 0x071f, + BNXT_ULP_CLASS_HID_012b = 0x012b, + BNXT_ULP_CLASS_HID_03b7 = 0x03b7, + BNXT_ULP_CLASS_HID_0543 = 0x0543, + BNXT_ULP_CLASS_HID_0679 = 0x0679, + BNXT_ULP_CLASS_HID_0035 = 0x0035, + BNXT_ULP_CLASS_HID_0291 = 0x0291, + BNXT_ULP_CLASS_HID_04ad = 0x04ad, + BNXT_ULP_CLASS_HID_01da = 0x01da, + BNXT_ULP_CLASS_HID_03ee = 0x03ee, + BNXT_ULP_CLASS_HID_0642 = 0x0642, + BNXT_ULP_CLASS_HID_0016 = 0x0016, + BNXT_ULP_CLASS_HID_0776 = 0x0776, + BNXT_ULP_CLASS_HID_013a = 0x013a, + BNXT_ULP_CLASS_HID_039e = 0x039e, + BNXT_ULP_CLASS_HID_05a2 = 0x05a2, + BNXT_ULP_CLASS_HID_0697 = 0x0697, + BNXT_ULP_CLASS_HID_005b = 0x005b, + BNXT_ULP_CLASS_HID_0715 = 0x0715, BNXT_ULP_CLASS_HID_00d9 = 0x00d9, - BNXT_ULP_CLASS_HID_0023 = 0x0023, - BNXT_ULP_CLASS_HID_0017 = 0x0017, - BNXT_ULP_CLASS_HID_0079 = 0x0079, - BNXT_ULP_CLASS_HID_00e1 = 0x00e1, - BNXT_ULP_CLASS_HID_0015 = 0x0015 + BNXT_ULP_CLASS_HID_05e9 = 0x05e9, + BNXT_ULP_CLASS_HID_07bd = 0x07bd, + BNXT_ULP_CLASS_HID_066f = 0x066f, + BNXT_ULP_CLASS_HID_0033 = 0x0033, + BNXT_ULP_CLASS_HID_046f = 0x046f, + BNXT_ULP_CLASS_HID_0633 = 0x0633, + BNXT_ULP_CLASS_HID_0097 = 0x0097, + BNXT_ULP_CLASS_HID_025b = 0x025b, + BNXT_ULP_CLASS_HID_0341 = 0x0341, + BNXT_ULP_CLASS_HID_0515 = 0x0515, + BNXT_ULP_CLASS_HID_07e9 = 0x07e9, + BNXT_ULP_CLASS_HID_01bd = 0x01bd, + BNXT_ULP_CLASS_HID_0147 = 0x0147, + BNXT_ULP_CLASS_HID_030b = 0x030b, + BNXT_ULP_CLASS_HID_05ef = 0x05ef, + BNXT_ULP_CLASS_HID_07b3 = 0x07b3, + BNXT_ULP_CLASS_HID_0059 = 0x0059, + BNXT_ULP_CLASS_HID_026d = 0x026d, + BNXT_ULP_CLASS_HID_00df = 0x00df, + BNXT_ULP_CLASS_HID_0695 = 0x0695, + BNXT_ULP_CLASS_HID_02c1 = 0x02c1, + BNXT_ULP_CLASS_HID_0495 = 0x0495, + BNXT_ULP_CLASS_HID_0347 = 0x0347, + BNXT_ULP_CLASS_HID_050b = 0x050b, + BNXT_ULP_CLASS_HID_0631 = 0x0631, + BNXT_ULP_CLASS_HID_03ef = 0x03ef, + BNXT_ULP_CLASS_HID_0259 = 0x0259, + BNXT_ULP_CLASS_HID_046d = 0x046d }; enum bnxt_ulp_act_hid { @@ -1013,11 +1139,11 @@ enum bnxt_ulp_act_hid { }; enum bnxt_ulp_df_tpl { - BNXT_ULP_DF_TPL_PORT_TO_VS = 3, - BNXT_ULP_DF_TPL_VS_TO_PORT = 4, - BNXT_ULP_DF_TPL_VFREP_TO_VF = 5, - BNXT_ULP_DF_TPL_VF_TO_VFREP = 6, - BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7 + BNXT_ULP_DF_TPL_PORT_TO_VS = 2, + BNXT_ULP_DF_TPL_VS_TO_PORT = 3, + BNXT_ULP_DF_TPL_VFREP_TO_VF = 4, + BNXT_ULP_DF_TPL_VF_TO_VFREP = 5, + BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 6 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h index 0e7278a38f..0e197e362e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h @@ -3,108 +3,108 @@ * All rights reserved. */ -/* date: Wed Nov 18 12:19:40 2020 */ +/* date: Tue Dec 1 10:17:11 2020 */ #ifndef ULP_HDR_FIELD_ENUMS_H_ #define ULP_HDR_FIELD_ENUMS_H_ enum bnxt_ulp_glb_hf { - BNXT_ULP_GLB_HF_WM, - BNXT_ULP_GLB_HF_SVIF_INDEX, - BNXT_ULP_GLB_HF_O_ETH_DMAC, - BNXT_ULP_GLB_HF_I_ETH_DMAC, - BNXT_ULP_GLB_HF_O_ETH_SMAC, - BNXT_ULP_GLB_HF_I_ETH_SMAC, - BNXT_ULP_GLB_HF_O_ETH_TYPE, - BNXT_ULP_GLB_HF_I_ETH_TYPE, - BNXT_ULP_GLB_HF_O_IPV4_VER, - BNXT_ULP_GLB_HF_I_IPV4_VER, - BNXT_ULP_GLB_HF_O_IPV4_TOS, - BNXT_ULP_GLB_HF_I_IPV4_TOS, - BNXT_ULP_GLB_HF_O_IPV4_LEN, - BNXT_ULP_GLB_HF_I_IPV4_LEN, - BNXT_ULP_GLB_HF_O_IPV4_FRAG_ID, - BNXT_ULP_GLB_HF_I_IPV4_FRAG_ID, - BNXT_ULP_GLB_HF_O_IPV4_FRAG_OFF, - BNXT_ULP_GLB_HF_I_IPV4_FRAG_OFF, - BNXT_ULP_GLB_HF_O_IPV4_TTL, - BNXT_ULP_GLB_HF_I_IPV4_TTL, - BNXT_ULP_GLB_HF_O_IPV4_PROTO_ID, - BNXT_ULP_GLB_HF_I_IPV4_PROTO_ID, - BNXT_ULP_GLB_HF_O_IPV4_CSUM, - BNXT_ULP_GLB_HF_I_IPV4_CSUM, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR, - BNXT_ULP_GLB_HF_I_IPV4_SRC_ADDR, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR, - BNXT_ULP_GLB_HF_I_IPV4_DST_ADDR, - BNXT_ULP_GLB_HF_O_IPV6_VER, - BNXT_ULP_GLB_HF_I_IPV6_VER, - BNXT_ULP_GLB_HF_O_IPV6_TC, - BNXT_ULP_GLB_HF_I_IPV6_TC, - BNXT_ULP_GLB_HF_O_IPV6_FLOW_LABEL, - BNXT_ULP_GLB_HF_I_IPV6_FLOW_LABEL, - BNXT_ULP_GLB_HF_O_IPV6_PAYLOAD_LEN, - BNXT_ULP_GLB_HF_I_IPV6_PAYLOAD_LEN, - BNXT_ULP_GLB_HF_O_IPV6_PROTO_ID, - BNXT_ULP_GLB_HF_I_IPV6_PROTO_ID, - BNXT_ULP_GLB_HF_O_IPV6_TTL, - BNXT_ULP_GLB_HF_I_IPV6_TTL, - BNXT_ULP_GLB_HF_O_IPV6_SRC_ADDR, - BNXT_ULP_GLB_HF_I_IPV6_SRC_ADDR, - BNXT_ULP_GLB_HF_O_IPV6_DST_ADDR, - BNXT_ULP_GLB_HF_I_IPV6_DST_ADDR, - BNXT_ULP_GLB_HF_O_L3_PROTO_ID, - BNXT_ULP_GLB_HF_I_L3_PROTO_ID, - BNXT_ULP_GLB_HF_O_L3_SRC_ADDR, - BNXT_ULP_GLB_HF_I_L3_SRC_ADDR, - BNXT_ULP_GLB_HF_O_L3_DST_ADDR, - BNXT_ULP_GLB_HF_I_L3_DST_ADDR, - BNXT_ULP_GLB_HF_O_L4_SRC_PORT, - BNXT_ULP_GLB_HF_I_L4_SRC_PORT, - BNXT_ULP_GLB_HF_O_L4_DST_PORT, - BNXT_ULP_GLB_HF_I_L4_DST_PORT, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT, - BNXT_ULP_GLB_HF_I_TCP_SRC_PORT, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT, - BNXT_ULP_GLB_HF_I_TCP_DST_PORT, - BNXT_ULP_GLB_HF_O_TCP_SENT_SEQ, - BNXT_ULP_GLB_HF_I_TCP_SENT_SEQ, - BNXT_ULP_GLB_HF_O_TCP_RECV_ACK, - BNXT_ULP_GLB_HF_I_TCP_RECV_ACK, - BNXT_ULP_GLB_HF_O_TCP_DATA_OFF, - BNXT_ULP_GLB_HF_I_TCP_DATA_OFF, - BNXT_ULP_GLB_HF_O_TCP_TCP_FLAGS, - BNXT_ULP_GLB_HF_I_TCP_TCP_FLAGS, - BNXT_ULP_GLB_HF_O_TCP_RX_WIN, - BNXT_ULP_GLB_HF_I_TCP_RX_WIN, - BNXT_ULP_GLB_HF_O_TCP_CSUM, - BNXT_ULP_GLB_HF_I_TCP_CSUM, - BNXT_ULP_GLB_HF_O_TCP_URP, - BNXT_ULP_GLB_HF_I_TCP_URP, - BNXT_ULP_GLB_HF_O_UDP_SRC_PORT, - BNXT_ULP_GLB_HF_I_UDP_SRC_PORT, - BNXT_ULP_GLB_HF_O_UDP_DST_PORT, - BNXT_ULP_GLB_HF_I_UDP_DST_PORT, - BNXT_ULP_GLB_HF_O_UDP_LENGTH, - BNXT_ULP_GLB_HF_I_UDP_LENGTH, - BNXT_ULP_GLB_HF_O_UDP_CSUM, - BNXT_ULP_GLB_HF_I_UDP_CSUM, - BNXT_ULP_GLB_HF_OO_VLAN_CFI_PRI, - BNXT_ULP_GLB_HF_OI_VLAN_CFI_PRI, - BNXT_ULP_GLB_HF_IO_VLAN_CFI_PRI, - BNXT_ULP_GLB_HF_II_VLAN_CFI_PRI, - BNXT_ULP_GLB_HF_OO_VLAN_VID, - BNXT_ULP_GLB_HF_OI_VLAN_VID, - BNXT_ULP_GLB_HF_IO_VLAN_VID, - BNXT_ULP_GLB_HF_II_VLAN_VID, - BNXT_ULP_GLB_HF_OO_VLAN_TYPE, - BNXT_ULP_GLB_HF_OI_VLAN_TYPE, - BNXT_ULP_GLB_HF_IO_VLAN_TYPE, - BNXT_ULP_GLB_HF_II_VLAN_TYPE, - BNXT_ULP_GLB_HF_T_VXLAN_FLAGS, - BNXT_ULP_GLB_HF_T_VXLAN_RSVD0, - BNXT_ULP_GLB_HF_T_VXLAN_VNI, - BNXT_ULP_GLB_HF_T_VXLAN_RSVD1 + BNXT_ULP_GLB_HF_ID_WM, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE, + BNXT_ULP_GLB_HF_ID_I_ETH_TYPE, + BNXT_ULP_GLB_HF_ID_O_IPV4_VER, + BNXT_ULP_GLB_HF_ID_I_IPV4_VER, + BNXT_ULP_GLB_HF_ID_O_IPV4_TOS, + BNXT_ULP_GLB_HF_ID_I_IPV4_TOS, + BNXT_ULP_GLB_HF_ID_O_IPV4_LEN, + BNXT_ULP_GLB_HF_ID_I_IPV4_LEN, + BNXT_ULP_GLB_HF_ID_O_IPV4_FRAG_ID, + BNXT_ULP_GLB_HF_ID_I_IPV4_FRAG_ID, + BNXT_ULP_GLB_HF_ID_O_IPV4_FRAG_OFF, + BNXT_ULP_GLB_HF_ID_I_IPV4_FRAG_OFF, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL, + BNXT_ULP_GLB_HF_ID_I_IPV4_TTL, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID, + BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID, + BNXT_ULP_GLB_HF_ID_O_IPV4_CSUM, + BNXT_ULP_GLB_HF_ID_I_IPV4_CSUM, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR, + BNXT_ULP_GLB_HF_ID_O_IPV6_VER, + BNXT_ULP_GLB_HF_ID_I_IPV6_VER, + BNXT_ULP_GLB_HF_ID_O_IPV6_TC, + BNXT_ULP_GLB_HF_ID_I_IPV6_TC, + BNXT_ULP_GLB_HF_ID_O_IPV6_FLOW_LABEL, + BNXT_ULP_GLB_HF_ID_I_IPV6_FLOW_LABEL, + BNXT_ULP_GLB_HF_ID_O_IPV6_PAYLOAD_LEN, + BNXT_ULP_GLB_HF_ID_I_IPV6_PAYLOAD_LEN, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID, + BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL, + BNXT_ULP_GLB_HF_ID_I_IPV6_TTL, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR, + BNXT_ULP_GLB_HF_ID_O_L3_PROTO_ID, + BNXT_ULP_GLB_HF_ID_I_L3_PROTO_ID, + BNXT_ULP_GLB_HF_ID_O_L3_SRC_ADDR, + BNXT_ULP_GLB_HF_ID_I_L3_SRC_ADDR, + BNXT_ULP_GLB_HF_ID_O_L3_DST_ADDR, + BNXT_ULP_GLB_HF_ID_I_L3_DST_ADDR, + BNXT_ULP_GLB_HF_ID_O_L4_SRC_PORT, + BNXT_ULP_GLB_HF_ID_I_L4_SRC_PORT, + BNXT_ULP_GLB_HF_ID_O_L4_DST_PORT, + BNXT_ULP_GLB_HF_ID_I_L4_DST_PORT, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT, + BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT, + BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT, + BNXT_ULP_GLB_HF_ID_O_TCP_SENT_SEQ, + BNXT_ULP_GLB_HF_ID_I_TCP_SENT_SEQ, + BNXT_ULP_GLB_HF_ID_O_TCP_RECV_ACK, + BNXT_ULP_GLB_HF_ID_I_TCP_RECV_ACK, + BNXT_ULP_GLB_HF_ID_O_TCP_DATA_OFF, + BNXT_ULP_GLB_HF_ID_I_TCP_DATA_OFF, + BNXT_ULP_GLB_HF_ID_O_TCP_TCP_FLAGS, + BNXT_ULP_GLB_HF_ID_I_TCP_TCP_FLAGS, + BNXT_ULP_GLB_HF_ID_O_TCP_RX_WIN, + BNXT_ULP_GLB_HF_ID_I_TCP_RX_WIN, + BNXT_ULP_GLB_HF_ID_O_TCP_CSUM, + BNXT_ULP_GLB_HF_ID_I_TCP_CSUM, + BNXT_ULP_GLB_HF_ID_O_TCP_URP, + BNXT_ULP_GLB_HF_ID_I_TCP_URP, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT, + BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT, + BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT, + BNXT_ULP_GLB_HF_ID_O_UDP_LENGTH, + BNXT_ULP_GLB_HF_ID_I_UDP_LENGTH, + BNXT_ULP_GLB_HF_ID_O_UDP_CSUM, + BNXT_ULP_GLB_HF_ID_I_UDP_CSUM, + BNXT_ULP_GLB_HF_ID_OO_VLAN_CFI_PRI, + BNXT_ULP_GLB_HF_ID_OI_VLAN_CFI_PRI, + BNXT_ULP_GLB_HF_ID_IO_VLAN_CFI_PRI, + BNXT_ULP_GLB_HF_ID_II_VLAN_CFI_PRI, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID, + BNXT_ULP_GLB_HF_ID_II_VLAN_VID, + BNXT_ULP_GLB_HF_ID_OO_VLAN_TYPE, + BNXT_ULP_GLB_HF_ID_OI_VLAN_TYPE, + BNXT_ULP_GLB_HF_ID_IO_VLAN_TYPE, + BNXT_ULP_GLB_HF_ID_II_VLAN_TYPE, + BNXT_ULP_GLB_HF_ID_T_VXLAN_FLAGS, + BNXT_ULP_GLB_HF_ID_T_VXLAN_RSVD0, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI, + BNXT_ULP_GLB_HF_ID_T_VXLAN_RSVD1 }; enum bnxt_ulp_hf1_0_bitmask { @@ -113,25 +113,23 @@ enum bnxt_ulp_hf1_0_bitmask { BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_URP = 0x0000010000000000 + BNXT_ULP_HF1_0_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM = 0x0000080000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_URP = 0x0000040000000000 }; enum bnxt_ulp_hf1_1_bitmask { @@ -143,81 +141,169 @@ enum bnxt_ulp_hf1_1_bitmask { BNXT_ULP_HF1_1_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_URP = 0x0000002000000000 + BNXT_ULP_HF1_1_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_URP = 0x0000008000000000 }; -enum bnxt_ulp_hf2_0_bitmask { - BNXT_ULP_HF2_0_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_0_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF2_0_BITMASK_O_TCP_URP = 0x0000010000000000 +enum bnxt_ulp_hf1_2_bitmask { + BNXT_ULP_HF1_2_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_2_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_URP = 0x0000010000000000 }; -enum bnxt_ulp_hf2_1_bitmask { - BNXT_ULP_HF2_1_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_1_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_URP = 0x0000002000000000 +enum bnxt_ulp_hf1_3_bitmask { + BNXT_ULP_HF1_3_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_3_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF1_3_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF1_3_BITMASK_O_UDP_CSUM = 0x0000800000000000 +}; + +enum bnxt_ulp_hf1_4_bitmask { + BNXT_ULP_HF1_4_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_4_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_URP = 0x0000002000000000 +}; + +enum bnxt_ulp_hf1_5_bitmask { + BNXT_ULP_HF1_5_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_5_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM = 0x0000100000000000 +}; + +enum bnxt_ulp_hf1_6_bitmask { + BNXT_ULP_HF1_6_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_6_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_6_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF1_6_BITMASK_O_UDP_CSUM = 0x0000200000000000 +}; + +enum bnxt_ulp_hf1_7_bitmask { + BNXT_ULP_HF1_7_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_7_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM = 0x0000040000000000 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c index 87d6347196..7610950507 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Nov 23 17:33:02 2020 */ +/* date: Tue Dec 1 17:07:12 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -32,6 +32,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, .cond_nums = 1 }, @@ -53,6 +54,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 1, .cond_nums = 1 }, @@ -74,6 +76,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 2, .cond_nums = 0 }, @@ -95,6 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 2, .cond_nums = 0 }, @@ -112,12 +116,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { struct bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[] = { { - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, { - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN } }; @@ -126,559 +130,580 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[] = { { .description = "count", .field_bit_size = 64, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, stingray, table: int_vtag_encap_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} }, { .description = "vtag_de", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, { .description = "spare", .field_bit_size = 80, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, stingray, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_DECAP_FUNC_THRU_TUN}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_SR_SYM_DECAP_FUNC_NONE} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, stingray, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_DECAP_FUNC_THRU_TUN}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_SR_SYM_DECAP_FUNC_NONE} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c index c836e2f8ed..a0cab178ec 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Nov 23 17:33:02 2020 */ +/* date: Wed Dec 2 12:05:11 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = { /* class_tid: 1, stingray, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, + .num_tbls = 9, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -26,17 +26,17 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = { [2] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 6, - .start_tbl_idx = 6, + .start_tbl_idx = 9, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 2, + .cond_start_idx = 4, .cond_nums = 0 } }, - /* class_tid: 3, stingray, ingress */ + /* class_tid: 3, stingray, egress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 12, + .num_tbls = 8, + .start_tbl_idx = 15, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 4, @@ -45,18 +45,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = { /* class_tid: 4, stingray, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 8, - .start_tbl_idx = 18, + .num_tbls = 7, + .start_tbl_idx = 23, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 4, + .cond_start_idx = 10, .cond_nums = 0 } }, /* class_tid: 5, stingray, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 7, - .start_tbl_idx = 26, + .start_tbl_idx = 30, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 10, @@ -65,18 +65,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = { /* class_tid: 6, stingray, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 7, - .start_tbl_idx = 33, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, - .cond_nums = 0 } - }, - /* class_tid: 7, stingray, egress */ - [7] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, .num_tbls = 1, - .start_tbl_idx = 40, + .start_tbl_idx = 37, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 10, @@ -85,13 +75,35 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = { }; struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { + { /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 0, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 0, + .ident_nums = 1 + }, { /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -99,7 +111,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 0, + .key_start_idx = 1, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -107,7 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 0, + .ident_start_idx = 1, .ident_nums = 1 }, { /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ @@ -117,27 +129,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 13, + .key_start_idx = 14, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .ident_start_idx = 1, + .ident_start_idx = 2, .ident_nums = 3 }, + { /* class_tid: 1, stingray, table: branch.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 1, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH + }, { /* class_tid: 1, stingray, table: profile_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 0, - .cond_nums = 1 }, + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, @@ -145,7 +170,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 16, + .key_start_idx = 17, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -153,7 +178,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_bit_size = 38, .result_num_fields = 8, .encap_num_fields = 0, - .ident_start_idx = 4, + .ident_start_idx = 5, .ident_nums = 1 }, { /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ @@ -163,13 +188,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, - .cond_nums = 1 }, + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 59, + .key_start_idx = 60, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, @@ -178,194 +204,71 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .result_num_fields = 5, .encap_num_fields = 0 }, - { /* class_tid: 1, stingray, table: eem.ext_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 62, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 10, - .result_start_idx = 26, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 - }, { /* class_tid: 1, stingray, table: em.int_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 2, - .cond_nums = 0 }, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 72, + .key_start_idx = 63, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, - .result_start_idx = 35, + .result_start_idx = 26, .result_bit_size = 64, .result_num_fields = 9, .encap_num_fields = 0 }, - { /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 82, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 44, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 1 - }, - { /* class_tid: 2, stingray, table: profile_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 95, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .ident_start_idx = 6, - .ident_nums = 3 - }, - { /* class_tid: 2, stingray, table: profile_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 2, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 98, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 57, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 1 - }, - { /* class_tid: 2, stingray, table: profile_tcam_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 3, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 141, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .result_start_idx = 65, - .result_bit_size = 66, - .result_num_fields = 5, - .encap_num_fields = 0 - }, - { /* class_tid: 2, stingray, table: eem.ext_0 */ + { /* class_tid: 1, stingray, table: eem.ext_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, - .cond_nums = 0 }, + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 3, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 144, + .key_start_idx = 73, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, - .result_start_idx = 70, + .result_start_idx = 35, .result_bit_size = 64, .result_num_fields = 9, .encap_num_fields = 0 }, - { /* class_tid: 2, stingray, table: em.int_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, + { /* class_tid: 1, stingray, table: last */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 154, - .blob_key_bit_size = 176, - .key_bit_size = 176, - .key_num_fields = 10, - .result_start_idx = 79, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH }, - { /* class_tid: 3, stingray, table: int_full_act_record.0 */ + { /* class_tid: 2, stingray, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -374,16 +277,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 88, + .result_start_idx = 44, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ + { /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -396,44 +300,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 164, + .key_start_idx = 83, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 114, + .result_start_idx = 70, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 10, + .ident_start_idx = 6, .ident_nums = 1 }, - { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 177, + .key_start_idx = 96, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 127, + .result_start_idx = 83, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 }, - { /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */ + { /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -441,16 +347,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 131, + .result_start_idx = 87, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */ + { /* class_tid: 2, stingray, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -458,16 +365,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 132, + .result_start_idx = 88, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */ + { /* class_tid: 2, stingray, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -475,18 +383,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 133, + .result_start_idx = 89, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 4, stingray, table: int_full_act_record.0 */ + { /* class_tid: 3, stingray, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -495,16 +404,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 134, + .result_start_idx = 90, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ + { /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 4, .cond_nums = 1 }, @@ -516,42 +426,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 178, + .key_start_idx = 97, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 160, + .result_start_idx = 116, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 11, + .ident_start_idx = 7, .ident_nums = 0 }, - { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 5, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 191, + .key_start_idx = 110, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 11, + .ident_start_idx = 7, .ident_nums = 1 }, - { /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */ + { /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 6, .cond_nums = 2 }, @@ -562,44 +474,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 192, + .key_start_idx = 111, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 173, + .result_start_idx = 129, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 12, + .ident_start_idx = 8, .ident_nums = 1 }, - { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 8, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 205, + .key_start_idx = 124, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 186, + .result_start_idx = 142, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 }, - { /* class_tid: 4, stingray, table: parif_def_lkup_arec_ptr.0 */ + { /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -607,16 +521,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 190, + .result_start_idx = 146, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 4, stingray, table: parif_def_arec_ptr.0 */ + { /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -624,16 +539,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 191, + .result_start_idx = 147, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 4, stingray, table: parif_def_err_arec_ptr.0 */ + { /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -641,18 +557,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 192, + .result_start_idx = 148, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 5, stingray, table: int_vtag_encap_record.egr0 */ + { /* class_tid: 4, stingray, table: int_vtag_encap_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -661,18 +578,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 193, + .result_start_idx = 149, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12 }, - { /* class_tid: 5, stingray, table: int_full_act_record.egr0 */ + { /* class_tid: 4, stingray, table: int_full_act_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -681,16 +599,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 205, + .result_start_idx = 161, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */ + { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -701,48 +620,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 206, + .key_start_idx = 125, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 231, + .result_start_idx = 187, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 0 }, - { /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ + { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 219, + .key_start_idx = 138, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 244, + .result_start_idx = 200, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 0 }, - { /* class_tid: 5, stingray, table: int_full_act_record.ing0 */ + { /* class_tid: 4, stingray, table: int_full_act_record.ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -751,16 +672,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 248, + .result_start_idx = 204, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -772,22 +694,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 220, + .key_start_idx = 139, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 274, + .result_start_idx = 230, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 0 }, - { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -799,22 +722,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 233, + .key_start_idx = 152, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 287, + .result_start_idx = 243, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 0 }, - { /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */ + { /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -825,44 +749,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 246, + .key_start_idx = 165, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 300, + .result_start_idx = 256, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 1 }, - { /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */ + { /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 259, + .key_start_idx = 178, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 313, + .result_start_idx = 269, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 }, - { /* class_tid: 6, stingray, table: parif_def_lkup_arec_ptr.egr */ + { /* class_tid: 5, stingray, table: parif_def_lkup_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -870,16 +796,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 317, + .result_start_idx = 273, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 6, stingray, table: parif_def_arec_ptr.egr */ + { /* class_tid: 5, stingray, table: parif_def_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -887,16 +814,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 318, + .result_start_idx = 274, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 6, stingray, table: parif_def_err_arec_ptr.egr */ + { /* class_tid: 5, stingray, table: parif_def_err_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -904,18 +832,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 319, + .result_start_idx = 275, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 6, stingray, table: int_full_act_record.ing */ + { /* class_tid: 5, stingray, table: int_full_act_record.ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -924,16 +853,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, - .result_start_idx = 320, + .result_start_idx = 276, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */ + { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -945,24 +875,25 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 260, + .key_start_idx = 179, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 346, + .result_start_idx = 302, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 14, + .ident_start_idx = 10, .ident_nums = 0 }, - { /* class_tid: 7, stingray, table: int_full_act_record.0 */ + { /* class_tid: 6, stingray, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -971,7 +902,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 359, + .result_start_idx = 315, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -980,246 +911,279 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { struct bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[] = { { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT } }; struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { + /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ @@ -1227,52 +1191,54 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, /* class_tid: 1, stingray, table: profile_tcam.0 */ @@ -1280,580 +1246,684 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_L4_HDR_TYPE_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_SR_SYM_L4_HDR_TYPE_UDP} } }, { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_L4_HDR_VALID_YES} } }, { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_L3_HDR_TYPE_IPV4}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_SR_SYM_L3_HDR_TYPE_IPV6} } }, { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_L3_HDR_VALID_YES} } }, { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_L2_HDR_VALID_YES} } }, { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "reserved", .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ @@ -1861,3165 +1931,2188 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 1, stingray, table: eem.ext_0 */ + /* class_tid: 1, stingray, table: em.int_0 */ { .field_info_mask = { .description = "spare", - .field_bit_size = 275, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", - .field_bit_size = 275, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "o_l4.dport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} } }, { .field_info_mask = { .description = "o_l4.sport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} } }, { .field_info_mask = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_IP_PROTO_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_SR_SYM_IP_PROTO_UDP} } }, { .field_info_mask = { .description = "o_ipv4.dst", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "o_ipv4.dst", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_ipv4.src", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "o_ipv4.src", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, stingray, table: em.int_0 */ + /* class_tid: 1, stingray, table: eem.ext_0 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "spare", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, stingray, table: profile_tcam_cache.rd */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, stingray, table: profile_tcam.0 */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, stingray, table: profile_tcam_cache.wr */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, stingray, table: eem.ext_0 */ - { - .field_info_mask = { - .description = "spare", - .field_bit_size = 275, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { .description = "spare", .field_bit_size = 275, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, stingray, table: em.int_0 */ - { - .field_info_mask = { - .description = "spare", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_bit_size = 275, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "o_l4.dport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} } }, { .field_info_mask = { .description = "o_l4.sport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} } }, { .field_info_mask = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_IP_PROTO_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_SR_SYM_IP_PROTO_UDP} } }, { .field_info_mask = { .description = "o_ipv4.dst", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "o_ipv4.dst", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_ipv4.src", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "o_ipv4.src", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } } }; @@ -5029,2372 +4122,2300 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 1, stingray, table: profile_tcam.0 */ { .description = "wc_key_id", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { .description = "wc_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (0x007d >> 8) & 0xff, - 0x007d & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (125 >> 8) & 0xff, + 125 & 0xff} }, { .description = "em_key_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "em_search_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "profile_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} }, { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "wm_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_sig_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, stingray, table: eem.ext_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_cntr", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (0x00ad >> 8) & 0xff, - 0x00ad & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, /* class_tid: 1, stingray, table: em.int_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { .description = "l1_cacheable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - /* class_tid: 2, stingray, table: profile_tcam.0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (0x0079 >> 8) & 0xff, - 0x0079 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - /* class_tid: 2, stingray, table: profile_tcam_cache.wr */ - { - .description = "rid", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "profile_tcam_index", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "wm_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "flow_sig_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 2, stingray, table: eem.ext_0 */ + /* class_tid: 1, stingray, table: eem.ext_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_EEM_EXT_FLOW_CNTR} }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (0x00ad >> 8) & 0xff, - 0x00ad & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, stingray, table: em.int_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_cntr", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { .description = "key_size", .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (173 >> 8) & 0xff, + 173 & 0xff} }, { .description = "reserved", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { .description = "l1_cacheable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 3, stingray, table: int_full_act_record.0 */ + /* class_tid: 2, stingray, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */ + /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */ + /* class_tid: 2, stingray, table: parif_def_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */ + /* class_tid: 2, stingray, table: parif_def_err_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, stingray, table: int_full_act_record.0 */ + /* class_tid: 3, stingray, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: parif_def_lkup_arec_ptr.0 */ + /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, stingray, table: parif_def_arec_ptr.0 */ + /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, stingray, table: parif_def_err_arec_ptr.0 */ + /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 5, stingray, table: int_vtag_encap_record.egr0 */ + /* class_tid: 4, stingray, table: int_vtag_encap_record.egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x81, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0x81, + 0x00} }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} }, { .description = "vtag_de", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 80, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: int_full_act_record.egr0 */ + /* class_tid: 4, stingray, table: int_full_act_record.egr0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_SR_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_SR_SYM_LOOPBACK_PORT & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: int_full_act_record.ing0 */ + /* class_tid: 4, stingray, table: int_full_act_record.ing0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, stingray, table: parif_def_lkup_arec_ptr.egr */ + /* class_tid: 5, stingray, table: parif_def_lkup_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 6, stingray, table: parif_def_arec_ptr.egr */ + /* class_tid: 5, stingray, table: parif_def_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 6, stingray, table: parif_def_err_arec_ptr.egr */ + /* class_tid: 5, stingray, table: parif_def_err_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 6, stingray, table: int_full_act_record.ing */ + /* class_tid: 5, stingray, table: int_full_act_record.ing */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 7, stingray, table: int_full_act_record.0 */ + /* class_tid: 6, stingray, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_SR_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_SR_SYM_LOOPBACK_PORT & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }; struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { + /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -7406,12 +6427,6 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { }, /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ { - .description = "flow_sig_id", - .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 8, - .ident_bit_pos = 58 - }, - { .description = "profile_tcam_index", .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .ident_bit_size = 10, @@ -7423,44 +6438,13 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 42 }, - /* class_tid: 1, stingray, table: profile_tcam.0 */ - { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 28 - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - /* class_tid: 2, stingray, table: profile_tcam_cache.rd */ - { - .description = "profile_tcam_index", - .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .ident_bit_size = 10, - .ident_bit_pos = 32 - }, { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, .ident_bit_size = 8, .ident_bit_pos = 58 }, - { - .description = "em_profile_id", - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 42 - }, - /* class_tid: 2, stingray, table: profile_tcam.0 */ + /* class_tid: 1, stingray, table: profile_tcam.0 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -7469,7 +6453,7 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -7478,14 +6462,14 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */ { .description = "l2_cntxt_id", .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 42 }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -7494,7 +6478,7 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */ + /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 30a71def95..ff003b2ebd 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Nov 23 17:33:02 2020 */ +/* date: Tue Dec 1 10:17:11 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -209,11 +209,11 @@ uint32_t ulp_glb_template_tbl[] = { struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = { [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .act_bitmask = BNXT_ULP_ACTION_BIT_SHARED_SAMPLE + .act_bitmask = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .act_bitmask = BNXT_ULP_ACTION_BIT_SHARED_SAMPLE + .act_bitmask = BNXT_ULP_ACT_BIT_SHARED_SAMPLE } }; @@ -312,78 +312,176 @@ uint8_t ulp_glb_field_tbl[] = { [2050] = 2, [2052] = 3, [2054] = 4, - [2056] = 5, - [2058] = 6, - [2060] = 7, - [2062] = 8, - [2064] = 9, - [2066] = 10, - [2068] = 11, - [2070] = 12, - [2072] = 13, - [2074] = 14, - [2102] = 15, - [2104] = 16, - [2106] = 17, - [2108] = 18, - [2110] = 19, - [2112] = 20, - [2114] = 21, - [2116] = 22, - [2118] = 23, + [2076] = 5, + [2078] = 6, + [2080] = 7, + [2082] = 8, + [2084] = 9, + [2086] = 10, + [2088] = 11, + [2090] = 12, + [2102] = 13, + [2104] = 14, + [2106] = 15, + [2108] = 16, + [2110] = 17, + [2112] = 18, + [2114] = 19, + [2116] = 20, + [2118] = 21, [2176] = 0, [2177] = 1, [2178] = 2, [2180] = 3, [2182] = 4, - [2184] = 8, - [2186] = 9, - [2188] = 10, - [2190] = 11, - [2192] = 12, - [2194] = 13, - [2196] = 14, - [2198] = 15, - [2200] = 16, - [2202] = 17, - [2230] = 18, - [2232] = 19, - [2234] = 20, - [2236] = 21, - [2238] = 22, - [2240] = 23, - [2242] = 24, - [2244] = 25, - [2246] = 26, + [2204] = 8, + [2206] = 9, + [2208] = 10, + [2210] = 11, + [2212] = 12, + [2214] = 13, + [2216] = 14, + [2218] = 15, + [2230] = 16, + [2232] = 17, + [2234] = 18, + [2236] = 19, + [2238] = 20, + [2240] = 21, + [2242] = 22, + [2244] = 23, + [2246] = 24, [2256] = 5, [2260] = 6, [2264] = 7, - [4352] = 0, - [4353] = 1, - [4354] = 2, - [4356] = 3, - [4358] = 4, - [4360] = 8, - [4362] = 9, - [4364] = 10, - [4366] = 11, - [4368] = 12, - [4370] = 13, - [4372] = 14, - [4374] = 15, - [4376] = 16, - [4378] = 17, - [4406] = 18, - [4408] = 19, - [4410] = 20, - [4412] = 21, - [4414] = 22, - [4416] = 23, - [4418] = 24, - [4420] = 25, - [4422] = 26, - [4432] = 5, - [4436] = 6, - [4440] = 7 + [2304] = 0, + [2305] = 1, + [2306] = 2, + [2308] = 3, + [2310] = 4, + [2312] = 5, + [2314] = 6, + [2316] = 7, + [2318] = 8, + [2320] = 9, + [2322] = 10, + [2324] = 11, + [2326] = 12, + [2328] = 13, + [2330] = 14, + [2358] = 15, + [2360] = 16, + [2362] = 17, + [2364] = 18, + [2366] = 19, + [2368] = 20, + [2370] = 21, + [2372] = 22, + [2374] = 23, + [2432] = 0, + [2433] = 1, + [2434] = 2, + [2436] = 3, + [2438] = 4, + [2460] = 5, + [2462] = 6, + [2464] = 7, + [2466] = 8, + [2468] = 9, + [2470] = 10, + [2472] = 11, + [2474] = 12, + [2504] = 13, + [2506] = 14, + [2508] = 15, + [2510] = 16, + [2560] = 0, + [2561] = 1, + [2562] = 2, + [2564] = 3, + [2566] = 4, + [2568] = 8, + [2570] = 9, + [2572] = 10, + [2574] = 11, + [2576] = 12, + [2578] = 13, + [2580] = 14, + [2582] = 15, + [2584] = 16, + [2586] = 17, + [2614] = 18, + [2616] = 19, + [2618] = 20, + [2620] = 21, + [2622] = 22, + [2624] = 23, + [2626] = 24, + [2628] = 25, + [2630] = 26, + [2640] = 5, + [2644] = 6, + [2648] = 7, + [2688] = 0, + [2689] = 1, + [2690] = 2, + [2692] = 3, + [2694] = 4, + [2716] = 8, + [2718] = 9, + [2720] = 10, + [2722] = 11, + [2724] = 12, + [2726] = 13, + [2728] = 14, + [2730] = 15, + [2760] = 16, + [2762] = 17, + [2764] = 18, + [2766] = 19, + [2768] = 5, + [2772] = 6, + [2776] = 7, + [2816] = 0, + [2817] = 1, + [2818] = 2, + [2820] = 3, + [2822] = 4, + [2824] = 5, + [2826] = 6, + [2828] = 7, + [2830] = 8, + [2832] = 9, + [2834] = 10, + [2836] = 11, + [2838] = 12, + [2840] = 13, + [2842] = 14, + [2888] = 15, + [2890] = 16, + [2892] = 17, + [2894] = 18, + [2944] = 0, + [2945] = 1, + [2946] = 2, + [2948] = 3, + [2950] = 4, + [2952] = 8, + [2954] = 9, + [2956] = 10, + [2958] = 11, + [2960] = 12, + [2962] = 13, + [2964] = 14, + [2966] = 15, + [2968] = 16, + [2970] = 17, + [3016] = 18, + [3018] = 19, + [3020] = 20, + [3022] = 21, + [3024] = 5, + [3028] = 6, + [3032] = 7 }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 69cc7f33f9..5b098cff37 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Nov 18 12:19:40 2020 */ +/* date: Tue Dec 1 17:07:12 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -32,6 +32,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, .cond_nums = 1 }, @@ -53,6 +54,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 1, .cond_nums = 1 }, @@ -74,6 +76,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 2, .cond_nums = 0 }, @@ -95,6 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 2, .cond_nums = 0 }, @@ -112,12 +116,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { { - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, { - .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN } }; @@ -126,557 +130,578 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "count", .field_bit_size = 64, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} }, { .description = "vtag_de", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, { .description = "spare", .field_bit_size = 80, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_NONE} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_NONE} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT, - .field_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 0bce60d4e3..52eab7a715 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Nov 23 17:33:02 2020 */ +/* date: Wed Dec 2 12:05:11 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 9, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -26,17 +26,17 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 6, + .start_tbl_idx = 9, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 2, + .cond_start_idx = 4, .cond_nums = 0 } }, - /* class_tid: 3, wh_plus, ingress */ + /* class_tid: 3, wh_plus, egress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 12, + .num_tbls = 8, + .start_tbl_idx = 15, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 4, @@ -45,18 +45,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 8, - .start_tbl_idx = 18, + .num_tbls = 7, + .start_tbl_idx = 23, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 4, + .cond_start_idx = 10, .cond_nums = 0 } }, /* class_tid: 5, wh_plus, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 7, - .start_tbl_idx = 26, + .start_tbl_idx = 30, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 10, @@ -65,18 +65,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 6, wh_plus, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 7, - .start_tbl_idx = 33, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, - .cond_nums = 0 } - }, - /* class_tid: 7, wh_plus, egress */ - [7] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 1, - .start_tbl_idx = 40, + .start_tbl_idx = 37, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 10, @@ -85,13 +75,35 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { + { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 0, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 0, + .ident_nums = 1 + }, { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -99,7 +111,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 0, + .key_start_idx = 1, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -107,7 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 0, + .ident_start_idx = 1, .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ @@ -117,27 +129,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 13, + .key_start_idx = 14, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .ident_start_idx = 1, + .ident_start_idx = 2, .ident_nums = 3 }, + { /* class_tid: 1, wh_plus, table: branch.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 1, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH + }, { /* class_tid: 1, wh_plus, table: profile_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 0, - .cond_nums = 1 }, + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, @@ -145,7 +170,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 16, + .key_start_idx = 17, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -153,7 +178,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 38, .result_num_fields = 8, .encap_num_fields = 0, - .ident_start_idx = 4, + .ident_start_idx = 5, .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ @@ -163,13 +188,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, - .cond_nums = 1 }, + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 59, + .key_start_idx = 60, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, @@ -178,194 +204,71 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 5, .encap_num_fields = 0 }, - { /* class_tid: 1, wh_plus, table: eem.ext_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 62, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 10, - .result_start_idx = 26, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 - }, { /* class_tid: 1, wh_plus, table: em.int_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 2, - .cond_nums = 0 }, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 72, + .key_start_idx = 63, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, - .result_start_idx = 35, + .result_start_idx = 26, .result_bit_size = 64, .result_num_fields = 9, .encap_num_fields = 0 }, - { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 82, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 44, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 1 - }, - { /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 95, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .ident_start_idx = 6, - .ident_nums = 3 - }, - { /* class_tid: 2, wh_plus, table: profile_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 2, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 98, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 57, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 1 - }, - { /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 3, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 141, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .result_start_idx = 65, - .result_bit_size = 66, - .result_num_fields = 5, - .encap_num_fields = 0 - }, - { /* class_tid: 2, wh_plus, table: eem.ext_0 */ + { /* class_tid: 1, wh_plus, table: eem.ext_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, - .cond_nums = 0 }, + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 3, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 144, + .key_start_idx = 73, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, - .result_start_idx = 70, + .result_start_idx = 35, .result_bit_size = 64, .result_num_fields = 9, .encap_num_fields = 0 }, - { /* class_tid: 2, wh_plus, table: em.int_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, + { /* class_tid: 1, wh_plus, table: last */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 154, - .blob_key_bit_size = 176, - .key_bit_size = 176, - .key_num_fields = 10, - .result_start_idx = 79, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH }, - { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ + { /* class_tid: 2, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -374,16 +277,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 88, + .result_start_idx = 44, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -396,44 +300,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 164, + .key_start_idx = 83, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 114, + .result_start_idx = 70, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 10, + .ident_start_idx = 6, .ident_nums = 1 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 177, + .key_start_idx = 96, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 127, + .result_start_idx = 83, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 }, - { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + { /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -441,16 +347,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 131, + .result_start_idx = 87, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ + { /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -458,16 +365,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 132, + .result_start_idx = 88, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ + { /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -475,18 +383,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 133, + .result_start_idx = 89, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.0 */ + { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, @@ -495,16 +404,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 134, + .result_start_idx = 90, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 4, .cond_nums = 1 }, @@ -516,42 +426,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 178, + .key_start_idx = 97, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 160, + .result_start_idx = 116, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 11, + .ident_start_idx = 7, .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 5, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 191, + .key_start_idx = 110, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 11, + .ident_start_idx = 7, .ident_nums = 1 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 6, .cond_nums = 2 }, @@ -562,44 +474,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 192, + .key_start_idx = 111, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 173, + .result_start_idx = 129, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 12, + .ident_start_idx = 8, .ident_nums = 1 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 8, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 205, + .key_start_idx = 124, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 186, + .result_start_idx = 142, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -607,16 +521,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 190, + .result_start_idx = 146, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -624,16 +539,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 191, + .result_start_idx = 147, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -641,18 +557,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 192, + .result_start_idx = 148, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */ + { /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -661,18 +578,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 193, + .result_start_idx = 149, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12 }, - { /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */ + { /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -681,16 +599,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 205, + .result_start_idx = 161, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -701,48 +620,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 206, + .key_start_idx = 125, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 231, + .result_start_idx = 187, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 0 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 219, + .key_start_idx = 138, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 244, + .result_start_idx = 200, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 0 }, - { /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */ + { /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -751,16 +672,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 248, + .result_start_idx = 204, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -772,22 +694,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 220, + .key_start_idx = 139, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 274, + .result_start_idx = 230, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 0 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -799,22 +722,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 233, + .key_start_idx = 152, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 287, + .result_start_idx = 243, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 0 }, - { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -825,44 +749,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 246, + .key_start_idx = 165, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 300, + .result_start_idx = 256, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 13, + .ident_start_idx = 9, .ident_nums = 1 }, - { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 259, + .key_start_idx = 178, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 313, + .result_start_idx = 269, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 }, - { /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */ + { /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -870,16 +796,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 317, + .result_start_idx = 273, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */ + { /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -887,16 +814,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 318, + .result_start_idx = 274, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */ + { /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -904,18 +832,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 319, + .result_start_idx = 275, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, - { /* class_tid: 6, wh_plus, table: int_full_act_record.ing */ + { /* class_tid: 5, wh_plus, table: int_full_act_record.ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -924,16 +853,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, - .result_start_idx = 320, + .result_start_idx = 276, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -945,24 +875,25 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 260, + .key_start_idx = 179, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 346, + .result_start_idx = 302, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 14, + .ident_start_idx = 10, .ident_nums = 0 }, - { /* class_tid: 7, wh_plus, table: int_full_act_record.0 */ + { /* class_tid: 6, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { + .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, @@ -971,7 +902,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 359, + .result_start_idx = 315, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -980,246 +911,279 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET, + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT }, { - .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET, + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT } }; struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ @@ -1227,52 +1191,54 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, /* class_tid: 1, wh_plus, table: profile_tcam.0 */ @@ -1280,580 +1246,684 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L4_HDR_VALID_YES} } }, { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV4}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV6} } }, { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L2_HDR_VALID_YES} } }, { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "reserved", .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ @@ -1861,3165 +1931,2188 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 1, wh_plus, table: eem.ext_0 */ + /* class_tid: 1, wh_plus, table: em.int_0 */ { .field_info_mask = { .description = "spare", - .field_bit_size = 275, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", - .field_bit_size = 275, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "o_l4.dport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} } }, { .field_info_mask = { .description = "o_l4.sport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} } }, { .field_info_mask = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_IP_PROTO_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_IP_PROTO_UDP} } }, { .field_info_mask = { .description = "o_ipv4.dst", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "o_ipv4.dst", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_ipv4.src", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "o_ipv4.src", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: em.int_0 */ + /* class_tid: 1, wh_plus, table: eem.ext_0 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "spare", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, wh_plus, table: profile_tcam.0 */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, wh_plus, table: eem.ext_0 */ - { - .field_info_mask = { - .description = "spare", - .field_bit_size = 275, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { .description = "spare", .field_bit_size = 275, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } - }, - /* class_tid: 2, wh_plus, table: em.int_0 */ - { - .field_info_mask = { - .description = "spare", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_bit_size = 275, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "o_l4.dport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} } }, { .field_info_mask = { .description = "o_l4.sport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} } }, { .field_info_mask = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_IP_PROTO_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_IP_PROTO_UDP} } }, { .field_info_mask = { .description = "o_ipv4.dst", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "o_ipv4.dst", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD, - .field_operand = { - (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_ipv4.src", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "o_ipv4.src", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } } }; @@ -5029,2380 +4122,2308 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 1, wh_plus, table: profile_tcam.0 */ { .description = "wc_key_id", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { .description = "wc_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (0x007d >> 8) & 0xff, - 0x007d & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (125 >> 8) & 0xff, + 125 & 0xff} }, { .description = "em_key_id", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "em_search_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "profile_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} }, { .description = "em_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "wm_profile_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_sig_id", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 1, wh_plus, table: eem.ext_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_cntr", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (0x00ad >> 8) & 0xff, - 0x00ad & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, /* class_tid: 1, wh_plus, table: em.int_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { .description = "l1_cacheable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - /* class_tid: 2, wh_plus, table: profile_tcam.0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (0x0079 >> 8) & 0xff, - 0x0079 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ - { - .description = "rid", - .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "profile_tcam_index", - .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "wm_profile_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "flow_sig_id", - .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 2, wh_plus, table: eem.ext_0 */ + /* class_tid: 1, wh_plus, table: eem.ext_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_EEM_ACT_REC_INT} }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "key_size", - .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (0x00ad >> 8) & 0xff, - 0x00ad & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "reserved", - .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - /* class_tid: 2, wh_plus, table: em.int_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .description = "ext_flow_cntr", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { .description = "key_size", .field_bit_size = 9, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (173 >> 8) & 0xff, + 173 & 0xff} }, { .description = "reserved", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { .description = "l1_cacheable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ + /* class_tid: 2, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ + /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ + /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: int_full_act_record.0 */ + /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */ + /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x81, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0x81, + 0x00} }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} }, { .description = "vtag_de", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 80, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */ + /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_WP_SYM_LOOPBACK_PORT & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */ + /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", .field_bit_size = 7, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { .description = "rid", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */ + /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */ + /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */ + /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 6, wh_plus, table: int_full_act_record.ing */ + /* class_tid: 5, wh_plus, table: int_full_act_record.ing */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE, - .field_operand = { + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "parif", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 7, wh_plus, table: int_full_act_record.0 */ + /* class_tid: 6, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT, - .field_operand = { - (BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_WP_SYM_LOOPBACK_PORT & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }; struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -7414,12 +6435,6 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ { - .description = "flow_sig_id", - .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 8, - .ident_bit_pos = 58 - }, - { .description = "profile_tcam_index", .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .ident_bit_size = 10, @@ -7431,44 +6446,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 42 }, - /* class_tid: 1, wh_plus, table: profile_tcam.0 */ - { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 28 - }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ - { - .description = "profile_tcam_index", - .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .ident_bit_size = 10, - .ident_bit_pos = 32 - }, { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, .ident_bit_size = 8, .ident_bit_pos = 58 }, - { - .description = "em_profile_id", - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 42 - }, - /* class_tid: 2, wh_plus, table: profile_tcam.0 */ + /* class_tid: 1, wh_plus, table: profile_tcam.0 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -7477,7 +6461,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -7486,14 +6470,14 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ { .description = "l2_cntxt_id", .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 42 }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -7502,7 +6486,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index b06b1b12d3..16802fb89a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -160,6 +160,7 @@ struct bnxt_ulp_mapper_cond_list_info { enum bnxt_ulp_cond_list_opc cond_list_opcode; uint32_t cond_start_idx; uint32_t cond_nums; + uint32_t cond_goto; }; struct bnxt_ulp_template_device_tbls { @@ -252,12 +253,15 @@ struct bnxt_ulp_mapper_tbl_info { }; struct bnxt_ulp_mapper_field_info { - uint8_t description[64]; - enum bnxt_ulp_field_opc field_opcode; - uint16_t field_bit_size; - uint8_t field_operand[16]; - uint8_t field_operand_true[16]; - uint8_t field_operand_false[16]; + uint8_t description[64]; + uint16_t field_bit_size; + enum bnxt_ulp_field_cond_src field_cond_src; + uint8_t field_cond_opr[16]; + enum bnxt_ulp_field_src field_src1; + uint8_t field_opr1[16]; + enum bnxt_ulp_field_src field_src2; + uint8_t field_opr2[16]; + }; struct bnxt_ulp_mapper_key_info { diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c index e8d2861880..dd3d8703fb 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.c +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c @@ -25,7 +25,7 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params, /* Reset the JUMP action bit in the action bitmap as we don't * offload this action. */ - ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP); + ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP); ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1); diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h index ad70ae6164..763138218b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.h +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h @@ -18,7 +18,7 @@ #define BNXT_OUTER_TUN_SIGNATURE(l3_tun, params) \ ((l3_tun) && \ ULP_BITMAP_ISSET((params)->act_bitmap.bits, \ - BNXT_ULP_ACTION_BIT_JUMP)) + BNXT_ULP_ACT_BIT_JUMP)) #define BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params) \ ((l3_tun) && (l3_tun_decap) && \ !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \ From patchwork Sun May 30 08:59:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93582 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7B016A0524; Sun, 30 May 2021 11:05:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 92BB2411D5; Sun, 30 May 2021 11:01:30 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 45A6140DFB for ; Sun, 30 May 2021 11:01:29 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id D84AD7DC0; Sun, 30 May 2021 02:01:27 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com D84AD7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365288; bh=kjEAOYnNfzsSZ43Frn2QO3UHLTqQ7WvdZWvXKid/z9k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lEWjTZYfjSIPxlpjtPeWJFlF0AG+YLMxBIgvk2ZTJVvaPRKpPetwLOSEZaeoF18Kp qFZgyGbfidsz+/neds9p21PXxRIAlnHyf9vMSxjsk9kClR2naBY+X8IWCBaLhc+tO/ mb/37T0gakn9EJMhFXNjFIS7Nn/1blQuF6NxsN/0= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:07 +0530 Message-Id: <20210530085929.29695-37-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 36/58] net/bnxt: set shared handle for generic table X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The shared handle is set in the mapper params when generic resource are created, this shall be used by application as a handle to the shared resource like mirror handle. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 1 + drivers/net/bnxt/tf_ulp/ulp_mapper.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index ad5fde9730..73a6a4cdb5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -2403,6 +2403,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* increment the reference count */ ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent); fdb_write = 1; + parms->shared_hndl = (uint64_t)tbl_idx << 32 | ckey; break; default: BNXT_TF_DBG(ERR, "Invalid table opcode %x\n", tbl->tbl_opcode); diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index bef72696d3..b7399b8949 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -57,6 +57,7 @@ struct bnxt_ulp_mapper_parms { uint32_t parent_flow; uint8_t tun_idx; uint32_t app_priority; + uint64_t shared_hndl; }; struct bnxt_ulp_mapper_create_parms { From patchwork Sun May 30 08:59:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93583 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2BF42A0524; Sun, 30 May 2021 11:05:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 36697411D3; Sun, 30 May 2021 11:01:34 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id C6CE8411D6 for ; Sun, 30 May 2021 11:01:30 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 614587DAF; Sun, 30 May 2021 02:01:29 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 614587DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365290; bh=1SIm1JJQaF4m3Quz+aVIA51E4NaqThXqfbn/Oy4TAYg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YmxFoBPmIAtscXVFb5xbQZC6SNNctJslwawWhiH1JAseyO4yIQuT0YNwNhwabCn8E V7yYz3E6VYJJSgsyxWmIxn3JrJp21suMOJvvyI4M0qDRCTfS8UCrfmPSkVA1Lba8Oi M7AACWpK6mMbcs6+qfGCF9t3ZpeELW7DpHLdUiDk= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:08 +0530 Message-Id: <20210530085929.29695-38-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 37/58] net/bnxt: modify ULP template X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha 1. Update template to add both ipv4 and ipv6 flows. 2. The VF representor template missed generic table read. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Ajit Kumar Khaparde Reviewed-by: Shahaji Bhosle Reviewed-by: Michael Baucom --- .../net/bnxt/tf_ulp/ulp_template_db_class.c | 3224 ++++------------- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 272 +- .../net/bnxt/tf_ulp/ulp_template_db_field.h | 194 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 202 +- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 72 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 2163 +++++++++-- 6 files changed, 2946 insertions(+), 3181 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index a5133f7caf..3197ed2072 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 1 11:40:24 2020 */ +/* date: Mon Dec 7 09:51:03 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -16,1800 +16,571 @@ * maps hash id to ulp_class_match_list[] index */ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_07e0] = 1, - [BNXT_ULP_CLASS_HID_01dc] = 2, - [BNXT_ULP_CLASS_HID_006e] = 3, - [BNXT_ULP_CLASS_HID_025a] = 4, - [BNXT_ULP_CLASS_HID_0146] = 5, - [BNXT_ULP_CLASS_HID_0332] = 6, - [BNXT_ULP_CLASS_HID_01c4] = 7, - [BNXT_ULP_CLASS_HID_078a] = 8, - [BNXT_ULP_CLASS_HID_02ed] = 9, - [BNXT_ULP_CLASS_HID_04d9] = 10, - [BNXT_ULP_CLASS_HID_036b] = 11, - [BNXT_ULP_CLASS_HID_0131] = 12, - [BNXT_ULP_CLASS_HID_0217] = 13, - [BNXT_ULP_CLASS_HID_03c3] = 14, - [BNXT_ULP_CLASS_HID_0295] = 15, - [BNXT_ULP_CLASS_HID_0441] = 16, - [BNXT_ULP_CLASS_HID_0095] = 17, - [BNXT_ULP_CLASS_HID_0241] = 18, - [BNXT_ULP_CLASS_HID_04ed] = 19, - [BNXT_ULP_CLASS_HID_06d9] = 20, - [BNXT_ULP_CLASS_HID_07bf] = 21, - [BNXT_ULP_CLASS_HID_016b] = 22, - [BNXT_ULP_CLASS_HID_0417] = 23, - [BNXT_ULP_CLASS_HID_05c3] = 24, - [BNXT_ULP_CLASS_HID_0187] = 25, - [BNXT_ULP_CLASS_HID_0373] = 26, - [BNXT_ULP_CLASS_HID_0205] = 27, - [BNXT_ULP_CLASS_HID_03f1] = 28, - [BNXT_ULP_CLASS_HID_00a1] = 29, - [BNXT_ULP_CLASS_HID_029d] = 30, - [BNXT_ULP_CLASS_HID_012f] = 31, - [BNXT_ULP_CLASS_HID_031b] = 32, - [BNXT_ULP_CLASS_HID_072f] = 33, - [BNXT_ULP_CLASS_HID_011b] = 34, - [BNXT_ULP_CLASS_HID_0387] = 35, - [BNXT_ULP_CLASS_HID_0573] = 36, - [BNXT_ULP_CLASS_HID_0649] = 37, - [BNXT_ULP_CLASS_HID_0005] = 38, - [BNXT_ULP_CLASS_HID_02a1] = 39, - [BNXT_ULP_CLASS_HID_049d] = 40, - [BNXT_ULP_CLASS_HID_01ea] = 41, - [BNXT_ULP_CLASS_HID_03de] = 42, - [BNXT_ULP_CLASS_HID_0672] = 43, - [BNXT_ULP_CLASS_HID_0026] = 44, - [BNXT_ULP_CLASS_HID_0746] = 45, - [BNXT_ULP_CLASS_HID_010a] = 46, - [BNXT_ULP_CLASS_HID_03ae] = 47, - [BNXT_ULP_CLASS_HID_0592] = 48, - [BNXT_ULP_CLASS_HID_07d0] = 49, - [BNXT_ULP_CLASS_HID_01ec] = 50, - [BNXT_ULP_CLASS_HID_005e] = 51, - [BNXT_ULP_CLASS_HID_026a] = 52, - [BNXT_ULP_CLASS_HID_0176] = 53, - [BNXT_ULP_CLASS_HID_0302] = 54, - [BNXT_ULP_CLASS_HID_01f4] = 55, - [BNXT_ULP_CLASS_HID_07ba] = 56, - [BNXT_ULP_CLASS_HID_06a7] = 57, - [BNXT_ULP_CLASS_HID_006b] = 58, - [BNXT_ULP_CLASS_HID_0725] = 59, - [BNXT_ULP_CLASS_HID_00e9] = 60, - [BNXT_ULP_CLASS_HID_05d9] = 61, - [BNXT_ULP_CLASS_HID_078d] = 62, - [BNXT_ULP_CLASS_HID_065f] = 63, - [BNXT_ULP_CLASS_HID_0003] = 64, - [BNXT_ULP_CLASS_HID_045f] = 65, - [BNXT_ULP_CLASS_HID_0603] = 66, - [BNXT_ULP_CLASS_HID_00a7] = 67, - [BNXT_ULP_CLASS_HID_026b] = 68, - [BNXT_ULP_CLASS_HID_0371] = 69, - [BNXT_ULP_CLASS_HID_0525] = 70, - [BNXT_ULP_CLASS_HID_07d9] = 71, - [BNXT_ULP_CLASS_HID_018d] = 72, - [BNXT_ULP_CLASS_HID_0177] = 73, - [BNXT_ULP_CLASS_HID_033b] = 74, - [BNXT_ULP_CLASS_HID_05df] = 75, - [BNXT_ULP_CLASS_HID_0783] = 76, - [BNXT_ULP_CLASS_HID_0069] = 77, - [BNXT_ULP_CLASS_HID_025d] = 78, - [BNXT_ULP_CLASS_HID_00ef] = 79, - [BNXT_ULP_CLASS_HID_06a5] = 80, - [BNXT_ULP_CLASS_HID_02f1] = 81, - [BNXT_ULP_CLASS_HID_04a5] = 82, - [BNXT_ULP_CLASS_HID_0377] = 83, - [BNXT_ULP_CLASS_HID_053b] = 84, - [BNXT_ULP_CLASS_HID_0601] = 85, - [BNXT_ULP_CLASS_HID_03df] = 86, - [BNXT_ULP_CLASS_HID_0269] = 87, - [BNXT_ULP_CLASS_HID_045d] = 88, - [BNXT_ULP_CLASS_HID_02dd] = 89, - [BNXT_ULP_CLASS_HID_04e9] = 90, - [BNXT_ULP_CLASS_HID_035b] = 91, - [BNXT_ULP_CLASS_HID_0101] = 92, - [BNXT_ULP_CLASS_HID_0227] = 93, - [BNXT_ULP_CLASS_HID_03f3] = 94, - [BNXT_ULP_CLASS_HID_02a5] = 95, - [BNXT_ULP_CLASS_HID_0471] = 96, - [BNXT_ULP_CLASS_HID_00a5] = 97, - [BNXT_ULP_CLASS_HID_0271] = 98, - [BNXT_ULP_CLASS_HID_04dd] = 99, - [BNXT_ULP_CLASS_HID_06e9] = 100, - [BNXT_ULP_CLASS_HID_078f] = 101, - [BNXT_ULP_CLASS_HID_015b] = 102, - [BNXT_ULP_CLASS_HID_0427] = 103, - [BNXT_ULP_CLASS_HID_05f3] = 104, - [BNXT_ULP_CLASS_HID_01b7] = 105, - [BNXT_ULP_CLASS_HID_0343] = 106, - [BNXT_ULP_CLASS_HID_0235] = 107, - [BNXT_ULP_CLASS_HID_03c1] = 108, - [BNXT_ULP_CLASS_HID_0091] = 109, - [BNXT_ULP_CLASS_HID_02ad] = 110, - [BNXT_ULP_CLASS_HID_011f] = 111, - [BNXT_ULP_CLASS_HID_032b] = 112, - [BNXT_ULP_CLASS_HID_071f] = 113, - [BNXT_ULP_CLASS_HID_012b] = 114, - [BNXT_ULP_CLASS_HID_03b7] = 115, - [BNXT_ULP_CLASS_HID_0543] = 116, - [BNXT_ULP_CLASS_HID_0679] = 117, - [BNXT_ULP_CLASS_HID_0035] = 118, - [BNXT_ULP_CLASS_HID_0291] = 119, - [BNXT_ULP_CLASS_HID_04ad] = 120, - [BNXT_ULP_CLASS_HID_01da] = 121, - [BNXT_ULP_CLASS_HID_03ee] = 122, - [BNXT_ULP_CLASS_HID_0642] = 123, - [BNXT_ULP_CLASS_HID_0016] = 124, - [BNXT_ULP_CLASS_HID_0776] = 125, - [BNXT_ULP_CLASS_HID_013a] = 126, - [BNXT_ULP_CLASS_HID_039e] = 127, - [BNXT_ULP_CLASS_HID_05a2] = 128, - [BNXT_ULP_CLASS_HID_0697] = 129, - [BNXT_ULP_CLASS_HID_005b] = 130, - [BNXT_ULP_CLASS_HID_0715] = 131, - [BNXT_ULP_CLASS_HID_00d9] = 132, - [BNXT_ULP_CLASS_HID_05e9] = 133, - [BNXT_ULP_CLASS_HID_07bd] = 134, - [BNXT_ULP_CLASS_HID_066f] = 135, - [BNXT_ULP_CLASS_HID_0033] = 136, - [BNXT_ULP_CLASS_HID_046f] = 137, - [BNXT_ULP_CLASS_HID_0633] = 138, - [BNXT_ULP_CLASS_HID_0097] = 139, - [BNXT_ULP_CLASS_HID_025b] = 140, - [BNXT_ULP_CLASS_HID_0341] = 141, - [BNXT_ULP_CLASS_HID_0515] = 142, - [BNXT_ULP_CLASS_HID_07e9] = 143, - [BNXT_ULP_CLASS_HID_01bd] = 144, - [BNXT_ULP_CLASS_HID_0147] = 145, - [BNXT_ULP_CLASS_HID_030b] = 146, - [BNXT_ULP_CLASS_HID_05ef] = 147, - [BNXT_ULP_CLASS_HID_07b3] = 148, - [BNXT_ULP_CLASS_HID_0059] = 149, - [BNXT_ULP_CLASS_HID_026d] = 150, - [BNXT_ULP_CLASS_HID_00df] = 151, - [BNXT_ULP_CLASS_HID_0695] = 152, - [BNXT_ULP_CLASS_HID_02c1] = 153, - [BNXT_ULP_CLASS_HID_0495] = 154, - [BNXT_ULP_CLASS_HID_0347] = 155, - [BNXT_ULP_CLASS_HID_050b] = 156, - [BNXT_ULP_CLASS_HID_0631] = 157, - [BNXT_ULP_CLASS_HID_03ef] = 158, - [BNXT_ULP_CLASS_HID_0259] = 159, - [BNXT_ULP_CLASS_HID_046d] = 160 + [BNXT_ULP_CLASS_HID_005c] = 1, + [BNXT_ULP_CLASS_HID_0003] = 2, + [BNXT_ULP_CLASS_HID_0132] = 3, + [BNXT_ULP_CLASS_HID_00e1] = 4, + [BNXT_ULP_CLASS_HID_0044] = 5, + [BNXT_ULP_CLASS_HID_001b] = 6, + [BNXT_ULP_CLASS_HID_012a] = 7, + [BNXT_ULP_CLASS_HID_00f9] = 8, + [BNXT_ULP_CLASS_HID_018d] = 9, + [BNXT_ULP_CLASS_HID_00a7] = 10, + [BNXT_ULP_CLASS_HID_006f] = 11, + [BNXT_ULP_CLASS_HID_0181] = 12, + [BNXT_ULP_CLASS_HID_0195] = 13, + [BNXT_ULP_CLASS_HID_00bf] = 14, + [BNXT_ULP_CLASS_HID_0077] = 15, + [BNXT_ULP_CLASS_HID_0199] = 16, + [BNXT_ULP_CLASS_HID_009a] = 17, + [BNXT_ULP_CLASS_HID_0192] = 18, + [BNXT_ULP_CLASS_HID_01e2] = 19, + [BNXT_ULP_CLASS_HID_00fa] = 20, + [BNXT_ULP_CLASS_HID_0165] = 21, + [BNXT_ULP_CLASS_HID_0042] = 22, + [BNXT_ULP_CLASS_HID_00cd] = 23, + [BNXT_ULP_CLASS_HID_01aa] = 24, + [BNXT_ULP_CLASS_HID_0178] = 25, + [BNXT_ULP_CLASS_HID_0070] = 26, + [BNXT_ULP_CLASS_HID_00f3] = 27, + [BNXT_ULP_CLASS_HID_01d8] = 28, + [BNXT_ULP_CLASS_HID_005b] = 29, + [BNXT_ULP_CLASS_HID_0153] = 30, + [BNXT_ULP_CLASS_HID_01a3] = 31, + [BNXT_ULP_CLASS_HID_00bb] = 32, + [BNXT_ULP_CLASS_HID_0082] = 33, + [BNXT_ULP_CLASS_HID_018a] = 34, + [BNXT_ULP_CLASS_HID_01fa] = 35, + [BNXT_ULP_CLASS_HID_00e2] = 36, + [BNXT_ULP_CLASS_HID_017d] = 37, + [BNXT_ULP_CLASS_HID_005a] = 38, + [BNXT_ULP_CLASS_HID_00d5] = 39, + [BNXT_ULP_CLASS_HID_01b2] = 40, + [BNXT_ULP_CLASS_HID_0160] = 41, + [BNXT_ULP_CLASS_HID_0068] = 42, + [BNXT_ULP_CLASS_HID_00eb] = 43, + [BNXT_ULP_CLASS_HID_01c0] = 44, + [BNXT_ULP_CLASS_HID_0043] = 45, + [BNXT_ULP_CLASS_HID_014b] = 46, + [BNXT_ULP_CLASS_HID_01bb] = 47, + [BNXT_ULP_CLASS_HID_00a3] = 48, + [BNXT_ULP_CLASS_HID_00cb] = 49, + [BNXT_ULP_CLASS_HID_00b4] = 50, + [BNXT_ULP_CLASS_HID_0013] = 51, + [BNXT_ULP_CLASS_HID_001c] = 52, + [BNXT_ULP_CLASS_HID_017b] = 53, + [BNXT_ULP_CLASS_HID_0164] = 54, + [BNXT_ULP_CLASS_HID_00c3] = 55, + [BNXT_ULP_CLASS_HID_00cc] = 56, + [BNXT_ULP_CLASS_HID_01a5] = 57, + [BNXT_ULP_CLASS_HID_0196] = 58, + [BNXT_ULP_CLASS_HID_010d] = 59, + [BNXT_ULP_CLASS_HID_00fe] = 60, + [BNXT_ULP_CLASS_HID_0084] = 61, + [BNXT_ULP_CLASS_HID_0046] = 62, + [BNXT_ULP_CLASS_HID_01ec] = 63, + [BNXT_ULP_CLASS_HID_01ae] = 64, + [BNXT_ULP_CLASS_HID_00d3] = 65, + [BNXT_ULP_CLASS_HID_00ac] = 66, + [BNXT_ULP_CLASS_HID_000b] = 67, + [BNXT_ULP_CLASS_HID_0004] = 68, + [BNXT_ULP_CLASS_HID_0163] = 69, + [BNXT_ULP_CLASS_HID_017c] = 70, + [BNXT_ULP_CLASS_HID_00db] = 71, + [BNXT_ULP_CLASS_HID_00d4] = 72, + [BNXT_ULP_CLASS_HID_01bd] = 73, + [BNXT_ULP_CLASS_HID_018e] = 74, + [BNXT_ULP_CLASS_HID_0115] = 75, + [BNXT_ULP_CLASS_HID_00e6] = 76, + [BNXT_ULP_CLASS_HID_009c] = 77, + [BNXT_ULP_CLASS_HID_005e] = 78, + [BNXT_ULP_CLASS_HID_01f4] = 79, + [BNXT_ULP_CLASS_HID_01b6] = 80 }; /* Array for the proto matcher list */ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { [1] = { - .class_hid = BNXT_ULP_CLASS_HID_07e0, + .class_hid = BNXT_ULP_CLASS_HID_005c, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2] = { - .class_hid = BNXT_ULP_CLASS_HID_01dc, + .class_hid = BNXT_ULP_CLASS_HID_0003, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [3] = { - .class_hid = BNXT_ULP_CLASS_HID_006e, + .class_hid = BNXT_ULP_CLASS_HID_0132, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 2, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [4] = { - .class_hid = BNXT_ULP_CLASS_HID_025a, + .class_hid = BNXT_ULP_CLASS_HID_00e1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 2, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [5] = { - .class_hid = BNXT_ULP_CLASS_HID_0146, + .class_hid = BNXT_ULP_CLASS_HID_0044, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 2, + .hdr_sig_id = 1, + .flow_sig_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [6] = { - .class_hid = BNXT_ULP_CLASS_HID_0332, + .class_hid = BNXT_ULP_CLASS_HID_001b, .class_tid = 1, - .hdr_sig_id = 0, + .hdr_sig_id = 1, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [7] = { - .class_hid = BNXT_ULP_CLASS_HID_01c4, + .class_hid = BNXT_ULP_CLASS_HID_012a, .class_tid = 1, - .hdr_sig_id = 0, + .hdr_sig_id = 1, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [8] = { - .class_hid = BNXT_ULP_CLASS_HID_078a, + .class_hid = BNXT_ULP_CLASS_HID_00f9, .class_tid = 1, - .hdr_sig_id = 0, + .hdr_sig_id = 1, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [9] = { - .class_hid = BNXT_ULP_CLASS_HID_02ed, + .class_hid = BNXT_ULP_CLASS_HID_018d, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 2, .flow_sig_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [10] = { - .class_hid = BNXT_ULP_CLASS_HID_04d9, + .class_hid = BNXT_ULP_CLASS_HID_00a7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 2, + .hdr_sig_id = 2, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [11] = { - .class_hid = BNXT_ULP_CLASS_HID_036b, + .class_hid = BNXT_ULP_CLASS_HID_006f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 2, + .hdr_sig_id = 2, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [12] = { - .class_hid = BNXT_ULP_CLASS_HID_0131, + .class_hid = BNXT_ULP_CLASS_HID_0181, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 2, + .hdr_sig_id = 2, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [13] = { - .class_hid = BNXT_ULP_CLASS_HID_0217, + .class_hid = BNXT_ULP_CLASS_HID_0195, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [14] = { - .class_hid = BNXT_ULP_CLASS_HID_03c3, + .class_hid = BNXT_ULP_CLASS_HID_00bf, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 3, + .hdr_sig_id = 3, + .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [15] = { - .class_hid = BNXT_ULP_CLASS_HID_0295, + .class_hid = BNXT_ULP_CLASS_HID_0077, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 3, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [16] = { - .class_hid = BNXT_ULP_CLASS_HID_0441, + .class_hid = BNXT_ULP_CLASS_HID_0199, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 3, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [17] = { - .class_hid = BNXT_ULP_CLASS_HID_0095, + .class_hid = BNXT_ULP_CLASS_HID_009a, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 4, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [18] = { - .class_hid = BNXT_ULP_CLASS_HID_0241, + .class_hid = BNXT_ULP_CLASS_HID_0192, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 4, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [19] = { - .class_hid = BNXT_ULP_CLASS_HID_04ed, + .class_hid = BNXT_ULP_CLASS_HID_01e2, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 4, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [20] = { - .class_hid = BNXT_ULP_CLASS_HID_06d9, + .class_hid = BNXT_ULP_CLASS_HID_00fa, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 4, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [21] = { - .class_hid = BNXT_ULP_CLASS_HID_07bf, + .class_hid = BNXT_ULP_CLASS_HID_0165, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 4, .flow_sig_id = 4, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [22] = { - .class_hid = BNXT_ULP_CLASS_HID_016b, + .class_hid = BNXT_ULP_CLASS_HID_0042, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, + .hdr_sig_id = 4, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [23] = { - .class_hid = BNXT_ULP_CLASS_HID_0417, + .class_hid = BNXT_ULP_CLASS_HID_00cd, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, + .hdr_sig_id = 4, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [24] = { - .class_hid = BNXT_ULP_CLASS_HID_05c3, + .class_hid = BNXT_ULP_CLASS_HID_01aa, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, + .hdr_sig_id = 4, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [25] = { - .class_hid = BNXT_ULP_CLASS_HID_0187, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [26] = { - .class_hid = BNXT_ULP_CLASS_HID_0373, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [27] = { - .class_hid = BNXT_ULP_CLASS_HID_0205, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [28] = { - .class_hid = BNXT_ULP_CLASS_HID_03f1, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [29] = { - .class_hid = BNXT_ULP_CLASS_HID_00a1, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [30] = { - .class_hid = BNXT_ULP_CLASS_HID_029d, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [31] = { - .class_hid = BNXT_ULP_CLASS_HID_012f, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [32] = { - .class_hid = BNXT_ULP_CLASS_HID_031b, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [33] = { - .class_hid = BNXT_ULP_CLASS_HID_072f, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [34] = { - .class_hid = BNXT_ULP_CLASS_HID_011b, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [35] = { - .class_hid = BNXT_ULP_CLASS_HID_0387, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [36] = { - .class_hid = BNXT_ULP_CLASS_HID_0573, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [37] = { - .class_hid = BNXT_ULP_CLASS_HID_0649, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [38] = { - .class_hid = BNXT_ULP_CLASS_HID_0005, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [39] = { - .class_hid = BNXT_ULP_CLASS_HID_02a1, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [40] = { - .class_hid = BNXT_ULP_CLASS_HID_049d, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [41] = { - .class_hid = BNXT_ULP_CLASS_HID_01ea, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 4, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [42] = { - .class_hid = BNXT_ULP_CLASS_HID_03de, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 5, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [43] = { - .class_hid = BNXT_ULP_CLASS_HID_0672, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [44] = { - .class_hid = BNXT_ULP_CLASS_HID_0026, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [45] = { - .class_hid = BNXT_ULP_CLASS_HID_0746, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [46] = { - .class_hid = BNXT_ULP_CLASS_HID_010a, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [47] = { - .class_hid = BNXT_ULP_CLASS_HID_03ae, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [48] = { - .class_hid = BNXT_ULP_CLASS_HID_0592, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [49] = { - .class_hid = BNXT_ULP_CLASS_HID_07d0, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 6, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [50] = { - .class_hid = BNXT_ULP_CLASS_HID_01ec, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 7, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [51] = { - .class_hid = BNXT_ULP_CLASS_HID_005e, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [52] = { - .class_hid = BNXT_ULP_CLASS_HID_026a, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [53] = { - .class_hid = BNXT_ULP_CLASS_HID_0176, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [54] = { - .class_hid = BNXT_ULP_CLASS_HID_0302, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [55] = { - .class_hid = BNXT_ULP_CLASS_HID_01f4, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [56] = { - .class_hid = BNXT_ULP_CLASS_HID_07ba, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [57] = { - .class_hid = BNXT_ULP_CLASS_HID_06a7, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [58] = { - .class_hid = BNXT_ULP_CLASS_HID_006b, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [59] = { - .class_hid = BNXT_ULP_CLASS_HID_0725, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [60] = { - .class_hid = BNXT_ULP_CLASS_HID_00e9, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [61] = { - .class_hid = BNXT_ULP_CLASS_HID_05d9, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [62] = { - .class_hid = BNXT_ULP_CLASS_HID_078d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 9, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [63] = { - .class_hid = BNXT_ULP_CLASS_HID_065f, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [64] = { - .class_hid = BNXT_ULP_CLASS_HID_0003, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [65] = { - .class_hid = BNXT_ULP_CLASS_HID_045f, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [66] = { - .class_hid = BNXT_ULP_CLASS_HID_0603, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [67] = { - .class_hid = BNXT_ULP_CLASS_HID_00a7, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [68] = { - .class_hid = BNXT_ULP_CLASS_HID_026b, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [69] = { - .class_hid = BNXT_ULP_CLASS_HID_0371, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [70] = { - .class_hid = BNXT_ULP_CLASS_HID_0525, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [71] = { - .class_hid = BNXT_ULP_CLASS_HID_07d9, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [72] = { - .class_hid = BNXT_ULP_CLASS_HID_018d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [73] = { - .class_hid = BNXT_ULP_CLASS_HID_0177, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [74] = { - .class_hid = BNXT_ULP_CLASS_HID_033b, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [75] = { - .class_hid = BNXT_ULP_CLASS_HID_05df, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [76] = { - .class_hid = BNXT_ULP_CLASS_HID_0783, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [77] = { - .class_hid = BNXT_ULP_CLASS_HID_0069, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [78] = { - .class_hid = BNXT_ULP_CLASS_HID_025d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [79] = { - .class_hid = BNXT_ULP_CLASS_HID_00ef, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [80] = { - .class_hid = BNXT_ULP_CLASS_HID_06a5, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [81] = { - .class_hid = BNXT_ULP_CLASS_HID_02f1, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [82] = { - .class_hid = BNXT_ULP_CLASS_HID_04a5, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [83] = { - .class_hid = BNXT_ULP_CLASS_HID_0377, + [25] = { + .class_hid = BNXT_ULP_CLASS_HID_0178, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 10, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -1817,8 +588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | @@ -1826,11 +596,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [84] = { - .class_hid = BNXT_ULP_CLASS_HID_053b, + [26] = { + .class_hid = BNXT_ULP_CLASS_HID_0070, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 10, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -1839,20 +609,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [85] = { - .class_hid = BNXT_ULP_CLASS_HID_0601, + [27] = { + .class_hid = BNXT_ULP_CLASS_HID_00f3, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 10, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -1860,7 +627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | @@ -1869,11 +636,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [86] = { - .class_hid = BNXT_ULP_CLASS_HID_03df, + [28] = { + .class_hid = BNXT_ULP_CLASS_HID_01d8, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 10, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -1882,20 +649,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [87] = { - .class_hid = BNXT_ULP_CLASS_HID_0269, + [29] = { + .class_hid = BNXT_ULP_CLASS_HID_005b, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 10, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -1903,9 +668,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | @@ -1913,11 +677,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [88] = { - .class_hid = BNXT_ULP_CLASS_HID_045d, + [30] = { + .class_hid = BNXT_ULP_CLASS_HID_0153, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 10, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -1926,1472 +690,1060 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [89] = { - .class_hid = BNXT_ULP_CLASS_HID_02dd, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [90] = { - .class_hid = BNXT_ULP_CLASS_HID_04e9, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [91] = { - .class_hid = BNXT_ULP_CLASS_HID_035b, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [92] = { - .class_hid = BNXT_ULP_CLASS_HID_0101, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [93] = { - .class_hid = BNXT_ULP_CLASS_HID_0227, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 10, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [94] = { - .class_hid = BNXT_ULP_CLASS_HID_03f3, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 11, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [95] = { - .class_hid = BNXT_ULP_CLASS_HID_02a5, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [96] = { - .class_hid = BNXT_ULP_CLASS_HID_0471, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [97] = { - .class_hid = BNXT_ULP_CLASS_HID_00a5, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [98] = { - .class_hid = BNXT_ULP_CLASS_HID_0271, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [99] = { - .class_hid = BNXT_ULP_CLASS_HID_04dd, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [100] = { - .class_hid = BNXT_ULP_CLASS_HID_06e9, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [101] = { - .class_hid = BNXT_ULP_CLASS_HID_078f, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [102] = { - .class_hid = BNXT_ULP_CLASS_HID_015b, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [103] = { - .class_hid = BNXT_ULP_CLASS_HID_0427, + [31] = { + .class_hid = BNXT_ULP_CLASS_HID_01a3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, + .hdr_sig_id = 4, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [104] = { - .class_hid = BNXT_ULP_CLASS_HID_05f3, + [32] = { + .class_hid = BNXT_ULP_CLASS_HID_00bb, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 12, + .hdr_sig_id = 4, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [105] = { - .class_hid = BNXT_ULP_CLASS_HID_01b7, + [33] = { + .class_hid = BNXT_ULP_CLASS_HID_0082, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [106] = { - .class_hid = BNXT_ULP_CLASS_HID_0343, + [34] = { + .class_hid = BNXT_ULP_CLASS_HID_018a, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [107] = { - .class_hid = BNXT_ULP_CLASS_HID_0235, + [35] = { + .class_hid = BNXT_ULP_CLASS_HID_01fa, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [108] = { - .class_hid = BNXT_ULP_CLASS_HID_03c1, + [36] = { + .class_hid = BNXT_ULP_CLASS_HID_00e2, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [109] = { - .class_hid = BNXT_ULP_CLASS_HID_0091, + [37] = { + .class_hid = BNXT_ULP_CLASS_HID_017d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 5, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [110] = { - .class_hid = BNXT_ULP_CLASS_HID_02ad, + [38] = { + .class_hid = BNXT_ULP_CLASS_HID_005a, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [111] = { - .class_hid = BNXT_ULP_CLASS_HID_011f, + [39] = { + .class_hid = BNXT_ULP_CLASS_HID_00d5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [112] = { - .class_hid = BNXT_ULP_CLASS_HID_032b, + [40] = { + .class_hid = BNXT_ULP_CLASS_HID_01b2, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [113] = { - .class_hid = BNXT_ULP_CLASS_HID_071f, + [41] = { + .class_hid = BNXT_ULP_CLASS_HID_0160, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [114] = { - .class_hid = BNXT_ULP_CLASS_HID_012b, + [42] = { + .class_hid = BNXT_ULP_CLASS_HID_0068, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [115] = { - .class_hid = BNXT_ULP_CLASS_HID_03b7, + [43] = { + .class_hid = BNXT_ULP_CLASS_HID_00eb, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [116] = { - .class_hid = BNXT_ULP_CLASS_HID_0543, + [44] = { + .class_hid = BNXT_ULP_CLASS_HID_01c0, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [117] = { - .class_hid = BNXT_ULP_CLASS_HID_0679, + [45] = { + .class_hid = BNXT_ULP_CLASS_HID_0043, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [118] = { - .class_hid = BNXT_ULP_CLASS_HID_0035, + [46] = { + .class_hid = BNXT_ULP_CLASS_HID_014b, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [119] = { - .class_hid = BNXT_ULP_CLASS_HID_0291, + [47] = { + .class_hid = BNXT_ULP_CLASS_HID_01bb, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [120] = { - .class_hid = BNXT_ULP_CLASS_HID_04ad, + [48] = { + .class_hid = BNXT_ULP_CLASS_HID_00a3, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 12, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [121] = { - .class_hid = BNXT_ULP_CLASS_HID_01da, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [122] = { - .class_hid = BNXT_ULP_CLASS_HID_03ee, + [49] = { + .class_hid = BNXT_ULP_CLASS_HID_00cb, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 13, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [123] = { - .class_hid = BNXT_ULP_CLASS_HID_0642, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [124] = { - .class_hid = BNXT_ULP_CLASS_HID_0016, + [50] = { + .class_hid = BNXT_ULP_CLASS_HID_00b4, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [125] = { - .class_hid = BNXT_ULP_CLASS_HID_0776, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [126] = { - .class_hid = BNXT_ULP_CLASS_HID_013a, + [51] = { + .class_hid = BNXT_ULP_CLASS_HID_0013, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [127] = { - .class_hid = BNXT_ULP_CLASS_HID_039e, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [128] = { - .class_hid = BNXT_ULP_CLASS_HID_05a2, + [52] = { + .class_hid = BNXT_ULP_CLASS_HID_001c, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [129] = { - .class_hid = BNXT_ULP_CLASS_HID_0697, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 14, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [130] = { - .class_hid = BNXT_ULP_CLASS_HID_005b, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 14, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [131] = { - .class_hid = BNXT_ULP_CLASS_HID_0715, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 14, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [132] = { - .class_hid = BNXT_ULP_CLASS_HID_00d9, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 14, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [133] = { - .class_hid = BNXT_ULP_CLASS_HID_05e9, + [53] = { + .class_hid = BNXT_ULP_CLASS_HID_017b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 14, + .hdr_sig_id = 6, + .flow_sig_id = 6, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [134] = { - .class_hid = BNXT_ULP_CLASS_HID_07bd, + [54] = { + .class_hid = BNXT_ULP_CLASS_HID_0164, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 15, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [135] = { - .class_hid = BNXT_ULP_CLASS_HID_066f, + [55] = { + .class_hid = BNXT_ULP_CLASS_HID_00c3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [136] = { - .class_hid = BNXT_ULP_CLASS_HID_0033, + [56] = { + .class_hid = BNXT_ULP_CLASS_HID_00cc, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [137] = { - .class_hid = BNXT_ULP_CLASS_HID_046f, + [57] = { + .class_hid = BNXT_ULP_CLASS_HID_01a5, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [138] = { - .class_hid = BNXT_ULP_CLASS_HID_0633, + [58] = { + .class_hid = BNXT_ULP_CLASS_HID_0196, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [139] = { - .class_hid = BNXT_ULP_CLASS_HID_0097, + [59] = { + .class_hid = BNXT_ULP_CLASS_HID_010d, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [140] = { - .class_hid = BNXT_ULP_CLASS_HID_025b, + [60] = { + .class_hid = BNXT_ULP_CLASS_HID_00fe, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [141] = { - .class_hid = BNXT_ULP_CLASS_HID_0341, + [61] = { + .class_hid = BNXT_ULP_CLASS_HID_0084, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [142] = { - .class_hid = BNXT_ULP_CLASS_HID_0515, + [62] = { + .class_hid = BNXT_ULP_CLASS_HID_0046, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [143] = { - .class_hid = BNXT_ULP_CLASS_HID_07e9, + [63] = { + .class_hid = BNXT_ULP_CLASS_HID_01ec, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [144] = { - .class_hid = BNXT_ULP_CLASS_HID_01bd, + [64] = { + .class_hid = BNXT_ULP_CLASS_HID_01ae, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16, + .hdr_sig_id = 6, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [145] = { - .class_hid = BNXT_ULP_CLASS_HID_0147, + [65] = { + .class_hid = BNXT_ULP_CLASS_HID_00d3, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [146] = { - .class_hid = BNXT_ULP_CLASS_HID_030b, + [66] = { + .class_hid = BNXT_ULP_CLASS_HID_00ac, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [147] = { - .class_hid = BNXT_ULP_CLASS_HID_05ef, + [67] = { + .class_hid = BNXT_ULP_CLASS_HID_000b, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [148] = { - .class_hid = BNXT_ULP_CLASS_HID_07b3, + [68] = { + .class_hid = BNXT_ULP_CLASS_HID_0004, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [149] = { - .class_hid = BNXT_ULP_CLASS_HID_0059, + [69] = { + .class_hid = BNXT_ULP_CLASS_HID_0163, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 7, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [150] = { - .class_hid = BNXT_ULP_CLASS_HID_026d, + [70] = { + .class_hid = BNXT_ULP_CLASS_HID_017c, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [151] = { - .class_hid = BNXT_ULP_CLASS_HID_00df, + [71] = { + .class_hid = BNXT_ULP_CLASS_HID_00db, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [152] = { - .class_hid = BNXT_ULP_CLASS_HID_0695, + [72] = { + .class_hid = BNXT_ULP_CLASS_HID_00d4, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [153] = { - .class_hid = BNXT_ULP_CLASS_HID_02c1, + [73] = { + .class_hid = BNXT_ULP_CLASS_HID_01bd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [154] = { - .class_hid = BNXT_ULP_CLASS_HID_0495, + [74] = { + .class_hid = BNXT_ULP_CLASS_HID_018e, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [155] = { - .class_hid = BNXT_ULP_CLASS_HID_0347, + [75] = { + .class_hid = BNXT_ULP_CLASS_HID_0115, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [156] = { - .class_hid = BNXT_ULP_CLASS_HID_050b, + [76] = { + .class_hid = BNXT_ULP_CLASS_HID_00e6, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [157] = { - .class_hid = BNXT_ULP_CLASS_HID_0631, + [77] = { + .class_hid = BNXT_ULP_CLASS_HID_009c, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [158] = { - .class_hid = BNXT_ULP_CLASS_HID_03ef, + [78] = { + .class_hid = BNXT_ULP_CLASS_HID_005e, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [159] = { - .class_hid = BNXT_ULP_CLASS_HID_0259, + [79] = { + .class_hid = BNXT_ULP_CLASS_HID_01f4, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [160] = { - .class_hid = BNXT_ULP_CLASS_HID_046d, + [80] = { + .class_hid = BNXT_ULP_CLASS_HID_01b6, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16, + .flow_sig_id = 8, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index fc342bef0a..0bae79fe03 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,22 +3,22 @@ * All rights reserved. */ -/* date: Tue Dec 1 10:17:11 2020 */ +/* date: Fri Dec 4 18:49:44 2020 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 31 +#define BNXT_ULP_REGFILE_MAX_SZ 32 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 #define BNXT_ULP_GEN_TBL_MAX_SZ 6 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 161 -#define BNXT_ULP_CLASS_HID_LOW_PRIME 7669 +#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 512 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 81 +#define BNXT_ULP_CLASS_HID_LOW_PRIME 4049 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919 -#define BNXT_ULP_CLASS_HID_SHFTR 24 +#define BNXT_ULP_CLASS_HID_SHFTR 25 #define BNXT_ULP_CLASS_HID_SHFTL 23 -#define BNXT_ULP_CLASS_HID_MASK 2047 +#define BNXT_ULP_CLASS_HID_MASK 511 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 15 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 @@ -32,11 +32,11 @@ #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 #define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033 #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 38 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 192 -#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 10 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 341 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 10 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 257 +#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 11 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 367 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 14 #define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7 #define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38 #define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192 @@ -48,7 +48,7 @@ #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 0 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 0 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 65 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 2 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 11 #define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2 #define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4 #define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0 @@ -248,7 +248,8 @@ enum bnxt_ulp_field_cond_src { BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3, BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4, BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5, - BNXT_ULP_FIELD_COND_SRC_LAST = 6 + BNXT_ULP_FIELD_COND_SRC_SRC1_PLUS_SRC2 = 6, + BNXT_ULP_FIELD_COND_SRC_LAST = 7 }; enum bnxt_ulp_field_src { @@ -368,10 +369,11 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_SRC_PROPERTY_PTR = 25, BNXT_ULP_RF_IDX_GENERIC_TBL_HIT = 26, BNXT_ULP_RF_IDX_MIRROR_PTR_0 = 27, - BNXT_ULP_RF_IDX_HDR_SIG_ID = 28, - BNXT_ULP_RF_IDX_FLOW_SIG_ID = 29, - BNXT_ULP_RF_IDX_RID = 30, - BNXT_ULP_RF_IDX_LAST = 31 + BNXT_ULP_RF_IDX_MIRROR_ID_0 = 28, + BNXT_ULP_RF_IDX_HDR_SIG_ID = 29, + BNXT_ULP_RF_IDX_FLOW_SIG_ID = 30, + BNXT_ULP_RF_IDX_RID = 31, + BNXT_ULP_RF_IDX_LAST = 32 }; enum bnxt_ulp_tcam_tbl_opc { @@ -427,7 +429,7 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT = 4, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM = 0, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL = 2 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2 }; enum bnxt_ulp_act_prop_sz { @@ -959,166 +961,86 @@ enum ulp_sr_sym { }; enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_07e0 = 0x07e0, - BNXT_ULP_CLASS_HID_01dc = 0x01dc, - BNXT_ULP_CLASS_HID_006e = 0x006e, - BNXT_ULP_CLASS_HID_025a = 0x025a, - BNXT_ULP_CLASS_HID_0146 = 0x0146, - BNXT_ULP_CLASS_HID_0332 = 0x0332, - BNXT_ULP_CLASS_HID_01c4 = 0x01c4, - BNXT_ULP_CLASS_HID_078a = 0x078a, - BNXT_ULP_CLASS_HID_02ed = 0x02ed, - BNXT_ULP_CLASS_HID_04d9 = 0x04d9, - BNXT_ULP_CLASS_HID_036b = 0x036b, - BNXT_ULP_CLASS_HID_0131 = 0x0131, - BNXT_ULP_CLASS_HID_0217 = 0x0217, - BNXT_ULP_CLASS_HID_03c3 = 0x03c3, - BNXT_ULP_CLASS_HID_0295 = 0x0295, - BNXT_ULP_CLASS_HID_0441 = 0x0441, - BNXT_ULP_CLASS_HID_0095 = 0x0095, - BNXT_ULP_CLASS_HID_0241 = 0x0241, - BNXT_ULP_CLASS_HID_04ed = 0x04ed, - BNXT_ULP_CLASS_HID_06d9 = 0x06d9, - BNXT_ULP_CLASS_HID_07bf = 0x07bf, - BNXT_ULP_CLASS_HID_016b = 0x016b, - BNXT_ULP_CLASS_HID_0417 = 0x0417, - BNXT_ULP_CLASS_HID_05c3 = 0x05c3, - BNXT_ULP_CLASS_HID_0187 = 0x0187, - BNXT_ULP_CLASS_HID_0373 = 0x0373, - BNXT_ULP_CLASS_HID_0205 = 0x0205, - BNXT_ULP_CLASS_HID_03f1 = 0x03f1, - BNXT_ULP_CLASS_HID_00a1 = 0x00a1, - BNXT_ULP_CLASS_HID_029d = 0x029d, - BNXT_ULP_CLASS_HID_012f = 0x012f, - BNXT_ULP_CLASS_HID_031b = 0x031b, - BNXT_ULP_CLASS_HID_072f = 0x072f, - BNXT_ULP_CLASS_HID_011b = 0x011b, - BNXT_ULP_CLASS_HID_0387 = 0x0387, - BNXT_ULP_CLASS_HID_0573 = 0x0573, - BNXT_ULP_CLASS_HID_0649 = 0x0649, - BNXT_ULP_CLASS_HID_0005 = 0x0005, - BNXT_ULP_CLASS_HID_02a1 = 0x02a1, - BNXT_ULP_CLASS_HID_049d = 0x049d, - BNXT_ULP_CLASS_HID_01ea = 0x01ea, - BNXT_ULP_CLASS_HID_03de = 0x03de, - BNXT_ULP_CLASS_HID_0672 = 0x0672, - BNXT_ULP_CLASS_HID_0026 = 0x0026, - BNXT_ULP_CLASS_HID_0746 = 0x0746, - BNXT_ULP_CLASS_HID_010a = 0x010a, - BNXT_ULP_CLASS_HID_03ae = 0x03ae, - BNXT_ULP_CLASS_HID_0592 = 0x0592, - BNXT_ULP_CLASS_HID_07d0 = 0x07d0, - BNXT_ULP_CLASS_HID_01ec = 0x01ec, - BNXT_ULP_CLASS_HID_005e = 0x005e, - BNXT_ULP_CLASS_HID_026a = 0x026a, - BNXT_ULP_CLASS_HID_0176 = 0x0176, - BNXT_ULP_CLASS_HID_0302 = 0x0302, - BNXT_ULP_CLASS_HID_01f4 = 0x01f4, - BNXT_ULP_CLASS_HID_07ba = 0x07ba, - BNXT_ULP_CLASS_HID_06a7 = 0x06a7, - BNXT_ULP_CLASS_HID_006b = 0x006b, - BNXT_ULP_CLASS_HID_0725 = 0x0725, - BNXT_ULP_CLASS_HID_00e9 = 0x00e9, - BNXT_ULP_CLASS_HID_05d9 = 0x05d9, - BNXT_ULP_CLASS_HID_078d = 0x078d, - BNXT_ULP_CLASS_HID_065f = 0x065f, + BNXT_ULP_CLASS_HID_005c = 0x005c, BNXT_ULP_CLASS_HID_0003 = 0x0003, - BNXT_ULP_CLASS_HID_045f = 0x045f, - BNXT_ULP_CLASS_HID_0603 = 0x0603, - BNXT_ULP_CLASS_HID_00a7 = 0x00a7, - BNXT_ULP_CLASS_HID_026b = 0x026b, - BNXT_ULP_CLASS_HID_0371 = 0x0371, - BNXT_ULP_CLASS_HID_0525 = 0x0525, - BNXT_ULP_CLASS_HID_07d9 = 0x07d9, + BNXT_ULP_CLASS_HID_0132 = 0x0132, + BNXT_ULP_CLASS_HID_00e1 = 0x00e1, + BNXT_ULP_CLASS_HID_0044 = 0x0044, + BNXT_ULP_CLASS_HID_001b = 0x001b, + BNXT_ULP_CLASS_HID_012a = 0x012a, + BNXT_ULP_CLASS_HID_00f9 = 0x00f9, BNXT_ULP_CLASS_HID_018d = 0x018d, - BNXT_ULP_CLASS_HID_0177 = 0x0177, - BNXT_ULP_CLASS_HID_033b = 0x033b, - BNXT_ULP_CLASS_HID_05df = 0x05df, - BNXT_ULP_CLASS_HID_0783 = 0x0783, - BNXT_ULP_CLASS_HID_0069 = 0x0069, - BNXT_ULP_CLASS_HID_025d = 0x025d, - BNXT_ULP_CLASS_HID_00ef = 0x00ef, - BNXT_ULP_CLASS_HID_06a5 = 0x06a5, - BNXT_ULP_CLASS_HID_02f1 = 0x02f1, - BNXT_ULP_CLASS_HID_04a5 = 0x04a5, - BNXT_ULP_CLASS_HID_0377 = 0x0377, - BNXT_ULP_CLASS_HID_053b = 0x053b, - BNXT_ULP_CLASS_HID_0601 = 0x0601, - BNXT_ULP_CLASS_HID_03df = 0x03df, - BNXT_ULP_CLASS_HID_0269 = 0x0269, - BNXT_ULP_CLASS_HID_045d = 0x045d, - BNXT_ULP_CLASS_HID_02dd = 0x02dd, - BNXT_ULP_CLASS_HID_04e9 = 0x04e9, - BNXT_ULP_CLASS_HID_035b = 0x035b, - BNXT_ULP_CLASS_HID_0101 = 0x0101, - BNXT_ULP_CLASS_HID_0227 = 0x0227, - BNXT_ULP_CLASS_HID_03f3 = 0x03f3, - BNXT_ULP_CLASS_HID_02a5 = 0x02a5, - BNXT_ULP_CLASS_HID_0471 = 0x0471, - BNXT_ULP_CLASS_HID_00a5 = 0x00a5, - BNXT_ULP_CLASS_HID_0271 = 0x0271, - BNXT_ULP_CLASS_HID_04dd = 0x04dd, - BNXT_ULP_CLASS_HID_06e9 = 0x06e9, - BNXT_ULP_CLASS_HID_078f = 0x078f, - BNXT_ULP_CLASS_HID_015b = 0x015b, - BNXT_ULP_CLASS_HID_0427 = 0x0427, - BNXT_ULP_CLASS_HID_05f3 = 0x05f3, - BNXT_ULP_CLASS_HID_01b7 = 0x01b7, - BNXT_ULP_CLASS_HID_0343 = 0x0343, - BNXT_ULP_CLASS_HID_0235 = 0x0235, - BNXT_ULP_CLASS_HID_03c1 = 0x03c1, - BNXT_ULP_CLASS_HID_0091 = 0x0091, - BNXT_ULP_CLASS_HID_02ad = 0x02ad, - BNXT_ULP_CLASS_HID_011f = 0x011f, - BNXT_ULP_CLASS_HID_032b = 0x032b, - BNXT_ULP_CLASS_HID_071f = 0x071f, - BNXT_ULP_CLASS_HID_012b = 0x012b, - BNXT_ULP_CLASS_HID_03b7 = 0x03b7, - BNXT_ULP_CLASS_HID_0543 = 0x0543, - BNXT_ULP_CLASS_HID_0679 = 0x0679, - BNXT_ULP_CLASS_HID_0035 = 0x0035, - BNXT_ULP_CLASS_HID_0291 = 0x0291, - BNXT_ULP_CLASS_HID_04ad = 0x04ad, - BNXT_ULP_CLASS_HID_01da = 0x01da, - BNXT_ULP_CLASS_HID_03ee = 0x03ee, - BNXT_ULP_CLASS_HID_0642 = 0x0642, - BNXT_ULP_CLASS_HID_0016 = 0x0016, - BNXT_ULP_CLASS_HID_0776 = 0x0776, - BNXT_ULP_CLASS_HID_013a = 0x013a, - BNXT_ULP_CLASS_HID_039e = 0x039e, - BNXT_ULP_CLASS_HID_05a2 = 0x05a2, - BNXT_ULP_CLASS_HID_0697 = 0x0697, + BNXT_ULP_CLASS_HID_00a7 = 0x00a7, + BNXT_ULP_CLASS_HID_006f = 0x006f, + BNXT_ULP_CLASS_HID_0181 = 0x0181, + BNXT_ULP_CLASS_HID_0195 = 0x0195, + BNXT_ULP_CLASS_HID_00bf = 0x00bf, + BNXT_ULP_CLASS_HID_0077 = 0x0077, + BNXT_ULP_CLASS_HID_0199 = 0x0199, + BNXT_ULP_CLASS_HID_009a = 0x009a, + BNXT_ULP_CLASS_HID_0192 = 0x0192, + BNXT_ULP_CLASS_HID_01e2 = 0x01e2, + BNXT_ULP_CLASS_HID_00fa = 0x00fa, + BNXT_ULP_CLASS_HID_0165 = 0x0165, + BNXT_ULP_CLASS_HID_0042 = 0x0042, + BNXT_ULP_CLASS_HID_00cd = 0x00cd, + BNXT_ULP_CLASS_HID_01aa = 0x01aa, + BNXT_ULP_CLASS_HID_0178 = 0x0178, + BNXT_ULP_CLASS_HID_0070 = 0x0070, + BNXT_ULP_CLASS_HID_00f3 = 0x00f3, + BNXT_ULP_CLASS_HID_01d8 = 0x01d8, BNXT_ULP_CLASS_HID_005b = 0x005b, - BNXT_ULP_CLASS_HID_0715 = 0x0715, - BNXT_ULP_CLASS_HID_00d9 = 0x00d9, - BNXT_ULP_CLASS_HID_05e9 = 0x05e9, - BNXT_ULP_CLASS_HID_07bd = 0x07bd, - BNXT_ULP_CLASS_HID_066f = 0x066f, - BNXT_ULP_CLASS_HID_0033 = 0x0033, - BNXT_ULP_CLASS_HID_046f = 0x046f, - BNXT_ULP_CLASS_HID_0633 = 0x0633, - BNXT_ULP_CLASS_HID_0097 = 0x0097, - BNXT_ULP_CLASS_HID_025b = 0x025b, - BNXT_ULP_CLASS_HID_0341 = 0x0341, - BNXT_ULP_CLASS_HID_0515 = 0x0515, - BNXT_ULP_CLASS_HID_07e9 = 0x07e9, + BNXT_ULP_CLASS_HID_0153 = 0x0153, + BNXT_ULP_CLASS_HID_01a3 = 0x01a3, + BNXT_ULP_CLASS_HID_00bb = 0x00bb, + BNXT_ULP_CLASS_HID_0082 = 0x0082, + BNXT_ULP_CLASS_HID_018a = 0x018a, + BNXT_ULP_CLASS_HID_01fa = 0x01fa, + BNXT_ULP_CLASS_HID_00e2 = 0x00e2, + BNXT_ULP_CLASS_HID_017d = 0x017d, + BNXT_ULP_CLASS_HID_005a = 0x005a, + BNXT_ULP_CLASS_HID_00d5 = 0x00d5, + BNXT_ULP_CLASS_HID_01b2 = 0x01b2, + BNXT_ULP_CLASS_HID_0160 = 0x0160, + BNXT_ULP_CLASS_HID_0068 = 0x0068, + BNXT_ULP_CLASS_HID_00eb = 0x00eb, + BNXT_ULP_CLASS_HID_01c0 = 0x01c0, + BNXT_ULP_CLASS_HID_0043 = 0x0043, + BNXT_ULP_CLASS_HID_014b = 0x014b, + BNXT_ULP_CLASS_HID_01bb = 0x01bb, + BNXT_ULP_CLASS_HID_00a3 = 0x00a3, + BNXT_ULP_CLASS_HID_00cb = 0x00cb, + BNXT_ULP_CLASS_HID_00b4 = 0x00b4, + BNXT_ULP_CLASS_HID_0013 = 0x0013, + BNXT_ULP_CLASS_HID_001c = 0x001c, + BNXT_ULP_CLASS_HID_017b = 0x017b, + BNXT_ULP_CLASS_HID_0164 = 0x0164, + BNXT_ULP_CLASS_HID_00c3 = 0x00c3, + BNXT_ULP_CLASS_HID_00cc = 0x00cc, + BNXT_ULP_CLASS_HID_01a5 = 0x01a5, + BNXT_ULP_CLASS_HID_0196 = 0x0196, + BNXT_ULP_CLASS_HID_010d = 0x010d, + BNXT_ULP_CLASS_HID_00fe = 0x00fe, + BNXT_ULP_CLASS_HID_0084 = 0x0084, + BNXT_ULP_CLASS_HID_0046 = 0x0046, + BNXT_ULP_CLASS_HID_01ec = 0x01ec, + BNXT_ULP_CLASS_HID_01ae = 0x01ae, + BNXT_ULP_CLASS_HID_00d3 = 0x00d3, + BNXT_ULP_CLASS_HID_00ac = 0x00ac, + BNXT_ULP_CLASS_HID_000b = 0x000b, + BNXT_ULP_CLASS_HID_0004 = 0x0004, + BNXT_ULP_CLASS_HID_0163 = 0x0163, + BNXT_ULP_CLASS_HID_017c = 0x017c, + BNXT_ULP_CLASS_HID_00db = 0x00db, + BNXT_ULP_CLASS_HID_00d4 = 0x00d4, BNXT_ULP_CLASS_HID_01bd = 0x01bd, - BNXT_ULP_CLASS_HID_0147 = 0x0147, - BNXT_ULP_CLASS_HID_030b = 0x030b, - BNXT_ULP_CLASS_HID_05ef = 0x05ef, - BNXT_ULP_CLASS_HID_07b3 = 0x07b3, - BNXT_ULP_CLASS_HID_0059 = 0x0059, - BNXT_ULP_CLASS_HID_026d = 0x026d, - BNXT_ULP_CLASS_HID_00df = 0x00df, - BNXT_ULP_CLASS_HID_0695 = 0x0695, - BNXT_ULP_CLASS_HID_02c1 = 0x02c1, - BNXT_ULP_CLASS_HID_0495 = 0x0495, - BNXT_ULP_CLASS_HID_0347 = 0x0347, - BNXT_ULP_CLASS_HID_050b = 0x050b, - BNXT_ULP_CLASS_HID_0631 = 0x0631, - BNXT_ULP_CLASS_HID_03ef = 0x03ef, - BNXT_ULP_CLASS_HID_0259 = 0x0259, - BNXT_ULP_CLASS_HID_046d = 0x046d + BNXT_ULP_CLASS_HID_018e = 0x018e, + BNXT_ULP_CLASS_HID_0115 = 0x0115, + BNXT_ULP_CLASS_HID_00e6 = 0x00e6, + BNXT_ULP_CLASS_HID_009c = 0x009c, + BNXT_ULP_CLASS_HID_005e = 0x005e, + BNXT_ULP_CLASS_HID_01f4 = 0x01f4, + BNXT_ULP_CLASS_HID_01b6 = 0x01b6 }; enum bnxt_ulp_act_hid { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h index 0e197e362e..fc388cc490 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 1 10:17:11 2020 */ +/* date: Mon Dec 7 09:51:03 2020 */ #ifndef ULP_HDR_FIELD_ENUMS_H_ #define ULP_HDR_FIELD_ENUMS_H_ @@ -113,23 +113,25 @@ enum bnxt_ulp_hf1_0_bitmask { BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM = 0x0000080000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_URP = 0x0000040000000000 + BNXT_ULP_HF1_0_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF1_0_BITMASK_O_TCP_URP = 0x0000010000000000 }; enum bnxt_ulp_hf1_1_bitmask { @@ -138,26 +140,20 @@ enum bnxt_ulp_hf1_1_bitmask { BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_URP = 0x0000008000000000 + BNXT_ULP_HF1_1_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_1_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF1_1_BITMASK_O_UDP_CSUM = 0x0000200000000000 }; enum bnxt_ulp_hf1_2_bitmask { @@ -166,25 +162,23 @@ enum bnxt_ulp_hf1_2_bitmask { BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_URP = 0x0000010000000000 + BNXT_ULP_HF1_2_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM = 0x0000080000000000, + BNXT_ULP_HF1_2_BITMASK_O_TCP_URP = 0x0000040000000000 }; enum bnxt_ulp_hf1_3_bitmask { @@ -246,18 +240,20 @@ enum bnxt_ulp_hf1_5_bitmask { BNXT_ULP_HF1_5_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM = 0x0000100000000000 + BNXT_ULP_HF1_5_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM = 0x0000040000000000 }; enum bnxt_ulp_hf1_6_bitmask { @@ -266,20 +262,26 @@ enum bnxt_ulp_hf1_6_bitmask { BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_6_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF1_6_BITMASK_O_UDP_CSUM = 0x0000200000000000 + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF1_6_BITMASK_O_TCP_URP = 0x0000008000000000 }; enum bnxt_ulp_hf1_7_bitmask { @@ -291,19 +293,17 @@ enum bnxt_ulp_hf1_7_bitmask { BNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM = 0x0000040000000000 + BNXT_ULP_HF1_7_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM = 0x0000100000000000 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index ff003b2ebd..6b49a9d93f 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 1 10:17:11 2020 */ +/* date: Fri Dec 4 19:01:47 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -36,13 +36,13 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .result_num_bytes = 16, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_INGRESS] = { .result_num_entries = 16, .result_num_bytes = 16, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_EGRESS] = { .result_num_entries = 16, .result_num_bytes = 16, @@ -207,11 +207,11 @@ uint32_t ulp_glb_template_tbl[] = { /* Provides act_bitmask */ struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = { - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_INGRESS] = { .act_bitmask = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_EGRESS] = { .act_bitmask = BNXT_ULP_ACT_BIT_SHARED_SAMPLE } @@ -312,72 +312,66 @@ uint8_t ulp_glb_field_tbl[] = { [2050] = 2, [2052] = 3, [2054] = 4, - [2076] = 5, - [2078] = 6, - [2080] = 7, - [2082] = 8, - [2084] = 9, - [2086] = 10, - [2088] = 11, - [2090] = 12, - [2102] = 13, - [2104] = 14, - [2106] = 15, - [2108] = 16, - [2110] = 17, - [2112] = 18, - [2114] = 19, - [2116] = 20, - [2118] = 21, + [2056] = 5, + [2058] = 6, + [2060] = 7, + [2062] = 8, + [2064] = 9, + [2066] = 10, + [2068] = 11, + [2070] = 12, + [2072] = 13, + [2074] = 14, + [2102] = 15, + [2104] = 16, + [2106] = 17, + [2108] = 18, + [2110] = 19, + [2112] = 20, + [2114] = 21, + [2116] = 22, + [2118] = 23, [2176] = 0, [2177] = 1, [2178] = 2, [2180] = 3, [2182] = 4, - [2204] = 8, - [2206] = 9, - [2208] = 10, - [2210] = 11, - [2212] = 12, - [2214] = 13, - [2216] = 14, - [2218] = 15, - [2230] = 16, - [2232] = 17, - [2234] = 18, - [2236] = 19, - [2238] = 20, - [2240] = 21, - [2242] = 22, - [2244] = 23, - [2246] = 24, - [2256] = 5, - [2260] = 6, - [2264] = 7, + [2184] = 5, + [2186] = 6, + [2188] = 7, + [2190] = 8, + [2192] = 9, + [2194] = 10, + [2196] = 11, + [2198] = 12, + [2200] = 13, + [2202] = 14, + [2248] = 15, + [2250] = 16, + [2252] = 17, + [2254] = 18, [2304] = 0, [2305] = 1, [2306] = 2, [2308] = 3, [2310] = 4, - [2312] = 5, - [2314] = 6, - [2316] = 7, - [2318] = 8, - [2320] = 9, - [2322] = 10, - [2324] = 11, - [2326] = 12, - [2328] = 13, - [2330] = 14, - [2358] = 15, - [2360] = 16, - [2362] = 17, - [2364] = 18, - [2366] = 19, - [2368] = 20, - [2370] = 21, - [2372] = 22, - [2374] = 23, + [2332] = 5, + [2334] = 6, + [2336] = 7, + [2338] = 8, + [2340] = 9, + [2342] = 10, + [2344] = 11, + [2346] = 12, + [2358] = 13, + [2360] = 14, + [2362] = 15, + [2364] = 16, + [2366] = 17, + [2368] = 18, + [2370] = 19, + [2372] = 20, + [2374] = 21, [2432] = 0, [2433] = 1, [2434] = 2, @@ -427,18 +421,20 @@ uint8_t ulp_glb_field_tbl[] = { [2690] = 2, [2692] = 3, [2694] = 4, - [2716] = 8, - [2718] = 9, - [2720] = 10, - [2722] = 11, - [2724] = 12, - [2726] = 13, - [2728] = 14, - [2730] = 15, - [2760] = 16, - [2762] = 17, - [2764] = 18, - [2766] = 19, + [2696] = 8, + [2698] = 9, + [2700] = 10, + [2702] = 11, + [2704] = 12, + [2706] = 13, + [2708] = 14, + [2710] = 15, + [2712] = 16, + [2714] = 17, + [2760] = 18, + [2762] = 19, + [2764] = 20, + [2766] = 21, [2768] = 5, [2772] = 6, [2776] = 7, @@ -447,39 +443,43 @@ uint8_t ulp_glb_field_tbl[] = { [2818] = 2, [2820] = 3, [2822] = 4, - [2824] = 5, - [2826] = 6, - [2828] = 7, - [2830] = 8, - [2832] = 9, - [2834] = 10, - [2836] = 11, - [2838] = 12, - [2840] = 13, - [2842] = 14, - [2888] = 15, - [2890] = 16, - [2892] = 17, - [2894] = 18, + [2844] = 8, + [2846] = 9, + [2848] = 10, + [2850] = 11, + [2852] = 12, + [2854] = 13, + [2856] = 14, + [2858] = 15, + [2870] = 16, + [2872] = 17, + [2874] = 18, + [2876] = 19, + [2878] = 20, + [2880] = 21, + [2882] = 22, + [2884] = 23, + [2886] = 24, + [2896] = 5, + [2900] = 6, + [2904] = 7, [2944] = 0, [2945] = 1, [2946] = 2, [2948] = 3, [2950] = 4, - [2952] = 8, - [2954] = 9, - [2956] = 10, - [2958] = 11, - [2960] = 12, - [2962] = 13, - [2964] = 14, - [2966] = 15, - [2968] = 16, - [2970] = 17, - [3016] = 18, - [3018] = 19, - [3020] = 20, - [3022] = 21, + [2972] = 8, + [2974] = 9, + [2976] = 10, + [2978] = 11, + [2980] = 12, + [2982] = 13, + [2984] = 14, + [2986] = 15, + [3016] = 16, + [3018] = 17, + [3020] = 18, + [3022] = 19, [3024] = 5, [3028] = 6, [3032] = 7 diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 5b098cff37..78ee8ed6d1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 1 17:07:12 2020 */ +/* date: Mon Dec 7 09:51:03 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,9 +18,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .num_tbls = 4, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, - .cond_nums = 0 } + .cond_nums = 9 } } }; @@ -34,7 +34,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 0, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -56,7 +56,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, + .cond_start_idx = 10, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -78,7 +78,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -100,7 +100,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -115,6 +115,42 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_SRC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_DST + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP + }, { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT @@ -432,8 +468,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "mirror", .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST }, { .description = "drop", @@ -687,7 +736,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .description = "mirror", .field_bit_size = 2, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff} }, { .description = "drop", diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 52eab7a715..82cbb9b964 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Dec 2 12:05:11 2020 */ +/* date: Mon Dec 7 10:38:39 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 9, + .num_tbls = 11, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -26,76 +26,55 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 9, + .start_tbl_idx = 11, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 } }, /* class_tid: 3, wh_plus, egress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 8, - .start_tbl_idx = 15, + .start_tbl_idx = 17, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 } }, /* class_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 7, - .start_tbl_idx = 23, + .num_tbls = 8, + .start_tbl_idx = 25, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 } }, /* class_tid: 5, wh_plus, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 7, - .start_tbl_idx = 30, + .start_tbl_idx = 33, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 } }, /* class_tid: 6, wh_plus, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 1, - .start_tbl_idx = 37, + .start_tbl_idx = 40, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 } } }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { - { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_goto = 2, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 0, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 0, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 0, - .ident_nums = 1 - }, { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, @@ -103,7 +82,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -111,7 +90,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 1, + .key_start_idx = 0, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -119,7 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 1, + .ident_start_idx = 0, .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ @@ -131,30 +110,57 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 14, + .key_start_idx = 13, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .ident_start_idx = 2, + .ident_start_idx = 1, .ident_nums = 3 }, { /* class_tid: 1, wh_plus, table: branch.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 3, + .cond_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH }, - { /* class_tid: 1, wh_plus, table: profile_tcam.0 */ + { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 1, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 16, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 13, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 4, + .ident_nums = 1 + }, + { /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -170,11 +176,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 17, + .key_start_idx = 59, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 13, + .result_start_idx = 21, .result_bit_size = 38, .result_num_fields = 8, .encap_num_fields = 0, @@ -195,16 +201,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 60, + .key_start_idx = 102, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 21, + .result_start_idx = 29, .result_bit_size = 66, .result_num_fields = 5, .encap_num_fields = 0 }, - { /* class_tid: 1, wh_plus, table: em.int_0 */ + { /* class_tid: 1, wh_plus, table: em.ipv4_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, @@ -218,22 +224,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 63, + .key_start_idx = 105, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, - .result_start_idx = 26, + .result_start_idx = 34, .result_bit_size = 64, .result_num_fields = 9, .encap_num_fields = 0 }, - { /* class_tid: 1, wh_plus, table: eem.ext_0 */ + { /* class_tid: 1, wh_plus, table: eem.ipv4_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 1, + .cond_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 3, .cond_nums = 1 }, @@ -241,22 +247,68 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 73, + .key_start_idx = 115, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, - .result_start_idx = 35, + .result_start_idx = 43, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 + }, + { /* class_tid: 1, wh_plus, table: em.ipv6_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 4, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 125, + .blob_key_bit_size = 416, + .key_bit_size = 416, + .key_num_fields = 11, + .result_start_idx = 52, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0 + }, + { /* class_tid: 1, wh_plus, table: eem.ipv6_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 5, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 136, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 11, + .result_start_idx = 61, .result_bit_size = 64, .result_num_fields = 9, .encap_num_fields = 0 }, - { /* class_tid: 1, wh_plus, table: last */ + { /* class_tid: 1, wh_plus, table: branch.last */ .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH @@ -270,14 +322,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 44, + .result_start_idx = 70, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -289,7 +341,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -300,11 +352,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 83, + .key_start_idx = 147, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 70, + .result_start_idx = 96, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, @@ -320,16 +372,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 96, + .key_start_idx = 160, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 83, + .result_start_idx = 109, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 @@ -341,13 +393,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 87, + .result_start_idx = 113, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 @@ -359,13 +411,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 88, + .result_start_idx = 114, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 @@ -377,13 +429,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 89, + .result_start_idx = 115, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 @@ -397,14 +449,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 90, + .result_start_idx = 116, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -416,7 +468,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 4, + .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -426,11 +478,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 97, + .key_start_idx = 161, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 116, + .result_start_idx = 142, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, @@ -446,12 +498,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 5, + .cond_start_idx = 7, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 110, + .key_start_idx = 174, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -465,7 +517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, + .cond_start_idx = 8, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -474,11 +526,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 111, + .key_start_idx = 175, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 129, + .result_start_idx = 155, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, @@ -494,16 +546,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 124, + .key_start_idx = 188, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 142, + .result_start_idx = 168, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 @@ -515,13 +567,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 146, + .result_start_idx = 172, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 @@ -533,13 +585,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 147, + .result_start_idx = 173, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 @@ -551,17 +603,38 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 148, + .result_start_idx = 174, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 }, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 12, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 189, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 9, + .ident_nums = 1 + }, { /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, @@ -571,14 +644,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 149, + .result_start_idx = 175, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12 @@ -592,14 +665,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 161, + .result_start_idx = 187, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -610,9 +683,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .execute_info = { .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 12, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, @@ -620,15 +693,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 125, + .key_start_idx = 190, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 187, + .result_start_idx = 213, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 9, + .ident_start_idx = 10, .ident_nums = 0 }, { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ @@ -639,22 +712,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_TX, .execute_info = { .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 13, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 138, + .key_start_idx = 203, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 200, + .result_start_idx = 226, .result_bit_size = 62, .result_num_fields = 4, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0 + .encap_num_fields = 0 }, { /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -665,14 +736,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 204, + .result_start_idx = 230, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -684,7 +755,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -694,15 +765,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 139, + .key_start_idx = 204, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 230, + .result_start_idx = 256, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 9, + .ident_start_idx = 10, .ident_nums = 0 }, { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ @@ -712,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -722,15 +793,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 152, + .key_start_idx = 217, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 243, + .result_start_idx = 269, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 9, + .ident_start_idx = 10, .ident_nums = 0 }, { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ @@ -740,24 +811,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 165, + .key_start_idx = 230, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 256, + .result_start_idx = 282, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 9, + .ident_start_idx = 10, .ident_nums = 1 }, { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ @@ -769,16 +839,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 178, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 243, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 269, + .result_start_idx = 295, .result_bit_size = 62, .result_num_fields = 4, .encap_num_fields = 0 @@ -790,13 +861,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 273, + .result_start_idx = 299, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 @@ -808,13 +879,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 274, + .result_start_idx = 300, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 @@ -826,13 +897,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 275, + .result_start_idx = 301, .result_bit_size = 32, .result_num_fields = 1, .encap_num_fields = 0 @@ -846,14 +917,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, - .result_start_idx = 276, + .result_start_idx = 302, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -865,7 +936,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -875,15 +946,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 179, + .key_start_idx = 244, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 302, + .result_start_idx = 328, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0, - .ident_start_idx = 10, + .ident_start_idx = 11, .ident_nums = 0 }, { /* class_tid: 6, wh_plus, table: int_full_act_record.0 */ @@ -895,14 +966,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 315, + .result_start_idx = 341, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -910,10 +981,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { - { - .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, - .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC - }, { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT @@ -927,6 +994,18 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, @@ -949,31 +1028,18 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { { .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT } }; struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .field_info_mask = { @@ -1241,7 +1307,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 1, wh_plus, table: profile_tcam.0 */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */ { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", @@ -1374,22 +1440,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV4}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV6} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -1926,281 +1978,1181 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */ { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l4_hdr_type", + .field_bit_size = 4, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + ULP_WP_SYM_L4_HDR_VALID_YES} } }, - /* class_tid: 1, wh_plus, table: em.int_0 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + ULP_WP_SYM_L3_HDR_TYPE_IPV6} } }, { .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, + .description = "l3_hdr_valid", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_IP_PROTO_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_IP_PROTO_UDP} + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, 0xff} }, .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: em.ipv4_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_IP_PROTO_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_IP_PROTO_UDP} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: eem.ipv4_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 275, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 275, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_IP_PROTO_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_IP_PROTO_UDP} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2208,17 +3160,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: eem.ext_0 */ + /* class_tid: 1, wh_plus, table: em.ipv6_0 */ { .field_info_mask = { .description = "spare", - .field_bit_size = 275, + .field_bit_size = 3, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", - .field_bit_size = 275, + .field_bit_size = 3, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2307,7 +3259,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", + .description = "o_ipv6.ip_proto", .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2315,7 +3267,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "o_ipv4.ip_proto", + .description = "o_ipv6.ip_proto", .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { @@ -2337,42 +3289,290 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "o_ipv6.dst", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "o_ipv6.dst", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: eem.ipv6_0 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 35, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 35, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_IP_PROTO_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_IP_PROTO_UDP} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.src", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "o_ipv6.src", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { @@ -2397,6 +3597,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { } }, { + .field_info_mask = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -3077,6 +4298,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ { .field_info_mask = { @@ -4208,14 +5449,12 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.0 */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */ { .description = "wc_key_id", .field_bit_size = 4, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_profile_id", @@ -4269,6 +5508,65 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */ + { + .description = "wc_key_id", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (249 >> 8) & 0xff, + 249 & 0xff} + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 7} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ { .description = "rid", @@ -4312,7 +5610,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, - /* class_tid: 1, wh_plus, table: em.int_0 */ + /* class_tid: 1, wh_plus, table: em.ipv4_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -4374,7 +5672,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, wh_plus, table: eem.ext_0 */ + /* class_tid: 1, wh_plus, table: eem.ipv4_0 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -4444,6 +5742,138 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, + /* class_tid: 1, wh_plus, table: em.ipv6_0 */ + { + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_int", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "key_size", + .field_bit_size = 9, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 11, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "l1_cacheable", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, wh_plus, table: eem.ipv6_0 */ + { + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_int", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_EEM_ACT_REC_INT} + }, + { + .description = "act_rec_size", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + }, + { + .description = "key_size", + .field_bit_size = 9, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (413 >> 8) & 0xff, + 413 & 0xff} + }, + { + .description = "reserved", + .field_bit_size = 11, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "l1_cacheable", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, /* class_tid: 2, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", @@ -6417,13 +7847,6 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }; struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ - { - .description = "l2_cntxt_id", - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 42 - }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -6435,6 +7858,12 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ { + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 8, + .ident_bit_pos = 58 + }, + { .description = "profile_tcam_index", .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .ident_bit_size = 10, @@ -6446,13 +7875,16 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 42 }, + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */ { - .description = "flow_sig_id", - .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .description = "em_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, .ident_bit_size = 8, - .ident_bit_pos = 58 + .ident_bit_pos = 28 }, - /* class_tid: 1, wh_plus, table: profile_tcam.0 */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -6486,6 +7918,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ + { + .description = "l2_cntxt_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .ident_bit_size = 10, + .ident_bit_pos = 32 + }, /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", From patchwork Sun May 30 08:59:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93584 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E95C9A0524; Sun, 30 May 2021 11:05:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 64F59411D6; Sun, 30 May 2021 11:01:35 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 4DDBB4113C for ; Sun, 30 May 2021 11:01:32 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id DF4D37DC0; Sun, 30 May 2021 02:01:30 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com DF4D37DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365291; bh=l0JVh93MPPiME4jx5vqKJNyPQDFSFGMRtXQINNQH/e0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LNJPm8AeFLf3grN49WycR2k7FER7yRcxBbWaNrZ+VrGInsTiFMZtmRJtwVHWz5pmW MW7KqcTpAaUnJYhuOtPxFHdl+AeF6YFKoaUavSmfW/c/Twq/chbwhNMHu4F19g9k80 bWoNBj0bYsMO2BKB5ZSM8EFxy1d5DVqVw8mciYGw= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:09 +0530 Message-Id: <20210530085929.29695-39-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 38/58] net/bnxt: add conditional opcode and L4 port fields X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The conditional field opcode provides capability to perform changes to the field values specified by template to address platform specific modifications. For instance, mirror id value is modified before it is configured in the hardware. The addition of L4 port compute fields enables support of generic exact match rule that can support both TCP and UDP flows with the same template. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Shahaji Bhosle Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 138 ++- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 21 +- drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 172 +++- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 125 ++- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 801 ++++++++++++++++- .../tf_ulp/ulp_template_db_wh_plus_class.c | 837 ++++++++++++++++-- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 + 7 files changed, 1953 insertions(+), 142 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 73a6a4cdb5..377a78c7e2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -879,6 +879,39 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, return rc; } +static int32_t +ulp_mapper_field_process_inc_dec(struct bnxt_ulp_mapper_field_info *fld, + struct ulp_blob *blob, + uint64_t *val64, + uint16_t const_val16, + uint32_t bitlen, + uint32_t *update_flag) +{ + uint64_t l_val64 = *val64; + + if (fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST || + fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST) { + l_val64 += const_val16; + l_val64 = tfp_be_to_cpu_64(l_val64); + ulp_blob_push_64(blob, &l_val64, bitlen); + } else if (fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST || + fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST_POST) { + l_val64 -= const_val16; + l_val64 = tfp_be_to_cpu_64(l_val64); + ulp_blob_push_64(blob, &l_val64, bitlen); + } else { + BNXT_TF_DBG(ERR, "Invalid field opcode %u\n", fld->field_opc); + return -EINVAL; + } + + if (fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST_POST || + fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST) { + *val64 = l_val64; + *update_flag = 1; + } + return 0; +} + static int32_t ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, enum tf_dir dir, @@ -897,10 +930,24 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, uint32_t src1_sel = 0; enum bnxt_ulp_field_src fld_src; uint8_t *fld_src_oper; + enum bnxt_ulp_field_cond_src field_cond_src; + uint16_t const_val = 0; + uint32_t update_flag = 0; + uint64_t src1_val64; + + /* process the field opcode */ + if (fld->field_opc != BNXT_ULP_FIELD_OPC_COND_OP) { + field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE; + /* Read the constant from the second operand */ + memcpy(&const_val, fld->field_opr2, sizeof(uint16_t)); + const_val = tfp_be_to_cpu_16(const_val); + } else { + field_cond_src = fld->field_cond_src; + } bitlen = fld->field_bit_size; /* Evaluate the condition */ - switch (fld->field_cond_src) { + switch (field_cond_src) { case BNXT_ULP_FIELD_COND_SRC_TRUE: src1_sel = 1; break; @@ -1010,12 +1057,35 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } idx = tfp_be_to_cpu_16(idx); - if (idx < BNXT_ULP_CF_IDX_LAST) + if (idx >= BNXT_ULP_CF_IDX_LAST) { + BNXT_TF_DBG(ERR, "%s comp field [%d] read oob\n", + name, idx); + return -EINVAL; + } + if (fld->field_opc == BNXT_ULP_FIELD_OPC_COND_OP) { val = ulp_blob_push_32(blob, &parms->comp_fld[idx], bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); - return -EINVAL; + if (!val) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", + name); + return -EINVAL; + } + } else { + src1_val64 = ULP_COMP_FLD_IDX_RD(parms, idx); + if (ulp_mapper_field_process_inc_dec(fld, blob, + &src1_val64, + const_val, + bitlen, + &update_flag)) { + BNXT_TF_DBG(ERR, "%s field cond opc failed\n", + name); + return -EINVAL; + } + if (update_flag) { + BNXT_TF_DBG(ERR, "%s invalid field cond opc\n", + name); + return -EINVAL; + } } break; case BNXT_ULP_FIELD_SRC_RF: @@ -1032,11 +1102,33 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, name, idx); return -EINVAL; } - - val = ulp_blob_push_64(blob, ®val, bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); - return -EINVAL; + if (fld->field_opc == BNXT_ULP_FIELD_OPC_COND_OP) { + val = ulp_blob_push_64(blob, ®val, bitlen); + if (!val) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", + name); + return -EINVAL; + } + } else { + if (ulp_mapper_field_process_inc_dec(fld, blob, + ®val, + const_val, + bitlen, + &update_flag)) { + BNXT_TF_DBG(ERR, "%s field cond opc failed\n", + name); + return -EINVAL; + } + if (update_flag) { + regval = tfp_cpu_to_be_64(regval); + if (ulp_regfile_write(parms->regfile, idx, + regval)) { + BNXT_TF_DBG(ERR, + "Write regfile[%d] fail\n", + idx); + return -EINVAL; + } + } } break; case BNXT_ULP_FIELD_SRC_ACT_PROP: @@ -1109,10 +1201,28 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, name, idx); return -EINVAL; } - val = ulp_blob_push_64(blob, ®val, bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); - return -EINVAL; + if (fld->field_opc == BNXT_ULP_FIELD_OPC_COND_OP) { + val = ulp_blob_push_64(blob, ®val, bitlen); + if (!val) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", + name); + return -EINVAL; + } + } else { + if (ulp_mapper_field_process_inc_dec(fld, blob, + ®val, + const_val, + bitlen, + &update_flag)) { + BNXT_TF_DBG(ERR, "%s field cond opc failed\n", + name); + return -EINVAL; + } + if (update_flag) { + BNXT_TF_DBG(ERR, "%s invalid field cond opc\n", + name); + return -EINVAL; + } } break; case BNXT_ULP_FIELD_SRC_HF: diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 02e2b7fdc0..f491405a9e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1176,7 +1176,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; uint32_t size; - uint16_t dst_port = 0; + uint16_t dport = 0, sport = 0; uint32_t cnt; cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT); @@ -1194,12 +1194,12 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], &udp_spec->hdr.src_port, size); - + sport = udp_spec->hdr.src_port; size = sizeof(udp_spec->hdr.dst_port); field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dst_port, size); - dst_port = udp_spec->hdr.dst_port; + dport = udp_spec->hdr.dst_port; size = sizeof(udp_spec->hdr.dgram_len); field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dgram_len, @@ -1232,11 +1232,17 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SPORT, sport); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DPORT, dport); + } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SPORT, sport); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DPORT, dport); + /* Update the field protocol hdr bitmap */ - ulp_rte_l4_proto_type_update(params, dst_port); + ulp_rte_l4_proto_type_update(params, dport); } ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt); return BNXT_TF_RC_SUCCESS; @@ -1252,6 +1258,7 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; + uint16_t dport = 0, sport = 0; uint32_t size; uint32_t cnt; @@ -1266,10 +1273,12 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, * header fields */ if (tcp_spec) { + sport = tcp_spec->hdr.src_port; size = sizeof(tcp_spec->hdr.src_port); field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], &tcp_spec->hdr.src_port, size); + dport = tcp_spec->hdr.dst_port; size = sizeof(tcp_spec->hdr.dst_port); field = ulp_rte_parser_fld_copy(field, &tcp_spec->hdr.dst_port, @@ -1343,9 +1352,13 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SPORT, sport); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DPORT, dport); } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SPORT, sport); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DPORT, dport); } ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt); return BNXT_TF_RC_SUCCESS; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index fa7d67bcd0..483005f2bc 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 1 11:40:24 2020 */ +/* date: Tue Dec 8 14:57:13 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,17 +18,32 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_0000] = 1, [BNXT_ULP_ACT_HID_0001] = 2, [BNXT_ULP_ACT_HID_0400] = 3, - [BNXT_ULP_ACT_HID_0331] = 4, + [BNXT_ULP_ACT_HID_0325] = 4, [BNXT_ULP_ACT_HID_0010] = 5, - [BNXT_ULP_ACT_HID_0731] = 6, - [BNXT_ULP_ACT_HID_0341] = 7, + [BNXT_ULP_ACT_HID_0725] = 6, + [BNXT_ULP_ACT_HID_0335] = 7, [BNXT_ULP_ACT_HID_0002] = 8, [BNXT_ULP_ACT_HID_0003] = 9, [BNXT_ULP_ACT_HID_0402] = 10, - [BNXT_ULP_ACT_HID_0333] = 11, + [BNXT_ULP_ACT_HID_0327] = 11, [BNXT_ULP_ACT_HID_0012] = 12, - [BNXT_ULP_ACT_HID_0733] = 13, - [BNXT_ULP_ACT_HID_0343] = 14 + [BNXT_ULP_ACT_HID_0727] = 13, + [BNXT_ULP_ACT_HID_0337] = 14, + [BNXT_ULP_ACT_HID_01de] = 15, + [BNXT_ULP_ACT_HID_00c6] = 16, + [BNXT_ULP_ACT_HID_0506] = 17, + [BNXT_ULP_ACT_HID_01ed] = 18, + [BNXT_ULP_ACT_HID_03ef] = 19, + [BNXT_ULP_ACT_HID_0516] = 20, + [BNXT_ULP_ACT_HID_01df] = 21, + [BNXT_ULP_ACT_HID_01e4] = 22, + [BNXT_ULP_ACT_HID_00cc] = 23, + [BNXT_ULP_ACT_HID_0504] = 24, + [BNXT_ULP_ACT_HID_01ef] = 25, + [BNXT_ULP_ACT_HID_03ed] = 26, + [BNXT_ULP_ACT_HID_0514] = 27, + [BNXT_ULP_ACT_HID_00db] = 28, + [BNXT_ULP_ACT_HID_00df] = 29 }; /* Array for the act matcher list */ @@ -54,7 +69,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [4] = { - .act_hid = BNXT_ULP_ACT_HID_0331, + .act_hid = BNXT_ULP_ACT_HID_0325, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -68,7 +83,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [6] = { - .act_hid = BNXT_ULP_ACT_HID_0731, + .act_hid = BNXT_ULP_ACT_HID_0725, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -76,7 +91,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [7] = { - .act_hid = BNXT_ULP_ACT_HID_0341, + .act_hid = BNXT_ULP_ACT_HID_0335, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -107,7 +122,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [11] = { - .act_hid = BNXT_ULP_ACT_HID_0333, + .act_hid = BNXT_ULP_ACT_HID_0327, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -123,7 +138,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [13] = { - .act_hid = BNXT_ULP_ACT_HID_0733, + .act_hid = BNXT_ULP_ACT_HID_0727, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -132,12 +147,143 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [14] = { - .act_hid = BNXT_ULP_ACT_HID_0343, + .act_hid = BNXT_ULP_ACT_HID_0337, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 + }, + [15] = { + .act_hid = BNXT_ULP_ACT_HID_01de, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [16] = { + .act_hid = BNXT_ULP_ACT_HID_00c6, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [17] = { + .act_hid = BNXT_ULP_ACT_HID_0506, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [18] = { + .act_hid = BNXT_ULP_ACT_HID_01ed, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [19] = { + .act_hid = BNXT_ULP_ACT_HID_03ef, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [20] = { + .act_hid = BNXT_ULP_ACT_HID_0516, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [21] = { + .act_hid = BNXT_ULP_ACT_HID_01df, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [22] = { + .act_hid = BNXT_ULP_ACT_HID_01e4, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [23] = { + .act_hid = BNXT_ULP_ACT_HID_00cc, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [24] = { + .act_hid = BNXT_ULP_ACT_HID_0504, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [25] = { + .act_hid = BNXT_ULP_ACT_HID_01ef, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [26] = { + .act_hid = BNXT_ULP_ACT_HID_03ed, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [27] = { + .act_hid = BNXT_ULP_ACT_HID_0514, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [28] = { + .act_hid = BNXT_ULP_ACT_HID_00db, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED | + BNXT_ULP_ACT_BIT_SAMPLE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 + }, + [29] = { + .act_hid = BNXT_ULP_ACT_HID_00df, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED | + BNXT_ULP_ACT_BIT_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 0bae79fe03..a38e3de6fa 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Dec 4 18:49:44 2020 */ +/* date: Tue Dec 8 14:57:13 2020 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -20,9 +20,9 @@ #define BNXT_ULP_CLASS_HID_SHFTL 23 #define BNXT_ULP_CLASS_HID_MASK 511 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 15 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 30 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 -#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919 +#define BNXT_ULP_ACT_HID_HIGH_PRIME 6701 #define BNXT_ULP_ACT_HID_SHFTR 24 #define BNXT_ULP_ACT_HID_SHFTL 23 #define BNXT_ULP_ACT_HID_MASK 2047 @@ -43,12 +43,12 @@ #define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10 #define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341 #define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10 -#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 2 -#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 4 -#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 0 -#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 0 -#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 65 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 11 +#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 3 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 11 +#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 +#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 +#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 132 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 13 #define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2 #define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4 #define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0 @@ -145,38 +145,42 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_I_L3 = 14, BNXT_ULP_CF_IDX_O_L4 = 15, BNXT_ULP_CF_IDX_I_L4 = 16, - BNXT_ULP_CF_IDX_DEV_PORT_ID = 17, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 18, - BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 19, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 20, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 21, - BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 22, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 23, - BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 24, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 25, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 26, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 27, - BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 28, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 29, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 30, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 31, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 32, - BNXT_ULP_CF_IDX_ACT_DEC_TTL = 33, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 34, - BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 35, - BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 36, - BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 37, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 38, - BNXT_ULP_CF_IDX_VF_TO_VF = 39, - BNXT_ULP_CF_IDX_L3_HDR_CNT = 40, - BNXT_ULP_CF_IDX_L4_HDR_CNT = 41, - BNXT_ULP_CF_IDX_VFR_MODE = 42, - BNXT_ULP_CF_IDX_L3_TUN = 43, - BNXT_ULP_CF_IDX_L3_TUN_DECAP = 44, - BNXT_ULP_CF_IDX_FID = 45, - BNXT_ULP_CF_IDX_HDR_SIG_ID = 46, - BNXT_ULP_CF_IDX_FLOW_SIG_ID = 47, - BNXT_ULP_CF_IDX_LAST = 48 + BNXT_ULP_CF_IDX_O_L4_SPORT = 17, + BNXT_ULP_CF_IDX_O_L4_DPORT = 18, + BNXT_ULP_CF_IDX_I_L4_SPORT = 19, + BNXT_ULP_CF_IDX_I_L4_DPORT = 20, + BNXT_ULP_CF_IDX_DEV_PORT_ID = 21, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 22, + BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 23, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 24, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 25, + BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 26, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 27, + BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 28, + BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 29, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 30, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 31, + BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 32, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 33, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 34, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 35, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 36, + BNXT_ULP_CF_IDX_ACT_DEC_TTL = 37, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 38, + BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 39, + BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 40, + BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 41, + BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 42, + BNXT_ULP_CF_IDX_VF_TO_VF = 43, + BNXT_ULP_CF_IDX_L3_HDR_CNT = 44, + BNXT_ULP_CF_IDX_L4_HDR_CNT = 45, + BNXT_ULP_CF_IDX_VFR_MODE = 46, + BNXT_ULP_CF_IDX_L3_TUN = 47, + BNXT_ULP_CF_IDX_L3_TUN_DECAP = 48, + BNXT_ULP_CF_IDX_FID = 49, + BNXT_ULP_CF_IDX_HDR_SIG_ID = 50, + BNXT_ULP_CF_IDX_FLOW_SIG_ID = 51, + BNXT_ULP_CF_IDX_LAST = 52 }; enum bnxt_ulp_cond_list_opc { @@ -248,8 +252,16 @@ enum bnxt_ulp_field_cond_src { BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3, BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4, BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5, - BNXT_ULP_FIELD_COND_SRC_SRC1_PLUS_SRC2 = 6, - BNXT_ULP_FIELD_COND_SRC_LAST = 7 + BNXT_ULP_FIELD_COND_SRC_LAST = 6 +}; + +enum bnxt_ulp_field_opc { + BNXT_ULP_FIELD_OPC_COND_OP = 0, + BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST = 1, + BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST = 2, + BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST = 3, + BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST_POST = 4, + BNXT_ULP_FIELD_OPC_LAST = 5 }; enum bnxt_ulp_field_src { @@ -1047,17 +1059,32 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_0000 = 0x0000, BNXT_ULP_ACT_HID_0001 = 0x0001, BNXT_ULP_ACT_HID_0400 = 0x0400, - BNXT_ULP_ACT_HID_0331 = 0x0331, + BNXT_ULP_ACT_HID_0325 = 0x0325, BNXT_ULP_ACT_HID_0010 = 0x0010, - BNXT_ULP_ACT_HID_0731 = 0x0731, - BNXT_ULP_ACT_HID_0341 = 0x0341, + BNXT_ULP_ACT_HID_0725 = 0x0725, + BNXT_ULP_ACT_HID_0335 = 0x0335, BNXT_ULP_ACT_HID_0002 = 0x0002, BNXT_ULP_ACT_HID_0003 = 0x0003, BNXT_ULP_ACT_HID_0402 = 0x0402, - BNXT_ULP_ACT_HID_0333 = 0x0333, + BNXT_ULP_ACT_HID_0327 = 0x0327, BNXT_ULP_ACT_HID_0012 = 0x0012, - BNXT_ULP_ACT_HID_0733 = 0x0733, - BNXT_ULP_ACT_HID_0343 = 0x0343 + BNXT_ULP_ACT_HID_0727 = 0x0727, + BNXT_ULP_ACT_HID_0337 = 0x0337, + BNXT_ULP_ACT_HID_01de = 0x01de, + BNXT_ULP_ACT_HID_00c6 = 0x00c6, + BNXT_ULP_ACT_HID_0506 = 0x0506, + BNXT_ULP_ACT_HID_01ed = 0x01ed, + BNXT_ULP_ACT_HID_03ef = 0x03ef, + BNXT_ULP_ACT_HID_0516 = 0x0516, + BNXT_ULP_ACT_HID_01df = 0x01df, + BNXT_ULP_ACT_HID_01e4 = 0x01e4, + BNXT_ULP_ACT_HID_00cc = 0x00cc, + BNXT_ULP_ACT_HID_0504 = 0x0504, + BNXT_ULP_ACT_HID_01ef = 0x01ef, + BNXT_ULP_ACT_HID_03ed = 0x03ed, + BNXT_ULP_ACT_HID_0514 = 0x0514, + BNXT_ULP_ACT_HID_00db = 0x00db, + BNXT_ULP_ACT_HID_00df = 0x00df }; enum bnxt_ulp_df_tpl { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 78ee8ed6d1..c827be4996 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Dec 7 09:51:03 2020 */ +/* date: Tue Dec 8 14:57:13 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -15,16 +15,47 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { /* act_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 4, + .num_tbls = 5, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, .cond_nums = 9 } + }, + /* act_tid: 2, wh_plus, ingress */ + [2] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 6, + .start_tbl_idx = 5, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 12, + .cond_nums = 0 } } }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { + { /* act_tid: 1, wh_plus, table: shared_mirror_record.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 9, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 0, + .blob_key_bit_size = 1, + .key_bit_size = 1, + .key_num_fields = 1, + .ident_start_idx = 0, + .ident_nums = 1 + }, { /* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -34,7 +65,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 9, + .cond_start_idx = 10, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -43,8 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 0, .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -56,7 +86,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 10, + .cond_start_idx = 11, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -78,7 +108,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -100,7 +130,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -111,6 +141,132 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 + }, + { /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 12, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 65, + .result_bit_size = 32, + .result_num_fields = 6 + }, + { /* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 12, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 71, + .result_bit_size = 64, + .result_num_fields = 1 + }, + { /* act_tid: 2, wh_plus, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 72, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 + }, + { /* act_tid: 2, wh_plus, table: ext_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EXT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 98, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 + }, + { /* act_tid: 2, wh_plus, table: mirror_tbl.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 124, + .result_bit_size = 32, + .result_num_fields = 6 + }, + { /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .key_start_idx = 1, + .blob_key_bit_size = 1, + .key_bit_size = 1, + .key_num_fields = 1, + .result_start_idx = 130, + .result_bit_size = 34, + .result_num_fields = 2 } }; @@ -153,11 +309,64 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { }, { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + } +}; + +struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { + /* act_tid: 1, wh_plus, table: shared_mirror_record.rd */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + } + }, + /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} + } } }; @@ -166,6 +375,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "count", .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -173,30 +383,35 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_tun_type", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -205,12 +420,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_custom_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -235,6 +452,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_de", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -250,6 +468,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "spare", .field_bit_size = 80, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -266,18 +485,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -299,18 +521,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcpflags_key", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -382,18 +607,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -462,6 +690,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -502,12 +731,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "hit", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -524,18 +755,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -557,36 +791,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -649,18 +889,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -729,6 +972,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -755,5 +999,546 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ + { + .description = "act_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "copy", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ign_drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sp_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: int_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: ext_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "flow_cntr_ext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: mirror_tbl.wr */ + { + .description = "act_rec_ptr", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "copy", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ign_drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sp_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FID & 0xff} + }, + { + .description = "mirror_id", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + (1 >> 8) & 0xff, + 1 & 0xff} + } +}; + +struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[] = { + /* act_tid: 1, wh_plus, table: shared_mirror_record.rd */ + { + .description = "mirror_id", + .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0, + .ident_bit_size = 2, + .ident_bit_pos = 32 } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 82cbb9b964..6f5ab14ab1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Dec 7 10:38:39 2020 */ +/* date: Tue Dec 8 14:57:13 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -97,7 +97,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 0, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 0, .ident_nums = 1 }, @@ -156,7 +155,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 13, .result_bit_size = 38, .result_num_fields = 8, - .encap_num_fields = 0, .ident_start_idx = 4, .ident_nums = 1 }, @@ -183,7 +181,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 21, .result_bit_size = 38, .result_num_fields = 8, - .encap_num_fields = 0, .ident_start_idx = 5, .ident_nums = 1 }, @@ -207,8 +204,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 3, .result_start_idx = 29, .result_bit_size = 66, - .result_num_fields = 5, - .encap_num_fields = 0 + .result_num_fields = 5 }, { /* class_tid: 1, wh_plus, table: em.ipv4_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, @@ -230,8 +226,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 10, .result_start_idx = 34, .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 + .result_num_fields = 9 }, { /* class_tid: 1, wh_plus, table: eem.ipv4_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, @@ -253,8 +248,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 10, .result_start_idx = 43, .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 + .result_num_fields = 9 }, { /* class_tid: 1, wh_plus, table: em.ipv6_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, @@ -276,8 +270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 11, .result_start_idx = 52, .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 + .result_num_fields = 9 }, { /* class_tid: 1, wh_plus, table: eem.ipv6_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, @@ -299,8 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 11, .result_start_idx = 61, .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 + .result_num_fields = 9 }, { /* class_tid: 1, wh_plus, table: branch.last */ .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, @@ -359,7 +351,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 96, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 6, .ident_nums = 1 }, @@ -383,8 +374,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 1, .result_start_idx = 109, .result_bit_size = 62, - .result_num_fields = 4, - .encap_num_fields = 0 + .result_num_fields = 4 }, { /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -401,8 +391,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 113, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -419,8 +408,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 114, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -437,8 +425,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 115, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -485,7 +472,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 142, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 7, .ident_nums = 0 }, @@ -533,7 +519,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 155, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 8, .ident_nums = 1 }, @@ -557,8 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 1, .result_start_idx = 168, .result_bit_size = 62, - .result_num_fields = 4, - .encap_num_fields = 0 + .result_num_fields = 4 }, { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -575,8 +559,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 172, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -593,8 +576,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 173, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -611,8 +593,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 174, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, @@ -700,7 +681,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 213, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 10, .ident_nums = 0 }, @@ -724,8 +704,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 1, .result_start_idx = 226, .result_bit_size = 62, - .result_num_fields = 4, - .encap_num_fields = 0 + .result_num_fields = 4 }, { /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -772,7 +751,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 256, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 10, .ident_nums = 0 }, @@ -800,7 +778,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 269, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 10, .ident_nums = 0 }, @@ -826,7 +803,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 282, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 10, .ident_nums = 1 }, @@ -851,8 +827,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_num_fields = 1, .result_start_idx = 295, .result_bit_size = 62, - .result_num_fields = 4, - .encap_num_fields = 0 + .result_num_fields = 4 }, { /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -869,8 +844,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 299, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -887,8 +861,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 300, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, @@ -905,8 +878,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, .result_start_idx = 301, .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .result_num_fields = 1 }, { /* class_tid: 5, wh_plus, table: int_full_act_record.ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -953,7 +925,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_start_idx = 328, .result_bit_size = 64, .result_num_fields = 13, - .encap_num_fields = 0, .ident_start_idx = 11, .ident_nums = 0 }, @@ -1065,12 +1036,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1119,12 +1092,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1133,12 +1108,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1147,12 +1124,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1161,12 +1140,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1175,6 +1156,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1194,12 +1176,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1208,12 +1192,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1222,6 +1208,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1230,6 +1217,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1238,6 +1226,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1246,6 +1235,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1257,6 +1247,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1265,6 +1256,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1273,6 +1265,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1292,6 +1285,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1312,12 +1306,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1326,6 +1322,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1356,6 +1353,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1364,6 +1362,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1372,6 +1371,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1380,6 +1380,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1390,12 +1391,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1404,12 +1407,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1418,12 +1423,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1432,6 +1439,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1440,6 +1448,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1448,6 +1457,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1456,6 +1466,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1464,6 +1475,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1472,6 +1484,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1482,6 +1495,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1490,6 +1504,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1498,6 +1513,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1517,6 +1533,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1525,6 +1542,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1533,6 +1551,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1541,6 +1560,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1549,6 +1569,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1557,6 +1578,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1565,6 +1587,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1573,6 +1596,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1583,12 +1607,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1597,12 +1623,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1611,12 +1639,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1625,6 +1655,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1633,6 +1664,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1641,12 +1673,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1655,12 +1689,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1669,12 +1705,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1683,6 +1721,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1691,6 +1730,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1699,12 +1739,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1713,12 +1755,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1727,12 +1771,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1741,12 +1787,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1755,12 +1803,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1769,6 +1819,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1777,6 +1828,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1785,12 +1837,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1799,12 +1853,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1813,12 +1869,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1827,12 +1885,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1841,6 +1901,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1849,6 +1910,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1857,12 +1919,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1871,12 +1935,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "reserved", .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1885,6 +1951,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1904,12 +1971,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1918,6 +1987,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1926,6 +1996,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1934,12 +2005,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1948,6 +2021,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1956,6 +2030,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1964,6 +2039,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1972,6 +2048,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1983,12 +2060,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1997,6 +2076,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2027,6 +2107,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2035,6 +2116,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2043,6 +2125,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2051,6 +2134,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2061,12 +2145,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2075,12 +2161,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2089,12 +2177,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2103,6 +2193,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2111,6 +2202,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2121,6 +2213,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2129,6 +2222,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2137,6 +2231,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2145,6 +2240,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2155,6 +2251,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2163,6 +2260,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2171,6 +2269,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2190,6 +2289,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2198,6 +2298,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2206,6 +2307,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2214,6 +2316,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2222,6 +2325,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2230,6 +2334,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2238,6 +2343,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2246,6 +2352,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2256,12 +2363,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2270,12 +2379,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2284,12 +2395,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2298,6 +2411,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2306,6 +2420,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2314,12 +2429,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2328,12 +2445,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2342,12 +2461,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2356,6 +2477,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2364,6 +2486,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2372,12 +2495,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2386,12 +2511,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2400,12 +2527,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2414,12 +2543,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2428,12 +2559,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2442,6 +2575,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2450,6 +2584,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2458,12 +2593,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2472,12 +2609,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2486,12 +2625,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2500,12 +2641,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2514,6 +2657,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2522,6 +2666,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2530,12 +2675,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2544,12 +2691,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "reserved", .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2558,6 +2707,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2577,12 +2727,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2591,6 +2743,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2599,6 +2752,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2607,12 +2761,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2621,6 +2777,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2629,6 +2786,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2637,6 +2795,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2645,6 +2804,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2656,6 +2816,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2664,6 +2825,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2672,6 +2834,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2691,6 +2854,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2711,12 +2875,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2725,6 +2891,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2733,6 +2900,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "local_cos", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2741,6 +2909,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2774,6 +2943,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2807,6 +2977,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2877,6 +3048,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2890,6 +3062,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2898,6 +3071,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2918,6 +3092,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2938,12 +3113,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 275, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 275, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2952,6 +3129,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2960,6 +3138,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "local_cos", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -2968,6 +3147,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3001,6 +3181,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3034,6 +3215,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv4.ip_proto", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3104,6 +3286,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3117,6 +3300,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3125,6 +3309,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3145,6 +3330,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3165,12 +3351,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3179,6 +3367,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3187,6 +3376,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "local_cos", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3195,6 +3385,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3228,6 +3419,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3261,6 +3453,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.ip_proto", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3331,6 +3524,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3344,6 +3538,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3352,6 +3547,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3365,6 +3561,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3373,6 +3570,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3393,6 +3591,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3413,12 +3612,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3427,6 +3628,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3435,6 +3637,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "local_cos", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3443,6 +3646,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3476,6 +3680,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3509,6 +3714,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.ip_proto", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3579,6 +3785,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3592,6 +3799,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3600,6 +3808,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3613,6 +3822,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3621,6 +3831,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3641,6 +3852,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3661,12 +3873,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3675,12 +3889,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3689,12 +3905,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3703,6 +3921,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3722,12 +3941,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3736,12 +3957,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3750,12 +3973,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3764,12 +3989,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3778,12 +4005,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3792,12 +4021,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3806,12 +4037,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3820,6 +4053,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3828,6 +4062,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3836,6 +4071,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3844,6 +4080,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3855,6 +4092,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3875,12 +4113,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3889,12 +4129,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3903,12 +4145,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3917,6 +4161,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3936,12 +4181,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3950,12 +4197,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3964,12 +4213,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3978,12 +4229,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -3992,12 +4245,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4006,12 +4261,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4020,12 +4277,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4034,6 +4293,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4042,6 +4302,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4050,6 +4311,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4058,6 +4320,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4069,6 +4332,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4089,12 +4353,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4103,12 +4369,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4117,12 +4385,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4131,6 +4401,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4150,12 +4421,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4164,12 +4437,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4178,12 +4453,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4192,12 +4469,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4206,12 +4485,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4220,12 +4501,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4234,12 +4517,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4248,6 +4533,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4256,6 +4542,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4264,6 +4551,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4272,6 +4560,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4283,6 +4572,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4303,6 +4593,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4323,12 +4614,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4337,12 +4630,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4351,12 +4646,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4365,6 +4662,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4384,12 +4682,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4398,12 +4698,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4412,12 +4714,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4426,12 +4730,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4440,12 +4746,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4454,12 +4762,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4468,12 +4778,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4482,6 +4794,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4490,6 +4803,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4498,6 +4812,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4506,6 +4821,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4517,6 +4833,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4537,12 +4854,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4551,6 +4870,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4571,12 +4891,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4585,6 +4907,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4604,12 +4927,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4618,12 +4943,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4632,12 +4959,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4646,12 +4975,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4660,6 +4991,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4668,6 +5000,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4678,12 +5011,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4692,6 +5027,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4700,6 +5036,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4710,6 +5047,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4718,6 +5056,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4726,6 +5065,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4734,6 +5074,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4745,6 +5086,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4765,12 +5107,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4779,12 +5123,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4793,6 +5139,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4812,12 +5159,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4826,12 +5175,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4840,12 +5191,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4854,12 +5207,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4868,6 +5223,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4876,6 +5232,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4886,12 +5243,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4900,6 +5259,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4908,6 +5268,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4918,6 +5279,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4926,6 +5288,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4934,6 +5297,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4942,6 +5306,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -4953,12 +5318,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4967,12 +5334,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4981,12 +5350,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -4995,6 +5366,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5014,12 +5386,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5028,12 +5402,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5042,12 +5418,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5056,12 +5434,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5070,12 +5450,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5084,12 +5466,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5098,12 +5482,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5112,6 +5498,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5120,6 +5507,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5128,6 +5516,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5136,6 +5525,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5147,6 +5537,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5167,12 +5558,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5181,12 +5574,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5195,12 +5590,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5209,6 +5606,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5228,12 +5626,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5242,12 +5642,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5256,12 +5658,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5270,12 +5674,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5284,12 +5690,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5298,12 +5706,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5312,12 +5722,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5326,6 +5738,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5334,6 +5747,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "key_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -5342,6 +5756,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5350,6 +5765,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5381,6 +5797,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -5396,42 +5813,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5440,12 +5864,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -5453,24 +5879,28 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "wc_key_id", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5480,6 +5910,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5497,6 +5928,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_search_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5505,6 +5937,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pl_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -5512,24 +5945,28 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "wc_key_id", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5539,6 +5976,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5556,6 +5994,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_search_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5564,6 +6003,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pl_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -5598,6 +6038,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "wm_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -5623,36 +6064,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5661,12 +6108,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5685,12 +6134,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5708,6 +6159,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "key_size", .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5717,12 +6169,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5731,12 +6185,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5755,36 +6211,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5793,12 +6255,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5817,12 +6281,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5840,6 +6306,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "key_size", .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5849,12 +6316,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5863,12 +6332,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5878,114 +6349,133 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6001,36 +6491,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6056,6 +6552,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6071,42 +6568,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6115,12 +6619,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6155,6 +6661,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6192,114 +6699,133 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6315,36 +6841,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6352,18 +6884,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_record_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6381,30 +6916,35 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6413,12 +6953,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6427,12 +6969,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6458,6 +7002,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6473,42 +7018,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6517,12 +7069,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6557,6 +7111,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6594,30 +7149,35 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ecv_tun_type", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6626,18 +7186,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ecv_custom_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_tpid", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6656,18 +7219,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vtag_de", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 80, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6675,48 +7241,56 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6732,66 +7306,77 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6801,36 +7386,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6838,18 +7429,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_record_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6858,36 +7452,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6896,12 +7496,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6910,12 +7512,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6941,12 +7545,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_property_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6954,114 +7560,133 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7077,6 +7702,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7085,30 +7711,35 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "meter", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7125,12 +7756,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7139,48 +7772,56 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7189,12 +7830,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7211,12 +7854,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7225,48 +7870,56 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7275,12 +7928,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7306,6 +7961,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7321,42 +7977,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7365,12 +8028,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7405,6 +8070,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7442,114 +8108,133 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7565,36 +8250,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7611,12 +8302,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7625,48 +8318,56 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7675,12 +8376,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -7688,120 +8391,140 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -7811,36 +8534,42 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -7858,18 +8587,18 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ { - .description = "flow_sig_id", - .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 8, - .ident_bit_pos = 58 - }, - { .description = "profile_tcam_index", .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .ident_bit_size = 10, .ident_bit_pos = 32 }, { + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 8, + .ident_bit_pos = 58 + }, + { .description = "em_profile_id", .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, .ident_bit_size = 8, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 16802fb89a..c4ce5e45e3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -255,6 +255,7 @@ struct bnxt_ulp_mapper_tbl_info { struct bnxt_ulp_mapper_field_info { uint8_t description[64]; uint16_t field_bit_size; + enum bnxt_ulp_field_opc field_opc; enum bnxt_ulp_field_cond_src field_cond_src; uint8_t field_cond_opr[16]; enum bnxt_ulp_field_src field_src1; From patchwork Sun May 30 08:59:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93694 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3C1DA0524; Tue, 1 Jun 2021 09:41:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 45C8641124; Tue, 1 Jun 2021 09:40:03 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id BD4A0411DB for ; Sun, 30 May 2021 11:01:35 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 6F6FD7DC2; Sun, 30 May 2021 02:01:32 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 6F6FD7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365295; bh=2cUFGWd9C13UQbiMX2CVU1pkPOotRwJWS8NPctSpimQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NvHKSj5cSNUlSe8GQ1ttuMPZH64xuFVtt/KDLVaUZ1wfPbirCEVgjXsMl1DFR/S2e t8Qv7cSvwALOGnn2ab9edHF+V7q4pIgJG8sZ24mCaow6qd+CZ67n9csU7FvfNf99tN yyzY30rVPYyTe3ljq7de4Rpu1L08oEcZp0mrclQA= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:10 +0530 Message-Id: <20210530085929.29695-40-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:53 +0200 Subject: [dpdk-dev] [PATCH 39/58] net/bnxt: refactor TF ULP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha 1. The flow database opcode is updated to split the alloc push resource item so it can be controlled using the control table. 2. The class and action match signatures are populated with pattern ids that are matched against template pattern id to reject any unsupported class and action combinations. 3. The flow DB opcode should be no op when accessing the global registry identifiers. 4. The resource function for branch is changed to control so that it is extended to perform flow database operations and not just branch operations. 5. The conditional goto processing now supports negative numbers to support looping of the mapper tables to support flow ranges and also enable conditional fail goto to support failure path mapper tables. 6. The field mapper opcode is updated to add all ones to fields that support exact match. 7. Added key info and identifier list to whitney action templates The whitney plus templates are updated to use the mapper infrastructure changes. 8. The partition interface table configuration of the default egress rule for the representor interface needs to use the reserved parif interface that is specific to each platform. The pipeline for the representor interface is broken since incorrect parif configuration cause the miss path packets to be dropped. 9. In the mapper table processing, if a failure condition is hit due to invalid memory type then use the conditional goto failure configuration instead of jumping to next table. This causes ipv6 exact match entry to be skipped. This patch fixes that issue. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Shahaji Bhosle Reviewed-by: Randy Schacher Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 32 +- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 3 + drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 55 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 101 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 7 + drivers/net/bnxt/tf_ulp/ulp_matcher.c | 2 + drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 644 +- .../net/bnxt/tf_ulp/ulp_template_db_class.c | 80798 +++++++++++++++- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 4140 +- .../net/bnxt/tf_ulp/ulp_template_db_field.h | 558 +- .../tf_ulp/ulp_template_db_stingray_act.c | 16 +- .../tf_ulp/ulp_template_db_stingray_class.c | 154 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 512 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h | 4 + .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 4470 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 13072 ++- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 7 +- 17 files changed, 98371 insertions(+), 6204 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 1655b0f29a..0af2f6aaa6 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -79,21 +79,23 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, struct ulp_rte_parser_params *params, enum bnxt_ulp_fdb_type flow_type) { - mapper_cparms->flow_type = flow_type; - mapper_cparms->app_priority = params->priority; - mapper_cparms->dir_attr = params->dir_attr; - mapper_cparms->class_tid = params->class_id; - mapper_cparms->act_tid = params->act_tmpl; - mapper_cparms->func_id = params->func_id; - mapper_cparms->hdr_bitmap = ¶ms->hdr_bitmap; - mapper_cparms->hdr_field = params->hdr_field; - mapper_cparms->comp_fld = params->comp_fld; - mapper_cparms->act = ¶ms->act_bitmap; - mapper_cparms->act_prop = ¶ms->act_prop; - mapper_cparms->flow_id = params->fid; - mapper_cparms->parent_flow = params->parent_flow; - mapper_cparms->parent_fid = params->parent_fid; - mapper_cparms->fld_bitmap = ¶ms->fld_bitmap; + mapper_cparms->flow_type = flow_type; + mapper_cparms->app_priority = params->priority; + mapper_cparms->dir_attr = params->dir_attr; + mapper_cparms->class_tid = params->class_id; + mapper_cparms->act_tid = params->act_tmpl; + mapper_cparms->func_id = params->func_id; + mapper_cparms->hdr_bitmap = ¶ms->hdr_bitmap; + mapper_cparms->hdr_field = params->hdr_field; + mapper_cparms->comp_fld = params->comp_fld; + mapper_cparms->act = ¶ms->act_bitmap; + mapper_cparms->act_prop = ¶ms->act_prop; + mapper_cparms->flow_id = params->fid; + mapper_cparms->parent_flow = params->parent_flow; + mapper_cparms->parent_fid = params->parent_fid; + mapper_cparms->fld_bitmap = ¶ms->fld_bitmap; + mapper_cparms->flow_pattern_id = params->flow_pattern_id; + mapper_cparms->act_pattern_id = params->act_pattern_id; /* update the signature fields into the computed field list */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID, diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index 6d6c22b157..ce8bfdc61f 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -360,6 +360,9 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, goto err1; } + BNXT_TF_DBG(DEBUG, "Creating default flow with template id: %u\n", + ulp_class_tid); + /* Protect flow creation */ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 96398d8a01..1326f79ff5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -48,21 +48,17 @@ ulp_flow_db_active_flows_bit_set(struct bnxt_ulp_flow_db *flow_db, uint32_t a_idx = idx / ULP_INDEX_BITMAP_SIZE; if (flag) { - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type == - BNXT_ULP_FDB_TYPE_RID) + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) ULP_INDEX_BITMAP_SET(f_tbl->active_reg_flows[a_idx], idx); - if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type == - BNXT_ULP_FDB_TYPE_RID) + else ULP_INDEX_BITMAP_SET(f_tbl->active_dflt_flows[a_idx], idx); } else { - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type == - BNXT_ULP_FDB_TYPE_RID) + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) ULP_INDEX_BITMAP_RESET(f_tbl->active_reg_flows[a_idx], idx); - if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type == - BNXT_ULP_FDB_TYPE_RID) + else ULP_INDEX_BITMAP_RESET(f_tbl->active_dflt_flows[a_idx], idx); } @@ -89,15 +85,9 @@ ulp_flow_db_active_flows_bit_is_set(struct bnxt_ulp_flow_db *flow_db, if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) return ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx], idx); - else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT) + else return ULP_INDEX_BITMAP_GET(f_tbl->active_dflt_flows[a_idx], idx); - else if (flow_type == BNXT_ULP_FDB_TYPE_RID) - return (ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx], - idx) && - ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx], - idx)); - return 0; } static inline enum tf_dir @@ -223,7 +213,7 @@ ulp_flow_db_alloc_resource(struct bnxt_ulp_flow_db *flow_db) return -ENOMEM; } size = (flow_tbl->num_flows / sizeof(uint64_t)) + 1; - size = ULP_BYTE_ROUND_OFF_8(size); + size = ULP_BYTE_ROUND_OFF_8(size); flow_tbl->active_reg_flows = rte_zmalloc("active reg flows", size, ULP_BUFFER_ALIGN_64_BYTE); if (!flow_tbl->active_reg_flows) { @@ -627,7 +617,7 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { + if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -684,7 +674,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { + if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -698,7 +688,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); + BNXT_TF_DBG(ERR, "flow does not exist\n"); return -EINVAL; } @@ -779,7 +769,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { + if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -793,7 +783,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); + BNXT_TF_DBG(ERR, "flow does not exist\n"); return -EINVAL; } @@ -887,7 +877,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { + if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -902,7 +892,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); + BNXT_TF_DBG(ERR, "flow does not exist\n"); return -EINVAL; } flow_tbl->head_index--; @@ -910,7 +900,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, BNXT_TF_DBG(ERR, "FlowDB: Head Ptr is zero\n"); return -ENOENT; } - flow_tbl->flow_tbl_stack[flow_tbl->head_index] = fid; /* Clear the flows bitmap */ @@ -924,7 +913,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, } /* - *Get the flow database entry details + * Get the flow database entry details * * ulp_ctxt [in] Ptr to ulp_context * flow_type [in] - specify default or regular @@ -951,7 +940,7 @@ ulp_flow_db_resource_get(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { + if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -1007,14 +996,10 @@ ulp_flow_db_next_entry_get(struct bnxt_ulp_flow_db *flow_db, uint64_t *active_flows; struct bnxt_ulp_flow_tbl *flowtbl = &flow_db->flow_tbl; - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) { + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) active_flows = flowtbl->active_reg_flows; - } else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT) { + else active_flows = flowtbl->active_dflt_flows; - } else { - BNXT_TF_DBG(ERR, "Invalid flow type %x\n", flow_type); - return -EINVAL; - } do { /* increment the flow id to find the next valid flow id */ @@ -1207,7 +1192,7 @@ ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } - if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { + if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -1609,7 +1594,7 @@ ulp_flow_db_child_flow_reset(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { + if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 377a78c7e2..c2e36823bf 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -19,6 +19,11 @@ #include "tf_util.h" #include "ulp_template_db_tbl.h" +static uint8_t mapper_fld_ones[16] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +}; + static const char * ulp_mapper_tmpl_name_str(enum bnxt_ulp_template_type tmpl_type) { @@ -591,12 +596,11 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms, int32_t rc = 0; switch (tbl->fdb_opcode) { - case BNXT_ULP_FDB_OPC_PUSH: + case BNXT_ULP_FDB_OPC_PUSH_FID: push_fid = parms->fid; flow_type = parms->flow_type; break; - case BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE: - case BNXT_ULP_FDB_OPC_PUSH_REGFILE: + case BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE: /* get the fid from the regfile */ rc = ulp_regfile_read(parms->regfile, tbl->fdb_operand, &val64); @@ -1049,6 +1053,13 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } break; + case BNXT_ULP_FIELD_SRC_ONES: + val = mapper_fld_ones; + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s too large for blob\n", name); + return -EINVAL; + } + break; case BNXT_ULP_FIELD_SRC_CF: if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx, sizeof(uint16_t))) { @@ -2076,6 +2087,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, write = true; break; case BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE: + if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) { + BNXT_TF_DBG(ERR, "Template error, wrong fdb opcode\n"); + return -EINVAL; + } /* * get the index to write to from the global regfile and then * write the table. @@ -2470,8 +2485,10 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, "Failed to scan ident list\n"); return -EINVAL; } - /* increment the reference count */ - ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent); + if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) { + /* increment the reference count */ + ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent); + } /* it is a hit */ gen_tbl_hit = 1; @@ -2545,6 +2562,23 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } +static int32_t +ulp_mapper_ctrl_tbl_process(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl) +{ + int32_t rc = 0; + + /* process the fdb opcode for alloc push */ + if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE) { + rc = ulp_mapper_fdb_opc_alloc_rid(parms, tbl); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to do fdb alloc\n"); + return rc; + } + } + return rc; +} + static int32_t ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_mapper_data *mapper_data) @@ -2598,7 +2632,10 @@ ulp_mapper_tbl_memtype_opcode_process(struct bnxt_ulp_mapper_parms *parms, enum bnxt_ulp_flow_mem_type mtype = BNXT_ULP_FLOW_MEM_TYPE_INT; int32_t rc = 1; - bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype); + if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) { + BNXT_TF_DBG(ERR, "Failed to get the mem type\n"); + return rc; + } switch (tbl->mem_type_opcode) { case BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT: @@ -2725,6 +2762,20 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, } *res = regval == 0; break; + case BNXT_ULP_COND_OPC_FLOW_PAT_MATCH: + if (parms->flow_pattern_id == operand) { + BNXT_TF_DBG(ERR, "field pattern match failed %x\n", + parms->flow_pattern_id); + return -EINVAL; + } + break; + case BNXT_ULP_COND_OPC_ACT_PAT_MATCH: + if (parms->act_pattern_id == operand) { + BNXT_TF_DBG(ERR, "act pattern match failed %x\n", + parms->act_pattern_id); + return -EINVAL; + } + break; default: BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc); rc = -EINVAL; @@ -2748,7 +2799,7 @@ ulp_mapper_cond_opc_list_process(struct bnxt_ulp_mapper_parms *parms, int32_t *res) { uint32_t i; - int32_t rc = 0, trc; + int32_t rc = 0, trc = 0; switch (list_opc) { case BNXT_ULP_COND_LIST_OPC_AND: @@ -2870,7 +2921,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) struct bnxt_ulp_mapper_tbl_info *tbl; uint32_t num_tbls, tbl_idx, num_cond_tbls; int32_t rc = -EINVAL, cond_rc = 0; - uint32_t cond_goto = 1; + int32_t cond_goto = 1; cond_tbls = ulp_mapper_tmpl_reject_list_get(parms, tid, &num_cond_tbls, @@ -2907,11 +2958,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) { tbl = &tbls[tbl_idx]; - cond_goto = tbl->execute_info.cond_goto; /* Handle the table level opcodes to determine if required. */ if (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) { - tbl_idx += 1; - continue; + cond_goto = tbl->execute_info.cond_false_goto; + goto next_iteration; } cond_tbls = ulp_mapper_tbl_execute_list_get(parms, tbl, @@ -2927,17 +2977,8 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) } /* Skip the table if False */ if (!cond_rc) { - tbl_idx += 1; - continue; - } - - /* process the fdb opcode for alloc push */ - if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE) { - rc = ulp_mapper_fdb_opc_alloc_rid(parms, tbl); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to do fdb alloc\n"); - return rc; - } + cond_goto = tbl->execute_info.cond_false_goto; + goto next_iteration; } switch (tbl->resource_func) { @@ -2957,8 +2998,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) case BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE: rc = ulp_mapper_gen_tbl_process(parms, tbl); break; + case BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE: + rc = ulp_mapper_ctrl_tbl_process(parms, tbl); + break; case BNXT_ULP_RESOURCE_FUNC_INVALID: - case BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE: rc = 0; break; default: @@ -2982,6 +3025,12 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) rc = -EINVAL; goto error; } +next_iteration: + if (cond_goto < 0 && ((int32_t)tbl_idx + cond_goto) < 0) { + BNXT_TF_DBG(ERR, "invalid conditional goto %d\n", + cond_goto); + goto error; + } tbl_idx += cond_goto; } @@ -3062,7 +3111,9 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx, * Set the critical resource on the first resource del, then iterate * while status is good */ - res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES; + if (flow_type != BNXT_ULP_FDB_TYPE_RID) + res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES; + rc = ulp_flow_db_resource_del(ulp_ctx, flow_type, fid, &res_parms); if (rc) { @@ -3236,6 +3287,8 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, parms.fid = cparms->flow_id; parms.tun_idx = cparms->tun_idx; parms.app_priority = cparms->app_priority; + parms.flow_pattern_id = cparms->flow_pattern_id; + parms.act_pattern_id = cparms->act_pattern_id; /* Get the device id from the ulp context */ if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index b7399b8949..8f0b894d39 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -58,6 +58,8 @@ struct bnxt_ulp_mapper_parms { uint8_t tun_idx; uint32_t app_priority; uint64_t shared_hndl; + uint32_t flow_pattern_id; + uint32_t act_pattern_id; }; struct bnxt_ulp_mapper_create_parms { @@ -80,6 +82,11 @@ struct bnxt_ulp_mapper_create_parms { /* if set then create a parent flow */ uint32_t parent_flow; uint8_t tun_idx; + + /* support pattern based rejection */ + uint32_t flow_pattern_id; + uint32_t act_pattern_id; + }; /* Function to initialize any dynamic mapper data. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c index 6e2506cfa3..21eb97b7eb 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c @@ -79,6 +79,7 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params, *class_id = class_match->class_tid; params->hdr_sig_id = class_match->hdr_sig_id; params->flow_sig_id = class_match->flow_sig_id; + params->flow_pattern_id = class_match->flow_pattern_id; return BNXT_TF_RC_SUCCESS; error: @@ -115,6 +116,7 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params, goto error; } *act_id = act_match->act_tid; + params->act_pattern_id = act_match->act_pattern_id; BNXT_TF_DBG(DEBUG, "Found matching action template %u\n", *act_id); return BNXT_TF_RC_SUCCESS; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index 483005f2bc..8e482700e9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 8 14:57:13 2020 */ +/* date: Thu Dec 17 19:43:07 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,32 +18,88 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_0000] = 1, [BNXT_ULP_ACT_HID_0001] = 2, [BNXT_ULP_ACT_HID_0400] = 3, - [BNXT_ULP_ACT_HID_0325] = 4, + [BNXT_ULP_ACT_HID_01ab] = 4, [BNXT_ULP_ACT_HID_0010] = 5, - [BNXT_ULP_ACT_HID_0725] = 6, - [BNXT_ULP_ACT_HID_0335] = 7, + [BNXT_ULP_ACT_HID_05ab] = 6, + [BNXT_ULP_ACT_HID_01bb] = 7, [BNXT_ULP_ACT_HID_0002] = 8, [BNXT_ULP_ACT_HID_0003] = 9, [BNXT_ULP_ACT_HID_0402] = 10, - [BNXT_ULP_ACT_HID_0327] = 11, + [BNXT_ULP_ACT_HID_01ad] = 11, [BNXT_ULP_ACT_HID_0012] = 12, - [BNXT_ULP_ACT_HID_0727] = 13, - [BNXT_ULP_ACT_HID_0337] = 14, - [BNXT_ULP_ACT_HID_01de] = 15, - [BNXT_ULP_ACT_HID_00c6] = 16, - [BNXT_ULP_ACT_HID_0506] = 17, - [BNXT_ULP_ACT_HID_01ed] = 18, - [BNXT_ULP_ACT_HID_03ef] = 19, - [BNXT_ULP_ACT_HID_0516] = 20, - [BNXT_ULP_ACT_HID_01df] = 21, - [BNXT_ULP_ACT_HID_01e4] = 22, - [BNXT_ULP_ACT_HID_00cc] = 23, - [BNXT_ULP_ACT_HID_0504] = 24, - [BNXT_ULP_ACT_HID_01ef] = 25, - [BNXT_ULP_ACT_HID_03ed] = 26, - [BNXT_ULP_ACT_HID_0514] = 27, - [BNXT_ULP_ACT_HID_00db] = 28, - [BNXT_ULP_ACT_HID_00df] = 29 + [BNXT_ULP_ACT_HID_05ad] = 13, + [BNXT_ULP_ACT_HID_01bd] = 14, + [BNXT_ULP_ACT_HID_0613] = 15, + [BNXT_ULP_ACT_HID_02a9] = 16, + [BNXT_ULP_ACT_HID_0054] = 17, + [BNXT_ULP_ACT_HID_0622] = 18, + [BNXT_ULP_ACT_HID_0454] = 19, + [BNXT_ULP_ACT_HID_0064] = 20, + [BNXT_ULP_ACT_HID_0614] = 21, + [BNXT_ULP_ACT_HID_0615] = 22, + [BNXT_ULP_ACT_HID_02ab] = 23, + [BNXT_ULP_ACT_HID_0056] = 24, + [BNXT_ULP_ACT_HID_0624] = 25, + [BNXT_ULP_ACT_HID_0456] = 26, + [BNXT_ULP_ACT_HID_0066] = 27, + [BNXT_ULP_ACT_HID_048d] = 28, + [BNXT_ULP_ACT_HID_048f] = 29, + [BNXT_ULP_ACT_HID_04bc] = 30, + [BNXT_ULP_ACT_HID_00a9] = 31, + [BNXT_ULP_ACT_HID_020f] = 32, + [BNXT_ULP_ACT_HID_04a9] = 33, + [BNXT_ULP_ACT_HID_01fc] = 34, + [BNXT_ULP_ACT_HID_04be] = 35, + [BNXT_ULP_ACT_HID_00ab] = 36, + [BNXT_ULP_ACT_HID_0211] = 37, + [BNXT_ULP_ACT_HID_04ab] = 38, + [BNXT_ULP_ACT_HID_01fe] = 39, + [BNXT_ULP_ACT_HID_0667] = 40, + [BNXT_ULP_ACT_HID_0254] = 41, + [BNXT_ULP_ACT_HID_03ba] = 42, + [BNXT_ULP_ACT_HID_0654] = 43, + [BNXT_ULP_ACT_HID_03a7] = 44, + [BNXT_ULP_ACT_HID_0669] = 45, + [BNXT_ULP_ACT_HID_0256] = 46, + [BNXT_ULP_ACT_HID_03bc] = 47, + [BNXT_ULP_ACT_HID_0656] = 48, + [BNXT_ULP_ACT_HID_03a9] = 49, + [BNXT_ULP_ACT_HID_021b] = 50, + [BNXT_ULP_ACT_HID_021c] = 51, + [BNXT_ULP_ACT_HID_021e] = 52, + [BNXT_ULP_ACT_HID_063f] = 53, + [BNXT_ULP_ACT_HID_0510] = 54, + [BNXT_ULP_ACT_HID_03c6] = 55, + [BNXT_ULP_ACT_HID_0082] = 56, + [BNXT_ULP_ACT_HID_06bb] = 57, + [BNXT_ULP_ACT_HID_021d] = 58, + [BNXT_ULP_ACT_HID_0641] = 59, + [BNXT_ULP_ACT_HID_0512] = 60, + [BNXT_ULP_ACT_HID_03c8] = 61, + [BNXT_ULP_ACT_HID_0084] = 62, + [BNXT_ULP_ACT_HID_06bd] = 63, + [BNXT_ULP_ACT_HID_06d7] = 64, + [BNXT_ULP_ACT_HID_02c4] = 65, + [BNXT_ULP_ACT_HID_042a] = 66, + [BNXT_ULP_ACT_HID_06c4] = 67, + [BNXT_ULP_ACT_HID_0417] = 68, + [BNXT_ULP_ACT_HID_06d9] = 69, + [BNXT_ULP_ACT_HID_02c6] = 70, + [BNXT_ULP_ACT_HID_042c] = 71, + [BNXT_ULP_ACT_HID_06c6] = 72, + [BNXT_ULP_ACT_HID_0419] = 73, + [BNXT_ULP_ACT_HID_0119] = 74, + [BNXT_ULP_ACT_HID_046f] = 75, + [BNXT_ULP_ACT_HID_05d5] = 76, + [BNXT_ULP_ACT_HID_0106] = 77, + [BNXT_ULP_ACT_HID_05c2] = 78, + [BNXT_ULP_ACT_HID_011b] = 79, + [BNXT_ULP_ACT_HID_0471] = 80, + [BNXT_ULP_ACT_HID_05d7] = 81, + [BNXT_ULP_ACT_HID_0108] = 82, + [BNXT_ULP_ACT_HID_05c4] = 83, + [BNXT_ULP_ACT_HID_00a2] = 84, + [BNXT_ULP_ACT_HID_00a4] = 85 }; /* Array for the act matcher list */ @@ -69,7 +125,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [4] = { - .act_hid = BNXT_ULP_ACT_HID_0325, + .act_hid = BNXT_ULP_ACT_HID_01ab, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -83,7 +139,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [6] = { - .act_hid = BNXT_ULP_ACT_HID_0725, + .act_hid = BNXT_ULP_ACT_HID_05ab, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -91,7 +147,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [7] = { - .act_hid = BNXT_ULP_ACT_HID_0335, + .act_hid = BNXT_ULP_ACT_HID_01bb, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -122,7 +178,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [11] = { - .act_hid = BNXT_ULP_ACT_HID_0327, + .act_hid = BNXT_ULP_ACT_HID_01ad, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -138,7 +194,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [13] = { - .act_hid = BNXT_ULP_ACT_HID_0727, + .act_hid = BNXT_ULP_ACT_HID_05ad, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -147,7 +203,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [14] = { - .act_hid = BNXT_ULP_ACT_HID_0337, + .act_hid = BNXT_ULP_ACT_HID_01bd, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -156,7 +212,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [15] = { - .act_hid = BNXT_ULP_ACT_HID_01de, + .act_hid = BNXT_ULP_ACT_HID_0613, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DROP | @@ -164,7 +220,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [16] = { - .act_hid = BNXT_ULP_ACT_HID_00c6, + .act_hid = BNXT_ULP_ACT_HID_02a9, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -172,7 +228,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [17] = { - .act_hid = BNXT_ULP_ACT_HID_0506, + .act_hid = BNXT_ULP_ACT_HID_0054, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -180,7 +236,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [18] = { - .act_hid = BNXT_ULP_ACT_HID_01ed, + .act_hid = BNXT_ULP_ACT_HID_0622, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -188,7 +244,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [19] = { - .act_hid = BNXT_ULP_ACT_HID_03ef, + .act_hid = BNXT_ULP_ACT_HID_0454, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -197,7 +253,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [20] = { - .act_hid = BNXT_ULP_ACT_HID_0516, + .act_hid = BNXT_ULP_ACT_HID_0064, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -206,7 +262,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [21] = { - .act_hid = BNXT_ULP_ACT_HID_01df, + .act_hid = BNXT_ULP_ACT_HID_0614, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -214,7 +270,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [22] = { - .act_hid = BNXT_ULP_ACT_HID_01e4, + .act_hid = BNXT_ULP_ACT_HID_0615, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -223,7 +279,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [23] = { - .act_hid = BNXT_ULP_ACT_HID_00cc, + .act_hid = BNXT_ULP_ACT_HID_02ab, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -232,7 +288,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [24] = { - .act_hid = BNXT_ULP_ACT_HID_0504, + .act_hid = BNXT_ULP_ACT_HID_0056, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -241,7 +297,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [25] = { - .act_hid = BNXT_ULP_ACT_HID_01ef, + .act_hid = BNXT_ULP_ACT_HID_0624, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -250,7 +306,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [26] = { - .act_hid = BNXT_ULP_ACT_HID_03ed, + .act_hid = BNXT_ULP_ACT_HID_0456, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -260,7 +316,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [27] = { - .act_hid = BNXT_ULP_ACT_HID_0514, + .act_hid = BNXT_ULP_ACT_HID_0066, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -270,7 +326,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [28] = { - .act_hid = BNXT_ULP_ACT_HID_00db, + .act_hid = BNXT_ULP_ACT_HID_048d, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED | BNXT_ULP_ACT_BIT_SAMPLE | @@ -278,12 +334,514 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 2 }, [29] = { - .act_hid = BNXT_ULP_ACT_HID_00df, + .act_hid = BNXT_ULP_ACT_HID_048f, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED | BNXT_ULP_ACT_BIT_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 + }, + [30] = { + .act_hid = BNXT_ULP_ACT_HID_04bc, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [31] = { + .act_hid = BNXT_ULP_ACT_HID_00a9, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [32] = { + .act_hid = BNXT_ULP_ACT_HID_020f, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [33] = { + .act_hid = BNXT_ULP_ACT_HID_04a9, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [34] = { + .act_hid = BNXT_ULP_ACT_HID_01fc, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [35] = { + .act_hid = BNXT_ULP_ACT_HID_04be, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [36] = { + .act_hid = BNXT_ULP_ACT_HID_00ab, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [37] = { + .act_hid = BNXT_ULP_ACT_HID_0211, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [38] = { + .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [39] = { + .act_hid = BNXT_ULP_ACT_HID_01fe, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [40] = { + .act_hid = BNXT_ULP_ACT_HID_0667, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [41] = { + .act_hid = BNXT_ULP_ACT_HID_0254, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [42] = { + .act_hid = BNXT_ULP_ACT_HID_03ba, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [43] = { + .act_hid = BNXT_ULP_ACT_HID_0654, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [44] = { + .act_hid = BNXT_ULP_ACT_HID_03a7, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [45] = { + .act_hid = BNXT_ULP_ACT_HID_0669, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [46] = { + .act_hid = BNXT_ULP_ACT_HID_0256, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [47] = { + .act_hid = BNXT_ULP_ACT_HID_03bc, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [48] = { + .act_hid = BNXT_ULP_ACT_HID_0656, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [49] = { + .act_hid = BNXT_ULP_ACT_HID_03a9, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [50] = { + .act_hid = BNXT_ULP_ACT_HID_021b, + .act_sig = { .bits = + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [51] = { + .act_hid = BNXT_ULP_ACT_HID_021c, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [52] = { + .act_hid = BNXT_ULP_ACT_HID_021e, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [53] = { + .act_hid = BNXT_ULP_ACT_HID_063f, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [54] = { + .act_hid = BNXT_ULP_ACT_HID_0510, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [55] = { + .act_hid = BNXT_ULP_ACT_HID_03c6, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [56] = { + .act_hid = BNXT_ULP_ACT_HID_0082, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [57] = { + .act_hid = BNXT_ULP_ACT_HID_06bb, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [58] = { + .act_hid = BNXT_ULP_ACT_HID_021d, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [59] = { + .act_hid = BNXT_ULP_ACT_HID_0641, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [60] = { + .act_hid = BNXT_ULP_ACT_HID_0512, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [61] = { + .act_hid = BNXT_ULP_ACT_HID_03c8, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [62] = { + .act_hid = BNXT_ULP_ACT_HID_0084, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [63] = { + .act_hid = BNXT_ULP_ACT_HID_06bd, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [64] = { + .act_hid = BNXT_ULP_ACT_HID_06d7, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [65] = { + .act_hid = BNXT_ULP_ACT_HID_02c4, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [66] = { + .act_hid = BNXT_ULP_ACT_HID_042a, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [67] = { + .act_hid = BNXT_ULP_ACT_HID_06c4, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [68] = { + .act_hid = BNXT_ULP_ACT_HID_0417, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [69] = { + .act_hid = BNXT_ULP_ACT_HID_06d9, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [70] = { + .act_hid = BNXT_ULP_ACT_HID_02c6, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_042c, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_06c6, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [73] = { + .act_hid = BNXT_ULP_ACT_HID_0419, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [74] = { + .act_hid = BNXT_ULP_ACT_HID_0119, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [75] = { + .act_hid = BNXT_ULP_ACT_HID_046f, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [76] = { + .act_hid = BNXT_ULP_ACT_HID_05d5, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [77] = { + .act_hid = BNXT_ULP_ACT_HID_0106, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [78] = { + .act_hid = BNXT_ULP_ACT_HID_05c2, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [79] = { + .act_hid = BNXT_ULP_ACT_HID_011b, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [80] = { + .act_hid = BNXT_ULP_ACT_HID_0471, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [81] = { + .act_hid = BNXT_ULP_ACT_HID_05d7, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [82] = { + .act_hid = BNXT_ULP_ACT_HID_0108, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [83] = { + .act_hid = BNXT_ULP_ACT_HID_05c4, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [84] = { + .act_hid = BNXT_ULP_ACT_HID_00a2, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [85] = { + .act_hid = BNXT_ULP_ACT_HID_00a4, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index 3197ed2072..0ca0d2b366 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Dec 7 09:51:03 2020 */ +/* date: Wed Dec 16 16:37:41 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -16,1736 +16,80484 @@ * maps hash id to ulp_class_match_list[] index */ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_005c] = 1, - [BNXT_ULP_CLASS_HID_0003] = 2, - [BNXT_ULP_CLASS_HID_0132] = 3, - [BNXT_ULP_CLASS_HID_00e1] = 4, - [BNXT_ULP_CLASS_HID_0044] = 5, - [BNXT_ULP_CLASS_HID_001b] = 6, - [BNXT_ULP_CLASS_HID_012a] = 7, - [BNXT_ULP_CLASS_HID_00f9] = 8, - [BNXT_ULP_CLASS_HID_018d] = 9, - [BNXT_ULP_CLASS_HID_00a7] = 10, - [BNXT_ULP_CLASS_HID_006f] = 11, - [BNXT_ULP_CLASS_HID_0181] = 12, - [BNXT_ULP_CLASS_HID_0195] = 13, - [BNXT_ULP_CLASS_HID_00bf] = 14, - [BNXT_ULP_CLASS_HID_0077] = 15, - [BNXT_ULP_CLASS_HID_0199] = 16, - [BNXT_ULP_CLASS_HID_009a] = 17, - [BNXT_ULP_CLASS_HID_0192] = 18, - [BNXT_ULP_CLASS_HID_01e2] = 19, - [BNXT_ULP_CLASS_HID_00fa] = 20, - [BNXT_ULP_CLASS_HID_0165] = 21, - [BNXT_ULP_CLASS_HID_0042] = 22, - [BNXT_ULP_CLASS_HID_00cd] = 23, - [BNXT_ULP_CLASS_HID_01aa] = 24, - [BNXT_ULP_CLASS_HID_0178] = 25, - [BNXT_ULP_CLASS_HID_0070] = 26, - [BNXT_ULP_CLASS_HID_00f3] = 27, - [BNXT_ULP_CLASS_HID_01d8] = 28, - [BNXT_ULP_CLASS_HID_005b] = 29, - [BNXT_ULP_CLASS_HID_0153] = 30, - [BNXT_ULP_CLASS_HID_01a3] = 31, - [BNXT_ULP_CLASS_HID_00bb] = 32, - [BNXT_ULP_CLASS_HID_0082] = 33, - [BNXT_ULP_CLASS_HID_018a] = 34, - [BNXT_ULP_CLASS_HID_01fa] = 35, - [BNXT_ULP_CLASS_HID_00e2] = 36, - [BNXT_ULP_CLASS_HID_017d] = 37, - [BNXT_ULP_CLASS_HID_005a] = 38, - [BNXT_ULP_CLASS_HID_00d5] = 39, - [BNXT_ULP_CLASS_HID_01b2] = 40, - [BNXT_ULP_CLASS_HID_0160] = 41, - [BNXT_ULP_CLASS_HID_0068] = 42, - [BNXT_ULP_CLASS_HID_00eb] = 43, - [BNXT_ULP_CLASS_HID_01c0] = 44, - [BNXT_ULP_CLASS_HID_0043] = 45, - [BNXT_ULP_CLASS_HID_014b] = 46, - [BNXT_ULP_CLASS_HID_01bb] = 47, - [BNXT_ULP_CLASS_HID_00a3] = 48, - [BNXT_ULP_CLASS_HID_00cb] = 49, - [BNXT_ULP_CLASS_HID_00b4] = 50, - [BNXT_ULP_CLASS_HID_0013] = 51, - [BNXT_ULP_CLASS_HID_001c] = 52, - [BNXT_ULP_CLASS_HID_017b] = 53, - [BNXT_ULP_CLASS_HID_0164] = 54, - [BNXT_ULP_CLASS_HID_00c3] = 55, - [BNXT_ULP_CLASS_HID_00cc] = 56, - [BNXT_ULP_CLASS_HID_01a5] = 57, - [BNXT_ULP_CLASS_HID_0196] = 58, - [BNXT_ULP_CLASS_HID_010d] = 59, - [BNXT_ULP_CLASS_HID_00fe] = 60, - [BNXT_ULP_CLASS_HID_0084] = 61, - [BNXT_ULP_CLASS_HID_0046] = 62, - [BNXT_ULP_CLASS_HID_01ec] = 63, - [BNXT_ULP_CLASS_HID_01ae] = 64, - [BNXT_ULP_CLASS_HID_00d3] = 65, - [BNXT_ULP_CLASS_HID_00ac] = 66, - [BNXT_ULP_CLASS_HID_000b] = 67, - [BNXT_ULP_CLASS_HID_0004] = 68, - [BNXT_ULP_CLASS_HID_0163] = 69, - [BNXT_ULP_CLASS_HID_017c] = 70, - [BNXT_ULP_CLASS_HID_00db] = 71, - [BNXT_ULP_CLASS_HID_00d4] = 72, - [BNXT_ULP_CLASS_HID_01bd] = 73, - [BNXT_ULP_CLASS_HID_018e] = 74, - [BNXT_ULP_CLASS_HID_0115] = 75, - [BNXT_ULP_CLASS_HID_00e6] = 76, - [BNXT_ULP_CLASS_HID_009c] = 77, - [BNXT_ULP_CLASS_HID_005e] = 78, - [BNXT_ULP_CLASS_HID_01f4] = 79, - [BNXT_ULP_CLASS_HID_01b6] = 80 + [BNXT_ULP_CLASS_HID_26d1] = 1, + [BNXT_ULP_CLASS_HID_0071] = 2, + [BNXT_ULP_CLASS_HID_53a5] = 3, + [BNXT_ULP_CLASS_HID_1d49] = 4, + [BNXT_ULP_CLASS_HID_2095] = 5, + [BNXT_ULP_CLASS_HID_5701] = 6, + [BNXT_ULP_CLASS_HID_4d79] = 7, + [BNXT_ULP_CLASS_HID_170d] = 8, + [BNXT_ULP_CLASS_HID_1a69] = 9, + [BNXT_ULP_CLASS_HID_50c5] = 10, + [BNXT_ULP_CLASS_HID_473d] = 11, + [BNXT_ULP_CLASS_HID_10c1] = 12, + [BNXT_ULP_CLASS_HID_142d] = 13, + [BNXT_ULP_CLASS_HID_4a99] = 14, + [BNXT_ULP_CLASS_HID_40f1] = 15, + [BNXT_ULP_CLASS_HID_0a85] = 16, + [BNXT_ULP_CLASS_HID_0179] = 17, + [BNXT_ULP_CLASS_HID_37d5] = 18, + [BNXT_ULP_CLASS_HID_2e4d] = 19, + [BNXT_ULP_CLASS_HID_54ad] = 20, + [BNXT_ULP_CLASS_HID_5809] = 21, + [BNXT_ULP_CLASS_HID_31a9] = 22, + [BNXT_ULP_CLASS_HID_2801] = 23, + [BNXT_ULP_CLASS_HID_4e61] = 24, + [BNXT_ULP_CLASS_HID_2561] = 25, + [BNXT_ULP_CLASS_HID_2bad] = 26, + [BNXT_ULP_CLASS_HID_26f1] = 27, + [BNXT_ULP_CLASS_HID_13cf1] = 28, + [BNXT_ULP_CLASS_HID_252f1] = 29, + [BNXT_ULP_CLASS_HID_30c25] = 30, + [BNXT_ULP_CLASS_HID_0051] = 31, + [BNXT_ULP_CLASS_HID_11651] = 32, + [BNXT_ULP_CLASS_HID_22c51] = 33, + [BNXT_ULP_CLASS_HID_34251] = 34, + [BNXT_ULP_CLASS_HID_5385] = 35, + [BNXT_ULP_CLASS_HID_10cc9] = 36, + [BNXT_ULP_CLASS_HID_222c9] = 37, + [BNXT_ULP_CLASS_HID_338c9] = 38, + [BNXT_ULP_CLASS_HID_1d69] = 39, + [BNXT_ULP_CLASS_HID_13369] = 40, + [BNXT_ULP_CLASS_HID_24969] = 41, + [BNXT_ULP_CLASS_HID_3025d] = 42, + [BNXT_ULP_CLASS_HID_20b5] = 43, + [BNXT_ULP_CLASS_HID_136b5] = 44, + [BNXT_ULP_CLASS_HID_24cb5] = 45, + [BNXT_ULP_CLASS_HID_305f9] = 46, + [BNXT_ULP_CLASS_HID_5721] = 47, + [BNXT_ULP_CLASS_HID_11015] = 48, + [BNXT_ULP_CLASS_HID_22615] = 49, + [BNXT_ULP_CLASS_HID_33c15] = 50, + [BNXT_ULP_CLASS_HID_4d59] = 51, + [BNXT_ULP_CLASS_HID_1068d] = 52, + [BNXT_ULP_CLASS_HID_21c8d] = 53, + [BNXT_ULP_CLASS_HID_3328d] = 54, + [BNXT_ULP_CLASS_HID_172d] = 55, + [BNXT_ULP_CLASS_HID_12d2d] = 56, + [BNXT_ULP_CLASS_HID_2432d] = 57, + [BNXT_ULP_CLASS_HID_3592d] = 58, + [BNXT_ULP_CLASS_HID_1a49] = 59, + [BNXT_ULP_CLASS_HID_13049] = 60, + [BNXT_ULP_CLASS_HID_24649] = 61, + [BNXT_ULP_CLASS_HID_35c49] = 62, + [BNXT_ULP_CLASS_HID_50e5] = 63, + [BNXT_ULP_CLASS_HID_10a29] = 64, + [BNXT_ULP_CLASS_HID_22029] = 65, + [BNXT_ULP_CLASS_HID_33629] = 66, + [BNXT_ULP_CLASS_HID_471d] = 67, + [BNXT_ULP_CLASS_HID_10041] = 68, + [BNXT_ULP_CLASS_HID_21641] = 69, + [BNXT_ULP_CLASS_HID_32c41] = 70, + [BNXT_ULP_CLASS_HID_10e1] = 71, + [BNXT_ULP_CLASS_HID_126e1] = 72, + [BNXT_ULP_CLASS_HID_23ce1] = 73, + [BNXT_ULP_CLASS_HID_352e1] = 74, + [BNXT_ULP_CLASS_HID_140d] = 75, + [BNXT_ULP_CLASS_HID_12a0d] = 76, + [BNXT_ULP_CLASS_HID_2400d] = 77, + [BNXT_ULP_CLASS_HID_3560d] = 78, + [BNXT_ULP_CLASS_HID_4ab9] = 79, + [BNXT_ULP_CLASS_HID_103ed] = 80, + [BNXT_ULP_CLASS_HID_219ed] = 81, + [BNXT_ULP_CLASS_HID_32fed] = 82, + [BNXT_ULP_CLASS_HID_40d1] = 83, + [BNXT_ULP_CLASS_HID_156d1] = 84, + [BNXT_ULP_CLASS_HID_21005] = 85, + [BNXT_ULP_CLASS_HID_32605] = 86, + [BNXT_ULP_CLASS_HID_0aa5] = 87, + [BNXT_ULP_CLASS_HID_120a5] = 88, + [BNXT_ULP_CLASS_HID_236a5] = 89, + [BNXT_ULP_CLASS_HID_34ca5] = 90, + [BNXT_ULP_CLASS_HID_0159] = 91, + [BNXT_ULP_CLASS_HID_11759] = 92, + [BNXT_ULP_CLASS_HID_22d59] = 93, + [BNXT_ULP_CLASS_HID_34359] = 94, + [BNXT_ULP_CLASS_HID_37f5] = 95, + [BNXT_ULP_CLASS_HID_14df5] = 96, + [BNXT_ULP_CLASS_HID_20739] = 97, + [BNXT_ULP_CLASS_HID_31d39] = 98, + [BNXT_ULP_CLASS_HID_2e6d] = 99, + [BNXT_ULP_CLASS_HID_1446d] = 100, + [BNXT_ULP_CLASS_HID_25a6d] = 101, + [BNXT_ULP_CLASS_HID_31351] = 102, + [BNXT_ULP_CLASS_HID_548d] = 103, + [BNXT_ULP_CLASS_HID_10df1] = 104, + [BNXT_ULP_CLASS_HID_223f1] = 105, + [BNXT_ULP_CLASS_HID_339f1] = 106, + [BNXT_ULP_CLASS_HID_5829] = 107, + [BNXT_ULP_CLASS_HID_1111d] = 108, + [BNXT_ULP_CLASS_HID_2271d] = 109, + [BNXT_ULP_CLASS_HID_33d1d] = 110, + [BNXT_ULP_CLASS_HID_3189] = 111, + [BNXT_ULP_CLASS_HID_14789] = 112, + [BNXT_ULP_CLASS_HID_200fd] = 113, + [BNXT_ULP_CLASS_HID_316fd] = 114, + [BNXT_ULP_CLASS_HID_2821] = 115, + [BNXT_ULP_CLASS_HID_13e21] = 116, + [BNXT_ULP_CLASS_HID_25421] = 117, + [BNXT_ULP_CLASS_HID_30d15] = 118, + [BNXT_ULP_CLASS_HID_4e41] = 119, + [BNXT_ULP_CLASS_HID_107b5] = 120, + [BNXT_ULP_CLASS_HID_21db5] = 121, + [BNXT_ULP_CLASS_HID_333b5] = 122, + [BNXT_ULP_CLASS_HID_2541] = 123, + [BNXT_ULP_CLASS_HID_2b8d] = 124, + [BNXT_ULP_CLASS_HID_2691] = 125, + [BNXT_ULP_CLASS_HID_13c91] = 126, + [BNXT_ULP_CLASS_HID_25291] = 127, + [BNXT_ULP_CLASS_HID_30c45] = 128, + [BNXT_ULP_CLASS_HID_0031] = 129, + [BNXT_ULP_CLASS_HID_11631] = 130, + [BNXT_ULP_CLASS_HID_22c31] = 131, + [BNXT_ULP_CLASS_HID_34231] = 132, + [BNXT_ULP_CLASS_HID_53e5] = 133, + [BNXT_ULP_CLASS_HID_10ca9] = 134, + [BNXT_ULP_CLASS_HID_222a9] = 135, + [BNXT_ULP_CLASS_HID_338a9] = 136, + [BNXT_ULP_CLASS_HID_1d09] = 137, + [BNXT_ULP_CLASS_HID_13309] = 138, + [BNXT_ULP_CLASS_HID_24909] = 139, + [BNXT_ULP_CLASS_HID_3023d] = 140, + [BNXT_ULP_CLASS_HID_20d5] = 141, + [BNXT_ULP_CLASS_HID_136d5] = 142, + [BNXT_ULP_CLASS_HID_24cd5] = 143, + [BNXT_ULP_CLASS_HID_30599] = 144, + [BNXT_ULP_CLASS_HID_5741] = 145, + [BNXT_ULP_CLASS_HID_11075] = 146, + [BNXT_ULP_CLASS_HID_22675] = 147, + [BNXT_ULP_CLASS_HID_33c75] = 148, + [BNXT_ULP_CLASS_HID_4d39] = 149, + [BNXT_ULP_CLASS_HID_106ed] = 150, + [BNXT_ULP_CLASS_HID_21ced] = 151, + [BNXT_ULP_CLASS_HID_332ed] = 152, + [BNXT_ULP_CLASS_HID_174d] = 153, + [BNXT_ULP_CLASS_HID_12d4d] = 154, + [BNXT_ULP_CLASS_HID_2434d] = 155, + [BNXT_ULP_CLASS_HID_3594d] = 156, + [BNXT_ULP_CLASS_HID_1a29] = 157, + [BNXT_ULP_CLASS_HID_13029] = 158, + [BNXT_ULP_CLASS_HID_24629] = 159, + [BNXT_ULP_CLASS_HID_35c29] = 160, + [BNXT_ULP_CLASS_HID_5085] = 161, + [BNXT_ULP_CLASS_HID_10a49] = 162, + [BNXT_ULP_CLASS_HID_22049] = 163, + [BNXT_ULP_CLASS_HID_33649] = 164, + [BNXT_ULP_CLASS_HID_477d] = 165, + [BNXT_ULP_CLASS_HID_10021] = 166, + [BNXT_ULP_CLASS_HID_21621] = 167, + [BNXT_ULP_CLASS_HID_32c21] = 168, + [BNXT_ULP_CLASS_HID_1081] = 169, + [BNXT_ULP_CLASS_HID_12681] = 170, + [BNXT_ULP_CLASS_HID_23c81] = 171, + [BNXT_ULP_CLASS_HID_35281] = 172, + [BNXT_ULP_CLASS_HID_146d] = 173, + [BNXT_ULP_CLASS_HID_12a6d] = 174, + [BNXT_ULP_CLASS_HID_2406d] = 175, + [BNXT_ULP_CLASS_HID_3566d] = 176, + [BNXT_ULP_CLASS_HID_4ad9] = 177, + [BNXT_ULP_CLASS_HID_1038d] = 178, + [BNXT_ULP_CLASS_HID_2198d] = 179, + [BNXT_ULP_CLASS_HID_32f8d] = 180, + [BNXT_ULP_CLASS_HID_40b1] = 181, + [BNXT_ULP_CLASS_HID_156b1] = 182, + [BNXT_ULP_CLASS_HID_21065] = 183, + [BNXT_ULP_CLASS_HID_32665] = 184, + [BNXT_ULP_CLASS_HID_0ac5] = 185, + [BNXT_ULP_CLASS_HID_120c5] = 186, + [BNXT_ULP_CLASS_HID_236c5] = 187, + [BNXT_ULP_CLASS_HID_34cc5] = 188, + [BNXT_ULP_CLASS_HID_0139] = 189, + [BNXT_ULP_CLASS_HID_11739] = 190, + [BNXT_ULP_CLASS_HID_22d39] = 191, + [BNXT_ULP_CLASS_HID_34339] = 192, + [BNXT_ULP_CLASS_HID_3795] = 193, + [BNXT_ULP_CLASS_HID_14d95] = 194, + [BNXT_ULP_CLASS_HID_20759] = 195, + [BNXT_ULP_CLASS_HID_31d59] = 196, + [BNXT_ULP_CLASS_HID_2e0d] = 197, + [BNXT_ULP_CLASS_HID_1440d] = 198, + [BNXT_ULP_CLASS_HID_25a0d] = 199, + [BNXT_ULP_CLASS_HID_31331] = 200, + [BNXT_ULP_CLASS_HID_54ed] = 201, + [BNXT_ULP_CLASS_HID_10d91] = 202, + [BNXT_ULP_CLASS_HID_22391] = 203, + [BNXT_ULP_CLASS_HID_33991] = 204, + [BNXT_ULP_CLASS_HID_5849] = 205, + [BNXT_ULP_CLASS_HID_1117d] = 206, + [BNXT_ULP_CLASS_HID_2277d] = 207, + [BNXT_ULP_CLASS_HID_33d7d] = 208, + [BNXT_ULP_CLASS_HID_31e9] = 209, + [BNXT_ULP_CLASS_HID_147e9] = 210, + [BNXT_ULP_CLASS_HID_2009d] = 211, + [BNXT_ULP_CLASS_HID_3169d] = 212, + [BNXT_ULP_CLASS_HID_2841] = 213, + [BNXT_ULP_CLASS_HID_13e41] = 214, + [BNXT_ULP_CLASS_HID_25441] = 215, + [BNXT_ULP_CLASS_HID_30d75] = 216, + [BNXT_ULP_CLASS_HID_4e21] = 217, + [BNXT_ULP_CLASS_HID_107d5] = 218, + [BNXT_ULP_CLASS_HID_21dd5] = 219, + [BNXT_ULP_CLASS_HID_333d5] = 220, + [BNXT_ULP_CLASS_HID_2521] = 221, + [BNXT_ULP_CLASS_HID_2bed] = 222, + [BNXT_ULP_CLASS_HID_1865] = 223, + [BNXT_ULP_CLASS_HID_389d] = 224, + [BNXT_ULP_CLASS_HID_123d] = 225, + [BNXT_ULP_CLASS_HID_4ef1] = 226, + [BNXT_ULP_CLASS_HID_1229] = 227, + [BNXT_ULP_CLASS_HID_3241] = 228, + [BNXT_ULP_CLASS_HID_0be1] = 229, + [BNXT_ULP_CLASS_HID_48b5] = 230, + [BNXT_ULP_CLASS_HID_0bed] = 231, + [BNXT_ULP_CLASS_HID_2c05] = 232, + [BNXT_ULP_CLASS_HID_05a5] = 233, + [BNXT_ULP_CLASS_HID_4279] = 234, + [BNXT_ULP_CLASS_HID_05d1] = 235, + [BNXT_ULP_CLASS_HID_25c9] = 236, + [BNXT_ULP_CLASS_HID_5c55] = 237, + [BNXT_ULP_CLASS_HID_3c3d] = 238, + [BNXT_ULP_CLASS_HID_4fc9] = 239, + [BNXT_ULP_CLASS_HID_1335] = 240, + [BNXT_ULP_CLASS_HID_4981] = 241, + [BNXT_ULP_CLASS_HID_2969] = 242, + [BNXT_ULP_CLASS_HID_498d] = 243, + [BNXT_ULP_CLASS_HID_0cf9] = 244, + [BNXT_ULP_CLASS_HID_4345] = 245, + [BNXT_ULP_CLASS_HID_232d] = 246, + [BNXT_ULP_CLASS_HID_2579] = 247, + [BNXT_ULP_CLASS_HID_2bb5] = 248, + [BNXT_ULP_CLASS_HID_1845] = 249, + [BNXT_ULP_CLASS_HID_1399] = 250, + [BNXT_ULP_CLASS_HID_0eed] = 251, + [BNXT_ULP_CLASS_HID_0a21] = 252, + [BNXT_ULP_CLASS_HID_38bd] = 253, + [BNXT_ULP_CLASS_HID_33f1] = 254, + [BNXT_ULP_CLASS_HID_2ec5] = 255, + [BNXT_ULP_CLASS_HID_2a19] = 256, + [BNXT_ULP_CLASS_HID_121d] = 257, + [BNXT_ULP_CLASS_HID_0d51] = 258, + [BNXT_ULP_CLASS_HID_08a5] = 259, + [BNXT_ULP_CLASS_HID_03f9] = 260, + [BNXT_ULP_CLASS_HID_4ed1] = 261, + [BNXT_ULP_CLASS_HID_4a25] = 262, + [BNXT_ULP_CLASS_HID_4579] = 263, + [BNXT_ULP_CLASS_HID_404d] = 264, + [BNXT_ULP_CLASS_HID_1209] = 265, + [BNXT_ULP_CLASS_HID_0d5d] = 266, + [BNXT_ULP_CLASS_HID_0891] = 267, + [BNXT_ULP_CLASS_HID_03e5] = 268, + [BNXT_ULP_CLASS_HID_3261] = 269, + [BNXT_ULP_CLASS_HID_2db5] = 270, + [BNXT_ULP_CLASS_HID_2889] = 271, + [BNXT_ULP_CLASS_HID_23dd] = 272, + [BNXT_ULP_CLASS_HID_0bc1] = 273, + [BNXT_ULP_CLASS_HID_0715] = 274, + [BNXT_ULP_CLASS_HID_0269] = 275, + [BNXT_ULP_CLASS_HID_5a69] = 276, + [BNXT_ULP_CLASS_HID_4895] = 277, + [BNXT_ULP_CLASS_HID_43e9] = 278, + [BNXT_ULP_CLASS_HID_3f3d] = 279, + [BNXT_ULP_CLASS_HID_3a71] = 280, + [BNXT_ULP_CLASS_HID_0bcd] = 281, + [BNXT_ULP_CLASS_HID_0701] = 282, + [BNXT_ULP_CLASS_HID_0255] = 283, + [BNXT_ULP_CLASS_HID_5a55] = 284, + [BNXT_ULP_CLASS_HID_2c25] = 285, + [BNXT_ULP_CLASS_HID_2779] = 286, + [BNXT_ULP_CLASS_HID_224d] = 287, + [BNXT_ULP_CLASS_HID_1d81] = 288, + [BNXT_ULP_CLASS_HID_0585] = 289, + [BNXT_ULP_CLASS_HID_00d9] = 290, + [BNXT_ULP_CLASS_HID_58d9] = 291, + [BNXT_ULP_CLASS_HID_542d] = 292, + [BNXT_ULP_CLASS_HID_4259] = 293, + [BNXT_ULP_CLASS_HID_3dad] = 294, + [BNXT_ULP_CLASS_HID_38e1] = 295, + [BNXT_ULP_CLASS_HID_3435] = 296, + [BNXT_ULP_CLASS_HID_05f1] = 297, + [BNXT_ULP_CLASS_HID_00c5] = 298, + [BNXT_ULP_CLASS_HID_58c5] = 299, + [BNXT_ULP_CLASS_HID_5419] = 300, + [BNXT_ULP_CLASS_HID_25e9] = 301, + [BNXT_ULP_CLASS_HID_213d] = 302, + [BNXT_ULP_CLASS_HID_1c71] = 303, + [BNXT_ULP_CLASS_HID_1745] = 304, + [BNXT_ULP_CLASS_HID_5c75] = 305, + [BNXT_ULP_CLASS_HID_5749] = 306, + [BNXT_ULP_CLASS_HID_529d] = 307, + [BNXT_ULP_CLASS_HID_4dd1] = 308, + [BNXT_ULP_CLASS_HID_3c1d] = 309, + [BNXT_ULP_CLASS_HID_3751] = 310, + [BNXT_ULP_CLASS_HID_32a5] = 311, + [BNXT_ULP_CLASS_HID_2df9] = 312, + [BNXT_ULP_CLASS_HID_4fe9] = 313, + [BNXT_ULP_CLASS_HID_4b3d] = 314, + [BNXT_ULP_CLASS_HID_4671] = 315, + [BNXT_ULP_CLASS_HID_4145] = 316, + [BNXT_ULP_CLASS_HID_1315] = 317, + [BNXT_ULP_CLASS_HID_0e69] = 318, + [BNXT_ULP_CLASS_HID_09bd] = 319, + [BNXT_ULP_CLASS_HID_04f1] = 320, + [BNXT_ULP_CLASS_HID_49a1] = 321, + [BNXT_ULP_CLASS_HID_44f5] = 322, + [BNXT_ULP_CLASS_HID_3fc9] = 323, + [BNXT_ULP_CLASS_HID_3b1d] = 324, + [BNXT_ULP_CLASS_HID_2949] = 325, + [BNXT_ULP_CLASS_HID_249d] = 326, + [BNXT_ULP_CLASS_HID_1fd1] = 327, + [BNXT_ULP_CLASS_HID_1b25] = 328, + [BNXT_ULP_CLASS_HID_49ad] = 329, + [BNXT_ULP_CLASS_HID_44e1] = 330, + [BNXT_ULP_CLASS_HID_4035] = 331, + [BNXT_ULP_CLASS_HID_3b09] = 332, + [BNXT_ULP_CLASS_HID_0cd9] = 333, + [BNXT_ULP_CLASS_HID_082d] = 334, + [BNXT_ULP_CLASS_HID_0361] = 335, + [BNXT_ULP_CLASS_HID_5b61] = 336, + [BNXT_ULP_CLASS_HID_4365] = 337, + [BNXT_ULP_CLASS_HID_3eb9] = 338, + [BNXT_ULP_CLASS_HID_398d] = 339, + [BNXT_ULP_CLASS_HID_34c1] = 340, + [BNXT_ULP_CLASS_HID_230d] = 341, + [BNXT_ULP_CLASS_HID_1e41] = 342, + [BNXT_ULP_CLASS_HID_1995] = 343, + [BNXT_ULP_CLASS_HID_14e9] = 344, + [BNXT_ULP_CLASS_HID_2559] = 345, + [BNXT_ULP_CLASS_HID_2b95] = 346, + [BNXT_ULP_CLASS_HID_1825] = 347, + [BNXT_ULP_CLASS_HID_13f9] = 348, + [BNXT_ULP_CLASS_HID_0e8d] = 349, + [BNXT_ULP_CLASS_HID_0a41] = 350, + [BNXT_ULP_CLASS_HID_38dd] = 351, + [BNXT_ULP_CLASS_HID_3391] = 352, + [BNXT_ULP_CLASS_HID_2ea5] = 353, + [BNXT_ULP_CLASS_HID_2a79] = 354, + [BNXT_ULP_CLASS_HID_127d] = 355, + [BNXT_ULP_CLASS_HID_0d31] = 356, + [BNXT_ULP_CLASS_HID_08c5] = 357, + [BNXT_ULP_CLASS_HID_0399] = 358, + [BNXT_ULP_CLASS_HID_4eb1] = 359, + [BNXT_ULP_CLASS_HID_4a45] = 360, + [BNXT_ULP_CLASS_HID_4519] = 361, + [BNXT_ULP_CLASS_HID_402d] = 362, + [BNXT_ULP_CLASS_HID_1269] = 363, + [BNXT_ULP_CLASS_HID_0d3d] = 364, + [BNXT_ULP_CLASS_HID_08f1] = 365, + [BNXT_ULP_CLASS_HID_0385] = 366, + [BNXT_ULP_CLASS_HID_3201] = 367, + [BNXT_ULP_CLASS_HID_2dd5] = 368, + [BNXT_ULP_CLASS_HID_28e9] = 369, + [BNXT_ULP_CLASS_HID_23bd] = 370, + [BNXT_ULP_CLASS_HID_0ba1] = 371, + [BNXT_ULP_CLASS_HID_0775] = 372, + [BNXT_ULP_CLASS_HID_0209] = 373, + [BNXT_ULP_CLASS_HID_5a09] = 374, + [BNXT_ULP_CLASS_HID_48f5] = 375, + [BNXT_ULP_CLASS_HID_4389] = 376, + [BNXT_ULP_CLASS_HID_3f5d] = 377, + [BNXT_ULP_CLASS_HID_3a11] = 378, + [BNXT_ULP_CLASS_HID_0bad] = 379, + [BNXT_ULP_CLASS_HID_0761] = 380, + [BNXT_ULP_CLASS_HID_0235] = 381, + [BNXT_ULP_CLASS_HID_5a35] = 382, + [BNXT_ULP_CLASS_HID_2c45] = 383, + [BNXT_ULP_CLASS_HID_2719] = 384, + [BNXT_ULP_CLASS_HID_222d] = 385, + [BNXT_ULP_CLASS_HID_1de1] = 386, + [BNXT_ULP_CLASS_HID_05e5] = 387, + [BNXT_ULP_CLASS_HID_00b9] = 388, + [BNXT_ULP_CLASS_HID_58b9] = 389, + [BNXT_ULP_CLASS_HID_544d] = 390, + [BNXT_ULP_CLASS_HID_4239] = 391, + [BNXT_ULP_CLASS_HID_3dcd] = 392, + [BNXT_ULP_CLASS_HID_3881] = 393, + [BNXT_ULP_CLASS_HID_3455] = 394, + [BNXT_ULP_CLASS_HID_0591] = 395, + [BNXT_ULP_CLASS_HID_00a5] = 396, + [BNXT_ULP_CLASS_HID_58a5] = 397, + [BNXT_ULP_CLASS_HID_5479] = 398, + [BNXT_ULP_CLASS_HID_2589] = 399, + [BNXT_ULP_CLASS_HID_215d] = 400, + [BNXT_ULP_CLASS_HID_1c11] = 401, + [BNXT_ULP_CLASS_HID_1725] = 402, + [BNXT_ULP_CLASS_HID_5c15] = 403, + [BNXT_ULP_CLASS_HID_5729] = 404, + [BNXT_ULP_CLASS_HID_52fd] = 405, + [BNXT_ULP_CLASS_HID_4db1] = 406, + [BNXT_ULP_CLASS_HID_3c7d] = 407, + [BNXT_ULP_CLASS_HID_3731] = 408, + [BNXT_ULP_CLASS_HID_32c5] = 409, + [BNXT_ULP_CLASS_HID_2d99] = 410, + [BNXT_ULP_CLASS_HID_4f89] = 411, + [BNXT_ULP_CLASS_HID_4b5d] = 412, + [BNXT_ULP_CLASS_HID_4611] = 413, + [BNXT_ULP_CLASS_HID_4125] = 414, + [BNXT_ULP_CLASS_HID_1375] = 415, + [BNXT_ULP_CLASS_HID_0e09] = 416, + [BNXT_ULP_CLASS_HID_09dd] = 417, + [BNXT_ULP_CLASS_HID_0491] = 418, + [BNXT_ULP_CLASS_HID_49c1] = 419, + [BNXT_ULP_CLASS_HID_4495] = 420, + [BNXT_ULP_CLASS_HID_3fa9] = 421, + [BNXT_ULP_CLASS_HID_3b7d] = 422, + [BNXT_ULP_CLASS_HID_2929] = 423, + [BNXT_ULP_CLASS_HID_24fd] = 424, + [BNXT_ULP_CLASS_HID_1fb1] = 425, + [BNXT_ULP_CLASS_HID_1b45] = 426, + [BNXT_ULP_CLASS_HID_49cd] = 427, + [BNXT_ULP_CLASS_HID_4481] = 428, + [BNXT_ULP_CLASS_HID_4055] = 429, + [BNXT_ULP_CLASS_HID_3b69] = 430, + [BNXT_ULP_CLASS_HID_0cb9] = 431, + [BNXT_ULP_CLASS_HID_084d] = 432, + [BNXT_ULP_CLASS_HID_0301] = 433, + [BNXT_ULP_CLASS_HID_5b01] = 434, + [BNXT_ULP_CLASS_HID_4305] = 435, + [BNXT_ULP_CLASS_HID_3ed9] = 436, + [BNXT_ULP_CLASS_HID_39ed] = 437, + [BNXT_ULP_CLASS_HID_34a1] = 438, + [BNXT_ULP_CLASS_HID_236d] = 439, + [BNXT_ULP_CLASS_HID_1e21] = 440, + [BNXT_ULP_CLASS_HID_19f5] = 441, + [BNXT_ULP_CLASS_HID_1489] = 442, + [BNXT_ULP_CLASS_HID_2539] = 443, + [BNXT_ULP_CLASS_HID_2bf5] = 444, + [BNXT_ULP_CLASS_HID_b6af] = 445, + [BNXT_ULP_CLASS_HID_b1d3] = 446, + [BNXT_ULP_CLASS_HID_1c7d3] = 447, + [BNXT_ULP_CLASS_HID_1ccaf] = 448, + [BNXT_ULP_CLASS_HID_da33] = 449, + [BNXT_ULP_CLASS_HID_d567] = 450, + [BNXT_ULP_CLASS_HID_18eab] = 451, + [BNXT_ULP_CLASS_HID_19367] = 452, + [BNXT_ULP_CLASS_HID_a10b] = 453, + [BNXT_ULP_CLASS_HID_9c3f] = 454, + [BNXT_ULP_CLASS_HID_1b23f] = 455, + [BNXT_ULP_CLASS_HID_1b70b] = 456, + [BNXT_ULP_CLASS_HID_c49f] = 457, + [BNXT_ULP_CLASS_HID_bfc3] = 458, + [BNXT_ULP_CLASS_HID_1d5c3] = 459, + [BNXT_ULP_CLASS_HID_1da9f] = 460, + [BNXT_ULP_CLASS_HID_b063] = 461, + [BNXT_ULP_CLASS_HID_ab97] = 462, + [BNXT_ULP_CLASS_HID_1c197] = 463, + [BNXT_ULP_CLASS_HID_1c663] = 464, + [BNXT_ULP_CLASS_HID_d3f7] = 465, + [BNXT_ULP_CLASS_HID_cf3b] = 466, + [BNXT_ULP_CLASS_HID_1886f] = 467, + [BNXT_ULP_CLASS_HID_18d3b] = 468, + [BNXT_ULP_CLASS_HID_9acf] = 469, + [BNXT_ULP_CLASS_HID_95f3] = 470, + [BNXT_ULP_CLASS_HID_1abf3] = 471, + [BNXT_ULP_CLASS_HID_1b0cf] = 472, + [BNXT_ULP_CLASS_HID_be53] = 473, + [BNXT_ULP_CLASS_HID_b987] = 474, + [BNXT_ULP_CLASS_HID_1cf87] = 475, + [BNXT_ULP_CLASS_HID_1d453] = 476, + [BNXT_ULP_CLASS_HID_aa27] = 477, + [BNXT_ULP_CLASS_HID_a56b] = 478, + [BNXT_ULP_CLASS_HID_1bb6b] = 479, + [BNXT_ULP_CLASS_HID_1c027] = 480, + [BNXT_ULP_CLASS_HID_cdcb] = 481, + [BNXT_ULP_CLASS_HID_c8ff] = 482, + [BNXT_ULP_CLASS_HID_18223] = 483, + [BNXT_ULP_CLASS_HID_186ff] = 484, + [BNXT_ULP_CLASS_HID_9483] = 485, + [BNXT_ULP_CLASS_HID_8fb7] = 486, + [BNXT_ULP_CLASS_HID_1a5b7] = 487, + [BNXT_ULP_CLASS_HID_1aa83] = 488, + [BNXT_ULP_CLASS_HID_b817] = 489, + [BNXT_ULP_CLASS_HID_b35b] = 490, + [BNXT_ULP_CLASS_HID_1c95b] = 491, + [BNXT_ULP_CLASS_HID_1ce17] = 492, + [BNXT_ULP_CLASS_HID_a3fb] = 493, + [BNXT_ULP_CLASS_HID_9f2f] = 494, + [BNXT_ULP_CLASS_HID_1b52f] = 495, + [BNXT_ULP_CLASS_HID_1b9fb] = 496, + [BNXT_ULP_CLASS_HID_c78f] = 497, + [BNXT_ULP_CLASS_HID_c2b3] = 498, + [BNXT_ULP_CLASS_HID_1d8b3] = 499, + [BNXT_ULP_CLASS_HID_180b3] = 500, + [BNXT_ULP_CLASS_HID_8e47] = 501, + [BNXT_ULP_CLASS_HID_898b] = 502, + [BNXT_ULP_CLASS_HID_19f8b] = 503, + [BNXT_ULP_CLASS_HID_1a447] = 504, + [BNXT_ULP_CLASS_HID_b1eb] = 505, + [BNXT_ULP_CLASS_HID_ad1f] = 506, + [BNXT_ULP_CLASS_HID_1c31f] = 507, + [BNXT_ULP_CLASS_HID_1c7eb] = 508, + [BNXT_ULP_CLASS_HID_9137] = 509, + [BNXT_ULP_CLASS_HID_8c7b] = 510, + [BNXT_ULP_CLASS_HID_1a27b] = 511, + [BNXT_ULP_CLASS_HID_1a737] = 512, + [BNXT_ULP_CLASS_HID_b4db] = 513, + [BNXT_ULP_CLASS_HID_b00f] = 514, + [BNXT_ULP_CLASS_HID_1c60f] = 515, + [BNXT_ULP_CLASS_HID_1cadb] = 516, + [BNXT_ULP_CLASS_HID_8b0b] = 517, + [BNXT_ULP_CLASS_HID_863f] = 518, + [BNXT_ULP_CLASS_HID_19c3f] = 519, + [BNXT_ULP_CLASS_HID_1a10b] = 520, + [BNXT_ULP_CLASS_HID_ae9f] = 521, + [BNXT_ULP_CLASS_HID_a9c3] = 522, + [BNXT_ULP_CLASS_HID_1bfc3] = 523, + [BNXT_ULP_CLASS_HID_1c49f] = 524, + [BNXT_ULP_CLASS_HID_2563] = 525, + [BNXT_ULP_CLASS_HID_2baf] = 526, + [BNXT_ULP_CLASS_HID_4f33] = 527, + [BNXT_ULP_CLASS_HID_160b] = 528, + [BNXT_ULP_CLASS_HID_399f] = 529, + [BNXT_ULP_CLASS_HID_48f7] = 530, + [BNXT_ULP_CLASS_HID_0fcf] = 531, + [BNXT_ULP_CLASS_HID_3353] = 532, + [BNXT_ULP_CLASS_HID_b68f] = 533, + [BNXT_ULP_CLASS_HID_b94f] = 534, + [BNXT_ULP_CLASS_HID_fc0f] = 535, + [BNXT_ULP_CLASS_HID_fecf] = 536, + [BNXT_ULP_CLASS_HID_b1f3] = 537, + [BNXT_ULP_CLASS_HID_b4b3] = 538, + [BNXT_ULP_CLASS_HID_f773] = 539, + [BNXT_ULP_CLASS_HID_fa33] = 540, + [BNXT_ULP_CLASS_HID_1c7f3] = 541, + [BNXT_ULP_CLASS_HID_1eab3] = 542, + [BNXT_ULP_CLASS_HID_1cd73] = 543, + [BNXT_ULP_CLASS_HID_1f033] = 544, + [BNXT_ULP_CLASS_HID_1cc8f] = 545, + [BNXT_ULP_CLASS_HID_1ef4f] = 546, + [BNXT_ULP_CLASS_HID_1d20f] = 547, + [BNXT_ULP_CLASS_HID_1f4cf] = 548, + [BNXT_ULP_CLASS_HID_da13] = 549, + [BNXT_ULP_CLASS_HID_a007] = 550, + [BNXT_ULP_CLASS_HID_c2c7] = 551, + [BNXT_ULP_CLASS_HID_e587] = 552, + [BNXT_ULP_CLASS_HID_d547] = 553, + [BNXT_ULP_CLASS_HID_f807] = 554, + [BNXT_ULP_CLASS_HID_dac7] = 555, + [BNXT_ULP_CLASS_HID_e0cb] = 556, + [BNXT_ULP_CLASS_HID_18e8b] = 557, + [BNXT_ULP_CLASS_HID_1b14b] = 558, + [BNXT_ULP_CLASS_HID_1d40b] = 559, + [BNXT_ULP_CLASS_HID_1f6cb] = 560, + [BNXT_ULP_CLASS_HID_19347] = 561, + [BNXT_ULP_CLASS_HID_1b607] = 562, + [BNXT_ULP_CLASS_HID_1d8c7] = 563, + [BNXT_ULP_CLASS_HID_1fb87] = 564, + [BNXT_ULP_CLASS_HID_a12b] = 565, + [BNXT_ULP_CLASS_HID_a3eb] = 566, + [BNXT_ULP_CLASS_HID_e6ab] = 567, + [BNXT_ULP_CLASS_HID_e96b] = 568, + [BNXT_ULP_CLASS_HID_9c1f] = 569, + [BNXT_ULP_CLASS_HID_bedf] = 570, + [BNXT_ULP_CLASS_HID_e19f] = 571, + [BNXT_ULP_CLASS_HID_e45f] = 572, + [BNXT_ULP_CLASS_HID_1b21f] = 573, + [BNXT_ULP_CLASS_HID_1b4df] = 574, + [BNXT_ULP_CLASS_HID_1f79f] = 575, + [BNXT_ULP_CLASS_HID_1fa5f] = 576, + [BNXT_ULP_CLASS_HID_1b72b] = 577, + [BNXT_ULP_CLASS_HID_1b9eb] = 578, + [BNXT_ULP_CLASS_HID_1fcab] = 579, + [BNXT_ULP_CLASS_HID_1ff6b] = 580, + [BNXT_ULP_CLASS_HID_c4bf] = 581, + [BNXT_ULP_CLASS_HID_e77f] = 582, + [BNXT_ULP_CLASS_HID_ca3f] = 583, + [BNXT_ULP_CLASS_HID_ecff] = 584, + [BNXT_ULP_CLASS_HID_bfe3] = 585, + [BNXT_ULP_CLASS_HID_e2a3] = 586, + [BNXT_ULP_CLASS_HID_c563] = 587, + [BNXT_ULP_CLASS_HID_e823] = 588, + [BNXT_ULP_CLASS_HID_1d5e3] = 589, + [BNXT_ULP_CLASS_HID_1f8a3] = 590, + [BNXT_ULP_CLASS_HID_1db63] = 591, + [BNXT_ULP_CLASS_HID_1e117] = 592, + [BNXT_ULP_CLASS_HID_1dabf] = 593, + [BNXT_ULP_CLASS_HID_1a0a3] = 594, + [BNXT_ULP_CLASS_HID_1c363] = 595, + [BNXT_ULP_CLASS_HID_1e623] = 596, + [BNXT_ULP_CLASS_HID_b043] = 597, + [BNXT_ULP_CLASS_HID_b303] = 598, + [BNXT_ULP_CLASS_HID_f5c3] = 599, + [BNXT_ULP_CLASS_HID_f883] = 600, + [BNXT_ULP_CLASS_HID_abb7] = 601, + [BNXT_ULP_CLASS_HID_ae77] = 602, + [BNXT_ULP_CLASS_HID_f137] = 603, + [BNXT_ULP_CLASS_HID_f3f7] = 604, + [BNXT_ULP_CLASS_HID_1c1b7] = 605, + [BNXT_ULP_CLASS_HID_1e477] = 606, + [BNXT_ULP_CLASS_HID_1c737] = 607, + [BNXT_ULP_CLASS_HID_1e9f7] = 608, + [BNXT_ULP_CLASS_HID_1c643] = 609, + [BNXT_ULP_CLASS_HID_1e903] = 610, + [BNXT_ULP_CLASS_HID_1cbc3] = 611, + [BNXT_ULP_CLASS_HID_1ee83] = 612, + [BNXT_ULP_CLASS_HID_d3d7] = 613, + [BNXT_ULP_CLASS_HID_f697] = 614, + [BNXT_ULP_CLASS_HID_d957] = 615, + [BNXT_ULP_CLASS_HID_fc17] = 616, + [BNXT_ULP_CLASS_HID_cf1b] = 617, + [BNXT_ULP_CLASS_HID_f1db] = 618, + [BNXT_ULP_CLASS_HID_d49b] = 619, + [BNXT_ULP_CLASS_HID_f75b] = 620, + [BNXT_ULP_CLASS_HID_1884f] = 621, + [BNXT_ULP_CLASS_HID_1ab0f] = 622, + [BNXT_ULP_CLASS_HID_1cdcf] = 623, + [BNXT_ULP_CLASS_HID_1f08f] = 624, + [BNXT_ULP_CLASS_HID_18d1b] = 625, + [BNXT_ULP_CLASS_HID_1afdb] = 626, + [BNXT_ULP_CLASS_HID_1d29b] = 627, + [BNXT_ULP_CLASS_HID_1f55b] = 628, + [BNXT_ULP_CLASS_HID_9aef] = 629, + [BNXT_ULP_CLASS_HID_bdaf] = 630, + [BNXT_ULP_CLASS_HID_e06f] = 631, + [BNXT_ULP_CLASS_HID_e32f] = 632, + [BNXT_ULP_CLASS_HID_95d3] = 633, + [BNXT_ULP_CLASS_HID_b893] = 634, + [BNXT_ULP_CLASS_HID_db53] = 635, + [BNXT_ULP_CLASS_HID_fe13] = 636, + [BNXT_ULP_CLASS_HID_1abd3] = 637, + [BNXT_ULP_CLASS_HID_1ae93] = 638, + [BNXT_ULP_CLASS_HID_1f153] = 639, + [BNXT_ULP_CLASS_HID_1f413] = 640, + [BNXT_ULP_CLASS_HID_1b0ef] = 641, + [BNXT_ULP_CLASS_HID_1b3af] = 642, + [BNXT_ULP_CLASS_HID_1f66f] = 643, + [BNXT_ULP_CLASS_HID_1f92f] = 644, + [BNXT_ULP_CLASS_HID_be73] = 645, + [BNXT_ULP_CLASS_HID_e133] = 646, + [BNXT_ULP_CLASS_HID_c3f3] = 647, + [BNXT_ULP_CLASS_HID_e6b3] = 648, + [BNXT_ULP_CLASS_HID_b9a7] = 649, + [BNXT_ULP_CLASS_HID_bc67] = 650, + [BNXT_ULP_CLASS_HID_ff27] = 651, + [BNXT_ULP_CLASS_HID_e1e7] = 652, + [BNXT_ULP_CLASS_HID_1cfa7] = 653, + [BNXT_ULP_CLASS_HID_1f267] = 654, + [BNXT_ULP_CLASS_HID_1d527] = 655, + [BNXT_ULP_CLASS_HID_1f7e7] = 656, + [BNXT_ULP_CLASS_HID_1d473] = 657, + [BNXT_ULP_CLASS_HID_1f733] = 658, + [BNXT_ULP_CLASS_HID_1d9f3] = 659, + [BNXT_ULP_CLASS_HID_1fcb3] = 660, + [BNXT_ULP_CLASS_HID_aa07] = 661, + [BNXT_ULP_CLASS_HID_acc7] = 662, + [BNXT_ULP_CLASS_HID_ef87] = 663, + [BNXT_ULP_CLASS_HID_f247] = 664, + [BNXT_ULP_CLASS_HID_a54b] = 665, + [BNXT_ULP_CLASS_HID_a80b] = 666, + [BNXT_ULP_CLASS_HID_eacb] = 667, + [BNXT_ULP_CLASS_HID_ed8b] = 668, + [BNXT_ULP_CLASS_HID_1bb4b] = 669, + [BNXT_ULP_CLASS_HID_1be0b] = 670, + [BNXT_ULP_CLASS_HID_1c0cb] = 671, + [BNXT_ULP_CLASS_HID_1e38b] = 672, + [BNXT_ULP_CLASS_HID_1c007] = 673, + [BNXT_ULP_CLASS_HID_1e2c7] = 674, + [BNXT_ULP_CLASS_HID_1c587] = 675, + [BNXT_ULP_CLASS_HID_1e847] = 676, + [BNXT_ULP_CLASS_HID_cdeb] = 677, + [BNXT_ULP_CLASS_HID_f0ab] = 678, + [BNXT_ULP_CLASS_HID_d36b] = 679, + [BNXT_ULP_CLASS_HID_f62b] = 680, + [BNXT_ULP_CLASS_HID_c8df] = 681, + [BNXT_ULP_CLASS_HID_eb9f] = 682, + [BNXT_ULP_CLASS_HID_ce5f] = 683, + [BNXT_ULP_CLASS_HID_f11f] = 684, + [BNXT_ULP_CLASS_HID_18203] = 685, + [BNXT_ULP_CLASS_HID_1a4c3] = 686, + [BNXT_ULP_CLASS_HID_1c783] = 687, + [BNXT_ULP_CLASS_HID_1ea43] = 688, + [BNXT_ULP_CLASS_HID_186df] = 689, + [BNXT_ULP_CLASS_HID_1a99f] = 690, + [BNXT_ULP_CLASS_HID_1cc5f] = 691, + [BNXT_ULP_CLASS_HID_1ef1f] = 692, + [BNXT_ULP_CLASS_HID_94a3] = 693, + [BNXT_ULP_CLASS_HID_b763] = 694, + [BNXT_ULP_CLASS_HID_da23] = 695, + [BNXT_ULP_CLASS_HID_fce3] = 696, + [BNXT_ULP_CLASS_HID_8f97] = 697, + [BNXT_ULP_CLASS_HID_b257] = 698, + [BNXT_ULP_CLASS_HID_d517] = 699, + [BNXT_ULP_CLASS_HID_f7d7] = 700, + [BNXT_ULP_CLASS_HID_1a597] = 701, + [BNXT_ULP_CLASS_HID_1a857] = 702, + [BNXT_ULP_CLASS_HID_1eb17] = 703, + [BNXT_ULP_CLASS_HID_1edd7] = 704, + [BNXT_ULP_CLASS_HID_1aaa3] = 705, + [BNXT_ULP_CLASS_HID_1ad63] = 706, + [BNXT_ULP_CLASS_HID_1f023] = 707, + [BNXT_ULP_CLASS_HID_1f2e3] = 708, + [BNXT_ULP_CLASS_HID_b837] = 709, + [BNXT_ULP_CLASS_HID_baf7] = 710, + [BNXT_ULP_CLASS_HID_fdb7] = 711, + [BNXT_ULP_CLASS_HID_e077] = 712, + [BNXT_ULP_CLASS_HID_b37b] = 713, + [BNXT_ULP_CLASS_HID_b63b] = 714, + [BNXT_ULP_CLASS_HID_f8fb] = 715, + [BNXT_ULP_CLASS_HID_fbbb] = 716, + [BNXT_ULP_CLASS_HID_1c97b] = 717, + [BNXT_ULP_CLASS_HID_1ec3b] = 718, + [BNXT_ULP_CLASS_HID_1cefb] = 719, + [BNXT_ULP_CLASS_HID_1f1bb] = 720, + [BNXT_ULP_CLASS_HID_1ce37] = 721, + [BNXT_ULP_CLASS_HID_1f0f7] = 722, + [BNXT_ULP_CLASS_HID_1d3b7] = 723, + [BNXT_ULP_CLASS_HID_1f677] = 724, + [BNXT_ULP_CLASS_HID_a3db] = 725, + [BNXT_ULP_CLASS_HID_a69b] = 726, + [BNXT_ULP_CLASS_HID_e95b] = 727, + [BNXT_ULP_CLASS_HID_ec1b] = 728, + [BNXT_ULP_CLASS_HID_9f0f] = 729, + [BNXT_ULP_CLASS_HID_a1cf] = 730, + [BNXT_ULP_CLASS_HID_e48f] = 731, + [BNXT_ULP_CLASS_HID_e74f] = 732, + [BNXT_ULP_CLASS_HID_1b50f] = 733, + [BNXT_ULP_CLASS_HID_1b7cf] = 734, + [BNXT_ULP_CLASS_HID_1fa8f] = 735, + [BNXT_ULP_CLASS_HID_1fd4f] = 736, + [BNXT_ULP_CLASS_HID_1b9db] = 737, + [BNXT_ULP_CLASS_HID_1bc9b] = 738, + [BNXT_ULP_CLASS_HID_1ff5b] = 739, + [BNXT_ULP_CLASS_HID_1e21b] = 740, + [BNXT_ULP_CLASS_HID_c7af] = 741, + [BNXT_ULP_CLASS_HID_ea6f] = 742, + [BNXT_ULP_CLASS_HID_cd2f] = 743, + [BNXT_ULP_CLASS_HID_efef] = 744, + [BNXT_ULP_CLASS_HID_c293] = 745, + [BNXT_ULP_CLASS_HID_e553] = 746, + [BNXT_ULP_CLASS_HID_c813] = 747, + [BNXT_ULP_CLASS_HID_ead3] = 748, + [BNXT_ULP_CLASS_HID_1d893] = 749, + [BNXT_ULP_CLASS_HID_1fb53] = 750, + [BNXT_ULP_CLASS_HID_1c147] = 751, + [BNXT_ULP_CLASS_HID_1e407] = 752, + [BNXT_ULP_CLASS_HID_18093] = 753, + [BNXT_ULP_CLASS_HID_1a353] = 754, + [BNXT_ULP_CLASS_HID_1c613] = 755, + [BNXT_ULP_CLASS_HID_1e8d3] = 756, + [BNXT_ULP_CLASS_HID_8e67] = 757, + [BNXT_ULP_CLASS_HID_b127] = 758, + [BNXT_ULP_CLASS_HID_d3e7] = 759, + [BNXT_ULP_CLASS_HID_f6a7] = 760, + [BNXT_ULP_CLASS_HID_89ab] = 761, + [BNXT_ULP_CLASS_HID_ac6b] = 762, + [BNXT_ULP_CLASS_HID_cf2b] = 763, + [BNXT_ULP_CLASS_HID_f1eb] = 764, + [BNXT_ULP_CLASS_HID_19fab] = 765, + [BNXT_ULP_CLASS_HID_1a26b] = 766, + [BNXT_ULP_CLASS_HID_1e52b] = 767, + [BNXT_ULP_CLASS_HID_1e7eb] = 768, + [BNXT_ULP_CLASS_HID_1a467] = 769, + [BNXT_ULP_CLASS_HID_1a727] = 770, + [BNXT_ULP_CLASS_HID_1e9e7] = 771, + [BNXT_ULP_CLASS_HID_1eca7] = 772, + [BNXT_ULP_CLASS_HID_b1cb] = 773, + [BNXT_ULP_CLASS_HID_b48b] = 774, + [BNXT_ULP_CLASS_HID_f74b] = 775, + [BNXT_ULP_CLASS_HID_fa0b] = 776, + [BNXT_ULP_CLASS_HID_ad3f] = 777, + [BNXT_ULP_CLASS_HID_afff] = 778, + [BNXT_ULP_CLASS_HID_f2bf] = 779, + [BNXT_ULP_CLASS_HID_f57f] = 780, + [BNXT_ULP_CLASS_HID_1c33f] = 781, + [BNXT_ULP_CLASS_HID_1e5ff] = 782, + [BNXT_ULP_CLASS_HID_1c8bf] = 783, + [BNXT_ULP_CLASS_HID_1eb7f] = 784, + [BNXT_ULP_CLASS_HID_1c7cb] = 785, + [BNXT_ULP_CLASS_HID_1ea8b] = 786, + [BNXT_ULP_CLASS_HID_1cd4b] = 787, + [BNXT_ULP_CLASS_HID_1f00b] = 788, + [BNXT_ULP_CLASS_HID_9117] = 789, + [BNXT_ULP_CLASS_HID_b3d7] = 790, + [BNXT_ULP_CLASS_HID_d697] = 791, + [BNXT_ULP_CLASS_HID_f957] = 792, + [BNXT_ULP_CLASS_HID_8c5b] = 793, + [BNXT_ULP_CLASS_HID_af1b] = 794, + [BNXT_ULP_CLASS_HID_d1db] = 795, + [BNXT_ULP_CLASS_HID_f49b] = 796, + [BNXT_ULP_CLASS_HID_1a25b] = 797, + [BNXT_ULP_CLASS_HID_1a51b] = 798, + [BNXT_ULP_CLASS_HID_1e7db] = 799, + [BNXT_ULP_CLASS_HID_1ea9b] = 800, + [BNXT_ULP_CLASS_HID_1a717] = 801, + [BNXT_ULP_CLASS_HID_1a9d7] = 802, + [BNXT_ULP_CLASS_HID_1ec97] = 803, + [BNXT_ULP_CLASS_HID_1ef57] = 804, + [BNXT_ULP_CLASS_HID_b4fb] = 805, + [BNXT_ULP_CLASS_HID_b7bb] = 806, + [BNXT_ULP_CLASS_HID_fa7b] = 807, + [BNXT_ULP_CLASS_HID_fd3b] = 808, + [BNXT_ULP_CLASS_HID_b02f] = 809, + [BNXT_ULP_CLASS_HID_b2ef] = 810, + [BNXT_ULP_CLASS_HID_f5af] = 811, + [BNXT_ULP_CLASS_HID_f86f] = 812, + [BNXT_ULP_CLASS_HID_1c62f] = 813, + [BNXT_ULP_CLASS_HID_1e8ef] = 814, + [BNXT_ULP_CLASS_HID_1cbaf] = 815, + [BNXT_ULP_CLASS_HID_1ee6f] = 816, + [BNXT_ULP_CLASS_HID_1cafb] = 817, + [BNXT_ULP_CLASS_HID_1edbb] = 818, + [BNXT_ULP_CLASS_HID_1d07b] = 819, + [BNXT_ULP_CLASS_HID_1f33b] = 820, + [BNXT_ULP_CLASS_HID_8b2b] = 821, + [BNXT_ULP_CLASS_HID_adeb] = 822, + [BNXT_ULP_CLASS_HID_d0ab] = 823, + [BNXT_ULP_CLASS_HID_f36b] = 824, + [BNXT_ULP_CLASS_HID_861f] = 825, + [BNXT_ULP_CLASS_HID_a8df] = 826, + [BNXT_ULP_CLASS_HID_cb9f] = 827, + [BNXT_ULP_CLASS_HID_ee5f] = 828, + [BNXT_ULP_CLASS_HID_19c1f] = 829, + [BNXT_ULP_CLASS_HID_1bedf] = 830, + [BNXT_ULP_CLASS_HID_1e19f] = 831, + [BNXT_ULP_CLASS_HID_1e45f] = 832, + [BNXT_ULP_CLASS_HID_1a12b] = 833, + [BNXT_ULP_CLASS_HID_1a3eb] = 834, + [BNXT_ULP_CLASS_HID_1e6ab] = 835, + [BNXT_ULP_CLASS_HID_1e96b] = 836, + [BNXT_ULP_CLASS_HID_aebf] = 837, + [BNXT_ULP_CLASS_HID_b17f] = 838, + [BNXT_ULP_CLASS_HID_f43f] = 839, + [BNXT_ULP_CLASS_HID_f6ff] = 840, + [BNXT_ULP_CLASS_HID_a9e3] = 841, + [BNXT_ULP_CLASS_HID_aca3] = 842, + [BNXT_ULP_CLASS_HID_ef63] = 843, + [BNXT_ULP_CLASS_HID_f223] = 844, + [BNXT_ULP_CLASS_HID_1bfe3] = 845, + [BNXT_ULP_CLASS_HID_1e2a3] = 846, + [BNXT_ULP_CLASS_HID_1c563] = 847, + [BNXT_ULP_CLASS_HID_1e823] = 848, + [BNXT_ULP_CLASS_HID_1c4bf] = 849, + [BNXT_ULP_CLASS_HID_1e77f] = 850, + [BNXT_ULP_CLASS_HID_1ca3f] = 851, + [BNXT_ULP_CLASS_HID_1ecff] = 852, + [BNXT_ULP_CLASS_HID_2543] = 853, + [BNXT_ULP_CLASS_HID_2b8f] = 854, + [BNXT_ULP_CLASS_HID_4f13] = 855, + [BNXT_ULP_CLASS_HID_162b] = 856, + [BNXT_ULP_CLASS_HID_39bf] = 857, + [BNXT_ULP_CLASS_HID_48d7] = 858, + [BNXT_ULP_CLASS_HID_0fef] = 859, + [BNXT_ULP_CLASS_HID_3373] = 860, + [BNXT_ULP_CLASS_HID_b6ef] = 861, + [BNXT_ULP_CLASS_HID_b92f] = 862, + [BNXT_ULP_CLASS_HID_fc6f] = 863, + [BNXT_ULP_CLASS_HID_feaf] = 864, + [BNXT_ULP_CLASS_HID_b193] = 865, + [BNXT_ULP_CLASS_HID_b4d3] = 866, + [BNXT_ULP_CLASS_HID_f713] = 867, + [BNXT_ULP_CLASS_HID_fa53] = 868, + [BNXT_ULP_CLASS_HID_1c793] = 869, + [BNXT_ULP_CLASS_HID_1ead3] = 870, + [BNXT_ULP_CLASS_HID_1cd13] = 871, + [BNXT_ULP_CLASS_HID_1f053] = 872, + [BNXT_ULP_CLASS_HID_1ccef] = 873, + [BNXT_ULP_CLASS_HID_1ef2f] = 874, + [BNXT_ULP_CLASS_HID_1d26f] = 875, + [BNXT_ULP_CLASS_HID_1f4af] = 876, + [BNXT_ULP_CLASS_HID_da73] = 877, + [BNXT_ULP_CLASS_HID_a067] = 878, + [BNXT_ULP_CLASS_HID_c2a7] = 879, + [BNXT_ULP_CLASS_HID_e5e7] = 880, + [BNXT_ULP_CLASS_HID_d527] = 881, + [BNXT_ULP_CLASS_HID_f867] = 882, + [BNXT_ULP_CLASS_HID_daa7] = 883, + [BNXT_ULP_CLASS_HID_e0ab] = 884, + [BNXT_ULP_CLASS_HID_18eeb] = 885, + [BNXT_ULP_CLASS_HID_1b12b] = 886, + [BNXT_ULP_CLASS_HID_1d46b] = 887, + [BNXT_ULP_CLASS_HID_1f6ab] = 888, + [BNXT_ULP_CLASS_HID_19327] = 889, + [BNXT_ULP_CLASS_HID_1b667] = 890, + [BNXT_ULP_CLASS_HID_1d8a7] = 891, + [BNXT_ULP_CLASS_HID_1fbe7] = 892, + [BNXT_ULP_CLASS_HID_a14b] = 893, + [BNXT_ULP_CLASS_HID_a38b] = 894, + [BNXT_ULP_CLASS_HID_e6cb] = 895, + [BNXT_ULP_CLASS_HID_e90b] = 896, + [BNXT_ULP_CLASS_HID_9c7f] = 897, + [BNXT_ULP_CLASS_HID_bebf] = 898, + [BNXT_ULP_CLASS_HID_e1ff] = 899, + [BNXT_ULP_CLASS_HID_e43f] = 900, + [BNXT_ULP_CLASS_HID_1b27f] = 901, + [BNXT_ULP_CLASS_HID_1b4bf] = 902, + [BNXT_ULP_CLASS_HID_1f7ff] = 903, + [BNXT_ULP_CLASS_HID_1fa3f] = 904, + [BNXT_ULP_CLASS_HID_1b74b] = 905, + [BNXT_ULP_CLASS_HID_1b98b] = 906, + [BNXT_ULP_CLASS_HID_1fccb] = 907, + [BNXT_ULP_CLASS_HID_1ff0b] = 908, + [BNXT_ULP_CLASS_HID_c4df] = 909, + [BNXT_ULP_CLASS_HID_e71f] = 910, + [BNXT_ULP_CLASS_HID_ca5f] = 911, + [BNXT_ULP_CLASS_HID_ec9f] = 912, + [BNXT_ULP_CLASS_HID_bf83] = 913, + [BNXT_ULP_CLASS_HID_e2c3] = 914, + [BNXT_ULP_CLASS_HID_c503] = 915, + [BNXT_ULP_CLASS_HID_e843] = 916, + [BNXT_ULP_CLASS_HID_1d583] = 917, + [BNXT_ULP_CLASS_HID_1f8c3] = 918, + [BNXT_ULP_CLASS_HID_1db03] = 919, + [BNXT_ULP_CLASS_HID_1e177] = 920, + [BNXT_ULP_CLASS_HID_1dadf] = 921, + [BNXT_ULP_CLASS_HID_1a0c3] = 922, + [BNXT_ULP_CLASS_HID_1c303] = 923, + [BNXT_ULP_CLASS_HID_1e643] = 924, + [BNXT_ULP_CLASS_HID_b023] = 925, + [BNXT_ULP_CLASS_HID_b363] = 926, + [BNXT_ULP_CLASS_HID_f5a3] = 927, + [BNXT_ULP_CLASS_HID_f8e3] = 928, + [BNXT_ULP_CLASS_HID_abd7] = 929, + [BNXT_ULP_CLASS_HID_ae17] = 930, + [BNXT_ULP_CLASS_HID_f157] = 931, + [BNXT_ULP_CLASS_HID_f397] = 932, + [BNXT_ULP_CLASS_HID_1c1d7] = 933, + [BNXT_ULP_CLASS_HID_1e417] = 934, + [BNXT_ULP_CLASS_HID_1c757] = 935, + [BNXT_ULP_CLASS_HID_1e997] = 936, + [BNXT_ULP_CLASS_HID_1c623] = 937, + [BNXT_ULP_CLASS_HID_1e963] = 938, + [BNXT_ULP_CLASS_HID_1cba3] = 939, + [BNXT_ULP_CLASS_HID_1eee3] = 940, + [BNXT_ULP_CLASS_HID_d3b7] = 941, + [BNXT_ULP_CLASS_HID_f6f7] = 942, + [BNXT_ULP_CLASS_HID_d937] = 943, + [BNXT_ULP_CLASS_HID_fc77] = 944, + [BNXT_ULP_CLASS_HID_cf7b] = 945, + [BNXT_ULP_CLASS_HID_f1bb] = 946, + [BNXT_ULP_CLASS_HID_d4fb] = 947, + [BNXT_ULP_CLASS_HID_f73b] = 948, + [BNXT_ULP_CLASS_HID_1882f] = 949, + [BNXT_ULP_CLASS_HID_1ab6f] = 950, + [BNXT_ULP_CLASS_HID_1cdaf] = 951, + [BNXT_ULP_CLASS_HID_1f0ef] = 952, + [BNXT_ULP_CLASS_HID_18d7b] = 953, + [BNXT_ULP_CLASS_HID_1afbb] = 954, + [BNXT_ULP_CLASS_HID_1d2fb] = 955, + [BNXT_ULP_CLASS_HID_1f53b] = 956, + [BNXT_ULP_CLASS_HID_9a8f] = 957, + [BNXT_ULP_CLASS_HID_bdcf] = 958, + [BNXT_ULP_CLASS_HID_e00f] = 959, + [BNXT_ULP_CLASS_HID_e34f] = 960, + [BNXT_ULP_CLASS_HID_95b3] = 961, + [BNXT_ULP_CLASS_HID_b8f3] = 962, + [BNXT_ULP_CLASS_HID_db33] = 963, + [BNXT_ULP_CLASS_HID_fe73] = 964, + [BNXT_ULP_CLASS_HID_1abb3] = 965, + [BNXT_ULP_CLASS_HID_1aef3] = 966, + [BNXT_ULP_CLASS_HID_1f133] = 967, + [BNXT_ULP_CLASS_HID_1f473] = 968, + [BNXT_ULP_CLASS_HID_1b08f] = 969, + [BNXT_ULP_CLASS_HID_1b3cf] = 970, + [BNXT_ULP_CLASS_HID_1f60f] = 971, + [BNXT_ULP_CLASS_HID_1f94f] = 972, + [BNXT_ULP_CLASS_HID_be13] = 973, + [BNXT_ULP_CLASS_HID_e153] = 974, + [BNXT_ULP_CLASS_HID_c393] = 975, + [BNXT_ULP_CLASS_HID_e6d3] = 976, + [BNXT_ULP_CLASS_HID_b9c7] = 977, + [BNXT_ULP_CLASS_HID_bc07] = 978, + [BNXT_ULP_CLASS_HID_ff47] = 979, + [BNXT_ULP_CLASS_HID_e187] = 980, + [BNXT_ULP_CLASS_HID_1cfc7] = 981, + [BNXT_ULP_CLASS_HID_1f207] = 982, + [BNXT_ULP_CLASS_HID_1d547] = 983, + [BNXT_ULP_CLASS_HID_1f787] = 984, + [BNXT_ULP_CLASS_HID_1d413] = 985, + [BNXT_ULP_CLASS_HID_1f753] = 986, + [BNXT_ULP_CLASS_HID_1d993] = 987, + [BNXT_ULP_CLASS_HID_1fcd3] = 988, + [BNXT_ULP_CLASS_HID_aa67] = 989, + [BNXT_ULP_CLASS_HID_aca7] = 990, + [BNXT_ULP_CLASS_HID_efe7] = 991, + [BNXT_ULP_CLASS_HID_f227] = 992, + [BNXT_ULP_CLASS_HID_a52b] = 993, + [BNXT_ULP_CLASS_HID_a86b] = 994, + [BNXT_ULP_CLASS_HID_eaab] = 995, + [BNXT_ULP_CLASS_HID_edeb] = 996, + [BNXT_ULP_CLASS_HID_1bb2b] = 997, + [BNXT_ULP_CLASS_HID_1be6b] = 998, + [BNXT_ULP_CLASS_HID_1c0ab] = 999, + [BNXT_ULP_CLASS_HID_1e3eb] = 1000, + [BNXT_ULP_CLASS_HID_1c067] = 1001, + [BNXT_ULP_CLASS_HID_1e2a7] = 1002, + [BNXT_ULP_CLASS_HID_1c5e7] = 1003, + [BNXT_ULP_CLASS_HID_1e827] = 1004, + [BNXT_ULP_CLASS_HID_cd8b] = 1005, + [BNXT_ULP_CLASS_HID_f0cb] = 1006, + [BNXT_ULP_CLASS_HID_d30b] = 1007, + [BNXT_ULP_CLASS_HID_f64b] = 1008, + [BNXT_ULP_CLASS_HID_c8bf] = 1009, + [BNXT_ULP_CLASS_HID_ebff] = 1010, + [BNXT_ULP_CLASS_HID_ce3f] = 1011, + [BNXT_ULP_CLASS_HID_f17f] = 1012, + [BNXT_ULP_CLASS_HID_18263] = 1013, + [BNXT_ULP_CLASS_HID_1a4a3] = 1014, + [BNXT_ULP_CLASS_HID_1c7e3] = 1015, + [BNXT_ULP_CLASS_HID_1ea23] = 1016, + [BNXT_ULP_CLASS_HID_186bf] = 1017, + [BNXT_ULP_CLASS_HID_1a9ff] = 1018, + [BNXT_ULP_CLASS_HID_1cc3f] = 1019, + [BNXT_ULP_CLASS_HID_1ef7f] = 1020, + [BNXT_ULP_CLASS_HID_94c3] = 1021, + [BNXT_ULP_CLASS_HID_b703] = 1022, + [BNXT_ULP_CLASS_HID_da43] = 1023, + [BNXT_ULP_CLASS_HID_fc83] = 1024, + [BNXT_ULP_CLASS_HID_8ff7] = 1025, + [BNXT_ULP_CLASS_HID_b237] = 1026, + [BNXT_ULP_CLASS_HID_d577] = 1027, + [BNXT_ULP_CLASS_HID_f7b7] = 1028, + [BNXT_ULP_CLASS_HID_1a5f7] = 1029, + [BNXT_ULP_CLASS_HID_1a837] = 1030, + [BNXT_ULP_CLASS_HID_1eb77] = 1031, + [BNXT_ULP_CLASS_HID_1edb7] = 1032, + [BNXT_ULP_CLASS_HID_1aac3] = 1033, + [BNXT_ULP_CLASS_HID_1ad03] = 1034, + [BNXT_ULP_CLASS_HID_1f043] = 1035, + [BNXT_ULP_CLASS_HID_1f283] = 1036, + [BNXT_ULP_CLASS_HID_b857] = 1037, + [BNXT_ULP_CLASS_HID_ba97] = 1038, + [BNXT_ULP_CLASS_HID_fdd7] = 1039, + [BNXT_ULP_CLASS_HID_e017] = 1040, + [BNXT_ULP_CLASS_HID_b31b] = 1041, + [BNXT_ULP_CLASS_HID_b65b] = 1042, + [BNXT_ULP_CLASS_HID_f89b] = 1043, + [BNXT_ULP_CLASS_HID_fbdb] = 1044, + [BNXT_ULP_CLASS_HID_1c91b] = 1045, + [BNXT_ULP_CLASS_HID_1ec5b] = 1046, + [BNXT_ULP_CLASS_HID_1ce9b] = 1047, + [BNXT_ULP_CLASS_HID_1f1db] = 1048, + [BNXT_ULP_CLASS_HID_1ce57] = 1049, + [BNXT_ULP_CLASS_HID_1f097] = 1050, + [BNXT_ULP_CLASS_HID_1d3d7] = 1051, + [BNXT_ULP_CLASS_HID_1f617] = 1052, + [BNXT_ULP_CLASS_HID_a3bb] = 1053, + [BNXT_ULP_CLASS_HID_a6fb] = 1054, + [BNXT_ULP_CLASS_HID_e93b] = 1055, + [BNXT_ULP_CLASS_HID_ec7b] = 1056, + [BNXT_ULP_CLASS_HID_9f6f] = 1057, + [BNXT_ULP_CLASS_HID_a1af] = 1058, + [BNXT_ULP_CLASS_HID_e4ef] = 1059, + [BNXT_ULP_CLASS_HID_e72f] = 1060, + [BNXT_ULP_CLASS_HID_1b56f] = 1061, + [BNXT_ULP_CLASS_HID_1b7af] = 1062, + [BNXT_ULP_CLASS_HID_1faef] = 1063, + [BNXT_ULP_CLASS_HID_1fd2f] = 1064, + [BNXT_ULP_CLASS_HID_1b9bb] = 1065, + [BNXT_ULP_CLASS_HID_1bcfb] = 1066, + [BNXT_ULP_CLASS_HID_1ff3b] = 1067, + [BNXT_ULP_CLASS_HID_1e27b] = 1068, + [BNXT_ULP_CLASS_HID_c7cf] = 1069, + [BNXT_ULP_CLASS_HID_ea0f] = 1070, + [BNXT_ULP_CLASS_HID_cd4f] = 1071, + [BNXT_ULP_CLASS_HID_ef8f] = 1072, + [BNXT_ULP_CLASS_HID_c2f3] = 1073, + [BNXT_ULP_CLASS_HID_e533] = 1074, + [BNXT_ULP_CLASS_HID_c873] = 1075, + [BNXT_ULP_CLASS_HID_eab3] = 1076, + [BNXT_ULP_CLASS_HID_1d8f3] = 1077, + [BNXT_ULP_CLASS_HID_1fb33] = 1078, + [BNXT_ULP_CLASS_HID_1c127] = 1079, + [BNXT_ULP_CLASS_HID_1e467] = 1080, + [BNXT_ULP_CLASS_HID_180f3] = 1081, + [BNXT_ULP_CLASS_HID_1a333] = 1082, + [BNXT_ULP_CLASS_HID_1c673] = 1083, + [BNXT_ULP_CLASS_HID_1e8b3] = 1084, + [BNXT_ULP_CLASS_HID_8e07] = 1085, + [BNXT_ULP_CLASS_HID_b147] = 1086, + [BNXT_ULP_CLASS_HID_d387] = 1087, + [BNXT_ULP_CLASS_HID_f6c7] = 1088, + [BNXT_ULP_CLASS_HID_89cb] = 1089, + [BNXT_ULP_CLASS_HID_ac0b] = 1090, + [BNXT_ULP_CLASS_HID_cf4b] = 1091, + [BNXT_ULP_CLASS_HID_f18b] = 1092, + [BNXT_ULP_CLASS_HID_19fcb] = 1093, + [BNXT_ULP_CLASS_HID_1a20b] = 1094, + [BNXT_ULP_CLASS_HID_1e54b] = 1095, + [BNXT_ULP_CLASS_HID_1e78b] = 1096, + [BNXT_ULP_CLASS_HID_1a407] = 1097, + [BNXT_ULP_CLASS_HID_1a747] = 1098, + [BNXT_ULP_CLASS_HID_1e987] = 1099, + [BNXT_ULP_CLASS_HID_1ecc7] = 1100, + [BNXT_ULP_CLASS_HID_b1ab] = 1101, + [BNXT_ULP_CLASS_HID_b4eb] = 1102, + [BNXT_ULP_CLASS_HID_f72b] = 1103, + [BNXT_ULP_CLASS_HID_fa6b] = 1104, + [BNXT_ULP_CLASS_HID_ad5f] = 1105, + [BNXT_ULP_CLASS_HID_af9f] = 1106, + [BNXT_ULP_CLASS_HID_f2df] = 1107, + [BNXT_ULP_CLASS_HID_f51f] = 1108, + [BNXT_ULP_CLASS_HID_1c35f] = 1109, + [BNXT_ULP_CLASS_HID_1e59f] = 1110, + [BNXT_ULP_CLASS_HID_1c8df] = 1111, + [BNXT_ULP_CLASS_HID_1eb1f] = 1112, + [BNXT_ULP_CLASS_HID_1c7ab] = 1113, + [BNXT_ULP_CLASS_HID_1eaeb] = 1114, + [BNXT_ULP_CLASS_HID_1cd2b] = 1115, + [BNXT_ULP_CLASS_HID_1f06b] = 1116, + [BNXT_ULP_CLASS_HID_9177] = 1117, + [BNXT_ULP_CLASS_HID_b3b7] = 1118, + [BNXT_ULP_CLASS_HID_d6f7] = 1119, + [BNXT_ULP_CLASS_HID_f937] = 1120, + [BNXT_ULP_CLASS_HID_8c3b] = 1121, + [BNXT_ULP_CLASS_HID_af7b] = 1122, + [BNXT_ULP_CLASS_HID_d1bb] = 1123, + [BNXT_ULP_CLASS_HID_f4fb] = 1124, + [BNXT_ULP_CLASS_HID_1a23b] = 1125, + [BNXT_ULP_CLASS_HID_1a57b] = 1126, + [BNXT_ULP_CLASS_HID_1e7bb] = 1127, + [BNXT_ULP_CLASS_HID_1eafb] = 1128, + [BNXT_ULP_CLASS_HID_1a777] = 1129, + [BNXT_ULP_CLASS_HID_1a9b7] = 1130, + [BNXT_ULP_CLASS_HID_1ecf7] = 1131, + [BNXT_ULP_CLASS_HID_1ef37] = 1132, + [BNXT_ULP_CLASS_HID_b49b] = 1133, + [BNXT_ULP_CLASS_HID_b7db] = 1134, + [BNXT_ULP_CLASS_HID_fa1b] = 1135, + [BNXT_ULP_CLASS_HID_fd5b] = 1136, + [BNXT_ULP_CLASS_HID_b04f] = 1137, + [BNXT_ULP_CLASS_HID_b28f] = 1138, + [BNXT_ULP_CLASS_HID_f5cf] = 1139, + [BNXT_ULP_CLASS_HID_f80f] = 1140, + [BNXT_ULP_CLASS_HID_1c64f] = 1141, + [BNXT_ULP_CLASS_HID_1e88f] = 1142, + [BNXT_ULP_CLASS_HID_1cbcf] = 1143, + [BNXT_ULP_CLASS_HID_1ee0f] = 1144, + [BNXT_ULP_CLASS_HID_1ca9b] = 1145, + [BNXT_ULP_CLASS_HID_1eddb] = 1146, + [BNXT_ULP_CLASS_HID_1d01b] = 1147, + [BNXT_ULP_CLASS_HID_1f35b] = 1148, + [BNXT_ULP_CLASS_HID_8b4b] = 1149, + [BNXT_ULP_CLASS_HID_ad8b] = 1150, + [BNXT_ULP_CLASS_HID_d0cb] = 1151, + [BNXT_ULP_CLASS_HID_f30b] = 1152, + [BNXT_ULP_CLASS_HID_867f] = 1153, + [BNXT_ULP_CLASS_HID_a8bf] = 1154, + [BNXT_ULP_CLASS_HID_cbff] = 1155, + [BNXT_ULP_CLASS_HID_ee3f] = 1156, + [BNXT_ULP_CLASS_HID_19c7f] = 1157, + [BNXT_ULP_CLASS_HID_1bebf] = 1158, + [BNXT_ULP_CLASS_HID_1e1ff] = 1159, + [BNXT_ULP_CLASS_HID_1e43f] = 1160, + [BNXT_ULP_CLASS_HID_1a14b] = 1161, + [BNXT_ULP_CLASS_HID_1a38b] = 1162, + [BNXT_ULP_CLASS_HID_1e6cb] = 1163, + [BNXT_ULP_CLASS_HID_1e90b] = 1164, + [BNXT_ULP_CLASS_HID_aedf] = 1165, + [BNXT_ULP_CLASS_HID_b11f] = 1166, + [BNXT_ULP_CLASS_HID_f45f] = 1167, + [BNXT_ULP_CLASS_HID_f69f] = 1168, + [BNXT_ULP_CLASS_HID_a983] = 1169, + [BNXT_ULP_CLASS_HID_acc3] = 1170, + [BNXT_ULP_CLASS_HID_ef03] = 1171, + [BNXT_ULP_CLASS_HID_f243] = 1172, + [BNXT_ULP_CLASS_HID_1bf83] = 1173, + [BNXT_ULP_CLASS_HID_1e2c3] = 1174, + [BNXT_ULP_CLASS_HID_1c503] = 1175, + [BNXT_ULP_CLASS_HID_1e843] = 1176, + [BNXT_ULP_CLASS_HID_1c4df] = 1177, + [BNXT_ULP_CLASS_HID_1e71f] = 1178, + [BNXT_ULP_CLASS_HID_1ca5f] = 1179, + [BNXT_ULP_CLASS_HID_1ec9f] = 1180, + [BNXT_ULP_CLASS_HID_2523] = 1181, + [BNXT_ULP_CLASS_HID_2bef] = 1182, + [BNXT_ULP_CLASS_HID_4f73] = 1183, + [BNXT_ULP_CLASS_HID_164b] = 1184, + [BNXT_ULP_CLASS_HID_39df] = 1185, + [BNXT_ULP_CLASS_HID_48b7] = 1186, + [BNXT_ULP_CLASS_HID_0f8f] = 1187, + [BNXT_ULP_CLASS_HID_3313] = 1188, + [BNXT_ULP_CLASS_HID_257b7] = 1189, + [BNXT_ULP_CLASS_HID_24467] = 1190, + [BNXT_ULP_CLASS_HID_23fbb] = 1191, + [BNXT_ULP_CLASS_HID_252cb] = 1192, + [BNXT_ULP_CLASS_HID_21e7f] = 1193, + [BNXT_ULP_CLASS_HID_20b2f] = 1194, + [BNXT_ULP_CLASS_HID_20663] = 1195, + [BNXT_ULP_CLASS_HID_219b3] = 1196, + [BNXT_ULP_CLASS_HID_24213] = 1197, + [BNXT_ULP_CLASS_HID_22ec3] = 1198, + [BNXT_ULP_CLASS_HID_22a17] = 1199, + [BNXT_ULP_CLASS_HID_23d27] = 1200, + [BNXT_ULP_CLASS_HID_208db] = 1201, + [BNXT_ULP_CLASS_HID_25277] = 1202, + [BNXT_ULP_CLASS_HID_24d8b] = 1203, + [BNXT_ULP_CLASS_HID_203ef] = 1204, + [BNXT_ULP_CLASS_HID_2517b] = 1205, + [BNXT_ULP_CLASS_HID_23e2b] = 1206, + [BNXT_ULP_CLASS_HID_2397f] = 1207, + [BNXT_ULP_CLASS_HID_24c8f] = 1208, + [BNXT_ULP_CLASS_HID_21823] = 1209, + [BNXT_ULP_CLASS_HID_20513] = 1210, + [BNXT_ULP_CLASS_HID_20027] = 1211, + [BNXT_ULP_CLASS_HID_21377] = 1212, + [BNXT_ULP_CLASS_HID_23bd7] = 1213, + [BNXT_ULP_CLASS_HID_22887] = 1214, + [BNXT_ULP_CLASS_HID_223db] = 1215, + [BNXT_ULP_CLASS_HID_236eb] = 1216, + [BNXT_ULP_CLASS_HID_2029f] = 1217, + [BNXT_ULP_CLASS_HID_24c3b] = 1218, + [BNXT_ULP_CLASS_HID_2474f] = 1219, + [BNXT_ULP_CLASS_HID_25a9f] = 1220, + [BNXT_ULP_CLASS_HID_24b3f] = 1221, + [BNXT_ULP_CLASS_HID_237ef] = 1222, + [BNXT_ULP_CLASS_HID_23323] = 1223, + [BNXT_ULP_CLASS_HID_24673] = 1224, + [BNXT_ULP_CLASS_HID_211e7] = 1225, + [BNXT_ULP_CLASS_HID_25b83] = 1226, + [BNXT_ULP_CLASS_HID_256d7] = 1227, + [BNXT_ULP_CLASS_HID_20d3b] = 1228, + [BNXT_ULP_CLASS_HID_2359b] = 1229, + [BNXT_ULP_CLASS_HID_2224b] = 1230, + [BNXT_ULP_CLASS_HID_21d9f] = 1231, + [BNXT_ULP_CLASS_HID_230af] = 1232, + [BNXT_ULP_CLASS_HID_2590f] = 1233, + [BNXT_ULP_CLASS_HID_245ff] = 1234, + [BNXT_ULP_CLASS_HID_24133] = 1235, + [BNXT_ULP_CLASS_HID_25443] = 1236, + [BNXT_ULP_CLASS_HID_244e3] = 1237, + [BNXT_ULP_CLASS_HID_231d3] = 1238, + [BNXT_ULP_CLASS_HID_22ce7] = 1239, + [BNXT_ULP_CLASS_HID_24037] = 1240, + [BNXT_ULP_CLASS_HID_20bab] = 1241, + [BNXT_ULP_CLASS_HID_25547] = 1242, + [BNXT_ULP_CLASS_HID_2509b] = 1243, + [BNXT_ULP_CLASS_HID_206ff] = 1244, + [BNXT_ULP_CLASS_HID_22f5f] = 1245, + [BNXT_ULP_CLASS_HID_21c0f] = 1246, + [BNXT_ULP_CLASS_HID_21743] = 1247, + [BNXT_ULP_CLASS_HID_22a93] = 1248, + [BNXT_ULP_CLASS_HID_252f3] = 1249, + [BNXT_ULP_CLASS_HID_23fa3] = 1250, + [BNXT_ULP_CLASS_HID_23af7] = 1251, + [BNXT_ULP_CLASS_HID_24e07] = 1252, + [BNXT_ULP_CLASS_HID_2322f] = 1253, + [BNXT_ULP_CLASS_HID_21f1f] = 1254, + [BNXT_ULP_CLASS_HID_21a53] = 1255, + [BNXT_ULP_CLASS_HID_22d63] = 1256, + [BNXT_ULP_CLASS_HID_255c3] = 1257, + [BNXT_ULP_CLASS_HID_242b3] = 1258, + [BNXT_ULP_CLASS_HID_23dc7] = 1259, + [BNXT_ULP_CLASS_HID_25117] = 1260, + [BNXT_ULP_CLASS_HID_22c13] = 1261, + [BNXT_ULP_CLASS_HID_218c3] = 1262, + [BNXT_ULP_CLASS_HID_21417] = 1263, + [BNXT_ULP_CLASS_HID_22727] = 1264, + [BNXT_ULP_CLASS_HID_24f87] = 1265, + [BNXT_ULP_CLASS_HID_23c77] = 1266, + [BNXT_ULP_CLASS_HID_2378b] = 1267, + [BNXT_ULP_CLASS_HID_24adb] = 1268, + [BNXT_ULP_CLASS_HID_257b] = 1269, + [BNXT_ULP_CLASS_HID_2bb7] = 1270, + [BNXT_ULP_CLASS_HID_4f2b] = 1271, + [BNXT_ULP_CLASS_HID_1613] = 1272, + [BNXT_ULP_CLASS_HID_3987] = 1273, + [BNXT_ULP_CLASS_HID_48ef] = 1274, + [BNXT_ULP_CLASS_HID_0fd7] = 1275, + [BNXT_ULP_CLASS_HID_334b] = 1276, + [BNXT_ULP_CLASS_HID_25797] = 1277, + [BNXT_ULP_CLASS_HID_285eb] = 1278, + [BNXT_ULP_CLASS_HID_310eb] = 1279, + [BNXT_ULP_CLASS_HID_39beb] = 1280, + [BNXT_ULP_CLASS_HID_24447] = 1281, + [BNXT_ULP_CLASS_HID_2cf47] = 1282, + [BNXT_ULP_CLASS_HID_35a47] = 1283, + [BNXT_ULP_CLASS_HID_3889b] = 1284, + [BNXT_ULP_CLASS_HID_23f9b] = 1285, + [BNXT_ULP_CLASS_HID_2ca9b] = 1286, + [BNXT_ULP_CLASS_HID_3559b] = 1287, + [BNXT_ULP_CLASS_HID_383ef] = 1288, + [BNXT_ULP_CLASS_HID_252eb] = 1289, + [BNXT_ULP_CLASS_HID_2813f] = 1290, + [BNXT_ULP_CLASS_HID_30c3f] = 1291, + [BNXT_ULP_CLASS_HID_3973f] = 1292, + [BNXT_ULP_CLASS_HID_21e5f] = 1293, + [BNXT_ULP_CLASS_HID_2a95f] = 1294, + [BNXT_ULP_CLASS_HID_3345f] = 1295, + [BNXT_ULP_CLASS_HID_3bf5f] = 1296, + [BNXT_ULP_CLASS_HID_20b0f] = 1297, + [BNXT_ULP_CLASS_HID_2960f] = 1298, + [BNXT_ULP_CLASS_HID_3210f] = 1299, + [BNXT_ULP_CLASS_HID_3ac0f] = 1300, + [BNXT_ULP_CLASS_HID_20643] = 1301, + [BNXT_ULP_CLASS_HID_29143] = 1302, + [BNXT_ULP_CLASS_HID_31c43] = 1303, + [BNXT_ULP_CLASS_HID_3a743] = 1304, + [BNXT_ULP_CLASS_HID_21993] = 1305, + [BNXT_ULP_CLASS_HID_2a493] = 1306, + [BNXT_ULP_CLASS_HID_32f93] = 1307, + [BNXT_ULP_CLASS_HID_3ba93] = 1308, + [BNXT_ULP_CLASS_HID_24233] = 1309, + [BNXT_ULP_CLASS_HID_2cd33] = 1310, + [BNXT_ULP_CLASS_HID_35833] = 1311, + [BNXT_ULP_CLASS_HID_38607] = 1312, + [BNXT_ULP_CLASS_HID_22ee3] = 1313, + [BNXT_ULP_CLASS_HID_2b9e3] = 1314, + [BNXT_ULP_CLASS_HID_344e3] = 1315, + [BNXT_ULP_CLASS_HID_3cfe3] = 1316, + [BNXT_ULP_CLASS_HID_22a37] = 1317, + [BNXT_ULP_CLASS_HID_2b537] = 1318, + [BNXT_ULP_CLASS_HID_34037] = 1319, + [BNXT_ULP_CLASS_HID_3cb37] = 1320, + [BNXT_ULP_CLASS_HID_23d07] = 1321, + [BNXT_ULP_CLASS_HID_2c807] = 1322, + [BNXT_ULP_CLASS_HID_35307] = 1323, + [BNXT_ULP_CLASS_HID_3815b] = 1324, + [BNXT_ULP_CLASS_HID_208fb] = 1325, + [BNXT_ULP_CLASS_HID_293fb] = 1326, + [BNXT_ULP_CLASS_HID_31efb] = 1327, + [BNXT_ULP_CLASS_HID_3a9fb] = 1328, + [BNXT_ULP_CLASS_HID_25257] = 1329, + [BNXT_ULP_CLASS_HID_280ab] = 1330, + [BNXT_ULP_CLASS_HID_30bab] = 1331, + [BNXT_ULP_CLASS_HID_396ab] = 1332, + [BNXT_ULP_CLASS_HID_24dab] = 1333, + [BNXT_ULP_CLASS_HID_2d8ab] = 1334, + [BNXT_ULP_CLASS_HID_306ff] = 1335, + [BNXT_ULP_CLASS_HID_391ff] = 1336, + [BNXT_ULP_CLASS_HID_203cf] = 1337, + [BNXT_ULP_CLASS_HID_28ecf] = 1338, + [BNXT_ULP_CLASS_HID_319cf] = 1339, + [BNXT_ULP_CLASS_HID_3a4cf] = 1340, + [BNXT_ULP_CLASS_HID_2515b] = 1341, + [BNXT_ULP_CLASS_HID_2dc5b] = 1342, + [BNXT_ULP_CLASS_HID_30aaf] = 1343, + [BNXT_ULP_CLASS_HID_395af] = 1344, + [BNXT_ULP_CLASS_HID_23e0b] = 1345, + [BNXT_ULP_CLASS_HID_2c90b] = 1346, + [BNXT_ULP_CLASS_HID_3540b] = 1347, + [BNXT_ULP_CLASS_HID_3825f] = 1348, + [BNXT_ULP_CLASS_HID_2395f] = 1349, + [BNXT_ULP_CLASS_HID_2c45f] = 1350, + [BNXT_ULP_CLASS_HID_34f5f] = 1351, + [BNXT_ULP_CLASS_HID_3da5f] = 1352, + [BNXT_ULP_CLASS_HID_24caf] = 1353, + [BNXT_ULP_CLASS_HID_2d7af] = 1354, + [BNXT_ULP_CLASS_HID_305e3] = 1355, + [BNXT_ULP_CLASS_HID_390e3] = 1356, + [BNXT_ULP_CLASS_HID_21803] = 1357, + [BNXT_ULP_CLASS_HID_2a303] = 1358, + [BNXT_ULP_CLASS_HID_32e03] = 1359, + [BNXT_ULP_CLASS_HID_3b903] = 1360, + [BNXT_ULP_CLASS_HID_20533] = 1361, + [BNXT_ULP_CLASS_HID_29033] = 1362, + [BNXT_ULP_CLASS_HID_31b33] = 1363, + [BNXT_ULP_CLASS_HID_3a633] = 1364, + [BNXT_ULP_CLASS_HID_20007] = 1365, + [BNXT_ULP_CLASS_HID_28b07] = 1366, + [BNXT_ULP_CLASS_HID_31607] = 1367, + [BNXT_ULP_CLASS_HID_3a107] = 1368, + [BNXT_ULP_CLASS_HID_21357] = 1369, + [BNXT_ULP_CLASS_HID_29e57] = 1370, + [BNXT_ULP_CLASS_HID_32957] = 1371, + [BNXT_ULP_CLASS_HID_3b457] = 1372, + [BNXT_ULP_CLASS_HID_23bf7] = 1373, + [BNXT_ULP_CLASS_HID_2c6f7] = 1374, + [BNXT_ULP_CLASS_HID_351f7] = 1375, + [BNXT_ULP_CLASS_HID_3dcf7] = 1376, + [BNXT_ULP_CLASS_HID_228a7] = 1377, + [BNXT_ULP_CLASS_HID_2b3a7] = 1378, + [BNXT_ULP_CLASS_HID_33ea7] = 1379, + [BNXT_ULP_CLASS_HID_3c9a7] = 1380, + [BNXT_ULP_CLASS_HID_223fb] = 1381, + [BNXT_ULP_CLASS_HID_2aefb] = 1382, + [BNXT_ULP_CLASS_HID_339fb] = 1383, + [BNXT_ULP_CLASS_HID_3c4fb] = 1384, + [BNXT_ULP_CLASS_HID_236cb] = 1385, + [BNXT_ULP_CLASS_HID_2c1cb] = 1386, + [BNXT_ULP_CLASS_HID_34ccb] = 1387, + [BNXT_ULP_CLASS_HID_3d7cb] = 1388, + [BNXT_ULP_CLASS_HID_202bf] = 1389, + [BNXT_ULP_CLASS_HID_28dbf] = 1390, + [BNXT_ULP_CLASS_HID_318bf] = 1391, + [BNXT_ULP_CLASS_HID_3a3bf] = 1392, + [BNXT_ULP_CLASS_HID_24c1b] = 1393, + [BNXT_ULP_CLASS_HID_2d71b] = 1394, + [BNXT_ULP_CLASS_HID_3056f] = 1395, + [BNXT_ULP_CLASS_HID_3906f] = 1396, + [BNXT_ULP_CLASS_HID_2476f] = 1397, + [BNXT_ULP_CLASS_HID_2d26f] = 1398, + [BNXT_ULP_CLASS_HID_300a3] = 1399, + [BNXT_ULP_CLASS_HID_38ba3] = 1400, + [BNXT_ULP_CLASS_HID_25abf] = 1401, + [BNXT_ULP_CLASS_HID_288f3] = 1402, + [BNXT_ULP_CLASS_HID_313f3] = 1403, + [BNXT_ULP_CLASS_HID_39ef3] = 1404, + [BNXT_ULP_CLASS_HID_24b1f] = 1405, + [BNXT_ULP_CLASS_HID_2d61f] = 1406, + [BNXT_ULP_CLASS_HID_30453] = 1407, + [BNXT_ULP_CLASS_HID_38f53] = 1408, + [BNXT_ULP_CLASS_HID_237cf] = 1409, + [BNXT_ULP_CLASS_HID_2c2cf] = 1410, + [BNXT_ULP_CLASS_HID_34dcf] = 1411, + [BNXT_ULP_CLASS_HID_3d8cf] = 1412, + [BNXT_ULP_CLASS_HID_23303] = 1413, + [BNXT_ULP_CLASS_HID_2be03] = 1414, + [BNXT_ULP_CLASS_HID_34903] = 1415, + [BNXT_ULP_CLASS_HID_3d403] = 1416, + [BNXT_ULP_CLASS_HID_24653] = 1417, + [BNXT_ULP_CLASS_HID_2d153] = 1418, + [BNXT_ULP_CLASS_HID_35c53] = 1419, + [BNXT_ULP_CLASS_HID_38aa7] = 1420, + [BNXT_ULP_CLASS_HID_211c7] = 1421, + [BNXT_ULP_CLASS_HID_29cc7] = 1422, + [BNXT_ULP_CLASS_HID_327c7] = 1423, + [BNXT_ULP_CLASS_HID_3b2c7] = 1424, + [BNXT_ULP_CLASS_HID_25ba3] = 1425, + [BNXT_ULP_CLASS_HID_289f7] = 1426, + [BNXT_ULP_CLASS_HID_314f7] = 1427, + [BNXT_ULP_CLASS_HID_39ff7] = 1428, + [BNXT_ULP_CLASS_HID_256f7] = 1429, + [BNXT_ULP_CLASS_HID_284cb] = 1430, + [BNXT_ULP_CLASS_HID_30fcb] = 1431, + [BNXT_ULP_CLASS_HID_39acb] = 1432, + [BNXT_ULP_CLASS_HID_20d1b] = 1433, + [BNXT_ULP_CLASS_HID_2981b] = 1434, + [BNXT_ULP_CLASS_HID_3231b] = 1435, + [BNXT_ULP_CLASS_HID_3ae1b] = 1436, + [BNXT_ULP_CLASS_HID_235bb] = 1437, + [BNXT_ULP_CLASS_HID_2c0bb] = 1438, + [BNXT_ULP_CLASS_HID_34bbb] = 1439, + [BNXT_ULP_CLASS_HID_3d6bb] = 1440, + [BNXT_ULP_CLASS_HID_2226b] = 1441, + [BNXT_ULP_CLASS_HID_2ad6b] = 1442, + [BNXT_ULP_CLASS_HID_3386b] = 1443, + [BNXT_ULP_CLASS_HID_3c36b] = 1444, + [BNXT_ULP_CLASS_HID_21dbf] = 1445, + [BNXT_ULP_CLASS_HID_2a8bf] = 1446, + [BNXT_ULP_CLASS_HID_333bf] = 1447, + [BNXT_ULP_CLASS_HID_3bebf] = 1448, + [BNXT_ULP_CLASS_HID_2308f] = 1449, + [BNXT_ULP_CLASS_HID_2bb8f] = 1450, + [BNXT_ULP_CLASS_HID_3468f] = 1451, + [BNXT_ULP_CLASS_HID_3d18f] = 1452, + [BNXT_ULP_CLASS_HID_2592f] = 1453, + [BNXT_ULP_CLASS_HID_28763] = 1454, + [BNXT_ULP_CLASS_HID_31263] = 1455, + [BNXT_ULP_CLASS_HID_39d63] = 1456, + [BNXT_ULP_CLASS_HID_245df] = 1457, + [BNXT_ULP_CLASS_HID_2d0df] = 1458, + [BNXT_ULP_CLASS_HID_35bdf] = 1459, + [BNXT_ULP_CLASS_HID_38a13] = 1460, + [BNXT_ULP_CLASS_HID_24113] = 1461, + [BNXT_ULP_CLASS_HID_2cc13] = 1462, + [BNXT_ULP_CLASS_HID_35713] = 1463, + [BNXT_ULP_CLASS_HID_38567] = 1464, + [BNXT_ULP_CLASS_HID_25463] = 1465, + [BNXT_ULP_CLASS_HID_282b7] = 1466, + [BNXT_ULP_CLASS_HID_30db7] = 1467, + [BNXT_ULP_CLASS_HID_398b7] = 1468, + [BNXT_ULP_CLASS_HID_244c3] = 1469, + [BNXT_ULP_CLASS_HID_2cfc3] = 1470, + [BNXT_ULP_CLASS_HID_35ac3] = 1471, + [BNXT_ULP_CLASS_HID_38917] = 1472, + [BNXT_ULP_CLASS_HID_231f3] = 1473, + [BNXT_ULP_CLASS_HID_2bcf3] = 1474, + [BNXT_ULP_CLASS_HID_347f3] = 1475, + [BNXT_ULP_CLASS_HID_3d2f3] = 1476, + [BNXT_ULP_CLASS_HID_22cc7] = 1477, + [BNXT_ULP_CLASS_HID_2b7c7] = 1478, + [BNXT_ULP_CLASS_HID_342c7] = 1479, + [BNXT_ULP_CLASS_HID_3cdc7] = 1480, + [BNXT_ULP_CLASS_HID_24017] = 1481, + [BNXT_ULP_CLASS_HID_2cb17] = 1482, + [BNXT_ULP_CLASS_HID_35617] = 1483, + [BNXT_ULP_CLASS_HID_3846b] = 1484, + [BNXT_ULP_CLASS_HID_20b8b] = 1485, + [BNXT_ULP_CLASS_HID_2968b] = 1486, + [BNXT_ULP_CLASS_HID_3218b] = 1487, + [BNXT_ULP_CLASS_HID_3ac8b] = 1488, + [BNXT_ULP_CLASS_HID_25567] = 1489, + [BNXT_ULP_CLASS_HID_283bb] = 1490, + [BNXT_ULP_CLASS_HID_30ebb] = 1491, + [BNXT_ULP_CLASS_HID_399bb] = 1492, + [BNXT_ULP_CLASS_HID_250bb] = 1493, + [BNXT_ULP_CLASS_HID_2dbbb] = 1494, + [BNXT_ULP_CLASS_HID_3098f] = 1495, + [BNXT_ULP_CLASS_HID_3948f] = 1496, + [BNXT_ULP_CLASS_HID_206df] = 1497, + [BNXT_ULP_CLASS_HID_291df] = 1498, + [BNXT_ULP_CLASS_HID_31cdf] = 1499, + [BNXT_ULP_CLASS_HID_3a7df] = 1500, + [BNXT_ULP_CLASS_HID_22f7f] = 1501, + [BNXT_ULP_CLASS_HID_2ba7f] = 1502, + [BNXT_ULP_CLASS_HID_3457f] = 1503, + [BNXT_ULP_CLASS_HID_3d07f] = 1504, + [BNXT_ULP_CLASS_HID_21c2f] = 1505, + [BNXT_ULP_CLASS_HID_2a72f] = 1506, + [BNXT_ULP_CLASS_HID_3322f] = 1507, + [BNXT_ULP_CLASS_HID_3bd2f] = 1508, + [BNXT_ULP_CLASS_HID_21763] = 1509, + [BNXT_ULP_CLASS_HID_2a263] = 1510, + [BNXT_ULP_CLASS_HID_32d63] = 1511, + [BNXT_ULP_CLASS_HID_3b863] = 1512, + [BNXT_ULP_CLASS_HID_22ab3] = 1513, + [BNXT_ULP_CLASS_HID_2b5b3] = 1514, + [BNXT_ULP_CLASS_HID_340b3] = 1515, + [BNXT_ULP_CLASS_HID_3cbb3] = 1516, + [BNXT_ULP_CLASS_HID_252d3] = 1517, + [BNXT_ULP_CLASS_HID_28127] = 1518, + [BNXT_ULP_CLASS_HID_30c27] = 1519, + [BNXT_ULP_CLASS_HID_39727] = 1520, + [BNXT_ULP_CLASS_HID_23f83] = 1521, + [BNXT_ULP_CLASS_HID_2ca83] = 1522, + [BNXT_ULP_CLASS_HID_35583] = 1523, + [BNXT_ULP_CLASS_HID_383d7] = 1524, + [BNXT_ULP_CLASS_HID_23ad7] = 1525, + [BNXT_ULP_CLASS_HID_2c5d7] = 1526, + [BNXT_ULP_CLASS_HID_350d7] = 1527, + [BNXT_ULP_CLASS_HID_3dbd7] = 1528, + [BNXT_ULP_CLASS_HID_24e27] = 1529, + [BNXT_ULP_CLASS_HID_2d927] = 1530, + [BNXT_ULP_CLASS_HID_3077b] = 1531, + [BNXT_ULP_CLASS_HID_3927b] = 1532, + [BNXT_ULP_CLASS_HID_2320f] = 1533, + [BNXT_ULP_CLASS_HID_2bd0f] = 1534, + [BNXT_ULP_CLASS_HID_3480f] = 1535, + [BNXT_ULP_CLASS_HID_3d30f] = 1536, + [BNXT_ULP_CLASS_HID_21f3f] = 1537, + [BNXT_ULP_CLASS_HID_2aa3f] = 1538, + [BNXT_ULP_CLASS_HID_3353f] = 1539, + [BNXT_ULP_CLASS_HID_3c03f] = 1540, + [BNXT_ULP_CLASS_HID_21a73] = 1541, + [BNXT_ULP_CLASS_HID_2a573] = 1542, + [BNXT_ULP_CLASS_HID_33073] = 1543, + [BNXT_ULP_CLASS_HID_3bb73] = 1544, + [BNXT_ULP_CLASS_HID_22d43] = 1545, + [BNXT_ULP_CLASS_HID_2b843] = 1546, + [BNXT_ULP_CLASS_HID_34343] = 1547, + [BNXT_ULP_CLASS_HID_3ce43] = 1548, + [BNXT_ULP_CLASS_HID_255e3] = 1549, + [BNXT_ULP_CLASS_HID_28437] = 1550, + [BNXT_ULP_CLASS_HID_30f37] = 1551, + [BNXT_ULP_CLASS_HID_39a37] = 1552, + [BNXT_ULP_CLASS_HID_24293] = 1553, + [BNXT_ULP_CLASS_HID_2cd93] = 1554, + [BNXT_ULP_CLASS_HID_35893] = 1555, + [BNXT_ULP_CLASS_HID_386e7] = 1556, + [BNXT_ULP_CLASS_HID_23de7] = 1557, + [BNXT_ULP_CLASS_HID_2c8e7] = 1558, + [BNXT_ULP_CLASS_HID_353e7] = 1559, + [BNXT_ULP_CLASS_HID_3823b] = 1560, + [BNXT_ULP_CLASS_HID_25137] = 1561, + [BNXT_ULP_CLASS_HID_2dc37] = 1562, + [BNXT_ULP_CLASS_HID_30a0b] = 1563, + [BNXT_ULP_CLASS_HID_3950b] = 1564, + [BNXT_ULP_CLASS_HID_22c33] = 1565, + [BNXT_ULP_CLASS_HID_2b733] = 1566, + [BNXT_ULP_CLASS_HID_34233] = 1567, + [BNXT_ULP_CLASS_HID_3cd33] = 1568, + [BNXT_ULP_CLASS_HID_218e3] = 1569, + [BNXT_ULP_CLASS_HID_2a3e3] = 1570, + [BNXT_ULP_CLASS_HID_32ee3] = 1571, + [BNXT_ULP_CLASS_HID_3b9e3] = 1572, + [BNXT_ULP_CLASS_HID_21437] = 1573, + [BNXT_ULP_CLASS_HID_29f37] = 1574, + [BNXT_ULP_CLASS_HID_32a37] = 1575, + [BNXT_ULP_CLASS_HID_3b537] = 1576, + [BNXT_ULP_CLASS_HID_22707] = 1577, + [BNXT_ULP_CLASS_HID_2b207] = 1578, + [BNXT_ULP_CLASS_HID_33d07] = 1579, + [BNXT_ULP_CLASS_HID_3c807] = 1580, + [BNXT_ULP_CLASS_HID_24fa7] = 1581, + [BNXT_ULP_CLASS_HID_2daa7] = 1582, + [BNXT_ULP_CLASS_HID_308fb] = 1583, + [BNXT_ULP_CLASS_HID_393fb] = 1584, + [BNXT_ULP_CLASS_HID_23c57] = 1585, + [BNXT_ULP_CLASS_HID_2c757] = 1586, + [BNXT_ULP_CLASS_HID_35257] = 1587, + [BNXT_ULP_CLASS_HID_380ab] = 1588, + [BNXT_ULP_CLASS_HID_237ab] = 1589, + [BNXT_ULP_CLASS_HID_2c2ab] = 1590, + [BNXT_ULP_CLASS_HID_34dab] = 1591, + [BNXT_ULP_CLASS_HID_3d8ab] = 1592, + [BNXT_ULP_CLASS_HID_24afb] = 1593, + [BNXT_ULP_CLASS_HID_2d5fb] = 1594, + [BNXT_ULP_CLASS_HID_303cf] = 1595, + [BNXT_ULP_CLASS_HID_38ecf] = 1596, + [BNXT_ULP_CLASS_HID_255b] = 1597, + [BNXT_ULP_CLASS_HID_2b97] = 1598, + [BNXT_ULP_CLASS_HID_4f0b] = 1599, + [BNXT_ULP_CLASS_HID_1633] = 1600, + [BNXT_ULP_CLASS_HID_39a7] = 1601, + [BNXT_ULP_CLASS_HID_48cf] = 1602, + [BNXT_ULP_CLASS_HID_0ff7] = 1603, + [BNXT_ULP_CLASS_HID_336b] = 1604, + [BNXT_ULP_CLASS_HID_257f7] = 1605, + [BNXT_ULP_CLASS_HID_2858b] = 1606, + [BNXT_ULP_CLASS_HID_3108b] = 1607, + [BNXT_ULP_CLASS_HID_39b8b] = 1608, + [BNXT_ULP_CLASS_HID_24427] = 1609, + [BNXT_ULP_CLASS_HID_2cf27] = 1610, + [BNXT_ULP_CLASS_HID_35a27] = 1611, + [BNXT_ULP_CLASS_HID_388fb] = 1612, + [BNXT_ULP_CLASS_HID_23ffb] = 1613, + [BNXT_ULP_CLASS_HID_2cafb] = 1614, + [BNXT_ULP_CLASS_HID_355fb] = 1615, + [BNXT_ULP_CLASS_HID_3838f] = 1616, + [BNXT_ULP_CLASS_HID_2528b] = 1617, + [BNXT_ULP_CLASS_HID_2815f] = 1618, + [BNXT_ULP_CLASS_HID_30c5f] = 1619, + [BNXT_ULP_CLASS_HID_3975f] = 1620, + [BNXT_ULP_CLASS_HID_21e3f] = 1621, + [BNXT_ULP_CLASS_HID_2a93f] = 1622, + [BNXT_ULP_CLASS_HID_3343f] = 1623, + [BNXT_ULP_CLASS_HID_3bf3f] = 1624, + [BNXT_ULP_CLASS_HID_20b6f] = 1625, + [BNXT_ULP_CLASS_HID_2966f] = 1626, + [BNXT_ULP_CLASS_HID_3216f] = 1627, + [BNXT_ULP_CLASS_HID_3ac6f] = 1628, + [BNXT_ULP_CLASS_HID_20623] = 1629, + [BNXT_ULP_CLASS_HID_29123] = 1630, + [BNXT_ULP_CLASS_HID_31c23] = 1631, + [BNXT_ULP_CLASS_HID_3a723] = 1632, + [BNXT_ULP_CLASS_HID_219f3] = 1633, + [BNXT_ULP_CLASS_HID_2a4f3] = 1634, + [BNXT_ULP_CLASS_HID_32ff3] = 1635, + [BNXT_ULP_CLASS_HID_3baf3] = 1636, + [BNXT_ULP_CLASS_HID_24253] = 1637, + [BNXT_ULP_CLASS_HID_2cd53] = 1638, + [BNXT_ULP_CLASS_HID_35853] = 1639, + [BNXT_ULP_CLASS_HID_38667] = 1640, + [BNXT_ULP_CLASS_HID_22e83] = 1641, + [BNXT_ULP_CLASS_HID_2b983] = 1642, + [BNXT_ULP_CLASS_HID_34483] = 1643, + [BNXT_ULP_CLASS_HID_3cf83] = 1644, + [BNXT_ULP_CLASS_HID_22a57] = 1645, + [BNXT_ULP_CLASS_HID_2b557] = 1646, + [BNXT_ULP_CLASS_HID_34057] = 1647, + [BNXT_ULP_CLASS_HID_3cb57] = 1648, + [BNXT_ULP_CLASS_HID_23d67] = 1649, + [BNXT_ULP_CLASS_HID_2c867] = 1650, + [BNXT_ULP_CLASS_HID_35367] = 1651, + [BNXT_ULP_CLASS_HID_3813b] = 1652, + [BNXT_ULP_CLASS_HID_2089b] = 1653, + [BNXT_ULP_CLASS_HID_2939b] = 1654, + [BNXT_ULP_CLASS_HID_31e9b] = 1655, + [BNXT_ULP_CLASS_HID_3a99b] = 1656, + [BNXT_ULP_CLASS_HID_25237] = 1657, + [BNXT_ULP_CLASS_HID_280cb] = 1658, + [BNXT_ULP_CLASS_HID_30bcb] = 1659, + [BNXT_ULP_CLASS_HID_396cb] = 1660, + [BNXT_ULP_CLASS_HID_24dcb] = 1661, + [BNXT_ULP_CLASS_HID_2d8cb] = 1662, + [BNXT_ULP_CLASS_HID_3069f] = 1663, + [BNXT_ULP_CLASS_HID_3919f] = 1664, + [BNXT_ULP_CLASS_HID_203af] = 1665, + [BNXT_ULP_CLASS_HID_28eaf] = 1666, + [BNXT_ULP_CLASS_HID_319af] = 1667, + [BNXT_ULP_CLASS_HID_3a4af] = 1668, + [BNXT_ULP_CLASS_HID_2513b] = 1669, + [BNXT_ULP_CLASS_HID_2dc3b] = 1670, + [BNXT_ULP_CLASS_HID_30acf] = 1671, + [BNXT_ULP_CLASS_HID_395cf] = 1672, + [BNXT_ULP_CLASS_HID_23e6b] = 1673, + [BNXT_ULP_CLASS_HID_2c96b] = 1674, + [BNXT_ULP_CLASS_HID_3546b] = 1675, + [BNXT_ULP_CLASS_HID_3823f] = 1676, + [BNXT_ULP_CLASS_HID_2393f] = 1677, + [BNXT_ULP_CLASS_HID_2c43f] = 1678, + [BNXT_ULP_CLASS_HID_34f3f] = 1679, + [BNXT_ULP_CLASS_HID_3da3f] = 1680, + [BNXT_ULP_CLASS_HID_24ccf] = 1681, + [BNXT_ULP_CLASS_HID_2d7cf] = 1682, + [BNXT_ULP_CLASS_HID_30583] = 1683, + [BNXT_ULP_CLASS_HID_39083] = 1684, + [BNXT_ULP_CLASS_HID_21863] = 1685, + [BNXT_ULP_CLASS_HID_2a363] = 1686, + [BNXT_ULP_CLASS_HID_32e63] = 1687, + [BNXT_ULP_CLASS_HID_3b963] = 1688, + [BNXT_ULP_CLASS_HID_20553] = 1689, + [BNXT_ULP_CLASS_HID_29053] = 1690, + [BNXT_ULP_CLASS_HID_31b53] = 1691, + [BNXT_ULP_CLASS_HID_3a653] = 1692, + [BNXT_ULP_CLASS_HID_20067] = 1693, + [BNXT_ULP_CLASS_HID_28b67] = 1694, + [BNXT_ULP_CLASS_HID_31667] = 1695, + [BNXT_ULP_CLASS_HID_3a167] = 1696, + [BNXT_ULP_CLASS_HID_21337] = 1697, + [BNXT_ULP_CLASS_HID_29e37] = 1698, + [BNXT_ULP_CLASS_HID_32937] = 1699, + [BNXT_ULP_CLASS_HID_3b437] = 1700, + [BNXT_ULP_CLASS_HID_23b97] = 1701, + [BNXT_ULP_CLASS_HID_2c697] = 1702, + [BNXT_ULP_CLASS_HID_35197] = 1703, + [BNXT_ULP_CLASS_HID_3dc97] = 1704, + [BNXT_ULP_CLASS_HID_228c7] = 1705, + [BNXT_ULP_CLASS_HID_2b3c7] = 1706, + [BNXT_ULP_CLASS_HID_33ec7] = 1707, + [BNXT_ULP_CLASS_HID_3c9c7] = 1708, + [BNXT_ULP_CLASS_HID_2239b] = 1709, + [BNXT_ULP_CLASS_HID_2ae9b] = 1710, + [BNXT_ULP_CLASS_HID_3399b] = 1711, + [BNXT_ULP_CLASS_HID_3c49b] = 1712, + [BNXT_ULP_CLASS_HID_236ab] = 1713, + [BNXT_ULP_CLASS_HID_2c1ab] = 1714, + [BNXT_ULP_CLASS_HID_34cab] = 1715, + [BNXT_ULP_CLASS_HID_3d7ab] = 1716, + [BNXT_ULP_CLASS_HID_202df] = 1717, + [BNXT_ULP_CLASS_HID_28ddf] = 1718, + [BNXT_ULP_CLASS_HID_318df] = 1719, + [BNXT_ULP_CLASS_HID_3a3df] = 1720, + [BNXT_ULP_CLASS_HID_24c7b] = 1721, + [BNXT_ULP_CLASS_HID_2d77b] = 1722, + [BNXT_ULP_CLASS_HID_3050f] = 1723, + [BNXT_ULP_CLASS_HID_3900f] = 1724, + [BNXT_ULP_CLASS_HID_2470f] = 1725, + [BNXT_ULP_CLASS_HID_2d20f] = 1726, + [BNXT_ULP_CLASS_HID_300c3] = 1727, + [BNXT_ULP_CLASS_HID_38bc3] = 1728, + [BNXT_ULP_CLASS_HID_25adf] = 1729, + [BNXT_ULP_CLASS_HID_28893] = 1730, + [BNXT_ULP_CLASS_HID_31393] = 1731, + [BNXT_ULP_CLASS_HID_39e93] = 1732, + [BNXT_ULP_CLASS_HID_24b7f] = 1733, + [BNXT_ULP_CLASS_HID_2d67f] = 1734, + [BNXT_ULP_CLASS_HID_30433] = 1735, + [BNXT_ULP_CLASS_HID_38f33] = 1736, + [BNXT_ULP_CLASS_HID_237af] = 1737, + [BNXT_ULP_CLASS_HID_2c2af] = 1738, + [BNXT_ULP_CLASS_HID_34daf] = 1739, + [BNXT_ULP_CLASS_HID_3d8af] = 1740, + [BNXT_ULP_CLASS_HID_23363] = 1741, + [BNXT_ULP_CLASS_HID_2be63] = 1742, + [BNXT_ULP_CLASS_HID_34963] = 1743, + [BNXT_ULP_CLASS_HID_3d463] = 1744, + [BNXT_ULP_CLASS_HID_24633] = 1745, + [BNXT_ULP_CLASS_HID_2d133] = 1746, + [BNXT_ULP_CLASS_HID_35c33] = 1747, + [BNXT_ULP_CLASS_HID_38ac7] = 1748, + [BNXT_ULP_CLASS_HID_211a7] = 1749, + [BNXT_ULP_CLASS_HID_29ca7] = 1750, + [BNXT_ULP_CLASS_HID_327a7] = 1751, + [BNXT_ULP_CLASS_HID_3b2a7] = 1752, + [BNXT_ULP_CLASS_HID_25bc3] = 1753, + [BNXT_ULP_CLASS_HID_28997] = 1754, + [BNXT_ULP_CLASS_HID_31497] = 1755, + [BNXT_ULP_CLASS_HID_39f97] = 1756, + [BNXT_ULP_CLASS_HID_25697] = 1757, + [BNXT_ULP_CLASS_HID_284ab] = 1758, + [BNXT_ULP_CLASS_HID_30fab] = 1759, + [BNXT_ULP_CLASS_HID_39aab] = 1760, + [BNXT_ULP_CLASS_HID_20d7b] = 1761, + [BNXT_ULP_CLASS_HID_2987b] = 1762, + [BNXT_ULP_CLASS_HID_3237b] = 1763, + [BNXT_ULP_CLASS_HID_3ae7b] = 1764, + [BNXT_ULP_CLASS_HID_235db] = 1765, + [BNXT_ULP_CLASS_HID_2c0db] = 1766, + [BNXT_ULP_CLASS_HID_34bdb] = 1767, + [BNXT_ULP_CLASS_HID_3d6db] = 1768, + [BNXT_ULP_CLASS_HID_2220b] = 1769, + [BNXT_ULP_CLASS_HID_2ad0b] = 1770, + [BNXT_ULP_CLASS_HID_3380b] = 1771, + [BNXT_ULP_CLASS_HID_3c30b] = 1772, + [BNXT_ULP_CLASS_HID_21ddf] = 1773, + [BNXT_ULP_CLASS_HID_2a8df] = 1774, + [BNXT_ULP_CLASS_HID_333df] = 1775, + [BNXT_ULP_CLASS_HID_3bedf] = 1776, + [BNXT_ULP_CLASS_HID_230ef] = 1777, + [BNXT_ULP_CLASS_HID_2bbef] = 1778, + [BNXT_ULP_CLASS_HID_346ef] = 1779, + [BNXT_ULP_CLASS_HID_3d1ef] = 1780, + [BNXT_ULP_CLASS_HID_2594f] = 1781, + [BNXT_ULP_CLASS_HID_28703] = 1782, + [BNXT_ULP_CLASS_HID_31203] = 1783, + [BNXT_ULP_CLASS_HID_39d03] = 1784, + [BNXT_ULP_CLASS_HID_245bf] = 1785, + [BNXT_ULP_CLASS_HID_2d0bf] = 1786, + [BNXT_ULP_CLASS_HID_35bbf] = 1787, + [BNXT_ULP_CLASS_HID_38a73] = 1788, + [BNXT_ULP_CLASS_HID_24173] = 1789, + [BNXT_ULP_CLASS_HID_2cc73] = 1790, + [BNXT_ULP_CLASS_HID_35773] = 1791, + [BNXT_ULP_CLASS_HID_38507] = 1792, + [BNXT_ULP_CLASS_HID_25403] = 1793, + [BNXT_ULP_CLASS_HID_282d7] = 1794, + [BNXT_ULP_CLASS_HID_30dd7] = 1795, + [BNXT_ULP_CLASS_HID_398d7] = 1796, + [BNXT_ULP_CLASS_HID_244a3] = 1797, + [BNXT_ULP_CLASS_HID_2cfa3] = 1798, + [BNXT_ULP_CLASS_HID_35aa3] = 1799, + [BNXT_ULP_CLASS_HID_38977] = 1800, + [BNXT_ULP_CLASS_HID_23193] = 1801, + [BNXT_ULP_CLASS_HID_2bc93] = 1802, + [BNXT_ULP_CLASS_HID_34793] = 1803, + [BNXT_ULP_CLASS_HID_3d293] = 1804, + [BNXT_ULP_CLASS_HID_22ca7] = 1805, + [BNXT_ULP_CLASS_HID_2b7a7] = 1806, + [BNXT_ULP_CLASS_HID_342a7] = 1807, + [BNXT_ULP_CLASS_HID_3cda7] = 1808, + [BNXT_ULP_CLASS_HID_24077] = 1809, + [BNXT_ULP_CLASS_HID_2cb77] = 1810, + [BNXT_ULP_CLASS_HID_35677] = 1811, + [BNXT_ULP_CLASS_HID_3840b] = 1812, + [BNXT_ULP_CLASS_HID_20beb] = 1813, + [BNXT_ULP_CLASS_HID_296eb] = 1814, + [BNXT_ULP_CLASS_HID_321eb] = 1815, + [BNXT_ULP_CLASS_HID_3aceb] = 1816, + [BNXT_ULP_CLASS_HID_25507] = 1817, + [BNXT_ULP_CLASS_HID_283db] = 1818, + [BNXT_ULP_CLASS_HID_30edb] = 1819, + [BNXT_ULP_CLASS_HID_399db] = 1820, + [BNXT_ULP_CLASS_HID_250db] = 1821, + [BNXT_ULP_CLASS_HID_2dbdb] = 1822, + [BNXT_ULP_CLASS_HID_309ef] = 1823, + [BNXT_ULP_CLASS_HID_394ef] = 1824, + [BNXT_ULP_CLASS_HID_206bf] = 1825, + [BNXT_ULP_CLASS_HID_291bf] = 1826, + [BNXT_ULP_CLASS_HID_31cbf] = 1827, + [BNXT_ULP_CLASS_HID_3a7bf] = 1828, + [BNXT_ULP_CLASS_HID_22f1f] = 1829, + [BNXT_ULP_CLASS_HID_2ba1f] = 1830, + [BNXT_ULP_CLASS_HID_3451f] = 1831, + [BNXT_ULP_CLASS_HID_3d01f] = 1832, + [BNXT_ULP_CLASS_HID_21c4f] = 1833, + [BNXT_ULP_CLASS_HID_2a74f] = 1834, + [BNXT_ULP_CLASS_HID_3324f] = 1835, + [BNXT_ULP_CLASS_HID_3bd4f] = 1836, + [BNXT_ULP_CLASS_HID_21703] = 1837, + [BNXT_ULP_CLASS_HID_2a203] = 1838, + [BNXT_ULP_CLASS_HID_32d03] = 1839, + [BNXT_ULP_CLASS_HID_3b803] = 1840, + [BNXT_ULP_CLASS_HID_22ad3] = 1841, + [BNXT_ULP_CLASS_HID_2b5d3] = 1842, + [BNXT_ULP_CLASS_HID_340d3] = 1843, + [BNXT_ULP_CLASS_HID_3cbd3] = 1844, + [BNXT_ULP_CLASS_HID_252b3] = 1845, + [BNXT_ULP_CLASS_HID_28147] = 1846, + [BNXT_ULP_CLASS_HID_30c47] = 1847, + [BNXT_ULP_CLASS_HID_39747] = 1848, + [BNXT_ULP_CLASS_HID_23fe3] = 1849, + [BNXT_ULP_CLASS_HID_2cae3] = 1850, + [BNXT_ULP_CLASS_HID_355e3] = 1851, + [BNXT_ULP_CLASS_HID_383b7] = 1852, + [BNXT_ULP_CLASS_HID_23ab7] = 1853, + [BNXT_ULP_CLASS_HID_2c5b7] = 1854, + [BNXT_ULP_CLASS_HID_350b7] = 1855, + [BNXT_ULP_CLASS_HID_3dbb7] = 1856, + [BNXT_ULP_CLASS_HID_24e47] = 1857, + [BNXT_ULP_CLASS_HID_2d947] = 1858, + [BNXT_ULP_CLASS_HID_3071b] = 1859, + [BNXT_ULP_CLASS_HID_3921b] = 1860, + [BNXT_ULP_CLASS_HID_2326f] = 1861, + [BNXT_ULP_CLASS_HID_2bd6f] = 1862, + [BNXT_ULP_CLASS_HID_3486f] = 1863, + [BNXT_ULP_CLASS_HID_3d36f] = 1864, + [BNXT_ULP_CLASS_HID_21f5f] = 1865, + [BNXT_ULP_CLASS_HID_2aa5f] = 1866, + [BNXT_ULP_CLASS_HID_3355f] = 1867, + [BNXT_ULP_CLASS_HID_3c05f] = 1868, + [BNXT_ULP_CLASS_HID_21a13] = 1869, + [BNXT_ULP_CLASS_HID_2a513] = 1870, + [BNXT_ULP_CLASS_HID_33013] = 1871, + [BNXT_ULP_CLASS_HID_3bb13] = 1872, + [BNXT_ULP_CLASS_HID_22d23] = 1873, + [BNXT_ULP_CLASS_HID_2b823] = 1874, + [BNXT_ULP_CLASS_HID_34323] = 1875, + [BNXT_ULP_CLASS_HID_3ce23] = 1876, + [BNXT_ULP_CLASS_HID_25583] = 1877, + [BNXT_ULP_CLASS_HID_28457] = 1878, + [BNXT_ULP_CLASS_HID_30f57] = 1879, + [BNXT_ULP_CLASS_HID_39a57] = 1880, + [BNXT_ULP_CLASS_HID_242f3] = 1881, + [BNXT_ULP_CLASS_HID_2cdf3] = 1882, + [BNXT_ULP_CLASS_HID_358f3] = 1883, + [BNXT_ULP_CLASS_HID_38687] = 1884, + [BNXT_ULP_CLASS_HID_23d87] = 1885, + [BNXT_ULP_CLASS_HID_2c887] = 1886, + [BNXT_ULP_CLASS_HID_35387] = 1887, + [BNXT_ULP_CLASS_HID_3825b] = 1888, + [BNXT_ULP_CLASS_HID_25157] = 1889, + [BNXT_ULP_CLASS_HID_2dc57] = 1890, + [BNXT_ULP_CLASS_HID_30a6b] = 1891, + [BNXT_ULP_CLASS_HID_3956b] = 1892, + [BNXT_ULP_CLASS_HID_22c53] = 1893, + [BNXT_ULP_CLASS_HID_2b753] = 1894, + [BNXT_ULP_CLASS_HID_34253] = 1895, + [BNXT_ULP_CLASS_HID_3cd53] = 1896, + [BNXT_ULP_CLASS_HID_21883] = 1897, + [BNXT_ULP_CLASS_HID_2a383] = 1898, + [BNXT_ULP_CLASS_HID_32e83] = 1899, + [BNXT_ULP_CLASS_HID_3b983] = 1900, + [BNXT_ULP_CLASS_HID_21457] = 1901, + [BNXT_ULP_CLASS_HID_29f57] = 1902, + [BNXT_ULP_CLASS_HID_32a57] = 1903, + [BNXT_ULP_CLASS_HID_3b557] = 1904, + [BNXT_ULP_CLASS_HID_22767] = 1905, + [BNXT_ULP_CLASS_HID_2b267] = 1906, + [BNXT_ULP_CLASS_HID_33d67] = 1907, + [BNXT_ULP_CLASS_HID_3c867] = 1908, + [BNXT_ULP_CLASS_HID_24fc7] = 1909, + [BNXT_ULP_CLASS_HID_2dac7] = 1910, + [BNXT_ULP_CLASS_HID_3089b] = 1911, + [BNXT_ULP_CLASS_HID_3939b] = 1912, + [BNXT_ULP_CLASS_HID_23c37] = 1913, + [BNXT_ULP_CLASS_HID_2c737] = 1914, + [BNXT_ULP_CLASS_HID_35237] = 1915, + [BNXT_ULP_CLASS_HID_380cb] = 1916, + [BNXT_ULP_CLASS_HID_237cb] = 1917, + [BNXT_ULP_CLASS_HID_2c2cb] = 1918, + [BNXT_ULP_CLASS_HID_34dcb] = 1919, + [BNXT_ULP_CLASS_HID_3d8cb] = 1920, + [BNXT_ULP_CLASS_HID_24a9b] = 1921, + [BNXT_ULP_CLASS_HID_2d59b] = 1922, + [BNXT_ULP_CLASS_HID_303af] = 1923, + [BNXT_ULP_CLASS_HID_38eaf] = 1924, + [BNXT_ULP_CLASS_HID_253b] = 1925, + [BNXT_ULP_CLASS_HID_2bf7] = 1926, + [BNXT_ULP_CLASS_HID_4f6b] = 1927, + [BNXT_ULP_CLASS_HID_1653] = 1928, + [BNXT_ULP_CLASS_HID_39c7] = 1929, + [BNXT_ULP_CLASS_HID_48af] = 1930, + [BNXT_ULP_CLASS_HID_0f97] = 1931, + [BNXT_ULP_CLASS_HID_330b] = 1932, + [BNXT_ULP_CLASS_HID_374e] = 1933, + [BNXT_ULP_CLASS_HID_11ee] = 1934, + [BNXT_ULP_CLASS_HID_423a] = 1935, + [BNXT_ULP_CLASS_HID_0cd6] = 1936, + [BNXT_ULP_CLASS_HID_310a] = 1937, + [BNXT_ULP_CLASS_HID_469e] = 1938, + [BNXT_ULP_CLASS_HID_5ce6] = 1939, + [BNXT_ULP_CLASS_HID_0692] = 1940, + [BNXT_ULP_CLASS_HID_1c7e] = 1941, + [BNXT_ULP_CLASS_HID_55c2] = 1942, + [BNXT_ULP_CLASS_HID_2b2a] = 1943, + [BNXT_ULP_CLASS_HID_15c6] = 1944, + [BNXT_ULP_CLASS_HID_163a] = 1945, + [BNXT_ULP_CLASS_HID_2f8e] = 1946, + [BNXT_ULP_CLASS_HID_2516] = 1947, + [BNXT_ULP_CLASS_HID_4b76] = 1948, + [BNXT_ULP_CLASS_HID_10e6] = 1949, + [BNXT_ULP_CLASS_HID_264a] = 1950, + [BNXT_ULP_CLASS_HID_3fd2] = 1951, + [BNXT_ULP_CLASS_HID_4532] = 1952, + [BNXT_ULP_CLASS_HID_4996] = 1953, + [BNXT_ULP_CLASS_HID_2036] = 1954, + [BNXT_ULP_CLASS_HID_399e] = 1955, + [BNXT_ULP_CLASS_HID_5ffe] = 1956, + [BNXT_ULP_CLASS_HID_34fe] = 1957, + [BNXT_ULP_CLASS_HID_3a32] = 1958, + [BNXT_ULP_CLASS_HID_376e] = 1959, + [BNXT_ULP_CLASS_HID_12d6e] = 1960, + [BNXT_ULP_CLASS_HID_2436e] = 1961, + [BNXT_ULP_CLASS_HID_31dba] = 1962, + [BNXT_ULP_CLASS_HID_11ce] = 1963, + [BNXT_ULP_CLASS_HID_107ce] = 1964, + [BNXT_ULP_CLASS_HID_23dce] = 1965, + [BNXT_ULP_CLASS_HID_353ce] = 1966, + [BNXT_ULP_CLASS_HID_421a] = 1967, + [BNXT_ULP_CLASS_HID_11d56] = 1968, + [BNXT_ULP_CLASS_HID_23356] = 1969, + [BNXT_ULP_CLASS_HID_32956] = 1970, + [BNXT_ULP_CLASS_HID_0cf6] = 1971, + [BNXT_ULP_CLASS_HID_122f6] = 1972, + [BNXT_ULP_CLASS_HID_258f6] = 1973, + [BNXT_ULP_CLASS_HID_313c2] = 1974, + [BNXT_ULP_CLASS_HID_312a] = 1975, + [BNXT_ULP_CLASS_HID_1272a] = 1976, + [BNXT_ULP_CLASS_HID_25d2a] = 1977, + [BNXT_ULP_CLASS_HID_31466] = 1978, + [BNXT_ULP_CLASS_HID_46be] = 1979, + [BNXT_ULP_CLASS_HID_1018a] = 1980, + [BNXT_ULP_CLASS_HID_2378a] = 1981, + [BNXT_ULP_CLASS_HID_32d8a] = 1982, + [BNXT_ULP_CLASS_HID_5cc6] = 1983, + [BNXT_ULP_CLASS_HID_11712] = 1984, + [BNXT_ULP_CLASS_HID_20d12] = 1985, + [BNXT_ULP_CLASS_HID_32312] = 1986, + [BNXT_ULP_CLASS_HID_06b2] = 1987, + [BNXT_ULP_CLASS_HID_13cb2] = 1988, + [BNXT_ULP_CLASS_HID_252b2] = 1989, + [BNXT_ULP_CLASS_HID_348b2] = 1990, + [BNXT_ULP_CLASS_HID_1c5e] = 1991, + [BNXT_ULP_CLASS_HID_1325e] = 1992, + [BNXT_ULP_CLASS_HID_2285e] = 1993, + [BNXT_ULP_CLASS_HID_35e5e] = 1994, + [BNXT_ULP_CLASS_HID_55e2] = 1995, + [BNXT_ULP_CLASS_HID_14be2] = 1996, + [BNXT_ULP_CLASS_HID_2023e] = 1997, + [BNXT_ULP_CLASS_HID_3383e] = 1998, + [BNXT_ULP_CLASS_HID_2b0a] = 1999, + [BNXT_ULP_CLASS_HID_1410a] = 2000, + [BNXT_ULP_CLASS_HID_21846] = 2001, + [BNXT_ULP_CLASS_HID_30e46] = 2002, + [BNXT_ULP_CLASS_HID_15e6] = 2003, + [BNXT_ULP_CLASS_HID_10be6] = 2004, + [BNXT_ULP_CLASS_HID_221e6] = 2005, + [BNXT_ULP_CLASS_HID_357e6] = 2006, + [BNXT_ULP_CLASS_HID_161a] = 2007, + [BNXT_ULP_CLASS_HID_10c1a] = 2008, + [BNXT_ULP_CLASS_HID_2221a] = 2009, + [BNXT_ULP_CLASS_HID_3581a] = 2010, + [BNXT_ULP_CLASS_HID_2fae] = 2011, + [BNXT_ULP_CLASS_HID_145ae] = 2012, + [BNXT_ULP_CLASS_HID_21cfa] = 2013, + [BNXT_ULP_CLASS_HID_332fa] = 2014, + [BNXT_ULP_CLASS_HID_2536] = 2015, + [BNXT_ULP_CLASS_HID_15b36] = 2016, + [BNXT_ULP_CLASS_HID_21202] = 2017, + [BNXT_ULP_CLASS_HID_30802] = 2018, + [BNXT_ULP_CLASS_HID_4b56] = 2019, + [BNXT_ULP_CLASS_HID_105a2] = 2020, + [BNXT_ULP_CLASS_HID_23ba2] = 2021, + [BNXT_ULP_CLASS_HID_351a2] = 2022, + [BNXT_ULP_CLASS_HID_10c6] = 2023, + [BNXT_ULP_CLASS_HID_106c6] = 2024, + [BNXT_ULP_CLASS_HID_23cc6] = 2025, + [BNXT_ULP_CLASS_HID_352c6] = 2026, + [BNXT_ULP_CLASS_HID_266a] = 2027, + [BNXT_ULP_CLASS_HID_15c6a] = 2028, + [BNXT_ULP_CLASS_HID_216a6] = 2029, + [BNXT_ULP_CLASS_HID_30ca6] = 2030, + [BNXT_ULP_CLASS_HID_3ff2] = 2031, + [BNXT_ULP_CLASS_HID_155f2] = 2032, + [BNXT_ULP_CLASS_HID_24bf2] = 2033, + [BNXT_ULP_CLASS_HID_302ce] = 2034, + [BNXT_ULP_CLASS_HID_4512] = 2035, + [BNXT_ULP_CLASS_HID_11c6e] = 2036, + [BNXT_ULP_CLASS_HID_2326e] = 2037, + [BNXT_ULP_CLASS_HID_3286e] = 2038, + [BNXT_ULP_CLASS_HID_49b6] = 2039, + [BNXT_ULP_CLASS_HID_10082] = 2040, + [BNXT_ULP_CLASS_HID_23682] = 2041, + [BNXT_ULP_CLASS_HID_32c82] = 2042, + [BNXT_ULP_CLASS_HID_2016] = 2043, + [BNXT_ULP_CLASS_HID_15616] = 2044, + [BNXT_ULP_CLASS_HID_21162] = 2045, + [BNXT_ULP_CLASS_HID_30762] = 2046, + [BNXT_ULP_CLASS_HID_39be] = 2047, + [BNXT_ULP_CLASS_HID_12fbe] = 2048, + [BNXT_ULP_CLASS_HID_245be] = 2049, + [BNXT_ULP_CLASS_HID_31c8a] = 2050, + [BNXT_ULP_CLASS_HID_5fde] = 2051, + [BNXT_ULP_CLASS_HID_1162a] = 2052, + [BNXT_ULP_CLASS_HID_20c2a] = 2053, + [BNXT_ULP_CLASS_HID_3222a] = 2054, + [BNXT_ULP_CLASS_HID_34de] = 2055, + [BNXT_ULP_CLASS_HID_3a12] = 2056, + [BNXT_ULP_CLASS_HID_370e] = 2057, + [BNXT_ULP_CLASS_HID_12d0e] = 2058, + [BNXT_ULP_CLASS_HID_2430e] = 2059, + [BNXT_ULP_CLASS_HID_31dda] = 2060, + [BNXT_ULP_CLASS_HID_11ae] = 2061, + [BNXT_ULP_CLASS_HID_107ae] = 2062, + [BNXT_ULP_CLASS_HID_23dae] = 2063, + [BNXT_ULP_CLASS_HID_353ae] = 2064, + [BNXT_ULP_CLASS_HID_427a] = 2065, + [BNXT_ULP_CLASS_HID_11d36] = 2066, + [BNXT_ULP_CLASS_HID_23336] = 2067, + [BNXT_ULP_CLASS_HID_32936] = 2068, + [BNXT_ULP_CLASS_HID_0c96] = 2069, + [BNXT_ULP_CLASS_HID_12296] = 2070, + [BNXT_ULP_CLASS_HID_25896] = 2071, + [BNXT_ULP_CLASS_HID_313a2] = 2072, + [BNXT_ULP_CLASS_HID_314a] = 2073, + [BNXT_ULP_CLASS_HID_1274a] = 2074, + [BNXT_ULP_CLASS_HID_25d4a] = 2075, + [BNXT_ULP_CLASS_HID_31406] = 2076, + [BNXT_ULP_CLASS_HID_46de] = 2077, + [BNXT_ULP_CLASS_HID_101ea] = 2078, + [BNXT_ULP_CLASS_HID_237ea] = 2079, + [BNXT_ULP_CLASS_HID_32dea] = 2080, + [BNXT_ULP_CLASS_HID_5ca6] = 2081, + [BNXT_ULP_CLASS_HID_11772] = 2082, + [BNXT_ULP_CLASS_HID_20d72] = 2083, + [BNXT_ULP_CLASS_HID_32372] = 2084, + [BNXT_ULP_CLASS_HID_06d2] = 2085, + [BNXT_ULP_CLASS_HID_13cd2] = 2086, + [BNXT_ULP_CLASS_HID_252d2] = 2087, + [BNXT_ULP_CLASS_HID_348d2] = 2088, + [BNXT_ULP_CLASS_HID_1c3e] = 2089, + [BNXT_ULP_CLASS_HID_1323e] = 2090, + [BNXT_ULP_CLASS_HID_2283e] = 2091, + [BNXT_ULP_CLASS_HID_35e3e] = 2092, + [BNXT_ULP_CLASS_HID_5582] = 2093, + [BNXT_ULP_CLASS_HID_14b82] = 2094, + [BNXT_ULP_CLASS_HID_2025e] = 2095, + [BNXT_ULP_CLASS_HID_3385e] = 2096, + [BNXT_ULP_CLASS_HID_2b6a] = 2097, + [BNXT_ULP_CLASS_HID_1416a] = 2098, + [BNXT_ULP_CLASS_HID_21826] = 2099, + [BNXT_ULP_CLASS_HID_30e26] = 2100, + [BNXT_ULP_CLASS_HID_1586] = 2101, + [BNXT_ULP_CLASS_HID_10b86] = 2102, + [BNXT_ULP_CLASS_HID_22186] = 2103, + [BNXT_ULP_CLASS_HID_35786] = 2104, + [BNXT_ULP_CLASS_HID_167a] = 2105, + [BNXT_ULP_CLASS_HID_10c7a] = 2106, + [BNXT_ULP_CLASS_HID_2227a] = 2107, + [BNXT_ULP_CLASS_HID_3587a] = 2108, + [BNXT_ULP_CLASS_HID_2fce] = 2109, + [BNXT_ULP_CLASS_HID_145ce] = 2110, + [BNXT_ULP_CLASS_HID_21c9a] = 2111, + [BNXT_ULP_CLASS_HID_3329a] = 2112, + [BNXT_ULP_CLASS_HID_2556] = 2113, + [BNXT_ULP_CLASS_HID_15b56] = 2114, + [BNXT_ULP_CLASS_HID_21262] = 2115, + [BNXT_ULP_CLASS_HID_30862] = 2116, + [BNXT_ULP_CLASS_HID_4b36] = 2117, + [BNXT_ULP_CLASS_HID_105c2] = 2118, + [BNXT_ULP_CLASS_HID_23bc2] = 2119, + [BNXT_ULP_CLASS_HID_351c2] = 2120, + [BNXT_ULP_CLASS_HID_10a6] = 2121, + [BNXT_ULP_CLASS_HID_106a6] = 2122, + [BNXT_ULP_CLASS_HID_23ca6] = 2123, + [BNXT_ULP_CLASS_HID_352a6] = 2124, + [BNXT_ULP_CLASS_HID_260a] = 2125, + [BNXT_ULP_CLASS_HID_15c0a] = 2126, + [BNXT_ULP_CLASS_HID_216c6] = 2127, + [BNXT_ULP_CLASS_HID_30cc6] = 2128, + [BNXT_ULP_CLASS_HID_3f92] = 2129, + [BNXT_ULP_CLASS_HID_15592] = 2130, + [BNXT_ULP_CLASS_HID_24b92] = 2131, + [BNXT_ULP_CLASS_HID_302ae] = 2132, + [BNXT_ULP_CLASS_HID_4572] = 2133, + [BNXT_ULP_CLASS_HID_11c0e] = 2134, + [BNXT_ULP_CLASS_HID_2320e] = 2135, + [BNXT_ULP_CLASS_HID_3280e] = 2136, + [BNXT_ULP_CLASS_HID_49d6] = 2137, + [BNXT_ULP_CLASS_HID_100e2] = 2138, + [BNXT_ULP_CLASS_HID_236e2] = 2139, + [BNXT_ULP_CLASS_HID_32ce2] = 2140, + [BNXT_ULP_CLASS_HID_2076] = 2141, + [BNXT_ULP_CLASS_HID_15676] = 2142, + [BNXT_ULP_CLASS_HID_21102] = 2143, + [BNXT_ULP_CLASS_HID_30702] = 2144, + [BNXT_ULP_CLASS_HID_39de] = 2145, + [BNXT_ULP_CLASS_HID_12fde] = 2146, + [BNXT_ULP_CLASS_HID_245de] = 2147, + [BNXT_ULP_CLASS_HID_31cea] = 2148, + [BNXT_ULP_CLASS_HID_5fbe] = 2149, + [BNXT_ULP_CLASS_HID_1164a] = 2150, + [BNXT_ULP_CLASS_HID_20c4a] = 2151, + [BNXT_ULP_CLASS_HID_3224a] = 2152, + [BNXT_ULP_CLASS_HID_34be] = 2153, + [BNXT_ULP_CLASS_HID_3a72] = 2154, + [BNXT_ULP_CLASS_HID_09ea] = 2155, + [BNXT_ULP_CLASS_HID_2912] = 2156, + [BNXT_ULP_CLASS_HID_03b2] = 2157, + [BNXT_ULP_CLASS_HID_5f7e] = 2158, + [BNXT_ULP_CLASS_HID_03a6] = 2159, + [BNXT_ULP_CLASS_HID_23ce] = 2160, + [BNXT_ULP_CLASS_HID_1a6e] = 2161, + [BNXT_ULP_CLASS_HID_593a] = 2162, + [BNXT_ULP_CLASS_HID_4dce] = 2163, + [BNXT_ULP_CLASS_HID_0e02] = 2164, + [BNXT_ULP_CLASS_HID_4796] = 2165, + [BNXT_ULP_CLASS_HID_246e] = 2166, + [BNXT_ULP_CLASS_HID_478a] = 2167, + [BNXT_ULP_CLASS_HID_08fe] = 2168, + [BNXT_ULP_CLASS_HID_5e52] = 2169, + [BNXT_ULP_CLASS_HID_3e2a] = 2170, + [BNXT_ULP_CLASS_HID_5e46] = 2171, + [BNXT_ULP_CLASS_HID_02ba] = 2172, + [BNXT_ULP_CLASS_HID_580e] = 2173, + [BNXT_ULP_CLASS_HID_38e6] = 2174, + [BNXT_ULP_CLASS_HID_5802] = 2175, + [BNXT_ULP_CLASS_HID_1d76] = 2176, + [BNXT_ULP_CLASS_HID_52ca] = 2177, + [BNXT_ULP_CLASS_HID_32a2] = 2178, + [BNXT_ULP_CLASS_HID_34f6] = 2179, + [BNXT_ULP_CLASS_HID_3a3a] = 2180, + [BNXT_ULP_CLASS_HID_09ca] = 2181, + [BNXT_ULP_CLASS_HID_0216] = 2182, + [BNXT_ULP_CLASS_HID_1f62] = 2183, + [BNXT_ULP_CLASS_HID_1bae] = 2184, + [BNXT_ULP_CLASS_HID_2932] = 2185, + [BNXT_ULP_CLASS_HID_227e] = 2186, + [BNXT_ULP_CLASS_HID_3f4a] = 2187, + [BNXT_ULP_CLASS_HID_3b96] = 2188, + [BNXT_ULP_CLASS_HID_0392] = 2189, + [BNXT_ULP_CLASS_HID_1cde] = 2190, + [BNXT_ULP_CLASS_HID_192a] = 2191, + [BNXT_ULP_CLASS_HID_1276] = 2192, + [BNXT_ULP_CLASS_HID_5f5e] = 2193, + [BNXT_ULP_CLASS_HID_5baa] = 2194, + [BNXT_ULP_CLASS_HID_54f6] = 2195, + [BNXT_ULP_CLASS_HID_51c2] = 2196, + [BNXT_ULP_CLASS_HID_0386] = 2197, + [BNXT_ULP_CLASS_HID_1cd2] = 2198, + [BNXT_ULP_CLASS_HID_191e] = 2199, + [BNXT_ULP_CLASS_HID_126a] = 2200, + [BNXT_ULP_CLASS_HID_23ee] = 2201, + [BNXT_ULP_CLASS_HID_3c3a] = 2202, + [BNXT_ULP_CLASS_HID_3906] = 2203, + [BNXT_ULP_CLASS_HID_3252] = 2204, + [BNXT_ULP_CLASS_HID_1a4e] = 2205, + [BNXT_ULP_CLASS_HID_169a] = 2206, + [BNXT_ULP_CLASS_HID_13e6] = 2207, + [BNXT_ULP_CLASS_HID_4be6] = 2208, + [BNXT_ULP_CLASS_HID_591a] = 2209, + [BNXT_ULP_CLASS_HID_5266] = 2210, + [BNXT_ULP_CLASS_HID_2eb2] = 2211, + [BNXT_ULP_CLASS_HID_2bfe] = 2212, + [BNXT_ULP_CLASS_HID_4dee] = 2213, + [BNXT_ULP_CLASS_HID_463a] = 2214, + [BNXT_ULP_CLASS_HID_4306] = 2215, + [BNXT_ULP_CLASS_HID_5c52] = 2216, + [BNXT_ULP_CLASS_HID_0e22] = 2217, + [BNXT_ULP_CLASS_HID_0b6e] = 2218, + [BNXT_ULP_CLASS_HID_07ba] = 2219, + [BNXT_ULP_CLASS_HID_0086] = 2220, + [BNXT_ULP_CLASS_HID_47b6] = 2221, + [BNXT_ULP_CLASS_HID_4082] = 2222, + [BNXT_ULP_CLASS_HID_5dce] = 2223, + [BNXT_ULP_CLASS_HID_561a] = 2224, + [BNXT_ULP_CLASS_HID_244e] = 2225, + [BNXT_ULP_CLASS_HID_209a] = 2226, + [BNXT_ULP_CLASS_HID_3de6] = 2227, + [BNXT_ULP_CLASS_HID_3632] = 2228, + [BNXT_ULP_CLASS_HID_47aa] = 2229, + [BNXT_ULP_CLASS_HID_40f6] = 2230, + [BNXT_ULP_CLASS_HID_5dc2] = 2231, + [BNXT_ULP_CLASS_HID_560e] = 2232, + [BNXT_ULP_CLASS_HID_08de] = 2233, + [BNXT_ULP_CLASS_HID_052a] = 2234, + [BNXT_ULP_CLASS_HID_1e76] = 2235, + [BNXT_ULP_CLASS_HID_1b42] = 2236, + [BNXT_ULP_CLASS_HID_5e72] = 2237, + [BNXT_ULP_CLASS_HID_5abe] = 2238, + [BNXT_ULP_CLASS_HID_578a] = 2239, + [BNXT_ULP_CLASS_HID_50d6] = 2240, + [BNXT_ULP_CLASS_HID_3e0a] = 2241, + [BNXT_ULP_CLASS_HID_3b56] = 2242, + [BNXT_ULP_CLASS_HID_37a2] = 2243, + [BNXT_ULP_CLASS_HID_30ee] = 2244, + [BNXT_ULP_CLASS_HID_5e66] = 2245, + [BNXT_ULP_CLASS_HID_5ab2] = 2246, + [BNXT_ULP_CLASS_HID_57fe] = 2247, + [BNXT_ULP_CLASS_HID_50ca] = 2248, + [BNXT_ULP_CLASS_HID_029a] = 2249, + [BNXT_ULP_CLASS_HID_1fe6] = 2250, + [BNXT_ULP_CLASS_HID_1832] = 2251, + [BNXT_ULP_CLASS_HID_157e] = 2252, + [BNXT_ULP_CLASS_HID_582e] = 2253, + [BNXT_ULP_CLASS_HID_557a] = 2254, + [BNXT_ULP_CLASS_HID_2e46] = 2255, + [BNXT_ULP_CLASS_HID_2a92] = 2256, + [BNXT_ULP_CLASS_HID_38c6] = 2257, + [BNXT_ULP_CLASS_HID_3512] = 2258, + [BNXT_ULP_CLASS_HID_0e5e] = 2259, + [BNXT_ULP_CLASS_HID_0aaa] = 2260, + [BNXT_ULP_CLASS_HID_5822] = 2261, + [BNXT_ULP_CLASS_HID_556e] = 2262, + [BNXT_ULP_CLASS_HID_51ba] = 2263, + [BNXT_ULP_CLASS_HID_2a86] = 2264, + [BNXT_ULP_CLASS_HID_1d56] = 2265, + [BNXT_ULP_CLASS_HID_19a2] = 2266, + [BNXT_ULP_CLASS_HID_12ee] = 2267, + [BNXT_ULP_CLASS_HID_4aee] = 2268, + [BNXT_ULP_CLASS_HID_52ea] = 2269, + [BNXT_ULP_CLASS_HID_2f36] = 2270, + [BNXT_ULP_CLASS_HID_2802] = 2271, + [BNXT_ULP_CLASS_HID_254e] = 2272, + [BNXT_ULP_CLASS_HID_3282] = 2273, + [BNXT_ULP_CLASS_HID_0fce] = 2274, + [BNXT_ULP_CLASS_HID_081a] = 2275, + [BNXT_ULP_CLASS_HID_0566] = 2276, + [BNXT_ULP_CLASS_HID_34d6] = 2277, + [BNXT_ULP_CLASS_HID_3a1a] = 2278, + [BNXT_ULP_CLASS_HID_09aa] = 2279, + [BNXT_ULP_CLASS_HID_0276] = 2280, + [BNXT_ULP_CLASS_HID_1f02] = 2281, + [BNXT_ULP_CLASS_HID_1bce] = 2282, + [BNXT_ULP_CLASS_HID_2952] = 2283, + [BNXT_ULP_CLASS_HID_221e] = 2284, + [BNXT_ULP_CLASS_HID_3f2a] = 2285, + [BNXT_ULP_CLASS_HID_3bf6] = 2286, + [BNXT_ULP_CLASS_HID_03f2] = 2287, + [BNXT_ULP_CLASS_HID_1cbe] = 2288, + [BNXT_ULP_CLASS_HID_194a] = 2289, + [BNXT_ULP_CLASS_HID_1216] = 2290, + [BNXT_ULP_CLASS_HID_5f3e] = 2291, + [BNXT_ULP_CLASS_HID_5bca] = 2292, + [BNXT_ULP_CLASS_HID_5496] = 2293, + [BNXT_ULP_CLASS_HID_51a2] = 2294, + [BNXT_ULP_CLASS_HID_03e6] = 2295, + [BNXT_ULP_CLASS_HID_1cb2] = 2296, + [BNXT_ULP_CLASS_HID_197e] = 2297, + [BNXT_ULP_CLASS_HID_120a] = 2298, + [BNXT_ULP_CLASS_HID_238e] = 2299, + [BNXT_ULP_CLASS_HID_3c5a] = 2300, + [BNXT_ULP_CLASS_HID_3966] = 2301, + [BNXT_ULP_CLASS_HID_3232] = 2302, + [BNXT_ULP_CLASS_HID_1a2e] = 2303, + [BNXT_ULP_CLASS_HID_16fa] = 2304, + [BNXT_ULP_CLASS_HID_1386] = 2305, + [BNXT_ULP_CLASS_HID_4b86] = 2306, + [BNXT_ULP_CLASS_HID_597a] = 2307, + [BNXT_ULP_CLASS_HID_5206] = 2308, + [BNXT_ULP_CLASS_HID_2ed2] = 2309, + [BNXT_ULP_CLASS_HID_2b9e] = 2310, + [BNXT_ULP_CLASS_HID_4d8e] = 2311, + [BNXT_ULP_CLASS_HID_465a] = 2312, + [BNXT_ULP_CLASS_HID_4366] = 2313, + [BNXT_ULP_CLASS_HID_5c32] = 2314, + [BNXT_ULP_CLASS_HID_0e42] = 2315, + [BNXT_ULP_CLASS_HID_0b0e] = 2316, + [BNXT_ULP_CLASS_HID_07da] = 2317, + [BNXT_ULP_CLASS_HID_00e6] = 2318, + [BNXT_ULP_CLASS_HID_47d6] = 2319, + [BNXT_ULP_CLASS_HID_40e2] = 2320, + [BNXT_ULP_CLASS_HID_5dae] = 2321, + [BNXT_ULP_CLASS_HID_567a] = 2322, + [BNXT_ULP_CLASS_HID_242e] = 2323, + [BNXT_ULP_CLASS_HID_20fa] = 2324, + [BNXT_ULP_CLASS_HID_3d86] = 2325, + [BNXT_ULP_CLASS_HID_3652] = 2326, + [BNXT_ULP_CLASS_HID_47ca] = 2327, + [BNXT_ULP_CLASS_HID_4096] = 2328, + [BNXT_ULP_CLASS_HID_5da2] = 2329, + [BNXT_ULP_CLASS_HID_566e] = 2330, + [BNXT_ULP_CLASS_HID_08be] = 2331, + [BNXT_ULP_CLASS_HID_054a] = 2332, + [BNXT_ULP_CLASS_HID_1e16] = 2333, + [BNXT_ULP_CLASS_HID_1b22] = 2334, + [BNXT_ULP_CLASS_HID_5e12] = 2335, + [BNXT_ULP_CLASS_HID_5ade] = 2336, + [BNXT_ULP_CLASS_HID_57ea] = 2337, + [BNXT_ULP_CLASS_HID_50b6] = 2338, + [BNXT_ULP_CLASS_HID_3e6a] = 2339, + [BNXT_ULP_CLASS_HID_3b36] = 2340, + [BNXT_ULP_CLASS_HID_37c2] = 2341, + [BNXT_ULP_CLASS_HID_308e] = 2342, + [BNXT_ULP_CLASS_HID_5e06] = 2343, + [BNXT_ULP_CLASS_HID_5ad2] = 2344, + [BNXT_ULP_CLASS_HID_579e] = 2345, + [BNXT_ULP_CLASS_HID_50aa] = 2346, + [BNXT_ULP_CLASS_HID_02fa] = 2347, + [BNXT_ULP_CLASS_HID_1f86] = 2348, + [BNXT_ULP_CLASS_HID_1852] = 2349, + [BNXT_ULP_CLASS_HID_151e] = 2350, + [BNXT_ULP_CLASS_HID_584e] = 2351, + [BNXT_ULP_CLASS_HID_551a] = 2352, + [BNXT_ULP_CLASS_HID_2e26] = 2353, + [BNXT_ULP_CLASS_HID_2af2] = 2354, + [BNXT_ULP_CLASS_HID_38a6] = 2355, + [BNXT_ULP_CLASS_HID_3572] = 2356, + [BNXT_ULP_CLASS_HID_0e3e] = 2357, + [BNXT_ULP_CLASS_HID_0aca] = 2358, + [BNXT_ULP_CLASS_HID_5842] = 2359, + [BNXT_ULP_CLASS_HID_550e] = 2360, + [BNXT_ULP_CLASS_HID_51da] = 2361, + [BNXT_ULP_CLASS_HID_2ae6] = 2362, + [BNXT_ULP_CLASS_HID_1d36] = 2363, + [BNXT_ULP_CLASS_HID_19c2] = 2364, + [BNXT_ULP_CLASS_HID_128e] = 2365, + [BNXT_ULP_CLASS_HID_4a8e] = 2366, + [BNXT_ULP_CLASS_HID_528a] = 2367, + [BNXT_ULP_CLASS_HID_2f56] = 2368, + [BNXT_ULP_CLASS_HID_2862] = 2369, + [BNXT_ULP_CLASS_HID_252e] = 2370, + [BNXT_ULP_CLASS_HID_32e2] = 2371, + [BNXT_ULP_CLASS_HID_0fae] = 2372, + [BNXT_ULP_CLASS_HID_087a] = 2373, + [BNXT_ULP_CLASS_HID_0506] = 2374, + [BNXT_ULP_CLASS_HID_34b6] = 2375, + [BNXT_ULP_CLASS_HID_3a7a] = 2376, + [BNXT_ULP_CLASS_HID_a73c] = 2377, + [BNXT_ULP_CLASS_HID_a040] = 2378, + [BNXT_ULP_CLASS_HID_1d640] = 2379, + [BNXT_ULP_CLASS_HID_1dd3c] = 2380, + [BNXT_ULP_CLASS_HID_cba0] = 2381, + [BNXT_ULP_CLASS_HID_c4f4] = 2382, + [BNXT_ULP_CLASS_HID_19f38] = 2383, + [BNXT_ULP_CLASS_HID_182f4] = 2384, + [BNXT_ULP_CLASS_HID_b098] = 2385, + [BNXT_ULP_CLASS_HID_8dac] = 2386, + [BNXT_ULP_CLASS_HID_1a3ac] = 2387, + [BNXT_ULP_CLASS_HID_1a698] = 2388, + [BNXT_ULP_CLASS_HID_d50c] = 2389, + [BNXT_ULP_CLASS_HID_ae50] = 2390, + [BNXT_ULP_CLASS_HID_1c450] = 2391, + [BNXT_ULP_CLASS_HID_1cb0c] = 2392, + [BNXT_ULP_CLASS_HID_a1f0] = 2393, + [BNXT_ULP_CLASS_HID_ba04] = 2394, + [BNXT_ULP_CLASS_HID_1d004] = 2395, + [BNXT_ULP_CLASS_HID_1d7f0] = 2396, + [BNXT_ULP_CLASS_HID_c264] = 2397, + [BNXT_ULP_CLASS_HID_dea8] = 2398, + [BNXT_ULP_CLASS_HID_199fc] = 2399, + [BNXT_ULP_CLASS_HID_19ca8] = 2400, + [BNXT_ULP_CLASS_HID_8b5c] = 2401, + [BNXT_ULP_CLASS_HID_8460] = 2402, + [BNXT_ULP_CLASS_HID_1ba60] = 2403, + [BNXT_ULP_CLASS_HID_1a15c] = 2404, + [BNXT_ULP_CLASS_HID_afc0] = 2405, + [BNXT_ULP_CLASS_HID_a814] = 2406, + [BNXT_ULP_CLASS_HID_1de14] = 2407, + [BNXT_ULP_CLASS_HID_1c5c0] = 2408, + [BNXT_ULP_CLASS_HID_8c2c] = 2409, + [BNXT_ULP_CLASS_HID_8970] = 2410, + [BNXT_ULP_CLASS_HID_1bf70] = 2411, + [BNXT_ULP_CLASS_HID_1a22c] = 2412, + [BNXT_ULP_CLASS_HID_d0d0] = 2413, + [BNXT_ULP_CLASS_HID_ade4] = 2414, + [BNXT_ULP_CLASS_HID_1c3e4] = 2415, + [BNXT_ULP_CLASS_HID_1c6d0] = 2416, + [BNXT_ULP_CLASS_HID_9988] = 2417, + [BNXT_ULP_CLASS_HID_92dc] = 2418, + [BNXT_ULP_CLASS_HID_188dc] = 2419, + [BNXT_ULP_CLASS_HID_18f88] = 2420, + [BNXT_ULP_CLASS_HID_ba3c] = 2421, + [BNXT_ULP_CLASS_HID_b740] = 2422, + [BNXT_ULP_CLASS_HID_1ad40] = 2423, + [BNXT_ULP_CLASS_HID_1d03c] = 2424, + [BNXT_ULP_CLASS_HID_86e0] = 2425, + [BNXT_ULP_CLASS_HID_8334] = 2426, + [BNXT_ULP_CLASS_HID_1b934] = 2427, + [BNXT_ULP_CLASS_HID_1bce0] = 2428, + [BNXT_ULP_CLASS_HID_aa94] = 2429, + [BNXT_ULP_CLASS_HID_a7d8] = 2430, + [BNXT_ULP_CLASS_HID_1ddd8] = 2431, + [BNXT_ULP_CLASS_HID_1c094] = 2432, + [BNXT_ULP_CLASS_HID_904c] = 2433, + [BNXT_ULP_CLASS_HID_c84c] = 2434, + [BNXT_ULP_CLASS_HID_18290] = 2435, + [BNXT_ULP_CLASS_HID_1864c] = 2436, + [BNXT_ULP_CLASS_HID_b4f0] = 2437, + [BNXT_ULP_CLASS_HID_b104] = 2438, + [BNXT_ULP_CLASS_HID_1a704] = 2439, + [BNXT_ULP_CLASS_HID_1aaf0] = 2440, + [BNXT_ULP_CLASS_HID_80a4] = 2441, + [BNXT_ULP_CLASS_HID_9de8] = 2442, + [BNXT_ULP_CLASS_HID_1b3e8] = 2443, + [BNXT_ULP_CLASS_HID_1b6a4] = 2444, + [BNXT_ULP_CLASS_HID_a548] = 2445, + [BNXT_ULP_CLASS_HID_a19c] = 2446, + [BNXT_ULP_CLASS_HID_1d79c] = 2447, + [BNXT_ULP_CLASS_HID_1db48] = 2448, + [BNXT_ULP_CLASS_HID_9a98] = 2449, + [BNXT_ULP_CLASS_HID_97ac] = 2450, + [BNXT_ULP_CLASS_HID_18dac] = 2451, + [BNXT_ULP_CLASS_HID_1b098] = 2452, + [BNXT_ULP_CLASS_HID_bf0c] = 2453, + [BNXT_ULP_CLASS_HID_b850] = 2454, + [BNXT_ULP_CLASS_HID_1ae50] = 2455, + [BNXT_ULP_CLASS_HID_1d50c] = 2456, + [BNXT_ULP_CLASS_HID_34f0] = 2457, + [BNXT_ULP_CLASS_HID_3a3c] = 2458, + [BNXT_ULP_CLASS_HID_5ea0] = 2459, + [BNXT_ULP_CLASS_HID_0798] = 2460, + [BNXT_ULP_CLASS_HID_280c] = 2461, + [BNXT_ULP_CLASS_HID_5964] = 2462, + [BNXT_ULP_CLASS_HID_1e5c] = 2463, + [BNXT_ULP_CLASS_HID_22c0] = 2464, + [BNXT_ULP_CLASS_HID_a71c] = 2465, + [BNXT_ULP_CLASS_HID_a8dc] = 2466, + [BNXT_ULP_CLASS_HID_ed9c] = 2467, + [BNXT_ULP_CLASS_HID_ef5c] = 2468, + [BNXT_ULP_CLASS_HID_a060] = 2469, + [BNXT_ULP_CLASS_HID_a520] = 2470, + [BNXT_ULP_CLASS_HID_e6e0] = 2471, + [BNXT_ULP_CLASS_HID_eba0] = 2472, + [BNXT_ULP_CLASS_HID_1d660] = 2473, + [BNXT_ULP_CLASS_HID_1fb20] = 2474, + [BNXT_ULP_CLASS_HID_1dce0] = 2475, + [BNXT_ULP_CLASS_HID_1e1a0] = 2476, + [BNXT_ULP_CLASS_HID_1dd1c] = 2477, + [BNXT_ULP_CLASS_HID_1fedc] = 2478, + [BNXT_ULP_CLASS_HID_1c39c] = 2479, + [BNXT_ULP_CLASS_HID_1e55c] = 2480, + [BNXT_ULP_CLASS_HID_cb80] = 2481, + [BNXT_ULP_CLASS_HID_b194] = 2482, + [BNXT_ULP_CLASS_HID_d354] = 2483, + [BNXT_ULP_CLASS_HID_f414] = 2484, + [BNXT_ULP_CLASS_HID_c4d4] = 2485, + [BNXT_ULP_CLASS_HID_e994] = 2486, + [BNXT_ULP_CLASS_HID_cb54] = 2487, + [BNXT_ULP_CLASS_HID_f158] = 2488, + [BNXT_ULP_CLASS_HID_19f18] = 2489, + [BNXT_ULP_CLASS_HID_1a0d8] = 2490, + [BNXT_ULP_CLASS_HID_1c598] = 2491, + [BNXT_ULP_CLASS_HID_1e758] = 2492, + [BNXT_ULP_CLASS_HID_182d4] = 2493, + [BNXT_ULP_CLASS_HID_1a794] = 2494, + [BNXT_ULP_CLASS_HID_1c954] = 2495, + [BNXT_ULP_CLASS_HID_1ea14] = 2496, + [BNXT_ULP_CLASS_HID_b0b8] = 2497, + [BNXT_ULP_CLASS_HID_b278] = 2498, + [BNXT_ULP_CLASS_HID_f738] = 2499, + [BNXT_ULP_CLASS_HID_f8f8] = 2500, + [BNXT_ULP_CLASS_HID_8d8c] = 2501, + [BNXT_ULP_CLASS_HID_af4c] = 2502, + [BNXT_ULP_CLASS_HID_f00c] = 2503, + [BNXT_ULP_CLASS_HID_f5cc] = 2504, + [BNXT_ULP_CLASS_HID_1a38c] = 2505, + [BNXT_ULP_CLASS_HID_1a54c] = 2506, + [BNXT_ULP_CLASS_HID_1e60c] = 2507, + [BNXT_ULP_CLASS_HID_1ebcc] = 2508, + [BNXT_ULP_CLASS_HID_1a6b8] = 2509, + [BNXT_ULP_CLASS_HID_1a878] = 2510, + [BNXT_ULP_CLASS_HID_1ed38] = 2511, + [BNXT_ULP_CLASS_HID_1eef8] = 2512, + [BNXT_ULP_CLASS_HID_d52c] = 2513, + [BNXT_ULP_CLASS_HID_f6ec] = 2514, + [BNXT_ULP_CLASS_HID_dbac] = 2515, + [BNXT_ULP_CLASS_HID_fd6c] = 2516, + [BNXT_ULP_CLASS_HID_ae70] = 2517, + [BNXT_ULP_CLASS_HID_f330] = 2518, + [BNXT_ULP_CLASS_HID_d4f0] = 2519, + [BNXT_ULP_CLASS_HID_f9b0] = 2520, + [BNXT_ULP_CLASS_HID_1c470] = 2521, + [BNXT_ULP_CLASS_HID_1e930] = 2522, + [BNXT_ULP_CLASS_HID_1caf0] = 2523, + [BNXT_ULP_CLASS_HID_1f084] = 2524, + [BNXT_ULP_CLASS_HID_1cb2c] = 2525, + [BNXT_ULP_CLASS_HID_1b130] = 2526, + [BNXT_ULP_CLASS_HID_1d2f0] = 2527, + [BNXT_ULP_CLASS_HID_1f7b0] = 2528, + [BNXT_ULP_CLASS_HID_a1d0] = 2529, + [BNXT_ULP_CLASS_HID_a290] = 2530, + [BNXT_ULP_CLASS_HID_e450] = 2531, + [BNXT_ULP_CLASS_HID_e910] = 2532, + [BNXT_ULP_CLASS_HID_ba24] = 2533, + [BNXT_ULP_CLASS_HID_bfe4] = 2534, + [BNXT_ULP_CLASS_HID_e0a4] = 2535, + [BNXT_ULP_CLASS_HID_e264] = 2536, + [BNXT_ULP_CLASS_HID_1d024] = 2537, + [BNXT_ULP_CLASS_HID_1f5e4] = 2538, + [BNXT_ULP_CLASS_HID_1d6a4] = 2539, + [BNXT_ULP_CLASS_HID_1f864] = 2540, + [BNXT_ULP_CLASS_HID_1d7d0] = 2541, + [BNXT_ULP_CLASS_HID_1f890] = 2542, + [BNXT_ULP_CLASS_HID_1da50] = 2543, + [BNXT_ULP_CLASS_HID_1ff10] = 2544, + [BNXT_ULP_CLASS_HID_c244] = 2545, + [BNXT_ULP_CLASS_HID_e704] = 2546, + [BNXT_ULP_CLASS_HID_c8c4] = 2547, + [BNXT_ULP_CLASS_HID_ed84] = 2548, + [BNXT_ULP_CLASS_HID_de88] = 2549, + [BNXT_ULP_CLASS_HID_e048] = 2550, + [BNXT_ULP_CLASS_HID_c508] = 2551, + [BNXT_ULP_CLASS_HID_e6c8] = 2552, + [BNXT_ULP_CLASS_HID_199dc] = 2553, + [BNXT_ULP_CLASS_HID_1ba9c] = 2554, + [BNXT_ULP_CLASS_HID_1dc5c] = 2555, + [BNXT_ULP_CLASS_HID_1e11c] = 2556, + [BNXT_ULP_CLASS_HID_19c88] = 2557, + [BNXT_ULP_CLASS_HID_1be48] = 2558, + [BNXT_ULP_CLASS_HID_1c308] = 2559, + [BNXT_ULP_CLASS_HID_1e4c8] = 2560, + [BNXT_ULP_CLASS_HID_8b7c] = 2561, + [BNXT_ULP_CLASS_HID_ac3c] = 2562, + [BNXT_ULP_CLASS_HID_f1fc] = 2563, + [BNXT_ULP_CLASS_HID_f2bc] = 2564, + [BNXT_ULP_CLASS_HID_8440] = 2565, + [BNXT_ULP_CLASS_HID_a900] = 2566, + [BNXT_ULP_CLASS_HID_cac0] = 2567, + [BNXT_ULP_CLASS_HID_ef80] = 2568, + [BNXT_ULP_CLASS_HID_1ba40] = 2569, + [BNXT_ULP_CLASS_HID_1bf00] = 2570, + [BNXT_ULP_CLASS_HID_1e0c0] = 2571, + [BNXT_ULP_CLASS_HID_1e580] = 2572, + [BNXT_ULP_CLASS_HID_1a17c] = 2573, + [BNXT_ULP_CLASS_HID_1a23c] = 2574, + [BNXT_ULP_CLASS_HID_1e7fc] = 2575, + [BNXT_ULP_CLASS_HID_1e8bc] = 2576, + [BNXT_ULP_CLASS_HID_afe0] = 2577, + [BNXT_ULP_CLASS_HID_f0a0] = 2578, + [BNXT_ULP_CLASS_HID_d260] = 2579, + [BNXT_ULP_CLASS_HID_f720] = 2580, + [BNXT_ULP_CLASS_HID_a834] = 2581, + [BNXT_ULP_CLASS_HID_adf4] = 2582, + [BNXT_ULP_CLASS_HID_eeb4] = 2583, + [BNXT_ULP_CLASS_HID_f074] = 2584, + [BNXT_ULP_CLASS_HID_1de34] = 2585, + [BNXT_ULP_CLASS_HID_1e3f4] = 2586, + [BNXT_ULP_CLASS_HID_1c4b4] = 2587, + [BNXT_ULP_CLASS_HID_1e674] = 2588, + [BNXT_ULP_CLASS_HID_1c5e0] = 2589, + [BNXT_ULP_CLASS_HID_1e6a0] = 2590, + [BNXT_ULP_CLASS_HID_1c860] = 2591, + [BNXT_ULP_CLASS_HID_1ed20] = 2592, + [BNXT_ULP_CLASS_HID_8c0c] = 2593, + [BNXT_ULP_CLASS_HID_b1cc] = 2594, + [BNXT_ULP_CLASS_HID_f28c] = 2595, + [BNXT_ULP_CLASS_HID_f44c] = 2596, + [BNXT_ULP_CLASS_HID_8950] = 2597, + [BNXT_ULP_CLASS_HID_aa10] = 2598, + [BNXT_ULP_CLASS_HID_cfd0] = 2599, + [BNXT_ULP_CLASS_HID_f090] = 2600, + [BNXT_ULP_CLASS_HID_1bf50] = 2601, + [BNXT_ULP_CLASS_HID_1a010] = 2602, + [BNXT_ULP_CLASS_HID_1e5d0] = 2603, + [BNXT_ULP_CLASS_HID_1e690] = 2604, + [BNXT_ULP_CLASS_HID_1a20c] = 2605, + [BNXT_ULP_CLASS_HID_1a7cc] = 2606, + [BNXT_ULP_CLASS_HID_1e88c] = 2607, + [BNXT_ULP_CLASS_HID_1ea4c] = 2608, + [BNXT_ULP_CLASS_HID_d0f0] = 2609, + [BNXT_ULP_CLASS_HID_f5b0] = 2610, + [BNXT_ULP_CLASS_HID_d770] = 2611, + [BNXT_ULP_CLASS_HID_f830] = 2612, + [BNXT_ULP_CLASS_HID_adc4] = 2613, + [BNXT_ULP_CLASS_HID_ae84] = 2614, + [BNXT_ULP_CLASS_HID_d044] = 2615, + [BNXT_ULP_CLASS_HID_f504] = 2616, + [BNXT_ULP_CLASS_HID_1c3c4] = 2617, + [BNXT_ULP_CLASS_HID_1e484] = 2618, + [BNXT_ULP_CLASS_HID_1c644] = 2619, + [BNXT_ULP_CLASS_HID_1eb04] = 2620, + [BNXT_ULP_CLASS_HID_1c6f0] = 2621, + [BNXT_ULP_CLASS_HID_1ebb0] = 2622, + [BNXT_ULP_CLASS_HID_1cd70] = 2623, + [BNXT_ULP_CLASS_HID_1f304] = 2624, + [BNXT_ULP_CLASS_HID_99a8] = 2625, + [BNXT_ULP_CLASS_HID_bb68] = 2626, + [BNXT_ULP_CLASS_HID_dc28] = 2627, + [BNXT_ULP_CLASS_HID_e1e8] = 2628, + [BNXT_ULP_CLASS_HID_92fc] = 2629, + [BNXT_ULP_CLASS_HID_b7bc] = 2630, + [BNXT_ULP_CLASS_HID_d97c] = 2631, + [BNXT_ULP_CLASS_HID_fa3c] = 2632, + [BNXT_ULP_CLASS_HID_188fc] = 2633, + [BNXT_ULP_CLASS_HID_1adbc] = 2634, + [BNXT_ULP_CLASS_HID_1cf7c] = 2635, + [BNXT_ULP_CLASS_HID_1f03c] = 2636, + [BNXT_ULP_CLASS_HID_18fa8] = 2637, + [BNXT_ULP_CLASS_HID_1b168] = 2638, + [BNXT_ULP_CLASS_HID_1f228] = 2639, + [BNXT_ULP_CLASS_HID_1f7e8] = 2640, + [BNXT_ULP_CLASS_HID_ba1c] = 2641, + [BNXT_ULP_CLASS_HID_bfdc] = 2642, + [BNXT_ULP_CLASS_HID_e09c] = 2643, + [BNXT_ULP_CLASS_HID_e25c] = 2644, + [BNXT_ULP_CLASS_HID_b760] = 2645, + [BNXT_ULP_CLASS_HID_b820] = 2646, + [BNXT_ULP_CLASS_HID_fde0] = 2647, + [BNXT_ULP_CLASS_HID_fea0] = 2648, + [BNXT_ULP_CLASS_HID_1ad60] = 2649, + [BNXT_ULP_CLASS_HID_1ae20] = 2650, + [BNXT_ULP_CLASS_HID_1d3e0] = 2651, + [BNXT_ULP_CLASS_HID_1f4a0] = 2652, + [BNXT_ULP_CLASS_HID_1d01c] = 2653, + [BNXT_ULP_CLASS_HID_1f5dc] = 2654, + [BNXT_ULP_CLASS_HID_1d69c] = 2655, + [BNXT_ULP_CLASS_HID_1f85c] = 2656, + [BNXT_ULP_CLASS_HID_86c0] = 2657, + [BNXT_ULP_CLASS_HID_ab80] = 2658, + [BNXT_ULP_CLASS_HID_cd40] = 2659, + [BNXT_ULP_CLASS_HID_ee00] = 2660, + [BNXT_ULP_CLASS_HID_8314] = 2661, + [BNXT_ULP_CLASS_HID_a4d4] = 2662, + [BNXT_ULP_CLASS_HID_c994] = 2663, + [BNXT_ULP_CLASS_HID_eb54] = 2664, + [BNXT_ULP_CLASS_HID_1b914] = 2665, + [BNXT_ULP_CLASS_HID_1bad4] = 2666, + [BNXT_ULP_CLASS_HID_1ff94] = 2667, + [BNXT_ULP_CLASS_HID_1e154] = 2668, + [BNXT_ULP_CLASS_HID_1bcc0] = 2669, + [BNXT_ULP_CLASS_HID_1a180] = 2670, + [BNXT_ULP_CLASS_HID_1e340] = 2671, + [BNXT_ULP_CLASS_HID_1e400] = 2672, + [BNXT_ULP_CLASS_HID_aab4] = 2673, + [BNXT_ULP_CLASS_HID_ac74] = 2674, + [BNXT_ULP_CLASS_HID_d134] = 2675, + [BNXT_ULP_CLASS_HID_f2f4] = 2676, + [BNXT_ULP_CLASS_HID_a7f8] = 2677, + [BNXT_ULP_CLASS_HID_a8b8] = 2678, + [BNXT_ULP_CLASS_HID_ea78] = 2679, + [BNXT_ULP_CLASS_HID_ef38] = 2680, + [BNXT_ULP_CLASS_HID_1ddf8] = 2681, + [BNXT_ULP_CLASS_HID_1feb8] = 2682, + [BNXT_ULP_CLASS_HID_1c078] = 2683, + [BNXT_ULP_CLASS_HID_1e538] = 2684, + [BNXT_ULP_CLASS_HID_1c0b4] = 2685, + [BNXT_ULP_CLASS_HID_1e274] = 2686, + [BNXT_ULP_CLASS_HID_1c734] = 2687, + [BNXT_ULP_CLASS_HID_1e8f4] = 2688, + [BNXT_ULP_CLASS_HID_906c] = 2689, + [BNXT_ULP_CLASS_HID_b52c] = 2690, + [BNXT_ULP_CLASS_HID_d6ec] = 2691, + [BNXT_ULP_CLASS_HID_fbac] = 2692, + [BNXT_ULP_CLASS_HID_c86c] = 2693, + [BNXT_ULP_CLASS_HID_ed2c] = 2694, + [BNXT_ULP_CLASS_HID_d330] = 2695, + [BNXT_ULP_CLASS_HID_f4f0] = 2696, + [BNXT_ULP_CLASS_HID_182b0] = 2697, + [BNXT_ULP_CLASS_HID_1a470] = 2698, + [BNXT_ULP_CLASS_HID_1c930] = 2699, + [BNXT_ULP_CLASS_HID_1eaf0] = 2700, + [BNXT_ULP_CLASS_HID_1866c] = 2701, + [BNXT_ULP_CLASS_HID_1ab2c] = 2702, + [BNXT_ULP_CLASS_HID_1ccec] = 2703, + [BNXT_ULP_CLASS_HID_1f1ac] = 2704, + [BNXT_ULP_CLASS_HID_b4d0] = 2705, + [BNXT_ULP_CLASS_HID_b990] = 2706, + [BNXT_ULP_CLASS_HID_fb50] = 2707, + [BNXT_ULP_CLASS_HID_fc10] = 2708, + [BNXT_ULP_CLASS_HID_b124] = 2709, + [BNXT_ULP_CLASS_HID_b2e4] = 2710, + [BNXT_ULP_CLASS_HID_f7a4] = 2711, + [BNXT_ULP_CLASS_HID_f964] = 2712, + [BNXT_ULP_CLASS_HID_1a724] = 2713, + [BNXT_ULP_CLASS_HID_1a8e4] = 2714, + [BNXT_ULP_CLASS_HID_1eda4] = 2715, + [BNXT_ULP_CLASS_HID_1ef64] = 2716, + [BNXT_ULP_CLASS_HID_1aad0] = 2717, + [BNXT_ULP_CLASS_HID_1af90] = 2718, + [BNXT_ULP_CLASS_HID_1d150] = 2719, + [BNXT_ULP_CLASS_HID_1f210] = 2720, + [BNXT_ULP_CLASS_HID_8084] = 2721, + [BNXT_ULP_CLASS_HID_a244] = 2722, + [BNXT_ULP_CLASS_HID_c704] = 2723, + [BNXT_ULP_CLASS_HID_e8c4] = 2724, + [BNXT_ULP_CLASS_HID_9dc8] = 2725, + [BNXT_ULP_CLASS_HID_be88] = 2726, + [BNXT_ULP_CLASS_HID_c048] = 2727, + [BNXT_ULP_CLASS_HID_e508] = 2728, + [BNXT_ULP_CLASS_HID_1b3c8] = 2729, + [BNXT_ULP_CLASS_HID_1b488] = 2730, + [BNXT_ULP_CLASS_HID_1f648] = 2731, + [BNXT_ULP_CLASS_HID_1fb08] = 2732, + [BNXT_ULP_CLASS_HID_1b684] = 2733, + [BNXT_ULP_CLASS_HID_1b844] = 2734, + [BNXT_ULP_CLASS_HID_1fd04] = 2735, + [BNXT_ULP_CLASS_HID_1fec4] = 2736, + [BNXT_ULP_CLASS_HID_a568] = 2737, + [BNXT_ULP_CLASS_HID_a628] = 2738, + [BNXT_ULP_CLASS_HID_ebe8] = 2739, + [BNXT_ULP_CLASS_HID_eca8] = 2740, + [BNXT_ULP_CLASS_HID_a1bc] = 2741, + [BNXT_ULP_CLASS_HID_a37c] = 2742, + [BNXT_ULP_CLASS_HID_e43c] = 2743, + [BNXT_ULP_CLASS_HID_e9fc] = 2744, + [BNXT_ULP_CLASS_HID_1d7bc] = 2745, + [BNXT_ULP_CLASS_HID_1f97c] = 2746, + [BNXT_ULP_CLASS_HID_1da3c] = 2747, + [BNXT_ULP_CLASS_HID_1fffc] = 2748, + [BNXT_ULP_CLASS_HID_1db68] = 2749, + [BNXT_ULP_CLASS_HID_1fc28] = 2750, + [BNXT_ULP_CLASS_HID_1c1e8] = 2751, + [BNXT_ULP_CLASS_HID_1e2a8] = 2752, + [BNXT_ULP_CLASS_HID_9ab8] = 2753, + [BNXT_ULP_CLASS_HID_bc78] = 2754, + [BNXT_ULP_CLASS_HID_c138] = 2755, + [BNXT_ULP_CLASS_HID_e2f8] = 2756, + [BNXT_ULP_CLASS_HID_978c] = 2757, + [BNXT_ULP_CLASS_HID_b94c] = 2758, + [BNXT_ULP_CLASS_HID_da0c] = 2759, + [BNXT_ULP_CLASS_HID_ffcc] = 2760, + [BNXT_ULP_CLASS_HID_18d8c] = 2761, + [BNXT_ULP_CLASS_HID_1af4c] = 2762, + [BNXT_ULP_CLASS_HID_1f00c] = 2763, + [BNXT_ULP_CLASS_HID_1f5cc] = 2764, + [BNXT_ULP_CLASS_HID_1b0b8] = 2765, + [BNXT_ULP_CLASS_HID_1b278] = 2766, + [BNXT_ULP_CLASS_HID_1f738] = 2767, + [BNXT_ULP_CLASS_HID_1f8f8] = 2768, + [BNXT_ULP_CLASS_HID_bf2c] = 2769, + [BNXT_ULP_CLASS_HID_a0ec] = 2770, + [BNXT_ULP_CLASS_HID_e5ac] = 2771, + [BNXT_ULP_CLASS_HID_e76c] = 2772, + [BNXT_ULP_CLASS_HID_b870] = 2773, + [BNXT_ULP_CLASS_HID_bd30] = 2774, + [BNXT_ULP_CLASS_HID_fef0] = 2775, + [BNXT_ULP_CLASS_HID_e3b0] = 2776, + [BNXT_ULP_CLASS_HID_1ae70] = 2777, + [BNXT_ULP_CLASS_HID_1f330] = 2778, + [BNXT_ULP_CLASS_HID_1d4f0] = 2779, + [BNXT_ULP_CLASS_HID_1f9b0] = 2780, + [BNXT_ULP_CLASS_HID_1d52c] = 2781, + [BNXT_ULP_CLASS_HID_1f6ec] = 2782, + [BNXT_ULP_CLASS_HID_1dbac] = 2783, + [BNXT_ULP_CLASS_HID_1fd6c] = 2784, + [BNXT_ULP_CLASS_HID_34d0] = 2785, + [BNXT_ULP_CLASS_HID_3a1c] = 2786, + [BNXT_ULP_CLASS_HID_5e80] = 2787, + [BNXT_ULP_CLASS_HID_07b8] = 2788, + [BNXT_ULP_CLASS_HID_282c] = 2789, + [BNXT_ULP_CLASS_HID_5944] = 2790, + [BNXT_ULP_CLASS_HID_1e7c] = 2791, + [BNXT_ULP_CLASS_HID_22e0] = 2792, + [BNXT_ULP_CLASS_HID_a77c] = 2793, + [BNXT_ULP_CLASS_HID_a8bc] = 2794, + [BNXT_ULP_CLASS_HID_edfc] = 2795, + [BNXT_ULP_CLASS_HID_ef3c] = 2796, + [BNXT_ULP_CLASS_HID_a000] = 2797, + [BNXT_ULP_CLASS_HID_a540] = 2798, + [BNXT_ULP_CLASS_HID_e680] = 2799, + [BNXT_ULP_CLASS_HID_ebc0] = 2800, + [BNXT_ULP_CLASS_HID_1d600] = 2801, + [BNXT_ULP_CLASS_HID_1fb40] = 2802, + [BNXT_ULP_CLASS_HID_1dc80] = 2803, + [BNXT_ULP_CLASS_HID_1e1c0] = 2804, + [BNXT_ULP_CLASS_HID_1dd7c] = 2805, + [BNXT_ULP_CLASS_HID_1febc] = 2806, + [BNXT_ULP_CLASS_HID_1c3fc] = 2807, + [BNXT_ULP_CLASS_HID_1e53c] = 2808, + [BNXT_ULP_CLASS_HID_cbe0] = 2809, + [BNXT_ULP_CLASS_HID_b1f4] = 2810, + [BNXT_ULP_CLASS_HID_d334] = 2811, + [BNXT_ULP_CLASS_HID_f474] = 2812, + [BNXT_ULP_CLASS_HID_c4b4] = 2813, + [BNXT_ULP_CLASS_HID_e9f4] = 2814, + [BNXT_ULP_CLASS_HID_cb34] = 2815, + [BNXT_ULP_CLASS_HID_f138] = 2816, + [BNXT_ULP_CLASS_HID_19f78] = 2817, + [BNXT_ULP_CLASS_HID_1a0b8] = 2818, + [BNXT_ULP_CLASS_HID_1c5f8] = 2819, + [BNXT_ULP_CLASS_HID_1e738] = 2820, + [BNXT_ULP_CLASS_HID_182b4] = 2821, + [BNXT_ULP_CLASS_HID_1a7f4] = 2822, + [BNXT_ULP_CLASS_HID_1c934] = 2823, + [BNXT_ULP_CLASS_HID_1ea74] = 2824, + [BNXT_ULP_CLASS_HID_b0d8] = 2825, + [BNXT_ULP_CLASS_HID_b218] = 2826, + [BNXT_ULP_CLASS_HID_f758] = 2827, + [BNXT_ULP_CLASS_HID_f898] = 2828, + [BNXT_ULP_CLASS_HID_8dec] = 2829, + [BNXT_ULP_CLASS_HID_af2c] = 2830, + [BNXT_ULP_CLASS_HID_f06c] = 2831, + [BNXT_ULP_CLASS_HID_f5ac] = 2832, + [BNXT_ULP_CLASS_HID_1a3ec] = 2833, + [BNXT_ULP_CLASS_HID_1a52c] = 2834, + [BNXT_ULP_CLASS_HID_1e66c] = 2835, + [BNXT_ULP_CLASS_HID_1ebac] = 2836, + [BNXT_ULP_CLASS_HID_1a6d8] = 2837, + [BNXT_ULP_CLASS_HID_1a818] = 2838, + [BNXT_ULP_CLASS_HID_1ed58] = 2839, + [BNXT_ULP_CLASS_HID_1ee98] = 2840, + [BNXT_ULP_CLASS_HID_d54c] = 2841, + [BNXT_ULP_CLASS_HID_f68c] = 2842, + [BNXT_ULP_CLASS_HID_dbcc] = 2843, + [BNXT_ULP_CLASS_HID_fd0c] = 2844, + [BNXT_ULP_CLASS_HID_ae10] = 2845, + [BNXT_ULP_CLASS_HID_f350] = 2846, + [BNXT_ULP_CLASS_HID_d490] = 2847, + [BNXT_ULP_CLASS_HID_f9d0] = 2848, + [BNXT_ULP_CLASS_HID_1c410] = 2849, + [BNXT_ULP_CLASS_HID_1e950] = 2850, + [BNXT_ULP_CLASS_HID_1ca90] = 2851, + [BNXT_ULP_CLASS_HID_1f0e4] = 2852, + [BNXT_ULP_CLASS_HID_1cb4c] = 2853, + [BNXT_ULP_CLASS_HID_1b150] = 2854, + [BNXT_ULP_CLASS_HID_1d290] = 2855, + [BNXT_ULP_CLASS_HID_1f7d0] = 2856, + [BNXT_ULP_CLASS_HID_a1b0] = 2857, + [BNXT_ULP_CLASS_HID_a2f0] = 2858, + [BNXT_ULP_CLASS_HID_e430] = 2859, + [BNXT_ULP_CLASS_HID_e970] = 2860, + [BNXT_ULP_CLASS_HID_ba44] = 2861, + [BNXT_ULP_CLASS_HID_bf84] = 2862, + [BNXT_ULP_CLASS_HID_e0c4] = 2863, + [BNXT_ULP_CLASS_HID_e204] = 2864, + [BNXT_ULP_CLASS_HID_1d044] = 2865, + [BNXT_ULP_CLASS_HID_1f584] = 2866, + [BNXT_ULP_CLASS_HID_1d6c4] = 2867, + [BNXT_ULP_CLASS_HID_1f804] = 2868, + [BNXT_ULP_CLASS_HID_1d7b0] = 2869, + [BNXT_ULP_CLASS_HID_1f8f0] = 2870, + [BNXT_ULP_CLASS_HID_1da30] = 2871, + [BNXT_ULP_CLASS_HID_1ff70] = 2872, + [BNXT_ULP_CLASS_HID_c224] = 2873, + [BNXT_ULP_CLASS_HID_e764] = 2874, + [BNXT_ULP_CLASS_HID_c8a4] = 2875, + [BNXT_ULP_CLASS_HID_ede4] = 2876, + [BNXT_ULP_CLASS_HID_dee8] = 2877, + [BNXT_ULP_CLASS_HID_e028] = 2878, + [BNXT_ULP_CLASS_HID_c568] = 2879, + [BNXT_ULP_CLASS_HID_e6a8] = 2880, + [BNXT_ULP_CLASS_HID_199bc] = 2881, + [BNXT_ULP_CLASS_HID_1bafc] = 2882, + [BNXT_ULP_CLASS_HID_1dc3c] = 2883, + [BNXT_ULP_CLASS_HID_1e17c] = 2884, + [BNXT_ULP_CLASS_HID_19ce8] = 2885, + [BNXT_ULP_CLASS_HID_1be28] = 2886, + [BNXT_ULP_CLASS_HID_1c368] = 2887, + [BNXT_ULP_CLASS_HID_1e4a8] = 2888, + [BNXT_ULP_CLASS_HID_8b1c] = 2889, + [BNXT_ULP_CLASS_HID_ac5c] = 2890, + [BNXT_ULP_CLASS_HID_f19c] = 2891, + [BNXT_ULP_CLASS_HID_f2dc] = 2892, + [BNXT_ULP_CLASS_HID_8420] = 2893, + [BNXT_ULP_CLASS_HID_a960] = 2894, + [BNXT_ULP_CLASS_HID_caa0] = 2895, + [BNXT_ULP_CLASS_HID_efe0] = 2896, + [BNXT_ULP_CLASS_HID_1ba20] = 2897, + [BNXT_ULP_CLASS_HID_1bf60] = 2898, + [BNXT_ULP_CLASS_HID_1e0a0] = 2899, + [BNXT_ULP_CLASS_HID_1e5e0] = 2900, + [BNXT_ULP_CLASS_HID_1a11c] = 2901, + [BNXT_ULP_CLASS_HID_1a25c] = 2902, + [BNXT_ULP_CLASS_HID_1e79c] = 2903, + [BNXT_ULP_CLASS_HID_1e8dc] = 2904, + [BNXT_ULP_CLASS_HID_af80] = 2905, + [BNXT_ULP_CLASS_HID_f0c0] = 2906, + [BNXT_ULP_CLASS_HID_d200] = 2907, + [BNXT_ULP_CLASS_HID_f740] = 2908, + [BNXT_ULP_CLASS_HID_a854] = 2909, + [BNXT_ULP_CLASS_HID_ad94] = 2910, + [BNXT_ULP_CLASS_HID_eed4] = 2911, + [BNXT_ULP_CLASS_HID_f014] = 2912, + [BNXT_ULP_CLASS_HID_1de54] = 2913, + [BNXT_ULP_CLASS_HID_1e394] = 2914, + [BNXT_ULP_CLASS_HID_1c4d4] = 2915, + [BNXT_ULP_CLASS_HID_1e614] = 2916, + [BNXT_ULP_CLASS_HID_1c580] = 2917, + [BNXT_ULP_CLASS_HID_1e6c0] = 2918, + [BNXT_ULP_CLASS_HID_1c800] = 2919, + [BNXT_ULP_CLASS_HID_1ed40] = 2920, + [BNXT_ULP_CLASS_HID_8c6c] = 2921, + [BNXT_ULP_CLASS_HID_b1ac] = 2922, + [BNXT_ULP_CLASS_HID_f2ec] = 2923, + [BNXT_ULP_CLASS_HID_f42c] = 2924, + [BNXT_ULP_CLASS_HID_8930] = 2925, + [BNXT_ULP_CLASS_HID_aa70] = 2926, + [BNXT_ULP_CLASS_HID_cfb0] = 2927, + [BNXT_ULP_CLASS_HID_f0f0] = 2928, + [BNXT_ULP_CLASS_HID_1bf30] = 2929, + [BNXT_ULP_CLASS_HID_1a070] = 2930, + [BNXT_ULP_CLASS_HID_1e5b0] = 2931, + [BNXT_ULP_CLASS_HID_1e6f0] = 2932, + [BNXT_ULP_CLASS_HID_1a26c] = 2933, + [BNXT_ULP_CLASS_HID_1a7ac] = 2934, + [BNXT_ULP_CLASS_HID_1e8ec] = 2935, + [BNXT_ULP_CLASS_HID_1ea2c] = 2936, + [BNXT_ULP_CLASS_HID_d090] = 2937, + [BNXT_ULP_CLASS_HID_f5d0] = 2938, + [BNXT_ULP_CLASS_HID_d710] = 2939, + [BNXT_ULP_CLASS_HID_f850] = 2940, + [BNXT_ULP_CLASS_HID_ada4] = 2941, + [BNXT_ULP_CLASS_HID_aee4] = 2942, + [BNXT_ULP_CLASS_HID_d024] = 2943, + [BNXT_ULP_CLASS_HID_f564] = 2944, + [BNXT_ULP_CLASS_HID_1c3a4] = 2945, + [BNXT_ULP_CLASS_HID_1e4e4] = 2946, + [BNXT_ULP_CLASS_HID_1c624] = 2947, + [BNXT_ULP_CLASS_HID_1eb64] = 2948, + [BNXT_ULP_CLASS_HID_1c690] = 2949, + [BNXT_ULP_CLASS_HID_1ebd0] = 2950, + [BNXT_ULP_CLASS_HID_1cd10] = 2951, + [BNXT_ULP_CLASS_HID_1f364] = 2952, + [BNXT_ULP_CLASS_HID_99c8] = 2953, + [BNXT_ULP_CLASS_HID_bb08] = 2954, + [BNXT_ULP_CLASS_HID_dc48] = 2955, + [BNXT_ULP_CLASS_HID_e188] = 2956, + [BNXT_ULP_CLASS_HID_929c] = 2957, + [BNXT_ULP_CLASS_HID_b7dc] = 2958, + [BNXT_ULP_CLASS_HID_d91c] = 2959, + [BNXT_ULP_CLASS_HID_fa5c] = 2960, + [BNXT_ULP_CLASS_HID_1889c] = 2961, + [BNXT_ULP_CLASS_HID_1addc] = 2962, + [BNXT_ULP_CLASS_HID_1cf1c] = 2963, + [BNXT_ULP_CLASS_HID_1f05c] = 2964, + [BNXT_ULP_CLASS_HID_18fc8] = 2965, + [BNXT_ULP_CLASS_HID_1b108] = 2966, + [BNXT_ULP_CLASS_HID_1f248] = 2967, + [BNXT_ULP_CLASS_HID_1f788] = 2968, + [BNXT_ULP_CLASS_HID_ba7c] = 2969, + [BNXT_ULP_CLASS_HID_bfbc] = 2970, + [BNXT_ULP_CLASS_HID_e0fc] = 2971, + [BNXT_ULP_CLASS_HID_e23c] = 2972, + [BNXT_ULP_CLASS_HID_b700] = 2973, + [BNXT_ULP_CLASS_HID_b840] = 2974, + [BNXT_ULP_CLASS_HID_fd80] = 2975, + [BNXT_ULP_CLASS_HID_fec0] = 2976, + [BNXT_ULP_CLASS_HID_1ad00] = 2977, + [BNXT_ULP_CLASS_HID_1ae40] = 2978, + [BNXT_ULP_CLASS_HID_1d380] = 2979, + [BNXT_ULP_CLASS_HID_1f4c0] = 2980, + [BNXT_ULP_CLASS_HID_1d07c] = 2981, + [BNXT_ULP_CLASS_HID_1f5bc] = 2982, + [BNXT_ULP_CLASS_HID_1d6fc] = 2983, + [BNXT_ULP_CLASS_HID_1f83c] = 2984, + [BNXT_ULP_CLASS_HID_86a0] = 2985, + [BNXT_ULP_CLASS_HID_abe0] = 2986, + [BNXT_ULP_CLASS_HID_cd20] = 2987, + [BNXT_ULP_CLASS_HID_ee60] = 2988, + [BNXT_ULP_CLASS_HID_8374] = 2989, + [BNXT_ULP_CLASS_HID_a4b4] = 2990, + [BNXT_ULP_CLASS_HID_c9f4] = 2991, + [BNXT_ULP_CLASS_HID_eb34] = 2992, + [BNXT_ULP_CLASS_HID_1b974] = 2993, + [BNXT_ULP_CLASS_HID_1bab4] = 2994, + [BNXT_ULP_CLASS_HID_1fff4] = 2995, + [BNXT_ULP_CLASS_HID_1e134] = 2996, + [BNXT_ULP_CLASS_HID_1bca0] = 2997, + [BNXT_ULP_CLASS_HID_1a1e0] = 2998, + [BNXT_ULP_CLASS_HID_1e320] = 2999, + [BNXT_ULP_CLASS_HID_1e460] = 3000, + [BNXT_ULP_CLASS_HID_aad4] = 3001, + [BNXT_ULP_CLASS_HID_ac14] = 3002, + [BNXT_ULP_CLASS_HID_d154] = 3003, + [BNXT_ULP_CLASS_HID_f294] = 3004, + [BNXT_ULP_CLASS_HID_a798] = 3005, + [BNXT_ULP_CLASS_HID_a8d8] = 3006, + [BNXT_ULP_CLASS_HID_ea18] = 3007, + [BNXT_ULP_CLASS_HID_ef58] = 3008, + [BNXT_ULP_CLASS_HID_1dd98] = 3009, + [BNXT_ULP_CLASS_HID_1fed8] = 3010, + [BNXT_ULP_CLASS_HID_1c018] = 3011, + [BNXT_ULP_CLASS_HID_1e558] = 3012, + [BNXT_ULP_CLASS_HID_1c0d4] = 3013, + [BNXT_ULP_CLASS_HID_1e214] = 3014, + [BNXT_ULP_CLASS_HID_1c754] = 3015, + [BNXT_ULP_CLASS_HID_1e894] = 3016, + [BNXT_ULP_CLASS_HID_900c] = 3017, + [BNXT_ULP_CLASS_HID_b54c] = 3018, + [BNXT_ULP_CLASS_HID_d68c] = 3019, + [BNXT_ULP_CLASS_HID_fbcc] = 3020, + [BNXT_ULP_CLASS_HID_c80c] = 3021, + [BNXT_ULP_CLASS_HID_ed4c] = 3022, + [BNXT_ULP_CLASS_HID_d350] = 3023, + [BNXT_ULP_CLASS_HID_f490] = 3024, + [BNXT_ULP_CLASS_HID_182d0] = 3025, + [BNXT_ULP_CLASS_HID_1a410] = 3026, + [BNXT_ULP_CLASS_HID_1c950] = 3027, + [BNXT_ULP_CLASS_HID_1ea90] = 3028, + [BNXT_ULP_CLASS_HID_1860c] = 3029, + [BNXT_ULP_CLASS_HID_1ab4c] = 3030, + [BNXT_ULP_CLASS_HID_1cc8c] = 3031, + [BNXT_ULP_CLASS_HID_1f1cc] = 3032, + [BNXT_ULP_CLASS_HID_b4b0] = 3033, + [BNXT_ULP_CLASS_HID_b9f0] = 3034, + [BNXT_ULP_CLASS_HID_fb30] = 3035, + [BNXT_ULP_CLASS_HID_fc70] = 3036, + [BNXT_ULP_CLASS_HID_b144] = 3037, + [BNXT_ULP_CLASS_HID_b284] = 3038, + [BNXT_ULP_CLASS_HID_f7c4] = 3039, + [BNXT_ULP_CLASS_HID_f904] = 3040, + [BNXT_ULP_CLASS_HID_1a744] = 3041, + [BNXT_ULP_CLASS_HID_1a884] = 3042, + [BNXT_ULP_CLASS_HID_1edc4] = 3043, + [BNXT_ULP_CLASS_HID_1ef04] = 3044, + [BNXT_ULP_CLASS_HID_1aab0] = 3045, + [BNXT_ULP_CLASS_HID_1aff0] = 3046, + [BNXT_ULP_CLASS_HID_1d130] = 3047, + [BNXT_ULP_CLASS_HID_1f270] = 3048, + [BNXT_ULP_CLASS_HID_80e4] = 3049, + [BNXT_ULP_CLASS_HID_a224] = 3050, + [BNXT_ULP_CLASS_HID_c764] = 3051, + [BNXT_ULP_CLASS_HID_e8a4] = 3052, + [BNXT_ULP_CLASS_HID_9da8] = 3053, + [BNXT_ULP_CLASS_HID_bee8] = 3054, + [BNXT_ULP_CLASS_HID_c028] = 3055, + [BNXT_ULP_CLASS_HID_e568] = 3056, + [BNXT_ULP_CLASS_HID_1b3a8] = 3057, + [BNXT_ULP_CLASS_HID_1b4e8] = 3058, + [BNXT_ULP_CLASS_HID_1f628] = 3059, + [BNXT_ULP_CLASS_HID_1fb68] = 3060, + [BNXT_ULP_CLASS_HID_1b6e4] = 3061, + [BNXT_ULP_CLASS_HID_1b824] = 3062, + [BNXT_ULP_CLASS_HID_1fd64] = 3063, + [BNXT_ULP_CLASS_HID_1fea4] = 3064, + [BNXT_ULP_CLASS_HID_a508] = 3065, + [BNXT_ULP_CLASS_HID_a648] = 3066, + [BNXT_ULP_CLASS_HID_eb88] = 3067, + [BNXT_ULP_CLASS_HID_ecc8] = 3068, + [BNXT_ULP_CLASS_HID_a1dc] = 3069, + [BNXT_ULP_CLASS_HID_a31c] = 3070, + [BNXT_ULP_CLASS_HID_e45c] = 3071, + [BNXT_ULP_CLASS_HID_e99c] = 3072, + [BNXT_ULP_CLASS_HID_1d7dc] = 3073, + [BNXT_ULP_CLASS_HID_1f91c] = 3074, + [BNXT_ULP_CLASS_HID_1da5c] = 3075, + [BNXT_ULP_CLASS_HID_1ff9c] = 3076, + [BNXT_ULP_CLASS_HID_1db08] = 3077, + [BNXT_ULP_CLASS_HID_1fc48] = 3078, + [BNXT_ULP_CLASS_HID_1c188] = 3079, + [BNXT_ULP_CLASS_HID_1e2c8] = 3080, + [BNXT_ULP_CLASS_HID_9ad8] = 3081, + [BNXT_ULP_CLASS_HID_bc18] = 3082, + [BNXT_ULP_CLASS_HID_c158] = 3083, + [BNXT_ULP_CLASS_HID_e298] = 3084, + [BNXT_ULP_CLASS_HID_97ec] = 3085, + [BNXT_ULP_CLASS_HID_b92c] = 3086, + [BNXT_ULP_CLASS_HID_da6c] = 3087, + [BNXT_ULP_CLASS_HID_ffac] = 3088, + [BNXT_ULP_CLASS_HID_18dec] = 3089, + [BNXT_ULP_CLASS_HID_1af2c] = 3090, + [BNXT_ULP_CLASS_HID_1f06c] = 3091, + [BNXT_ULP_CLASS_HID_1f5ac] = 3092, + [BNXT_ULP_CLASS_HID_1b0d8] = 3093, + [BNXT_ULP_CLASS_HID_1b218] = 3094, + [BNXT_ULP_CLASS_HID_1f758] = 3095, + [BNXT_ULP_CLASS_HID_1f898] = 3096, + [BNXT_ULP_CLASS_HID_bf4c] = 3097, + [BNXT_ULP_CLASS_HID_a08c] = 3098, + [BNXT_ULP_CLASS_HID_e5cc] = 3099, + [BNXT_ULP_CLASS_HID_e70c] = 3100, + [BNXT_ULP_CLASS_HID_b810] = 3101, + [BNXT_ULP_CLASS_HID_bd50] = 3102, + [BNXT_ULP_CLASS_HID_fe90] = 3103, + [BNXT_ULP_CLASS_HID_e3d0] = 3104, + [BNXT_ULP_CLASS_HID_1ae10] = 3105, + [BNXT_ULP_CLASS_HID_1f350] = 3106, + [BNXT_ULP_CLASS_HID_1d490] = 3107, + [BNXT_ULP_CLASS_HID_1f9d0] = 3108, + [BNXT_ULP_CLASS_HID_1d54c] = 3109, + [BNXT_ULP_CLASS_HID_1f68c] = 3110, + [BNXT_ULP_CLASS_HID_1dbcc] = 3111, + [BNXT_ULP_CLASS_HID_1fd0c] = 3112, + [BNXT_ULP_CLASS_HID_34b0] = 3113, + [BNXT_ULP_CLASS_HID_3a7c] = 3114, + [BNXT_ULP_CLASS_HID_5ee0] = 3115, + [BNXT_ULP_CLASS_HID_07d8] = 3116, + [BNXT_ULP_CLASS_HID_284c] = 3117, + [BNXT_ULP_CLASS_HID_5924] = 3118, + [BNXT_ULP_CLASS_HID_1e1c] = 3119, + [BNXT_ULP_CLASS_HID_2280] = 3120, + [BNXT_ULP_CLASS_HID_24604] = 3121, + [BNXT_ULP_CLASS_HID_255d4] = 3122, + [BNXT_ULP_CLASS_HID_22e08] = 3123, + [BNXT_ULP_CLASS_HID_24378] = 3124, + [BNXT_ULP_CLASS_HID_20fcc] = 3125, + [BNXT_ULP_CLASS_HID_21a9c] = 3126, + [BNXT_ULP_CLASS_HID_217d0] = 3127, + [BNXT_ULP_CLASS_HID_20800] = 3128, + [BNXT_ULP_CLASS_HID_253a0] = 3129, + [BNXT_ULP_CLASS_HID_23f70] = 3130, + [BNXT_ULP_CLASS_HID_23ba4] = 3131, + [BNXT_ULP_CLASS_HID_22c94] = 3132, + [BNXT_ULP_CLASS_HID_21968] = 3133, + [BNXT_ULP_CLASS_HID_243c4] = 3134, + [BNXT_ULP_CLASS_HID_25c38] = 3135, + [BNXT_ULP_CLASS_HID_2125c] = 3136, + [BNXT_ULP_CLASS_HID_240c8] = 3137, + [BNXT_ULP_CLASS_HID_22f98] = 3138, + [BNXT_ULP_CLASS_HID_228cc] = 3139, + [BNXT_ULP_CLASS_HID_25d3c] = 3140, + [BNXT_ULP_CLASS_HID_20990] = 3141, + [BNXT_ULP_CLASS_HID_214a0] = 3142, + [BNXT_ULP_CLASS_HID_21194] = 3143, + [BNXT_ULP_CLASS_HID_202c4] = 3144, + [BNXT_ULP_CLASS_HID_22a64] = 3145, + [BNXT_ULP_CLASS_HID_23934] = 3146, + [BNXT_ULP_CLASS_HID_23268] = 3147, + [BNXT_ULP_CLASS_HID_22758] = 3148, + [BNXT_ULP_CLASS_HID_2132c] = 3149, + [BNXT_ULP_CLASS_HID_25d88] = 3150, + [BNXT_ULP_CLASS_HID_256fc] = 3151, + [BNXT_ULP_CLASS_HID_24b2c] = 3152, + [BNXT_ULP_CLASS_HID_22f14] = 3153, + [BNXT_ULP_CLASS_HID_23a24] = 3154, + [BNXT_ULP_CLASS_HID_23718] = 3155, + [BNXT_ULP_CLASS_HID_22848] = 3156, + [BNXT_ULP_CLASS_HID_214dc] = 3157, + [BNXT_ULP_CLASS_HID_25eb8] = 3158, + [BNXT_ULP_CLASS_HID_25bec] = 3159, + [BNXT_ULP_CLASS_HID_21110] = 3160, + [BNXT_ULP_CLASS_HID_238b0] = 3161, + [BNXT_ULP_CLASS_HID_20440] = 3162, + [BNXT_ULP_CLASS_HID_200b4] = 3163, + [BNXT_ULP_CLASS_HID_235e4] = 3164, + [BNXT_ULP_CLASS_HID_25d04] = 3165, + [BNXT_ULP_CLASS_HID_228d4] = 3166, + [BNXT_ULP_CLASS_HID_22508] = 3167, + [BNXT_ULP_CLASS_HID_25678] = 3168, + [BNXT_ULP_CLASS_HID_229d8] = 3169, + [BNXT_ULP_CLASS_HID_234e8] = 3170, + [BNXT_ULP_CLASS_HID_231dc] = 3171, + [BNXT_ULP_CLASS_HID_2220c] = 3172, + [BNXT_ULP_CLASS_HID_24dac] = 3173, + [BNXT_ULP_CLASS_HID_2597c] = 3174, + [BNXT_ULP_CLASS_HID_255b0] = 3175, + [BNXT_ULP_CLASS_HID_246e0] = 3176, + [BNXT_ULP_CLASS_HID_23374] = 3177, + [BNXT_ULP_CLASS_HID_21e04] = 3178, + [BNXT_ULP_CLASS_HID_21b78] = 3179, + [BNXT_ULP_CLASS_HID_20fa8] = 3180, + [BNXT_ULP_CLASS_HID_257c8] = 3181, + [BNXT_ULP_CLASS_HID_22298] = 3182, + [BNXT_ULP_CLASS_HID_23fcc] = 3183, + [BNXT_ULP_CLASS_HID_2503c] = 3184, + [BNXT_ULP_CLASS_HID_2239c] = 3185, + [BNXT_ULP_CLASS_HID_20eac] = 3186, + [BNXT_ULP_CLASS_HID_20be0] = 3187, + [BNXT_ULP_CLASS_HID_23cd0] = 3188, + [BNXT_ULP_CLASS_HID_24470] = 3189, + [BNXT_ULP_CLASS_HID_25300] = 3190, + [BNXT_ULP_CLASS_HID_22c74] = 3191, + [BNXT_ULP_CLASS_HID_240a4] = 3192, + [BNXT_ULP_CLASS_HID_23da0] = 3193, + [BNXT_ULP_CLASS_HID_20970] = 3194, + [BNXT_ULP_CLASS_HID_205a4] = 3195, + [BNXT_ULP_CLASS_HID_23694] = 3196, + [BNXT_ULP_CLASS_HID_25e34] = 3197, + [BNXT_ULP_CLASS_HID_22dc4] = 3198, + [BNXT_ULP_CLASS_HID_22638] = 3199, + [BNXT_ULP_CLASS_HID_25b68] = 3200, + [BNXT_ULP_CLASS_HID_34c8] = 3201, + [BNXT_ULP_CLASS_HID_3a04] = 3202, + [BNXT_ULP_CLASS_HID_5e98] = 3203, + [BNXT_ULP_CLASS_HID_07a0] = 3204, + [BNXT_ULP_CLASS_HID_2834] = 3205, + [BNXT_ULP_CLASS_HID_595c] = 3206, + [BNXT_ULP_CLASS_HID_1e64] = 3207, + [BNXT_ULP_CLASS_HID_22f8] = 3208, + [BNXT_ULP_CLASS_HID_24664] = 3209, + [BNXT_ULP_CLASS_HID_29418] = 3210, + [BNXT_ULP_CLASS_HID_30118] = 3211, + [BNXT_ULP_CLASS_HID_38a18] = 3212, + [BNXT_ULP_CLASS_HID_255b4] = 3213, + [BNXT_ULP_CLASS_HID_2deb4] = 3214, + [BNXT_ULP_CLASS_HID_34bb4] = 3215, + [BNXT_ULP_CLASS_HID_39968] = 3216, + [BNXT_ULP_CLASS_HID_22e68] = 3217, + [BNXT_ULP_CLASS_HID_2db68] = 3218, + [BNXT_ULP_CLASS_HID_34468] = 3219, + [BNXT_ULP_CLASS_HID_3921c] = 3220, + [BNXT_ULP_CLASS_HID_24318] = 3221, + [BNXT_ULP_CLASS_HID_290cc] = 3222, + [BNXT_ULP_CLASS_HID_31dcc] = 3223, + [BNXT_ULP_CLASS_HID_386cc] = 3224, + [BNXT_ULP_CLASS_HID_20fac] = 3225, + [BNXT_ULP_CLASS_HID_2b8ac] = 3226, + [BNXT_ULP_CLASS_HID_325ac] = 3227, + [BNXT_ULP_CLASS_HID_3aeac] = 3228, + [BNXT_ULP_CLASS_HID_21afc] = 3229, + [BNXT_ULP_CLASS_HID_287fc] = 3230, + [BNXT_ULP_CLASS_HID_330fc] = 3231, + [BNXT_ULP_CLASS_HID_3bdfc] = 3232, + [BNXT_ULP_CLASS_HID_217b0] = 3233, + [BNXT_ULP_CLASS_HID_280b0] = 3234, + [BNXT_ULP_CLASS_HID_30db0] = 3235, + [BNXT_ULP_CLASS_HID_3b6b0] = 3236, + [BNXT_ULP_CLASS_HID_20860] = 3237, + [BNXT_ULP_CLASS_HID_2b560] = 3238, + [BNXT_ULP_CLASS_HID_33e60] = 3239, + [BNXT_ULP_CLASS_HID_3ab60] = 3240, + [BNXT_ULP_CLASS_HID_253c0] = 3241, + [BNXT_ULP_CLASS_HID_2dcc0] = 3242, + [BNXT_ULP_CLASS_HID_349c0] = 3243, + [BNXT_ULP_CLASS_HID_397f4] = 3244, + [BNXT_ULP_CLASS_HID_23f10] = 3245, + [BNXT_ULP_CLASS_HID_2a810] = 3246, + [BNXT_ULP_CLASS_HID_35510] = 3247, + [BNXT_ULP_CLASS_HID_3de10] = 3248, + [BNXT_ULP_CLASS_HID_23bc4] = 3249, + [BNXT_ULP_CLASS_HID_2a4c4] = 3250, + [BNXT_ULP_CLASS_HID_351c4] = 3251, + [BNXT_ULP_CLASS_HID_3dac4] = 3252, + [BNXT_ULP_CLASS_HID_22cf4] = 3253, + [BNXT_ULP_CLASS_HID_2d9f4] = 3254, + [BNXT_ULP_CLASS_HID_342f4] = 3255, + [BNXT_ULP_CLASS_HID_390a8] = 3256, + [BNXT_ULP_CLASS_HID_21908] = 3257, + [BNXT_ULP_CLASS_HID_28208] = 3258, + [BNXT_ULP_CLASS_HID_30f08] = 3259, + [BNXT_ULP_CLASS_HID_3b808] = 3260, + [BNXT_ULP_CLASS_HID_243a4] = 3261, + [BNXT_ULP_CLASS_HID_29158] = 3262, + [BNXT_ULP_CLASS_HID_31a58] = 3263, + [BNXT_ULP_CLASS_HID_38758] = 3264, + [BNXT_ULP_CLASS_HID_25c58] = 3265, + [BNXT_ULP_CLASS_HID_2c958] = 3266, + [BNXT_ULP_CLASS_HID_3170c] = 3267, + [BNXT_ULP_CLASS_HID_3800c] = 3268, + [BNXT_ULP_CLASS_HID_2123c] = 3269, + [BNXT_ULP_CLASS_HID_29f3c] = 3270, + [BNXT_ULP_CLASS_HID_3083c] = 3271, + [BNXT_ULP_CLASS_HID_3b53c] = 3272, + [BNXT_ULP_CLASS_HID_240a8] = 3273, + [BNXT_ULP_CLASS_HID_2cda8] = 3274, + [BNXT_ULP_CLASS_HID_31b5c] = 3275, + [BNXT_ULP_CLASS_HID_3845c] = 3276, + [BNXT_ULP_CLASS_HID_22ff8] = 3277, + [BNXT_ULP_CLASS_HID_2d8f8] = 3278, + [BNXT_ULP_CLASS_HID_345f8] = 3279, + [BNXT_ULP_CLASS_HID_393ac] = 3280, + [BNXT_ULP_CLASS_HID_228ac] = 3281, + [BNXT_ULP_CLASS_HID_2d5ac] = 3282, + [BNXT_ULP_CLASS_HID_35eac] = 3283, + [BNXT_ULP_CLASS_HID_3cbac] = 3284, + [BNXT_ULP_CLASS_HID_25d5c] = 3285, + [BNXT_ULP_CLASS_HID_2c65c] = 3286, + [BNXT_ULP_CLASS_HID_31410] = 3287, + [BNXT_ULP_CLASS_HID_38110] = 3288, + [BNXT_ULP_CLASS_HID_209f0] = 3289, + [BNXT_ULP_CLASS_HID_2b2f0] = 3290, + [BNXT_ULP_CLASS_HID_33ff0] = 3291, + [BNXT_ULP_CLASS_HID_3a8f0] = 3292, + [BNXT_ULP_CLASS_HID_214c0] = 3293, + [BNXT_ULP_CLASS_HID_281c0] = 3294, + [BNXT_ULP_CLASS_HID_30ac0] = 3295, + [BNXT_ULP_CLASS_HID_3b7c0] = 3296, + [BNXT_ULP_CLASS_HID_211f4] = 3297, + [BNXT_ULP_CLASS_HID_29af4] = 3298, + [BNXT_ULP_CLASS_HID_307f4] = 3299, + [BNXT_ULP_CLASS_HID_3b0f4] = 3300, + [BNXT_ULP_CLASS_HID_202a4] = 3301, + [BNXT_ULP_CLASS_HID_28fa4] = 3302, + [BNXT_ULP_CLASS_HID_338a4] = 3303, + [BNXT_ULP_CLASS_HID_3a5a4] = 3304, + [BNXT_ULP_CLASS_HID_22a04] = 3305, + [BNXT_ULP_CLASS_HID_2d704] = 3306, + [BNXT_ULP_CLASS_HID_34004] = 3307, + [BNXT_ULP_CLASS_HID_3cd04] = 3308, + [BNXT_ULP_CLASS_HID_23954] = 3309, + [BNXT_ULP_CLASS_HID_2a254] = 3310, + [BNXT_ULP_CLASS_HID_32f54] = 3311, + [BNXT_ULP_CLASS_HID_3d854] = 3312, + [BNXT_ULP_CLASS_HID_23208] = 3313, + [BNXT_ULP_CLASS_HID_2bf08] = 3314, + [BNXT_ULP_CLASS_HID_32808] = 3315, + [BNXT_ULP_CLASS_HID_3d508] = 3316, + [BNXT_ULP_CLASS_HID_22738] = 3317, + [BNXT_ULP_CLASS_HID_2d038] = 3318, + [BNXT_ULP_CLASS_HID_35d38] = 3319, + [BNXT_ULP_CLASS_HID_3c638] = 3320, + [BNXT_ULP_CLASS_HID_2134c] = 3321, + [BNXT_ULP_CLASS_HID_29c4c] = 3322, + [BNXT_ULP_CLASS_HID_3094c] = 3323, + [BNXT_ULP_CLASS_HID_3b24c] = 3324, + [BNXT_ULP_CLASS_HID_25de8] = 3325, + [BNXT_ULP_CLASS_HID_2c6e8] = 3326, + [BNXT_ULP_CLASS_HID_3149c] = 3327, + [BNXT_ULP_CLASS_HID_3819c] = 3328, + [BNXT_ULP_CLASS_HID_2569c] = 3329, + [BNXT_ULP_CLASS_HID_2c39c] = 3330, + [BNXT_ULP_CLASS_HID_31150] = 3331, + [BNXT_ULP_CLASS_HID_39a50] = 3332, + [BNXT_ULP_CLASS_HID_24b4c] = 3333, + [BNXT_ULP_CLASS_HID_29900] = 3334, + [BNXT_ULP_CLASS_HID_30200] = 3335, + [BNXT_ULP_CLASS_HID_38f00] = 3336, + [BNXT_ULP_CLASS_HID_22f74] = 3337, + [BNXT_ULP_CLASS_HID_2d874] = 3338, + [BNXT_ULP_CLASS_HID_34574] = 3339, + [BNXT_ULP_CLASS_HID_39328] = 3340, + [BNXT_ULP_CLASS_HID_23a44] = 3341, + [BNXT_ULP_CLASS_HID_2a744] = 3342, + [BNXT_ULP_CLASS_HID_35044] = 3343, + [BNXT_ULP_CLASS_HID_3dd44] = 3344, + [BNXT_ULP_CLASS_HID_23778] = 3345, + [BNXT_ULP_CLASS_HID_2a078] = 3346, + [BNXT_ULP_CLASS_HID_32d78] = 3347, + [BNXT_ULP_CLASS_HID_3d678] = 3348, + [BNXT_ULP_CLASS_HID_22828] = 3349, + [BNXT_ULP_CLASS_HID_2d528] = 3350, + [BNXT_ULP_CLASS_HID_35e28] = 3351, + [BNXT_ULP_CLASS_HID_3cb28] = 3352, + [BNXT_ULP_CLASS_HID_214bc] = 3353, + [BNXT_ULP_CLASS_HID_281bc] = 3354, + [BNXT_ULP_CLASS_HID_30abc] = 3355, + [BNXT_ULP_CLASS_HID_3b7bc] = 3356, + [BNXT_ULP_CLASS_HID_25ed8] = 3357, + [BNXT_ULP_CLASS_HID_2cbd8] = 3358, + [BNXT_ULP_CLASS_HID_3198c] = 3359, + [BNXT_ULP_CLASS_HID_3828c] = 3360, + [BNXT_ULP_CLASS_HID_25b8c] = 3361, + [BNXT_ULP_CLASS_HID_2c48c] = 3362, + [BNXT_ULP_CLASS_HID_31240] = 3363, + [BNXT_ULP_CLASS_HID_39f40] = 3364, + [BNXT_ULP_CLASS_HID_21170] = 3365, + [BNXT_ULP_CLASS_HID_29a70] = 3366, + [BNXT_ULP_CLASS_HID_30770] = 3367, + [BNXT_ULP_CLASS_HID_3b070] = 3368, + [BNXT_ULP_CLASS_HID_238d0] = 3369, + [BNXT_ULP_CLASS_HID_2a5d0] = 3370, + [BNXT_ULP_CLASS_HID_32ed0] = 3371, + [BNXT_ULP_CLASS_HID_3dbd0] = 3372, + [BNXT_ULP_CLASS_HID_20420] = 3373, + [BNXT_ULP_CLASS_HID_2b120] = 3374, + [BNXT_ULP_CLASS_HID_33a20] = 3375, + [BNXT_ULP_CLASS_HID_3a720] = 3376, + [BNXT_ULP_CLASS_HID_200d4] = 3377, + [BNXT_ULP_CLASS_HID_28dd4] = 3378, + [BNXT_ULP_CLASS_HID_336d4] = 3379, + [BNXT_ULP_CLASS_HID_3a3d4] = 3380, + [BNXT_ULP_CLASS_HID_23584] = 3381, + [BNXT_ULP_CLASS_HID_2be84] = 3382, + [BNXT_ULP_CLASS_HID_32b84] = 3383, + [BNXT_ULP_CLASS_HID_3d484] = 3384, + [BNXT_ULP_CLASS_HID_25d64] = 3385, + [BNXT_ULP_CLASS_HID_2c664] = 3386, + [BNXT_ULP_CLASS_HID_31418] = 3387, + [BNXT_ULP_CLASS_HID_38118] = 3388, + [BNXT_ULP_CLASS_HID_228b4] = 3389, + [BNXT_ULP_CLASS_HID_2d5b4] = 3390, + [BNXT_ULP_CLASS_HID_35eb4] = 3391, + [BNXT_ULP_CLASS_HID_3cbb4] = 3392, + [BNXT_ULP_CLASS_HID_22568] = 3393, + [BNXT_ULP_CLASS_HID_2ae68] = 3394, + [BNXT_ULP_CLASS_HID_35b68] = 3395, + [BNXT_ULP_CLASS_HID_3c468] = 3396, + [BNXT_ULP_CLASS_HID_25618] = 3397, + [BNXT_ULP_CLASS_HID_2c318] = 3398, + [BNXT_ULP_CLASS_HID_310cc] = 3399, + [BNXT_ULP_CLASS_HID_39dcc] = 3400, + [BNXT_ULP_CLASS_HID_229b8] = 3401, + [BNXT_ULP_CLASS_HID_2d2b8] = 3402, + [BNXT_ULP_CLASS_HID_35fb8] = 3403, + [BNXT_ULP_CLASS_HID_3c8b8] = 3404, + [BNXT_ULP_CLASS_HID_23488] = 3405, + [BNXT_ULP_CLASS_HID_2a188] = 3406, + [BNXT_ULP_CLASS_HID_32a88] = 3407, + [BNXT_ULP_CLASS_HID_3d788] = 3408, + [BNXT_ULP_CLASS_HID_231bc] = 3409, + [BNXT_ULP_CLASS_HID_2babc] = 3410, + [BNXT_ULP_CLASS_HID_327bc] = 3411, + [BNXT_ULP_CLASS_HID_3d0bc] = 3412, + [BNXT_ULP_CLASS_HID_2226c] = 3413, + [BNXT_ULP_CLASS_HID_2af6c] = 3414, + [BNXT_ULP_CLASS_HID_3586c] = 3415, + [BNXT_ULP_CLASS_HID_3c56c] = 3416, + [BNXT_ULP_CLASS_HID_24dcc] = 3417, + [BNXT_ULP_CLASS_HID_29b80] = 3418, + [BNXT_ULP_CLASS_HID_30480] = 3419, + [BNXT_ULP_CLASS_HID_3b180] = 3420, + [BNXT_ULP_CLASS_HID_2591c] = 3421, + [BNXT_ULP_CLASS_HID_2c21c] = 3422, + [BNXT_ULP_CLASS_HID_313d0] = 3423, + [BNXT_ULP_CLASS_HID_39cd0] = 3424, + [BNXT_ULP_CLASS_HID_255d0] = 3425, + [BNXT_ULP_CLASS_HID_2ded0] = 3426, + [BNXT_ULP_CLASS_HID_34bd0] = 3427, + [BNXT_ULP_CLASS_HID_39984] = 3428, + [BNXT_ULP_CLASS_HID_24680] = 3429, + [BNXT_ULP_CLASS_HID_294b4] = 3430, + [BNXT_ULP_CLASS_HID_301b4] = 3431, + [BNXT_ULP_CLASS_HID_38ab4] = 3432, + [BNXT_ULP_CLASS_HID_23314] = 3433, + [BNXT_ULP_CLASS_HID_2bc14] = 3434, + [BNXT_ULP_CLASS_HID_32914] = 3435, + [BNXT_ULP_CLASS_HID_3d214] = 3436, + [BNXT_ULP_CLASS_HID_21e64] = 3437, + [BNXT_ULP_CLASS_HID_28b64] = 3438, + [BNXT_ULP_CLASS_HID_33464] = 3439, + [BNXT_ULP_CLASS_HID_3a164] = 3440, + [BNXT_ULP_CLASS_HID_21b18] = 3441, + [BNXT_ULP_CLASS_HID_28418] = 3442, + [BNXT_ULP_CLASS_HID_33118] = 3443, + [BNXT_ULP_CLASS_HID_3ba18] = 3444, + [BNXT_ULP_CLASS_HID_20fc8] = 3445, + [BNXT_ULP_CLASS_HID_2b8c8] = 3446, + [BNXT_ULP_CLASS_HID_325c8] = 3447, + [BNXT_ULP_CLASS_HID_3aec8] = 3448, + [BNXT_ULP_CLASS_HID_257a8] = 3449, + [BNXT_ULP_CLASS_HID_2c0a8] = 3450, + [BNXT_ULP_CLASS_HID_34da8] = 3451, + [BNXT_ULP_CLASS_HID_39b5c] = 3452, + [BNXT_ULP_CLASS_HID_222f8] = 3453, + [BNXT_ULP_CLASS_HID_2aff8] = 3454, + [BNXT_ULP_CLASS_HID_358f8] = 3455, + [BNXT_ULP_CLASS_HID_3c5f8] = 3456, + [BNXT_ULP_CLASS_HID_23fac] = 3457, + [BNXT_ULP_CLASS_HID_2a8ac] = 3458, + [BNXT_ULP_CLASS_HID_355ac] = 3459, + [BNXT_ULP_CLASS_HID_3deac] = 3460, + [BNXT_ULP_CLASS_HID_2505c] = 3461, + [BNXT_ULP_CLASS_HID_2dd5c] = 3462, + [BNXT_ULP_CLASS_HID_3465c] = 3463, + [BNXT_ULP_CLASS_HID_39410] = 3464, + [BNXT_ULP_CLASS_HID_223fc] = 3465, + [BNXT_ULP_CLASS_HID_2acfc] = 3466, + [BNXT_ULP_CLASS_HID_359fc] = 3467, + [BNXT_ULP_CLASS_HID_3c2fc] = 3468, + [BNXT_ULP_CLASS_HID_20ecc] = 3469, + [BNXT_ULP_CLASS_HID_2bbcc] = 3470, + [BNXT_ULP_CLASS_HID_324cc] = 3471, + [BNXT_ULP_CLASS_HID_3d1cc] = 3472, + [BNXT_ULP_CLASS_HID_20b80] = 3473, + [BNXT_ULP_CLASS_HID_2b480] = 3474, + [BNXT_ULP_CLASS_HID_32180] = 3475, + [BNXT_ULP_CLASS_HID_3aa80] = 3476, + [BNXT_ULP_CLASS_HID_23cb0] = 3477, + [BNXT_ULP_CLASS_HID_2a9b0] = 3478, + [BNXT_ULP_CLASS_HID_352b0] = 3479, + [BNXT_ULP_CLASS_HID_3dfb0] = 3480, + [BNXT_ULP_CLASS_HID_24410] = 3481, + [BNXT_ULP_CLASS_HID_295c4] = 3482, + [BNXT_ULP_CLASS_HID_31ec4] = 3483, + [BNXT_ULP_CLASS_HID_38bc4] = 3484, + [BNXT_ULP_CLASS_HID_25360] = 3485, + [BNXT_ULP_CLASS_HID_2dc60] = 3486, + [BNXT_ULP_CLASS_HID_34960] = 3487, + [BNXT_ULP_CLASS_HID_39714] = 3488, + [BNXT_ULP_CLASS_HID_22c14] = 3489, + [BNXT_ULP_CLASS_HID_2d914] = 3490, + [BNXT_ULP_CLASS_HID_34214] = 3491, + [BNXT_ULP_CLASS_HID_393c8] = 3492, + [BNXT_ULP_CLASS_HID_240c4] = 3493, + [BNXT_ULP_CLASS_HID_2cdc4] = 3494, + [BNXT_ULP_CLASS_HID_31bf8] = 3495, + [BNXT_ULP_CLASS_HID_384f8] = 3496, + [BNXT_ULP_CLASS_HID_23dc0] = 3497, + [BNXT_ULP_CLASS_HID_2a6c0] = 3498, + [BNXT_ULP_CLASS_HID_353c0] = 3499, + [BNXT_ULP_CLASS_HID_3dcc0] = 3500, + [BNXT_ULP_CLASS_HID_20910] = 3501, + [BNXT_ULP_CLASS_HID_2b210] = 3502, + [BNXT_ULP_CLASS_HID_33f10] = 3503, + [BNXT_ULP_CLASS_HID_3a810] = 3504, + [BNXT_ULP_CLASS_HID_205c4] = 3505, + [BNXT_ULP_CLASS_HID_28ec4] = 3506, + [BNXT_ULP_CLASS_HID_33bc4] = 3507, + [BNXT_ULP_CLASS_HID_3a4c4] = 3508, + [BNXT_ULP_CLASS_HID_236f4] = 3509, + [BNXT_ULP_CLASS_HID_2a3f4] = 3510, + [BNXT_ULP_CLASS_HID_32cf4] = 3511, + [BNXT_ULP_CLASS_HID_3d9f4] = 3512, + [BNXT_ULP_CLASS_HID_25e54] = 3513, + [BNXT_ULP_CLASS_HID_2cb54] = 3514, + [BNXT_ULP_CLASS_HID_31908] = 3515, + [BNXT_ULP_CLASS_HID_38208] = 3516, + [BNXT_ULP_CLASS_HID_22da4] = 3517, + [BNXT_ULP_CLASS_HID_2d6a4] = 3518, + [BNXT_ULP_CLASS_HID_343a4] = 3519, + [BNXT_ULP_CLASS_HID_39158] = 3520, + [BNXT_ULP_CLASS_HID_22658] = 3521, + [BNXT_ULP_CLASS_HID_2d358] = 3522, + [BNXT_ULP_CLASS_HID_35c58] = 3523, + [BNXT_ULP_CLASS_HID_3c958] = 3524, + [BNXT_ULP_CLASS_HID_25b08] = 3525, + [BNXT_ULP_CLASS_HID_2c408] = 3526, + [BNXT_ULP_CLASS_HID_3123c] = 3527, + [BNXT_ULP_CLASS_HID_39f3c] = 3528, + [BNXT_ULP_CLASS_HID_34a8] = 3529, + [BNXT_ULP_CLASS_HID_3a64] = 3530, + [BNXT_ULP_CLASS_HID_5ef8] = 3531, + [BNXT_ULP_CLASS_HID_07c0] = 3532, + [BNXT_ULP_CLASS_HID_2854] = 3533, + [BNXT_ULP_CLASS_HID_593c] = 3534, + [BNXT_ULP_CLASS_HID_1e04] = 3535, + [BNXT_ULP_CLASS_HID_2298] = 3536, + [BNXT_ULP_CLASS_HID_24644] = 3537, + [BNXT_ULP_CLASS_HID_29438] = 3538, + [BNXT_ULP_CLASS_HID_30138] = 3539, + [BNXT_ULP_CLASS_HID_38a38] = 3540, + [BNXT_ULP_CLASS_HID_25594] = 3541, + [BNXT_ULP_CLASS_HID_2de94] = 3542, + [BNXT_ULP_CLASS_HID_34b94] = 3543, + [BNXT_ULP_CLASS_HID_39948] = 3544, + [BNXT_ULP_CLASS_HID_22e48] = 3545, + [BNXT_ULP_CLASS_HID_2db48] = 3546, + [BNXT_ULP_CLASS_HID_34448] = 3547, + [BNXT_ULP_CLASS_HID_3923c] = 3548, + [BNXT_ULP_CLASS_HID_24338] = 3549, + [BNXT_ULP_CLASS_HID_290ec] = 3550, + [BNXT_ULP_CLASS_HID_31dec] = 3551, + [BNXT_ULP_CLASS_HID_386ec] = 3552, + [BNXT_ULP_CLASS_HID_20f8c] = 3553, + [BNXT_ULP_CLASS_HID_2b88c] = 3554, + [BNXT_ULP_CLASS_HID_3258c] = 3555, + [BNXT_ULP_CLASS_HID_3ae8c] = 3556, + [BNXT_ULP_CLASS_HID_21adc] = 3557, + [BNXT_ULP_CLASS_HID_287dc] = 3558, + [BNXT_ULP_CLASS_HID_330dc] = 3559, + [BNXT_ULP_CLASS_HID_3bddc] = 3560, + [BNXT_ULP_CLASS_HID_21790] = 3561, + [BNXT_ULP_CLASS_HID_28090] = 3562, + [BNXT_ULP_CLASS_HID_30d90] = 3563, + [BNXT_ULP_CLASS_HID_3b690] = 3564, + [BNXT_ULP_CLASS_HID_20840] = 3565, + [BNXT_ULP_CLASS_HID_2b540] = 3566, + [BNXT_ULP_CLASS_HID_33e40] = 3567, + [BNXT_ULP_CLASS_HID_3ab40] = 3568, + [BNXT_ULP_CLASS_HID_253e0] = 3569, + [BNXT_ULP_CLASS_HID_2dce0] = 3570, + [BNXT_ULP_CLASS_HID_349e0] = 3571, + [BNXT_ULP_CLASS_HID_397d4] = 3572, + [BNXT_ULP_CLASS_HID_23f30] = 3573, + [BNXT_ULP_CLASS_HID_2a830] = 3574, + [BNXT_ULP_CLASS_HID_35530] = 3575, + [BNXT_ULP_CLASS_HID_3de30] = 3576, + [BNXT_ULP_CLASS_HID_23be4] = 3577, + [BNXT_ULP_CLASS_HID_2a4e4] = 3578, + [BNXT_ULP_CLASS_HID_351e4] = 3579, + [BNXT_ULP_CLASS_HID_3dae4] = 3580, + [BNXT_ULP_CLASS_HID_22cd4] = 3581, + [BNXT_ULP_CLASS_HID_2d9d4] = 3582, + [BNXT_ULP_CLASS_HID_342d4] = 3583, + [BNXT_ULP_CLASS_HID_39088] = 3584, + [BNXT_ULP_CLASS_HID_21928] = 3585, + [BNXT_ULP_CLASS_HID_28228] = 3586, + [BNXT_ULP_CLASS_HID_30f28] = 3587, + [BNXT_ULP_CLASS_HID_3b828] = 3588, + [BNXT_ULP_CLASS_HID_24384] = 3589, + [BNXT_ULP_CLASS_HID_29178] = 3590, + [BNXT_ULP_CLASS_HID_31a78] = 3591, + [BNXT_ULP_CLASS_HID_38778] = 3592, + [BNXT_ULP_CLASS_HID_25c78] = 3593, + [BNXT_ULP_CLASS_HID_2c978] = 3594, + [BNXT_ULP_CLASS_HID_3172c] = 3595, + [BNXT_ULP_CLASS_HID_3802c] = 3596, + [BNXT_ULP_CLASS_HID_2121c] = 3597, + [BNXT_ULP_CLASS_HID_29f1c] = 3598, + [BNXT_ULP_CLASS_HID_3081c] = 3599, + [BNXT_ULP_CLASS_HID_3b51c] = 3600, + [BNXT_ULP_CLASS_HID_24088] = 3601, + [BNXT_ULP_CLASS_HID_2cd88] = 3602, + [BNXT_ULP_CLASS_HID_31b7c] = 3603, + [BNXT_ULP_CLASS_HID_3847c] = 3604, + [BNXT_ULP_CLASS_HID_22fd8] = 3605, + [BNXT_ULP_CLASS_HID_2d8d8] = 3606, + [BNXT_ULP_CLASS_HID_345d8] = 3607, + [BNXT_ULP_CLASS_HID_3938c] = 3608, + [BNXT_ULP_CLASS_HID_2288c] = 3609, + [BNXT_ULP_CLASS_HID_2d58c] = 3610, + [BNXT_ULP_CLASS_HID_35e8c] = 3611, + [BNXT_ULP_CLASS_HID_3cb8c] = 3612, + [BNXT_ULP_CLASS_HID_25d7c] = 3613, + [BNXT_ULP_CLASS_HID_2c67c] = 3614, + [BNXT_ULP_CLASS_HID_31430] = 3615, + [BNXT_ULP_CLASS_HID_38130] = 3616, + [BNXT_ULP_CLASS_HID_209d0] = 3617, + [BNXT_ULP_CLASS_HID_2b2d0] = 3618, + [BNXT_ULP_CLASS_HID_33fd0] = 3619, + [BNXT_ULP_CLASS_HID_3a8d0] = 3620, + [BNXT_ULP_CLASS_HID_214e0] = 3621, + [BNXT_ULP_CLASS_HID_281e0] = 3622, + [BNXT_ULP_CLASS_HID_30ae0] = 3623, + [BNXT_ULP_CLASS_HID_3b7e0] = 3624, + [BNXT_ULP_CLASS_HID_211d4] = 3625, + [BNXT_ULP_CLASS_HID_29ad4] = 3626, + [BNXT_ULP_CLASS_HID_307d4] = 3627, + [BNXT_ULP_CLASS_HID_3b0d4] = 3628, + [BNXT_ULP_CLASS_HID_20284] = 3629, + [BNXT_ULP_CLASS_HID_28f84] = 3630, + [BNXT_ULP_CLASS_HID_33884] = 3631, + [BNXT_ULP_CLASS_HID_3a584] = 3632, + [BNXT_ULP_CLASS_HID_22a24] = 3633, + [BNXT_ULP_CLASS_HID_2d724] = 3634, + [BNXT_ULP_CLASS_HID_34024] = 3635, + [BNXT_ULP_CLASS_HID_3cd24] = 3636, + [BNXT_ULP_CLASS_HID_23974] = 3637, + [BNXT_ULP_CLASS_HID_2a274] = 3638, + [BNXT_ULP_CLASS_HID_32f74] = 3639, + [BNXT_ULP_CLASS_HID_3d874] = 3640, + [BNXT_ULP_CLASS_HID_23228] = 3641, + [BNXT_ULP_CLASS_HID_2bf28] = 3642, + [BNXT_ULP_CLASS_HID_32828] = 3643, + [BNXT_ULP_CLASS_HID_3d528] = 3644, + [BNXT_ULP_CLASS_HID_22718] = 3645, + [BNXT_ULP_CLASS_HID_2d018] = 3646, + [BNXT_ULP_CLASS_HID_35d18] = 3647, + [BNXT_ULP_CLASS_HID_3c618] = 3648, + [BNXT_ULP_CLASS_HID_2136c] = 3649, + [BNXT_ULP_CLASS_HID_29c6c] = 3650, + [BNXT_ULP_CLASS_HID_3096c] = 3651, + [BNXT_ULP_CLASS_HID_3b26c] = 3652, + [BNXT_ULP_CLASS_HID_25dc8] = 3653, + [BNXT_ULP_CLASS_HID_2c6c8] = 3654, + [BNXT_ULP_CLASS_HID_314bc] = 3655, + [BNXT_ULP_CLASS_HID_381bc] = 3656, + [BNXT_ULP_CLASS_HID_256bc] = 3657, + [BNXT_ULP_CLASS_HID_2c3bc] = 3658, + [BNXT_ULP_CLASS_HID_31170] = 3659, + [BNXT_ULP_CLASS_HID_39a70] = 3660, + [BNXT_ULP_CLASS_HID_24b6c] = 3661, + [BNXT_ULP_CLASS_HID_29920] = 3662, + [BNXT_ULP_CLASS_HID_30220] = 3663, + [BNXT_ULP_CLASS_HID_38f20] = 3664, + [BNXT_ULP_CLASS_HID_22f54] = 3665, + [BNXT_ULP_CLASS_HID_2d854] = 3666, + [BNXT_ULP_CLASS_HID_34554] = 3667, + [BNXT_ULP_CLASS_HID_39308] = 3668, + [BNXT_ULP_CLASS_HID_23a64] = 3669, + [BNXT_ULP_CLASS_HID_2a764] = 3670, + [BNXT_ULP_CLASS_HID_35064] = 3671, + [BNXT_ULP_CLASS_HID_3dd64] = 3672, + [BNXT_ULP_CLASS_HID_23758] = 3673, + [BNXT_ULP_CLASS_HID_2a058] = 3674, + [BNXT_ULP_CLASS_HID_32d58] = 3675, + [BNXT_ULP_CLASS_HID_3d658] = 3676, + [BNXT_ULP_CLASS_HID_22808] = 3677, + [BNXT_ULP_CLASS_HID_2d508] = 3678, + [BNXT_ULP_CLASS_HID_35e08] = 3679, + [BNXT_ULP_CLASS_HID_3cb08] = 3680, + [BNXT_ULP_CLASS_HID_2149c] = 3681, + [BNXT_ULP_CLASS_HID_2819c] = 3682, + [BNXT_ULP_CLASS_HID_30a9c] = 3683, + [BNXT_ULP_CLASS_HID_3b79c] = 3684, + [BNXT_ULP_CLASS_HID_25ef8] = 3685, + [BNXT_ULP_CLASS_HID_2cbf8] = 3686, + [BNXT_ULP_CLASS_HID_319ac] = 3687, + [BNXT_ULP_CLASS_HID_382ac] = 3688, + [BNXT_ULP_CLASS_HID_25bac] = 3689, + [BNXT_ULP_CLASS_HID_2c4ac] = 3690, + [BNXT_ULP_CLASS_HID_31260] = 3691, + [BNXT_ULP_CLASS_HID_39f60] = 3692, + [BNXT_ULP_CLASS_HID_21150] = 3693, + [BNXT_ULP_CLASS_HID_29a50] = 3694, + [BNXT_ULP_CLASS_HID_30750] = 3695, + [BNXT_ULP_CLASS_HID_3b050] = 3696, + [BNXT_ULP_CLASS_HID_238f0] = 3697, + [BNXT_ULP_CLASS_HID_2a5f0] = 3698, + [BNXT_ULP_CLASS_HID_32ef0] = 3699, + [BNXT_ULP_CLASS_HID_3dbf0] = 3700, + [BNXT_ULP_CLASS_HID_20400] = 3701, + [BNXT_ULP_CLASS_HID_2b100] = 3702, + [BNXT_ULP_CLASS_HID_33a00] = 3703, + [BNXT_ULP_CLASS_HID_3a700] = 3704, + [BNXT_ULP_CLASS_HID_200f4] = 3705, + [BNXT_ULP_CLASS_HID_28df4] = 3706, + [BNXT_ULP_CLASS_HID_336f4] = 3707, + [BNXT_ULP_CLASS_HID_3a3f4] = 3708, + [BNXT_ULP_CLASS_HID_235a4] = 3709, + [BNXT_ULP_CLASS_HID_2bea4] = 3710, + [BNXT_ULP_CLASS_HID_32ba4] = 3711, + [BNXT_ULP_CLASS_HID_3d4a4] = 3712, + [BNXT_ULP_CLASS_HID_25d44] = 3713, + [BNXT_ULP_CLASS_HID_2c644] = 3714, + [BNXT_ULP_CLASS_HID_31438] = 3715, + [BNXT_ULP_CLASS_HID_38138] = 3716, + [BNXT_ULP_CLASS_HID_22894] = 3717, + [BNXT_ULP_CLASS_HID_2d594] = 3718, + [BNXT_ULP_CLASS_HID_35e94] = 3719, + [BNXT_ULP_CLASS_HID_3cb94] = 3720, + [BNXT_ULP_CLASS_HID_22548] = 3721, + [BNXT_ULP_CLASS_HID_2ae48] = 3722, + [BNXT_ULP_CLASS_HID_35b48] = 3723, + [BNXT_ULP_CLASS_HID_3c448] = 3724, + [BNXT_ULP_CLASS_HID_25638] = 3725, + [BNXT_ULP_CLASS_HID_2c338] = 3726, + [BNXT_ULP_CLASS_HID_310ec] = 3727, + [BNXT_ULP_CLASS_HID_39dec] = 3728, + [BNXT_ULP_CLASS_HID_22998] = 3729, + [BNXT_ULP_CLASS_HID_2d298] = 3730, + [BNXT_ULP_CLASS_HID_35f98] = 3731, + [BNXT_ULP_CLASS_HID_3c898] = 3732, + [BNXT_ULP_CLASS_HID_234a8] = 3733, + [BNXT_ULP_CLASS_HID_2a1a8] = 3734, + [BNXT_ULP_CLASS_HID_32aa8] = 3735, + [BNXT_ULP_CLASS_HID_3d7a8] = 3736, + [BNXT_ULP_CLASS_HID_2319c] = 3737, + [BNXT_ULP_CLASS_HID_2ba9c] = 3738, + [BNXT_ULP_CLASS_HID_3279c] = 3739, + [BNXT_ULP_CLASS_HID_3d09c] = 3740, + [BNXT_ULP_CLASS_HID_2224c] = 3741, + [BNXT_ULP_CLASS_HID_2af4c] = 3742, + [BNXT_ULP_CLASS_HID_3584c] = 3743, + [BNXT_ULP_CLASS_HID_3c54c] = 3744, + [BNXT_ULP_CLASS_HID_24dec] = 3745, + [BNXT_ULP_CLASS_HID_29ba0] = 3746, + [BNXT_ULP_CLASS_HID_304a0] = 3747, + [BNXT_ULP_CLASS_HID_3b1a0] = 3748, + [BNXT_ULP_CLASS_HID_2593c] = 3749, + [BNXT_ULP_CLASS_HID_2c23c] = 3750, + [BNXT_ULP_CLASS_HID_313f0] = 3751, + [BNXT_ULP_CLASS_HID_39cf0] = 3752, + [BNXT_ULP_CLASS_HID_255f0] = 3753, + [BNXT_ULP_CLASS_HID_2def0] = 3754, + [BNXT_ULP_CLASS_HID_34bf0] = 3755, + [BNXT_ULP_CLASS_HID_399a4] = 3756, + [BNXT_ULP_CLASS_HID_246a0] = 3757, + [BNXT_ULP_CLASS_HID_29494] = 3758, + [BNXT_ULP_CLASS_HID_30194] = 3759, + [BNXT_ULP_CLASS_HID_38a94] = 3760, + [BNXT_ULP_CLASS_HID_23334] = 3761, + [BNXT_ULP_CLASS_HID_2bc34] = 3762, + [BNXT_ULP_CLASS_HID_32934] = 3763, + [BNXT_ULP_CLASS_HID_3d234] = 3764, + [BNXT_ULP_CLASS_HID_21e44] = 3765, + [BNXT_ULP_CLASS_HID_28b44] = 3766, + [BNXT_ULP_CLASS_HID_33444] = 3767, + [BNXT_ULP_CLASS_HID_3a144] = 3768, + [BNXT_ULP_CLASS_HID_21b38] = 3769, + [BNXT_ULP_CLASS_HID_28438] = 3770, + [BNXT_ULP_CLASS_HID_33138] = 3771, + [BNXT_ULP_CLASS_HID_3ba38] = 3772, + [BNXT_ULP_CLASS_HID_20fe8] = 3773, + [BNXT_ULP_CLASS_HID_2b8e8] = 3774, + [BNXT_ULP_CLASS_HID_325e8] = 3775, + [BNXT_ULP_CLASS_HID_3aee8] = 3776, + [BNXT_ULP_CLASS_HID_25788] = 3777, + [BNXT_ULP_CLASS_HID_2c088] = 3778, + [BNXT_ULP_CLASS_HID_34d88] = 3779, + [BNXT_ULP_CLASS_HID_39b7c] = 3780, + [BNXT_ULP_CLASS_HID_222d8] = 3781, + [BNXT_ULP_CLASS_HID_2afd8] = 3782, + [BNXT_ULP_CLASS_HID_358d8] = 3783, + [BNXT_ULP_CLASS_HID_3c5d8] = 3784, + [BNXT_ULP_CLASS_HID_23f8c] = 3785, + [BNXT_ULP_CLASS_HID_2a88c] = 3786, + [BNXT_ULP_CLASS_HID_3558c] = 3787, + [BNXT_ULP_CLASS_HID_3de8c] = 3788, + [BNXT_ULP_CLASS_HID_2507c] = 3789, + [BNXT_ULP_CLASS_HID_2dd7c] = 3790, + [BNXT_ULP_CLASS_HID_3467c] = 3791, + [BNXT_ULP_CLASS_HID_39430] = 3792, + [BNXT_ULP_CLASS_HID_223dc] = 3793, + [BNXT_ULP_CLASS_HID_2acdc] = 3794, + [BNXT_ULP_CLASS_HID_359dc] = 3795, + [BNXT_ULP_CLASS_HID_3c2dc] = 3796, + [BNXT_ULP_CLASS_HID_20eec] = 3797, + [BNXT_ULP_CLASS_HID_2bbec] = 3798, + [BNXT_ULP_CLASS_HID_324ec] = 3799, + [BNXT_ULP_CLASS_HID_3d1ec] = 3800, + [BNXT_ULP_CLASS_HID_20ba0] = 3801, + [BNXT_ULP_CLASS_HID_2b4a0] = 3802, + [BNXT_ULP_CLASS_HID_321a0] = 3803, + [BNXT_ULP_CLASS_HID_3aaa0] = 3804, + [BNXT_ULP_CLASS_HID_23c90] = 3805, + [BNXT_ULP_CLASS_HID_2a990] = 3806, + [BNXT_ULP_CLASS_HID_35290] = 3807, + [BNXT_ULP_CLASS_HID_3df90] = 3808, + [BNXT_ULP_CLASS_HID_24430] = 3809, + [BNXT_ULP_CLASS_HID_295e4] = 3810, + [BNXT_ULP_CLASS_HID_31ee4] = 3811, + [BNXT_ULP_CLASS_HID_38be4] = 3812, + [BNXT_ULP_CLASS_HID_25340] = 3813, + [BNXT_ULP_CLASS_HID_2dc40] = 3814, + [BNXT_ULP_CLASS_HID_34940] = 3815, + [BNXT_ULP_CLASS_HID_39734] = 3816, + [BNXT_ULP_CLASS_HID_22c34] = 3817, + [BNXT_ULP_CLASS_HID_2d934] = 3818, + [BNXT_ULP_CLASS_HID_34234] = 3819, + [BNXT_ULP_CLASS_HID_393e8] = 3820, + [BNXT_ULP_CLASS_HID_240e4] = 3821, + [BNXT_ULP_CLASS_HID_2cde4] = 3822, + [BNXT_ULP_CLASS_HID_31bd8] = 3823, + [BNXT_ULP_CLASS_HID_384d8] = 3824, + [BNXT_ULP_CLASS_HID_23de0] = 3825, + [BNXT_ULP_CLASS_HID_2a6e0] = 3826, + [BNXT_ULP_CLASS_HID_353e0] = 3827, + [BNXT_ULP_CLASS_HID_3dce0] = 3828, + [BNXT_ULP_CLASS_HID_20930] = 3829, + [BNXT_ULP_CLASS_HID_2b230] = 3830, + [BNXT_ULP_CLASS_HID_33f30] = 3831, + [BNXT_ULP_CLASS_HID_3a830] = 3832, + [BNXT_ULP_CLASS_HID_205e4] = 3833, + [BNXT_ULP_CLASS_HID_28ee4] = 3834, + [BNXT_ULP_CLASS_HID_33be4] = 3835, + [BNXT_ULP_CLASS_HID_3a4e4] = 3836, + [BNXT_ULP_CLASS_HID_236d4] = 3837, + [BNXT_ULP_CLASS_HID_2a3d4] = 3838, + [BNXT_ULP_CLASS_HID_32cd4] = 3839, + [BNXT_ULP_CLASS_HID_3d9d4] = 3840, + [BNXT_ULP_CLASS_HID_25e74] = 3841, + [BNXT_ULP_CLASS_HID_2cb74] = 3842, + [BNXT_ULP_CLASS_HID_31928] = 3843, + [BNXT_ULP_CLASS_HID_38228] = 3844, + [BNXT_ULP_CLASS_HID_22d84] = 3845, + [BNXT_ULP_CLASS_HID_2d684] = 3846, + [BNXT_ULP_CLASS_HID_34384] = 3847, + [BNXT_ULP_CLASS_HID_39178] = 3848, + [BNXT_ULP_CLASS_HID_22678] = 3849, + [BNXT_ULP_CLASS_HID_2d378] = 3850, + [BNXT_ULP_CLASS_HID_35c78] = 3851, + [BNXT_ULP_CLASS_HID_3c978] = 3852, + [BNXT_ULP_CLASS_HID_25b28] = 3853, + [BNXT_ULP_CLASS_HID_2c428] = 3854, + [BNXT_ULP_CLASS_HID_3121c] = 3855, + [BNXT_ULP_CLASS_HID_39f1c] = 3856, + [BNXT_ULP_CLASS_HID_3488] = 3857, + [BNXT_ULP_CLASS_HID_3a44] = 3858, + [BNXT_ULP_CLASS_HID_5ed8] = 3859, + [BNXT_ULP_CLASS_HID_07e0] = 3860, + [BNXT_ULP_CLASS_HID_2874] = 3861, + [BNXT_ULP_CLASS_HID_591c] = 3862, + [BNXT_ULP_CLASS_HID_1e24] = 3863, + [BNXT_ULP_CLASS_HID_22b8] = 3864 }; /* Array for the proto matcher list */ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { [1] = { - .class_hid = BNXT_ULP_CLASS_HID_005c, + .class_hid = BNXT_ULP_CLASS_HID_26d1, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 0, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2] = { - .class_hid = BNXT_ULP_CLASS_HID_0003, + .class_hid = BNXT_ULP_CLASS_HID_0071, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 1, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [3] = { - .class_hid = BNXT_ULP_CLASS_HID_0132, + .class_hid = BNXT_ULP_CLASS_HID_53a5, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 1, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [4] = { - .class_hid = BNXT_ULP_CLASS_HID_00e1, + .class_hid = BNXT_ULP_CLASS_HID_1d49, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 1, + .flow_sig_id = 2, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [5] = { - .class_hid = BNXT_ULP_CLASS_HID_0044, + .class_hid = BNXT_ULP_CLASS_HID_2095, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 1, + .hdr_sig_id = 0, + .flow_sig_id = 2, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [6] = { - .class_hid = BNXT_ULP_CLASS_HID_001b, + .class_hid = BNXT_ULP_CLASS_HID_5701, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 0, .flow_sig_id = 2, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [7] = { - .class_hid = BNXT_ULP_CLASS_HID_012a, + .class_hid = BNXT_ULP_CLASS_HID_4d79, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 0, .flow_sig_id = 2, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [8] = { - .class_hid = BNXT_ULP_CLASS_HID_00f9, + .class_hid = BNXT_ULP_CLASS_HID_170d, .class_tid = 1, - .hdr_sig_id = 1, + .hdr_sig_id = 0, .flow_sig_id = 2, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [9] = { - .class_hid = BNXT_ULP_CLASS_HID_018d, + .class_hid = BNXT_ULP_CLASS_HID_1a69, .class_tid = 1, - .hdr_sig_id = 2, + .hdr_sig_id = 0, .flow_sig_id = 2, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [10] = { - .class_hid = BNXT_ULP_CLASS_HID_00a7, + .class_hid = BNXT_ULP_CLASS_HID_50c5, .class_tid = 1, - .hdr_sig_id = 2, + .hdr_sig_id = 0, .flow_sig_id = 3, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [11] = { - .class_hid = BNXT_ULP_CLASS_HID_006f, + .class_hid = BNXT_ULP_CLASS_HID_473d, .class_tid = 1, - .hdr_sig_id = 2, + .hdr_sig_id = 0, .flow_sig_id = 3, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [12] = { - .class_hid = BNXT_ULP_CLASS_HID_0181, + .class_hid = BNXT_ULP_CLASS_HID_10c1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 3, + .hdr_sig_id = 0, + .flow_sig_id = 4, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [13] = { - .class_hid = BNXT_ULP_CLASS_HID_0195, + .class_hid = BNXT_ULP_CLASS_HID_142d, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 3, + .hdr_sig_id = 0, + .flow_sig_id = 4, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [14] = { - .class_hid = BNXT_ULP_CLASS_HID_00bf, + .class_hid = BNXT_ULP_CLASS_HID_4a99, .class_tid = 1, - .hdr_sig_id = 3, + .hdr_sig_id = 0, .flow_sig_id = 4, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [15] = { - .class_hid = BNXT_ULP_CLASS_HID_0077, + .class_hid = BNXT_ULP_CLASS_HID_40f1, .class_tid = 1, - .hdr_sig_id = 3, + .hdr_sig_id = 0, .flow_sig_id = 4, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [16] = { - .class_hid = BNXT_ULP_CLASS_HID_0199, + .class_hid = BNXT_ULP_CLASS_HID_0a85, .class_tid = 1, - .hdr_sig_id = 3, + .hdr_sig_id = 0, .flow_sig_id = 4, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [17] = { - .class_hid = BNXT_ULP_CLASS_HID_009a, + .class_hid = BNXT_ULP_CLASS_HID_0179, .class_tid = 1, - .hdr_sig_id = 4, + .hdr_sig_id = 0, .flow_sig_id = 4, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [18] = { - .class_hid = BNXT_ULP_CLASS_HID_0192, + .class_hid = BNXT_ULP_CLASS_HID_37d5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4, + .hdr_sig_id = 0, + .flow_sig_id = 5, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [19] = { - .class_hid = BNXT_ULP_CLASS_HID_01e2, + .class_hid = BNXT_ULP_CLASS_HID_2e4d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4, + .hdr_sig_id = 0, + .flow_sig_id = 5, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [20] = { - .class_hid = BNXT_ULP_CLASS_HID_00fa, + .class_hid = BNXT_ULP_CLASS_HID_54ad, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4, + .hdr_sig_id = 0, + .flow_sig_id = 6, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [21] = { - .class_hid = BNXT_ULP_CLASS_HID_0165, + .class_hid = BNXT_ULP_CLASS_HID_5809, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4, + .hdr_sig_id = 0, + .flow_sig_id = 6, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [22] = { - .class_hid = BNXT_ULP_CLASS_HID_0042, + .class_hid = BNXT_ULP_CLASS_HID_31a9, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 0, + .flow_sig_id = 6, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [23] = { - .class_hid = BNXT_ULP_CLASS_HID_00cd, + .class_hid = BNXT_ULP_CLASS_HID_2801, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 0, + .flow_sig_id = 6, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [24] = { - .class_hid = BNXT_ULP_CLASS_HID_01aa, + .class_hid = BNXT_ULP_CLASS_HID_4e61, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 0, + .flow_sig_id = 6, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [25] = { - .class_hid = BNXT_ULP_CLASS_HID_0178, + .class_hid = BNXT_ULP_CLASS_HID_2561, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 0, + .flow_sig_id = 6, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [26] = { - .class_hid = BNXT_ULP_CLASS_HID_0070, + .class_hid = BNXT_ULP_CLASS_HID_2bad, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 0, + .flow_sig_id = 7, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [27] = { - .class_hid = BNXT_ULP_CLASS_HID_00f3, + .class_hid = BNXT_ULP_CLASS_HID_26f1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 7, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [28] = { - .class_hid = BNXT_ULP_CLASS_HID_01d8, + .class_hid = BNXT_ULP_CLASS_HID_13cf1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 7, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [29] = { - .class_hid = BNXT_ULP_CLASS_HID_005b, + .class_hid = BNXT_ULP_CLASS_HID_252f1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 8, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [30] = { - .class_hid = BNXT_ULP_CLASS_HID_0153, + .class_hid = BNXT_ULP_CLASS_HID_30c25, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 9, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [31] = { - .class_hid = BNXT_ULP_CLASS_HID_01a3, + .class_hid = BNXT_ULP_CLASS_HID_0051, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 10, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [32] = { - .class_hid = BNXT_ULP_CLASS_HID_00bb, + .class_hid = BNXT_ULP_CLASS_HID_11651, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 10, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [33] = { - .class_hid = BNXT_ULP_CLASS_HID_0082, + .class_hid = BNXT_ULP_CLASS_HID_22c51, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 10, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [34] = { - .class_hid = BNXT_ULP_CLASS_HID_018a, + .class_hid = BNXT_ULP_CLASS_HID_34251, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 10, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [35] = { - .class_hid = BNXT_ULP_CLASS_HID_01fa, + .class_hid = BNXT_ULP_CLASS_HID_5385, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 10, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [36] = { - .class_hid = BNXT_ULP_CLASS_HID_00e2, + .class_hid = BNXT_ULP_CLASS_HID_10cc9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 10, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [37] = { - .class_hid = BNXT_ULP_CLASS_HID_017d, + .class_hid = BNXT_ULP_CLASS_HID_222c9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 5, + .hdr_sig_id = 1, + .flow_sig_id = 11, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [38] = { - .class_hid = BNXT_ULP_CLASS_HID_005a, + .class_hid = BNXT_ULP_CLASS_HID_338c9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 12, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [39] = { - .class_hid = BNXT_ULP_CLASS_HID_00d5, + .class_hid = BNXT_ULP_CLASS_HID_1d69, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [40] = { - .class_hid = BNXT_ULP_CLASS_HID_01b2, + .class_hid = BNXT_ULP_CLASS_HID_13369, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [41] = { - .class_hid = BNXT_ULP_CLASS_HID_0160, + .class_hid = BNXT_ULP_CLASS_HID_24969, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [42] = { - .class_hid = BNXT_ULP_CLASS_HID_0068, + .class_hid = BNXT_ULP_CLASS_HID_3025d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [43] = { - .class_hid = BNXT_ULP_CLASS_HID_00eb, + .class_hid = BNXT_ULP_CLASS_HID_20b5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [44] = { - .class_hid = BNXT_ULP_CLASS_HID_01c0, + .class_hid = BNXT_ULP_CLASS_HID_136b5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [45] = { - .class_hid = BNXT_ULP_CLASS_HID_0043, + .class_hid = BNXT_ULP_CLASS_HID_24cb5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [46] = { - .class_hid = BNXT_ULP_CLASS_HID_014b, + .class_hid = BNXT_ULP_CLASS_HID_305f9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [47] = { - .class_hid = BNXT_ULP_CLASS_HID_01bb, + .class_hid = BNXT_ULP_CLASS_HID_5721, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [48] = { - .class_hid = BNXT_ULP_CLASS_HID_00a3, + .class_hid = BNXT_ULP_CLASS_HID_11015, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [49] = { - .class_hid = BNXT_ULP_CLASS_HID_00cb, + .class_hid = BNXT_ULP_CLASS_HID_22615, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [50] = { - .class_hid = BNXT_ULP_CLASS_HID_00b4, + .class_hid = BNXT_ULP_CLASS_HID_33c15, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [51] = { + .class_hid = BNXT_ULP_CLASS_HID_4d59, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [52] = { + .class_hid = BNXT_ULP_CLASS_HID_1068d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [53] = { + .class_hid = BNXT_ULP_CLASS_HID_21c8d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [54] = { + .class_hid = BNXT_ULP_CLASS_HID_3328d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [55] = { + .class_hid = BNXT_ULP_CLASS_HID_172d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [56] = { + .class_hid = BNXT_ULP_CLASS_HID_12d2d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [57] = { + .class_hid = BNXT_ULP_CLASS_HID_2432d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [58] = { + .class_hid = BNXT_ULP_CLASS_HID_3592d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [59] = { + .class_hid = BNXT_ULP_CLASS_HID_1a49, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [60] = { + .class_hid = BNXT_ULP_CLASS_HID_13049, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 13, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [61] = { + .class_hid = BNXT_ULP_CLASS_HID_24649, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 14, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [62] = { + .class_hid = BNXT_ULP_CLASS_HID_35c49, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 15, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [63] = { + .class_hid = BNXT_ULP_CLASS_HID_50e5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [64] = { + .class_hid = BNXT_ULP_CLASS_HID_10a29, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [65] = { + .class_hid = BNXT_ULP_CLASS_HID_22029, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [66] = { + .class_hid = BNXT_ULP_CLASS_HID_33629, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [67] = { + .class_hid = BNXT_ULP_CLASS_HID_471d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [68] = { + .class_hid = BNXT_ULP_CLASS_HID_10041, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [69] = { + .class_hid = BNXT_ULP_CLASS_HID_21641, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 17, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [70] = { + .class_hid = BNXT_ULP_CLASS_HID_32c41, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 18, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [71] = { + .class_hid = BNXT_ULP_CLASS_HID_10e1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [72] = { + .class_hid = BNXT_ULP_CLASS_HID_126e1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [73] = { + .class_hid = BNXT_ULP_CLASS_HID_23ce1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [74] = { + .class_hid = BNXT_ULP_CLASS_HID_352e1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [75] = { + .class_hid = BNXT_ULP_CLASS_HID_140d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [76] = { + .class_hid = BNXT_ULP_CLASS_HID_12a0d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [77] = { + .class_hid = BNXT_ULP_CLASS_HID_2400d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [78] = { + .class_hid = BNXT_ULP_CLASS_HID_3560d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [79] = { + .class_hid = BNXT_ULP_CLASS_HID_4ab9, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [80] = { + .class_hid = BNXT_ULP_CLASS_HID_103ed, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [81] = { + .class_hid = BNXT_ULP_CLASS_HID_219ed, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [82] = { + .class_hid = BNXT_ULP_CLASS_HID_32fed, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [83] = { + .class_hid = BNXT_ULP_CLASS_HID_40d1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [84] = { + .class_hid = BNXT_ULP_CLASS_HID_156d1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [85] = { + .class_hid = BNXT_ULP_CLASS_HID_21005, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [86] = { + .class_hid = BNXT_ULP_CLASS_HID_32605, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [87] = { + .class_hid = BNXT_ULP_CLASS_HID_0aa5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [88] = { + .class_hid = BNXT_ULP_CLASS_HID_120a5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [89] = { + .class_hid = BNXT_ULP_CLASS_HID_236a5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [90] = { + .class_hid = BNXT_ULP_CLASS_HID_34ca5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [91] = { + .class_hid = BNXT_ULP_CLASS_HID_0159, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [92] = { + .class_hid = BNXT_ULP_CLASS_HID_11759, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 19, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [93] = { + .class_hid = BNXT_ULP_CLASS_HID_22d59, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 20, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [94] = { + .class_hid = BNXT_ULP_CLASS_HID_34359, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 21, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [95] = { + .class_hid = BNXT_ULP_CLASS_HID_37f5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 22, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [96] = { + .class_hid = BNXT_ULP_CLASS_HID_14df5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 22, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [97] = { + .class_hid = BNXT_ULP_CLASS_HID_20739, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 22, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [98] = { + .class_hid = BNXT_ULP_CLASS_HID_31d39, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 22, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [99] = { + .class_hid = BNXT_ULP_CLASS_HID_2e6d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 22, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [100] = { + .class_hid = BNXT_ULP_CLASS_HID_1446d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 22, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [101] = { + .class_hid = BNXT_ULP_CLASS_HID_25a6d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 23, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [102] = { + .class_hid = BNXT_ULP_CLASS_HID_31351, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 24, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [103] = { + .class_hid = BNXT_ULP_CLASS_HID_548d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [104] = { + .class_hid = BNXT_ULP_CLASS_HID_10df1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [105] = { + .class_hid = BNXT_ULP_CLASS_HID_223f1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [106] = { + .class_hid = BNXT_ULP_CLASS_HID_339f1, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [107] = { + .class_hid = BNXT_ULP_CLASS_HID_5829, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [108] = { + .class_hid = BNXT_ULP_CLASS_HID_1111d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [109] = { + .class_hid = BNXT_ULP_CLASS_HID_2271d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [110] = { + .class_hid = BNXT_ULP_CLASS_HID_33d1d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [111] = { + .class_hid = BNXT_ULP_CLASS_HID_3189, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [112] = { + .class_hid = BNXT_ULP_CLASS_HID_14789, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [113] = { + .class_hid = BNXT_ULP_CLASS_HID_200fd, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [114] = { + .class_hid = BNXT_ULP_CLASS_HID_316fd, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [115] = { + .class_hid = BNXT_ULP_CLASS_HID_2821, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [116] = { + .class_hid = BNXT_ULP_CLASS_HID_13e21, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [117] = { + .class_hid = BNXT_ULP_CLASS_HID_25421, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [118] = { + .class_hid = BNXT_ULP_CLASS_HID_30d15, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [119] = { + .class_hid = BNXT_ULP_CLASS_HID_4e41, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [120] = { + .class_hid = BNXT_ULP_CLASS_HID_107b5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [121] = { + .class_hid = BNXT_ULP_CLASS_HID_21db5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [122] = { + .class_hid = BNXT_ULP_CLASS_HID_333b5, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [123] = { + .class_hid = BNXT_ULP_CLASS_HID_2541, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [124] = { + .class_hid = BNXT_ULP_CLASS_HID_2b8d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [125] = { + .class_hid = BNXT_ULP_CLASS_HID_2691, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 25, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [126] = { + .class_hid = BNXT_ULP_CLASS_HID_13c91, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 25, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [127] = { + .class_hid = BNXT_ULP_CLASS_HID_25291, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 26, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [128] = { + .class_hid = BNXT_ULP_CLASS_HID_30c45, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 27, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [129] = { + .class_hid = BNXT_ULP_CLASS_HID_0031, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 28, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [130] = { + .class_hid = BNXT_ULP_CLASS_HID_11631, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 28, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [131] = { + .class_hid = BNXT_ULP_CLASS_HID_22c31, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 28, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [132] = { + .class_hid = BNXT_ULP_CLASS_HID_34231, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 28, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [133] = { + .class_hid = BNXT_ULP_CLASS_HID_53e5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 28, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [134] = { + .class_hid = BNXT_ULP_CLASS_HID_10ca9, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 28, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [135] = { + .class_hid = BNXT_ULP_CLASS_HID_222a9, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 29, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [136] = { + .class_hid = BNXT_ULP_CLASS_HID_338a9, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 30, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [137] = { + .class_hid = BNXT_ULP_CLASS_HID_1d09, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [138] = { + .class_hid = BNXT_ULP_CLASS_HID_13309, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [139] = { + .class_hid = BNXT_ULP_CLASS_HID_24909, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [140] = { + .class_hid = BNXT_ULP_CLASS_HID_3023d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [141] = { + .class_hid = BNXT_ULP_CLASS_HID_20d5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [142] = { + .class_hid = BNXT_ULP_CLASS_HID_136d5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [143] = { + .class_hid = BNXT_ULP_CLASS_HID_24cd5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [144] = { + .class_hid = BNXT_ULP_CLASS_HID_30599, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [145] = { + .class_hid = BNXT_ULP_CLASS_HID_5741, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [146] = { + .class_hid = BNXT_ULP_CLASS_HID_11075, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [147] = { + .class_hid = BNXT_ULP_CLASS_HID_22675, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [148] = { + .class_hid = BNXT_ULP_CLASS_HID_33c75, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [149] = { + .class_hid = BNXT_ULP_CLASS_HID_4d39, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [150] = { + .class_hid = BNXT_ULP_CLASS_HID_106ed, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [151] = { + .class_hid = BNXT_ULP_CLASS_HID_21ced, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [152] = { + .class_hid = BNXT_ULP_CLASS_HID_332ed, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [153] = { + .class_hid = BNXT_ULP_CLASS_HID_174d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [154] = { + .class_hid = BNXT_ULP_CLASS_HID_12d4d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [155] = { + .class_hid = BNXT_ULP_CLASS_HID_2434d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [156] = { + .class_hid = BNXT_ULP_CLASS_HID_3594d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [157] = { + .class_hid = BNXT_ULP_CLASS_HID_1a29, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [158] = { + .class_hid = BNXT_ULP_CLASS_HID_13029, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 31, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [159] = { + .class_hid = BNXT_ULP_CLASS_HID_24629, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 32, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [160] = { + .class_hid = BNXT_ULP_CLASS_HID_35c29, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 33, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [161] = { + .class_hid = BNXT_ULP_CLASS_HID_5085, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 34, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [162] = { + .class_hid = BNXT_ULP_CLASS_HID_10a49, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 34, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [163] = { + .class_hid = BNXT_ULP_CLASS_HID_22049, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 34, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [164] = { + .class_hid = BNXT_ULP_CLASS_HID_33649, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 34, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [165] = { + .class_hid = BNXT_ULP_CLASS_HID_477d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 34, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [166] = { + .class_hid = BNXT_ULP_CLASS_HID_10021, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 34, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [167] = { + .class_hid = BNXT_ULP_CLASS_HID_21621, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 35, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [168] = { + .class_hid = BNXT_ULP_CLASS_HID_32c21, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 36, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [169] = { + .class_hid = BNXT_ULP_CLASS_HID_1081, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [170] = { + .class_hid = BNXT_ULP_CLASS_HID_12681, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [171] = { + .class_hid = BNXT_ULP_CLASS_HID_23c81, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [172] = { + .class_hid = BNXT_ULP_CLASS_HID_35281, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [173] = { + .class_hid = BNXT_ULP_CLASS_HID_146d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [174] = { + .class_hid = BNXT_ULP_CLASS_HID_12a6d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [175] = { + .class_hid = BNXT_ULP_CLASS_HID_2406d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [176] = { + .class_hid = BNXT_ULP_CLASS_HID_3566d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [177] = { + .class_hid = BNXT_ULP_CLASS_HID_4ad9, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [178] = { + .class_hid = BNXT_ULP_CLASS_HID_1038d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [179] = { + .class_hid = BNXT_ULP_CLASS_HID_2198d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [180] = { + .class_hid = BNXT_ULP_CLASS_HID_32f8d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [181] = { + .class_hid = BNXT_ULP_CLASS_HID_40b1, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [182] = { + .class_hid = BNXT_ULP_CLASS_HID_156b1, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [183] = { + .class_hid = BNXT_ULP_CLASS_HID_21065, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [184] = { + .class_hid = BNXT_ULP_CLASS_HID_32665, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [185] = { + .class_hid = BNXT_ULP_CLASS_HID_0ac5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [186] = { + .class_hid = BNXT_ULP_CLASS_HID_120c5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [187] = { + .class_hid = BNXT_ULP_CLASS_HID_236c5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [188] = { + .class_hid = BNXT_ULP_CLASS_HID_34cc5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [189] = { + .class_hid = BNXT_ULP_CLASS_HID_0139, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [190] = { + .class_hid = BNXT_ULP_CLASS_HID_11739, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 37, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [191] = { + .class_hid = BNXT_ULP_CLASS_HID_22d39, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 38, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [192] = { + .class_hid = BNXT_ULP_CLASS_HID_34339, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 39, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [193] = { + .class_hid = BNXT_ULP_CLASS_HID_3795, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 40, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [194] = { + .class_hid = BNXT_ULP_CLASS_HID_14d95, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 40, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [195] = { + .class_hid = BNXT_ULP_CLASS_HID_20759, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 40, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [196] = { + .class_hid = BNXT_ULP_CLASS_HID_31d59, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 40, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [197] = { + .class_hid = BNXT_ULP_CLASS_HID_2e0d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 40, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [198] = { + .class_hid = BNXT_ULP_CLASS_HID_1440d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 40, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [199] = { + .class_hid = BNXT_ULP_CLASS_HID_25a0d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 41, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [200] = { + .class_hid = BNXT_ULP_CLASS_HID_31331, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 42, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [201] = { + .class_hid = BNXT_ULP_CLASS_HID_54ed, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [202] = { + .class_hid = BNXT_ULP_CLASS_HID_10d91, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [203] = { + .class_hid = BNXT_ULP_CLASS_HID_22391, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [204] = { + .class_hid = BNXT_ULP_CLASS_HID_33991, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [205] = { + .class_hid = BNXT_ULP_CLASS_HID_5849, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [206] = { + .class_hid = BNXT_ULP_CLASS_HID_1117d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [207] = { + .class_hid = BNXT_ULP_CLASS_HID_2277d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [208] = { + .class_hid = BNXT_ULP_CLASS_HID_33d7d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [209] = { + .class_hid = BNXT_ULP_CLASS_HID_31e9, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [210] = { + .class_hid = BNXT_ULP_CLASS_HID_147e9, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [211] = { + .class_hid = BNXT_ULP_CLASS_HID_2009d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [212] = { + .class_hid = BNXT_ULP_CLASS_HID_3169d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [213] = { + .class_hid = BNXT_ULP_CLASS_HID_2841, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [214] = { + .class_hid = BNXT_ULP_CLASS_HID_13e41, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [215] = { + .class_hid = BNXT_ULP_CLASS_HID_25441, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [216] = { + .class_hid = BNXT_ULP_CLASS_HID_30d75, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [217] = { + .class_hid = BNXT_ULP_CLASS_HID_4e21, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [218] = { + .class_hid = BNXT_ULP_CLASS_HID_107d5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [219] = { + .class_hid = BNXT_ULP_CLASS_HID_21dd5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [220] = { + .class_hid = BNXT_ULP_CLASS_HID_333d5, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [221] = { + .class_hid = BNXT_ULP_CLASS_HID_2521, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [222] = { + .class_hid = BNXT_ULP_CLASS_HID_2bed, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [223] = { + .class_hid = BNXT_ULP_CLASS_HID_1865, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 43, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [224] = { + .class_hid = BNXT_ULP_CLASS_HID_389d, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 44, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [225] = { + .class_hid = BNXT_ULP_CLASS_HID_123d, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 44, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [226] = { + .class_hid = BNXT_ULP_CLASS_HID_4ef1, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 45, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [227] = { + .class_hid = BNXT_ULP_CLASS_HID_1229, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 45, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [228] = { + .class_hid = BNXT_ULP_CLASS_HID_3241, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 45, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [229] = { + .class_hid = BNXT_ULP_CLASS_HID_0be1, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 45, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [230] = { + .class_hid = BNXT_ULP_CLASS_HID_48b5, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 45, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [231] = { + .class_hid = BNXT_ULP_CLASS_HID_0bed, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 45, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [232] = { + .class_hid = BNXT_ULP_CLASS_HID_2c05, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 46, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [233] = { + .class_hid = BNXT_ULP_CLASS_HID_05a5, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 46, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [234] = { + .class_hid = BNXT_ULP_CLASS_HID_4279, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 47, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [235] = { + .class_hid = BNXT_ULP_CLASS_HID_05d1, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 47, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [236] = { + .class_hid = BNXT_ULP_CLASS_HID_25c9, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 47, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [237] = { + .class_hid = BNXT_ULP_CLASS_HID_5c55, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 47, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [238] = { + .class_hid = BNXT_ULP_CLASS_HID_3c3d, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 47, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [239] = { + .class_hid = BNXT_ULP_CLASS_HID_4fc9, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 47, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [240] = { + .class_hid = BNXT_ULP_CLASS_HID_1335, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 48, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [241] = { + .class_hid = BNXT_ULP_CLASS_HID_4981, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 48, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [242] = { + .class_hid = BNXT_ULP_CLASS_HID_2969, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [243] = { + .class_hid = BNXT_ULP_CLASS_HID_498d, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [244] = { + .class_hid = BNXT_ULP_CLASS_HID_0cf9, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [245] = { + .class_hid = BNXT_ULP_CLASS_HID_4345, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [246] = { + .class_hid = BNXT_ULP_CLASS_HID_232d, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [247] = { + .class_hid = BNXT_ULP_CLASS_HID_2579, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [248] = { + .class_hid = BNXT_ULP_CLASS_HID_2bb5, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [249] = { + .class_hid = BNXT_ULP_CLASS_HID_1845, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 49, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [250] = { + .class_hid = BNXT_ULP_CLASS_HID_1399, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 49, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [251] = { + .class_hid = BNXT_ULP_CLASS_HID_0eed, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 50, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [252] = { + .class_hid = BNXT_ULP_CLASS_HID_0a21, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 51, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [253] = { + .class_hid = BNXT_ULP_CLASS_HID_38bd, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 52, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [254] = { + .class_hid = BNXT_ULP_CLASS_HID_33f1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 52, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [255] = { + .class_hid = BNXT_ULP_CLASS_HID_2ec5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 52, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [256] = { + .class_hid = BNXT_ULP_CLASS_HID_2a19, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 52, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [257] = { + .class_hid = BNXT_ULP_CLASS_HID_121d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 52, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [258] = { + .class_hid = BNXT_ULP_CLASS_HID_0d51, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 52, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [259] = { + .class_hid = BNXT_ULP_CLASS_HID_08a5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 53, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [260] = { + .class_hid = BNXT_ULP_CLASS_HID_03f9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 54, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [261] = { + .class_hid = BNXT_ULP_CLASS_HID_4ed1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [262] = { + .class_hid = BNXT_ULP_CLASS_HID_4a25, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [263] = { + .class_hid = BNXT_ULP_CLASS_HID_4579, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [264] = { + .class_hid = BNXT_ULP_CLASS_HID_404d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [265] = { + .class_hid = BNXT_ULP_CLASS_HID_1209, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [266] = { + .class_hid = BNXT_ULP_CLASS_HID_0d5d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [267] = { + .class_hid = BNXT_ULP_CLASS_HID_0891, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [268] = { + .class_hid = BNXT_ULP_CLASS_HID_03e5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [269] = { + .class_hid = BNXT_ULP_CLASS_HID_3261, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [270] = { + .class_hid = BNXT_ULP_CLASS_HID_2db5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [271] = { + .class_hid = BNXT_ULP_CLASS_HID_2889, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [272] = { + .class_hid = BNXT_ULP_CLASS_HID_23dd, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [273] = { + .class_hid = BNXT_ULP_CLASS_HID_0bc1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [274] = { + .class_hid = BNXT_ULP_CLASS_HID_0715, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [275] = { + .class_hid = BNXT_ULP_CLASS_HID_0269, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [276] = { + .class_hid = BNXT_ULP_CLASS_HID_5a69, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [277] = { + .class_hid = BNXT_ULP_CLASS_HID_4895, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [278] = { + .class_hid = BNXT_ULP_CLASS_HID_43e9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [279] = { + .class_hid = BNXT_ULP_CLASS_HID_3f3d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [280] = { + .class_hid = BNXT_ULP_CLASS_HID_3a71, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [281] = { + .class_hid = BNXT_ULP_CLASS_HID_0bcd, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [282] = { + .class_hid = BNXT_ULP_CLASS_HID_0701, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 55, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [283] = { + .class_hid = BNXT_ULP_CLASS_HID_0255, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 56, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [284] = { + .class_hid = BNXT_ULP_CLASS_HID_5a55, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 57, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [285] = { + .class_hid = BNXT_ULP_CLASS_HID_2c25, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 58, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [286] = { + .class_hid = BNXT_ULP_CLASS_HID_2779, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 58, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [287] = { + .class_hid = BNXT_ULP_CLASS_HID_224d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 58, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [288] = { + .class_hid = BNXT_ULP_CLASS_HID_1d81, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 58, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [289] = { + .class_hid = BNXT_ULP_CLASS_HID_0585, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 58, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [290] = { + .class_hid = BNXT_ULP_CLASS_HID_00d9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 58, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [291] = { + .class_hid = BNXT_ULP_CLASS_HID_58d9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 59, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [292] = { + .class_hid = BNXT_ULP_CLASS_HID_542d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 60, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [293] = { + .class_hid = BNXT_ULP_CLASS_HID_4259, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [294] = { + .class_hid = BNXT_ULP_CLASS_HID_3dad, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [295] = { + .class_hid = BNXT_ULP_CLASS_HID_38e1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [296] = { + .class_hid = BNXT_ULP_CLASS_HID_3435, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [297] = { + .class_hid = BNXT_ULP_CLASS_HID_05f1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [298] = { + .class_hid = BNXT_ULP_CLASS_HID_00c5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [299] = { + .class_hid = BNXT_ULP_CLASS_HID_58c5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [300] = { + .class_hid = BNXT_ULP_CLASS_HID_5419, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [301] = { + .class_hid = BNXT_ULP_CLASS_HID_25e9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [302] = { + .class_hid = BNXT_ULP_CLASS_HID_213d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [303] = { + .class_hid = BNXT_ULP_CLASS_HID_1c71, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [304] = { + .class_hid = BNXT_ULP_CLASS_HID_1745, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [305] = { + .class_hid = BNXT_ULP_CLASS_HID_5c75, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [306] = { + .class_hid = BNXT_ULP_CLASS_HID_5749, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [307] = { + .class_hid = BNXT_ULP_CLASS_HID_529d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [308] = { + .class_hid = BNXT_ULP_CLASS_HID_4dd1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [309] = { + .class_hid = BNXT_ULP_CLASS_HID_3c1d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [310] = { + .class_hid = BNXT_ULP_CLASS_HID_3751, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [311] = { + .class_hid = BNXT_ULP_CLASS_HID_32a5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [312] = { + .class_hid = BNXT_ULP_CLASS_HID_2df9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [313] = { + .class_hid = BNXT_ULP_CLASS_HID_4fe9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [314] = { + .class_hid = BNXT_ULP_CLASS_HID_4b3d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 61, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [315] = { + .class_hid = BNXT_ULP_CLASS_HID_4671, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 62, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [316] = { + .class_hid = BNXT_ULP_CLASS_HID_4145, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 63, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [317] = { + .class_hid = BNXT_ULP_CLASS_HID_1315, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 64, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [318] = { + .class_hid = BNXT_ULP_CLASS_HID_0e69, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 64, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [319] = { + .class_hid = BNXT_ULP_CLASS_HID_09bd, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 64, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [320] = { + .class_hid = BNXT_ULP_CLASS_HID_04f1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 64, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [321] = { + .class_hid = BNXT_ULP_CLASS_HID_49a1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 64, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [322] = { + .class_hid = BNXT_ULP_CLASS_HID_44f5, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 64, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [323] = { + .class_hid = BNXT_ULP_CLASS_HID_3fc9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 65, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [324] = { + .class_hid = BNXT_ULP_CLASS_HID_3b1d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 66, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [325] = { + .class_hid = BNXT_ULP_CLASS_HID_2949, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [326] = { + .class_hid = BNXT_ULP_CLASS_HID_249d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [327] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [328] = { + .class_hid = BNXT_ULP_CLASS_HID_1b25, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [329] = { + .class_hid = BNXT_ULP_CLASS_HID_49ad, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [330] = { + .class_hid = BNXT_ULP_CLASS_HID_44e1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [331] = { + .class_hid = BNXT_ULP_CLASS_HID_4035, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [332] = { + .class_hid = BNXT_ULP_CLASS_HID_3b09, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [333] = { + .class_hid = BNXT_ULP_CLASS_HID_0cd9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [334] = { + .class_hid = BNXT_ULP_CLASS_HID_082d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [335] = { + .class_hid = BNXT_ULP_CLASS_HID_0361, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [336] = { + .class_hid = BNXT_ULP_CLASS_HID_5b61, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [337] = { + .class_hid = BNXT_ULP_CLASS_HID_4365, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [338] = { + .class_hid = BNXT_ULP_CLASS_HID_3eb9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [339] = { + .class_hid = BNXT_ULP_CLASS_HID_398d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [340] = { + .class_hid = BNXT_ULP_CLASS_HID_34c1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [341] = { + .class_hid = BNXT_ULP_CLASS_HID_230d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [342] = { + .class_hid = BNXT_ULP_CLASS_HID_1e41, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [343] = { + .class_hid = BNXT_ULP_CLASS_HID_1995, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [344] = { + .class_hid = BNXT_ULP_CLASS_HID_14e9, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [345] = { + .class_hid = BNXT_ULP_CLASS_HID_2559, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [346] = { + .class_hid = BNXT_ULP_CLASS_HID_2b95, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [347] = { + .class_hid = BNXT_ULP_CLASS_HID_1825, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 67, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [348] = { + .class_hid = BNXT_ULP_CLASS_HID_13f9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 67, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [349] = { + .class_hid = BNXT_ULP_CLASS_HID_0e8d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 68, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [350] = { + .class_hid = BNXT_ULP_CLASS_HID_0a41, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 69, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [351] = { + .class_hid = BNXT_ULP_CLASS_HID_38dd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 70, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [352] = { + .class_hid = BNXT_ULP_CLASS_HID_3391, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 70, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [353] = { + .class_hid = BNXT_ULP_CLASS_HID_2ea5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 70, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [354] = { + .class_hid = BNXT_ULP_CLASS_HID_2a79, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 70, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [355] = { + .class_hid = BNXT_ULP_CLASS_HID_127d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 70, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [356] = { + .class_hid = BNXT_ULP_CLASS_HID_0d31, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 70, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [357] = { + .class_hid = BNXT_ULP_CLASS_HID_08c5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 71, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [358] = { + .class_hid = BNXT_ULP_CLASS_HID_0399, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 72, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [359] = { + .class_hid = BNXT_ULP_CLASS_HID_4eb1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [360] = { + .class_hid = BNXT_ULP_CLASS_HID_4a45, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [361] = { + .class_hid = BNXT_ULP_CLASS_HID_4519, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [362] = { + .class_hid = BNXT_ULP_CLASS_HID_402d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [363] = { + .class_hid = BNXT_ULP_CLASS_HID_1269, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [364] = { + .class_hid = BNXT_ULP_CLASS_HID_0d3d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [365] = { + .class_hid = BNXT_ULP_CLASS_HID_08f1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [366] = { + .class_hid = BNXT_ULP_CLASS_HID_0385, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [367] = { + .class_hid = BNXT_ULP_CLASS_HID_3201, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [368] = { + .class_hid = BNXT_ULP_CLASS_HID_2dd5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [369] = { + .class_hid = BNXT_ULP_CLASS_HID_28e9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [370] = { + .class_hid = BNXT_ULP_CLASS_HID_23bd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [371] = { + .class_hid = BNXT_ULP_CLASS_HID_0ba1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [372] = { + .class_hid = BNXT_ULP_CLASS_HID_0775, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [373] = { + .class_hid = BNXT_ULP_CLASS_HID_0209, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [374] = { + .class_hid = BNXT_ULP_CLASS_HID_5a09, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [375] = { + .class_hid = BNXT_ULP_CLASS_HID_48f5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [376] = { + .class_hid = BNXT_ULP_CLASS_HID_4389, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [377] = { + .class_hid = BNXT_ULP_CLASS_HID_3f5d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [378] = { + .class_hid = BNXT_ULP_CLASS_HID_3a11, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [379] = { + .class_hid = BNXT_ULP_CLASS_HID_0bad, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [380] = { + .class_hid = BNXT_ULP_CLASS_HID_0761, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 73, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [381] = { + .class_hid = BNXT_ULP_CLASS_HID_0235, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 74, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [382] = { + .class_hid = BNXT_ULP_CLASS_HID_5a35, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 75, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [383] = { + .class_hid = BNXT_ULP_CLASS_HID_2c45, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 76, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [384] = { + .class_hid = BNXT_ULP_CLASS_HID_2719, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 76, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [385] = { + .class_hid = BNXT_ULP_CLASS_HID_222d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 76, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [386] = { + .class_hid = BNXT_ULP_CLASS_HID_1de1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 76, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [387] = { + .class_hid = BNXT_ULP_CLASS_HID_05e5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 76, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [388] = { + .class_hid = BNXT_ULP_CLASS_HID_00b9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 76, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [389] = { + .class_hid = BNXT_ULP_CLASS_HID_58b9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 77, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [390] = { + .class_hid = BNXT_ULP_CLASS_HID_544d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 78, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [391] = { + .class_hid = BNXT_ULP_CLASS_HID_4239, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [392] = { + .class_hid = BNXT_ULP_CLASS_HID_3dcd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [393] = { + .class_hid = BNXT_ULP_CLASS_HID_3881, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [394] = { + .class_hid = BNXT_ULP_CLASS_HID_3455, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [395] = { + .class_hid = BNXT_ULP_CLASS_HID_0591, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [396] = { + .class_hid = BNXT_ULP_CLASS_HID_00a5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [397] = { + .class_hid = BNXT_ULP_CLASS_HID_58a5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [398] = { + .class_hid = BNXT_ULP_CLASS_HID_5479, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [399] = { + .class_hid = BNXT_ULP_CLASS_HID_2589, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [400] = { + .class_hid = BNXT_ULP_CLASS_HID_215d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [401] = { + .class_hid = BNXT_ULP_CLASS_HID_1c11, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [402] = { + .class_hid = BNXT_ULP_CLASS_HID_1725, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [403] = { + .class_hid = BNXT_ULP_CLASS_HID_5c15, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [404] = { + .class_hid = BNXT_ULP_CLASS_HID_5729, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [405] = { + .class_hid = BNXT_ULP_CLASS_HID_52fd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [406] = { + .class_hid = BNXT_ULP_CLASS_HID_4db1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [407] = { + .class_hid = BNXT_ULP_CLASS_HID_3c7d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [408] = { + .class_hid = BNXT_ULP_CLASS_HID_3731, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [409] = { + .class_hid = BNXT_ULP_CLASS_HID_32c5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [410] = { + .class_hid = BNXT_ULP_CLASS_HID_2d99, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [411] = { + .class_hid = BNXT_ULP_CLASS_HID_4f89, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [412] = { + .class_hid = BNXT_ULP_CLASS_HID_4b5d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 79, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [413] = { + .class_hid = BNXT_ULP_CLASS_HID_4611, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 80, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [414] = { + .class_hid = BNXT_ULP_CLASS_HID_4125, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 81, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [415] = { + .class_hid = BNXT_ULP_CLASS_HID_1375, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 82, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [416] = { + .class_hid = BNXT_ULP_CLASS_HID_0e09, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 82, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [417] = { + .class_hid = BNXT_ULP_CLASS_HID_09dd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 82, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [418] = { + .class_hid = BNXT_ULP_CLASS_HID_0491, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 82, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [419] = { + .class_hid = BNXT_ULP_CLASS_HID_49c1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 82, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [420] = { + .class_hid = BNXT_ULP_CLASS_HID_4495, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 82, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [421] = { + .class_hid = BNXT_ULP_CLASS_HID_3fa9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 83, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [422] = { + .class_hid = BNXT_ULP_CLASS_HID_3b7d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 84, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [423] = { + .class_hid = BNXT_ULP_CLASS_HID_2929, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [424] = { + .class_hid = BNXT_ULP_CLASS_HID_24fd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [425] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [426] = { + .class_hid = BNXT_ULP_CLASS_HID_1b45, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [427] = { + .class_hid = BNXT_ULP_CLASS_HID_49cd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [428] = { + .class_hid = BNXT_ULP_CLASS_HID_4481, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [429] = { + .class_hid = BNXT_ULP_CLASS_HID_4055, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [430] = { + .class_hid = BNXT_ULP_CLASS_HID_3b69, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [431] = { + .class_hid = BNXT_ULP_CLASS_HID_0cb9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [432] = { + .class_hid = BNXT_ULP_CLASS_HID_084d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [433] = { + .class_hid = BNXT_ULP_CLASS_HID_0301, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [434] = { + .class_hid = BNXT_ULP_CLASS_HID_5b01, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [435] = { + .class_hid = BNXT_ULP_CLASS_HID_4305, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [436] = { + .class_hid = BNXT_ULP_CLASS_HID_3ed9, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [437] = { + .class_hid = BNXT_ULP_CLASS_HID_39ed, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [438] = { + .class_hid = BNXT_ULP_CLASS_HID_34a1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [439] = { + .class_hid = BNXT_ULP_CLASS_HID_236d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [440] = { + .class_hid = BNXT_ULP_CLASS_HID_1e21, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [441] = { + .class_hid = BNXT_ULP_CLASS_HID_19f5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [442] = { + .class_hid = BNXT_ULP_CLASS_HID_1489, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [443] = { + .class_hid = BNXT_ULP_CLASS_HID_2539, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [444] = { + .class_hid = BNXT_ULP_CLASS_HID_2bf5, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [445] = { + .class_hid = BNXT_ULP_CLASS_HID_b6af, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [446] = { + .class_hid = BNXT_ULP_CLASS_HID_b1d3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [447] = { + .class_hid = BNXT_ULP_CLASS_HID_1c7d3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [448] = { + .class_hid = BNXT_ULP_CLASS_HID_1ccaf, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [449] = { + .class_hid = BNXT_ULP_CLASS_HID_da33, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [450] = { + .class_hid = BNXT_ULP_CLASS_HID_d567, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [451] = { + .class_hid = BNXT_ULP_CLASS_HID_18eab, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [452] = { + .class_hid = BNXT_ULP_CLASS_HID_19367, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [453] = { + .class_hid = BNXT_ULP_CLASS_HID_a10b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 85, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [454] = { + .class_hid = BNXT_ULP_CLASS_HID_9c3f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 86, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [455] = { + .class_hid = BNXT_ULP_CLASS_HID_1b23f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 86, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [456] = { + .class_hid = BNXT_ULP_CLASS_HID_1b70b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [457] = { + .class_hid = BNXT_ULP_CLASS_HID_c49f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [458] = { + .class_hid = BNXT_ULP_CLASS_HID_bfc3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [459] = { + .class_hid = BNXT_ULP_CLASS_HID_1d5c3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [460] = { + .class_hid = BNXT_ULP_CLASS_HID_1da9f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [461] = { + .class_hid = BNXT_ULP_CLASS_HID_b063, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [462] = { + .class_hid = BNXT_ULP_CLASS_HID_ab97, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [463] = { + .class_hid = BNXT_ULP_CLASS_HID_1c197, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [464] = { + .class_hid = BNXT_ULP_CLASS_HID_1c663, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [465] = { + .class_hid = BNXT_ULP_CLASS_HID_d3f7, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [466] = { + .class_hid = BNXT_ULP_CLASS_HID_cf3b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [467] = { + .class_hid = BNXT_ULP_CLASS_HID_1886f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [468] = { + .class_hid = BNXT_ULP_CLASS_HID_18d3b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [469] = { + .class_hid = BNXT_ULP_CLASS_HID_9acf, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [470] = { + .class_hid = BNXT_ULP_CLASS_HID_95f3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [471] = { + .class_hid = BNXT_ULP_CLASS_HID_1abf3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [472] = { + .class_hid = BNXT_ULP_CLASS_HID_1b0cf, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [473] = { + .class_hid = BNXT_ULP_CLASS_HID_be53, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [474] = { + .class_hid = BNXT_ULP_CLASS_HID_b987, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [475] = { + .class_hid = BNXT_ULP_CLASS_HID_1cf87, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [476] = { + .class_hid = BNXT_ULP_CLASS_HID_1d453, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [477] = { + .class_hid = BNXT_ULP_CLASS_HID_aa27, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [478] = { + .class_hid = BNXT_ULP_CLASS_HID_a56b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [479] = { + .class_hid = BNXT_ULP_CLASS_HID_1bb6b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [480] = { + .class_hid = BNXT_ULP_CLASS_HID_1c027, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [481] = { + .class_hid = BNXT_ULP_CLASS_HID_cdcb, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [482] = { + .class_hid = BNXT_ULP_CLASS_HID_c8ff, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [483] = { + .class_hid = BNXT_ULP_CLASS_HID_18223, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [484] = { + .class_hid = BNXT_ULP_CLASS_HID_186ff, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [485] = { + .class_hid = BNXT_ULP_CLASS_HID_9483, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 87, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [486] = { + .class_hid = BNXT_ULP_CLASS_HID_8fb7, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 88, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [487] = { + .class_hid = BNXT_ULP_CLASS_HID_1a5b7, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 88, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [488] = { + .class_hid = BNXT_ULP_CLASS_HID_1aa83, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [489] = { + .class_hid = BNXT_ULP_CLASS_HID_b817, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [490] = { + .class_hid = BNXT_ULP_CLASS_HID_b35b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [491] = { + .class_hid = BNXT_ULP_CLASS_HID_1c95b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [492] = { + .class_hid = BNXT_ULP_CLASS_HID_1ce17, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [493] = { + .class_hid = BNXT_ULP_CLASS_HID_a3fb, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [494] = { + .class_hid = BNXT_ULP_CLASS_HID_9f2f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [495] = { + .class_hid = BNXT_ULP_CLASS_HID_1b52f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [496] = { + .class_hid = BNXT_ULP_CLASS_HID_1b9fb, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [497] = { + .class_hid = BNXT_ULP_CLASS_HID_c78f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [498] = { + .class_hid = BNXT_ULP_CLASS_HID_c2b3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [499] = { + .class_hid = BNXT_ULP_CLASS_HID_1d8b3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [500] = { + .class_hid = BNXT_ULP_CLASS_HID_180b3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [501] = { + .class_hid = BNXT_ULP_CLASS_HID_8e47, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [502] = { + .class_hid = BNXT_ULP_CLASS_HID_898b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [503] = { + .class_hid = BNXT_ULP_CLASS_HID_19f8b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [504] = { + .class_hid = BNXT_ULP_CLASS_HID_1a447, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [505] = { + .class_hid = BNXT_ULP_CLASS_HID_b1eb, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [506] = { + .class_hid = BNXT_ULP_CLASS_HID_ad1f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [507] = { + .class_hid = BNXT_ULP_CLASS_HID_1c31f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [508] = { + .class_hid = BNXT_ULP_CLASS_HID_1c7eb, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [509] = { + .class_hid = BNXT_ULP_CLASS_HID_9137, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [510] = { + .class_hid = BNXT_ULP_CLASS_HID_8c7b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [511] = { + .class_hid = BNXT_ULP_CLASS_HID_1a27b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [512] = { + .class_hid = BNXT_ULP_CLASS_HID_1a737, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [513] = { + .class_hid = BNXT_ULP_CLASS_HID_b4db, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [514] = { + .class_hid = BNXT_ULP_CLASS_HID_b00f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [515] = { + .class_hid = BNXT_ULP_CLASS_HID_1c60f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [516] = { + .class_hid = BNXT_ULP_CLASS_HID_1cadb, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [517] = { + .class_hid = BNXT_ULP_CLASS_HID_8b0b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [518] = { + .class_hid = BNXT_ULP_CLASS_HID_863f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [519] = { + .class_hid = BNXT_ULP_CLASS_HID_19c3f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [520] = { + .class_hid = BNXT_ULP_CLASS_HID_1a10b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [521] = { + .class_hid = BNXT_ULP_CLASS_HID_ae9f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [522] = { + .class_hid = BNXT_ULP_CLASS_HID_a9c3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [523] = { + .class_hid = BNXT_ULP_CLASS_HID_1bfc3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [524] = { + .class_hid = BNXT_ULP_CLASS_HID_1c49f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [525] = { + .class_hid = BNXT_ULP_CLASS_HID_2563, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [526] = { + .class_hid = BNXT_ULP_CLASS_HID_2baf, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [527] = { + .class_hid = BNXT_ULP_CLASS_HID_4f33, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [528] = { + .class_hid = BNXT_ULP_CLASS_HID_160b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [529] = { + .class_hid = BNXT_ULP_CLASS_HID_399f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [530] = { + .class_hid = BNXT_ULP_CLASS_HID_48f7, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [531] = { + .class_hid = BNXT_ULP_CLASS_HID_0fcf, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [532] = { + .class_hid = BNXT_ULP_CLASS_HID_3353, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [533] = { + .class_hid = BNXT_ULP_CLASS_HID_b68f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [534] = { + .class_hid = BNXT_ULP_CLASS_HID_b94f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [535] = { + .class_hid = BNXT_ULP_CLASS_HID_fc0f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [536] = { + .class_hid = BNXT_ULP_CLASS_HID_fecf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [537] = { + .class_hid = BNXT_ULP_CLASS_HID_b1f3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [538] = { + .class_hid = BNXT_ULP_CLASS_HID_b4b3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [539] = { + .class_hid = BNXT_ULP_CLASS_HID_f773, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [540] = { + .class_hid = BNXT_ULP_CLASS_HID_fa33, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [541] = { + .class_hid = BNXT_ULP_CLASS_HID_1c7f3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [542] = { + .class_hid = BNXT_ULP_CLASS_HID_1eab3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [543] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd73, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [544] = { + .class_hid = BNXT_ULP_CLASS_HID_1f033, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [545] = { + .class_hid = BNXT_ULP_CLASS_HID_1cc8f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [546] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef4f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [547] = { + .class_hid = BNXT_ULP_CLASS_HID_1d20f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [548] = { + .class_hid = BNXT_ULP_CLASS_HID_1f4cf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [549] = { + .class_hid = BNXT_ULP_CLASS_HID_da13, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [550] = { + .class_hid = BNXT_ULP_CLASS_HID_a007, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [551] = { + .class_hid = BNXT_ULP_CLASS_HID_c2c7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [552] = { + .class_hid = BNXT_ULP_CLASS_HID_e587, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [553] = { + .class_hid = BNXT_ULP_CLASS_HID_d547, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [554] = { + .class_hid = BNXT_ULP_CLASS_HID_f807, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [555] = { + .class_hid = BNXT_ULP_CLASS_HID_dac7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [556] = { + .class_hid = BNXT_ULP_CLASS_HID_e0cb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [557] = { + .class_hid = BNXT_ULP_CLASS_HID_18e8b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [558] = { + .class_hid = BNXT_ULP_CLASS_HID_1b14b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [559] = { + .class_hid = BNXT_ULP_CLASS_HID_1d40b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [560] = { + .class_hid = BNXT_ULP_CLASS_HID_1f6cb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [561] = { + .class_hid = BNXT_ULP_CLASS_HID_19347, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [562] = { + .class_hid = BNXT_ULP_CLASS_HID_1b607, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [563] = { + .class_hid = BNXT_ULP_CLASS_HID_1d8c7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [564] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb87, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [565] = { + .class_hid = BNXT_ULP_CLASS_HID_a12b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [566] = { + .class_hid = BNXT_ULP_CLASS_HID_a3eb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [567] = { + .class_hid = BNXT_ULP_CLASS_HID_e6ab, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 91, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [568] = { + .class_hid = BNXT_ULP_CLASS_HID_e96b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 92, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [569] = { + .class_hid = BNXT_ULP_CLASS_HID_9c1f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 93, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [570] = { + .class_hid = BNXT_ULP_CLASS_HID_bedf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 93, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [571] = { + .class_hid = BNXT_ULP_CLASS_HID_e19f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 93, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [572] = { + .class_hid = BNXT_ULP_CLASS_HID_e45f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 93, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [573] = { + .class_hid = BNXT_ULP_CLASS_HID_1b21f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 93, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [574] = { + .class_hid = BNXT_ULP_CLASS_HID_1b4df, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 93, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [575] = { + .class_hid = BNXT_ULP_CLASS_HID_1f79f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 94, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [576] = { + .class_hid = BNXT_ULP_CLASS_HID_1fa5f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 95, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [577] = { + .class_hid = BNXT_ULP_CLASS_HID_1b72b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [578] = { + .class_hid = BNXT_ULP_CLASS_HID_1b9eb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [579] = { + .class_hid = BNXT_ULP_CLASS_HID_1fcab, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [580] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff6b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [581] = { + .class_hid = BNXT_ULP_CLASS_HID_c4bf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [582] = { + .class_hid = BNXT_ULP_CLASS_HID_e77f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [583] = { + .class_hid = BNXT_ULP_CLASS_HID_ca3f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [584] = { + .class_hid = BNXT_ULP_CLASS_HID_ecff, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [585] = { + .class_hid = BNXT_ULP_CLASS_HID_bfe3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [586] = { + .class_hid = BNXT_ULP_CLASS_HID_e2a3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [587] = { + .class_hid = BNXT_ULP_CLASS_HID_c563, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [588] = { + .class_hid = BNXT_ULP_CLASS_HID_e823, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [589] = { + .class_hid = BNXT_ULP_CLASS_HID_1d5e3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [590] = { + .class_hid = BNXT_ULP_CLASS_HID_1f8a3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [591] = { + .class_hid = BNXT_ULP_CLASS_HID_1db63, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [592] = { + .class_hid = BNXT_ULP_CLASS_HID_1e117, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [593] = { + .class_hid = BNXT_ULP_CLASS_HID_1dabf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [594] = { + .class_hid = BNXT_ULP_CLASS_HID_1a0a3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [595] = { + .class_hid = BNXT_ULP_CLASS_HID_1c363, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [596] = { + .class_hid = BNXT_ULP_CLASS_HID_1e623, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [597] = { + .class_hid = BNXT_ULP_CLASS_HID_b043, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [598] = { + .class_hid = BNXT_ULP_CLASS_HID_b303, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [599] = { + .class_hid = BNXT_ULP_CLASS_HID_f5c3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [600] = { + .class_hid = BNXT_ULP_CLASS_HID_f883, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [601] = { + .class_hid = BNXT_ULP_CLASS_HID_abb7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [602] = { + .class_hid = BNXT_ULP_CLASS_HID_ae77, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [603] = { + .class_hid = BNXT_ULP_CLASS_HID_f137, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [604] = { + .class_hid = BNXT_ULP_CLASS_HID_f3f7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [605] = { + .class_hid = BNXT_ULP_CLASS_HID_1c1b7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [606] = { + .class_hid = BNXT_ULP_CLASS_HID_1e477, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [607] = { + .class_hid = BNXT_ULP_CLASS_HID_1c737, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [608] = { + .class_hid = BNXT_ULP_CLASS_HID_1e9f7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [609] = { + .class_hid = BNXT_ULP_CLASS_HID_1c643, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [610] = { + .class_hid = BNXT_ULP_CLASS_HID_1e903, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [611] = { + .class_hid = BNXT_ULP_CLASS_HID_1cbc3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [612] = { + .class_hid = BNXT_ULP_CLASS_HID_1ee83, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [613] = { + .class_hid = BNXT_ULP_CLASS_HID_d3d7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [614] = { + .class_hid = BNXT_ULP_CLASS_HID_f697, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [615] = { + .class_hid = BNXT_ULP_CLASS_HID_d957, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [616] = { + .class_hid = BNXT_ULP_CLASS_HID_fc17, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [617] = { + .class_hid = BNXT_ULP_CLASS_HID_cf1b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [618] = { + .class_hid = BNXT_ULP_CLASS_HID_f1db, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [619] = { + .class_hid = BNXT_ULP_CLASS_HID_d49b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [620] = { + .class_hid = BNXT_ULP_CLASS_HID_f75b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [621] = { + .class_hid = BNXT_ULP_CLASS_HID_1884f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [622] = { + .class_hid = BNXT_ULP_CLASS_HID_1ab0f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [623] = { + .class_hid = BNXT_ULP_CLASS_HID_1cdcf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [624] = { + .class_hid = BNXT_ULP_CLASS_HID_1f08f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [625] = { + .class_hid = BNXT_ULP_CLASS_HID_18d1b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [626] = { + .class_hid = BNXT_ULP_CLASS_HID_1afdb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [627] = { + .class_hid = BNXT_ULP_CLASS_HID_1d29b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [628] = { + .class_hid = BNXT_ULP_CLASS_HID_1f55b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [629] = { + .class_hid = BNXT_ULP_CLASS_HID_9aef, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [630] = { + .class_hid = BNXT_ULP_CLASS_HID_bdaf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [631] = { + .class_hid = BNXT_ULP_CLASS_HID_e06f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [632] = { + .class_hid = BNXT_ULP_CLASS_HID_e32f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [633] = { + .class_hid = BNXT_ULP_CLASS_HID_95d3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [634] = { + .class_hid = BNXT_ULP_CLASS_HID_b893, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [635] = { + .class_hid = BNXT_ULP_CLASS_HID_db53, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [636] = { + .class_hid = BNXT_ULP_CLASS_HID_fe13, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [637] = { + .class_hid = BNXT_ULP_CLASS_HID_1abd3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [638] = { + .class_hid = BNXT_ULP_CLASS_HID_1ae93, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [639] = { + .class_hid = BNXT_ULP_CLASS_HID_1f153, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [640] = { + .class_hid = BNXT_ULP_CLASS_HID_1f413, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [641] = { + .class_hid = BNXT_ULP_CLASS_HID_1b0ef, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [642] = { + .class_hid = BNXT_ULP_CLASS_HID_1b3af, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [643] = { + .class_hid = BNXT_ULP_CLASS_HID_1f66f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [644] = { + .class_hid = BNXT_ULP_CLASS_HID_1f92f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [645] = { + .class_hid = BNXT_ULP_CLASS_HID_be73, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [646] = { + .class_hid = BNXT_ULP_CLASS_HID_e133, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [647] = { + .class_hid = BNXT_ULP_CLASS_HID_c3f3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [648] = { + .class_hid = BNXT_ULP_CLASS_HID_e6b3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [649] = { + .class_hid = BNXT_ULP_CLASS_HID_b9a7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [650] = { + .class_hid = BNXT_ULP_CLASS_HID_bc67, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [651] = { + .class_hid = BNXT_ULP_CLASS_HID_ff27, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [652] = { + .class_hid = BNXT_ULP_CLASS_HID_e1e7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [653] = { + .class_hid = BNXT_ULP_CLASS_HID_1cfa7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [654] = { + .class_hid = BNXT_ULP_CLASS_HID_1f267, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [655] = { + .class_hid = BNXT_ULP_CLASS_HID_1d527, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [656] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7e7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [657] = { + .class_hid = BNXT_ULP_CLASS_HID_1d473, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [658] = { + .class_hid = BNXT_ULP_CLASS_HID_1f733, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [659] = { + .class_hid = BNXT_ULP_CLASS_HID_1d9f3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [660] = { + .class_hid = BNXT_ULP_CLASS_HID_1fcb3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [661] = { + .class_hid = BNXT_ULP_CLASS_HID_aa07, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [662] = { + .class_hid = BNXT_ULP_CLASS_HID_acc7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [663] = { + .class_hid = BNXT_ULP_CLASS_HID_ef87, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [664] = { + .class_hid = BNXT_ULP_CLASS_HID_f247, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [665] = { + .class_hid = BNXT_ULP_CLASS_HID_a54b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [666] = { + .class_hid = BNXT_ULP_CLASS_HID_a80b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [667] = { + .class_hid = BNXT_ULP_CLASS_HID_eacb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [668] = { + .class_hid = BNXT_ULP_CLASS_HID_ed8b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [669] = { + .class_hid = BNXT_ULP_CLASS_HID_1bb4b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [670] = { + .class_hid = BNXT_ULP_CLASS_HID_1be0b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [671] = { + .class_hid = BNXT_ULP_CLASS_HID_1c0cb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [672] = { + .class_hid = BNXT_ULP_CLASS_HID_1e38b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [673] = { + .class_hid = BNXT_ULP_CLASS_HID_1c007, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [674] = { + .class_hid = BNXT_ULP_CLASS_HID_1e2c7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [675] = { + .class_hid = BNXT_ULP_CLASS_HID_1c587, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [676] = { + .class_hid = BNXT_ULP_CLASS_HID_1e847, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [677] = { + .class_hid = BNXT_ULP_CLASS_HID_cdeb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [678] = { + .class_hid = BNXT_ULP_CLASS_HID_f0ab, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [679] = { + .class_hid = BNXT_ULP_CLASS_HID_d36b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [680] = { + .class_hid = BNXT_ULP_CLASS_HID_f62b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [681] = { + .class_hid = BNXT_ULP_CLASS_HID_c8df, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [682] = { + .class_hid = BNXT_ULP_CLASS_HID_eb9f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [683] = { + .class_hid = BNXT_ULP_CLASS_HID_ce5f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [684] = { + .class_hid = BNXT_ULP_CLASS_HID_f11f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [685] = { + .class_hid = BNXT_ULP_CLASS_HID_18203, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [686] = { + .class_hid = BNXT_ULP_CLASS_HID_1a4c3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [687] = { + .class_hid = BNXT_ULP_CLASS_HID_1c783, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [688] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea43, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [689] = { + .class_hid = BNXT_ULP_CLASS_HID_186df, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [690] = { + .class_hid = BNXT_ULP_CLASS_HID_1a99f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [691] = { + .class_hid = BNXT_ULP_CLASS_HID_1cc5f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [692] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef1f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [693] = { + .class_hid = BNXT_ULP_CLASS_HID_94a3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [694] = { + .class_hid = BNXT_ULP_CLASS_HID_b763, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 96, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [695] = { + .class_hid = BNXT_ULP_CLASS_HID_da23, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 97, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [696] = { + .class_hid = BNXT_ULP_CLASS_HID_fce3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 98, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [697] = { + .class_hid = BNXT_ULP_CLASS_HID_8f97, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 99, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [698] = { + .class_hid = BNXT_ULP_CLASS_HID_b257, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 99, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [699] = { + .class_hid = BNXT_ULP_CLASS_HID_d517, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 99, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [700] = { + .class_hid = BNXT_ULP_CLASS_HID_f7d7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 99, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [701] = { + .class_hid = BNXT_ULP_CLASS_HID_1a597, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 99, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [702] = { + .class_hid = BNXT_ULP_CLASS_HID_1a857, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 99, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [703] = { + .class_hid = BNXT_ULP_CLASS_HID_1eb17, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [704] = { + .class_hid = BNXT_ULP_CLASS_HID_1edd7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 101, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [705] = { + .class_hid = BNXT_ULP_CLASS_HID_1aaa3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [706] = { + .class_hid = BNXT_ULP_CLASS_HID_1ad63, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [707] = { + .class_hid = BNXT_ULP_CLASS_HID_1f023, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [708] = { + .class_hid = BNXT_ULP_CLASS_HID_1f2e3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [709] = { + .class_hid = BNXT_ULP_CLASS_HID_b837, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [710] = { + .class_hid = BNXT_ULP_CLASS_HID_baf7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [711] = { + .class_hid = BNXT_ULP_CLASS_HID_fdb7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [712] = { + .class_hid = BNXT_ULP_CLASS_HID_e077, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [713] = { + .class_hid = BNXT_ULP_CLASS_HID_b37b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [714] = { + .class_hid = BNXT_ULP_CLASS_HID_b63b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [715] = { + .class_hid = BNXT_ULP_CLASS_HID_f8fb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [716] = { + .class_hid = BNXT_ULP_CLASS_HID_fbbb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [717] = { + .class_hid = BNXT_ULP_CLASS_HID_1c97b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [718] = { + .class_hid = BNXT_ULP_CLASS_HID_1ec3b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [719] = { + .class_hid = BNXT_ULP_CLASS_HID_1cefb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [720] = { + .class_hid = BNXT_ULP_CLASS_HID_1f1bb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [721] = { + .class_hid = BNXT_ULP_CLASS_HID_1ce37, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [722] = { + .class_hid = BNXT_ULP_CLASS_HID_1f0f7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [723] = { + .class_hid = BNXT_ULP_CLASS_HID_1d3b7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [724] = { + .class_hid = BNXT_ULP_CLASS_HID_1f677, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [725] = { + .class_hid = BNXT_ULP_CLASS_HID_a3db, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [726] = { + .class_hid = BNXT_ULP_CLASS_HID_a69b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [727] = { + .class_hid = BNXT_ULP_CLASS_HID_e95b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [728] = { + .class_hid = BNXT_ULP_CLASS_HID_ec1b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [729] = { + .class_hid = BNXT_ULP_CLASS_HID_9f0f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [730] = { + .class_hid = BNXT_ULP_CLASS_HID_a1cf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [731] = { + .class_hid = BNXT_ULP_CLASS_HID_e48f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [732] = { + .class_hid = BNXT_ULP_CLASS_HID_e74f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [733] = { + .class_hid = BNXT_ULP_CLASS_HID_1b50f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [734] = { + .class_hid = BNXT_ULP_CLASS_HID_1b7cf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [735] = { + .class_hid = BNXT_ULP_CLASS_HID_1fa8f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [736] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd4f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [737] = { + .class_hid = BNXT_ULP_CLASS_HID_1b9db, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [738] = { + .class_hid = BNXT_ULP_CLASS_HID_1bc9b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [739] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff5b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [740] = { + .class_hid = BNXT_ULP_CLASS_HID_1e21b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [741] = { + .class_hid = BNXT_ULP_CLASS_HID_c7af, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [742] = { + .class_hid = BNXT_ULP_CLASS_HID_ea6f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [743] = { + .class_hid = BNXT_ULP_CLASS_HID_cd2f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [744] = { + .class_hid = BNXT_ULP_CLASS_HID_efef, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [745] = { + .class_hid = BNXT_ULP_CLASS_HID_c293, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [746] = { + .class_hid = BNXT_ULP_CLASS_HID_e553, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [747] = { + .class_hid = BNXT_ULP_CLASS_HID_c813, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [748] = { + .class_hid = BNXT_ULP_CLASS_HID_ead3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [749] = { + .class_hid = BNXT_ULP_CLASS_HID_1d893, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [750] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb53, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [751] = { + .class_hid = BNXT_ULP_CLASS_HID_1c147, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [752] = { + .class_hid = BNXT_ULP_CLASS_HID_1e407, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [753] = { + .class_hid = BNXT_ULP_CLASS_HID_18093, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [754] = { + .class_hid = BNXT_ULP_CLASS_HID_1a353, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [755] = { + .class_hid = BNXT_ULP_CLASS_HID_1c613, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [756] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8d3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [757] = { + .class_hid = BNXT_ULP_CLASS_HID_8e67, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [758] = { + .class_hid = BNXT_ULP_CLASS_HID_b127, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [759] = { + .class_hid = BNXT_ULP_CLASS_HID_d3e7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [760] = { + .class_hid = BNXT_ULP_CLASS_HID_f6a7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [761] = { + .class_hid = BNXT_ULP_CLASS_HID_89ab, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [762] = { + .class_hid = BNXT_ULP_CLASS_HID_ac6b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [763] = { + .class_hid = BNXT_ULP_CLASS_HID_cf2b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [764] = { + .class_hid = BNXT_ULP_CLASS_HID_f1eb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [765] = { + .class_hid = BNXT_ULP_CLASS_HID_19fab, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [766] = { + .class_hid = BNXT_ULP_CLASS_HID_1a26b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [767] = { + .class_hid = BNXT_ULP_CLASS_HID_1e52b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [768] = { + .class_hid = BNXT_ULP_CLASS_HID_1e7eb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [769] = { + .class_hid = BNXT_ULP_CLASS_HID_1a467, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [770] = { + .class_hid = BNXT_ULP_CLASS_HID_1a727, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [771] = { + .class_hid = BNXT_ULP_CLASS_HID_1e9e7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [772] = { + .class_hid = BNXT_ULP_CLASS_HID_1eca7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [773] = { + .class_hid = BNXT_ULP_CLASS_HID_b1cb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [774] = { + .class_hid = BNXT_ULP_CLASS_HID_b48b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [775] = { + .class_hid = BNXT_ULP_CLASS_HID_f74b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [776] = { + .class_hid = BNXT_ULP_CLASS_HID_fa0b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [777] = { + .class_hid = BNXT_ULP_CLASS_HID_ad3f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [778] = { + .class_hid = BNXT_ULP_CLASS_HID_afff, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [779] = { + .class_hid = BNXT_ULP_CLASS_HID_f2bf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [780] = { + .class_hid = BNXT_ULP_CLASS_HID_f57f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [781] = { + .class_hid = BNXT_ULP_CLASS_HID_1c33f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [782] = { + .class_hid = BNXT_ULP_CLASS_HID_1e5ff, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [783] = { + .class_hid = BNXT_ULP_CLASS_HID_1c8bf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [784] = { + .class_hid = BNXT_ULP_CLASS_HID_1eb7f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [785] = { + .class_hid = BNXT_ULP_CLASS_HID_1c7cb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [786] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea8b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [787] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd4b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [788] = { + .class_hid = BNXT_ULP_CLASS_HID_1f00b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [789] = { + .class_hid = BNXT_ULP_CLASS_HID_9117, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [790] = { + .class_hid = BNXT_ULP_CLASS_HID_b3d7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [791] = { + .class_hid = BNXT_ULP_CLASS_HID_d697, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [792] = { + .class_hid = BNXT_ULP_CLASS_HID_f957, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [793] = { + .class_hid = BNXT_ULP_CLASS_HID_8c5b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [794] = { + .class_hid = BNXT_ULP_CLASS_HID_af1b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [795] = { + .class_hid = BNXT_ULP_CLASS_HID_d1db, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [796] = { + .class_hid = BNXT_ULP_CLASS_HID_f49b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [797] = { + .class_hid = BNXT_ULP_CLASS_HID_1a25b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [798] = { + .class_hid = BNXT_ULP_CLASS_HID_1a51b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [799] = { + .class_hid = BNXT_ULP_CLASS_HID_1e7db, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [800] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea9b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [801] = { + .class_hid = BNXT_ULP_CLASS_HID_1a717, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [802] = { + .class_hid = BNXT_ULP_CLASS_HID_1a9d7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [803] = { + .class_hid = BNXT_ULP_CLASS_HID_1ec97, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [804] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef57, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [805] = { + .class_hid = BNXT_ULP_CLASS_HID_b4fb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [806] = { + .class_hid = BNXT_ULP_CLASS_HID_b7bb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [807] = { + .class_hid = BNXT_ULP_CLASS_HID_fa7b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [808] = { + .class_hid = BNXT_ULP_CLASS_HID_fd3b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [809] = { + .class_hid = BNXT_ULP_CLASS_HID_b02f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [810] = { + .class_hid = BNXT_ULP_CLASS_HID_b2ef, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [811] = { + .class_hid = BNXT_ULP_CLASS_HID_f5af, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [812] = { + .class_hid = BNXT_ULP_CLASS_HID_f86f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [813] = { + .class_hid = BNXT_ULP_CLASS_HID_1c62f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [814] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8ef, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [815] = { + .class_hid = BNXT_ULP_CLASS_HID_1cbaf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [816] = { + .class_hid = BNXT_ULP_CLASS_HID_1ee6f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [817] = { + .class_hid = BNXT_ULP_CLASS_HID_1cafb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [818] = { + .class_hid = BNXT_ULP_CLASS_HID_1edbb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [819] = { + .class_hid = BNXT_ULP_CLASS_HID_1d07b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [820] = { + .class_hid = BNXT_ULP_CLASS_HID_1f33b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [821] = { + .class_hid = BNXT_ULP_CLASS_HID_8b2b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [822] = { + .class_hid = BNXT_ULP_CLASS_HID_adeb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [823] = { + .class_hid = BNXT_ULP_CLASS_HID_d0ab, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [824] = { + .class_hid = BNXT_ULP_CLASS_HID_f36b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [825] = { + .class_hid = BNXT_ULP_CLASS_HID_861f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [826] = { + .class_hid = BNXT_ULP_CLASS_HID_a8df, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [827] = { + .class_hid = BNXT_ULP_CLASS_HID_cb9f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [828] = { + .class_hid = BNXT_ULP_CLASS_HID_ee5f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [829] = { + .class_hid = BNXT_ULP_CLASS_HID_19c1f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [830] = { + .class_hid = BNXT_ULP_CLASS_HID_1bedf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [831] = { + .class_hid = BNXT_ULP_CLASS_HID_1e19f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [832] = { + .class_hid = BNXT_ULP_CLASS_HID_1e45f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [833] = { + .class_hid = BNXT_ULP_CLASS_HID_1a12b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [834] = { + .class_hid = BNXT_ULP_CLASS_HID_1a3eb, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [835] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6ab, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [836] = { + .class_hid = BNXT_ULP_CLASS_HID_1e96b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [837] = { + .class_hid = BNXT_ULP_CLASS_HID_aebf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [838] = { + .class_hid = BNXT_ULP_CLASS_HID_b17f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [839] = { + .class_hid = BNXT_ULP_CLASS_HID_f43f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [840] = { + .class_hid = BNXT_ULP_CLASS_HID_f6ff, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [841] = { + .class_hid = BNXT_ULP_CLASS_HID_a9e3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [842] = { + .class_hid = BNXT_ULP_CLASS_HID_aca3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [843] = { + .class_hid = BNXT_ULP_CLASS_HID_ef63, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [844] = { + .class_hid = BNXT_ULP_CLASS_HID_f223, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [845] = { + .class_hid = BNXT_ULP_CLASS_HID_1bfe3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [846] = { + .class_hid = BNXT_ULP_CLASS_HID_1e2a3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [847] = { + .class_hid = BNXT_ULP_CLASS_HID_1c563, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [848] = { + .class_hid = BNXT_ULP_CLASS_HID_1e823, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [849] = { + .class_hid = BNXT_ULP_CLASS_HID_1c4bf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [850] = { + .class_hid = BNXT_ULP_CLASS_HID_1e77f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [851] = { + .class_hid = BNXT_ULP_CLASS_HID_1ca3f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [852] = { + .class_hid = BNXT_ULP_CLASS_HID_1ecff, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [853] = { + .class_hid = BNXT_ULP_CLASS_HID_2543, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [854] = { + .class_hid = BNXT_ULP_CLASS_HID_2b8f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [855] = { + .class_hid = BNXT_ULP_CLASS_HID_4f13, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [856] = { + .class_hid = BNXT_ULP_CLASS_HID_162b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [857] = { + .class_hid = BNXT_ULP_CLASS_HID_39bf, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [858] = { + .class_hid = BNXT_ULP_CLASS_HID_48d7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [859] = { + .class_hid = BNXT_ULP_CLASS_HID_0fef, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [860] = { + .class_hid = BNXT_ULP_CLASS_HID_3373, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [861] = { + .class_hid = BNXT_ULP_CLASS_HID_b6ef, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [862] = { + .class_hid = BNXT_ULP_CLASS_HID_b92f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [863] = { + .class_hid = BNXT_ULP_CLASS_HID_fc6f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [864] = { + .class_hid = BNXT_ULP_CLASS_HID_feaf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [865] = { + .class_hid = BNXT_ULP_CLASS_HID_b193, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [866] = { + .class_hid = BNXT_ULP_CLASS_HID_b4d3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [867] = { + .class_hid = BNXT_ULP_CLASS_HID_f713, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [868] = { + .class_hid = BNXT_ULP_CLASS_HID_fa53, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [869] = { + .class_hid = BNXT_ULP_CLASS_HID_1c793, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [870] = { + .class_hid = BNXT_ULP_CLASS_HID_1ead3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [871] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd13, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [872] = { + .class_hid = BNXT_ULP_CLASS_HID_1f053, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [873] = { + .class_hid = BNXT_ULP_CLASS_HID_1ccef, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [874] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef2f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [875] = { + .class_hid = BNXT_ULP_CLASS_HID_1d26f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [876] = { + .class_hid = BNXT_ULP_CLASS_HID_1f4af, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [877] = { + .class_hid = BNXT_ULP_CLASS_HID_da73, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [878] = { + .class_hid = BNXT_ULP_CLASS_HID_a067, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [879] = { + .class_hid = BNXT_ULP_CLASS_HID_c2a7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [880] = { + .class_hid = BNXT_ULP_CLASS_HID_e5e7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [881] = { + .class_hid = BNXT_ULP_CLASS_HID_d527, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [882] = { + .class_hid = BNXT_ULP_CLASS_HID_f867, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [883] = { + .class_hid = BNXT_ULP_CLASS_HID_daa7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [884] = { + .class_hid = BNXT_ULP_CLASS_HID_e0ab, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [885] = { + .class_hid = BNXT_ULP_CLASS_HID_18eeb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [886] = { + .class_hid = BNXT_ULP_CLASS_HID_1b12b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [887] = { + .class_hid = BNXT_ULP_CLASS_HID_1d46b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [888] = { + .class_hid = BNXT_ULP_CLASS_HID_1f6ab, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [889] = { + .class_hid = BNXT_ULP_CLASS_HID_19327, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [890] = { + .class_hid = BNXT_ULP_CLASS_HID_1b667, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [891] = { + .class_hid = BNXT_ULP_CLASS_HID_1d8a7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [892] = { + .class_hid = BNXT_ULP_CLASS_HID_1fbe7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [893] = { + .class_hid = BNXT_ULP_CLASS_HID_a14b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [894] = { + .class_hid = BNXT_ULP_CLASS_HID_a38b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 102, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [895] = { + .class_hid = BNXT_ULP_CLASS_HID_e6cb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 103, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [896] = { + .class_hid = BNXT_ULP_CLASS_HID_e90b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 104, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [897] = { + .class_hid = BNXT_ULP_CLASS_HID_9c7f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 105, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [898] = { + .class_hid = BNXT_ULP_CLASS_HID_bebf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 105, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [899] = { + .class_hid = BNXT_ULP_CLASS_HID_e1ff, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 105, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [900] = { + .class_hid = BNXT_ULP_CLASS_HID_e43f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 105, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [901] = { + .class_hid = BNXT_ULP_CLASS_HID_1b27f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 105, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [902] = { + .class_hid = BNXT_ULP_CLASS_HID_1b4bf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 105, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [903] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7ff, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 106, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [904] = { + .class_hid = BNXT_ULP_CLASS_HID_1fa3f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 107, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [905] = { + .class_hid = BNXT_ULP_CLASS_HID_1b74b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [906] = { + .class_hid = BNXT_ULP_CLASS_HID_1b98b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [907] = { + .class_hid = BNXT_ULP_CLASS_HID_1fccb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [908] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff0b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [909] = { + .class_hid = BNXT_ULP_CLASS_HID_c4df, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [910] = { + .class_hid = BNXT_ULP_CLASS_HID_e71f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [911] = { + .class_hid = BNXT_ULP_CLASS_HID_ca5f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [912] = { + .class_hid = BNXT_ULP_CLASS_HID_ec9f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [913] = { + .class_hid = BNXT_ULP_CLASS_HID_bf83, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [914] = { + .class_hid = BNXT_ULP_CLASS_HID_e2c3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [915] = { + .class_hid = BNXT_ULP_CLASS_HID_c503, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [916] = { + .class_hid = BNXT_ULP_CLASS_HID_e843, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [917] = { + .class_hid = BNXT_ULP_CLASS_HID_1d583, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [918] = { + .class_hid = BNXT_ULP_CLASS_HID_1f8c3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [919] = { + .class_hid = BNXT_ULP_CLASS_HID_1db03, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [920] = { + .class_hid = BNXT_ULP_CLASS_HID_1e177, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [921] = { + .class_hid = BNXT_ULP_CLASS_HID_1dadf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [922] = { + .class_hid = BNXT_ULP_CLASS_HID_1a0c3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [923] = { + .class_hid = BNXT_ULP_CLASS_HID_1c303, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [924] = { + .class_hid = BNXT_ULP_CLASS_HID_1e643, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [925] = { + .class_hid = BNXT_ULP_CLASS_HID_b023, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [926] = { + .class_hid = BNXT_ULP_CLASS_HID_b363, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [927] = { + .class_hid = BNXT_ULP_CLASS_HID_f5a3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [928] = { + .class_hid = BNXT_ULP_CLASS_HID_f8e3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [929] = { + .class_hid = BNXT_ULP_CLASS_HID_abd7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [930] = { + .class_hid = BNXT_ULP_CLASS_HID_ae17, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [931] = { + .class_hid = BNXT_ULP_CLASS_HID_f157, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [932] = { + .class_hid = BNXT_ULP_CLASS_HID_f397, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [933] = { + .class_hid = BNXT_ULP_CLASS_HID_1c1d7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [934] = { + .class_hid = BNXT_ULP_CLASS_HID_1e417, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [935] = { + .class_hid = BNXT_ULP_CLASS_HID_1c757, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [936] = { + .class_hid = BNXT_ULP_CLASS_HID_1e997, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [937] = { + .class_hid = BNXT_ULP_CLASS_HID_1c623, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [938] = { + .class_hid = BNXT_ULP_CLASS_HID_1e963, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [939] = { + .class_hid = BNXT_ULP_CLASS_HID_1cba3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [940] = { + .class_hid = BNXT_ULP_CLASS_HID_1eee3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [941] = { + .class_hid = BNXT_ULP_CLASS_HID_d3b7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [942] = { + .class_hid = BNXT_ULP_CLASS_HID_f6f7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [943] = { + .class_hid = BNXT_ULP_CLASS_HID_d937, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [944] = { + .class_hid = BNXT_ULP_CLASS_HID_fc77, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [945] = { + .class_hid = BNXT_ULP_CLASS_HID_cf7b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [946] = { + .class_hid = BNXT_ULP_CLASS_HID_f1bb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [947] = { + .class_hid = BNXT_ULP_CLASS_HID_d4fb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [948] = { + .class_hid = BNXT_ULP_CLASS_HID_f73b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [949] = { + .class_hid = BNXT_ULP_CLASS_HID_1882f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [950] = { + .class_hid = BNXT_ULP_CLASS_HID_1ab6f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [951] = { + .class_hid = BNXT_ULP_CLASS_HID_1cdaf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [952] = { + .class_hid = BNXT_ULP_CLASS_HID_1f0ef, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [953] = { + .class_hid = BNXT_ULP_CLASS_HID_18d7b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [954] = { + .class_hid = BNXT_ULP_CLASS_HID_1afbb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [955] = { + .class_hid = BNXT_ULP_CLASS_HID_1d2fb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [956] = { + .class_hid = BNXT_ULP_CLASS_HID_1f53b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [957] = { + .class_hid = BNXT_ULP_CLASS_HID_9a8f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [958] = { + .class_hid = BNXT_ULP_CLASS_HID_bdcf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [959] = { + .class_hid = BNXT_ULP_CLASS_HID_e00f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [960] = { + .class_hid = BNXT_ULP_CLASS_HID_e34f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [961] = { + .class_hid = BNXT_ULP_CLASS_HID_95b3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [962] = { + .class_hid = BNXT_ULP_CLASS_HID_b8f3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [963] = { + .class_hid = BNXT_ULP_CLASS_HID_db33, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [964] = { + .class_hid = BNXT_ULP_CLASS_HID_fe73, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [965] = { + .class_hid = BNXT_ULP_CLASS_HID_1abb3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [966] = { + .class_hid = BNXT_ULP_CLASS_HID_1aef3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [967] = { + .class_hid = BNXT_ULP_CLASS_HID_1f133, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [968] = { + .class_hid = BNXT_ULP_CLASS_HID_1f473, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [969] = { + .class_hid = BNXT_ULP_CLASS_HID_1b08f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [970] = { + .class_hid = BNXT_ULP_CLASS_HID_1b3cf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [971] = { + .class_hid = BNXT_ULP_CLASS_HID_1f60f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [972] = { + .class_hid = BNXT_ULP_CLASS_HID_1f94f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [973] = { + .class_hid = BNXT_ULP_CLASS_HID_be13, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [974] = { + .class_hid = BNXT_ULP_CLASS_HID_e153, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [975] = { + .class_hid = BNXT_ULP_CLASS_HID_c393, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [976] = { + .class_hid = BNXT_ULP_CLASS_HID_e6d3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [977] = { + .class_hid = BNXT_ULP_CLASS_HID_b9c7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [978] = { + .class_hid = BNXT_ULP_CLASS_HID_bc07, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [979] = { + .class_hid = BNXT_ULP_CLASS_HID_ff47, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [980] = { + .class_hid = BNXT_ULP_CLASS_HID_e187, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [981] = { + .class_hid = BNXT_ULP_CLASS_HID_1cfc7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [982] = { + .class_hid = BNXT_ULP_CLASS_HID_1f207, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [983] = { + .class_hid = BNXT_ULP_CLASS_HID_1d547, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [984] = { + .class_hid = BNXT_ULP_CLASS_HID_1f787, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [985] = { + .class_hid = BNXT_ULP_CLASS_HID_1d413, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [986] = { + .class_hid = BNXT_ULP_CLASS_HID_1f753, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [987] = { + .class_hid = BNXT_ULP_CLASS_HID_1d993, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [988] = { + .class_hid = BNXT_ULP_CLASS_HID_1fcd3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [989] = { + .class_hid = BNXT_ULP_CLASS_HID_aa67, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [990] = { + .class_hid = BNXT_ULP_CLASS_HID_aca7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [991] = { + .class_hid = BNXT_ULP_CLASS_HID_efe7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [992] = { + .class_hid = BNXT_ULP_CLASS_HID_f227, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [993] = { + .class_hid = BNXT_ULP_CLASS_HID_a52b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [994] = { + .class_hid = BNXT_ULP_CLASS_HID_a86b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [995] = { + .class_hid = BNXT_ULP_CLASS_HID_eaab, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [996] = { + .class_hid = BNXT_ULP_CLASS_HID_edeb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [997] = { + .class_hid = BNXT_ULP_CLASS_HID_1bb2b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [998] = { + .class_hid = BNXT_ULP_CLASS_HID_1be6b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [999] = { + .class_hid = BNXT_ULP_CLASS_HID_1c0ab, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1000] = { + .class_hid = BNXT_ULP_CLASS_HID_1e3eb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1001] = { + .class_hid = BNXT_ULP_CLASS_HID_1c067, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1002] = { + .class_hid = BNXT_ULP_CLASS_HID_1e2a7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1003] = { + .class_hid = BNXT_ULP_CLASS_HID_1c5e7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1004] = { + .class_hid = BNXT_ULP_CLASS_HID_1e827, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1005] = { + .class_hid = BNXT_ULP_CLASS_HID_cd8b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1006] = { + .class_hid = BNXT_ULP_CLASS_HID_f0cb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1007] = { + .class_hid = BNXT_ULP_CLASS_HID_d30b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1008] = { + .class_hid = BNXT_ULP_CLASS_HID_f64b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1009] = { + .class_hid = BNXT_ULP_CLASS_HID_c8bf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1010] = { + .class_hid = BNXT_ULP_CLASS_HID_ebff, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1011] = { + .class_hid = BNXT_ULP_CLASS_HID_ce3f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1012] = { + .class_hid = BNXT_ULP_CLASS_HID_f17f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1013] = { + .class_hid = BNXT_ULP_CLASS_HID_18263, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1014] = { + .class_hid = BNXT_ULP_CLASS_HID_1a4a3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1015] = { + .class_hid = BNXT_ULP_CLASS_HID_1c7e3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1016] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea23, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1017] = { + .class_hid = BNXT_ULP_CLASS_HID_186bf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1018] = { + .class_hid = BNXT_ULP_CLASS_HID_1a9ff, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1019] = { + .class_hid = BNXT_ULP_CLASS_HID_1cc3f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1020] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef7f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1021] = { + .class_hid = BNXT_ULP_CLASS_HID_94c3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1022] = { + .class_hid = BNXT_ULP_CLASS_HID_b703, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 108, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1023] = { + .class_hid = BNXT_ULP_CLASS_HID_da43, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 109, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1024] = { + .class_hid = BNXT_ULP_CLASS_HID_fc83, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 110, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1025] = { + .class_hid = BNXT_ULP_CLASS_HID_8ff7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 111, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1026] = { + .class_hid = BNXT_ULP_CLASS_HID_b237, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 111, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1027] = { + .class_hid = BNXT_ULP_CLASS_HID_d577, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 111, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1028] = { + .class_hid = BNXT_ULP_CLASS_HID_f7b7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 111, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1029] = { + .class_hid = BNXT_ULP_CLASS_HID_1a5f7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 111, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1030] = { + .class_hid = BNXT_ULP_CLASS_HID_1a837, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 111, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1031] = { + .class_hid = BNXT_ULP_CLASS_HID_1eb77, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 112, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1032] = { + .class_hid = BNXT_ULP_CLASS_HID_1edb7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 113, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1033] = { + .class_hid = BNXT_ULP_CLASS_HID_1aac3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1034] = { + .class_hid = BNXT_ULP_CLASS_HID_1ad03, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1035] = { + .class_hid = BNXT_ULP_CLASS_HID_1f043, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1036] = { + .class_hid = BNXT_ULP_CLASS_HID_1f283, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1037] = { + .class_hid = BNXT_ULP_CLASS_HID_b857, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1038] = { + .class_hid = BNXT_ULP_CLASS_HID_ba97, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1039] = { + .class_hid = BNXT_ULP_CLASS_HID_fdd7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1040] = { + .class_hid = BNXT_ULP_CLASS_HID_e017, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1041] = { + .class_hid = BNXT_ULP_CLASS_HID_b31b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1042] = { + .class_hid = BNXT_ULP_CLASS_HID_b65b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1043] = { + .class_hid = BNXT_ULP_CLASS_HID_f89b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1044] = { + .class_hid = BNXT_ULP_CLASS_HID_fbdb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1045] = { + .class_hid = BNXT_ULP_CLASS_HID_1c91b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1046] = { + .class_hid = BNXT_ULP_CLASS_HID_1ec5b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1047] = { + .class_hid = BNXT_ULP_CLASS_HID_1ce9b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1048] = { + .class_hid = BNXT_ULP_CLASS_HID_1f1db, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1049] = { + .class_hid = BNXT_ULP_CLASS_HID_1ce57, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1050] = { + .class_hid = BNXT_ULP_CLASS_HID_1f097, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1051] = { + .class_hid = BNXT_ULP_CLASS_HID_1d3d7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1052] = { + .class_hid = BNXT_ULP_CLASS_HID_1f617, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1053] = { + .class_hid = BNXT_ULP_CLASS_HID_a3bb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1054] = { + .class_hid = BNXT_ULP_CLASS_HID_a6fb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1055] = { + .class_hid = BNXT_ULP_CLASS_HID_e93b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1056] = { + .class_hid = BNXT_ULP_CLASS_HID_ec7b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1057] = { + .class_hid = BNXT_ULP_CLASS_HID_9f6f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1058] = { + .class_hid = BNXT_ULP_CLASS_HID_a1af, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1059] = { + .class_hid = BNXT_ULP_CLASS_HID_e4ef, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1060] = { + .class_hid = BNXT_ULP_CLASS_HID_e72f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1061] = { + .class_hid = BNXT_ULP_CLASS_HID_1b56f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1062] = { + .class_hid = BNXT_ULP_CLASS_HID_1b7af, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1063] = { + .class_hid = BNXT_ULP_CLASS_HID_1faef, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1064] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd2f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1065] = { + .class_hid = BNXT_ULP_CLASS_HID_1b9bb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1066] = { + .class_hid = BNXT_ULP_CLASS_HID_1bcfb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1067] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff3b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1068] = { + .class_hid = BNXT_ULP_CLASS_HID_1e27b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1069] = { + .class_hid = BNXT_ULP_CLASS_HID_c7cf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1070] = { + .class_hid = BNXT_ULP_CLASS_HID_ea0f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1071] = { + .class_hid = BNXT_ULP_CLASS_HID_cd4f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1072] = { + .class_hid = BNXT_ULP_CLASS_HID_ef8f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1073] = { + .class_hid = BNXT_ULP_CLASS_HID_c2f3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1074] = { + .class_hid = BNXT_ULP_CLASS_HID_e533, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1075] = { + .class_hid = BNXT_ULP_CLASS_HID_c873, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1076] = { + .class_hid = BNXT_ULP_CLASS_HID_eab3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1077] = { + .class_hid = BNXT_ULP_CLASS_HID_1d8f3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1078] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb33, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1079] = { + .class_hid = BNXT_ULP_CLASS_HID_1c127, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1080] = { + .class_hid = BNXT_ULP_CLASS_HID_1e467, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1081] = { + .class_hid = BNXT_ULP_CLASS_HID_180f3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1082] = { + .class_hid = BNXT_ULP_CLASS_HID_1a333, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1083] = { + .class_hid = BNXT_ULP_CLASS_HID_1c673, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1084] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8b3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1085] = { + .class_hid = BNXT_ULP_CLASS_HID_8e07, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1086] = { + .class_hid = BNXT_ULP_CLASS_HID_b147, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1087] = { + .class_hid = BNXT_ULP_CLASS_HID_d387, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1088] = { + .class_hid = BNXT_ULP_CLASS_HID_f6c7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1089] = { + .class_hid = BNXT_ULP_CLASS_HID_89cb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1090] = { + .class_hid = BNXT_ULP_CLASS_HID_ac0b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1091] = { + .class_hid = BNXT_ULP_CLASS_HID_cf4b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1092] = { + .class_hid = BNXT_ULP_CLASS_HID_f18b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1093] = { + .class_hid = BNXT_ULP_CLASS_HID_19fcb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1094] = { + .class_hid = BNXT_ULP_CLASS_HID_1a20b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1095] = { + .class_hid = BNXT_ULP_CLASS_HID_1e54b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1096] = { + .class_hid = BNXT_ULP_CLASS_HID_1e78b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1097] = { + .class_hid = BNXT_ULP_CLASS_HID_1a407, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1098] = { + .class_hid = BNXT_ULP_CLASS_HID_1a747, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1099] = { + .class_hid = BNXT_ULP_CLASS_HID_1e987, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1100] = { + .class_hid = BNXT_ULP_CLASS_HID_1ecc7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1101] = { + .class_hid = BNXT_ULP_CLASS_HID_b1ab, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1102] = { + .class_hid = BNXT_ULP_CLASS_HID_b4eb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1103] = { + .class_hid = BNXT_ULP_CLASS_HID_f72b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1104] = { + .class_hid = BNXT_ULP_CLASS_HID_fa6b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1105] = { + .class_hid = BNXT_ULP_CLASS_HID_ad5f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1106] = { + .class_hid = BNXT_ULP_CLASS_HID_af9f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1107] = { + .class_hid = BNXT_ULP_CLASS_HID_f2df, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1108] = { + .class_hid = BNXT_ULP_CLASS_HID_f51f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1109] = { + .class_hid = BNXT_ULP_CLASS_HID_1c35f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1110] = { + .class_hid = BNXT_ULP_CLASS_HID_1e59f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1111] = { + .class_hid = BNXT_ULP_CLASS_HID_1c8df, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1112] = { + .class_hid = BNXT_ULP_CLASS_HID_1eb1f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1113] = { + .class_hid = BNXT_ULP_CLASS_HID_1c7ab, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1114] = { + .class_hid = BNXT_ULP_CLASS_HID_1eaeb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1115] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd2b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1116] = { + .class_hid = BNXT_ULP_CLASS_HID_1f06b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1117] = { + .class_hid = BNXT_ULP_CLASS_HID_9177, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1118] = { + .class_hid = BNXT_ULP_CLASS_HID_b3b7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1119] = { + .class_hid = BNXT_ULP_CLASS_HID_d6f7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1120] = { + .class_hid = BNXT_ULP_CLASS_HID_f937, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1121] = { + .class_hid = BNXT_ULP_CLASS_HID_8c3b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1122] = { + .class_hid = BNXT_ULP_CLASS_HID_af7b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1123] = { + .class_hid = BNXT_ULP_CLASS_HID_d1bb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1124] = { + .class_hid = BNXT_ULP_CLASS_HID_f4fb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1125] = { + .class_hid = BNXT_ULP_CLASS_HID_1a23b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1126] = { + .class_hid = BNXT_ULP_CLASS_HID_1a57b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1127] = { + .class_hid = BNXT_ULP_CLASS_HID_1e7bb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1128] = { + .class_hid = BNXT_ULP_CLASS_HID_1eafb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1129] = { + .class_hid = BNXT_ULP_CLASS_HID_1a777, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1130] = { + .class_hid = BNXT_ULP_CLASS_HID_1a9b7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1131] = { + .class_hid = BNXT_ULP_CLASS_HID_1ecf7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1132] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef37, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1133] = { + .class_hid = BNXT_ULP_CLASS_HID_b49b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1134] = { + .class_hid = BNXT_ULP_CLASS_HID_b7db, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1135] = { + .class_hid = BNXT_ULP_CLASS_HID_fa1b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1136] = { + .class_hid = BNXT_ULP_CLASS_HID_fd5b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1137] = { + .class_hid = BNXT_ULP_CLASS_HID_b04f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1138] = { + .class_hid = BNXT_ULP_CLASS_HID_b28f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1139] = { + .class_hid = BNXT_ULP_CLASS_HID_f5cf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1140] = { + .class_hid = BNXT_ULP_CLASS_HID_f80f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1141] = { + .class_hid = BNXT_ULP_CLASS_HID_1c64f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1142] = { + .class_hid = BNXT_ULP_CLASS_HID_1e88f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1143] = { + .class_hid = BNXT_ULP_CLASS_HID_1cbcf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1144] = { + .class_hid = BNXT_ULP_CLASS_HID_1ee0f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1145] = { + .class_hid = BNXT_ULP_CLASS_HID_1ca9b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1146] = { + .class_hid = BNXT_ULP_CLASS_HID_1eddb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1147] = { + .class_hid = BNXT_ULP_CLASS_HID_1d01b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1148] = { + .class_hid = BNXT_ULP_CLASS_HID_1f35b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1149] = { + .class_hid = BNXT_ULP_CLASS_HID_8b4b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1150] = { + .class_hid = BNXT_ULP_CLASS_HID_ad8b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1151] = { + .class_hid = BNXT_ULP_CLASS_HID_d0cb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1152] = { + .class_hid = BNXT_ULP_CLASS_HID_f30b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1153] = { + .class_hid = BNXT_ULP_CLASS_HID_867f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1154] = { + .class_hid = BNXT_ULP_CLASS_HID_a8bf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1155] = { + .class_hid = BNXT_ULP_CLASS_HID_cbff, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1156] = { + .class_hid = BNXT_ULP_CLASS_HID_ee3f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1157] = { + .class_hid = BNXT_ULP_CLASS_HID_19c7f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1158] = { + .class_hid = BNXT_ULP_CLASS_HID_1bebf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1159] = { + .class_hid = BNXT_ULP_CLASS_HID_1e1ff, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1160] = { + .class_hid = BNXT_ULP_CLASS_HID_1e43f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1161] = { + .class_hid = BNXT_ULP_CLASS_HID_1a14b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1162] = { + .class_hid = BNXT_ULP_CLASS_HID_1a38b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1163] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6cb, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1164] = { + .class_hid = BNXT_ULP_CLASS_HID_1e90b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1165] = { + .class_hid = BNXT_ULP_CLASS_HID_aedf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1166] = { + .class_hid = BNXT_ULP_CLASS_HID_b11f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1167] = { + .class_hid = BNXT_ULP_CLASS_HID_f45f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1168] = { + .class_hid = BNXT_ULP_CLASS_HID_f69f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1169] = { + .class_hid = BNXT_ULP_CLASS_HID_a983, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1170] = { + .class_hid = BNXT_ULP_CLASS_HID_acc3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1171] = { + .class_hid = BNXT_ULP_CLASS_HID_ef03, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1172] = { + .class_hid = BNXT_ULP_CLASS_HID_f243, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1173] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf83, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1174] = { + .class_hid = BNXT_ULP_CLASS_HID_1e2c3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1175] = { + .class_hid = BNXT_ULP_CLASS_HID_1c503, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1176] = { + .class_hid = BNXT_ULP_CLASS_HID_1e843, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1177] = { + .class_hid = BNXT_ULP_CLASS_HID_1c4df, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1178] = { + .class_hid = BNXT_ULP_CLASS_HID_1e71f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1179] = { + .class_hid = BNXT_ULP_CLASS_HID_1ca5f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1180] = { + .class_hid = BNXT_ULP_CLASS_HID_1ec9f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1181] = { + .class_hid = BNXT_ULP_CLASS_HID_2523, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1182] = { + .class_hid = BNXT_ULP_CLASS_HID_2bef, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1183] = { + .class_hid = BNXT_ULP_CLASS_HID_4f73, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1184] = { + .class_hid = BNXT_ULP_CLASS_HID_164b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1185] = { + .class_hid = BNXT_ULP_CLASS_HID_39df, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1186] = { + .class_hid = BNXT_ULP_CLASS_HID_48b7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1187] = { + .class_hid = BNXT_ULP_CLASS_HID_0f8f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1188] = { + .class_hid = BNXT_ULP_CLASS_HID_3313, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1189] = { + .class_hid = BNXT_ULP_CLASS_HID_257b7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1190] = { + .class_hid = BNXT_ULP_CLASS_HID_24467, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1191] = { + .class_hid = BNXT_ULP_CLASS_HID_23fbb, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1192] = { + .class_hid = BNXT_ULP_CLASS_HID_252cb, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1193] = { + .class_hid = BNXT_ULP_CLASS_HID_21e7f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1194] = { + .class_hid = BNXT_ULP_CLASS_HID_20b2f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1195] = { + .class_hid = BNXT_ULP_CLASS_HID_20663, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1196] = { + .class_hid = BNXT_ULP_CLASS_HID_219b3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1197] = { + .class_hid = BNXT_ULP_CLASS_HID_24213, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 114, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1198] = { + .class_hid = BNXT_ULP_CLASS_HID_22ec3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 115, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1199] = { + .class_hid = BNXT_ULP_CLASS_HID_22a17, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 115, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1200] = { + .class_hid = BNXT_ULP_CLASS_HID_23d27, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1201] = { + .class_hid = BNXT_ULP_CLASS_HID_208db, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1202] = { + .class_hid = BNXT_ULP_CLASS_HID_25277, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1203] = { + .class_hid = BNXT_ULP_CLASS_HID_24d8b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1204] = { + .class_hid = BNXT_ULP_CLASS_HID_203ef, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1205] = { + .class_hid = BNXT_ULP_CLASS_HID_2517b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1206] = { + .class_hid = BNXT_ULP_CLASS_HID_23e2b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1207] = { + .class_hid = BNXT_ULP_CLASS_HID_2397f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1208] = { + .class_hid = BNXT_ULP_CLASS_HID_24c8f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1209] = { + .class_hid = BNXT_ULP_CLASS_HID_21823, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1210] = { + .class_hid = BNXT_ULP_CLASS_HID_20513, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1211] = { + .class_hid = BNXT_ULP_CLASS_HID_20027, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1212] = { + .class_hid = BNXT_ULP_CLASS_HID_21377, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1213] = { + .class_hid = BNXT_ULP_CLASS_HID_23bd7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1214] = { + .class_hid = BNXT_ULP_CLASS_HID_22887, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1215] = { + .class_hid = BNXT_ULP_CLASS_HID_223db, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1216] = { + .class_hid = BNXT_ULP_CLASS_HID_236eb, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1217] = { + .class_hid = BNXT_ULP_CLASS_HID_2029f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1218] = { + .class_hid = BNXT_ULP_CLASS_HID_24c3b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1219] = { + .class_hid = BNXT_ULP_CLASS_HID_2474f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1220] = { + .class_hid = BNXT_ULP_CLASS_HID_25a9f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1221] = { + .class_hid = BNXT_ULP_CLASS_HID_24b3f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1222] = { + .class_hid = BNXT_ULP_CLASS_HID_237ef, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1223] = { + .class_hid = BNXT_ULP_CLASS_HID_23323, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1224] = { + .class_hid = BNXT_ULP_CLASS_HID_24673, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1225] = { + .class_hid = BNXT_ULP_CLASS_HID_211e7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1226] = { + .class_hid = BNXT_ULP_CLASS_HID_25b83, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1227] = { + .class_hid = BNXT_ULP_CLASS_HID_256d7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1228] = { + .class_hid = BNXT_ULP_CLASS_HID_20d3b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1229] = { + .class_hid = BNXT_ULP_CLASS_HID_2359b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1230] = { + .class_hid = BNXT_ULP_CLASS_HID_2224b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 117, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1231] = { + .class_hid = BNXT_ULP_CLASS_HID_21d9f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 117, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1232] = { + .class_hid = BNXT_ULP_CLASS_HID_230af, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1233] = { + .class_hid = BNXT_ULP_CLASS_HID_2590f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1234] = { + .class_hid = BNXT_ULP_CLASS_HID_245ff, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1235] = { + .class_hid = BNXT_ULP_CLASS_HID_24133, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1236] = { + .class_hid = BNXT_ULP_CLASS_HID_25443, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1237] = { + .class_hid = BNXT_ULP_CLASS_HID_244e3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1238] = { + .class_hid = BNXT_ULP_CLASS_HID_231d3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1239] = { + .class_hid = BNXT_ULP_CLASS_HID_22ce7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1240] = { + .class_hid = BNXT_ULP_CLASS_HID_24037, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1241] = { + .class_hid = BNXT_ULP_CLASS_HID_20bab, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1242] = { + .class_hid = BNXT_ULP_CLASS_HID_25547, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1243] = { + .class_hid = BNXT_ULP_CLASS_HID_2509b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1244] = { + .class_hid = BNXT_ULP_CLASS_HID_206ff, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1245] = { + .class_hid = BNXT_ULP_CLASS_HID_22f5f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1246] = { + .class_hid = BNXT_ULP_CLASS_HID_21c0f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1247] = { + .class_hid = BNXT_ULP_CLASS_HID_21743, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1248] = { + .class_hid = BNXT_ULP_CLASS_HID_22a93, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1249] = { + .class_hid = BNXT_ULP_CLASS_HID_252f3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1250] = { + .class_hid = BNXT_ULP_CLASS_HID_23fa3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1251] = { + .class_hid = BNXT_ULP_CLASS_HID_23af7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1252] = { + .class_hid = BNXT_ULP_CLASS_HID_24e07, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1253] = { + .class_hid = BNXT_ULP_CLASS_HID_2322f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1254] = { + .class_hid = BNXT_ULP_CLASS_HID_21f1f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1255] = { + .class_hid = BNXT_ULP_CLASS_HID_21a53, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1256] = { + .class_hid = BNXT_ULP_CLASS_HID_22d63, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1257] = { + .class_hid = BNXT_ULP_CLASS_HID_255c3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1258] = { + .class_hid = BNXT_ULP_CLASS_HID_242b3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1259] = { + .class_hid = BNXT_ULP_CLASS_HID_23dc7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1260] = { + .class_hid = BNXT_ULP_CLASS_HID_25117, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1261] = { + .class_hid = BNXT_ULP_CLASS_HID_22c13, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1262] = { + .class_hid = BNXT_ULP_CLASS_HID_218c3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1263] = { + .class_hid = BNXT_ULP_CLASS_HID_21417, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1264] = { + .class_hid = BNXT_ULP_CLASS_HID_22727, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1265] = { + .class_hid = BNXT_ULP_CLASS_HID_24f87, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1266] = { + .class_hid = BNXT_ULP_CLASS_HID_23c77, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1267] = { + .class_hid = BNXT_ULP_CLASS_HID_2378b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1268] = { + .class_hid = BNXT_ULP_CLASS_HID_24adb, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1269] = { + .class_hid = BNXT_ULP_CLASS_HID_257b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1270] = { + .class_hid = BNXT_ULP_CLASS_HID_2bb7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1271] = { + .class_hid = BNXT_ULP_CLASS_HID_4f2b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1272] = { + .class_hid = BNXT_ULP_CLASS_HID_1613, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1273] = { + .class_hid = BNXT_ULP_CLASS_HID_3987, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1274] = { + .class_hid = BNXT_ULP_CLASS_HID_48ef, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1275] = { + .class_hid = BNXT_ULP_CLASS_HID_0fd7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1276] = { + .class_hid = BNXT_ULP_CLASS_HID_334b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1277] = { + .class_hid = BNXT_ULP_CLASS_HID_25797, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1278] = { + .class_hid = BNXT_ULP_CLASS_HID_285eb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1279] = { + .class_hid = BNXT_ULP_CLASS_HID_310eb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1280] = { + .class_hid = BNXT_ULP_CLASS_HID_39beb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1281] = { + .class_hid = BNXT_ULP_CLASS_HID_24447, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1282] = { + .class_hid = BNXT_ULP_CLASS_HID_2cf47, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1283] = { + .class_hid = BNXT_ULP_CLASS_HID_35a47, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1284] = { + .class_hid = BNXT_ULP_CLASS_HID_3889b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1285] = { + .class_hid = BNXT_ULP_CLASS_HID_23f9b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1286] = { + .class_hid = BNXT_ULP_CLASS_HID_2ca9b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1287] = { + .class_hid = BNXT_ULP_CLASS_HID_3559b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1288] = { + .class_hid = BNXT_ULP_CLASS_HID_383ef, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1289] = { + .class_hid = BNXT_ULP_CLASS_HID_252eb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1290] = { + .class_hid = BNXT_ULP_CLASS_HID_2813f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1291] = { + .class_hid = BNXT_ULP_CLASS_HID_30c3f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1292] = { + .class_hid = BNXT_ULP_CLASS_HID_3973f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1293] = { + .class_hid = BNXT_ULP_CLASS_HID_21e5f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1294] = { + .class_hid = BNXT_ULP_CLASS_HID_2a95f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1295] = { + .class_hid = BNXT_ULP_CLASS_HID_3345f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1296] = { + .class_hid = BNXT_ULP_CLASS_HID_3bf5f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1297] = { + .class_hid = BNXT_ULP_CLASS_HID_20b0f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1298] = { + .class_hid = BNXT_ULP_CLASS_HID_2960f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1299] = { + .class_hid = BNXT_ULP_CLASS_HID_3210f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1300] = { + .class_hid = BNXT_ULP_CLASS_HID_3ac0f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1301] = { + .class_hid = BNXT_ULP_CLASS_HID_20643, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1302] = { + .class_hid = BNXT_ULP_CLASS_HID_29143, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1303] = { + .class_hid = BNXT_ULP_CLASS_HID_31c43, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1304] = { + .class_hid = BNXT_ULP_CLASS_HID_3a743, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1305] = { + .class_hid = BNXT_ULP_CLASS_HID_21993, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1306] = { + .class_hid = BNXT_ULP_CLASS_HID_2a493, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1307] = { + .class_hid = BNXT_ULP_CLASS_HID_32f93, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1308] = { + .class_hid = BNXT_ULP_CLASS_HID_3ba93, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1309] = { + .class_hid = BNXT_ULP_CLASS_HID_24233, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1310] = { + .class_hid = BNXT_ULP_CLASS_HID_2cd33, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 118, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1311] = { + .class_hid = BNXT_ULP_CLASS_HID_35833, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 119, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1312] = { + .class_hid = BNXT_ULP_CLASS_HID_38607, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 120, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1313] = { + .class_hid = BNXT_ULP_CLASS_HID_22ee3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 121, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1314] = { + .class_hid = BNXT_ULP_CLASS_HID_2b9e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 121, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1315] = { + .class_hid = BNXT_ULP_CLASS_HID_344e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 121, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1316] = { + .class_hid = BNXT_ULP_CLASS_HID_3cfe3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 121, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1317] = { + .class_hid = BNXT_ULP_CLASS_HID_22a37, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 121, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1318] = { + .class_hid = BNXT_ULP_CLASS_HID_2b537, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 121, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1319] = { + .class_hid = BNXT_ULP_CLASS_HID_34037, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 122, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1320] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb37, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 123, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1321] = { + .class_hid = BNXT_ULP_CLASS_HID_23d07, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1322] = { + .class_hid = BNXT_ULP_CLASS_HID_2c807, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1323] = { + .class_hid = BNXT_ULP_CLASS_HID_35307, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1324] = { + .class_hid = BNXT_ULP_CLASS_HID_3815b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1325] = { + .class_hid = BNXT_ULP_CLASS_HID_208fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1326] = { + .class_hid = BNXT_ULP_CLASS_HID_293fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1327] = { + .class_hid = BNXT_ULP_CLASS_HID_31efb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1328] = { + .class_hid = BNXT_ULP_CLASS_HID_3a9fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1329] = { + .class_hid = BNXT_ULP_CLASS_HID_25257, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1330] = { + .class_hid = BNXT_ULP_CLASS_HID_280ab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1331] = { + .class_hid = BNXT_ULP_CLASS_HID_30bab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1332] = { + .class_hid = BNXT_ULP_CLASS_HID_396ab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1333] = { + .class_hid = BNXT_ULP_CLASS_HID_24dab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1334] = { + .class_hid = BNXT_ULP_CLASS_HID_2d8ab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1335] = { + .class_hid = BNXT_ULP_CLASS_HID_306ff, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1336] = { + .class_hid = BNXT_ULP_CLASS_HID_391ff, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1337] = { + .class_hid = BNXT_ULP_CLASS_HID_203cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1338] = { + .class_hid = BNXT_ULP_CLASS_HID_28ecf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1339] = { + .class_hid = BNXT_ULP_CLASS_HID_319cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1340] = { + .class_hid = BNXT_ULP_CLASS_HID_3a4cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1341] = { + .class_hid = BNXT_ULP_CLASS_HID_2515b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1342] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc5b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1343] = { + .class_hid = BNXT_ULP_CLASS_HID_30aaf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1344] = { + .class_hid = BNXT_ULP_CLASS_HID_395af, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1345] = { + .class_hid = BNXT_ULP_CLASS_HID_23e0b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1346] = { + .class_hid = BNXT_ULP_CLASS_HID_2c90b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1347] = { + .class_hid = BNXT_ULP_CLASS_HID_3540b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1348] = { + .class_hid = BNXT_ULP_CLASS_HID_3825f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1349] = { + .class_hid = BNXT_ULP_CLASS_HID_2395f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1350] = { + .class_hid = BNXT_ULP_CLASS_HID_2c45f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1351] = { + .class_hid = BNXT_ULP_CLASS_HID_34f5f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1352] = { + .class_hid = BNXT_ULP_CLASS_HID_3da5f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1353] = { + .class_hid = BNXT_ULP_CLASS_HID_24caf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1354] = { + .class_hid = BNXT_ULP_CLASS_HID_2d7af, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1355] = { + .class_hid = BNXT_ULP_CLASS_HID_305e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1356] = { + .class_hid = BNXT_ULP_CLASS_HID_390e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1357] = { + .class_hid = BNXT_ULP_CLASS_HID_21803, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1358] = { + .class_hid = BNXT_ULP_CLASS_HID_2a303, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1359] = { + .class_hid = BNXT_ULP_CLASS_HID_32e03, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1360] = { + .class_hid = BNXT_ULP_CLASS_HID_3b903, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1361] = { + .class_hid = BNXT_ULP_CLASS_HID_20533, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1362] = { + .class_hid = BNXT_ULP_CLASS_HID_29033, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1363] = { + .class_hid = BNXT_ULP_CLASS_HID_31b33, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1364] = { + .class_hid = BNXT_ULP_CLASS_HID_3a633, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1365] = { + .class_hid = BNXT_ULP_CLASS_HID_20007, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1366] = { + .class_hid = BNXT_ULP_CLASS_HID_28b07, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1367] = { + .class_hid = BNXT_ULP_CLASS_HID_31607, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1368] = { + .class_hid = BNXT_ULP_CLASS_HID_3a107, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1369] = { + .class_hid = BNXT_ULP_CLASS_HID_21357, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1370] = { + .class_hid = BNXT_ULP_CLASS_HID_29e57, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1371] = { + .class_hid = BNXT_ULP_CLASS_HID_32957, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1372] = { + .class_hid = BNXT_ULP_CLASS_HID_3b457, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1373] = { + .class_hid = BNXT_ULP_CLASS_HID_23bf7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1374] = { + .class_hid = BNXT_ULP_CLASS_HID_2c6f7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1375] = { + .class_hid = BNXT_ULP_CLASS_HID_351f7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1376] = { + .class_hid = BNXT_ULP_CLASS_HID_3dcf7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1377] = { + .class_hid = BNXT_ULP_CLASS_HID_228a7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1378] = { + .class_hid = BNXT_ULP_CLASS_HID_2b3a7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1379] = { + .class_hid = BNXT_ULP_CLASS_HID_33ea7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1380] = { + .class_hid = BNXT_ULP_CLASS_HID_3c9a7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1381] = { + .class_hid = BNXT_ULP_CLASS_HID_223fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1382] = { + .class_hid = BNXT_ULP_CLASS_HID_2aefb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1383] = { + .class_hid = BNXT_ULP_CLASS_HID_339fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1384] = { + .class_hid = BNXT_ULP_CLASS_HID_3c4fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1385] = { + .class_hid = BNXT_ULP_CLASS_HID_236cb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1386] = { + .class_hid = BNXT_ULP_CLASS_HID_2c1cb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1387] = { + .class_hid = BNXT_ULP_CLASS_HID_34ccb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1388] = { + .class_hid = BNXT_ULP_CLASS_HID_3d7cb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1389] = { + .class_hid = BNXT_ULP_CLASS_HID_202bf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1390] = { + .class_hid = BNXT_ULP_CLASS_HID_28dbf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1391] = { + .class_hid = BNXT_ULP_CLASS_HID_318bf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1392] = { + .class_hid = BNXT_ULP_CLASS_HID_3a3bf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1393] = { + .class_hid = BNXT_ULP_CLASS_HID_24c1b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1394] = { + .class_hid = BNXT_ULP_CLASS_HID_2d71b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1395] = { + .class_hid = BNXT_ULP_CLASS_HID_3056f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1396] = { + .class_hid = BNXT_ULP_CLASS_HID_3906f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1397] = { + .class_hid = BNXT_ULP_CLASS_HID_2476f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1398] = { + .class_hid = BNXT_ULP_CLASS_HID_2d26f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1399] = { + .class_hid = BNXT_ULP_CLASS_HID_300a3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1400] = { + .class_hid = BNXT_ULP_CLASS_HID_38ba3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1401] = { + .class_hid = BNXT_ULP_CLASS_HID_25abf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1402] = { + .class_hid = BNXT_ULP_CLASS_HID_288f3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1403] = { + .class_hid = BNXT_ULP_CLASS_HID_313f3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1404] = { + .class_hid = BNXT_ULP_CLASS_HID_39ef3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1405] = { + .class_hid = BNXT_ULP_CLASS_HID_24b1f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1406] = { + .class_hid = BNXT_ULP_CLASS_HID_2d61f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1407] = { + .class_hid = BNXT_ULP_CLASS_HID_30453, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1408] = { + .class_hid = BNXT_ULP_CLASS_HID_38f53, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1409] = { + .class_hid = BNXT_ULP_CLASS_HID_237cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1410] = { + .class_hid = BNXT_ULP_CLASS_HID_2c2cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1411] = { + .class_hid = BNXT_ULP_CLASS_HID_34dcf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1412] = { + .class_hid = BNXT_ULP_CLASS_HID_3d8cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1413] = { + .class_hid = BNXT_ULP_CLASS_HID_23303, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1414] = { + .class_hid = BNXT_ULP_CLASS_HID_2be03, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1415] = { + .class_hid = BNXT_ULP_CLASS_HID_34903, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1416] = { + .class_hid = BNXT_ULP_CLASS_HID_3d403, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1417] = { + .class_hid = BNXT_ULP_CLASS_HID_24653, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1418] = { + .class_hid = BNXT_ULP_CLASS_HID_2d153, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1419] = { + .class_hid = BNXT_ULP_CLASS_HID_35c53, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1420] = { + .class_hid = BNXT_ULP_CLASS_HID_38aa7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1421] = { + .class_hid = BNXT_ULP_CLASS_HID_211c7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1422] = { + .class_hid = BNXT_ULP_CLASS_HID_29cc7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1423] = { + .class_hid = BNXT_ULP_CLASS_HID_327c7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1424] = { + .class_hid = BNXT_ULP_CLASS_HID_3b2c7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1425] = { + .class_hid = BNXT_ULP_CLASS_HID_25ba3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1426] = { + .class_hid = BNXT_ULP_CLASS_HID_289f7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1427] = { + .class_hid = BNXT_ULP_CLASS_HID_314f7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1428] = { + .class_hid = BNXT_ULP_CLASS_HID_39ff7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1429] = { + .class_hid = BNXT_ULP_CLASS_HID_256f7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1430] = { + .class_hid = BNXT_ULP_CLASS_HID_284cb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1431] = { + .class_hid = BNXT_ULP_CLASS_HID_30fcb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1432] = { + .class_hid = BNXT_ULP_CLASS_HID_39acb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1433] = { + .class_hid = BNXT_ULP_CLASS_HID_20d1b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1434] = { + .class_hid = BNXT_ULP_CLASS_HID_2981b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1435] = { + .class_hid = BNXT_ULP_CLASS_HID_3231b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1436] = { + .class_hid = BNXT_ULP_CLASS_HID_3ae1b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1437] = { + .class_hid = BNXT_ULP_CLASS_HID_235bb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1438] = { + .class_hid = BNXT_ULP_CLASS_HID_2c0bb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 124, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1439] = { + .class_hid = BNXT_ULP_CLASS_HID_34bbb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 125, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1440] = { + .class_hid = BNXT_ULP_CLASS_HID_3d6bb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 126, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1441] = { + .class_hid = BNXT_ULP_CLASS_HID_2226b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 127, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1442] = { + .class_hid = BNXT_ULP_CLASS_HID_2ad6b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 127, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1443] = { + .class_hid = BNXT_ULP_CLASS_HID_3386b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 127, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1444] = { + .class_hid = BNXT_ULP_CLASS_HID_3c36b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 127, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1445] = { + .class_hid = BNXT_ULP_CLASS_HID_21dbf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 127, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1446] = { + .class_hid = BNXT_ULP_CLASS_HID_2a8bf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 127, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1447] = { + .class_hid = BNXT_ULP_CLASS_HID_333bf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 128, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1448] = { + .class_hid = BNXT_ULP_CLASS_HID_3bebf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 129, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1449] = { + .class_hid = BNXT_ULP_CLASS_HID_2308f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1450] = { + .class_hid = BNXT_ULP_CLASS_HID_2bb8f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1451] = { + .class_hid = BNXT_ULP_CLASS_HID_3468f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1452] = { + .class_hid = BNXT_ULP_CLASS_HID_3d18f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1453] = { + .class_hid = BNXT_ULP_CLASS_HID_2592f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1454] = { + .class_hid = BNXT_ULP_CLASS_HID_28763, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1455] = { + .class_hid = BNXT_ULP_CLASS_HID_31263, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1456] = { + .class_hid = BNXT_ULP_CLASS_HID_39d63, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1457] = { + .class_hid = BNXT_ULP_CLASS_HID_245df, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1458] = { + .class_hid = BNXT_ULP_CLASS_HID_2d0df, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1459] = { + .class_hid = BNXT_ULP_CLASS_HID_35bdf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1460] = { + .class_hid = BNXT_ULP_CLASS_HID_38a13, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1461] = { + .class_hid = BNXT_ULP_CLASS_HID_24113, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1462] = { + .class_hid = BNXT_ULP_CLASS_HID_2cc13, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1463] = { + .class_hid = BNXT_ULP_CLASS_HID_35713, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1464] = { + .class_hid = BNXT_ULP_CLASS_HID_38567, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1465] = { + .class_hid = BNXT_ULP_CLASS_HID_25463, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1466] = { + .class_hid = BNXT_ULP_CLASS_HID_282b7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1467] = { + .class_hid = BNXT_ULP_CLASS_HID_30db7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1468] = { + .class_hid = BNXT_ULP_CLASS_HID_398b7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1469] = { + .class_hid = BNXT_ULP_CLASS_HID_244c3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1470] = { + .class_hid = BNXT_ULP_CLASS_HID_2cfc3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1471] = { + .class_hid = BNXT_ULP_CLASS_HID_35ac3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1472] = { + .class_hid = BNXT_ULP_CLASS_HID_38917, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1473] = { + .class_hid = BNXT_ULP_CLASS_HID_231f3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1474] = { + .class_hid = BNXT_ULP_CLASS_HID_2bcf3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1475] = { + .class_hid = BNXT_ULP_CLASS_HID_347f3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1476] = { + .class_hid = BNXT_ULP_CLASS_HID_3d2f3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1477] = { + .class_hid = BNXT_ULP_CLASS_HID_22cc7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1478] = { + .class_hid = BNXT_ULP_CLASS_HID_2b7c7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1479] = { + .class_hid = BNXT_ULP_CLASS_HID_342c7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1480] = { + .class_hid = BNXT_ULP_CLASS_HID_3cdc7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1481] = { + .class_hid = BNXT_ULP_CLASS_HID_24017, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1482] = { + .class_hid = BNXT_ULP_CLASS_HID_2cb17, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1483] = { + .class_hid = BNXT_ULP_CLASS_HID_35617, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1484] = { + .class_hid = BNXT_ULP_CLASS_HID_3846b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1485] = { + .class_hid = BNXT_ULP_CLASS_HID_20b8b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1486] = { + .class_hid = BNXT_ULP_CLASS_HID_2968b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1487] = { + .class_hid = BNXT_ULP_CLASS_HID_3218b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1488] = { + .class_hid = BNXT_ULP_CLASS_HID_3ac8b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1489] = { + .class_hid = BNXT_ULP_CLASS_HID_25567, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1490] = { + .class_hid = BNXT_ULP_CLASS_HID_283bb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1491] = { + .class_hid = BNXT_ULP_CLASS_HID_30ebb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1492] = { + .class_hid = BNXT_ULP_CLASS_HID_399bb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1493] = { + .class_hid = BNXT_ULP_CLASS_HID_250bb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1494] = { + .class_hid = BNXT_ULP_CLASS_HID_2dbbb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1495] = { + .class_hid = BNXT_ULP_CLASS_HID_3098f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1496] = { + .class_hid = BNXT_ULP_CLASS_HID_3948f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1497] = { + .class_hid = BNXT_ULP_CLASS_HID_206df, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1498] = { + .class_hid = BNXT_ULP_CLASS_HID_291df, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1499] = { + .class_hid = BNXT_ULP_CLASS_HID_31cdf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1500] = { + .class_hid = BNXT_ULP_CLASS_HID_3a7df, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1501] = { + .class_hid = BNXT_ULP_CLASS_HID_22f7f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1502] = { + .class_hid = BNXT_ULP_CLASS_HID_2ba7f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1503] = { + .class_hid = BNXT_ULP_CLASS_HID_3457f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1504] = { + .class_hid = BNXT_ULP_CLASS_HID_3d07f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1505] = { + .class_hid = BNXT_ULP_CLASS_HID_21c2f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1506] = { + .class_hid = BNXT_ULP_CLASS_HID_2a72f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1507] = { + .class_hid = BNXT_ULP_CLASS_HID_3322f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1508] = { + .class_hid = BNXT_ULP_CLASS_HID_3bd2f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1509] = { + .class_hid = BNXT_ULP_CLASS_HID_21763, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1510] = { + .class_hid = BNXT_ULP_CLASS_HID_2a263, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1511] = { + .class_hid = BNXT_ULP_CLASS_HID_32d63, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1512] = { + .class_hid = BNXT_ULP_CLASS_HID_3b863, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1513] = { + .class_hid = BNXT_ULP_CLASS_HID_22ab3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1514] = { + .class_hid = BNXT_ULP_CLASS_HID_2b5b3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1515] = { + .class_hid = BNXT_ULP_CLASS_HID_340b3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1516] = { + .class_hid = BNXT_ULP_CLASS_HID_3cbb3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1517] = { + .class_hid = BNXT_ULP_CLASS_HID_252d3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1518] = { + .class_hid = BNXT_ULP_CLASS_HID_28127, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1519] = { + .class_hid = BNXT_ULP_CLASS_HID_30c27, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1520] = { + .class_hid = BNXT_ULP_CLASS_HID_39727, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1521] = { + .class_hid = BNXT_ULP_CLASS_HID_23f83, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1522] = { + .class_hid = BNXT_ULP_CLASS_HID_2ca83, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1523] = { + .class_hid = BNXT_ULP_CLASS_HID_35583, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1524] = { + .class_hid = BNXT_ULP_CLASS_HID_383d7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1525] = { + .class_hid = BNXT_ULP_CLASS_HID_23ad7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1526] = { + .class_hid = BNXT_ULP_CLASS_HID_2c5d7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1527] = { + .class_hid = BNXT_ULP_CLASS_HID_350d7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1528] = { + .class_hid = BNXT_ULP_CLASS_HID_3dbd7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1529] = { + .class_hid = BNXT_ULP_CLASS_HID_24e27, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1530] = { + .class_hid = BNXT_ULP_CLASS_HID_2d927, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1531] = { + .class_hid = BNXT_ULP_CLASS_HID_3077b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1532] = { + .class_hid = BNXT_ULP_CLASS_HID_3927b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1533] = { + .class_hid = BNXT_ULP_CLASS_HID_2320f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1534] = { + .class_hid = BNXT_ULP_CLASS_HID_2bd0f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1535] = { + .class_hid = BNXT_ULP_CLASS_HID_3480f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1536] = { + .class_hid = BNXT_ULP_CLASS_HID_3d30f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1537] = { + .class_hid = BNXT_ULP_CLASS_HID_21f3f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1538] = { + .class_hid = BNXT_ULP_CLASS_HID_2aa3f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1539] = { + .class_hid = BNXT_ULP_CLASS_HID_3353f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1540] = { + .class_hid = BNXT_ULP_CLASS_HID_3c03f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1541] = { + .class_hid = BNXT_ULP_CLASS_HID_21a73, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1542] = { + .class_hid = BNXT_ULP_CLASS_HID_2a573, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1543] = { + .class_hid = BNXT_ULP_CLASS_HID_33073, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1544] = { + .class_hid = BNXT_ULP_CLASS_HID_3bb73, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1545] = { + .class_hid = BNXT_ULP_CLASS_HID_22d43, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1546] = { + .class_hid = BNXT_ULP_CLASS_HID_2b843, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1547] = { + .class_hid = BNXT_ULP_CLASS_HID_34343, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1548] = { + .class_hid = BNXT_ULP_CLASS_HID_3ce43, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1549] = { + .class_hid = BNXT_ULP_CLASS_HID_255e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1550] = { + .class_hid = BNXT_ULP_CLASS_HID_28437, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1551] = { + .class_hid = BNXT_ULP_CLASS_HID_30f37, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1552] = { + .class_hid = BNXT_ULP_CLASS_HID_39a37, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1553] = { + .class_hid = BNXT_ULP_CLASS_HID_24293, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1554] = { + .class_hid = BNXT_ULP_CLASS_HID_2cd93, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1555] = { + .class_hid = BNXT_ULP_CLASS_HID_35893, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1556] = { + .class_hid = BNXT_ULP_CLASS_HID_386e7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1557] = { + .class_hid = BNXT_ULP_CLASS_HID_23de7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1558] = { + .class_hid = BNXT_ULP_CLASS_HID_2c8e7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1559] = { + .class_hid = BNXT_ULP_CLASS_HID_353e7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1560] = { + .class_hid = BNXT_ULP_CLASS_HID_3823b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1561] = { + .class_hid = BNXT_ULP_CLASS_HID_25137, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1562] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc37, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1563] = { + .class_hid = BNXT_ULP_CLASS_HID_30a0b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1564] = { + .class_hid = BNXT_ULP_CLASS_HID_3950b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1565] = { + .class_hid = BNXT_ULP_CLASS_HID_22c33, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1566] = { + .class_hid = BNXT_ULP_CLASS_HID_2b733, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1567] = { + .class_hid = BNXT_ULP_CLASS_HID_34233, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1568] = { + .class_hid = BNXT_ULP_CLASS_HID_3cd33, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1569] = { + .class_hid = BNXT_ULP_CLASS_HID_218e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1570] = { + .class_hid = BNXT_ULP_CLASS_HID_2a3e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1571] = { + .class_hid = BNXT_ULP_CLASS_HID_32ee3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1572] = { + .class_hid = BNXT_ULP_CLASS_HID_3b9e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1573] = { + .class_hid = BNXT_ULP_CLASS_HID_21437, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1574] = { + .class_hid = BNXT_ULP_CLASS_HID_29f37, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1575] = { + .class_hid = BNXT_ULP_CLASS_HID_32a37, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1576] = { + .class_hid = BNXT_ULP_CLASS_HID_3b537, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1577] = { + .class_hid = BNXT_ULP_CLASS_HID_22707, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1578] = { + .class_hid = BNXT_ULP_CLASS_HID_2b207, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1579] = { + .class_hid = BNXT_ULP_CLASS_HID_33d07, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1580] = { + .class_hid = BNXT_ULP_CLASS_HID_3c807, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1581] = { + .class_hid = BNXT_ULP_CLASS_HID_24fa7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1582] = { + .class_hid = BNXT_ULP_CLASS_HID_2daa7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1583] = { + .class_hid = BNXT_ULP_CLASS_HID_308fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1584] = { + .class_hid = BNXT_ULP_CLASS_HID_393fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1585] = { + .class_hid = BNXT_ULP_CLASS_HID_23c57, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1586] = { + .class_hid = BNXT_ULP_CLASS_HID_2c757, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1587] = { + .class_hid = BNXT_ULP_CLASS_HID_35257, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1588] = { + .class_hid = BNXT_ULP_CLASS_HID_380ab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1589] = { + .class_hid = BNXT_ULP_CLASS_HID_237ab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1590] = { + .class_hid = BNXT_ULP_CLASS_HID_2c2ab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1591] = { + .class_hid = BNXT_ULP_CLASS_HID_34dab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1592] = { + .class_hid = BNXT_ULP_CLASS_HID_3d8ab, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1593] = { + .class_hid = BNXT_ULP_CLASS_HID_24afb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1594] = { + .class_hid = BNXT_ULP_CLASS_HID_2d5fb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1595] = { + .class_hid = BNXT_ULP_CLASS_HID_303cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1596] = { + .class_hid = BNXT_ULP_CLASS_HID_38ecf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1597] = { + .class_hid = BNXT_ULP_CLASS_HID_255b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1598] = { + .class_hid = BNXT_ULP_CLASS_HID_2b97, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1599] = { + .class_hid = BNXT_ULP_CLASS_HID_4f0b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1600] = { + .class_hid = BNXT_ULP_CLASS_HID_1633, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1601] = { + .class_hid = BNXT_ULP_CLASS_HID_39a7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1602] = { + .class_hid = BNXT_ULP_CLASS_HID_48cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1603] = { + .class_hid = BNXT_ULP_CLASS_HID_0ff7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1604] = { + .class_hid = BNXT_ULP_CLASS_HID_336b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1605] = { + .class_hid = BNXT_ULP_CLASS_HID_257f7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1606] = { + .class_hid = BNXT_ULP_CLASS_HID_2858b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1607] = { + .class_hid = BNXT_ULP_CLASS_HID_3108b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1608] = { + .class_hid = BNXT_ULP_CLASS_HID_39b8b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1609] = { + .class_hid = BNXT_ULP_CLASS_HID_24427, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1610] = { + .class_hid = BNXT_ULP_CLASS_HID_2cf27, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1611] = { + .class_hid = BNXT_ULP_CLASS_HID_35a27, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1612] = { + .class_hid = BNXT_ULP_CLASS_HID_388fb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1613] = { + .class_hid = BNXT_ULP_CLASS_HID_23ffb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1614] = { + .class_hid = BNXT_ULP_CLASS_HID_2cafb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1615] = { + .class_hid = BNXT_ULP_CLASS_HID_355fb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1616] = { + .class_hid = BNXT_ULP_CLASS_HID_3838f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1617] = { + .class_hid = BNXT_ULP_CLASS_HID_2528b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1618] = { + .class_hid = BNXT_ULP_CLASS_HID_2815f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1619] = { + .class_hid = BNXT_ULP_CLASS_HID_30c5f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1620] = { + .class_hid = BNXT_ULP_CLASS_HID_3975f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1621] = { + .class_hid = BNXT_ULP_CLASS_HID_21e3f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1622] = { + .class_hid = BNXT_ULP_CLASS_HID_2a93f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1623] = { + .class_hid = BNXT_ULP_CLASS_HID_3343f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1624] = { + .class_hid = BNXT_ULP_CLASS_HID_3bf3f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1625] = { + .class_hid = BNXT_ULP_CLASS_HID_20b6f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1626] = { + .class_hid = BNXT_ULP_CLASS_HID_2966f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1627] = { + .class_hid = BNXT_ULP_CLASS_HID_3216f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1628] = { + .class_hid = BNXT_ULP_CLASS_HID_3ac6f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1629] = { + .class_hid = BNXT_ULP_CLASS_HID_20623, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1630] = { + .class_hid = BNXT_ULP_CLASS_HID_29123, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1631] = { + .class_hid = BNXT_ULP_CLASS_HID_31c23, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1632] = { + .class_hid = BNXT_ULP_CLASS_HID_3a723, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1633] = { + .class_hid = BNXT_ULP_CLASS_HID_219f3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1634] = { + .class_hid = BNXT_ULP_CLASS_HID_2a4f3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1635] = { + .class_hid = BNXT_ULP_CLASS_HID_32ff3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1636] = { + .class_hid = BNXT_ULP_CLASS_HID_3baf3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1637] = { + .class_hid = BNXT_ULP_CLASS_HID_24253, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1638] = { + .class_hid = BNXT_ULP_CLASS_HID_2cd53, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 130, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1639] = { + .class_hid = BNXT_ULP_CLASS_HID_35853, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1640] = { + .class_hid = BNXT_ULP_CLASS_HID_38667, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 132, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1641] = { + .class_hid = BNXT_ULP_CLASS_HID_22e83, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 133, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1642] = { + .class_hid = BNXT_ULP_CLASS_HID_2b983, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 133, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1643] = { + .class_hid = BNXT_ULP_CLASS_HID_34483, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 133, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1644] = { + .class_hid = BNXT_ULP_CLASS_HID_3cf83, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 133, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1645] = { + .class_hid = BNXT_ULP_CLASS_HID_22a57, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 133, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1646] = { + .class_hid = BNXT_ULP_CLASS_HID_2b557, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 133, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1647] = { + .class_hid = BNXT_ULP_CLASS_HID_34057, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 134, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1648] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb57, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 135, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1649] = { + .class_hid = BNXT_ULP_CLASS_HID_23d67, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1650] = { + .class_hid = BNXT_ULP_CLASS_HID_2c867, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1651] = { + .class_hid = BNXT_ULP_CLASS_HID_35367, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1652] = { + .class_hid = BNXT_ULP_CLASS_HID_3813b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1653] = { + .class_hid = BNXT_ULP_CLASS_HID_2089b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1654] = { + .class_hid = BNXT_ULP_CLASS_HID_2939b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1655] = { + .class_hid = BNXT_ULP_CLASS_HID_31e9b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1656] = { + .class_hid = BNXT_ULP_CLASS_HID_3a99b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1657] = { + .class_hid = BNXT_ULP_CLASS_HID_25237, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1658] = { + .class_hid = BNXT_ULP_CLASS_HID_280cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1659] = { + .class_hid = BNXT_ULP_CLASS_HID_30bcb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1660] = { + .class_hid = BNXT_ULP_CLASS_HID_396cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1661] = { + .class_hid = BNXT_ULP_CLASS_HID_24dcb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1662] = { + .class_hid = BNXT_ULP_CLASS_HID_2d8cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1663] = { + .class_hid = BNXT_ULP_CLASS_HID_3069f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1664] = { + .class_hid = BNXT_ULP_CLASS_HID_3919f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1665] = { + .class_hid = BNXT_ULP_CLASS_HID_203af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1666] = { + .class_hid = BNXT_ULP_CLASS_HID_28eaf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1667] = { + .class_hid = BNXT_ULP_CLASS_HID_319af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1668] = { + .class_hid = BNXT_ULP_CLASS_HID_3a4af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1669] = { + .class_hid = BNXT_ULP_CLASS_HID_2513b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1670] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc3b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1671] = { + .class_hid = BNXT_ULP_CLASS_HID_30acf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1672] = { + .class_hid = BNXT_ULP_CLASS_HID_395cf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1673] = { + .class_hid = BNXT_ULP_CLASS_HID_23e6b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1674] = { + .class_hid = BNXT_ULP_CLASS_HID_2c96b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1675] = { + .class_hid = BNXT_ULP_CLASS_HID_3546b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1676] = { + .class_hid = BNXT_ULP_CLASS_HID_3823f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1677] = { + .class_hid = BNXT_ULP_CLASS_HID_2393f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1678] = { + .class_hid = BNXT_ULP_CLASS_HID_2c43f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1679] = { + .class_hid = BNXT_ULP_CLASS_HID_34f3f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1680] = { + .class_hid = BNXT_ULP_CLASS_HID_3da3f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1681] = { + .class_hid = BNXT_ULP_CLASS_HID_24ccf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1682] = { + .class_hid = BNXT_ULP_CLASS_HID_2d7cf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1683] = { + .class_hid = BNXT_ULP_CLASS_HID_30583, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1684] = { + .class_hid = BNXT_ULP_CLASS_HID_39083, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1685] = { + .class_hid = BNXT_ULP_CLASS_HID_21863, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1686] = { + .class_hid = BNXT_ULP_CLASS_HID_2a363, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1687] = { + .class_hid = BNXT_ULP_CLASS_HID_32e63, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1688] = { + .class_hid = BNXT_ULP_CLASS_HID_3b963, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1689] = { + .class_hid = BNXT_ULP_CLASS_HID_20553, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1690] = { + .class_hid = BNXT_ULP_CLASS_HID_29053, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1691] = { + .class_hid = BNXT_ULP_CLASS_HID_31b53, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1692] = { + .class_hid = BNXT_ULP_CLASS_HID_3a653, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1693] = { + .class_hid = BNXT_ULP_CLASS_HID_20067, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1694] = { + .class_hid = BNXT_ULP_CLASS_HID_28b67, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1695] = { + .class_hid = BNXT_ULP_CLASS_HID_31667, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1696] = { + .class_hid = BNXT_ULP_CLASS_HID_3a167, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1697] = { + .class_hid = BNXT_ULP_CLASS_HID_21337, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1698] = { + .class_hid = BNXT_ULP_CLASS_HID_29e37, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1699] = { + .class_hid = BNXT_ULP_CLASS_HID_32937, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1700] = { + .class_hid = BNXT_ULP_CLASS_HID_3b437, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1701] = { + .class_hid = BNXT_ULP_CLASS_HID_23b97, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1702] = { + .class_hid = BNXT_ULP_CLASS_HID_2c697, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1703] = { + .class_hid = BNXT_ULP_CLASS_HID_35197, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1704] = { + .class_hid = BNXT_ULP_CLASS_HID_3dc97, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1705] = { + .class_hid = BNXT_ULP_CLASS_HID_228c7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1706] = { + .class_hid = BNXT_ULP_CLASS_HID_2b3c7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1707] = { + .class_hid = BNXT_ULP_CLASS_HID_33ec7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1708] = { + .class_hid = BNXT_ULP_CLASS_HID_3c9c7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1709] = { + .class_hid = BNXT_ULP_CLASS_HID_2239b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1710] = { + .class_hid = BNXT_ULP_CLASS_HID_2ae9b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1711] = { + .class_hid = BNXT_ULP_CLASS_HID_3399b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1712] = { + .class_hid = BNXT_ULP_CLASS_HID_3c49b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1713] = { + .class_hid = BNXT_ULP_CLASS_HID_236ab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1714] = { + .class_hid = BNXT_ULP_CLASS_HID_2c1ab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1715] = { + .class_hid = BNXT_ULP_CLASS_HID_34cab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1716] = { + .class_hid = BNXT_ULP_CLASS_HID_3d7ab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1717] = { + .class_hid = BNXT_ULP_CLASS_HID_202df, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1718] = { + .class_hid = BNXT_ULP_CLASS_HID_28ddf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1719] = { + .class_hid = BNXT_ULP_CLASS_HID_318df, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1720] = { + .class_hid = BNXT_ULP_CLASS_HID_3a3df, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1721] = { + .class_hid = BNXT_ULP_CLASS_HID_24c7b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1722] = { + .class_hid = BNXT_ULP_CLASS_HID_2d77b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1723] = { + .class_hid = BNXT_ULP_CLASS_HID_3050f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1724] = { + .class_hid = BNXT_ULP_CLASS_HID_3900f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1725] = { + .class_hid = BNXT_ULP_CLASS_HID_2470f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1726] = { + .class_hid = BNXT_ULP_CLASS_HID_2d20f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1727] = { + .class_hid = BNXT_ULP_CLASS_HID_300c3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1728] = { + .class_hid = BNXT_ULP_CLASS_HID_38bc3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1729] = { + .class_hid = BNXT_ULP_CLASS_HID_25adf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1730] = { + .class_hid = BNXT_ULP_CLASS_HID_28893, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1731] = { + .class_hid = BNXT_ULP_CLASS_HID_31393, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1732] = { + .class_hid = BNXT_ULP_CLASS_HID_39e93, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1733] = { + .class_hid = BNXT_ULP_CLASS_HID_24b7f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1734] = { + .class_hid = BNXT_ULP_CLASS_HID_2d67f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1735] = { + .class_hid = BNXT_ULP_CLASS_HID_30433, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1736] = { + .class_hid = BNXT_ULP_CLASS_HID_38f33, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1737] = { + .class_hid = BNXT_ULP_CLASS_HID_237af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1738] = { + .class_hid = BNXT_ULP_CLASS_HID_2c2af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1739] = { + .class_hid = BNXT_ULP_CLASS_HID_34daf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1740] = { + .class_hid = BNXT_ULP_CLASS_HID_3d8af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1741] = { + .class_hid = BNXT_ULP_CLASS_HID_23363, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1742] = { + .class_hid = BNXT_ULP_CLASS_HID_2be63, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1743] = { + .class_hid = BNXT_ULP_CLASS_HID_34963, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1744] = { + .class_hid = BNXT_ULP_CLASS_HID_3d463, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1745] = { + .class_hid = BNXT_ULP_CLASS_HID_24633, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1746] = { + .class_hid = BNXT_ULP_CLASS_HID_2d133, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1747] = { + .class_hid = BNXT_ULP_CLASS_HID_35c33, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1748] = { + .class_hid = BNXT_ULP_CLASS_HID_38ac7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1749] = { + .class_hid = BNXT_ULP_CLASS_HID_211a7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1750] = { + .class_hid = BNXT_ULP_CLASS_HID_29ca7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1751] = { + .class_hid = BNXT_ULP_CLASS_HID_327a7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1752] = { + .class_hid = BNXT_ULP_CLASS_HID_3b2a7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1753] = { + .class_hid = BNXT_ULP_CLASS_HID_25bc3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1754] = { + .class_hid = BNXT_ULP_CLASS_HID_28997, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1755] = { + .class_hid = BNXT_ULP_CLASS_HID_31497, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1756] = { + .class_hid = BNXT_ULP_CLASS_HID_39f97, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1757] = { + .class_hid = BNXT_ULP_CLASS_HID_25697, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1758] = { + .class_hid = BNXT_ULP_CLASS_HID_284ab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1759] = { + .class_hid = BNXT_ULP_CLASS_HID_30fab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1760] = { + .class_hid = BNXT_ULP_CLASS_HID_39aab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1761] = { + .class_hid = BNXT_ULP_CLASS_HID_20d7b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1762] = { + .class_hid = BNXT_ULP_CLASS_HID_2987b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1763] = { + .class_hid = BNXT_ULP_CLASS_HID_3237b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1764] = { + .class_hid = BNXT_ULP_CLASS_HID_3ae7b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1765] = { + .class_hid = BNXT_ULP_CLASS_HID_235db, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1766] = { + .class_hid = BNXT_ULP_CLASS_HID_2c0db, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1767] = { + .class_hid = BNXT_ULP_CLASS_HID_34bdb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 137, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1768] = { + .class_hid = BNXT_ULP_CLASS_HID_3d6db, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 138, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1769] = { + .class_hid = BNXT_ULP_CLASS_HID_2220b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 139, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1770] = { + .class_hid = BNXT_ULP_CLASS_HID_2ad0b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 139, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1771] = { + .class_hid = BNXT_ULP_CLASS_HID_3380b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 139, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1772] = { + .class_hid = BNXT_ULP_CLASS_HID_3c30b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 139, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1773] = { + .class_hid = BNXT_ULP_CLASS_HID_21ddf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 139, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1774] = { + .class_hid = BNXT_ULP_CLASS_HID_2a8df, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 139, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1775] = { + .class_hid = BNXT_ULP_CLASS_HID_333df, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1776] = { + .class_hid = BNXT_ULP_CLASS_HID_3bedf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 141, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1777] = { + .class_hid = BNXT_ULP_CLASS_HID_230ef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1778] = { + .class_hid = BNXT_ULP_CLASS_HID_2bbef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1779] = { + .class_hid = BNXT_ULP_CLASS_HID_346ef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1780] = { + .class_hid = BNXT_ULP_CLASS_HID_3d1ef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1781] = { + .class_hid = BNXT_ULP_CLASS_HID_2594f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1782] = { + .class_hid = BNXT_ULP_CLASS_HID_28703, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1783] = { + .class_hid = BNXT_ULP_CLASS_HID_31203, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1784] = { + .class_hid = BNXT_ULP_CLASS_HID_39d03, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1785] = { + .class_hid = BNXT_ULP_CLASS_HID_245bf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1786] = { + .class_hid = BNXT_ULP_CLASS_HID_2d0bf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1787] = { + .class_hid = BNXT_ULP_CLASS_HID_35bbf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1788] = { + .class_hid = BNXT_ULP_CLASS_HID_38a73, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1789] = { + .class_hid = BNXT_ULP_CLASS_HID_24173, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1790] = { + .class_hid = BNXT_ULP_CLASS_HID_2cc73, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1791] = { + .class_hid = BNXT_ULP_CLASS_HID_35773, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1792] = { + .class_hid = BNXT_ULP_CLASS_HID_38507, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1793] = { + .class_hid = BNXT_ULP_CLASS_HID_25403, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1794] = { + .class_hid = BNXT_ULP_CLASS_HID_282d7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1795] = { + .class_hid = BNXT_ULP_CLASS_HID_30dd7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1796] = { + .class_hid = BNXT_ULP_CLASS_HID_398d7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1797] = { + .class_hid = BNXT_ULP_CLASS_HID_244a3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1798] = { + .class_hid = BNXT_ULP_CLASS_HID_2cfa3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1799] = { + .class_hid = BNXT_ULP_CLASS_HID_35aa3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1800] = { + .class_hid = BNXT_ULP_CLASS_HID_38977, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1801] = { + .class_hid = BNXT_ULP_CLASS_HID_23193, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1802] = { + .class_hid = BNXT_ULP_CLASS_HID_2bc93, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1803] = { + .class_hid = BNXT_ULP_CLASS_HID_34793, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1804] = { + .class_hid = BNXT_ULP_CLASS_HID_3d293, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1805] = { + .class_hid = BNXT_ULP_CLASS_HID_22ca7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1806] = { + .class_hid = BNXT_ULP_CLASS_HID_2b7a7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1807] = { + .class_hid = BNXT_ULP_CLASS_HID_342a7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1808] = { + .class_hid = BNXT_ULP_CLASS_HID_3cda7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1809] = { + .class_hid = BNXT_ULP_CLASS_HID_24077, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1810] = { + .class_hid = BNXT_ULP_CLASS_HID_2cb77, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1811] = { + .class_hid = BNXT_ULP_CLASS_HID_35677, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1812] = { + .class_hid = BNXT_ULP_CLASS_HID_3840b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1813] = { + .class_hid = BNXT_ULP_CLASS_HID_20beb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1814] = { + .class_hid = BNXT_ULP_CLASS_HID_296eb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1815] = { + .class_hid = BNXT_ULP_CLASS_HID_321eb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1816] = { + .class_hid = BNXT_ULP_CLASS_HID_3aceb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1817] = { + .class_hid = BNXT_ULP_CLASS_HID_25507, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1818] = { + .class_hid = BNXT_ULP_CLASS_HID_283db, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1819] = { + .class_hid = BNXT_ULP_CLASS_HID_30edb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1820] = { + .class_hid = BNXT_ULP_CLASS_HID_399db, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1821] = { + .class_hid = BNXT_ULP_CLASS_HID_250db, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1822] = { + .class_hid = BNXT_ULP_CLASS_HID_2dbdb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1823] = { + .class_hid = BNXT_ULP_CLASS_HID_309ef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1824] = { + .class_hid = BNXT_ULP_CLASS_HID_394ef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1825] = { + .class_hid = BNXT_ULP_CLASS_HID_206bf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1826] = { + .class_hid = BNXT_ULP_CLASS_HID_291bf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1827] = { + .class_hid = BNXT_ULP_CLASS_HID_31cbf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1828] = { + .class_hid = BNXT_ULP_CLASS_HID_3a7bf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1829] = { + .class_hid = BNXT_ULP_CLASS_HID_22f1f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1830] = { + .class_hid = BNXT_ULP_CLASS_HID_2ba1f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1831] = { + .class_hid = BNXT_ULP_CLASS_HID_3451f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1832] = { + .class_hid = BNXT_ULP_CLASS_HID_3d01f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1833] = { + .class_hid = BNXT_ULP_CLASS_HID_21c4f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1834] = { + .class_hid = BNXT_ULP_CLASS_HID_2a74f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1835] = { + .class_hid = BNXT_ULP_CLASS_HID_3324f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1836] = { + .class_hid = BNXT_ULP_CLASS_HID_3bd4f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1837] = { + .class_hid = BNXT_ULP_CLASS_HID_21703, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1838] = { + .class_hid = BNXT_ULP_CLASS_HID_2a203, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1839] = { + .class_hid = BNXT_ULP_CLASS_HID_32d03, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1840] = { + .class_hid = BNXT_ULP_CLASS_HID_3b803, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1841] = { + .class_hid = BNXT_ULP_CLASS_HID_22ad3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1842] = { + .class_hid = BNXT_ULP_CLASS_HID_2b5d3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1843] = { + .class_hid = BNXT_ULP_CLASS_HID_340d3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1844] = { + .class_hid = BNXT_ULP_CLASS_HID_3cbd3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1845] = { + .class_hid = BNXT_ULP_CLASS_HID_252b3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1846] = { + .class_hid = BNXT_ULP_CLASS_HID_28147, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1847] = { + .class_hid = BNXT_ULP_CLASS_HID_30c47, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1848] = { + .class_hid = BNXT_ULP_CLASS_HID_39747, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1849] = { + .class_hid = BNXT_ULP_CLASS_HID_23fe3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1850] = { + .class_hid = BNXT_ULP_CLASS_HID_2cae3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1851] = { + .class_hid = BNXT_ULP_CLASS_HID_355e3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1852] = { + .class_hid = BNXT_ULP_CLASS_HID_383b7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1853] = { + .class_hid = BNXT_ULP_CLASS_HID_23ab7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1854] = { + .class_hid = BNXT_ULP_CLASS_HID_2c5b7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1855] = { + .class_hid = BNXT_ULP_CLASS_HID_350b7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1856] = { + .class_hid = BNXT_ULP_CLASS_HID_3dbb7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1857] = { + .class_hid = BNXT_ULP_CLASS_HID_24e47, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1858] = { + .class_hid = BNXT_ULP_CLASS_HID_2d947, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1859] = { + .class_hid = BNXT_ULP_CLASS_HID_3071b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1860] = { + .class_hid = BNXT_ULP_CLASS_HID_3921b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1861] = { + .class_hid = BNXT_ULP_CLASS_HID_2326f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1862] = { + .class_hid = BNXT_ULP_CLASS_HID_2bd6f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1863] = { + .class_hid = BNXT_ULP_CLASS_HID_3486f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1864] = { + .class_hid = BNXT_ULP_CLASS_HID_3d36f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1865] = { + .class_hid = BNXT_ULP_CLASS_HID_21f5f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1866] = { + .class_hid = BNXT_ULP_CLASS_HID_2aa5f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1867] = { + .class_hid = BNXT_ULP_CLASS_HID_3355f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1868] = { + .class_hid = BNXT_ULP_CLASS_HID_3c05f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1869] = { + .class_hid = BNXT_ULP_CLASS_HID_21a13, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1870] = { + .class_hid = BNXT_ULP_CLASS_HID_2a513, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1871] = { + .class_hid = BNXT_ULP_CLASS_HID_33013, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1872] = { + .class_hid = BNXT_ULP_CLASS_HID_3bb13, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1873] = { + .class_hid = BNXT_ULP_CLASS_HID_22d23, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1874] = { + .class_hid = BNXT_ULP_CLASS_HID_2b823, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1875] = { + .class_hid = BNXT_ULP_CLASS_HID_34323, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1876] = { + .class_hid = BNXT_ULP_CLASS_HID_3ce23, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1877] = { + .class_hid = BNXT_ULP_CLASS_HID_25583, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1878] = { + .class_hid = BNXT_ULP_CLASS_HID_28457, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1879] = { + .class_hid = BNXT_ULP_CLASS_HID_30f57, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1880] = { + .class_hid = BNXT_ULP_CLASS_HID_39a57, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1881] = { + .class_hid = BNXT_ULP_CLASS_HID_242f3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1882] = { + .class_hid = BNXT_ULP_CLASS_HID_2cdf3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1883] = { + .class_hid = BNXT_ULP_CLASS_HID_358f3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1884] = { + .class_hid = BNXT_ULP_CLASS_HID_38687, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1885] = { + .class_hid = BNXT_ULP_CLASS_HID_23d87, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1886] = { + .class_hid = BNXT_ULP_CLASS_HID_2c887, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1887] = { + .class_hid = BNXT_ULP_CLASS_HID_35387, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1888] = { + .class_hid = BNXT_ULP_CLASS_HID_3825b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1889] = { + .class_hid = BNXT_ULP_CLASS_HID_25157, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1890] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc57, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1891] = { + .class_hid = BNXT_ULP_CLASS_HID_30a6b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1892] = { + .class_hid = BNXT_ULP_CLASS_HID_3956b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1893] = { + .class_hid = BNXT_ULP_CLASS_HID_22c53, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1894] = { + .class_hid = BNXT_ULP_CLASS_HID_2b753, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1895] = { + .class_hid = BNXT_ULP_CLASS_HID_34253, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1896] = { + .class_hid = BNXT_ULP_CLASS_HID_3cd53, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1897] = { + .class_hid = BNXT_ULP_CLASS_HID_21883, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1898] = { + .class_hid = BNXT_ULP_CLASS_HID_2a383, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1899] = { + .class_hid = BNXT_ULP_CLASS_HID_32e83, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1900] = { + .class_hid = BNXT_ULP_CLASS_HID_3b983, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1901] = { + .class_hid = BNXT_ULP_CLASS_HID_21457, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1902] = { + .class_hid = BNXT_ULP_CLASS_HID_29f57, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1903] = { + .class_hid = BNXT_ULP_CLASS_HID_32a57, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1904] = { + .class_hid = BNXT_ULP_CLASS_HID_3b557, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1905] = { + .class_hid = BNXT_ULP_CLASS_HID_22767, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1906] = { + .class_hid = BNXT_ULP_CLASS_HID_2b267, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1907] = { + .class_hid = BNXT_ULP_CLASS_HID_33d67, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1908] = { + .class_hid = BNXT_ULP_CLASS_HID_3c867, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1909] = { + .class_hid = BNXT_ULP_CLASS_HID_24fc7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1910] = { + .class_hid = BNXT_ULP_CLASS_HID_2dac7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1911] = { + .class_hid = BNXT_ULP_CLASS_HID_3089b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1912] = { + .class_hid = BNXT_ULP_CLASS_HID_3939b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1913] = { + .class_hid = BNXT_ULP_CLASS_HID_23c37, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1914] = { + .class_hid = BNXT_ULP_CLASS_HID_2c737, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1915] = { + .class_hid = BNXT_ULP_CLASS_HID_35237, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1916] = { + .class_hid = BNXT_ULP_CLASS_HID_380cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1917] = { + .class_hid = BNXT_ULP_CLASS_HID_237cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1918] = { + .class_hid = BNXT_ULP_CLASS_HID_2c2cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1919] = { + .class_hid = BNXT_ULP_CLASS_HID_34dcb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1920] = { + .class_hid = BNXT_ULP_CLASS_HID_3d8cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1921] = { + .class_hid = BNXT_ULP_CLASS_HID_24a9b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1922] = { + .class_hid = BNXT_ULP_CLASS_HID_2d59b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1923] = { + .class_hid = BNXT_ULP_CLASS_HID_303af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1924] = { + .class_hid = BNXT_ULP_CLASS_HID_38eaf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1925] = { + .class_hid = BNXT_ULP_CLASS_HID_253b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1926] = { + .class_hid = BNXT_ULP_CLASS_HID_2bf7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1927] = { + .class_hid = BNXT_ULP_CLASS_HID_4f6b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1928] = { + .class_hid = BNXT_ULP_CLASS_HID_1653, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1929] = { + .class_hid = BNXT_ULP_CLASS_HID_39c7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1930] = { + .class_hid = BNXT_ULP_CLASS_HID_48af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1931] = { + .class_hid = BNXT_ULP_CLASS_HID_0f97, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1932] = { + .class_hid = BNXT_ULP_CLASS_HID_330b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1933] = { + .class_hid = BNXT_ULP_CLASS_HID_374e, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 142, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1934] = { + .class_hid = BNXT_ULP_CLASS_HID_11ee, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 143, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1935] = { + .class_hid = BNXT_ULP_CLASS_HID_423a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 143, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1936] = { + .class_hid = BNXT_ULP_CLASS_HID_0cd6, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1937] = { + .class_hid = BNXT_ULP_CLASS_HID_310a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1938] = { + .class_hid = BNXT_ULP_CLASS_HID_469e, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1939] = { + .class_hid = BNXT_ULP_CLASS_HID_5ce6, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1940] = { + .class_hid = BNXT_ULP_CLASS_HID_0692, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1941] = { + .class_hid = BNXT_ULP_CLASS_HID_1c7e, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1942] = { + .class_hid = BNXT_ULP_CLASS_HID_55c2, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 145, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1943] = { + .class_hid = BNXT_ULP_CLASS_HID_2b2a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 145, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1944] = { + .class_hid = BNXT_ULP_CLASS_HID_15c6, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 146, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1945] = { + .class_hid = BNXT_ULP_CLASS_HID_163a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 146, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1946] = { + .class_hid = BNXT_ULP_CLASS_HID_2f8e, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 146, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1947] = { + .class_hid = BNXT_ULP_CLASS_HID_2516, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 146, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1948] = { + .class_hid = BNXT_ULP_CLASS_HID_4b76, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 146, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1949] = { + .class_hid = BNXT_ULP_CLASS_HID_10e6, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 146, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1950] = { + .class_hid = BNXT_ULP_CLASS_HID_264a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 147, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1951] = { + .class_hid = BNXT_ULP_CLASS_HID_3fd2, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 147, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1952] = { + .class_hid = BNXT_ULP_CLASS_HID_4532, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 148, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1953] = { + .class_hid = BNXT_ULP_CLASS_HID_4996, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 148, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1954] = { + .class_hid = BNXT_ULP_CLASS_HID_2036, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 148, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1955] = { + .class_hid = BNXT_ULP_CLASS_HID_399e, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 148, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1956] = { + .class_hid = BNXT_ULP_CLASS_HID_5ffe, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 148, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1957] = { + .class_hid = BNXT_ULP_CLASS_HID_34fe, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 148, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1958] = { + .class_hid = BNXT_ULP_CLASS_HID_3a32, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 149, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1959] = { + .class_hid = BNXT_ULP_CLASS_HID_376e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 149, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1960] = { + .class_hid = BNXT_ULP_CLASS_HID_12d6e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 149, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1961] = { + .class_hid = BNXT_ULP_CLASS_HID_2436e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 150, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1962] = { + .class_hid = BNXT_ULP_CLASS_HID_31dba, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 151, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1963] = { + .class_hid = BNXT_ULP_CLASS_HID_11ce, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1964] = { + .class_hid = BNXT_ULP_CLASS_HID_107ce, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1965] = { + .class_hid = BNXT_ULP_CLASS_HID_23dce, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1966] = { + .class_hid = BNXT_ULP_CLASS_HID_353ce, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1967] = { + .class_hid = BNXT_ULP_CLASS_HID_421a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1968] = { + .class_hid = BNXT_ULP_CLASS_HID_11d56, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1969] = { + .class_hid = BNXT_ULP_CLASS_HID_23356, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 153, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1970] = { + .class_hid = BNXT_ULP_CLASS_HID_32956, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 154, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1971] = { + .class_hid = BNXT_ULP_CLASS_HID_0cf6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1972] = { + .class_hid = BNXT_ULP_CLASS_HID_122f6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1973] = { + .class_hid = BNXT_ULP_CLASS_HID_258f6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1974] = { + .class_hid = BNXT_ULP_CLASS_HID_313c2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1975] = { + .class_hid = BNXT_ULP_CLASS_HID_312a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1976] = { + .class_hid = BNXT_ULP_CLASS_HID_1272a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1977] = { + .class_hid = BNXT_ULP_CLASS_HID_25d2a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1978] = { + .class_hid = BNXT_ULP_CLASS_HID_31466, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1979] = { + .class_hid = BNXT_ULP_CLASS_HID_46be, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1980] = { + .class_hid = BNXT_ULP_CLASS_HID_1018a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1981] = { + .class_hid = BNXT_ULP_CLASS_HID_2378a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1982] = { + .class_hid = BNXT_ULP_CLASS_HID_32d8a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1983] = { + .class_hid = BNXT_ULP_CLASS_HID_5cc6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1984] = { + .class_hid = BNXT_ULP_CLASS_HID_11712, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1985] = { + .class_hid = BNXT_ULP_CLASS_HID_20d12, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1986] = { + .class_hid = BNXT_ULP_CLASS_HID_32312, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1987] = { + .class_hid = BNXT_ULP_CLASS_HID_06b2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1988] = { + .class_hid = BNXT_ULP_CLASS_HID_13cb2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1989] = { + .class_hid = BNXT_ULP_CLASS_HID_252b2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1990] = { + .class_hid = BNXT_ULP_CLASS_HID_348b2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1991] = { + .class_hid = BNXT_ULP_CLASS_HID_1c5e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1992] = { + .class_hid = BNXT_ULP_CLASS_HID_1325e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 155, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1993] = { + .class_hid = BNXT_ULP_CLASS_HID_2285e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1994] = { + .class_hid = BNXT_ULP_CLASS_HID_35e5e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 157, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1995] = { + .class_hid = BNXT_ULP_CLASS_HID_55e2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 158, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1996] = { + .class_hid = BNXT_ULP_CLASS_HID_14be2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 158, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1997] = { + .class_hid = BNXT_ULP_CLASS_HID_2023e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 158, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1998] = { + .class_hid = BNXT_ULP_CLASS_HID_3383e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 158, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1999] = { + .class_hid = BNXT_ULP_CLASS_HID_2b0a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 158, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2000] = { + .class_hid = BNXT_ULP_CLASS_HID_1410a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 158, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2001] = { + .class_hid = BNXT_ULP_CLASS_HID_21846, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 159, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2002] = { + .class_hid = BNXT_ULP_CLASS_HID_30e46, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 160, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2003] = { + .class_hid = BNXT_ULP_CLASS_HID_15e6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2004] = { + .class_hid = BNXT_ULP_CLASS_HID_10be6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2005] = { + .class_hid = BNXT_ULP_CLASS_HID_221e6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2006] = { + .class_hid = BNXT_ULP_CLASS_HID_357e6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2007] = { + .class_hid = BNXT_ULP_CLASS_HID_161a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2008] = { + .class_hid = BNXT_ULP_CLASS_HID_10c1a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2009] = { + .class_hid = BNXT_ULP_CLASS_HID_2221a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2010] = { + .class_hid = BNXT_ULP_CLASS_HID_3581a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2011] = { + .class_hid = BNXT_ULP_CLASS_HID_2fae, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2012] = { + .class_hid = BNXT_ULP_CLASS_HID_145ae, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2013] = { + .class_hid = BNXT_ULP_CLASS_HID_21cfa, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2014] = { + .class_hid = BNXT_ULP_CLASS_HID_332fa, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2015] = { + .class_hid = BNXT_ULP_CLASS_HID_2536, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2016] = { + .class_hid = BNXT_ULP_CLASS_HID_15b36, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2017] = { + .class_hid = BNXT_ULP_CLASS_HID_21202, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2018] = { + .class_hid = BNXT_ULP_CLASS_HID_30802, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2019] = { + .class_hid = BNXT_ULP_CLASS_HID_4b56, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2020] = { + .class_hid = BNXT_ULP_CLASS_HID_105a2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2021] = { + .class_hid = BNXT_ULP_CLASS_HID_23ba2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2022] = { + .class_hid = BNXT_ULP_CLASS_HID_351a2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2023] = { + .class_hid = BNXT_ULP_CLASS_HID_10c6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2024] = { + .class_hid = BNXT_ULP_CLASS_HID_106c6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 161, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2025] = { + .class_hid = BNXT_ULP_CLASS_HID_23cc6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 162, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2026] = { + .class_hid = BNXT_ULP_CLASS_HID_352c6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 163, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2027] = { + .class_hid = BNXT_ULP_CLASS_HID_266a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 164, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2028] = { + .class_hid = BNXT_ULP_CLASS_HID_15c6a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 164, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2029] = { + .class_hid = BNXT_ULP_CLASS_HID_216a6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 164, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2030] = { + .class_hid = BNXT_ULP_CLASS_HID_30ca6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 164, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2031] = { + .class_hid = BNXT_ULP_CLASS_HID_3ff2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 164, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2032] = { + .class_hid = BNXT_ULP_CLASS_HID_155f2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 164, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2033] = { + .class_hid = BNXT_ULP_CLASS_HID_24bf2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 165, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2034] = { + .class_hid = BNXT_ULP_CLASS_HID_302ce, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 166, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2035] = { + .class_hid = BNXT_ULP_CLASS_HID_4512, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2036] = { + .class_hid = BNXT_ULP_CLASS_HID_11c6e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2037] = { + .class_hid = BNXT_ULP_CLASS_HID_2326e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2038] = { + .class_hid = BNXT_ULP_CLASS_HID_3286e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2039] = { + .class_hid = BNXT_ULP_CLASS_HID_49b6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2040] = { + .class_hid = BNXT_ULP_CLASS_HID_10082, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2041] = { + .class_hid = BNXT_ULP_CLASS_HID_23682, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2042] = { + .class_hid = BNXT_ULP_CLASS_HID_32c82, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2043] = { + .class_hid = BNXT_ULP_CLASS_HID_2016, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2044] = { + .class_hid = BNXT_ULP_CLASS_HID_15616, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2045] = { + .class_hid = BNXT_ULP_CLASS_HID_21162, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2046] = { + .class_hid = BNXT_ULP_CLASS_HID_30762, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2047] = { + .class_hid = BNXT_ULP_CLASS_HID_39be, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2048] = { + .class_hid = BNXT_ULP_CLASS_HID_12fbe, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2049] = { + .class_hid = BNXT_ULP_CLASS_HID_245be, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2050] = { + .class_hid = BNXT_ULP_CLASS_HID_31c8a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2051] = { + .class_hid = BNXT_ULP_CLASS_HID_5fde, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2052] = { + .class_hid = BNXT_ULP_CLASS_HID_1162a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2053] = { + .class_hid = BNXT_ULP_CLASS_HID_20c2a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2054] = { + .class_hid = BNXT_ULP_CLASS_HID_3222a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2055] = { + .class_hid = BNXT_ULP_CLASS_HID_34de, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2056] = { + .class_hid = BNXT_ULP_CLASS_HID_3a12, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2057] = { + .class_hid = BNXT_ULP_CLASS_HID_370e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 167, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2058] = { + .class_hid = BNXT_ULP_CLASS_HID_12d0e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 167, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2059] = { + .class_hid = BNXT_ULP_CLASS_HID_2430e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 168, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2060] = { + .class_hid = BNXT_ULP_CLASS_HID_31dda, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 169, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2061] = { + .class_hid = BNXT_ULP_CLASS_HID_11ae, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 170, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2062] = { + .class_hid = BNXT_ULP_CLASS_HID_107ae, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 170, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2063] = { + .class_hid = BNXT_ULP_CLASS_HID_23dae, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 170, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2064] = { + .class_hid = BNXT_ULP_CLASS_HID_353ae, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 170, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2065] = { + .class_hid = BNXT_ULP_CLASS_HID_427a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 170, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2066] = { + .class_hid = BNXT_ULP_CLASS_HID_11d36, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 170, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2067] = { + .class_hid = BNXT_ULP_CLASS_HID_23336, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 171, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2068] = { + .class_hid = BNXT_ULP_CLASS_HID_32936, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 172, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2069] = { + .class_hid = BNXT_ULP_CLASS_HID_0c96, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2070] = { + .class_hid = BNXT_ULP_CLASS_HID_12296, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2071] = { + .class_hid = BNXT_ULP_CLASS_HID_25896, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2072] = { + .class_hid = BNXT_ULP_CLASS_HID_313a2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2073] = { + .class_hid = BNXT_ULP_CLASS_HID_314a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2074] = { + .class_hid = BNXT_ULP_CLASS_HID_1274a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2075] = { + .class_hid = BNXT_ULP_CLASS_HID_25d4a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2076] = { + .class_hid = BNXT_ULP_CLASS_HID_31406, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2077] = { + .class_hid = BNXT_ULP_CLASS_HID_46de, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2078] = { + .class_hid = BNXT_ULP_CLASS_HID_101ea, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2079] = { + .class_hid = BNXT_ULP_CLASS_HID_237ea, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2080] = { + .class_hid = BNXT_ULP_CLASS_HID_32dea, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2081] = { + .class_hid = BNXT_ULP_CLASS_HID_5ca6, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2082] = { + .class_hid = BNXT_ULP_CLASS_HID_11772, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2083] = { + .class_hid = BNXT_ULP_CLASS_HID_20d72, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2084] = { + .class_hid = BNXT_ULP_CLASS_HID_32372, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2085] = { + .class_hid = BNXT_ULP_CLASS_HID_06d2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2086] = { + .class_hid = BNXT_ULP_CLASS_HID_13cd2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2087] = { + .class_hid = BNXT_ULP_CLASS_HID_252d2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2088] = { + .class_hid = BNXT_ULP_CLASS_HID_348d2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2089] = { + .class_hid = BNXT_ULP_CLASS_HID_1c3e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2090] = { + .class_hid = BNXT_ULP_CLASS_HID_1323e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 173, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2091] = { + .class_hid = BNXT_ULP_CLASS_HID_2283e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 174, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2092] = { + .class_hid = BNXT_ULP_CLASS_HID_35e3e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 175, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2093] = { + .class_hid = BNXT_ULP_CLASS_HID_5582, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 176, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2094] = { + .class_hid = BNXT_ULP_CLASS_HID_14b82, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 176, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2095] = { + .class_hid = BNXT_ULP_CLASS_HID_2025e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 176, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2096] = { + .class_hid = BNXT_ULP_CLASS_HID_3385e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 176, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2097] = { + .class_hid = BNXT_ULP_CLASS_HID_2b6a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 176, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2098] = { + .class_hid = BNXT_ULP_CLASS_HID_1416a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 176, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2099] = { + .class_hid = BNXT_ULP_CLASS_HID_21826, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 177, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2100] = { + .class_hid = BNXT_ULP_CLASS_HID_30e26, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 178, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2101] = { + .class_hid = BNXT_ULP_CLASS_HID_1586, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2102] = { + .class_hid = BNXT_ULP_CLASS_HID_10b86, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2103] = { + .class_hid = BNXT_ULP_CLASS_HID_22186, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2104] = { + .class_hid = BNXT_ULP_CLASS_HID_35786, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2105] = { + .class_hid = BNXT_ULP_CLASS_HID_167a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2106] = { + .class_hid = BNXT_ULP_CLASS_HID_10c7a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2107] = { + .class_hid = BNXT_ULP_CLASS_HID_2227a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2108] = { + .class_hid = BNXT_ULP_CLASS_HID_3587a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2109] = { + .class_hid = BNXT_ULP_CLASS_HID_2fce, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2110] = { + .class_hid = BNXT_ULP_CLASS_HID_145ce, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2111] = { + .class_hid = BNXT_ULP_CLASS_HID_21c9a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2112] = { + .class_hid = BNXT_ULP_CLASS_HID_3329a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2113] = { + .class_hid = BNXT_ULP_CLASS_HID_2556, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2114] = { + .class_hid = BNXT_ULP_CLASS_HID_15b56, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2115] = { + .class_hid = BNXT_ULP_CLASS_HID_21262, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2116] = { + .class_hid = BNXT_ULP_CLASS_HID_30862, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2117] = { + .class_hid = BNXT_ULP_CLASS_HID_4b36, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2118] = { + .class_hid = BNXT_ULP_CLASS_HID_105c2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2119] = { + .class_hid = BNXT_ULP_CLASS_HID_23bc2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2120] = { + .class_hid = BNXT_ULP_CLASS_HID_351c2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2121] = { + .class_hid = BNXT_ULP_CLASS_HID_10a6, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2122] = { + .class_hid = BNXT_ULP_CLASS_HID_106a6, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 179, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2123] = { + .class_hid = BNXT_ULP_CLASS_HID_23ca6, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 180, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2124] = { + .class_hid = BNXT_ULP_CLASS_HID_352a6, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 181, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2125] = { + .class_hid = BNXT_ULP_CLASS_HID_260a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 182, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2126] = { + .class_hid = BNXT_ULP_CLASS_HID_15c0a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 182, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2127] = { + .class_hid = BNXT_ULP_CLASS_HID_216c6, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 182, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2128] = { + .class_hid = BNXT_ULP_CLASS_HID_30cc6, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 182, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2129] = { + .class_hid = BNXT_ULP_CLASS_HID_3f92, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 182, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2130] = { + .class_hid = BNXT_ULP_CLASS_HID_15592, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 182, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2131] = { + .class_hid = BNXT_ULP_CLASS_HID_24b92, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 183, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2132] = { + .class_hid = BNXT_ULP_CLASS_HID_302ae, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 184, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2133] = { + .class_hid = BNXT_ULP_CLASS_HID_4572, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2134] = { + .class_hid = BNXT_ULP_CLASS_HID_11c0e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2135] = { + .class_hid = BNXT_ULP_CLASS_HID_2320e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2136] = { + .class_hid = BNXT_ULP_CLASS_HID_3280e, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2137] = { + .class_hid = BNXT_ULP_CLASS_HID_49d6, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2138] = { + .class_hid = BNXT_ULP_CLASS_HID_100e2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2139] = { + .class_hid = BNXT_ULP_CLASS_HID_236e2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2140] = { + .class_hid = BNXT_ULP_CLASS_HID_32ce2, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2141] = { + .class_hid = BNXT_ULP_CLASS_HID_2076, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2142] = { + .class_hid = BNXT_ULP_CLASS_HID_15676, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2143] = { + .class_hid = BNXT_ULP_CLASS_HID_21102, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2144] = { + .class_hid = BNXT_ULP_CLASS_HID_30702, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2145] = { + .class_hid = BNXT_ULP_CLASS_HID_39de, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2146] = { + .class_hid = BNXT_ULP_CLASS_HID_12fde, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2147] = { + .class_hid = BNXT_ULP_CLASS_HID_245de, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2148] = { + .class_hid = BNXT_ULP_CLASS_HID_31cea, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2149] = { + .class_hid = BNXT_ULP_CLASS_HID_5fbe, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2150] = { + .class_hid = BNXT_ULP_CLASS_HID_1164a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2151] = { + .class_hid = BNXT_ULP_CLASS_HID_20c4a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2152] = { + .class_hid = BNXT_ULP_CLASS_HID_3224a, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2153] = { + .class_hid = BNXT_ULP_CLASS_HID_34be, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2154] = { + .class_hid = BNXT_ULP_CLASS_HID_3a72, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2155] = { + .class_hid = BNXT_ULP_CLASS_HID_09ea, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 185, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2156] = { + .class_hid = BNXT_ULP_CLASS_HID_2912, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 186, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2157] = { + .class_hid = BNXT_ULP_CLASS_HID_03b2, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 186, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2158] = { + .class_hid = BNXT_ULP_CLASS_HID_5f7e, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 187, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2159] = { + .class_hid = BNXT_ULP_CLASS_HID_03a6, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 187, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2160] = { + .class_hid = BNXT_ULP_CLASS_HID_23ce, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 187, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2161] = { + .class_hid = BNXT_ULP_CLASS_HID_1a6e, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 187, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2162] = { + .class_hid = BNXT_ULP_CLASS_HID_593a, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 187, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2163] = { + .class_hid = BNXT_ULP_CLASS_HID_4dce, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 187, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2164] = { + .class_hid = BNXT_ULP_CLASS_HID_0e02, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 188, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2165] = { + .class_hid = BNXT_ULP_CLASS_HID_4796, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 188, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2166] = { + .class_hid = BNXT_ULP_CLASS_HID_246e, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 189, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2167] = { + .class_hid = BNXT_ULP_CLASS_HID_478a, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 189, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2168] = { + .class_hid = BNXT_ULP_CLASS_HID_08fe, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 189, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2169] = { + .class_hid = BNXT_ULP_CLASS_HID_5e52, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 189, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2170] = { + .class_hid = BNXT_ULP_CLASS_HID_3e2a, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 189, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2171] = { + .class_hid = BNXT_ULP_CLASS_HID_5e46, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 189, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2172] = { + .class_hid = BNXT_ULP_CLASS_HID_02ba, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 190, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2173] = { + .class_hid = BNXT_ULP_CLASS_HID_580e, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 190, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2174] = { + .class_hid = BNXT_ULP_CLASS_HID_38e6, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2175] = { + .class_hid = BNXT_ULP_CLASS_HID_5802, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2176] = { + .class_hid = BNXT_ULP_CLASS_HID_1d76, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2177] = { + .class_hid = BNXT_ULP_CLASS_HID_52ca, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2178] = { + .class_hid = BNXT_ULP_CLASS_HID_32a2, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2179] = { + .class_hid = BNXT_ULP_CLASS_HID_34f6, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2180] = { + .class_hid = BNXT_ULP_CLASS_HID_3a3a, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2181] = { + .class_hid = BNXT_ULP_CLASS_HID_09ca, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 191, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2182] = { + .class_hid = BNXT_ULP_CLASS_HID_0216, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 191, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2183] = { + .class_hid = BNXT_ULP_CLASS_HID_1f62, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 192, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2184] = { + .class_hid = BNXT_ULP_CLASS_HID_1bae, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 193, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2185] = { + .class_hid = BNXT_ULP_CLASS_HID_2932, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 194, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2186] = { + .class_hid = BNXT_ULP_CLASS_HID_227e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 194, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2187] = { + .class_hid = BNXT_ULP_CLASS_HID_3f4a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 194, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2188] = { + .class_hid = BNXT_ULP_CLASS_HID_3b96, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 194, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2189] = { + .class_hid = BNXT_ULP_CLASS_HID_0392, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 194, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2190] = { + .class_hid = BNXT_ULP_CLASS_HID_1cde, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 194, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2191] = { + .class_hid = BNXT_ULP_CLASS_HID_192a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 195, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2192] = { + .class_hid = BNXT_ULP_CLASS_HID_1276, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 196, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2193] = { + .class_hid = BNXT_ULP_CLASS_HID_5f5e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2194] = { + .class_hid = BNXT_ULP_CLASS_HID_5baa, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2195] = { + .class_hid = BNXT_ULP_CLASS_HID_54f6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2196] = { + .class_hid = BNXT_ULP_CLASS_HID_51c2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2197] = { + .class_hid = BNXT_ULP_CLASS_HID_0386, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2198] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2199] = { + .class_hid = BNXT_ULP_CLASS_HID_191e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2200] = { + .class_hid = BNXT_ULP_CLASS_HID_126a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2201] = { + .class_hid = BNXT_ULP_CLASS_HID_23ee, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2202] = { + .class_hid = BNXT_ULP_CLASS_HID_3c3a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2203] = { + .class_hid = BNXT_ULP_CLASS_HID_3906, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2204] = { + .class_hid = BNXT_ULP_CLASS_HID_3252, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2205] = { + .class_hid = BNXT_ULP_CLASS_HID_1a4e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2206] = { + .class_hid = BNXT_ULP_CLASS_HID_169a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2207] = { + .class_hid = BNXT_ULP_CLASS_HID_13e6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2208] = { + .class_hid = BNXT_ULP_CLASS_HID_4be6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2209] = { + .class_hid = BNXT_ULP_CLASS_HID_591a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2210] = { + .class_hid = BNXT_ULP_CLASS_HID_5266, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2211] = { + .class_hid = BNXT_ULP_CLASS_HID_2eb2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2212] = { + .class_hid = BNXT_ULP_CLASS_HID_2bfe, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2213] = { + .class_hid = BNXT_ULP_CLASS_HID_4dee, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2214] = { + .class_hid = BNXT_ULP_CLASS_HID_463a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 197, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2215] = { + .class_hid = BNXT_ULP_CLASS_HID_4306, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 198, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2216] = { + .class_hid = BNXT_ULP_CLASS_HID_5c52, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 199, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2217] = { + .class_hid = BNXT_ULP_CLASS_HID_0e22, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 200, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2218] = { + .class_hid = BNXT_ULP_CLASS_HID_0b6e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 200, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2219] = { + .class_hid = BNXT_ULP_CLASS_HID_07ba, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 200, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2220] = { + .class_hid = BNXT_ULP_CLASS_HID_0086, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 200, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2221] = { + .class_hid = BNXT_ULP_CLASS_HID_47b6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 200, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2222] = { + .class_hid = BNXT_ULP_CLASS_HID_4082, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 200, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2223] = { + .class_hid = BNXT_ULP_CLASS_HID_5dce, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 201, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2224] = { + .class_hid = BNXT_ULP_CLASS_HID_561a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 202, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2225] = { + .class_hid = BNXT_ULP_CLASS_HID_244e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2226] = { + .class_hid = BNXT_ULP_CLASS_HID_209a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2227] = { + .class_hid = BNXT_ULP_CLASS_HID_3de6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2228] = { + .class_hid = BNXT_ULP_CLASS_HID_3632, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2229] = { + .class_hid = BNXT_ULP_CLASS_HID_47aa, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2230] = { + .class_hid = BNXT_ULP_CLASS_HID_40f6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2231] = { + .class_hid = BNXT_ULP_CLASS_HID_5dc2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2232] = { + .class_hid = BNXT_ULP_CLASS_HID_560e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2233] = { + .class_hid = BNXT_ULP_CLASS_HID_08de, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2234] = { + .class_hid = BNXT_ULP_CLASS_HID_052a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2235] = { + .class_hid = BNXT_ULP_CLASS_HID_1e76, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2236] = { + .class_hid = BNXT_ULP_CLASS_HID_1b42, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2237] = { + .class_hid = BNXT_ULP_CLASS_HID_5e72, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2238] = { + .class_hid = BNXT_ULP_CLASS_HID_5abe, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2239] = { + .class_hid = BNXT_ULP_CLASS_HID_578a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2240] = { + .class_hid = BNXT_ULP_CLASS_HID_50d6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2241] = { + .class_hid = BNXT_ULP_CLASS_HID_3e0a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2242] = { + .class_hid = BNXT_ULP_CLASS_HID_3b56, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2243] = { + .class_hid = BNXT_ULP_CLASS_HID_37a2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2244] = { + .class_hid = BNXT_ULP_CLASS_HID_30ee, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2245] = { + .class_hid = BNXT_ULP_CLASS_HID_5e66, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2246] = { + .class_hid = BNXT_ULP_CLASS_HID_5ab2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 203, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2247] = { + .class_hid = BNXT_ULP_CLASS_HID_57fe, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 204, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2248] = { + .class_hid = BNXT_ULP_CLASS_HID_50ca, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 205, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2249] = { + .class_hid = BNXT_ULP_CLASS_HID_029a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 206, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2250] = { + .class_hid = BNXT_ULP_CLASS_HID_1fe6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 206, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2251] = { + .class_hid = BNXT_ULP_CLASS_HID_1832, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 206, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2252] = { + .class_hid = BNXT_ULP_CLASS_HID_157e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 206, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2253] = { + .class_hid = BNXT_ULP_CLASS_HID_582e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 206, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2254] = { + .class_hid = BNXT_ULP_CLASS_HID_557a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 206, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2255] = { + .class_hid = BNXT_ULP_CLASS_HID_2e46, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 207, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2256] = { + .class_hid = BNXT_ULP_CLASS_HID_2a92, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 208, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2257] = { + .class_hid = BNXT_ULP_CLASS_HID_38c6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2258] = { + .class_hid = BNXT_ULP_CLASS_HID_3512, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2259] = { + .class_hid = BNXT_ULP_CLASS_HID_0e5e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2260] = { + .class_hid = BNXT_ULP_CLASS_HID_0aaa, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2261] = { + .class_hid = BNXT_ULP_CLASS_HID_5822, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2262] = { + .class_hid = BNXT_ULP_CLASS_HID_556e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2263] = { + .class_hid = BNXT_ULP_CLASS_HID_51ba, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2264] = { + .class_hid = BNXT_ULP_CLASS_HID_2a86, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2265] = { + .class_hid = BNXT_ULP_CLASS_HID_1d56, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2266] = { + .class_hid = BNXT_ULP_CLASS_HID_19a2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2267] = { + .class_hid = BNXT_ULP_CLASS_HID_12ee, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2268] = { + .class_hid = BNXT_ULP_CLASS_HID_4aee, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2269] = { + .class_hid = BNXT_ULP_CLASS_HID_52ea, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2270] = { + .class_hid = BNXT_ULP_CLASS_HID_2f36, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2271] = { + .class_hid = BNXT_ULP_CLASS_HID_2802, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2272] = { + .class_hid = BNXT_ULP_CLASS_HID_254e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2273] = { + .class_hid = BNXT_ULP_CLASS_HID_3282, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2274] = { + .class_hid = BNXT_ULP_CLASS_HID_0fce, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2275] = { + .class_hid = BNXT_ULP_CLASS_HID_081a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2276] = { + .class_hid = BNXT_ULP_CLASS_HID_0566, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2277] = { + .class_hid = BNXT_ULP_CLASS_HID_34d6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2278] = { + .class_hid = BNXT_ULP_CLASS_HID_3a1a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2279] = { + .class_hid = BNXT_ULP_CLASS_HID_09aa, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 209, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2280] = { + .class_hid = BNXT_ULP_CLASS_HID_0276, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 209, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2281] = { + .class_hid = BNXT_ULP_CLASS_HID_1f02, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 210, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2282] = { + .class_hid = BNXT_ULP_CLASS_HID_1bce, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 211, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2283] = { + .class_hid = BNXT_ULP_CLASS_HID_2952, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 212, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2284] = { + .class_hid = BNXT_ULP_CLASS_HID_221e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 212, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2285] = { + .class_hid = BNXT_ULP_CLASS_HID_3f2a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 212, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2286] = { + .class_hid = BNXT_ULP_CLASS_HID_3bf6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 212, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2287] = { + .class_hid = BNXT_ULP_CLASS_HID_03f2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 212, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2288] = { + .class_hid = BNXT_ULP_CLASS_HID_1cbe, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 212, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2289] = { + .class_hid = BNXT_ULP_CLASS_HID_194a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 213, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2290] = { + .class_hid = BNXT_ULP_CLASS_HID_1216, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 214, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2291] = { + .class_hid = BNXT_ULP_CLASS_HID_5f3e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2292] = { + .class_hid = BNXT_ULP_CLASS_HID_5bca, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2293] = { + .class_hid = BNXT_ULP_CLASS_HID_5496, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2294] = { + .class_hid = BNXT_ULP_CLASS_HID_51a2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2295] = { + .class_hid = BNXT_ULP_CLASS_HID_03e6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2296] = { + .class_hid = BNXT_ULP_CLASS_HID_1cb2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2297] = { + .class_hid = BNXT_ULP_CLASS_HID_197e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2298] = { + .class_hid = BNXT_ULP_CLASS_HID_120a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2299] = { + .class_hid = BNXT_ULP_CLASS_HID_238e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2300] = { + .class_hid = BNXT_ULP_CLASS_HID_3c5a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2301] = { + .class_hid = BNXT_ULP_CLASS_HID_3966, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2302] = { + .class_hid = BNXT_ULP_CLASS_HID_3232, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2303] = { + .class_hid = BNXT_ULP_CLASS_HID_1a2e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2304] = { + .class_hid = BNXT_ULP_CLASS_HID_16fa, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2305] = { + .class_hid = BNXT_ULP_CLASS_HID_1386, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2306] = { + .class_hid = BNXT_ULP_CLASS_HID_4b86, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2307] = { + .class_hid = BNXT_ULP_CLASS_HID_597a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2308] = { + .class_hid = BNXT_ULP_CLASS_HID_5206, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2309] = { + .class_hid = BNXT_ULP_CLASS_HID_2ed2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2310] = { + .class_hid = BNXT_ULP_CLASS_HID_2b9e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2311] = { + .class_hid = BNXT_ULP_CLASS_HID_4d8e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2312] = { + .class_hid = BNXT_ULP_CLASS_HID_465a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 215, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2313] = { + .class_hid = BNXT_ULP_CLASS_HID_4366, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2314] = { + .class_hid = BNXT_ULP_CLASS_HID_5c32, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 217, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2315] = { + .class_hid = BNXT_ULP_CLASS_HID_0e42, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 218, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2316] = { + .class_hid = BNXT_ULP_CLASS_HID_0b0e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 218, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2317] = { + .class_hid = BNXT_ULP_CLASS_HID_07da, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 218, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2318] = { + .class_hid = BNXT_ULP_CLASS_HID_00e6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 218, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2319] = { + .class_hid = BNXT_ULP_CLASS_HID_47d6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 218, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2320] = { + .class_hid = BNXT_ULP_CLASS_HID_40e2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 218, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2321] = { + .class_hid = BNXT_ULP_CLASS_HID_5dae, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 219, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2322] = { + .class_hid = BNXT_ULP_CLASS_HID_567a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2323] = { + .class_hid = BNXT_ULP_CLASS_HID_242e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2324] = { + .class_hid = BNXT_ULP_CLASS_HID_20fa, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2325] = { + .class_hid = BNXT_ULP_CLASS_HID_3d86, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2326] = { + .class_hid = BNXT_ULP_CLASS_HID_3652, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2327] = { + .class_hid = BNXT_ULP_CLASS_HID_47ca, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2328] = { + .class_hid = BNXT_ULP_CLASS_HID_4096, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2329] = { + .class_hid = BNXT_ULP_CLASS_HID_5da2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2330] = { + .class_hid = BNXT_ULP_CLASS_HID_566e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2331] = { + .class_hid = BNXT_ULP_CLASS_HID_08be, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2332] = { + .class_hid = BNXT_ULP_CLASS_HID_054a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2333] = { + .class_hid = BNXT_ULP_CLASS_HID_1e16, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2334] = { + .class_hid = BNXT_ULP_CLASS_HID_1b22, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2335] = { + .class_hid = BNXT_ULP_CLASS_HID_5e12, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2336] = { + .class_hid = BNXT_ULP_CLASS_HID_5ade, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2337] = { + .class_hid = BNXT_ULP_CLASS_HID_57ea, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2338] = { + .class_hid = BNXT_ULP_CLASS_HID_50b6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2339] = { + .class_hid = BNXT_ULP_CLASS_HID_3e6a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2340] = { + .class_hid = BNXT_ULP_CLASS_HID_3b36, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2341] = { + .class_hid = BNXT_ULP_CLASS_HID_37c2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2342] = { + .class_hid = BNXT_ULP_CLASS_HID_308e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2343] = { + .class_hid = BNXT_ULP_CLASS_HID_5e06, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2344] = { + .class_hid = BNXT_ULP_CLASS_HID_5ad2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 221, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2345] = { + .class_hid = BNXT_ULP_CLASS_HID_579e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 222, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2346] = { + .class_hid = BNXT_ULP_CLASS_HID_50aa, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 223, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2347] = { + .class_hid = BNXT_ULP_CLASS_HID_02fa, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 224, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2348] = { + .class_hid = BNXT_ULP_CLASS_HID_1f86, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 224, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2349] = { + .class_hid = BNXT_ULP_CLASS_HID_1852, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 224, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2350] = { + .class_hid = BNXT_ULP_CLASS_HID_151e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 224, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2351] = { + .class_hid = BNXT_ULP_CLASS_HID_584e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 224, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2352] = { + .class_hid = BNXT_ULP_CLASS_HID_551a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 224, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2353] = { + .class_hid = BNXT_ULP_CLASS_HID_2e26, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 225, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2354] = { + .class_hid = BNXT_ULP_CLASS_HID_2af2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 226, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2355] = { + .class_hid = BNXT_ULP_CLASS_HID_38a6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2356] = { + .class_hid = BNXT_ULP_CLASS_HID_3572, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2357] = { + .class_hid = BNXT_ULP_CLASS_HID_0e3e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2358] = { + .class_hid = BNXT_ULP_CLASS_HID_0aca, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2359] = { + .class_hid = BNXT_ULP_CLASS_HID_5842, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2360] = { + .class_hid = BNXT_ULP_CLASS_HID_550e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2361] = { + .class_hid = BNXT_ULP_CLASS_HID_51da, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2362] = { + .class_hid = BNXT_ULP_CLASS_HID_2ae6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2363] = { + .class_hid = BNXT_ULP_CLASS_HID_1d36, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2364] = { + .class_hid = BNXT_ULP_CLASS_HID_19c2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2365] = { + .class_hid = BNXT_ULP_CLASS_HID_128e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2366] = { + .class_hid = BNXT_ULP_CLASS_HID_4a8e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2367] = { + .class_hid = BNXT_ULP_CLASS_HID_528a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2368] = { + .class_hid = BNXT_ULP_CLASS_HID_2f56, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2369] = { + .class_hid = BNXT_ULP_CLASS_HID_2862, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2370] = { + .class_hid = BNXT_ULP_CLASS_HID_252e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2371] = { + .class_hid = BNXT_ULP_CLASS_HID_32e2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2372] = { + .class_hid = BNXT_ULP_CLASS_HID_0fae, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2373] = { + .class_hid = BNXT_ULP_CLASS_HID_087a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2374] = { + .class_hid = BNXT_ULP_CLASS_HID_0506, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2375] = { + .class_hid = BNXT_ULP_CLASS_HID_34b6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2376] = { + .class_hid = BNXT_ULP_CLASS_HID_3a7a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2377] = { + .class_hid = BNXT_ULP_CLASS_HID_a73c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2378] = { + .class_hid = BNXT_ULP_CLASS_HID_a040, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2379] = { + .class_hid = BNXT_ULP_CLASS_HID_1d640, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2380] = { + .class_hid = BNXT_ULP_CLASS_HID_1dd3c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2381] = { + .class_hid = BNXT_ULP_CLASS_HID_cba0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2382] = { + .class_hid = BNXT_ULP_CLASS_HID_c4f4, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2383] = { + .class_hid = BNXT_ULP_CLASS_HID_19f38, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2384] = { + .class_hid = BNXT_ULP_CLASS_HID_182f4, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2385] = { + .class_hid = BNXT_ULP_CLASS_HID_b098, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 227, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2386] = { + .class_hid = BNXT_ULP_CLASS_HID_8dac, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 228, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2387] = { + .class_hid = BNXT_ULP_CLASS_HID_1a3ac, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 228, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2388] = { + .class_hid = BNXT_ULP_CLASS_HID_1a698, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2389] = { + .class_hid = BNXT_ULP_CLASS_HID_d50c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2390] = { + .class_hid = BNXT_ULP_CLASS_HID_ae50, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2391] = { + .class_hid = BNXT_ULP_CLASS_HID_1c450, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2392] = { + .class_hid = BNXT_ULP_CLASS_HID_1cb0c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2393] = { + .class_hid = BNXT_ULP_CLASS_HID_a1f0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2394] = { + .class_hid = BNXT_ULP_CLASS_HID_ba04, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2395] = { + .class_hid = BNXT_ULP_CLASS_HID_1d004, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2396] = { + .class_hid = BNXT_ULP_CLASS_HID_1d7f0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2397] = { + .class_hid = BNXT_ULP_CLASS_HID_c264, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2398] = { + .class_hid = BNXT_ULP_CLASS_HID_dea8, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2399] = { + .class_hid = BNXT_ULP_CLASS_HID_199fc, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2400] = { + .class_hid = BNXT_ULP_CLASS_HID_19ca8, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2401] = { + .class_hid = BNXT_ULP_CLASS_HID_8b5c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2402] = { + .class_hid = BNXT_ULP_CLASS_HID_8460, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2403] = { + .class_hid = BNXT_ULP_CLASS_HID_1ba60, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2404] = { + .class_hid = BNXT_ULP_CLASS_HID_1a15c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2405] = { + .class_hid = BNXT_ULP_CLASS_HID_afc0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2406] = { + .class_hid = BNXT_ULP_CLASS_HID_a814, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2407] = { + .class_hid = BNXT_ULP_CLASS_HID_1de14, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2408] = { + .class_hid = BNXT_ULP_CLASS_HID_1c5c0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2409] = { + .class_hid = BNXT_ULP_CLASS_HID_8c2c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2410] = { + .class_hid = BNXT_ULP_CLASS_HID_8970, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2411] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf70, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2412] = { + .class_hid = BNXT_ULP_CLASS_HID_1a22c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2413] = { + .class_hid = BNXT_ULP_CLASS_HID_d0d0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2414] = { + .class_hid = BNXT_ULP_CLASS_HID_ade4, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2415] = { + .class_hid = BNXT_ULP_CLASS_HID_1c3e4, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2416] = { + .class_hid = BNXT_ULP_CLASS_HID_1c6d0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2417] = { + .class_hid = BNXT_ULP_CLASS_HID_9988, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 229, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2418] = { + .class_hid = BNXT_ULP_CLASS_HID_92dc, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 230, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2419] = { + .class_hid = BNXT_ULP_CLASS_HID_188dc, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 230, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2420] = { + .class_hid = BNXT_ULP_CLASS_HID_18f88, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2421] = { + .class_hid = BNXT_ULP_CLASS_HID_ba3c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2422] = { + .class_hid = BNXT_ULP_CLASS_HID_b740, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2423] = { + .class_hid = BNXT_ULP_CLASS_HID_1ad40, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2424] = { + .class_hid = BNXT_ULP_CLASS_HID_1d03c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2425] = { + .class_hid = BNXT_ULP_CLASS_HID_86e0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2426] = { + .class_hid = BNXT_ULP_CLASS_HID_8334, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2427] = { + .class_hid = BNXT_ULP_CLASS_HID_1b934, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2428] = { + .class_hid = BNXT_ULP_CLASS_HID_1bce0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2429] = { + .class_hid = BNXT_ULP_CLASS_HID_aa94, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2430] = { + .class_hid = BNXT_ULP_CLASS_HID_a7d8, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2431] = { + .class_hid = BNXT_ULP_CLASS_HID_1ddd8, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2432] = { + .class_hid = BNXT_ULP_CLASS_HID_1c094, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2433] = { + .class_hid = BNXT_ULP_CLASS_HID_904c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2434] = { + .class_hid = BNXT_ULP_CLASS_HID_c84c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2435] = { + .class_hid = BNXT_ULP_CLASS_HID_18290, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2436] = { + .class_hid = BNXT_ULP_CLASS_HID_1864c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2437] = { + .class_hid = BNXT_ULP_CLASS_HID_b4f0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2438] = { + .class_hid = BNXT_ULP_CLASS_HID_b104, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2439] = { + .class_hid = BNXT_ULP_CLASS_HID_1a704, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2440] = { + .class_hid = BNXT_ULP_CLASS_HID_1aaf0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2441] = { + .class_hid = BNXT_ULP_CLASS_HID_80a4, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2442] = { + .class_hid = BNXT_ULP_CLASS_HID_9de8, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2443] = { + .class_hid = BNXT_ULP_CLASS_HID_1b3e8, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2444] = { + .class_hid = BNXT_ULP_CLASS_HID_1b6a4, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2445] = { + .class_hid = BNXT_ULP_CLASS_HID_a548, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2446] = { + .class_hid = BNXT_ULP_CLASS_HID_a19c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2447] = { + .class_hid = BNXT_ULP_CLASS_HID_1d79c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2448] = { + .class_hid = BNXT_ULP_CLASS_HID_1db48, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2449] = { + .class_hid = BNXT_ULP_CLASS_HID_9a98, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2450] = { + .class_hid = BNXT_ULP_CLASS_HID_97ac, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2451] = { + .class_hid = BNXT_ULP_CLASS_HID_18dac, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2452] = { + .class_hid = BNXT_ULP_CLASS_HID_1b098, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2453] = { + .class_hid = BNXT_ULP_CLASS_HID_bf0c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2454] = { + .class_hid = BNXT_ULP_CLASS_HID_b850, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2455] = { + .class_hid = BNXT_ULP_CLASS_HID_1ae50, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2456] = { + .class_hid = BNXT_ULP_CLASS_HID_1d50c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2457] = { + .class_hid = BNXT_ULP_CLASS_HID_34f0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2458] = { + .class_hid = BNXT_ULP_CLASS_HID_3a3c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2459] = { + .class_hid = BNXT_ULP_CLASS_HID_5ea0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2460] = { + .class_hid = BNXT_ULP_CLASS_HID_0798, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2461] = { + .class_hid = BNXT_ULP_CLASS_HID_280c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2462] = { + .class_hid = BNXT_ULP_CLASS_HID_5964, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2463] = { + .class_hid = BNXT_ULP_CLASS_HID_1e5c, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2464] = { + .class_hid = BNXT_ULP_CLASS_HID_22c0, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2465] = { + .class_hid = BNXT_ULP_CLASS_HID_a71c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2466] = { + .class_hid = BNXT_ULP_CLASS_HID_a8dc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2467] = { + .class_hid = BNXT_ULP_CLASS_HID_ed9c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2468] = { + .class_hid = BNXT_ULP_CLASS_HID_ef5c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2469] = { + .class_hid = BNXT_ULP_CLASS_HID_a060, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2470] = { + .class_hid = BNXT_ULP_CLASS_HID_a520, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2471] = { + .class_hid = BNXT_ULP_CLASS_HID_e6e0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2472] = { + .class_hid = BNXT_ULP_CLASS_HID_eba0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2473] = { + .class_hid = BNXT_ULP_CLASS_HID_1d660, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2474] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb20, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2475] = { + .class_hid = BNXT_ULP_CLASS_HID_1dce0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2476] = { + .class_hid = BNXT_ULP_CLASS_HID_1e1a0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2477] = { + .class_hid = BNXT_ULP_CLASS_HID_1dd1c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2478] = { + .class_hid = BNXT_ULP_CLASS_HID_1fedc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2479] = { + .class_hid = BNXT_ULP_CLASS_HID_1c39c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2480] = { + .class_hid = BNXT_ULP_CLASS_HID_1e55c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2481] = { + .class_hid = BNXT_ULP_CLASS_HID_cb80, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2482] = { + .class_hid = BNXT_ULP_CLASS_HID_b194, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2483] = { + .class_hid = BNXT_ULP_CLASS_HID_d354, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2484] = { + .class_hid = BNXT_ULP_CLASS_HID_f414, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2485] = { + .class_hid = BNXT_ULP_CLASS_HID_c4d4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2486] = { + .class_hid = BNXT_ULP_CLASS_HID_e994, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2487] = { + .class_hid = BNXT_ULP_CLASS_HID_cb54, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2488] = { + .class_hid = BNXT_ULP_CLASS_HID_f158, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2489] = { + .class_hid = BNXT_ULP_CLASS_HID_19f18, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2490] = { + .class_hid = BNXT_ULP_CLASS_HID_1a0d8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2491] = { + .class_hid = BNXT_ULP_CLASS_HID_1c598, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2492] = { + .class_hid = BNXT_ULP_CLASS_HID_1e758, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2493] = { + .class_hid = BNXT_ULP_CLASS_HID_182d4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2494] = { + .class_hid = BNXT_ULP_CLASS_HID_1a794, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2495] = { + .class_hid = BNXT_ULP_CLASS_HID_1c954, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2496] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea14, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2497] = { + .class_hid = BNXT_ULP_CLASS_HID_b0b8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2498] = { + .class_hid = BNXT_ULP_CLASS_HID_b278, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 232, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2499] = { + .class_hid = BNXT_ULP_CLASS_HID_f738, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 233, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2500] = { + .class_hid = BNXT_ULP_CLASS_HID_f8f8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 234, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2501] = { + .class_hid = BNXT_ULP_CLASS_HID_8d8c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 235, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2502] = { + .class_hid = BNXT_ULP_CLASS_HID_af4c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 235, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2503] = { + .class_hid = BNXT_ULP_CLASS_HID_f00c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 235, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2504] = { + .class_hid = BNXT_ULP_CLASS_HID_f5cc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 235, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2505] = { + .class_hid = BNXT_ULP_CLASS_HID_1a38c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 235, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2506] = { + .class_hid = BNXT_ULP_CLASS_HID_1a54c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 235, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2507] = { + .class_hid = BNXT_ULP_CLASS_HID_1e60c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 236, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2508] = { + .class_hid = BNXT_ULP_CLASS_HID_1ebcc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 237, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2509] = { + .class_hid = BNXT_ULP_CLASS_HID_1a6b8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2510] = { + .class_hid = BNXT_ULP_CLASS_HID_1a878, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2511] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed38, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2512] = { + .class_hid = BNXT_ULP_CLASS_HID_1eef8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2513] = { + .class_hid = BNXT_ULP_CLASS_HID_d52c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2514] = { + .class_hid = BNXT_ULP_CLASS_HID_f6ec, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2515] = { + .class_hid = BNXT_ULP_CLASS_HID_dbac, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2516] = { + .class_hid = BNXT_ULP_CLASS_HID_fd6c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2517] = { + .class_hid = BNXT_ULP_CLASS_HID_ae70, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2518] = { + .class_hid = BNXT_ULP_CLASS_HID_f330, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2519] = { + .class_hid = BNXT_ULP_CLASS_HID_d4f0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2520] = { + .class_hid = BNXT_ULP_CLASS_HID_f9b0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2521] = { + .class_hid = BNXT_ULP_CLASS_HID_1c470, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2522] = { + .class_hid = BNXT_ULP_CLASS_HID_1e930, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2523] = { + .class_hid = BNXT_ULP_CLASS_HID_1caf0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2524] = { + .class_hid = BNXT_ULP_CLASS_HID_1f084, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2525] = { + .class_hid = BNXT_ULP_CLASS_HID_1cb2c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2526] = { + .class_hid = BNXT_ULP_CLASS_HID_1b130, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2527] = { + .class_hid = BNXT_ULP_CLASS_HID_1d2f0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2528] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7b0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2529] = { + .class_hid = BNXT_ULP_CLASS_HID_a1d0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2530] = { + .class_hid = BNXT_ULP_CLASS_HID_a290, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2531] = { + .class_hid = BNXT_ULP_CLASS_HID_e450, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2532] = { + .class_hid = BNXT_ULP_CLASS_HID_e910, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2533] = { + .class_hid = BNXT_ULP_CLASS_HID_ba24, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2534] = { + .class_hid = BNXT_ULP_CLASS_HID_bfe4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2535] = { + .class_hid = BNXT_ULP_CLASS_HID_e0a4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2536] = { + .class_hid = BNXT_ULP_CLASS_HID_e264, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2537] = { + .class_hid = BNXT_ULP_CLASS_HID_1d024, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2538] = { + .class_hid = BNXT_ULP_CLASS_HID_1f5e4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2539] = { + .class_hid = BNXT_ULP_CLASS_HID_1d6a4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2540] = { + .class_hid = BNXT_ULP_CLASS_HID_1f864, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2541] = { + .class_hid = BNXT_ULP_CLASS_HID_1d7d0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2542] = { + .class_hid = BNXT_ULP_CLASS_HID_1f890, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2543] = { + .class_hid = BNXT_ULP_CLASS_HID_1da50, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2544] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff10, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2545] = { + .class_hid = BNXT_ULP_CLASS_HID_c244, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2546] = { + .class_hid = BNXT_ULP_CLASS_HID_e704, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2547] = { + .class_hid = BNXT_ULP_CLASS_HID_c8c4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2548] = { + .class_hid = BNXT_ULP_CLASS_HID_ed84, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2549] = { + .class_hid = BNXT_ULP_CLASS_HID_de88, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2550] = { + .class_hid = BNXT_ULP_CLASS_HID_e048, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2551] = { + .class_hid = BNXT_ULP_CLASS_HID_c508, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2552] = { + .class_hid = BNXT_ULP_CLASS_HID_e6c8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2553] = { + .class_hid = BNXT_ULP_CLASS_HID_199dc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2554] = { + .class_hid = BNXT_ULP_CLASS_HID_1ba9c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2555] = { + .class_hid = BNXT_ULP_CLASS_HID_1dc5c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2556] = { + .class_hid = BNXT_ULP_CLASS_HID_1e11c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2557] = { + .class_hid = BNXT_ULP_CLASS_HID_19c88, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2558] = { + .class_hid = BNXT_ULP_CLASS_HID_1be48, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2559] = { + .class_hid = BNXT_ULP_CLASS_HID_1c308, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2560] = { + .class_hid = BNXT_ULP_CLASS_HID_1e4c8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2561] = { + .class_hid = BNXT_ULP_CLASS_HID_8b7c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2562] = { + .class_hid = BNXT_ULP_CLASS_HID_ac3c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2563] = { + .class_hid = BNXT_ULP_CLASS_HID_f1fc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2564] = { + .class_hid = BNXT_ULP_CLASS_HID_f2bc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2565] = { + .class_hid = BNXT_ULP_CLASS_HID_8440, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2566] = { + .class_hid = BNXT_ULP_CLASS_HID_a900, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2567] = { + .class_hid = BNXT_ULP_CLASS_HID_cac0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2568] = { + .class_hid = BNXT_ULP_CLASS_HID_ef80, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2569] = { + .class_hid = BNXT_ULP_CLASS_HID_1ba40, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2570] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf00, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2571] = { + .class_hid = BNXT_ULP_CLASS_HID_1e0c0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2572] = { + .class_hid = BNXT_ULP_CLASS_HID_1e580, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2573] = { + .class_hid = BNXT_ULP_CLASS_HID_1a17c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2574] = { + .class_hid = BNXT_ULP_CLASS_HID_1a23c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2575] = { + .class_hid = BNXT_ULP_CLASS_HID_1e7fc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2576] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8bc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2577] = { + .class_hid = BNXT_ULP_CLASS_HID_afe0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2578] = { + .class_hid = BNXT_ULP_CLASS_HID_f0a0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2579] = { + .class_hid = BNXT_ULP_CLASS_HID_d260, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2580] = { + .class_hid = BNXT_ULP_CLASS_HID_f720, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2581] = { + .class_hid = BNXT_ULP_CLASS_HID_a834, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2582] = { + .class_hid = BNXT_ULP_CLASS_HID_adf4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2583] = { + .class_hid = BNXT_ULP_CLASS_HID_eeb4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2584] = { + .class_hid = BNXT_ULP_CLASS_HID_f074, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2585] = { + .class_hid = BNXT_ULP_CLASS_HID_1de34, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2586] = { + .class_hid = BNXT_ULP_CLASS_HID_1e3f4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2587] = { + .class_hid = BNXT_ULP_CLASS_HID_1c4b4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2588] = { + .class_hid = BNXT_ULP_CLASS_HID_1e674, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2589] = { + .class_hid = BNXT_ULP_CLASS_HID_1c5e0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2590] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6a0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2591] = { + .class_hid = BNXT_ULP_CLASS_HID_1c860, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2592] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed20, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2593] = { + .class_hid = BNXT_ULP_CLASS_HID_8c0c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2594] = { + .class_hid = BNXT_ULP_CLASS_HID_b1cc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2595] = { + .class_hid = BNXT_ULP_CLASS_HID_f28c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2596] = { + .class_hid = BNXT_ULP_CLASS_HID_f44c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2597] = { + .class_hid = BNXT_ULP_CLASS_HID_8950, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2598] = { + .class_hid = BNXT_ULP_CLASS_HID_aa10, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2599] = { + .class_hid = BNXT_ULP_CLASS_HID_cfd0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2600] = { + .class_hid = BNXT_ULP_CLASS_HID_f090, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2601] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf50, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2602] = { + .class_hid = BNXT_ULP_CLASS_HID_1a010, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2603] = { + .class_hid = BNXT_ULP_CLASS_HID_1e5d0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2604] = { + .class_hid = BNXT_ULP_CLASS_HID_1e690, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2605] = { + .class_hid = BNXT_ULP_CLASS_HID_1a20c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2606] = { + .class_hid = BNXT_ULP_CLASS_HID_1a7cc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2607] = { + .class_hid = BNXT_ULP_CLASS_HID_1e88c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2608] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea4c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2609] = { + .class_hid = BNXT_ULP_CLASS_HID_d0f0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2610] = { + .class_hid = BNXT_ULP_CLASS_HID_f5b0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2611] = { + .class_hid = BNXT_ULP_CLASS_HID_d770, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2612] = { + .class_hid = BNXT_ULP_CLASS_HID_f830, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2613] = { + .class_hid = BNXT_ULP_CLASS_HID_adc4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2614] = { + .class_hid = BNXT_ULP_CLASS_HID_ae84, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2615] = { + .class_hid = BNXT_ULP_CLASS_HID_d044, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2616] = { + .class_hid = BNXT_ULP_CLASS_HID_f504, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2617] = { + .class_hid = BNXT_ULP_CLASS_HID_1c3c4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2618] = { + .class_hid = BNXT_ULP_CLASS_HID_1e484, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2619] = { + .class_hid = BNXT_ULP_CLASS_HID_1c644, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2620] = { + .class_hid = BNXT_ULP_CLASS_HID_1eb04, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2621] = { + .class_hid = BNXT_ULP_CLASS_HID_1c6f0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2622] = { + .class_hid = BNXT_ULP_CLASS_HID_1ebb0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2623] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd70, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2624] = { + .class_hid = BNXT_ULP_CLASS_HID_1f304, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2625] = { + .class_hid = BNXT_ULP_CLASS_HID_99a8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2626] = { + .class_hid = BNXT_ULP_CLASS_HID_bb68, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 238, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2627] = { + .class_hid = BNXT_ULP_CLASS_HID_dc28, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 239, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2628] = { + .class_hid = BNXT_ULP_CLASS_HID_e1e8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 240, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2629] = { + .class_hid = BNXT_ULP_CLASS_HID_92fc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 241, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2630] = { + .class_hid = BNXT_ULP_CLASS_HID_b7bc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 241, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2631] = { + .class_hid = BNXT_ULP_CLASS_HID_d97c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 241, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2632] = { + .class_hid = BNXT_ULP_CLASS_HID_fa3c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 241, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2633] = { + .class_hid = BNXT_ULP_CLASS_HID_188fc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 241, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2634] = { + .class_hid = BNXT_ULP_CLASS_HID_1adbc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 241, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2635] = { + .class_hid = BNXT_ULP_CLASS_HID_1cf7c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 242, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2636] = { + .class_hid = BNXT_ULP_CLASS_HID_1f03c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 243, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2637] = { + .class_hid = BNXT_ULP_CLASS_HID_18fa8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2638] = { + .class_hid = BNXT_ULP_CLASS_HID_1b168, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2639] = { + .class_hid = BNXT_ULP_CLASS_HID_1f228, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2640] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7e8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2641] = { + .class_hid = BNXT_ULP_CLASS_HID_ba1c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2642] = { + .class_hid = BNXT_ULP_CLASS_HID_bfdc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2643] = { + .class_hid = BNXT_ULP_CLASS_HID_e09c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2644] = { + .class_hid = BNXT_ULP_CLASS_HID_e25c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2645] = { + .class_hid = BNXT_ULP_CLASS_HID_b760, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2646] = { + .class_hid = BNXT_ULP_CLASS_HID_b820, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2647] = { + .class_hid = BNXT_ULP_CLASS_HID_fde0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2648] = { + .class_hid = BNXT_ULP_CLASS_HID_fea0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2649] = { + .class_hid = BNXT_ULP_CLASS_HID_1ad60, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2650] = { + .class_hid = BNXT_ULP_CLASS_HID_1ae20, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2651] = { + .class_hid = BNXT_ULP_CLASS_HID_1d3e0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2652] = { + .class_hid = BNXT_ULP_CLASS_HID_1f4a0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2653] = { + .class_hid = BNXT_ULP_CLASS_HID_1d01c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2654] = { + .class_hid = BNXT_ULP_CLASS_HID_1f5dc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2655] = { + .class_hid = BNXT_ULP_CLASS_HID_1d69c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2656] = { + .class_hid = BNXT_ULP_CLASS_HID_1f85c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2657] = { + .class_hid = BNXT_ULP_CLASS_HID_86c0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2658] = { + .class_hid = BNXT_ULP_CLASS_HID_ab80, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2659] = { + .class_hid = BNXT_ULP_CLASS_HID_cd40, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2660] = { + .class_hid = BNXT_ULP_CLASS_HID_ee00, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2661] = { + .class_hid = BNXT_ULP_CLASS_HID_8314, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2662] = { + .class_hid = BNXT_ULP_CLASS_HID_a4d4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2663] = { + .class_hid = BNXT_ULP_CLASS_HID_c994, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2664] = { + .class_hid = BNXT_ULP_CLASS_HID_eb54, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2665] = { + .class_hid = BNXT_ULP_CLASS_HID_1b914, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2666] = { + .class_hid = BNXT_ULP_CLASS_HID_1bad4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2667] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff94, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2668] = { + .class_hid = BNXT_ULP_CLASS_HID_1e154, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2669] = { + .class_hid = BNXT_ULP_CLASS_HID_1bcc0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2670] = { + .class_hid = BNXT_ULP_CLASS_HID_1a180, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2671] = { + .class_hid = BNXT_ULP_CLASS_HID_1e340, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2672] = { + .class_hid = BNXT_ULP_CLASS_HID_1e400, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2673] = { + .class_hid = BNXT_ULP_CLASS_HID_aab4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2674] = { + .class_hid = BNXT_ULP_CLASS_HID_ac74, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2675] = { + .class_hid = BNXT_ULP_CLASS_HID_d134, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2676] = { + .class_hid = BNXT_ULP_CLASS_HID_f2f4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2677] = { + .class_hid = BNXT_ULP_CLASS_HID_a7f8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2678] = { + .class_hid = BNXT_ULP_CLASS_HID_a8b8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2679] = { + .class_hid = BNXT_ULP_CLASS_HID_ea78, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2680] = { + .class_hid = BNXT_ULP_CLASS_HID_ef38, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2681] = { + .class_hid = BNXT_ULP_CLASS_HID_1ddf8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2682] = { + .class_hid = BNXT_ULP_CLASS_HID_1feb8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2683] = { + .class_hid = BNXT_ULP_CLASS_HID_1c078, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2684] = { + .class_hid = BNXT_ULP_CLASS_HID_1e538, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2685] = { + .class_hid = BNXT_ULP_CLASS_HID_1c0b4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2686] = { + .class_hid = BNXT_ULP_CLASS_HID_1e274, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2687] = { + .class_hid = BNXT_ULP_CLASS_HID_1c734, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2688] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8f4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2689] = { + .class_hid = BNXT_ULP_CLASS_HID_906c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2690] = { + .class_hid = BNXT_ULP_CLASS_HID_b52c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2691] = { + .class_hid = BNXT_ULP_CLASS_HID_d6ec, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2692] = { + .class_hid = BNXT_ULP_CLASS_HID_fbac, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2693] = { + .class_hid = BNXT_ULP_CLASS_HID_c86c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2694] = { + .class_hid = BNXT_ULP_CLASS_HID_ed2c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2695] = { + .class_hid = BNXT_ULP_CLASS_HID_d330, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2696] = { + .class_hid = BNXT_ULP_CLASS_HID_f4f0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2697] = { + .class_hid = BNXT_ULP_CLASS_HID_182b0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2698] = { + .class_hid = BNXT_ULP_CLASS_HID_1a470, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2699] = { + .class_hid = BNXT_ULP_CLASS_HID_1c930, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2700] = { + .class_hid = BNXT_ULP_CLASS_HID_1eaf0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2701] = { + .class_hid = BNXT_ULP_CLASS_HID_1866c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2702] = { + .class_hid = BNXT_ULP_CLASS_HID_1ab2c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2703] = { + .class_hid = BNXT_ULP_CLASS_HID_1ccec, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2704] = { + .class_hid = BNXT_ULP_CLASS_HID_1f1ac, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2705] = { + .class_hid = BNXT_ULP_CLASS_HID_b4d0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2706] = { + .class_hid = BNXT_ULP_CLASS_HID_b990, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2707] = { + .class_hid = BNXT_ULP_CLASS_HID_fb50, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2708] = { + .class_hid = BNXT_ULP_CLASS_HID_fc10, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2709] = { + .class_hid = BNXT_ULP_CLASS_HID_b124, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2710] = { + .class_hid = BNXT_ULP_CLASS_HID_b2e4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2711] = { + .class_hid = BNXT_ULP_CLASS_HID_f7a4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2712] = { + .class_hid = BNXT_ULP_CLASS_HID_f964, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2713] = { + .class_hid = BNXT_ULP_CLASS_HID_1a724, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2714] = { + .class_hid = BNXT_ULP_CLASS_HID_1a8e4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2715] = { + .class_hid = BNXT_ULP_CLASS_HID_1eda4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2716] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef64, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2717] = { + .class_hid = BNXT_ULP_CLASS_HID_1aad0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2718] = { + .class_hid = BNXT_ULP_CLASS_HID_1af90, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2719] = { + .class_hid = BNXT_ULP_CLASS_HID_1d150, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2720] = { + .class_hid = BNXT_ULP_CLASS_HID_1f210, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2721] = { + .class_hid = BNXT_ULP_CLASS_HID_8084, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2722] = { + .class_hid = BNXT_ULP_CLASS_HID_a244, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2723] = { + .class_hid = BNXT_ULP_CLASS_HID_c704, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2724] = { + .class_hid = BNXT_ULP_CLASS_HID_e8c4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2725] = { + .class_hid = BNXT_ULP_CLASS_HID_9dc8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2726] = { + .class_hid = BNXT_ULP_CLASS_HID_be88, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2727] = { + .class_hid = BNXT_ULP_CLASS_HID_c048, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2728] = { + .class_hid = BNXT_ULP_CLASS_HID_e508, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2729] = { + .class_hid = BNXT_ULP_CLASS_HID_1b3c8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2730] = { + .class_hid = BNXT_ULP_CLASS_HID_1b488, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2731] = { + .class_hid = BNXT_ULP_CLASS_HID_1f648, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2732] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb08, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2733] = { + .class_hid = BNXT_ULP_CLASS_HID_1b684, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2734] = { + .class_hid = BNXT_ULP_CLASS_HID_1b844, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2735] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd04, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2736] = { + .class_hid = BNXT_ULP_CLASS_HID_1fec4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2737] = { + .class_hid = BNXT_ULP_CLASS_HID_a568, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2738] = { + .class_hid = BNXT_ULP_CLASS_HID_a628, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2739] = { + .class_hid = BNXT_ULP_CLASS_HID_ebe8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2740] = { + .class_hid = BNXT_ULP_CLASS_HID_eca8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2741] = { + .class_hid = BNXT_ULP_CLASS_HID_a1bc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2742] = { + .class_hid = BNXT_ULP_CLASS_HID_a37c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2743] = { + .class_hid = BNXT_ULP_CLASS_HID_e43c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2744] = { + .class_hid = BNXT_ULP_CLASS_HID_e9fc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2745] = { + .class_hid = BNXT_ULP_CLASS_HID_1d7bc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2746] = { + .class_hid = BNXT_ULP_CLASS_HID_1f97c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2747] = { + .class_hid = BNXT_ULP_CLASS_HID_1da3c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2748] = { + .class_hid = BNXT_ULP_CLASS_HID_1fffc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2749] = { + .class_hid = BNXT_ULP_CLASS_HID_1db68, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2750] = { + .class_hid = BNXT_ULP_CLASS_HID_1fc28, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2751] = { + .class_hid = BNXT_ULP_CLASS_HID_1c1e8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2752] = { + .class_hid = BNXT_ULP_CLASS_HID_1e2a8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2753] = { + .class_hid = BNXT_ULP_CLASS_HID_9ab8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2754] = { + .class_hid = BNXT_ULP_CLASS_HID_bc78, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2755] = { + .class_hid = BNXT_ULP_CLASS_HID_c138, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2756] = { + .class_hid = BNXT_ULP_CLASS_HID_e2f8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2757] = { + .class_hid = BNXT_ULP_CLASS_HID_978c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2758] = { + .class_hid = BNXT_ULP_CLASS_HID_b94c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2759] = { + .class_hid = BNXT_ULP_CLASS_HID_da0c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2760] = { + .class_hid = BNXT_ULP_CLASS_HID_ffcc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2761] = { + .class_hid = BNXT_ULP_CLASS_HID_18d8c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2762] = { + .class_hid = BNXT_ULP_CLASS_HID_1af4c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2763] = { + .class_hid = BNXT_ULP_CLASS_HID_1f00c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2764] = { + .class_hid = BNXT_ULP_CLASS_HID_1f5cc, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2765] = { + .class_hid = BNXT_ULP_CLASS_HID_1b0b8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2766] = { + .class_hid = BNXT_ULP_CLASS_HID_1b278, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2767] = { + .class_hid = BNXT_ULP_CLASS_HID_1f738, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2768] = { + .class_hid = BNXT_ULP_CLASS_HID_1f8f8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2769] = { + .class_hid = BNXT_ULP_CLASS_HID_bf2c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2770] = { + .class_hid = BNXT_ULP_CLASS_HID_a0ec, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2771] = { + .class_hid = BNXT_ULP_CLASS_HID_e5ac, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2772] = { + .class_hid = BNXT_ULP_CLASS_HID_e76c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2773] = { + .class_hid = BNXT_ULP_CLASS_HID_b870, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2774] = { + .class_hid = BNXT_ULP_CLASS_HID_bd30, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2775] = { + .class_hid = BNXT_ULP_CLASS_HID_fef0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2776] = { + .class_hid = BNXT_ULP_CLASS_HID_e3b0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2777] = { + .class_hid = BNXT_ULP_CLASS_HID_1ae70, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2778] = { + .class_hid = BNXT_ULP_CLASS_HID_1f330, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2779] = { + .class_hid = BNXT_ULP_CLASS_HID_1d4f0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2780] = { + .class_hid = BNXT_ULP_CLASS_HID_1f9b0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2781] = { + .class_hid = BNXT_ULP_CLASS_HID_1d52c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2782] = { + .class_hid = BNXT_ULP_CLASS_HID_1f6ec, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2783] = { + .class_hid = BNXT_ULP_CLASS_HID_1dbac, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2784] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd6c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2785] = { + .class_hid = BNXT_ULP_CLASS_HID_34d0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2786] = { + .class_hid = BNXT_ULP_CLASS_HID_3a1c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2787] = { + .class_hid = BNXT_ULP_CLASS_HID_5e80, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2788] = { + .class_hid = BNXT_ULP_CLASS_HID_07b8, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2789] = { + .class_hid = BNXT_ULP_CLASS_HID_282c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2790] = { + .class_hid = BNXT_ULP_CLASS_HID_5944, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2791] = { + .class_hid = BNXT_ULP_CLASS_HID_1e7c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2792] = { + .class_hid = BNXT_ULP_CLASS_HID_22e0, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2793] = { + .class_hid = BNXT_ULP_CLASS_HID_a77c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2794] = { + .class_hid = BNXT_ULP_CLASS_HID_a8bc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2795] = { + .class_hid = BNXT_ULP_CLASS_HID_edfc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2796] = { + .class_hid = BNXT_ULP_CLASS_HID_ef3c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2797] = { + .class_hid = BNXT_ULP_CLASS_HID_a000, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2798] = { + .class_hid = BNXT_ULP_CLASS_HID_a540, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2799] = { + .class_hid = BNXT_ULP_CLASS_HID_e680, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2800] = { + .class_hid = BNXT_ULP_CLASS_HID_ebc0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2801] = { + .class_hid = BNXT_ULP_CLASS_HID_1d600, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2802] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb40, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2803] = { + .class_hid = BNXT_ULP_CLASS_HID_1dc80, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2804] = { + .class_hid = BNXT_ULP_CLASS_HID_1e1c0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2805] = { + .class_hid = BNXT_ULP_CLASS_HID_1dd7c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2806] = { + .class_hid = BNXT_ULP_CLASS_HID_1febc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2807] = { + .class_hid = BNXT_ULP_CLASS_HID_1c3fc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2808] = { + .class_hid = BNXT_ULP_CLASS_HID_1e53c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2809] = { + .class_hid = BNXT_ULP_CLASS_HID_cbe0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2810] = { + .class_hid = BNXT_ULP_CLASS_HID_b1f4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2811] = { + .class_hid = BNXT_ULP_CLASS_HID_d334, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2812] = { + .class_hid = BNXT_ULP_CLASS_HID_f474, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2813] = { + .class_hid = BNXT_ULP_CLASS_HID_c4b4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2814] = { + .class_hid = BNXT_ULP_CLASS_HID_e9f4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2815] = { + .class_hid = BNXT_ULP_CLASS_HID_cb34, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2816] = { + .class_hid = BNXT_ULP_CLASS_HID_f138, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2817] = { + .class_hid = BNXT_ULP_CLASS_HID_19f78, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2818] = { + .class_hid = BNXT_ULP_CLASS_HID_1a0b8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2819] = { + .class_hid = BNXT_ULP_CLASS_HID_1c5f8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2820] = { + .class_hid = BNXT_ULP_CLASS_HID_1e738, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2821] = { + .class_hid = BNXT_ULP_CLASS_HID_182b4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2822] = { + .class_hid = BNXT_ULP_CLASS_HID_1a7f4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2823] = { + .class_hid = BNXT_ULP_CLASS_HID_1c934, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2824] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea74, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2825] = { + .class_hid = BNXT_ULP_CLASS_HID_b0d8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2826] = { + .class_hid = BNXT_ULP_CLASS_HID_b218, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 244, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2827] = { + .class_hid = BNXT_ULP_CLASS_HID_f758, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 245, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2828] = { + .class_hid = BNXT_ULP_CLASS_HID_f898, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 246, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2829] = { + .class_hid = BNXT_ULP_CLASS_HID_8dec, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 247, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2830] = { + .class_hid = BNXT_ULP_CLASS_HID_af2c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 247, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2831] = { + .class_hid = BNXT_ULP_CLASS_HID_f06c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 247, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2832] = { + .class_hid = BNXT_ULP_CLASS_HID_f5ac, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 247, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2833] = { + .class_hid = BNXT_ULP_CLASS_HID_1a3ec, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 247, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2834] = { + .class_hid = BNXT_ULP_CLASS_HID_1a52c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 247, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2835] = { + .class_hid = BNXT_ULP_CLASS_HID_1e66c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 248, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2836] = { + .class_hid = BNXT_ULP_CLASS_HID_1ebac, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 249, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2837] = { + .class_hid = BNXT_ULP_CLASS_HID_1a6d8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2838] = { + .class_hid = BNXT_ULP_CLASS_HID_1a818, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2839] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed58, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2840] = { + .class_hid = BNXT_ULP_CLASS_HID_1ee98, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2841] = { + .class_hid = BNXT_ULP_CLASS_HID_d54c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2842] = { + .class_hid = BNXT_ULP_CLASS_HID_f68c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2843] = { + .class_hid = BNXT_ULP_CLASS_HID_dbcc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2844] = { + .class_hid = BNXT_ULP_CLASS_HID_fd0c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2845] = { + .class_hid = BNXT_ULP_CLASS_HID_ae10, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2846] = { + .class_hid = BNXT_ULP_CLASS_HID_f350, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2847] = { + .class_hid = BNXT_ULP_CLASS_HID_d490, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2848] = { + .class_hid = BNXT_ULP_CLASS_HID_f9d0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2849] = { + .class_hid = BNXT_ULP_CLASS_HID_1c410, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2850] = { + .class_hid = BNXT_ULP_CLASS_HID_1e950, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2851] = { + .class_hid = BNXT_ULP_CLASS_HID_1ca90, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2852] = { + .class_hid = BNXT_ULP_CLASS_HID_1f0e4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2853] = { + .class_hid = BNXT_ULP_CLASS_HID_1cb4c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2854] = { + .class_hid = BNXT_ULP_CLASS_HID_1b150, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2855] = { + .class_hid = BNXT_ULP_CLASS_HID_1d290, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2856] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7d0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2857] = { + .class_hid = BNXT_ULP_CLASS_HID_a1b0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2858] = { + .class_hid = BNXT_ULP_CLASS_HID_a2f0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2859] = { + .class_hid = BNXT_ULP_CLASS_HID_e430, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2860] = { + .class_hid = BNXT_ULP_CLASS_HID_e970, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2861] = { + .class_hid = BNXT_ULP_CLASS_HID_ba44, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2862] = { + .class_hid = BNXT_ULP_CLASS_HID_bf84, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2863] = { + .class_hid = BNXT_ULP_CLASS_HID_e0c4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2864] = { + .class_hid = BNXT_ULP_CLASS_HID_e204, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2865] = { + .class_hid = BNXT_ULP_CLASS_HID_1d044, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2866] = { + .class_hid = BNXT_ULP_CLASS_HID_1f584, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2867] = { + .class_hid = BNXT_ULP_CLASS_HID_1d6c4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2868] = { + .class_hid = BNXT_ULP_CLASS_HID_1f804, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2869] = { + .class_hid = BNXT_ULP_CLASS_HID_1d7b0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2870] = { + .class_hid = BNXT_ULP_CLASS_HID_1f8f0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2871] = { + .class_hid = BNXT_ULP_CLASS_HID_1da30, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2872] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff70, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2873] = { + .class_hid = BNXT_ULP_CLASS_HID_c224, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2874] = { + .class_hid = BNXT_ULP_CLASS_HID_e764, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2875] = { + .class_hid = BNXT_ULP_CLASS_HID_c8a4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2876] = { + .class_hid = BNXT_ULP_CLASS_HID_ede4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2877] = { + .class_hid = BNXT_ULP_CLASS_HID_dee8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2878] = { + .class_hid = BNXT_ULP_CLASS_HID_e028, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2879] = { + .class_hid = BNXT_ULP_CLASS_HID_c568, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2880] = { + .class_hid = BNXT_ULP_CLASS_HID_e6a8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2881] = { + .class_hid = BNXT_ULP_CLASS_HID_199bc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2882] = { + .class_hid = BNXT_ULP_CLASS_HID_1bafc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2883] = { + .class_hid = BNXT_ULP_CLASS_HID_1dc3c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2884] = { + .class_hid = BNXT_ULP_CLASS_HID_1e17c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2885] = { + .class_hid = BNXT_ULP_CLASS_HID_19ce8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2886] = { + .class_hid = BNXT_ULP_CLASS_HID_1be28, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2887] = { + .class_hid = BNXT_ULP_CLASS_HID_1c368, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2888] = { + .class_hid = BNXT_ULP_CLASS_HID_1e4a8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2889] = { + .class_hid = BNXT_ULP_CLASS_HID_8b1c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2890] = { + .class_hid = BNXT_ULP_CLASS_HID_ac5c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2891] = { + .class_hid = BNXT_ULP_CLASS_HID_f19c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2892] = { + .class_hid = BNXT_ULP_CLASS_HID_f2dc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2893] = { + .class_hid = BNXT_ULP_CLASS_HID_8420, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2894] = { + .class_hid = BNXT_ULP_CLASS_HID_a960, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2895] = { + .class_hid = BNXT_ULP_CLASS_HID_caa0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2896] = { + .class_hid = BNXT_ULP_CLASS_HID_efe0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2897] = { + .class_hid = BNXT_ULP_CLASS_HID_1ba20, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2898] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf60, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2899] = { + .class_hid = BNXT_ULP_CLASS_HID_1e0a0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2900] = { + .class_hid = BNXT_ULP_CLASS_HID_1e5e0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2901] = { + .class_hid = BNXT_ULP_CLASS_HID_1a11c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2902] = { + .class_hid = BNXT_ULP_CLASS_HID_1a25c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2903] = { + .class_hid = BNXT_ULP_CLASS_HID_1e79c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2904] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8dc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2905] = { + .class_hid = BNXT_ULP_CLASS_HID_af80, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2906] = { + .class_hid = BNXT_ULP_CLASS_HID_f0c0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2907] = { + .class_hid = BNXT_ULP_CLASS_HID_d200, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2908] = { + .class_hid = BNXT_ULP_CLASS_HID_f740, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2909] = { + .class_hid = BNXT_ULP_CLASS_HID_a854, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2910] = { + .class_hid = BNXT_ULP_CLASS_HID_ad94, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2911] = { + .class_hid = BNXT_ULP_CLASS_HID_eed4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2912] = { + .class_hid = BNXT_ULP_CLASS_HID_f014, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2913] = { + .class_hid = BNXT_ULP_CLASS_HID_1de54, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2914] = { + .class_hid = BNXT_ULP_CLASS_HID_1e394, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2915] = { + .class_hid = BNXT_ULP_CLASS_HID_1c4d4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2916] = { + .class_hid = BNXT_ULP_CLASS_HID_1e614, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2917] = { + .class_hid = BNXT_ULP_CLASS_HID_1c580, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2918] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6c0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2919] = { + .class_hid = BNXT_ULP_CLASS_HID_1c800, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2920] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed40, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2921] = { + .class_hid = BNXT_ULP_CLASS_HID_8c6c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2922] = { + .class_hid = BNXT_ULP_CLASS_HID_b1ac, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2923] = { + .class_hid = BNXT_ULP_CLASS_HID_f2ec, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2924] = { + .class_hid = BNXT_ULP_CLASS_HID_f42c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2925] = { + .class_hid = BNXT_ULP_CLASS_HID_8930, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2926] = { + .class_hid = BNXT_ULP_CLASS_HID_aa70, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2927] = { + .class_hid = BNXT_ULP_CLASS_HID_cfb0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2928] = { + .class_hid = BNXT_ULP_CLASS_HID_f0f0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2929] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf30, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2930] = { + .class_hid = BNXT_ULP_CLASS_HID_1a070, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2931] = { + .class_hid = BNXT_ULP_CLASS_HID_1e5b0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2932] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6f0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2933] = { + .class_hid = BNXT_ULP_CLASS_HID_1a26c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2934] = { + .class_hid = BNXT_ULP_CLASS_HID_1a7ac, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2935] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8ec, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2936] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea2c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2937] = { + .class_hid = BNXT_ULP_CLASS_HID_d090, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2938] = { + .class_hid = BNXT_ULP_CLASS_HID_f5d0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2939] = { + .class_hid = BNXT_ULP_CLASS_HID_d710, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2940] = { + .class_hid = BNXT_ULP_CLASS_HID_f850, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2941] = { + .class_hid = BNXT_ULP_CLASS_HID_ada4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2942] = { + .class_hid = BNXT_ULP_CLASS_HID_aee4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2943] = { + .class_hid = BNXT_ULP_CLASS_HID_d024, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2944] = { + .class_hid = BNXT_ULP_CLASS_HID_f564, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2945] = { + .class_hid = BNXT_ULP_CLASS_HID_1c3a4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2946] = { + .class_hid = BNXT_ULP_CLASS_HID_1e4e4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2947] = { + .class_hid = BNXT_ULP_CLASS_HID_1c624, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2948] = { + .class_hid = BNXT_ULP_CLASS_HID_1eb64, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2949] = { + .class_hid = BNXT_ULP_CLASS_HID_1c690, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2950] = { + .class_hid = BNXT_ULP_CLASS_HID_1ebd0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2951] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd10, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2952] = { + .class_hid = BNXT_ULP_CLASS_HID_1f364, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2953] = { + .class_hid = BNXT_ULP_CLASS_HID_99c8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2954] = { + .class_hid = BNXT_ULP_CLASS_HID_bb08, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 250, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2955] = { + .class_hid = BNXT_ULP_CLASS_HID_dc48, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 251, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2956] = { + .class_hid = BNXT_ULP_CLASS_HID_e188, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 252, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2957] = { + .class_hid = BNXT_ULP_CLASS_HID_929c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 253, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2958] = { + .class_hid = BNXT_ULP_CLASS_HID_b7dc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 253, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2959] = { + .class_hid = BNXT_ULP_CLASS_HID_d91c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 253, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2960] = { + .class_hid = BNXT_ULP_CLASS_HID_fa5c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 253, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2961] = { + .class_hid = BNXT_ULP_CLASS_HID_1889c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 253, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2962] = { + .class_hid = BNXT_ULP_CLASS_HID_1addc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 253, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2963] = { + .class_hid = BNXT_ULP_CLASS_HID_1cf1c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 254, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2964] = { + .class_hid = BNXT_ULP_CLASS_HID_1f05c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 255, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2965] = { + .class_hid = BNXT_ULP_CLASS_HID_18fc8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2966] = { + .class_hid = BNXT_ULP_CLASS_HID_1b108, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2967] = { + .class_hid = BNXT_ULP_CLASS_HID_1f248, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2968] = { + .class_hid = BNXT_ULP_CLASS_HID_1f788, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2969] = { + .class_hid = BNXT_ULP_CLASS_HID_ba7c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2970] = { + .class_hid = BNXT_ULP_CLASS_HID_bfbc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2971] = { + .class_hid = BNXT_ULP_CLASS_HID_e0fc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2972] = { + .class_hid = BNXT_ULP_CLASS_HID_e23c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2973] = { + .class_hid = BNXT_ULP_CLASS_HID_b700, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2974] = { + .class_hid = BNXT_ULP_CLASS_HID_b840, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2975] = { + .class_hid = BNXT_ULP_CLASS_HID_fd80, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2976] = { + .class_hid = BNXT_ULP_CLASS_HID_fec0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2977] = { + .class_hid = BNXT_ULP_CLASS_HID_1ad00, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2978] = { + .class_hid = BNXT_ULP_CLASS_HID_1ae40, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2979] = { + .class_hid = BNXT_ULP_CLASS_HID_1d380, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2980] = { + .class_hid = BNXT_ULP_CLASS_HID_1f4c0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2981] = { + .class_hid = BNXT_ULP_CLASS_HID_1d07c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2982] = { + .class_hid = BNXT_ULP_CLASS_HID_1f5bc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2983] = { + .class_hid = BNXT_ULP_CLASS_HID_1d6fc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2984] = { + .class_hid = BNXT_ULP_CLASS_HID_1f83c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2985] = { + .class_hid = BNXT_ULP_CLASS_HID_86a0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2986] = { + .class_hid = BNXT_ULP_CLASS_HID_abe0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2987] = { + .class_hid = BNXT_ULP_CLASS_HID_cd20, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2988] = { + .class_hid = BNXT_ULP_CLASS_HID_ee60, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2989] = { + .class_hid = BNXT_ULP_CLASS_HID_8374, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2990] = { + .class_hid = BNXT_ULP_CLASS_HID_a4b4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2991] = { + .class_hid = BNXT_ULP_CLASS_HID_c9f4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2992] = { + .class_hid = BNXT_ULP_CLASS_HID_eb34, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2993] = { + .class_hid = BNXT_ULP_CLASS_HID_1b974, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2994] = { + .class_hid = BNXT_ULP_CLASS_HID_1bab4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2995] = { + .class_hid = BNXT_ULP_CLASS_HID_1fff4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2996] = { + .class_hid = BNXT_ULP_CLASS_HID_1e134, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2997] = { + .class_hid = BNXT_ULP_CLASS_HID_1bca0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2998] = { + .class_hid = BNXT_ULP_CLASS_HID_1a1e0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2999] = { + .class_hid = BNXT_ULP_CLASS_HID_1e320, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3000] = { + .class_hid = BNXT_ULP_CLASS_HID_1e460, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3001] = { + .class_hid = BNXT_ULP_CLASS_HID_aad4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3002] = { + .class_hid = BNXT_ULP_CLASS_HID_ac14, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3003] = { + .class_hid = BNXT_ULP_CLASS_HID_d154, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3004] = { + .class_hid = BNXT_ULP_CLASS_HID_f294, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3005] = { + .class_hid = BNXT_ULP_CLASS_HID_a798, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3006] = { + .class_hid = BNXT_ULP_CLASS_HID_a8d8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3007] = { + .class_hid = BNXT_ULP_CLASS_HID_ea18, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3008] = { + .class_hid = BNXT_ULP_CLASS_HID_ef58, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3009] = { + .class_hid = BNXT_ULP_CLASS_HID_1dd98, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3010] = { + .class_hid = BNXT_ULP_CLASS_HID_1fed8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3011] = { + .class_hid = BNXT_ULP_CLASS_HID_1c018, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3012] = { + .class_hid = BNXT_ULP_CLASS_HID_1e558, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3013] = { + .class_hid = BNXT_ULP_CLASS_HID_1c0d4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3014] = { + .class_hid = BNXT_ULP_CLASS_HID_1e214, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3015] = { + .class_hid = BNXT_ULP_CLASS_HID_1c754, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3016] = { + .class_hid = BNXT_ULP_CLASS_HID_1e894, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3017] = { + .class_hid = BNXT_ULP_CLASS_HID_900c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3018] = { + .class_hid = BNXT_ULP_CLASS_HID_b54c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3019] = { + .class_hid = BNXT_ULP_CLASS_HID_d68c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3020] = { + .class_hid = BNXT_ULP_CLASS_HID_fbcc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3021] = { + .class_hid = BNXT_ULP_CLASS_HID_c80c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3022] = { + .class_hid = BNXT_ULP_CLASS_HID_ed4c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3023] = { + .class_hid = BNXT_ULP_CLASS_HID_d350, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3024] = { + .class_hid = BNXT_ULP_CLASS_HID_f490, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3025] = { + .class_hid = BNXT_ULP_CLASS_HID_182d0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3026] = { + .class_hid = BNXT_ULP_CLASS_HID_1a410, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3027] = { + .class_hid = BNXT_ULP_CLASS_HID_1c950, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3028] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea90, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3029] = { + .class_hid = BNXT_ULP_CLASS_HID_1860c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3030] = { + .class_hid = BNXT_ULP_CLASS_HID_1ab4c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3031] = { + .class_hid = BNXT_ULP_CLASS_HID_1cc8c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3032] = { + .class_hid = BNXT_ULP_CLASS_HID_1f1cc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3033] = { + .class_hid = BNXT_ULP_CLASS_HID_b4b0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3034] = { + .class_hid = BNXT_ULP_CLASS_HID_b9f0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3035] = { + .class_hid = BNXT_ULP_CLASS_HID_fb30, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3036] = { + .class_hid = BNXT_ULP_CLASS_HID_fc70, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3037] = { + .class_hid = BNXT_ULP_CLASS_HID_b144, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3038] = { + .class_hid = BNXT_ULP_CLASS_HID_b284, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3039] = { + .class_hid = BNXT_ULP_CLASS_HID_f7c4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3040] = { + .class_hid = BNXT_ULP_CLASS_HID_f904, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3041] = { + .class_hid = BNXT_ULP_CLASS_HID_1a744, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3042] = { + .class_hid = BNXT_ULP_CLASS_HID_1a884, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3043] = { + .class_hid = BNXT_ULP_CLASS_HID_1edc4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3044] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef04, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3045] = { + .class_hid = BNXT_ULP_CLASS_HID_1aab0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3046] = { + .class_hid = BNXT_ULP_CLASS_HID_1aff0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3047] = { + .class_hid = BNXT_ULP_CLASS_HID_1d130, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3048] = { + .class_hid = BNXT_ULP_CLASS_HID_1f270, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3049] = { + .class_hid = BNXT_ULP_CLASS_HID_80e4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3050] = { + .class_hid = BNXT_ULP_CLASS_HID_a224, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3051] = { + .class_hid = BNXT_ULP_CLASS_HID_c764, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3052] = { + .class_hid = BNXT_ULP_CLASS_HID_e8a4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3053] = { + .class_hid = BNXT_ULP_CLASS_HID_9da8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3054] = { + .class_hid = BNXT_ULP_CLASS_HID_bee8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3055] = { + .class_hid = BNXT_ULP_CLASS_HID_c028, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3056] = { + .class_hid = BNXT_ULP_CLASS_HID_e568, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3057] = { + .class_hid = BNXT_ULP_CLASS_HID_1b3a8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3058] = { + .class_hid = BNXT_ULP_CLASS_HID_1b4e8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3059] = { + .class_hid = BNXT_ULP_CLASS_HID_1f628, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3060] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb68, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3061] = { + .class_hid = BNXT_ULP_CLASS_HID_1b6e4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3062] = { + .class_hid = BNXT_ULP_CLASS_HID_1b824, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3063] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd64, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3064] = { + .class_hid = BNXT_ULP_CLASS_HID_1fea4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3065] = { + .class_hid = BNXT_ULP_CLASS_HID_a508, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3066] = { + .class_hid = BNXT_ULP_CLASS_HID_a648, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3067] = { + .class_hid = BNXT_ULP_CLASS_HID_eb88, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3068] = { + .class_hid = BNXT_ULP_CLASS_HID_ecc8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3069] = { + .class_hid = BNXT_ULP_CLASS_HID_a1dc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3070] = { + .class_hid = BNXT_ULP_CLASS_HID_a31c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3071] = { + .class_hid = BNXT_ULP_CLASS_HID_e45c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3072] = { + .class_hid = BNXT_ULP_CLASS_HID_e99c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3073] = { + .class_hid = BNXT_ULP_CLASS_HID_1d7dc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3074] = { + .class_hid = BNXT_ULP_CLASS_HID_1f91c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3075] = { + .class_hid = BNXT_ULP_CLASS_HID_1da5c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3076] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff9c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3077] = { + .class_hid = BNXT_ULP_CLASS_HID_1db08, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3078] = { + .class_hid = BNXT_ULP_CLASS_HID_1fc48, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3079] = { + .class_hid = BNXT_ULP_CLASS_HID_1c188, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3080] = { + .class_hid = BNXT_ULP_CLASS_HID_1e2c8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3081] = { + .class_hid = BNXT_ULP_CLASS_HID_9ad8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3082] = { + .class_hid = BNXT_ULP_CLASS_HID_bc18, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3083] = { + .class_hid = BNXT_ULP_CLASS_HID_c158, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3084] = { + .class_hid = BNXT_ULP_CLASS_HID_e298, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3085] = { + .class_hid = BNXT_ULP_CLASS_HID_97ec, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3086] = { + .class_hid = BNXT_ULP_CLASS_HID_b92c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3087] = { + .class_hid = BNXT_ULP_CLASS_HID_da6c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3088] = { + .class_hid = BNXT_ULP_CLASS_HID_ffac, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3089] = { + .class_hid = BNXT_ULP_CLASS_HID_18dec, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3090] = { + .class_hid = BNXT_ULP_CLASS_HID_1af2c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3091] = { + .class_hid = BNXT_ULP_CLASS_HID_1f06c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3092] = { + .class_hid = BNXT_ULP_CLASS_HID_1f5ac, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3093] = { + .class_hid = BNXT_ULP_CLASS_HID_1b0d8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3094] = { + .class_hid = BNXT_ULP_CLASS_HID_1b218, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3095] = { + .class_hid = BNXT_ULP_CLASS_HID_1f758, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3096] = { + .class_hid = BNXT_ULP_CLASS_HID_1f898, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3097] = { + .class_hid = BNXT_ULP_CLASS_HID_bf4c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3098] = { + .class_hid = BNXT_ULP_CLASS_HID_a08c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3099] = { + .class_hid = BNXT_ULP_CLASS_HID_e5cc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3100] = { + .class_hid = BNXT_ULP_CLASS_HID_e70c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3101] = { + .class_hid = BNXT_ULP_CLASS_HID_b810, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3102] = { + .class_hid = BNXT_ULP_CLASS_HID_bd50, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3103] = { + .class_hid = BNXT_ULP_CLASS_HID_fe90, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3104] = { + .class_hid = BNXT_ULP_CLASS_HID_e3d0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3105] = { + .class_hid = BNXT_ULP_CLASS_HID_1ae10, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3106] = { + .class_hid = BNXT_ULP_CLASS_HID_1f350, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3107] = { + .class_hid = BNXT_ULP_CLASS_HID_1d490, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3108] = { + .class_hid = BNXT_ULP_CLASS_HID_1f9d0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3109] = { + .class_hid = BNXT_ULP_CLASS_HID_1d54c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3110] = { + .class_hid = BNXT_ULP_CLASS_HID_1f68c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3111] = { + .class_hid = BNXT_ULP_CLASS_HID_1dbcc, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3112] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd0c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3113] = { + .class_hid = BNXT_ULP_CLASS_HID_34b0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3114] = { + .class_hid = BNXT_ULP_CLASS_HID_3a7c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3115] = { + .class_hid = BNXT_ULP_CLASS_HID_5ee0, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3116] = { + .class_hid = BNXT_ULP_CLASS_HID_07d8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3117] = { + .class_hid = BNXT_ULP_CLASS_HID_284c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3118] = { + .class_hid = BNXT_ULP_CLASS_HID_5924, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3119] = { + .class_hid = BNXT_ULP_CLASS_HID_1e1c, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3120] = { + .class_hid = BNXT_ULP_CLASS_HID_2280, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3121] = { + .class_hid = BNXT_ULP_CLASS_HID_24604, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3122] = { + .class_hid = BNXT_ULP_CLASS_HID_255d4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3123] = { + .class_hid = BNXT_ULP_CLASS_HID_22e08, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3124] = { + .class_hid = BNXT_ULP_CLASS_HID_24378, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3125] = { + .class_hid = BNXT_ULP_CLASS_HID_20fcc, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3126] = { + .class_hid = BNXT_ULP_CLASS_HID_21a9c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3127] = { + .class_hid = BNXT_ULP_CLASS_HID_217d0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3128] = { + .class_hid = BNXT_ULP_CLASS_HID_20800, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3129] = { + .class_hid = BNXT_ULP_CLASS_HID_253a0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 256, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3130] = { + .class_hid = BNXT_ULP_CLASS_HID_23f70, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 257, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3131] = { + .class_hid = BNXT_ULP_CLASS_HID_23ba4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 257, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3132] = { + .class_hid = BNXT_ULP_CLASS_HID_22c94, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3133] = { + .class_hid = BNXT_ULP_CLASS_HID_21968, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3134] = { + .class_hid = BNXT_ULP_CLASS_HID_243c4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3135] = { + .class_hid = BNXT_ULP_CLASS_HID_25c38, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3136] = { + .class_hid = BNXT_ULP_CLASS_HID_2125c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3137] = { + .class_hid = BNXT_ULP_CLASS_HID_240c8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3138] = { + .class_hid = BNXT_ULP_CLASS_HID_22f98, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3139] = { + .class_hid = BNXT_ULP_CLASS_HID_228cc, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3140] = { + .class_hid = BNXT_ULP_CLASS_HID_25d3c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3141] = { + .class_hid = BNXT_ULP_CLASS_HID_20990, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3142] = { + .class_hid = BNXT_ULP_CLASS_HID_214a0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3143] = { + .class_hid = BNXT_ULP_CLASS_HID_21194, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3144] = { + .class_hid = BNXT_ULP_CLASS_HID_202c4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3145] = { + .class_hid = BNXT_ULP_CLASS_HID_22a64, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3146] = { + .class_hid = BNXT_ULP_CLASS_HID_23934, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3147] = { + .class_hid = BNXT_ULP_CLASS_HID_23268, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3148] = { + .class_hid = BNXT_ULP_CLASS_HID_22758, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3149] = { + .class_hid = BNXT_ULP_CLASS_HID_2132c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3150] = { + .class_hid = BNXT_ULP_CLASS_HID_25d88, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3151] = { + .class_hid = BNXT_ULP_CLASS_HID_256fc, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3152] = { + .class_hid = BNXT_ULP_CLASS_HID_24b2c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3153] = { + .class_hid = BNXT_ULP_CLASS_HID_22f14, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3154] = { + .class_hid = BNXT_ULP_CLASS_HID_23a24, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3155] = { + .class_hid = BNXT_ULP_CLASS_HID_23718, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3156] = { + .class_hid = BNXT_ULP_CLASS_HID_22848, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3157] = { + .class_hid = BNXT_ULP_CLASS_HID_214dc, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3158] = { + .class_hid = BNXT_ULP_CLASS_HID_25eb8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3159] = { + .class_hid = BNXT_ULP_CLASS_HID_25bec, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3160] = { + .class_hid = BNXT_ULP_CLASS_HID_21110, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3161] = { + .class_hid = BNXT_ULP_CLASS_HID_238b0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 258, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3162] = { + .class_hid = BNXT_ULP_CLASS_HID_20440, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 259, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3163] = { + .class_hid = BNXT_ULP_CLASS_HID_200b4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 259, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3164] = { + .class_hid = BNXT_ULP_CLASS_HID_235e4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3165] = { + .class_hid = BNXT_ULP_CLASS_HID_25d04, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3166] = { + .class_hid = BNXT_ULP_CLASS_HID_228d4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3167] = { + .class_hid = BNXT_ULP_CLASS_HID_22508, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3168] = { + .class_hid = BNXT_ULP_CLASS_HID_25678, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3169] = { + .class_hid = BNXT_ULP_CLASS_HID_229d8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3170] = { + .class_hid = BNXT_ULP_CLASS_HID_234e8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3171] = { + .class_hid = BNXT_ULP_CLASS_HID_231dc, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3172] = { + .class_hid = BNXT_ULP_CLASS_HID_2220c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3173] = { + .class_hid = BNXT_ULP_CLASS_HID_24dac, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3174] = { + .class_hid = BNXT_ULP_CLASS_HID_2597c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3175] = { + .class_hid = BNXT_ULP_CLASS_HID_255b0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3176] = { + .class_hid = BNXT_ULP_CLASS_HID_246e0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3177] = { + .class_hid = BNXT_ULP_CLASS_HID_23374, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3178] = { + .class_hid = BNXT_ULP_CLASS_HID_21e04, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3179] = { + .class_hid = BNXT_ULP_CLASS_HID_21b78, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3180] = { + .class_hid = BNXT_ULP_CLASS_HID_20fa8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3181] = { + .class_hid = BNXT_ULP_CLASS_HID_257c8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3182] = { + .class_hid = BNXT_ULP_CLASS_HID_22298, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3183] = { + .class_hid = BNXT_ULP_CLASS_HID_23fcc, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3184] = { + .class_hid = BNXT_ULP_CLASS_HID_2503c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3185] = { + .class_hid = BNXT_ULP_CLASS_HID_2239c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3186] = { + .class_hid = BNXT_ULP_CLASS_HID_20eac, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3187] = { + .class_hid = BNXT_ULP_CLASS_HID_20be0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3188] = { + .class_hid = BNXT_ULP_CLASS_HID_23cd0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3189] = { + .class_hid = BNXT_ULP_CLASS_HID_24470, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3190] = { + .class_hid = BNXT_ULP_CLASS_HID_25300, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3191] = { + .class_hid = BNXT_ULP_CLASS_HID_22c74, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3192] = { + .class_hid = BNXT_ULP_CLASS_HID_240a4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3193] = { + .class_hid = BNXT_ULP_CLASS_HID_23da0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3194] = { + .class_hid = BNXT_ULP_CLASS_HID_20970, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3195] = { + .class_hid = BNXT_ULP_CLASS_HID_205a4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3196] = { + .class_hid = BNXT_ULP_CLASS_HID_23694, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3197] = { + .class_hid = BNXT_ULP_CLASS_HID_25e34, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3198] = { + .class_hid = BNXT_ULP_CLASS_HID_22dc4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3199] = { + .class_hid = BNXT_ULP_CLASS_HID_22638, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3200] = { + .class_hid = BNXT_ULP_CLASS_HID_25b68, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3201] = { + .class_hid = BNXT_ULP_CLASS_HID_34c8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3202] = { + .class_hid = BNXT_ULP_CLASS_HID_3a04, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3203] = { + .class_hid = BNXT_ULP_CLASS_HID_5e98, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3204] = { + .class_hid = BNXT_ULP_CLASS_HID_07a0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3205] = { + .class_hid = BNXT_ULP_CLASS_HID_2834, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3206] = { + .class_hid = BNXT_ULP_CLASS_HID_595c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3207] = { + .class_hid = BNXT_ULP_CLASS_HID_1e64, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3208] = { + .class_hid = BNXT_ULP_CLASS_HID_22f8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3209] = { + .class_hid = BNXT_ULP_CLASS_HID_24664, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3210] = { + .class_hid = BNXT_ULP_CLASS_HID_29418, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3211] = { + .class_hid = BNXT_ULP_CLASS_HID_30118, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3212] = { + .class_hid = BNXT_ULP_CLASS_HID_38a18, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3213] = { + .class_hid = BNXT_ULP_CLASS_HID_255b4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3214] = { + .class_hid = BNXT_ULP_CLASS_HID_2deb4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3215] = { + .class_hid = BNXT_ULP_CLASS_HID_34bb4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3216] = { + .class_hid = BNXT_ULP_CLASS_HID_39968, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3217] = { + .class_hid = BNXT_ULP_CLASS_HID_22e68, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3218] = { + .class_hid = BNXT_ULP_CLASS_HID_2db68, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3219] = { + .class_hid = BNXT_ULP_CLASS_HID_34468, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3220] = { + .class_hid = BNXT_ULP_CLASS_HID_3921c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3221] = { + .class_hid = BNXT_ULP_CLASS_HID_24318, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3222] = { + .class_hid = BNXT_ULP_CLASS_HID_290cc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3223] = { + .class_hid = BNXT_ULP_CLASS_HID_31dcc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3224] = { + .class_hid = BNXT_ULP_CLASS_HID_386cc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3225] = { + .class_hid = BNXT_ULP_CLASS_HID_20fac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3226] = { + .class_hid = BNXT_ULP_CLASS_HID_2b8ac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3227] = { + .class_hid = BNXT_ULP_CLASS_HID_325ac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3228] = { + .class_hid = BNXT_ULP_CLASS_HID_3aeac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3229] = { + .class_hid = BNXT_ULP_CLASS_HID_21afc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3230] = { + .class_hid = BNXT_ULP_CLASS_HID_287fc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3231] = { + .class_hid = BNXT_ULP_CLASS_HID_330fc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3232] = { + .class_hid = BNXT_ULP_CLASS_HID_3bdfc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3233] = { + .class_hid = BNXT_ULP_CLASS_HID_217b0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3234] = { + .class_hid = BNXT_ULP_CLASS_HID_280b0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3235] = { + .class_hid = BNXT_ULP_CLASS_HID_30db0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3236] = { + .class_hid = BNXT_ULP_CLASS_HID_3b6b0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3237] = { + .class_hid = BNXT_ULP_CLASS_HID_20860, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3238] = { + .class_hid = BNXT_ULP_CLASS_HID_2b560, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3239] = { + .class_hid = BNXT_ULP_CLASS_HID_33e60, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3240] = { + .class_hid = BNXT_ULP_CLASS_HID_3ab60, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3241] = { + .class_hid = BNXT_ULP_CLASS_HID_253c0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3242] = { + .class_hid = BNXT_ULP_CLASS_HID_2dcc0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 260, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3243] = { + .class_hid = BNXT_ULP_CLASS_HID_349c0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 261, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3244] = { + .class_hid = BNXT_ULP_CLASS_HID_397f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 262, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3245] = { + .class_hid = BNXT_ULP_CLASS_HID_23f10, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 263, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3246] = { + .class_hid = BNXT_ULP_CLASS_HID_2a810, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 263, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3247] = { + .class_hid = BNXT_ULP_CLASS_HID_35510, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 263, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3248] = { + .class_hid = BNXT_ULP_CLASS_HID_3de10, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 263, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3249] = { + .class_hid = BNXT_ULP_CLASS_HID_23bc4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 263, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3250] = { + .class_hid = BNXT_ULP_CLASS_HID_2a4c4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 263, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3251] = { + .class_hid = BNXT_ULP_CLASS_HID_351c4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 264, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3252] = { + .class_hid = BNXT_ULP_CLASS_HID_3dac4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 265, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3253] = { + .class_hid = BNXT_ULP_CLASS_HID_22cf4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3254] = { + .class_hid = BNXT_ULP_CLASS_HID_2d9f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3255] = { + .class_hid = BNXT_ULP_CLASS_HID_342f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3256] = { + .class_hid = BNXT_ULP_CLASS_HID_390a8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3257] = { + .class_hid = BNXT_ULP_CLASS_HID_21908, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3258] = { + .class_hid = BNXT_ULP_CLASS_HID_28208, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3259] = { + .class_hid = BNXT_ULP_CLASS_HID_30f08, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3260] = { + .class_hid = BNXT_ULP_CLASS_HID_3b808, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3261] = { + .class_hid = BNXT_ULP_CLASS_HID_243a4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3262] = { + .class_hid = BNXT_ULP_CLASS_HID_29158, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3263] = { + .class_hid = BNXT_ULP_CLASS_HID_31a58, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3264] = { + .class_hid = BNXT_ULP_CLASS_HID_38758, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3265] = { + .class_hid = BNXT_ULP_CLASS_HID_25c58, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3266] = { + .class_hid = BNXT_ULP_CLASS_HID_2c958, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3267] = { + .class_hid = BNXT_ULP_CLASS_HID_3170c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3268] = { + .class_hid = BNXT_ULP_CLASS_HID_3800c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3269] = { + .class_hid = BNXT_ULP_CLASS_HID_2123c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3270] = { + .class_hid = BNXT_ULP_CLASS_HID_29f3c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3271] = { + .class_hid = BNXT_ULP_CLASS_HID_3083c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3272] = { + .class_hid = BNXT_ULP_CLASS_HID_3b53c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3273] = { + .class_hid = BNXT_ULP_CLASS_HID_240a8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3274] = { + .class_hid = BNXT_ULP_CLASS_HID_2cda8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3275] = { + .class_hid = BNXT_ULP_CLASS_HID_31b5c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3276] = { + .class_hid = BNXT_ULP_CLASS_HID_3845c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3277] = { + .class_hid = BNXT_ULP_CLASS_HID_22ff8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3278] = { + .class_hid = BNXT_ULP_CLASS_HID_2d8f8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3279] = { + .class_hid = BNXT_ULP_CLASS_HID_345f8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3280] = { + .class_hid = BNXT_ULP_CLASS_HID_393ac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3281] = { + .class_hid = BNXT_ULP_CLASS_HID_228ac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3282] = { + .class_hid = BNXT_ULP_CLASS_HID_2d5ac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3283] = { + .class_hid = BNXT_ULP_CLASS_HID_35eac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3284] = { + .class_hid = BNXT_ULP_CLASS_HID_3cbac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3285] = { + .class_hid = BNXT_ULP_CLASS_HID_25d5c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3286] = { + .class_hid = BNXT_ULP_CLASS_HID_2c65c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3287] = { + .class_hid = BNXT_ULP_CLASS_HID_31410, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3288] = { + .class_hid = BNXT_ULP_CLASS_HID_38110, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3289] = { + .class_hid = BNXT_ULP_CLASS_HID_209f0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3290] = { + .class_hid = BNXT_ULP_CLASS_HID_2b2f0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3291] = { + .class_hid = BNXT_ULP_CLASS_HID_33ff0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3292] = { + .class_hid = BNXT_ULP_CLASS_HID_3a8f0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3293] = { + .class_hid = BNXT_ULP_CLASS_HID_214c0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3294] = { + .class_hid = BNXT_ULP_CLASS_HID_281c0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3295] = { + .class_hid = BNXT_ULP_CLASS_HID_30ac0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3296] = { + .class_hid = BNXT_ULP_CLASS_HID_3b7c0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3297] = { + .class_hid = BNXT_ULP_CLASS_HID_211f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3298] = { + .class_hid = BNXT_ULP_CLASS_HID_29af4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3299] = { + .class_hid = BNXT_ULP_CLASS_HID_307f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3300] = { + .class_hid = BNXT_ULP_CLASS_HID_3b0f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3301] = { + .class_hid = BNXT_ULP_CLASS_HID_202a4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3302] = { + .class_hid = BNXT_ULP_CLASS_HID_28fa4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3303] = { + .class_hid = BNXT_ULP_CLASS_HID_338a4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3304] = { + .class_hid = BNXT_ULP_CLASS_HID_3a5a4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3305] = { + .class_hid = BNXT_ULP_CLASS_HID_22a04, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3306] = { + .class_hid = BNXT_ULP_CLASS_HID_2d704, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3307] = { + .class_hid = BNXT_ULP_CLASS_HID_34004, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3308] = { + .class_hid = BNXT_ULP_CLASS_HID_3cd04, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3309] = { + .class_hid = BNXT_ULP_CLASS_HID_23954, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3310] = { + .class_hid = BNXT_ULP_CLASS_HID_2a254, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3311] = { + .class_hid = BNXT_ULP_CLASS_HID_32f54, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3312] = { + .class_hid = BNXT_ULP_CLASS_HID_3d854, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3313] = { + .class_hid = BNXT_ULP_CLASS_HID_23208, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3314] = { + .class_hid = BNXT_ULP_CLASS_HID_2bf08, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3315] = { + .class_hid = BNXT_ULP_CLASS_HID_32808, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3316] = { + .class_hid = BNXT_ULP_CLASS_HID_3d508, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3317] = { + .class_hid = BNXT_ULP_CLASS_HID_22738, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3318] = { + .class_hid = BNXT_ULP_CLASS_HID_2d038, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3319] = { + .class_hid = BNXT_ULP_CLASS_HID_35d38, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3320] = { + .class_hid = BNXT_ULP_CLASS_HID_3c638, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3321] = { + .class_hid = BNXT_ULP_CLASS_HID_2134c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3322] = { + .class_hid = BNXT_ULP_CLASS_HID_29c4c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3323] = { + .class_hid = BNXT_ULP_CLASS_HID_3094c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3324] = { + .class_hid = BNXT_ULP_CLASS_HID_3b24c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3325] = { + .class_hid = BNXT_ULP_CLASS_HID_25de8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3326] = { + .class_hid = BNXT_ULP_CLASS_HID_2c6e8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3327] = { + .class_hid = BNXT_ULP_CLASS_HID_3149c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3328] = { + .class_hid = BNXT_ULP_CLASS_HID_3819c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3329] = { + .class_hid = BNXT_ULP_CLASS_HID_2569c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3330] = { + .class_hid = BNXT_ULP_CLASS_HID_2c39c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3331] = { + .class_hid = BNXT_ULP_CLASS_HID_31150, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3332] = { + .class_hid = BNXT_ULP_CLASS_HID_39a50, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3333] = { + .class_hid = BNXT_ULP_CLASS_HID_24b4c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3334] = { + .class_hid = BNXT_ULP_CLASS_HID_29900, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3335] = { + .class_hid = BNXT_ULP_CLASS_HID_30200, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3336] = { + .class_hid = BNXT_ULP_CLASS_HID_38f00, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3337] = { + .class_hid = BNXT_ULP_CLASS_HID_22f74, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3338] = { + .class_hid = BNXT_ULP_CLASS_HID_2d874, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3339] = { + .class_hid = BNXT_ULP_CLASS_HID_34574, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3340] = { + .class_hid = BNXT_ULP_CLASS_HID_39328, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3341] = { + .class_hid = BNXT_ULP_CLASS_HID_23a44, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3342] = { + .class_hid = BNXT_ULP_CLASS_HID_2a744, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3343] = { + .class_hid = BNXT_ULP_CLASS_HID_35044, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3344] = { + .class_hid = BNXT_ULP_CLASS_HID_3dd44, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3345] = { + .class_hid = BNXT_ULP_CLASS_HID_23778, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3346] = { + .class_hid = BNXT_ULP_CLASS_HID_2a078, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3347] = { + .class_hid = BNXT_ULP_CLASS_HID_32d78, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3348] = { + .class_hid = BNXT_ULP_CLASS_HID_3d678, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3349] = { + .class_hid = BNXT_ULP_CLASS_HID_22828, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3350] = { + .class_hid = BNXT_ULP_CLASS_HID_2d528, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3351] = { + .class_hid = BNXT_ULP_CLASS_HID_35e28, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3352] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb28, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3353] = { + .class_hid = BNXT_ULP_CLASS_HID_214bc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3354] = { + .class_hid = BNXT_ULP_CLASS_HID_281bc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3355] = { + .class_hid = BNXT_ULP_CLASS_HID_30abc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3356] = { + .class_hid = BNXT_ULP_CLASS_HID_3b7bc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3357] = { + .class_hid = BNXT_ULP_CLASS_HID_25ed8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3358] = { + .class_hid = BNXT_ULP_CLASS_HID_2cbd8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3359] = { + .class_hid = BNXT_ULP_CLASS_HID_3198c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3360] = { + .class_hid = BNXT_ULP_CLASS_HID_3828c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3361] = { + .class_hid = BNXT_ULP_CLASS_HID_25b8c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3362] = { + .class_hid = BNXT_ULP_CLASS_HID_2c48c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3363] = { + .class_hid = BNXT_ULP_CLASS_HID_31240, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3364] = { + .class_hid = BNXT_ULP_CLASS_HID_39f40, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3365] = { + .class_hid = BNXT_ULP_CLASS_HID_21170, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3366] = { + .class_hid = BNXT_ULP_CLASS_HID_29a70, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3367] = { + .class_hid = BNXT_ULP_CLASS_HID_30770, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3368] = { + .class_hid = BNXT_ULP_CLASS_HID_3b070, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3369] = { + .class_hid = BNXT_ULP_CLASS_HID_238d0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3370] = { + .class_hid = BNXT_ULP_CLASS_HID_2a5d0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 266, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3371] = { + .class_hid = BNXT_ULP_CLASS_HID_32ed0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 267, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3372] = { + .class_hid = BNXT_ULP_CLASS_HID_3dbd0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 268, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3373] = { + .class_hid = BNXT_ULP_CLASS_HID_20420, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 269, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3374] = { + .class_hid = BNXT_ULP_CLASS_HID_2b120, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 269, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3375] = { + .class_hid = BNXT_ULP_CLASS_HID_33a20, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 269, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3376] = { + .class_hid = BNXT_ULP_CLASS_HID_3a720, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 269, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3377] = { + .class_hid = BNXT_ULP_CLASS_HID_200d4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 269, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3378] = { + .class_hid = BNXT_ULP_CLASS_HID_28dd4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 269, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3379] = { + .class_hid = BNXT_ULP_CLASS_HID_336d4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 270, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3380] = { + .class_hid = BNXT_ULP_CLASS_HID_3a3d4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 271, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3381] = { + .class_hid = BNXT_ULP_CLASS_HID_23584, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3382] = { + .class_hid = BNXT_ULP_CLASS_HID_2be84, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3383] = { + .class_hid = BNXT_ULP_CLASS_HID_32b84, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3384] = { + .class_hid = BNXT_ULP_CLASS_HID_3d484, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3385] = { + .class_hid = BNXT_ULP_CLASS_HID_25d64, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3386] = { + .class_hid = BNXT_ULP_CLASS_HID_2c664, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3387] = { + .class_hid = BNXT_ULP_CLASS_HID_31418, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3388] = { + .class_hid = BNXT_ULP_CLASS_HID_38118, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3389] = { + .class_hid = BNXT_ULP_CLASS_HID_228b4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3390] = { + .class_hid = BNXT_ULP_CLASS_HID_2d5b4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3391] = { + .class_hid = BNXT_ULP_CLASS_HID_35eb4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3392] = { + .class_hid = BNXT_ULP_CLASS_HID_3cbb4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3393] = { + .class_hid = BNXT_ULP_CLASS_HID_22568, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3394] = { + .class_hid = BNXT_ULP_CLASS_HID_2ae68, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3395] = { + .class_hid = BNXT_ULP_CLASS_HID_35b68, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3396] = { + .class_hid = BNXT_ULP_CLASS_HID_3c468, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3397] = { + .class_hid = BNXT_ULP_CLASS_HID_25618, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3398] = { + .class_hid = BNXT_ULP_CLASS_HID_2c318, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3399] = { + .class_hid = BNXT_ULP_CLASS_HID_310cc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3400] = { + .class_hid = BNXT_ULP_CLASS_HID_39dcc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3401] = { + .class_hid = BNXT_ULP_CLASS_HID_229b8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3402] = { + .class_hid = BNXT_ULP_CLASS_HID_2d2b8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3403] = { + .class_hid = BNXT_ULP_CLASS_HID_35fb8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3404] = { + .class_hid = BNXT_ULP_CLASS_HID_3c8b8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3405] = { + .class_hid = BNXT_ULP_CLASS_HID_23488, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3406] = { + .class_hid = BNXT_ULP_CLASS_HID_2a188, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3407] = { + .class_hid = BNXT_ULP_CLASS_HID_32a88, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3408] = { + .class_hid = BNXT_ULP_CLASS_HID_3d788, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3409] = { + .class_hid = BNXT_ULP_CLASS_HID_231bc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3410] = { + .class_hid = BNXT_ULP_CLASS_HID_2babc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3411] = { + .class_hid = BNXT_ULP_CLASS_HID_327bc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3412] = { + .class_hid = BNXT_ULP_CLASS_HID_3d0bc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3413] = { + .class_hid = BNXT_ULP_CLASS_HID_2226c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3414] = { + .class_hid = BNXT_ULP_CLASS_HID_2af6c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3415] = { + .class_hid = BNXT_ULP_CLASS_HID_3586c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3416] = { + .class_hid = BNXT_ULP_CLASS_HID_3c56c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3417] = { + .class_hid = BNXT_ULP_CLASS_HID_24dcc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3418] = { + .class_hid = BNXT_ULP_CLASS_HID_29b80, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3419] = { + .class_hid = BNXT_ULP_CLASS_HID_30480, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3420] = { + .class_hid = BNXT_ULP_CLASS_HID_3b180, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3421] = { + .class_hid = BNXT_ULP_CLASS_HID_2591c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3422] = { + .class_hid = BNXT_ULP_CLASS_HID_2c21c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3423] = { + .class_hid = BNXT_ULP_CLASS_HID_313d0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3424] = { + .class_hid = BNXT_ULP_CLASS_HID_39cd0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3425] = { + .class_hid = BNXT_ULP_CLASS_HID_255d0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3426] = { + .class_hid = BNXT_ULP_CLASS_HID_2ded0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3427] = { + .class_hid = BNXT_ULP_CLASS_HID_34bd0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3428] = { + .class_hid = BNXT_ULP_CLASS_HID_39984, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3429] = { + .class_hid = BNXT_ULP_CLASS_HID_24680, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3430] = { + .class_hid = BNXT_ULP_CLASS_HID_294b4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3431] = { + .class_hid = BNXT_ULP_CLASS_HID_301b4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3432] = { + .class_hid = BNXT_ULP_CLASS_HID_38ab4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3433] = { + .class_hid = BNXT_ULP_CLASS_HID_23314, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3434] = { + .class_hid = BNXT_ULP_CLASS_HID_2bc14, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3435] = { + .class_hid = BNXT_ULP_CLASS_HID_32914, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3436] = { + .class_hid = BNXT_ULP_CLASS_HID_3d214, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3437] = { + .class_hid = BNXT_ULP_CLASS_HID_21e64, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3438] = { + .class_hid = BNXT_ULP_CLASS_HID_28b64, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3439] = { + .class_hid = BNXT_ULP_CLASS_HID_33464, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3440] = { + .class_hid = BNXT_ULP_CLASS_HID_3a164, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3441] = { + .class_hid = BNXT_ULP_CLASS_HID_21b18, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3442] = { + .class_hid = BNXT_ULP_CLASS_HID_28418, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3443] = { + .class_hid = BNXT_ULP_CLASS_HID_33118, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3444] = { + .class_hid = BNXT_ULP_CLASS_HID_3ba18, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3445] = { + .class_hid = BNXT_ULP_CLASS_HID_20fc8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3446] = { + .class_hid = BNXT_ULP_CLASS_HID_2b8c8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3447] = { + .class_hid = BNXT_ULP_CLASS_HID_325c8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3448] = { + .class_hid = BNXT_ULP_CLASS_HID_3aec8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3449] = { + .class_hid = BNXT_ULP_CLASS_HID_257a8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3450] = { + .class_hid = BNXT_ULP_CLASS_HID_2c0a8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3451] = { + .class_hid = BNXT_ULP_CLASS_HID_34da8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3452] = { + .class_hid = BNXT_ULP_CLASS_HID_39b5c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3453] = { + .class_hid = BNXT_ULP_CLASS_HID_222f8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3454] = { + .class_hid = BNXT_ULP_CLASS_HID_2aff8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3455] = { + .class_hid = BNXT_ULP_CLASS_HID_358f8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3456] = { + .class_hid = BNXT_ULP_CLASS_HID_3c5f8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3457] = { + .class_hid = BNXT_ULP_CLASS_HID_23fac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3458] = { + .class_hid = BNXT_ULP_CLASS_HID_2a8ac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3459] = { + .class_hid = BNXT_ULP_CLASS_HID_355ac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3460] = { + .class_hid = BNXT_ULP_CLASS_HID_3deac, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3461] = { + .class_hid = BNXT_ULP_CLASS_HID_2505c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3462] = { + .class_hid = BNXT_ULP_CLASS_HID_2dd5c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3463] = { + .class_hid = BNXT_ULP_CLASS_HID_3465c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3464] = { + .class_hid = BNXT_ULP_CLASS_HID_39410, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3465] = { + .class_hid = BNXT_ULP_CLASS_HID_223fc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3466] = { + .class_hid = BNXT_ULP_CLASS_HID_2acfc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3467] = { + .class_hid = BNXT_ULP_CLASS_HID_359fc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3468] = { + .class_hid = BNXT_ULP_CLASS_HID_3c2fc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3469] = { + .class_hid = BNXT_ULP_CLASS_HID_20ecc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3470] = { + .class_hid = BNXT_ULP_CLASS_HID_2bbcc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3471] = { + .class_hid = BNXT_ULP_CLASS_HID_324cc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3472] = { + .class_hid = BNXT_ULP_CLASS_HID_3d1cc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3473] = { + .class_hid = BNXT_ULP_CLASS_HID_20b80, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3474] = { + .class_hid = BNXT_ULP_CLASS_HID_2b480, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3475] = { + .class_hid = BNXT_ULP_CLASS_HID_32180, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3476] = { + .class_hid = BNXT_ULP_CLASS_HID_3aa80, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3477] = { + .class_hid = BNXT_ULP_CLASS_HID_23cb0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3478] = { + .class_hid = BNXT_ULP_CLASS_HID_2a9b0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3479] = { + .class_hid = BNXT_ULP_CLASS_HID_352b0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3480] = { + .class_hid = BNXT_ULP_CLASS_HID_3dfb0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3481] = { + .class_hid = BNXT_ULP_CLASS_HID_24410, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3482] = { + .class_hid = BNXT_ULP_CLASS_HID_295c4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3483] = { + .class_hid = BNXT_ULP_CLASS_HID_31ec4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3484] = { + .class_hid = BNXT_ULP_CLASS_HID_38bc4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3485] = { + .class_hid = BNXT_ULP_CLASS_HID_25360, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3486] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc60, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3487] = { + .class_hid = BNXT_ULP_CLASS_HID_34960, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3488] = { + .class_hid = BNXT_ULP_CLASS_HID_39714, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3489] = { + .class_hid = BNXT_ULP_CLASS_HID_22c14, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3490] = { + .class_hid = BNXT_ULP_CLASS_HID_2d914, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3491] = { + .class_hid = BNXT_ULP_CLASS_HID_34214, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3492] = { + .class_hid = BNXT_ULP_CLASS_HID_393c8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3493] = { + .class_hid = BNXT_ULP_CLASS_HID_240c4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3494] = { + .class_hid = BNXT_ULP_CLASS_HID_2cdc4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3495] = { + .class_hid = BNXT_ULP_CLASS_HID_31bf8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3496] = { + .class_hid = BNXT_ULP_CLASS_HID_384f8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3497] = { + .class_hid = BNXT_ULP_CLASS_HID_23dc0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3498] = { + .class_hid = BNXT_ULP_CLASS_HID_2a6c0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3499] = { + .class_hid = BNXT_ULP_CLASS_HID_353c0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3500] = { + .class_hid = BNXT_ULP_CLASS_HID_3dcc0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3501] = { + .class_hid = BNXT_ULP_CLASS_HID_20910, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3502] = { + .class_hid = BNXT_ULP_CLASS_HID_2b210, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3503] = { + .class_hid = BNXT_ULP_CLASS_HID_33f10, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3504] = { + .class_hid = BNXT_ULP_CLASS_HID_3a810, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3505] = { + .class_hid = BNXT_ULP_CLASS_HID_205c4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3506] = { + .class_hid = BNXT_ULP_CLASS_HID_28ec4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3507] = { + .class_hid = BNXT_ULP_CLASS_HID_33bc4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3508] = { + .class_hid = BNXT_ULP_CLASS_HID_3a4c4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3509] = { + .class_hid = BNXT_ULP_CLASS_HID_236f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3510] = { + .class_hid = BNXT_ULP_CLASS_HID_2a3f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3511] = { + .class_hid = BNXT_ULP_CLASS_HID_32cf4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3512] = { + .class_hid = BNXT_ULP_CLASS_HID_3d9f4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3513] = { + .class_hid = BNXT_ULP_CLASS_HID_25e54, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3514] = { + .class_hid = BNXT_ULP_CLASS_HID_2cb54, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3515] = { + .class_hid = BNXT_ULP_CLASS_HID_31908, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3516] = { + .class_hid = BNXT_ULP_CLASS_HID_38208, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3517] = { + .class_hid = BNXT_ULP_CLASS_HID_22da4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3518] = { + .class_hid = BNXT_ULP_CLASS_HID_2d6a4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3519] = { + .class_hid = BNXT_ULP_CLASS_HID_343a4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3520] = { + .class_hid = BNXT_ULP_CLASS_HID_39158, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3521] = { + .class_hid = BNXT_ULP_CLASS_HID_22658, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3522] = { + .class_hid = BNXT_ULP_CLASS_HID_2d358, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3523] = { + .class_hid = BNXT_ULP_CLASS_HID_35c58, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3524] = { + .class_hid = BNXT_ULP_CLASS_HID_3c958, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3525] = { + .class_hid = BNXT_ULP_CLASS_HID_25b08, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3526] = { + .class_hid = BNXT_ULP_CLASS_HID_2c408, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3527] = { + .class_hid = BNXT_ULP_CLASS_HID_3123c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3528] = { + .class_hid = BNXT_ULP_CLASS_HID_39f3c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3529] = { + .class_hid = BNXT_ULP_CLASS_HID_34a8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3530] = { + .class_hid = BNXT_ULP_CLASS_HID_3a64, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3531] = { + .class_hid = BNXT_ULP_CLASS_HID_5ef8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3532] = { + .class_hid = BNXT_ULP_CLASS_HID_07c0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3533] = { + .class_hid = BNXT_ULP_CLASS_HID_2854, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3534] = { + .class_hid = BNXT_ULP_CLASS_HID_593c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3535] = { + .class_hid = BNXT_ULP_CLASS_HID_1e04, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3536] = { + .class_hid = BNXT_ULP_CLASS_HID_2298, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3537] = { + .class_hid = BNXT_ULP_CLASS_HID_24644, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3538] = { + .class_hid = BNXT_ULP_CLASS_HID_29438, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3539] = { + .class_hid = BNXT_ULP_CLASS_HID_30138, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3540] = { + .class_hid = BNXT_ULP_CLASS_HID_38a38, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3541] = { + .class_hid = BNXT_ULP_CLASS_HID_25594, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3542] = { + .class_hid = BNXT_ULP_CLASS_HID_2de94, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3543] = { + .class_hid = BNXT_ULP_CLASS_HID_34b94, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3544] = { + .class_hid = BNXT_ULP_CLASS_HID_39948, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3545] = { + .class_hid = BNXT_ULP_CLASS_HID_22e48, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3546] = { + .class_hid = BNXT_ULP_CLASS_HID_2db48, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3547] = { + .class_hid = BNXT_ULP_CLASS_HID_34448, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3548] = { + .class_hid = BNXT_ULP_CLASS_HID_3923c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3549] = { + .class_hid = BNXT_ULP_CLASS_HID_24338, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3550] = { + .class_hid = BNXT_ULP_CLASS_HID_290ec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3551] = { + .class_hid = BNXT_ULP_CLASS_HID_31dec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3552] = { + .class_hid = BNXT_ULP_CLASS_HID_386ec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3553] = { + .class_hid = BNXT_ULP_CLASS_HID_20f8c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3554] = { + .class_hid = BNXT_ULP_CLASS_HID_2b88c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3555] = { + .class_hid = BNXT_ULP_CLASS_HID_3258c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3556] = { + .class_hid = BNXT_ULP_CLASS_HID_3ae8c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3557] = { + .class_hid = BNXT_ULP_CLASS_HID_21adc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3558] = { + .class_hid = BNXT_ULP_CLASS_HID_287dc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3559] = { + .class_hid = BNXT_ULP_CLASS_HID_330dc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3560] = { + .class_hid = BNXT_ULP_CLASS_HID_3bddc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3561] = { + .class_hid = BNXT_ULP_CLASS_HID_21790, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3562] = { + .class_hid = BNXT_ULP_CLASS_HID_28090, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3563] = { + .class_hid = BNXT_ULP_CLASS_HID_30d90, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3564] = { + .class_hid = BNXT_ULP_CLASS_HID_3b690, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3565] = { + .class_hid = BNXT_ULP_CLASS_HID_20840, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3566] = { + .class_hid = BNXT_ULP_CLASS_HID_2b540, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3567] = { + .class_hid = BNXT_ULP_CLASS_HID_33e40, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3568] = { + .class_hid = BNXT_ULP_CLASS_HID_3ab40, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3569] = { + .class_hid = BNXT_ULP_CLASS_HID_253e0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3570] = { + .class_hid = BNXT_ULP_CLASS_HID_2dce0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 272, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3571] = { + .class_hid = BNXT_ULP_CLASS_HID_349e0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 273, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3572] = { + .class_hid = BNXT_ULP_CLASS_HID_397d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 274, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3573] = { + .class_hid = BNXT_ULP_CLASS_HID_23f30, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 275, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3574] = { + .class_hid = BNXT_ULP_CLASS_HID_2a830, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 275, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3575] = { + .class_hid = BNXT_ULP_CLASS_HID_35530, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 275, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3576] = { + .class_hid = BNXT_ULP_CLASS_HID_3de30, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 275, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3577] = { + .class_hid = BNXT_ULP_CLASS_HID_23be4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 275, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3578] = { + .class_hid = BNXT_ULP_CLASS_HID_2a4e4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 275, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3579] = { + .class_hid = BNXT_ULP_CLASS_HID_351e4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 276, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3580] = { + .class_hid = BNXT_ULP_CLASS_HID_3dae4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 277, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3581] = { + .class_hid = BNXT_ULP_CLASS_HID_22cd4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3582] = { + .class_hid = BNXT_ULP_CLASS_HID_2d9d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3583] = { + .class_hid = BNXT_ULP_CLASS_HID_342d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3584] = { + .class_hid = BNXT_ULP_CLASS_HID_39088, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3585] = { + .class_hid = BNXT_ULP_CLASS_HID_21928, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3586] = { + .class_hid = BNXT_ULP_CLASS_HID_28228, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3587] = { + .class_hid = BNXT_ULP_CLASS_HID_30f28, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3588] = { + .class_hid = BNXT_ULP_CLASS_HID_3b828, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3589] = { + .class_hid = BNXT_ULP_CLASS_HID_24384, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3590] = { + .class_hid = BNXT_ULP_CLASS_HID_29178, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3591] = { + .class_hid = BNXT_ULP_CLASS_HID_31a78, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3592] = { + .class_hid = BNXT_ULP_CLASS_HID_38778, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3593] = { + .class_hid = BNXT_ULP_CLASS_HID_25c78, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3594] = { + .class_hid = BNXT_ULP_CLASS_HID_2c978, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3595] = { + .class_hid = BNXT_ULP_CLASS_HID_3172c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3596] = { + .class_hid = BNXT_ULP_CLASS_HID_3802c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3597] = { + .class_hid = BNXT_ULP_CLASS_HID_2121c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3598] = { + .class_hid = BNXT_ULP_CLASS_HID_29f1c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3599] = { + .class_hid = BNXT_ULP_CLASS_HID_3081c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3600] = { + .class_hid = BNXT_ULP_CLASS_HID_3b51c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3601] = { + .class_hid = BNXT_ULP_CLASS_HID_24088, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3602] = { + .class_hid = BNXT_ULP_CLASS_HID_2cd88, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3603] = { + .class_hid = BNXT_ULP_CLASS_HID_31b7c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3604] = { + .class_hid = BNXT_ULP_CLASS_HID_3847c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3605] = { + .class_hid = BNXT_ULP_CLASS_HID_22fd8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3606] = { + .class_hid = BNXT_ULP_CLASS_HID_2d8d8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3607] = { + .class_hid = BNXT_ULP_CLASS_HID_345d8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3608] = { + .class_hid = BNXT_ULP_CLASS_HID_3938c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3609] = { + .class_hid = BNXT_ULP_CLASS_HID_2288c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3610] = { + .class_hid = BNXT_ULP_CLASS_HID_2d58c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3611] = { + .class_hid = BNXT_ULP_CLASS_HID_35e8c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3612] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb8c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3613] = { + .class_hid = BNXT_ULP_CLASS_HID_25d7c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3614] = { + .class_hid = BNXT_ULP_CLASS_HID_2c67c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3615] = { + .class_hid = BNXT_ULP_CLASS_HID_31430, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3616] = { + .class_hid = BNXT_ULP_CLASS_HID_38130, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3617] = { + .class_hid = BNXT_ULP_CLASS_HID_209d0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3618] = { + .class_hid = BNXT_ULP_CLASS_HID_2b2d0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3619] = { + .class_hid = BNXT_ULP_CLASS_HID_33fd0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3620] = { + .class_hid = BNXT_ULP_CLASS_HID_3a8d0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3621] = { + .class_hid = BNXT_ULP_CLASS_HID_214e0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3622] = { + .class_hid = BNXT_ULP_CLASS_HID_281e0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3623] = { + .class_hid = BNXT_ULP_CLASS_HID_30ae0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3624] = { + .class_hid = BNXT_ULP_CLASS_HID_3b7e0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3625] = { + .class_hid = BNXT_ULP_CLASS_HID_211d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3626] = { + .class_hid = BNXT_ULP_CLASS_HID_29ad4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3627] = { + .class_hid = BNXT_ULP_CLASS_HID_307d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3628] = { + .class_hid = BNXT_ULP_CLASS_HID_3b0d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3629] = { + .class_hid = BNXT_ULP_CLASS_HID_20284, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3630] = { + .class_hid = BNXT_ULP_CLASS_HID_28f84, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3631] = { + .class_hid = BNXT_ULP_CLASS_HID_33884, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3632] = { + .class_hid = BNXT_ULP_CLASS_HID_3a584, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3633] = { + .class_hid = BNXT_ULP_CLASS_HID_22a24, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3634] = { + .class_hid = BNXT_ULP_CLASS_HID_2d724, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3635] = { + .class_hid = BNXT_ULP_CLASS_HID_34024, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3636] = { + .class_hid = BNXT_ULP_CLASS_HID_3cd24, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3637] = { + .class_hid = BNXT_ULP_CLASS_HID_23974, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3638] = { + .class_hid = BNXT_ULP_CLASS_HID_2a274, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3639] = { + .class_hid = BNXT_ULP_CLASS_HID_32f74, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3640] = { + .class_hid = BNXT_ULP_CLASS_HID_3d874, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3641] = { + .class_hid = BNXT_ULP_CLASS_HID_23228, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3642] = { + .class_hid = BNXT_ULP_CLASS_HID_2bf28, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3643] = { + .class_hid = BNXT_ULP_CLASS_HID_32828, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3644] = { + .class_hid = BNXT_ULP_CLASS_HID_3d528, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3645] = { + .class_hid = BNXT_ULP_CLASS_HID_22718, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3646] = { + .class_hid = BNXT_ULP_CLASS_HID_2d018, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3647] = { + .class_hid = BNXT_ULP_CLASS_HID_35d18, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3648] = { + .class_hid = BNXT_ULP_CLASS_HID_3c618, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3649] = { + .class_hid = BNXT_ULP_CLASS_HID_2136c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3650] = { + .class_hid = BNXT_ULP_CLASS_HID_29c6c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3651] = { + .class_hid = BNXT_ULP_CLASS_HID_3096c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3652] = { + .class_hid = BNXT_ULP_CLASS_HID_3b26c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3653] = { + .class_hid = BNXT_ULP_CLASS_HID_25dc8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3654] = { + .class_hid = BNXT_ULP_CLASS_HID_2c6c8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3655] = { + .class_hid = BNXT_ULP_CLASS_HID_314bc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3656] = { + .class_hid = BNXT_ULP_CLASS_HID_381bc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3657] = { + .class_hid = BNXT_ULP_CLASS_HID_256bc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3658] = { + .class_hid = BNXT_ULP_CLASS_HID_2c3bc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3659] = { + .class_hid = BNXT_ULP_CLASS_HID_31170, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3660] = { + .class_hid = BNXT_ULP_CLASS_HID_39a70, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3661] = { + .class_hid = BNXT_ULP_CLASS_HID_24b6c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3662] = { + .class_hid = BNXT_ULP_CLASS_HID_29920, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3663] = { + .class_hid = BNXT_ULP_CLASS_HID_30220, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3664] = { + .class_hid = BNXT_ULP_CLASS_HID_38f20, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3665] = { + .class_hid = BNXT_ULP_CLASS_HID_22f54, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3666] = { + .class_hid = BNXT_ULP_CLASS_HID_2d854, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3667] = { + .class_hid = BNXT_ULP_CLASS_HID_34554, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3668] = { + .class_hid = BNXT_ULP_CLASS_HID_39308, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3669] = { + .class_hid = BNXT_ULP_CLASS_HID_23a64, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3670] = { + .class_hid = BNXT_ULP_CLASS_HID_2a764, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3671] = { + .class_hid = BNXT_ULP_CLASS_HID_35064, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3672] = { + .class_hid = BNXT_ULP_CLASS_HID_3dd64, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3673] = { + .class_hid = BNXT_ULP_CLASS_HID_23758, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3674] = { + .class_hid = BNXT_ULP_CLASS_HID_2a058, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3675] = { + .class_hid = BNXT_ULP_CLASS_HID_32d58, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3676] = { + .class_hid = BNXT_ULP_CLASS_HID_3d658, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3677] = { + .class_hid = BNXT_ULP_CLASS_HID_22808, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3678] = { + .class_hid = BNXT_ULP_CLASS_HID_2d508, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3679] = { + .class_hid = BNXT_ULP_CLASS_HID_35e08, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3680] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb08, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3681] = { + .class_hid = BNXT_ULP_CLASS_HID_2149c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3682] = { + .class_hid = BNXT_ULP_CLASS_HID_2819c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3683] = { + .class_hid = BNXT_ULP_CLASS_HID_30a9c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3684] = { + .class_hid = BNXT_ULP_CLASS_HID_3b79c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3685] = { + .class_hid = BNXT_ULP_CLASS_HID_25ef8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3686] = { + .class_hid = BNXT_ULP_CLASS_HID_2cbf8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3687] = { + .class_hid = BNXT_ULP_CLASS_HID_319ac, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3688] = { + .class_hid = BNXT_ULP_CLASS_HID_382ac, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3689] = { + .class_hid = BNXT_ULP_CLASS_HID_25bac, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3690] = { + .class_hid = BNXT_ULP_CLASS_HID_2c4ac, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3691] = { + .class_hid = BNXT_ULP_CLASS_HID_31260, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3692] = { + .class_hid = BNXT_ULP_CLASS_HID_39f60, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3693] = { + .class_hid = BNXT_ULP_CLASS_HID_21150, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3694] = { + .class_hid = BNXT_ULP_CLASS_HID_29a50, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3695] = { + .class_hid = BNXT_ULP_CLASS_HID_30750, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3696] = { + .class_hid = BNXT_ULP_CLASS_HID_3b050, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3697] = { + .class_hid = BNXT_ULP_CLASS_HID_238f0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3698] = { + .class_hid = BNXT_ULP_CLASS_HID_2a5f0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 278, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3699] = { + .class_hid = BNXT_ULP_CLASS_HID_32ef0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 279, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3700] = { + .class_hid = BNXT_ULP_CLASS_HID_3dbf0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 280, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3701] = { + .class_hid = BNXT_ULP_CLASS_HID_20400, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 281, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3702] = { + .class_hid = BNXT_ULP_CLASS_HID_2b100, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 281, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3703] = { + .class_hid = BNXT_ULP_CLASS_HID_33a00, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 281, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3704] = { + .class_hid = BNXT_ULP_CLASS_HID_3a700, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 281, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3705] = { + .class_hid = BNXT_ULP_CLASS_HID_200f4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 281, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3706] = { + .class_hid = BNXT_ULP_CLASS_HID_28df4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 281, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3707] = { + .class_hid = BNXT_ULP_CLASS_HID_336f4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 282, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3708] = { + .class_hid = BNXT_ULP_CLASS_HID_3a3f4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 283, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3709] = { + .class_hid = BNXT_ULP_CLASS_HID_235a4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3710] = { + .class_hid = BNXT_ULP_CLASS_HID_2bea4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3711] = { + .class_hid = BNXT_ULP_CLASS_HID_32ba4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3712] = { + .class_hid = BNXT_ULP_CLASS_HID_3d4a4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3713] = { + .class_hid = BNXT_ULP_CLASS_HID_25d44, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3714] = { + .class_hid = BNXT_ULP_CLASS_HID_2c644, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3715] = { + .class_hid = BNXT_ULP_CLASS_HID_31438, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3716] = { + .class_hid = BNXT_ULP_CLASS_HID_38138, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3717] = { + .class_hid = BNXT_ULP_CLASS_HID_22894, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3718] = { + .class_hid = BNXT_ULP_CLASS_HID_2d594, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3719] = { + .class_hid = BNXT_ULP_CLASS_HID_35e94, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3720] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb94, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3721] = { + .class_hid = BNXT_ULP_CLASS_HID_22548, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3722] = { + .class_hid = BNXT_ULP_CLASS_HID_2ae48, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3723] = { + .class_hid = BNXT_ULP_CLASS_HID_35b48, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3724] = { + .class_hid = BNXT_ULP_CLASS_HID_3c448, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3725] = { + .class_hid = BNXT_ULP_CLASS_HID_25638, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3726] = { + .class_hid = BNXT_ULP_CLASS_HID_2c338, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3727] = { + .class_hid = BNXT_ULP_CLASS_HID_310ec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3728] = { + .class_hid = BNXT_ULP_CLASS_HID_39dec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3729] = { + .class_hid = BNXT_ULP_CLASS_HID_22998, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3730] = { + .class_hid = BNXT_ULP_CLASS_HID_2d298, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3731] = { + .class_hid = BNXT_ULP_CLASS_HID_35f98, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3732] = { + .class_hid = BNXT_ULP_CLASS_HID_3c898, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3733] = { + .class_hid = BNXT_ULP_CLASS_HID_234a8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3734] = { + .class_hid = BNXT_ULP_CLASS_HID_2a1a8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3735] = { + .class_hid = BNXT_ULP_CLASS_HID_32aa8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3736] = { + .class_hid = BNXT_ULP_CLASS_HID_3d7a8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3737] = { + .class_hid = BNXT_ULP_CLASS_HID_2319c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3738] = { + .class_hid = BNXT_ULP_CLASS_HID_2ba9c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3739] = { + .class_hid = BNXT_ULP_CLASS_HID_3279c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3740] = { + .class_hid = BNXT_ULP_CLASS_HID_3d09c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3741] = { + .class_hid = BNXT_ULP_CLASS_HID_2224c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3742] = { + .class_hid = BNXT_ULP_CLASS_HID_2af4c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3743] = { + .class_hid = BNXT_ULP_CLASS_HID_3584c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3744] = { + .class_hid = BNXT_ULP_CLASS_HID_3c54c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3745] = { + .class_hid = BNXT_ULP_CLASS_HID_24dec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3746] = { + .class_hid = BNXT_ULP_CLASS_HID_29ba0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3747] = { + .class_hid = BNXT_ULP_CLASS_HID_304a0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3748] = { + .class_hid = BNXT_ULP_CLASS_HID_3b1a0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3749] = { + .class_hid = BNXT_ULP_CLASS_HID_2593c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3750] = { + .class_hid = BNXT_ULP_CLASS_HID_2c23c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3751] = { + .class_hid = BNXT_ULP_CLASS_HID_313f0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3752] = { + .class_hid = BNXT_ULP_CLASS_HID_39cf0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3753] = { + .class_hid = BNXT_ULP_CLASS_HID_255f0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3754] = { + .class_hid = BNXT_ULP_CLASS_HID_2def0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3755] = { + .class_hid = BNXT_ULP_CLASS_HID_34bf0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3756] = { + .class_hid = BNXT_ULP_CLASS_HID_399a4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3757] = { + .class_hid = BNXT_ULP_CLASS_HID_246a0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3758] = { + .class_hid = BNXT_ULP_CLASS_HID_29494, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3759] = { + .class_hid = BNXT_ULP_CLASS_HID_30194, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3760] = { + .class_hid = BNXT_ULP_CLASS_HID_38a94, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3761] = { + .class_hid = BNXT_ULP_CLASS_HID_23334, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3762] = { + .class_hid = BNXT_ULP_CLASS_HID_2bc34, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3763] = { + .class_hid = BNXT_ULP_CLASS_HID_32934, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3764] = { + .class_hid = BNXT_ULP_CLASS_HID_3d234, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3765] = { + .class_hid = BNXT_ULP_CLASS_HID_21e44, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3766] = { + .class_hid = BNXT_ULP_CLASS_HID_28b44, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3767] = { + .class_hid = BNXT_ULP_CLASS_HID_33444, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3768] = { + .class_hid = BNXT_ULP_CLASS_HID_3a144, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3769] = { + .class_hid = BNXT_ULP_CLASS_HID_21b38, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3770] = { + .class_hid = BNXT_ULP_CLASS_HID_28438, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3771] = { + .class_hid = BNXT_ULP_CLASS_HID_33138, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3772] = { + .class_hid = BNXT_ULP_CLASS_HID_3ba38, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3773] = { + .class_hid = BNXT_ULP_CLASS_HID_20fe8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3774] = { + .class_hid = BNXT_ULP_CLASS_HID_2b8e8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3775] = { + .class_hid = BNXT_ULP_CLASS_HID_325e8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3776] = { + .class_hid = BNXT_ULP_CLASS_HID_3aee8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3777] = { + .class_hid = BNXT_ULP_CLASS_HID_25788, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3778] = { + .class_hid = BNXT_ULP_CLASS_HID_2c088, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3779] = { + .class_hid = BNXT_ULP_CLASS_HID_34d88, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3780] = { + .class_hid = BNXT_ULP_CLASS_HID_39b7c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3781] = { + .class_hid = BNXT_ULP_CLASS_HID_222d8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3782] = { + .class_hid = BNXT_ULP_CLASS_HID_2afd8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3783] = { + .class_hid = BNXT_ULP_CLASS_HID_358d8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3784] = { + .class_hid = BNXT_ULP_CLASS_HID_3c5d8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3785] = { + .class_hid = BNXT_ULP_CLASS_HID_23f8c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3786] = { + .class_hid = BNXT_ULP_CLASS_HID_2a88c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3787] = { + .class_hid = BNXT_ULP_CLASS_HID_3558c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3788] = { + .class_hid = BNXT_ULP_CLASS_HID_3de8c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3789] = { + .class_hid = BNXT_ULP_CLASS_HID_2507c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3790] = { + .class_hid = BNXT_ULP_CLASS_HID_2dd7c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3791] = { + .class_hid = BNXT_ULP_CLASS_HID_3467c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3792] = { + .class_hid = BNXT_ULP_CLASS_HID_39430, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3793] = { + .class_hid = BNXT_ULP_CLASS_HID_223dc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3794] = { + .class_hid = BNXT_ULP_CLASS_HID_2acdc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3795] = { + .class_hid = BNXT_ULP_CLASS_HID_359dc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3796] = { + .class_hid = BNXT_ULP_CLASS_HID_3c2dc, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3797] = { + .class_hid = BNXT_ULP_CLASS_HID_20eec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3798] = { + .class_hid = BNXT_ULP_CLASS_HID_2bbec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3799] = { + .class_hid = BNXT_ULP_CLASS_HID_324ec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3800] = { + .class_hid = BNXT_ULP_CLASS_HID_3d1ec, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3801] = { + .class_hid = BNXT_ULP_CLASS_HID_20ba0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3802] = { + .class_hid = BNXT_ULP_CLASS_HID_2b4a0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3803] = { + .class_hid = BNXT_ULP_CLASS_HID_321a0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3804] = { + .class_hid = BNXT_ULP_CLASS_HID_3aaa0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3805] = { + .class_hid = BNXT_ULP_CLASS_HID_23c90, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3806] = { + .class_hid = BNXT_ULP_CLASS_HID_2a990, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3807] = { + .class_hid = BNXT_ULP_CLASS_HID_35290, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3808] = { + .class_hid = BNXT_ULP_CLASS_HID_3df90, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3809] = { + .class_hid = BNXT_ULP_CLASS_HID_24430, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3810] = { + .class_hid = BNXT_ULP_CLASS_HID_295e4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3811] = { + .class_hid = BNXT_ULP_CLASS_HID_31ee4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3812] = { + .class_hid = BNXT_ULP_CLASS_HID_38be4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3813] = { + .class_hid = BNXT_ULP_CLASS_HID_25340, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3814] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc40, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3815] = { + .class_hid = BNXT_ULP_CLASS_HID_34940, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3816] = { + .class_hid = BNXT_ULP_CLASS_HID_39734, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3817] = { + .class_hid = BNXT_ULP_CLASS_HID_22c34, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3818] = { + .class_hid = BNXT_ULP_CLASS_HID_2d934, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3819] = { + .class_hid = BNXT_ULP_CLASS_HID_34234, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3820] = { + .class_hid = BNXT_ULP_CLASS_HID_393e8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3821] = { + .class_hid = BNXT_ULP_CLASS_HID_240e4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3822] = { + .class_hid = BNXT_ULP_CLASS_HID_2cde4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3823] = { + .class_hid = BNXT_ULP_CLASS_HID_31bd8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3824] = { + .class_hid = BNXT_ULP_CLASS_HID_384d8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3825] = { + .class_hid = BNXT_ULP_CLASS_HID_23de0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3826] = { + .class_hid = BNXT_ULP_CLASS_HID_2a6e0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3827] = { + .class_hid = BNXT_ULP_CLASS_HID_353e0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3828] = { + .class_hid = BNXT_ULP_CLASS_HID_3dce0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3829] = { + .class_hid = BNXT_ULP_CLASS_HID_20930, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3830] = { + .class_hid = BNXT_ULP_CLASS_HID_2b230, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3831] = { + .class_hid = BNXT_ULP_CLASS_HID_33f30, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3832] = { + .class_hid = BNXT_ULP_CLASS_HID_3a830, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3833] = { + .class_hid = BNXT_ULP_CLASS_HID_205e4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3834] = { + .class_hid = BNXT_ULP_CLASS_HID_28ee4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [51] = { - .class_hid = BNXT_ULP_CLASS_HID_0013, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6, + [3835] = { + .class_hid = BNXT_ULP_CLASS_HID_33be4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [52] = { - .class_hid = BNXT_ULP_CLASS_HID_001c, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6, + [3836] = { + .class_hid = BNXT_ULP_CLASS_HID_3a4e4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [53] = { - .class_hid = BNXT_ULP_CLASS_HID_017b, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6, + [3837] = { + .class_hid = BNXT_ULP_CLASS_HID_236d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [54] = { - .class_hid = BNXT_ULP_CLASS_HID_0164, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3838] = { + .class_hid = BNXT_ULP_CLASS_HID_2a3d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [55] = { - .class_hid = BNXT_ULP_CLASS_HID_00c3, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3839] = { + .class_hid = BNXT_ULP_CLASS_HID_32cd4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [56] = { - .class_hid = BNXT_ULP_CLASS_HID_00cc, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3840] = { + .class_hid = BNXT_ULP_CLASS_HID_3d9d4, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [57] = { - .class_hid = BNXT_ULP_CLASS_HID_01a5, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3841] = { + .class_hid = BNXT_ULP_CLASS_HID_25e74, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [58] = { - .class_hid = BNXT_ULP_CLASS_HID_0196, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3842] = { + .class_hid = BNXT_ULP_CLASS_HID_2cb74, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [59] = { - .class_hid = BNXT_ULP_CLASS_HID_010d, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3843] = { + .class_hid = BNXT_ULP_CLASS_HID_31928, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [60] = { - .class_hid = BNXT_ULP_CLASS_HID_00fe, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3844] = { + .class_hid = BNXT_ULP_CLASS_HID_38228, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [61] = { - .class_hid = BNXT_ULP_CLASS_HID_0084, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3845] = { + .class_hid = BNXT_ULP_CLASS_HID_22d84, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [62] = { - .class_hid = BNXT_ULP_CLASS_HID_0046, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3846] = { + .class_hid = BNXT_ULP_CLASS_HID_2d684, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [63] = { - .class_hid = BNXT_ULP_CLASS_HID_01ec, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3847] = { + .class_hid = BNXT_ULP_CLASS_HID_34384, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [64] = { - .class_hid = BNXT_ULP_CLASS_HID_01ae, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 7, + [3848] = { + .class_hid = BNXT_ULP_CLASS_HID_39178, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [65] = { - .class_hid = BNXT_ULP_CLASS_HID_00d3, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 7, + [3849] = { + .class_hid = BNXT_ULP_CLASS_HID_22678, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [66] = { - .class_hid = BNXT_ULP_CLASS_HID_00ac, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 7, + [3850] = { + .class_hid = BNXT_ULP_CLASS_HID_2d378, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [67] = { - .class_hid = BNXT_ULP_CLASS_HID_000b, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 7, + [3851] = { + .class_hid = BNXT_ULP_CLASS_HID_35c78, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [68] = { - .class_hid = BNXT_ULP_CLASS_HID_0004, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 7, + [3852] = { + .class_hid = BNXT_ULP_CLASS_HID_3c978, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [69] = { - .class_hid = BNXT_ULP_CLASS_HID_0163, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 7, + [3853] = { + .class_hid = BNXT_ULP_CLASS_HID_25b28, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [70] = { - .class_hid = BNXT_ULP_CLASS_HID_017c, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3854] = { + .class_hid = BNXT_ULP_CLASS_HID_2c428, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [71] = { - .class_hid = BNXT_ULP_CLASS_HID_00db, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3855] = { + .class_hid = BNXT_ULP_CLASS_HID_3121c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [72] = { - .class_hid = BNXT_ULP_CLASS_HID_00d4, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3856] = { + .class_hid = BNXT_ULP_CLASS_HID_39f1c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [73] = { - .class_hid = BNXT_ULP_CLASS_HID_01bd, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3857] = { + .class_hid = BNXT_ULP_CLASS_HID_3488, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [74] = { - .class_hid = BNXT_ULP_CLASS_HID_018e, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3858] = { + .class_hid = BNXT_ULP_CLASS_HID_3a44, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [75] = { - .class_hid = BNXT_ULP_CLASS_HID_0115, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3859] = { + .class_hid = BNXT_ULP_CLASS_HID_5ed8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [76] = { - .class_hid = BNXT_ULP_CLASS_HID_00e6, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3860] = { + .class_hid = BNXT_ULP_CLASS_HID_07e0, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [77] = { - .class_hid = BNXT_ULP_CLASS_HID_009c, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3861] = { + .class_hid = BNXT_ULP_CLASS_HID_2874, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [78] = { - .class_hid = BNXT_ULP_CLASS_HID_005e, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3862] = { + .class_hid = BNXT_ULP_CLASS_HID_591c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [79] = { - .class_hid = BNXT_ULP_CLASS_HID_01f4, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3863] = { + .class_hid = BNXT_ULP_CLASS_HID_1e24, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [80] = { - .class_hid = BNXT_ULP_CLASS_HID_01b6, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, + [3864] = { + .class_hid = BNXT_ULP_CLASS_HID_22b8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index a38e3de6fa..7c6a93e4d5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 8 14:57:13 2020 */ +/* date: Thu Dec 17 19:43:07 2020 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -12,43 +12,43 @@ #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 #define BNXT_ULP_GEN_TBL_MAX_SZ 6 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 512 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 81 -#define BNXT_ULP_CLASS_HID_LOW_PRIME 4049 -#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919 -#define BNXT_ULP_CLASS_HID_SHFTR 25 -#define BNXT_ULP_CLASS_HID_SHFTL 23 -#define BNXT_ULP_CLASS_HID_MASK 511 +#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 262144 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 3865 +#define BNXT_ULP_CLASS_HID_LOW_PRIME 5939 +#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7669 +#define BNXT_ULP_CLASS_HID_SHFTR 31 +#define BNXT_ULP_CLASS_HID_SHFTL 31 +#define BNXT_ULP_CLASS_HID_MASK 262143 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 30 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 -#define BNXT_ULP_ACT_HID_HIGH_PRIME 6701 -#define BNXT_ULP_ACT_HID_SHFTR 24 -#define BNXT_ULP_ACT_HID_SHFTL 23 +#define BNXT_ULP_ACT_HID_HIGH_PRIME 3793 +#define BNXT_ULP_ACT_HID_SHFTR 27 +#define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 -#define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033 -#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 257 -#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 11 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 367 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 14 +#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5593 +#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 63 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 412 +#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 17 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 503 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 16 #define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7 #define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38 #define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192 #define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10 #define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341 #define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10 -#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 3 -#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 11 +#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 -#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 132 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 13 +#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 26 #define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2 #define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4 #define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0 @@ -202,7 +202,9 @@ enum bnxt_ulp_cond_opc { BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7, BNXT_ULP_COND_OPC_RF_IS_SET = 8, BNXT_ULP_COND_OPC_RF_NOT_SET = 9, - BNXT_ULP_COND_OPC_LAST = 10 + BNXT_ULP_COND_OPC_FLOW_PAT_MATCH = 10, + BNXT_ULP_COND_OPC_ACT_PAT_MATCH = 11, + BNXT_ULP_COND_OPC_LAST = 12 }; enum bnxt_ulp_critical_resource { @@ -231,9 +233,9 @@ enum bnxt_ulp_direction { }; enum bnxt_ulp_fdb_opc { - BNXT_ULP_FDB_OPC_PUSH = 0, - BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE = 1, - BNXT_ULP_FDB_OPC_PUSH_REGFILE = 2, + BNXT_ULP_FDB_OPC_PUSH_FID = 0, + BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1, + BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE = 2, BNXT_ULP_FDB_OPC_NOP = 3, BNXT_ULP_FDB_OPC_LAST = 4 }; @@ -252,7 +254,9 @@ enum bnxt_ulp_field_cond_src { BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3, BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4, BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5, - BNXT_ULP_FIELD_COND_SRC_LAST = 6 + BNXT_ULP_FIELD_COND_SRC_FLOW_PAT_MATCH = 6, + BNXT_ULP_FIELD_COND_SRC_ACT_PAT_MATCH = 7, + BNXT_ULP_FIELD_COND_SRC_LAST = 8 }; enum bnxt_ulp_field_opc { @@ -266,19 +270,20 @@ enum bnxt_ulp_field_opc { enum bnxt_ulp_field_src { BNXT_ULP_FIELD_SRC_ZERO = 0, - BNXT_ULP_FIELD_SRC_CONST = 1, - BNXT_ULP_FIELD_SRC_CF = 2, - BNXT_ULP_FIELD_SRC_RF = 3, - BNXT_ULP_FIELD_SRC_ACT_PROP = 4, - BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 5, - BNXT_ULP_FIELD_SRC_GLB_RF = 6, - BNXT_ULP_FIELD_SRC_HF = 7, - BNXT_ULP_FIELD_SRC_HDR_BIT = 8, - BNXT_ULP_FIELD_SRC_ACT_BIT = 9, - BNXT_ULP_FIELD_SRC_FIELD_BIT = 10, - BNXT_ULP_FIELD_SRC_SKIP = 11, - BNXT_ULP_FIELD_SRC_REJECT = 12, - BNXT_ULP_FIELD_SRC_LAST = 13 + BNXT_ULP_FIELD_SRC_ONES = 1, + BNXT_ULP_FIELD_SRC_CONST = 2, + BNXT_ULP_FIELD_SRC_CF = 3, + BNXT_ULP_FIELD_SRC_RF = 4, + BNXT_ULP_FIELD_SRC_ACT_PROP = 5, + BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 6, + BNXT_ULP_FIELD_SRC_GLB_RF = 7, + BNXT_ULP_FIELD_SRC_HF = 8, + BNXT_ULP_FIELD_SRC_HDR_BIT = 9, + BNXT_ULP_FIELD_SRC_ACT_BIT = 10, + BNXT_ULP_FIELD_SRC_FIELD_BIT = 11, + BNXT_ULP_FIELD_SRC_SKIP = 12, + BNXT_ULP_FIELD_SRC_REJECT = 13, + BNXT_ULP_FIELD_SRC_LAST = 14 }; enum bnxt_ulp_generic_tbl_opc { @@ -429,7 +434,7 @@ enum bnxt_ulp_resource_func { BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85, BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86, BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87, - BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE = 0x88 + BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE = 0x88 }; enum bnxt_ulp_resource_sub_type { @@ -973,126 +978,3965 @@ enum ulp_sr_sym { }; enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_005c = 0x005c, - BNXT_ULP_CLASS_HID_0003 = 0x0003, - BNXT_ULP_CLASS_HID_0132 = 0x0132, - BNXT_ULP_CLASS_HID_00e1 = 0x00e1, - BNXT_ULP_CLASS_HID_0044 = 0x0044, - BNXT_ULP_CLASS_HID_001b = 0x001b, - BNXT_ULP_CLASS_HID_012a = 0x012a, - BNXT_ULP_CLASS_HID_00f9 = 0x00f9, - BNXT_ULP_CLASS_HID_018d = 0x018d, - BNXT_ULP_CLASS_HID_00a7 = 0x00a7, - BNXT_ULP_CLASS_HID_006f = 0x006f, - BNXT_ULP_CLASS_HID_0181 = 0x0181, - BNXT_ULP_CLASS_HID_0195 = 0x0195, - BNXT_ULP_CLASS_HID_00bf = 0x00bf, - BNXT_ULP_CLASS_HID_0077 = 0x0077, - BNXT_ULP_CLASS_HID_0199 = 0x0199, - BNXT_ULP_CLASS_HID_009a = 0x009a, - BNXT_ULP_CLASS_HID_0192 = 0x0192, - BNXT_ULP_CLASS_HID_01e2 = 0x01e2, - BNXT_ULP_CLASS_HID_00fa = 0x00fa, - BNXT_ULP_CLASS_HID_0165 = 0x0165, - BNXT_ULP_CLASS_HID_0042 = 0x0042, - BNXT_ULP_CLASS_HID_00cd = 0x00cd, - BNXT_ULP_CLASS_HID_01aa = 0x01aa, - BNXT_ULP_CLASS_HID_0178 = 0x0178, - BNXT_ULP_CLASS_HID_0070 = 0x0070, - BNXT_ULP_CLASS_HID_00f3 = 0x00f3, - BNXT_ULP_CLASS_HID_01d8 = 0x01d8, - BNXT_ULP_CLASS_HID_005b = 0x005b, - BNXT_ULP_CLASS_HID_0153 = 0x0153, - BNXT_ULP_CLASS_HID_01a3 = 0x01a3, - BNXT_ULP_CLASS_HID_00bb = 0x00bb, - BNXT_ULP_CLASS_HID_0082 = 0x0082, - BNXT_ULP_CLASS_HID_018a = 0x018a, - BNXT_ULP_CLASS_HID_01fa = 0x01fa, - BNXT_ULP_CLASS_HID_00e2 = 0x00e2, - BNXT_ULP_CLASS_HID_017d = 0x017d, - BNXT_ULP_CLASS_HID_005a = 0x005a, - BNXT_ULP_CLASS_HID_00d5 = 0x00d5, - BNXT_ULP_CLASS_HID_01b2 = 0x01b2, - BNXT_ULP_CLASS_HID_0160 = 0x0160, - BNXT_ULP_CLASS_HID_0068 = 0x0068, - BNXT_ULP_CLASS_HID_00eb = 0x00eb, - BNXT_ULP_CLASS_HID_01c0 = 0x01c0, - BNXT_ULP_CLASS_HID_0043 = 0x0043, - BNXT_ULP_CLASS_HID_014b = 0x014b, - BNXT_ULP_CLASS_HID_01bb = 0x01bb, - BNXT_ULP_CLASS_HID_00a3 = 0x00a3, - BNXT_ULP_CLASS_HID_00cb = 0x00cb, - BNXT_ULP_CLASS_HID_00b4 = 0x00b4, - BNXT_ULP_CLASS_HID_0013 = 0x0013, - BNXT_ULP_CLASS_HID_001c = 0x001c, - BNXT_ULP_CLASS_HID_017b = 0x017b, - BNXT_ULP_CLASS_HID_0164 = 0x0164, - BNXT_ULP_CLASS_HID_00c3 = 0x00c3, - BNXT_ULP_CLASS_HID_00cc = 0x00cc, - BNXT_ULP_CLASS_HID_01a5 = 0x01a5, - BNXT_ULP_CLASS_HID_0196 = 0x0196, - BNXT_ULP_CLASS_HID_010d = 0x010d, - BNXT_ULP_CLASS_HID_00fe = 0x00fe, - BNXT_ULP_CLASS_HID_0084 = 0x0084, - BNXT_ULP_CLASS_HID_0046 = 0x0046, - BNXT_ULP_CLASS_HID_01ec = 0x01ec, - BNXT_ULP_CLASS_HID_01ae = 0x01ae, - BNXT_ULP_CLASS_HID_00d3 = 0x00d3, - BNXT_ULP_CLASS_HID_00ac = 0x00ac, - BNXT_ULP_CLASS_HID_000b = 0x000b, - BNXT_ULP_CLASS_HID_0004 = 0x0004, - BNXT_ULP_CLASS_HID_0163 = 0x0163, - BNXT_ULP_CLASS_HID_017c = 0x017c, - BNXT_ULP_CLASS_HID_00db = 0x00db, - BNXT_ULP_CLASS_HID_00d4 = 0x00d4, - BNXT_ULP_CLASS_HID_01bd = 0x01bd, - BNXT_ULP_CLASS_HID_018e = 0x018e, - BNXT_ULP_CLASS_HID_0115 = 0x0115, + BNXT_ULP_CLASS_HID_26d1 = 0x26d1, + BNXT_ULP_CLASS_HID_0071 = 0x0071, + BNXT_ULP_CLASS_HID_53a5 = 0x53a5, + BNXT_ULP_CLASS_HID_1d49 = 0x1d49, + BNXT_ULP_CLASS_HID_2095 = 0x2095, + BNXT_ULP_CLASS_HID_5701 = 0x5701, + BNXT_ULP_CLASS_HID_4d79 = 0x4d79, + BNXT_ULP_CLASS_HID_170d = 0x170d, + BNXT_ULP_CLASS_HID_1a69 = 0x1a69, + BNXT_ULP_CLASS_HID_50c5 = 0x50c5, + BNXT_ULP_CLASS_HID_473d = 0x473d, + BNXT_ULP_CLASS_HID_10c1 = 0x10c1, + BNXT_ULP_CLASS_HID_142d = 0x142d, + BNXT_ULP_CLASS_HID_4a99 = 0x4a99, + BNXT_ULP_CLASS_HID_40f1 = 0x40f1, + BNXT_ULP_CLASS_HID_0a85 = 0x0a85, + BNXT_ULP_CLASS_HID_0179 = 0x0179, + BNXT_ULP_CLASS_HID_37d5 = 0x37d5, + BNXT_ULP_CLASS_HID_2e4d = 0x2e4d, + BNXT_ULP_CLASS_HID_54ad = 0x54ad, + BNXT_ULP_CLASS_HID_5809 = 0x5809, + BNXT_ULP_CLASS_HID_31a9 = 0x31a9, + BNXT_ULP_CLASS_HID_2801 = 0x2801, + BNXT_ULP_CLASS_HID_4e61 = 0x4e61, + BNXT_ULP_CLASS_HID_2561 = 0x2561, + BNXT_ULP_CLASS_HID_2bad = 0x2bad, + BNXT_ULP_CLASS_HID_26f1 = 0x26f1, + BNXT_ULP_CLASS_HID_13cf1 = 0x13cf1, + BNXT_ULP_CLASS_HID_252f1 = 0x252f1, + BNXT_ULP_CLASS_HID_30c25 = 0x30c25, + BNXT_ULP_CLASS_HID_0051 = 0x0051, + BNXT_ULP_CLASS_HID_11651 = 0x11651, + BNXT_ULP_CLASS_HID_22c51 = 0x22c51, + BNXT_ULP_CLASS_HID_34251 = 0x34251, + BNXT_ULP_CLASS_HID_5385 = 0x5385, + BNXT_ULP_CLASS_HID_10cc9 = 0x10cc9, + BNXT_ULP_CLASS_HID_222c9 = 0x222c9, + BNXT_ULP_CLASS_HID_338c9 = 0x338c9, + BNXT_ULP_CLASS_HID_1d69 = 0x1d69, + BNXT_ULP_CLASS_HID_13369 = 0x13369, + BNXT_ULP_CLASS_HID_24969 = 0x24969, + BNXT_ULP_CLASS_HID_3025d = 0x3025d, + BNXT_ULP_CLASS_HID_20b5 = 0x20b5, + BNXT_ULP_CLASS_HID_136b5 = 0x136b5, + BNXT_ULP_CLASS_HID_24cb5 = 0x24cb5, + BNXT_ULP_CLASS_HID_305f9 = 0x305f9, + BNXT_ULP_CLASS_HID_5721 = 0x5721, + BNXT_ULP_CLASS_HID_11015 = 0x11015, + BNXT_ULP_CLASS_HID_22615 = 0x22615, + BNXT_ULP_CLASS_HID_33c15 = 0x33c15, + BNXT_ULP_CLASS_HID_4d59 = 0x4d59, + BNXT_ULP_CLASS_HID_1068d = 0x1068d, + BNXT_ULP_CLASS_HID_21c8d = 0x21c8d, + BNXT_ULP_CLASS_HID_3328d = 0x3328d, + BNXT_ULP_CLASS_HID_172d = 0x172d, + BNXT_ULP_CLASS_HID_12d2d = 0x12d2d, + BNXT_ULP_CLASS_HID_2432d = 0x2432d, + BNXT_ULP_CLASS_HID_3592d = 0x3592d, + BNXT_ULP_CLASS_HID_1a49 = 0x1a49, + BNXT_ULP_CLASS_HID_13049 = 0x13049, + BNXT_ULP_CLASS_HID_24649 = 0x24649, + BNXT_ULP_CLASS_HID_35c49 = 0x35c49, + BNXT_ULP_CLASS_HID_50e5 = 0x50e5, + BNXT_ULP_CLASS_HID_10a29 = 0x10a29, + BNXT_ULP_CLASS_HID_22029 = 0x22029, + BNXT_ULP_CLASS_HID_33629 = 0x33629, + BNXT_ULP_CLASS_HID_471d = 0x471d, + BNXT_ULP_CLASS_HID_10041 = 0x10041, + BNXT_ULP_CLASS_HID_21641 = 0x21641, + BNXT_ULP_CLASS_HID_32c41 = 0x32c41, + BNXT_ULP_CLASS_HID_10e1 = 0x10e1, + BNXT_ULP_CLASS_HID_126e1 = 0x126e1, + BNXT_ULP_CLASS_HID_23ce1 = 0x23ce1, + BNXT_ULP_CLASS_HID_352e1 = 0x352e1, + BNXT_ULP_CLASS_HID_140d = 0x140d, + BNXT_ULP_CLASS_HID_12a0d = 0x12a0d, + BNXT_ULP_CLASS_HID_2400d = 0x2400d, + BNXT_ULP_CLASS_HID_3560d = 0x3560d, + BNXT_ULP_CLASS_HID_4ab9 = 0x4ab9, + BNXT_ULP_CLASS_HID_103ed = 0x103ed, + BNXT_ULP_CLASS_HID_219ed = 0x219ed, + BNXT_ULP_CLASS_HID_32fed = 0x32fed, + BNXT_ULP_CLASS_HID_40d1 = 0x40d1, + BNXT_ULP_CLASS_HID_156d1 = 0x156d1, + BNXT_ULP_CLASS_HID_21005 = 0x21005, + BNXT_ULP_CLASS_HID_32605 = 0x32605, + BNXT_ULP_CLASS_HID_0aa5 = 0x0aa5, + BNXT_ULP_CLASS_HID_120a5 = 0x120a5, + BNXT_ULP_CLASS_HID_236a5 = 0x236a5, + BNXT_ULP_CLASS_HID_34ca5 = 0x34ca5, + BNXT_ULP_CLASS_HID_0159 = 0x0159, + BNXT_ULP_CLASS_HID_11759 = 0x11759, + BNXT_ULP_CLASS_HID_22d59 = 0x22d59, + BNXT_ULP_CLASS_HID_34359 = 0x34359, + BNXT_ULP_CLASS_HID_37f5 = 0x37f5, + BNXT_ULP_CLASS_HID_14df5 = 0x14df5, + BNXT_ULP_CLASS_HID_20739 = 0x20739, + BNXT_ULP_CLASS_HID_31d39 = 0x31d39, + BNXT_ULP_CLASS_HID_2e6d = 0x2e6d, + BNXT_ULP_CLASS_HID_1446d = 0x1446d, + BNXT_ULP_CLASS_HID_25a6d = 0x25a6d, + BNXT_ULP_CLASS_HID_31351 = 0x31351, + BNXT_ULP_CLASS_HID_548d = 0x548d, + BNXT_ULP_CLASS_HID_10df1 = 0x10df1, + BNXT_ULP_CLASS_HID_223f1 = 0x223f1, + BNXT_ULP_CLASS_HID_339f1 = 0x339f1, + BNXT_ULP_CLASS_HID_5829 = 0x5829, + BNXT_ULP_CLASS_HID_1111d = 0x1111d, + BNXT_ULP_CLASS_HID_2271d = 0x2271d, + BNXT_ULP_CLASS_HID_33d1d = 0x33d1d, + BNXT_ULP_CLASS_HID_3189 = 0x3189, + BNXT_ULP_CLASS_HID_14789 = 0x14789, + BNXT_ULP_CLASS_HID_200fd = 0x200fd, + BNXT_ULP_CLASS_HID_316fd = 0x316fd, + BNXT_ULP_CLASS_HID_2821 = 0x2821, + BNXT_ULP_CLASS_HID_13e21 = 0x13e21, + BNXT_ULP_CLASS_HID_25421 = 0x25421, + BNXT_ULP_CLASS_HID_30d15 = 0x30d15, + BNXT_ULP_CLASS_HID_4e41 = 0x4e41, + BNXT_ULP_CLASS_HID_107b5 = 0x107b5, + BNXT_ULP_CLASS_HID_21db5 = 0x21db5, + BNXT_ULP_CLASS_HID_333b5 = 0x333b5, + BNXT_ULP_CLASS_HID_2541 = 0x2541, + BNXT_ULP_CLASS_HID_2b8d = 0x2b8d, + BNXT_ULP_CLASS_HID_2691 = 0x2691, + BNXT_ULP_CLASS_HID_13c91 = 0x13c91, + BNXT_ULP_CLASS_HID_25291 = 0x25291, + BNXT_ULP_CLASS_HID_30c45 = 0x30c45, + BNXT_ULP_CLASS_HID_0031 = 0x0031, + BNXT_ULP_CLASS_HID_11631 = 0x11631, + BNXT_ULP_CLASS_HID_22c31 = 0x22c31, + BNXT_ULP_CLASS_HID_34231 = 0x34231, + BNXT_ULP_CLASS_HID_53e5 = 0x53e5, + BNXT_ULP_CLASS_HID_10ca9 = 0x10ca9, + BNXT_ULP_CLASS_HID_222a9 = 0x222a9, + BNXT_ULP_CLASS_HID_338a9 = 0x338a9, + BNXT_ULP_CLASS_HID_1d09 = 0x1d09, + BNXT_ULP_CLASS_HID_13309 = 0x13309, + BNXT_ULP_CLASS_HID_24909 = 0x24909, + BNXT_ULP_CLASS_HID_3023d = 0x3023d, + BNXT_ULP_CLASS_HID_20d5 = 0x20d5, + BNXT_ULP_CLASS_HID_136d5 = 0x136d5, + BNXT_ULP_CLASS_HID_24cd5 = 0x24cd5, + BNXT_ULP_CLASS_HID_30599 = 0x30599, + BNXT_ULP_CLASS_HID_5741 = 0x5741, + BNXT_ULP_CLASS_HID_11075 = 0x11075, + BNXT_ULP_CLASS_HID_22675 = 0x22675, + BNXT_ULP_CLASS_HID_33c75 = 0x33c75, + BNXT_ULP_CLASS_HID_4d39 = 0x4d39, + BNXT_ULP_CLASS_HID_106ed = 0x106ed, + BNXT_ULP_CLASS_HID_21ced = 0x21ced, + BNXT_ULP_CLASS_HID_332ed = 0x332ed, + BNXT_ULP_CLASS_HID_174d = 0x174d, + BNXT_ULP_CLASS_HID_12d4d = 0x12d4d, + BNXT_ULP_CLASS_HID_2434d = 0x2434d, + BNXT_ULP_CLASS_HID_3594d = 0x3594d, + BNXT_ULP_CLASS_HID_1a29 = 0x1a29, + BNXT_ULP_CLASS_HID_13029 = 0x13029, + BNXT_ULP_CLASS_HID_24629 = 0x24629, + BNXT_ULP_CLASS_HID_35c29 = 0x35c29, + BNXT_ULP_CLASS_HID_5085 = 0x5085, + BNXT_ULP_CLASS_HID_10a49 = 0x10a49, + BNXT_ULP_CLASS_HID_22049 = 0x22049, + BNXT_ULP_CLASS_HID_33649 = 0x33649, + BNXT_ULP_CLASS_HID_477d = 0x477d, + BNXT_ULP_CLASS_HID_10021 = 0x10021, + BNXT_ULP_CLASS_HID_21621 = 0x21621, + BNXT_ULP_CLASS_HID_32c21 = 0x32c21, + BNXT_ULP_CLASS_HID_1081 = 0x1081, + BNXT_ULP_CLASS_HID_12681 = 0x12681, + BNXT_ULP_CLASS_HID_23c81 = 0x23c81, + BNXT_ULP_CLASS_HID_35281 = 0x35281, + BNXT_ULP_CLASS_HID_146d = 0x146d, + BNXT_ULP_CLASS_HID_12a6d = 0x12a6d, + BNXT_ULP_CLASS_HID_2406d = 0x2406d, + BNXT_ULP_CLASS_HID_3566d = 0x3566d, + BNXT_ULP_CLASS_HID_4ad9 = 0x4ad9, + BNXT_ULP_CLASS_HID_1038d = 0x1038d, + BNXT_ULP_CLASS_HID_2198d = 0x2198d, + BNXT_ULP_CLASS_HID_32f8d = 0x32f8d, + BNXT_ULP_CLASS_HID_40b1 = 0x40b1, + BNXT_ULP_CLASS_HID_156b1 = 0x156b1, + BNXT_ULP_CLASS_HID_21065 = 0x21065, + BNXT_ULP_CLASS_HID_32665 = 0x32665, + BNXT_ULP_CLASS_HID_0ac5 = 0x0ac5, + BNXT_ULP_CLASS_HID_120c5 = 0x120c5, + BNXT_ULP_CLASS_HID_236c5 = 0x236c5, + BNXT_ULP_CLASS_HID_34cc5 = 0x34cc5, + BNXT_ULP_CLASS_HID_0139 = 0x0139, + BNXT_ULP_CLASS_HID_11739 = 0x11739, + BNXT_ULP_CLASS_HID_22d39 = 0x22d39, + BNXT_ULP_CLASS_HID_34339 = 0x34339, + BNXT_ULP_CLASS_HID_3795 = 0x3795, + BNXT_ULP_CLASS_HID_14d95 = 0x14d95, + BNXT_ULP_CLASS_HID_20759 = 0x20759, + BNXT_ULP_CLASS_HID_31d59 = 0x31d59, + BNXT_ULP_CLASS_HID_2e0d = 0x2e0d, + BNXT_ULP_CLASS_HID_1440d = 0x1440d, + BNXT_ULP_CLASS_HID_25a0d = 0x25a0d, + BNXT_ULP_CLASS_HID_31331 = 0x31331, + BNXT_ULP_CLASS_HID_54ed = 0x54ed, + BNXT_ULP_CLASS_HID_10d91 = 0x10d91, + BNXT_ULP_CLASS_HID_22391 = 0x22391, + BNXT_ULP_CLASS_HID_33991 = 0x33991, + BNXT_ULP_CLASS_HID_5849 = 0x5849, + BNXT_ULP_CLASS_HID_1117d = 0x1117d, + BNXT_ULP_CLASS_HID_2277d = 0x2277d, + BNXT_ULP_CLASS_HID_33d7d = 0x33d7d, + BNXT_ULP_CLASS_HID_31e9 = 0x31e9, + BNXT_ULP_CLASS_HID_147e9 = 0x147e9, + BNXT_ULP_CLASS_HID_2009d = 0x2009d, + BNXT_ULP_CLASS_HID_3169d = 0x3169d, + BNXT_ULP_CLASS_HID_2841 = 0x2841, + BNXT_ULP_CLASS_HID_13e41 = 0x13e41, + BNXT_ULP_CLASS_HID_25441 = 0x25441, + BNXT_ULP_CLASS_HID_30d75 = 0x30d75, + BNXT_ULP_CLASS_HID_4e21 = 0x4e21, + BNXT_ULP_CLASS_HID_107d5 = 0x107d5, + BNXT_ULP_CLASS_HID_21dd5 = 0x21dd5, + BNXT_ULP_CLASS_HID_333d5 = 0x333d5, + BNXT_ULP_CLASS_HID_2521 = 0x2521, + BNXT_ULP_CLASS_HID_2bed = 0x2bed, + BNXT_ULP_CLASS_HID_1865 = 0x1865, + BNXT_ULP_CLASS_HID_389d = 0x389d, + BNXT_ULP_CLASS_HID_123d = 0x123d, + BNXT_ULP_CLASS_HID_4ef1 = 0x4ef1, + BNXT_ULP_CLASS_HID_1229 = 0x1229, + BNXT_ULP_CLASS_HID_3241 = 0x3241, + BNXT_ULP_CLASS_HID_0be1 = 0x0be1, + BNXT_ULP_CLASS_HID_48b5 = 0x48b5, + BNXT_ULP_CLASS_HID_0bed = 0x0bed, + BNXT_ULP_CLASS_HID_2c05 = 0x2c05, + BNXT_ULP_CLASS_HID_05a5 = 0x05a5, + BNXT_ULP_CLASS_HID_4279 = 0x4279, + BNXT_ULP_CLASS_HID_05d1 = 0x05d1, + BNXT_ULP_CLASS_HID_25c9 = 0x25c9, + BNXT_ULP_CLASS_HID_5c55 = 0x5c55, + BNXT_ULP_CLASS_HID_3c3d = 0x3c3d, + BNXT_ULP_CLASS_HID_4fc9 = 0x4fc9, + BNXT_ULP_CLASS_HID_1335 = 0x1335, + BNXT_ULP_CLASS_HID_4981 = 0x4981, + BNXT_ULP_CLASS_HID_2969 = 0x2969, + BNXT_ULP_CLASS_HID_498d = 0x498d, + BNXT_ULP_CLASS_HID_0cf9 = 0x0cf9, + BNXT_ULP_CLASS_HID_4345 = 0x4345, + BNXT_ULP_CLASS_HID_232d = 0x232d, + BNXT_ULP_CLASS_HID_2579 = 0x2579, + BNXT_ULP_CLASS_HID_2bb5 = 0x2bb5, + BNXT_ULP_CLASS_HID_1845 = 0x1845, + BNXT_ULP_CLASS_HID_1399 = 0x1399, + BNXT_ULP_CLASS_HID_0eed = 0x0eed, + BNXT_ULP_CLASS_HID_0a21 = 0x0a21, + BNXT_ULP_CLASS_HID_38bd = 0x38bd, + BNXT_ULP_CLASS_HID_33f1 = 0x33f1, + BNXT_ULP_CLASS_HID_2ec5 = 0x2ec5, + BNXT_ULP_CLASS_HID_2a19 = 0x2a19, + BNXT_ULP_CLASS_HID_121d = 0x121d, + BNXT_ULP_CLASS_HID_0d51 = 0x0d51, + BNXT_ULP_CLASS_HID_08a5 = 0x08a5, + BNXT_ULP_CLASS_HID_03f9 = 0x03f9, + BNXT_ULP_CLASS_HID_4ed1 = 0x4ed1, + BNXT_ULP_CLASS_HID_4a25 = 0x4a25, + BNXT_ULP_CLASS_HID_4579 = 0x4579, + BNXT_ULP_CLASS_HID_404d = 0x404d, + BNXT_ULP_CLASS_HID_1209 = 0x1209, + BNXT_ULP_CLASS_HID_0d5d = 0x0d5d, + BNXT_ULP_CLASS_HID_0891 = 0x0891, + BNXT_ULP_CLASS_HID_03e5 = 0x03e5, + BNXT_ULP_CLASS_HID_3261 = 0x3261, + BNXT_ULP_CLASS_HID_2db5 = 0x2db5, + BNXT_ULP_CLASS_HID_2889 = 0x2889, + BNXT_ULP_CLASS_HID_23dd = 0x23dd, + BNXT_ULP_CLASS_HID_0bc1 = 0x0bc1, + BNXT_ULP_CLASS_HID_0715 = 0x0715, + BNXT_ULP_CLASS_HID_0269 = 0x0269, + BNXT_ULP_CLASS_HID_5a69 = 0x5a69, + BNXT_ULP_CLASS_HID_4895 = 0x4895, + BNXT_ULP_CLASS_HID_43e9 = 0x43e9, + BNXT_ULP_CLASS_HID_3f3d = 0x3f3d, + BNXT_ULP_CLASS_HID_3a71 = 0x3a71, + BNXT_ULP_CLASS_HID_0bcd = 0x0bcd, + BNXT_ULP_CLASS_HID_0701 = 0x0701, + BNXT_ULP_CLASS_HID_0255 = 0x0255, + BNXT_ULP_CLASS_HID_5a55 = 0x5a55, + BNXT_ULP_CLASS_HID_2c25 = 0x2c25, + BNXT_ULP_CLASS_HID_2779 = 0x2779, + BNXT_ULP_CLASS_HID_224d = 0x224d, + BNXT_ULP_CLASS_HID_1d81 = 0x1d81, + BNXT_ULP_CLASS_HID_0585 = 0x0585, + BNXT_ULP_CLASS_HID_00d9 = 0x00d9, + BNXT_ULP_CLASS_HID_58d9 = 0x58d9, + BNXT_ULP_CLASS_HID_542d = 0x542d, + BNXT_ULP_CLASS_HID_4259 = 0x4259, + BNXT_ULP_CLASS_HID_3dad = 0x3dad, + BNXT_ULP_CLASS_HID_38e1 = 0x38e1, + BNXT_ULP_CLASS_HID_3435 = 0x3435, + BNXT_ULP_CLASS_HID_05f1 = 0x05f1, + BNXT_ULP_CLASS_HID_00c5 = 0x00c5, + BNXT_ULP_CLASS_HID_58c5 = 0x58c5, + BNXT_ULP_CLASS_HID_5419 = 0x5419, + BNXT_ULP_CLASS_HID_25e9 = 0x25e9, + BNXT_ULP_CLASS_HID_213d = 0x213d, + BNXT_ULP_CLASS_HID_1c71 = 0x1c71, + BNXT_ULP_CLASS_HID_1745 = 0x1745, + BNXT_ULP_CLASS_HID_5c75 = 0x5c75, + BNXT_ULP_CLASS_HID_5749 = 0x5749, + BNXT_ULP_CLASS_HID_529d = 0x529d, + BNXT_ULP_CLASS_HID_4dd1 = 0x4dd1, + BNXT_ULP_CLASS_HID_3c1d = 0x3c1d, + BNXT_ULP_CLASS_HID_3751 = 0x3751, + BNXT_ULP_CLASS_HID_32a5 = 0x32a5, + BNXT_ULP_CLASS_HID_2df9 = 0x2df9, + BNXT_ULP_CLASS_HID_4fe9 = 0x4fe9, + BNXT_ULP_CLASS_HID_4b3d = 0x4b3d, + BNXT_ULP_CLASS_HID_4671 = 0x4671, + BNXT_ULP_CLASS_HID_4145 = 0x4145, + BNXT_ULP_CLASS_HID_1315 = 0x1315, + BNXT_ULP_CLASS_HID_0e69 = 0x0e69, + BNXT_ULP_CLASS_HID_09bd = 0x09bd, + BNXT_ULP_CLASS_HID_04f1 = 0x04f1, + BNXT_ULP_CLASS_HID_49a1 = 0x49a1, + BNXT_ULP_CLASS_HID_44f5 = 0x44f5, + BNXT_ULP_CLASS_HID_3fc9 = 0x3fc9, + BNXT_ULP_CLASS_HID_3b1d = 0x3b1d, + BNXT_ULP_CLASS_HID_2949 = 0x2949, + BNXT_ULP_CLASS_HID_249d = 0x249d, + BNXT_ULP_CLASS_HID_1fd1 = 0x1fd1, + BNXT_ULP_CLASS_HID_1b25 = 0x1b25, + BNXT_ULP_CLASS_HID_49ad = 0x49ad, + BNXT_ULP_CLASS_HID_44e1 = 0x44e1, + BNXT_ULP_CLASS_HID_4035 = 0x4035, + BNXT_ULP_CLASS_HID_3b09 = 0x3b09, + BNXT_ULP_CLASS_HID_0cd9 = 0x0cd9, + BNXT_ULP_CLASS_HID_082d = 0x082d, + BNXT_ULP_CLASS_HID_0361 = 0x0361, + BNXT_ULP_CLASS_HID_5b61 = 0x5b61, + BNXT_ULP_CLASS_HID_4365 = 0x4365, + BNXT_ULP_CLASS_HID_3eb9 = 0x3eb9, + BNXT_ULP_CLASS_HID_398d = 0x398d, + BNXT_ULP_CLASS_HID_34c1 = 0x34c1, + BNXT_ULP_CLASS_HID_230d = 0x230d, + BNXT_ULP_CLASS_HID_1e41 = 0x1e41, + BNXT_ULP_CLASS_HID_1995 = 0x1995, + BNXT_ULP_CLASS_HID_14e9 = 0x14e9, + BNXT_ULP_CLASS_HID_2559 = 0x2559, + BNXT_ULP_CLASS_HID_2b95 = 0x2b95, + BNXT_ULP_CLASS_HID_1825 = 0x1825, + BNXT_ULP_CLASS_HID_13f9 = 0x13f9, + BNXT_ULP_CLASS_HID_0e8d = 0x0e8d, + BNXT_ULP_CLASS_HID_0a41 = 0x0a41, + BNXT_ULP_CLASS_HID_38dd = 0x38dd, + BNXT_ULP_CLASS_HID_3391 = 0x3391, + BNXT_ULP_CLASS_HID_2ea5 = 0x2ea5, + BNXT_ULP_CLASS_HID_2a79 = 0x2a79, + BNXT_ULP_CLASS_HID_127d = 0x127d, + BNXT_ULP_CLASS_HID_0d31 = 0x0d31, + BNXT_ULP_CLASS_HID_08c5 = 0x08c5, + BNXT_ULP_CLASS_HID_0399 = 0x0399, + BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1, + BNXT_ULP_CLASS_HID_4a45 = 0x4a45, + BNXT_ULP_CLASS_HID_4519 = 0x4519, + BNXT_ULP_CLASS_HID_402d = 0x402d, + BNXT_ULP_CLASS_HID_1269 = 0x1269, + BNXT_ULP_CLASS_HID_0d3d = 0x0d3d, + BNXT_ULP_CLASS_HID_08f1 = 0x08f1, + BNXT_ULP_CLASS_HID_0385 = 0x0385, + BNXT_ULP_CLASS_HID_3201 = 0x3201, + BNXT_ULP_CLASS_HID_2dd5 = 0x2dd5, + BNXT_ULP_CLASS_HID_28e9 = 0x28e9, + BNXT_ULP_CLASS_HID_23bd = 0x23bd, + BNXT_ULP_CLASS_HID_0ba1 = 0x0ba1, + BNXT_ULP_CLASS_HID_0775 = 0x0775, + BNXT_ULP_CLASS_HID_0209 = 0x0209, + BNXT_ULP_CLASS_HID_5a09 = 0x5a09, + BNXT_ULP_CLASS_HID_48f5 = 0x48f5, + BNXT_ULP_CLASS_HID_4389 = 0x4389, + BNXT_ULP_CLASS_HID_3f5d = 0x3f5d, + BNXT_ULP_CLASS_HID_3a11 = 0x3a11, + BNXT_ULP_CLASS_HID_0bad = 0x0bad, + BNXT_ULP_CLASS_HID_0761 = 0x0761, + BNXT_ULP_CLASS_HID_0235 = 0x0235, + BNXT_ULP_CLASS_HID_5a35 = 0x5a35, + BNXT_ULP_CLASS_HID_2c45 = 0x2c45, + BNXT_ULP_CLASS_HID_2719 = 0x2719, + BNXT_ULP_CLASS_HID_222d = 0x222d, + BNXT_ULP_CLASS_HID_1de1 = 0x1de1, + BNXT_ULP_CLASS_HID_05e5 = 0x05e5, + BNXT_ULP_CLASS_HID_00b9 = 0x00b9, + BNXT_ULP_CLASS_HID_58b9 = 0x58b9, + BNXT_ULP_CLASS_HID_544d = 0x544d, + BNXT_ULP_CLASS_HID_4239 = 0x4239, + BNXT_ULP_CLASS_HID_3dcd = 0x3dcd, + BNXT_ULP_CLASS_HID_3881 = 0x3881, + BNXT_ULP_CLASS_HID_3455 = 0x3455, + BNXT_ULP_CLASS_HID_0591 = 0x0591, + BNXT_ULP_CLASS_HID_00a5 = 0x00a5, + BNXT_ULP_CLASS_HID_58a5 = 0x58a5, + BNXT_ULP_CLASS_HID_5479 = 0x5479, + BNXT_ULP_CLASS_HID_2589 = 0x2589, + BNXT_ULP_CLASS_HID_215d = 0x215d, + BNXT_ULP_CLASS_HID_1c11 = 0x1c11, + BNXT_ULP_CLASS_HID_1725 = 0x1725, + BNXT_ULP_CLASS_HID_5c15 = 0x5c15, + BNXT_ULP_CLASS_HID_5729 = 0x5729, + BNXT_ULP_CLASS_HID_52fd = 0x52fd, + BNXT_ULP_CLASS_HID_4db1 = 0x4db1, + BNXT_ULP_CLASS_HID_3c7d = 0x3c7d, + BNXT_ULP_CLASS_HID_3731 = 0x3731, + BNXT_ULP_CLASS_HID_32c5 = 0x32c5, + BNXT_ULP_CLASS_HID_2d99 = 0x2d99, + BNXT_ULP_CLASS_HID_4f89 = 0x4f89, + BNXT_ULP_CLASS_HID_4b5d = 0x4b5d, + BNXT_ULP_CLASS_HID_4611 = 0x4611, + BNXT_ULP_CLASS_HID_4125 = 0x4125, + BNXT_ULP_CLASS_HID_1375 = 0x1375, + BNXT_ULP_CLASS_HID_0e09 = 0x0e09, + BNXT_ULP_CLASS_HID_09dd = 0x09dd, + BNXT_ULP_CLASS_HID_0491 = 0x0491, + BNXT_ULP_CLASS_HID_49c1 = 0x49c1, + BNXT_ULP_CLASS_HID_4495 = 0x4495, + BNXT_ULP_CLASS_HID_3fa9 = 0x3fa9, + BNXT_ULP_CLASS_HID_3b7d = 0x3b7d, + BNXT_ULP_CLASS_HID_2929 = 0x2929, + BNXT_ULP_CLASS_HID_24fd = 0x24fd, + BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1, + BNXT_ULP_CLASS_HID_1b45 = 0x1b45, + BNXT_ULP_CLASS_HID_49cd = 0x49cd, + BNXT_ULP_CLASS_HID_4481 = 0x4481, + BNXT_ULP_CLASS_HID_4055 = 0x4055, + BNXT_ULP_CLASS_HID_3b69 = 0x3b69, + BNXT_ULP_CLASS_HID_0cb9 = 0x0cb9, + BNXT_ULP_CLASS_HID_084d = 0x084d, + BNXT_ULP_CLASS_HID_0301 = 0x0301, + BNXT_ULP_CLASS_HID_5b01 = 0x5b01, + BNXT_ULP_CLASS_HID_4305 = 0x4305, + BNXT_ULP_CLASS_HID_3ed9 = 0x3ed9, + BNXT_ULP_CLASS_HID_39ed = 0x39ed, + BNXT_ULP_CLASS_HID_34a1 = 0x34a1, + BNXT_ULP_CLASS_HID_236d = 0x236d, + BNXT_ULP_CLASS_HID_1e21 = 0x1e21, + BNXT_ULP_CLASS_HID_19f5 = 0x19f5, + BNXT_ULP_CLASS_HID_1489 = 0x1489, + BNXT_ULP_CLASS_HID_2539 = 0x2539, + BNXT_ULP_CLASS_HID_2bf5 = 0x2bf5, + BNXT_ULP_CLASS_HID_b6af = 0xb6af, + BNXT_ULP_CLASS_HID_b1d3 = 0xb1d3, + BNXT_ULP_CLASS_HID_1c7d3 = 0x1c7d3, + BNXT_ULP_CLASS_HID_1ccaf = 0x1ccaf, + BNXT_ULP_CLASS_HID_da33 = 0xda33, + BNXT_ULP_CLASS_HID_d567 = 0xd567, + BNXT_ULP_CLASS_HID_18eab = 0x18eab, + BNXT_ULP_CLASS_HID_19367 = 0x19367, + BNXT_ULP_CLASS_HID_a10b = 0xa10b, + BNXT_ULP_CLASS_HID_9c3f = 0x9c3f, + BNXT_ULP_CLASS_HID_1b23f = 0x1b23f, + BNXT_ULP_CLASS_HID_1b70b = 0x1b70b, + BNXT_ULP_CLASS_HID_c49f = 0xc49f, + BNXT_ULP_CLASS_HID_bfc3 = 0xbfc3, + BNXT_ULP_CLASS_HID_1d5c3 = 0x1d5c3, + BNXT_ULP_CLASS_HID_1da9f = 0x1da9f, + BNXT_ULP_CLASS_HID_b063 = 0xb063, + BNXT_ULP_CLASS_HID_ab97 = 0xab97, + BNXT_ULP_CLASS_HID_1c197 = 0x1c197, + BNXT_ULP_CLASS_HID_1c663 = 0x1c663, + BNXT_ULP_CLASS_HID_d3f7 = 0xd3f7, + BNXT_ULP_CLASS_HID_cf3b = 0xcf3b, + BNXT_ULP_CLASS_HID_1886f = 0x1886f, + BNXT_ULP_CLASS_HID_18d3b = 0x18d3b, + BNXT_ULP_CLASS_HID_9acf = 0x9acf, + BNXT_ULP_CLASS_HID_95f3 = 0x95f3, + BNXT_ULP_CLASS_HID_1abf3 = 0x1abf3, + BNXT_ULP_CLASS_HID_1b0cf = 0x1b0cf, + BNXT_ULP_CLASS_HID_be53 = 0xbe53, + BNXT_ULP_CLASS_HID_b987 = 0xb987, + BNXT_ULP_CLASS_HID_1cf87 = 0x1cf87, + BNXT_ULP_CLASS_HID_1d453 = 0x1d453, + BNXT_ULP_CLASS_HID_aa27 = 0xaa27, + BNXT_ULP_CLASS_HID_a56b = 0xa56b, + BNXT_ULP_CLASS_HID_1bb6b = 0x1bb6b, + BNXT_ULP_CLASS_HID_1c027 = 0x1c027, + BNXT_ULP_CLASS_HID_cdcb = 0xcdcb, + BNXT_ULP_CLASS_HID_c8ff = 0xc8ff, + BNXT_ULP_CLASS_HID_18223 = 0x18223, + BNXT_ULP_CLASS_HID_186ff = 0x186ff, + BNXT_ULP_CLASS_HID_9483 = 0x9483, + BNXT_ULP_CLASS_HID_8fb7 = 0x8fb7, + BNXT_ULP_CLASS_HID_1a5b7 = 0x1a5b7, + BNXT_ULP_CLASS_HID_1aa83 = 0x1aa83, + BNXT_ULP_CLASS_HID_b817 = 0xb817, + BNXT_ULP_CLASS_HID_b35b = 0xb35b, + BNXT_ULP_CLASS_HID_1c95b = 0x1c95b, + BNXT_ULP_CLASS_HID_1ce17 = 0x1ce17, + BNXT_ULP_CLASS_HID_a3fb = 0xa3fb, + BNXT_ULP_CLASS_HID_9f2f = 0x9f2f, + BNXT_ULP_CLASS_HID_1b52f = 0x1b52f, + BNXT_ULP_CLASS_HID_1b9fb = 0x1b9fb, + BNXT_ULP_CLASS_HID_c78f = 0xc78f, + BNXT_ULP_CLASS_HID_c2b3 = 0xc2b3, + BNXT_ULP_CLASS_HID_1d8b3 = 0x1d8b3, + BNXT_ULP_CLASS_HID_180b3 = 0x180b3, + BNXT_ULP_CLASS_HID_8e47 = 0x8e47, + BNXT_ULP_CLASS_HID_898b = 0x898b, + BNXT_ULP_CLASS_HID_19f8b = 0x19f8b, + BNXT_ULP_CLASS_HID_1a447 = 0x1a447, + BNXT_ULP_CLASS_HID_b1eb = 0xb1eb, + BNXT_ULP_CLASS_HID_ad1f = 0xad1f, + BNXT_ULP_CLASS_HID_1c31f = 0x1c31f, + BNXT_ULP_CLASS_HID_1c7eb = 0x1c7eb, + BNXT_ULP_CLASS_HID_9137 = 0x9137, + BNXT_ULP_CLASS_HID_8c7b = 0x8c7b, + BNXT_ULP_CLASS_HID_1a27b = 0x1a27b, + BNXT_ULP_CLASS_HID_1a737 = 0x1a737, + BNXT_ULP_CLASS_HID_b4db = 0xb4db, + BNXT_ULP_CLASS_HID_b00f = 0xb00f, + BNXT_ULP_CLASS_HID_1c60f = 0x1c60f, + BNXT_ULP_CLASS_HID_1cadb = 0x1cadb, + BNXT_ULP_CLASS_HID_8b0b = 0x8b0b, + BNXT_ULP_CLASS_HID_863f = 0x863f, + BNXT_ULP_CLASS_HID_19c3f = 0x19c3f, + BNXT_ULP_CLASS_HID_1a10b = 0x1a10b, + BNXT_ULP_CLASS_HID_ae9f = 0xae9f, + BNXT_ULP_CLASS_HID_a9c3 = 0xa9c3, + BNXT_ULP_CLASS_HID_1bfc3 = 0x1bfc3, + BNXT_ULP_CLASS_HID_1c49f = 0x1c49f, + BNXT_ULP_CLASS_HID_2563 = 0x2563, + BNXT_ULP_CLASS_HID_2baf = 0x2baf, + BNXT_ULP_CLASS_HID_4f33 = 0x4f33, + BNXT_ULP_CLASS_HID_160b = 0x160b, + BNXT_ULP_CLASS_HID_399f = 0x399f, + BNXT_ULP_CLASS_HID_48f7 = 0x48f7, + BNXT_ULP_CLASS_HID_0fcf = 0x0fcf, + BNXT_ULP_CLASS_HID_3353 = 0x3353, + BNXT_ULP_CLASS_HID_b68f = 0xb68f, + BNXT_ULP_CLASS_HID_b94f = 0xb94f, + BNXT_ULP_CLASS_HID_fc0f = 0xfc0f, + BNXT_ULP_CLASS_HID_fecf = 0xfecf, + BNXT_ULP_CLASS_HID_b1f3 = 0xb1f3, + BNXT_ULP_CLASS_HID_b4b3 = 0xb4b3, + BNXT_ULP_CLASS_HID_f773 = 0xf773, + BNXT_ULP_CLASS_HID_fa33 = 0xfa33, + BNXT_ULP_CLASS_HID_1c7f3 = 0x1c7f3, + BNXT_ULP_CLASS_HID_1eab3 = 0x1eab3, + BNXT_ULP_CLASS_HID_1cd73 = 0x1cd73, + BNXT_ULP_CLASS_HID_1f033 = 0x1f033, + BNXT_ULP_CLASS_HID_1cc8f = 0x1cc8f, + BNXT_ULP_CLASS_HID_1ef4f = 0x1ef4f, + BNXT_ULP_CLASS_HID_1d20f = 0x1d20f, + BNXT_ULP_CLASS_HID_1f4cf = 0x1f4cf, + BNXT_ULP_CLASS_HID_da13 = 0xda13, + BNXT_ULP_CLASS_HID_a007 = 0xa007, + BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7, + BNXT_ULP_CLASS_HID_e587 = 0xe587, + BNXT_ULP_CLASS_HID_d547 = 0xd547, + BNXT_ULP_CLASS_HID_f807 = 0xf807, + BNXT_ULP_CLASS_HID_dac7 = 0xdac7, + BNXT_ULP_CLASS_HID_e0cb = 0xe0cb, + BNXT_ULP_CLASS_HID_18e8b = 0x18e8b, + BNXT_ULP_CLASS_HID_1b14b = 0x1b14b, + BNXT_ULP_CLASS_HID_1d40b = 0x1d40b, + BNXT_ULP_CLASS_HID_1f6cb = 0x1f6cb, + BNXT_ULP_CLASS_HID_19347 = 0x19347, + BNXT_ULP_CLASS_HID_1b607 = 0x1b607, + BNXT_ULP_CLASS_HID_1d8c7 = 0x1d8c7, + BNXT_ULP_CLASS_HID_1fb87 = 0x1fb87, + BNXT_ULP_CLASS_HID_a12b = 0xa12b, + BNXT_ULP_CLASS_HID_a3eb = 0xa3eb, + BNXT_ULP_CLASS_HID_e6ab = 0xe6ab, + BNXT_ULP_CLASS_HID_e96b = 0xe96b, + BNXT_ULP_CLASS_HID_9c1f = 0x9c1f, + BNXT_ULP_CLASS_HID_bedf = 0xbedf, + BNXT_ULP_CLASS_HID_e19f = 0xe19f, + BNXT_ULP_CLASS_HID_e45f = 0xe45f, + BNXT_ULP_CLASS_HID_1b21f = 0x1b21f, + BNXT_ULP_CLASS_HID_1b4df = 0x1b4df, + BNXT_ULP_CLASS_HID_1f79f = 0x1f79f, + BNXT_ULP_CLASS_HID_1fa5f = 0x1fa5f, + BNXT_ULP_CLASS_HID_1b72b = 0x1b72b, + BNXT_ULP_CLASS_HID_1b9eb = 0x1b9eb, + BNXT_ULP_CLASS_HID_1fcab = 0x1fcab, + BNXT_ULP_CLASS_HID_1ff6b = 0x1ff6b, + BNXT_ULP_CLASS_HID_c4bf = 0xc4bf, + BNXT_ULP_CLASS_HID_e77f = 0xe77f, + BNXT_ULP_CLASS_HID_ca3f = 0xca3f, + BNXT_ULP_CLASS_HID_ecff = 0xecff, + BNXT_ULP_CLASS_HID_bfe3 = 0xbfe3, + BNXT_ULP_CLASS_HID_e2a3 = 0xe2a3, + BNXT_ULP_CLASS_HID_c563 = 0xc563, + BNXT_ULP_CLASS_HID_e823 = 0xe823, + BNXT_ULP_CLASS_HID_1d5e3 = 0x1d5e3, + BNXT_ULP_CLASS_HID_1f8a3 = 0x1f8a3, + BNXT_ULP_CLASS_HID_1db63 = 0x1db63, + BNXT_ULP_CLASS_HID_1e117 = 0x1e117, + BNXT_ULP_CLASS_HID_1dabf = 0x1dabf, + BNXT_ULP_CLASS_HID_1a0a3 = 0x1a0a3, + BNXT_ULP_CLASS_HID_1c363 = 0x1c363, + BNXT_ULP_CLASS_HID_1e623 = 0x1e623, + BNXT_ULP_CLASS_HID_b043 = 0xb043, + BNXT_ULP_CLASS_HID_b303 = 0xb303, + BNXT_ULP_CLASS_HID_f5c3 = 0xf5c3, + BNXT_ULP_CLASS_HID_f883 = 0xf883, + BNXT_ULP_CLASS_HID_abb7 = 0xabb7, + BNXT_ULP_CLASS_HID_ae77 = 0xae77, + BNXT_ULP_CLASS_HID_f137 = 0xf137, + BNXT_ULP_CLASS_HID_f3f7 = 0xf3f7, + BNXT_ULP_CLASS_HID_1c1b7 = 0x1c1b7, + BNXT_ULP_CLASS_HID_1e477 = 0x1e477, + BNXT_ULP_CLASS_HID_1c737 = 0x1c737, + BNXT_ULP_CLASS_HID_1e9f7 = 0x1e9f7, + BNXT_ULP_CLASS_HID_1c643 = 0x1c643, + BNXT_ULP_CLASS_HID_1e903 = 0x1e903, + BNXT_ULP_CLASS_HID_1cbc3 = 0x1cbc3, + BNXT_ULP_CLASS_HID_1ee83 = 0x1ee83, + BNXT_ULP_CLASS_HID_d3d7 = 0xd3d7, + BNXT_ULP_CLASS_HID_f697 = 0xf697, + BNXT_ULP_CLASS_HID_d957 = 0xd957, + BNXT_ULP_CLASS_HID_fc17 = 0xfc17, + BNXT_ULP_CLASS_HID_cf1b = 0xcf1b, + BNXT_ULP_CLASS_HID_f1db = 0xf1db, + BNXT_ULP_CLASS_HID_d49b = 0xd49b, + BNXT_ULP_CLASS_HID_f75b = 0xf75b, + BNXT_ULP_CLASS_HID_1884f = 0x1884f, + BNXT_ULP_CLASS_HID_1ab0f = 0x1ab0f, + BNXT_ULP_CLASS_HID_1cdcf = 0x1cdcf, + BNXT_ULP_CLASS_HID_1f08f = 0x1f08f, + BNXT_ULP_CLASS_HID_18d1b = 0x18d1b, + BNXT_ULP_CLASS_HID_1afdb = 0x1afdb, + BNXT_ULP_CLASS_HID_1d29b = 0x1d29b, + BNXT_ULP_CLASS_HID_1f55b = 0x1f55b, + BNXT_ULP_CLASS_HID_9aef = 0x9aef, + BNXT_ULP_CLASS_HID_bdaf = 0xbdaf, + BNXT_ULP_CLASS_HID_e06f = 0xe06f, + BNXT_ULP_CLASS_HID_e32f = 0xe32f, + BNXT_ULP_CLASS_HID_95d3 = 0x95d3, + BNXT_ULP_CLASS_HID_b893 = 0xb893, + BNXT_ULP_CLASS_HID_db53 = 0xdb53, + BNXT_ULP_CLASS_HID_fe13 = 0xfe13, + BNXT_ULP_CLASS_HID_1abd3 = 0x1abd3, + BNXT_ULP_CLASS_HID_1ae93 = 0x1ae93, + BNXT_ULP_CLASS_HID_1f153 = 0x1f153, + BNXT_ULP_CLASS_HID_1f413 = 0x1f413, + BNXT_ULP_CLASS_HID_1b0ef = 0x1b0ef, + BNXT_ULP_CLASS_HID_1b3af = 0x1b3af, + BNXT_ULP_CLASS_HID_1f66f = 0x1f66f, + BNXT_ULP_CLASS_HID_1f92f = 0x1f92f, + BNXT_ULP_CLASS_HID_be73 = 0xbe73, + BNXT_ULP_CLASS_HID_e133 = 0xe133, + BNXT_ULP_CLASS_HID_c3f3 = 0xc3f3, + BNXT_ULP_CLASS_HID_e6b3 = 0xe6b3, + BNXT_ULP_CLASS_HID_b9a7 = 0xb9a7, + BNXT_ULP_CLASS_HID_bc67 = 0xbc67, + BNXT_ULP_CLASS_HID_ff27 = 0xff27, + BNXT_ULP_CLASS_HID_e1e7 = 0xe1e7, + BNXT_ULP_CLASS_HID_1cfa7 = 0x1cfa7, + BNXT_ULP_CLASS_HID_1f267 = 0x1f267, + BNXT_ULP_CLASS_HID_1d527 = 0x1d527, + BNXT_ULP_CLASS_HID_1f7e7 = 0x1f7e7, + BNXT_ULP_CLASS_HID_1d473 = 0x1d473, + BNXT_ULP_CLASS_HID_1f733 = 0x1f733, + BNXT_ULP_CLASS_HID_1d9f3 = 0x1d9f3, + BNXT_ULP_CLASS_HID_1fcb3 = 0x1fcb3, + BNXT_ULP_CLASS_HID_aa07 = 0xaa07, + BNXT_ULP_CLASS_HID_acc7 = 0xacc7, + BNXT_ULP_CLASS_HID_ef87 = 0xef87, + BNXT_ULP_CLASS_HID_f247 = 0xf247, + BNXT_ULP_CLASS_HID_a54b = 0xa54b, + BNXT_ULP_CLASS_HID_a80b = 0xa80b, + BNXT_ULP_CLASS_HID_eacb = 0xeacb, + BNXT_ULP_CLASS_HID_ed8b = 0xed8b, + BNXT_ULP_CLASS_HID_1bb4b = 0x1bb4b, + BNXT_ULP_CLASS_HID_1be0b = 0x1be0b, + BNXT_ULP_CLASS_HID_1c0cb = 0x1c0cb, + BNXT_ULP_CLASS_HID_1e38b = 0x1e38b, + BNXT_ULP_CLASS_HID_1c007 = 0x1c007, + BNXT_ULP_CLASS_HID_1e2c7 = 0x1e2c7, + BNXT_ULP_CLASS_HID_1c587 = 0x1c587, + BNXT_ULP_CLASS_HID_1e847 = 0x1e847, + BNXT_ULP_CLASS_HID_cdeb = 0xcdeb, + BNXT_ULP_CLASS_HID_f0ab = 0xf0ab, + BNXT_ULP_CLASS_HID_d36b = 0xd36b, + BNXT_ULP_CLASS_HID_f62b = 0xf62b, + BNXT_ULP_CLASS_HID_c8df = 0xc8df, + BNXT_ULP_CLASS_HID_eb9f = 0xeb9f, + BNXT_ULP_CLASS_HID_ce5f = 0xce5f, + BNXT_ULP_CLASS_HID_f11f = 0xf11f, + BNXT_ULP_CLASS_HID_18203 = 0x18203, + BNXT_ULP_CLASS_HID_1a4c3 = 0x1a4c3, + BNXT_ULP_CLASS_HID_1c783 = 0x1c783, + BNXT_ULP_CLASS_HID_1ea43 = 0x1ea43, + BNXT_ULP_CLASS_HID_186df = 0x186df, + BNXT_ULP_CLASS_HID_1a99f = 0x1a99f, + BNXT_ULP_CLASS_HID_1cc5f = 0x1cc5f, + BNXT_ULP_CLASS_HID_1ef1f = 0x1ef1f, + BNXT_ULP_CLASS_HID_94a3 = 0x94a3, + BNXT_ULP_CLASS_HID_b763 = 0xb763, + BNXT_ULP_CLASS_HID_da23 = 0xda23, + BNXT_ULP_CLASS_HID_fce3 = 0xfce3, + BNXT_ULP_CLASS_HID_8f97 = 0x8f97, + BNXT_ULP_CLASS_HID_b257 = 0xb257, + BNXT_ULP_CLASS_HID_d517 = 0xd517, + BNXT_ULP_CLASS_HID_f7d7 = 0xf7d7, + BNXT_ULP_CLASS_HID_1a597 = 0x1a597, + BNXT_ULP_CLASS_HID_1a857 = 0x1a857, + BNXT_ULP_CLASS_HID_1eb17 = 0x1eb17, + BNXT_ULP_CLASS_HID_1edd7 = 0x1edd7, + BNXT_ULP_CLASS_HID_1aaa3 = 0x1aaa3, + BNXT_ULP_CLASS_HID_1ad63 = 0x1ad63, + BNXT_ULP_CLASS_HID_1f023 = 0x1f023, + BNXT_ULP_CLASS_HID_1f2e3 = 0x1f2e3, + BNXT_ULP_CLASS_HID_b837 = 0xb837, + BNXT_ULP_CLASS_HID_baf7 = 0xbaf7, + BNXT_ULP_CLASS_HID_fdb7 = 0xfdb7, + BNXT_ULP_CLASS_HID_e077 = 0xe077, + BNXT_ULP_CLASS_HID_b37b = 0xb37b, + BNXT_ULP_CLASS_HID_b63b = 0xb63b, + BNXT_ULP_CLASS_HID_f8fb = 0xf8fb, + BNXT_ULP_CLASS_HID_fbbb = 0xfbbb, + BNXT_ULP_CLASS_HID_1c97b = 0x1c97b, + BNXT_ULP_CLASS_HID_1ec3b = 0x1ec3b, + BNXT_ULP_CLASS_HID_1cefb = 0x1cefb, + BNXT_ULP_CLASS_HID_1f1bb = 0x1f1bb, + BNXT_ULP_CLASS_HID_1ce37 = 0x1ce37, + BNXT_ULP_CLASS_HID_1f0f7 = 0x1f0f7, + BNXT_ULP_CLASS_HID_1d3b7 = 0x1d3b7, + BNXT_ULP_CLASS_HID_1f677 = 0x1f677, + BNXT_ULP_CLASS_HID_a3db = 0xa3db, + BNXT_ULP_CLASS_HID_a69b = 0xa69b, + BNXT_ULP_CLASS_HID_e95b = 0xe95b, + BNXT_ULP_CLASS_HID_ec1b = 0xec1b, + BNXT_ULP_CLASS_HID_9f0f = 0x9f0f, + BNXT_ULP_CLASS_HID_a1cf = 0xa1cf, + BNXT_ULP_CLASS_HID_e48f = 0xe48f, + BNXT_ULP_CLASS_HID_e74f = 0xe74f, + BNXT_ULP_CLASS_HID_1b50f = 0x1b50f, + BNXT_ULP_CLASS_HID_1b7cf = 0x1b7cf, + BNXT_ULP_CLASS_HID_1fa8f = 0x1fa8f, + BNXT_ULP_CLASS_HID_1fd4f = 0x1fd4f, + BNXT_ULP_CLASS_HID_1b9db = 0x1b9db, + BNXT_ULP_CLASS_HID_1bc9b = 0x1bc9b, + BNXT_ULP_CLASS_HID_1ff5b = 0x1ff5b, + BNXT_ULP_CLASS_HID_1e21b = 0x1e21b, + BNXT_ULP_CLASS_HID_c7af = 0xc7af, + BNXT_ULP_CLASS_HID_ea6f = 0xea6f, + BNXT_ULP_CLASS_HID_cd2f = 0xcd2f, + BNXT_ULP_CLASS_HID_efef = 0xefef, + BNXT_ULP_CLASS_HID_c293 = 0xc293, + BNXT_ULP_CLASS_HID_e553 = 0xe553, + BNXT_ULP_CLASS_HID_c813 = 0xc813, + BNXT_ULP_CLASS_HID_ead3 = 0xead3, + BNXT_ULP_CLASS_HID_1d893 = 0x1d893, + BNXT_ULP_CLASS_HID_1fb53 = 0x1fb53, + BNXT_ULP_CLASS_HID_1c147 = 0x1c147, + BNXT_ULP_CLASS_HID_1e407 = 0x1e407, + BNXT_ULP_CLASS_HID_18093 = 0x18093, + BNXT_ULP_CLASS_HID_1a353 = 0x1a353, + BNXT_ULP_CLASS_HID_1c613 = 0x1c613, + BNXT_ULP_CLASS_HID_1e8d3 = 0x1e8d3, + BNXT_ULP_CLASS_HID_8e67 = 0x8e67, + BNXT_ULP_CLASS_HID_b127 = 0xb127, + BNXT_ULP_CLASS_HID_d3e7 = 0xd3e7, + BNXT_ULP_CLASS_HID_f6a7 = 0xf6a7, + BNXT_ULP_CLASS_HID_89ab = 0x89ab, + BNXT_ULP_CLASS_HID_ac6b = 0xac6b, + BNXT_ULP_CLASS_HID_cf2b = 0xcf2b, + BNXT_ULP_CLASS_HID_f1eb = 0xf1eb, + BNXT_ULP_CLASS_HID_19fab = 0x19fab, + BNXT_ULP_CLASS_HID_1a26b = 0x1a26b, + BNXT_ULP_CLASS_HID_1e52b = 0x1e52b, + BNXT_ULP_CLASS_HID_1e7eb = 0x1e7eb, + BNXT_ULP_CLASS_HID_1a467 = 0x1a467, + BNXT_ULP_CLASS_HID_1a727 = 0x1a727, + BNXT_ULP_CLASS_HID_1e9e7 = 0x1e9e7, + BNXT_ULP_CLASS_HID_1eca7 = 0x1eca7, + BNXT_ULP_CLASS_HID_b1cb = 0xb1cb, + BNXT_ULP_CLASS_HID_b48b = 0xb48b, + BNXT_ULP_CLASS_HID_f74b = 0xf74b, + BNXT_ULP_CLASS_HID_fa0b = 0xfa0b, + BNXT_ULP_CLASS_HID_ad3f = 0xad3f, + BNXT_ULP_CLASS_HID_afff = 0xafff, + BNXT_ULP_CLASS_HID_f2bf = 0xf2bf, + BNXT_ULP_CLASS_HID_f57f = 0xf57f, + BNXT_ULP_CLASS_HID_1c33f = 0x1c33f, + BNXT_ULP_CLASS_HID_1e5ff = 0x1e5ff, + BNXT_ULP_CLASS_HID_1c8bf = 0x1c8bf, + BNXT_ULP_CLASS_HID_1eb7f = 0x1eb7f, + BNXT_ULP_CLASS_HID_1c7cb = 0x1c7cb, + BNXT_ULP_CLASS_HID_1ea8b = 0x1ea8b, + BNXT_ULP_CLASS_HID_1cd4b = 0x1cd4b, + BNXT_ULP_CLASS_HID_1f00b = 0x1f00b, + BNXT_ULP_CLASS_HID_9117 = 0x9117, + BNXT_ULP_CLASS_HID_b3d7 = 0xb3d7, + BNXT_ULP_CLASS_HID_d697 = 0xd697, + BNXT_ULP_CLASS_HID_f957 = 0xf957, + BNXT_ULP_CLASS_HID_8c5b = 0x8c5b, + BNXT_ULP_CLASS_HID_af1b = 0xaf1b, + BNXT_ULP_CLASS_HID_d1db = 0xd1db, + BNXT_ULP_CLASS_HID_f49b = 0xf49b, + BNXT_ULP_CLASS_HID_1a25b = 0x1a25b, + BNXT_ULP_CLASS_HID_1a51b = 0x1a51b, + BNXT_ULP_CLASS_HID_1e7db = 0x1e7db, + BNXT_ULP_CLASS_HID_1ea9b = 0x1ea9b, + BNXT_ULP_CLASS_HID_1a717 = 0x1a717, + BNXT_ULP_CLASS_HID_1a9d7 = 0x1a9d7, + BNXT_ULP_CLASS_HID_1ec97 = 0x1ec97, + BNXT_ULP_CLASS_HID_1ef57 = 0x1ef57, + BNXT_ULP_CLASS_HID_b4fb = 0xb4fb, + BNXT_ULP_CLASS_HID_b7bb = 0xb7bb, + BNXT_ULP_CLASS_HID_fa7b = 0xfa7b, + BNXT_ULP_CLASS_HID_fd3b = 0xfd3b, + BNXT_ULP_CLASS_HID_b02f = 0xb02f, + BNXT_ULP_CLASS_HID_b2ef = 0xb2ef, + BNXT_ULP_CLASS_HID_f5af = 0xf5af, + BNXT_ULP_CLASS_HID_f86f = 0xf86f, + BNXT_ULP_CLASS_HID_1c62f = 0x1c62f, + BNXT_ULP_CLASS_HID_1e8ef = 0x1e8ef, + BNXT_ULP_CLASS_HID_1cbaf = 0x1cbaf, + BNXT_ULP_CLASS_HID_1ee6f = 0x1ee6f, + BNXT_ULP_CLASS_HID_1cafb = 0x1cafb, + BNXT_ULP_CLASS_HID_1edbb = 0x1edbb, + BNXT_ULP_CLASS_HID_1d07b = 0x1d07b, + BNXT_ULP_CLASS_HID_1f33b = 0x1f33b, + BNXT_ULP_CLASS_HID_8b2b = 0x8b2b, + BNXT_ULP_CLASS_HID_adeb = 0xadeb, + BNXT_ULP_CLASS_HID_d0ab = 0xd0ab, + BNXT_ULP_CLASS_HID_f36b = 0xf36b, + BNXT_ULP_CLASS_HID_861f = 0x861f, + BNXT_ULP_CLASS_HID_a8df = 0xa8df, + BNXT_ULP_CLASS_HID_cb9f = 0xcb9f, + BNXT_ULP_CLASS_HID_ee5f = 0xee5f, + BNXT_ULP_CLASS_HID_19c1f = 0x19c1f, + BNXT_ULP_CLASS_HID_1bedf = 0x1bedf, + BNXT_ULP_CLASS_HID_1e19f = 0x1e19f, + BNXT_ULP_CLASS_HID_1e45f = 0x1e45f, + BNXT_ULP_CLASS_HID_1a12b = 0x1a12b, + BNXT_ULP_CLASS_HID_1a3eb = 0x1a3eb, + BNXT_ULP_CLASS_HID_1e6ab = 0x1e6ab, + BNXT_ULP_CLASS_HID_1e96b = 0x1e96b, + BNXT_ULP_CLASS_HID_aebf = 0xaebf, + BNXT_ULP_CLASS_HID_b17f = 0xb17f, + BNXT_ULP_CLASS_HID_f43f = 0xf43f, + BNXT_ULP_CLASS_HID_f6ff = 0xf6ff, + BNXT_ULP_CLASS_HID_a9e3 = 0xa9e3, + BNXT_ULP_CLASS_HID_aca3 = 0xaca3, + BNXT_ULP_CLASS_HID_ef63 = 0xef63, + BNXT_ULP_CLASS_HID_f223 = 0xf223, + BNXT_ULP_CLASS_HID_1bfe3 = 0x1bfe3, + BNXT_ULP_CLASS_HID_1e2a3 = 0x1e2a3, + BNXT_ULP_CLASS_HID_1c563 = 0x1c563, + BNXT_ULP_CLASS_HID_1e823 = 0x1e823, + BNXT_ULP_CLASS_HID_1c4bf = 0x1c4bf, + BNXT_ULP_CLASS_HID_1e77f = 0x1e77f, + BNXT_ULP_CLASS_HID_1ca3f = 0x1ca3f, + BNXT_ULP_CLASS_HID_1ecff = 0x1ecff, + BNXT_ULP_CLASS_HID_2543 = 0x2543, + BNXT_ULP_CLASS_HID_2b8f = 0x2b8f, + BNXT_ULP_CLASS_HID_4f13 = 0x4f13, + BNXT_ULP_CLASS_HID_162b = 0x162b, + BNXT_ULP_CLASS_HID_39bf = 0x39bf, + BNXT_ULP_CLASS_HID_48d7 = 0x48d7, + BNXT_ULP_CLASS_HID_0fef = 0x0fef, + BNXT_ULP_CLASS_HID_3373 = 0x3373, + BNXT_ULP_CLASS_HID_b6ef = 0xb6ef, + BNXT_ULP_CLASS_HID_b92f = 0xb92f, + BNXT_ULP_CLASS_HID_fc6f = 0xfc6f, + BNXT_ULP_CLASS_HID_feaf = 0xfeaf, + BNXT_ULP_CLASS_HID_b193 = 0xb193, + BNXT_ULP_CLASS_HID_b4d3 = 0xb4d3, + BNXT_ULP_CLASS_HID_f713 = 0xf713, + BNXT_ULP_CLASS_HID_fa53 = 0xfa53, + BNXT_ULP_CLASS_HID_1c793 = 0x1c793, + BNXT_ULP_CLASS_HID_1ead3 = 0x1ead3, + BNXT_ULP_CLASS_HID_1cd13 = 0x1cd13, + BNXT_ULP_CLASS_HID_1f053 = 0x1f053, + BNXT_ULP_CLASS_HID_1ccef = 0x1ccef, + BNXT_ULP_CLASS_HID_1ef2f = 0x1ef2f, + BNXT_ULP_CLASS_HID_1d26f = 0x1d26f, + BNXT_ULP_CLASS_HID_1f4af = 0x1f4af, + BNXT_ULP_CLASS_HID_da73 = 0xda73, + BNXT_ULP_CLASS_HID_a067 = 0xa067, + BNXT_ULP_CLASS_HID_c2a7 = 0xc2a7, + BNXT_ULP_CLASS_HID_e5e7 = 0xe5e7, + BNXT_ULP_CLASS_HID_d527 = 0xd527, + BNXT_ULP_CLASS_HID_f867 = 0xf867, + BNXT_ULP_CLASS_HID_daa7 = 0xdaa7, + BNXT_ULP_CLASS_HID_e0ab = 0xe0ab, + BNXT_ULP_CLASS_HID_18eeb = 0x18eeb, + BNXT_ULP_CLASS_HID_1b12b = 0x1b12b, + BNXT_ULP_CLASS_HID_1d46b = 0x1d46b, + BNXT_ULP_CLASS_HID_1f6ab = 0x1f6ab, + BNXT_ULP_CLASS_HID_19327 = 0x19327, + BNXT_ULP_CLASS_HID_1b667 = 0x1b667, + BNXT_ULP_CLASS_HID_1d8a7 = 0x1d8a7, + BNXT_ULP_CLASS_HID_1fbe7 = 0x1fbe7, + BNXT_ULP_CLASS_HID_a14b = 0xa14b, + BNXT_ULP_CLASS_HID_a38b = 0xa38b, + BNXT_ULP_CLASS_HID_e6cb = 0xe6cb, + BNXT_ULP_CLASS_HID_e90b = 0xe90b, + BNXT_ULP_CLASS_HID_9c7f = 0x9c7f, + BNXT_ULP_CLASS_HID_bebf = 0xbebf, + BNXT_ULP_CLASS_HID_e1ff = 0xe1ff, + BNXT_ULP_CLASS_HID_e43f = 0xe43f, + BNXT_ULP_CLASS_HID_1b27f = 0x1b27f, + BNXT_ULP_CLASS_HID_1b4bf = 0x1b4bf, + BNXT_ULP_CLASS_HID_1f7ff = 0x1f7ff, + BNXT_ULP_CLASS_HID_1fa3f = 0x1fa3f, + BNXT_ULP_CLASS_HID_1b74b = 0x1b74b, + BNXT_ULP_CLASS_HID_1b98b = 0x1b98b, + BNXT_ULP_CLASS_HID_1fccb = 0x1fccb, + BNXT_ULP_CLASS_HID_1ff0b = 0x1ff0b, + BNXT_ULP_CLASS_HID_c4df = 0xc4df, + BNXT_ULP_CLASS_HID_e71f = 0xe71f, + BNXT_ULP_CLASS_HID_ca5f = 0xca5f, + BNXT_ULP_CLASS_HID_ec9f = 0xec9f, + BNXT_ULP_CLASS_HID_bf83 = 0xbf83, + BNXT_ULP_CLASS_HID_e2c3 = 0xe2c3, + BNXT_ULP_CLASS_HID_c503 = 0xc503, + BNXT_ULP_CLASS_HID_e843 = 0xe843, + BNXT_ULP_CLASS_HID_1d583 = 0x1d583, + BNXT_ULP_CLASS_HID_1f8c3 = 0x1f8c3, + BNXT_ULP_CLASS_HID_1db03 = 0x1db03, + BNXT_ULP_CLASS_HID_1e177 = 0x1e177, + BNXT_ULP_CLASS_HID_1dadf = 0x1dadf, + BNXT_ULP_CLASS_HID_1a0c3 = 0x1a0c3, + BNXT_ULP_CLASS_HID_1c303 = 0x1c303, + BNXT_ULP_CLASS_HID_1e643 = 0x1e643, + BNXT_ULP_CLASS_HID_b023 = 0xb023, + BNXT_ULP_CLASS_HID_b363 = 0xb363, + BNXT_ULP_CLASS_HID_f5a3 = 0xf5a3, + BNXT_ULP_CLASS_HID_f8e3 = 0xf8e3, + BNXT_ULP_CLASS_HID_abd7 = 0xabd7, + BNXT_ULP_CLASS_HID_ae17 = 0xae17, + BNXT_ULP_CLASS_HID_f157 = 0xf157, + BNXT_ULP_CLASS_HID_f397 = 0xf397, + BNXT_ULP_CLASS_HID_1c1d7 = 0x1c1d7, + BNXT_ULP_CLASS_HID_1e417 = 0x1e417, + BNXT_ULP_CLASS_HID_1c757 = 0x1c757, + BNXT_ULP_CLASS_HID_1e997 = 0x1e997, + BNXT_ULP_CLASS_HID_1c623 = 0x1c623, + BNXT_ULP_CLASS_HID_1e963 = 0x1e963, + BNXT_ULP_CLASS_HID_1cba3 = 0x1cba3, + BNXT_ULP_CLASS_HID_1eee3 = 0x1eee3, + BNXT_ULP_CLASS_HID_d3b7 = 0xd3b7, + BNXT_ULP_CLASS_HID_f6f7 = 0xf6f7, + BNXT_ULP_CLASS_HID_d937 = 0xd937, + BNXT_ULP_CLASS_HID_fc77 = 0xfc77, + BNXT_ULP_CLASS_HID_cf7b = 0xcf7b, + BNXT_ULP_CLASS_HID_f1bb = 0xf1bb, + BNXT_ULP_CLASS_HID_d4fb = 0xd4fb, + BNXT_ULP_CLASS_HID_f73b = 0xf73b, + BNXT_ULP_CLASS_HID_1882f = 0x1882f, + BNXT_ULP_CLASS_HID_1ab6f = 0x1ab6f, + BNXT_ULP_CLASS_HID_1cdaf = 0x1cdaf, + BNXT_ULP_CLASS_HID_1f0ef = 0x1f0ef, + BNXT_ULP_CLASS_HID_18d7b = 0x18d7b, + BNXT_ULP_CLASS_HID_1afbb = 0x1afbb, + BNXT_ULP_CLASS_HID_1d2fb = 0x1d2fb, + BNXT_ULP_CLASS_HID_1f53b = 0x1f53b, + BNXT_ULP_CLASS_HID_9a8f = 0x9a8f, + BNXT_ULP_CLASS_HID_bdcf = 0xbdcf, + BNXT_ULP_CLASS_HID_e00f = 0xe00f, + BNXT_ULP_CLASS_HID_e34f = 0xe34f, + BNXT_ULP_CLASS_HID_95b3 = 0x95b3, + BNXT_ULP_CLASS_HID_b8f3 = 0xb8f3, + BNXT_ULP_CLASS_HID_db33 = 0xdb33, + BNXT_ULP_CLASS_HID_fe73 = 0xfe73, + BNXT_ULP_CLASS_HID_1abb3 = 0x1abb3, + BNXT_ULP_CLASS_HID_1aef3 = 0x1aef3, + BNXT_ULP_CLASS_HID_1f133 = 0x1f133, + BNXT_ULP_CLASS_HID_1f473 = 0x1f473, + BNXT_ULP_CLASS_HID_1b08f = 0x1b08f, + BNXT_ULP_CLASS_HID_1b3cf = 0x1b3cf, + BNXT_ULP_CLASS_HID_1f60f = 0x1f60f, + BNXT_ULP_CLASS_HID_1f94f = 0x1f94f, + BNXT_ULP_CLASS_HID_be13 = 0xbe13, + BNXT_ULP_CLASS_HID_e153 = 0xe153, + BNXT_ULP_CLASS_HID_c393 = 0xc393, + BNXT_ULP_CLASS_HID_e6d3 = 0xe6d3, + BNXT_ULP_CLASS_HID_b9c7 = 0xb9c7, + BNXT_ULP_CLASS_HID_bc07 = 0xbc07, + BNXT_ULP_CLASS_HID_ff47 = 0xff47, + BNXT_ULP_CLASS_HID_e187 = 0xe187, + BNXT_ULP_CLASS_HID_1cfc7 = 0x1cfc7, + BNXT_ULP_CLASS_HID_1f207 = 0x1f207, + BNXT_ULP_CLASS_HID_1d547 = 0x1d547, + BNXT_ULP_CLASS_HID_1f787 = 0x1f787, + BNXT_ULP_CLASS_HID_1d413 = 0x1d413, + BNXT_ULP_CLASS_HID_1f753 = 0x1f753, + BNXT_ULP_CLASS_HID_1d993 = 0x1d993, + BNXT_ULP_CLASS_HID_1fcd3 = 0x1fcd3, + BNXT_ULP_CLASS_HID_aa67 = 0xaa67, + BNXT_ULP_CLASS_HID_aca7 = 0xaca7, + BNXT_ULP_CLASS_HID_efe7 = 0xefe7, + BNXT_ULP_CLASS_HID_f227 = 0xf227, + BNXT_ULP_CLASS_HID_a52b = 0xa52b, + BNXT_ULP_CLASS_HID_a86b = 0xa86b, + BNXT_ULP_CLASS_HID_eaab = 0xeaab, + BNXT_ULP_CLASS_HID_edeb = 0xedeb, + BNXT_ULP_CLASS_HID_1bb2b = 0x1bb2b, + BNXT_ULP_CLASS_HID_1be6b = 0x1be6b, + BNXT_ULP_CLASS_HID_1c0ab = 0x1c0ab, + BNXT_ULP_CLASS_HID_1e3eb = 0x1e3eb, + BNXT_ULP_CLASS_HID_1c067 = 0x1c067, + BNXT_ULP_CLASS_HID_1e2a7 = 0x1e2a7, + BNXT_ULP_CLASS_HID_1c5e7 = 0x1c5e7, + BNXT_ULP_CLASS_HID_1e827 = 0x1e827, + BNXT_ULP_CLASS_HID_cd8b = 0xcd8b, + BNXT_ULP_CLASS_HID_f0cb = 0xf0cb, + BNXT_ULP_CLASS_HID_d30b = 0xd30b, + BNXT_ULP_CLASS_HID_f64b = 0xf64b, + BNXT_ULP_CLASS_HID_c8bf = 0xc8bf, + BNXT_ULP_CLASS_HID_ebff = 0xebff, + BNXT_ULP_CLASS_HID_ce3f = 0xce3f, + BNXT_ULP_CLASS_HID_f17f = 0xf17f, + BNXT_ULP_CLASS_HID_18263 = 0x18263, + BNXT_ULP_CLASS_HID_1a4a3 = 0x1a4a3, + BNXT_ULP_CLASS_HID_1c7e3 = 0x1c7e3, + BNXT_ULP_CLASS_HID_1ea23 = 0x1ea23, + BNXT_ULP_CLASS_HID_186bf = 0x186bf, + BNXT_ULP_CLASS_HID_1a9ff = 0x1a9ff, + BNXT_ULP_CLASS_HID_1cc3f = 0x1cc3f, + BNXT_ULP_CLASS_HID_1ef7f = 0x1ef7f, + BNXT_ULP_CLASS_HID_94c3 = 0x94c3, + BNXT_ULP_CLASS_HID_b703 = 0xb703, + BNXT_ULP_CLASS_HID_da43 = 0xda43, + BNXT_ULP_CLASS_HID_fc83 = 0xfc83, + BNXT_ULP_CLASS_HID_8ff7 = 0x8ff7, + BNXT_ULP_CLASS_HID_b237 = 0xb237, + BNXT_ULP_CLASS_HID_d577 = 0xd577, + BNXT_ULP_CLASS_HID_f7b7 = 0xf7b7, + BNXT_ULP_CLASS_HID_1a5f7 = 0x1a5f7, + BNXT_ULP_CLASS_HID_1a837 = 0x1a837, + BNXT_ULP_CLASS_HID_1eb77 = 0x1eb77, + BNXT_ULP_CLASS_HID_1edb7 = 0x1edb7, + BNXT_ULP_CLASS_HID_1aac3 = 0x1aac3, + BNXT_ULP_CLASS_HID_1ad03 = 0x1ad03, + BNXT_ULP_CLASS_HID_1f043 = 0x1f043, + BNXT_ULP_CLASS_HID_1f283 = 0x1f283, + BNXT_ULP_CLASS_HID_b857 = 0xb857, + BNXT_ULP_CLASS_HID_ba97 = 0xba97, + BNXT_ULP_CLASS_HID_fdd7 = 0xfdd7, + BNXT_ULP_CLASS_HID_e017 = 0xe017, + BNXT_ULP_CLASS_HID_b31b = 0xb31b, + BNXT_ULP_CLASS_HID_b65b = 0xb65b, + BNXT_ULP_CLASS_HID_f89b = 0xf89b, + BNXT_ULP_CLASS_HID_fbdb = 0xfbdb, + BNXT_ULP_CLASS_HID_1c91b = 0x1c91b, + BNXT_ULP_CLASS_HID_1ec5b = 0x1ec5b, + BNXT_ULP_CLASS_HID_1ce9b = 0x1ce9b, + BNXT_ULP_CLASS_HID_1f1db = 0x1f1db, + BNXT_ULP_CLASS_HID_1ce57 = 0x1ce57, + BNXT_ULP_CLASS_HID_1f097 = 0x1f097, + BNXT_ULP_CLASS_HID_1d3d7 = 0x1d3d7, + BNXT_ULP_CLASS_HID_1f617 = 0x1f617, + BNXT_ULP_CLASS_HID_a3bb = 0xa3bb, + BNXT_ULP_CLASS_HID_a6fb = 0xa6fb, + BNXT_ULP_CLASS_HID_e93b = 0xe93b, + BNXT_ULP_CLASS_HID_ec7b = 0xec7b, + BNXT_ULP_CLASS_HID_9f6f = 0x9f6f, + BNXT_ULP_CLASS_HID_a1af = 0xa1af, + BNXT_ULP_CLASS_HID_e4ef = 0xe4ef, + BNXT_ULP_CLASS_HID_e72f = 0xe72f, + BNXT_ULP_CLASS_HID_1b56f = 0x1b56f, + BNXT_ULP_CLASS_HID_1b7af = 0x1b7af, + BNXT_ULP_CLASS_HID_1faef = 0x1faef, + BNXT_ULP_CLASS_HID_1fd2f = 0x1fd2f, + BNXT_ULP_CLASS_HID_1b9bb = 0x1b9bb, + BNXT_ULP_CLASS_HID_1bcfb = 0x1bcfb, + BNXT_ULP_CLASS_HID_1ff3b = 0x1ff3b, + BNXT_ULP_CLASS_HID_1e27b = 0x1e27b, + BNXT_ULP_CLASS_HID_c7cf = 0xc7cf, + BNXT_ULP_CLASS_HID_ea0f = 0xea0f, + BNXT_ULP_CLASS_HID_cd4f = 0xcd4f, + BNXT_ULP_CLASS_HID_ef8f = 0xef8f, + BNXT_ULP_CLASS_HID_c2f3 = 0xc2f3, + BNXT_ULP_CLASS_HID_e533 = 0xe533, + BNXT_ULP_CLASS_HID_c873 = 0xc873, + BNXT_ULP_CLASS_HID_eab3 = 0xeab3, + BNXT_ULP_CLASS_HID_1d8f3 = 0x1d8f3, + BNXT_ULP_CLASS_HID_1fb33 = 0x1fb33, + BNXT_ULP_CLASS_HID_1c127 = 0x1c127, + BNXT_ULP_CLASS_HID_1e467 = 0x1e467, + BNXT_ULP_CLASS_HID_180f3 = 0x180f3, + BNXT_ULP_CLASS_HID_1a333 = 0x1a333, + BNXT_ULP_CLASS_HID_1c673 = 0x1c673, + BNXT_ULP_CLASS_HID_1e8b3 = 0x1e8b3, + BNXT_ULP_CLASS_HID_8e07 = 0x8e07, + BNXT_ULP_CLASS_HID_b147 = 0xb147, + BNXT_ULP_CLASS_HID_d387 = 0xd387, + BNXT_ULP_CLASS_HID_f6c7 = 0xf6c7, + BNXT_ULP_CLASS_HID_89cb = 0x89cb, + BNXT_ULP_CLASS_HID_ac0b = 0xac0b, + BNXT_ULP_CLASS_HID_cf4b = 0xcf4b, + BNXT_ULP_CLASS_HID_f18b = 0xf18b, + BNXT_ULP_CLASS_HID_19fcb = 0x19fcb, + BNXT_ULP_CLASS_HID_1a20b = 0x1a20b, + BNXT_ULP_CLASS_HID_1e54b = 0x1e54b, + BNXT_ULP_CLASS_HID_1e78b = 0x1e78b, + BNXT_ULP_CLASS_HID_1a407 = 0x1a407, + BNXT_ULP_CLASS_HID_1a747 = 0x1a747, + BNXT_ULP_CLASS_HID_1e987 = 0x1e987, + BNXT_ULP_CLASS_HID_1ecc7 = 0x1ecc7, + BNXT_ULP_CLASS_HID_b1ab = 0xb1ab, + BNXT_ULP_CLASS_HID_b4eb = 0xb4eb, + BNXT_ULP_CLASS_HID_f72b = 0xf72b, + BNXT_ULP_CLASS_HID_fa6b = 0xfa6b, + BNXT_ULP_CLASS_HID_ad5f = 0xad5f, + BNXT_ULP_CLASS_HID_af9f = 0xaf9f, + BNXT_ULP_CLASS_HID_f2df = 0xf2df, + BNXT_ULP_CLASS_HID_f51f = 0xf51f, + BNXT_ULP_CLASS_HID_1c35f = 0x1c35f, + BNXT_ULP_CLASS_HID_1e59f = 0x1e59f, + BNXT_ULP_CLASS_HID_1c8df = 0x1c8df, + BNXT_ULP_CLASS_HID_1eb1f = 0x1eb1f, + BNXT_ULP_CLASS_HID_1c7ab = 0x1c7ab, + BNXT_ULP_CLASS_HID_1eaeb = 0x1eaeb, + BNXT_ULP_CLASS_HID_1cd2b = 0x1cd2b, + BNXT_ULP_CLASS_HID_1f06b = 0x1f06b, + BNXT_ULP_CLASS_HID_9177 = 0x9177, + BNXT_ULP_CLASS_HID_b3b7 = 0xb3b7, + BNXT_ULP_CLASS_HID_d6f7 = 0xd6f7, + BNXT_ULP_CLASS_HID_f937 = 0xf937, + BNXT_ULP_CLASS_HID_8c3b = 0x8c3b, + BNXT_ULP_CLASS_HID_af7b = 0xaf7b, + BNXT_ULP_CLASS_HID_d1bb = 0xd1bb, + BNXT_ULP_CLASS_HID_f4fb = 0xf4fb, + BNXT_ULP_CLASS_HID_1a23b = 0x1a23b, + BNXT_ULP_CLASS_HID_1a57b = 0x1a57b, + BNXT_ULP_CLASS_HID_1e7bb = 0x1e7bb, + BNXT_ULP_CLASS_HID_1eafb = 0x1eafb, + BNXT_ULP_CLASS_HID_1a777 = 0x1a777, + BNXT_ULP_CLASS_HID_1a9b7 = 0x1a9b7, + BNXT_ULP_CLASS_HID_1ecf7 = 0x1ecf7, + BNXT_ULP_CLASS_HID_1ef37 = 0x1ef37, + BNXT_ULP_CLASS_HID_b49b = 0xb49b, + BNXT_ULP_CLASS_HID_b7db = 0xb7db, + BNXT_ULP_CLASS_HID_fa1b = 0xfa1b, + BNXT_ULP_CLASS_HID_fd5b = 0xfd5b, + BNXT_ULP_CLASS_HID_b04f = 0xb04f, + BNXT_ULP_CLASS_HID_b28f = 0xb28f, + BNXT_ULP_CLASS_HID_f5cf = 0xf5cf, + BNXT_ULP_CLASS_HID_f80f = 0xf80f, + BNXT_ULP_CLASS_HID_1c64f = 0x1c64f, + BNXT_ULP_CLASS_HID_1e88f = 0x1e88f, + BNXT_ULP_CLASS_HID_1cbcf = 0x1cbcf, + BNXT_ULP_CLASS_HID_1ee0f = 0x1ee0f, + BNXT_ULP_CLASS_HID_1ca9b = 0x1ca9b, + BNXT_ULP_CLASS_HID_1eddb = 0x1eddb, + BNXT_ULP_CLASS_HID_1d01b = 0x1d01b, + BNXT_ULP_CLASS_HID_1f35b = 0x1f35b, + BNXT_ULP_CLASS_HID_8b4b = 0x8b4b, + BNXT_ULP_CLASS_HID_ad8b = 0xad8b, + BNXT_ULP_CLASS_HID_d0cb = 0xd0cb, + BNXT_ULP_CLASS_HID_f30b = 0xf30b, + BNXT_ULP_CLASS_HID_867f = 0x867f, + BNXT_ULP_CLASS_HID_a8bf = 0xa8bf, + BNXT_ULP_CLASS_HID_cbff = 0xcbff, + BNXT_ULP_CLASS_HID_ee3f = 0xee3f, + BNXT_ULP_CLASS_HID_19c7f = 0x19c7f, + BNXT_ULP_CLASS_HID_1bebf = 0x1bebf, + BNXT_ULP_CLASS_HID_1e1ff = 0x1e1ff, + BNXT_ULP_CLASS_HID_1e43f = 0x1e43f, + BNXT_ULP_CLASS_HID_1a14b = 0x1a14b, + BNXT_ULP_CLASS_HID_1a38b = 0x1a38b, + BNXT_ULP_CLASS_HID_1e6cb = 0x1e6cb, + BNXT_ULP_CLASS_HID_1e90b = 0x1e90b, + BNXT_ULP_CLASS_HID_aedf = 0xaedf, + BNXT_ULP_CLASS_HID_b11f = 0xb11f, + BNXT_ULP_CLASS_HID_f45f = 0xf45f, + BNXT_ULP_CLASS_HID_f69f = 0xf69f, + BNXT_ULP_CLASS_HID_a983 = 0xa983, + BNXT_ULP_CLASS_HID_acc3 = 0xacc3, + BNXT_ULP_CLASS_HID_ef03 = 0xef03, + BNXT_ULP_CLASS_HID_f243 = 0xf243, + BNXT_ULP_CLASS_HID_1bf83 = 0x1bf83, + BNXT_ULP_CLASS_HID_1e2c3 = 0x1e2c3, + BNXT_ULP_CLASS_HID_1c503 = 0x1c503, + BNXT_ULP_CLASS_HID_1e843 = 0x1e843, + BNXT_ULP_CLASS_HID_1c4df = 0x1c4df, + BNXT_ULP_CLASS_HID_1e71f = 0x1e71f, + BNXT_ULP_CLASS_HID_1ca5f = 0x1ca5f, + BNXT_ULP_CLASS_HID_1ec9f = 0x1ec9f, + BNXT_ULP_CLASS_HID_2523 = 0x2523, + BNXT_ULP_CLASS_HID_2bef = 0x2bef, + BNXT_ULP_CLASS_HID_4f73 = 0x4f73, + BNXT_ULP_CLASS_HID_164b = 0x164b, + BNXT_ULP_CLASS_HID_39df = 0x39df, + BNXT_ULP_CLASS_HID_48b7 = 0x48b7, + BNXT_ULP_CLASS_HID_0f8f = 0x0f8f, + BNXT_ULP_CLASS_HID_3313 = 0x3313, + BNXT_ULP_CLASS_HID_257b7 = 0x257b7, + BNXT_ULP_CLASS_HID_24467 = 0x24467, + BNXT_ULP_CLASS_HID_23fbb = 0x23fbb, + BNXT_ULP_CLASS_HID_252cb = 0x252cb, + BNXT_ULP_CLASS_HID_21e7f = 0x21e7f, + BNXT_ULP_CLASS_HID_20b2f = 0x20b2f, + BNXT_ULP_CLASS_HID_20663 = 0x20663, + BNXT_ULP_CLASS_HID_219b3 = 0x219b3, + BNXT_ULP_CLASS_HID_24213 = 0x24213, + BNXT_ULP_CLASS_HID_22ec3 = 0x22ec3, + BNXT_ULP_CLASS_HID_22a17 = 0x22a17, + BNXT_ULP_CLASS_HID_23d27 = 0x23d27, + BNXT_ULP_CLASS_HID_208db = 0x208db, + BNXT_ULP_CLASS_HID_25277 = 0x25277, + BNXT_ULP_CLASS_HID_24d8b = 0x24d8b, + BNXT_ULP_CLASS_HID_203ef = 0x203ef, + BNXT_ULP_CLASS_HID_2517b = 0x2517b, + BNXT_ULP_CLASS_HID_23e2b = 0x23e2b, + BNXT_ULP_CLASS_HID_2397f = 0x2397f, + BNXT_ULP_CLASS_HID_24c8f = 0x24c8f, + BNXT_ULP_CLASS_HID_21823 = 0x21823, + BNXT_ULP_CLASS_HID_20513 = 0x20513, + BNXT_ULP_CLASS_HID_20027 = 0x20027, + BNXT_ULP_CLASS_HID_21377 = 0x21377, + BNXT_ULP_CLASS_HID_23bd7 = 0x23bd7, + BNXT_ULP_CLASS_HID_22887 = 0x22887, + BNXT_ULP_CLASS_HID_223db = 0x223db, + BNXT_ULP_CLASS_HID_236eb = 0x236eb, + BNXT_ULP_CLASS_HID_2029f = 0x2029f, + BNXT_ULP_CLASS_HID_24c3b = 0x24c3b, + BNXT_ULP_CLASS_HID_2474f = 0x2474f, + BNXT_ULP_CLASS_HID_25a9f = 0x25a9f, + BNXT_ULP_CLASS_HID_24b3f = 0x24b3f, + BNXT_ULP_CLASS_HID_237ef = 0x237ef, + BNXT_ULP_CLASS_HID_23323 = 0x23323, + BNXT_ULP_CLASS_HID_24673 = 0x24673, + BNXT_ULP_CLASS_HID_211e7 = 0x211e7, + BNXT_ULP_CLASS_HID_25b83 = 0x25b83, + BNXT_ULP_CLASS_HID_256d7 = 0x256d7, + BNXT_ULP_CLASS_HID_20d3b = 0x20d3b, + BNXT_ULP_CLASS_HID_2359b = 0x2359b, + BNXT_ULP_CLASS_HID_2224b = 0x2224b, + BNXT_ULP_CLASS_HID_21d9f = 0x21d9f, + BNXT_ULP_CLASS_HID_230af = 0x230af, + BNXT_ULP_CLASS_HID_2590f = 0x2590f, + BNXT_ULP_CLASS_HID_245ff = 0x245ff, + BNXT_ULP_CLASS_HID_24133 = 0x24133, + BNXT_ULP_CLASS_HID_25443 = 0x25443, + BNXT_ULP_CLASS_HID_244e3 = 0x244e3, + BNXT_ULP_CLASS_HID_231d3 = 0x231d3, + BNXT_ULP_CLASS_HID_22ce7 = 0x22ce7, + BNXT_ULP_CLASS_HID_24037 = 0x24037, + BNXT_ULP_CLASS_HID_20bab = 0x20bab, + BNXT_ULP_CLASS_HID_25547 = 0x25547, + BNXT_ULP_CLASS_HID_2509b = 0x2509b, + BNXT_ULP_CLASS_HID_206ff = 0x206ff, + BNXT_ULP_CLASS_HID_22f5f = 0x22f5f, + BNXT_ULP_CLASS_HID_21c0f = 0x21c0f, + BNXT_ULP_CLASS_HID_21743 = 0x21743, + BNXT_ULP_CLASS_HID_22a93 = 0x22a93, + BNXT_ULP_CLASS_HID_252f3 = 0x252f3, + BNXT_ULP_CLASS_HID_23fa3 = 0x23fa3, + BNXT_ULP_CLASS_HID_23af7 = 0x23af7, + BNXT_ULP_CLASS_HID_24e07 = 0x24e07, + BNXT_ULP_CLASS_HID_2322f = 0x2322f, + BNXT_ULP_CLASS_HID_21f1f = 0x21f1f, + BNXT_ULP_CLASS_HID_21a53 = 0x21a53, + BNXT_ULP_CLASS_HID_22d63 = 0x22d63, + BNXT_ULP_CLASS_HID_255c3 = 0x255c3, + BNXT_ULP_CLASS_HID_242b3 = 0x242b3, + BNXT_ULP_CLASS_HID_23dc7 = 0x23dc7, + BNXT_ULP_CLASS_HID_25117 = 0x25117, + BNXT_ULP_CLASS_HID_22c13 = 0x22c13, + BNXT_ULP_CLASS_HID_218c3 = 0x218c3, + BNXT_ULP_CLASS_HID_21417 = 0x21417, + BNXT_ULP_CLASS_HID_22727 = 0x22727, + BNXT_ULP_CLASS_HID_24f87 = 0x24f87, + BNXT_ULP_CLASS_HID_23c77 = 0x23c77, + BNXT_ULP_CLASS_HID_2378b = 0x2378b, + BNXT_ULP_CLASS_HID_24adb = 0x24adb, + BNXT_ULP_CLASS_HID_257b = 0x257b, + BNXT_ULP_CLASS_HID_2bb7 = 0x2bb7, + BNXT_ULP_CLASS_HID_4f2b = 0x4f2b, + BNXT_ULP_CLASS_HID_1613 = 0x1613, + BNXT_ULP_CLASS_HID_3987 = 0x3987, + BNXT_ULP_CLASS_HID_48ef = 0x48ef, + BNXT_ULP_CLASS_HID_0fd7 = 0x0fd7, + BNXT_ULP_CLASS_HID_334b = 0x334b, + BNXT_ULP_CLASS_HID_25797 = 0x25797, + BNXT_ULP_CLASS_HID_285eb = 0x285eb, + BNXT_ULP_CLASS_HID_310eb = 0x310eb, + BNXT_ULP_CLASS_HID_39beb = 0x39beb, + BNXT_ULP_CLASS_HID_24447 = 0x24447, + BNXT_ULP_CLASS_HID_2cf47 = 0x2cf47, + BNXT_ULP_CLASS_HID_35a47 = 0x35a47, + BNXT_ULP_CLASS_HID_3889b = 0x3889b, + BNXT_ULP_CLASS_HID_23f9b = 0x23f9b, + BNXT_ULP_CLASS_HID_2ca9b = 0x2ca9b, + BNXT_ULP_CLASS_HID_3559b = 0x3559b, + BNXT_ULP_CLASS_HID_383ef = 0x383ef, + BNXT_ULP_CLASS_HID_252eb = 0x252eb, + BNXT_ULP_CLASS_HID_2813f = 0x2813f, + BNXT_ULP_CLASS_HID_30c3f = 0x30c3f, + BNXT_ULP_CLASS_HID_3973f = 0x3973f, + BNXT_ULP_CLASS_HID_21e5f = 0x21e5f, + BNXT_ULP_CLASS_HID_2a95f = 0x2a95f, + BNXT_ULP_CLASS_HID_3345f = 0x3345f, + BNXT_ULP_CLASS_HID_3bf5f = 0x3bf5f, + BNXT_ULP_CLASS_HID_20b0f = 0x20b0f, + BNXT_ULP_CLASS_HID_2960f = 0x2960f, + BNXT_ULP_CLASS_HID_3210f = 0x3210f, + BNXT_ULP_CLASS_HID_3ac0f = 0x3ac0f, + BNXT_ULP_CLASS_HID_20643 = 0x20643, + BNXT_ULP_CLASS_HID_29143 = 0x29143, + BNXT_ULP_CLASS_HID_31c43 = 0x31c43, + BNXT_ULP_CLASS_HID_3a743 = 0x3a743, + BNXT_ULP_CLASS_HID_21993 = 0x21993, + BNXT_ULP_CLASS_HID_2a493 = 0x2a493, + BNXT_ULP_CLASS_HID_32f93 = 0x32f93, + BNXT_ULP_CLASS_HID_3ba93 = 0x3ba93, + BNXT_ULP_CLASS_HID_24233 = 0x24233, + BNXT_ULP_CLASS_HID_2cd33 = 0x2cd33, + BNXT_ULP_CLASS_HID_35833 = 0x35833, + BNXT_ULP_CLASS_HID_38607 = 0x38607, + BNXT_ULP_CLASS_HID_22ee3 = 0x22ee3, + BNXT_ULP_CLASS_HID_2b9e3 = 0x2b9e3, + BNXT_ULP_CLASS_HID_344e3 = 0x344e3, + BNXT_ULP_CLASS_HID_3cfe3 = 0x3cfe3, + BNXT_ULP_CLASS_HID_22a37 = 0x22a37, + BNXT_ULP_CLASS_HID_2b537 = 0x2b537, + BNXT_ULP_CLASS_HID_34037 = 0x34037, + BNXT_ULP_CLASS_HID_3cb37 = 0x3cb37, + BNXT_ULP_CLASS_HID_23d07 = 0x23d07, + BNXT_ULP_CLASS_HID_2c807 = 0x2c807, + BNXT_ULP_CLASS_HID_35307 = 0x35307, + BNXT_ULP_CLASS_HID_3815b = 0x3815b, + BNXT_ULP_CLASS_HID_208fb = 0x208fb, + BNXT_ULP_CLASS_HID_293fb = 0x293fb, + BNXT_ULP_CLASS_HID_31efb = 0x31efb, + BNXT_ULP_CLASS_HID_3a9fb = 0x3a9fb, + BNXT_ULP_CLASS_HID_25257 = 0x25257, + BNXT_ULP_CLASS_HID_280ab = 0x280ab, + BNXT_ULP_CLASS_HID_30bab = 0x30bab, + BNXT_ULP_CLASS_HID_396ab = 0x396ab, + BNXT_ULP_CLASS_HID_24dab = 0x24dab, + BNXT_ULP_CLASS_HID_2d8ab = 0x2d8ab, + BNXT_ULP_CLASS_HID_306ff = 0x306ff, + BNXT_ULP_CLASS_HID_391ff = 0x391ff, + BNXT_ULP_CLASS_HID_203cf = 0x203cf, + BNXT_ULP_CLASS_HID_28ecf = 0x28ecf, + BNXT_ULP_CLASS_HID_319cf = 0x319cf, + BNXT_ULP_CLASS_HID_3a4cf = 0x3a4cf, + BNXT_ULP_CLASS_HID_2515b = 0x2515b, + BNXT_ULP_CLASS_HID_2dc5b = 0x2dc5b, + BNXT_ULP_CLASS_HID_30aaf = 0x30aaf, + BNXT_ULP_CLASS_HID_395af = 0x395af, + BNXT_ULP_CLASS_HID_23e0b = 0x23e0b, + BNXT_ULP_CLASS_HID_2c90b = 0x2c90b, + BNXT_ULP_CLASS_HID_3540b = 0x3540b, + BNXT_ULP_CLASS_HID_3825f = 0x3825f, + BNXT_ULP_CLASS_HID_2395f = 0x2395f, + BNXT_ULP_CLASS_HID_2c45f = 0x2c45f, + BNXT_ULP_CLASS_HID_34f5f = 0x34f5f, + BNXT_ULP_CLASS_HID_3da5f = 0x3da5f, + BNXT_ULP_CLASS_HID_24caf = 0x24caf, + BNXT_ULP_CLASS_HID_2d7af = 0x2d7af, + BNXT_ULP_CLASS_HID_305e3 = 0x305e3, + BNXT_ULP_CLASS_HID_390e3 = 0x390e3, + BNXT_ULP_CLASS_HID_21803 = 0x21803, + BNXT_ULP_CLASS_HID_2a303 = 0x2a303, + BNXT_ULP_CLASS_HID_32e03 = 0x32e03, + BNXT_ULP_CLASS_HID_3b903 = 0x3b903, + BNXT_ULP_CLASS_HID_20533 = 0x20533, + BNXT_ULP_CLASS_HID_29033 = 0x29033, + BNXT_ULP_CLASS_HID_31b33 = 0x31b33, + BNXT_ULP_CLASS_HID_3a633 = 0x3a633, + BNXT_ULP_CLASS_HID_20007 = 0x20007, + BNXT_ULP_CLASS_HID_28b07 = 0x28b07, + BNXT_ULP_CLASS_HID_31607 = 0x31607, + BNXT_ULP_CLASS_HID_3a107 = 0x3a107, + BNXT_ULP_CLASS_HID_21357 = 0x21357, + BNXT_ULP_CLASS_HID_29e57 = 0x29e57, + BNXT_ULP_CLASS_HID_32957 = 0x32957, + BNXT_ULP_CLASS_HID_3b457 = 0x3b457, + BNXT_ULP_CLASS_HID_23bf7 = 0x23bf7, + BNXT_ULP_CLASS_HID_2c6f7 = 0x2c6f7, + BNXT_ULP_CLASS_HID_351f7 = 0x351f7, + BNXT_ULP_CLASS_HID_3dcf7 = 0x3dcf7, + BNXT_ULP_CLASS_HID_228a7 = 0x228a7, + BNXT_ULP_CLASS_HID_2b3a7 = 0x2b3a7, + BNXT_ULP_CLASS_HID_33ea7 = 0x33ea7, + BNXT_ULP_CLASS_HID_3c9a7 = 0x3c9a7, + BNXT_ULP_CLASS_HID_223fb = 0x223fb, + BNXT_ULP_CLASS_HID_2aefb = 0x2aefb, + BNXT_ULP_CLASS_HID_339fb = 0x339fb, + BNXT_ULP_CLASS_HID_3c4fb = 0x3c4fb, + BNXT_ULP_CLASS_HID_236cb = 0x236cb, + BNXT_ULP_CLASS_HID_2c1cb = 0x2c1cb, + BNXT_ULP_CLASS_HID_34ccb = 0x34ccb, + BNXT_ULP_CLASS_HID_3d7cb = 0x3d7cb, + BNXT_ULP_CLASS_HID_202bf = 0x202bf, + BNXT_ULP_CLASS_HID_28dbf = 0x28dbf, + BNXT_ULP_CLASS_HID_318bf = 0x318bf, + BNXT_ULP_CLASS_HID_3a3bf = 0x3a3bf, + BNXT_ULP_CLASS_HID_24c1b = 0x24c1b, + BNXT_ULP_CLASS_HID_2d71b = 0x2d71b, + BNXT_ULP_CLASS_HID_3056f = 0x3056f, + BNXT_ULP_CLASS_HID_3906f = 0x3906f, + BNXT_ULP_CLASS_HID_2476f = 0x2476f, + BNXT_ULP_CLASS_HID_2d26f = 0x2d26f, + BNXT_ULP_CLASS_HID_300a3 = 0x300a3, + BNXT_ULP_CLASS_HID_38ba3 = 0x38ba3, + BNXT_ULP_CLASS_HID_25abf = 0x25abf, + BNXT_ULP_CLASS_HID_288f3 = 0x288f3, + BNXT_ULP_CLASS_HID_313f3 = 0x313f3, + BNXT_ULP_CLASS_HID_39ef3 = 0x39ef3, + BNXT_ULP_CLASS_HID_24b1f = 0x24b1f, + BNXT_ULP_CLASS_HID_2d61f = 0x2d61f, + BNXT_ULP_CLASS_HID_30453 = 0x30453, + BNXT_ULP_CLASS_HID_38f53 = 0x38f53, + BNXT_ULP_CLASS_HID_237cf = 0x237cf, + BNXT_ULP_CLASS_HID_2c2cf = 0x2c2cf, + BNXT_ULP_CLASS_HID_34dcf = 0x34dcf, + BNXT_ULP_CLASS_HID_3d8cf = 0x3d8cf, + BNXT_ULP_CLASS_HID_23303 = 0x23303, + BNXT_ULP_CLASS_HID_2be03 = 0x2be03, + BNXT_ULP_CLASS_HID_34903 = 0x34903, + BNXT_ULP_CLASS_HID_3d403 = 0x3d403, + BNXT_ULP_CLASS_HID_24653 = 0x24653, + BNXT_ULP_CLASS_HID_2d153 = 0x2d153, + BNXT_ULP_CLASS_HID_35c53 = 0x35c53, + BNXT_ULP_CLASS_HID_38aa7 = 0x38aa7, + BNXT_ULP_CLASS_HID_211c7 = 0x211c7, + BNXT_ULP_CLASS_HID_29cc7 = 0x29cc7, + BNXT_ULP_CLASS_HID_327c7 = 0x327c7, + BNXT_ULP_CLASS_HID_3b2c7 = 0x3b2c7, + BNXT_ULP_CLASS_HID_25ba3 = 0x25ba3, + BNXT_ULP_CLASS_HID_289f7 = 0x289f7, + BNXT_ULP_CLASS_HID_314f7 = 0x314f7, + BNXT_ULP_CLASS_HID_39ff7 = 0x39ff7, + BNXT_ULP_CLASS_HID_256f7 = 0x256f7, + BNXT_ULP_CLASS_HID_284cb = 0x284cb, + BNXT_ULP_CLASS_HID_30fcb = 0x30fcb, + BNXT_ULP_CLASS_HID_39acb = 0x39acb, + BNXT_ULP_CLASS_HID_20d1b = 0x20d1b, + BNXT_ULP_CLASS_HID_2981b = 0x2981b, + BNXT_ULP_CLASS_HID_3231b = 0x3231b, + BNXT_ULP_CLASS_HID_3ae1b = 0x3ae1b, + BNXT_ULP_CLASS_HID_235bb = 0x235bb, + BNXT_ULP_CLASS_HID_2c0bb = 0x2c0bb, + BNXT_ULP_CLASS_HID_34bbb = 0x34bbb, + BNXT_ULP_CLASS_HID_3d6bb = 0x3d6bb, + BNXT_ULP_CLASS_HID_2226b = 0x2226b, + BNXT_ULP_CLASS_HID_2ad6b = 0x2ad6b, + BNXT_ULP_CLASS_HID_3386b = 0x3386b, + BNXT_ULP_CLASS_HID_3c36b = 0x3c36b, + BNXT_ULP_CLASS_HID_21dbf = 0x21dbf, + BNXT_ULP_CLASS_HID_2a8bf = 0x2a8bf, + BNXT_ULP_CLASS_HID_333bf = 0x333bf, + BNXT_ULP_CLASS_HID_3bebf = 0x3bebf, + BNXT_ULP_CLASS_HID_2308f = 0x2308f, + BNXT_ULP_CLASS_HID_2bb8f = 0x2bb8f, + BNXT_ULP_CLASS_HID_3468f = 0x3468f, + BNXT_ULP_CLASS_HID_3d18f = 0x3d18f, + BNXT_ULP_CLASS_HID_2592f = 0x2592f, + BNXT_ULP_CLASS_HID_28763 = 0x28763, + BNXT_ULP_CLASS_HID_31263 = 0x31263, + BNXT_ULP_CLASS_HID_39d63 = 0x39d63, + BNXT_ULP_CLASS_HID_245df = 0x245df, + BNXT_ULP_CLASS_HID_2d0df = 0x2d0df, + BNXT_ULP_CLASS_HID_35bdf = 0x35bdf, + BNXT_ULP_CLASS_HID_38a13 = 0x38a13, + BNXT_ULP_CLASS_HID_24113 = 0x24113, + BNXT_ULP_CLASS_HID_2cc13 = 0x2cc13, + BNXT_ULP_CLASS_HID_35713 = 0x35713, + BNXT_ULP_CLASS_HID_38567 = 0x38567, + BNXT_ULP_CLASS_HID_25463 = 0x25463, + BNXT_ULP_CLASS_HID_282b7 = 0x282b7, + BNXT_ULP_CLASS_HID_30db7 = 0x30db7, + BNXT_ULP_CLASS_HID_398b7 = 0x398b7, + BNXT_ULP_CLASS_HID_244c3 = 0x244c3, + BNXT_ULP_CLASS_HID_2cfc3 = 0x2cfc3, + BNXT_ULP_CLASS_HID_35ac3 = 0x35ac3, + BNXT_ULP_CLASS_HID_38917 = 0x38917, + BNXT_ULP_CLASS_HID_231f3 = 0x231f3, + BNXT_ULP_CLASS_HID_2bcf3 = 0x2bcf3, + BNXT_ULP_CLASS_HID_347f3 = 0x347f3, + BNXT_ULP_CLASS_HID_3d2f3 = 0x3d2f3, + BNXT_ULP_CLASS_HID_22cc7 = 0x22cc7, + BNXT_ULP_CLASS_HID_2b7c7 = 0x2b7c7, + BNXT_ULP_CLASS_HID_342c7 = 0x342c7, + BNXT_ULP_CLASS_HID_3cdc7 = 0x3cdc7, + BNXT_ULP_CLASS_HID_24017 = 0x24017, + BNXT_ULP_CLASS_HID_2cb17 = 0x2cb17, + BNXT_ULP_CLASS_HID_35617 = 0x35617, + BNXT_ULP_CLASS_HID_3846b = 0x3846b, + BNXT_ULP_CLASS_HID_20b8b = 0x20b8b, + BNXT_ULP_CLASS_HID_2968b = 0x2968b, + BNXT_ULP_CLASS_HID_3218b = 0x3218b, + BNXT_ULP_CLASS_HID_3ac8b = 0x3ac8b, + BNXT_ULP_CLASS_HID_25567 = 0x25567, + BNXT_ULP_CLASS_HID_283bb = 0x283bb, + BNXT_ULP_CLASS_HID_30ebb = 0x30ebb, + BNXT_ULP_CLASS_HID_399bb = 0x399bb, + BNXT_ULP_CLASS_HID_250bb = 0x250bb, + BNXT_ULP_CLASS_HID_2dbbb = 0x2dbbb, + BNXT_ULP_CLASS_HID_3098f = 0x3098f, + BNXT_ULP_CLASS_HID_3948f = 0x3948f, + BNXT_ULP_CLASS_HID_206df = 0x206df, + BNXT_ULP_CLASS_HID_291df = 0x291df, + BNXT_ULP_CLASS_HID_31cdf = 0x31cdf, + BNXT_ULP_CLASS_HID_3a7df = 0x3a7df, + BNXT_ULP_CLASS_HID_22f7f = 0x22f7f, + BNXT_ULP_CLASS_HID_2ba7f = 0x2ba7f, + BNXT_ULP_CLASS_HID_3457f = 0x3457f, + BNXT_ULP_CLASS_HID_3d07f = 0x3d07f, + BNXT_ULP_CLASS_HID_21c2f = 0x21c2f, + BNXT_ULP_CLASS_HID_2a72f = 0x2a72f, + BNXT_ULP_CLASS_HID_3322f = 0x3322f, + BNXT_ULP_CLASS_HID_3bd2f = 0x3bd2f, + BNXT_ULP_CLASS_HID_21763 = 0x21763, + BNXT_ULP_CLASS_HID_2a263 = 0x2a263, + BNXT_ULP_CLASS_HID_32d63 = 0x32d63, + BNXT_ULP_CLASS_HID_3b863 = 0x3b863, + BNXT_ULP_CLASS_HID_22ab3 = 0x22ab3, + BNXT_ULP_CLASS_HID_2b5b3 = 0x2b5b3, + BNXT_ULP_CLASS_HID_340b3 = 0x340b3, + BNXT_ULP_CLASS_HID_3cbb3 = 0x3cbb3, + BNXT_ULP_CLASS_HID_252d3 = 0x252d3, + BNXT_ULP_CLASS_HID_28127 = 0x28127, + BNXT_ULP_CLASS_HID_30c27 = 0x30c27, + BNXT_ULP_CLASS_HID_39727 = 0x39727, + BNXT_ULP_CLASS_HID_23f83 = 0x23f83, + BNXT_ULP_CLASS_HID_2ca83 = 0x2ca83, + BNXT_ULP_CLASS_HID_35583 = 0x35583, + BNXT_ULP_CLASS_HID_383d7 = 0x383d7, + BNXT_ULP_CLASS_HID_23ad7 = 0x23ad7, + BNXT_ULP_CLASS_HID_2c5d7 = 0x2c5d7, + BNXT_ULP_CLASS_HID_350d7 = 0x350d7, + BNXT_ULP_CLASS_HID_3dbd7 = 0x3dbd7, + BNXT_ULP_CLASS_HID_24e27 = 0x24e27, + BNXT_ULP_CLASS_HID_2d927 = 0x2d927, + BNXT_ULP_CLASS_HID_3077b = 0x3077b, + BNXT_ULP_CLASS_HID_3927b = 0x3927b, + BNXT_ULP_CLASS_HID_2320f = 0x2320f, + BNXT_ULP_CLASS_HID_2bd0f = 0x2bd0f, + BNXT_ULP_CLASS_HID_3480f = 0x3480f, + BNXT_ULP_CLASS_HID_3d30f = 0x3d30f, + BNXT_ULP_CLASS_HID_21f3f = 0x21f3f, + BNXT_ULP_CLASS_HID_2aa3f = 0x2aa3f, + BNXT_ULP_CLASS_HID_3353f = 0x3353f, + BNXT_ULP_CLASS_HID_3c03f = 0x3c03f, + BNXT_ULP_CLASS_HID_21a73 = 0x21a73, + BNXT_ULP_CLASS_HID_2a573 = 0x2a573, + BNXT_ULP_CLASS_HID_33073 = 0x33073, + BNXT_ULP_CLASS_HID_3bb73 = 0x3bb73, + BNXT_ULP_CLASS_HID_22d43 = 0x22d43, + BNXT_ULP_CLASS_HID_2b843 = 0x2b843, + BNXT_ULP_CLASS_HID_34343 = 0x34343, + BNXT_ULP_CLASS_HID_3ce43 = 0x3ce43, + BNXT_ULP_CLASS_HID_255e3 = 0x255e3, + BNXT_ULP_CLASS_HID_28437 = 0x28437, + BNXT_ULP_CLASS_HID_30f37 = 0x30f37, + BNXT_ULP_CLASS_HID_39a37 = 0x39a37, + BNXT_ULP_CLASS_HID_24293 = 0x24293, + BNXT_ULP_CLASS_HID_2cd93 = 0x2cd93, + BNXT_ULP_CLASS_HID_35893 = 0x35893, + BNXT_ULP_CLASS_HID_386e7 = 0x386e7, + BNXT_ULP_CLASS_HID_23de7 = 0x23de7, + BNXT_ULP_CLASS_HID_2c8e7 = 0x2c8e7, + BNXT_ULP_CLASS_HID_353e7 = 0x353e7, + BNXT_ULP_CLASS_HID_3823b = 0x3823b, + BNXT_ULP_CLASS_HID_25137 = 0x25137, + BNXT_ULP_CLASS_HID_2dc37 = 0x2dc37, + BNXT_ULP_CLASS_HID_30a0b = 0x30a0b, + BNXT_ULP_CLASS_HID_3950b = 0x3950b, + BNXT_ULP_CLASS_HID_22c33 = 0x22c33, + BNXT_ULP_CLASS_HID_2b733 = 0x2b733, + BNXT_ULP_CLASS_HID_34233 = 0x34233, + BNXT_ULP_CLASS_HID_3cd33 = 0x3cd33, + BNXT_ULP_CLASS_HID_218e3 = 0x218e3, + BNXT_ULP_CLASS_HID_2a3e3 = 0x2a3e3, + BNXT_ULP_CLASS_HID_32ee3 = 0x32ee3, + BNXT_ULP_CLASS_HID_3b9e3 = 0x3b9e3, + BNXT_ULP_CLASS_HID_21437 = 0x21437, + BNXT_ULP_CLASS_HID_29f37 = 0x29f37, + BNXT_ULP_CLASS_HID_32a37 = 0x32a37, + BNXT_ULP_CLASS_HID_3b537 = 0x3b537, + BNXT_ULP_CLASS_HID_22707 = 0x22707, + BNXT_ULP_CLASS_HID_2b207 = 0x2b207, + BNXT_ULP_CLASS_HID_33d07 = 0x33d07, + BNXT_ULP_CLASS_HID_3c807 = 0x3c807, + BNXT_ULP_CLASS_HID_24fa7 = 0x24fa7, + BNXT_ULP_CLASS_HID_2daa7 = 0x2daa7, + BNXT_ULP_CLASS_HID_308fb = 0x308fb, + BNXT_ULP_CLASS_HID_393fb = 0x393fb, + BNXT_ULP_CLASS_HID_23c57 = 0x23c57, + BNXT_ULP_CLASS_HID_2c757 = 0x2c757, + BNXT_ULP_CLASS_HID_35257 = 0x35257, + BNXT_ULP_CLASS_HID_380ab = 0x380ab, + BNXT_ULP_CLASS_HID_237ab = 0x237ab, + BNXT_ULP_CLASS_HID_2c2ab = 0x2c2ab, + BNXT_ULP_CLASS_HID_34dab = 0x34dab, + BNXT_ULP_CLASS_HID_3d8ab = 0x3d8ab, + BNXT_ULP_CLASS_HID_24afb = 0x24afb, + BNXT_ULP_CLASS_HID_2d5fb = 0x2d5fb, + BNXT_ULP_CLASS_HID_303cf = 0x303cf, + BNXT_ULP_CLASS_HID_38ecf = 0x38ecf, + BNXT_ULP_CLASS_HID_255b = 0x255b, + BNXT_ULP_CLASS_HID_2b97 = 0x2b97, + BNXT_ULP_CLASS_HID_4f0b = 0x4f0b, + BNXT_ULP_CLASS_HID_1633 = 0x1633, + BNXT_ULP_CLASS_HID_39a7 = 0x39a7, + BNXT_ULP_CLASS_HID_48cf = 0x48cf, + BNXT_ULP_CLASS_HID_0ff7 = 0x0ff7, + BNXT_ULP_CLASS_HID_336b = 0x336b, + BNXT_ULP_CLASS_HID_257f7 = 0x257f7, + BNXT_ULP_CLASS_HID_2858b = 0x2858b, + BNXT_ULP_CLASS_HID_3108b = 0x3108b, + BNXT_ULP_CLASS_HID_39b8b = 0x39b8b, + BNXT_ULP_CLASS_HID_24427 = 0x24427, + BNXT_ULP_CLASS_HID_2cf27 = 0x2cf27, + BNXT_ULP_CLASS_HID_35a27 = 0x35a27, + BNXT_ULP_CLASS_HID_388fb = 0x388fb, + BNXT_ULP_CLASS_HID_23ffb = 0x23ffb, + BNXT_ULP_CLASS_HID_2cafb = 0x2cafb, + BNXT_ULP_CLASS_HID_355fb = 0x355fb, + BNXT_ULP_CLASS_HID_3838f = 0x3838f, + BNXT_ULP_CLASS_HID_2528b = 0x2528b, + BNXT_ULP_CLASS_HID_2815f = 0x2815f, + BNXT_ULP_CLASS_HID_30c5f = 0x30c5f, + BNXT_ULP_CLASS_HID_3975f = 0x3975f, + BNXT_ULP_CLASS_HID_21e3f = 0x21e3f, + BNXT_ULP_CLASS_HID_2a93f = 0x2a93f, + BNXT_ULP_CLASS_HID_3343f = 0x3343f, + BNXT_ULP_CLASS_HID_3bf3f = 0x3bf3f, + BNXT_ULP_CLASS_HID_20b6f = 0x20b6f, + BNXT_ULP_CLASS_HID_2966f = 0x2966f, + BNXT_ULP_CLASS_HID_3216f = 0x3216f, + BNXT_ULP_CLASS_HID_3ac6f = 0x3ac6f, + BNXT_ULP_CLASS_HID_20623 = 0x20623, + BNXT_ULP_CLASS_HID_29123 = 0x29123, + BNXT_ULP_CLASS_HID_31c23 = 0x31c23, + BNXT_ULP_CLASS_HID_3a723 = 0x3a723, + BNXT_ULP_CLASS_HID_219f3 = 0x219f3, + BNXT_ULP_CLASS_HID_2a4f3 = 0x2a4f3, + BNXT_ULP_CLASS_HID_32ff3 = 0x32ff3, + BNXT_ULP_CLASS_HID_3baf3 = 0x3baf3, + BNXT_ULP_CLASS_HID_24253 = 0x24253, + BNXT_ULP_CLASS_HID_2cd53 = 0x2cd53, + BNXT_ULP_CLASS_HID_35853 = 0x35853, + BNXT_ULP_CLASS_HID_38667 = 0x38667, + BNXT_ULP_CLASS_HID_22e83 = 0x22e83, + BNXT_ULP_CLASS_HID_2b983 = 0x2b983, + BNXT_ULP_CLASS_HID_34483 = 0x34483, + BNXT_ULP_CLASS_HID_3cf83 = 0x3cf83, + BNXT_ULP_CLASS_HID_22a57 = 0x22a57, + BNXT_ULP_CLASS_HID_2b557 = 0x2b557, + BNXT_ULP_CLASS_HID_34057 = 0x34057, + BNXT_ULP_CLASS_HID_3cb57 = 0x3cb57, + BNXT_ULP_CLASS_HID_23d67 = 0x23d67, + BNXT_ULP_CLASS_HID_2c867 = 0x2c867, + BNXT_ULP_CLASS_HID_35367 = 0x35367, + BNXT_ULP_CLASS_HID_3813b = 0x3813b, + BNXT_ULP_CLASS_HID_2089b = 0x2089b, + BNXT_ULP_CLASS_HID_2939b = 0x2939b, + BNXT_ULP_CLASS_HID_31e9b = 0x31e9b, + BNXT_ULP_CLASS_HID_3a99b = 0x3a99b, + BNXT_ULP_CLASS_HID_25237 = 0x25237, + BNXT_ULP_CLASS_HID_280cb = 0x280cb, + BNXT_ULP_CLASS_HID_30bcb = 0x30bcb, + BNXT_ULP_CLASS_HID_396cb = 0x396cb, + BNXT_ULP_CLASS_HID_24dcb = 0x24dcb, + BNXT_ULP_CLASS_HID_2d8cb = 0x2d8cb, + BNXT_ULP_CLASS_HID_3069f = 0x3069f, + BNXT_ULP_CLASS_HID_3919f = 0x3919f, + BNXT_ULP_CLASS_HID_203af = 0x203af, + BNXT_ULP_CLASS_HID_28eaf = 0x28eaf, + BNXT_ULP_CLASS_HID_319af = 0x319af, + BNXT_ULP_CLASS_HID_3a4af = 0x3a4af, + BNXT_ULP_CLASS_HID_2513b = 0x2513b, + BNXT_ULP_CLASS_HID_2dc3b = 0x2dc3b, + BNXT_ULP_CLASS_HID_30acf = 0x30acf, + BNXT_ULP_CLASS_HID_395cf = 0x395cf, + BNXT_ULP_CLASS_HID_23e6b = 0x23e6b, + BNXT_ULP_CLASS_HID_2c96b = 0x2c96b, + BNXT_ULP_CLASS_HID_3546b = 0x3546b, + BNXT_ULP_CLASS_HID_3823f = 0x3823f, + BNXT_ULP_CLASS_HID_2393f = 0x2393f, + BNXT_ULP_CLASS_HID_2c43f = 0x2c43f, + BNXT_ULP_CLASS_HID_34f3f = 0x34f3f, + BNXT_ULP_CLASS_HID_3da3f = 0x3da3f, + BNXT_ULP_CLASS_HID_24ccf = 0x24ccf, + BNXT_ULP_CLASS_HID_2d7cf = 0x2d7cf, + BNXT_ULP_CLASS_HID_30583 = 0x30583, + BNXT_ULP_CLASS_HID_39083 = 0x39083, + BNXT_ULP_CLASS_HID_21863 = 0x21863, + BNXT_ULP_CLASS_HID_2a363 = 0x2a363, + BNXT_ULP_CLASS_HID_32e63 = 0x32e63, + BNXT_ULP_CLASS_HID_3b963 = 0x3b963, + BNXT_ULP_CLASS_HID_20553 = 0x20553, + BNXT_ULP_CLASS_HID_29053 = 0x29053, + BNXT_ULP_CLASS_HID_31b53 = 0x31b53, + BNXT_ULP_CLASS_HID_3a653 = 0x3a653, + BNXT_ULP_CLASS_HID_20067 = 0x20067, + BNXT_ULP_CLASS_HID_28b67 = 0x28b67, + BNXT_ULP_CLASS_HID_31667 = 0x31667, + BNXT_ULP_CLASS_HID_3a167 = 0x3a167, + BNXT_ULP_CLASS_HID_21337 = 0x21337, + BNXT_ULP_CLASS_HID_29e37 = 0x29e37, + BNXT_ULP_CLASS_HID_32937 = 0x32937, + BNXT_ULP_CLASS_HID_3b437 = 0x3b437, + BNXT_ULP_CLASS_HID_23b97 = 0x23b97, + BNXT_ULP_CLASS_HID_2c697 = 0x2c697, + BNXT_ULP_CLASS_HID_35197 = 0x35197, + BNXT_ULP_CLASS_HID_3dc97 = 0x3dc97, + BNXT_ULP_CLASS_HID_228c7 = 0x228c7, + BNXT_ULP_CLASS_HID_2b3c7 = 0x2b3c7, + BNXT_ULP_CLASS_HID_33ec7 = 0x33ec7, + BNXT_ULP_CLASS_HID_3c9c7 = 0x3c9c7, + BNXT_ULP_CLASS_HID_2239b = 0x2239b, + BNXT_ULP_CLASS_HID_2ae9b = 0x2ae9b, + BNXT_ULP_CLASS_HID_3399b = 0x3399b, + BNXT_ULP_CLASS_HID_3c49b = 0x3c49b, + BNXT_ULP_CLASS_HID_236ab = 0x236ab, + BNXT_ULP_CLASS_HID_2c1ab = 0x2c1ab, + BNXT_ULP_CLASS_HID_34cab = 0x34cab, + BNXT_ULP_CLASS_HID_3d7ab = 0x3d7ab, + BNXT_ULP_CLASS_HID_202df = 0x202df, + BNXT_ULP_CLASS_HID_28ddf = 0x28ddf, + BNXT_ULP_CLASS_HID_318df = 0x318df, + BNXT_ULP_CLASS_HID_3a3df = 0x3a3df, + BNXT_ULP_CLASS_HID_24c7b = 0x24c7b, + BNXT_ULP_CLASS_HID_2d77b = 0x2d77b, + BNXT_ULP_CLASS_HID_3050f = 0x3050f, + BNXT_ULP_CLASS_HID_3900f = 0x3900f, + BNXT_ULP_CLASS_HID_2470f = 0x2470f, + BNXT_ULP_CLASS_HID_2d20f = 0x2d20f, + BNXT_ULP_CLASS_HID_300c3 = 0x300c3, + BNXT_ULP_CLASS_HID_38bc3 = 0x38bc3, + BNXT_ULP_CLASS_HID_25adf = 0x25adf, + BNXT_ULP_CLASS_HID_28893 = 0x28893, + BNXT_ULP_CLASS_HID_31393 = 0x31393, + BNXT_ULP_CLASS_HID_39e93 = 0x39e93, + BNXT_ULP_CLASS_HID_24b7f = 0x24b7f, + BNXT_ULP_CLASS_HID_2d67f = 0x2d67f, + BNXT_ULP_CLASS_HID_30433 = 0x30433, + BNXT_ULP_CLASS_HID_38f33 = 0x38f33, + BNXT_ULP_CLASS_HID_237af = 0x237af, + BNXT_ULP_CLASS_HID_2c2af = 0x2c2af, + BNXT_ULP_CLASS_HID_34daf = 0x34daf, + BNXT_ULP_CLASS_HID_3d8af = 0x3d8af, + BNXT_ULP_CLASS_HID_23363 = 0x23363, + BNXT_ULP_CLASS_HID_2be63 = 0x2be63, + BNXT_ULP_CLASS_HID_34963 = 0x34963, + BNXT_ULP_CLASS_HID_3d463 = 0x3d463, + BNXT_ULP_CLASS_HID_24633 = 0x24633, + BNXT_ULP_CLASS_HID_2d133 = 0x2d133, + BNXT_ULP_CLASS_HID_35c33 = 0x35c33, + BNXT_ULP_CLASS_HID_38ac7 = 0x38ac7, + BNXT_ULP_CLASS_HID_211a7 = 0x211a7, + BNXT_ULP_CLASS_HID_29ca7 = 0x29ca7, + BNXT_ULP_CLASS_HID_327a7 = 0x327a7, + BNXT_ULP_CLASS_HID_3b2a7 = 0x3b2a7, + BNXT_ULP_CLASS_HID_25bc3 = 0x25bc3, + BNXT_ULP_CLASS_HID_28997 = 0x28997, + BNXT_ULP_CLASS_HID_31497 = 0x31497, + BNXT_ULP_CLASS_HID_39f97 = 0x39f97, + BNXT_ULP_CLASS_HID_25697 = 0x25697, + BNXT_ULP_CLASS_HID_284ab = 0x284ab, + BNXT_ULP_CLASS_HID_30fab = 0x30fab, + BNXT_ULP_CLASS_HID_39aab = 0x39aab, + BNXT_ULP_CLASS_HID_20d7b = 0x20d7b, + BNXT_ULP_CLASS_HID_2987b = 0x2987b, + BNXT_ULP_CLASS_HID_3237b = 0x3237b, + BNXT_ULP_CLASS_HID_3ae7b = 0x3ae7b, + BNXT_ULP_CLASS_HID_235db = 0x235db, + BNXT_ULP_CLASS_HID_2c0db = 0x2c0db, + BNXT_ULP_CLASS_HID_34bdb = 0x34bdb, + BNXT_ULP_CLASS_HID_3d6db = 0x3d6db, + BNXT_ULP_CLASS_HID_2220b = 0x2220b, + BNXT_ULP_CLASS_HID_2ad0b = 0x2ad0b, + BNXT_ULP_CLASS_HID_3380b = 0x3380b, + BNXT_ULP_CLASS_HID_3c30b = 0x3c30b, + BNXT_ULP_CLASS_HID_21ddf = 0x21ddf, + BNXT_ULP_CLASS_HID_2a8df = 0x2a8df, + BNXT_ULP_CLASS_HID_333df = 0x333df, + BNXT_ULP_CLASS_HID_3bedf = 0x3bedf, + BNXT_ULP_CLASS_HID_230ef = 0x230ef, + BNXT_ULP_CLASS_HID_2bbef = 0x2bbef, + BNXT_ULP_CLASS_HID_346ef = 0x346ef, + BNXT_ULP_CLASS_HID_3d1ef = 0x3d1ef, + BNXT_ULP_CLASS_HID_2594f = 0x2594f, + BNXT_ULP_CLASS_HID_28703 = 0x28703, + BNXT_ULP_CLASS_HID_31203 = 0x31203, + BNXT_ULP_CLASS_HID_39d03 = 0x39d03, + BNXT_ULP_CLASS_HID_245bf = 0x245bf, + BNXT_ULP_CLASS_HID_2d0bf = 0x2d0bf, + BNXT_ULP_CLASS_HID_35bbf = 0x35bbf, + BNXT_ULP_CLASS_HID_38a73 = 0x38a73, + BNXT_ULP_CLASS_HID_24173 = 0x24173, + BNXT_ULP_CLASS_HID_2cc73 = 0x2cc73, + BNXT_ULP_CLASS_HID_35773 = 0x35773, + BNXT_ULP_CLASS_HID_38507 = 0x38507, + BNXT_ULP_CLASS_HID_25403 = 0x25403, + BNXT_ULP_CLASS_HID_282d7 = 0x282d7, + BNXT_ULP_CLASS_HID_30dd7 = 0x30dd7, + BNXT_ULP_CLASS_HID_398d7 = 0x398d7, + BNXT_ULP_CLASS_HID_244a3 = 0x244a3, + BNXT_ULP_CLASS_HID_2cfa3 = 0x2cfa3, + BNXT_ULP_CLASS_HID_35aa3 = 0x35aa3, + BNXT_ULP_CLASS_HID_38977 = 0x38977, + BNXT_ULP_CLASS_HID_23193 = 0x23193, + BNXT_ULP_CLASS_HID_2bc93 = 0x2bc93, + BNXT_ULP_CLASS_HID_34793 = 0x34793, + BNXT_ULP_CLASS_HID_3d293 = 0x3d293, + BNXT_ULP_CLASS_HID_22ca7 = 0x22ca7, + BNXT_ULP_CLASS_HID_2b7a7 = 0x2b7a7, + BNXT_ULP_CLASS_HID_342a7 = 0x342a7, + BNXT_ULP_CLASS_HID_3cda7 = 0x3cda7, + BNXT_ULP_CLASS_HID_24077 = 0x24077, + BNXT_ULP_CLASS_HID_2cb77 = 0x2cb77, + BNXT_ULP_CLASS_HID_35677 = 0x35677, + BNXT_ULP_CLASS_HID_3840b = 0x3840b, + BNXT_ULP_CLASS_HID_20beb = 0x20beb, + BNXT_ULP_CLASS_HID_296eb = 0x296eb, + BNXT_ULP_CLASS_HID_321eb = 0x321eb, + BNXT_ULP_CLASS_HID_3aceb = 0x3aceb, + BNXT_ULP_CLASS_HID_25507 = 0x25507, + BNXT_ULP_CLASS_HID_283db = 0x283db, + BNXT_ULP_CLASS_HID_30edb = 0x30edb, + BNXT_ULP_CLASS_HID_399db = 0x399db, + BNXT_ULP_CLASS_HID_250db = 0x250db, + BNXT_ULP_CLASS_HID_2dbdb = 0x2dbdb, + BNXT_ULP_CLASS_HID_309ef = 0x309ef, + BNXT_ULP_CLASS_HID_394ef = 0x394ef, + BNXT_ULP_CLASS_HID_206bf = 0x206bf, + BNXT_ULP_CLASS_HID_291bf = 0x291bf, + BNXT_ULP_CLASS_HID_31cbf = 0x31cbf, + BNXT_ULP_CLASS_HID_3a7bf = 0x3a7bf, + BNXT_ULP_CLASS_HID_22f1f = 0x22f1f, + BNXT_ULP_CLASS_HID_2ba1f = 0x2ba1f, + BNXT_ULP_CLASS_HID_3451f = 0x3451f, + BNXT_ULP_CLASS_HID_3d01f = 0x3d01f, + BNXT_ULP_CLASS_HID_21c4f = 0x21c4f, + BNXT_ULP_CLASS_HID_2a74f = 0x2a74f, + BNXT_ULP_CLASS_HID_3324f = 0x3324f, + BNXT_ULP_CLASS_HID_3bd4f = 0x3bd4f, + BNXT_ULP_CLASS_HID_21703 = 0x21703, + BNXT_ULP_CLASS_HID_2a203 = 0x2a203, + BNXT_ULP_CLASS_HID_32d03 = 0x32d03, + BNXT_ULP_CLASS_HID_3b803 = 0x3b803, + BNXT_ULP_CLASS_HID_22ad3 = 0x22ad3, + BNXT_ULP_CLASS_HID_2b5d3 = 0x2b5d3, + BNXT_ULP_CLASS_HID_340d3 = 0x340d3, + BNXT_ULP_CLASS_HID_3cbd3 = 0x3cbd3, + BNXT_ULP_CLASS_HID_252b3 = 0x252b3, + BNXT_ULP_CLASS_HID_28147 = 0x28147, + BNXT_ULP_CLASS_HID_30c47 = 0x30c47, + BNXT_ULP_CLASS_HID_39747 = 0x39747, + BNXT_ULP_CLASS_HID_23fe3 = 0x23fe3, + BNXT_ULP_CLASS_HID_2cae3 = 0x2cae3, + BNXT_ULP_CLASS_HID_355e3 = 0x355e3, + BNXT_ULP_CLASS_HID_383b7 = 0x383b7, + BNXT_ULP_CLASS_HID_23ab7 = 0x23ab7, + BNXT_ULP_CLASS_HID_2c5b7 = 0x2c5b7, + BNXT_ULP_CLASS_HID_350b7 = 0x350b7, + BNXT_ULP_CLASS_HID_3dbb7 = 0x3dbb7, + BNXT_ULP_CLASS_HID_24e47 = 0x24e47, + BNXT_ULP_CLASS_HID_2d947 = 0x2d947, + BNXT_ULP_CLASS_HID_3071b = 0x3071b, + BNXT_ULP_CLASS_HID_3921b = 0x3921b, + BNXT_ULP_CLASS_HID_2326f = 0x2326f, + BNXT_ULP_CLASS_HID_2bd6f = 0x2bd6f, + BNXT_ULP_CLASS_HID_3486f = 0x3486f, + BNXT_ULP_CLASS_HID_3d36f = 0x3d36f, + BNXT_ULP_CLASS_HID_21f5f = 0x21f5f, + BNXT_ULP_CLASS_HID_2aa5f = 0x2aa5f, + BNXT_ULP_CLASS_HID_3355f = 0x3355f, + BNXT_ULP_CLASS_HID_3c05f = 0x3c05f, + BNXT_ULP_CLASS_HID_21a13 = 0x21a13, + BNXT_ULP_CLASS_HID_2a513 = 0x2a513, + BNXT_ULP_CLASS_HID_33013 = 0x33013, + BNXT_ULP_CLASS_HID_3bb13 = 0x3bb13, + BNXT_ULP_CLASS_HID_22d23 = 0x22d23, + BNXT_ULP_CLASS_HID_2b823 = 0x2b823, + BNXT_ULP_CLASS_HID_34323 = 0x34323, + BNXT_ULP_CLASS_HID_3ce23 = 0x3ce23, + BNXT_ULP_CLASS_HID_25583 = 0x25583, + BNXT_ULP_CLASS_HID_28457 = 0x28457, + BNXT_ULP_CLASS_HID_30f57 = 0x30f57, + BNXT_ULP_CLASS_HID_39a57 = 0x39a57, + BNXT_ULP_CLASS_HID_242f3 = 0x242f3, + BNXT_ULP_CLASS_HID_2cdf3 = 0x2cdf3, + BNXT_ULP_CLASS_HID_358f3 = 0x358f3, + BNXT_ULP_CLASS_HID_38687 = 0x38687, + BNXT_ULP_CLASS_HID_23d87 = 0x23d87, + BNXT_ULP_CLASS_HID_2c887 = 0x2c887, + BNXT_ULP_CLASS_HID_35387 = 0x35387, + BNXT_ULP_CLASS_HID_3825b = 0x3825b, + BNXT_ULP_CLASS_HID_25157 = 0x25157, + BNXT_ULP_CLASS_HID_2dc57 = 0x2dc57, + BNXT_ULP_CLASS_HID_30a6b = 0x30a6b, + BNXT_ULP_CLASS_HID_3956b = 0x3956b, + BNXT_ULP_CLASS_HID_22c53 = 0x22c53, + BNXT_ULP_CLASS_HID_2b753 = 0x2b753, + BNXT_ULP_CLASS_HID_34253 = 0x34253, + BNXT_ULP_CLASS_HID_3cd53 = 0x3cd53, + BNXT_ULP_CLASS_HID_21883 = 0x21883, + BNXT_ULP_CLASS_HID_2a383 = 0x2a383, + BNXT_ULP_CLASS_HID_32e83 = 0x32e83, + BNXT_ULP_CLASS_HID_3b983 = 0x3b983, + BNXT_ULP_CLASS_HID_21457 = 0x21457, + BNXT_ULP_CLASS_HID_29f57 = 0x29f57, + BNXT_ULP_CLASS_HID_32a57 = 0x32a57, + BNXT_ULP_CLASS_HID_3b557 = 0x3b557, + BNXT_ULP_CLASS_HID_22767 = 0x22767, + BNXT_ULP_CLASS_HID_2b267 = 0x2b267, + BNXT_ULP_CLASS_HID_33d67 = 0x33d67, + BNXT_ULP_CLASS_HID_3c867 = 0x3c867, + BNXT_ULP_CLASS_HID_24fc7 = 0x24fc7, + BNXT_ULP_CLASS_HID_2dac7 = 0x2dac7, + BNXT_ULP_CLASS_HID_3089b = 0x3089b, + BNXT_ULP_CLASS_HID_3939b = 0x3939b, + BNXT_ULP_CLASS_HID_23c37 = 0x23c37, + BNXT_ULP_CLASS_HID_2c737 = 0x2c737, + BNXT_ULP_CLASS_HID_35237 = 0x35237, + BNXT_ULP_CLASS_HID_380cb = 0x380cb, + BNXT_ULP_CLASS_HID_237cb = 0x237cb, + BNXT_ULP_CLASS_HID_2c2cb = 0x2c2cb, + BNXT_ULP_CLASS_HID_34dcb = 0x34dcb, + BNXT_ULP_CLASS_HID_3d8cb = 0x3d8cb, + BNXT_ULP_CLASS_HID_24a9b = 0x24a9b, + BNXT_ULP_CLASS_HID_2d59b = 0x2d59b, + BNXT_ULP_CLASS_HID_303af = 0x303af, + BNXT_ULP_CLASS_HID_38eaf = 0x38eaf, + BNXT_ULP_CLASS_HID_253b = 0x253b, + BNXT_ULP_CLASS_HID_2bf7 = 0x2bf7, + BNXT_ULP_CLASS_HID_4f6b = 0x4f6b, + BNXT_ULP_CLASS_HID_1653 = 0x1653, + BNXT_ULP_CLASS_HID_39c7 = 0x39c7, + BNXT_ULP_CLASS_HID_48af = 0x48af, + BNXT_ULP_CLASS_HID_0f97 = 0x0f97, + BNXT_ULP_CLASS_HID_330b = 0x330b, + BNXT_ULP_CLASS_HID_374e = 0x374e, + BNXT_ULP_CLASS_HID_11ee = 0x11ee, + BNXT_ULP_CLASS_HID_423a = 0x423a, + BNXT_ULP_CLASS_HID_0cd6 = 0x0cd6, + BNXT_ULP_CLASS_HID_310a = 0x310a, + BNXT_ULP_CLASS_HID_469e = 0x469e, + BNXT_ULP_CLASS_HID_5ce6 = 0x5ce6, + BNXT_ULP_CLASS_HID_0692 = 0x0692, + BNXT_ULP_CLASS_HID_1c7e = 0x1c7e, + BNXT_ULP_CLASS_HID_55c2 = 0x55c2, + BNXT_ULP_CLASS_HID_2b2a = 0x2b2a, + BNXT_ULP_CLASS_HID_15c6 = 0x15c6, + BNXT_ULP_CLASS_HID_163a = 0x163a, + BNXT_ULP_CLASS_HID_2f8e = 0x2f8e, + BNXT_ULP_CLASS_HID_2516 = 0x2516, + BNXT_ULP_CLASS_HID_4b76 = 0x4b76, + BNXT_ULP_CLASS_HID_10e6 = 0x10e6, + BNXT_ULP_CLASS_HID_264a = 0x264a, + BNXT_ULP_CLASS_HID_3fd2 = 0x3fd2, + BNXT_ULP_CLASS_HID_4532 = 0x4532, + BNXT_ULP_CLASS_HID_4996 = 0x4996, + BNXT_ULP_CLASS_HID_2036 = 0x2036, + BNXT_ULP_CLASS_HID_399e = 0x399e, + BNXT_ULP_CLASS_HID_5ffe = 0x5ffe, + BNXT_ULP_CLASS_HID_34fe = 0x34fe, + BNXT_ULP_CLASS_HID_3a32 = 0x3a32, + BNXT_ULP_CLASS_HID_376e = 0x376e, + BNXT_ULP_CLASS_HID_12d6e = 0x12d6e, + BNXT_ULP_CLASS_HID_2436e = 0x2436e, + BNXT_ULP_CLASS_HID_31dba = 0x31dba, + BNXT_ULP_CLASS_HID_11ce = 0x11ce, + BNXT_ULP_CLASS_HID_107ce = 0x107ce, + BNXT_ULP_CLASS_HID_23dce = 0x23dce, + BNXT_ULP_CLASS_HID_353ce = 0x353ce, + BNXT_ULP_CLASS_HID_421a = 0x421a, + BNXT_ULP_CLASS_HID_11d56 = 0x11d56, + BNXT_ULP_CLASS_HID_23356 = 0x23356, + BNXT_ULP_CLASS_HID_32956 = 0x32956, + BNXT_ULP_CLASS_HID_0cf6 = 0x0cf6, + BNXT_ULP_CLASS_HID_122f6 = 0x122f6, + BNXT_ULP_CLASS_HID_258f6 = 0x258f6, + BNXT_ULP_CLASS_HID_313c2 = 0x313c2, + BNXT_ULP_CLASS_HID_312a = 0x312a, + BNXT_ULP_CLASS_HID_1272a = 0x1272a, + BNXT_ULP_CLASS_HID_25d2a = 0x25d2a, + BNXT_ULP_CLASS_HID_31466 = 0x31466, + BNXT_ULP_CLASS_HID_46be = 0x46be, + BNXT_ULP_CLASS_HID_1018a = 0x1018a, + BNXT_ULP_CLASS_HID_2378a = 0x2378a, + BNXT_ULP_CLASS_HID_32d8a = 0x32d8a, + BNXT_ULP_CLASS_HID_5cc6 = 0x5cc6, + BNXT_ULP_CLASS_HID_11712 = 0x11712, + BNXT_ULP_CLASS_HID_20d12 = 0x20d12, + BNXT_ULP_CLASS_HID_32312 = 0x32312, + BNXT_ULP_CLASS_HID_06b2 = 0x06b2, + BNXT_ULP_CLASS_HID_13cb2 = 0x13cb2, + BNXT_ULP_CLASS_HID_252b2 = 0x252b2, + BNXT_ULP_CLASS_HID_348b2 = 0x348b2, + BNXT_ULP_CLASS_HID_1c5e = 0x1c5e, + BNXT_ULP_CLASS_HID_1325e = 0x1325e, + BNXT_ULP_CLASS_HID_2285e = 0x2285e, + BNXT_ULP_CLASS_HID_35e5e = 0x35e5e, + BNXT_ULP_CLASS_HID_55e2 = 0x55e2, + BNXT_ULP_CLASS_HID_14be2 = 0x14be2, + BNXT_ULP_CLASS_HID_2023e = 0x2023e, + BNXT_ULP_CLASS_HID_3383e = 0x3383e, + BNXT_ULP_CLASS_HID_2b0a = 0x2b0a, + BNXT_ULP_CLASS_HID_1410a = 0x1410a, + BNXT_ULP_CLASS_HID_21846 = 0x21846, + BNXT_ULP_CLASS_HID_30e46 = 0x30e46, + BNXT_ULP_CLASS_HID_15e6 = 0x15e6, + BNXT_ULP_CLASS_HID_10be6 = 0x10be6, + BNXT_ULP_CLASS_HID_221e6 = 0x221e6, + BNXT_ULP_CLASS_HID_357e6 = 0x357e6, + BNXT_ULP_CLASS_HID_161a = 0x161a, + BNXT_ULP_CLASS_HID_10c1a = 0x10c1a, + BNXT_ULP_CLASS_HID_2221a = 0x2221a, + BNXT_ULP_CLASS_HID_3581a = 0x3581a, + BNXT_ULP_CLASS_HID_2fae = 0x2fae, + BNXT_ULP_CLASS_HID_145ae = 0x145ae, + BNXT_ULP_CLASS_HID_21cfa = 0x21cfa, + BNXT_ULP_CLASS_HID_332fa = 0x332fa, + BNXT_ULP_CLASS_HID_2536 = 0x2536, + BNXT_ULP_CLASS_HID_15b36 = 0x15b36, + BNXT_ULP_CLASS_HID_21202 = 0x21202, + BNXT_ULP_CLASS_HID_30802 = 0x30802, + BNXT_ULP_CLASS_HID_4b56 = 0x4b56, + BNXT_ULP_CLASS_HID_105a2 = 0x105a2, + BNXT_ULP_CLASS_HID_23ba2 = 0x23ba2, + BNXT_ULP_CLASS_HID_351a2 = 0x351a2, + BNXT_ULP_CLASS_HID_10c6 = 0x10c6, + BNXT_ULP_CLASS_HID_106c6 = 0x106c6, + BNXT_ULP_CLASS_HID_23cc6 = 0x23cc6, + BNXT_ULP_CLASS_HID_352c6 = 0x352c6, + BNXT_ULP_CLASS_HID_266a = 0x266a, + BNXT_ULP_CLASS_HID_15c6a = 0x15c6a, + BNXT_ULP_CLASS_HID_216a6 = 0x216a6, + BNXT_ULP_CLASS_HID_30ca6 = 0x30ca6, + BNXT_ULP_CLASS_HID_3ff2 = 0x3ff2, + BNXT_ULP_CLASS_HID_155f2 = 0x155f2, + BNXT_ULP_CLASS_HID_24bf2 = 0x24bf2, + BNXT_ULP_CLASS_HID_302ce = 0x302ce, + BNXT_ULP_CLASS_HID_4512 = 0x4512, + BNXT_ULP_CLASS_HID_11c6e = 0x11c6e, + BNXT_ULP_CLASS_HID_2326e = 0x2326e, + BNXT_ULP_CLASS_HID_3286e = 0x3286e, + BNXT_ULP_CLASS_HID_49b6 = 0x49b6, + BNXT_ULP_CLASS_HID_10082 = 0x10082, + BNXT_ULP_CLASS_HID_23682 = 0x23682, + BNXT_ULP_CLASS_HID_32c82 = 0x32c82, + BNXT_ULP_CLASS_HID_2016 = 0x2016, + BNXT_ULP_CLASS_HID_15616 = 0x15616, + BNXT_ULP_CLASS_HID_21162 = 0x21162, + BNXT_ULP_CLASS_HID_30762 = 0x30762, + BNXT_ULP_CLASS_HID_39be = 0x39be, + BNXT_ULP_CLASS_HID_12fbe = 0x12fbe, + BNXT_ULP_CLASS_HID_245be = 0x245be, + BNXT_ULP_CLASS_HID_31c8a = 0x31c8a, + BNXT_ULP_CLASS_HID_5fde = 0x5fde, + BNXT_ULP_CLASS_HID_1162a = 0x1162a, + BNXT_ULP_CLASS_HID_20c2a = 0x20c2a, + BNXT_ULP_CLASS_HID_3222a = 0x3222a, + BNXT_ULP_CLASS_HID_34de = 0x34de, + BNXT_ULP_CLASS_HID_3a12 = 0x3a12, + BNXT_ULP_CLASS_HID_370e = 0x370e, + BNXT_ULP_CLASS_HID_12d0e = 0x12d0e, + BNXT_ULP_CLASS_HID_2430e = 0x2430e, + BNXT_ULP_CLASS_HID_31dda = 0x31dda, + BNXT_ULP_CLASS_HID_11ae = 0x11ae, + BNXT_ULP_CLASS_HID_107ae = 0x107ae, + BNXT_ULP_CLASS_HID_23dae = 0x23dae, + BNXT_ULP_CLASS_HID_353ae = 0x353ae, + BNXT_ULP_CLASS_HID_427a = 0x427a, + BNXT_ULP_CLASS_HID_11d36 = 0x11d36, + BNXT_ULP_CLASS_HID_23336 = 0x23336, + BNXT_ULP_CLASS_HID_32936 = 0x32936, + BNXT_ULP_CLASS_HID_0c96 = 0x0c96, + BNXT_ULP_CLASS_HID_12296 = 0x12296, + BNXT_ULP_CLASS_HID_25896 = 0x25896, + BNXT_ULP_CLASS_HID_313a2 = 0x313a2, + BNXT_ULP_CLASS_HID_314a = 0x314a, + BNXT_ULP_CLASS_HID_1274a = 0x1274a, + BNXT_ULP_CLASS_HID_25d4a = 0x25d4a, + BNXT_ULP_CLASS_HID_31406 = 0x31406, + BNXT_ULP_CLASS_HID_46de = 0x46de, + BNXT_ULP_CLASS_HID_101ea = 0x101ea, + BNXT_ULP_CLASS_HID_237ea = 0x237ea, + BNXT_ULP_CLASS_HID_32dea = 0x32dea, + BNXT_ULP_CLASS_HID_5ca6 = 0x5ca6, + BNXT_ULP_CLASS_HID_11772 = 0x11772, + BNXT_ULP_CLASS_HID_20d72 = 0x20d72, + BNXT_ULP_CLASS_HID_32372 = 0x32372, + BNXT_ULP_CLASS_HID_06d2 = 0x06d2, + BNXT_ULP_CLASS_HID_13cd2 = 0x13cd2, + BNXT_ULP_CLASS_HID_252d2 = 0x252d2, + BNXT_ULP_CLASS_HID_348d2 = 0x348d2, + BNXT_ULP_CLASS_HID_1c3e = 0x1c3e, + BNXT_ULP_CLASS_HID_1323e = 0x1323e, + BNXT_ULP_CLASS_HID_2283e = 0x2283e, + BNXT_ULP_CLASS_HID_35e3e = 0x35e3e, + BNXT_ULP_CLASS_HID_5582 = 0x5582, + BNXT_ULP_CLASS_HID_14b82 = 0x14b82, + BNXT_ULP_CLASS_HID_2025e = 0x2025e, + BNXT_ULP_CLASS_HID_3385e = 0x3385e, + BNXT_ULP_CLASS_HID_2b6a = 0x2b6a, + BNXT_ULP_CLASS_HID_1416a = 0x1416a, + BNXT_ULP_CLASS_HID_21826 = 0x21826, + BNXT_ULP_CLASS_HID_30e26 = 0x30e26, + BNXT_ULP_CLASS_HID_1586 = 0x1586, + BNXT_ULP_CLASS_HID_10b86 = 0x10b86, + BNXT_ULP_CLASS_HID_22186 = 0x22186, + BNXT_ULP_CLASS_HID_35786 = 0x35786, + BNXT_ULP_CLASS_HID_167a = 0x167a, + BNXT_ULP_CLASS_HID_10c7a = 0x10c7a, + BNXT_ULP_CLASS_HID_2227a = 0x2227a, + BNXT_ULP_CLASS_HID_3587a = 0x3587a, + BNXT_ULP_CLASS_HID_2fce = 0x2fce, + BNXT_ULP_CLASS_HID_145ce = 0x145ce, + BNXT_ULP_CLASS_HID_21c9a = 0x21c9a, + BNXT_ULP_CLASS_HID_3329a = 0x3329a, + BNXT_ULP_CLASS_HID_2556 = 0x2556, + BNXT_ULP_CLASS_HID_15b56 = 0x15b56, + BNXT_ULP_CLASS_HID_21262 = 0x21262, + BNXT_ULP_CLASS_HID_30862 = 0x30862, + BNXT_ULP_CLASS_HID_4b36 = 0x4b36, + BNXT_ULP_CLASS_HID_105c2 = 0x105c2, + BNXT_ULP_CLASS_HID_23bc2 = 0x23bc2, + BNXT_ULP_CLASS_HID_351c2 = 0x351c2, + BNXT_ULP_CLASS_HID_10a6 = 0x10a6, + BNXT_ULP_CLASS_HID_106a6 = 0x106a6, + BNXT_ULP_CLASS_HID_23ca6 = 0x23ca6, + BNXT_ULP_CLASS_HID_352a6 = 0x352a6, + BNXT_ULP_CLASS_HID_260a = 0x260a, + BNXT_ULP_CLASS_HID_15c0a = 0x15c0a, + BNXT_ULP_CLASS_HID_216c6 = 0x216c6, + BNXT_ULP_CLASS_HID_30cc6 = 0x30cc6, + BNXT_ULP_CLASS_HID_3f92 = 0x3f92, + BNXT_ULP_CLASS_HID_15592 = 0x15592, + BNXT_ULP_CLASS_HID_24b92 = 0x24b92, + BNXT_ULP_CLASS_HID_302ae = 0x302ae, + BNXT_ULP_CLASS_HID_4572 = 0x4572, + BNXT_ULP_CLASS_HID_11c0e = 0x11c0e, + BNXT_ULP_CLASS_HID_2320e = 0x2320e, + BNXT_ULP_CLASS_HID_3280e = 0x3280e, + BNXT_ULP_CLASS_HID_49d6 = 0x49d6, + BNXT_ULP_CLASS_HID_100e2 = 0x100e2, + BNXT_ULP_CLASS_HID_236e2 = 0x236e2, + BNXT_ULP_CLASS_HID_32ce2 = 0x32ce2, + BNXT_ULP_CLASS_HID_2076 = 0x2076, + BNXT_ULP_CLASS_HID_15676 = 0x15676, + BNXT_ULP_CLASS_HID_21102 = 0x21102, + BNXT_ULP_CLASS_HID_30702 = 0x30702, + BNXT_ULP_CLASS_HID_39de = 0x39de, + BNXT_ULP_CLASS_HID_12fde = 0x12fde, + BNXT_ULP_CLASS_HID_245de = 0x245de, + BNXT_ULP_CLASS_HID_31cea = 0x31cea, + BNXT_ULP_CLASS_HID_5fbe = 0x5fbe, + BNXT_ULP_CLASS_HID_1164a = 0x1164a, + BNXT_ULP_CLASS_HID_20c4a = 0x20c4a, + BNXT_ULP_CLASS_HID_3224a = 0x3224a, + BNXT_ULP_CLASS_HID_34be = 0x34be, + BNXT_ULP_CLASS_HID_3a72 = 0x3a72, + BNXT_ULP_CLASS_HID_09ea = 0x09ea, + BNXT_ULP_CLASS_HID_2912 = 0x2912, + BNXT_ULP_CLASS_HID_03b2 = 0x03b2, + BNXT_ULP_CLASS_HID_5f7e = 0x5f7e, + BNXT_ULP_CLASS_HID_03a6 = 0x03a6, + BNXT_ULP_CLASS_HID_23ce = 0x23ce, + BNXT_ULP_CLASS_HID_1a6e = 0x1a6e, + BNXT_ULP_CLASS_HID_593a = 0x593a, + BNXT_ULP_CLASS_HID_4dce = 0x4dce, + BNXT_ULP_CLASS_HID_0e02 = 0x0e02, + BNXT_ULP_CLASS_HID_4796 = 0x4796, + BNXT_ULP_CLASS_HID_246e = 0x246e, + BNXT_ULP_CLASS_HID_478a = 0x478a, + BNXT_ULP_CLASS_HID_08fe = 0x08fe, + BNXT_ULP_CLASS_HID_5e52 = 0x5e52, + BNXT_ULP_CLASS_HID_3e2a = 0x3e2a, + BNXT_ULP_CLASS_HID_5e46 = 0x5e46, + BNXT_ULP_CLASS_HID_02ba = 0x02ba, + BNXT_ULP_CLASS_HID_580e = 0x580e, + BNXT_ULP_CLASS_HID_38e6 = 0x38e6, + BNXT_ULP_CLASS_HID_5802 = 0x5802, + BNXT_ULP_CLASS_HID_1d76 = 0x1d76, + BNXT_ULP_CLASS_HID_52ca = 0x52ca, + BNXT_ULP_CLASS_HID_32a2 = 0x32a2, + BNXT_ULP_CLASS_HID_34f6 = 0x34f6, + BNXT_ULP_CLASS_HID_3a3a = 0x3a3a, + BNXT_ULP_CLASS_HID_09ca = 0x09ca, + BNXT_ULP_CLASS_HID_0216 = 0x0216, + BNXT_ULP_CLASS_HID_1f62 = 0x1f62, + BNXT_ULP_CLASS_HID_1bae = 0x1bae, + BNXT_ULP_CLASS_HID_2932 = 0x2932, + BNXT_ULP_CLASS_HID_227e = 0x227e, + BNXT_ULP_CLASS_HID_3f4a = 0x3f4a, + BNXT_ULP_CLASS_HID_3b96 = 0x3b96, + BNXT_ULP_CLASS_HID_0392 = 0x0392, + BNXT_ULP_CLASS_HID_1cde = 0x1cde, + BNXT_ULP_CLASS_HID_192a = 0x192a, + BNXT_ULP_CLASS_HID_1276 = 0x1276, + BNXT_ULP_CLASS_HID_5f5e = 0x5f5e, + BNXT_ULP_CLASS_HID_5baa = 0x5baa, + BNXT_ULP_CLASS_HID_54f6 = 0x54f6, + BNXT_ULP_CLASS_HID_51c2 = 0x51c2, + BNXT_ULP_CLASS_HID_0386 = 0x0386, + BNXT_ULP_CLASS_HID_1cd2 = 0x1cd2, + BNXT_ULP_CLASS_HID_191e = 0x191e, + BNXT_ULP_CLASS_HID_126a = 0x126a, + BNXT_ULP_CLASS_HID_23ee = 0x23ee, + BNXT_ULP_CLASS_HID_3c3a = 0x3c3a, + BNXT_ULP_CLASS_HID_3906 = 0x3906, + BNXT_ULP_CLASS_HID_3252 = 0x3252, + BNXT_ULP_CLASS_HID_1a4e = 0x1a4e, + BNXT_ULP_CLASS_HID_169a = 0x169a, + BNXT_ULP_CLASS_HID_13e6 = 0x13e6, + BNXT_ULP_CLASS_HID_4be6 = 0x4be6, + BNXT_ULP_CLASS_HID_591a = 0x591a, + BNXT_ULP_CLASS_HID_5266 = 0x5266, + BNXT_ULP_CLASS_HID_2eb2 = 0x2eb2, + BNXT_ULP_CLASS_HID_2bfe = 0x2bfe, + BNXT_ULP_CLASS_HID_4dee = 0x4dee, + BNXT_ULP_CLASS_HID_463a = 0x463a, + BNXT_ULP_CLASS_HID_4306 = 0x4306, + BNXT_ULP_CLASS_HID_5c52 = 0x5c52, + BNXT_ULP_CLASS_HID_0e22 = 0x0e22, + BNXT_ULP_CLASS_HID_0b6e = 0x0b6e, + BNXT_ULP_CLASS_HID_07ba = 0x07ba, + BNXT_ULP_CLASS_HID_0086 = 0x0086, + BNXT_ULP_CLASS_HID_47b6 = 0x47b6, + BNXT_ULP_CLASS_HID_4082 = 0x4082, + BNXT_ULP_CLASS_HID_5dce = 0x5dce, + BNXT_ULP_CLASS_HID_561a = 0x561a, + BNXT_ULP_CLASS_HID_244e = 0x244e, + BNXT_ULP_CLASS_HID_209a = 0x209a, + BNXT_ULP_CLASS_HID_3de6 = 0x3de6, + BNXT_ULP_CLASS_HID_3632 = 0x3632, + BNXT_ULP_CLASS_HID_47aa = 0x47aa, + BNXT_ULP_CLASS_HID_40f6 = 0x40f6, + BNXT_ULP_CLASS_HID_5dc2 = 0x5dc2, + BNXT_ULP_CLASS_HID_560e = 0x560e, + BNXT_ULP_CLASS_HID_08de = 0x08de, + BNXT_ULP_CLASS_HID_052a = 0x052a, + BNXT_ULP_CLASS_HID_1e76 = 0x1e76, + BNXT_ULP_CLASS_HID_1b42 = 0x1b42, + BNXT_ULP_CLASS_HID_5e72 = 0x5e72, + BNXT_ULP_CLASS_HID_5abe = 0x5abe, + BNXT_ULP_CLASS_HID_578a = 0x578a, + BNXT_ULP_CLASS_HID_50d6 = 0x50d6, + BNXT_ULP_CLASS_HID_3e0a = 0x3e0a, + BNXT_ULP_CLASS_HID_3b56 = 0x3b56, + BNXT_ULP_CLASS_HID_37a2 = 0x37a2, + BNXT_ULP_CLASS_HID_30ee = 0x30ee, + BNXT_ULP_CLASS_HID_5e66 = 0x5e66, + BNXT_ULP_CLASS_HID_5ab2 = 0x5ab2, + BNXT_ULP_CLASS_HID_57fe = 0x57fe, + BNXT_ULP_CLASS_HID_50ca = 0x50ca, + BNXT_ULP_CLASS_HID_029a = 0x029a, + BNXT_ULP_CLASS_HID_1fe6 = 0x1fe6, + BNXT_ULP_CLASS_HID_1832 = 0x1832, + BNXT_ULP_CLASS_HID_157e = 0x157e, + BNXT_ULP_CLASS_HID_582e = 0x582e, + BNXT_ULP_CLASS_HID_557a = 0x557a, + BNXT_ULP_CLASS_HID_2e46 = 0x2e46, + BNXT_ULP_CLASS_HID_2a92 = 0x2a92, + BNXT_ULP_CLASS_HID_38c6 = 0x38c6, + BNXT_ULP_CLASS_HID_3512 = 0x3512, + BNXT_ULP_CLASS_HID_0e5e = 0x0e5e, + BNXT_ULP_CLASS_HID_0aaa = 0x0aaa, + BNXT_ULP_CLASS_HID_5822 = 0x5822, + BNXT_ULP_CLASS_HID_556e = 0x556e, + BNXT_ULP_CLASS_HID_51ba = 0x51ba, + BNXT_ULP_CLASS_HID_2a86 = 0x2a86, + BNXT_ULP_CLASS_HID_1d56 = 0x1d56, + BNXT_ULP_CLASS_HID_19a2 = 0x19a2, + BNXT_ULP_CLASS_HID_12ee = 0x12ee, + BNXT_ULP_CLASS_HID_4aee = 0x4aee, + BNXT_ULP_CLASS_HID_52ea = 0x52ea, + BNXT_ULP_CLASS_HID_2f36 = 0x2f36, + BNXT_ULP_CLASS_HID_2802 = 0x2802, + BNXT_ULP_CLASS_HID_254e = 0x254e, + BNXT_ULP_CLASS_HID_3282 = 0x3282, + BNXT_ULP_CLASS_HID_0fce = 0x0fce, + BNXT_ULP_CLASS_HID_081a = 0x081a, + BNXT_ULP_CLASS_HID_0566 = 0x0566, + BNXT_ULP_CLASS_HID_34d6 = 0x34d6, + BNXT_ULP_CLASS_HID_3a1a = 0x3a1a, + BNXT_ULP_CLASS_HID_09aa = 0x09aa, + BNXT_ULP_CLASS_HID_0276 = 0x0276, + BNXT_ULP_CLASS_HID_1f02 = 0x1f02, + BNXT_ULP_CLASS_HID_1bce = 0x1bce, + BNXT_ULP_CLASS_HID_2952 = 0x2952, + BNXT_ULP_CLASS_HID_221e = 0x221e, + BNXT_ULP_CLASS_HID_3f2a = 0x3f2a, + BNXT_ULP_CLASS_HID_3bf6 = 0x3bf6, + BNXT_ULP_CLASS_HID_03f2 = 0x03f2, + BNXT_ULP_CLASS_HID_1cbe = 0x1cbe, + BNXT_ULP_CLASS_HID_194a = 0x194a, + BNXT_ULP_CLASS_HID_1216 = 0x1216, + BNXT_ULP_CLASS_HID_5f3e = 0x5f3e, + BNXT_ULP_CLASS_HID_5bca = 0x5bca, + BNXT_ULP_CLASS_HID_5496 = 0x5496, + BNXT_ULP_CLASS_HID_51a2 = 0x51a2, + BNXT_ULP_CLASS_HID_03e6 = 0x03e6, + BNXT_ULP_CLASS_HID_1cb2 = 0x1cb2, + BNXT_ULP_CLASS_HID_197e = 0x197e, + BNXT_ULP_CLASS_HID_120a = 0x120a, + BNXT_ULP_CLASS_HID_238e = 0x238e, + BNXT_ULP_CLASS_HID_3c5a = 0x3c5a, + BNXT_ULP_CLASS_HID_3966 = 0x3966, + BNXT_ULP_CLASS_HID_3232 = 0x3232, + BNXT_ULP_CLASS_HID_1a2e = 0x1a2e, + BNXT_ULP_CLASS_HID_16fa = 0x16fa, + BNXT_ULP_CLASS_HID_1386 = 0x1386, + BNXT_ULP_CLASS_HID_4b86 = 0x4b86, + BNXT_ULP_CLASS_HID_597a = 0x597a, + BNXT_ULP_CLASS_HID_5206 = 0x5206, + BNXT_ULP_CLASS_HID_2ed2 = 0x2ed2, + BNXT_ULP_CLASS_HID_2b9e = 0x2b9e, + BNXT_ULP_CLASS_HID_4d8e = 0x4d8e, + BNXT_ULP_CLASS_HID_465a = 0x465a, + BNXT_ULP_CLASS_HID_4366 = 0x4366, + BNXT_ULP_CLASS_HID_5c32 = 0x5c32, + BNXT_ULP_CLASS_HID_0e42 = 0x0e42, + BNXT_ULP_CLASS_HID_0b0e = 0x0b0e, + BNXT_ULP_CLASS_HID_07da = 0x07da, BNXT_ULP_CLASS_HID_00e6 = 0x00e6, - BNXT_ULP_CLASS_HID_009c = 0x009c, - BNXT_ULP_CLASS_HID_005e = 0x005e, - BNXT_ULP_CLASS_HID_01f4 = 0x01f4, - BNXT_ULP_CLASS_HID_01b6 = 0x01b6 + BNXT_ULP_CLASS_HID_47d6 = 0x47d6, + BNXT_ULP_CLASS_HID_40e2 = 0x40e2, + BNXT_ULP_CLASS_HID_5dae = 0x5dae, + BNXT_ULP_CLASS_HID_567a = 0x567a, + BNXT_ULP_CLASS_HID_242e = 0x242e, + BNXT_ULP_CLASS_HID_20fa = 0x20fa, + BNXT_ULP_CLASS_HID_3d86 = 0x3d86, + BNXT_ULP_CLASS_HID_3652 = 0x3652, + BNXT_ULP_CLASS_HID_47ca = 0x47ca, + BNXT_ULP_CLASS_HID_4096 = 0x4096, + BNXT_ULP_CLASS_HID_5da2 = 0x5da2, + BNXT_ULP_CLASS_HID_566e = 0x566e, + BNXT_ULP_CLASS_HID_08be = 0x08be, + BNXT_ULP_CLASS_HID_054a = 0x054a, + BNXT_ULP_CLASS_HID_1e16 = 0x1e16, + BNXT_ULP_CLASS_HID_1b22 = 0x1b22, + BNXT_ULP_CLASS_HID_5e12 = 0x5e12, + BNXT_ULP_CLASS_HID_5ade = 0x5ade, + BNXT_ULP_CLASS_HID_57ea = 0x57ea, + BNXT_ULP_CLASS_HID_50b6 = 0x50b6, + BNXT_ULP_CLASS_HID_3e6a = 0x3e6a, + BNXT_ULP_CLASS_HID_3b36 = 0x3b36, + BNXT_ULP_CLASS_HID_37c2 = 0x37c2, + BNXT_ULP_CLASS_HID_308e = 0x308e, + BNXT_ULP_CLASS_HID_5e06 = 0x5e06, + BNXT_ULP_CLASS_HID_5ad2 = 0x5ad2, + BNXT_ULP_CLASS_HID_579e = 0x579e, + BNXT_ULP_CLASS_HID_50aa = 0x50aa, + BNXT_ULP_CLASS_HID_02fa = 0x02fa, + BNXT_ULP_CLASS_HID_1f86 = 0x1f86, + BNXT_ULP_CLASS_HID_1852 = 0x1852, + BNXT_ULP_CLASS_HID_151e = 0x151e, + BNXT_ULP_CLASS_HID_584e = 0x584e, + BNXT_ULP_CLASS_HID_551a = 0x551a, + BNXT_ULP_CLASS_HID_2e26 = 0x2e26, + BNXT_ULP_CLASS_HID_2af2 = 0x2af2, + BNXT_ULP_CLASS_HID_38a6 = 0x38a6, + BNXT_ULP_CLASS_HID_3572 = 0x3572, + BNXT_ULP_CLASS_HID_0e3e = 0x0e3e, + BNXT_ULP_CLASS_HID_0aca = 0x0aca, + BNXT_ULP_CLASS_HID_5842 = 0x5842, + BNXT_ULP_CLASS_HID_550e = 0x550e, + BNXT_ULP_CLASS_HID_51da = 0x51da, + BNXT_ULP_CLASS_HID_2ae6 = 0x2ae6, + BNXT_ULP_CLASS_HID_1d36 = 0x1d36, + BNXT_ULP_CLASS_HID_19c2 = 0x19c2, + BNXT_ULP_CLASS_HID_128e = 0x128e, + BNXT_ULP_CLASS_HID_4a8e = 0x4a8e, + BNXT_ULP_CLASS_HID_528a = 0x528a, + BNXT_ULP_CLASS_HID_2f56 = 0x2f56, + BNXT_ULP_CLASS_HID_2862 = 0x2862, + BNXT_ULP_CLASS_HID_252e = 0x252e, + BNXT_ULP_CLASS_HID_32e2 = 0x32e2, + BNXT_ULP_CLASS_HID_0fae = 0x0fae, + BNXT_ULP_CLASS_HID_087a = 0x087a, + BNXT_ULP_CLASS_HID_0506 = 0x0506, + BNXT_ULP_CLASS_HID_34b6 = 0x34b6, + BNXT_ULP_CLASS_HID_3a7a = 0x3a7a, + BNXT_ULP_CLASS_HID_a73c = 0xa73c, + BNXT_ULP_CLASS_HID_a040 = 0xa040, + BNXT_ULP_CLASS_HID_1d640 = 0x1d640, + BNXT_ULP_CLASS_HID_1dd3c = 0x1dd3c, + BNXT_ULP_CLASS_HID_cba0 = 0xcba0, + BNXT_ULP_CLASS_HID_c4f4 = 0xc4f4, + BNXT_ULP_CLASS_HID_19f38 = 0x19f38, + BNXT_ULP_CLASS_HID_182f4 = 0x182f4, + BNXT_ULP_CLASS_HID_b098 = 0xb098, + BNXT_ULP_CLASS_HID_8dac = 0x8dac, + BNXT_ULP_CLASS_HID_1a3ac = 0x1a3ac, + BNXT_ULP_CLASS_HID_1a698 = 0x1a698, + BNXT_ULP_CLASS_HID_d50c = 0xd50c, + BNXT_ULP_CLASS_HID_ae50 = 0xae50, + BNXT_ULP_CLASS_HID_1c450 = 0x1c450, + BNXT_ULP_CLASS_HID_1cb0c = 0x1cb0c, + BNXT_ULP_CLASS_HID_a1f0 = 0xa1f0, + BNXT_ULP_CLASS_HID_ba04 = 0xba04, + BNXT_ULP_CLASS_HID_1d004 = 0x1d004, + BNXT_ULP_CLASS_HID_1d7f0 = 0x1d7f0, + BNXT_ULP_CLASS_HID_c264 = 0xc264, + BNXT_ULP_CLASS_HID_dea8 = 0xdea8, + BNXT_ULP_CLASS_HID_199fc = 0x199fc, + BNXT_ULP_CLASS_HID_19ca8 = 0x19ca8, + BNXT_ULP_CLASS_HID_8b5c = 0x8b5c, + BNXT_ULP_CLASS_HID_8460 = 0x8460, + BNXT_ULP_CLASS_HID_1ba60 = 0x1ba60, + BNXT_ULP_CLASS_HID_1a15c = 0x1a15c, + BNXT_ULP_CLASS_HID_afc0 = 0xafc0, + BNXT_ULP_CLASS_HID_a814 = 0xa814, + BNXT_ULP_CLASS_HID_1de14 = 0x1de14, + BNXT_ULP_CLASS_HID_1c5c0 = 0x1c5c0, + BNXT_ULP_CLASS_HID_8c2c = 0x8c2c, + BNXT_ULP_CLASS_HID_8970 = 0x8970, + BNXT_ULP_CLASS_HID_1bf70 = 0x1bf70, + BNXT_ULP_CLASS_HID_1a22c = 0x1a22c, + BNXT_ULP_CLASS_HID_d0d0 = 0xd0d0, + BNXT_ULP_CLASS_HID_ade4 = 0xade4, + BNXT_ULP_CLASS_HID_1c3e4 = 0x1c3e4, + BNXT_ULP_CLASS_HID_1c6d0 = 0x1c6d0, + BNXT_ULP_CLASS_HID_9988 = 0x9988, + BNXT_ULP_CLASS_HID_92dc = 0x92dc, + BNXT_ULP_CLASS_HID_188dc = 0x188dc, + BNXT_ULP_CLASS_HID_18f88 = 0x18f88, + BNXT_ULP_CLASS_HID_ba3c = 0xba3c, + BNXT_ULP_CLASS_HID_b740 = 0xb740, + BNXT_ULP_CLASS_HID_1ad40 = 0x1ad40, + BNXT_ULP_CLASS_HID_1d03c = 0x1d03c, + BNXT_ULP_CLASS_HID_86e0 = 0x86e0, + BNXT_ULP_CLASS_HID_8334 = 0x8334, + BNXT_ULP_CLASS_HID_1b934 = 0x1b934, + BNXT_ULP_CLASS_HID_1bce0 = 0x1bce0, + BNXT_ULP_CLASS_HID_aa94 = 0xaa94, + BNXT_ULP_CLASS_HID_a7d8 = 0xa7d8, + BNXT_ULP_CLASS_HID_1ddd8 = 0x1ddd8, + BNXT_ULP_CLASS_HID_1c094 = 0x1c094, + BNXT_ULP_CLASS_HID_904c = 0x904c, + BNXT_ULP_CLASS_HID_c84c = 0xc84c, + BNXT_ULP_CLASS_HID_18290 = 0x18290, + BNXT_ULP_CLASS_HID_1864c = 0x1864c, + BNXT_ULP_CLASS_HID_b4f0 = 0xb4f0, + BNXT_ULP_CLASS_HID_b104 = 0xb104, + BNXT_ULP_CLASS_HID_1a704 = 0x1a704, + BNXT_ULP_CLASS_HID_1aaf0 = 0x1aaf0, + BNXT_ULP_CLASS_HID_80a4 = 0x80a4, + BNXT_ULP_CLASS_HID_9de8 = 0x9de8, + BNXT_ULP_CLASS_HID_1b3e8 = 0x1b3e8, + BNXT_ULP_CLASS_HID_1b6a4 = 0x1b6a4, + BNXT_ULP_CLASS_HID_a548 = 0xa548, + BNXT_ULP_CLASS_HID_a19c = 0xa19c, + BNXT_ULP_CLASS_HID_1d79c = 0x1d79c, + BNXT_ULP_CLASS_HID_1db48 = 0x1db48, + BNXT_ULP_CLASS_HID_9a98 = 0x9a98, + BNXT_ULP_CLASS_HID_97ac = 0x97ac, + BNXT_ULP_CLASS_HID_18dac = 0x18dac, + BNXT_ULP_CLASS_HID_1b098 = 0x1b098, + BNXT_ULP_CLASS_HID_bf0c = 0xbf0c, + BNXT_ULP_CLASS_HID_b850 = 0xb850, + BNXT_ULP_CLASS_HID_1ae50 = 0x1ae50, + BNXT_ULP_CLASS_HID_1d50c = 0x1d50c, + BNXT_ULP_CLASS_HID_34f0 = 0x34f0, + BNXT_ULP_CLASS_HID_3a3c = 0x3a3c, + BNXT_ULP_CLASS_HID_5ea0 = 0x5ea0, + BNXT_ULP_CLASS_HID_0798 = 0x0798, + BNXT_ULP_CLASS_HID_280c = 0x280c, + BNXT_ULP_CLASS_HID_5964 = 0x5964, + BNXT_ULP_CLASS_HID_1e5c = 0x1e5c, + BNXT_ULP_CLASS_HID_22c0 = 0x22c0, + BNXT_ULP_CLASS_HID_a71c = 0xa71c, + BNXT_ULP_CLASS_HID_a8dc = 0xa8dc, + BNXT_ULP_CLASS_HID_ed9c = 0xed9c, + BNXT_ULP_CLASS_HID_ef5c = 0xef5c, + BNXT_ULP_CLASS_HID_a060 = 0xa060, + BNXT_ULP_CLASS_HID_a520 = 0xa520, + BNXT_ULP_CLASS_HID_e6e0 = 0xe6e0, + BNXT_ULP_CLASS_HID_eba0 = 0xeba0, + BNXT_ULP_CLASS_HID_1d660 = 0x1d660, + BNXT_ULP_CLASS_HID_1fb20 = 0x1fb20, + BNXT_ULP_CLASS_HID_1dce0 = 0x1dce0, + BNXT_ULP_CLASS_HID_1e1a0 = 0x1e1a0, + BNXT_ULP_CLASS_HID_1dd1c = 0x1dd1c, + BNXT_ULP_CLASS_HID_1fedc = 0x1fedc, + BNXT_ULP_CLASS_HID_1c39c = 0x1c39c, + BNXT_ULP_CLASS_HID_1e55c = 0x1e55c, + BNXT_ULP_CLASS_HID_cb80 = 0xcb80, + BNXT_ULP_CLASS_HID_b194 = 0xb194, + BNXT_ULP_CLASS_HID_d354 = 0xd354, + BNXT_ULP_CLASS_HID_f414 = 0xf414, + BNXT_ULP_CLASS_HID_c4d4 = 0xc4d4, + BNXT_ULP_CLASS_HID_e994 = 0xe994, + BNXT_ULP_CLASS_HID_cb54 = 0xcb54, + BNXT_ULP_CLASS_HID_f158 = 0xf158, + BNXT_ULP_CLASS_HID_19f18 = 0x19f18, + BNXT_ULP_CLASS_HID_1a0d8 = 0x1a0d8, + BNXT_ULP_CLASS_HID_1c598 = 0x1c598, + BNXT_ULP_CLASS_HID_1e758 = 0x1e758, + BNXT_ULP_CLASS_HID_182d4 = 0x182d4, + BNXT_ULP_CLASS_HID_1a794 = 0x1a794, + BNXT_ULP_CLASS_HID_1c954 = 0x1c954, + BNXT_ULP_CLASS_HID_1ea14 = 0x1ea14, + BNXT_ULP_CLASS_HID_b0b8 = 0xb0b8, + BNXT_ULP_CLASS_HID_b278 = 0xb278, + BNXT_ULP_CLASS_HID_f738 = 0xf738, + BNXT_ULP_CLASS_HID_f8f8 = 0xf8f8, + BNXT_ULP_CLASS_HID_8d8c = 0x8d8c, + BNXT_ULP_CLASS_HID_af4c = 0xaf4c, + BNXT_ULP_CLASS_HID_f00c = 0xf00c, + BNXT_ULP_CLASS_HID_f5cc = 0xf5cc, + BNXT_ULP_CLASS_HID_1a38c = 0x1a38c, + BNXT_ULP_CLASS_HID_1a54c = 0x1a54c, + BNXT_ULP_CLASS_HID_1e60c = 0x1e60c, + BNXT_ULP_CLASS_HID_1ebcc = 0x1ebcc, + BNXT_ULP_CLASS_HID_1a6b8 = 0x1a6b8, + BNXT_ULP_CLASS_HID_1a878 = 0x1a878, + BNXT_ULP_CLASS_HID_1ed38 = 0x1ed38, + BNXT_ULP_CLASS_HID_1eef8 = 0x1eef8, + BNXT_ULP_CLASS_HID_d52c = 0xd52c, + BNXT_ULP_CLASS_HID_f6ec = 0xf6ec, + BNXT_ULP_CLASS_HID_dbac = 0xdbac, + BNXT_ULP_CLASS_HID_fd6c = 0xfd6c, + BNXT_ULP_CLASS_HID_ae70 = 0xae70, + BNXT_ULP_CLASS_HID_f330 = 0xf330, + BNXT_ULP_CLASS_HID_d4f0 = 0xd4f0, + BNXT_ULP_CLASS_HID_f9b0 = 0xf9b0, + BNXT_ULP_CLASS_HID_1c470 = 0x1c470, + BNXT_ULP_CLASS_HID_1e930 = 0x1e930, + BNXT_ULP_CLASS_HID_1caf0 = 0x1caf0, + BNXT_ULP_CLASS_HID_1f084 = 0x1f084, + BNXT_ULP_CLASS_HID_1cb2c = 0x1cb2c, + BNXT_ULP_CLASS_HID_1b130 = 0x1b130, + BNXT_ULP_CLASS_HID_1d2f0 = 0x1d2f0, + BNXT_ULP_CLASS_HID_1f7b0 = 0x1f7b0, + BNXT_ULP_CLASS_HID_a1d0 = 0xa1d0, + BNXT_ULP_CLASS_HID_a290 = 0xa290, + BNXT_ULP_CLASS_HID_e450 = 0xe450, + BNXT_ULP_CLASS_HID_e910 = 0xe910, + BNXT_ULP_CLASS_HID_ba24 = 0xba24, + BNXT_ULP_CLASS_HID_bfe4 = 0xbfe4, + BNXT_ULP_CLASS_HID_e0a4 = 0xe0a4, + BNXT_ULP_CLASS_HID_e264 = 0xe264, + BNXT_ULP_CLASS_HID_1d024 = 0x1d024, + BNXT_ULP_CLASS_HID_1f5e4 = 0x1f5e4, + BNXT_ULP_CLASS_HID_1d6a4 = 0x1d6a4, + BNXT_ULP_CLASS_HID_1f864 = 0x1f864, + BNXT_ULP_CLASS_HID_1d7d0 = 0x1d7d0, + BNXT_ULP_CLASS_HID_1f890 = 0x1f890, + BNXT_ULP_CLASS_HID_1da50 = 0x1da50, + BNXT_ULP_CLASS_HID_1ff10 = 0x1ff10, + BNXT_ULP_CLASS_HID_c244 = 0xc244, + BNXT_ULP_CLASS_HID_e704 = 0xe704, + BNXT_ULP_CLASS_HID_c8c4 = 0xc8c4, + BNXT_ULP_CLASS_HID_ed84 = 0xed84, + BNXT_ULP_CLASS_HID_de88 = 0xde88, + BNXT_ULP_CLASS_HID_e048 = 0xe048, + BNXT_ULP_CLASS_HID_c508 = 0xc508, + BNXT_ULP_CLASS_HID_e6c8 = 0xe6c8, + BNXT_ULP_CLASS_HID_199dc = 0x199dc, + BNXT_ULP_CLASS_HID_1ba9c = 0x1ba9c, + BNXT_ULP_CLASS_HID_1dc5c = 0x1dc5c, + BNXT_ULP_CLASS_HID_1e11c = 0x1e11c, + BNXT_ULP_CLASS_HID_19c88 = 0x19c88, + BNXT_ULP_CLASS_HID_1be48 = 0x1be48, + BNXT_ULP_CLASS_HID_1c308 = 0x1c308, + BNXT_ULP_CLASS_HID_1e4c8 = 0x1e4c8, + BNXT_ULP_CLASS_HID_8b7c = 0x8b7c, + BNXT_ULP_CLASS_HID_ac3c = 0xac3c, + BNXT_ULP_CLASS_HID_f1fc = 0xf1fc, + BNXT_ULP_CLASS_HID_f2bc = 0xf2bc, + BNXT_ULP_CLASS_HID_8440 = 0x8440, + BNXT_ULP_CLASS_HID_a900 = 0xa900, + BNXT_ULP_CLASS_HID_cac0 = 0xcac0, + BNXT_ULP_CLASS_HID_ef80 = 0xef80, + BNXT_ULP_CLASS_HID_1ba40 = 0x1ba40, + BNXT_ULP_CLASS_HID_1bf00 = 0x1bf00, + BNXT_ULP_CLASS_HID_1e0c0 = 0x1e0c0, + BNXT_ULP_CLASS_HID_1e580 = 0x1e580, + BNXT_ULP_CLASS_HID_1a17c = 0x1a17c, + BNXT_ULP_CLASS_HID_1a23c = 0x1a23c, + BNXT_ULP_CLASS_HID_1e7fc = 0x1e7fc, + BNXT_ULP_CLASS_HID_1e8bc = 0x1e8bc, + BNXT_ULP_CLASS_HID_afe0 = 0xafe0, + BNXT_ULP_CLASS_HID_f0a0 = 0xf0a0, + BNXT_ULP_CLASS_HID_d260 = 0xd260, + BNXT_ULP_CLASS_HID_f720 = 0xf720, + BNXT_ULP_CLASS_HID_a834 = 0xa834, + BNXT_ULP_CLASS_HID_adf4 = 0xadf4, + BNXT_ULP_CLASS_HID_eeb4 = 0xeeb4, + BNXT_ULP_CLASS_HID_f074 = 0xf074, + BNXT_ULP_CLASS_HID_1de34 = 0x1de34, + BNXT_ULP_CLASS_HID_1e3f4 = 0x1e3f4, + BNXT_ULP_CLASS_HID_1c4b4 = 0x1c4b4, + BNXT_ULP_CLASS_HID_1e674 = 0x1e674, + BNXT_ULP_CLASS_HID_1c5e0 = 0x1c5e0, + BNXT_ULP_CLASS_HID_1e6a0 = 0x1e6a0, + BNXT_ULP_CLASS_HID_1c860 = 0x1c860, + BNXT_ULP_CLASS_HID_1ed20 = 0x1ed20, + BNXT_ULP_CLASS_HID_8c0c = 0x8c0c, + BNXT_ULP_CLASS_HID_b1cc = 0xb1cc, + BNXT_ULP_CLASS_HID_f28c = 0xf28c, + BNXT_ULP_CLASS_HID_f44c = 0xf44c, + BNXT_ULP_CLASS_HID_8950 = 0x8950, + BNXT_ULP_CLASS_HID_aa10 = 0xaa10, + BNXT_ULP_CLASS_HID_cfd0 = 0xcfd0, + BNXT_ULP_CLASS_HID_f090 = 0xf090, + BNXT_ULP_CLASS_HID_1bf50 = 0x1bf50, + BNXT_ULP_CLASS_HID_1a010 = 0x1a010, + BNXT_ULP_CLASS_HID_1e5d0 = 0x1e5d0, + BNXT_ULP_CLASS_HID_1e690 = 0x1e690, + BNXT_ULP_CLASS_HID_1a20c = 0x1a20c, + BNXT_ULP_CLASS_HID_1a7cc = 0x1a7cc, + BNXT_ULP_CLASS_HID_1e88c = 0x1e88c, + BNXT_ULP_CLASS_HID_1ea4c = 0x1ea4c, + BNXT_ULP_CLASS_HID_d0f0 = 0xd0f0, + BNXT_ULP_CLASS_HID_f5b0 = 0xf5b0, + BNXT_ULP_CLASS_HID_d770 = 0xd770, + BNXT_ULP_CLASS_HID_f830 = 0xf830, + BNXT_ULP_CLASS_HID_adc4 = 0xadc4, + BNXT_ULP_CLASS_HID_ae84 = 0xae84, + BNXT_ULP_CLASS_HID_d044 = 0xd044, + BNXT_ULP_CLASS_HID_f504 = 0xf504, + BNXT_ULP_CLASS_HID_1c3c4 = 0x1c3c4, + BNXT_ULP_CLASS_HID_1e484 = 0x1e484, + BNXT_ULP_CLASS_HID_1c644 = 0x1c644, + BNXT_ULP_CLASS_HID_1eb04 = 0x1eb04, + BNXT_ULP_CLASS_HID_1c6f0 = 0x1c6f0, + BNXT_ULP_CLASS_HID_1ebb0 = 0x1ebb0, + BNXT_ULP_CLASS_HID_1cd70 = 0x1cd70, + BNXT_ULP_CLASS_HID_1f304 = 0x1f304, + BNXT_ULP_CLASS_HID_99a8 = 0x99a8, + BNXT_ULP_CLASS_HID_bb68 = 0xbb68, + BNXT_ULP_CLASS_HID_dc28 = 0xdc28, + BNXT_ULP_CLASS_HID_e1e8 = 0xe1e8, + BNXT_ULP_CLASS_HID_92fc = 0x92fc, + BNXT_ULP_CLASS_HID_b7bc = 0xb7bc, + BNXT_ULP_CLASS_HID_d97c = 0xd97c, + BNXT_ULP_CLASS_HID_fa3c = 0xfa3c, + BNXT_ULP_CLASS_HID_188fc = 0x188fc, + BNXT_ULP_CLASS_HID_1adbc = 0x1adbc, + BNXT_ULP_CLASS_HID_1cf7c = 0x1cf7c, + BNXT_ULP_CLASS_HID_1f03c = 0x1f03c, + BNXT_ULP_CLASS_HID_18fa8 = 0x18fa8, + BNXT_ULP_CLASS_HID_1b168 = 0x1b168, + BNXT_ULP_CLASS_HID_1f228 = 0x1f228, + BNXT_ULP_CLASS_HID_1f7e8 = 0x1f7e8, + BNXT_ULP_CLASS_HID_ba1c = 0xba1c, + BNXT_ULP_CLASS_HID_bfdc = 0xbfdc, + BNXT_ULP_CLASS_HID_e09c = 0xe09c, + BNXT_ULP_CLASS_HID_e25c = 0xe25c, + BNXT_ULP_CLASS_HID_b760 = 0xb760, + BNXT_ULP_CLASS_HID_b820 = 0xb820, + BNXT_ULP_CLASS_HID_fde0 = 0xfde0, + BNXT_ULP_CLASS_HID_fea0 = 0xfea0, + BNXT_ULP_CLASS_HID_1ad60 = 0x1ad60, + BNXT_ULP_CLASS_HID_1ae20 = 0x1ae20, + BNXT_ULP_CLASS_HID_1d3e0 = 0x1d3e0, + BNXT_ULP_CLASS_HID_1f4a0 = 0x1f4a0, + BNXT_ULP_CLASS_HID_1d01c = 0x1d01c, + BNXT_ULP_CLASS_HID_1f5dc = 0x1f5dc, + BNXT_ULP_CLASS_HID_1d69c = 0x1d69c, + BNXT_ULP_CLASS_HID_1f85c = 0x1f85c, + BNXT_ULP_CLASS_HID_86c0 = 0x86c0, + BNXT_ULP_CLASS_HID_ab80 = 0xab80, + BNXT_ULP_CLASS_HID_cd40 = 0xcd40, + BNXT_ULP_CLASS_HID_ee00 = 0xee00, + BNXT_ULP_CLASS_HID_8314 = 0x8314, + BNXT_ULP_CLASS_HID_a4d4 = 0xa4d4, + BNXT_ULP_CLASS_HID_c994 = 0xc994, + BNXT_ULP_CLASS_HID_eb54 = 0xeb54, + BNXT_ULP_CLASS_HID_1b914 = 0x1b914, + BNXT_ULP_CLASS_HID_1bad4 = 0x1bad4, + BNXT_ULP_CLASS_HID_1ff94 = 0x1ff94, + BNXT_ULP_CLASS_HID_1e154 = 0x1e154, + BNXT_ULP_CLASS_HID_1bcc0 = 0x1bcc0, + BNXT_ULP_CLASS_HID_1a180 = 0x1a180, + BNXT_ULP_CLASS_HID_1e340 = 0x1e340, + BNXT_ULP_CLASS_HID_1e400 = 0x1e400, + BNXT_ULP_CLASS_HID_aab4 = 0xaab4, + BNXT_ULP_CLASS_HID_ac74 = 0xac74, + BNXT_ULP_CLASS_HID_d134 = 0xd134, + BNXT_ULP_CLASS_HID_f2f4 = 0xf2f4, + BNXT_ULP_CLASS_HID_a7f8 = 0xa7f8, + BNXT_ULP_CLASS_HID_a8b8 = 0xa8b8, + BNXT_ULP_CLASS_HID_ea78 = 0xea78, + BNXT_ULP_CLASS_HID_ef38 = 0xef38, + BNXT_ULP_CLASS_HID_1ddf8 = 0x1ddf8, + BNXT_ULP_CLASS_HID_1feb8 = 0x1feb8, + BNXT_ULP_CLASS_HID_1c078 = 0x1c078, + BNXT_ULP_CLASS_HID_1e538 = 0x1e538, + BNXT_ULP_CLASS_HID_1c0b4 = 0x1c0b4, + BNXT_ULP_CLASS_HID_1e274 = 0x1e274, + BNXT_ULP_CLASS_HID_1c734 = 0x1c734, + BNXT_ULP_CLASS_HID_1e8f4 = 0x1e8f4, + BNXT_ULP_CLASS_HID_906c = 0x906c, + BNXT_ULP_CLASS_HID_b52c = 0xb52c, + BNXT_ULP_CLASS_HID_d6ec = 0xd6ec, + BNXT_ULP_CLASS_HID_fbac = 0xfbac, + BNXT_ULP_CLASS_HID_c86c = 0xc86c, + BNXT_ULP_CLASS_HID_ed2c = 0xed2c, + BNXT_ULP_CLASS_HID_d330 = 0xd330, + BNXT_ULP_CLASS_HID_f4f0 = 0xf4f0, + BNXT_ULP_CLASS_HID_182b0 = 0x182b0, + BNXT_ULP_CLASS_HID_1a470 = 0x1a470, + BNXT_ULP_CLASS_HID_1c930 = 0x1c930, + BNXT_ULP_CLASS_HID_1eaf0 = 0x1eaf0, + BNXT_ULP_CLASS_HID_1866c = 0x1866c, + BNXT_ULP_CLASS_HID_1ab2c = 0x1ab2c, + BNXT_ULP_CLASS_HID_1ccec = 0x1ccec, + BNXT_ULP_CLASS_HID_1f1ac = 0x1f1ac, + BNXT_ULP_CLASS_HID_b4d0 = 0xb4d0, + BNXT_ULP_CLASS_HID_b990 = 0xb990, + BNXT_ULP_CLASS_HID_fb50 = 0xfb50, + BNXT_ULP_CLASS_HID_fc10 = 0xfc10, + BNXT_ULP_CLASS_HID_b124 = 0xb124, + BNXT_ULP_CLASS_HID_b2e4 = 0xb2e4, + BNXT_ULP_CLASS_HID_f7a4 = 0xf7a4, + BNXT_ULP_CLASS_HID_f964 = 0xf964, + BNXT_ULP_CLASS_HID_1a724 = 0x1a724, + BNXT_ULP_CLASS_HID_1a8e4 = 0x1a8e4, + BNXT_ULP_CLASS_HID_1eda4 = 0x1eda4, + BNXT_ULP_CLASS_HID_1ef64 = 0x1ef64, + BNXT_ULP_CLASS_HID_1aad0 = 0x1aad0, + BNXT_ULP_CLASS_HID_1af90 = 0x1af90, + BNXT_ULP_CLASS_HID_1d150 = 0x1d150, + BNXT_ULP_CLASS_HID_1f210 = 0x1f210, + BNXT_ULP_CLASS_HID_8084 = 0x8084, + BNXT_ULP_CLASS_HID_a244 = 0xa244, + BNXT_ULP_CLASS_HID_c704 = 0xc704, + BNXT_ULP_CLASS_HID_e8c4 = 0xe8c4, + BNXT_ULP_CLASS_HID_9dc8 = 0x9dc8, + BNXT_ULP_CLASS_HID_be88 = 0xbe88, + BNXT_ULP_CLASS_HID_c048 = 0xc048, + BNXT_ULP_CLASS_HID_e508 = 0xe508, + BNXT_ULP_CLASS_HID_1b3c8 = 0x1b3c8, + BNXT_ULP_CLASS_HID_1b488 = 0x1b488, + BNXT_ULP_CLASS_HID_1f648 = 0x1f648, + BNXT_ULP_CLASS_HID_1fb08 = 0x1fb08, + BNXT_ULP_CLASS_HID_1b684 = 0x1b684, + BNXT_ULP_CLASS_HID_1b844 = 0x1b844, + BNXT_ULP_CLASS_HID_1fd04 = 0x1fd04, + BNXT_ULP_CLASS_HID_1fec4 = 0x1fec4, + BNXT_ULP_CLASS_HID_a568 = 0xa568, + BNXT_ULP_CLASS_HID_a628 = 0xa628, + BNXT_ULP_CLASS_HID_ebe8 = 0xebe8, + BNXT_ULP_CLASS_HID_eca8 = 0xeca8, + BNXT_ULP_CLASS_HID_a1bc = 0xa1bc, + BNXT_ULP_CLASS_HID_a37c = 0xa37c, + BNXT_ULP_CLASS_HID_e43c = 0xe43c, + BNXT_ULP_CLASS_HID_e9fc = 0xe9fc, + BNXT_ULP_CLASS_HID_1d7bc = 0x1d7bc, + BNXT_ULP_CLASS_HID_1f97c = 0x1f97c, + BNXT_ULP_CLASS_HID_1da3c = 0x1da3c, + BNXT_ULP_CLASS_HID_1fffc = 0x1fffc, + BNXT_ULP_CLASS_HID_1db68 = 0x1db68, + BNXT_ULP_CLASS_HID_1fc28 = 0x1fc28, + BNXT_ULP_CLASS_HID_1c1e8 = 0x1c1e8, + BNXT_ULP_CLASS_HID_1e2a8 = 0x1e2a8, + BNXT_ULP_CLASS_HID_9ab8 = 0x9ab8, + BNXT_ULP_CLASS_HID_bc78 = 0xbc78, + BNXT_ULP_CLASS_HID_c138 = 0xc138, + BNXT_ULP_CLASS_HID_e2f8 = 0xe2f8, + BNXT_ULP_CLASS_HID_978c = 0x978c, + BNXT_ULP_CLASS_HID_b94c = 0xb94c, + BNXT_ULP_CLASS_HID_da0c = 0xda0c, + BNXT_ULP_CLASS_HID_ffcc = 0xffcc, + BNXT_ULP_CLASS_HID_18d8c = 0x18d8c, + BNXT_ULP_CLASS_HID_1af4c = 0x1af4c, + BNXT_ULP_CLASS_HID_1f00c = 0x1f00c, + BNXT_ULP_CLASS_HID_1f5cc = 0x1f5cc, + BNXT_ULP_CLASS_HID_1b0b8 = 0x1b0b8, + BNXT_ULP_CLASS_HID_1b278 = 0x1b278, + BNXT_ULP_CLASS_HID_1f738 = 0x1f738, + BNXT_ULP_CLASS_HID_1f8f8 = 0x1f8f8, + BNXT_ULP_CLASS_HID_bf2c = 0xbf2c, + BNXT_ULP_CLASS_HID_a0ec = 0xa0ec, + BNXT_ULP_CLASS_HID_e5ac = 0xe5ac, + BNXT_ULP_CLASS_HID_e76c = 0xe76c, + BNXT_ULP_CLASS_HID_b870 = 0xb870, + BNXT_ULP_CLASS_HID_bd30 = 0xbd30, + BNXT_ULP_CLASS_HID_fef0 = 0xfef0, + BNXT_ULP_CLASS_HID_e3b0 = 0xe3b0, + BNXT_ULP_CLASS_HID_1ae70 = 0x1ae70, + BNXT_ULP_CLASS_HID_1f330 = 0x1f330, + BNXT_ULP_CLASS_HID_1d4f0 = 0x1d4f0, + BNXT_ULP_CLASS_HID_1f9b0 = 0x1f9b0, + BNXT_ULP_CLASS_HID_1d52c = 0x1d52c, + BNXT_ULP_CLASS_HID_1f6ec = 0x1f6ec, + BNXT_ULP_CLASS_HID_1dbac = 0x1dbac, + BNXT_ULP_CLASS_HID_1fd6c = 0x1fd6c, + BNXT_ULP_CLASS_HID_34d0 = 0x34d0, + BNXT_ULP_CLASS_HID_3a1c = 0x3a1c, + BNXT_ULP_CLASS_HID_5e80 = 0x5e80, + BNXT_ULP_CLASS_HID_07b8 = 0x07b8, + BNXT_ULP_CLASS_HID_282c = 0x282c, + BNXT_ULP_CLASS_HID_5944 = 0x5944, + BNXT_ULP_CLASS_HID_1e7c = 0x1e7c, + BNXT_ULP_CLASS_HID_22e0 = 0x22e0, + BNXT_ULP_CLASS_HID_a77c = 0xa77c, + BNXT_ULP_CLASS_HID_a8bc = 0xa8bc, + BNXT_ULP_CLASS_HID_edfc = 0xedfc, + BNXT_ULP_CLASS_HID_ef3c = 0xef3c, + BNXT_ULP_CLASS_HID_a000 = 0xa000, + BNXT_ULP_CLASS_HID_a540 = 0xa540, + BNXT_ULP_CLASS_HID_e680 = 0xe680, + BNXT_ULP_CLASS_HID_ebc0 = 0xebc0, + BNXT_ULP_CLASS_HID_1d600 = 0x1d600, + BNXT_ULP_CLASS_HID_1fb40 = 0x1fb40, + BNXT_ULP_CLASS_HID_1dc80 = 0x1dc80, + BNXT_ULP_CLASS_HID_1e1c0 = 0x1e1c0, + BNXT_ULP_CLASS_HID_1dd7c = 0x1dd7c, + BNXT_ULP_CLASS_HID_1febc = 0x1febc, + BNXT_ULP_CLASS_HID_1c3fc = 0x1c3fc, + BNXT_ULP_CLASS_HID_1e53c = 0x1e53c, + BNXT_ULP_CLASS_HID_cbe0 = 0xcbe0, + BNXT_ULP_CLASS_HID_b1f4 = 0xb1f4, + BNXT_ULP_CLASS_HID_d334 = 0xd334, + BNXT_ULP_CLASS_HID_f474 = 0xf474, + BNXT_ULP_CLASS_HID_c4b4 = 0xc4b4, + BNXT_ULP_CLASS_HID_e9f4 = 0xe9f4, + BNXT_ULP_CLASS_HID_cb34 = 0xcb34, + BNXT_ULP_CLASS_HID_f138 = 0xf138, + BNXT_ULP_CLASS_HID_19f78 = 0x19f78, + BNXT_ULP_CLASS_HID_1a0b8 = 0x1a0b8, + BNXT_ULP_CLASS_HID_1c5f8 = 0x1c5f8, + BNXT_ULP_CLASS_HID_1e738 = 0x1e738, + BNXT_ULP_CLASS_HID_182b4 = 0x182b4, + BNXT_ULP_CLASS_HID_1a7f4 = 0x1a7f4, + BNXT_ULP_CLASS_HID_1c934 = 0x1c934, + BNXT_ULP_CLASS_HID_1ea74 = 0x1ea74, + BNXT_ULP_CLASS_HID_b0d8 = 0xb0d8, + BNXT_ULP_CLASS_HID_b218 = 0xb218, + BNXT_ULP_CLASS_HID_f758 = 0xf758, + BNXT_ULP_CLASS_HID_f898 = 0xf898, + BNXT_ULP_CLASS_HID_8dec = 0x8dec, + BNXT_ULP_CLASS_HID_af2c = 0xaf2c, + BNXT_ULP_CLASS_HID_f06c = 0xf06c, + BNXT_ULP_CLASS_HID_f5ac = 0xf5ac, + BNXT_ULP_CLASS_HID_1a3ec = 0x1a3ec, + BNXT_ULP_CLASS_HID_1a52c = 0x1a52c, + BNXT_ULP_CLASS_HID_1e66c = 0x1e66c, + BNXT_ULP_CLASS_HID_1ebac = 0x1ebac, + BNXT_ULP_CLASS_HID_1a6d8 = 0x1a6d8, + BNXT_ULP_CLASS_HID_1a818 = 0x1a818, + BNXT_ULP_CLASS_HID_1ed58 = 0x1ed58, + BNXT_ULP_CLASS_HID_1ee98 = 0x1ee98, + BNXT_ULP_CLASS_HID_d54c = 0xd54c, + BNXT_ULP_CLASS_HID_f68c = 0xf68c, + BNXT_ULP_CLASS_HID_dbcc = 0xdbcc, + BNXT_ULP_CLASS_HID_fd0c = 0xfd0c, + BNXT_ULP_CLASS_HID_ae10 = 0xae10, + BNXT_ULP_CLASS_HID_f350 = 0xf350, + BNXT_ULP_CLASS_HID_d490 = 0xd490, + BNXT_ULP_CLASS_HID_f9d0 = 0xf9d0, + BNXT_ULP_CLASS_HID_1c410 = 0x1c410, + BNXT_ULP_CLASS_HID_1e950 = 0x1e950, + BNXT_ULP_CLASS_HID_1ca90 = 0x1ca90, + BNXT_ULP_CLASS_HID_1f0e4 = 0x1f0e4, + BNXT_ULP_CLASS_HID_1cb4c = 0x1cb4c, + BNXT_ULP_CLASS_HID_1b150 = 0x1b150, + BNXT_ULP_CLASS_HID_1d290 = 0x1d290, + BNXT_ULP_CLASS_HID_1f7d0 = 0x1f7d0, + BNXT_ULP_CLASS_HID_a1b0 = 0xa1b0, + BNXT_ULP_CLASS_HID_a2f0 = 0xa2f0, + BNXT_ULP_CLASS_HID_e430 = 0xe430, + BNXT_ULP_CLASS_HID_e970 = 0xe970, + BNXT_ULP_CLASS_HID_ba44 = 0xba44, + BNXT_ULP_CLASS_HID_bf84 = 0xbf84, + BNXT_ULP_CLASS_HID_e0c4 = 0xe0c4, + BNXT_ULP_CLASS_HID_e204 = 0xe204, + BNXT_ULP_CLASS_HID_1d044 = 0x1d044, + BNXT_ULP_CLASS_HID_1f584 = 0x1f584, + BNXT_ULP_CLASS_HID_1d6c4 = 0x1d6c4, + BNXT_ULP_CLASS_HID_1f804 = 0x1f804, + BNXT_ULP_CLASS_HID_1d7b0 = 0x1d7b0, + BNXT_ULP_CLASS_HID_1f8f0 = 0x1f8f0, + BNXT_ULP_CLASS_HID_1da30 = 0x1da30, + BNXT_ULP_CLASS_HID_1ff70 = 0x1ff70, + BNXT_ULP_CLASS_HID_c224 = 0xc224, + BNXT_ULP_CLASS_HID_e764 = 0xe764, + BNXT_ULP_CLASS_HID_c8a4 = 0xc8a4, + BNXT_ULP_CLASS_HID_ede4 = 0xede4, + BNXT_ULP_CLASS_HID_dee8 = 0xdee8, + BNXT_ULP_CLASS_HID_e028 = 0xe028, + BNXT_ULP_CLASS_HID_c568 = 0xc568, + BNXT_ULP_CLASS_HID_e6a8 = 0xe6a8, + BNXT_ULP_CLASS_HID_199bc = 0x199bc, + BNXT_ULP_CLASS_HID_1bafc = 0x1bafc, + BNXT_ULP_CLASS_HID_1dc3c = 0x1dc3c, + BNXT_ULP_CLASS_HID_1e17c = 0x1e17c, + BNXT_ULP_CLASS_HID_19ce8 = 0x19ce8, + BNXT_ULP_CLASS_HID_1be28 = 0x1be28, + BNXT_ULP_CLASS_HID_1c368 = 0x1c368, + BNXT_ULP_CLASS_HID_1e4a8 = 0x1e4a8, + BNXT_ULP_CLASS_HID_8b1c = 0x8b1c, + BNXT_ULP_CLASS_HID_ac5c = 0xac5c, + BNXT_ULP_CLASS_HID_f19c = 0xf19c, + BNXT_ULP_CLASS_HID_f2dc = 0xf2dc, + BNXT_ULP_CLASS_HID_8420 = 0x8420, + BNXT_ULP_CLASS_HID_a960 = 0xa960, + BNXT_ULP_CLASS_HID_caa0 = 0xcaa0, + BNXT_ULP_CLASS_HID_efe0 = 0xefe0, + BNXT_ULP_CLASS_HID_1ba20 = 0x1ba20, + BNXT_ULP_CLASS_HID_1bf60 = 0x1bf60, + BNXT_ULP_CLASS_HID_1e0a0 = 0x1e0a0, + BNXT_ULP_CLASS_HID_1e5e0 = 0x1e5e0, + BNXT_ULP_CLASS_HID_1a11c = 0x1a11c, + BNXT_ULP_CLASS_HID_1a25c = 0x1a25c, + BNXT_ULP_CLASS_HID_1e79c = 0x1e79c, + BNXT_ULP_CLASS_HID_1e8dc = 0x1e8dc, + BNXT_ULP_CLASS_HID_af80 = 0xaf80, + BNXT_ULP_CLASS_HID_f0c0 = 0xf0c0, + BNXT_ULP_CLASS_HID_d200 = 0xd200, + BNXT_ULP_CLASS_HID_f740 = 0xf740, + BNXT_ULP_CLASS_HID_a854 = 0xa854, + BNXT_ULP_CLASS_HID_ad94 = 0xad94, + BNXT_ULP_CLASS_HID_eed4 = 0xeed4, + BNXT_ULP_CLASS_HID_f014 = 0xf014, + BNXT_ULP_CLASS_HID_1de54 = 0x1de54, + BNXT_ULP_CLASS_HID_1e394 = 0x1e394, + BNXT_ULP_CLASS_HID_1c4d4 = 0x1c4d4, + BNXT_ULP_CLASS_HID_1e614 = 0x1e614, + BNXT_ULP_CLASS_HID_1c580 = 0x1c580, + BNXT_ULP_CLASS_HID_1e6c0 = 0x1e6c0, + BNXT_ULP_CLASS_HID_1c800 = 0x1c800, + BNXT_ULP_CLASS_HID_1ed40 = 0x1ed40, + BNXT_ULP_CLASS_HID_8c6c = 0x8c6c, + BNXT_ULP_CLASS_HID_b1ac = 0xb1ac, + BNXT_ULP_CLASS_HID_f2ec = 0xf2ec, + BNXT_ULP_CLASS_HID_f42c = 0xf42c, + BNXT_ULP_CLASS_HID_8930 = 0x8930, + BNXT_ULP_CLASS_HID_aa70 = 0xaa70, + BNXT_ULP_CLASS_HID_cfb0 = 0xcfb0, + BNXT_ULP_CLASS_HID_f0f0 = 0xf0f0, + BNXT_ULP_CLASS_HID_1bf30 = 0x1bf30, + BNXT_ULP_CLASS_HID_1a070 = 0x1a070, + BNXT_ULP_CLASS_HID_1e5b0 = 0x1e5b0, + BNXT_ULP_CLASS_HID_1e6f0 = 0x1e6f0, + BNXT_ULP_CLASS_HID_1a26c = 0x1a26c, + BNXT_ULP_CLASS_HID_1a7ac = 0x1a7ac, + BNXT_ULP_CLASS_HID_1e8ec = 0x1e8ec, + BNXT_ULP_CLASS_HID_1ea2c = 0x1ea2c, + BNXT_ULP_CLASS_HID_d090 = 0xd090, + BNXT_ULP_CLASS_HID_f5d0 = 0xf5d0, + BNXT_ULP_CLASS_HID_d710 = 0xd710, + BNXT_ULP_CLASS_HID_f850 = 0xf850, + BNXT_ULP_CLASS_HID_ada4 = 0xada4, + BNXT_ULP_CLASS_HID_aee4 = 0xaee4, + BNXT_ULP_CLASS_HID_d024 = 0xd024, + BNXT_ULP_CLASS_HID_f564 = 0xf564, + BNXT_ULP_CLASS_HID_1c3a4 = 0x1c3a4, + BNXT_ULP_CLASS_HID_1e4e4 = 0x1e4e4, + BNXT_ULP_CLASS_HID_1c624 = 0x1c624, + BNXT_ULP_CLASS_HID_1eb64 = 0x1eb64, + BNXT_ULP_CLASS_HID_1c690 = 0x1c690, + BNXT_ULP_CLASS_HID_1ebd0 = 0x1ebd0, + BNXT_ULP_CLASS_HID_1cd10 = 0x1cd10, + BNXT_ULP_CLASS_HID_1f364 = 0x1f364, + BNXT_ULP_CLASS_HID_99c8 = 0x99c8, + BNXT_ULP_CLASS_HID_bb08 = 0xbb08, + BNXT_ULP_CLASS_HID_dc48 = 0xdc48, + BNXT_ULP_CLASS_HID_e188 = 0xe188, + BNXT_ULP_CLASS_HID_929c = 0x929c, + BNXT_ULP_CLASS_HID_b7dc = 0xb7dc, + BNXT_ULP_CLASS_HID_d91c = 0xd91c, + BNXT_ULP_CLASS_HID_fa5c = 0xfa5c, + BNXT_ULP_CLASS_HID_1889c = 0x1889c, + BNXT_ULP_CLASS_HID_1addc = 0x1addc, + BNXT_ULP_CLASS_HID_1cf1c = 0x1cf1c, + BNXT_ULP_CLASS_HID_1f05c = 0x1f05c, + BNXT_ULP_CLASS_HID_18fc8 = 0x18fc8, + BNXT_ULP_CLASS_HID_1b108 = 0x1b108, + BNXT_ULP_CLASS_HID_1f248 = 0x1f248, + BNXT_ULP_CLASS_HID_1f788 = 0x1f788, + BNXT_ULP_CLASS_HID_ba7c = 0xba7c, + BNXT_ULP_CLASS_HID_bfbc = 0xbfbc, + BNXT_ULP_CLASS_HID_e0fc = 0xe0fc, + BNXT_ULP_CLASS_HID_e23c = 0xe23c, + BNXT_ULP_CLASS_HID_b700 = 0xb700, + BNXT_ULP_CLASS_HID_b840 = 0xb840, + BNXT_ULP_CLASS_HID_fd80 = 0xfd80, + BNXT_ULP_CLASS_HID_fec0 = 0xfec0, + BNXT_ULP_CLASS_HID_1ad00 = 0x1ad00, + BNXT_ULP_CLASS_HID_1ae40 = 0x1ae40, + BNXT_ULP_CLASS_HID_1d380 = 0x1d380, + BNXT_ULP_CLASS_HID_1f4c0 = 0x1f4c0, + BNXT_ULP_CLASS_HID_1d07c = 0x1d07c, + BNXT_ULP_CLASS_HID_1f5bc = 0x1f5bc, + BNXT_ULP_CLASS_HID_1d6fc = 0x1d6fc, + BNXT_ULP_CLASS_HID_1f83c = 0x1f83c, + BNXT_ULP_CLASS_HID_86a0 = 0x86a0, + BNXT_ULP_CLASS_HID_abe0 = 0xabe0, + BNXT_ULP_CLASS_HID_cd20 = 0xcd20, + BNXT_ULP_CLASS_HID_ee60 = 0xee60, + BNXT_ULP_CLASS_HID_8374 = 0x8374, + BNXT_ULP_CLASS_HID_a4b4 = 0xa4b4, + BNXT_ULP_CLASS_HID_c9f4 = 0xc9f4, + BNXT_ULP_CLASS_HID_eb34 = 0xeb34, + BNXT_ULP_CLASS_HID_1b974 = 0x1b974, + BNXT_ULP_CLASS_HID_1bab4 = 0x1bab4, + BNXT_ULP_CLASS_HID_1fff4 = 0x1fff4, + BNXT_ULP_CLASS_HID_1e134 = 0x1e134, + BNXT_ULP_CLASS_HID_1bca0 = 0x1bca0, + BNXT_ULP_CLASS_HID_1a1e0 = 0x1a1e0, + BNXT_ULP_CLASS_HID_1e320 = 0x1e320, + BNXT_ULP_CLASS_HID_1e460 = 0x1e460, + BNXT_ULP_CLASS_HID_aad4 = 0xaad4, + BNXT_ULP_CLASS_HID_ac14 = 0xac14, + BNXT_ULP_CLASS_HID_d154 = 0xd154, + BNXT_ULP_CLASS_HID_f294 = 0xf294, + BNXT_ULP_CLASS_HID_a798 = 0xa798, + BNXT_ULP_CLASS_HID_a8d8 = 0xa8d8, + BNXT_ULP_CLASS_HID_ea18 = 0xea18, + BNXT_ULP_CLASS_HID_ef58 = 0xef58, + BNXT_ULP_CLASS_HID_1dd98 = 0x1dd98, + BNXT_ULP_CLASS_HID_1fed8 = 0x1fed8, + BNXT_ULP_CLASS_HID_1c018 = 0x1c018, + BNXT_ULP_CLASS_HID_1e558 = 0x1e558, + BNXT_ULP_CLASS_HID_1c0d4 = 0x1c0d4, + BNXT_ULP_CLASS_HID_1e214 = 0x1e214, + BNXT_ULP_CLASS_HID_1c754 = 0x1c754, + BNXT_ULP_CLASS_HID_1e894 = 0x1e894, + BNXT_ULP_CLASS_HID_900c = 0x900c, + BNXT_ULP_CLASS_HID_b54c = 0xb54c, + BNXT_ULP_CLASS_HID_d68c = 0xd68c, + BNXT_ULP_CLASS_HID_fbcc = 0xfbcc, + BNXT_ULP_CLASS_HID_c80c = 0xc80c, + BNXT_ULP_CLASS_HID_ed4c = 0xed4c, + BNXT_ULP_CLASS_HID_d350 = 0xd350, + BNXT_ULP_CLASS_HID_f490 = 0xf490, + BNXT_ULP_CLASS_HID_182d0 = 0x182d0, + BNXT_ULP_CLASS_HID_1a410 = 0x1a410, + BNXT_ULP_CLASS_HID_1c950 = 0x1c950, + BNXT_ULP_CLASS_HID_1ea90 = 0x1ea90, + BNXT_ULP_CLASS_HID_1860c = 0x1860c, + BNXT_ULP_CLASS_HID_1ab4c = 0x1ab4c, + BNXT_ULP_CLASS_HID_1cc8c = 0x1cc8c, + BNXT_ULP_CLASS_HID_1f1cc = 0x1f1cc, + BNXT_ULP_CLASS_HID_b4b0 = 0xb4b0, + BNXT_ULP_CLASS_HID_b9f0 = 0xb9f0, + BNXT_ULP_CLASS_HID_fb30 = 0xfb30, + BNXT_ULP_CLASS_HID_fc70 = 0xfc70, + BNXT_ULP_CLASS_HID_b144 = 0xb144, + BNXT_ULP_CLASS_HID_b284 = 0xb284, + BNXT_ULP_CLASS_HID_f7c4 = 0xf7c4, + BNXT_ULP_CLASS_HID_f904 = 0xf904, + BNXT_ULP_CLASS_HID_1a744 = 0x1a744, + BNXT_ULP_CLASS_HID_1a884 = 0x1a884, + BNXT_ULP_CLASS_HID_1edc4 = 0x1edc4, + BNXT_ULP_CLASS_HID_1ef04 = 0x1ef04, + BNXT_ULP_CLASS_HID_1aab0 = 0x1aab0, + BNXT_ULP_CLASS_HID_1aff0 = 0x1aff0, + BNXT_ULP_CLASS_HID_1d130 = 0x1d130, + BNXT_ULP_CLASS_HID_1f270 = 0x1f270, + BNXT_ULP_CLASS_HID_80e4 = 0x80e4, + BNXT_ULP_CLASS_HID_a224 = 0xa224, + BNXT_ULP_CLASS_HID_c764 = 0xc764, + BNXT_ULP_CLASS_HID_e8a4 = 0xe8a4, + BNXT_ULP_CLASS_HID_9da8 = 0x9da8, + BNXT_ULP_CLASS_HID_bee8 = 0xbee8, + BNXT_ULP_CLASS_HID_c028 = 0xc028, + BNXT_ULP_CLASS_HID_e568 = 0xe568, + BNXT_ULP_CLASS_HID_1b3a8 = 0x1b3a8, + BNXT_ULP_CLASS_HID_1b4e8 = 0x1b4e8, + BNXT_ULP_CLASS_HID_1f628 = 0x1f628, + BNXT_ULP_CLASS_HID_1fb68 = 0x1fb68, + BNXT_ULP_CLASS_HID_1b6e4 = 0x1b6e4, + BNXT_ULP_CLASS_HID_1b824 = 0x1b824, + BNXT_ULP_CLASS_HID_1fd64 = 0x1fd64, + BNXT_ULP_CLASS_HID_1fea4 = 0x1fea4, + BNXT_ULP_CLASS_HID_a508 = 0xa508, + BNXT_ULP_CLASS_HID_a648 = 0xa648, + BNXT_ULP_CLASS_HID_eb88 = 0xeb88, + BNXT_ULP_CLASS_HID_ecc8 = 0xecc8, + BNXT_ULP_CLASS_HID_a1dc = 0xa1dc, + BNXT_ULP_CLASS_HID_a31c = 0xa31c, + BNXT_ULP_CLASS_HID_e45c = 0xe45c, + BNXT_ULP_CLASS_HID_e99c = 0xe99c, + BNXT_ULP_CLASS_HID_1d7dc = 0x1d7dc, + BNXT_ULP_CLASS_HID_1f91c = 0x1f91c, + BNXT_ULP_CLASS_HID_1da5c = 0x1da5c, + BNXT_ULP_CLASS_HID_1ff9c = 0x1ff9c, + BNXT_ULP_CLASS_HID_1db08 = 0x1db08, + BNXT_ULP_CLASS_HID_1fc48 = 0x1fc48, + BNXT_ULP_CLASS_HID_1c188 = 0x1c188, + BNXT_ULP_CLASS_HID_1e2c8 = 0x1e2c8, + BNXT_ULP_CLASS_HID_9ad8 = 0x9ad8, + BNXT_ULP_CLASS_HID_bc18 = 0xbc18, + BNXT_ULP_CLASS_HID_c158 = 0xc158, + BNXT_ULP_CLASS_HID_e298 = 0xe298, + BNXT_ULP_CLASS_HID_97ec = 0x97ec, + BNXT_ULP_CLASS_HID_b92c = 0xb92c, + BNXT_ULP_CLASS_HID_da6c = 0xda6c, + BNXT_ULP_CLASS_HID_ffac = 0xffac, + BNXT_ULP_CLASS_HID_18dec = 0x18dec, + BNXT_ULP_CLASS_HID_1af2c = 0x1af2c, + BNXT_ULP_CLASS_HID_1f06c = 0x1f06c, + BNXT_ULP_CLASS_HID_1f5ac = 0x1f5ac, + BNXT_ULP_CLASS_HID_1b0d8 = 0x1b0d8, + BNXT_ULP_CLASS_HID_1b218 = 0x1b218, + BNXT_ULP_CLASS_HID_1f758 = 0x1f758, + BNXT_ULP_CLASS_HID_1f898 = 0x1f898, + BNXT_ULP_CLASS_HID_bf4c = 0xbf4c, + BNXT_ULP_CLASS_HID_a08c = 0xa08c, + BNXT_ULP_CLASS_HID_e5cc = 0xe5cc, + BNXT_ULP_CLASS_HID_e70c = 0xe70c, + BNXT_ULP_CLASS_HID_b810 = 0xb810, + BNXT_ULP_CLASS_HID_bd50 = 0xbd50, + BNXT_ULP_CLASS_HID_fe90 = 0xfe90, + BNXT_ULP_CLASS_HID_e3d0 = 0xe3d0, + BNXT_ULP_CLASS_HID_1ae10 = 0x1ae10, + BNXT_ULP_CLASS_HID_1f350 = 0x1f350, + BNXT_ULP_CLASS_HID_1d490 = 0x1d490, + BNXT_ULP_CLASS_HID_1f9d0 = 0x1f9d0, + BNXT_ULP_CLASS_HID_1d54c = 0x1d54c, + BNXT_ULP_CLASS_HID_1f68c = 0x1f68c, + BNXT_ULP_CLASS_HID_1dbcc = 0x1dbcc, + BNXT_ULP_CLASS_HID_1fd0c = 0x1fd0c, + BNXT_ULP_CLASS_HID_34b0 = 0x34b0, + BNXT_ULP_CLASS_HID_3a7c = 0x3a7c, + BNXT_ULP_CLASS_HID_5ee0 = 0x5ee0, + BNXT_ULP_CLASS_HID_07d8 = 0x07d8, + BNXT_ULP_CLASS_HID_284c = 0x284c, + BNXT_ULP_CLASS_HID_5924 = 0x5924, + BNXT_ULP_CLASS_HID_1e1c = 0x1e1c, + BNXT_ULP_CLASS_HID_2280 = 0x2280, + BNXT_ULP_CLASS_HID_24604 = 0x24604, + BNXT_ULP_CLASS_HID_255d4 = 0x255d4, + BNXT_ULP_CLASS_HID_22e08 = 0x22e08, + BNXT_ULP_CLASS_HID_24378 = 0x24378, + BNXT_ULP_CLASS_HID_20fcc = 0x20fcc, + BNXT_ULP_CLASS_HID_21a9c = 0x21a9c, + BNXT_ULP_CLASS_HID_217d0 = 0x217d0, + BNXT_ULP_CLASS_HID_20800 = 0x20800, + BNXT_ULP_CLASS_HID_253a0 = 0x253a0, + BNXT_ULP_CLASS_HID_23f70 = 0x23f70, + BNXT_ULP_CLASS_HID_23ba4 = 0x23ba4, + BNXT_ULP_CLASS_HID_22c94 = 0x22c94, + BNXT_ULP_CLASS_HID_21968 = 0x21968, + BNXT_ULP_CLASS_HID_243c4 = 0x243c4, + BNXT_ULP_CLASS_HID_25c38 = 0x25c38, + BNXT_ULP_CLASS_HID_2125c = 0x2125c, + BNXT_ULP_CLASS_HID_240c8 = 0x240c8, + BNXT_ULP_CLASS_HID_22f98 = 0x22f98, + BNXT_ULP_CLASS_HID_228cc = 0x228cc, + BNXT_ULP_CLASS_HID_25d3c = 0x25d3c, + BNXT_ULP_CLASS_HID_20990 = 0x20990, + BNXT_ULP_CLASS_HID_214a0 = 0x214a0, + BNXT_ULP_CLASS_HID_21194 = 0x21194, + BNXT_ULP_CLASS_HID_202c4 = 0x202c4, + BNXT_ULP_CLASS_HID_22a64 = 0x22a64, + BNXT_ULP_CLASS_HID_23934 = 0x23934, + BNXT_ULP_CLASS_HID_23268 = 0x23268, + BNXT_ULP_CLASS_HID_22758 = 0x22758, + BNXT_ULP_CLASS_HID_2132c = 0x2132c, + BNXT_ULP_CLASS_HID_25d88 = 0x25d88, + BNXT_ULP_CLASS_HID_256fc = 0x256fc, + BNXT_ULP_CLASS_HID_24b2c = 0x24b2c, + BNXT_ULP_CLASS_HID_22f14 = 0x22f14, + BNXT_ULP_CLASS_HID_23a24 = 0x23a24, + BNXT_ULP_CLASS_HID_23718 = 0x23718, + BNXT_ULP_CLASS_HID_22848 = 0x22848, + BNXT_ULP_CLASS_HID_214dc = 0x214dc, + BNXT_ULP_CLASS_HID_25eb8 = 0x25eb8, + BNXT_ULP_CLASS_HID_25bec = 0x25bec, + BNXT_ULP_CLASS_HID_21110 = 0x21110, + BNXT_ULP_CLASS_HID_238b0 = 0x238b0, + BNXT_ULP_CLASS_HID_20440 = 0x20440, + BNXT_ULP_CLASS_HID_200b4 = 0x200b4, + BNXT_ULP_CLASS_HID_235e4 = 0x235e4, + BNXT_ULP_CLASS_HID_25d04 = 0x25d04, + BNXT_ULP_CLASS_HID_228d4 = 0x228d4, + BNXT_ULP_CLASS_HID_22508 = 0x22508, + BNXT_ULP_CLASS_HID_25678 = 0x25678, + BNXT_ULP_CLASS_HID_229d8 = 0x229d8, + BNXT_ULP_CLASS_HID_234e8 = 0x234e8, + BNXT_ULP_CLASS_HID_231dc = 0x231dc, + BNXT_ULP_CLASS_HID_2220c = 0x2220c, + BNXT_ULP_CLASS_HID_24dac = 0x24dac, + BNXT_ULP_CLASS_HID_2597c = 0x2597c, + BNXT_ULP_CLASS_HID_255b0 = 0x255b0, + BNXT_ULP_CLASS_HID_246e0 = 0x246e0, + BNXT_ULP_CLASS_HID_23374 = 0x23374, + BNXT_ULP_CLASS_HID_21e04 = 0x21e04, + BNXT_ULP_CLASS_HID_21b78 = 0x21b78, + BNXT_ULP_CLASS_HID_20fa8 = 0x20fa8, + BNXT_ULP_CLASS_HID_257c8 = 0x257c8, + BNXT_ULP_CLASS_HID_22298 = 0x22298, + BNXT_ULP_CLASS_HID_23fcc = 0x23fcc, + BNXT_ULP_CLASS_HID_2503c = 0x2503c, + BNXT_ULP_CLASS_HID_2239c = 0x2239c, + BNXT_ULP_CLASS_HID_20eac = 0x20eac, + BNXT_ULP_CLASS_HID_20be0 = 0x20be0, + BNXT_ULP_CLASS_HID_23cd0 = 0x23cd0, + BNXT_ULP_CLASS_HID_24470 = 0x24470, + BNXT_ULP_CLASS_HID_25300 = 0x25300, + BNXT_ULP_CLASS_HID_22c74 = 0x22c74, + BNXT_ULP_CLASS_HID_240a4 = 0x240a4, + BNXT_ULP_CLASS_HID_23da0 = 0x23da0, + BNXT_ULP_CLASS_HID_20970 = 0x20970, + BNXT_ULP_CLASS_HID_205a4 = 0x205a4, + BNXT_ULP_CLASS_HID_23694 = 0x23694, + BNXT_ULP_CLASS_HID_25e34 = 0x25e34, + BNXT_ULP_CLASS_HID_22dc4 = 0x22dc4, + BNXT_ULP_CLASS_HID_22638 = 0x22638, + BNXT_ULP_CLASS_HID_25b68 = 0x25b68, + BNXT_ULP_CLASS_HID_34c8 = 0x34c8, + BNXT_ULP_CLASS_HID_3a04 = 0x3a04, + BNXT_ULP_CLASS_HID_5e98 = 0x5e98, + BNXT_ULP_CLASS_HID_07a0 = 0x07a0, + BNXT_ULP_CLASS_HID_2834 = 0x2834, + BNXT_ULP_CLASS_HID_595c = 0x595c, + BNXT_ULP_CLASS_HID_1e64 = 0x1e64, + BNXT_ULP_CLASS_HID_22f8 = 0x22f8, + BNXT_ULP_CLASS_HID_24664 = 0x24664, + BNXT_ULP_CLASS_HID_29418 = 0x29418, + BNXT_ULP_CLASS_HID_30118 = 0x30118, + BNXT_ULP_CLASS_HID_38a18 = 0x38a18, + BNXT_ULP_CLASS_HID_255b4 = 0x255b4, + BNXT_ULP_CLASS_HID_2deb4 = 0x2deb4, + BNXT_ULP_CLASS_HID_34bb4 = 0x34bb4, + BNXT_ULP_CLASS_HID_39968 = 0x39968, + BNXT_ULP_CLASS_HID_22e68 = 0x22e68, + BNXT_ULP_CLASS_HID_2db68 = 0x2db68, + BNXT_ULP_CLASS_HID_34468 = 0x34468, + BNXT_ULP_CLASS_HID_3921c = 0x3921c, + BNXT_ULP_CLASS_HID_24318 = 0x24318, + BNXT_ULP_CLASS_HID_290cc = 0x290cc, + BNXT_ULP_CLASS_HID_31dcc = 0x31dcc, + BNXT_ULP_CLASS_HID_386cc = 0x386cc, + BNXT_ULP_CLASS_HID_20fac = 0x20fac, + BNXT_ULP_CLASS_HID_2b8ac = 0x2b8ac, + BNXT_ULP_CLASS_HID_325ac = 0x325ac, + BNXT_ULP_CLASS_HID_3aeac = 0x3aeac, + BNXT_ULP_CLASS_HID_21afc = 0x21afc, + BNXT_ULP_CLASS_HID_287fc = 0x287fc, + BNXT_ULP_CLASS_HID_330fc = 0x330fc, + BNXT_ULP_CLASS_HID_3bdfc = 0x3bdfc, + BNXT_ULP_CLASS_HID_217b0 = 0x217b0, + BNXT_ULP_CLASS_HID_280b0 = 0x280b0, + BNXT_ULP_CLASS_HID_30db0 = 0x30db0, + BNXT_ULP_CLASS_HID_3b6b0 = 0x3b6b0, + BNXT_ULP_CLASS_HID_20860 = 0x20860, + BNXT_ULP_CLASS_HID_2b560 = 0x2b560, + BNXT_ULP_CLASS_HID_33e60 = 0x33e60, + BNXT_ULP_CLASS_HID_3ab60 = 0x3ab60, + BNXT_ULP_CLASS_HID_253c0 = 0x253c0, + BNXT_ULP_CLASS_HID_2dcc0 = 0x2dcc0, + BNXT_ULP_CLASS_HID_349c0 = 0x349c0, + BNXT_ULP_CLASS_HID_397f4 = 0x397f4, + BNXT_ULP_CLASS_HID_23f10 = 0x23f10, + BNXT_ULP_CLASS_HID_2a810 = 0x2a810, + BNXT_ULP_CLASS_HID_35510 = 0x35510, + BNXT_ULP_CLASS_HID_3de10 = 0x3de10, + BNXT_ULP_CLASS_HID_23bc4 = 0x23bc4, + BNXT_ULP_CLASS_HID_2a4c4 = 0x2a4c4, + BNXT_ULP_CLASS_HID_351c4 = 0x351c4, + BNXT_ULP_CLASS_HID_3dac4 = 0x3dac4, + BNXT_ULP_CLASS_HID_22cf4 = 0x22cf4, + BNXT_ULP_CLASS_HID_2d9f4 = 0x2d9f4, + BNXT_ULP_CLASS_HID_342f4 = 0x342f4, + BNXT_ULP_CLASS_HID_390a8 = 0x390a8, + BNXT_ULP_CLASS_HID_21908 = 0x21908, + BNXT_ULP_CLASS_HID_28208 = 0x28208, + BNXT_ULP_CLASS_HID_30f08 = 0x30f08, + BNXT_ULP_CLASS_HID_3b808 = 0x3b808, + BNXT_ULP_CLASS_HID_243a4 = 0x243a4, + BNXT_ULP_CLASS_HID_29158 = 0x29158, + BNXT_ULP_CLASS_HID_31a58 = 0x31a58, + BNXT_ULP_CLASS_HID_38758 = 0x38758, + BNXT_ULP_CLASS_HID_25c58 = 0x25c58, + BNXT_ULP_CLASS_HID_2c958 = 0x2c958, + BNXT_ULP_CLASS_HID_3170c = 0x3170c, + BNXT_ULP_CLASS_HID_3800c = 0x3800c, + BNXT_ULP_CLASS_HID_2123c = 0x2123c, + BNXT_ULP_CLASS_HID_29f3c = 0x29f3c, + BNXT_ULP_CLASS_HID_3083c = 0x3083c, + BNXT_ULP_CLASS_HID_3b53c = 0x3b53c, + BNXT_ULP_CLASS_HID_240a8 = 0x240a8, + BNXT_ULP_CLASS_HID_2cda8 = 0x2cda8, + BNXT_ULP_CLASS_HID_31b5c = 0x31b5c, + BNXT_ULP_CLASS_HID_3845c = 0x3845c, + BNXT_ULP_CLASS_HID_22ff8 = 0x22ff8, + BNXT_ULP_CLASS_HID_2d8f8 = 0x2d8f8, + BNXT_ULP_CLASS_HID_345f8 = 0x345f8, + BNXT_ULP_CLASS_HID_393ac = 0x393ac, + BNXT_ULP_CLASS_HID_228ac = 0x228ac, + BNXT_ULP_CLASS_HID_2d5ac = 0x2d5ac, + BNXT_ULP_CLASS_HID_35eac = 0x35eac, + BNXT_ULP_CLASS_HID_3cbac = 0x3cbac, + BNXT_ULP_CLASS_HID_25d5c = 0x25d5c, + BNXT_ULP_CLASS_HID_2c65c = 0x2c65c, + BNXT_ULP_CLASS_HID_31410 = 0x31410, + BNXT_ULP_CLASS_HID_38110 = 0x38110, + BNXT_ULP_CLASS_HID_209f0 = 0x209f0, + BNXT_ULP_CLASS_HID_2b2f0 = 0x2b2f0, + BNXT_ULP_CLASS_HID_33ff0 = 0x33ff0, + BNXT_ULP_CLASS_HID_3a8f0 = 0x3a8f0, + BNXT_ULP_CLASS_HID_214c0 = 0x214c0, + BNXT_ULP_CLASS_HID_281c0 = 0x281c0, + BNXT_ULP_CLASS_HID_30ac0 = 0x30ac0, + BNXT_ULP_CLASS_HID_3b7c0 = 0x3b7c0, + BNXT_ULP_CLASS_HID_211f4 = 0x211f4, + BNXT_ULP_CLASS_HID_29af4 = 0x29af4, + BNXT_ULP_CLASS_HID_307f4 = 0x307f4, + BNXT_ULP_CLASS_HID_3b0f4 = 0x3b0f4, + BNXT_ULP_CLASS_HID_202a4 = 0x202a4, + BNXT_ULP_CLASS_HID_28fa4 = 0x28fa4, + BNXT_ULP_CLASS_HID_338a4 = 0x338a4, + BNXT_ULP_CLASS_HID_3a5a4 = 0x3a5a4, + BNXT_ULP_CLASS_HID_22a04 = 0x22a04, + BNXT_ULP_CLASS_HID_2d704 = 0x2d704, + BNXT_ULP_CLASS_HID_34004 = 0x34004, + BNXT_ULP_CLASS_HID_3cd04 = 0x3cd04, + BNXT_ULP_CLASS_HID_23954 = 0x23954, + BNXT_ULP_CLASS_HID_2a254 = 0x2a254, + BNXT_ULP_CLASS_HID_32f54 = 0x32f54, + BNXT_ULP_CLASS_HID_3d854 = 0x3d854, + BNXT_ULP_CLASS_HID_23208 = 0x23208, + BNXT_ULP_CLASS_HID_2bf08 = 0x2bf08, + BNXT_ULP_CLASS_HID_32808 = 0x32808, + BNXT_ULP_CLASS_HID_3d508 = 0x3d508, + BNXT_ULP_CLASS_HID_22738 = 0x22738, + BNXT_ULP_CLASS_HID_2d038 = 0x2d038, + BNXT_ULP_CLASS_HID_35d38 = 0x35d38, + BNXT_ULP_CLASS_HID_3c638 = 0x3c638, + BNXT_ULP_CLASS_HID_2134c = 0x2134c, + BNXT_ULP_CLASS_HID_29c4c = 0x29c4c, + BNXT_ULP_CLASS_HID_3094c = 0x3094c, + BNXT_ULP_CLASS_HID_3b24c = 0x3b24c, + BNXT_ULP_CLASS_HID_25de8 = 0x25de8, + BNXT_ULP_CLASS_HID_2c6e8 = 0x2c6e8, + BNXT_ULP_CLASS_HID_3149c = 0x3149c, + BNXT_ULP_CLASS_HID_3819c = 0x3819c, + BNXT_ULP_CLASS_HID_2569c = 0x2569c, + BNXT_ULP_CLASS_HID_2c39c = 0x2c39c, + BNXT_ULP_CLASS_HID_31150 = 0x31150, + BNXT_ULP_CLASS_HID_39a50 = 0x39a50, + BNXT_ULP_CLASS_HID_24b4c = 0x24b4c, + BNXT_ULP_CLASS_HID_29900 = 0x29900, + BNXT_ULP_CLASS_HID_30200 = 0x30200, + BNXT_ULP_CLASS_HID_38f00 = 0x38f00, + BNXT_ULP_CLASS_HID_22f74 = 0x22f74, + BNXT_ULP_CLASS_HID_2d874 = 0x2d874, + BNXT_ULP_CLASS_HID_34574 = 0x34574, + BNXT_ULP_CLASS_HID_39328 = 0x39328, + BNXT_ULP_CLASS_HID_23a44 = 0x23a44, + BNXT_ULP_CLASS_HID_2a744 = 0x2a744, + BNXT_ULP_CLASS_HID_35044 = 0x35044, + BNXT_ULP_CLASS_HID_3dd44 = 0x3dd44, + BNXT_ULP_CLASS_HID_23778 = 0x23778, + BNXT_ULP_CLASS_HID_2a078 = 0x2a078, + BNXT_ULP_CLASS_HID_32d78 = 0x32d78, + BNXT_ULP_CLASS_HID_3d678 = 0x3d678, + BNXT_ULP_CLASS_HID_22828 = 0x22828, + BNXT_ULP_CLASS_HID_2d528 = 0x2d528, + BNXT_ULP_CLASS_HID_35e28 = 0x35e28, + BNXT_ULP_CLASS_HID_3cb28 = 0x3cb28, + BNXT_ULP_CLASS_HID_214bc = 0x214bc, + BNXT_ULP_CLASS_HID_281bc = 0x281bc, + BNXT_ULP_CLASS_HID_30abc = 0x30abc, + BNXT_ULP_CLASS_HID_3b7bc = 0x3b7bc, + BNXT_ULP_CLASS_HID_25ed8 = 0x25ed8, + BNXT_ULP_CLASS_HID_2cbd8 = 0x2cbd8, + BNXT_ULP_CLASS_HID_3198c = 0x3198c, + BNXT_ULP_CLASS_HID_3828c = 0x3828c, + BNXT_ULP_CLASS_HID_25b8c = 0x25b8c, + BNXT_ULP_CLASS_HID_2c48c = 0x2c48c, + BNXT_ULP_CLASS_HID_31240 = 0x31240, + BNXT_ULP_CLASS_HID_39f40 = 0x39f40, + BNXT_ULP_CLASS_HID_21170 = 0x21170, + BNXT_ULP_CLASS_HID_29a70 = 0x29a70, + BNXT_ULP_CLASS_HID_30770 = 0x30770, + BNXT_ULP_CLASS_HID_3b070 = 0x3b070, + BNXT_ULP_CLASS_HID_238d0 = 0x238d0, + BNXT_ULP_CLASS_HID_2a5d0 = 0x2a5d0, + BNXT_ULP_CLASS_HID_32ed0 = 0x32ed0, + BNXT_ULP_CLASS_HID_3dbd0 = 0x3dbd0, + BNXT_ULP_CLASS_HID_20420 = 0x20420, + BNXT_ULP_CLASS_HID_2b120 = 0x2b120, + BNXT_ULP_CLASS_HID_33a20 = 0x33a20, + BNXT_ULP_CLASS_HID_3a720 = 0x3a720, + BNXT_ULP_CLASS_HID_200d4 = 0x200d4, + BNXT_ULP_CLASS_HID_28dd4 = 0x28dd4, + BNXT_ULP_CLASS_HID_336d4 = 0x336d4, + BNXT_ULP_CLASS_HID_3a3d4 = 0x3a3d4, + BNXT_ULP_CLASS_HID_23584 = 0x23584, + BNXT_ULP_CLASS_HID_2be84 = 0x2be84, + BNXT_ULP_CLASS_HID_32b84 = 0x32b84, + BNXT_ULP_CLASS_HID_3d484 = 0x3d484, + BNXT_ULP_CLASS_HID_25d64 = 0x25d64, + BNXT_ULP_CLASS_HID_2c664 = 0x2c664, + BNXT_ULP_CLASS_HID_31418 = 0x31418, + BNXT_ULP_CLASS_HID_38118 = 0x38118, + BNXT_ULP_CLASS_HID_228b4 = 0x228b4, + BNXT_ULP_CLASS_HID_2d5b4 = 0x2d5b4, + BNXT_ULP_CLASS_HID_35eb4 = 0x35eb4, + BNXT_ULP_CLASS_HID_3cbb4 = 0x3cbb4, + BNXT_ULP_CLASS_HID_22568 = 0x22568, + BNXT_ULP_CLASS_HID_2ae68 = 0x2ae68, + BNXT_ULP_CLASS_HID_35b68 = 0x35b68, + BNXT_ULP_CLASS_HID_3c468 = 0x3c468, + BNXT_ULP_CLASS_HID_25618 = 0x25618, + BNXT_ULP_CLASS_HID_2c318 = 0x2c318, + BNXT_ULP_CLASS_HID_310cc = 0x310cc, + BNXT_ULP_CLASS_HID_39dcc = 0x39dcc, + BNXT_ULP_CLASS_HID_229b8 = 0x229b8, + BNXT_ULP_CLASS_HID_2d2b8 = 0x2d2b8, + BNXT_ULP_CLASS_HID_35fb8 = 0x35fb8, + BNXT_ULP_CLASS_HID_3c8b8 = 0x3c8b8, + BNXT_ULP_CLASS_HID_23488 = 0x23488, + BNXT_ULP_CLASS_HID_2a188 = 0x2a188, + BNXT_ULP_CLASS_HID_32a88 = 0x32a88, + BNXT_ULP_CLASS_HID_3d788 = 0x3d788, + BNXT_ULP_CLASS_HID_231bc = 0x231bc, + BNXT_ULP_CLASS_HID_2babc = 0x2babc, + BNXT_ULP_CLASS_HID_327bc = 0x327bc, + BNXT_ULP_CLASS_HID_3d0bc = 0x3d0bc, + BNXT_ULP_CLASS_HID_2226c = 0x2226c, + BNXT_ULP_CLASS_HID_2af6c = 0x2af6c, + BNXT_ULP_CLASS_HID_3586c = 0x3586c, + BNXT_ULP_CLASS_HID_3c56c = 0x3c56c, + BNXT_ULP_CLASS_HID_24dcc = 0x24dcc, + BNXT_ULP_CLASS_HID_29b80 = 0x29b80, + BNXT_ULP_CLASS_HID_30480 = 0x30480, + BNXT_ULP_CLASS_HID_3b180 = 0x3b180, + BNXT_ULP_CLASS_HID_2591c = 0x2591c, + BNXT_ULP_CLASS_HID_2c21c = 0x2c21c, + BNXT_ULP_CLASS_HID_313d0 = 0x313d0, + BNXT_ULP_CLASS_HID_39cd0 = 0x39cd0, + BNXT_ULP_CLASS_HID_255d0 = 0x255d0, + BNXT_ULP_CLASS_HID_2ded0 = 0x2ded0, + BNXT_ULP_CLASS_HID_34bd0 = 0x34bd0, + BNXT_ULP_CLASS_HID_39984 = 0x39984, + BNXT_ULP_CLASS_HID_24680 = 0x24680, + BNXT_ULP_CLASS_HID_294b4 = 0x294b4, + BNXT_ULP_CLASS_HID_301b4 = 0x301b4, + BNXT_ULP_CLASS_HID_38ab4 = 0x38ab4, + BNXT_ULP_CLASS_HID_23314 = 0x23314, + BNXT_ULP_CLASS_HID_2bc14 = 0x2bc14, + BNXT_ULP_CLASS_HID_32914 = 0x32914, + BNXT_ULP_CLASS_HID_3d214 = 0x3d214, + BNXT_ULP_CLASS_HID_21e64 = 0x21e64, + BNXT_ULP_CLASS_HID_28b64 = 0x28b64, + BNXT_ULP_CLASS_HID_33464 = 0x33464, + BNXT_ULP_CLASS_HID_3a164 = 0x3a164, + BNXT_ULP_CLASS_HID_21b18 = 0x21b18, + BNXT_ULP_CLASS_HID_28418 = 0x28418, + BNXT_ULP_CLASS_HID_33118 = 0x33118, + BNXT_ULP_CLASS_HID_3ba18 = 0x3ba18, + BNXT_ULP_CLASS_HID_20fc8 = 0x20fc8, + BNXT_ULP_CLASS_HID_2b8c8 = 0x2b8c8, + BNXT_ULP_CLASS_HID_325c8 = 0x325c8, + BNXT_ULP_CLASS_HID_3aec8 = 0x3aec8, + BNXT_ULP_CLASS_HID_257a8 = 0x257a8, + BNXT_ULP_CLASS_HID_2c0a8 = 0x2c0a8, + BNXT_ULP_CLASS_HID_34da8 = 0x34da8, + BNXT_ULP_CLASS_HID_39b5c = 0x39b5c, + BNXT_ULP_CLASS_HID_222f8 = 0x222f8, + BNXT_ULP_CLASS_HID_2aff8 = 0x2aff8, + BNXT_ULP_CLASS_HID_358f8 = 0x358f8, + BNXT_ULP_CLASS_HID_3c5f8 = 0x3c5f8, + BNXT_ULP_CLASS_HID_23fac = 0x23fac, + BNXT_ULP_CLASS_HID_2a8ac = 0x2a8ac, + BNXT_ULP_CLASS_HID_355ac = 0x355ac, + BNXT_ULP_CLASS_HID_3deac = 0x3deac, + BNXT_ULP_CLASS_HID_2505c = 0x2505c, + BNXT_ULP_CLASS_HID_2dd5c = 0x2dd5c, + BNXT_ULP_CLASS_HID_3465c = 0x3465c, + BNXT_ULP_CLASS_HID_39410 = 0x39410, + BNXT_ULP_CLASS_HID_223fc = 0x223fc, + BNXT_ULP_CLASS_HID_2acfc = 0x2acfc, + BNXT_ULP_CLASS_HID_359fc = 0x359fc, + BNXT_ULP_CLASS_HID_3c2fc = 0x3c2fc, + BNXT_ULP_CLASS_HID_20ecc = 0x20ecc, + BNXT_ULP_CLASS_HID_2bbcc = 0x2bbcc, + BNXT_ULP_CLASS_HID_324cc = 0x324cc, + BNXT_ULP_CLASS_HID_3d1cc = 0x3d1cc, + BNXT_ULP_CLASS_HID_20b80 = 0x20b80, + BNXT_ULP_CLASS_HID_2b480 = 0x2b480, + BNXT_ULP_CLASS_HID_32180 = 0x32180, + BNXT_ULP_CLASS_HID_3aa80 = 0x3aa80, + BNXT_ULP_CLASS_HID_23cb0 = 0x23cb0, + BNXT_ULP_CLASS_HID_2a9b0 = 0x2a9b0, + BNXT_ULP_CLASS_HID_352b0 = 0x352b0, + BNXT_ULP_CLASS_HID_3dfb0 = 0x3dfb0, + BNXT_ULP_CLASS_HID_24410 = 0x24410, + BNXT_ULP_CLASS_HID_295c4 = 0x295c4, + BNXT_ULP_CLASS_HID_31ec4 = 0x31ec4, + BNXT_ULP_CLASS_HID_38bc4 = 0x38bc4, + BNXT_ULP_CLASS_HID_25360 = 0x25360, + BNXT_ULP_CLASS_HID_2dc60 = 0x2dc60, + BNXT_ULP_CLASS_HID_34960 = 0x34960, + BNXT_ULP_CLASS_HID_39714 = 0x39714, + BNXT_ULP_CLASS_HID_22c14 = 0x22c14, + BNXT_ULP_CLASS_HID_2d914 = 0x2d914, + BNXT_ULP_CLASS_HID_34214 = 0x34214, + BNXT_ULP_CLASS_HID_393c8 = 0x393c8, + BNXT_ULP_CLASS_HID_240c4 = 0x240c4, + BNXT_ULP_CLASS_HID_2cdc4 = 0x2cdc4, + BNXT_ULP_CLASS_HID_31bf8 = 0x31bf8, + BNXT_ULP_CLASS_HID_384f8 = 0x384f8, + BNXT_ULP_CLASS_HID_23dc0 = 0x23dc0, + BNXT_ULP_CLASS_HID_2a6c0 = 0x2a6c0, + BNXT_ULP_CLASS_HID_353c0 = 0x353c0, + BNXT_ULP_CLASS_HID_3dcc0 = 0x3dcc0, + BNXT_ULP_CLASS_HID_20910 = 0x20910, + BNXT_ULP_CLASS_HID_2b210 = 0x2b210, + BNXT_ULP_CLASS_HID_33f10 = 0x33f10, + BNXT_ULP_CLASS_HID_3a810 = 0x3a810, + BNXT_ULP_CLASS_HID_205c4 = 0x205c4, + BNXT_ULP_CLASS_HID_28ec4 = 0x28ec4, + BNXT_ULP_CLASS_HID_33bc4 = 0x33bc4, + BNXT_ULP_CLASS_HID_3a4c4 = 0x3a4c4, + BNXT_ULP_CLASS_HID_236f4 = 0x236f4, + BNXT_ULP_CLASS_HID_2a3f4 = 0x2a3f4, + BNXT_ULP_CLASS_HID_32cf4 = 0x32cf4, + BNXT_ULP_CLASS_HID_3d9f4 = 0x3d9f4, + BNXT_ULP_CLASS_HID_25e54 = 0x25e54, + BNXT_ULP_CLASS_HID_2cb54 = 0x2cb54, + BNXT_ULP_CLASS_HID_31908 = 0x31908, + BNXT_ULP_CLASS_HID_38208 = 0x38208, + BNXT_ULP_CLASS_HID_22da4 = 0x22da4, + BNXT_ULP_CLASS_HID_2d6a4 = 0x2d6a4, + BNXT_ULP_CLASS_HID_343a4 = 0x343a4, + BNXT_ULP_CLASS_HID_39158 = 0x39158, + BNXT_ULP_CLASS_HID_22658 = 0x22658, + BNXT_ULP_CLASS_HID_2d358 = 0x2d358, + BNXT_ULP_CLASS_HID_35c58 = 0x35c58, + BNXT_ULP_CLASS_HID_3c958 = 0x3c958, + BNXT_ULP_CLASS_HID_25b08 = 0x25b08, + BNXT_ULP_CLASS_HID_2c408 = 0x2c408, + BNXT_ULP_CLASS_HID_3123c = 0x3123c, + BNXT_ULP_CLASS_HID_39f3c = 0x39f3c, + BNXT_ULP_CLASS_HID_34a8 = 0x34a8, + BNXT_ULP_CLASS_HID_3a64 = 0x3a64, + BNXT_ULP_CLASS_HID_5ef8 = 0x5ef8, + BNXT_ULP_CLASS_HID_07c0 = 0x07c0, + BNXT_ULP_CLASS_HID_2854 = 0x2854, + BNXT_ULP_CLASS_HID_593c = 0x593c, + BNXT_ULP_CLASS_HID_1e04 = 0x1e04, + BNXT_ULP_CLASS_HID_2298 = 0x2298, + BNXT_ULP_CLASS_HID_24644 = 0x24644, + BNXT_ULP_CLASS_HID_29438 = 0x29438, + BNXT_ULP_CLASS_HID_30138 = 0x30138, + BNXT_ULP_CLASS_HID_38a38 = 0x38a38, + BNXT_ULP_CLASS_HID_25594 = 0x25594, + BNXT_ULP_CLASS_HID_2de94 = 0x2de94, + BNXT_ULP_CLASS_HID_34b94 = 0x34b94, + BNXT_ULP_CLASS_HID_39948 = 0x39948, + BNXT_ULP_CLASS_HID_22e48 = 0x22e48, + BNXT_ULP_CLASS_HID_2db48 = 0x2db48, + BNXT_ULP_CLASS_HID_34448 = 0x34448, + BNXT_ULP_CLASS_HID_3923c = 0x3923c, + BNXT_ULP_CLASS_HID_24338 = 0x24338, + BNXT_ULP_CLASS_HID_290ec = 0x290ec, + BNXT_ULP_CLASS_HID_31dec = 0x31dec, + BNXT_ULP_CLASS_HID_386ec = 0x386ec, + BNXT_ULP_CLASS_HID_20f8c = 0x20f8c, + BNXT_ULP_CLASS_HID_2b88c = 0x2b88c, + BNXT_ULP_CLASS_HID_3258c = 0x3258c, + BNXT_ULP_CLASS_HID_3ae8c = 0x3ae8c, + BNXT_ULP_CLASS_HID_21adc = 0x21adc, + BNXT_ULP_CLASS_HID_287dc = 0x287dc, + BNXT_ULP_CLASS_HID_330dc = 0x330dc, + BNXT_ULP_CLASS_HID_3bddc = 0x3bddc, + BNXT_ULP_CLASS_HID_21790 = 0x21790, + BNXT_ULP_CLASS_HID_28090 = 0x28090, + BNXT_ULP_CLASS_HID_30d90 = 0x30d90, + BNXT_ULP_CLASS_HID_3b690 = 0x3b690, + BNXT_ULP_CLASS_HID_20840 = 0x20840, + BNXT_ULP_CLASS_HID_2b540 = 0x2b540, + BNXT_ULP_CLASS_HID_33e40 = 0x33e40, + BNXT_ULP_CLASS_HID_3ab40 = 0x3ab40, + BNXT_ULP_CLASS_HID_253e0 = 0x253e0, + BNXT_ULP_CLASS_HID_2dce0 = 0x2dce0, + BNXT_ULP_CLASS_HID_349e0 = 0x349e0, + BNXT_ULP_CLASS_HID_397d4 = 0x397d4, + BNXT_ULP_CLASS_HID_23f30 = 0x23f30, + BNXT_ULP_CLASS_HID_2a830 = 0x2a830, + BNXT_ULP_CLASS_HID_35530 = 0x35530, + BNXT_ULP_CLASS_HID_3de30 = 0x3de30, + BNXT_ULP_CLASS_HID_23be4 = 0x23be4, + BNXT_ULP_CLASS_HID_2a4e4 = 0x2a4e4, + BNXT_ULP_CLASS_HID_351e4 = 0x351e4, + BNXT_ULP_CLASS_HID_3dae4 = 0x3dae4, + BNXT_ULP_CLASS_HID_22cd4 = 0x22cd4, + BNXT_ULP_CLASS_HID_2d9d4 = 0x2d9d4, + BNXT_ULP_CLASS_HID_342d4 = 0x342d4, + BNXT_ULP_CLASS_HID_39088 = 0x39088, + BNXT_ULP_CLASS_HID_21928 = 0x21928, + BNXT_ULP_CLASS_HID_28228 = 0x28228, + BNXT_ULP_CLASS_HID_30f28 = 0x30f28, + BNXT_ULP_CLASS_HID_3b828 = 0x3b828, + BNXT_ULP_CLASS_HID_24384 = 0x24384, + BNXT_ULP_CLASS_HID_29178 = 0x29178, + BNXT_ULP_CLASS_HID_31a78 = 0x31a78, + BNXT_ULP_CLASS_HID_38778 = 0x38778, + BNXT_ULP_CLASS_HID_25c78 = 0x25c78, + BNXT_ULP_CLASS_HID_2c978 = 0x2c978, + BNXT_ULP_CLASS_HID_3172c = 0x3172c, + BNXT_ULP_CLASS_HID_3802c = 0x3802c, + BNXT_ULP_CLASS_HID_2121c = 0x2121c, + BNXT_ULP_CLASS_HID_29f1c = 0x29f1c, + BNXT_ULP_CLASS_HID_3081c = 0x3081c, + BNXT_ULP_CLASS_HID_3b51c = 0x3b51c, + BNXT_ULP_CLASS_HID_24088 = 0x24088, + BNXT_ULP_CLASS_HID_2cd88 = 0x2cd88, + BNXT_ULP_CLASS_HID_31b7c = 0x31b7c, + BNXT_ULP_CLASS_HID_3847c = 0x3847c, + BNXT_ULP_CLASS_HID_22fd8 = 0x22fd8, + BNXT_ULP_CLASS_HID_2d8d8 = 0x2d8d8, + BNXT_ULP_CLASS_HID_345d8 = 0x345d8, + BNXT_ULP_CLASS_HID_3938c = 0x3938c, + BNXT_ULP_CLASS_HID_2288c = 0x2288c, + BNXT_ULP_CLASS_HID_2d58c = 0x2d58c, + BNXT_ULP_CLASS_HID_35e8c = 0x35e8c, + BNXT_ULP_CLASS_HID_3cb8c = 0x3cb8c, + BNXT_ULP_CLASS_HID_25d7c = 0x25d7c, + BNXT_ULP_CLASS_HID_2c67c = 0x2c67c, + BNXT_ULP_CLASS_HID_31430 = 0x31430, + BNXT_ULP_CLASS_HID_38130 = 0x38130, + BNXT_ULP_CLASS_HID_209d0 = 0x209d0, + BNXT_ULP_CLASS_HID_2b2d0 = 0x2b2d0, + BNXT_ULP_CLASS_HID_33fd0 = 0x33fd0, + BNXT_ULP_CLASS_HID_3a8d0 = 0x3a8d0, + BNXT_ULP_CLASS_HID_214e0 = 0x214e0, + BNXT_ULP_CLASS_HID_281e0 = 0x281e0, + BNXT_ULP_CLASS_HID_30ae0 = 0x30ae0, + BNXT_ULP_CLASS_HID_3b7e0 = 0x3b7e0, + BNXT_ULP_CLASS_HID_211d4 = 0x211d4, + BNXT_ULP_CLASS_HID_29ad4 = 0x29ad4, + BNXT_ULP_CLASS_HID_307d4 = 0x307d4, + BNXT_ULP_CLASS_HID_3b0d4 = 0x3b0d4, + BNXT_ULP_CLASS_HID_20284 = 0x20284, + BNXT_ULP_CLASS_HID_28f84 = 0x28f84, + BNXT_ULP_CLASS_HID_33884 = 0x33884, + BNXT_ULP_CLASS_HID_3a584 = 0x3a584, + BNXT_ULP_CLASS_HID_22a24 = 0x22a24, + BNXT_ULP_CLASS_HID_2d724 = 0x2d724, + BNXT_ULP_CLASS_HID_34024 = 0x34024, + BNXT_ULP_CLASS_HID_3cd24 = 0x3cd24, + BNXT_ULP_CLASS_HID_23974 = 0x23974, + BNXT_ULP_CLASS_HID_2a274 = 0x2a274, + BNXT_ULP_CLASS_HID_32f74 = 0x32f74, + BNXT_ULP_CLASS_HID_3d874 = 0x3d874, + BNXT_ULP_CLASS_HID_23228 = 0x23228, + BNXT_ULP_CLASS_HID_2bf28 = 0x2bf28, + BNXT_ULP_CLASS_HID_32828 = 0x32828, + BNXT_ULP_CLASS_HID_3d528 = 0x3d528, + BNXT_ULP_CLASS_HID_22718 = 0x22718, + BNXT_ULP_CLASS_HID_2d018 = 0x2d018, + BNXT_ULP_CLASS_HID_35d18 = 0x35d18, + BNXT_ULP_CLASS_HID_3c618 = 0x3c618, + BNXT_ULP_CLASS_HID_2136c = 0x2136c, + BNXT_ULP_CLASS_HID_29c6c = 0x29c6c, + BNXT_ULP_CLASS_HID_3096c = 0x3096c, + BNXT_ULP_CLASS_HID_3b26c = 0x3b26c, + BNXT_ULP_CLASS_HID_25dc8 = 0x25dc8, + BNXT_ULP_CLASS_HID_2c6c8 = 0x2c6c8, + BNXT_ULP_CLASS_HID_314bc = 0x314bc, + BNXT_ULP_CLASS_HID_381bc = 0x381bc, + BNXT_ULP_CLASS_HID_256bc = 0x256bc, + BNXT_ULP_CLASS_HID_2c3bc = 0x2c3bc, + BNXT_ULP_CLASS_HID_31170 = 0x31170, + BNXT_ULP_CLASS_HID_39a70 = 0x39a70, + BNXT_ULP_CLASS_HID_24b6c = 0x24b6c, + BNXT_ULP_CLASS_HID_29920 = 0x29920, + BNXT_ULP_CLASS_HID_30220 = 0x30220, + BNXT_ULP_CLASS_HID_38f20 = 0x38f20, + BNXT_ULP_CLASS_HID_22f54 = 0x22f54, + BNXT_ULP_CLASS_HID_2d854 = 0x2d854, + BNXT_ULP_CLASS_HID_34554 = 0x34554, + BNXT_ULP_CLASS_HID_39308 = 0x39308, + BNXT_ULP_CLASS_HID_23a64 = 0x23a64, + BNXT_ULP_CLASS_HID_2a764 = 0x2a764, + BNXT_ULP_CLASS_HID_35064 = 0x35064, + BNXT_ULP_CLASS_HID_3dd64 = 0x3dd64, + BNXT_ULP_CLASS_HID_23758 = 0x23758, + BNXT_ULP_CLASS_HID_2a058 = 0x2a058, + BNXT_ULP_CLASS_HID_32d58 = 0x32d58, + BNXT_ULP_CLASS_HID_3d658 = 0x3d658, + BNXT_ULP_CLASS_HID_22808 = 0x22808, + BNXT_ULP_CLASS_HID_2d508 = 0x2d508, + BNXT_ULP_CLASS_HID_35e08 = 0x35e08, + BNXT_ULP_CLASS_HID_3cb08 = 0x3cb08, + BNXT_ULP_CLASS_HID_2149c = 0x2149c, + BNXT_ULP_CLASS_HID_2819c = 0x2819c, + BNXT_ULP_CLASS_HID_30a9c = 0x30a9c, + BNXT_ULP_CLASS_HID_3b79c = 0x3b79c, + BNXT_ULP_CLASS_HID_25ef8 = 0x25ef8, + BNXT_ULP_CLASS_HID_2cbf8 = 0x2cbf8, + BNXT_ULP_CLASS_HID_319ac = 0x319ac, + BNXT_ULP_CLASS_HID_382ac = 0x382ac, + BNXT_ULP_CLASS_HID_25bac = 0x25bac, + BNXT_ULP_CLASS_HID_2c4ac = 0x2c4ac, + BNXT_ULP_CLASS_HID_31260 = 0x31260, + BNXT_ULP_CLASS_HID_39f60 = 0x39f60, + BNXT_ULP_CLASS_HID_21150 = 0x21150, + BNXT_ULP_CLASS_HID_29a50 = 0x29a50, + BNXT_ULP_CLASS_HID_30750 = 0x30750, + BNXT_ULP_CLASS_HID_3b050 = 0x3b050, + BNXT_ULP_CLASS_HID_238f0 = 0x238f0, + BNXT_ULP_CLASS_HID_2a5f0 = 0x2a5f0, + BNXT_ULP_CLASS_HID_32ef0 = 0x32ef0, + BNXT_ULP_CLASS_HID_3dbf0 = 0x3dbf0, + BNXT_ULP_CLASS_HID_20400 = 0x20400, + BNXT_ULP_CLASS_HID_2b100 = 0x2b100, + BNXT_ULP_CLASS_HID_33a00 = 0x33a00, + BNXT_ULP_CLASS_HID_3a700 = 0x3a700, + BNXT_ULP_CLASS_HID_200f4 = 0x200f4, + BNXT_ULP_CLASS_HID_28df4 = 0x28df4, + BNXT_ULP_CLASS_HID_336f4 = 0x336f4, + BNXT_ULP_CLASS_HID_3a3f4 = 0x3a3f4, + BNXT_ULP_CLASS_HID_235a4 = 0x235a4, + BNXT_ULP_CLASS_HID_2bea4 = 0x2bea4, + BNXT_ULP_CLASS_HID_32ba4 = 0x32ba4, + BNXT_ULP_CLASS_HID_3d4a4 = 0x3d4a4, + BNXT_ULP_CLASS_HID_25d44 = 0x25d44, + BNXT_ULP_CLASS_HID_2c644 = 0x2c644, + BNXT_ULP_CLASS_HID_31438 = 0x31438, + BNXT_ULP_CLASS_HID_38138 = 0x38138, + BNXT_ULP_CLASS_HID_22894 = 0x22894, + BNXT_ULP_CLASS_HID_2d594 = 0x2d594, + BNXT_ULP_CLASS_HID_35e94 = 0x35e94, + BNXT_ULP_CLASS_HID_3cb94 = 0x3cb94, + BNXT_ULP_CLASS_HID_22548 = 0x22548, + BNXT_ULP_CLASS_HID_2ae48 = 0x2ae48, + BNXT_ULP_CLASS_HID_35b48 = 0x35b48, + BNXT_ULP_CLASS_HID_3c448 = 0x3c448, + BNXT_ULP_CLASS_HID_25638 = 0x25638, + BNXT_ULP_CLASS_HID_2c338 = 0x2c338, + BNXT_ULP_CLASS_HID_310ec = 0x310ec, + BNXT_ULP_CLASS_HID_39dec = 0x39dec, + BNXT_ULP_CLASS_HID_22998 = 0x22998, + BNXT_ULP_CLASS_HID_2d298 = 0x2d298, + BNXT_ULP_CLASS_HID_35f98 = 0x35f98, + BNXT_ULP_CLASS_HID_3c898 = 0x3c898, + BNXT_ULP_CLASS_HID_234a8 = 0x234a8, + BNXT_ULP_CLASS_HID_2a1a8 = 0x2a1a8, + BNXT_ULP_CLASS_HID_32aa8 = 0x32aa8, + BNXT_ULP_CLASS_HID_3d7a8 = 0x3d7a8, + BNXT_ULP_CLASS_HID_2319c = 0x2319c, + BNXT_ULP_CLASS_HID_2ba9c = 0x2ba9c, + BNXT_ULP_CLASS_HID_3279c = 0x3279c, + BNXT_ULP_CLASS_HID_3d09c = 0x3d09c, + BNXT_ULP_CLASS_HID_2224c = 0x2224c, + BNXT_ULP_CLASS_HID_2af4c = 0x2af4c, + BNXT_ULP_CLASS_HID_3584c = 0x3584c, + BNXT_ULP_CLASS_HID_3c54c = 0x3c54c, + BNXT_ULP_CLASS_HID_24dec = 0x24dec, + BNXT_ULP_CLASS_HID_29ba0 = 0x29ba0, + BNXT_ULP_CLASS_HID_304a0 = 0x304a0, + BNXT_ULP_CLASS_HID_3b1a0 = 0x3b1a0, + BNXT_ULP_CLASS_HID_2593c = 0x2593c, + BNXT_ULP_CLASS_HID_2c23c = 0x2c23c, + BNXT_ULP_CLASS_HID_313f0 = 0x313f0, + BNXT_ULP_CLASS_HID_39cf0 = 0x39cf0, + BNXT_ULP_CLASS_HID_255f0 = 0x255f0, + BNXT_ULP_CLASS_HID_2def0 = 0x2def0, + BNXT_ULP_CLASS_HID_34bf0 = 0x34bf0, + BNXT_ULP_CLASS_HID_399a4 = 0x399a4, + BNXT_ULP_CLASS_HID_246a0 = 0x246a0, + BNXT_ULP_CLASS_HID_29494 = 0x29494, + BNXT_ULP_CLASS_HID_30194 = 0x30194, + BNXT_ULP_CLASS_HID_38a94 = 0x38a94, + BNXT_ULP_CLASS_HID_23334 = 0x23334, + BNXT_ULP_CLASS_HID_2bc34 = 0x2bc34, + BNXT_ULP_CLASS_HID_32934 = 0x32934, + BNXT_ULP_CLASS_HID_3d234 = 0x3d234, + BNXT_ULP_CLASS_HID_21e44 = 0x21e44, + BNXT_ULP_CLASS_HID_28b44 = 0x28b44, + BNXT_ULP_CLASS_HID_33444 = 0x33444, + BNXT_ULP_CLASS_HID_3a144 = 0x3a144, + BNXT_ULP_CLASS_HID_21b38 = 0x21b38, + BNXT_ULP_CLASS_HID_28438 = 0x28438, + BNXT_ULP_CLASS_HID_33138 = 0x33138, + BNXT_ULP_CLASS_HID_3ba38 = 0x3ba38, + BNXT_ULP_CLASS_HID_20fe8 = 0x20fe8, + BNXT_ULP_CLASS_HID_2b8e8 = 0x2b8e8, + BNXT_ULP_CLASS_HID_325e8 = 0x325e8, + BNXT_ULP_CLASS_HID_3aee8 = 0x3aee8, + BNXT_ULP_CLASS_HID_25788 = 0x25788, + BNXT_ULP_CLASS_HID_2c088 = 0x2c088, + BNXT_ULP_CLASS_HID_34d88 = 0x34d88, + BNXT_ULP_CLASS_HID_39b7c = 0x39b7c, + BNXT_ULP_CLASS_HID_222d8 = 0x222d8, + BNXT_ULP_CLASS_HID_2afd8 = 0x2afd8, + BNXT_ULP_CLASS_HID_358d8 = 0x358d8, + BNXT_ULP_CLASS_HID_3c5d8 = 0x3c5d8, + BNXT_ULP_CLASS_HID_23f8c = 0x23f8c, + BNXT_ULP_CLASS_HID_2a88c = 0x2a88c, + BNXT_ULP_CLASS_HID_3558c = 0x3558c, + BNXT_ULP_CLASS_HID_3de8c = 0x3de8c, + BNXT_ULP_CLASS_HID_2507c = 0x2507c, + BNXT_ULP_CLASS_HID_2dd7c = 0x2dd7c, + BNXT_ULP_CLASS_HID_3467c = 0x3467c, + BNXT_ULP_CLASS_HID_39430 = 0x39430, + BNXT_ULP_CLASS_HID_223dc = 0x223dc, + BNXT_ULP_CLASS_HID_2acdc = 0x2acdc, + BNXT_ULP_CLASS_HID_359dc = 0x359dc, + BNXT_ULP_CLASS_HID_3c2dc = 0x3c2dc, + BNXT_ULP_CLASS_HID_20eec = 0x20eec, + BNXT_ULP_CLASS_HID_2bbec = 0x2bbec, + BNXT_ULP_CLASS_HID_324ec = 0x324ec, + BNXT_ULP_CLASS_HID_3d1ec = 0x3d1ec, + BNXT_ULP_CLASS_HID_20ba0 = 0x20ba0, + BNXT_ULP_CLASS_HID_2b4a0 = 0x2b4a0, + BNXT_ULP_CLASS_HID_321a0 = 0x321a0, + BNXT_ULP_CLASS_HID_3aaa0 = 0x3aaa0, + BNXT_ULP_CLASS_HID_23c90 = 0x23c90, + BNXT_ULP_CLASS_HID_2a990 = 0x2a990, + BNXT_ULP_CLASS_HID_35290 = 0x35290, + BNXT_ULP_CLASS_HID_3df90 = 0x3df90, + BNXT_ULP_CLASS_HID_24430 = 0x24430, + BNXT_ULP_CLASS_HID_295e4 = 0x295e4, + BNXT_ULP_CLASS_HID_31ee4 = 0x31ee4, + BNXT_ULP_CLASS_HID_38be4 = 0x38be4, + BNXT_ULP_CLASS_HID_25340 = 0x25340, + BNXT_ULP_CLASS_HID_2dc40 = 0x2dc40, + BNXT_ULP_CLASS_HID_34940 = 0x34940, + BNXT_ULP_CLASS_HID_39734 = 0x39734, + BNXT_ULP_CLASS_HID_22c34 = 0x22c34, + BNXT_ULP_CLASS_HID_2d934 = 0x2d934, + BNXT_ULP_CLASS_HID_34234 = 0x34234, + BNXT_ULP_CLASS_HID_393e8 = 0x393e8, + BNXT_ULP_CLASS_HID_240e4 = 0x240e4, + BNXT_ULP_CLASS_HID_2cde4 = 0x2cde4, + BNXT_ULP_CLASS_HID_31bd8 = 0x31bd8, + BNXT_ULP_CLASS_HID_384d8 = 0x384d8, + BNXT_ULP_CLASS_HID_23de0 = 0x23de0, + BNXT_ULP_CLASS_HID_2a6e0 = 0x2a6e0, + BNXT_ULP_CLASS_HID_353e0 = 0x353e0, + BNXT_ULP_CLASS_HID_3dce0 = 0x3dce0, + BNXT_ULP_CLASS_HID_20930 = 0x20930, + BNXT_ULP_CLASS_HID_2b230 = 0x2b230, + BNXT_ULP_CLASS_HID_33f30 = 0x33f30, + BNXT_ULP_CLASS_HID_3a830 = 0x3a830, + BNXT_ULP_CLASS_HID_205e4 = 0x205e4, + BNXT_ULP_CLASS_HID_28ee4 = 0x28ee4, + BNXT_ULP_CLASS_HID_33be4 = 0x33be4, + BNXT_ULP_CLASS_HID_3a4e4 = 0x3a4e4, + BNXT_ULP_CLASS_HID_236d4 = 0x236d4, + BNXT_ULP_CLASS_HID_2a3d4 = 0x2a3d4, + BNXT_ULP_CLASS_HID_32cd4 = 0x32cd4, + BNXT_ULP_CLASS_HID_3d9d4 = 0x3d9d4, + BNXT_ULP_CLASS_HID_25e74 = 0x25e74, + BNXT_ULP_CLASS_HID_2cb74 = 0x2cb74, + BNXT_ULP_CLASS_HID_31928 = 0x31928, + BNXT_ULP_CLASS_HID_38228 = 0x38228, + BNXT_ULP_CLASS_HID_22d84 = 0x22d84, + BNXT_ULP_CLASS_HID_2d684 = 0x2d684, + BNXT_ULP_CLASS_HID_34384 = 0x34384, + BNXT_ULP_CLASS_HID_39178 = 0x39178, + BNXT_ULP_CLASS_HID_22678 = 0x22678, + BNXT_ULP_CLASS_HID_2d378 = 0x2d378, + BNXT_ULP_CLASS_HID_35c78 = 0x35c78, + BNXT_ULP_CLASS_HID_3c978 = 0x3c978, + BNXT_ULP_CLASS_HID_25b28 = 0x25b28, + BNXT_ULP_CLASS_HID_2c428 = 0x2c428, + BNXT_ULP_CLASS_HID_3121c = 0x3121c, + BNXT_ULP_CLASS_HID_39f1c = 0x39f1c, + BNXT_ULP_CLASS_HID_3488 = 0x3488, + BNXT_ULP_CLASS_HID_3a44 = 0x3a44, + BNXT_ULP_CLASS_HID_5ed8 = 0x5ed8, + BNXT_ULP_CLASS_HID_07e0 = 0x07e0, + BNXT_ULP_CLASS_HID_2874 = 0x2874, + BNXT_ULP_CLASS_HID_591c = 0x591c, + BNXT_ULP_CLASS_HID_1e24 = 0x1e24, + BNXT_ULP_CLASS_HID_22b8 = 0x22b8 }; enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_0000 = 0x0000, BNXT_ULP_ACT_HID_0001 = 0x0001, BNXT_ULP_ACT_HID_0400 = 0x0400, - BNXT_ULP_ACT_HID_0325 = 0x0325, + BNXT_ULP_ACT_HID_01ab = 0x01ab, BNXT_ULP_ACT_HID_0010 = 0x0010, - BNXT_ULP_ACT_HID_0725 = 0x0725, - BNXT_ULP_ACT_HID_0335 = 0x0335, + BNXT_ULP_ACT_HID_05ab = 0x05ab, + BNXT_ULP_ACT_HID_01bb = 0x01bb, BNXT_ULP_ACT_HID_0002 = 0x0002, BNXT_ULP_ACT_HID_0003 = 0x0003, BNXT_ULP_ACT_HID_0402 = 0x0402, - BNXT_ULP_ACT_HID_0327 = 0x0327, + BNXT_ULP_ACT_HID_01ad = 0x01ad, BNXT_ULP_ACT_HID_0012 = 0x0012, - BNXT_ULP_ACT_HID_0727 = 0x0727, - BNXT_ULP_ACT_HID_0337 = 0x0337, - BNXT_ULP_ACT_HID_01de = 0x01de, - BNXT_ULP_ACT_HID_00c6 = 0x00c6, - BNXT_ULP_ACT_HID_0506 = 0x0506, - BNXT_ULP_ACT_HID_01ed = 0x01ed, - BNXT_ULP_ACT_HID_03ef = 0x03ef, - BNXT_ULP_ACT_HID_0516 = 0x0516, - BNXT_ULP_ACT_HID_01df = 0x01df, - BNXT_ULP_ACT_HID_01e4 = 0x01e4, - BNXT_ULP_ACT_HID_00cc = 0x00cc, - BNXT_ULP_ACT_HID_0504 = 0x0504, - BNXT_ULP_ACT_HID_01ef = 0x01ef, - BNXT_ULP_ACT_HID_03ed = 0x03ed, - BNXT_ULP_ACT_HID_0514 = 0x0514, - BNXT_ULP_ACT_HID_00db = 0x00db, - BNXT_ULP_ACT_HID_00df = 0x00df + BNXT_ULP_ACT_HID_05ad = 0x05ad, + BNXT_ULP_ACT_HID_01bd = 0x01bd, + BNXT_ULP_ACT_HID_0613 = 0x0613, + BNXT_ULP_ACT_HID_02a9 = 0x02a9, + BNXT_ULP_ACT_HID_0054 = 0x0054, + BNXT_ULP_ACT_HID_0622 = 0x0622, + BNXT_ULP_ACT_HID_0454 = 0x0454, + BNXT_ULP_ACT_HID_0064 = 0x0064, + BNXT_ULP_ACT_HID_0614 = 0x0614, + BNXT_ULP_ACT_HID_0615 = 0x0615, + BNXT_ULP_ACT_HID_02ab = 0x02ab, + BNXT_ULP_ACT_HID_0056 = 0x0056, + BNXT_ULP_ACT_HID_0624 = 0x0624, + BNXT_ULP_ACT_HID_0456 = 0x0456, + BNXT_ULP_ACT_HID_0066 = 0x0066, + BNXT_ULP_ACT_HID_048d = 0x048d, + BNXT_ULP_ACT_HID_048f = 0x048f, + BNXT_ULP_ACT_HID_04bc = 0x04bc, + BNXT_ULP_ACT_HID_00a9 = 0x00a9, + BNXT_ULP_ACT_HID_020f = 0x020f, + BNXT_ULP_ACT_HID_04a9 = 0x04a9, + BNXT_ULP_ACT_HID_01fc = 0x01fc, + BNXT_ULP_ACT_HID_04be = 0x04be, + BNXT_ULP_ACT_HID_00ab = 0x00ab, + BNXT_ULP_ACT_HID_0211 = 0x0211, + BNXT_ULP_ACT_HID_04ab = 0x04ab, + BNXT_ULP_ACT_HID_01fe = 0x01fe, + BNXT_ULP_ACT_HID_0667 = 0x0667, + BNXT_ULP_ACT_HID_0254 = 0x0254, + BNXT_ULP_ACT_HID_03ba = 0x03ba, + BNXT_ULP_ACT_HID_0654 = 0x0654, + BNXT_ULP_ACT_HID_03a7 = 0x03a7, + BNXT_ULP_ACT_HID_0669 = 0x0669, + BNXT_ULP_ACT_HID_0256 = 0x0256, + BNXT_ULP_ACT_HID_03bc = 0x03bc, + BNXT_ULP_ACT_HID_0656 = 0x0656, + BNXT_ULP_ACT_HID_03a9 = 0x03a9, + BNXT_ULP_ACT_HID_021b = 0x021b, + BNXT_ULP_ACT_HID_021c = 0x021c, + BNXT_ULP_ACT_HID_021e = 0x021e, + BNXT_ULP_ACT_HID_063f = 0x063f, + BNXT_ULP_ACT_HID_0510 = 0x0510, + BNXT_ULP_ACT_HID_03c6 = 0x03c6, + BNXT_ULP_ACT_HID_0082 = 0x0082, + BNXT_ULP_ACT_HID_06bb = 0x06bb, + BNXT_ULP_ACT_HID_021d = 0x021d, + BNXT_ULP_ACT_HID_0641 = 0x0641, + BNXT_ULP_ACT_HID_0512 = 0x0512, + BNXT_ULP_ACT_HID_03c8 = 0x03c8, + BNXT_ULP_ACT_HID_0084 = 0x0084, + BNXT_ULP_ACT_HID_06bd = 0x06bd, + BNXT_ULP_ACT_HID_06d7 = 0x06d7, + BNXT_ULP_ACT_HID_02c4 = 0x02c4, + BNXT_ULP_ACT_HID_042a = 0x042a, + BNXT_ULP_ACT_HID_06c4 = 0x06c4, + BNXT_ULP_ACT_HID_0417 = 0x0417, + BNXT_ULP_ACT_HID_06d9 = 0x06d9, + BNXT_ULP_ACT_HID_02c6 = 0x02c6, + BNXT_ULP_ACT_HID_042c = 0x042c, + BNXT_ULP_ACT_HID_06c6 = 0x06c6, + BNXT_ULP_ACT_HID_0419 = 0x0419, + BNXT_ULP_ACT_HID_0119 = 0x0119, + BNXT_ULP_ACT_HID_046f = 0x046f, + BNXT_ULP_ACT_HID_05d5 = 0x05d5, + BNXT_ULP_ACT_HID_0106 = 0x0106, + BNXT_ULP_ACT_HID_05c2 = 0x05c2, + BNXT_ULP_ACT_HID_011b = 0x011b, + BNXT_ULP_ACT_HID_0471 = 0x0471, + BNXT_ULP_ACT_HID_05d7 = 0x05d7, + BNXT_ULP_ACT_HID_0108 = 0x0108, + BNXT_ULP_ACT_HID_05c4 = 0x05c4, + BNXT_ULP_ACT_HID_00a2 = 0x00a2, + BNXT_ULP_ACT_HID_00a4 = 0x00a4 }; enum bnxt_ulp_df_tpl { - BNXT_ULP_DF_TPL_PORT_TO_VS = 2, - BNXT_ULP_DF_TPL_VS_TO_PORT = 3, - BNXT_ULP_DF_TPL_VFREP_TO_VF = 4, - BNXT_ULP_DF_TPL_VF_TO_VFREP = 5, - BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 6 + BNXT_ULP_DF_TPL_PORT_TO_VS = 3, + BNXT_ULP_DF_TPL_VS_TO_PORT = 4, + BNXT_ULP_DF_TPL_VFREP_TO_VF = 5, + BNXT_ULP_DF_TPL_VF_TO_VFREP = 6, + BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7 }; - #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h index fc388cc490..4daa9f2031 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Dec 7 09:51:03 2020 */ +/* date: Wed Dec 16 16:03:45 2020 */ #ifndef ULP_HDR_FIELD_ENUMS_H_ #define ULP_HDR_FIELD_ENUMS_H_ @@ -122,16 +122,7 @@ enum bnxt_ulp_hf1_0_bitmask { BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, BNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF1_0_BITMASK_O_TCP_URP = 0x0000010000000000 + BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 }; enum bnxt_ulp_hf1_1_bitmask { @@ -150,10 +141,15 @@ enum bnxt_ulp_hf1_1_bitmask { BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_1_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF1_1_BITMASK_O_UDP_CSUM = 0x0000200000000000 + BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF1_1_BITMASK_O_TCP_URP = 0x0000010000000000 }; enum bnxt_ulp_hf1_2_bitmask { @@ -162,23 +158,20 @@ enum bnxt_ulp_hf1_2_bitmask { BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM = 0x0000080000000000, - BNXT_ULP_HF1_2_BITMASK_O_TCP_URP = 0x0000040000000000 + BNXT_ULP_HF1_2_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_2_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF1_2_BITMASK_O_UDP_CSUM = 0x0000200000000000 }; enum bnxt_ulp_hf1_3_bitmask { @@ -194,11 +187,7 @@ enum bnxt_ulp_hf1_3_bitmask { BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, BNXT_ULP_HF1_3_BITMASK_O_IPV6_TTL = 0x0020000000000000, BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF1_3_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF1_3_BITMASK_O_UDP_CSUM = 0x0000800000000000 + BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 }; enum bnxt_ulp_hf1_4_bitmask { @@ -207,28 +196,23 @@ enum bnxt_ulp_hf1_4_bitmask { BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_URP = 0x0000002000000000 + BNXT_ULP_HF1_4_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, + BNXT_ULP_HF1_4_BITMASK_O_TCP_URP = 0x0000040000000000 }; enum bnxt_ulp_hf1_5_bitmask { @@ -237,23 +221,18 @@ enum bnxt_ulp_hf1_5_bitmask { BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM = 0x0000040000000000 + BNXT_ULP_HF1_5_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM = 0x0000800000000000 }; enum bnxt_ulp_hf1_6_bitmask { @@ -265,23 +244,16 @@ enum bnxt_ulp_hf1_6_bitmask { BNXT_ULP_HF1_6_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF1_6_BITMASK_O_TCP_URP = 0x0000008000000000 + BNXT_ULP_HF1_6_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 }; enum bnxt_ulp_hf1_7_bitmask { @@ -293,17 +265,393 @@ enum bnxt_ulp_hf1_7_bitmask { BNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM = 0x0000100000000000 + BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF1_7_BITMASK_O_TCP_URP = 0x0000002000000000 +}; + +enum bnxt_ulp_hf1_8_bitmask { + BNXT_ULP_HF1_8_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_8_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF1_8_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF1_8_BITMASK_O_UDP_CSUM = 0x0000040000000000 +}; + +enum bnxt_ulp_hf1_9_bitmask { + BNXT_ULP_HF1_9_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_9_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 +}; + +enum bnxt_ulp_hf1_10_bitmask { + BNXT_ULP_HF1_10_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_10_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF1_10_BITMASK_O_TCP_URP = 0x0000008000000000 +}; + +enum bnxt_ulp_hf1_11_bitmask { + BNXT_ULP_HF1_11_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_11_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF1_11_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF1_11_BITMASK_O_UDP_CSUM = 0x0000100000000000 +}; + +enum bnxt_ulp_hf2_0_bitmask { + BNXT_ULP_HF2_0_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_0_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 +}; + +enum bnxt_ulp_hf2_1_bitmask { + BNXT_ULP_HF2_1_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_1_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF2_1_BITMASK_O_TCP_URP = 0x0000010000000000 +}; + +enum bnxt_ulp_hf2_2_bitmask { + BNXT_ULP_HF2_2_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_2_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF2_2_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF2_2_BITMASK_O_UDP_CSUM = 0x0000200000000000 +}; + +enum bnxt_ulp_hf2_3_bitmask { + BNXT_ULP_HF2_3_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_3_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 +}; + +enum bnxt_ulp_hf2_4_bitmask { + BNXT_ULP_HF2_4_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_4_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, + BNXT_ULP_HF2_4_BITMASK_O_TCP_URP = 0x0000040000000000 +}; + +enum bnxt_ulp_hf2_5_bitmask { + BNXT_ULP_HF2_5_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_5_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF2_5_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF2_5_BITMASK_O_UDP_CSUM = 0x0000800000000000 +}; + +enum bnxt_ulp_hf2_6_bitmask { + BNXT_ULP_HF2_6_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_6_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 +}; + +enum bnxt_ulp_hf2_7_bitmask { + BNXT_ULP_HF2_7_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_7_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF2_7_BITMASK_O_TCP_URP = 0x0000002000000000 +}; + +enum bnxt_ulp_hf2_8_bitmask { + BNXT_ULP_HF2_8_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_8_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF2_8_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF2_8_BITMASK_O_UDP_CSUM = 0x0000040000000000 +}; + +enum bnxt_ulp_hf2_9_bitmask { + BNXT_ULP_HF2_9_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_9_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 +}; + +enum bnxt_ulp_hf2_10_bitmask { + BNXT_ULP_HF2_10_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_10_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF2_10_BITMASK_O_TCP_URP = 0x0000008000000000 +}; + +enum bnxt_ulp_hf2_11_bitmask { + BNXT_ULP_HF2_11_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF2_11_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF2_11_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF2_11_BITMASK_O_UDP_CSUM = 0x0000100000000000 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c index 7610950507..08f0e25b47 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c @@ -32,14 +32,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 0, .result_bit_size = 64, @@ -54,14 +54,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 1, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 1, .result_bit_size = 0, @@ -76,14 +76,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 13, .result_bit_size = 128, @@ -98,14 +98,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 39, .result_bit_size = 128, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c index a0cab178ec..df09de929e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c @@ -82,13 +82,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 2, + .cond_true_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 0, .blob_key_bit_size = 8, .key_bit_size = 8, @@ -101,14 +101,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .key_start_idx = 1, @@ -129,13 +129,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 14, .blob_key_bit_size = 14, .key_bit_size = 14, @@ -144,29 +144,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .ident_nums = 3 }, { /* class_tid: 1, stingray, table: branch.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 3, + .cond_true_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 1, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID }, { /* class_tid: 1, stingray, table: profile_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, @@ -188,13 +188,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 60, .blob_key_bit_size = 14, .key_bit_size = 14, @@ -210,12 +210,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 2, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .key_start_idx = 63, @@ -233,12 +233,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 3, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .key_start_idx = 73, @@ -251,15 +251,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0 }, { /* class_tid: 1, stingray, table: last */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID }, { /* class_tid: 2, stingray, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -268,14 +268,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 44, .result_bit_size = 128, @@ -287,14 +287,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, @@ -318,13 +318,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 96, .blob_key_bit_size = 8, .key_bit_size = 8, @@ -339,14 +339,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 87, .result_bit_size = 32, .result_num_fields = 1, @@ -357,14 +357,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 88, .result_bit_size = 32, .result_num_fields = 1, @@ -375,14 +375,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 89, .result_bit_size = 32, .result_num_fields = 1, @@ -395,14 +395,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 90, .result_bit_size = 128, @@ -414,14 +414,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 4, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -444,13 +444,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 5, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 110, .blob_key_bit_size = 8, .key_bit_size = 8, @@ -463,14 +463,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 6, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, @@ -492,13 +492,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 8, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 124, .blob_key_bit_size = 8, .key_bit_size = 8, @@ -513,14 +513,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 146, .result_bit_size = 32, .result_num_fields = 1, @@ -531,14 +531,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 147, .result_bit_size = 32, .result_num_fields = 1, @@ -549,14 +549,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 148, .result_bit_size = 32, .result_num_fields = 1, @@ -569,14 +569,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 149, .result_bit_size = 0, @@ -590,14 +590,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 161, .result_bit_size = 128, @@ -609,14 +609,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, @@ -638,13 +638,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 138, .blob_key_bit_size = 8, .key_bit_size = 8, @@ -663,14 +663,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 204, .result_bit_size = 128, @@ -682,14 +682,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -710,14 +710,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -738,14 +738,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, @@ -767,13 +767,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 178, .blob_key_bit_size = 8, .key_bit_size = 8, @@ -788,14 +788,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 273, .result_bit_size = 32, .result_num_fields = 1, @@ -806,14 +806,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 274, .result_bit_size = 32, .result_num_fields = 1, @@ -824,14 +824,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 275, .result_bit_size = 32, .result_num_fields = 1, @@ -844,14 +844,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, .result_start_idx = 276, .result_bit_size = 128, @@ -863,14 +863,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -893,7 +893,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 10, .cond_nums = 0 }, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 6b49a9d93f..64cf6534b9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Dec 4 19:01:47 2020 */ +/* date: Wed Dec 16 16:03:45 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -99,6 +99,10 @@ const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { .tmpl_list_size = ULP_WH_PLUS_ACT_TMPL_LIST_SIZE, .tbl_list = ulp_wh_plus_act_tbl_list, .tbl_list_size = ULP_WH_PLUS_ACT_TBL_LIST_SIZE, + .key_info_list = ulp_wh_plus_act_key_info_list, + .key_info_list_size = ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE, + .ident_list = ulp_wh_plus_act_ident_list, + .ident_list_size = ULP_WH_PLUS_ACT_IDENT_LIST_SIZE, .cond_list = ulp_wh_plus_act_cond_list, .cond_list_size = ULP_WH_PLUS_ACT_COND_LIST_SIZE, .result_field_list = ulp_wh_plus_act_result_field_list, @@ -322,15 +326,6 @@ uint8_t ulp_glb_field_tbl[] = { [2070] = 12, [2072] = 13, [2074] = 14, - [2102] = 15, - [2104] = 16, - [2106] = 17, - [2108] = 18, - [2110] = 19, - [2112] = 20, - [2114] = 21, - [2116] = 22, - [2118] = 23, [2176] = 0, [2177] = 1, [2178] = 2, @@ -346,32 +341,34 @@ uint8_t ulp_glb_field_tbl[] = { [2198] = 12, [2200] = 13, [2202] = 14, - [2248] = 15, - [2250] = 16, - [2252] = 17, - [2254] = 18, + [2230] = 15, + [2232] = 16, + [2234] = 17, + [2236] = 18, + [2238] = 19, + [2240] = 20, + [2242] = 21, + [2244] = 22, + [2246] = 23, [2304] = 0, [2305] = 1, [2306] = 2, [2308] = 3, [2310] = 4, - [2332] = 5, - [2334] = 6, - [2336] = 7, - [2338] = 8, - [2340] = 9, - [2342] = 10, - [2344] = 11, - [2346] = 12, - [2358] = 13, - [2360] = 14, - [2362] = 15, - [2364] = 16, - [2366] = 17, - [2368] = 18, - [2370] = 19, - [2372] = 20, - [2374] = 21, + [2312] = 5, + [2314] = 6, + [2316] = 7, + [2318] = 8, + [2320] = 9, + [2322] = 10, + [2324] = 11, + [2326] = 12, + [2328] = 13, + [2330] = 14, + [2376] = 15, + [2378] = 16, + [2380] = 17, + [2382] = 18, [2432] = 0, [2433] = 1, [2434] = 2, @@ -385,81 +382,60 @@ uint8_t ulp_glb_field_tbl[] = { [2470] = 10, [2472] = 11, [2474] = 12, - [2504] = 13, - [2506] = 14, - [2508] = 15, - [2510] = 16, [2560] = 0, [2561] = 1, [2562] = 2, [2564] = 3, [2566] = 4, - [2568] = 8, - [2570] = 9, - [2572] = 10, - [2574] = 11, - [2576] = 12, - [2578] = 13, - [2580] = 14, - [2582] = 15, - [2584] = 16, - [2586] = 17, - [2614] = 18, - [2616] = 19, - [2618] = 20, - [2620] = 21, - [2622] = 22, - [2624] = 23, - [2626] = 24, - [2628] = 25, - [2630] = 26, - [2640] = 5, - [2644] = 6, - [2648] = 7, + [2588] = 5, + [2590] = 6, + [2592] = 7, + [2594] = 8, + [2596] = 9, + [2598] = 10, + [2600] = 11, + [2602] = 12, + [2614] = 13, + [2616] = 14, + [2618] = 15, + [2620] = 16, + [2622] = 17, + [2624] = 18, + [2626] = 19, + [2628] = 20, + [2630] = 21, [2688] = 0, [2689] = 1, [2690] = 2, [2692] = 3, [2694] = 4, - [2696] = 8, - [2698] = 9, - [2700] = 10, - [2702] = 11, - [2704] = 12, - [2706] = 13, - [2708] = 14, - [2710] = 15, - [2712] = 16, - [2714] = 17, - [2760] = 18, - [2762] = 19, - [2764] = 20, - [2766] = 21, - [2768] = 5, - [2772] = 6, - [2776] = 7, + [2716] = 5, + [2718] = 6, + [2720] = 7, + [2722] = 8, + [2724] = 9, + [2726] = 10, + [2728] = 11, + [2730] = 12, + [2760] = 13, + [2762] = 14, + [2764] = 15, + [2766] = 16, [2816] = 0, [2817] = 1, [2818] = 2, [2820] = 3, [2822] = 4, - [2844] = 8, - [2846] = 9, - [2848] = 10, - [2850] = 11, - [2852] = 12, - [2854] = 13, - [2856] = 14, - [2858] = 15, - [2870] = 16, - [2872] = 17, - [2874] = 18, - [2876] = 19, - [2878] = 20, - [2880] = 21, - [2882] = 22, - [2884] = 23, - [2886] = 24, + [2824] = 8, + [2826] = 9, + [2828] = 10, + [2830] = 11, + [2832] = 12, + [2834] = 13, + [2836] = 14, + [2838] = 15, + [2840] = 16, + [2842] = 17, [2896] = 5, [2900] = 6, [2904] = 7, @@ -468,20 +444,348 @@ uint8_t ulp_glb_field_tbl[] = { [2946] = 2, [2948] = 3, [2950] = 4, - [2972] = 8, - [2974] = 9, - [2976] = 10, - [2978] = 11, - [2980] = 12, - [2982] = 13, - [2984] = 14, - [2986] = 15, - [3016] = 16, - [3018] = 17, - [3020] = 18, - [3022] = 19, + [2952] = 8, + [2954] = 9, + [2956] = 10, + [2958] = 11, + [2960] = 12, + [2962] = 13, + [2964] = 14, + [2966] = 15, + [2968] = 16, + [2970] = 17, + [2998] = 18, + [3000] = 19, + [3002] = 20, + [3004] = 21, + [3006] = 22, + [3008] = 23, + [3010] = 24, + [3012] = 25, + [3014] = 26, [3024] = 5, [3028] = 6, - [3032] = 7 + [3032] = 7, + [3072] = 0, + [3073] = 1, + [3074] = 2, + [3076] = 3, + [3078] = 4, + [3080] = 8, + [3082] = 9, + [3084] = 10, + [3086] = 11, + [3088] = 12, + [3090] = 13, + [3092] = 14, + [3094] = 15, + [3096] = 16, + [3098] = 17, + [3144] = 18, + [3146] = 19, + [3148] = 20, + [3150] = 21, + [3152] = 5, + [3156] = 6, + [3160] = 7, + [3200] = 0, + [3201] = 1, + [3202] = 2, + [3204] = 3, + [3206] = 4, + [3228] = 8, + [3230] = 9, + [3232] = 10, + [3234] = 11, + [3236] = 12, + [3238] = 13, + [3240] = 14, + [3242] = 15, + [3280] = 5, + [3284] = 6, + [3288] = 7, + [3328] = 0, + [3329] = 1, + [3330] = 2, + [3332] = 3, + [3334] = 4, + [3356] = 8, + [3358] = 9, + [3360] = 10, + [3362] = 11, + [3364] = 12, + [3366] = 13, + [3368] = 14, + [3370] = 15, + [3382] = 16, + [3384] = 17, + [3386] = 18, + [3388] = 19, + [3390] = 20, + [3392] = 21, + [3394] = 22, + [3396] = 23, + [3398] = 24, + [3408] = 5, + [3412] = 6, + [3416] = 7, + [3456] = 0, + [3457] = 1, + [3458] = 2, + [3460] = 3, + [3462] = 4, + [3484] = 8, + [3486] = 9, + [3488] = 10, + [3490] = 11, + [3492] = 12, + [3494] = 13, + [3496] = 14, + [3498] = 15, + [3528] = 16, + [3530] = 17, + [3532] = 18, + [3534] = 19, + [3536] = 5, + [3540] = 6, + [3544] = 7, + [4096] = 0, + [4097] = 1, + [4098] = 2, + [4100] = 3, + [4102] = 4, + [4104] = 5, + [4106] = 6, + [4108] = 7, + [4110] = 8, + [4112] = 9, + [4114] = 10, + [4116] = 11, + [4118] = 12, + [4120] = 13, + [4122] = 14, + [4224] = 0, + [4225] = 1, + [4226] = 2, + [4228] = 3, + [4230] = 4, + [4232] = 5, + [4234] = 6, + [4236] = 7, + [4238] = 8, + [4240] = 9, + [4242] = 10, + [4244] = 11, + [4246] = 12, + [4248] = 13, + [4250] = 14, + [4278] = 15, + [4280] = 16, + [4282] = 17, + [4284] = 18, + [4286] = 19, + [4288] = 20, + [4290] = 21, + [4292] = 22, + [4294] = 23, + [4352] = 0, + [4353] = 1, + [4354] = 2, + [4356] = 3, + [4358] = 4, + [4360] = 5, + [4362] = 6, + [4364] = 7, + [4366] = 8, + [4368] = 9, + [4370] = 10, + [4372] = 11, + [4374] = 12, + [4376] = 13, + [4378] = 14, + [4424] = 15, + [4426] = 16, + [4428] = 17, + [4430] = 18, + [4480] = 0, + [4481] = 1, + [4482] = 2, + [4484] = 3, + [4486] = 4, + [4508] = 5, + [4510] = 6, + [4512] = 7, + [4514] = 8, + [4516] = 9, + [4518] = 10, + [4520] = 11, + [4522] = 12, + [4608] = 0, + [4609] = 1, + [4610] = 2, + [4612] = 3, + [4614] = 4, + [4636] = 5, + [4638] = 6, + [4640] = 7, + [4642] = 8, + [4644] = 9, + [4646] = 10, + [4648] = 11, + [4650] = 12, + [4662] = 13, + [4664] = 14, + [4666] = 15, + [4668] = 16, + [4670] = 17, + [4672] = 18, + [4674] = 19, + [4676] = 20, + [4678] = 21, + [4736] = 0, + [4737] = 1, + [4738] = 2, + [4740] = 3, + [4742] = 4, + [4764] = 5, + [4766] = 6, + [4768] = 7, + [4770] = 8, + [4772] = 9, + [4774] = 10, + [4776] = 11, + [4778] = 12, + [4808] = 13, + [4810] = 14, + [4812] = 15, + [4814] = 16, + [4864] = 0, + [4865] = 1, + [4866] = 2, + [4868] = 3, + [4870] = 4, + [4872] = 8, + [4874] = 9, + [4876] = 10, + [4878] = 11, + [4880] = 12, + [4882] = 13, + [4884] = 14, + [4886] = 15, + [4888] = 16, + [4890] = 17, + [4944] = 5, + [4948] = 6, + [4952] = 7, + [4992] = 0, + [4993] = 1, + [4994] = 2, + [4996] = 3, + [4998] = 4, + [5000] = 8, + [5002] = 9, + [5004] = 10, + [5006] = 11, + [5008] = 12, + [5010] = 13, + [5012] = 14, + [5014] = 15, + [5016] = 16, + [5018] = 17, + [5046] = 18, + [5048] = 19, + [5050] = 20, + [5052] = 21, + [5054] = 22, + [5056] = 23, + [5058] = 24, + [5060] = 25, + [5062] = 26, + [5072] = 5, + [5076] = 6, + [5080] = 7, + [5120] = 0, + [5121] = 1, + [5122] = 2, + [5124] = 3, + [5126] = 4, + [5128] = 8, + [5130] = 9, + [5132] = 10, + [5134] = 11, + [5136] = 12, + [5138] = 13, + [5140] = 14, + [5142] = 15, + [5144] = 16, + [5146] = 17, + [5192] = 18, + [5194] = 19, + [5196] = 20, + [5198] = 21, + [5200] = 5, + [5204] = 6, + [5208] = 7, + [5248] = 0, + [5249] = 1, + [5250] = 2, + [5252] = 3, + [5254] = 4, + [5276] = 8, + [5278] = 9, + [5280] = 10, + [5282] = 11, + [5284] = 12, + [5286] = 13, + [5288] = 14, + [5290] = 15, + [5328] = 5, + [5332] = 6, + [5336] = 7, + [5376] = 0, + [5377] = 1, + [5378] = 2, + [5380] = 3, + [5382] = 4, + [5404] = 8, + [5406] = 9, + [5408] = 10, + [5410] = 11, + [5412] = 12, + [5414] = 13, + [5416] = 14, + [5418] = 15, + [5430] = 16, + [5432] = 17, + [5434] = 18, + [5436] = 19, + [5438] = 20, + [5440] = 21, + [5442] = 22, + [5444] = 23, + [5446] = 24, + [5456] = 5, + [5460] = 6, + [5464] = 7, + [5504] = 0, + [5505] = 1, + [5506] = 2, + [5508] = 3, + [5510] = 4, + [5532] = 8, + [5534] = 9, + [5536] = 10, + [5538] = 11, + [5540] = 12, + [5542] = 13, + [5544] = 14, + [5546] = 15, + [5576] = 16, + [5578] = 17, + [5580] = 18, + [5582] = 19, + [5584] = 5, + [5588] = 6, + [5592] = 7 }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h index 93b0afbf25..07f9075de7 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h @@ -36,6 +36,10 @@ bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[]; extern struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[]; +extern struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[]; + +extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[]; + /* STINGRAY template table declarations */ extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[]; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index c827be4996..267c4fd45f 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 8 14:57:13 2020 */ +/* date: Thu Dec 17 19:43:07 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -25,12 +25,52 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { /* act_tid: 2, wh_plus, ingress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 7, .start_tbl_idx = 5, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 12, .cond_nums = 0 } + }, + /* act_tid: 3, wh_plus, ingress */ + [3] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 6, + .start_tbl_idx = 12, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 13, + .cond_nums = 0 } + }, + /* act_tid: 4, wh_plus, egress */ + [4] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 18, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 16, + .cond_nums = 0 } + }, + /* act_tid: 5, wh_plus, egress */ + [5] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 6, + .start_tbl_idx = 23, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 20, + .cond_nums = 0 } + }, + /* act_tid: 6, wh_plus, egress */ + [6] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 6, + .start_tbl_idx = 29, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 23, + .cond_nums = 0 } } }; @@ -42,13 +82,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .key_start_idx = 0, .blob_key_bit_size = 1, .key_bit_size = 1, @@ -63,14 +104,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 10, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 0, .result_bit_size = 64, @@ -84,14 +126,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 11, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 1, .result_bit_size = 0, @@ -106,14 +149,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 13, .result_bit_size = 128, @@ -128,19 +172,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 39, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0 + .encap_num_fields = 12 + }, + { /* act_tid: 2, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 12, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID }, { /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -149,16 +207,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 65, + .result_start_idx = 77, .result_bit_size = 32, .result_num_fields = 6 }, @@ -169,16 +229,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 12, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 71, + .result_start_idx = 83, .result_bit_size = 64, .result_num_fields = 1 }, @@ -190,16 +252,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 72, + .result_start_idx = 84, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -212,19 +276,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 98, + .result_start_idx = 110, .result_bit_size = 128, .result_num_fields = 26, - .encap_num_fields = 0 + .encap_num_fields = 12 }, { /* act_tid: 2, wh_plus, table: mirror_tbl.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -233,7 +299,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 13, .cond_nums = 0 }, @@ -242,7 +309,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 124, + .result_start_idx = 148, .result_bit_size = 32, .result_num_fields = 6 }, @@ -253,133 +320,3643 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .key_start_idx = 1, .blob_key_bit_size = 1, .key_bit_size = 1, .key_num_fields = 1, - .result_start_idx = 130, + .result_start_idx = 154, .result_bit_size = 34, .result_num_fields = 2 - } -}; - -struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_SRC }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC + { /* act_tid: 3, wh_plus, table: int_flow_counter_tbl.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 13, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 156, + .result_bit_size = 64, + .result_num_fields = 1 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST + { /* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 14, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 157, + .result_bit_size = 32, + .result_num_fields = 1 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_DST + { /* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 15, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 158, + .result_bit_size = 32, + .result_num_fields = 1 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST + { /* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .result_start_idx = 159, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + { /* act_tid: 3, wh_plus, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 171, + .result_bit_size = 128, + .result_num_fields = 26 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID + { /* act_tid: 3, wh_plus, table: ext_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EXT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 197, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 12 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP + { /* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 16, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 235, + .result_bit_size = 64, + .result_num_fields = 1 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + { /* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 17, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 236, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_COUNT + { /* act_tid: 4, wh_plus, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 18, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 248, + .result_bit_size = 128, + .result_num_fields = 26 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + { /* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EXT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 18, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 274, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 12 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_COUNT - } -}; - -struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { - /* act_tid: 1, wh_plus, table: shared_mirror_record.rd */ - { - .field_info_mask = { - .description = "shared_index", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "shared_index", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} - } + { /* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EXT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 19, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 312, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 12 }, - /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ - { - .field_info_mask = { - .description = "shared_index", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "shared_index", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} - } + { /* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 20, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 350, + .result_bit_size = 64, + .result_num_fields = 1 + }, + { /* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 21, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 351, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 22, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 352, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* act_tid: 5, wh_plus, table: int_encap_mac_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 23, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .result_start_idx = 353, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12 + }, + { /* act_tid: 5, wh_plus, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 23, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 365, + .result_bit_size = 128, + .result_num_fields = 26 + }, + { /* act_tid: 5, wh_plus, table: ext_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EXT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 23, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 391, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 12 + }, + { /* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 23, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 429, + .result_bit_size = 64, + .result_num_fields = 1 + }, + { /* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 24, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 430, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 3 + }, + { /* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 25, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 433, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 3 + }, + { /* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 26, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 436, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12 + }, + { /* act_tid: 6, wh_plus, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 26, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 448, + .result_bit_size = 128, + .result_num_fields = 26 + }, + { /* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EXT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 26, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 474, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 12 } }; -struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { - /* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */ +struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { + /* cond_reject: wh_plus, act_tid: 1 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_SRC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_DST + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP + }, + /* cond_execute: act_tid: 1, shared_mirror_record.rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 1, int_vtag_encap_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 3, act_modify_ipv4_src.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC + }, + /* cond_execute: act_tid: 3, act_modify_ipv4_dst.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST + }, + /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + /* cond_execute: act_tid: 4, ext_full_act_record.no_tag */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + /* cond_execute: act_tid: 4, ext_full_act_record.one_tag */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 5, act_modify_ipv4_src.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC + }, + /* cond_execute: act_tid: 5, act_modify_ipv4_dst.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST + }, + /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG + }, + /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG + } +}; + +struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { + /* act_tid: 1, wh_plus, table: shared_mirror_record.rd */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + } + }, + /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { + /* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} + }, + { + .description = "spare", + .field_bit_size = 80, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 1, wh_plus, table: int_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_NONE} + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "flow_cntr_ext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_NONE} + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spare", + .field_bit_size = 0, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ + { + .description = "act_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "copy", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ign_drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sp_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: int_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: ext_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "flow_cntr_ext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spare", + .field_bit_size = 0, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: mirror_tbl.wr */ + { + .description = "act_rec_ptr", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "copy", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ign_drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sp_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "mirror_id", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + (1 >> 8) & 0xff, + 1 & 0xff} + }, + /* act_tid: 3, wh_plus, table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */ + { + .description = "ipv4_addr", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff} + }, + /* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */ + { + .description = "ipv4_addr", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} + }, + /* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */ + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spare", + .field_bit_size = 80, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 3, wh_plus, table: int_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_L2} + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 3, wh_plus, table: ext_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "flow_cntr_ext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} + }, + { + .description = "encap_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_L2} + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spare", + .field_bit_size = 0, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */ + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} + }, + { + .description = "spare", + .field_bit_size = 80, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 4, wh_plus, table: int_full_act_record.0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "type", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "flow_cntr_ext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spare", + .field_bit_size = 0, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + }, + { + .description = "flow_cntr_ext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} + }, + { + .description = "spare", + .field_bit_size = 0, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */ + { + .description = "ipv4_addr", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff} + }, + /* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */ { - .description = "count", - .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "ipv4_addr", + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} }, - /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ + /* act_tid: 5, wh_plus, table: int_encap_mac_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -406,16 +3983,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_L2_EN_YES} }, { .description = "ecv_vtag_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_custom_en", @@ -429,25 +4006,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "vtag_tpid", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_de", @@ -459,11 +4034,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_pcp", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", @@ -472,7 +4045,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 1, wh_plus, table: int_full_act_record.0 */ + /* act_tid: 5, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -543,10 +4116,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .description = "encap_ptr", .field_bit_size = 11, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} }, { .description = "dst_ip_ptr", @@ -574,7 +4147,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", @@ -602,7 +4175,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", @@ -646,22 +4219,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_NONE} + ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", @@ -669,23 +4242,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", @@ -697,36 +4262,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "mirror", .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", @@ -742,7 +4287,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */ + /* act_tid: 5, wh_plus, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -819,16 +4364,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} }, { .description = "encap_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "dst_ip_ptr", @@ -856,7 +4405,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", @@ -884,7 +4433,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", @@ -894,122 +4443,270 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", - .field_bit_size = 1, + .description = "l3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "tl3_ttl_dec", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "decap_func", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_L2} + }, + { + .description = "vnic_or_vport", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + }, + { + .description = "pop_vlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spare", + .field_bit_size = 0, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */ { - .description = "tl3_rdir", - .field_bit_size = 1, + .description = "count", + .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */ { - .description = "l3_ttl_dec", - .field_bit_size = 1, + .description = "smac", + .field_bit_size = 48, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff} }, { - .description = "tl3_ttl_dec", - .field_bit_size = 1, + .description = "ipv4_src_addr", + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff} }, { - .description = "decap_func", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_NONE} + .description = "reserved", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */ { - .description = "vnic_or_vport", - .field_bit_size = 12, + .description = "smac", + .field_bit_size = 48, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff} }, { - .description = "pop_vlan", - .field_bit_size = 1, + .description = "ipv6_src_addr", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff} }, { - .description = "meter", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */ { - .description = "mirror", - .field_bit_size = 2, + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff} + ULP_WP_SYM_ECV_TUN_TYPE_VXLAN} }, { - .description = "drop", - .field_bit_size = 1, + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM} }, - /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ { - .description = "act_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "ecv_l3_type", + .field_bit_size = 3, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} }, { - .description = "enable", + .description = "ecv_l2_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -1018,42 +4715,85 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { 1} }, { - .description = "copy", + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} + }, + { + .description = "ecv_custom_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ign_drop", + .description = "ecv_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "reserved", - .field_bit_size = 2, + .description = "encap_l2_dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff} + }, + { + .description = "encap_vtag", + .field_bit_size = 0, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff} }, { - .description = "sp_ptr", - .field_bit_size = 11, + .description = "encap_ip", + .field_bit_size = 0, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff} }, - /* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */ { - .description = "count", - .field_bit_size = 64, + .description = "encap_udp", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff} + }, + { + .description = "encap_tun", + .field_bit_size = 0, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff, + (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff} }, - /* act_tid: 2, wh_plus, table: int_full_act_record.0 */ + /* act_tid: 6, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -1123,9 +4863,11 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", @@ -1203,8 +4945,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", @@ -1223,14 +4965,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - 1} + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", @@ -1253,7 +4990,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 2, wh_plus, table: ext_full_act_record.0 */ + /* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -1417,23 +5154,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", @@ -1445,14 +5174,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - 1} + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", @@ -1461,18 +5185,35 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 2, wh_plus, table: mirror_tbl.wr */ { - .description = "act_rec_ptr", - .field_bit_size = 16, + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + ULP_WP_SYM_ECV_TUN_TYPE_VXLAN} }, { - .description = "enable", + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM} + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} + }, + { + .description = "ecv_l2_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -1481,55 +5222,80 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { 1} }, { - .description = "copy", + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} + }, + { + .description = "ecv_custom_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ign_drop", + .description = "ecv_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "reserved", - .field_bit_size = 2, + .description = "encap_l2_dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff} + }, + { + .description = "encap_vtag", + .field_bit_size = 0, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff} }, { - .description = "sp_ptr", - .field_bit_size = 11, + .description = "encap_ip", + .field_bit_size = 0, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff} }, - /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ { - .description = "rid", + .description = "encap_udp", .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_CF_IDX_FID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FID & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff} }, { - .description = "mirror_id", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .description = "encap_tun", + .field_bit_size = 80, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - (1 >> 8) & 0xff, - 1 & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff} } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 6f5ab14ab1..f373e139b1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Dec 8 14:57:13 2020 */ +/* date: Thu Dec 17 17:35:03 2020 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -22,41 +22,41 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .cond_start_idx = 0, .cond_nums = 0 } }, - /* class_tid: 2, wh_plus, ingress */ + /* class_tid: 2, wh_plus, egress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 11, .start_tbl_idx = 11, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 6, + .cond_start_idx = 4, .cond_nums = 0 } }, - /* class_tid: 3, wh_plus, egress */ + /* class_tid: 3, wh_plus, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 8, - .start_tbl_idx = 17, + .start_tbl_idx = 22, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 6, + .cond_start_idx = 8, .cond_nums = 0 } }, /* class_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 8, - .start_tbl_idx = 25, + .num_tbls = 14, + .start_tbl_idx = 30, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 12, + .cond_start_idx = 9, .cond_nums = 0 } }, /* class_tid: 5, wh_plus, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 7, - .start_tbl_idx = 33, + .num_tbls = 9, + .start_tbl_idx = 44, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 14, @@ -65,39 +65,72 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 6, wh_plus, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 9, + .start_tbl_idx = 53, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 15, + .cond_nums = 0 } + }, + /* class_tid: 7, wh_plus, egress */ + [7] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 1, - .start_tbl_idx = 40, + .start_tbl_idx = 62, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 0 } } }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { + { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 2, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 0, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 0, + .ident_nums = 1 + }, { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 0, + .key_start_idx = 1, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, .result_start_idx = 0, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 0, + .ident_start_idx = 1, .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ @@ -107,81 +140,86 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 13, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 14, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .ident_start_idx = 1, + .ident_start_idx = 2, .ident_nums = 3 }, - { /* class_tid: 1, wh_plus, table: branch.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, + { /* class_tid: 1, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 4, + .cond_true_goto = 1, + .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */ + { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 2, + .cond_true_goto = 2, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 16, + .key_start_idx = 17, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, .result_start_idx = 13, .result_bit_size = 38, - .result_num_fields = 8, - .ident_start_idx = 4, + .result_num_fields = 17, + .ident_start_idx = 5, .ident_nums = 1 }, - { /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */ + { /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 59, + .key_start_idx = 60, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 21, + .result_start_idx = 30, .result_bit_size = 38, - .result_num_fields = 8, - .ident_start_idx = 5, + .result_num_fields = 17, + .ident_start_idx = 6, .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ @@ -191,858 +229,6669 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 102, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 103, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 29, + .result_start_idx = 47, .result_bit_size = 66, .result_num_fields = 5 }, - { /* class_tid: 1, wh_plus, table: em.ipv4_0 */ + { /* class_tid: 1, wh_plus, table: em.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 0, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 105, + .key_start_idx = 106, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, - .result_start_idx = 34, + .result_start_idx = 52, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: eem.ipv4_0 */ + { /* class_tid: 1, wh_plus, table: eem.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 3, - .cond_nums = 1 }, + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 115, + .key_start_idx = 116, .blob_key_bit_size = 448, .key_bit_size = 448, - .key_num_fields = 10, - .result_start_idx = 43, + .key_num_fields = 11, + .result_start_idx = 61, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: em.ipv6_0 */ + { /* class_tid: 1, wh_plus, table: em.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 4, - .cond_nums = 1 }, + .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 125, + .key_start_idx = 127, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, - .result_start_idx = 52, + .result_start_idx = 70, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: eem.ipv6_0 */ + { /* class_tid: 1, wh_plus, table: eem.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 5, - .cond_nums = 1 }, + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 136, + .key_start_idx = 138, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, - .result_start_idx = 61, + .result_start_idx = 79, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: branch.last */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, - .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH - }, - { /* class_tid: 2, wh_plus, table: int_full_act_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .cond_true_goto = 2, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 4, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 70, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 149, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 7, + .ident_nums = 1 }, { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, + .cond_start_idx = 5, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 147, + .key_start_idx = 150, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 96, + .result_start_idx = 88, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 6, + .ident_start_idx = 8, .ident_nums = 1 }, - { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 160, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 109, - .result_bit_size = 62, - .result_num_fields = 4 - }, - { /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, - .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 113, - .result_bit_size = 32, - .result_num_fields = 1 - }, - { /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, - .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 114, - .result_bit_size = 32, - .result_num_fields = 1 - }, - { /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, + .cond_start_idx = 5, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 115, - .result_bit_size = 32, - .result_num_fields = 1 + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 163, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 9, + .ident_nums = 3 }, - { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + { /* class_tid: 2, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 5, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 116, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ + { /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 2, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 161, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 142, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 7, - .ident_nums = 0 - }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 7, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 174, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 7, + .key_start_idx = 166, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 101, + .result_bit_size = 38, + .result_num_fields = 17, + .ident_start_idx = 12, .ident_nums = 1 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + { /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, - .cond_nums = 2 }, + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 7, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 175, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 155, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 8, + .key_start_idx = 209, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 118, + .result_bit_size = 38, + .result_num_fields = 17, + .ident_start_idx = 13, .ident_nums = 1 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, - .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 188, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 168, - .result_bit_size = 62, - .result_num_fields = 4 - }, - { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 7, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 172, - .result_bit_size = 32, - .result_num_fields = 1 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 252, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 135, + .result_bit_size = 66, + .result_num_fields = 5 }, - { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + { /* class_tid: 2, wh_plus, table: em.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 7, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 173, - .result_bit_size = 32, - .result_num_fields = 1 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 255, + .blob_key_bit_size = 176, + .key_bit_size = 176, + .key_num_fields = 10, + .result_start_idx = 140, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + { /* class_tid: 2, wh_plus, table: eem.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 0, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 8, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 174, - .result_bit_size = 32, - .result_num_fields = 1 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 265, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 11, + .result_start_idx = 149, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + { /* class_tid: 2, wh_plus, table: em.ipv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 0, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 8, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 189, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 9, - .ident_nums = 1 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 276, + .blob_key_bit_size = 416, + .key_bit_size = 416, + .key_num_fields = 11, + .result_start_idx = 158, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + { /* class_tid: 2, wh_plus, table: eem.ipv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 8, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 175, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .key_start_idx = 287, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 11, + .result_start_idx = 167, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */ + { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 8, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 187, + .result_start_idx = 176, .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .result_num_fields = 26 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 12, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 190, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 213, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 10, - .ident_nums = 0 - }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 13, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .key_start_idx = 203, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 226, - .result_bit_size = 62, - .result_num_fields = 4 - }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 8, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 230, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 298, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 14, + .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + { /* class_tid: 3, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 8, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 204, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 256, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 10, - .ident_nums = 0 + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 9, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 217, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 269, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 10, - .ident_nums = 0 - }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .execute_info = { - .cond_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 230, + .key_start_idx = 299, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 282, + .result_start_idx = 202, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 10, + .ident_start_idx = 14, .ident_nums = 1 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 9, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .key_start_idx = 243, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 312, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 295, + .result_start_idx = 215, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */ + { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 9, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 299, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 219, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */ + { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 9, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 300, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 220, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */ + { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 9, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .result_start_idx = 301, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 221, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 5, wh_plus, table: int_full_act_record.ing */ + { /* class_tid: 4, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 6, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 9, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* class_tid: 4, wh_plus, table: int_full_act_record.vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, - .result_start_idx = 302, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 222, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 313, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 15, + .ident_nums = 0 + }, + { /* class_tid: 4, wh_plus, table: control.1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 10, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, + .key_start_idx = 314, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 248, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 15, + .ident_nums = 0 + }, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 11, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 327, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 261, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 11, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 328, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 15, + .ident_nums = 0 + }, + { /* class_tid: 4, wh_plus, table: control.2 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 11, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 12, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 244, + .key_start_idx = 329, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 328, + .result_start_idx = 265, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 11, - .ident_nums = 0 + .ident_start_idx = 15, + .ident_nums = 1 + }, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 12, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 342, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 278, + .result_bit_size = 62, + .result_num_fields = 4 }, - { /* class_tid: 6, wh_plus, table: int_full_act_record.0 */ + { /* class_tid: 4, wh_plus, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { - .cond_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 14, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 341, + .result_start_idx = 282, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 - } -}; - -struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + { /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 14, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 308, + .result_bit_size = 32, + .result_num_fields = 1 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + { /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 14, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 309, + .result_bit_size = 32, + .result_num_fields = 1 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + { /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 14, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 310, + .result_bit_size = 32, + .result_num_fields = 1 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 14, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 343, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 16, + .ident_nums = 0 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + { /* class_tid: 5, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 14, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 344, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 311, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 16, + .ident_nums = 0 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 357, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 324, + .result_bit_size = 62, + .result_num_fields = 4 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + { /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 328, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12 }, - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + { /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 340, + .result_bit_size = 128, + .result_num_fields = 26 + }, + { /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 366, + .result_bit_size = 128, + .result_num_fields = 26 + }, + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 358, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 392, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 16, + .ident_nums = 0 + }, + { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 371, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 405, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 16, + .ident_nums = 0 + }, + { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 384, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 16, + .ident_nums = 0 + }, + { /* class_tid: 6, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 15, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 385, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 418, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 16, + .ident_nums = 1 + }, + { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 398, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 431, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 435, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 436, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 437, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 6, wh_plus, table: int_full_act_record.ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .result_start_idx = 438, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 + }, + { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .key_start_idx = 399, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 464, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 17, + .ident_nums = 0 + }, + { /* class_tid: 7, wh_plus, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 477, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { + /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* cond_execute: class_tid: 1, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + /* cond_execute: class_tid: 1, profile_tcam.ipv4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* cond_execute: class_tid: 1, em.ipv4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* cond_execute: class_tid: 2, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + /* cond_execute: class_tid: 2, profile_tcam.ipv4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* cond_execute: class_tid: 2, em.ipv4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* cond_execute: class_tid: 3, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + /* cond_execute: class_tid: 4, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + }, + /* cond_execute: class_tid: 4, control.1 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + /* cond_execute: class_tid: 4, control.2 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.wr */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + /* cond_execute: class_tid: 5, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + }, + /* cond_execute: class_tid: 6, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + } +}; + +struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV6} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: em.ipv4 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: eem.ipv4 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: em.ipv6 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: eem.ipv6 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV6} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 2, wh_plus, table: em.ipv4 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_ipv4.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 2, wh_plus, table: eem.ipv4 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "o_eth.dmac", + .field_bit_size = 48, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 2, wh_plus, table: em.ipv6 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .field_info_mask = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "o_ipv6.dst", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + } }, { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT - } -}; - -struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ - { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "o_ipv6.src", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "o_ipv6.src", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "o_eth.smac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "o_eth.smac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1050,7 +6899,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "mac0_addr", + .description = "o_eth.dmac", .field_bit_size = 48, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, @@ -1059,7 +6908,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "mac0_addr", + .description = "o_eth.dmac", .field_bit_size = 48, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, @@ -1070,51 +6919,57 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "em_profile_id", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 2, wh_plus, table: eem.ipv6 */ { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 35, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 35, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1122,15 +6977,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1138,51 +6993,83 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "o_l4.dport", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "o_l4.dport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "o_l4.sport", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .description = "o_l4.sport", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "o_ipv6.ip_proto", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1190,33 +7077,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "o_ipv6.dst", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "o_ipv6.dst", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "o_ipv6.src", + .field_bit_size = 128, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "o_ipv6.src", + .field_bit_size = 128, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "o_eth.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "o_eth.smac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1224,47 +7133,49 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "o_eth.dmac", + .field_bit_size = 48, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "o_eth.dmac", + .field_bit_size = 48, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1272,19 +7183,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "em_profile_id", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1292,27 +7204,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ { .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1320,48 +7232,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1369,8 +7264,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1378,26 +7273,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - ULP_WP_SYM_L4_HDR_VALID_YES} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, { .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1405,15 +7300,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1421,15 +7316,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1437,17 +7332,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1455,17 +7348,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1473,37 +7364,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1511,27 +7396,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", + .description = "key_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -1540,7 +7405,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_uc_mc_bc", + .description = "key_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -1549,8 +7414,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1558,17 +7423,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ { .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1576,17 +7444,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */ { .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1594,26 +7465,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */ { .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1621,15 +7493,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1637,15 +7509,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1653,8 +7525,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1662,24 +7534,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1687,15 +7561,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1703,15 +7577,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1719,17 +7593,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1737,15 +7609,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1753,15 +7625,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1769,15 +7641,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1785,15 +7657,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1801,24 +7675,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_hdr_error", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_hdr_error", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */ { .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1826,40 +7705,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ { .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1867,15 +7754,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1883,15 +7770,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1899,8 +7786,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -1908,24 +7795,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1933,15 +7822,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1949,35 +7838,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -1985,16 +7870,30 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "recycle_cnt", + .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "recycle_cnt", + .description = "tl2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2003,15 +7902,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2019,7 +7918,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "pkt_type_1", + .description = "key_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2028,7 +7927,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "pkt_type_1", + .description = "key_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2055,27 +7954,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ { .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2083,48 +7966,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ { .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2132,26 +7987,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - ULP_WP_SYM_L4_HDR_VALID_YES} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ { .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2159,15 +8015,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2175,15 +8031,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2191,8 +8047,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2200,28 +8056,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV6} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2229,37 +8083,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2267,36 +8115,30 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_uc_mc_bc", + .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_uc_mc_bc", + .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2305,16 +8147,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_hdr_type", + .description = "tl2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_hdr_type", + .description = "tl2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2323,17 +8163,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2341,8 +8179,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2350,58 +8188,66 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2409,33 +8255,36 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2443,31 +8292,35 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2475,17 +8328,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2493,15 +8344,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2509,15 +8360,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2525,31 +8376,35 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} } }, { .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2557,24 +8412,28 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2582,8 +8441,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2591,47 +8450,57 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_two_vtags", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_two_vtags", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2639,15 +8508,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2655,8 +8524,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2664,24 +8533,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2689,15 +8560,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2705,35 +8576,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2741,7 +8608,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "recycle_cnt", + .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2750,7 +8617,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "recycle_cnt", + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2759,23 +8644,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { - .description = "pkt_type_1", + .description = "key_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2784,7 +8673,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "pkt_type_1", + .description = "key_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -2811,11 +8700,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */ { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2823,8 +8712,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2832,28 +8740,40 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -2861,27 +8781,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "svif", + .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, - /* class_tid: 1, wh_plus, table: em.ipv4_0 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2889,17 +8808,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -2907,161 +8824,97 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_IP_PROTO_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_IP_PROTO_UDP} + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, 0xff} }, .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3069,28 +8922,28 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + 1} } }, + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { .field_info_mask = { - .description = "em_profile_id", + .description = "svif", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -3099,27 +8952,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "em_profile_id", + .description = "svif", .field_bit_size = 8, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, - /* class_tid: 1, wh_plus, table: eem.ipv4_0 */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 275, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 275, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3127,17 +8980,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3145,75 +8996,23 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - } - }, - { - .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", + .description = "svif", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -3222,84 +9021,58 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "o_ipv4.ip_proto", + .description = "svif", .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - ULP_WP_SYM_IP_PROTO_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_IP_PROTO_UDP} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3307,57 +9080,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 1, wh_plus, table: em.ipv6_0 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3365,17 +9128,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3383,2477 +9144,1474 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + 1} } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + }, + { + .description = "l2_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + { + .description = "allowed_pri", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_pri", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_tpid", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "bd_act_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byp_sp_lkup", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ + { + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + { + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + { + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff} + }, + { + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff} + }, + { + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .field_info_mask = { - .description = "o_ipv6.ip_proto", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "o_ipv6.ip_proto", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_IP_PROTO_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_IP_PROTO_UDP} - } + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .field_info_mask = { - .description = "o_ipv6.dst", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} - }, - .field_info_spec = { - .description = "o_ipv6.dst", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} - } + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ { - .field_info_mask = { - .description = "o_ipv6.src", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} - }, - .field_info_spec = { - .description = "o_ipv6.src", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} - } + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "o_eth.dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "o_eth.dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - } + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: eem.ipv6_0 */ { - .field_info_mask = { - .description = "spare", - .field_bit_size = 35, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spare", - .field_bit_size = 35, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, { - .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, { - .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - } + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} - } + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff} }, { - .field_info_mask = { - .description = "o_ipv6.ip_proto", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "o_ipv6.ip_proto", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_IP_PROTO_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_IP_PROTO_UDP} - } + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff} }, { - .field_info_mask = { - .description = "o_ipv6.dst", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} - }, - .field_info_spec = { - .description = "o_ipv6.dst", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} - } + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "o_ipv6.src", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} - }, - .field_info_spec = { - .description = "o_ipv6.src", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} - } + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 7} }, { - .field_info_mask = { - .description = "o_eth.dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "o_eth.dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - } + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "rid", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} - } + .description = "wm_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "flow_sig_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, + /* class_tid: 1, wh_plus, table: em.ipv4 */ { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "l1_cacheable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} - } + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ + /* class_tid: 1, wh_plus, table: eem.ipv4 */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_EEM_ACT_REC_INT} }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "act_rec_size", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (413 >> 8) & 0xff, + 413 & 0xff} }, { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "l1_cacheable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 1, wh_plus, table: em.ipv6 */ { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "l1_cacheable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 1, wh_plus, table: eem.ipv6 */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_EEM_ACT_REC_INT} }, { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_size", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (413 >> 8) & 0xff, + 413 & 0xff} }, { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "l1_cacheable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "prof_func_id", + .field_bit_size = 7, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "l2_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "parif", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, + BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_LOOPBACK_PARIF}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "allowed_pri", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "default_pri", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "default_tpid", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "bd_act_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff} }, { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "byp_sp_lkup", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff} }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff} }, { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 4} }, { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 2} - } + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} - } + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff} }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff} }, { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} - } + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 7} }, { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "rid", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} - } + .description = "wm_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "flow_sig_id", + .field_bit_size = 8, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, + /* class_tid: 2, wh_plus, table: em.ipv4 */ { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "l1_cacheable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} - } + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + /* class_tid: 2, wh_plus, table: eem.ipv4 */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_EEM_ACT_REC_INT} }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_size", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} - } + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (413 >> 8) & 0xff, + 413 & 0xff} }, { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "l1_cacheable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 2, wh_plus, table: em.ipv6 */ { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - } -}; - -struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + 3} }, { - .description = "l2_byp_lkup_en", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + 1} }, + /* class_tid: 2, wh_plus, table: eem.ipv6 */ { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "ext_flow_cntr", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "act_rec_int", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_EEM_ACT_REC_INT} }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "act_rec_size", + .field_bit_size = 5, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + }, + { + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (413 >> 8) & 0xff, + 413 & 0xff} }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", - .field_bit_size = 1, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "l1_cacheable", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -5861,259 +10619,270 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, + /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "flow_cntr_ptr", + .field_bit_size = 14, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "age_enable", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, + .description = "agg_cntr_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_key", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_search_en", + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask", + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dst_ip_ptr", .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (125 >> 8) & 0xff, - 125 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 5, + .description = "tcp_dst_port", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_search_en", - .field_bit_size = 1, + .description = "tcp_src_port", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, + .description = "meter_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */ { - .description = "wc_key_id", - .field_bit_size = 4, + .description = "l3_rdir", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "tl3_rdir", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_search_en", + .description = "l3_ttl_dec", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask", - .field_bit_size = 10, + .description = "tl3_ttl_dec", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (249 >> 8) & 0xff, - 249 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 5, + .description = "decap_func", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 7} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "vnic_or_vport", + .field_bit_size = 12, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { - .description = "em_search_en", + .description = "pop_vlan", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "meter", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ { - .description = "rid", - .field_bit_size = 32, + .description = "mirror", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "profile_tcam_index", - .field_bit_size = 10, + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wm_profile_id", - .field_bit_size = 8, + .description = "type", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - { - .description = "flow_sig_id", - .field_bit_size = 8, + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + { + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, - /* class_tid: 1, wh_plus, table: em.ipv4_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "prof_func_id", + .field_bit_size = 7, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { - .description = "ext_flow_cntr", + .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_int", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + { + .description = "allowed_pri", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "default_pri", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "key_size", - .field_bit_size = 9, + .description = "allowed_tpid", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", - .field_bit_size = 11, + .description = "default_tpid", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "bd_act_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", - .field_bit_size = 1, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "byp_sp_lkup", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -6121,416 +10890,404 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, wh_plus, table: eem.ipv4_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ext_flow_cntr", - .field_bit_size = 1, + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ { - .description = "act_rec_int", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "rid", + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - ULP_WP_SYM_EEM_ACT_REC_INT} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { - .description = "key_size", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (173 >> 8) & 0xff, - 173 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "reserved", - .field_bit_size = 11, + .description = "src_property_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 3} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 1} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 1, wh_plus, table: em.ipv6_0 */ + /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ { .description = "act_rec_ptr", - .field_bit_size = 33, + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 4, wh_plus, table: int_full_act_record.vfr */ { - .description = "ext_flow_cntr", - .field_bit_size = 1, + .description = "flow_cntr_ptr", + .field_bit_size = 14, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_int", + .description = "age_enable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "agg_cntr_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "key_size", - .field_bit_size = 9, + .description = "rate_cntr_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", - .field_bit_size = 11, + .description = "flow_cntr_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "tcpflags_key", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", + .description = "tcpflags_mir", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "tcpflags_match", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - /* class_tid: 1, wh_plus, table: eem.ipv6_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ext_flow_cntr", - .field_bit_size = 1, + .description = "encap_ptr", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_int", - .field_bit_size = 1, + .description = "dst_ip_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_EEM_ACT_REC_INT} - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "key_size", - .field_bit_size = 9, + .description = "tcp_dst_port", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (413 >> 8) & 0xff, - 413 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", - .field_bit_size = 11, + .description = "src_ip_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "tcp_src_port", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", - .field_bit_size = 1, + .description = "meter_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "l3_rdir", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - /* class_tid: 2, wh_plus, table: int_full_act_record.0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "age_enable", + .description = "tl3_rdir", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "agg_cntr_en", + .description = "l3_ttl_dec", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rate_cntr_en", + .description = "tl3_ttl_dec", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "flow_cntr_en", - .field_bit_size = 1, + .description = "decap_func", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_key", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "vnic_or_vport", + .field_bit_size = 12, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} }, { - .description = "tcpflags_mir", + .description = "pop_vlan", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_match", + .description = "meter", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "encap_ptr", - .field_bit_size = 11, + .description = "mirror", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "dst_ip_ptr", - .field_bit_size = 10, + .description = "drop", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_dst_port", - .field_bit_size = 16, + .description = "hit", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, + .description = "type", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */ { - .description = "tcp_src_port", + .description = "act_record_ptr", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, + .description = "reserved", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", + .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tl3_rdir", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} + }, + { + .description = "allowed_pri", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl_dec", - .field_bit_size = 1, + .description = "default_pri", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ttl_dec", - .field_bit_size = 1, + .description = "allowed_tpid", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "decap_func", - .field_bit_size = 4, + .description = "default_tpid", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vnic_or_vport", - .field_bit_size = 12, + .description = "bd_act_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + 1} }, { - .description = "pop_vlan", - .field_bit_size = 1, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter", + .description = "byp_sp_lkup", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "mirror", + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drop", - .field_bit_size = 1, + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */ { - .description = "hit", - .field_bit_size = 1, + .description = "rid", + .field_bit_size = 32, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "type", - .field_bit_size = 1, + .description = "src_property_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -6562,8 +11319,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", @@ -6630,7 +11387,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -6665,37 +11422,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ + /* class_tid: 4, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -6880,140 +11607,66 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */ + /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */ { - .description = "act_record_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "reserved", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 1} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */ { - .description = "parif", - .field_bit_size = 4, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */ { - .description = "bd_act_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 1} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ { - .description = "sp_rec_ptr", + .description = "act_record_ptr", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "reserved", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", @@ -7048,7 +11701,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "sp_rec_ptr", @@ -7080,7 +11735,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ { .description = "rid", .field_bit_size = 32, @@ -7102,11 +11757,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_property_ptr", @@ -7115,37 +11768,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */ + /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -7195,7 +11818,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "vtag_tpid", @@ -7237,7 +11862,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */ + /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -7425,138 +12050,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ - { - .description = "act_record_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "reserved", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ - { - .description = "rid", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} - }, - { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "src_property_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */ + /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -7743,7 +12237,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -7841,7 +12335,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -7939,7 +12433,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -7969,10 +12463,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .description = "parif", .field_bit_size = 4, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = {ULP_WP_SYM_LOOPBACK_PARIF & 0xff} }, { .description = "allowed_pri", @@ -8039,7 +12531,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { .description = "rid", .field_bit_size = 32, @@ -8074,7 +12566,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */ + /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -8084,7 +12576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */ + /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -8094,7 +12586,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */ + /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -8104,7 +12596,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 5, wh_plus, table: int_full_act_record.ing */ + /* class_tid: 6, wh_plus, table: int_full_act_record.ing */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -8289,7 +12781,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -8387,7 +12879,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: int_full_act_record.0 */ + /* class_tid: 7, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -8576,6 +13068,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }; struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { + /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -8587,10 +13086,10 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ { - .description = "profile_tcam_index", - .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .ident_bit_size = 10, - .ident_bit_pos = 32 + .description = "em_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 }, { .description = "flow_sig_id", @@ -8599,12 +13098,12 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_pos = 58 }, { - .description = "em_profile_id", - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 42 + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .ident_bit_size = 10, + .ident_bit_pos = 32 }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -8613,7 +13112,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -8622,6 +13121,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, + /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -8631,13 +13137,43 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ { - .description = "l2_cntxt_id", - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, + .description = "em_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, .ident_bit_pos = 42 }, + { + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 8, + .ident_bit_pos = 58 + }, + { + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .ident_bit_size = 10, + .ident_bit_pos = 32 + }, + /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ + { + .description = "em_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 28 + }, + /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ + { + .description = "em_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 28 + }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -8647,14 +13183,16 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ { - .description = "l2_cntxt_tcam_index", - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 32 + .ident_bit_pos = 0 }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */ + /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index c4ce5e45e3..2950097685 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -81,6 +81,8 @@ struct ulp_rte_parser_params { struct bnxt_ulp_context *ulp_ctx; uint32_t hdr_sig_id; uint32_t flow_sig_id; + uint32_t flow_pattern_id; + uint32_t act_pattern_id; }; /* Flow Parser Header Information Structure */ @@ -128,6 +130,7 @@ struct bnxt_ulp_class_match_info { uint8_t wc_pri; uint32_t hdr_sig_id; uint32_t flow_sig_id; + uint32_t flow_pattern_id; }; /* Flow Matcher templates Structure for class entries */ @@ -144,6 +147,7 @@ struct bnxt_ulp_act_match_info { struct ulp_rte_bitmap act_sig; uint32_t act_hid; uint32_t act_tid; + uint32_t act_pattern_id; }; /* Flow Matcher templates Structure for action entries */ @@ -160,7 +164,8 @@ struct bnxt_ulp_mapper_cond_list_info { enum bnxt_ulp_cond_list_opc cond_list_opcode; uint32_t cond_start_idx; uint32_t cond_nums; - uint32_t cond_goto; + int32_t cond_true_goto; + int32_t cond_false_goto; }; struct bnxt_ulp_template_device_tbls { From patchwork Sun May 30 08:59:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93585 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2D433A0524; Sun, 30 May 2021 11:05:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C1FFB411E7; Sun, 30 May 2021 11:01:38 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 474774114D for ; Sun, 30 May 2021 11:01:37 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id D9A2F7DAF; Sun, 30 May 2021 02:01:35 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com D9A2F7DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365296; bh=4/kqQxsR5/novxpKin6H4+M3AATTkd5SF4LKZzQKPqY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ktTpr3F/reQd1YXDHVSj9ygBlPzmpWWGOFkPsf6SwAHrVo2JY6PhddKY1YTlJjSIs wP7YS8D3DbmQf5y4W2WER1fMb2aDOOmG9C2pAsaOh3o0hl1/k4eW6lutisoVTAn2hX JOcd2brrAQz8ezZcghW+VqVSpAVKbYRIvY19gIjw= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:11 +0530 Message-Id: <20210530085929.29695-41-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 40/58] net/bnxt: add partial header field processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha For support for wild card TCAM, some of the header fields have to be partially written, hence this new opcode is added. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Ajit Kumar Khaparde Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 64 +++++++++++++------ .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 13 ++-- 2 files changed, 51 insertions(+), 26 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index c2e36823bf..555a5c5d91 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -927,7 +927,7 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, uint32_t val_size = 0, field_size = 0; uint64_t hdr_bit, act_bit, regval; uint16_t write_idx = blob->write_idx; - uint16_t idx, size_idx, bitlen; + uint16_t idx, size_idx, bitlen, offset; uint8_t *val = NULL; uint8_t tmpval[16]; uint8_t bit; @@ -1340,6 +1340,46 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, break; case BNXT_ULP_FIELD_SRC_REJECT: return -EINVAL; + case BNXT_ULP_FIELD_SRC_SUB_HF: + if (!ulp_operand_read(fld_src_oper, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + idx = tfp_be_to_cpu_16(idx); + /* get the index from the global field list */ + if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) { + BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", + idx); + return -EINVAL; + } + + /* get the offset next */ + if (!ulp_operand_read(&fld_src_oper[sizeof(uint16_t)], + (uint8_t *)&offset, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + offset = tfp_be_to_cpu_16(offset); + if ((offset + bitlen) > + ULP_BYTE_2_BITS(parms->hdr_field[bit].size) || + ULP_BITS_IS_BYTE_NOT_ALIGNED(offset)) { + BNXT_TF_DBG(ERR, "Hdr field[%s] oob\n", name); + return -EINVAL; + } + offset = ULP_BITS_2_BYTE_NR(offset); + + /* write the value into blob */ + if (is_key) + val = &parms->hdr_field[bit].spec[offset]; + else + val = &parms->hdr_field[bit].mask[offset]; + + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + break; default: BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n", name, fld_src, write_idx); @@ -1630,25 +1670,9 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, return rc; } -#define BNXT_ULP_WC_TCAM_SLICE_SIZE 80 /* internal function to post process the key/mask blobs for wildcard tcam tbl */ -static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob, - uint32_t len) +static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob) { - uint8_t mode[2] = {0x0, 0x0}; - uint32_t mode_len = len / BNXT_ULP_WC_TCAM_SLICE_SIZE; - uint32_t size, idx; - - /* Add the mode bits to the key and mask*/ - if (mode_len == 2) - mode[1] = 2; - else if (mode_len > 2) - mode[1] = 3; - - size = BNXT_ULP_WC_TCAM_SLICE_SIZE + ULP_BYTE_2_BITS(sizeof(mode)); - for (idx = 0; idx < mode_len; idx++) - ulp_blob_insert(blob, (size * idx), mode, - ULP_BYTE_2_BITS(sizeof(mode))); ulp_blob_perform_64B_word_swap(blob); ulp_blob_perform_64B_byte_swap(blob); } @@ -1736,8 +1760,8 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* For wild card tcam perform the post process to swap the blob */ if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) { - ulp_mapper_wc_tcam_tbl_post_process(&key, tbl->key_bit_size); - ulp_mapper_wc_tcam_tbl_post_process(&mask, tbl->key_bit_size); + ulp_mapper_wc_tcam_tbl_post_process(&key); + ulp_mapper_wc_tcam_tbl_post_process(&mask); } if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 7c6a93e4d5..e1ceb42f30 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -278,12 +278,13 @@ enum bnxt_ulp_field_src { BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 6, BNXT_ULP_FIELD_SRC_GLB_RF = 7, BNXT_ULP_FIELD_SRC_HF = 8, - BNXT_ULP_FIELD_SRC_HDR_BIT = 9, - BNXT_ULP_FIELD_SRC_ACT_BIT = 10, - BNXT_ULP_FIELD_SRC_FIELD_BIT = 11, - BNXT_ULP_FIELD_SRC_SKIP = 12, - BNXT_ULP_FIELD_SRC_REJECT = 13, - BNXT_ULP_FIELD_SRC_LAST = 14 + BNXT_ULP_FIELD_SRC_SUB_HF = 9, + BNXT_ULP_FIELD_SRC_HDR_BIT = 10, + BNXT_ULP_FIELD_SRC_ACT_BIT = 11, + BNXT_ULP_FIELD_SRC_FIELD_BIT = 12, + BNXT_ULP_FIELD_SRC_SKIP = 13, + BNXT_ULP_FIELD_SRC_REJECT = 14, + BNXT_ULP_FIELD_SRC_LAST = 15 }; enum bnxt_ulp_generic_tbl_opc { From patchwork Sun May 30 08:59:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93586 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AAC6AA0524; Sun, 30 May 2021 11:06:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3ADFA411ED; Sun, 30 May 2021 11:01:40 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id C2606411E8 for ; Sun, 30 May 2021 11:01:38 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 6127D7DC0; Sun, 30 May 2021 02:01:37 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 6127D7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365298; bh=LMSlKVgzbasLxWQP8PSgudLuNswo65EfOxJW3KO4VmI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I5Bz18ou8Hb+aug1x0BMDaGjRxpDzaYTt0zWjDCq6AzrqtwKIUBi6Qmqx54D/aAv5 pqKqmpH8Sp72yzjGn+q98Pv1KnGaI6LDiUTJcoinr4MQD/7gXj4Y3EXQYNFh8CZ9lT 5AjwOhMObdmnusXuB1ODVBSfgJVTNe64VrbETtKE= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:12 +0530 Message-Id: <20210530085929.29695-42-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 41/58] net/bnxt: add support for wild card pattern match X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The computational field is enabled for wild card pattern support. The template checks the computational field to add a flow as wild card entry or exact match entry. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Venkat Duvvuru Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 4 ++-- drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index f491405a9e..554123679e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -50,8 +50,8 @@ ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params, ULP_INDEX_BITMAP_SET(params->fld_bitmap.bits, idx); /* Not exact match */ if (!ulp_bitmap_is_ones(field->mask, field->size)) - ULP_BITMAP_SET(params->fld_bitmap.bits, - BNXT_ULP_MATCH_TYPE_BITMASK_WM); + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_WC_MATCH, 1); } else { ULP_INDEX_BITMAP_RESET(params->fld_bitmap.bits, idx); } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index e1ceb42f30..89cbbc0a9e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -180,7 +180,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_FID = 49, BNXT_ULP_CF_IDX_HDR_SIG_ID = 50, BNXT_ULP_CF_IDX_FLOW_SIG_ID = 51, - BNXT_ULP_CF_IDX_LAST = 52 + BNXT_ULP_CF_IDX_WC_MATCH = 52, + BNXT_ULP_CF_IDX_LAST = 53 }; enum bnxt_ulp_cond_list_opc { From patchwork Sun May 30 08:59:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93587 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 495C0A0524; Sun, 30 May 2021 11:06:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A2B85411F1; Sun, 30 May 2021 11:01:41 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 171E4411EA for ; Sun, 30 May 2021 11:01:40 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id DCED57DC2; Sun, 30 May 2021 02:01:38 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com DCED57DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365299; bh=W1fic9UKbYNsH1M1b9jftaz6dIZyZs+tonPHIMGNNd4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cc8c2L3GKBksZMbxCQvjUA/6p7ulYrd4yBDCxozYfSuNI0C5ojcolbALaXQmcKw/F 8bKqH3bG+Ae3wRbfZFDwwLlNC+zFjYbAwyHPLDBxTCAiBmKA5mZa5o2YkuyCLvVADy VwGubied9QrHZk4RybRObaFeKw/tYwutk9fSUVy8= From: Venkat Duvvuru To: dev@dpdk.org Cc: Venkat Duvvuru Date: Sun, 30 May 2021 14:29:13 +0530 Message-Id: <20210530085929.29695-43-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 42/58] net/bnxt: add support for GRE flows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch does the following to support GRE flows: 1. RTE_FLOW_ITEM_TYPE_ANY & RTE_FLOW_ITEM_TYPE_GRE processing 2. Calculate the absolute function ID from the logical VF ID passed as part of RTE_FLOW_ACTION_TYPE_VF action. 3. Move bnxt_get_bp API to bnxt_ethdev.c Signed-off-by: Venkat Duvvuru Reviewed-by: Somnath Kotur Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/bnxt.h | 1 + drivers/net/bnxt/bnxt_ethdev.c | 26 +++++++ drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 75 ++++++++++++++++++- drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 9 +++ drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 + 5 files changed, 110 insertions(+), 3 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 882f577848..d3ab57ab8d 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -982,6 +982,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); int32_t bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); +struct bnxt *bnxt_get_bp(uint16_t port); uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, enum bnxt_ulp_intf_type type); uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index a0e0ba5884..ebb326b0d1 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -4787,6 +4787,32 @@ static void bnxt_config_vf_req_fwd(struct bnxt *bp) BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); } +struct bnxt * +bnxt_get_bp(uint16_t port) +{ + struct bnxt *bp; + struct rte_eth_dev *dev; + + if (!rte_eth_dev_is_valid_port(port)) { + PMD_DRV_LOG(ERR, "Invalid port %d\n", port); + return NULL; + } + + dev = &rte_eth_devices[port]; + if (!is_bnxt_supported(dev)) { + PMD_DRV_LOG(ERR, "Device %d not supported\n", port); + return NULL; + } + + bp = (struct bnxt *)dev->data->dev_private; + if (!BNXT_TRUFLOW_EN(bp)) { + PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); + return NULL; + } + + return bp; +} + uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, enum bnxt_ulp_intf_type type) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 554123679e..5a2249f349 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1008,6 +1008,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } + if (proto == IPPROTO_GRE) + ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); + /* Update the field protocol hdr bitmap */ ulp_rte_l3_proto_type_update(params, proto, inner_flag); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); @@ -1146,6 +1149,9 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } + if (proto == IPPROTO_GRE) + ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); + /* Update the field protocol hdr bitmap */ ulp_rte_l3_proto_type_update(params, proto, inner_flag); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); @@ -1420,6 +1426,57 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item, return BNXT_TF_RC_SUCCESS; } +/* Function to handle the parsing of RTE Flow item GRE Header. */ +int32_t +ulp_rte_gre_hdr_handler(const struct rte_flow_item *item, + struct ulp_rte_parser_params *params) +{ + const struct rte_flow_item_gre *gre_spec = item->spec; + const struct rte_flow_item_gre *gre_mask = item->mask; + struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; + uint32_t idx = params->field_idx; + uint32_t size; + struct ulp_rte_hdr_field *field; + + if (!gre_spec && !gre_mask) { + BNXT_TF_DBG(ERR, "Parse Error: GRE item is invalid\n"); + return BNXT_TF_RC_ERROR; + } + + if (gre_spec) { + size = sizeof(gre_spec->c_rsvd0_ver); + field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], + &gre_spec->c_rsvd0_ver, + size); + size = sizeof(gre_spec->protocol); + field = ulp_rte_parser_fld_copy(field, + &gre_spec->protocol, + size); + } + if (gre_mask) { + ulp_rte_prsr_mask_copy(params, &idx, + &gre_mask->c_rsvd0_ver, + sizeof(gre_mask->c_rsvd0_ver)); + ulp_rte_prsr_mask_copy(params, &idx, + &gre_mask->protocol, + sizeof(gre_mask->protocol)); + } + /* Add number of GRE header elements */ + params->field_idx += BNXT_ULP_PROTO_HDR_GRE_NUM; + + /* Update the hdr_bitmap with GRE */ + ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); + return BNXT_TF_RC_SUCCESS; +} + +/* Function to handle the parsing of RTE Flow item ANY. */ +int32_t +ulp_rte_item_any_handler(const struct rte_flow_item *item __rte_unused, + struct ulp_rte_parser_params *params __rte_unused) +{ + return BNXT_TF_RC_SUCCESS; +} + /* Function to handle the parsing of RTE Flow item void Header */ int32_t ulp_rte_void_hdr_handler(const struct rte_flow_item *item __rte_unused, @@ -1879,8 +1936,9 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item, struct ulp_rte_parser_params *params) { const struct rte_flow_action_vf *vf_action; - uint32_t ifindex; enum bnxt_ulp_intf_type intf_type; + uint32_t ifindex; + struct bnxt *bp; vf_action = action_item->conf; if (!vf_action) { @@ -1893,12 +1951,23 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item, return BNXT_TF_RC_PARSE_ERR; } - /* Check the port is VF port */ - if (ulp_port_db_dev_func_id_to_ulp_index(params->ulp_ctx, vf_action->id, + bp = bnxt_get_bp(params->port_id); + if (bp == NULL) { + BNXT_TF_DBG(ERR, "Invalid bp\n"); + return BNXT_TF_RC_ERROR; + } + + /* vf_action->id is a logical number which in this case is an + * offset from the first VF. So, to get the absolute VF id, the + * offset must be added to the absolute first vf id of that port. + */ + if (ulp_port_db_dev_func_id_to_ulp_index(params->ulp_ctx, + bp->first_vf_id + vf_action->id, &ifindex)) { BNXT_TF_DBG(ERR, "VF is not valid interface\n"); return BNXT_TF_RC_ERROR; } + /* Check the port is VF port */ intf_type = ulp_port_db_port_type_get(params->ulp_ctx, ifindex); if (intf_type != BNXT_ULP_INTF_TYPE_VF && intf_type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index 7996317903..cb9ae02371 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -126,6 +126,15 @@ int32_t ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_parser_params *params); +/* Function to handle the parsing of RTE Flow item GRE Header. */ +int32_t +ulp_rte_gre_hdr_handler(const struct rte_flow_item *item, + struct ulp_rte_parser_params *params); + +int32_t +ulp_rte_item_any_handler(const struct rte_flow_item *item __rte_unused, + struct ulp_rte_parser_params *params __rte_unused); + /* Function to handle the parsing of RTE Flow item void Header. */ int32_t ulp_rte_void_hdr_handler(const struct rte_flow_item *item, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 2950097685..5150ed2b07 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -27,6 +27,7 @@ #define BNXT_ULP_PROTO_HDR_UDP_NUM 4 #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 +#define BNXT_ULP_PROTO_HDR_GRE_NUM 6 #define BNXT_ULP_PROTO_HDR_MAX 128 #define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1 @@ -76,6 +77,7 @@ struct ulp_rte_parser_params { uint32_t parent_flow; uint32_t parent_fid; uint16_t func_id; + uint16_t port_id; uint32_t class_id; uint32_t act_tmpl; struct bnxt_ulp_context *ulp_ctx; From patchwork Sun May 30 08:59:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93588 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2DD29A0524; Sun, 30 May 2021 11:06:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5BB674113A; Sun, 30 May 2021 11:01:44 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 95620411EA for ; Sun, 30 May 2021 11:01:41 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 328047DAF; Sun, 30 May 2021 02:01:39 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 328047DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365301; bh=wdO6zqrRuwTAA45TtOVcxPtTf8DIBoHeCtHyEbj+Wms=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S0TlVIPLih55SrLby8GrSwel9JeN3Ju051qEn8sdV1HNhlmpCI9mMnWd3h/C8jkyZ JortRqDJ1IZRGTg3MPzHlSQjwIs9B8nhA6Ns/22tPRqWWCJHB4PrMlAqtU9g0tpJiW ma6mJ9RZaMSM/n5mMiA6KLbC9eQFe28rMPN62LxY= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:14 +0530 Message-Id: <20210530085929.29695-44-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 43/58] net/bnxt: enable extended exact match support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The templates are updated to enable the extended exact match table support. As part of this change, the action record size of the action has to be calculated dynamically so it can be included in the match table. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Ajit Kumar Khaparde Reviewed-by: Randy Schacher Reviewed-by: Farah Smith --- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 12 + drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 87 +- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 15 +- .../net/bnxt/tf_ulp/ulp_template_db_field.h | 2 + drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 712 ++++++------- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 141 ++- .../tf_ulp/ulp_template_db_wh_plus_class.c | 936 +++++++++++++----- 7 files changed, 1283 insertions(+), 622 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 555a5c5d91..bd28556a4b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -2042,6 +2042,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, bool alloc = false; bool write = false; bool search = false; + uint64_t act_rec_size; /* use the max size if encap is enabled */ if (tbl->encap_num_fields) @@ -2286,6 +2287,17 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, sparms.idx, rc); goto error; } + + /* Calculate action record size */ + if (tbl->resource_type == TF_TBL_TYPE_EXT) { + act_rec_size = (ULP_BITS_2_BYTE_NR(tmplen) + 15) / 16; + act_rec_size--; + if (ulp_regfile_write(parms->regfile, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE, + tfp_cpu_to_be_64(act_rec_size))) + BNXT_TF_DBG(ERR, + "Failed write the act rec size\n"); + } } /* Link the resource to the flow in the flow db */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index 8e482700e9..c848b70777 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Dec 17 19:43:07 2020 */ +/* date: Tue Jan 26 15:51:49 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -106,12 +106,14 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [1] = { .act_hid = BNXT_ULP_ACT_HID_0000, + .act_pattern_id = 0, .act_sig = { .bits = BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [2] = { .act_hid = BNXT_ULP_ACT_HID_0001, + .act_pattern_id = 1, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -119,6 +121,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [3] = { .act_hid = BNXT_ULP_ACT_HID_0400, + .act_pattern_id = 2, .act_sig = { .bits = BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -126,6 +129,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [4] = { .act_hid = BNXT_ULP_ACT_HID_01ab, + .act_pattern_id = 3, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -133,6 +137,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [5] = { .act_hid = BNXT_ULP_ACT_HID_0010, + .act_pattern_id = 4, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -140,6 +145,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [6] = { .act_hid = BNXT_ULP_ACT_HID_05ab, + .act_pattern_id = 5, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -148,6 +154,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [7] = { .act_hid = BNXT_ULP_ACT_HID_01bb, + .act_pattern_id = 6, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -156,6 +163,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [8] = { .act_hid = BNXT_ULP_ACT_HID_0002, + .act_pattern_id = 7, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -163,6 +171,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [9] = { .act_hid = BNXT_ULP_ACT_HID_0003, + .act_pattern_id = 8, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DROP | @@ -171,6 +180,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [10] = { .act_hid = BNXT_ULP_ACT_HID_0402, + .act_pattern_id = 9, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -179,6 +189,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [11] = { .act_hid = BNXT_ULP_ACT_HID_01ad, + .act_pattern_id = 10, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -187,6 +198,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [12] = { .act_hid = BNXT_ULP_ACT_HID_0012, + .act_pattern_id = 11, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -195,6 +207,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [13] = { .act_hid = BNXT_ULP_ACT_HID_05ad, + .act_pattern_id = 12, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -204,6 +217,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [14] = { .act_hid = BNXT_ULP_ACT_HID_01bd, + .act_pattern_id = 13, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -213,6 +227,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [15] = { .act_hid = BNXT_ULP_ACT_HID_0613, + .act_pattern_id = 14, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DROP | @@ -221,6 +236,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [16] = { .act_hid = BNXT_ULP_ACT_HID_02a9, + .act_pattern_id = 15, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -229,6 +245,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [17] = { .act_hid = BNXT_ULP_ACT_HID_0054, + .act_pattern_id = 16, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -237,6 +254,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [18] = { .act_hid = BNXT_ULP_ACT_HID_0622, + .act_pattern_id = 17, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -245,6 +263,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [19] = { .act_hid = BNXT_ULP_ACT_HID_0454, + .act_pattern_id = 18, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -254,6 +273,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [20] = { .act_hid = BNXT_ULP_ACT_HID_0064, + .act_pattern_id = 19, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -263,6 +283,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [21] = { .act_hid = BNXT_ULP_ACT_HID_0614, + .act_pattern_id = 20, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -271,6 +292,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [22] = { .act_hid = BNXT_ULP_ACT_HID_0615, + .act_pattern_id = 21, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -280,6 +302,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [23] = { .act_hid = BNXT_ULP_ACT_HID_02ab, + .act_pattern_id = 22, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -289,6 +312,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [24] = { .act_hid = BNXT_ULP_ACT_HID_0056, + .act_pattern_id = 23, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -298,6 +322,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [25] = { .act_hid = BNXT_ULP_ACT_HID_0624, + .act_pattern_id = 24, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -307,6 +332,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [26] = { .act_hid = BNXT_ULP_ACT_HID_0456, + .act_pattern_id = 25, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -317,6 +343,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [27] = { .act_hid = BNXT_ULP_ACT_HID_0066, + .act_pattern_id = 26, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -327,6 +354,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [28] = { .act_hid = BNXT_ULP_ACT_HID_048d, + .act_pattern_id = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED | BNXT_ULP_ACT_BIT_SAMPLE | @@ -335,6 +363,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [29] = { .act_hid = BNXT_ULP_ACT_HID_048f, + .act_pattern_id = 1, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED | BNXT_ULP_ACT_BIT_SAMPLE | @@ -344,6 +373,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [30] = { .act_hid = BNXT_ULP_ACT_HID_04bc, + .act_pattern_id = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -351,6 +381,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [31] = { .act_hid = BNXT_ULP_ACT_HID_00a9, + .act_pattern_id = 1, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -359,6 +390,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [32] = { .act_hid = BNXT_ULP_ACT_HID_020f, + .act_pattern_id = 2, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -366,6 +398,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [33] = { .act_hid = BNXT_ULP_ACT_HID_04a9, + .act_pattern_id = 3, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -375,6 +408,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [34] = { .act_hid = BNXT_ULP_ACT_HID_01fc, + .act_pattern_id = 4, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -385,6 +419,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [35] = { .act_hid = BNXT_ULP_ACT_HID_04be, + .act_pattern_id = 5, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -393,6 +428,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [36] = { .act_hid = BNXT_ULP_ACT_HID_00ab, + .act_pattern_id = 6, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -402,6 +438,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [37] = { .act_hid = BNXT_ULP_ACT_HID_0211, + .act_pattern_id = 7, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -410,6 +447,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [38] = { .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_pattern_id = 8, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -420,6 +458,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [39] = { .act_hid = BNXT_ULP_ACT_HID_01fe, + .act_pattern_id = 9, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -431,6 +470,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [40] = { .act_hid = BNXT_ULP_ACT_HID_0667, + .act_pattern_id = 10, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -439,6 +479,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [41] = { .act_hid = BNXT_ULP_ACT_HID_0254, + .act_pattern_id = 11, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -448,6 +489,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [42] = { .act_hid = BNXT_ULP_ACT_HID_03ba, + .act_pattern_id = 12, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -456,6 +498,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [43] = { .act_hid = BNXT_ULP_ACT_HID_0654, + .act_pattern_id = 13, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -466,6 +509,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [44] = { .act_hid = BNXT_ULP_ACT_HID_03a7, + .act_pattern_id = 14, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -477,6 +521,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [45] = { .act_hid = BNXT_ULP_ACT_HID_0669, + .act_pattern_id = 15, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -486,6 +531,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [46] = { .act_hid = BNXT_ULP_ACT_HID_0256, + .act_pattern_id = 16, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -496,6 +542,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [47] = { .act_hid = BNXT_ULP_ACT_HID_03bc, + .act_pattern_id = 17, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -505,6 +552,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [48] = { .act_hid = BNXT_ULP_ACT_HID_0656, + .act_pattern_id = 18, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -516,6 +564,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [49] = { .act_hid = BNXT_ULP_ACT_HID_03a9, + .act_pattern_id = 19, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -528,12 +577,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [50] = { .act_hid = BNXT_ULP_ACT_HID_021b, + .act_pattern_id = 0, .act_sig = { .bits = BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, [51] = { .act_hid = BNXT_ULP_ACT_HID_021c, + .act_pattern_id = 1, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -541,6 +592,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [52] = { .act_hid = BNXT_ULP_ACT_HID_021e, + .act_pattern_id = 2, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_ACT_BIT_COUNT | @@ -549,6 +601,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [53] = { .act_hid = BNXT_ULP_ACT_HID_063f, + .act_pattern_id = 3, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_VLAN_PCP | BNXT_ULP_ACT_BIT_SET_VLAN_VID | @@ -558,6 +611,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [54] = { .act_hid = BNXT_ULP_ACT_HID_0510, + .act_pattern_id = 4, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_VLAN_VID | BNXT_ULP_ACT_BIT_PUSH_VLAN | @@ -566,6 +620,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [55] = { .act_hid = BNXT_ULP_ACT_HID_03c6, + .act_pattern_id = 5, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -573,6 +628,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [56] = { .act_hid = BNXT_ULP_ACT_HID_0082, + .act_pattern_id = 6, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_VLAN_PCP | @@ -583,6 +639,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [57] = { .act_hid = BNXT_ULP_ACT_HID_06bb, + .act_pattern_id = 7, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_VLAN_VID | @@ -592,6 +649,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [58] = { .act_hid = BNXT_ULP_ACT_HID_021d, + .act_pattern_id = 8, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -599,6 +657,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [59] = { .act_hid = BNXT_ULP_ACT_HID_0641, + .act_pattern_id = 9, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_VLAN_PCP | @@ -609,6 +668,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [60] = { .act_hid = BNXT_ULP_ACT_HID_0512, + .act_pattern_id = 10, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_VLAN_VID | @@ -618,6 +678,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [61] = { .act_hid = BNXT_ULP_ACT_HID_03c8, + .act_pattern_id = 11, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -626,6 +687,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [62] = { .act_hid = BNXT_ULP_ACT_HID_0084, + .act_pattern_id = 12, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -637,6 +699,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [63] = { .act_hid = BNXT_ULP_ACT_HID_06bd, + .act_pattern_id = 13, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -647,6 +710,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [64] = { .act_hid = BNXT_ULP_ACT_HID_06d7, + .act_pattern_id = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -654,6 +718,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [65] = { .act_hid = BNXT_ULP_ACT_HID_02c4, + .act_pattern_id = 1, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -662,6 +727,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [66] = { .act_hid = BNXT_ULP_ACT_HID_042a, + .act_pattern_id = 2, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -669,6 +735,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [67] = { .act_hid = BNXT_ULP_ACT_HID_06c4, + .act_pattern_id = 3, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -678,6 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [68] = { .act_hid = BNXT_ULP_ACT_HID_0417, + .act_pattern_id = 4, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -688,6 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [69] = { .act_hid = BNXT_ULP_ACT_HID_06d9, + .act_pattern_id = 5, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -696,6 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [70] = { .act_hid = BNXT_ULP_ACT_HID_02c6, + .act_pattern_id = 6, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -705,6 +775,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [71] = { .act_hid = BNXT_ULP_ACT_HID_042c, + .act_pattern_id = 7, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -713,6 +784,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [72] = { .act_hid = BNXT_ULP_ACT_HID_06c6, + .act_pattern_id = 8, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -723,6 +795,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [73] = { .act_hid = BNXT_ULP_ACT_HID_0419, + .act_pattern_id = 9, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -734,6 +807,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [74] = { .act_hid = BNXT_ULP_ACT_HID_0119, + .act_pattern_id = 10, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -742,6 +816,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [75] = { .act_hid = BNXT_ULP_ACT_HID_046f, + .act_pattern_id = 11, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -751,6 +826,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [76] = { .act_hid = BNXT_ULP_ACT_HID_05d5, + .act_pattern_id = 12, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -759,6 +835,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [77] = { .act_hid = BNXT_ULP_ACT_HID_0106, + .act_pattern_id = 13, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -769,6 +846,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [78] = { .act_hid = BNXT_ULP_ACT_HID_05c2, + .act_pattern_id = 14, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -780,6 +858,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [79] = { .act_hid = BNXT_ULP_ACT_HID_011b, + .act_pattern_id = 15, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -789,6 +868,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [80] = { .act_hid = BNXT_ULP_ACT_HID_0471, + .act_pattern_id = 16, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -799,6 +879,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [81] = { .act_hid = BNXT_ULP_ACT_HID_05d7, + .act_pattern_id = 17, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -808,6 +889,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [82] = { .act_hid = BNXT_ULP_ACT_HID_0108, + .act_pattern_id = 18, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -819,6 +901,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [83] = { .act_hid = BNXT_ULP_ACT_HID_05c4, + .act_pattern_id = 19, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -831,6 +914,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [84] = { .act_hid = BNXT_ULP_ACT_HID_00a2, + .act_pattern_id = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_ENCAP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -838,6 +922,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { }, [85] = { .act_hid = BNXT_ULP_ACT_HID_00a4, + .act_pattern_id = 1, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_ENCAP | BNXT_ULP_ACT_BIT_COUNT | diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 89cbbc0a9e..418f6389eb 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,12 +3,12 @@ * All rights reserved. */ -/* date: Thu Dec 17 19:43:07 2020 */ +/* date: Tue Jan 26 15:51:49 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 32 +#define BNXT_ULP_REGFILE_MAX_SZ 34 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 #define BNXT_ULP_GEN_TBL_MAX_SZ 6 @@ -30,13 +30,13 @@ #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 -#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5593 +#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595 #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8 #define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 63 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 412 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 410 #define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 17 #define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 503 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 16 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 18 #define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7 #define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38 #define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192 @@ -392,7 +392,9 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_HDR_SIG_ID = 29, BNXT_ULP_RF_IDX_FLOW_SIG_ID = 30, BNXT_ULP_RF_IDX_RID = 31, - BNXT_ULP_RF_IDX_LAST = 32 + BNXT_ULP_RF_IDX_WC_KEY_ID_0 = 32, + BNXT_ULP_RF_IDX_EM_KEY_ID_0 = 33, + BNXT_ULP_RF_IDX_LAST = 34 }; enum bnxt_ulp_tcam_tbl_opc { @@ -4941,4 +4943,5 @@ enum bnxt_ulp_df_tpl { BNXT_ULP_DF_TPL_VF_TO_VFREP = 6, BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7 }; + #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h index 4daa9f2031..f7dd91626a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h @@ -17,6 +17,8 @@ enum bnxt_ulp_glb_hf { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC, BNXT_ULP_GLB_HF_ID_O_ETH_TYPE, BNXT_ULP_GLB_HF_ID_I_ETH_TYPE, + BNXT_ULP_GLB_HF_ID_T_GRE_VER, + BNXT_ULP_GLB_HF_ID_T_GRE_PROTO_TYPE, BNXT_ULP_GLB_HF_ID_O_IPV4_VER, BNXT_ULP_GLB_HF_ID_I_IPV4_VER, BNXT_ULP_GLB_HF_ID_O_IPV4_TOS, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 64cf6534b9..26e0ddfb1e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -316,476 +316,476 @@ uint8_t ulp_glb_field_tbl[] = { [2050] = 2, [2052] = 3, [2054] = 4, - [2056] = 5, - [2058] = 6, - [2060] = 7, - [2062] = 8, - [2064] = 9, - [2066] = 10, - [2068] = 11, - [2070] = 12, - [2072] = 13, - [2074] = 14, + [2058] = 5, + [2060] = 6, + [2062] = 7, + [2064] = 8, + [2066] = 9, + [2068] = 10, + [2070] = 11, + [2072] = 12, + [2074] = 13, + [2076] = 14, [2176] = 0, [2177] = 1, [2178] = 2, [2180] = 3, [2182] = 4, - [2184] = 5, - [2186] = 6, - [2188] = 7, - [2190] = 8, - [2192] = 9, - [2194] = 10, - [2196] = 11, - [2198] = 12, - [2200] = 13, - [2202] = 14, - [2230] = 15, - [2232] = 16, - [2234] = 17, - [2236] = 18, - [2238] = 19, - [2240] = 20, - [2242] = 21, - [2244] = 22, - [2246] = 23, + [2186] = 5, + [2188] = 6, + [2190] = 7, + [2192] = 8, + [2194] = 9, + [2196] = 10, + [2198] = 11, + [2200] = 12, + [2202] = 13, + [2204] = 14, + [2232] = 15, + [2234] = 16, + [2236] = 17, + [2238] = 18, + [2240] = 19, + [2242] = 20, + [2244] = 21, + [2246] = 22, + [2248] = 23, [2304] = 0, [2305] = 1, [2306] = 2, [2308] = 3, [2310] = 4, - [2312] = 5, - [2314] = 6, - [2316] = 7, - [2318] = 8, - [2320] = 9, - [2322] = 10, - [2324] = 11, - [2326] = 12, - [2328] = 13, - [2330] = 14, - [2376] = 15, - [2378] = 16, - [2380] = 17, - [2382] = 18, + [2314] = 5, + [2316] = 6, + [2318] = 7, + [2320] = 8, + [2322] = 9, + [2324] = 10, + [2326] = 11, + [2328] = 12, + [2330] = 13, + [2332] = 14, + [2378] = 15, + [2380] = 16, + [2382] = 17, + [2384] = 18, [2432] = 0, [2433] = 1, [2434] = 2, [2436] = 3, [2438] = 4, - [2460] = 5, - [2462] = 6, - [2464] = 7, - [2466] = 8, - [2468] = 9, - [2470] = 10, - [2472] = 11, - [2474] = 12, + [2462] = 5, + [2464] = 6, + [2466] = 7, + [2468] = 8, + [2470] = 9, + [2472] = 10, + [2474] = 11, + [2476] = 12, [2560] = 0, [2561] = 1, [2562] = 2, [2564] = 3, [2566] = 4, - [2588] = 5, - [2590] = 6, - [2592] = 7, - [2594] = 8, - [2596] = 9, - [2598] = 10, - [2600] = 11, - [2602] = 12, - [2614] = 13, - [2616] = 14, - [2618] = 15, - [2620] = 16, - [2622] = 17, - [2624] = 18, - [2626] = 19, - [2628] = 20, - [2630] = 21, + [2590] = 5, + [2592] = 6, + [2594] = 7, + [2596] = 8, + [2598] = 9, + [2600] = 10, + [2602] = 11, + [2604] = 12, + [2616] = 13, + [2618] = 14, + [2620] = 15, + [2622] = 16, + [2624] = 17, + [2626] = 18, + [2628] = 19, + [2630] = 20, + [2632] = 21, [2688] = 0, [2689] = 1, [2690] = 2, [2692] = 3, [2694] = 4, - [2716] = 5, - [2718] = 6, - [2720] = 7, - [2722] = 8, - [2724] = 9, - [2726] = 10, - [2728] = 11, - [2730] = 12, - [2760] = 13, - [2762] = 14, - [2764] = 15, - [2766] = 16, + [2718] = 5, + [2720] = 6, + [2722] = 7, + [2724] = 8, + [2726] = 9, + [2728] = 10, + [2730] = 11, + [2732] = 12, + [2762] = 13, + [2764] = 14, + [2766] = 15, + [2768] = 16, [2816] = 0, [2817] = 1, [2818] = 2, [2820] = 3, [2822] = 4, - [2824] = 8, - [2826] = 9, - [2828] = 10, - [2830] = 11, - [2832] = 12, - [2834] = 13, - [2836] = 14, - [2838] = 15, - [2840] = 16, - [2842] = 17, - [2896] = 5, - [2900] = 6, - [2904] = 7, + [2826] = 8, + [2828] = 9, + [2830] = 10, + [2832] = 11, + [2834] = 12, + [2836] = 13, + [2838] = 14, + [2840] = 15, + [2842] = 16, + [2844] = 17, + [2898] = 5, + [2902] = 6, + [2906] = 7, [2944] = 0, [2945] = 1, [2946] = 2, [2948] = 3, [2950] = 4, - [2952] = 8, - [2954] = 9, - [2956] = 10, - [2958] = 11, - [2960] = 12, - [2962] = 13, - [2964] = 14, - [2966] = 15, - [2968] = 16, - [2970] = 17, - [2998] = 18, - [3000] = 19, - [3002] = 20, - [3004] = 21, - [3006] = 22, - [3008] = 23, - [3010] = 24, - [3012] = 25, - [3014] = 26, - [3024] = 5, - [3028] = 6, - [3032] = 7, + [2954] = 8, + [2956] = 9, + [2958] = 10, + [2960] = 11, + [2962] = 12, + [2964] = 13, + [2966] = 14, + [2968] = 15, + [2970] = 16, + [2972] = 17, + [3000] = 18, + [3002] = 19, + [3004] = 20, + [3006] = 21, + [3008] = 22, + [3010] = 23, + [3012] = 24, + [3014] = 25, + [3016] = 26, + [3026] = 5, + [3030] = 6, + [3034] = 7, [3072] = 0, [3073] = 1, [3074] = 2, [3076] = 3, [3078] = 4, - [3080] = 8, - [3082] = 9, - [3084] = 10, - [3086] = 11, - [3088] = 12, - [3090] = 13, - [3092] = 14, - [3094] = 15, - [3096] = 16, - [3098] = 17, - [3144] = 18, - [3146] = 19, - [3148] = 20, - [3150] = 21, - [3152] = 5, - [3156] = 6, - [3160] = 7, + [3082] = 8, + [3084] = 9, + [3086] = 10, + [3088] = 11, + [3090] = 12, + [3092] = 13, + [3094] = 14, + [3096] = 15, + [3098] = 16, + [3100] = 17, + [3146] = 18, + [3148] = 19, + [3150] = 20, + [3152] = 21, + [3154] = 5, + [3158] = 6, + [3162] = 7, [3200] = 0, [3201] = 1, [3202] = 2, [3204] = 3, [3206] = 4, - [3228] = 8, - [3230] = 9, - [3232] = 10, - [3234] = 11, - [3236] = 12, - [3238] = 13, - [3240] = 14, - [3242] = 15, - [3280] = 5, - [3284] = 6, - [3288] = 7, + [3230] = 8, + [3232] = 9, + [3234] = 10, + [3236] = 11, + [3238] = 12, + [3240] = 13, + [3242] = 14, + [3244] = 15, + [3282] = 5, + [3286] = 6, + [3290] = 7, [3328] = 0, [3329] = 1, [3330] = 2, [3332] = 3, [3334] = 4, - [3356] = 8, - [3358] = 9, - [3360] = 10, - [3362] = 11, - [3364] = 12, - [3366] = 13, - [3368] = 14, - [3370] = 15, - [3382] = 16, - [3384] = 17, - [3386] = 18, - [3388] = 19, - [3390] = 20, - [3392] = 21, - [3394] = 22, - [3396] = 23, - [3398] = 24, - [3408] = 5, - [3412] = 6, - [3416] = 7, + [3358] = 8, + [3360] = 9, + [3362] = 10, + [3364] = 11, + [3366] = 12, + [3368] = 13, + [3370] = 14, + [3372] = 15, + [3384] = 16, + [3386] = 17, + [3388] = 18, + [3390] = 19, + [3392] = 20, + [3394] = 21, + [3396] = 22, + [3398] = 23, + [3400] = 24, + [3410] = 5, + [3414] = 6, + [3418] = 7, [3456] = 0, [3457] = 1, [3458] = 2, [3460] = 3, [3462] = 4, - [3484] = 8, - [3486] = 9, - [3488] = 10, - [3490] = 11, - [3492] = 12, - [3494] = 13, - [3496] = 14, - [3498] = 15, - [3528] = 16, - [3530] = 17, - [3532] = 18, - [3534] = 19, - [3536] = 5, - [3540] = 6, - [3544] = 7, + [3486] = 8, + [3488] = 9, + [3490] = 10, + [3492] = 11, + [3494] = 12, + [3496] = 13, + [3498] = 14, + [3500] = 15, + [3530] = 16, + [3532] = 17, + [3534] = 18, + [3536] = 19, + [3538] = 5, + [3542] = 6, + [3546] = 7, [4096] = 0, [4097] = 1, [4098] = 2, [4100] = 3, [4102] = 4, - [4104] = 5, - [4106] = 6, - [4108] = 7, - [4110] = 8, - [4112] = 9, - [4114] = 10, - [4116] = 11, - [4118] = 12, - [4120] = 13, - [4122] = 14, + [4106] = 5, + [4108] = 6, + [4110] = 7, + [4112] = 8, + [4114] = 9, + [4116] = 10, + [4118] = 11, + [4120] = 12, + [4122] = 13, + [4124] = 14, [4224] = 0, [4225] = 1, [4226] = 2, [4228] = 3, [4230] = 4, - [4232] = 5, - [4234] = 6, - [4236] = 7, - [4238] = 8, - [4240] = 9, - [4242] = 10, - [4244] = 11, - [4246] = 12, - [4248] = 13, - [4250] = 14, - [4278] = 15, - [4280] = 16, - [4282] = 17, - [4284] = 18, - [4286] = 19, - [4288] = 20, - [4290] = 21, - [4292] = 22, - [4294] = 23, + [4234] = 5, + [4236] = 6, + [4238] = 7, + [4240] = 8, + [4242] = 9, + [4244] = 10, + [4246] = 11, + [4248] = 12, + [4250] = 13, + [4252] = 14, + [4280] = 15, + [4282] = 16, + [4284] = 17, + [4286] = 18, + [4288] = 19, + [4290] = 20, + [4292] = 21, + [4294] = 22, + [4296] = 23, [4352] = 0, [4353] = 1, [4354] = 2, [4356] = 3, [4358] = 4, - [4360] = 5, - [4362] = 6, - [4364] = 7, - [4366] = 8, - [4368] = 9, - [4370] = 10, - [4372] = 11, - [4374] = 12, - [4376] = 13, - [4378] = 14, - [4424] = 15, - [4426] = 16, - [4428] = 17, - [4430] = 18, + [4362] = 5, + [4364] = 6, + [4366] = 7, + [4368] = 8, + [4370] = 9, + [4372] = 10, + [4374] = 11, + [4376] = 12, + [4378] = 13, + [4380] = 14, + [4426] = 15, + [4428] = 16, + [4430] = 17, + [4432] = 18, [4480] = 0, [4481] = 1, [4482] = 2, [4484] = 3, [4486] = 4, - [4508] = 5, - [4510] = 6, - [4512] = 7, - [4514] = 8, - [4516] = 9, - [4518] = 10, - [4520] = 11, - [4522] = 12, + [4510] = 5, + [4512] = 6, + [4514] = 7, + [4516] = 8, + [4518] = 9, + [4520] = 10, + [4522] = 11, + [4524] = 12, [4608] = 0, [4609] = 1, [4610] = 2, [4612] = 3, [4614] = 4, - [4636] = 5, - [4638] = 6, - [4640] = 7, - [4642] = 8, - [4644] = 9, - [4646] = 10, - [4648] = 11, - [4650] = 12, - [4662] = 13, - [4664] = 14, - [4666] = 15, - [4668] = 16, - [4670] = 17, - [4672] = 18, - [4674] = 19, - [4676] = 20, - [4678] = 21, + [4638] = 5, + [4640] = 6, + [4642] = 7, + [4644] = 8, + [4646] = 9, + [4648] = 10, + [4650] = 11, + [4652] = 12, + [4664] = 13, + [4666] = 14, + [4668] = 15, + [4670] = 16, + [4672] = 17, + [4674] = 18, + [4676] = 19, + [4678] = 20, + [4680] = 21, [4736] = 0, [4737] = 1, [4738] = 2, [4740] = 3, [4742] = 4, - [4764] = 5, - [4766] = 6, - [4768] = 7, - [4770] = 8, - [4772] = 9, - [4774] = 10, - [4776] = 11, - [4778] = 12, - [4808] = 13, - [4810] = 14, - [4812] = 15, - [4814] = 16, + [4766] = 5, + [4768] = 6, + [4770] = 7, + [4772] = 8, + [4774] = 9, + [4776] = 10, + [4778] = 11, + [4780] = 12, + [4810] = 13, + [4812] = 14, + [4814] = 15, + [4816] = 16, [4864] = 0, [4865] = 1, [4866] = 2, [4868] = 3, [4870] = 4, - [4872] = 8, - [4874] = 9, - [4876] = 10, - [4878] = 11, - [4880] = 12, - [4882] = 13, - [4884] = 14, - [4886] = 15, - [4888] = 16, - [4890] = 17, - [4944] = 5, - [4948] = 6, - [4952] = 7, + [4874] = 8, + [4876] = 9, + [4878] = 10, + [4880] = 11, + [4882] = 12, + [4884] = 13, + [4886] = 14, + [4888] = 15, + [4890] = 16, + [4892] = 17, + [4946] = 5, + [4950] = 6, + [4954] = 7, [4992] = 0, [4993] = 1, [4994] = 2, [4996] = 3, [4998] = 4, - [5000] = 8, - [5002] = 9, - [5004] = 10, - [5006] = 11, - [5008] = 12, - [5010] = 13, - [5012] = 14, - [5014] = 15, - [5016] = 16, - [5018] = 17, - [5046] = 18, - [5048] = 19, - [5050] = 20, - [5052] = 21, - [5054] = 22, - [5056] = 23, - [5058] = 24, - [5060] = 25, - [5062] = 26, - [5072] = 5, - [5076] = 6, - [5080] = 7, + [5002] = 8, + [5004] = 9, + [5006] = 10, + [5008] = 11, + [5010] = 12, + [5012] = 13, + [5014] = 14, + [5016] = 15, + [5018] = 16, + [5020] = 17, + [5048] = 18, + [5050] = 19, + [5052] = 20, + [5054] = 21, + [5056] = 22, + [5058] = 23, + [5060] = 24, + [5062] = 25, + [5064] = 26, + [5074] = 5, + [5078] = 6, + [5082] = 7, [5120] = 0, [5121] = 1, [5122] = 2, [5124] = 3, [5126] = 4, - [5128] = 8, - [5130] = 9, - [5132] = 10, - [5134] = 11, - [5136] = 12, - [5138] = 13, - [5140] = 14, - [5142] = 15, - [5144] = 16, - [5146] = 17, - [5192] = 18, - [5194] = 19, - [5196] = 20, - [5198] = 21, - [5200] = 5, - [5204] = 6, - [5208] = 7, + [5130] = 8, + [5132] = 9, + [5134] = 10, + [5136] = 11, + [5138] = 12, + [5140] = 13, + [5142] = 14, + [5144] = 15, + [5146] = 16, + [5148] = 17, + [5194] = 18, + [5196] = 19, + [5198] = 20, + [5200] = 21, + [5202] = 5, + [5206] = 6, + [5210] = 7, [5248] = 0, [5249] = 1, [5250] = 2, [5252] = 3, [5254] = 4, - [5276] = 8, - [5278] = 9, - [5280] = 10, - [5282] = 11, - [5284] = 12, - [5286] = 13, - [5288] = 14, - [5290] = 15, - [5328] = 5, - [5332] = 6, - [5336] = 7, + [5278] = 8, + [5280] = 9, + [5282] = 10, + [5284] = 11, + [5286] = 12, + [5288] = 13, + [5290] = 14, + [5292] = 15, + [5330] = 5, + [5334] = 6, + [5338] = 7, [5376] = 0, [5377] = 1, [5378] = 2, [5380] = 3, [5382] = 4, - [5404] = 8, - [5406] = 9, - [5408] = 10, - [5410] = 11, - [5412] = 12, - [5414] = 13, - [5416] = 14, - [5418] = 15, - [5430] = 16, - [5432] = 17, - [5434] = 18, - [5436] = 19, - [5438] = 20, - [5440] = 21, - [5442] = 22, - [5444] = 23, - [5446] = 24, - [5456] = 5, - [5460] = 6, - [5464] = 7, + [5406] = 8, + [5408] = 9, + [5410] = 10, + [5412] = 11, + [5414] = 12, + [5416] = 13, + [5418] = 14, + [5420] = 15, + [5432] = 16, + [5434] = 17, + [5436] = 18, + [5438] = 19, + [5440] = 20, + [5442] = 21, + [5444] = 22, + [5446] = 23, + [5448] = 24, + [5458] = 5, + [5462] = 6, + [5466] = 7, [5504] = 0, [5505] = 1, [5506] = 2, [5508] = 3, [5510] = 4, - [5532] = 8, - [5534] = 9, - [5536] = 10, - [5538] = 11, - [5540] = 12, - [5542] = 13, - [5544] = 14, - [5546] = 15, - [5576] = 16, - [5578] = 17, - [5580] = 18, - [5582] = 19, - [5584] = 5, - [5588] = 6, - [5592] = 7 + [5534] = 8, + [5536] = 9, + [5538] = 10, + [5540] = 11, + [5542] = 12, + [5544] = 13, + [5546] = 14, + [5548] = 15, + [5578] = 16, + [5580] = 17, + [5582] = 18, + [5584] = 19, + [5586] = 5, + [5590] = 6, + [5594] = 7 }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 267c4fd45f..8b672ab63c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Dec 17 19:43:07 2020 */ +/* date: Tue Jan 26 15:51:49 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* act_tid: 5, wh_plus, table: int_encap_mac_record.0 */ + { /* act_tid: 5, wh_plus, table: int_encap_mac_record.dummy */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = @@ -960,6 +960,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { .field_info_spec = { .description = "shared_index", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -981,6 +982,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { .field_info_spec = { .description = "shared_index", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1056,6 +1058,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -1065,6 +1068,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -1081,6 +1085,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_pcp", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -1098,6 +1103,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1128,6 +1134,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -1164,6 +1171,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1173,6 +1181,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1182,6 +1191,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, @@ -1201,6 +1211,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1210,6 +1221,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, @@ -1250,6 +1262,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1259,6 +1272,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1268,6 +1282,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, @@ -1288,6 +1303,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -1297,6 +1313,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -1319,6 +1336,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "mirror", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, @@ -1338,6 +1356,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -1368,6 +1387,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1398,6 +1418,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -1455,6 +1476,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1464,6 +1486,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, @@ -1483,6 +1506,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1492,6 +1516,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, @@ -1532,6 +1557,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1541,6 +1567,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1550,6 +1577,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, @@ -1570,6 +1598,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -1579,6 +1608,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -1601,6 +1631,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "mirror", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1610,6 +1641,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -1765,6 +1797,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1795,6 +1828,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -1908,6 +1942,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -1965,6 +2000,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -1995,6 +2031,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -2122,6 +2159,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2131,6 +2169,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -2259,6 +2298,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2306,6 +2346,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2337,6 +2378,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv4_addr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2347,6 +2389,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv4_addr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2446,6 +2489,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2476,6 +2520,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -2512,6 +2557,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -2521,6 +2567,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2530,6 +2577,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, @@ -2549,6 +2597,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2558,6 +2607,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, @@ -2598,6 +2648,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2607,6 +2658,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2616,6 +2668,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, @@ -2636,6 +2689,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2688,6 +2742,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2718,6 +2773,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -2761,6 +2817,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -2779,6 +2836,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2788,6 +2846,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, @@ -2807,6 +2866,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2816,6 +2876,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, @@ -2856,6 +2917,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2865,6 +2927,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2874,6 +2937,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, @@ -2894,6 +2958,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3079,6 +3144,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3088,6 +3154,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3104,6 +3171,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_pcp", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3121,6 +3189,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -3151,6 +3220,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -3187,6 +3257,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -3245,6 +3316,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -3254,6 +3326,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -3270,6 +3343,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3300,6 +3374,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -3330,6 +3405,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -3360,6 +3436,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -3466,6 +3543,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -3475,6 +3553,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -3491,6 +3570,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3521,6 +3601,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -3623,6 +3704,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -3653,6 +3735,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -3759,6 +3842,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -3768,6 +3852,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -3784,6 +3869,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3793,6 +3879,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -3822,6 +3909,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -3890,6 +3978,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3899,6 +3988,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3915,6 +4005,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_pcp", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3940,6 +4031,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv4_addr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -3950,13 +4042,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv4_addr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} }, - /* act_tid: 5, wh_plus, table: int_encap_mac_record.0 */ + /* act_tid: 5, wh_plus, table: int_encap_mac_record.dummy */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -4049,6 +4142,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4079,6 +4173,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -4115,6 +4210,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -4124,6 +4220,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4133,6 +4230,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, @@ -4152,6 +4250,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4161,6 +4260,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, @@ -4201,6 +4301,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4210,6 +4311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4219,6 +4321,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, @@ -4239,6 +4342,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4291,6 +4395,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4321,6 +4426,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -4364,6 +4470,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -4382,6 +4489,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4391,6 +4499,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, @@ -4410,6 +4519,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "src_ip_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4419,6 +4529,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, @@ -4459,6 +4570,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "l3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4468,6 +4580,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4477,6 +4590,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, @@ -4497,6 +4611,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4629,6 +4744,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4638,6 +4754,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv4_src_addr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4655,6 +4772,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4664,6 +4782,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv6_src_addr", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4699,6 +4818,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_l3_type", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4717,6 +4837,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4742,6 +4863,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_l2_dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4775,6 +4897,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_udp", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4797,6 +4920,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4827,6 +4951,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -4863,6 +4988,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4942,6 +5068,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -4994,6 +5121,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -5024,6 +5152,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { @@ -5151,6 +5280,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -5206,6 +5336,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_l3_type", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -5224,6 +5355,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -5249,6 +5381,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_l2_dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -5282,6 +5415,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_udp", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -5291,6 +5425,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_tun", .field_bit_size = 80, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index f373e139b1..5324bd2531 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Dec 17 17:35:03 2020 */ +/* date: Tue Jan 26 15:51:49 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -29,7 +29,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .start_tbl_idx = 11, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 4, + .cond_start_idx = 5, .cond_nums = 0 } }, /* class_tid: 3, wh_plus, ingress */ @@ -39,7 +39,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .start_tbl_idx = 22, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 0 } }, /* class_tid: 4, wh_plus, egress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .start_tbl_idx = 30, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 9, + .cond_start_idx = 11, .cond_nums = 0 } }, /* class_tid: 5, wh_plus, egress */ @@ -59,7 +59,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .start_tbl_idx = 44, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 0 } }, /* class_tid: 6, wh_plus, egress */ @@ -69,7 +69,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .start_tbl_idx = 53, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 } }, /* class_tid: 7, wh_plus, egress */ @@ -79,7 +79,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .start_tbl_idx = 62, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 } } }; @@ -276,9 +276,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 4, - .cond_nums = 0 }, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, @@ -286,7 +286,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_start_idx = 116, .blob_key_bit_size = 448, .key_bit_size = 448, - .key_num_fields = 11, + .key_num_fields = 10, .result_start_idx = 61, .result_bit_size = 64, .result_num_fields = 9 @@ -300,13 +300,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 5, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 127, + .key_start_idx = 126, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, @@ -318,18 +318,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 5, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 138, + .key_start_idx = 137, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, @@ -347,12 +346,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 4, + .cond_start_idx = 5, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 149, + .key_start_idx = 148, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -367,7 +366,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 5, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -375,7 +374,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 150, + .key_start_idx = 149, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -395,12 +394,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 5, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 163, + .key_start_idx = 162, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, @@ -414,7 +413,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 5, + .cond_start_idx = 6, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -428,7 +427,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 6, + .cond_start_idx = 7, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -437,7 +436,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 166, + .key_start_idx = 165, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -455,7 +454,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 8, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -464,7 +463,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 209, + .key_start_idx = 208, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -484,12 +483,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 8, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 252, + .key_start_idx = 251, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, @@ -506,13 +505,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 7, + .cond_start_idx = 8, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 255, + .key_start_idx = 254, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, @@ -528,17 +527,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 9, + .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 265, + .key_start_idx = 264, .blob_key_bit_size = 448, .key_bit_size = 448, - .key_num_fields = 11, + .key_num_fields = 10, .result_start_idx = 149, .result_bit_size = 64, .result_num_fields = 9 @@ -552,13 +551,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 276, + .key_start_idx = 274, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, @@ -570,18 +569,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 287, + .key_start_idx = 285, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, @@ -599,7 +597,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -620,12 +618,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 298, + .key_start_idx = 296, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -639,7 +637,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -653,7 +651,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -664,7 +662,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 299, + .key_start_idx = 297, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -684,12 +682,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 312, + .key_start_idx = 310, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -705,7 +703,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -723,7 +721,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -741,7 +739,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -758,7 +756,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 9, + .cond_start_idx = 11, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP @@ -773,7 +771,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -795,12 +793,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 313, + .key_start_idx = 311, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -814,7 +812,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -828,7 +826,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -837,7 +835,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 314, + .key_start_idx = 312, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -857,12 +855,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 327, + .key_start_idx = 325, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -880,12 +878,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 328, + .key_start_idx = 326, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -899,7 +897,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -913,7 +911,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -922,7 +920,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 329, + .key_start_idx = 327, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -942,12 +940,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 342, + .key_start_idx = 340, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -965,7 +963,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -985,7 +983,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1003,7 +1001,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1021,7 +1019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1041,12 +1039,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 343, + .key_start_idx = 341, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1060,7 +1058,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -1074,7 +1072,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1083,7 +1081,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 344, + .key_start_idx = 342, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -1103,12 +1101,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 357, + .key_start_idx = 355, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1126,7 +1124,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -1148,7 +1146,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1169,7 +1167,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1188,7 +1186,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1198,7 +1196,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 358, + .key_start_idx = 356, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -1216,7 +1214,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1226,7 +1224,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 371, + .key_start_idx = 369, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -1246,12 +1244,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 384, + .key_start_idx = 382, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1265,7 +1263,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -1279,7 +1277,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1288,7 +1286,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 385, + .key_start_idx = 383, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -1308,12 +1306,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 398, + .key_start_idx = 396, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1329,7 +1327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, @@ -1347,7 +1345,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, @@ -1365,7 +1363,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, @@ -1385,7 +1383,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1405,7 +1403,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1415,7 +1413,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 399, + .key_start_idx = 397, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -1435,7 +1433,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, @@ -1470,6 +1468,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* cond_execute: class_tid: 1, eem.ipv4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, @@ -1490,6 +1493,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* cond_execute: class_tid: 2, eem.ipv4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, /* cond_execute: class_tid: 3, control.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, @@ -1537,6 +1545,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -1546,6 +1555,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -1558,6 +1568,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -1567,6 +1578,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -1594,6 +1606,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -1603,6 +1616,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -1614,6 +1628,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -1623,6 +1638,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -1707,6 +1723,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1816,6 +1833,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -1843,6 +1861,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1871,6 +1890,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -1881,6 +1901,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -1903,6 +1924,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1921,6 +1943,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1930,6 +1953,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2072,6 +2096,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2510,6 +2535,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -2633,6 +2659,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -2643,6 +2670,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -2665,6 +2693,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2683,6 +2712,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2692,6 +2722,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -2836,6 +2867,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -3274,6 +3306,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -3408,6 +3441,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -3435,6 +3469,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -3480,15 +3515,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.dport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -3514,15 +3563,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.sport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -3563,6 +3626,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv4.dst", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -3572,6 +3636,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv4.dst", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -3583,6 +3648,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv4.src", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -3592,6 +3658,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv4.src", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -3603,6 +3670,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -3612,6 +3680,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -3633,6 +3702,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -3653,6 +3723,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -3664,14 +3735,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { { .field_info_mask = { .description = "spare", - .field_bit_size = 35, + .field_bit_size = 275, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", - .field_bit_size = 35, + .field_bit_size = 275, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3698,15 +3769,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.dport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -3732,15 +3817,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.sport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -3763,14 +3862,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv6.ip_proto", + .description = "o_ipv4.ip_proto", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.ip_proto", + .description = "o_ipv4.ip_proto", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -3779,48 +3878,53 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv6.dst", - .field_bit_size = 128, + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "o_ipv6.dst", - .field_bit_size = 128, + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "o_ipv6.src", - .field_bit_size = 128, + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "o_ipv6.src", - .field_bit_size = 128, + .description = "o_ipv4.src", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -3830,6 +3934,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -3838,22 +3943,6 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { } }, { - .field_info_mask = { - .description = "o_eth.dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "o_eth.dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -3867,6 +3956,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -3887,6 +3977,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -3932,15 +4023,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.dport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -3966,15 +4071,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.sport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -4015,6 +4134,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.dst", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4024,6 +4144,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv6.dst", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4035,6 +4156,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.src", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4044,6 +4166,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv6.src", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4055,6 +4178,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4064,6 +4188,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4101,6 +4226,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4121,6 +4247,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4166,15 +4293,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.dport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -4200,15 +4341,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.sport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -4249,6 +4404,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.dst", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4258,6 +4414,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv6.dst", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4269,6 +4426,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.src", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4278,6 +4436,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv6.src", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4289,6 +4448,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4298,6 +4458,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.smac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4335,6 +4496,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4355,6 +4517,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4367,6 +4530,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4376,6 +4540,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4388,6 +4553,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4397,6 +4563,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4424,6 +4591,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4433,6 +4601,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4444,6 +4613,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4453,6 +4623,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -4537,6 +4708,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4646,6 +4818,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -4673,6 +4846,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4701,6 +4875,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -4711,6 +4886,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -4733,6 +4909,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4751,6 +4928,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4760,6 +4938,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -4902,6 +5081,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -5340,6 +5520,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -5463,6 +5644,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -5473,6 +5655,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -5495,6 +5678,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -5513,6 +5697,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -5522,6 +5707,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -5666,6 +5852,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -6104,6 +6291,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -6238,6 +6426,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -6265,6 +6454,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -6310,15 +6500,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.dport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -6344,15 +6548,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.sport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -6393,6 +6611,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv4.dst", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6402,6 +6621,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv4.dst", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6413,6 +6633,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv4.src", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6422,6 +6643,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv4.src", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6433,6 +6655,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6442,6 +6665,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6463,6 +6687,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -6483,6 +6708,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -6494,14 +6720,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { { .field_info_mask = { .description = "spare", - .field_bit_size = 35, + .field_bit_size = 275, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", - .field_bit_size = 35, + .field_bit_size = 275, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6528,15 +6754,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.dport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -6562,15 +6802,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.sport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -6593,14 +6847,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv6.ip_proto", + .description = "o_ipv4.ip_proto", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.ip_proto", + .description = "o_ipv4.ip_proto", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -6609,64 +6863,53 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv6.dst", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} - }, - .field_info_spec = { - .description = "o_ipv6.dst", - .field_bit_size = 128, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} - } - }, - { - .field_info_mask = { - .description = "o_ipv6.src", - .field_bit_size = 128, + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "o_ipv6.src", - .field_bit_size = 128, + .description = "o_ipv4.dst", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "o_ipv4.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "o_ipv4.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6676,6 +6919,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6697,6 +6941,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -6717,6 +6962,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -6762,15 +7008,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.dport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -6796,15 +7056,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.sport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -6845,6 +7119,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.dst", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6854,6 +7129,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv6.dst", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6865,6 +7141,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.src", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6874,6 +7151,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv6.src", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6901,6 +7179,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6910,6 +7189,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -6931,6 +7211,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -6951,6 +7232,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -6996,15 +7278,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.dport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.dport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -7030,15 +7326,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "o_l4.sport", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { .description = "o_l4.sport", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -7079,6 +7389,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.dst", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -7088,6 +7399,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv6.dst", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -7099,6 +7411,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_ipv6.src", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -7108,6 +7421,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_ipv6.src", .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -7135,6 +7449,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -7144,6 +7459,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "o_eth.dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { @@ -7165,6 +7481,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -7185,6 +7502,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -7206,6 +7524,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7275,6 +7594,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7446,6 +7766,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7467,6 +7788,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7536,6 +7858,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7707,6 +8030,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7728,6 +8052,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7797,6 +8122,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7968,6 +8294,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -7989,6 +8316,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8058,6 +8386,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8229,6 +8558,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8267,6 +8597,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8303,6 +8634,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8483,6 +8815,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8535,6 +8868,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8714,6 +9048,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8783,6 +9118,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -8954,6 +9290,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -9023,6 +9360,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -9187,6 +9525,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9196,6 +9535,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -9212,6 +9552,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -9317,6 +9658,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.1", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -9326,6 +9668,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.2", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -9335,6 +9678,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.3", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -9351,6 +9695,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.5", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -9360,6 +9705,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.6", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -9399,6 +9745,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9462,6 +9809,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.2", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -9471,6 +9819,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.3", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -9480,6 +9829,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.4", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -9496,6 +9846,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.6", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -9505,6 +9856,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.7", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -9537,6 +9889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9563,6 +9916,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9572,6 +9926,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "profile_tcam_index", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9581,6 +9936,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9588,7 +9944,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "wm_profile_id", + .description = "wc_profile_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -9597,6 +9953,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_sig_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -9607,6 +9964,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9677,6 +10035,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9695,13 +10054,12 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_EEM_ACT_REC_INT} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9715,8 +10073,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (413 >> 8) & 0xff, - 413 & 0xff} + (173 >> 8) & 0xff, + 173 & 0xff} }, { .description = "reserved", @@ -9754,6 +10112,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9824,6 +10183,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9842,13 +10202,12 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_EEM_ACT_REC_INT} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9901,6 +10260,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -9910,6 +10270,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -9926,6 +10287,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, @@ -9976,6 +10338,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10039,6 +10402,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.1", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -10048,6 +10412,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.2", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -10057,6 +10422,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.3", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -10073,6 +10439,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.5", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -10082,6 +10449,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.6", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -10121,6 +10489,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10177,6 +10546,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.1", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -10193,6 +10563,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.3", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -10202,6 +10573,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.4", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { @@ -10218,6 +10590,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.6", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -10227,6 +10600,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.7", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -10259,6 +10633,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10285,6 +10660,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10294,6 +10670,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "profile_tcam_index", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10303,6 +10680,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10310,7 +10688,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "wm_profile_id", + .description = "wc_profile_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -10319,6 +10697,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_sig_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -10329,6 +10708,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10399,6 +10779,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10417,13 +10798,12 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_EEM_ACT_REC_INT} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10437,8 +10817,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (413 >> 8) & 0xff, - 413 & 0xff} + (173 >> 8) & 0xff, + 173 & 0xff} }, { .description = "reserved", @@ -10476,6 +10856,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10546,6 +10927,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10564,13 +10946,12 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_EEM_ACT_REC_INT} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10756,6 +11137,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -10808,6 +11190,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10817,6 +11200,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -10833,6 +11217,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -10908,6 +11293,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10917,6 +11303,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10926,6 +11313,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10943,6 +11331,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10953,6 +11342,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -10963,6 +11353,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11106,6 +11497,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -11181,6 +11573,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -11258,6 +11651,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11267,6 +11661,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11291,6 +11686,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11300,6 +11696,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -11316,6 +11713,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -11391,6 +11789,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11400,6 +11799,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11409,6 +11809,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11559,6 +11960,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -11611,6 +12013,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11621,6 +12024,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11631,6 +12035,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11739,6 +12144,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11748,6 +12154,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -11835,6 +12242,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vtag_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -11922,6 +12330,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "encap_ptr", .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -12187,6 +12596,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -12241,6 +12651,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_record_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -12339,6 +12750,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_record_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -12437,6 +12849,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -12446,6 +12859,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -12462,9 +12876,11 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = {ULP_WP_SYM_LOOPBACK_PARIF & 0xff} + .field_opr1 = { + ULP_WP_SYM_LOOPBACK_PARIF} }, { .description = "allowed_pri", @@ -12535,6 +12951,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -12544,6 +12961,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -12553,6 +12971,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -12570,6 +12989,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -12580,6 +13000,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -12590,6 +13011,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -12733,6 +13155,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vnic_or_vport", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -12785,6 +13208,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_record_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { From patchwork Sun May 30 08:59:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93589 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E197CA0524; Sun, 30 May 2021 11:06:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 863B7411DB; Sun, 30 May 2021 11:01:45 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 50AD6411EA for ; Sun, 30 May 2021 11:01:43 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id AFBE47DC0; Sun, 30 May 2021 02:01:41 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com AFBE47DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365302; bh=ZqRb/u4v+3mr38MN/P4O+VzBgsSmuKA6sK2KYVBK4Ng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=To1HK0QJ1As5mDsoDazqnCMlR8udf//Sy/UcoSKQmV+il/IQqzQu+L1Tv/kSl9OTp uPbAplHHj/gf+iVPFioYNJ6UDs0N4gcwslKP/0keq7z+9FRjjBad3M6QKE8hqXQpWe q2Yp3FHUkVwigRJVPdvKwg6StEBw+1KZxzfkryY4= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru , Jay Ding Date: Sun, 30 May 2021 14:29:15 +0530 Message-Id: <20210530085929.29695-45-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 44/58] net/bnxt: refactor ULP mapper and parser X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha 1. The internal and external exact match table resource types is combined since the resource handle contains the encoded type whether it is internal or external exact match entry. 2. When a flow doesn't hit the offloaded rules, the default action is to send it to the kernel (L2 driver interface). In order to do that, TRUFLOW must know the kernel interface's (PF's) default vnic id. This patch fetches the PF's default vnic id from the dpdk core and stores it in port database. It also stores the mac addr for the future usage. Renamed compute field for layer 4 port enums. Added support for port database opcode that can get port details like mac address which can then be populated in the l2 context entry. 3. Both active and default bit set need to considered to check if a specific flow type is enabled or not. 4. ulp mapper fetches the dpdk port id from the compute field index BNXT_ULP_CF_IDX_DEV_PORT_ID which is used to get the interface’s mac address eventually. However, the compute field array is not populated with dpdk port id at the index BNXT_ULP_CF_IDX_DEV_PORT_ID. The problem fixed by populating the compute field array correctly. 5. Some dpdk applications may accumulate the flow counters while some may not. In cases where the application is accumulating the counters the PMD need not do the accumulation itself and viceversa to report the correct flow counters. 6. Pointer to bp is added to open session parms to support shared session. Signed-off-by: Venkat Duvvuru Signed-off-by: Kishore Padmanabha Signed-off-by: Jay Ding Reviewed-by: Lance Richardson Reviewed-by: Ajit Kumar Khaparde Reviewed-by: Michael Baucom Reviewed-by: Somnath Kotur Reviewed-by: Randy Schacher --- drivers/net/bnxt/bnxt.h | 6 + drivers/net/bnxt/bnxt_ethdev.c | 86 +++++++ drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 5 + drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 + drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 2 + drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 25 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 95 +++++--- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 5 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 52 +++- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 37 +++ drivers/net/bnxt/tf_ulp/ulp_port_db.h | 15 ++ drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 114 +++++++-- drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 8 + .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 59 +++-- .../tf_ulp/ulp_template_db_stingray_class.c | 4 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 48 ++-- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 3 +- drivers/net/bnxt/tf_ulp/ulp_tun.c | 227 +++++++++++++----- drivers/net/bnxt/tf_ulp/ulp_tun.h | 44 ++-- 19 files changed, 637 insertions(+), 199 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index d3ab57ab8d..246f51fddf 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -668,8 +668,11 @@ struct bnxt { uint32_t flags2; #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) +#define BNXT_FLAGS2_ACCUM_STATS_EN BIT(2) #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) +#define BNXT_ACCUM_STATS_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_ACCUM_STATS_EN) uint16_t chip_num; #define CHIP_NUM_58818 0xd818 @@ -981,7 +984,10 @@ int32_t bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); int32_t bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); +void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, + uint8_t *mac, uint8_t *parent_mac); uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); +uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); struct bnxt *bnxt_get_bp(uint16_t port); uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, enum bnxt_ulp_intf_type type); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index ebb326b0d1..1c0eeb76b7 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -87,6 +87,7 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { { .vendor_id = 0, /* sentinel */ }, }; +#define BNXT_DEVARG_ACCUM_STATS "accum-stats" #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" #define BNXT_DEVARG_REPRESENTOR "representor" @@ -99,6 +100,7 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, + BNXT_DEVARG_ACCUM_STATS, BNXT_DEVARG_FLOW_XSTAT, BNXT_DEVARG_MAX_NUM_KFLOWS, BNXT_DEVARG_REP_BASED_PF, @@ -110,6 +112,12 @@ static const char *const bnxt_dev_args[] = { NULL }; +/* + * accum-stats == false to disable flow counter accumulation + * accum-stats == true to enable flow counter accumulation + */ +#define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) + /* * flow_xstat == false to disable the feature * flow_xstat == true to enable the feature @@ -4837,6 +4845,39 @@ bnxt_get_svif(uint16_t port_id, bool func_svif, return func_svif ? bp->func_svif : bp->port_svif; } +void +bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, + uint8_t *mac, uint8_t *parent_mac) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && + type != BNXT_ULP_INTF_TYPE_PF) + return; + + eth_dev = &rte_eth_devices[port]; + bp = eth_dev->data->dev_private; + memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); + + if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) + memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); +} + +uint16_t +bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) + return 0; + + eth_dev = &rte_eth_devices[port]; + bp = eth_dev->data->dev_private; + + return bp->parent->vnic; +} uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) { @@ -5200,6 +5241,45 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) return 0; } +static int +bnxt_parse_devarg_accum_stats(__rte_unused const char *key, + const char *value, void *opaque_arg) +{ + struct bnxt *bp = opaque_arg; + unsigned long accum_stats; + char *end = NULL; + + if (!value || !opaque_arg) { + PMD_DRV_LOG(ERR, + "Invalid parameter passed to accum-stats devargs.\n"); + return -EINVAL; + } + + accum_stats = strtoul(value, &end, 10); + if (end == NULL || *end != '\0' || + (accum_stats == ULONG_MAX && errno == ERANGE)) { + PMD_DRV_LOG(ERR, + "Invalid parameter passed to accum-stats devargs.\n"); + return -EINVAL; + } + + if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { + PMD_DRV_LOG(ERR, + "Invalid value passed to accum-stats devargs.\n"); + return -EINVAL; + } + + if (accum_stats) { + bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; + PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); + } else { + bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; + PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); + } + + return 0; +} + static int bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -5516,6 +5596,12 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) if (ret) goto err; + /* + * Handler for "accum-stats" devarg. + * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" + */ + rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, + bnxt_parse_devarg_accum_stats, bp); /* * Handler for "max_num_kflows" devarg. * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 458c37b4e9..d68cc889c6 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -287,6 +287,7 @@ ulp_ctx_session_open(struct bnxt *bp, return rc; } + params.bp = bp; rc = tf_open_session(&bp->tfp, ¶ms); if (rc) { BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n", @@ -1071,6 +1072,10 @@ bnxt_ulp_port_init(struct bnxt *bp) } /* create the default rules */ bnxt_ulp_create_df_rules(bp); + + if (BNXT_ACCUM_STATS_EN(bp)) + bp->ulp_ctx->cfg_data->accum_stats = true; + BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init\n", bp->eth_dev->data->port_id); return rc; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index c2e71430ec..47c9c802e2 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -67,6 +67,7 @@ struct bnxt_ulp_data { #define BNXT_ULP_TUN_ENTRY_INVALID -1 #define BNXT_ULP_MAX_TUN_CACHE_ENTRIES 16 struct bnxt_tun_cache_entry tun_tbl[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; + bool accum_stats; }; struct bnxt_ulp_context { diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 0af2f6aaa6..59d75bc496 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -143,6 +143,8 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, /* copy the device port id and direction for further processing */ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_INCOMING_IF, dev->data->port_id); + ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DEV_PORT_ID, + dev->data->port_id); ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_SVIF_FLAG, BNXT_ULP_INVALID_SVIF_VAL); diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 054a76b5ee..65029139e6 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -317,8 +317,18 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, /* TBD - Get PKT/BYTE COUNT SHIFT/MASK from Template */ sw_cntr_indx = hw_cntr_id - fc_info->shadow_hw_tbl[dir].start_idx; sw_acc_tbl_entry = &fc_info->sw_acc_tbl[dir][sw_cntr_indx]; - sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms); + /* Some dpdk applications may accumulate the flow counters while some + * may not. In cases where the application is accumulating the counters + * the PMD need not do the accumulation itself and viceversa to report + * the correct flow counters. + */ + if (ctxt->cfg_data->accum_stats) { + sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); + sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); + } else { + sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms); + sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms); + } /* Update the parent counters if it is child flow */ if (sw_acc_tbl_entry->parent_flow_id) { @@ -628,11 +638,10 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, pthread_mutex_unlock(&ulp_fc_info->fc_lock); } else if (params.resource_sub_type == BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) { - /* Get the stats from the parent child table */ - ulp_flow_db_parent_flow_count_get(ctxt, - flow_id, - &count->hits, - &count->bytes); + /* Get stats from the parent child table */ + ulp_flow_db_parent_flow_count_get(ctxt, flow_id, + &count->hits, &count->bytes, + count->reset); count->hits_set = 1; count->bytes_set = 1; } else { diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 1326f79ff5..47c8c48456 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -48,17 +48,21 @@ ulp_flow_db_active_flows_bit_set(struct bnxt_ulp_flow_db *flow_db, uint32_t a_idx = idx / ULP_INDEX_BITMAP_SIZE; if (flag) { - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type == + BNXT_ULP_FDB_TYPE_RID) ULP_INDEX_BITMAP_SET(f_tbl->active_reg_flows[a_idx], idx); - else + if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type == + BNXT_ULP_FDB_TYPE_RID) ULP_INDEX_BITMAP_SET(f_tbl->active_dflt_flows[a_idx], idx); } else { - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type == + BNXT_ULP_FDB_TYPE_RID) ULP_INDEX_BITMAP_RESET(f_tbl->active_reg_flows[a_idx], idx); - else + if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type == + BNXT_ULP_FDB_TYPE_RID) ULP_INDEX_BITMAP_RESET(f_tbl->active_dflt_flows[a_idx], idx); } @@ -81,13 +85,21 @@ ulp_flow_db_active_flows_bit_is_set(struct bnxt_ulp_flow_db *flow_db, { struct bnxt_ulp_flow_tbl *f_tbl = &flow_db->flow_tbl; uint32_t a_idx = idx / ULP_INDEX_BITMAP_SIZE; - - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) - return ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx], - idx); - else - return ULP_INDEX_BITMAP_GET(f_tbl->active_dflt_flows[a_idx], - idx); + uint32_t reg, dflt; + + reg = ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx], idx); + dflt = ULP_INDEX_BITMAP_GET(f_tbl->active_dflt_flows[a_idx], idx); + + switch (flow_type) { + case BNXT_ULP_FDB_TYPE_REGULAR: + return (reg && !dflt); + case BNXT_ULP_FDB_TYPE_DEFAULT: + return (!reg && dflt); + case BNXT_ULP_FDB_TYPE_RID: + return (reg && dflt); + default: + return 0; + } } static inline enum tf_dir @@ -140,8 +152,7 @@ ulp_flow_db_res_params_to_info(struct ulp_fdb_resource_info *resource_info, } /* Store the handle as 64bit only for EM table entries */ - if (params->resource_func != BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE && - params->resource_func != BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) { + if (params->resource_func != BNXT_ULP_RESOURCE_FUNC_EM_TABLE) { resource_info->resource_hndl = (uint32_t)params->resource_hndl; resource_info->resource_type = params->resource_type; resource_info->resource_sub_type = params->resource_sub_type; @@ -170,8 +181,7 @@ ulp_flow_db_res_info_to_params(struct ulp_fdb_resource_info *resource_info, params->direction = ulp_flow_db_resource_dir_get(resource_info); params->resource_func = ulp_flow_db_resource_func_get(resource_info); - if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE || - params->resource_func == BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) { + if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE) { params->resource_hndl = resource_info->resource_em_handle; } else if (params->resource_func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER) { params->resource_hndl = resource_info->resource_hndl; @@ -213,7 +223,7 @@ ulp_flow_db_alloc_resource(struct bnxt_ulp_flow_db *flow_db) return -ENOMEM; } size = (flow_tbl->num_flows / sizeof(uint64_t)) + 1; - size = ULP_BYTE_ROUND_OFF_8(size); + size = ULP_BYTE_ROUND_OFF_8(size); flow_tbl->active_reg_flows = rte_zmalloc("active reg flows", size, ULP_BUFFER_ALIGN_64_BYTE); if (!flow_tbl->active_reg_flows) { @@ -617,7 +627,7 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -674,7 +684,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -688,7 +698,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist\n"); + BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); return -EINVAL; } @@ -769,7 +779,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -783,7 +793,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist\n"); + BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); return -EINVAL; } @@ -868,8 +878,9 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, enum bnxt_ulp_fdb_type flow_type, uint32_t fid) { - struct bnxt_ulp_flow_db *flow_db; + struct bnxt_tun_cache_entry *tun_tbl; struct bnxt_ulp_flow_tbl *flow_tbl; + struct bnxt_ulp_flow_db *flow_db; flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); if (!flow_db) { @@ -877,7 +888,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -892,7 +903,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, /* check if the flow is active or not */ if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) { - BNXT_TF_DBG(ERR, "flow does not exist\n"); + BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid); return -EINVAL; } flow_tbl->head_index--; @@ -900,6 +911,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, BNXT_TF_DBG(ERR, "FlowDB: Head Ptr is zero\n"); return -ENOENT; } + flow_tbl->flow_tbl_stack[flow_tbl->head_index] = fid; /* Clear the flows bitmap */ @@ -908,12 +920,18 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) ulp_flow_db_func_id_set(flow_db, fid, 0); + tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt); + if (!tun_tbl) + return -EINVAL; + + ulp_clear_tun_inner_entry(tun_tbl, fid); + /* all good, return success */ return 0; } /* - * Get the flow database entry details + *Get the flow database entry details * * ulp_ctxt [in] Ptr to ulp_context * flow_type [in] - specify default or regular @@ -940,7 +958,7 @@ ulp_flow_db_resource_get(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -996,10 +1014,14 @@ ulp_flow_db_next_entry_get(struct bnxt_ulp_flow_db *flow_db, uint64_t *active_flows; struct bnxt_ulp_flow_tbl *flowtbl = &flow_db->flow_tbl; - if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) + if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) { active_flows = flowtbl->active_reg_flows; - else + } else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT) { active_flows = flowtbl->active_dflt_flows; + } else { + BNXT_TF_DBG(ERR, "Invalid flow type %x\n", flow_type); + return -EINVAL; + } do { /* increment the flow id to find the next valid flow id */ @@ -1192,7 +1214,7 @@ ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -1224,9 +1246,7 @@ ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx, } } else if (resource_func == - BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE || - resource_func == - BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) { + BNXT_ULP_RESOURCE_FUNC_EM_TABLE) { ulp_flow_db_res_info_to_params(fid_res, params); return 0; @@ -1594,7 +1614,7 @@ ulp_flow_db_child_flow_reset(struct bnxt_ulp_context *ulp_ctxt, return -EINVAL; } - if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) { + if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) { BNXT_TF_DBG(ERR, "Invalid flow type\n"); return -EINVAL; } @@ -1812,9 +1832,8 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt, */ int32_t ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, - uint64_t *packet_count, - uint64_t *byte_count) + uint32_t parent_fid, uint64_t *packet_count, + uint64_t *byte_count, uint8_t count_reset) { struct bnxt_ulp_flow_db *flow_db; struct ulp_fdb_parent_child_db *p_pdb; @@ -1835,6 +1854,10 @@ ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, p_pdb->parent_flow_tbl[idx].pkt_count; *byte_count = p_pdb->parent_flow_tbl[idx].byte_count; + if (count_reset) { + p_pdb->parent_flow_tbl[idx].pkt_count = 0; + p_pdb->parent_flow_tbl[idx].byte_count = 0; + } } return 0; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h index f7dfd67bed..62c914833b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2019 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -390,7 +390,8 @@ int32_t ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t parent_fid, uint64_t *packet_count, - uint64_t *byte_count); + uint64_t *byte_count, + uint8_t count_reset); /* * reset the parent accumulation counters diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index bd28556a4b..27c7c871b1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -18,6 +18,7 @@ #include "ulp_flow_db.h" #include "tf_util.h" #include "ulp_template_db_tbl.h" +#include "ulp_port_db.h" static uint8_t mapper_fld_ones[16] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, @@ -450,10 +451,6 @@ ulp_mapper_em_entry_free(struct bnxt_ulp_context *ulp, int32_t rc; fparms.dir = res->direction; - if (res->resource_func == BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE) - fparms.mem = TF_MEM_EXTERNAL; - else - fparms.mem = TF_MEM_INTERNAL; fparms.flow_handle = res->resource_hndl; rc = bnxt_ulp_cntxt_tbl_scope_id_get(ulp, &fparms.tbl_scope_id); @@ -883,6 +880,30 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, return rc; } +static int32_t +ulp_mapper_field_port_db_process(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_field_info *fld, + uint32_t port_id, + uint16_t val16, + uint8_t **val) +{ + enum bnxt_ulp_port_table port_data = val16; + + switch (port_data) { + case BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_MAC: + if (ulp_port_db_parent_mac_addr_get(parms->ulp_ctx, port_id, + val)) { + BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id); + return -EINVAL; + } + break; + default: + BNXT_TF_DBG(ERR, "Invalid port_data %s\n", fld->description); + return -EINVAL; + } + return 0; +} + static int32_t ulp_mapper_field_process_inc_dec(struct bnxt_ulp_mapper_field_info *fld, struct ulp_blob *blob, @@ -938,6 +959,7 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, uint16_t const_val = 0; uint32_t update_flag = 0; uint64_t src1_val64; + uint32_t port_id; /* process the field opcode */ if (fld->field_opc != BNXT_ULP_FIELD_OPC_COND_OP) { @@ -1081,6 +1103,20 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, name); return -EINVAL; } + } else if (fld->field_opc == BNXT_ULP_FIELD_OPC_PORT_TABLE) { + port_id = ULP_COMP_FLD_IDX_RD(parms, idx); + if (ulp_mapper_field_port_db_process(parms, fld, + port_id, const_val, + &val)) { + BNXT_TF_DBG(ERR, "%s field port table failed\n", + name); + return -EINVAL; + } + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", + name); + return -EINVAL; + } } else { src1_val64 = ULP_COMP_FLD_IDX_RD(parms, idx); if (ulp_mapper_field_process_inc_dec(fld, blob, @@ -1951,7 +1987,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } /* do the transpose for the internal EM keys */ - if (tbl->resource_func == BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) + if (tbl->resource_type == TF_MEM_INTERNAL) ulp_blob_perform_byte_reverse(&key); rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, @@ -3021,8 +3057,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: rc = ulp_mapper_tcam_tbl_process(parms, tbl); break; - case BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE: - case BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE: + case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: rc = ulp_mapper_em_tbl_process(parms, tbl); break; case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: @@ -3101,8 +3136,7 @@ ulp_mapper_resource_free(struct bnxt_ulp_context *ulp, case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: rc = ulp_mapper_tcam_entry_free(ulp, tfp, res); break; - case BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE: - case BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE: + case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: rc = ulp_mapper_em_entry_free(ulp, tfp, res); break; case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 94075784d8..2ee79ea3fe 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -182,6 +182,13 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt, func->ifindex = ifindex; } + /* When there is no match, the default action is to send the packet to + * the kernel. And to send it to the kernel, we need the PF's vnic id. + */ + func->func_parent_vnic = bnxt_get_parent_vnic_id(port_id, intf->type); + bnxt_get_iface_mac(port_id, intf->type, func->func_mac, + func->func_parent_mac); + port_data = &port_db->phy_port_list[func->phy_port_id]; if (!port_data->port_valid) { port_data->port_svif = @@ -579,3 +586,33 @@ ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt, } return 0; } + +/* + * Api to get the parent mac address for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in].device port id + * mac_addr [out] mac address + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_parent_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint8_t **mac_addr) +{ + struct bnxt_ulp_port_db *port_db; + uint16_t func_id; + + port_db = bnxt_ulp_cntxt_ptr2_port_db_get(ulp_ctxt); + if (ulp_port_db_port_func_id_get(ulp_ctxt, port_id, &func_id)) { + BNXT_TF_DBG(ERR, "Invalid port_id %x\n", port_id); + return -EINVAL; + } + + if (!port_db->ulp_func_id_tbl[func_id].func_valid) { + BNXT_TF_DBG(ERR, "Invalid func_id %x\n", func_id); + return -ENOENT; + } + *mac_addr = port_db->ulp_func_id_tbl[func_id].func_parent_mac; + return 0; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h index 7b85987a0c..b10a7ea58c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h @@ -46,6 +46,9 @@ struct ulp_func_if_info { uint16_t func_spif; uint16_t func_parif; uint16_t func_vnic; + uint8_t func_mac[RTE_ETHER_ADDR_LEN]; + uint16_t func_parent_vnic; + uint8_t func_parent_mac[RTE_ETHER_ADDR_LEN]; uint16_t phy_port_id; uint16_t ifindex; }; @@ -272,4 +275,16 @@ int32_t ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt, uint16_t port_id, uint16_t *func_id); +/* + * Api to get the parent mac address for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in].device port id + * mac_addr [out] mac address + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_parent_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint8_t **mac_addr); #endif /* _ULP_PORT_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 5a2249f349..1522328a5d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -16,6 +16,7 @@ #include "ulp_flow_db.h" #include "ulp_mapper.h" #include "ulp_tun.h" +#include "ulp_template_db_tbl.h" /* Local defines for the parsing functions */ #define ULP_VLAN_PRIORITY_SHIFT 13 /* First 3 bits */ @@ -240,6 +241,11 @@ bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params) BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, parif); } + if (mtype == BNXT_ULP_INTF_TYPE_PF) { + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF, + 1); + } } } @@ -623,7 +629,7 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param, } } -/* Internal Function to indentify broadcast or multicast packets */ +/* Internal Function to identify broadcast or multicast packets */ static int32_t ulp_rte_parser_is_bcmc_addr(const struct rte_ether_addr *eth_addr) { @@ -740,6 +746,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(field, &vlan_tag, sizeof(vlan_tag)); + field = ulp_rte_parser_fld_copy(field, &vlan_spec->inner_type, sizeof(vlan_spec->inner_type)); @@ -764,7 +771,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, vlan_tag = htons(vlan_tag); /* - * The priortiy field is ignored since OVS is seting it as + * The priority field is ignored since OVS is setting it as * wild card match and it is not supported. This is a work * around and shall be addressed in the future. */ @@ -960,7 +967,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, &ipv4_mask->hdr.version_ihl, sizeof(ipv4_mask->hdr.version_ihl)); /* - * The tos field is ignored since OVS is seting it as wild card + * The tos field is ignored since OVS is setting it as wild card * match and it is not supported. This is a work around and * shall be addressed in the future. */ @@ -1008,6 +1015,13 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } + /* Some of the PMD applications may set the protocol field + * in the IPv4 spec but don't set the mask. So, consider + * the mask in the proto value calculation. + */ + if (ipv4_mask) + proto &= ipv4_mask->hdr.next_proto_id; + if (proto == IPPROTO_GRE) ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); @@ -1108,8 +1122,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, &vtcf_mask, size); /* - * The TC and flow lable field are ignored since OVS is seting - * it for match and it is not supported. + * The TC and flow label field are ignored since OVS is + * setting it for match and it is not supported. * This is a work around and * shall be addressed in the future. */ @@ -1149,6 +1163,13 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } + /* Some of the PMD applications may set the protocol field + * in the IPv6 spec but don't set the mask. So, consider + * the mask in proto value calculation. + */ + if (ipv6_mask) + proto &= ipv6_mask->hdr.proto; + if (proto == IPPROTO_GRE) ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); @@ -1182,7 +1203,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; uint32_t size; - uint16_t dport = 0, sport = 0; + uint16_t dport = 0; uint32_t cnt; cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT); @@ -1200,7 +1221,6 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], &udp_spec->hdr.src_port, size); - sport = udp_spec->hdr.src_port; size = sizeof(udp_spec->hdr.dst_port); field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dst_port, @@ -1238,14 +1258,26 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SPORT, sport); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DPORT, dport); + if (udp_mask && udp_mask->hdr.src_port) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT, + 1); + if (udp_mask && udp_mask->hdr.dst_port) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT, + 1); } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SPORT, sport); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DPORT, dport); + if (udp_mask && udp_mask->hdr.src_port) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT, + 1); + if (udp_mask && udp_mask->hdr.dst_port) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT, + 1); /* Update the field protocol hdr bitmap */ ulp_rte_l4_proto_type_update(params, dport); @@ -1264,7 +1296,6 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; - uint16_t dport = 0, sport = 0; uint32_t size; uint32_t cnt; @@ -1279,12 +1310,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, * header fields */ if (tcp_spec) { - sport = tcp_spec->hdr.src_port; size = sizeof(tcp_spec->hdr.src_port); field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], &tcp_spec->hdr.src_port, size); - dport = tcp_spec->hdr.dst_port; size = sizeof(tcp_spec->hdr.dst_port); field = ulp_rte_parser_fld_copy(field, &tcp_spec->hdr.dst_port, @@ -1358,13 +1387,25 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SPORT, sport); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DPORT, dport); + if (tcp_mask && tcp_mask->hdr.src_port) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT, + 1); + if (tcp_mask && tcp_mask->hdr.dst_port) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT, + 1); } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SPORT, sport); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DPORT, dport); + if (tcp_mask && tcp_mask->hdr.src_port) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT, + 1); + if (tcp_mask && tcp_mask->hdr.dst_port) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT, + 1); } ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt); return BNXT_TF_RC_SUCCESS; @@ -2257,3 +2298,40 @@ ulp_rte_jump_act_handler(const struct rte_flow_action *action_item __rte_unused, ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP); return BNXT_TF_RC_SUCCESS; } + +int32_t +ulp_rte_sample_act_handler(const struct rte_flow_action *action_item, + struct ulp_rte_parser_params *params) +{ + const struct rte_flow_action_sample *sample; + int ret; + + sample = action_item->conf; + + /* if SAMPLE bit is set it means this sample action is nested within the + * actions of another sample action; this is not allowed + */ + if (ULP_BITMAP_ISSET(params->act_bitmap.bits, + BNXT_ULP_ACT_BIT_SAMPLE)) + return BNXT_TF_RC_ERROR; + + /* a sample action is only allowed as a shared action */ + if (!ULP_BITMAP_ISSET(params->act_bitmap.bits, + BNXT_ULP_ACT_BIT_SHARED)) + return BNXT_TF_RC_ERROR; + + /* only a ratio of 1 i.e. 100% is supported */ + if (sample->ratio != 1) + return BNXT_TF_RC_ERROR; + + if (!sample->actions) + return BNXT_TF_RC_ERROR; + + /* parse the nested actions for a sample action */ + ret = bnxt_ulp_rte_parser_act_parse(sample->actions, params); + if (ret == BNXT_TF_RC_SUCCESS) + /* Update the act_bitmap with sample */ + ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_SAMPLE); + + return ret; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index cb9ae02371..48a20e84b1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -245,4 +245,12 @@ int32_t ulp_rte_jump_act_handler(const struct rte_flow_action *action_item, struct ulp_rte_parser_params *params); +int32_t +ulp_rte_sample_act_handler(const struct rte_flow_action *action_item, + struct ulp_rte_parser_params *params); + +int32_t +ulp_rte_shared_act_handler(const struct rte_flow_action *action_item, + struct ulp_rte_parser_params *params); + #endif /* _ULP_RTE_PARSER_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 418f6389eb..0223296480 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -145,10 +145,10 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_I_L3 = 14, BNXT_ULP_CF_IDX_O_L4 = 15, BNXT_ULP_CF_IDX_I_L4 = 16, - BNXT_ULP_CF_IDX_O_L4_SPORT = 17, - BNXT_ULP_CF_IDX_O_L4_DPORT = 18, - BNXT_ULP_CF_IDX_I_L4_SPORT = 19, - BNXT_ULP_CF_IDX_I_L4_DPORT = 20, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 17, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 18, + BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 19, + BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 20, BNXT_ULP_CF_IDX_DEV_PORT_ID = 21, BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 22, BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 23, @@ -171,17 +171,18 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 40, BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 41, BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 42, - BNXT_ULP_CF_IDX_VF_TO_VF = 43, - BNXT_ULP_CF_IDX_L3_HDR_CNT = 44, - BNXT_ULP_CF_IDX_L4_HDR_CNT = 45, - BNXT_ULP_CF_IDX_VFR_MODE = 46, - BNXT_ULP_CF_IDX_L3_TUN = 47, - BNXT_ULP_CF_IDX_L3_TUN_DECAP = 48, - BNXT_ULP_CF_IDX_FID = 49, - BNXT_ULP_CF_IDX_HDR_SIG_ID = 50, - BNXT_ULP_CF_IDX_FLOW_SIG_ID = 51, - BNXT_ULP_CF_IDX_WC_MATCH = 52, - BNXT_ULP_CF_IDX_LAST = 53 + BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 43, + BNXT_ULP_CF_IDX_VF_TO_VF = 44, + BNXT_ULP_CF_IDX_L3_HDR_CNT = 45, + BNXT_ULP_CF_IDX_L4_HDR_CNT = 46, + BNXT_ULP_CF_IDX_VFR_MODE = 47, + BNXT_ULP_CF_IDX_L3_TUN = 48, + BNXT_ULP_CF_IDX_L3_TUN_DECAP = 49, + BNXT_ULP_CF_IDX_FID = 50, + BNXT_ULP_CF_IDX_HDR_SIG_ID = 51, + BNXT_ULP_CF_IDX_FLOW_SIG_ID = 52, + BNXT_ULP_CF_IDX_WC_MATCH = 53, + BNXT_ULP_CF_IDX_LAST = 54 }; enum bnxt_ulp_cond_list_opc { @@ -266,7 +267,8 @@ enum bnxt_ulp_field_opc { BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST = 2, BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST = 3, BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST_POST = 4, - BNXT_ULP_FIELD_OPC_LAST = 5 + BNXT_ULP_FIELD_OPC_PORT_TABLE = 5, + BNXT_ULP_FIELD_OPC_LAST = 6 }; enum bnxt_ulp_field_src { @@ -352,6 +354,27 @@ enum bnxt_ulp_mem_type_opc { BNXT_ULP_MEM_TYPE_OPC_LAST = 3 }; +enum bnxt_ulp_port_table { + BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_MAC = 0, + BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC = 1, + BNXT_ULP_PORT_TABLE_DRV_FUNC_SVIF = 2, + BNXT_ULP_PORT_TABLE_DRV_FUNC_SPIF = 3, + BNXT_ULP_PORT_TABLE_DRV_FUNC_PARIF = 4, + BNXT_ULP_PORT_TABLE_DRV_FUNC_VNIC = 5, + BNXT_ULP_PORT_TABLE_DRV_FUNC_PHY_PORT = 6, + BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC = 7, + BNXT_ULP_PORT_TABLE_VF_FUNC_SVIF = 8, + BNXT_ULP_PORT_TABLE_VF_FUNC_SPIF = 9, + BNXT_ULP_PORT_TABLE_VF_FUNC_PARIF = 10, + BNXT_ULP_PORT_TABLE_VF_FUNC_VNIC = 11, + BNXT_ULP_PORT_TABLE_VF_FUNC_MAC = 12, + BNXT_ULP_PORT_TABLE_PHY_PORT_SVIF = 13, + BNXT_ULP_PORT_TABLE_PHY_PORT_SPIF = 14, + BNXT_ULP_PORT_TABLE_PHY_PORT_PARIF = 15, + BNXT_ULP_PORT_TABLE_PHY_PORT_VPORT = 16, + BNXT_ULP_PORT_TABLE_LAST = 17 +}; + enum bnxt_ulp_pri_opc { BNXT_ULP_PRI_OPC_NOT_USED = 0, BNXT_ULP_PRI_OPC_CONST = 1, @@ -427,8 +450,8 @@ enum bnxt_ulp_match_type_bitmask { enum bnxt_ulp_resource_func { BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00, - BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE = 0x20, - BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE = 0x40, + BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20, + BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40, BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60, BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80, BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c index df09de929e..320a89a5d9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c @@ -205,7 +205,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0 }, { /* class_tid: 1, stingray, table: em.int_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, @@ -228,7 +228,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { .encap_num_fields = 0 }, { /* class_tid: 1, stingray, table: eem.ext_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 5324bd2531..973ba39f82 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -246,7 +246,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 5 }, { /* class_tid: 1, wh_plus, table: em.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, @@ -269,7 +269,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 9 }, { /* class_tid: 1, wh_plus, table: eem.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, @@ -292,7 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 9 }, { /* class_tid: 1, wh_plus, table: em.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, @@ -315,7 +315,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 9 }, { /* class_tid: 1, wh_plus, table: eem.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, .execute_info = { @@ -497,7 +497,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 5 }, { /* class_tid: 2, wh_plus, table: em.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, @@ -520,7 +520,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 9 }, { /* class_tid: 2, wh_plus, table: eem.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, @@ -543,7 +543,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 9 }, { /* class_tid: 2, wh_plus, table: em.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, @@ -566,7 +566,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 9 }, { /* class_tid: 2, wh_plus, table: eem.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, .execute_info = { @@ -9699,8 +9699,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} }, { .description = "em_key_mask.6", @@ -9709,8 +9709,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} }, { .description = "em_key_mask.7", @@ -9850,8 +9850,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} }, { .description = "em_key_mask.7", @@ -9860,8 +9860,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} }, { .description = "em_key_mask.8", @@ -10443,8 +10443,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} }, { .description = "em_key_mask.6", @@ -10453,8 +10453,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} }, { .description = "em_key_mask.7", @@ -10594,8 +10594,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} }, { .description = "em_key_mask.7", @@ -10604,8 +10604,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} }, { .description = "em_key_mask.8", diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 5150ed2b07..6e2c48e7b6 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2019 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -63,6 +63,7 @@ struct ulp_rte_act_prop { /* Structure to be used for passing all the parser functions */ struct ulp_rte_parser_params { + STAILQ_ENTRY(ulp_rte_parser_params) next; struct ulp_rte_hdr_bitmap hdr_bitmap; struct ulp_rte_hdr_bitmap hdr_fp_bit; struct ulp_rte_field_bitmap fld_bitmap; diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c index dd3d8703fb..a883e0ff08 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.c +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ +#include + #include #include "ulp_tun.h" @@ -48,18 +50,18 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params, goto err; /* Store the tunnel dmac in the tunnel cache table and use it while - * programming tunnel flow F2. + * programming tunnel inner flow. */ memcpy(tun_entry->t_dmac, ¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec, RTE_ETHER_ADDR_LEN); - tun_entry->valid = true; - tun_entry->state = BNXT_ULP_FLOW_STATE_TUN_O_OFFLD; + tun_entry->tun_flow_info[params->port_id].state = + BNXT_ULP_FLOW_STATE_TUN_O_OFFLD; tun_entry->outer_tun_flow_id = params->fid; - /* F1 and it's related F2s are correlated based on - * Tunnel Destination IP Address. + /* Tunnel outer flow and it's related inner flows are correlated + * based on Tunnel Destination IP Address. */ if (tun_entry->t_dst_ip_valid) goto done; @@ -83,27 +85,32 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params, /* This function programs the inner tunnel flow in the hardware. */ static void -ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry) +ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry, + struct ulp_rte_parser_params *tun_o_params) { struct bnxt_ulp_mapper_create_parms mparms = { 0 }; - struct ulp_rte_parser_params *params; + struct ulp_per_port_flow_info *flow_info; + struct ulp_rte_parser_params *inner_params; int ret; - /* F2 doesn't have tunnel dmac, use the tunnel dmac that was - * stored during F1 programming. + /* Tunnel inner flow doesn't have tunnel dmac, use the tunnel + * dmac that was stored during F1 programming. */ - params = &tun_entry->first_inner_tun_params; - memcpy(¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX], - tun_entry->t_dmac, RTE_ETHER_ADDR_LEN); - params->parent_fid = tun_entry->outer_tun_flow_id; - params->fid = tun_entry->first_inner_tun_flow_id; - - bnxt_ulp_init_mapper_params(&mparms, params, - BNXT_ULP_FDB_TYPE_REGULAR); - - ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms); - if (ret) - PMD_DRV_LOG(ERR, "Failed to create F2 flow."); + flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id]; + STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) { + memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX], + tun_entry->t_dmac, RTE_ETHER_ADDR_LEN); + inner_params->parent_fid = tun_entry->outer_tun_flow_id; + + bnxt_ulp_init_mapper_params(&mparms, inner_params, + BNXT_ULP_FDB_TYPE_REGULAR); + + ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms); + if (ret) + PMD_DRV_LOG(ERR, + "Failed to create inner tun flow, FID:%u.", + inner_params->fid); + } } /* This function either install outer tunnel flow & inner tunnel flow @@ -114,30 +121,31 @@ ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params, struct bnxt_tun_cache_entry *tun_entry, uint16_t tun_idx) { - enum bnxt_ulp_tun_flow_state flow_state; int ret; - flow_state = tun_entry->state; ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx); - if (ret) + if (ret == BNXT_TF_RC_ERROR) { + PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow."); return ret; + } - /* If flow_state == BNXT_ULP_FLOW_STATE_NORMAL before installing - * F1, that means F2 is not deferred. Hence, no need to install F2. + /* Install any cached tunnel inner flows that came before tunnel + * outer flow. */ - if (flow_state != BNXT_ULP_FLOW_STATE_NORMAL) - ulp_install_inner_tun_flow(tun_entry); + ulp_install_inner_tun_flow(tun_entry, params); - return 0; + return BNXT_TF_RC_FID; } /* This function will be called if inner tunnel flow request comes before * outer tunnel flow request. */ static int32_t -ulp_post_process_first_inner_tun_flow(struct ulp_rte_parser_params *params, +ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params, struct bnxt_tun_cache_entry *tun_entry) { + struct ulp_rte_parser_params *inner_tun_params; + struct ulp_per_port_flow_info *flow_info; int ret; ret = ulp_matcher_pattern_match(params, ¶ms->class_id); @@ -148,18 +156,22 @@ ulp_post_process_first_inner_tun_flow(struct ulp_rte_parser_params *params, if (ret != BNXT_TF_RC_SUCCESS) return BNXT_TF_RC_ERROR; - /* If Tunnel F2 flow comes first then we can't install it in the - * hardware, because, F2 flow will not have L2 context information. - * So, just cache the F2 information and program it in the context - * of F1 flow installation. + /* If Tunnel inner flow comes first then we can't install it in the + * hardware, because, Tunnel inner flow will not have L2 context + * information. So, just cache the Tunnel inner flow information + * and program it in the context of F1 flow installation. */ - memcpy(&tun_entry->first_inner_tun_params, params, - sizeof(struct ulp_rte_parser_params)); - - tun_entry->first_inner_tun_flow_id = params->fid; - tun_entry->state = BNXT_ULP_FLOW_STATE_TUN_I_CACHED; + flow_info = &tun_entry->tun_flow_info[params->port_id]; + inner_tun_params = rte_zmalloc("ulp_inner_tun_params", + sizeof(struct ulp_rte_parser_params), 0); + if (!inner_tun_params) + return BNXT_TF_RC_ERROR; + memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params)); + STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params, + next); + flow_info->tun_i_cnt++; - /* F1 and it's related F2s are correlated based on + /* F1 and it's related Tunnel inner flows are correlated based on * Tunnel Destination IP Address. It could be already set, if * the inner flow got offloaded first. */ @@ -240,8 +252,8 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params, int32_t ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) { - bool outer_tun_sig, inner_tun_sig, first_inner_tun_flow; - bool outer_tun_reject, inner_tun_reject, outer_tun_flow, inner_tun_flow; + bool inner_tun_sig, cache_inner_tun_flow; + bool outer_tun_reject, outer_tun_flow, inner_tun_flow; enum bnxt_ulp_tun_flow_state flow_state; struct bnxt_tun_cache_entry *tun_entry; uint32_t l3_tun, l3_tun_decap; @@ -259,40 +271,31 @@ ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) if (rc == BNXT_TF_RC_ERROR) return rc; - flow_state = tun_entry->state; + if (params->port_id >= RTE_MAX_ETHPORTS) + return BNXT_TF_RC_ERROR; + flow_state = tun_entry->tun_flow_info[params->port_id].state; /* Outer tunnel flow validation */ - outer_tun_sig = BNXT_OUTER_TUN_SIGNATURE(l3_tun, params); - outer_tun_flow = BNXT_OUTER_TUN_FLOW(outer_tun_sig); + outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params); outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state, - outer_tun_sig); + outer_tun_flow); /* Inner tunnel flow validation */ inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params); - first_inner_tun_flow = BNXT_FIRST_INNER_TUN_FLOW(flow_state, + cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state, inner_tun_sig); inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig); - inner_tun_reject = BNXT_REJECT_INNER_TUN_FLOW(flow_state, - inner_tun_sig); if (outer_tun_reject) { tun_entry->outer_tun_rej_cnt++; BNXT_TF_DBG(ERR, "Tunnel F1 flow rejected, COUNT: %d\n", tun_entry->outer_tun_rej_cnt); - /* Inner tunnel flow is rejected if it comes between first inner - * tunnel flow and outer flow requests. - */ - } else if (inner_tun_reject) { - tun_entry->inner_tun_rej_cnt++; - BNXT_TF_DBG(ERR, - "Tunnel F2 flow rejected, COUNT: %d\n", - tun_entry->inner_tun_rej_cnt); } - if (outer_tun_reject || inner_tun_reject) + if (outer_tun_reject) return BNXT_TF_RC_ERROR; - else if (first_inner_tun_flow) - return ulp_post_process_first_inner_tun_flow(params, tun_entry); + else if (cache_inner_tun_flow) + return ulp_post_process_cache_inner_tun_flow(params, tun_entry); else if (outer_tun_flow) return ulp_post_process_outer_tun_flow(params, tun_entry, tun_idx); @@ -302,9 +305,109 @@ ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) return BNXT_TF_RC_NORMAL; } +void +ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl) +{ + struct ulp_per_port_flow_info *flow_info; + int i, j; + + for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { + for (j = 0; j < RTE_MAX_ETHPORTS; j++) { + flow_info = &tun_tbl[i].tun_flow_info[j]; + STAILQ_INIT(&flow_info->tun_i_prms_list); + } + } +} + void ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx) { + struct ulp_rte_parser_params *inner_params; + struct ulp_per_port_flow_info *flow_info; + int j; + + for (j = 0; j < RTE_MAX_ETHPORTS; j++) { + flow_info = &tun_tbl[tun_idx].tun_flow_info[j]; + STAILQ_FOREACH(inner_params, + &flow_info->tun_i_prms_list, + next) { + STAILQ_REMOVE(&flow_info->tun_i_prms_list, + inner_params, + ulp_rte_parser_params, next); + rte_free(inner_params); + } + } + memset(&tun_tbl[tun_idx], 0, - sizeof(struct bnxt_tun_cache_entry)); + sizeof(struct bnxt_tun_cache_entry)); + + for (j = 0; j < RTE_MAX_ETHPORTS; j++) { + flow_info = &tun_tbl[tun_idx].tun_flow_info[j]; + STAILQ_INIT(&flow_info->tun_i_prms_list); + } +} + +static bool +ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry, + struct ulp_per_port_flow_info *flow_info, + uint32_t fid) +{ + struct ulp_rte_parser_params *inner_params; + int j; + + STAILQ_FOREACH(inner_params, + &flow_info->tun_i_prms_list, + next) { + if (inner_params->fid == fid) { + STAILQ_REMOVE(&flow_info->tun_i_prms_list, + inner_params, + ulp_rte_parser_params, + next); + rte_free(inner_params); + flow_info->tun_i_cnt--; + /* When a dpdk application offloads a duplicate + * tunnel inner flow on a port that it is not + * destined to, there won't be a tunnel outer flow + * associated with these duplicate tunnel inner flows. + * So, when the last tunnel inner flow ages out, the + * driver has to clear the tunnel entry, otherwise + * the tunnel entry cannot be reused. + */ + if (!flow_info->tun_i_cnt && + flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) { + memset(tun_entry, 0, + sizeof(struct bnxt_tun_cache_entry)); + for (j = 0; j < RTE_MAX_ETHPORTS; j++) + STAILQ_INIT(&flow_info->tun_i_prms_list); + } + return true; + } + } + + return false; +} + +/* When a dpdk application offloads the same tunnel inner flow + * on all the uplink ports, a tunnel inner flow entry is cached + * even if it is not for the right uplink port. Such tunnel + * inner flows will eventually get aged out as there won't be + * any traffic on these ports. When such a flow destroy is + * called, cleanup the tunnel inner flow entry. + */ +void +ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid) +{ + struct ulp_per_port_flow_info *flow_info; + int i, j; + + for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { + if (!tun_tbl[i].t_dst_ip_valid) + continue; + for (j = 0; j < RTE_MAX_ETHPORTS; j++) { + flow_info = &tun_tbl[i].tun_flow_info[j]; + if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i], + flow_info, fid) == true) + return; + } + } } diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h index 763138218b..2516eaca2c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.h +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -10,12 +10,17 @@ #include #include +#include "rte_version.h" #include "rte_ethdev.h" #include "ulp_template_db_enum.h" #include "ulp_template_struct.h" -#define BNXT_OUTER_TUN_SIGNATURE(l3_tun, params) \ +#if RTE_VERSION_NUM(17, 11, 10, 16) == RTE_VERSION +#define RTE_ETHER_ADDR_LEN ETHER_ADDR_LEN +#endif + +#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \ ((l3_tun) && \ ULP_BITMAP_ISSET((params)->act_bitmap.bits, \ BNXT_ULP_ACT_BIT_JUMP)) @@ -24,22 +29,16 @@ !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \ BNXT_ULP_HDR_BIT_O_ETH)) -#define BNXT_FIRST_INNER_TUN_FLOW(state, inner_tun_sig) \ +#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig)) #define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig)) -#define BNXT_OUTER_TUN_FLOW(outer_tun_sig) ((outer_tun_sig)) /* It is invalid to get another outer flow offload request * for the same tunnel, while the outer flow is already offloaded. */ #define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \ ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig)) -/* It is invalid to get another inner flow offload request - * for the same tunnel, while the outer flow is not yet offloaded. - */ -#define BNXT_REJECT_INNER_TUN_FLOW(state, inner_tun_sig) \ - ((state) == BNXT_ULP_FLOW_STATE_TUN_I_CACHED && (inner_tun_sig)) #define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1 #define ULP_TUN_O_IPV4_DIP_INDEX 19 @@ -50,10 +49,10 @@ * requests arrive. * * If inner tunnel flow offload request arrives first then the flow - * state will change from BNXT_ULP_FLOW_STATE_NORMAL to - * BNXT_ULP_FLOW_STATE_TUN_I_CACHED and the following outer tunnel - * flow offload request will change the state of the flow to - * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from BNXT_ULP_FLOW_STATE_TUN_I_CACHED. + * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state. + * The following outer tunnel flow offload request will change the + * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from + * BNXT_ULP_FLOW_STATE_NORMAL. * * If outer tunnel flow offload request arrives first then the flow state * will change from BNXT_ULP_FLOW_STATE_NORMAL to @@ -67,12 +66,15 @@ enum bnxt_ulp_tun_flow_state { BNXT_ULP_FLOW_STATE_NORMAL = 0, BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, - BNXT_ULP_FLOW_STATE_TUN_I_CACHED +}; + +struct ulp_per_port_flow_info { + enum bnxt_ulp_tun_flow_state state; + uint32_t tun_i_cnt; + STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list; }; struct bnxt_tun_cache_entry { - enum bnxt_ulp_tun_flow_state state; - bool valid; bool t_dst_ip_valid; uint8_t t_dmac[RTE_ETHER_ADDR_LEN]; union { @@ -80,13 +82,17 @@ struct bnxt_tun_cache_entry { uint8_t t_dst_ip6[16]; }; uint32_t outer_tun_flow_id; - uint32_t first_inner_tun_flow_id; uint16_t outer_tun_rej_cnt; - uint16_t inner_tun_rej_cnt; - struct ulp_rte_parser_params first_inner_tun_params; + struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS]; }; +void +ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl); + void ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx); +void +ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid); + #endif From patchwork Sun May 30 08:59:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93695 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C8B69A0524; Tue, 1 Jun 2021 09:41:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 96C4841139; Tue, 1 Jun 2021 09:40:05 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id AEEF5411F6 for ; Sun, 30 May 2021 11:01:45 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 6E89A7DC2; Sun, 30 May 2021 02:01:43 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 6E89A7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365305; bh=iSF84H/4fJVY2/hbDsaz+KNDHeouRChYO0fw32DO96U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kfs9o11nNnPBTDTF2v8e2OWxrRi81Bn3Y5zglTh9rFmW+x8M4w7FGgOmGDoRJITMQ sa+qPjFdGJyumMph/YWPTr80RmZVagOV/SDSMr4A6jdOpPg/i9+gO7g3VE7syprhhM hpiq2AeOCSqbKBH+EgYXxECSd+cvKuGJ2ChbaAxc= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:16 +0530 Message-Id: <20210530085929.29695-46-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:54 +0200 Subject: [dpdk-dev] [PATCH 45/58] net/bnxt: add support for generic hash table X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Added support for generic table to enable search of keys that are larger than 16 bits using hash table. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom --- drivers/net/bnxt/tf_ulp/meson.build | 1 + drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 369 + drivers/net/bnxt/tf_ulp/ulp_gen_hash.h | 166 + drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 130 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 30 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 90 +- .../net/bnxt/tf_ulp/ulp_template_db_class.c | 17724 +++++++++------- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 159 +- .../tf_ulp/ulp_template_db_stingray_class.c | 6 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 54 +- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 2 + .../tf_ulp/ulp_template_db_wh_plus_class.c | 882 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 5 + drivers/net/bnxt/tf_ulp/ulp_utils.c | 8 + drivers/net/bnxt/tf_ulp/ulp_utils.h | 3 + 15 files changed, 11669 insertions(+), 7960 deletions(-) create mode 100644 drivers/net/bnxt/tf_ulp/ulp_gen_hash.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_gen_hash.h diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build index 701a510f27..c7ec5a3161 100644 --- a/drivers/net/bnxt/tf_ulp/meson.build +++ b/drivers/net/bnxt/tf_ulp/meson.build @@ -23,6 +23,7 @@ sources += files( 'ulp_fc_mgr.c', 'ulp_tun.c', 'ulp_gen_tbl.c', + 'ulp_gen_hash.c', 'ulp_rte_handler_tbl.c', 'ulp_template_db_wh_plus_act.c', 'ulp_template_db_wh_plus_class.c', diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c new file mode 100644 index 0000000000..3c6e7fe924 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c @@ -0,0 +1,369 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2021 Broadcom + * All rights reserved. + */ + +#include +#include +#include "bnxt_tf_common.h" +#include "ulp_gen_hash.h" +#include "ulp_utils.h" +#include "tf_hash.h" + +static +int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist, + uint32_t *index) +{ + uint64_t bentry; + uint32_t idx = 0, jdx = 0; + + /* Iterate all numbers that have all 1's */ + do { + bentry = blist->bdata[idx++]; + } while (bentry == -1UL && idx < blist->bsize); + + if (idx < blist->bsize) { + if (bentry) + jdx = __builtin_clzl(~bentry); + *index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx; + ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx); + return 0; + } + jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE); + BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx); + return -1; +} + +static +int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist, + uint32_t index) +{ + uint32_t idx = 0, jdx; + + idx = index / ULP_INDEX_BITMAP_SIZE; + if (idx >= blist->bsize) { + BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx, + blist->bsize); + return -EINVAL; + } + jdx = index % ULP_INDEX_BITMAP_SIZE; + ULP_INDEX_BITMAP_RESET(blist->bdata[idx], jdx); + return 0; +} + +/* + * Initialize the Generic Hash table + * + * cparams [in] Pointer to hash create params list + * hash_tbl [out] the pointer to created hash table + * + * returns 0 on success + */ +int32_t +ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams, + struct ulp_gen_hash_tbl **hash_table) +{ + struct ulp_gen_hash_tbl *hash_tbl = NULL; + int32_t rc = 0; + uint32_t size = 0; + + /* validate the arguments */ + if (!hash_table || !cparams) { + BNXT_TF_DBG(ERR, "invalid arguments\n"); + return -EINVAL; + } + + /* validate the size parameters */ + if (ulp_util_is_power_of_2(cparams->num_hash_tbl_entries) || + ulp_util_is_power_of_2(cparams->num_key_entries) || + (cparams->num_buckets % ULP_HASH_BUCKET_ROW_SZ)) { + BNXT_TF_DBG(ERR, "invalid arguments for hash tbl\n"); + return -EINVAL; + } + + /* validate the size of the hash table size */ + if (cparams->num_hash_tbl_entries >= ULP_GEN_HASH_MAX_TBL_SIZE) { + BNXT_TF_DBG(ERR, "invalid size for hash tbl\n"); + return -EINVAL; + } + + hash_tbl = rte_zmalloc("Generic hash table", + sizeof(struct ulp_gen_hash_tbl), 0); + if (!hash_tbl) { + BNXT_TF_DBG(ERR, "failed to alloc mem for hash tbl\n"); + return -ENOMEM; + } + *hash_table = hash_tbl; + /* allocate the memory for the hash key table */ + hash_tbl->num_key_entries = cparams->num_key_entries; + hash_tbl->key_tbl.data_size = cparams->key_size; + hash_tbl->key_tbl.mem_size = cparams->key_size * + (cparams->num_key_entries + 1); + hash_tbl->key_tbl.key_data = rte_zmalloc("Generic hash keys", + hash_tbl->key_tbl.mem_size, 0); + if (!hash_tbl->key_tbl.key_data) { + BNXT_TF_DBG(ERR, "failed to alloc mem for hash key\n"); + rc = -ENOMEM; + goto init_error; + } + + /* allocate the memory for the hash table */ + hash_tbl->hash_bkt_num = cparams->num_buckets / ULP_HASH_BUCKET_ROW_SZ; + hash_tbl->hash_tbl_size = cparams->num_hash_tbl_entries; + size = hash_tbl->hash_tbl_size * hash_tbl->hash_bkt_num * + sizeof(struct ulp_hash_bucket_entry); + hash_tbl->hash_list = rte_zmalloc("Generic hash table list", size, + ULP_BUFFER_ALIGN_64_BYTE); + if (!hash_tbl->hash_list) { + BNXT_TF_DBG(ERR, "failed to alloc mem for hash tbl\n"); + rc = -ENOMEM; + goto init_error; + } + + /* calculate the hash_mask based on the tbl size */ + size = 1; + while (size < hash_tbl->hash_tbl_size) + size = size << 1; + hash_tbl->hash_mask = size - 1; + + /* allocate the memory for the bit allocator */ + size = (cparams->num_key_entries / sizeof(uint64_t)) + 1; + hash_tbl->bit_list.bsize = size; + hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size, + ULP_BUFFER_ALIGN_64_BYTE); + if (!hash_tbl->bit_list.bdata) { + BNXT_TF_DBG(ERR, "failed to alloc mem for hash bit list\n"); + rc = -ENOMEM; + goto init_error; + } + return rc; + +init_error: + if (hash_tbl) + ulp_gen_hash_tbl_list_deinit(hash_tbl); + return rc; +} + +/* + * Free the generic hash table + * + * hash_tbl [in] the pointer to hash table + * + * returns 0 on success + */ +int32_t +ulp_gen_hash_tbl_list_deinit(struct ulp_gen_hash_tbl *hash_tbl) +{ + if (!hash_tbl) + return -EINVAL; + + if (hash_tbl->key_tbl.key_data) { + rte_free(hash_tbl->key_tbl.key_data); + hash_tbl->key_tbl.key_data = NULL; + } + + if (hash_tbl->hash_list) { + rte_free(hash_tbl->hash_list); + hash_tbl->hash_list = NULL; + } + + if (hash_tbl->bit_list.bdata) { + rte_free(hash_tbl->bit_list.bdata); + hash_tbl->bit_list.bdata = NULL; + } + + rte_free(hash_tbl); + return 0; +} + +/* + * Search the generic hash table using key data + * + * hash_tbl [in] the pointer to hash table + * entry [in/out] pointer to hash entry details. + * + * returns 0 on success and marks search flag as found. + */ +int32_t +ulp_gen_hash_tbl_list_key_search(struct ulp_gen_hash_tbl *hash_tbl, + struct ulp_gen_hash_entry_params *entry) +{ + uint32_t hash_id, key_idx, idx; + uint16_t *bucket; + int32_t miss_idx = ULP_HASH_BUCKET_INVAL; + + /* validate the arguments */ + if (!hash_tbl || !entry || !entry->key_data || entry->key_length != + hash_tbl->key_tbl.data_size) { + BNXT_TF_DBG(ERR, "invalid arguments\n"); + return -EINVAL; + } + + /* calculate the hash */ + hash_id = tf_hash_calc_crc32(entry->key_data, + hash_tbl->key_tbl.data_size); + hash_id = (uint16_t)(((hash_id >> 16) & 0xffff) ^ (hash_id & 0xffff)); + hash_id &= hash_tbl->hash_mask; + hash_id = hash_id * hash_tbl->hash_bkt_num; + + /* Iterate the bucket list */ + bucket = (uint16_t *)&hash_tbl->hash_list[hash_id]; + for (idx = 0; idx < (hash_tbl->hash_bkt_num * ULP_HASH_BUCKET_ROW_SZ); + idx++, bucket++) { + if (ULP_HASH_BUCKET_INUSE(bucket)) { + /* compare the key contents */ + key_idx = ULP_HASH_BUCKET_INDEX(bucket); + if (key_idx >= hash_tbl->num_key_entries) { + BNXT_TF_DBG(ERR, "Hash table corruption\n"); + return -EINVAL; + } + if (!memcmp(entry->key_data, + &hash_tbl->key_tbl.key_data[key_idx * + hash_tbl->key_tbl.data_size], + hash_tbl->key_tbl.data_size)) { + /* Found the entry */ + entry->search_flag = ULP_GEN_HASH_SEARCH_FOUND; + entry->hash_index = ULP_HASH_INDEX_CALC(hash_id, + idx); + entry->key_idx = key_idx; + return 0; + } + } else if (miss_idx == ULP_HASH_BUCKET_INVAL) { + miss_idx = idx; + } + } + + if (miss_idx == ULP_HASH_BUCKET_INVAL) { + entry->search_flag = ULP_GEN_HASH_SEARCH_FULL; + } else { + entry->search_flag = ULP_GEN_HASH_SEARCH_MISSED; + entry->hash_index = ULP_HASH_INDEX_CALC(hash_id, miss_idx); + } + return 0; +} + +/* + * Search the generic hash table using hash index + * + * hash_tbl [in] the pointer to hash table + * entry [in/out] pointer to hash entry details. + * + * returns 0 on success and marks search flag as found. + */ +int32_t +ulp_gen_hash_tbl_list_index_search(struct ulp_gen_hash_tbl *hash_tbl, + struct ulp_gen_hash_entry_params *entry) +{ + uint32_t idx; + uint16_t *bucket; + + /* validate the arguments */ + if (!hash_tbl || !entry) { + BNXT_TF_DBG(ERR, "invalid arguments\n"); + return -EINVAL; + } + + idx = ULP_HASH_GET_H_INDEX(entry->hash_index); + if (idx > (hash_tbl->hash_tbl_size * hash_tbl->hash_bkt_num)) { + BNXT_TF_DBG(ERR, "invalid hash index %x\n", idx); + return -EINVAL; + } + bucket = (uint16_t *)&hash_tbl->hash_list[idx]; + idx = ULP_HASH_GET_B_INDEX(entry->hash_index); + if (idx >= (hash_tbl->hash_bkt_num * ULP_HASH_BUCKET_ROW_SZ)) { + BNXT_TF_DBG(ERR, "invalid bucket index %x\n", idx); + return -EINVAL; + } + bucket += idx; + if (ULP_HASH_BUCKET_INUSE(bucket)) { + entry->key_idx = ULP_HASH_BUCKET_INDEX(bucket); + entry->search_flag = ULP_GEN_HASH_SEARCH_FOUND; + } else { + entry->search_flag = ULP_GEN_HASH_SEARCH_MISSED; + return -ENOENT; + } + return 0; +} + +/* + * Add the entry to the generic hash table + * + * hash_tbl [in] the pointer to hash table + * entry [in/out] pointer to hash entry details. Fill the hash index and + * key data details to be added. + * + * returns 0 on success + * + */ +int32_t +ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, + struct ulp_gen_hash_entry_params *entry) +{ + int32_t rc = 0; + uint16_t *bucket; + uint32_t idx, key_index; + + /* add the entry */ + idx = ULP_HASH_GET_H_INDEX(entry->hash_index); + bucket = (uint16_t *)&hash_tbl->hash_list[idx]; + bucket += ULP_HASH_GET_B_INDEX(entry->hash_index); + if (ulp_bit_alloc_list_alloc(&hash_tbl->bit_list, &key_index)) { + BNXT_TF_DBG(ERR, "Error in bit list alloc\n"); + return -ENOMEM; + } + + /* Update the hash entry */ + ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index); + + /* update the hash key and key index */ + entry->key_idx = key_index; + key_index = key_index * hash_tbl->key_tbl.data_size; + memcpy(&hash_tbl->key_tbl.key_data[key_index], entry->key_data, + hash_tbl->key_tbl.data_size); + + return rc; +} + +/* + * Delete the entry in the generic hash table + * + * hash_tbl [in] the pointer to hash table + * entry [in] pointer to hash entry details. Fill the hash index details to be + * deleted. + * + * returns 0 on success + */ +int32_t +ulp_gen_hash_tbl_list_del(struct ulp_gen_hash_tbl *hash_tbl, + struct ulp_gen_hash_entry_params *entry) +{ + uint16_t *bucket; + uint32_t idx, key_index; + + /* delete the entry */ + idx = ULP_HASH_GET_H_INDEX(entry->hash_index); + bucket = (uint16_t *)&hash_tbl->hash_list[idx]; + bucket += ULP_HASH_GET_B_INDEX(entry->hash_index); + + /* Get the hash entry */ + key_index = ULP_HASH_BUCKET_INDEX(bucket); + if (key_index >= hash_tbl->num_key_entries) { + BNXT_TF_DBG(ERR, "Hash table corruption\n"); + return -EINVAL; + } + + /* reset the bit in the bit allocator */ + if (ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, + key_index)) { + BNXT_TF_DBG(ERR, "Error is bit list dealloc\n"); + return -EINVAL; + } + + /* erase key details and bucket details */ + key_index = key_index * hash_tbl->key_tbl.data_size; + memset(&hash_tbl->key_tbl.key_data[key_index], 0, + hash_tbl->key_tbl.data_size); + ULP_HASH_BUCKET_CLEAR(bucket); + + return 0; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h new file mode 100644 index 0000000000..543ef79d30 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2021 Broadcom + * All rights reserved. + */ + +#ifndef _ULP_GEN_HASH_H_ +#define _ULP_GEN_HASH_H_ + +#include "bnxt.h" + +#define ULP_GEN_HASH_MAX_TBL_SIZE BIT(15) + +/* Structure to store the hash key details */ +struct ulp_gen_hash_key_entry { + uint32_t mem_size; + uint32_t data_size; + uint8_t *key_data; +}; + +/* Macros for bucket entries */ +#define ULP_HASH_BUCKET_VALID 0x8000 +#define ULP_HASH_BUCKET_IDX_MSK 0x7FFF +#define ULP_HASH_BUCKET_ROW_SZ 4 +#define ULP_HASH_BUCKET_INUSE(x) ((*(x)) & (ULP_HASH_BUCKET_VALID)) +#define ULP_HASH_BUCKET_MARK_INUSE(x, y) \ + ((*(x)) = ((y) & ULP_HASH_BUCKET_IDX_MSK) | (ULP_HASH_BUCKET_VALID)) +#define ULP_HASH_BUCKET_CLEAR(x) ((*(x)) = 0) +#define ULP_HASH_BUCKET_INDEX(x) ((*(x)) & (ULP_HASH_BUCKET_IDX_MSK)) +#define ULP_HASH_INDEX_CALC(id1, id2) (((id1) << 16) | ((id2) & 0xFFFF)) +#define ULP_HASH_GET_H_INDEX(x) (((x) >> 16) & 0xFFFF) +#define ULP_HASH_GET_B_INDEX(x) ((x) & 0xFFFF) +#define ULP_HASH_BUCKET_INVAL -1 + +/* Structure for the hash bucket details */ +struct ulp_hash_bucket_entry { + uint64_t *bucket; +}; + +/* Structure for the hash bucket details */ +struct bit_alloc_list { + uint32_t bsize; + uint64_t *bdata; +}; + +/* + * Structure to store the generic tbl container + * The ref count and byte data contain list of "num_elem" elements. + * The size of each entry in byte_data is of size byte_data_size. + */ +struct ulp_gen_hash_tbl { + /* memory to store hash key */ + uint32_t num_key_entries; + struct ulp_gen_hash_key_entry key_tbl; + + /* Hash table memory */ + uint32_t hash_tbl_size; + uint32_t hash_bkt_num; + struct ulp_hash_bucket_entry *hash_list; + uint32_t hash_mask; + + /* Bit allocator - to allocate key_res index */ + struct bit_alloc_list bit_list; +}; + +/* structure to pass hash creation params */ +struct ulp_hash_create_params { + /* this is size of the hash tbl - try to keep it to power of 2.*/ + uint32_t num_hash_tbl_entries; + /* Bucket size must be multiple of 4 */ + uint32_t num_buckets; + /* This is size of hash key and data - try to keep it to power of 2 */ + /* This value has to be less than 2^15 */ + uint32_t num_key_entries; + /* the size of the hash key in bytes */ + uint32_t key_size; +}; + +enum ulp_gen_hash_search_flag { + ULP_GEN_HASH_SEARCH_MISSED = 1, + ULP_GEN_HASH_SEARCH_FOUND = 2, + ULP_GEN_HASH_SEARCH_FULL = 3 +}; + +/* structure to pass hash entry */ +struct ulp_gen_hash_entry_params { + uint8_t *key_data; + uint32_t key_length; + enum ulp_gen_hash_search_flag search_flag; + uint32_t hash_index; + uint32_t key_idx; +}; + +/* + * Initialize the Generic Hash table + * + * cparams [in] Pointer to hash create params list + * hash_tbl [out] the pointer to created hash table + * + * returns 0 on success + */ +int32_t +ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams, + struct ulp_gen_hash_tbl **hash_tbl); + +/* + * Free the generic hash table + * + * hash_tbl [in] the pointer to hash table + * + * returns 0 on success + */ +int32_t +ulp_gen_hash_tbl_list_deinit(struct ulp_gen_hash_tbl *hash_tbl); + +/* + * Search the generic hash table using key data + * + * hash_tbl [in] the pointer to hash table + * entry [in/out] pointer to hash entry details. + * + * returns 0 on success and marks search flag as found. + */ +int32_t +ulp_gen_hash_tbl_list_key_search(struct ulp_gen_hash_tbl *hash_tbl, + struct ulp_gen_hash_entry_params *entry); + +/* + * Search the generic hash table using hash index + * + * hash_tbl [in] the pointer to hash table + * entry [in/out] pointer to hash entry details. + * + * returns 0 on success and marks search flag as found. + */ +int32_t +ulp_gen_hash_tbl_list_index_search(struct ulp_gen_hash_tbl *hash_tbl, + struct ulp_gen_hash_entry_params *entry); + +/* + * Add the entry to the generic hash table + * + * hash_tbl [in] the pointer to hash table + * entry [in/out] pointer to hash entry details. Fill the hash index and + * key data details to be added. + * + * returns 0 on success + * + */ +int32_t +ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, + struct ulp_gen_hash_entry_params *entry); + +/* + * Delete the entry in the generic hash table + * + * hash_tbl [in] the pointer to hash table + * entry [in] pointer to hash entry details. Fill the hash index details to be + * deleted. + * + * returns 0 on success + */ +int32_t +ulp_gen_hash_tbl_list_del(struct ulp_gen_hash_tbl *hash_tbl, + struct ulp_gen_hash_entry_params *entry); + +#endif /* _ULP_GEN_HASH_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c index a762408d77..0b91520930 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c @@ -33,6 +33,7 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data) { struct bnxt_ulp_generic_tbl_params *tbl; struct ulp_mapper_gen_tbl_list *entry; + struct ulp_hash_create_params cparams; uint32_t idx, size; /* Allocate the generic tables. */ @@ -45,6 +46,8 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data) } entry = &mapper_data->gen_tbl_list[idx]; if (tbl->result_num_entries != 0) { + /* assign the name */ + entry->gen_tbl_name = tbl->name; /* add 4 bytes for reference count */ entry->mem_data_size = (tbl->result_num_entries + 1) * (tbl->result_num_bytes + sizeof(uint32_t)); @@ -54,8 +57,8 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data) entry->mem_data_size, 0); if (!entry->mem_data) { BNXT_TF_DBG(ERR, - "Failed to allocate gen table %d\n", - idx); + "%s:Failed to alloc gen table %d\n", + tbl->name, idx); return -ENOMEM; } /* Populate the generic table container */ @@ -66,6 +69,23 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data) size = sizeof(uint32_t) * (tbl->result_num_entries + 1); entry->container.byte_data = &entry->mem_data[size]; entry->container.byte_order = tbl->result_byte_order; + } else { + BNXT_TF_DBG(ERR, "%s:Invalid gen table num of ent %d\n", + tbl->name, idx); + return -EINVAL; + } + if (tbl->hash_tbl_entries) { + cparams.key_size = tbl->key_num_bytes; + cparams.num_buckets = tbl->num_buckets; + cparams.num_hash_tbl_entries = tbl->hash_tbl_entries; + cparams.num_key_entries = tbl->result_num_entries; + if (ulp_gen_hash_tbl_list_init(&cparams, + &entry->hash_tbl)) { + BNXT_TF_DBG(ERR, + "%s: Failed to alloc hash tbl %d\n", + tbl->name, idx); + return -ENOMEM; + } } } /* success */ @@ -93,6 +113,10 @@ ulp_mapper_generic_tbl_list_deinit(struct bnxt_ulp_mapper_data *mapper_data) rte_free(tbl_list->mem_data); tbl_list->mem_data = NULL; } + if (tbl_list->hash_tbl) { + ulp_gen_hash_tbl_list_deinit(tbl_list->hash_tbl); + tbl_list->hash_tbl = NULL; + } } /* success */ return 0; @@ -101,32 +125,21 @@ ulp_mapper_generic_tbl_list_deinit(struct bnxt_ulp_mapper_data *mapper_data) /* * Get the generic table list entry * - * ulp_ctxt [in] - Ptr to ulp_context - * tbl_idx [in] - Table index to the generic table list + * tbl_list [in] - Ptr to generic table * key [in] - Key index to the table * entry [out] - output will include the entry if found * * returns 0 on success. */ int32_t -ulp_mapper_gen_tbl_entry_get(struct bnxt_ulp_context *ulp, - uint32_t tbl_idx, +ulp_mapper_gen_tbl_entry_get(struct ulp_mapper_gen_tbl_list *tbl_list, uint32_t key, struct ulp_mapper_gen_tbl_entry *entry) { - struct bnxt_ulp_mapper_data *mapper_data; - struct ulp_mapper_gen_tbl_list *tbl_list; - - mapper_data = bnxt_ulp_cntxt_ptr2_mapper_data_get(ulp); - if (!mapper_data || tbl_idx >= BNXT_ULP_GEN_TBL_MAX_SZ || - !entry) { - BNXT_TF_DBG(ERR, "invalid arguments %x:%x\n", tbl_idx, key); - return -EINVAL; - } /* populate the output and return the values */ - tbl_list = &mapper_data->gen_tbl_list[tbl_idx]; if (key > tbl_list->container.num_elem) { - BNXT_TF_DBG(ERR, "invalid key %x:%x\n", key, + BNXT_TF_DBG(ERR, "%s: invalid key %x:%x\n", + tbl_list->gen_tbl_name, key, tbl_list->container.num_elem); return -EINVAL; } @@ -245,9 +258,13 @@ int32_t ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, struct ulp_flow_db_res_params *res) { + struct bnxt_ulp_mapper_data *mapper_data; + struct ulp_mapper_gen_tbl_list *gen_tbl_list; struct ulp_mapper_gen_tbl_entry entry; + struct ulp_gen_hash_entry_params hash_entry; int32_t tbl_idx; uint32_t fid = 0; + uint32_t key_idx; /* Extract the resource sub type and direction */ tbl_idx = ulp_mapper_gen_tbl_idx_calculate(res->resource_sub_type, @@ -258,9 +275,30 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } + mapper_data = bnxt_ulp_cntxt_ptr2_mapper_data_get(ulp_ctx); + if (!mapper_data) { + BNXT_TF_DBG(ERR, "invalid ulp context %x\n", tbl_idx); + return -EINVAL; + } + /* get the generic table */ + gen_tbl_list = &mapper_data->gen_tbl_list[tbl_idx]; + /* Get the generic table entry*/ - if (ulp_mapper_gen_tbl_entry_get(ulp_ctx, tbl_idx, res->resource_hndl, - &entry)) { + if (gen_tbl_list->hash_tbl) { + /* use the hash index to get the value */ + hash_entry.hash_index = (uint32_t)res->resource_hndl; + if (ulp_gen_hash_tbl_list_index_search(gen_tbl_list->hash_tbl, + &hash_entry)) { + BNXT_TF_DBG(ERR, "Unable to find has entry %x:%x\n", + tbl_idx, hash_entry.hash_index); + return -EINVAL; + } + key_idx = hash_entry.key_idx; + + } else { + key_idx = (uint32_t)res->resource_hndl; + } + if (ulp_mapper_gen_tbl_entry_get(gen_tbl_list, key_idx, &entry)) { BNXT_TF_DBG(ERR, "Gen tbl entry get failed %x:%" PRIX64 "\n", tbl_idx, res->resource_hndl); return -EINVAL; @@ -294,8 +332,62 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, fid)) BNXT_TF_DBG(ERR, "Error in deleting shared flow id %x\n", fid); + /* Delete the entry from the hash table */ + if (gen_tbl_list->hash_tbl) + ulp_gen_hash_tbl_list_del(gen_tbl_list->hash_tbl, &hash_entry); + /* clear the byte data of the generic table entry */ memset(entry.byte_data, 0, entry.byte_data_size); return 0; } + +/* + * Write the generic table list hash entry + * + * tbl_list [in] - pointer to the generic table list + * hash_entry [in] - Hash table entry + * gen_tbl_ent [out] - generic table entry + * + * returns 0 on success. + */ +int32_t +ulp_mapper_gen_tbl_hash_entry_add(struct ulp_mapper_gen_tbl_list *tbl_list, + struct ulp_gen_hash_entry_params *hash_entry, + struct ulp_mapper_gen_tbl_entry *gen_tbl_ent) +{ + uint32_t key; + int32_t rc = 0; + + switch (hash_entry->search_flag) { + case ULP_GEN_HASH_SEARCH_FOUND: + BNXT_TF_DBG(ERR, "%s: gen hash entry already present\n", + tbl_list->gen_tbl_name); + return -EINVAL; + case ULP_GEN_HASH_SEARCH_FULL: + BNXT_TF_DBG(ERR, "%s: gen hash table is full\n", + tbl_list->gen_tbl_name); + return -EINVAL; + case ULP_GEN_HASH_SEARCH_MISSED: + rc = ulp_gen_hash_tbl_list_add(tbl_list->hash_tbl, hash_entry); + if (rc) { + BNXT_TF_DBG(ERR, "%s: gen hash table add failed\n", + tbl_list->gen_tbl_name); + return -EINVAL; + } + key = hash_entry->key_idx; + gen_tbl_ent->ref_count = &tbl_list->container.ref_count[key]; + gen_tbl_ent->byte_data_size = + tbl_list->container.byte_data_size; + gen_tbl_ent->byte_data = &tbl_list->container.byte_data[key * + gen_tbl_ent->byte_data_size]; + gen_tbl_ent->byte_order = tbl_list->container.byte_order; + break; + default: + BNXT_TF_DBG(ERR, "%s: invalid search flag\n", + tbl_list->gen_tbl_name); + return -EINVAL; + } + + return rc; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h index 6236dc3ca2..7f4a877e9a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h @@ -6,6 +6,8 @@ #ifndef _ULP_GEN_TBL_H_ #define _ULP_GEN_TBL_H_ +#include "ulp_gen_hash.h" + /* Macros for reference count manipulation */ #define ULP_GEN_TBL_REF_CNT_INC(entry) {*(entry)->ref_count += 1; } #define ULP_GEN_TBL_REF_CNT_DEC(entry) {*(entry)->ref_count -= 1; } @@ -16,9 +18,9 @@ /* Structure to pass the generic table values across APIs */ struct ulp_mapper_gen_tbl_entry { - uint32_t *ref_count; - uint32_t byte_data_size; - uint8_t *byte_data; + uint32_t *ref_count; + uint32_t byte_data_size; + uint8_t *byte_data; enum bnxt_ulp_byte_order byte_order; }; @@ -39,9 +41,11 @@ struct ulp_mapper_gen_tbl_cont { /* Structure to store the generic tbl container */ struct ulp_mapper_gen_tbl_list { + const char *gen_tbl_name; struct ulp_mapper_gen_tbl_cont container; uint32_t mem_data_size; uint8_t *mem_data; + struct ulp_gen_hash_tbl *hash_tbl; }; /* Forward declaration */ @@ -73,16 +77,14 @@ ulp_mapper_generic_tbl_list_deinit(struct bnxt_ulp_mapper_data *mapper_data); /* * Get the generic table list entry * - * ulp_ctxt [in] - Ptr to ulp_context - * tbl_idx [in] - Table index to the generic table list + * tbl_list [in] - Ptr to generic table * key [in] - Key index to the table * entry [out] - output will include the entry if found * * returns 0 on success. */ int32_t -ulp_mapper_gen_tbl_entry_get(struct bnxt_ulp_context *ulp, - uint32_t tbl_idx, +ulp_mapper_gen_tbl_entry_get(struct ulp_mapper_gen_tbl_list *tbl_list, uint32_t key, struct ulp_mapper_gen_tbl_entry *entry); @@ -140,4 +142,18 @@ int32_t ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, struct ulp_flow_db_res_params *res); +/* + * Write the generic table list hash entry + * + * tbl_list [in] - pointer to the generic table list + * hash_entry [in] - Hash table entry + * gen_tbl_ent [out] - generic table entry + * + * returns 0 on success. + */ +int32_t +ulp_mapper_gen_tbl_hash_entry_add(struct ulp_mapper_gen_tbl_list *tbl_list, + struct ulp_gen_hash_entry_params *hash_entry, + struct ulp_mapper_gen_tbl_entry *gen_tbl_ent); + #endif /* _ULP_EN_TBL_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 27c7c871b1..996b80ebbf 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -38,7 +38,6 @@ ulp_mapper_tmpl_name_str(enum bnxt_ulp_template_type tmpl_type) } } - static struct bnxt_ulp_glb_resource_info * ulp_mapper_glb_resource_info_list_get(uint32_t *num_entries) { @@ -2486,15 +2485,17 @@ static int32_t ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { + struct ulp_mapper_gen_tbl_list *gen_tbl_list; struct bnxt_ulp_mapper_key_info *kflds; struct ulp_flow_db_res_params fid_parms; struct ulp_mapper_gen_tbl_entry gen_tbl_ent, *g; + struct ulp_gen_hash_entry_params hash_entry; uint16_t tmplen; struct ulp_blob key, data; uint8_t *cache_key; int32_t tbl_idx; - uint32_t i, ckey, num_kflds = 0; - uint32_t gen_tbl_hit = 0, fdb_write = 0; + uint32_t i, num_kflds = 0, key_index = 0; + uint32_t gen_tbl_miss = 1, fdb_write = 0; uint8_t *byte_data; int32_t rc = 0; @@ -2504,6 +2505,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, BNXT_TF_DBG(ERR, "Failed to get key fields\n"); return -EINVAL; } + if (!ulp_blob_init(&key, tbl->key_bit_size, parms->device_params->byte_order)) { BNXT_TF_DBG(ERR, "Failed to alloc blob\n"); @@ -2533,17 +2535,51 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* The_key is a byte array convert it to a search index */ cache_key = ulp_blob_data_get(&key, &tmplen); - memcpy(&ckey, cache_key, sizeof(ckey)); - /* Get the generic table entry */ - rc = ulp_mapper_gen_tbl_entry_get(parms->ulp_ctx, - tbl_idx, ckey, &gen_tbl_ent); - if (rc) { - BNXT_TF_DBG(ERR, - "Failed to create key for Gen tbl rc=%d\n", rc); - return -EINVAL; + /* get the generic table */ + gen_tbl_list = &parms->mapper_data->gen_tbl_list[tbl_idx]; + + /* Check if generic hash table */ + if (gen_tbl_list->hash_tbl) { + if (tbl->gen_tbl_lkup_type != + BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH) { + BNXT_TF_DBG(ERR, "%s: Invalid template lkup type\n", + gen_tbl_list->gen_tbl_name); + return -EINVAL; + } + hash_entry.key_data = cache_key; + hash_entry.key_length = ULP_BITS_2_BYTE(tmplen); + rc = ulp_gen_hash_tbl_list_key_search(gen_tbl_list->hash_tbl, + &hash_entry); + if (rc) { + BNXT_TF_DBG(ERR, "%s: hash tbl search failed\n", + gen_tbl_list->gen_tbl_name); + return rc; + } + if (hash_entry.search_flag == ULP_GEN_HASH_SEARCH_FOUND) { + key_index = hash_entry.key_idx; + /* Get the generic table entry */ + if (ulp_mapper_gen_tbl_entry_get(gen_tbl_list, + key_index, + &gen_tbl_ent)) + return -EINVAL; + /* store the hash index in the fdb */ + key_index = hash_entry.hash_index; + } + } else { + /* convert key to index directly */ + memcpy(&key_index, cache_key, ULP_BITS_2_BYTE(tmplen)); + /* Get the generic table entry */ + if (ulp_mapper_gen_tbl_entry_get(gen_tbl_list, key_index, + &gen_tbl_ent)) + return -EINVAL; } switch (tbl->tbl_opcode) { case BNXT_ULP_GENERIC_TBL_OPC_READ: + if (gen_tbl_list->hash_tbl) { + if (hash_entry.search_flag != ULP_GEN_HASH_SEARCH_FOUND) + break; /* nothing to be done , no entry */ + } + /* check the reference count */ if (ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) { g = &gen_tbl_ent; @@ -2563,16 +2599,24 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, } /* it is a hit */ - gen_tbl_hit = 1; + gen_tbl_miss = 0; fdb_write = 1; } break; case BNXT_ULP_GENERIC_TBL_OPC_WRITE: + if (gen_tbl_list->hash_tbl) { + rc = ulp_mapper_gen_tbl_hash_entry_add(gen_tbl_list, + &hash_entry, + &gen_tbl_ent); + if (rc) + return rc; + /* store the hash index in the fdb */ + key_index = hash_entry.hash_index; + } /* check the reference count */ if (ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) { /* a hit then error */ - BNXT_TF_DBG(ERR, "generic entry already present %x\n", - ckey); + BNXT_TF_DBG(ERR, "generic entry already present\n"); return -EINVAL; /* success */ } @@ -2602,7 +2646,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* increment the reference count */ ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent); fdb_write = 1; - parms->shared_hndl = (uint64_t)tbl_idx << 32 | ckey; + parms->shared_hndl = (uint64_t)tbl_idx << 32 | key_index; break; default: BNXT_TF_DBG(ERR, "Invalid table opcode %x\n", tbl->tbl_opcode); @@ -2611,11 +2655,11 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* Set the generic entry hit */ rc = ulp_regfile_write(parms->regfile, - BNXT_ULP_RF_IDX_GENERIC_TBL_HIT, - tfp_cpu_to_be_64(gen_tbl_hit)); + BNXT_ULP_RF_IDX_GENERIC_TBL_MISS, + tfp_cpu_to_be_64(gen_tbl_miss)); if (rc) { BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n", - BNXT_ULP_RF_IDX_GENERIC_TBL_HIT); + BNXT_ULP_RF_IDX_GENERIC_TBL_MISS); return -EIO; } @@ -2625,7 +2669,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.direction = tbl->direction; fid_parms.resource_func = tbl->resource_func; fid_parms.resource_sub_type = tbl->resource_sub_type; - fid_parms.resource_hndl = ckey; + fid_parms.resource_hndl = key_index; fid_parms.critical_resource = tbl->critical_resource; rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) @@ -2947,13 +2991,13 @@ ulp_mapper_conflict_resolution_process(struct bnxt_ulp_mapper_parms *parms, BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE) { /* Perform the check that generic table is hit or not */ if (!ulp_regfile_read(parms->regfile, - BNXT_ULP_RF_IDX_GENERIC_TBL_HIT, + BNXT_ULP_RF_IDX_GENERIC_TBL_MISS, ®val)) { BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", - BNXT_ULP_RF_IDX_GENERIC_TBL_HIT); + BNXT_ULP_RF_IDX_GENERIC_TBL_MISS); return -EINVAL; } - if (!regval) { + if (regval) { /* not a hit so no need to check flow sign*/ *res = 1; return rc; @@ -3204,7 +3248,7 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx, * remaining resources. Don't return */ BNXT_TF_DBG(ERR, - "Flow[%d][0x%x] Res[%d][0x%016" PRIx64 + "Flow[%d][0x%x] Res[%d][0x%016" PRIX64 "] failed rc=%d.\n", flow_type, fid, res_parms.resource_func, res_parms.resource_hndl, trc); diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index 0ca0d2b366..5c7b95bd08 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Dec 16 16:37:41 2020 */ +/* date: Fri Jan 29 09:44:41 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -42,3844 +42,3964 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { [BNXT_ULP_CLASS_HID_4e61] = 24, [BNXT_ULP_CLASS_HID_2561] = 25, [BNXT_ULP_CLASS_HID_2bad] = 26, - [BNXT_ULP_CLASS_HID_26f1] = 27, - [BNXT_ULP_CLASS_HID_13cf1] = 28, - [BNXT_ULP_CLASS_HID_252f1] = 29, - [BNXT_ULP_CLASS_HID_30c25] = 30, - [BNXT_ULP_CLASS_HID_0051] = 31, - [BNXT_ULP_CLASS_HID_11651] = 32, - [BNXT_ULP_CLASS_HID_22c51] = 33, - [BNXT_ULP_CLASS_HID_34251] = 34, - [BNXT_ULP_CLASS_HID_5385] = 35, - [BNXT_ULP_CLASS_HID_10cc9] = 36, - [BNXT_ULP_CLASS_HID_222c9] = 37, - [BNXT_ULP_CLASS_HID_338c9] = 38, - [BNXT_ULP_CLASS_HID_1d69] = 39, - [BNXT_ULP_CLASS_HID_13369] = 40, - [BNXT_ULP_CLASS_HID_24969] = 41, - [BNXT_ULP_CLASS_HID_3025d] = 42, - [BNXT_ULP_CLASS_HID_20b5] = 43, - [BNXT_ULP_CLASS_HID_136b5] = 44, - [BNXT_ULP_CLASS_HID_24cb5] = 45, - [BNXT_ULP_CLASS_HID_305f9] = 46, - [BNXT_ULP_CLASS_HID_5721] = 47, - [BNXT_ULP_CLASS_HID_11015] = 48, - [BNXT_ULP_CLASS_HID_22615] = 49, - [BNXT_ULP_CLASS_HID_33c15] = 50, - [BNXT_ULP_CLASS_HID_4d59] = 51, - [BNXT_ULP_CLASS_HID_1068d] = 52, - [BNXT_ULP_CLASS_HID_21c8d] = 53, - [BNXT_ULP_CLASS_HID_3328d] = 54, - [BNXT_ULP_CLASS_HID_172d] = 55, - [BNXT_ULP_CLASS_HID_12d2d] = 56, - [BNXT_ULP_CLASS_HID_2432d] = 57, - [BNXT_ULP_CLASS_HID_3592d] = 58, - [BNXT_ULP_CLASS_HID_1a49] = 59, - [BNXT_ULP_CLASS_HID_13049] = 60, - [BNXT_ULP_CLASS_HID_24649] = 61, - [BNXT_ULP_CLASS_HID_35c49] = 62, - [BNXT_ULP_CLASS_HID_50e5] = 63, - [BNXT_ULP_CLASS_HID_10a29] = 64, - [BNXT_ULP_CLASS_HID_22029] = 65, - [BNXT_ULP_CLASS_HID_33629] = 66, - [BNXT_ULP_CLASS_HID_471d] = 67, - [BNXT_ULP_CLASS_HID_10041] = 68, - [BNXT_ULP_CLASS_HID_21641] = 69, - [BNXT_ULP_CLASS_HID_32c41] = 70, - [BNXT_ULP_CLASS_HID_10e1] = 71, - [BNXT_ULP_CLASS_HID_126e1] = 72, - [BNXT_ULP_CLASS_HID_23ce1] = 73, - [BNXT_ULP_CLASS_HID_352e1] = 74, - [BNXT_ULP_CLASS_HID_140d] = 75, - [BNXT_ULP_CLASS_HID_12a0d] = 76, - [BNXT_ULP_CLASS_HID_2400d] = 77, - [BNXT_ULP_CLASS_HID_3560d] = 78, - [BNXT_ULP_CLASS_HID_4ab9] = 79, - [BNXT_ULP_CLASS_HID_103ed] = 80, - [BNXT_ULP_CLASS_HID_219ed] = 81, - [BNXT_ULP_CLASS_HID_32fed] = 82, - [BNXT_ULP_CLASS_HID_40d1] = 83, - [BNXT_ULP_CLASS_HID_156d1] = 84, - [BNXT_ULP_CLASS_HID_21005] = 85, - [BNXT_ULP_CLASS_HID_32605] = 86, - [BNXT_ULP_CLASS_HID_0aa5] = 87, - [BNXT_ULP_CLASS_HID_120a5] = 88, - [BNXT_ULP_CLASS_HID_236a5] = 89, - [BNXT_ULP_CLASS_HID_34ca5] = 90, - [BNXT_ULP_CLASS_HID_0159] = 91, - [BNXT_ULP_CLASS_HID_11759] = 92, - [BNXT_ULP_CLASS_HID_22d59] = 93, - [BNXT_ULP_CLASS_HID_34359] = 94, - [BNXT_ULP_CLASS_HID_37f5] = 95, - [BNXT_ULP_CLASS_HID_14df5] = 96, - [BNXT_ULP_CLASS_HID_20739] = 97, - [BNXT_ULP_CLASS_HID_31d39] = 98, - [BNXT_ULP_CLASS_HID_2e6d] = 99, - [BNXT_ULP_CLASS_HID_1446d] = 100, - [BNXT_ULP_CLASS_HID_25a6d] = 101, - [BNXT_ULP_CLASS_HID_31351] = 102, - [BNXT_ULP_CLASS_HID_548d] = 103, - [BNXT_ULP_CLASS_HID_10df1] = 104, - [BNXT_ULP_CLASS_HID_223f1] = 105, - [BNXT_ULP_CLASS_HID_339f1] = 106, - [BNXT_ULP_CLASS_HID_5829] = 107, - [BNXT_ULP_CLASS_HID_1111d] = 108, - [BNXT_ULP_CLASS_HID_2271d] = 109, - [BNXT_ULP_CLASS_HID_33d1d] = 110, - [BNXT_ULP_CLASS_HID_3189] = 111, - [BNXT_ULP_CLASS_HID_14789] = 112, - [BNXT_ULP_CLASS_HID_200fd] = 113, - [BNXT_ULP_CLASS_HID_316fd] = 114, - [BNXT_ULP_CLASS_HID_2821] = 115, - [BNXT_ULP_CLASS_HID_13e21] = 116, - [BNXT_ULP_CLASS_HID_25421] = 117, - [BNXT_ULP_CLASS_HID_30d15] = 118, - [BNXT_ULP_CLASS_HID_4e41] = 119, - [BNXT_ULP_CLASS_HID_107b5] = 120, - [BNXT_ULP_CLASS_HID_21db5] = 121, - [BNXT_ULP_CLASS_HID_333b5] = 122, - [BNXT_ULP_CLASS_HID_2541] = 123, - [BNXT_ULP_CLASS_HID_2b8d] = 124, - [BNXT_ULP_CLASS_HID_2691] = 125, - [BNXT_ULP_CLASS_HID_13c91] = 126, - [BNXT_ULP_CLASS_HID_25291] = 127, - [BNXT_ULP_CLASS_HID_30c45] = 128, - [BNXT_ULP_CLASS_HID_0031] = 129, - [BNXT_ULP_CLASS_HID_11631] = 130, - [BNXT_ULP_CLASS_HID_22c31] = 131, - [BNXT_ULP_CLASS_HID_34231] = 132, - [BNXT_ULP_CLASS_HID_53e5] = 133, - [BNXT_ULP_CLASS_HID_10ca9] = 134, - [BNXT_ULP_CLASS_HID_222a9] = 135, - [BNXT_ULP_CLASS_HID_338a9] = 136, - [BNXT_ULP_CLASS_HID_1d09] = 137, - [BNXT_ULP_CLASS_HID_13309] = 138, - [BNXT_ULP_CLASS_HID_24909] = 139, - [BNXT_ULP_CLASS_HID_3023d] = 140, - [BNXT_ULP_CLASS_HID_20d5] = 141, - [BNXT_ULP_CLASS_HID_136d5] = 142, - [BNXT_ULP_CLASS_HID_24cd5] = 143, - [BNXT_ULP_CLASS_HID_30599] = 144, - [BNXT_ULP_CLASS_HID_5741] = 145, - [BNXT_ULP_CLASS_HID_11075] = 146, - [BNXT_ULP_CLASS_HID_22675] = 147, - [BNXT_ULP_CLASS_HID_33c75] = 148, - [BNXT_ULP_CLASS_HID_4d39] = 149, - [BNXT_ULP_CLASS_HID_106ed] = 150, - [BNXT_ULP_CLASS_HID_21ced] = 151, - [BNXT_ULP_CLASS_HID_332ed] = 152, - [BNXT_ULP_CLASS_HID_174d] = 153, - [BNXT_ULP_CLASS_HID_12d4d] = 154, - [BNXT_ULP_CLASS_HID_2434d] = 155, - [BNXT_ULP_CLASS_HID_3594d] = 156, - [BNXT_ULP_CLASS_HID_1a29] = 157, - [BNXT_ULP_CLASS_HID_13029] = 158, - [BNXT_ULP_CLASS_HID_24629] = 159, - [BNXT_ULP_CLASS_HID_35c29] = 160, - [BNXT_ULP_CLASS_HID_5085] = 161, - [BNXT_ULP_CLASS_HID_10a49] = 162, - [BNXT_ULP_CLASS_HID_22049] = 163, - [BNXT_ULP_CLASS_HID_33649] = 164, - [BNXT_ULP_CLASS_HID_477d] = 165, - [BNXT_ULP_CLASS_HID_10021] = 166, - [BNXT_ULP_CLASS_HID_21621] = 167, - [BNXT_ULP_CLASS_HID_32c21] = 168, - [BNXT_ULP_CLASS_HID_1081] = 169, - [BNXT_ULP_CLASS_HID_12681] = 170, - [BNXT_ULP_CLASS_HID_23c81] = 171, - [BNXT_ULP_CLASS_HID_35281] = 172, - [BNXT_ULP_CLASS_HID_146d] = 173, - [BNXT_ULP_CLASS_HID_12a6d] = 174, - [BNXT_ULP_CLASS_HID_2406d] = 175, - [BNXT_ULP_CLASS_HID_3566d] = 176, - [BNXT_ULP_CLASS_HID_4ad9] = 177, - [BNXT_ULP_CLASS_HID_1038d] = 178, - [BNXT_ULP_CLASS_HID_2198d] = 179, - [BNXT_ULP_CLASS_HID_32f8d] = 180, - [BNXT_ULP_CLASS_HID_40b1] = 181, - [BNXT_ULP_CLASS_HID_156b1] = 182, - [BNXT_ULP_CLASS_HID_21065] = 183, - [BNXT_ULP_CLASS_HID_32665] = 184, - [BNXT_ULP_CLASS_HID_0ac5] = 185, - [BNXT_ULP_CLASS_HID_120c5] = 186, - [BNXT_ULP_CLASS_HID_236c5] = 187, - [BNXT_ULP_CLASS_HID_34cc5] = 188, - [BNXT_ULP_CLASS_HID_0139] = 189, - [BNXT_ULP_CLASS_HID_11739] = 190, - [BNXT_ULP_CLASS_HID_22d39] = 191, - [BNXT_ULP_CLASS_HID_34339] = 192, - [BNXT_ULP_CLASS_HID_3795] = 193, - [BNXT_ULP_CLASS_HID_14d95] = 194, - [BNXT_ULP_CLASS_HID_20759] = 195, - [BNXT_ULP_CLASS_HID_31d59] = 196, - [BNXT_ULP_CLASS_HID_2e0d] = 197, - [BNXT_ULP_CLASS_HID_1440d] = 198, - [BNXT_ULP_CLASS_HID_25a0d] = 199, - [BNXT_ULP_CLASS_HID_31331] = 200, - [BNXT_ULP_CLASS_HID_54ed] = 201, - [BNXT_ULP_CLASS_HID_10d91] = 202, - [BNXT_ULP_CLASS_HID_22391] = 203, - [BNXT_ULP_CLASS_HID_33991] = 204, - [BNXT_ULP_CLASS_HID_5849] = 205, - [BNXT_ULP_CLASS_HID_1117d] = 206, - [BNXT_ULP_CLASS_HID_2277d] = 207, - [BNXT_ULP_CLASS_HID_33d7d] = 208, - [BNXT_ULP_CLASS_HID_31e9] = 209, - [BNXT_ULP_CLASS_HID_147e9] = 210, - [BNXT_ULP_CLASS_HID_2009d] = 211, - [BNXT_ULP_CLASS_HID_3169d] = 212, - [BNXT_ULP_CLASS_HID_2841] = 213, - [BNXT_ULP_CLASS_HID_13e41] = 214, - [BNXT_ULP_CLASS_HID_25441] = 215, - [BNXT_ULP_CLASS_HID_30d75] = 216, - [BNXT_ULP_CLASS_HID_4e21] = 217, - [BNXT_ULP_CLASS_HID_107d5] = 218, - [BNXT_ULP_CLASS_HID_21dd5] = 219, - [BNXT_ULP_CLASS_HID_333d5] = 220, - [BNXT_ULP_CLASS_HID_2521] = 221, - [BNXT_ULP_CLASS_HID_2bed] = 222, - [BNXT_ULP_CLASS_HID_1865] = 223, - [BNXT_ULP_CLASS_HID_389d] = 224, - [BNXT_ULP_CLASS_HID_123d] = 225, - [BNXT_ULP_CLASS_HID_4ef1] = 226, - [BNXT_ULP_CLASS_HID_1229] = 227, - [BNXT_ULP_CLASS_HID_3241] = 228, - [BNXT_ULP_CLASS_HID_0be1] = 229, - [BNXT_ULP_CLASS_HID_48b5] = 230, - [BNXT_ULP_CLASS_HID_0bed] = 231, - [BNXT_ULP_CLASS_HID_2c05] = 232, - [BNXT_ULP_CLASS_HID_05a5] = 233, - [BNXT_ULP_CLASS_HID_4279] = 234, - [BNXT_ULP_CLASS_HID_05d1] = 235, - [BNXT_ULP_CLASS_HID_25c9] = 236, - [BNXT_ULP_CLASS_HID_5c55] = 237, - [BNXT_ULP_CLASS_HID_3c3d] = 238, - [BNXT_ULP_CLASS_HID_4fc9] = 239, - [BNXT_ULP_CLASS_HID_1335] = 240, - [BNXT_ULP_CLASS_HID_4981] = 241, - [BNXT_ULP_CLASS_HID_2969] = 242, - [BNXT_ULP_CLASS_HID_498d] = 243, - [BNXT_ULP_CLASS_HID_0cf9] = 244, - [BNXT_ULP_CLASS_HID_4345] = 245, - [BNXT_ULP_CLASS_HID_232d] = 246, - [BNXT_ULP_CLASS_HID_2579] = 247, - [BNXT_ULP_CLASS_HID_2bb5] = 248, - [BNXT_ULP_CLASS_HID_1845] = 249, - [BNXT_ULP_CLASS_HID_1399] = 250, - [BNXT_ULP_CLASS_HID_0eed] = 251, - [BNXT_ULP_CLASS_HID_0a21] = 252, - [BNXT_ULP_CLASS_HID_38bd] = 253, - [BNXT_ULP_CLASS_HID_33f1] = 254, - [BNXT_ULP_CLASS_HID_2ec5] = 255, - [BNXT_ULP_CLASS_HID_2a19] = 256, - [BNXT_ULP_CLASS_HID_121d] = 257, - [BNXT_ULP_CLASS_HID_0d51] = 258, - [BNXT_ULP_CLASS_HID_08a5] = 259, - [BNXT_ULP_CLASS_HID_03f9] = 260, - [BNXT_ULP_CLASS_HID_4ed1] = 261, - [BNXT_ULP_CLASS_HID_4a25] = 262, - [BNXT_ULP_CLASS_HID_4579] = 263, - [BNXT_ULP_CLASS_HID_404d] = 264, - [BNXT_ULP_CLASS_HID_1209] = 265, - [BNXT_ULP_CLASS_HID_0d5d] = 266, - [BNXT_ULP_CLASS_HID_0891] = 267, - [BNXT_ULP_CLASS_HID_03e5] = 268, - [BNXT_ULP_CLASS_HID_3261] = 269, - [BNXT_ULP_CLASS_HID_2db5] = 270, - [BNXT_ULP_CLASS_HID_2889] = 271, - [BNXT_ULP_CLASS_HID_23dd] = 272, - [BNXT_ULP_CLASS_HID_0bc1] = 273, - [BNXT_ULP_CLASS_HID_0715] = 274, - [BNXT_ULP_CLASS_HID_0269] = 275, - [BNXT_ULP_CLASS_HID_5a69] = 276, - [BNXT_ULP_CLASS_HID_4895] = 277, - [BNXT_ULP_CLASS_HID_43e9] = 278, - [BNXT_ULP_CLASS_HID_3f3d] = 279, - [BNXT_ULP_CLASS_HID_3a71] = 280, - [BNXT_ULP_CLASS_HID_0bcd] = 281, - [BNXT_ULP_CLASS_HID_0701] = 282, - [BNXT_ULP_CLASS_HID_0255] = 283, - [BNXT_ULP_CLASS_HID_5a55] = 284, - [BNXT_ULP_CLASS_HID_2c25] = 285, - [BNXT_ULP_CLASS_HID_2779] = 286, - [BNXT_ULP_CLASS_HID_224d] = 287, - [BNXT_ULP_CLASS_HID_1d81] = 288, - [BNXT_ULP_CLASS_HID_0585] = 289, - [BNXT_ULP_CLASS_HID_00d9] = 290, - [BNXT_ULP_CLASS_HID_58d9] = 291, - [BNXT_ULP_CLASS_HID_542d] = 292, - [BNXT_ULP_CLASS_HID_4259] = 293, - [BNXT_ULP_CLASS_HID_3dad] = 294, - [BNXT_ULP_CLASS_HID_38e1] = 295, - [BNXT_ULP_CLASS_HID_3435] = 296, - [BNXT_ULP_CLASS_HID_05f1] = 297, - [BNXT_ULP_CLASS_HID_00c5] = 298, - [BNXT_ULP_CLASS_HID_58c5] = 299, - [BNXT_ULP_CLASS_HID_5419] = 300, - [BNXT_ULP_CLASS_HID_25e9] = 301, - [BNXT_ULP_CLASS_HID_213d] = 302, - [BNXT_ULP_CLASS_HID_1c71] = 303, - [BNXT_ULP_CLASS_HID_1745] = 304, - [BNXT_ULP_CLASS_HID_5c75] = 305, - [BNXT_ULP_CLASS_HID_5749] = 306, - [BNXT_ULP_CLASS_HID_529d] = 307, - [BNXT_ULP_CLASS_HID_4dd1] = 308, - [BNXT_ULP_CLASS_HID_3c1d] = 309, - [BNXT_ULP_CLASS_HID_3751] = 310, - [BNXT_ULP_CLASS_HID_32a5] = 311, - [BNXT_ULP_CLASS_HID_2df9] = 312, - [BNXT_ULP_CLASS_HID_4fe9] = 313, - [BNXT_ULP_CLASS_HID_4b3d] = 314, - [BNXT_ULP_CLASS_HID_4671] = 315, - [BNXT_ULP_CLASS_HID_4145] = 316, - [BNXT_ULP_CLASS_HID_1315] = 317, - [BNXT_ULP_CLASS_HID_0e69] = 318, - [BNXT_ULP_CLASS_HID_09bd] = 319, - [BNXT_ULP_CLASS_HID_04f1] = 320, - [BNXT_ULP_CLASS_HID_49a1] = 321, - [BNXT_ULP_CLASS_HID_44f5] = 322, - [BNXT_ULP_CLASS_HID_3fc9] = 323, - [BNXT_ULP_CLASS_HID_3b1d] = 324, - [BNXT_ULP_CLASS_HID_2949] = 325, - [BNXT_ULP_CLASS_HID_249d] = 326, - [BNXT_ULP_CLASS_HID_1fd1] = 327, - [BNXT_ULP_CLASS_HID_1b25] = 328, - [BNXT_ULP_CLASS_HID_49ad] = 329, - [BNXT_ULP_CLASS_HID_44e1] = 330, - [BNXT_ULP_CLASS_HID_4035] = 331, - [BNXT_ULP_CLASS_HID_3b09] = 332, - [BNXT_ULP_CLASS_HID_0cd9] = 333, - [BNXT_ULP_CLASS_HID_082d] = 334, - [BNXT_ULP_CLASS_HID_0361] = 335, - [BNXT_ULP_CLASS_HID_5b61] = 336, - [BNXT_ULP_CLASS_HID_4365] = 337, - [BNXT_ULP_CLASS_HID_3eb9] = 338, - [BNXT_ULP_CLASS_HID_398d] = 339, - [BNXT_ULP_CLASS_HID_34c1] = 340, - [BNXT_ULP_CLASS_HID_230d] = 341, - [BNXT_ULP_CLASS_HID_1e41] = 342, - [BNXT_ULP_CLASS_HID_1995] = 343, - [BNXT_ULP_CLASS_HID_14e9] = 344, - [BNXT_ULP_CLASS_HID_2559] = 345, - [BNXT_ULP_CLASS_HID_2b95] = 346, - [BNXT_ULP_CLASS_HID_1825] = 347, - [BNXT_ULP_CLASS_HID_13f9] = 348, - [BNXT_ULP_CLASS_HID_0e8d] = 349, - [BNXT_ULP_CLASS_HID_0a41] = 350, - [BNXT_ULP_CLASS_HID_38dd] = 351, - [BNXT_ULP_CLASS_HID_3391] = 352, - [BNXT_ULP_CLASS_HID_2ea5] = 353, - [BNXT_ULP_CLASS_HID_2a79] = 354, - [BNXT_ULP_CLASS_HID_127d] = 355, - [BNXT_ULP_CLASS_HID_0d31] = 356, - [BNXT_ULP_CLASS_HID_08c5] = 357, - [BNXT_ULP_CLASS_HID_0399] = 358, - [BNXT_ULP_CLASS_HID_4eb1] = 359, - [BNXT_ULP_CLASS_HID_4a45] = 360, - [BNXT_ULP_CLASS_HID_4519] = 361, - [BNXT_ULP_CLASS_HID_402d] = 362, - [BNXT_ULP_CLASS_HID_1269] = 363, - [BNXT_ULP_CLASS_HID_0d3d] = 364, - [BNXT_ULP_CLASS_HID_08f1] = 365, - [BNXT_ULP_CLASS_HID_0385] = 366, - [BNXT_ULP_CLASS_HID_3201] = 367, - [BNXT_ULP_CLASS_HID_2dd5] = 368, - [BNXT_ULP_CLASS_HID_28e9] = 369, - [BNXT_ULP_CLASS_HID_23bd] = 370, - [BNXT_ULP_CLASS_HID_0ba1] = 371, - [BNXT_ULP_CLASS_HID_0775] = 372, - [BNXT_ULP_CLASS_HID_0209] = 373, - [BNXT_ULP_CLASS_HID_5a09] = 374, - [BNXT_ULP_CLASS_HID_48f5] = 375, - [BNXT_ULP_CLASS_HID_4389] = 376, - [BNXT_ULP_CLASS_HID_3f5d] = 377, - [BNXT_ULP_CLASS_HID_3a11] = 378, - [BNXT_ULP_CLASS_HID_0bad] = 379, - [BNXT_ULP_CLASS_HID_0761] = 380, - [BNXT_ULP_CLASS_HID_0235] = 381, - [BNXT_ULP_CLASS_HID_5a35] = 382, - [BNXT_ULP_CLASS_HID_2c45] = 383, - [BNXT_ULP_CLASS_HID_2719] = 384, - [BNXT_ULP_CLASS_HID_222d] = 385, - [BNXT_ULP_CLASS_HID_1de1] = 386, - [BNXT_ULP_CLASS_HID_05e5] = 387, - [BNXT_ULP_CLASS_HID_00b9] = 388, - [BNXT_ULP_CLASS_HID_58b9] = 389, - [BNXT_ULP_CLASS_HID_544d] = 390, - [BNXT_ULP_CLASS_HID_4239] = 391, - [BNXT_ULP_CLASS_HID_3dcd] = 392, - [BNXT_ULP_CLASS_HID_3881] = 393, - [BNXT_ULP_CLASS_HID_3455] = 394, - [BNXT_ULP_CLASS_HID_0591] = 395, - [BNXT_ULP_CLASS_HID_00a5] = 396, - [BNXT_ULP_CLASS_HID_58a5] = 397, - [BNXT_ULP_CLASS_HID_5479] = 398, - [BNXT_ULP_CLASS_HID_2589] = 399, - [BNXT_ULP_CLASS_HID_215d] = 400, - [BNXT_ULP_CLASS_HID_1c11] = 401, - [BNXT_ULP_CLASS_HID_1725] = 402, - [BNXT_ULP_CLASS_HID_5c15] = 403, - [BNXT_ULP_CLASS_HID_5729] = 404, - [BNXT_ULP_CLASS_HID_52fd] = 405, - [BNXT_ULP_CLASS_HID_4db1] = 406, - [BNXT_ULP_CLASS_HID_3c7d] = 407, - [BNXT_ULP_CLASS_HID_3731] = 408, - [BNXT_ULP_CLASS_HID_32c5] = 409, - [BNXT_ULP_CLASS_HID_2d99] = 410, - [BNXT_ULP_CLASS_HID_4f89] = 411, - [BNXT_ULP_CLASS_HID_4b5d] = 412, - [BNXT_ULP_CLASS_HID_4611] = 413, - [BNXT_ULP_CLASS_HID_4125] = 414, - [BNXT_ULP_CLASS_HID_1375] = 415, - [BNXT_ULP_CLASS_HID_0e09] = 416, - [BNXT_ULP_CLASS_HID_09dd] = 417, - [BNXT_ULP_CLASS_HID_0491] = 418, - [BNXT_ULP_CLASS_HID_49c1] = 419, - [BNXT_ULP_CLASS_HID_4495] = 420, - [BNXT_ULP_CLASS_HID_3fa9] = 421, - [BNXT_ULP_CLASS_HID_3b7d] = 422, - [BNXT_ULP_CLASS_HID_2929] = 423, - [BNXT_ULP_CLASS_HID_24fd] = 424, - [BNXT_ULP_CLASS_HID_1fb1] = 425, - [BNXT_ULP_CLASS_HID_1b45] = 426, - [BNXT_ULP_CLASS_HID_49cd] = 427, - [BNXT_ULP_CLASS_HID_4481] = 428, - [BNXT_ULP_CLASS_HID_4055] = 429, - [BNXT_ULP_CLASS_HID_3b69] = 430, - [BNXT_ULP_CLASS_HID_0cb9] = 431, - [BNXT_ULP_CLASS_HID_084d] = 432, - [BNXT_ULP_CLASS_HID_0301] = 433, - [BNXT_ULP_CLASS_HID_5b01] = 434, - [BNXT_ULP_CLASS_HID_4305] = 435, - [BNXT_ULP_CLASS_HID_3ed9] = 436, - [BNXT_ULP_CLASS_HID_39ed] = 437, - [BNXT_ULP_CLASS_HID_34a1] = 438, - [BNXT_ULP_CLASS_HID_236d] = 439, - [BNXT_ULP_CLASS_HID_1e21] = 440, - [BNXT_ULP_CLASS_HID_19f5] = 441, - [BNXT_ULP_CLASS_HID_1489] = 442, - [BNXT_ULP_CLASS_HID_2539] = 443, - [BNXT_ULP_CLASS_HID_2bf5] = 444, - [BNXT_ULP_CLASS_HID_b6af] = 445, - [BNXT_ULP_CLASS_HID_b1d3] = 446, - [BNXT_ULP_CLASS_HID_1c7d3] = 447, - [BNXT_ULP_CLASS_HID_1ccaf] = 448, - [BNXT_ULP_CLASS_HID_da33] = 449, - [BNXT_ULP_CLASS_HID_d567] = 450, - [BNXT_ULP_CLASS_HID_18eab] = 451, - [BNXT_ULP_CLASS_HID_19367] = 452, - [BNXT_ULP_CLASS_HID_a10b] = 453, - [BNXT_ULP_CLASS_HID_9c3f] = 454, - [BNXT_ULP_CLASS_HID_1b23f] = 455, - [BNXT_ULP_CLASS_HID_1b70b] = 456, - [BNXT_ULP_CLASS_HID_c49f] = 457, - [BNXT_ULP_CLASS_HID_bfc3] = 458, - [BNXT_ULP_CLASS_HID_1d5c3] = 459, - [BNXT_ULP_CLASS_HID_1da9f] = 460, - [BNXT_ULP_CLASS_HID_b063] = 461, - [BNXT_ULP_CLASS_HID_ab97] = 462, - [BNXT_ULP_CLASS_HID_1c197] = 463, - [BNXT_ULP_CLASS_HID_1c663] = 464, - [BNXT_ULP_CLASS_HID_d3f7] = 465, - [BNXT_ULP_CLASS_HID_cf3b] = 466, - [BNXT_ULP_CLASS_HID_1886f] = 467, - [BNXT_ULP_CLASS_HID_18d3b] = 468, - [BNXT_ULP_CLASS_HID_9acf] = 469, - [BNXT_ULP_CLASS_HID_95f3] = 470, - [BNXT_ULP_CLASS_HID_1abf3] = 471, - [BNXT_ULP_CLASS_HID_1b0cf] = 472, - [BNXT_ULP_CLASS_HID_be53] = 473, - [BNXT_ULP_CLASS_HID_b987] = 474, - [BNXT_ULP_CLASS_HID_1cf87] = 475, - [BNXT_ULP_CLASS_HID_1d453] = 476, - [BNXT_ULP_CLASS_HID_aa27] = 477, - [BNXT_ULP_CLASS_HID_a56b] = 478, - [BNXT_ULP_CLASS_HID_1bb6b] = 479, - [BNXT_ULP_CLASS_HID_1c027] = 480, - [BNXT_ULP_CLASS_HID_cdcb] = 481, - [BNXT_ULP_CLASS_HID_c8ff] = 482, - [BNXT_ULP_CLASS_HID_18223] = 483, - [BNXT_ULP_CLASS_HID_186ff] = 484, - [BNXT_ULP_CLASS_HID_9483] = 485, - [BNXT_ULP_CLASS_HID_8fb7] = 486, - [BNXT_ULP_CLASS_HID_1a5b7] = 487, - [BNXT_ULP_CLASS_HID_1aa83] = 488, - [BNXT_ULP_CLASS_HID_b817] = 489, - [BNXT_ULP_CLASS_HID_b35b] = 490, - [BNXT_ULP_CLASS_HID_1c95b] = 491, - [BNXT_ULP_CLASS_HID_1ce17] = 492, - [BNXT_ULP_CLASS_HID_a3fb] = 493, - [BNXT_ULP_CLASS_HID_9f2f] = 494, - [BNXT_ULP_CLASS_HID_1b52f] = 495, - [BNXT_ULP_CLASS_HID_1b9fb] = 496, - [BNXT_ULP_CLASS_HID_c78f] = 497, - [BNXT_ULP_CLASS_HID_c2b3] = 498, - [BNXT_ULP_CLASS_HID_1d8b3] = 499, - [BNXT_ULP_CLASS_HID_180b3] = 500, - [BNXT_ULP_CLASS_HID_8e47] = 501, - [BNXT_ULP_CLASS_HID_898b] = 502, - [BNXT_ULP_CLASS_HID_19f8b] = 503, - [BNXT_ULP_CLASS_HID_1a447] = 504, - [BNXT_ULP_CLASS_HID_b1eb] = 505, - [BNXT_ULP_CLASS_HID_ad1f] = 506, - [BNXT_ULP_CLASS_HID_1c31f] = 507, - [BNXT_ULP_CLASS_HID_1c7eb] = 508, - [BNXT_ULP_CLASS_HID_9137] = 509, - [BNXT_ULP_CLASS_HID_8c7b] = 510, - [BNXT_ULP_CLASS_HID_1a27b] = 511, - [BNXT_ULP_CLASS_HID_1a737] = 512, - [BNXT_ULP_CLASS_HID_b4db] = 513, - [BNXT_ULP_CLASS_HID_b00f] = 514, - [BNXT_ULP_CLASS_HID_1c60f] = 515, - [BNXT_ULP_CLASS_HID_1cadb] = 516, - [BNXT_ULP_CLASS_HID_8b0b] = 517, - [BNXT_ULP_CLASS_HID_863f] = 518, - [BNXT_ULP_CLASS_HID_19c3f] = 519, - [BNXT_ULP_CLASS_HID_1a10b] = 520, - [BNXT_ULP_CLASS_HID_ae9f] = 521, - [BNXT_ULP_CLASS_HID_a9c3] = 522, - [BNXT_ULP_CLASS_HID_1bfc3] = 523, - [BNXT_ULP_CLASS_HID_1c49f] = 524, - [BNXT_ULP_CLASS_HID_2563] = 525, - [BNXT_ULP_CLASS_HID_2baf] = 526, - [BNXT_ULP_CLASS_HID_4f33] = 527, - [BNXT_ULP_CLASS_HID_160b] = 528, - [BNXT_ULP_CLASS_HID_399f] = 529, - [BNXT_ULP_CLASS_HID_48f7] = 530, - [BNXT_ULP_CLASS_HID_0fcf] = 531, - [BNXT_ULP_CLASS_HID_3353] = 532, - [BNXT_ULP_CLASS_HID_b68f] = 533, - [BNXT_ULP_CLASS_HID_b94f] = 534, - [BNXT_ULP_CLASS_HID_fc0f] = 535, - [BNXT_ULP_CLASS_HID_fecf] = 536, - [BNXT_ULP_CLASS_HID_b1f3] = 537, - [BNXT_ULP_CLASS_HID_b4b3] = 538, - [BNXT_ULP_CLASS_HID_f773] = 539, - [BNXT_ULP_CLASS_HID_fa33] = 540, - [BNXT_ULP_CLASS_HID_1c7f3] = 541, - [BNXT_ULP_CLASS_HID_1eab3] = 542, - [BNXT_ULP_CLASS_HID_1cd73] = 543, - [BNXT_ULP_CLASS_HID_1f033] = 544, - [BNXT_ULP_CLASS_HID_1cc8f] = 545, - [BNXT_ULP_CLASS_HID_1ef4f] = 546, - [BNXT_ULP_CLASS_HID_1d20f] = 547, - [BNXT_ULP_CLASS_HID_1f4cf] = 548, - [BNXT_ULP_CLASS_HID_da13] = 549, - [BNXT_ULP_CLASS_HID_a007] = 550, - [BNXT_ULP_CLASS_HID_c2c7] = 551, - [BNXT_ULP_CLASS_HID_e587] = 552, - [BNXT_ULP_CLASS_HID_d547] = 553, - [BNXT_ULP_CLASS_HID_f807] = 554, - [BNXT_ULP_CLASS_HID_dac7] = 555, - [BNXT_ULP_CLASS_HID_e0cb] = 556, - [BNXT_ULP_CLASS_HID_18e8b] = 557, - [BNXT_ULP_CLASS_HID_1b14b] = 558, - [BNXT_ULP_CLASS_HID_1d40b] = 559, - [BNXT_ULP_CLASS_HID_1f6cb] = 560, - [BNXT_ULP_CLASS_HID_19347] = 561, - [BNXT_ULP_CLASS_HID_1b607] = 562, - [BNXT_ULP_CLASS_HID_1d8c7] = 563, - [BNXT_ULP_CLASS_HID_1fb87] = 564, - [BNXT_ULP_CLASS_HID_a12b] = 565, - [BNXT_ULP_CLASS_HID_a3eb] = 566, - [BNXT_ULP_CLASS_HID_e6ab] = 567, - [BNXT_ULP_CLASS_HID_e96b] = 568, - [BNXT_ULP_CLASS_HID_9c1f] = 569, - [BNXT_ULP_CLASS_HID_bedf] = 570, - [BNXT_ULP_CLASS_HID_e19f] = 571, - [BNXT_ULP_CLASS_HID_e45f] = 572, - [BNXT_ULP_CLASS_HID_1b21f] = 573, - [BNXT_ULP_CLASS_HID_1b4df] = 574, - [BNXT_ULP_CLASS_HID_1f79f] = 575, - [BNXT_ULP_CLASS_HID_1fa5f] = 576, - [BNXT_ULP_CLASS_HID_1b72b] = 577, - [BNXT_ULP_CLASS_HID_1b9eb] = 578, - [BNXT_ULP_CLASS_HID_1fcab] = 579, - [BNXT_ULP_CLASS_HID_1ff6b] = 580, - [BNXT_ULP_CLASS_HID_c4bf] = 581, - [BNXT_ULP_CLASS_HID_e77f] = 582, - [BNXT_ULP_CLASS_HID_ca3f] = 583, - [BNXT_ULP_CLASS_HID_ecff] = 584, - [BNXT_ULP_CLASS_HID_bfe3] = 585, - [BNXT_ULP_CLASS_HID_e2a3] = 586, - [BNXT_ULP_CLASS_HID_c563] = 587, - [BNXT_ULP_CLASS_HID_e823] = 588, - [BNXT_ULP_CLASS_HID_1d5e3] = 589, - [BNXT_ULP_CLASS_HID_1f8a3] = 590, - [BNXT_ULP_CLASS_HID_1db63] = 591, - [BNXT_ULP_CLASS_HID_1e117] = 592, - [BNXT_ULP_CLASS_HID_1dabf] = 593, - [BNXT_ULP_CLASS_HID_1a0a3] = 594, - [BNXT_ULP_CLASS_HID_1c363] = 595, - [BNXT_ULP_CLASS_HID_1e623] = 596, - [BNXT_ULP_CLASS_HID_b043] = 597, - [BNXT_ULP_CLASS_HID_b303] = 598, - [BNXT_ULP_CLASS_HID_f5c3] = 599, - [BNXT_ULP_CLASS_HID_f883] = 600, - [BNXT_ULP_CLASS_HID_abb7] = 601, - [BNXT_ULP_CLASS_HID_ae77] = 602, - [BNXT_ULP_CLASS_HID_f137] = 603, - [BNXT_ULP_CLASS_HID_f3f7] = 604, - [BNXT_ULP_CLASS_HID_1c1b7] = 605, - [BNXT_ULP_CLASS_HID_1e477] = 606, - [BNXT_ULP_CLASS_HID_1c737] = 607, - [BNXT_ULP_CLASS_HID_1e9f7] = 608, - [BNXT_ULP_CLASS_HID_1c643] = 609, - [BNXT_ULP_CLASS_HID_1e903] = 610, - [BNXT_ULP_CLASS_HID_1cbc3] = 611, - [BNXT_ULP_CLASS_HID_1ee83] = 612, - [BNXT_ULP_CLASS_HID_d3d7] = 613, - [BNXT_ULP_CLASS_HID_f697] = 614, - [BNXT_ULP_CLASS_HID_d957] = 615, - [BNXT_ULP_CLASS_HID_fc17] = 616, - [BNXT_ULP_CLASS_HID_cf1b] = 617, - [BNXT_ULP_CLASS_HID_f1db] = 618, - [BNXT_ULP_CLASS_HID_d49b] = 619, - [BNXT_ULP_CLASS_HID_f75b] = 620, - [BNXT_ULP_CLASS_HID_1884f] = 621, - [BNXT_ULP_CLASS_HID_1ab0f] = 622, - [BNXT_ULP_CLASS_HID_1cdcf] = 623, - [BNXT_ULP_CLASS_HID_1f08f] = 624, - [BNXT_ULP_CLASS_HID_18d1b] = 625, - [BNXT_ULP_CLASS_HID_1afdb] = 626, - [BNXT_ULP_CLASS_HID_1d29b] = 627, - [BNXT_ULP_CLASS_HID_1f55b] = 628, - [BNXT_ULP_CLASS_HID_9aef] = 629, - [BNXT_ULP_CLASS_HID_bdaf] = 630, - [BNXT_ULP_CLASS_HID_e06f] = 631, - [BNXT_ULP_CLASS_HID_e32f] = 632, - [BNXT_ULP_CLASS_HID_95d3] = 633, - [BNXT_ULP_CLASS_HID_b893] = 634, - [BNXT_ULP_CLASS_HID_db53] = 635, - [BNXT_ULP_CLASS_HID_fe13] = 636, - [BNXT_ULP_CLASS_HID_1abd3] = 637, - [BNXT_ULP_CLASS_HID_1ae93] = 638, - [BNXT_ULP_CLASS_HID_1f153] = 639, - [BNXT_ULP_CLASS_HID_1f413] = 640, - [BNXT_ULP_CLASS_HID_1b0ef] = 641, - [BNXT_ULP_CLASS_HID_1b3af] = 642, - [BNXT_ULP_CLASS_HID_1f66f] = 643, - [BNXT_ULP_CLASS_HID_1f92f] = 644, - [BNXT_ULP_CLASS_HID_be73] = 645, - [BNXT_ULP_CLASS_HID_e133] = 646, - [BNXT_ULP_CLASS_HID_c3f3] = 647, - [BNXT_ULP_CLASS_HID_e6b3] = 648, - [BNXT_ULP_CLASS_HID_b9a7] = 649, - [BNXT_ULP_CLASS_HID_bc67] = 650, - [BNXT_ULP_CLASS_HID_ff27] = 651, - [BNXT_ULP_CLASS_HID_e1e7] = 652, - [BNXT_ULP_CLASS_HID_1cfa7] = 653, - [BNXT_ULP_CLASS_HID_1f267] = 654, - [BNXT_ULP_CLASS_HID_1d527] = 655, - [BNXT_ULP_CLASS_HID_1f7e7] = 656, - [BNXT_ULP_CLASS_HID_1d473] = 657, - [BNXT_ULP_CLASS_HID_1f733] = 658, - [BNXT_ULP_CLASS_HID_1d9f3] = 659, - [BNXT_ULP_CLASS_HID_1fcb3] = 660, - [BNXT_ULP_CLASS_HID_aa07] = 661, - [BNXT_ULP_CLASS_HID_acc7] = 662, - [BNXT_ULP_CLASS_HID_ef87] = 663, - [BNXT_ULP_CLASS_HID_f247] = 664, - [BNXT_ULP_CLASS_HID_a54b] = 665, - [BNXT_ULP_CLASS_HID_a80b] = 666, - [BNXT_ULP_CLASS_HID_eacb] = 667, - [BNXT_ULP_CLASS_HID_ed8b] = 668, - [BNXT_ULP_CLASS_HID_1bb4b] = 669, - [BNXT_ULP_CLASS_HID_1be0b] = 670, - [BNXT_ULP_CLASS_HID_1c0cb] = 671, - [BNXT_ULP_CLASS_HID_1e38b] = 672, - [BNXT_ULP_CLASS_HID_1c007] = 673, - [BNXT_ULP_CLASS_HID_1e2c7] = 674, - [BNXT_ULP_CLASS_HID_1c587] = 675, - [BNXT_ULP_CLASS_HID_1e847] = 676, - [BNXT_ULP_CLASS_HID_cdeb] = 677, - [BNXT_ULP_CLASS_HID_f0ab] = 678, - [BNXT_ULP_CLASS_HID_d36b] = 679, - [BNXT_ULP_CLASS_HID_f62b] = 680, - [BNXT_ULP_CLASS_HID_c8df] = 681, - [BNXT_ULP_CLASS_HID_eb9f] = 682, - [BNXT_ULP_CLASS_HID_ce5f] = 683, - [BNXT_ULP_CLASS_HID_f11f] = 684, - [BNXT_ULP_CLASS_HID_18203] = 685, - [BNXT_ULP_CLASS_HID_1a4c3] = 686, - [BNXT_ULP_CLASS_HID_1c783] = 687, - [BNXT_ULP_CLASS_HID_1ea43] = 688, - [BNXT_ULP_CLASS_HID_186df] = 689, - [BNXT_ULP_CLASS_HID_1a99f] = 690, - [BNXT_ULP_CLASS_HID_1cc5f] = 691, - [BNXT_ULP_CLASS_HID_1ef1f] = 692, - [BNXT_ULP_CLASS_HID_94a3] = 693, - [BNXT_ULP_CLASS_HID_b763] = 694, - [BNXT_ULP_CLASS_HID_da23] = 695, - [BNXT_ULP_CLASS_HID_fce3] = 696, - [BNXT_ULP_CLASS_HID_8f97] = 697, - [BNXT_ULP_CLASS_HID_b257] = 698, - [BNXT_ULP_CLASS_HID_d517] = 699, - [BNXT_ULP_CLASS_HID_f7d7] = 700, - [BNXT_ULP_CLASS_HID_1a597] = 701, - [BNXT_ULP_CLASS_HID_1a857] = 702, - [BNXT_ULP_CLASS_HID_1eb17] = 703, - [BNXT_ULP_CLASS_HID_1edd7] = 704, - [BNXT_ULP_CLASS_HID_1aaa3] = 705, - [BNXT_ULP_CLASS_HID_1ad63] = 706, - [BNXT_ULP_CLASS_HID_1f023] = 707, - [BNXT_ULP_CLASS_HID_1f2e3] = 708, - [BNXT_ULP_CLASS_HID_b837] = 709, - [BNXT_ULP_CLASS_HID_baf7] = 710, - [BNXT_ULP_CLASS_HID_fdb7] = 711, - [BNXT_ULP_CLASS_HID_e077] = 712, - [BNXT_ULP_CLASS_HID_b37b] = 713, - [BNXT_ULP_CLASS_HID_b63b] = 714, - [BNXT_ULP_CLASS_HID_f8fb] = 715, - [BNXT_ULP_CLASS_HID_fbbb] = 716, - [BNXT_ULP_CLASS_HID_1c97b] = 717, - [BNXT_ULP_CLASS_HID_1ec3b] = 718, - [BNXT_ULP_CLASS_HID_1cefb] = 719, - [BNXT_ULP_CLASS_HID_1f1bb] = 720, - [BNXT_ULP_CLASS_HID_1ce37] = 721, - [BNXT_ULP_CLASS_HID_1f0f7] = 722, - [BNXT_ULP_CLASS_HID_1d3b7] = 723, - [BNXT_ULP_CLASS_HID_1f677] = 724, - [BNXT_ULP_CLASS_HID_a3db] = 725, - [BNXT_ULP_CLASS_HID_a69b] = 726, - [BNXT_ULP_CLASS_HID_e95b] = 727, - [BNXT_ULP_CLASS_HID_ec1b] = 728, - [BNXT_ULP_CLASS_HID_9f0f] = 729, - [BNXT_ULP_CLASS_HID_a1cf] = 730, - [BNXT_ULP_CLASS_HID_e48f] = 731, - [BNXT_ULP_CLASS_HID_e74f] = 732, - [BNXT_ULP_CLASS_HID_1b50f] = 733, - [BNXT_ULP_CLASS_HID_1b7cf] = 734, - [BNXT_ULP_CLASS_HID_1fa8f] = 735, - [BNXT_ULP_CLASS_HID_1fd4f] = 736, - [BNXT_ULP_CLASS_HID_1b9db] = 737, - [BNXT_ULP_CLASS_HID_1bc9b] = 738, - [BNXT_ULP_CLASS_HID_1ff5b] = 739, - [BNXT_ULP_CLASS_HID_1e21b] = 740, - [BNXT_ULP_CLASS_HID_c7af] = 741, - [BNXT_ULP_CLASS_HID_ea6f] = 742, - [BNXT_ULP_CLASS_HID_cd2f] = 743, - [BNXT_ULP_CLASS_HID_efef] = 744, - [BNXT_ULP_CLASS_HID_c293] = 745, - [BNXT_ULP_CLASS_HID_e553] = 746, - [BNXT_ULP_CLASS_HID_c813] = 747, - [BNXT_ULP_CLASS_HID_ead3] = 748, - [BNXT_ULP_CLASS_HID_1d893] = 749, - [BNXT_ULP_CLASS_HID_1fb53] = 750, - [BNXT_ULP_CLASS_HID_1c147] = 751, - [BNXT_ULP_CLASS_HID_1e407] = 752, - [BNXT_ULP_CLASS_HID_18093] = 753, - [BNXT_ULP_CLASS_HID_1a353] = 754, - [BNXT_ULP_CLASS_HID_1c613] = 755, - [BNXT_ULP_CLASS_HID_1e8d3] = 756, - [BNXT_ULP_CLASS_HID_8e67] = 757, - [BNXT_ULP_CLASS_HID_b127] = 758, - [BNXT_ULP_CLASS_HID_d3e7] = 759, - [BNXT_ULP_CLASS_HID_f6a7] = 760, - [BNXT_ULP_CLASS_HID_89ab] = 761, - [BNXT_ULP_CLASS_HID_ac6b] = 762, - [BNXT_ULP_CLASS_HID_cf2b] = 763, - [BNXT_ULP_CLASS_HID_f1eb] = 764, - [BNXT_ULP_CLASS_HID_19fab] = 765, - [BNXT_ULP_CLASS_HID_1a26b] = 766, - [BNXT_ULP_CLASS_HID_1e52b] = 767, - [BNXT_ULP_CLASS_HID_1e7eb] = 768, - [BNXT_ULP_CLASS_HID_1a467] = 769, - [BNXT_ULP_CLASS_HID_1a727] = 770, - [BNXT_ULP_CLASS_HID_1e9e7] = 771, - [BNXT_ULP_CLASS_HID_1eca7] = 772, - [BNXT_ULP_CLASS_HID_b1cb] = 773, - [BNXT_ULP_CLASS_HID_b48b] = 774, - [BNXT_ULP_CLASS_HID_f74b] = 775, - [BNXT_ULP_CLASS_HID_fa0b] = 776, - [BNXT_ULP_CLASS_HID_ad3f] = 777, - [BNXT_ULP_CLASS_HID_afff] = 778, - [BNXT_ULP_CLASS_HID_f2bf] = 779, - [BNXT_ULP_CLASS_HID_f57f] = 780, - [BNXT_ULP_CLASS_HID_1c33f] = 781, - [BNXT_ULP_CLASS_HID_1e5ff] = 782, - [BNXT_ULP_CLASS_HID_1c8bf] = 783, - [BNXT_ULP_CLASS_HID_1eb7f] = 784, - [BNXT_ULP_CLASS_HID_1c7cb] = 785, - [BNXT_ULP_CLASS_HID_1ea8b] = 786, - [BNXT_ULP_CLASS_HID_1cd4b] = 787, - [BNXT_ULP_CLASS_HID_1f00b] = 788, - [BNXT_ULP_CLASS_HID_9117] = 789, - [BNXT_ULP_CLASS_HID_b3d7] = 790, - [BNXT_ULP_CLASS_HID_d697] = 791, - [BNXT_ULP_CLASS_HID_f957] = 792, - [BNXT_ULP_CLASS_HID_8c5b] = 793, - [BNXT_ULP_CLASS_HID_af1b] = 794, - [BNXT_ULP_CLASS_HID_d1db] = 795, - [BNXT_ULP_CLASS_HID_f49b] = 796, - [BNXT_ULP_CLASS_HID_1a25b] = 797, - [BNXT_ULP_CLASS_HID_1a51b] = 798, - [BNXT_ULP_CLASS_HID_1e7db] = 799, - [BNXT_ULP_CLASS_HID_1ea9b] = 800, - [BNXT_ULP_CLASS_HID_1a717] = 801, - [BNXT_ULP_CLASS_HID_1a9d7] = 802, - [BNXT_ULP_CLASS_HID_1ec97] = 803, - [BNXT_ULP_CLASS_HID_1ef57] = 804, - [BNXT_ULP_CLASS_HID_b4fb] = 805, - [BNXT_ULP_CLASS_HID_b7bb] = 806, - [BNXT_ULP_CLASS_HID_fa7b] = 807, - [BNXT_ULP_CLASS_HID_fd3b] = 808, - [BNXT_ULP_CLASS_HID_b02f] = 809, - [BNXT_ULP_CLASS_HID_b2ef] = 810, - [BNXT_ULP_CLASS_HID_f5af] = 811, - [BNXT_ULP_CLASS_HID_f86f] = 812, - [BNXT_ULP_CLASS_HID_1c62f] = 813, - [BNXT_ULP_CLASS_HID_1e8ef] = 814, - [BNXT_ULP_CLASS_HID_1cbaf] = 815, - [BNXT_ULP_CLASS_HID_1ee6f] = 816, - [BNXT_ULP_CLASS_HID_1cafb] = 817, - [BNXT_ULP_CLASS_HID_1edbb] = 818, - [BNXT_ULP_CLASS_HID_1d07b] = 819, - [BNXT_ULP_CLASS_HID_1f33b] = 820, - [BNXT_ULP_CLASS_HID_8b2b] = 821, - [BNXT_ULP_CLASS_HID_adeb] = 822, - [BNXT_ULP_CLASS_HID_d0ab] = 823, - [BNXT_ULP_CLASS_HID_f36b] = 824, - [BNXT_ULP_CLASS_HID_861f] = 825, - [BNXT_ULP_CLASS_HID_a8df] = 826, - [BNXT_ULP_CLASS_HID_cb9f] = 827, - [BNXT_ULP_CLASS_HID_ee5f] = 828, - [BNXT_ULP_CLASS_HID_19c1f] = 829, - [BNXT_ULP_CLASS_HID_1bedf] = 830, - [BNXT_ULP_CLASS_HID_1e19f] = 831, - [BNXT_ULP_CLASS_HID_1e45f] = 832, - [BNXT_ULP_CLASS_HID_1a12b] = 833, - [BNXT_ULP_CLASS_HID_1a3eb] = 834, - [BNXT_ULP_CLASS_HID_1e6ab] = 835, - [BNXT_ULP_CLASS_HID_1e96b] = 836, - [BNXT_ULP_CLASS_HID_aebf] = 837, - [BNXT_ULP_CLASS_HID_b17f] = 838, - [BNXT_ULP_CLASS_HID_f43f] = 839, - [BNXT_ULP_CLASS_HID_f6ff] = 840, - [BNXT_ULP_CLASS_HID_a9e3] = 841, - [BNXT_ULP_CLASS_HID_aca3] = 842, - [BNXT_ULP_CLASS_HID_ef63] = 843, - [BNXT_ULP_CLASS_HID_f223] = 844, - [BNXT_ULP_CLASS_HID_1bfe3] = 845, - [BNXT_ULP_CLASS_HID_1e2a3] = 846, - [BNXT_ULP_CLASS_HID_1c563] = 847, - [BNXT_ULP_CLASS_HID_1e823] = 848, - [BNXT_ULP_CLASS_HID_1c4bf] = 849, - [BNXT_ULP_CLASS_HID_1e77f] = 850, - [BNXT_ULP_CLASS_HID_1ca3f] = 851, - [BNXT_ULP_CLASS_HID_1ecff] = 852, - [BNXT_ULP_CLASS_HID_2543] = 853, - [BNXT_ULP_CLASS_HID_2b8f] = 854, - [BNXT_ULP_CLASS_HID_4f13] = 855, - [BNXT_ULP_CLASS_HID_162b] = 856, - [BNXT_ULP_CLASS_HID_39bf] = 857, - [BNXT_ULP_CLASS_HID_48d7] = 858, - [BNXT_ULP_CLASS_HID_0fef] = 859, - [BNXT_ULP_CLASS_HID_3373] = 860, - [BNXT_ULP_CLASS_HID_b6ef] = 861, - [BNXT_ULP_CLASS_HID_b92f] = 862, - [BNXT_ULP_CLASS_HID_fc6f] = 863, - [BNXT_ULP_CLASS_HID_feaf] = 864, - [BNXT_ULP_CLASS_HID_b193] = 865, - [BNXT_ULP_CLASS_HID_b4d3] = 866, - [BNXT_ULP_CLASS_HID_f713] = 867, - [BNXT_ULP_CLASS_HID_fa53] = 868, - [BNXT_ULP_CLASS_HID_1c793] = 869, - [BNXT_ULP_CLASS_HID_1ead3] = 870, - [BNXT_ULP_CLASS_HID_1cd13] = 871, - [BNXT_ULP_CLASS_HID_1f053] = 872, - [BNXT_ULP_CLASS_HID_1ccef] = 873, - [BNXT_ULP_CLASS_HID_1ef2f] = 874, - [BNXT_ULP_CLASS_HID_1d26f] = 875, - [BNXT_ULP_CLASS_HID_1f4af] = 876, - [BNXT_ULP_CLASS_HID_da73] = 877, - [BNXT_ULP_CLASS_HID_a067] = 878, - [BNXT_ULP_CLASS_HID_c2a7] = 879, - [BNXT_ULP_CLASS_HID_e5e7] = 880, - [BNXT_ULP_CLASS_HID_d527] = 881, - [BNXT_ULP_CLASS_HID_f867] = 882, - [BNXT_ULP_CLASS_HID_daa7] = 883, - [BNXT_ULP_CLASS_HID_e0ab] = 884, - [BNXT_ULP_CLASS_HID_18eeb] = 885, - [BNXT_ULP_CLASS_HID_1b12b] = 886, - [BNXT_ULP_CLASS_HID_1d46b] = 887, - [BNXT_ULP_CLASS_HID_1f6ab] = 888, - [BNXT_ULP_CLASS_HID_19327] = 889, - [BNXT_ULP_CLASS_HID_1b667] = 890, - [BNXT_ULP_CLASS_HID_1d8a7] = 891, - [BNXT_ULP_CLASS_HID_1fbe7] = 892, - [BNXT_ULP_CLASS_HID_a14b] = 893, - [BNXT_ULP_CLASS_HID_a38b] = 894, - [BNXT_ULP_CLASS_HID_e6cb] = 895, - [BNXT_ULP_CLASS_HID_e90b] = 896, - [BNXT_ULP_CLASS_HID_9c7f] = 897, - [BNXT_ULP_CLASS_HID_bebf] = 898, - [BNXT_ULP_CLASS_HID_e1ff] = 899, - [BNXT_ULP_CLASS_HID_e43f] = 900, - [BNXT_ULP_CLASS_HID_1b27f] = 901, - [BNXT_ULP_CLASS_HID_1b4bf] = 902, - [BNXT_ULP_CLASS_HID_1f7ff] = 903, - [BNXT_ULP_CLASS_HID_1fa3f] = 904, - [BNXT_ULP_CLASS_HID_1b74b] = 905, - [BNXT_ULP_CLASS_HID_1b98b] = 906, - [BNXT_ULP_CLASS_HID_1fccb] = 907, - [BNXT_ULP_CLASS_HID_1ff0b] = 908, - [BNXT_ULP_CLASS_HID_c4df] = 909, - [BNXT_ULP_CLASS_HID_e71f] = 910, - [BNXT_ULP_CLASS_HID_ca5f] = 911, - [BNXT_ULP_CLASS_HID_ec9f] = 912, - [BNXT_ULP_CLASS_HID_bf83] = 913, - [BNXT_ULP_CLASS_HID_e2c3] = 914, - [BNXT_ULP_CLASS_HID_c503] = 915, - [BNXT_ULP_CLASS_HID_e843] = 916, - [BNXT_ULP_CLASS_HID_1d583] = 917, - [BNXT_ULP_CLASS_HID_1f8c3] = 918, - [BNXT_ULP_CLASS_HID_1db03] = 919, - [BNXT_ULP_CLASS_HID_1e177] = 920, - [BNXT_ULP_CLASS_HID_1dadf] = 921, - [BNXT_ULP_CLASS_HID_1a0c3] = 922, - [BNXT_ULP_CLASS_HID_1c303] = 923, - [BNXT_ULP_CLASS_HID_1e643] = 924, - [BNXT_ULP_CLASS_HID_b023] = 925, - [BNXT_ULP_CLASS_HID_b363] = 926, - [BNXT_ULP_CLASS_HID_f5a3] = 927, - [BNXT_ULP_CLASS_HID_f8e3] = 928, - [BNXT_ULP_CLASS_HID_abd7] = 929, - [BNXT_ULP_CLASS_HID_ae17] = 930, - [BNXT_ULP_CLASS_HID_f157] = 931, - [BNXT_ULP_CLASS_HID_f397] = 932, - [BNXT_ULP_CLASS_HID_1c1d7] = 933, - [BNXT_ULP_CLASS_HID_1e417] = 934, - [BNXT_ULP_CLASS_HID_1c757] = 935, - [BNXT_ULP_CLASS_HID_1e997] = 936, - [BNXT_ULP_CLASS_HID_1c623] = 937, - [BNXT_ULP_CLASS_HID_1e963] = 938, - [BNXT_ULP_CLASS_HID_1cba3] = 939, - [BNXT_ULP_CLASS_HID_1eee3] = 940, - [BNXT_ULP_CLASS_HID_d3b7] = 941, - [BNXT_ULP_CLASS_HID_f6f7] = 942, - [BNXT_ULP_CLASS_HID_d937] = 943, - [BNXT_ULP_CLASS_HID_fc77] = 944, - [BNXT_ULP_CLASS_HID_cf7b] = 945, - [BNXT_ULP_CLASS_HID_f1bb] = 946, - [BNXT_ULP_CLASS_HID_d4fb] = 947, - [BNXT_ULP_CLASS_HID_f73b] = 948, - [BNXT_ULP_CLASS_HID_1882f] = 949, - [BNXT_ULP_CLASS_HID_1ab6f] = 950, - [BNXT_ULP_CLASS_HID_1cdaf] = 951, - [BNXT_ULP_CLASS_HID_1f0ef] = 952, - [BNXT_ULP_CLASS_HID_18d7b] = 953, - [BNXT_ULP_CLASS_HID_1afbb] = 954, - [BNXT_ULP_CLASS_HID_1d2fb] = 955, - [BNXT_ULP_CLASS_HID_1f53b] = 956, - [BNXT_ULP_CLASS_HID_9a8f] = 957, - [BNXT_ULP_CLASS_HID_bdcf] = 958, - [BNXT_ULP_CLASS_HID_e00f] = 959, - [BNXT_ULP_CLASS_HID_e34f] = 960, - [BNXT_ULP_CLASS_HID_95b3] = 961, - [BNXT_ULP_CLASS_HID_b8f3] = 962, - [BNXT_ULP_CLASS_HID_db33] = 963, - [BNXT_ULP_CLASS_HID_fe73] = 964, - [BNXT_ULP_CLASS_HID_1abb3] = 965, - [BNXT_ULP_CLASS_HID_1aef3] = 966, - [BNXT_ULP_CLASS_HID_1f133] = 967, - [BNXT_ULP_CLASS_HID_1f473] = 968, - [BNXT_ULP_CLASS_HID_1b08f] = 969, - [BNXT_ULP_CLASS_HID_1b3cf] = 970, - [BNXT_ULP_CLASS_HID_1f60f] = 971, - [BNXT_ULP_CLASS_HID_1f94f] = 972, - [BNXT_ULP_CLASS_HID_be13] = 973, - [BNXT_ULP_CLASS_HID_e153] = 974, - [BNXT_ULP_CLASS_HID_c393] = 975, - [BNXT_ULP_CLASS_HID_e6d3] = 976, - [BNXT_ULP_CLASS_HID_b9c7] = 977, - [BNXT_ULP_CLASS_HID_bc07] = 978, - [BNXT_ULP_CLASS_HID_ff47] = 979, - [BNXT_ULP_CLASS_HID_e187] = 980, - [BNXT_ULP_CLASS_HID_1cfc7] = 981, - [BNXT_ULP_CLASS_HID_1f207] = 982, - [BNXT_ULP_CLASS_HID_1d547] = 983, - [BNXT_ULP_CLASS_HID_1f787] = 984, - [BNXT_ULP_CLASS_HID_1d413] = 985, - [BNXT_ULP_CLASS_HID_1f753] = 986, - [BNXT_ULP_CLASS_HID_1d993] = 987, - [BNXT_ULP_CLASS_HID_1fcd3] = 988, - [BNXT_ULP_CLASS_HID_aa67] = 989, - [BNXT_ULP_CLASS_HID_aca7] = 990, - [BNXT_ULP_CLASS_HID_efe7] = 991, - [BNXT_ULP_CLASS_HID_f227] = 992, - [BNXT_ULP_CLASS_HID_a52b] = 993, - [BNXT_ULP_CLASS_HID_a86b] = 994, - [BNXT_ULP_CLASS_HID_eaab] = 995, - [BNXT_ULP_CLASS_HID_edeb] = 996, - [BNXT_ULP_CLASS_HID_1bb2b] = 997, - [BNXT_ULP_CLASS_HID_1be6b] = 998, - [BNXT_ULP_CLASS_HID_1c0ab] = 999, - [BNXT_ULP_CLASS_HID_1e3eb] = 1000, - [BNXT_ULP_CLASS_HID_1c067] = 1001, - [BNXT_ULP_CLASS_HID_1e2a7] = 1002, - [BNXT_ULP_CLASS_HID_1c5e7] = 1003, - [BNXT_ULP_CLASS_HID_1e827] = 1004, - [BNXT_ULP_CLASS_HID_cd8b] = 1005, - [BNXT_ULP_CLASS_HID_f0cb] = 1006, - [BNXT_ULP_CLASS_HID_d30b] = 1007, - [BNXT_ULP_CLASS_HID_f64b] = 1008, - [BNXT_ULP_CLASS_HID_c8bf] = 1009, - [BNXT_ULP_CLASS_HID_ebff] = 1010, - [BNXT_ULP_CLASS_HID_ce3f] = 1011, - [BNXT_ULP_CLASS_HID_f17f] = 1012, - [BNXT_ULP_CLASS_HID_18263] = 1013, - [BNXT_ULP_CLASS_HID_1a4a3] = 1014, - [BNXT_ULP_CLASS_HID_1c7e3] = 1015, - [BNXT_ULP_CLASS_HID_1ea23] = 1016, - [BNXT_ULP_CLASS_HID_186bf] = 1017, - [BNXT_ULP_CLASS_HID_1a9ff] = 1018, - [BNXT_ULP_CLASS_HID_1cc3f] = 1019, - [BNXT_ULP_CLASS_HID_1ef7f] = 1020, - [BNXT_ULP_CLASS_HID_94c3] = 1021, - [BNXT_ULP_CLASS_HID_b703] = 1022, - [BNXT_ULP_CLASS_HID_da43] = 1023, - [BNXT_ULP_CLASS_HID_fc83] = 1024, - [BNXT_ULP_CLASS_HID_8ff7] = 1025, - [BNXT_ULP_CLASS_HID_b237] = 1026, - [BNXT_ULP_CLASS_HID_d577] = 1027, - [BNXT_ULP_CLASS_HID_f7b7] = 1028, - [BNXT_ULP_CLASS_HID_1a5f7] = 1029, - [BNXT_ULP_CLASS_HID_1a837] = 1030, - [BNXT_ULP_CLASS_HID_1eb77] = 1031, - [BNXT_ULP_CLASS_HID_1edb7] = 1032, - [BNXT_ULP_CLASS_HID_1aac3] = 1033, - [BNXT_ULP_CLASS_HID_1ad03] = 1034, - [BNXT_ULP_CLASS_HID_1f043] = 1035, - [BNXT_ULP_CLASS_HID_1f283] = 1036, - [BNXT_ULP_CLASS_HID_b857] = 1037, - [BNXT_ULP_CLASS_HID_ba97] = 1038, - [BNXT_ULP_CLASS_HID_fdd7] = 1039, - [BNXT_ULP_CLASS_HID_e017] = 1040, - [BNXT_ULP_CLASS_HID_b31b] = 1041, - [BNXT_ULP_CLASS_HID_b65b] = 1042, - [BNXT_ULP_CLASS_HID_f89b] = 1043, - [BNXT_ULP_CLASS_HID_fbdb] = 1044, - [BNXT_ULP_CLASS_HID_1c91b] = 1045, - [BNXT_ULP_CLASS_HID_1ec5b] = 1046, - [BNXT_ULP_CLASS_HID_1ce9b] = 1047, - [BNXT_ULP_CLASS_HID_1f1db] = 1048, - [BNXT_ULP_CLASS_HID_1ce57] = 1049, - [BNXT_ULP_CLASS_HID_1f097] = 1050, - [BNXT_ULP_CLASS_HID_1d3d7] = 1051, - [BNXT_ULP_CLASS_HID_1f617] = 1052, - [BNXT_ULP_CLASS_HID_a3bb] = 1053, - [BNXT_ULP_CLASS_HID_a6fb] = 1054, - [BNXT_ULP_CLASS_HID_e93b] = 1055, - [BNXT_ULP_CLASS_HID_ec7b] = 1056, - [BNXT_ULP_CLASS_HID_9f6f] = 1057, - [BNXT_ULP_CLASS_HID_a1af] = 1058, - [BNXT_ULP_CLASS_HID_e4ef] = 1059, - [BNXT_ULP_CLASS_HID_e72f] = 1060, - [BNXT_ULP_CLASS_HID_1b56f] = 1061, - [BNXT_ULP_CLASS_HID_1b7af] = 1062, - [BNXT_ULP_CLASS_HID_1faef] = 1063, - [BNXT_ULP_CLASS_HID_1fd2f] = 1064, - [BNXT_ULP_CLASS_HID_1b9bb] = 1065, - [BNXT_ULP_CLASS_HID_1bcfb] = 1066, - [BNXT_ULP_CLASS_HID_1ff3b] = 1067, - [BNXT_ULP_CLASS_HID_1e27b] = 1068, - [BNXT_ULP_CLASS_HID_c7cf] = 1069, - [BNXT_ULP_CLASS_HID_ea0f] = 1070, - [BNXT_ULP_CLASS_HID_cd4f] = 1071, - [BNXT_ULP_CLASS_HID_ef8f] = 1072, - [BNXT_ULP_CLASS_HID_c2f3] = 1073, - [BNXT_ULP_CLASS_HID_e533] = 1074, - [BNXT_ULP_CLASS_HID_c873] = 1075, - [BNXT_ULP_CLASS_HID_eab3] = 1076, - [BNXT_ULP_CLASS_HID_1d8f3] = 1077, - [BNXT_ULP_CLASS_HID_1fb33] = 1078, - [BNXT_ULP_CLASS_HID_1c127] = 1079, - [BNXT_ULP_CLASS_HID_1e467] = 1080, - [BNXT_ULP_CLASS_HID_180f3] = 1081, - [BNXT_ULP_CLASS_HID_1a333] = 1082, - [BNXT_ULP_CLASS_HID_1c673] = 1083, - [BNXT_ULP_CLASS_HID_1e8b3] = 1084, - [BNXT_ULP_CLASS_HID_8e07] = 1085, - [BNXT_ULP_CLASS_HID_b147] = 1086, - [BNXT_ULP_CLASS_HID_d387] = 1087, - [BNXT_ULP_CLASS_HID_f6c7] = 1088, - [BNXT_ULP_CLASS_HID_89cb] = 1089, - [BNXT_ULP_CLASS_HID_ac0b] = 1090, - [BNXT_ULP_CLASS_HID_cf4b] = 1091, - [BNXT_ULP_CLASS_HID_f18b] = 1092, - [BNXT_ULP_CLASS_HID_19fcb] = 1093, - [BNXT_ULP_CLASS_HID_1a20b] = 1094, - [BNXT_ULP_CLASS_HID_1e54b] = 1095, - [BNXT_ULP_CLASS_HID_1e78b] = 1096, - [BNXT_ULP_CLASS_HID_1a407] = 1097, - [BNXT_ULP_CLASS_HID_1a747] = 1098, - [BNXT_ULP_CLASS_HID_1e987] = 1099, - [BNXT_ULP_CLASS_HID_1ecc7] = 1100, - [BNXT_ULP_CLASS_HID_b1ab] = 1101, - [BNXT_ULP_CLASS_HID_b4eb] = 1102, - [BNXT_ULP_CLASS_HID_f72b] = 1103, - [BNXT_ULP_CLASS_HID_fa6b] = 1104, - [BNXT_ULP_CLASS_HID_ad5f] = 1105, - [BNXT_ULP_CLASS_HID_af9f] = 1106, - [BNXT_ULP_CLASS_HID_f2df] = 1107, - [BNXT_ULP_CLASS_HID_f51f] = 1108, - [BNXT_ULP_CLASS_HID_1c35f] = 1109, - [BNXT_ULP_CLASS_HID_1e59f] = 1110, - [BNXT_ULP_CLASS_HID_1c8df] = 1111, - [BNXT_ULP_CLASS_HID_1eb1f] = 1112, - [BNXT_ULP_CLASS_HID_1c7ab] = 1113, - [BNXT_ULP_CLASS_HID_1eaeb] = 1114, - [BNXT_ULP_CLASS_HID_1cd2b] = 1115, - [BNXT_ULP_CLASS_HID_1f06b] = 1116, - [BNXT_ULP_CLASS_HID_9177] = 1117, - [BNXT_ULP_CLASS_HID_b3b7] = 1118, - [BNXT_ULP_CLASS_HID_d6f7] = 1119, - [BNXT_ULP_CLASS_HID_f937] = 1120, - [BNXT_ULP_CLASS_HID_8c3b] = 1121, - [BNXT_ULP_CLASS_HID_af7b] = 1122, - [BNXT_ULP_CLASS_HID_d1bb] = 1123, - [BNXT_ULP_CLASS_HID_f4fb] = 1124, - [BNXT_ULP_CLASS_HID_1a23b] = 1125, - [BNXT_ULP_CLASS_HID_1a57b] = 1126, - [BNXT_ULP_CLASS_HID_1e7bb] = 1127, - [BNXT_ULP_CLASS_HID_1eafb] = 1128, - [BNXT_ULP_CLASS_HID_1a777] = 1129, - [BNXT_ULP_CLASS_HID_1a9b7] = 1130, - [BNXT_ULP_CLASS_HID_1ecf7] = 1131, - [BNXT_ULP_CLASS_HID_1ef37] = 1132, - [BNXT_ULP_CLASS_HID_b49b] = 1133, - [BNXT_ULP_CLASS_HID_b7db] = 1134, - [BNXT_ULP_CLASS_HID_fa1b] = 1135, - [BNXT_ULP_CLASS_HID_fd5b] = 1136, - [BNXT_ULP_CLASS_HID_b04f] = 1137, - [BNXT_ULP_CLASS_HID_b28f] = 1138, - [BNXT_ULP_CLASS_HID_f5cf] = 1139, - [BNXT_ULP_CLASS_HID_f80f] = 1140, - [BNXT_ULP_CLASS_HID_1c64f] = 1141, - [BNXT_ULP_CLASS_HID_1e88f] = 1142, - [BNXT_ULP_CLASS_HID_1cbcf] = 1143, - [BNXT_ULP_CLASS_HID_1ee0f] = 1144, - [BNXT_ULP_CLASS_HID_1ca9b] = 1145, - [BNXT_ULP_CLASS_HID_1eddb] = 1146, - [BNXT_ULP_CLASS_HID_1d01b] = 1147, - [BNXT_ULP_CLASS_HID_1f35b] = 1148, - [BNXT_ULP_CLASS_HID_8b4b] = 1149, - [BNXT_ULP_CLASS_HID_ad8b] = 1150, - [BNXT_ULP_CLASS_HID_d0cb] = 1151, - [BNXT_ULP_CLASS_HID_f30b] = 1152, - [BNXT_ULP_CLASS_HID_867f] = 1153, - [BNXT_ULP_CLASS_HID_a8bf] = 1154, - [BNXT_ULP_CLASS_HID_cbff] = 1155, - [BNXT_ULP_CLASS_HID_ee3f] = 1156, - [BNXT_ULP_CLASS_HID_19c7f] = 1157, - [BNXT_ULP_CLASS_HID_1bebf] = 1158, - [BNXT_ULP_CLASS_HID_1e1ff] = 1159, - [BNXT_ULP_CLASS_HID_1e43f] = 1160, - [BNXT_ULP_CLASS_HID_1a14b] = 1161, - [BNXT_ULP_CLASS_HID_1a38b] = 1162, - [BNXT_ULP_CLASS_HID_1e6cb] = 1163, - [BNXT_ULP_CLASS_HID_1e90b] = 1164, - [BNXT_ULP_CLASS_HID_aedf] = 1165, - [BNXT_ULP_CLASS_HID_b11f] = 1166, - [BNXT_ULP_CLASS_HID_f45f] = 1167, - [BNXT_ULP_CLASS_HID_f69f] = 1168, - [BNXT_ULP_CLASS_HID_a983] = 1169, - [BNXT_ULP_CLASS_HID_acc3] = 1170, - [BNXT_ULP_CLASS_HID_ef03] = 1171, - [BNXT_ULP_CLASS_HID_f243] = 1172, - [BNXT_ULP_CLASS_HID_1bf83] = 1173, - [BNXT_ULP_CLASS_HID_1e2c3] = 1174, - [BNXT_ULP_CLASS_HID_1c503] = 1175, - [BNXT_ULP_CLASS_HID_1e843] = 1176, - [BNXT_ULP_CLASS_HID_1c4df] = 1177, - [BNXT_ULP_CLASS_HID_1e71f] = 1178, - [BNXT_ULP_CLASS_HID_1ca5f] = 1179, - [BNXT_ULP_CLASS_HID_1ec9f] = 1180, - [BNXT_ULP_CLASS_HID_2523] = 1181, - [BNXT_ULP_CLASS_HID_2bef] = 1182, - [BNXT_ULP_CLASS_HID_4f73] = 1183, - [BNXT_ULP_CLASS_HID_164b] = 1184, - [BNXT_ULP_CLASS_HID_39df] = 1185, - [BNXT_ULP_CLASS_HID_48b7] = 1186, - [BNXT_ULP_CLASS_HID_0f8f] = 1187, - [BNXT_ULP_CLASS_HID_3313] = 1188, - [BNXT_ULP_CLASS_HID_257b7] = 1189, - [BNXT_ULP_CLASS_HID_24467] = 1190, - [BNXT_ULP_CLASS_HID_23fbb] = 1191, - [BNXT_ULP_CLASS_HID_252cb] = 1192, - [BNXT_ULP_CLASS_HID_21e7f] = 1193, - [BNXT_ULP_CLASS_HID_20b2f] = 1194, - [BNXT_ULP_CLASS_HID_20663] = 1195, - [BNXT_ULP_CLASS_HID_219b3] = 1196, - [BNXT_ULP_CLASS_HID_24213] = 1197, - [BNXT_ULP_CLASS_HID_22ec3] = 1198, - [BNXT_ULP_CLASS_HID_22a17] = 1199, - [BNXT_ULP_CLASS_HID_23d27] = 1200, - [BNXT_ULP_CLASS_HID_208db] = 1201, - [BNXT_ULP_CLASS_HID_25277] = 1202, - [BNXT_ULP_CLASS_HID_24d8b] = 1203, - [BNXT_ULP_CLASS_HID_203ef] = 1204, - [BNXT_ULP_CLASS_HID_2517b] = 1205, - [BNXT_ULP_CLASS_HID_23e2b] = 1206, - [BNXT_ULP_CLASS_HID_2397f] = 1207, - [BNXT_ULP_CLASS_HID_24c8f] = 1208, - [BNXT_ULP_CLASS_HID_21823] = 1209, - [BNXT_ULP_CLASS_HID_20513] = 1210, - [BNXT_ULP_CLASS_HID_20027] = 1211, - [BNXT_ULP_CLASS_HID_21377] = 1212, - [BNXT_ULP_CLASS_HID_23bd7] = 1213, - [BNXT_ULP_CLASS_HID_22887] = 1214, - [BNXT_ULP_CLASS_HID_223db] = 1215, - [BNXT_ULP_CLASS_HID_236eb] = 1216, - [BNXT_ULP_CLASS_HID_2029f] = 1217, - [BNXT_ULP_CLASS_HID_24c3b] = 1218, - [BNXT_ULP_CLASS_HID_2474f] = 1219, - [BNXT_ULP_CLASS_HID_25a9f] = 1220, - [BNXT_ULP_CLASS_HID_24b3f] = 1221, - [BNXT_ULP_CLASS_HID_237ef] = 1222, - [BNXT_ULP_CLASS_HID_23323] = 1223, - [BNXT_ULP_CLASS_HID_24673] = 1224, - [BNXT_ULP_CLASS_HID_211e7] = 1225, - [BNXT_ULP_CLASS_HID_25b83] = 1226, - [BNXT_ULP_CLASS_HID_256d7] = 1227, - [BNXT_ULP_CLASS_HID_20d3b] = 1228, - [BNXT_ULP_CLASS_HID_2359b] = 1229, - [BNXT_ULP_CLASS_HID_2224b] = 1230, - [BNXT_ULP_CLASS_HID_21d9f] = 1231, - [BNXT_ULP_CLASS_HID_230af] = 1232, - [BNXT_ULP_CLASS_HID_2590f] = 1233, - [BNXT_ULP_CLASS_HID_245ff] = 1234, - [BNXT_ULP_CLASS_HID_24133] = 1235, - [BNXT_ULP_CLASS_HID_25443] = 1236, - [BNXT_ULP_CLASS_HID_244e3] = 1237, - [BNXT_ULP_CLASS_HID_231d3] = 1238, - [BNXT_ULP_CLASS_HID_22ce7] = 1239, - [BNXT_ULP_CLASS_HID_24037] = 1240, - [BNXT_ULP_CLASS_HID_20bab] = 1241, - [BNXT_ULP_CLASS_HID_25547] = 1242, - [BNXT_ULP_CLASS_HID_2509b] = 1243, - [BNXT_ULP_CLASS_HID_206ff] = 1244, - [BNXT_ULP_CLASS_HID_22f5f] = 1245, - [BNXT_ULP_CLASS_HID_21c0f] = 1246, - [BNXT_ULP_CLASS_HID_21743] = 1247, - [BNXT_ULP_CLASS_HID_22a93] = 1248, - [BNXT_ULP_CLASS_HID_252f3] = 1249, - [BNXT_ULP_CLASS_HID_23fa3] = 1250, - [BNXT_ULP_CLASS_HID_23af7] = 1251, - [BNXT_ULP_CLASS_HID_24e07] = 1252, - [BNXT_ULP_CLASS_HID_2322f] = 1253, - [BNXT_ULP_CLASS_HID_21f1f] = 1254, - [BNXT_ULP_CLASS_HID_21a53] = 1255, - [BNXT_ULP_CLASS_HID_22d63] = 1256, - [BNXT_ULP_CLASS_HID_255c3] = 1257, - [BNXT_ULP_CLASS_HID_242b3] = 1258, - [BNXT_ULP_CLASS_HID_23dc7] = 1259, - [BNXT_ULP_CLASS_HID_25117] = 1260, - [BNXT_ULP_CLASS_HID_22c13] = 1261, - [BNXT_ULP_CLASS_HID_218c3] = 1262, - [BNXT_ULP_CLASS_HID_21417] = 1263, - [BNXT_ULP_CLASS_HID_22727] = 1264, - [BNXT_ULP_CLASS_HID_24f87] = 1265, - [BNXT_ULP_CLASS_HID_23c77] = 1266, - [BNXT_ULP_CLASS_HID_2378b] = 1267, - [BNXT_ULP_CLASS_HID_24adb] = 1268, - [BNXT_ULP_CLASS_HID_257b] = 1269, - [BNXT_ULP_CLASS_HID_2bb7] = 1270, - [BNXT_ULP_CLASS_HID_4f2b] = 1271, - [BNXT_ULP_CLASS_HID_1613] = 1272, - [BNXT_ULP_CLASS_HID_3987] = 1273, - [BNXT_ULP_CLASS_HID_48ef] = 1274, - [BNXT_ULP_CLASS_HID_0fd7] = 1275, - [BNXT_ULP_CLASS_HID_334b] = 1276, - [BNXT_ULP_CLASS_HID_25797] = 1277, - [BNXT_ULP_CLASS_HID_285eb] = 1278, - [BNXT_ULP_CLASS_HID_310eb] = 1279, - [BNXT_ULP_CLASS_HID_39beb] = 1280, - [BNXT_ULP_CLASS_HID_24447] = 1281, - [BNXT_ULP_CLASS_HID_2cf47] = 1282, - [BNXT_ULP_CLASS_HID_35a47] = 1283, - [BNXT_ULP_CLASS_HID_3889b] = 1284, - [BNXT_ULP_CLASS_HID_23f9b] = 1285, - [BNXT_ULP_CLASS_HID_2ca9b] = 1286, - [BNXT_ULP_CLASS_HID_3559b] = 1287, - [BNXT_ULP_CLASS_HID_383ef] = 1288, - [BNXT_ULP_CLASS_HID_252eb] = 1289, - [BNXT_ULP_CLASS_HID_2813f] = 1290, - [BNXT_ULP_CLASS_HID_30c3f] = 1291, - [BNXT_ULP_CLASS_HID_3973f] = 1292, - [BNXT_ULP_CLASS_HID_21e5f] = 1293, - [BNXT_ULP_CLASS_HID_2a95f] = 1294, - [BNXT_ULP_CLASS_HID_3345f] = 1295, - [BNXT_ULP_CLASS_HID_3bf5f] = 1296, - [BNXT_ULP_CLASS_HID_20b0f] = 1297, - [BNXT_ULP_CLASS_HID_2960f] = 1298, - [BNXT_ULP_CLASS_HID_3210f] = 1299, - [BNXT_ULP_CLASS_HID_3ac0f] = 1300, - [BNXT_ULP_CLASS_HID_20643] = 1301, - [BNXT_ULP_CLASS_HID_29143] = 1302, - [BNXT_ULP_CLASS_HID_31c43] = 1303, - [BNXT_ULP_CLASS_HID_3a743] = 1304, - [BNXT_ULP_CLASS_HID_21993] = 1305, - [BNXT_ULP_CLASS_HID_2a493] = 1306, - [BNXT_ULP_CLASS_HID_32f93] = 1307, - [BNXT_ULP_CLASS_HID_3ba93] = 1308, - [BNXT_ULP_CLASS_HID_24233] = 1309, - [BNXT_ULP_CLASS_HID_2cd33] = 1310, - [BNXT_ULP_CLASS_HID_35833] = 1311, - [BNXT_ULP_CLASS_HID_38607] = 1312, - [BNXT_ULP_CLASS_HID_22ee3] = 1313, - [BNXT_ULP_CLASS_HID_2b9e3] = 1314, - [BNXT_ULP_CLASS_HID_344e3] = 1315, - [BNXT_ULP_CLASS_HID_3cfe3] = 1316, - [BNXT_ULP_CLASS_HID_22a37] = 1317, - [BNXT_ULP_CLASS_HID_2b537] = 1318, - [BNXT_ULP_CLASS_HID_34037] = 1319, - [BNXT_ULP_CLASS_HID_3cb37] = 1320, - [BNXT_ULP_CLASS_HID_23d07] = 1321, - [BNXT_ULP_CLASS_HID_2c807] = 1322, - [BNXT_ULP_CLASS_HID_35307] = 1323, - [BNXT_ULP_CLASS_HID_3815b] = 1324, - [BNXT_ULP_CLASS_HID_208fb] = 1325, - [BNXT_ULP_CLASS_HID_293fb] = 1326, - [BNXT_ULP_CLASS_HID_31efb] = 1327, - [BNXT_ULP_CLASS_HID_3a9fb] = 1328, - [BNXT_ULP_CLASS_HID_25257] = 1329, - [BNXT_ULP_CLASS_HID_280ab] = 1330, - [BNXT_ULP_CLASS_HID_30bab] = 1331, - [BNXT_ULP_CLASS_HID_396ab] = 1332, - [BNXT_ULP_CLASS_HID_24dab] = 1333, - [BNXT_ULP_CLASS_HID_2d8ab] = 1334, - [BNXT_ULP_CLASS_HID_306ff] = 1335, - [BNXT_ULP_CLASS_HID_391ff] = 1336, - [BNXT_ULP_CLASS_HID_203cf] = 1337, - [BNXT_ULP_CLASS_HID_28ecf] = 1338, - [BNXT_ULP_CLASS_HID_319cf] = 1339, - [BNXT_ULP_CLASS_HID_3a4cf] = 1340, - [BNXT_ULP_CLASS_HID_2515b] = 1341, - [BNXT_ULP_CLASS_HID_2dc5b] = 1342, - [BNXT_ULP_CLASS_HID_30aaf] = 1343, - [BNXT_ULP_CLASS_HID_395af] = 1344, - [BNXT_ULP_CLASS_HID_23e0b] = 1345, - [BNXT_ULP_CLASS_HID_2c90b] = 1346, - [BNXT_ULP_CLASS_HID_3540b] = 1347, - [BNXT_ULP_CLASS_HID_3825f] = 1348, - [BNXT_ULP_CLASS_HID_2395f] = 1349, - [BNXT_ULP_CLASS_HID_2c45f] = 1350, - [BNXT_ULP_CLASS_HID_34f5f] = 1351, - [BNXT_ULP_CLASS_HID_3da5f] = 1352, - [BNXT_ULP_CLASS_HID_24caf] = 1353, - [BNXT_ULP_CLASS_HID_2d7af] = 1354, - [BNXT_ULP_CLASS_HID_305e3] = 1355, - [BNXT_ULP_CLASS_HID_390e3] = 1356, - [BNXT_ULP_CLASS_HID_21803] = 1357, - [BNXT_ULP_CLASS_HID_2a303] = 1358, - [BNXT_ULP_CLASS_HID_32e03] = 1359, - [BNXT_ULP_CLASS_HID_3b903] = 1360, - [BNXT_ULP_CLASS_HID_20533] = 1361, - [BNXT_ULP_CLASS_HID_29033] = 1362, - [BNXT_ULP_CLASS_HID_31b33] = 1363, - [BNXT_ULP_CLASS_HID_3a633] = 1364, - [BNXT_ULP_CLASS_HID_20007] = 1365, - [BNXT_ULP_CLASS_HID_28b07] = 1366, - [BNXT_ULP_CLASS_HID_31607] = 1367, - [BNXT_ULP_CLASS_HID_3a107] = 1368, - [BNXT_ULP_CLASS_HID_21357] = 1369, - [BNXT_ULP_CLASS_HID_29e57] = 1370, - [BNXT_ULP_CLASS_HID_32957] = 1371, - [BNXT_ULP_CLASS_HID_3b457] = 1372, - [BNXT_ULP_CLASS_HID_23bf7] = 1373, - [BNXT_ULP_CLASS_HID_2c6f7] = 1374, - [BNXT_ULP_CLASS_HID_351f7] = 1375, - [BNXT_ULP_CLASS_HID_3dcf7] = 1376, - [BNXT_ULP_CLASS_HID_228a7] = 1377, - [BNXT_ULP_CLASS_HID_2b3a7] = 1378, - [BNXT_ULP_CLASS_HID_33ea7] = 1379, - [BNXT_ULP_CLASS_HID_3c9a7] = 1380, - [BNXT_ULP_CLASS_HID_223fb] = 1381, - [BNXT_ULP_CLASS_HID_2aefb] = 1382, - [BNXT_ULP_CLASS_HID_339fb] = 1383, - [BNXT_ULP_CLASS_HID_3c4fb] = 1384, - [BNXT_ULP_CLASS_HID_236cb] = 1385, - [BNXT_ULP_CLASS_HID_2c1cb] = 1386, - [BNXT_ULP_CLASS_HID_34ccb] = 1387, - [BNXT_ULP_CLASS_HID_3d7cb] = 1388, - [BNXT_ULP_CLASS_HID_202bf] = 1389, - [BNXT_ULP_CLASS_HID_28dbf] = 1390, - [BNXT_ULP_CLASS_HID_318bf] = 1391, - [BNXT_ULP_CLASS_HID_3a3bf] = 1392, - [BNXT_ULP_CLASS_HID_24c1b] = 1393, - [BNXT_ULP_CLASS_HID_2d71b] = 1394, - [BNXT_ULP_CLASS_HID_3056f] = 1395, - [BNXT_ULP_CLASS_HID_3906f] = 1396, - [BNXT_ULP_CLASS_HID_2476f] = 1397, - [BNXT_ULP_CLASS_HID_2d26f] = 1398, - [BNXT_ULP_CLASS_HID_300a3] = 1399, - [BNXT_ULP_CLASS_HID_38ba3] = 1400, - [BNXT_ULP_CLASS_HID_25abf] = 1401, - [BNXT_ULP_CLASS_HID_288f3] = 1402, - [BNXT_ULP_CLASS_HID_313f3] = 1403, - [BNXT_ULP_CLASS_HID_39ef3] = 1404, - [BNXT_ULP_CLASS_HID_24b1f] = 1405, - [BNXT_ULP_CLASS_HID_2d61f] = 1406, - [BNXT_ULP_CLASS_HID_30453] = 1407, - [BNXT_ULP_CLASS_HID_38f53] = 1408, - [BNXT_ULP_CLASS_HID_237cf] = 1409, - [BNXT_ULP_CLASS_HID_2c2cf] = 1410, - [BNXT_ULP_CLASS_HID_34dcf] = 1411, - [BNXT_ULP_CLASS_HID_3d8cf] = 1412, - [BNXT_ULP_CLASS_HID_23303] = 1413, - [BNXT_ULP_CLASS_HID_2be03] = 1414, - [BNXT_ULP_CLASS_HID_34903] = 1415, - [BNXT_ULP_CLASS_HID_3d403] = 1416, - [BNXT_ULP_CLASS_HID_24653] = 1417, - [BNXT_ULP_CLASS_HID_2d153] = 1418, - [BNXT_ULP_CLASS_HID_35c53] = 1419, - [BNXT_ULP_CLASS_HID_38aa7] = 1420, - [BNXT_ULP_CLASS_HID_211c7] = 1421, - [BNXT_ULP_CLASS_HID_29cc7] = 1422, - [BNXT_ULP_CLASS_HID_327c7] = 1423, - [BNXT_ULP_CLASS_HID_3b2c7] = 1424, - [BNXT_ULP_CLASS_HID_25ba3] = 1425, - [BNXT_ULP_CLASS_HID_289f7] = 1426, - [BNXT_ULP_CLASS_HID_314f7] = 1427, - [BNXT_ULP_CLASS_HID_39ff7] = 1428, - [BNXT_ULP_CLASS_HID_256f7] = 1429, - [BNXT_ULP_CLASS_HID_284cb] = 1430, - [BNXT_ULP_CLASS_HID_30fcb] = 1431, - [BNXT_ULP_CLASS_HID_39acb] = 1432, - [BNXT_ULP_CLASS_HID_20d1b] = 1433, - [BNXT_ULP_CLASS_HID_2981b] = 1434, - [BNXT_ULP_CLASS_HID_3231b] = 1435, - [BNXT_ULP_CLASS_HID_3ae1b] = 1436, - [BNXT_ULP_CLASS_HID_235bb] = 1437, - [BNXT_ULP_CLASS_HID_2c0bb] = 1438, - [BNXT_ULP_CLASS_HID_34bbb] = 1439, - [BNXT_ULP_CLASS_HID_3d6bb] = 1440, - [BNXT_ULP_CLASS_HID_2226b] = 1441, - [BNXT_ULP_CLASS_HID_2ad6b] = 1442, - [BNXT_ULP_CLASS_HID_3386b] = 1443, - [BNXT_ULP_CLASS_HID_3c36b] = 1444, - [BNXT_ULP_CLASS_HID_21dbf] = 1445, - [BNXT_ULP_CLASS_HID_2a8bf] = 1446, - [BNXT_ULP_CLASS_HID_333bf] = 1447, - [BNXT_ULP_CLASS_HID_3bebf] = 1448, - [BNXT_ULP_CLASS_HID_2308f] = 1449, - [BNXT_ULP_CLASS_HID_2bb8f] = 1450, - [BNXT_ULP_CLASS_HID_3468f] = 1451, - [BNXT_ULP_CLASS_HID_3d18f] = 1452, - [BNXT_ULP_CLASS_HID_2592f] = 1453, - [BNXT_ULP_CLASS_HID_28763] = 1454, - [BNXT_ULP_CLASS_HID_31263] = 1455, - [BNXT_ULP_CLASS_HID_39d63] = 1456, - [BNXT_ULP_CLASS_HID_245df] = 1457, - [BNXT_ULP_CLASS_HID_2d0df] = 1458, - [BNXT_ULP_CLASS_HID_35bdf] = 1459, - [BNXT_ULP_CLASS_HID_38a13] = 1460, - [BNXT_ULP_CLASS_HID_24113] = 1461, - [BNXT_ULP_CLASS_HID_2cc13] = 1462, - [BNXT_ULP_CLASS_HID_35713] = 1463, - [BNXT_ULP_CLASS_HID_38567] = 1464, - [BNXT_ULP_CLASS_HID_25463] = 1465, - [BNXT_ULP_CLASS_HID_282b7] = 1466, - [BNXT_ULP_CLASS_HID_30db7] = 1467, - [BNXT_ULP_CLASS_HID_398b7] = 1468, - [BNXT_ULP_CLASS_HID_244c3] = 1469, - [BNXT_ULP_CLASS_HID_2cfc3] = 1470, - [BNXT_ULP_CLASS_HID_35ac3] = 1471, - [BNXT_ULP_CLASS_HID_38917] = 1472, - [BNXT_ULP_CLASS_HID_231f3] = 1473, - [BNXT_ULP_CLASS_HID_2bcf3] = 1474, - [BNXT_ULP_CLASS_HID_347f3] = 1475, - [BNXT_ULP_CLASS_HID_3d2f3] = 1476, - [BNXT_ULP_CLASS_HID_22cc7] = 1477, - [BNXT_ULP_CLASS_HID_2b7c7] = 1478, - [BNXT_ULP_CLASS_HID_342c7] = 1479, - [BNXT_ULP_CLASS_HID_3cdc7] = 1480, - [BNXT_ULP_CLASS_HID_24017] = 1481, - [BNXT_ULP_CLASS_HID_2cb17] = 1482, - [BNXT_ULP_CLASS_HID_35617] = 1483, - [BNXT_ULP_CLASS_HID_3846b] = 1484, - [BNXT_ULP_CLASS_HID_20b8b] = 1485, - [BNXT_ULP_CLASS_HID_2968b] = 1486, - [BNXT_ULP_CLASS_HID_3218b] = 1487, - [BNXT_ULP_CLASS_HID_3ac8b] = 1488, - [BNXT_ULP_CLASS_HID_25567] = 1489, - [BNXT_ULP_CLASS_HID_283bb] = 1490, - [BNXT_ULP_CLASS_HID_30ebb] = 1491, - [BNXT_ULP_CLASS_HID_399bb] = 1492, - [BNXT_ULP_CLASS_HID_250bb] = 1493, - [BNXT_ULP_CLASS_HID_2dbbb] = 1494, - [BNXT_ULP_CLASS_HID_3098f] = 1495, - [BNXT_ULP_CLASS_HID_3948f] = 1496, - [BNXT_ULP_CLASS_HID_206df] = 1497, - [BNXT_ULP_CLASS_HID_291df] = 1498, - [BNXT_ULP_CLASS_HID_31cdf] = 1499, - [BNXT_ULP_CLASS_HID_3a7df] = 1500, - [BNXT_ULP_CLASS_HID_22f7f] = 1501, - [BNXT_ULP_CLASS_HID_2ba7f] = 1502, - [BNXT_ULP_CLASS_HID_3457f] = 1503, - [BNXT_ULP_CLASS_HID_3d07f] = 1504, - [BNXT_ULP_CLASS_HID_21c2f] = 1505, - [BNXT_ULP_CLASS_HID_2a72f] = 1506, - [BNXT_ULP_CLASS_HID_3322f] = 1507, - [BNXT_ULP_CLASS_HID_3bd2f] = 1508, - [BNXT_ULP_CLASS_HID_21763] = 1509, - [BNXT_ULP_CLASS_HID_2a263] = 1510, - [BNXT_ULP_CLASS_HID_32d63] = 1511, - [BNXT_ULP_CLASS_HID_3b863] = 1512, - [BNXT_ULP_CLASS_HID_22ab3] = 1513, - [BNXT_ULP_CLASS_HID_2b5b3] = 1514, - [BNXT_ULP_CLASS_HID_340b3] = 1515, - [BNXT_ULP_CLASS_HID_3cbb3] = 1516, - [BNXT_ULP_CLASS_HID_252d3] = 1517, - [BNXT_ULP_CLASS_HID_28127] = 1518, - [BNXT_ULP_CLASS_HID_30c27] = 1519, - [BNXT_ULP_CLASS_HID_39727] = 1520, - [BNXT_ULP_CLASS_HID_23f83] = 1521, - [BNXT_ULP_CLASS_HID_2ca83] = 1522, - [BNXT_ULP_CLASS_HID_35583] = 1523, - [BNXT_ULP_CLASS_HID_383d7] = 1524, - [BNXT_ULP_CLASS_HID_23ad7] = 1525, - [BNXT_ULP_CLASS_HID_2c5d7] = 1526, - [BNXT_ULP_CLASS_HID_350d7] = 1527, - [BNXT_ULP_CLASS_HID_3dbd7] = 1528, - [BNXT_ULP_CLASS_HID_24e27] = 1529, - [BNXT_ULP_CLASS_HID_2d927] = 1530, - [BNXT_ULP_CLASS_HID_3077b] = 1531, - [BNXT_ULP_CLASS_HID_3927b] = 1532, - [BNXT_ULP_CLASS_HID_2320f] = 1533, - [BNXT_ULP_CLASS_HID_2bd0f] = 1534, - [BNXT_ULP_CLASS_HID_3480f] = 1535, - [BNXT_ULP_CLASS_HID_3d30f] = 1536, - [BNXT_ULP_CLASS_HID_21f3f] = 1537, - [BNXT_ULP_CLASS_HID_2aa3f] = 1538, - [BNXT_ULP_CLASS_HID_3353f] = 1539, - [BNXT_ULP_CLASS_HID_3c03f] = 1540, - [BNXT_ULP_CLASS_HID_21a73] = 1541, - [BNXT_ULP_CLASS_HID_2a573] = 1542, - [BNXT_ULP_CLASS_HID_33073] = 1543, - [BNXT_ULP_CLASS_HID_3bb73] = 1544, - [BNXT_ULP_CLASS_HID_22d43] = 1545, - [BNXT_ULP_CLASS_HID_2b843] = 1546, - [BNXT_ULP_CLASS_HID_34343] = 1547, - [BNXT_ULP_CLASS_HID_3ce43] = 1548, - [BNXT_ULP_CLASS_HID_255e3] = 1549, - [BNXT_ULP_CLASS_HID_28437] = 1550, - [BNXT_ULP_CLASS_HID_30f37] = 1551, - [BNXT_ULP_CLASS_HID_39a37] = 1552, - [BNXT_ULP_CLASS_HID_24293] = 1553, - [BNXT_ULP_CLASS_HID_2cd93] = 1554, - [BNXT_ULP_CLASS_HID_35893] = 1555, - [BNXT_ULP_CLASS_HID_386e7] = 1556, - [BNXT_ULP_CLASS_HID_23de7] = 1557, - [BNXT_ULP_CLASS_HID_2c8e7] = 1558, - [BNXT_ULP_CLASS_HID_353e7] = 1559, - [BNXT_ULP_CLASS_HID_3823b] = 1560, - [BNXT_ULP_CLASS_HID_25137] = 1561, - [BNXT_ULP_CLASS_HID_2dc37] = 1562, - [BNXT_ULP_CLASS_HID_30a0b] = 1563, - [BNXT_ULP_CLASS_HID_3950b] = 1564, - [BNXT_ULP_CLASS_HID_22c33] = 1565, - [BNXT_ULP_CLASS_HID_2b733] = 1566, - [BNXT_ULP_CLASS_HID_34233] = 1567, - [BNXT_ULP_CLASS_HID_3cd33] = 1568, - [BNXT_ULP_CLASS_HID_218e3] = 1569, - [BNXT_ULP_CLASS_HID_2a3e3] = 1570, - [BNXT_ULP_CLASS_HID_32ee3] = 1571, - [BNXT_ULP_CLASS_HID_3b9e3] = 1572, - [BNXT_ULP_CLASS_HID_21437] = 1573, - [BNXT_ULP_CLASS_HID_29f37] = 1574, - [BNXT_ULP_CLASS_HID_32a37] = 1575, - [BNXT_ULP_CLASS_HID_3b537] = 1576, - [BNXT_ULP_CLASS_HID_22707] = 1577, - [BNXT_ULP_CLASS_HID_2b207] = 1578, - [BNXT_ULP_CLASS_HID_33d07] = 1579, - [BNXT_ULP_CLASS_HID_3c807] = 1580, - [BNXT_ULP_CLASS_HID_24fa7] = 1581, - [BNXT_ULP_CLASS_HID_2daa7] = 1582, - [BNXT_ULP_CLASS_HID_308fb] = 1583, - [BNXT_ULP_CLASS_HID_393fb] = 1584, - [BNXT_ULP_CLASS_HID_23c57] = 1585, - [BNXT_ULP_CLASS_HID_2c757] = 1586, - [BNXT_ULP_CLASS_HID_35257] = 1587, - [BNXT_ULP_CLASS_HID_380ab] = 1588, - [BNXT_ULP_CLASS_HID_237ab] = 1589, - [BNXT_ULP_CLASS_HID_2c2ab] = 1590, - [BNXT_ULP_CLASS_HID_34dab] = 1591, - [BNXT_ULP_CLASS_HID_3d8ab] = 1592, - [BNXT_ULP_CLASS_HID_24afb] = 1593, - [BNXT_ULP_CLASS_HID_2d5fb] = 1594, - [BNXT_ULP_CLASS_HID_303cf] = 1595, - [BNXT_ULP_CLASS_HID_38ecf] = 1596, - [BNXT_ULP_CLASS_HID_255b] = 1597, - [BNXT_ULP_CLASS_HID_2b97] = 1598, - [BNXT_ULP_CLASS_HID_4f0b] = 1599, - [BNXT_ULP_CLASS_HID_1633] = 1600, - [BNXT_ULP_CLASS_HID_39a7] = 1601, - [BNXT_ULP_CLASS_HID_48cf] = 1602, - [BNXT_ULP_CLASS_HID_0ff7] = 1603, - [BNXT_ULP_CLASS_HID_336b] = 1604, - [BNXT_ULP_CLASS_HID_257f7] = 1605, - [BNXT_ULP_CLASS_HID_2858b] = 1606, - [BNXT_ULP_CLASS_HID_3108b] = 1607, - [BNXT_ULP_CLASS_HID_39b8b] = 1608, - [BNXT_ULP_CLASS_HID_24427] = 1609, - [BNXT_ULP_CLASS_HID_2cf27] = 1610, - [BNXT_ULP_CLASS_HID_35a27] = 1611, - [BNXT_ULP_CLASS_HID_388fb] = 1612, - [BNXT_ULP_CLASS_HID_23ffb] = 1613, - [BNXT_ULP_CLASS_HID_2cafb] = 1614, - [BNXT_ULP_CLASS_HID_355fb] = 1615, - [BNXT_ULP_CLASS_HID_3838f] = 1616, - [BNXT_ULP_CLASS_HID_2528b] = 1617, - [BNXT_ULP_CLASS_HID_2815f] = 1618, - [BNXT_ULP_CLASS_HID_30c5f] = 1619, - [BNXT_ULP_CLASS_HID_3975f] = 1620, - [BNXT_ULP_CLASS_HID_21e3f] = 1621, - [BNXT_ULP_CLASS_HID_2a93f] = 1622, - [BNXT_ULP_CLASS_HID_3343f] = 1623, - [BNXT_ULP_CLASS_HID_3bf3f] = 1624, - [BNXT_ULP_CLASS_HID_20b6f] = 1625, - [BNXT_ULP_CLASS_HID_2966f] = 1626, - [BNXT_ULP_CLASS_HID_3216f] = 1627, - [BNXT_ULP_CLASS_HID_3ac6f] = 1628, - [BNXT_ULP_CLASS_HID_20623] = 1629, - [BNXT_ULP_CLASS_HID_29123] = 1630, - [BNXT_ULP_CLASS_HID_31c23] = 1631, - [BNXT_ULP_CLASS_HID_3a723] = 1632, - [BNXT_ULP_CLASS_HID_219f3] = 1633, - [BNXT_ULP_CLASS_HID_2a4f3] = 1634, - [BNXT_ULP_CLASS_HID_32ff3] = 1635, - [BNXT_ULP_CLASS_HID_3baf3] = 1636, - [BNXT_ULP_CLASS_HID_24253] = 1637, - [BNXT_ULP_CLASS_HID_2cd53] = 1638, - [BNXT_ULP_CLASS_HID_35853] = 1639, - [BNXT_ULP_CLASS_HID_38667] = 1640, - [BNXT_ULP_CLASS_HID_22e83] = 1641, - [BNXT_ULP_CLASS_HID_2b983] = 1642, - [BNXT_ULP_CLASS_HID_34483] = 1643, - [BNXT_ULP_CLASS_HID_3cf83] = 1644, - [BNXT_ULP_CLASS_HID_22a57] = 1645, - [BNXT_ULP_CLASS_HID_2b557] = 1646, - [BNXT_ULP_CLASS_HID_34057] = 1647, - [BNXT_ULP_CLASS_HID_3cb57] = 1648, - [BNXT_ULP_CLASS_HID_23d67] = 1649, - [BNXT_ULP_CLASS_HID_2c867] = 1650, - [BNXT_ULP_CLASS_HID_35367] = 1651, - [BNXT_ULP_CLASS_HID_3813b] = 1652, - [BNXT_ULP_CLASS_HID_2089b] = 1653, - [BNXT_ULP_CLASS_HID_2939b] = 1654, - [BNXT_ULP_CLASS_HID_31e9b] = 1655, - [BNXT_ULP_CLASS_HID_3a99b] = 1656, - [BNXT_ULP_CLASS_HID_25237] = 1657, - [BNXT_ULP_CLASS_HID_280cb] = 1658, - [BNXT_ULP_CLASS_HID_30bcb] = 1659, - [BNXT_ULP_CLASS_HID_396cb] = 1660, - [BNXT_ULP_CLASS_HID_24dcb] = 1661, - [BNXT_ULP_CLASS_HID_2d8cb] = 1662, - [BNXT_ULP_CLASS_HID_3069f] = 1663, - [BNXT_ULP_CLASS_HID_3919f] = 1664, - [BNXT_ULP_CLASS_HID_203af] = 1665, - [BNXT_ULP_CLASS_HID_28eaf] = 1666, - [BNXT_ULP_CLASS_HID_319af] = 1667, - [BNXT_ULP_CLASS_HID_3a4af] = 1668, - [BNXT_ULP_CLASS_HID_2513b] = 1669, - [BNXT_ULP_CLASS_HID_2dc3b] = 1670, - [BNXT_ULP_CLASS_HID_30acf] = 1671, - [BNXT_ULP_CLASS_HID_395cf] = 1672, - [BNXT_ULP_CLASS_HID_23e6b] = 1673, - [BNXT_ULP_CLASS_HID_2c96b] = 1674, - [BNXT_ULP_CLASS_HID_3546b] = 1675, - [BNXT_ULP_CLASS_HID_3823f] = 1676, - [BNXT_ULP_CLASS_HID_2393f] = 1677, - [BNXT_ULP_CLASS_HID_2c43f] = 1678, - [BNXT_ULP_CLASS_HID_34f3f] = 1679, - [BNXT_ULP_CLASS_HID_3da3f] = 1680, - [BNXT_ULP_CLASS_HID_24ccf] = 1681, - [BNXT_ULP_CLASS_HID_2d7cf] = 1682, - [BNXT_ULP_CLASS_HID_30583] = 1683, - [BNXT_ULP_CLASS_HID_39083] = 1684, - [BNXT_ULP_CLASS_HID_21863] = 1685, - [BNXT_ULP_CLASS_HID_2a363] = 1686, - [BNXT_ULP_CLASS_HID_32e63] = 1687, - [BNXT_ULP_CLASS_HID_3b963] = 1688, - [BNXT_ULP_CLASS_HID_20553] = 1689, - [BNXT_ULP_CLASS_HID_29053] = 1690, - [BNXT_ULP_CLASS_HID_31b53] = 1691, - [BNXT_ULP_CLASS_HID_3a653] = 1692, - [BNXT_ULP_CLASS_HID_20067] = 1693, - [BNXT_ULP_CLASS_HID_28b67] = 1694, - [BNXT_ULP_CLASS_HID_31667] = 1695, - [BNXT_ULP_CLASS_HID_3a167] = 1696, - [BNXT_ULP_CLASS_HID_21337] = 1697, - [BNXT_ULP_CLASS_HID_29e37] = 1698, - [BNXT_ULP_CLASS_HID_32937] = 1699, - [BNXT_ULP_CLASS_HID_3b437] = 1700, - [BNXT_ULP_CLASS_HID_23b97] = 1701, - [BNXT_ULP_CLASS_HID_2c697] = 1702, - [BNXT_ULP_CLASS_HID_35197] = 1703, - [BNXT_ULP_CLASS_HID_3dc97] = 1704, - [BNXT_ULP_CLASS_HID_228c7] = 1705, - [BNXT_ULP_CLASS_HID_2b3c7] = 1706, - [BNXT_ULP_CLASS_HID_33ec7] = 1707, - [BNXT_ULP_CLASS_HID_3c9c7] = 1708, - [BNXT_ULP_CLASS_HID_2239b] = 1709, - [BNXT_ULP_CLASS_HID_2ae9b] = 1710, - [BNXT_ULP_CLASS_HID_3399b] = 1711, - [BNXT_ULP_CLASS_HID_3c49b] = 1712, - [BNXT_ULP_CLASS_HID_236ab] = 1713, - [BNXT_ULP_CLASS_HID_2c1ab] = 1714, - [BNXT_ULP_CLASS_HID_34cab] = 1715, - [BNXT_ULP_CLASS_HID_3d7ab] = 1716, - [BNXT_ULP_CLASS_HID_202df] = 1717, - [BNXT_ULP_CLASS_HID_28ddf] = 1718, - [BNXT_ULP_CLASS_HID_318df] = 1719, - [BNXT_ULP_CLASS_HID_3a3df] = 1720, - [BNXT_ULP_CLASS_HID_24c7b] = 1721, - [BNXT_ULP_CLASS_HID_2d77b] = 1722, - [BNXT_ULP_CLASS_HID_3050f] = 1723, - [BNXT_ULP_CLASS_HID_3900f] = 1724, - [BNXT_ULP_CLASS_HID_2470f] = 1725, - [BNXT_ULP_CLASS_HID_2d20f] = 1726, - [BNXT_ULP_CLASS_HID_300c3] = 1727, - [BNXT_ULP_CLASS_HID_38bc3] = 1728, - [BNXT_ULP_CLASS_HID_25adf] = 1729, - [BNXT_ULP_CLASS_HID_28893] = 1730, - [BNXT_ULP_CLASS_HID_31393] = 1731, - [BNXT_ULP_CLASS_HID_39e93] = 1732, - [BNXT_ULP_CLASS_HID_24b7f] = 1733, - [BNXT_ULP_CLASS_HID_2d67f] = 1734, - [BNXT_ULP_CLASS_HID_30433] = 1735, - [BNXT_ULP_CLASS_HID_38f33] = 1736, - [BNXT_ULP_CLASS_HID_237af] = 1737, - [BNXT_ULP_CLASS_HID_2c2af] = 1738, - [BNXT_ULP_CLASS_HID_34daf] = 1739, - [BNXT_ULP_CLASS_HID_3d8af] = 1740, - [BNXT_ULP_CLASS_HID_23363] = 1741, - [BNXT_ULP_CLASS_HID_2be63] = 1742, - [BNXT_ULP_CLASS_HID_34963] = 1743, - [BNXT_ULP_CLASS_HID_3d463] = 1744, - [BNXT_ULP_CLASS_HID_24633] = 1745, - [BNXT_ULP_CLASS_HID_2d133] = 1746, - [BNXT_ULP_CLASS_HID_35c33] = 1747, - [BNXT_ULP_CLASS_HID_38ac7] = 1748, - [BNXT_ULP_CLASS_HID_211a7] = 1749, - [BNXT_ULP_CLASS_HID_29ca7] = 1750, - [BNXT_ULP_CLASS_HID_327a7] = 1751, - [BNXT_ULP_CLASS_HID_3b2a7] = 1752, - [BNXT_ULP_CLASS_HID_25bc3] = 1753, - [BNXT_ULP_CLASS_HID_28997] = 1754, - [BNXT_ULP_CLASS_HID_31497] = 1755, - [BNXT_ULP_CLASS_HID_39f97] = 1756, - [BNXT_ULP_CLASS_HID_25697] = 1757, - [BNXT_ULP_CLASS_HID_284ab] = 1758, - [BNXT_ULP_CLASS_HID_30fab] = 1759, - [BNXT_ULP_CLASS_HID_39aab] = 1760, - [BNXT_ULP_CLASS_HID_20d7b] = 1761, - [BNXT_ULP_CLASS_HID_2987b] = 1762, - [BNXT_ULP_CLASS_HID_3237b] = 1763, - [BNXT_ULP_CLASS_HID_3ae7b] = 1764, - [BNXT_ULP_CLASS_HID_235db] = 1765, - [BNXT_ULP_CLASS_HID_2c0db] = 1766, - [BNXT_ULP_CLASS_HID_34bdb] = 1767, - [BNXT_ULP_CLASS_HID_3d6db] = 1768, - [BNXT_ULP_CLASS_HID_2220b] = 1769, - [BNXT_ULP_CLASS_HID_2ad0b] = 1770, - [BNXT_ULP_CLASS_HID_3380b] = 1771, - [BNXT_ULP_CLASS_HID_3c30b] = 1772, - [BNXT_ULP_CLASS_HID_21ddf] = 1773, - [BNXT_ULP_CLASS_HID_2a8df] = 1774, - [BNXT_ULP_CLASS_HID_333df] = 1775, - [BNXT_ULP_CLASS_HID_3bedf] = 1776, - [BNXT_ULP_CLASS_HID_230ef] = 1777, - [BNXT_ULP_CLASS_HID_2bbef] = 1778, - [BNXT_ULP_CLASS_HID_346ef] = 1779, - [BNXT_ULP_CLASS_HID_3d1ef] = 1780, - [BNXT_ULP_CLASS_HID_2594f] = 1781, - [BNXT_ULP_CLASS_HID_28703] = 1782, - [BNXT_ULP_CLASS_HID_31203] = 1783, - [BNXT_ULP_CLASS_HID_39d03] = 1784, - [BNXT_ULP_CLASS_HID_245bf] = 1785, - [BNXT_ULP_CLASS_HID_2d0bf] = 1786, - [BNXT_ULP_CLASS_HID_35bbf] = 1787, - [BNXT_ULP_CLASS_HID_38a73] = 1788, - [BNXT_ULP_CLASS_HID_24173] = 1789, - [BNXT_ULP_CLASS_HID_2cc73] = 1790, - [BNXT_ULP_CLASS_HID_35773] = 1791, - [BNXT_ULP_CLASS_HID_38507] = 1792, - [BNXT_ULP_CLASS_HID_25403] = 1793, - [BNXT_ULP_CLASS_HID_282d7] = 1794, - [BNXT_ULP_CLASS_HID_30dd7] = 1795, - [BNXT_ULP_CLASS_HID_398d7] = 1796, - [BNXT_ULP_CLASS_HID_244a3] = 1797, - [BNXT_ULP_CLASS_HID_2cfa3] = 1798, - [BNXT_ULP_CLASS_HID_35aa3] = 1799, - [BNXT_ULP_CLASS_HID_38977] = 1800, - [BNXT_ULP_CLASS_HID_23193] = 1801, - [BNXT_ULP_CLASS_HID_2bc93] = 1802, - [BNXT_ULP_CLASS_HID_34793] = 1803, - [BNXT_ULP_CLASS_HID_3d293] = 1804, - [BNXT_ULP_CLASS_HID_22ca7] = 1805, - [BNXT_ULP_CLASS_HID_2b7a7] = 1806, - [BNXT_ULP_CLASS_HID_342a7] = 1807, - [BNXT_ULP_CLASS_HID_3cda7] = 1808, - [BNXT_ULP_CLASS_HID_24077] = 1809, - [BNXT_ULP_CLASS_HID_2cb77] = 1810, - [BNXT_ULP_CLASS_HID_35677] = 1811, - [BNXT_ULP_CLASS_HID_3840b] = 1812, - [BNXT_ULP_CLASS_HID_20beb] = 1813, - [BNXT_ULP_CLASS_HID_296eb] = 1814, - [BNXT_ULP_CLASS_HID_321eb] = 1815, - [BNXT_ULP_CLASS_HID_3aceb] = 1816, - [BNXT_ULP_CLASS_HID_25507] = 1817, - [BNXT_ULP_CLASS_HID_283db] = 1818, - [BNXT_ULP_CLASS_HID_30edb] = 1819, - [BNXT_ULP_CLASS_HID_399db] = 1820, - [BNXT_ULP_CLASS_HID_250db] = 1821, - [BNXT_ULP_CLASS_HID_2dbdb] = 1822, - [BNXT_ULP_CLASS_HID_309ef] = 1823, - [BNXT_ULP_CLASS_HID_394ef] = 1824, - [BNXT_ULP_CLASS_HID_206bf] = 1825, - [BNXT_ULP_CLASS_HID_291bf] = 1826, - [BNXT_ULP_CLASS_HID_31cbf] = 1827, - [BNXT_ULP_CLASS_HID_3a7bf] = 1828, - [BNXT_ULP_CLASS_HID_22f1f] = 1829, - [BNXT_ULP_CLASS_HID_2ba1f] = 1830, - [BNXT_ULP_CLASS_HID_3451f] = 1831, - [BNXT_ULP_CLASS_HID_3d01f] = 1832, - [BNXT_ULP_CLASS_HID_21c4f] = 1833, - [BNXT_ULP_CLASS_HID_2a74f] = 1834, - [BNXT_ULP_CLASS_HID_3324f] = 1835, - [BNXT_ULP_CLASS_HID_3bd4f] = 1836, - [BNXT_ULP_CLASS_HID_21703] = 1837, - [BNXT_ULP_CLASS_HID_2a203] = 1838, - [BNXT_ULP_CLASS_HID_32d03] = 1839, - [BNXT_ULP_CLASS_HID_3b803] = 1840, - [BNXT_ULP_CLASS_HID_22ad3] = 1841, - [BNXT_ULP_CLASS_HID_2b5d3] = 1842, - [BNXT_ULP_CLASS_HID_340d3] = 1843, - [BNXT_ULP_CLASS_HID_3cbd3] = 1844, - [BNXT_ULP_CLASS_HID_252b3] = 1845, - [BNXT_ULP_CLASS_HID_28147] = 1846, - [BNXT_ULP_CLASS_HID_30c47] = 1847, - [BNXT_ULP_CLASS_HID_39747] = 1848, - [BNXT_ULP_CLASS_HID_23fe3] = 1849, - [BNXT_ULP_CLASS_HID_2cae3] = 1850, - [BNXT_ULP_CLASS_HID_355e3] = 1851, - [BNXT_ULP_CLASS_HID_383b7] = 1852, - [BNXT_ULP_CLASS_HID_23ab7] = 1853, - [BNXT_ULP_CLASS_HID_2c5b7] = 1854, - [BNXT_ULP_CLASS_HID_350b7] = 1855, - [BNXT_ULP_CLASS_HID_3dbb7] = 1856, - [BNXT_ULP_CLASS_HID_24e47] = 1857, - [BNXT_ULP_CLASS_HID_2d947] = 1858, - [BNXT_ULP_CLASS_HID_3071b] = 1859, - [BNXT_ULP_CLASS_HID_3921b] = 1860, - [BNXT_ULP_CLASS_HID_2326f] = 1861, - [BNXT_ULP_CLASS_HID_2bd6f] = 1862, - [BNXT_ULP_CLASS_HID_3486f] = 1863, - [BNXT_ULP_CLASS_HID_3d36f] = 1864, - [BNXT_ULP_CLASS_HID_21f5f] = 1865, - [BNXT_ULP_CLASS_HID_2aa5f] = 1866, - [BNXT_ULP_CLASS_HID_3355f] = 1867, - [BNXT_ULP_CLASS_HID_3c05f] = 1868, - [BNXT_ULP_CLASS_HID_21a13] = 1869, - [BNXT_ULP_CLASS_HID_2a513] = 1870, - [BNXT_ULP_CLASS_HID_33013] = 1871, - [BNXT_ULP_CLASS_HID_3bb13] = 1872, - [BNXT_ULP_CLASS_HID_22d23] = 1873, - [BNXT_ULP_CLASS_HID_2b823] = 1874, - [BNXT_ULP_CLASS_HID_34323] = 1875, - [BNXT_ULP_CLASS_HID_3ce23] = 1876, - [BNXT_ULP_CLASS_HID_25583] = 1877, - [BNXT_ULP_CLASS_HID_28457] = 1878, - [BNXT_ULP_CLASS_HID_30f57] = 1879, - [BNXT_ULP_CLASS_HID_39a57] = 1880, - [BNXT_ULP_CLASS_HID_242f3] = 1881, - [BNXT_ULP_CLASS_HID_2cdf3] = 1882, - [BNXT_ULP_CLASS_HID_358f3] = 1883, - [BNXT_ULP_CLASS_HID_38687] = 1884, - [BNXT_ULP_CLASS_HID_23d87] = 1885, - [BNXT_ULP_CLASS_HID_2c887] = 1886, - [BNXT_ULP_CLASS_HID_35387] = 1887, - [BNXT_ULP_CLASS_HID_3825b] = 1888, - [BNXT_ULP_CLASS_HID_25157] = 1889, - [BNXT_ULP_CLASS_HID_2dc57] = 1890, - [BNXT_ULP_CLASS_HID_30a6b] = 1891, - [BNXT_ULP_CLASS_HID_3956b] = 1892, - [BNXT_ULP_CLASS_HID_22c53] = 1893, - [BNXT_ULP_CLASS_HID_2b753] = 1894, - [BNXT_ULP_CLASS_HID_34253] = 1895, - [BNXT_ULP_CLASS_HID_3cd53] = 1896, - [BNXT_ULP_CLASS_HID_21883] = 1897, - [BNXT_ULP_CLASS_HID_2a383] = 1898, - [BNXT_ULP_CLASS_HID_32e83] = 1899, - [BNXT_ULP_CLASS_HID_3b983] = 1900, - [BNXT_ULP_CLASS_HID_21457] = 1901, - [BNXT_ULP_CLASS_HID_29f57] = 1902, - [BNXT_ULP_CLASS_HID_32a57] = 1903, - [BNXT_ULP_CLASS_HID_3b557] = 1904, - [BNXT_ULP_CLASS_HID_22767] = 1905, - [BNXT_ULP_CLASS_HID_2b267] = 1906, - [BNXT_ULP_CLASS_HID_33d67] = 1907, - [BNXT_ULP_CLASS_HID_3c867] = 1908, - [BNXT_ULP_CLASS_HID_24fc7] = 1909, - [BNXT_ULP_CLASS_HID_2dac7] = 1910, - [BNXT_ULP_CLASS_HID_3089b] = 1911, - [BNXT_ULP_CLASS_HID_3939b] = 1912, - [BNXT_ULP_CLASS_HID_23c37] = 1913, - [BNXT_ULP_CLASS_HID_2c737] = 1914, - [BNXT_ULP_CLASS_HID_35237] = 1915, - [BNXT_ULP_CLASS_HID_380cb] = 1916, - [BNXT_ULP_CLASS_HID_237cb] = 1917, - [BNXT_ULP_CLASS_HID_2c2cb] = 1918, - [BNXT_ULP_CLASS_HID_34dcb] = 1919, - [BNXT_ULP_CLASS_HID_3d8cb] = 1920, - [BNXT_ULP_CLASS_HID_24a9b] = 1921, - [BNXT_ULP_CLASS_HID_2d59b] = 1922, - [BNXT_ULP_CLASS_HID_303af] = 1923, - [BNXT_ULP_CLASS_HID_38eaf] = 1924, - [BNXT_ULP_CLASS_HID_253b] = 1925, - [BNXT_ULP_CLASS_HID_2bf7] = 1926, - [BNXT_ULP_CLASS_HID_4f6b] = 1927, - [BNXT_ULP_CLASS_HID_1653] = 1928, - [BNXT_ULP_CLASS_HID_39c7] = 1929, - [BNXT_ULP_CLASS_HID_48af] = 1930, - [BNXT_ULP_CLASS_HID_0f97] = 1931, - [BNXT_ULP_CLASS_HID_330b] = 1932, - [BNXT_ULP_CLASS_HID_374e] = 1933, - [BNXT_ULP_CLASS_HID_11ee] = 1934, - [BNXT_ULP_CLASS_HID_423a] = 1935, - [BNXT_ULP_CLASS_HID_0cd6] = 1936, - [BNXT_ULP_CLASS_HID_310a] = 1937, - [BNXT_ULP_CLASS_HID_469e] = 1938, - [BNXT_ULP_CLASS_HID_5ce6] = 1939, - [BNXT_ULP_CLASS_HID_0692] = 1940, - [BNXT_ULP_CLASS_HID_1c7e] = 1941, - [BNXT_ULP_CLASS_HID_55c2] = 1942, - [BNXT_ULP_CLASS_HID_2b2a] = 1943, - [BNXT_ULP_CLASS_HID_15c6] = 1944, - [BNXT_ULP_CLASS_HID_163a] = 1945, - [BNXT_ULP_CLASS_HID_2f8e] = 1946, - [BNXT_ULP_CLASS_HID_2516] = 1947, - [BNXT_ULP_CLASS_HID_4b76] = 1948, - [BNXT_ULP_CLASS_HID_10e6] = 1949, - [BNXT_ULP_CLASS_HID_264a] = 1950, - [BNXT_ULP_CLASS_HID_3fd2] = 1951, - [BNXT_ULP_CLASS_HID_4532] = 1952, - [BNXT_ULP_CLASS_HID_4996] = 1953, - [BNXT_ULP_CLASS_HID_2036] = 1954, - [BNXT_ULP_CLASS_HID_399e] = 1955, - [BNXT_ULP_CLASS_HID_5ffe] = 1956, - [BNXT_ULP_CLASS_HID_34fe] = 1957, - [BNXT_ULP_CLASS_HID_3a32] = 1958, - [BNXT_ULP_CLASS_HID_376e] = 1959, - [BNXT_ULP_CLASS_HID_12d6e] = 1960, - [BNXT_ULP_CLASS_HID_2436e] = 1961, - [BNXT_ULP_CLASS_HID_31dba] = 1962, - [BNXT_ULP_CLASS_HID_11ce] = 1963, - [BNXT_ULP_CLASS_HID_107ce] = 1964, - [BNXT_ULP_CLASS_HID_23dce] = 1965, - [BNXT_ULP_CLASS_HID_353ce] = 1966, - [BNXT_ULP_CLASS_HID_421a] = 1967, - [BNXT_ULP_CLASS_HID_11d56] = 1968, - [BNXT_ULP_CLASS_HID_23356] = 1969, - [BNXT_ULP_CLASS_HID_32956] = 1970, - [BNXT_ULP_CLASS_HID_0cf6] = 1971, - [BNXT_ULP_CLASS_HID_122f6] = 1972, - [BNXT_ULP_CLASS_HID_258f6] = 1973, - [BNXT_ULP_CLASS_HID_313c2] = 1974, - [BNXT_ULP_CLASS_HID_312a] = 1975, - [BNXT_ULP_CLASS_HID_1272a] = 1976, - [BNXT_ULP_CLASS_HID_25d2a] = 1977, - [BNXT_ULP_CLASS_HID_31466] = 1978, - [BNXT_ULP_CLASS_HID_46be] = 1979, - [BNXT_ULP_CLASS_HID_1018a] = 1980, - [BNXT_ULP_CLASS_HID_2378a] = 1981, - [BNXT_ULP_CLASS_HID_32d8a] = 1982, - [BNXT_ULP_CLASS_HID_5cc6] = 1983, - [BNXT_ULP_CLASS_HID_11712] = 1984, - [BNXT_ULP_CLASS_HID_20d12] = 1985, - [BNXT_ULP_CLASS_HID_32312] = 1986, - [BNXT_ULP_CLASS_HID_06b2] = 1987, - [BNXT_ULP_CLASS_HID_13cb2] = 1988, - [BNXT_ULP_CLASS_HID_252b2] = 1989, - [BNXT_ULP_CLASS_HID_348b2] = 1990, - [BNXT_ULP_CLASS_HID_1c5e] = 1991, - [BNXT_ULP_CLASS_HID_1325e] = 1992, - [BNXT_ULP_CLASS_HID_2285e] = 1993, - [BNXT_ULP_CLASS_HID_35e5e] = 1994, - [BNXT_ULP_CLASS_HID_55e2] = 1995, - [BNXT_ULP_CLASS_HID_14be2] = 1996, - [BNXT_ULP_CLASS_HID_2023e] = 1997, - [BNXT_ULP_CLASS_HID_3383e] = 1998, - [BNXT_ULP_CLASS_HID_2b0a] = 1999, - [BNXT_ULP_CLASS_HID_1410a] = 2000, - [BNXT_ULP_CLASS_HID_21846] = 2001, - [BNXT_ULP_CLASS_HID_30e46] = 2002, - [BNXT_ULP_CLASS_HID_15e6] = 2003, - [BNXT_ULP_CLASS_HID_10be6] = 2004, - [BNXT_ULP_CLASS_HID_221e6] = 2005, - [BNXT_ULP_CLASS_HID_357e6] = 2006, - [BNXT_ULP_CLASS_HID_161a] = 2007, - [BNXT_ULP_CLASS_HID_10c1a] = 2008, - [BNXT_ULP_CLASS_HID_2221a] = 2009, - [BNXT_ULP_CLASS_HID_3581a] = 2010, - [BNXT_ULP_CLASS_HID_2fae] = 2011, - [BNXT_ULP_CLASS_HID_145ae] = 2012, - [BNXT_ULP_CLASS_HID_21cfa] = 2013, - [BNXT_ULP_CLASS_HID_332fa] = 2014, - [BNXT_ULP_CLASS_HID_2536] = 2015, - [BNXT_ULP_CLASS_HID_15b36] = 2016, - [BNXT_ULP_CLASS_HID_21202] = 2017, - [BNXT_ULP_CLASS_HID_30802] = 2018, - [BNXT_ULP_CLASS_HID_4b56] = 2019, - [BNXT_ULP_CLASS_HID_105a2] = 2020, - [BNXT_ULP_CLASS_HID_23ba2] = 2021, - [BNXT_ULP_CLASS_HID_351a2] = 2022, - [BNXT_ULP_CLASS_HID_10c6] = 2023, - [BNXT_ULP_CLASS_HID_106c6] = 2024, - [BNXT_ULP_CLASS_HID_23cc6] = 2025, - [BNXT_ULP_CLASS_HID_352c6] = 2026, - [BNXT_ULP_CLASS_HID_266a] = 2027, - [BNXT_ULP_CLASS_HID_15c6a] = 2028, - [BNXT_ULP_CLASS_HID_216a6] = 2029, - [BNXT_ULP_CLASS_HID_30ca6] = 2030, - [BNXT_ULP_CLASS_HID_3ff2] = 2031, - [BNXT_ULP_CLASS_HID_155f2] = 2032, - [BNXT_ULP_CLASS_HID_24bf2] = 2033, - [BNXT_ULP_CLASS_HID_302ce] = 2034, - [BNXT_ULP_CLASS_HID_4512] = 2035, - [BNXT_ULP_CLASS_HID_11c6e] = 2036, - [BNXT_ULP_CLASS_HID_2326e] = 2037, - [BNXT_ULP_CLASS_HID_3286e] = 2038, - [BNXT_ULP_CLASS_HID_49b6] = 2039, - [BNXT_ULP_CLASS_HID_10082] = 2040, - [BNXT_ULP_CLASS_HID_23682] = 2041, - [BNXT_ULP_CLASS_HID_32c82] = 2042, - [BNXT_ULP_CLASS_HID_2016] = 2043, - [BNXT_ULP_CLASS_HID_15616] = 2044, - [BNXT_ULP_CLASS_HID_21162] = 2045, - [BNXT_ULP_CLASS_HID_30762] = 2046, - [BNXT_ULP_CLASS_HID_39be] = 2047, - [BNXT_ULP_CLASS_HID_12fbe] = 2048, - [BNXT_ULP_CLASS_HID_245be] = 2049, - [BNXT_ULP_CLASS_HID_31c8a] = 2050, - [BNXT_ULP_CLASS_HID_5fde] = 2051, - [BNXT_ULP_CLASS_HID_1162a] = 2052, - [BNXT_ULP_CLASS_HID_20c2a] = 2053, - [BNXT_ULP_CLASS_HID_3222a] = 2054, - [BNXT_ULP_CLASS_HID_34de] = 2055, - [BNXT_ULP_CLASS_HID_3a12] = 2056, - [BNXT_ULP_CLASS_HID_370e] = 2057, - [BNXT_ULP_CLASS_HID_12d0e] = 2058, - [BNXT_ULP_CLASS_HID_2430e] = 2059, - [BNXT_ULP_CLASS_HID_31dda] = 2060, - [BNXT_ULP_CLASS_HID_11ae] = 2061, - [BNXT_ULP_CLASS_HID_107ae] = 2062, - [BNXT_ULP_CLASS_HID_23dae] = 2063, - [BNXT_ULP_CLASS_HID_353ae] = 2064, - [BNXT_ULP_CLASS_HID_427a] = 2065, - [BNXT_ULP_CLASS_HID_11d36] = 2066, - [BNXT_ULP_CLASS_HID_23336] = 2067, - [BNXT_ULP_CLASS_HID_32936] = 2068, - [BNXT_ULP_CLASS_HID_0c96] = 2069, - [BNXT_ULP_CLASS_HID_12296] = 2070, - [BNXT_ULP_CLASS_HID_25896] = 2071, - [BNXT_ULP_CLASS_HID_313a2] = 2072, - [BNXT_ULP_CLASS_HID_314a] = 2073, - [BNXT_ULP_CLASS_HID_1274a] = 2074, - [BNXT_ULP_CLASS_HID_25d4a] = 2075, - [BNXT_ULP_CLASS_HID_31406] = 2076, - [BNXT_ULP_CLASS_HID_46de] = 2077, - [BNXT_ULP_CLASS_HID_101ea] = 2078, - [BNXT_ULP_CLASS_HID_237ea] = 2079, - [BNXT_ULP_CLASS_HID_32dea] = 2080, - [BNXT_ULP_CLASS_HID_5ca6] = 2081, - [BNXT_ULP_CLASS_HID_11772] = 2082, - [BNXT_ULP_CLASS_HID_20d72] = 2083, - [BNXT_ULP_CLASS_HID_32372] = 2084, - [BNXT_ULP_CLASS_HID_06d2] = 2085, - [BNXT_ULP_CLASS_HID_13cd2] = 2086, - [BNXT_ULP_CLASS_HID_252d2] = 2087, - [BNXT_ULP_CLASS_HID_348d2] = 2088, - [BNXT_ULP_CLASS_HID_1c3e] = 2089, - [BNXT_ULP_CLASS_HID_1323e] = 2090, - [BNXT_ULP_CLASS_HID_2283e] = 2091, - [BNXT_ULP_CLASS_HID_35e3e] = 2092, - [BNXT_ULP_CLASS_HID_5582] = 2093, - [BNXT_ULP_CLASS_HID_14b82] = 2094, - [BNXT_ULP_CLASS_HID_2025e] = 2095, - [BNXT_ULP_CLASS_HID_3385e] = 2096, - [BNXT_ULP_CLASS_HID_2b6a] = 2097, - [BNXT_ULP_CLASS_HID_1416a] = 2098, - [BNXT_ULP_CLASS_HID_21826] = 2099, - [BNXT_ULP_CLASS_HID_30e26] = 2100, - [BNXT_ULP_CLASS_HID_1586] = 2101, - [BNXT_ULP_CLASS_HID_10b86] = 2102, - [BNXT_ULP_CLASS_HID_22186] = 2103, - [BNXT_ULP_CLASS_HID_35786] = 2104, - [BNXT_ULP_CLASS_HID_167a] = 2105, - [BNXT_ULP_CLASS_HID_10c7a] = 2106, - [BNXT_ULP_CLASS_HID_2227a] = 2107, - [BNXT_ULP_CLASS_HID_3587a] = 2108, - [BNXT_ULP_CLASS_HID_2fce] = 2109, - [BNXT_ULP_CLASS_HID_145ce] = 2110, - [BNXT_ULP_CLASS_HID_21c9a] = 2111, - [BNXT_ULP_CLASS_HID_3329a] = 2112, - [BNXT_ULP_CLASS_HID_2556] = 2113, - [BNXT_ULP_CLASS_HID_15b56] = 2114, - [BNXT_ULP_CLASS_HID_21262] = 2115, - [BNXT_ULP_CLASS_HID_30862] = 2116, - [BNXT_ULP_CLASS_HID_4b36] = 2117, - [BNXT_ULP_CLASS_HID_105c2] = 2118, - [BNXT_ULP_CLASS_HID_23bc2] = 2119, - [BNXT_ULP_CLASS_HID_351c2] = 2120, - [BNXT_ULP_CLASS_HID_10a6] = 2121, - [BNXT_ULP_CLASS_HID_106a6] = 2122, - [BNXT_ULP_CLASS_HID_23ca6] = 2123, - [BNXT_ULP_CLASS_HID_352a6] = 2124, - [BNXT_ULP_CLASS_HID_260a] = 2125, - [BNXT_ULP_CLASS_HID_15c0a] = 2126, - [BNXT_ULP_CLASS_HID_216c6] = 2127, - [BNXT_ULP_CLASS_HID_30cc6] = 2128, - [BNXT_ULP_CLASS_HID_3f92] = 2129, - [BNXT_ULP_CLASS_HID_15592] = 2130, - [BNXT_ULP_CLASS_HID_24b92] = 2131, - [BNXT_ULP_CLASS_HID_302ae] = 2132, - [BNXT_ULP_CLASS_HID_4572] = 2133, - [BNXT_ULP_CLASS_HID_11c0e] = 2134, - [BNXT_ULP_CLASS_HID_2320e] = 2135, - [BNXT_ULP_CLASS_HID_3280e] = 2136, - [BNXT_ULP_CLASS_HID_49d6] = 2137, - [BNXT_ULP_CLASS_HID_100e2] = 2138, - [BNXT_ULP_CLASS_HID_236e2] = 2139, - [BNXT_ULP_CLASS_HID_32ce2] = 2140, - [BNXT_ULP_CLASS_HID_2076] = 2141, - [BNXT_ULP_CLASS_HID_15676] = 2142, - [BNXT_ULP_CLASS_HID_21102] = 2143, - [BNXT_ULP_CLASS_HID_30702] = 2144, - [BNXT_ULP_CLASS_HID_39de] = 2145, - [BNXT_ULP_CLASS_HID_12fde] = 2146, - [BNXT_ULP_CLASS_HID_245de] = 2147, - [BNXT_ULP_CLASS_HID_31cea] = 2148, - [BNXT_ULP_CLASS_HID_5fbe] = 2149, - [BNXT_ULP_CLASS_HID_1164a] = 2150, - [BNXT_ULP_CLASS_HID_20c4a] = 2151, - [BNXT_ULP_CLASS_HID_3224a] = 2152, - [BNXT_ULP_CLASS_HID_34be] = 2153, - [BNXT_ULP_CLASS_HID_3a72] = 2154, - [BNXT_ULP_CLASS_HID_09ea] = 2155, - [BNXT_ULP_CLASS_HID_2912] = 2156, - [BNXT_ULP_CLASS_HID_03b2] = 2157, - [BNXT_ULP_CLASS_HID_5f7e] = 2158, - [BNXT_ULP_CLASS_HID_03a6] = 2159, - [BNXT_ULP_CLASS_HID_23ce] = 2160, - [BNXT_ULP_CLASS_HID_1a6e] = 2161, - [BNXT_ULP_CLASS_HID_593a] = 2162, - [BNXT_ULP_CLASS_HID_4dce] = 2163, - [BNXT_ULP_CLASS_HID_0e02] = 2164, - [BNXT_ULP_CLASS_HID_4796] = 2165, - [BNXT_ULP_CLASS_HID_246e] = 2166, - [BNXT_ULP_CLASS_HID_478a] = 2167, - [BNXT_ULP_CLASS_HID_08fe] = 2168, - [BNXT_ULP_CLASS_HID_5e52] = 2169, - [BNXT_ULP_CLASS_HID_3e2a] = 2170, - [BNXT_ULP_CLASS_HID_5e46] = 2171, - [BNXT_ULP_CLASS_HID_02ba] = 2172, - [BNXT_ULP_CLASS_HID_580e] = 2173, - [BNXT_ULP_CLASS_HID_38e6] = 2174, - [BNXT_ULP_CLASS_HID_5802] = 2175, - [BNXT_ULP_CLASS_HID_1d76] = 2176, - [BNXT_ULP_CLASS_HID_52ca] = 2177, - [BNXT_ULP_CLASS_HID_32a2] = 2178, - [BNXT_ULP_CLASS_HID_34f6] = 2179, - [BNXT_ULP_CLASS_HID_3a3a] = 2180, - [BNXT_ULP_CLASS_HID_09ca] = 2181, - [BNXT_ULP_CLASS_HID_0216] = 2182, - [BNXT_ULP_CLASS_HID_1f62] = 2183, - [BNXT_ULP_CLASS_HID_1bae] = 2184, - [BNXT_ULP_CLASS_HID_2932] = 2185, - [BNXT_ULP_CLASS_HID_227e] = 2186, - [BNXT_ULP_CLASS_HID_3f4a] = 2187, - [BNXT_ULP_CLASS_HID_3b96] = 2188, - [BNXT_ULP_CLASS_HID_0392] = 2189, - [BNXT_ULP_CLASS_HID_1cde] = 2190, - [BNXT_ULP_CLASS_HID_192a] = 2191, - [BNXT_ULP_CLASS_HID_1276] = 2192, - [BNXT_ULP_CLASS_HID_5f5e] = 2193, - [BNXT_ULP_CLASS_HID_5baa] = 2194, - [BNXT_ULP_CLASS_HID_54f6] = 2195, - [BNXT_ULP_CLASS_HID_51c2] = 2196, - [BNXT_ULP_CLASS_HID_0386] = 2197, - [BNXT_ULP_CLASS_HID_1cd2] = 2198, - [BNXT_ULP_CLASS_HID_191e] = 2199, - [BNXT_ULP_CLASS_HID_126a] = 2200, - [BNXT_ULP_CLASS_HID_23ee] = 2201, - [BNXT_ULP_CLASS_HID_3c3a] = 2202, - [BNXT_ULP_CLASS_HID_3906] = 2203, - [BNXT_ULP_CLASS_HID_3252] = 2204, - [BNXT_ULP_CLASS_HID_1a4e] = 2205, - [BNXT_ULP_CLASS_HID_169a] = 2206, - [BNXT_ULP_CLASS_HID_13e6] = 2207, - [BNXT_ULP_CLASS_HID_4be6] = 2208, - [BNXT_ULP_CLASS_HID_591a] = 2209, - [BNXT_ULP_CLASS_HID_5266] = 2210, - [BNXT_ULP_CLASS_HID_2eb2] = 2211, - [BNXT_ULP_CLASS_HID_2bfe] = 2212, - [BNXT_ULP_CLASS_HID_4dee] = 2213, - [BNXT_ULP_CLASS_HID_463a] = 2214, - [BNXT_ULP_CLASS_HID_4306] = 2215, - [BNXT_ULP_CLASS_HID_5c52] = 2216, - [BNXT_ULP_CLASS_HID_0e22] = 2217, - [BNXT_ULP_CLASS_HID_0b6e] = 2218, - [BNXT_ULP_CLASS_HID_07ba] = 2219, - [BNXT_ULP_CLASS_HID_0086] = 2220, - [BNXT_ULP_CLASS_HID_47b6] = 2221, - [BNXT_ULP_CLASS_HID_4082] = 2222, - [BNXT_ULP_CLASS_HID_5dce] = 2223, - [BNXT_ULP_CLASS_HID_561a] = 2224, - [BNXT_ULP_CLASS_HID_244e] = 2225, - [BNXT_ULP_CLASS_HID_209a] = 2226, - [BNXT_ULP_CLASS_HID_3de6] = 2227, - [BNXT_ULP_CLASS_HID_3632] = 2228, - [BNXT_ULP_CLASS_HID_47aa] = 2229, - [BNXT_ULP_CLASS_HID_40f6] = 2230, - [BNXT_ULP_CLASS_HID_5dc2] = 2231, - [BNXT_ULP_CLASS_HID_560e] = 2232, - [BNXT_ULP_CLASS_HID_08de] = 2233, - [BNXT_ULP_CLASS_HID_052a] = 2234, - [BNXT_ULP_CLASS_HID_1e76] = 2235, - [BNXT_ULP_CLASS_HID_1b42] = 2236, - [BNXT_ULP_CLASS_HID_5e72] = 2237, - [BNXT_ULP_CLASS_HID_5abe] = 2238, - [BNXT_ULP_CLASS_HID_578a] = 2239, - [BNXT_ULP_CLASS_HID_50d6] = 2240, - [BNXT_ULP_CLASS_HID_3e0a] = 2241, - [BNXT_ULP_CLASS_HID_3b56] = 2242, - [BNXT_ULP_CLASS_HID_37a2] = 2243, - [BNXT_ULP_CLASS_HID_30ee] = 2244, - [BNXT_ULP_CLASS_HID_5e66] = 2245, - [BNXT_ULP_CLASS_HID_5ab2] = 2246, - [BNXT_ULP_CLASS_HID_57fe] = 2247, - [BNXT_ULP_CLASS_HID_50ca] = 2248, - [BNXT_ULP_CLASS_HID_029a] = 2249, - [BNXT_ULP_CLASS_HID_1fe6] = 2250, - [BNXT_ULP_CLASS_HID_1832] = 2251, - [BNXT_ULP_CLASS_HID_157e] = 2252, - [BNXT_ULP_CLASS_HID_582e] = 2253, - [BNXT_ULP_CLASS_HID_557a] = 2254, - [BNXT_ULP_CLASS_HID_2e46] = 2255, - [BNXT_ULP_CLASS_HID_2a92] = 2256, - [BNXT_ULP_CLASS_HID_38c6] = 2257, - [BNXT_ULP_CLASS_HID_3512] = 2258, - [BNXT_ULP_CLASS_HID_0e5e] = 2259, - [BNXT_ULP_CLASS_HID_0aaa] = 2260, - [BNXT_ULP_CLASS_HID_5822] = 2261, - [BNXT_ULP_CLASS_HID_556e] = 2262, - [BNXT_ULP_CLASS_HID_51ba] = 2263, - [BNXT_ULP_CLASS_HID_2a86] = 2264, - [BNXT_ULP_CLASS_HID_1d56] = 2265, - [BNXT_ULP_CLASS_HID_19a2] = 2266, - [BNXT_ULP_CLASS_HID_12ee] = 2267, - [BNXT_ULP_CLASS_HID_4aee] = 2268, - [BNXT_ULP_CLASS_HID_52ea] = 2269, - [BNXT_ULP_CLASS_HID_2f36] = 2270, - [BNXT_ULP_CLASS_HID_2802] = 2271, - [BNXT_ULP_CLASS_HID_254e] = 2272, - [BNXT_ULP_CLASS_HID_3282] = 2273, - [BNXT_ULP_CLASS_HID_0fce] = 2274, - [BNXT_ULP_CLASS_HID_081a] = 2275, - [BNXT_ULP_CLASS_HID_0566] = 2276, - [BNXT_ULP_CLASS_HID_34d6] = 2277, - [BNXT_ULP_CLASS_HID_3a1a] = 2278, - [BNXT_ULP_CLASS_HID_09aa] = 2279, - [BNXT_ULP_CLASS_HID_0276] = 2280, - [BNXT_ULP_CLASS_HID_1f02] = 2281, - [BNXT_ULP_CLASS_HID_1bce] = 2282, - [BNXT_ULP_CLASS_HID_2952] = 2283, - [BNXT_ULP_CLASS_HID_221e] = 2284, - [BNXT_ULP_CLASS_HID_3f2a] = 2285, - [BNXT_ULP_CLASS_HID_3bf6] = 2286, - [BNXT_ULP_CLASS_HID_03f2] = 2287, - [BNXT_ULP_CLASS_HID_1cbe] = 2288, - [BNXT_ULP_CLASS_HID_194a] = 2289, - [BNXT_ULP_CLASS_HID_1216] = 2290, - [BNXT_ULP_CLASS_HID_5f3e] = 2291, - [BNXT_ULP_CLASS_HID_5bca] = 2292, - [BNXT_ULP_CLASS_HID_5496] = 2293, - [BNXT_ULP_CLASS_HID_51a2] = 2294, - [BNXT_ULP_CLASS_HID_03e6] = 2295, - [BNXT_ULP_CLASS_HID_1cb2] = 2296, - [BNXT_ULP_CLASS_HID_197e] = 2297, - [BNXT_ULP_CLASS_HID_120a] = 2298, - [BNXT_ULP_CLASS_HID_238e] = 2299, - [BNXT_ULP_CLASS_HID_3c5a] = 2300, - [BNXT_ULP_CLASS_HID_3966] = 2301, - [BNXT_ULP_CLASS_HID_3232] = 2302, - [BNXT_ULP_CLASS_HID_1a2e] = 2303, - [BNXT_ULP_CLASS_HID_16fa] = 2304, - [BNXT_ULP_CLASS_HID_1386] = 2305, - [BNXT_ULP_CLASS_HID_4b86] = 2306, - [BNXT_ULP_CLASS_HID_597a] = 2307, - [BNXT_ULP_CLASS_HID_5206] = 2308, - [BNXT_ULP_CLASS_HID_2ed2] = 2309, - [BNXT_ULP_CLASS_HID_2b9e] = 2310, - [BNXT_ULP_CLASS_HID_4d8e] = 2311, - [BNXT_ULP_CLASS_HID_465a] = 2312, - [BNXT_ULP_CLASS_HID_4366] = 2313, - [BNXT_ULP_CLASS_HID_5c32] = 2314, - [BNXT_ULP_CLASS_HID_0e42] = 2315, - [BNXT_ULP_CLASS_HID_0b0e] = 2316, - [BNXT_ULP_CLASS_HID_07da] = 2317, - [BNXT_ULP_CLASS_HID_00e6] = 2318, - [BNXT_ULP_CLASS_HID_47d6] = 2319, - [BNXT_ULP_CLASS_HID_40e2] = 2320, - [BNXT_ULP_CLASS_HID_5dae] = 2321, - [BNXT_ULP_CLASS_HID_567a] = 2322, - [BNXT_ULP_CLASS_HID_242e] = 2323, - [BNXT_ULP_CLASS_HID_20fa] = 2324, - [BNXT_ULP_CLASS_HID_3d86] = 2325, - [BNXT_ULP_CLASS_HID_3652] = 2326, - [BNXT_ULP_CLASS_HID_47ca] = 2327, - [BNXT_ULP_CLASS_HID_4096] = 2328, - [BNXT_ULP_CLASS_HID_5da2] = 2329, - [BNXT_ULP_CLASS_HID_566e] = 2330, - [BNXT_ULP_CLASS_HID_08be] = 2331, - [BNXT_ULP_CLASS_HID_054a] = 2332, - [BNXT_ULP_CLASS_HID_1e16] = 2333, - [BNXT_ULP_CLASS_HID_1b22] = 2334, - [BNXT_ULP_CLASS_HID_5e12] = 2335, - [BNXT_ULP_CLASS_HID_5ade] = 2336, - [BNXT_ULP_CLASS_HID_57ea] = 2337, - [BNXT_ULP_CLASS_HID_50b6] = 2338, - [BNXT_ULP_CLASS_HID_3e6a] = 2339, - [BNXT_ULP_CLASS_HID_3b36] = 2340, - [BNXT_ULP_CLASS_HID_37c2] = 2341, - [BNXT_ULP_CLASS_HID_308e] = 2342, - [BNXT_ULP_CLASS_HID_5e06] = 2343, - [BNXT_ULP_CLASS_HID_5ad2] = 2344, - [BNXT_ULP_CLASS_HID_579e] = 2345, - [BNXT_ULP_CLASS_HID_50aa] = 2346, - [BNXT_ULP_CLASS_HID_02fa] = 2347, - [BNXT_ULP_CLASS_HID_1f86] = 2348, - [BNXT_ULP_CLASS_HID_1852] = 2349, - [BNXT_ULP_CLASS_HID_151e] = 2350, - [BNXT_ULP_CLASS_HID_584e] = 2351, - [BNXT_ULP_CLASS_HID_551a] = 2352, - [BNXT_ULP_CLASS_HID_2e26] = 2353, - [BNXT_ULP_CLASS_HID_2af2] = 2354, - [BNXT_ULP_CLASS_HID_38a6] = 2355, - [BNXT_ULP_CLASS_HID_3572] = 2356, - [BNXT_ULP_CLASS_HID_0e3e] = 2357, - [BNXT_ULP_CLASS_HID_0aca] = 2358, - [BNXT_ULP_CLASS_HID_5842] = 2359, - [BNXT_ULP_CLASS_HID_550e] = 2360, - [BNXT_ULP_CLASS_HID_51da] = 2361, - [BNXT_ULP_CLASS_HID_2ae6] = 2362, - [BNXT_ULP_CLASS_HID_1d36] = 2363, - [BNXT_ULP_CLASS_HID_19c2] = 2364, - [BNXT_ULP_CLASS_HID_128e] = 2365, - [BNXT_ULP_CLASS_HID_4a8e] = 2366, - [BNXT_ULP_CLASS_HID_528a] = 2367, - [BNXT_ULP_CLASS_HID_2f56] = 2368, - [BNXT_ULP_CLASS_HID_2862] = 2369, - [BNXT_ULP_CLASS_HID_252e] = 2370, - [BNXT_ULP_CLASS_HID_32e2] = 2371, - [BNXT_ULP_CLASS_HID_0fae] = 2372, - [BNXT_ULP_CLASS_HID_087a] = 2373, - [BNXT_ULP_CLASS_HID_0506] = 2374, - [BNXT_ULP_CLASS_HID_34b6] = 2375, - [BNXT_ULP_CLASS_HID_3a7a] = 2376, - [BNXT_ULP_CLASS_HID_a73c] = 2377, - [BNXT_ULP_CLASS_HID_a040] = 2378, - [BNXT_ULP_CLASS_HID_1d640] = 2379, - [BNXT_ULP_CLASS_HID_1dd3c] = 2380, - [BNXT_ULP_CLASS_HID_cba0] = 2381, - [BNXT_ULP_CLASS_HID_c4f4] = 2382, - [BNXT_ULP_CLASS_HID_19f38] = 2383, - [BNXT_ULP_CLASS_HID_182f4] = 2384, - [BNXT_ULP_CLASS_HID_b098] = 2385, - [BNXT_ULP_CLASS_HID_8dac] = 2386, - [BNXT_ULP_CLASS_HID_1a3ac] = 2387, - [BNXT_ULP_CLASS_HID_1a698] = 2388, - [BNXT_ULP_CLASS_HID_d50c] = 2389, - [BNXT_ULP_CLASS_HID_ae50] = 2390, - [BNXT_ULP_CLASS_HID_1c450] = 2391, - [BNXT_ULP_CLASS_HID_1cb0c] = 2392, - [BNXT_ULP_CLASS_HID_a1f0] = 2393, - [BNXT_ULP_CLASS_HID_ba04] = 2394, - [BNXT_ULP_CLASS_HID_1d004] = 2395, - [BNXT_ULP_CLASS_HID_1d7f0] = 2396, - [BNXT_ULP_CLASS_HID_c264] = 2397, - [BNXT_ULP_CLASS_HID_dea8] = 2398, - [BNXT_ULP_CLASS_HID_199fc] = 2399, - [BNXT_ULP_CLASS_HID_19ca8] = 2400, - [BNXT_ULP_CLASS_HID_8b5c] = 2401, - [BNXT_ULP_CLASS_HID_8460] = 2402, - [BNXT_ULP_CLASS_HID_1ba60] = 2403, - [BNXT_ULP_CLASS_HID_1a15c] = 2404, - [BNXT_ULP_CLASS_HID_afc0] = 2405, - [BNXT_ULP_CLASS_HID_a814] = 2406, - [BNXT_ULP_CLASS_HID_1de14] = 2407, - [BNXT_ULP_CLASS_HID_1c5c0] = 2408, - [BNXT_ULP_CLASS_HID_8c2c] = 2409, - [BNXT_ULP_CLASS_HID_8970] = 2410, - [BNXT_ULP_CLASS_HID_1bf70] = 2411, - [BNXT_ULP_CLASS_HID_1a22c] = 2412, - [BNXT_ULP_CLASS_HID_d0d0] = 2413, - [BNXT_ULP_CLASS_HID_ade4] = 2414, - [BNXT_ULP_CLASS_HID_1c3e4] = 2415, - [BNXT_ULP_CLASS_HID_1c6d0] = 2416, - [BNXT_ULP_CLASS_HID_9988] = 2417, - [BNXT_ULP_CLASS_HID_92dc] = 2418, - [BNXT_ULP_CLASS_HID_188dc] = 2419, - [BNXT_ULP_CLASS_HID_18f88] = 2420, - [BNXT_ULP_CLASS_HID_ba3c] = 2421, - [BNXT_ULP_CLASS_HID_b740] = 2422, - [BNXT_ULP_CLASS_HID_1ad40] = 2423, - [BNXT_ULP_CLASS_HID_1d03c] = 2424, - [BNXT_ULP_CLASS_HID_86e0] = 2425, - [BNXT_ULP_CLASS_HID_8334] = 2426, - [BNXT_ULP_CLASS_HID_1b934] = 2427, - [BNXT_ULP_CLASS_HID_1bce0] = 2428, - [BNXT_ULP_CLASS_HID_aa94] = 2429, - [BNXT_ULP_CLASS_HID_a7d8] = 2430, - [BNXT_ULP_CLASS_HID_1ddd8] = 2431, - [BNXT_ULP_CLASS_HID_1c094] = 2432, - [BNXT_ULP_CLASS_HID_904c] = 2433, - [BNXT_ULP_CLASS_HID_c84c] = 2434, - [BNXT_ULP_CLASS_HID_18290] = 2435, - [BNXT_ULP_CLASS_HID_1864c] = 2436, - [BNXT_ULP_CLASS_HID_b4f0] = 2437, - [BNXT_ULP_CLASS_HID_b104] = 2438, - [BNXT_ULP_CLASS_HID_1a704] = 2439, - [BNXT_ULP_CLASS_HID_1aaf0] = 2440, - [BNXT_ULP_CLASS_HID_80a4] = 2441, - [BNXT_ULP_CLASS_HID_9de8] = 2442, - [BNXT_ULP_CLASS_HID_1b3e8] = 2443, - [BNXT_ULP_CLASS_HID_1b6a4] = 2444, - [BNXT_ULP_CLASS_HID_a548] = 2445, - [BNXT_ULP_CLASS_HID_a19c] = 2446, - [BNXT_ULP_CLASS_HID_1d79c] = 2447, - [BNXT_ULP_CLASS_HID_1db48] = 2448, - [BNXT_ULP_CLASS_HID_9a98] = 2449, - [BNXT_ULP_CLASS_HID_97ac] = 2450, - [BNXT_ULP_CLASS_HID_18dac] = 2451, - [BNXT_ULP_CLASS_HID_1b098] = 2452, - [BNXT_ULP_CLASS_HID_bf0c] = 2453, - [BNXT_ULP_CLASS_HID_b850] = 2454, - [BNXT_ULP_CLASS_HID_1ae50] = 2455, - [BNXT_ULP_CLASS_HID_1d50c] = 2456, - [BNXT_ULP_CLASS_HID_34f0] = 2457, - [BNXT_ULP_CLASS_HID_3a3c] = 2458, - [BNXT_ULP_CLASS_HID_5ea0] = 2459, - [BNXT_ULP_CLASS_HID_0798] = 2460, - [BNXT_ULP_CLASS_HID_280c] = 2461, - [BNXT_ULP_CLASS_HID_5964] = 2462, - [BNXT_ULP_CLASS_HID_1e5c] = 2463, - [BNXT_ULP_CLASS_HID_22c0] = 2464, - [BNXT_ULP_CLASS_HID_a71c] = 2465, - [BNXT_ULP_CLASS_HID_a8dc] = 2466, - [BNXT_ULP_CLASS_HID_ed9c] = 2467, - [BNXT_ULP_CLASS_HID_ef5c] = 2468, - [BNXT_ULP_CLASS_HID_a060] = 2469, - [BNXT_ULP_CLASS_HID_a520] = 2470, - [BNXT_ULP_CLASS_HID_e6e0] = 2471, - [BNXT_ULP_CLASS_HID_eba0] = 2472, - [BNXT_ULP_CLASS_HID_1d660] = 2473, - [BNXT_ULP_CLASS_HID_1fb20] = 2474, - [BNXT_ULP_CLASS_HID_1dce0] = 2475, - [BNXT_ULP_CLASS_HID_1e1a0] = 2476, - [BNXT_ULP_CLASS_HID_1dd1c] = 2477, - [BNXT_ULP_CLASS_HID_1fedc] = 2478, - [BNXT_ULP_CLASS_HID_1c39c] = 2479, - [BNXT_ULP_CLASS_HID_1e55c] = 2480, - [BNXT_ULP_CLASS_HID_cb80] = 2481, - [BNXT_ULP_CLASS_HID_b194] = 2482, - [BNXT_ULP_CLASS_HID_d354] = 2483, - [BNXT_ULP_CLASS_HID_f414] = 2484, - [BNXT_ULP_CLASS_HID_c4d4] = 2485, - [BNXT_ULP_CLASS_HID_e994] = 2486, - [BNXT_ULP_CLASS_HID_cb54] = 2487, - [BNXT_ULP_CLASS_HID_f158] = 2488, - [BNXT_ULP_CLASS_HID_19f18] = 2489, - [BNXT_ULP_CLASS_HID_1a0d8] = 2490, - [BNXT_ULP_CLASS_HID_1c598] = 2491, - [BNXT_ULP_CLASS_HID_1e758] = 2492, - [BNXT_ULP_CLASS_HID_182d4] = 2493, - [BNXT_ULP_CLASS_HID_1a794] = 2494, - [BNXT_ULP_CLASS_HID_1c954] = 2495, - [BNXT_ULP_CLASS_HID_1ea14] = 2496, - [BNXT_ULP_CLASS_HID_b0b8] = 2497, - [BNXT_ULP_CLASS_HID_b278] = 2498, - [BNXT_ULP_CLASS_HID_f738] = 2499, - [BNXT_ULP_CLASS_HID_f8f8] = 2500, - [BNXT_ULP_CLASS_HID_8d8c] = 2501, - [BNXT_ULP_CLASS_HID_af4c] = 2502, - [BNXT_ULP_CLASS_HID_f00c] = 2503, - [BNXT_ULP_CLASS_HID_f5cc] = 2504, - [BNXT_ULP_CLASS_HID_1a38c] = 2505, - [BNXT_ULP_CLASS_HID_1a54c] = 2506, - [BNXT_ULP_CLASS_HID_1e60c] = 2507, - [BNXT_ULP_CLASS_HID_1ebcc] = 2508, - [BNXT_ULP_CLASS_HID_1a6b8] = 2509, - [BNXT_ULP_CLASS_HID_1a878] = 2510, - [BNXT_ULP_CLASS_HID_1ed38] = 2511, - [BNXT_ULP_CLASS_HID_1eef8] = 2512, - [BNXT_ULP_CLASS_HID_d52c] = 2513, - [BNXT_ULP_CLASS_HID_f6ec] = 2514, - [BNXT_ULP_CLASS_HID_dbac] = 2515, - [BNXT_ULP_CLASS_HID_fd6c] = 2516, - [BNXT_ULP_CLASS_HID_ae70] = 2517, - [BNXT_ULP_CLASS_HID_f330] = 2518, - [BNXT_ULP_CLASS_HID_d4f0] = 2519, - [BNXT_ULP_CLASS_HID_f9b0] = 2520, - [BNXT_ULP_CLASS_HID_1c470] = 2521, - [BNXT_ULP_CLASS_HID_1e930] = 2522, - [BNXT_ULP_CLASS_HID_1caf0] = 2523, - [BNXT_ULP_CLASS_HID_1f084] = 2524, - [BNXT_ULP_CLASS_HID_1cb2c] = 2525, - [BNXT_ULP_CLASS_HID_1b130] = 2526, - [BNXT_ULP_CLASS_HID_1d2f0] = 2527, - [BNXT_ULP_CLASS_HID_1f7b0] = 2528, - [BNXT_ULP_CLASS_HID_a1d0] = 2529, - [BNXT_ULP_CLASS_HID_a290] = 2530, - [BNXT_ULP_CLASS_HID_e450] = 2531, - [BNXT_ULP_CLASS_HID_e910] = 2532, - [BNXT_ULP_CLASS_HID_ba24] = 2533, - [BNXT_ULP_CLASS_HID_bfe4] = 2534, - [BNXT_ULP_CLASS_HID_e0a4] = 2535, - [BNXT_ULP_CLASS_HID_e264] = 2536, - [BNXT_ULP_CLASS_HID_1d024] = 2537, - [BNXT_ULP_CLASS_HID_1f5e4] = 2538, - [BNXT_ULP_CLASS_HID_1d6a4] = 2539, - [BNXT_ULP_CLASS_HID_1f864] = 2540, - [BNXT_ULP_CLASS_HID_1d7d0] = 2541, - [BNXT_ULP_CLASS_HID_1f890] = 2542, - [BNXT_ULP_CLASS_HID_1da50] = 2543, - [BNXT_ULP_CLASS_HID_1ff10] = 2544, - [BNXT_ULP_CLASS_HID_c244] = 2545, - [BNXT_ULP_CLASS_HID_e704] = 2546, - [BNXT_ULP_CLASS_HID_c8c4] = 2547, - [BNXT_ULP_CLASS_HID_ed84] = 2548, - [BNXT_ULP_CLASS_HID_de88] = 2549, - [BNXT_ULP_CLASS_HID_e048] = 2550, - [BNXT_ULP_CLASS_HID_c508] = 2551, - [BNXT_ULP_CLASS_HID_e6c8] = 2552, - [BNXT_ULP_CLASS_HID_199dc] = 2553, - [BNXT_ULP_CLASS_HID_1ba9c] = 2554, - [BNXT_ULP_CLASS_HID_1dc5c] = 2555, - [BNXT_ULP_CLASS_HID_1e11c] = 2556, - [BNXT_ULP_CLASS_HID_19c88] = 2557, - [BNXT_ULP_CLASS_HID_1be48] = 2558, - [BNXT_ULP_CLASS_HID_1c308] = 2559, - [BNXT_ULP_CLASS_HID_1e4c8] = 2560, - [BNXT_ULP_CLASS_HID_8b7c] = 2561, - [BNXT_ULP_CLASS_HID_ac3c] = 2562, - [BNXT_ULP_CLASS_HID_f1fc] = 2563, - [BNXT_ULP_CLASS_HID_f2bc] = 2564, - [BNXT_ULP_CLASS_HID_8440] = 2565, - [BNXT_ULP_CLASS_HID_a900] = 2566, - [BNXT_ULP_CLASS_HID_cac0] = 2567, - [BNXT_ULP_CLASS_HID_ef80] = 2568, - [BNXT_ULP_CLASS_HID_1ba40] = 2569, - [BNXT_ULP_CLASS_HID_1bf00] = 2570, - [BNXT_ULP_CLASS_HID_1e0c0] = 2571, - [BNXT_ULP_CLASS_HID_1e580] = 2572, - [BNXT_ULP_CLASS_HID_1a17c] = 2573, - [BNXT_ULP_CLASS_HID_1a23c] = 2574, - [BNXT_ULP_CLASS_HID_1e7fc] = 2575, - [BNXT_ULP_CLASS_HID_1e8bc] = 2576, - [BNXT_ULP_CLASS_HID_afe0] = 2577, - [BNXT_ULP_CLASS_HID_f0a0] = 2578, - [BNXT_ULP_CLASS_HID_d260] = 2579, - [BNXT_ULP_CLASS_HID_f720] = 2580, - [BNXT_ULP_CLASS_HID_a834] = 2581, - [BNXT_ULP_CLASS_HID_adf4] = 2582, - [BNXT_ULP_CLASS_HID_eeb4] = 2583, - [BNXT_ULP_CLASS_HID_f074] = 2584, - [BNXT_ULP_CLASS_HID_1de34] = 2585, - [BNXT_ULP_CLASS_HID_1e3f4] = 2586, - [BNXT_ULP_CLASS_HID_1c4b4] = 2587, - [BNXT_ULP_CLASS_HID_1e674] = 2588, - [BNXT_ULP_CLASS_HID_1c5e0] = 2589, - [BNXT_ULP_CLASS_HID_1e6a0] = 2590, - [BNXT_ULP_CLASS_HID_1c860] = 2591, - [BNXT_ULP_CLASS_HID_1ed20] = 2592, - [BNXT_ULP_CLASS_HID_8c0c] = 2593, - [BNXT_ULP_CLASS_HID_b1cc] = 2594, - [BNXT_ULP_CLASS_HID_f28c] = 2595, - [BNXT_ULP_CLASS_HID_f44c] = 2596, - [BNXT_ULP_CLASS_HID_8950] = 2597, - [BNXT_ULP_CLASS_HID_aa10] = 2598, - [BNXT_ULP_CLASS_HID_cfd0] = 2599, - [BNXT_ULP_CLASS_HID_f090] = 2600, - [BNXT_ULP_CLASS_HID_1bf50] = 2601, - [BNXT_ULP_CLASS_HID_1a010] = 2602, - [BNXT_ULP_CLASS_HID_1e5d0] = 2603, - [BNXT_ULP_CLASS_HID_1e690] = 2604, - [BNXT_ULP_CLASS_HID_1a20c] = 2605, - [BNXT_ULP_CLASS_HID_1a7cc] = 2606, - [BNXT_ULP_CLASS_HID_1e88c] = 2607, - [BNXT_ULP_CLASS_HID_1ea4c] = 2608, - [BNXT_ULP_CLASS_HID_d0f0] = 2609, - [BNXT_ULP_CLASS_HID_f5b0] = 2610, - [BNXT_ULP_CLASS_HID_d770] = 2611, - [BNXT_ULP_CLASS_HID_f830] = 2612, - [BNXT_ULP_CLASS_HID_adc4] = 2613, - [BNXT_ULP_CLASS_HID_ae84] = 2614, - [BNXT_ULP_CLASS_HID_d044] = 2615, - [BNXT_ULP_CLASS_HID_f504] = 2616, - [BNXT_ULP_CLASS_HID_1c3c4] = 2617, - [BNXT_ULP_CLASS_HID_1e484] = 2618, - [BNXT_ULP_CLASS_HID_1c644] = 2619, - [BNXT_ULP_CLASS_HID_1eb04] = 2620, - [BNXT_ULP_CLASS_HID_1c6f0] = 2621, - [BNXT_ULP_CLASS_HID_1ebb0] = 2622, - [BNXT_ULP_CLASS_HID_1cd70] = 2623, - [BNXT_ULP_CLASS_HID_1f304] = 2624, - [BNXT_ULP_CLASS_HID_99a8] = 2625, - [BNXT_ULP_CLASS_HID_bb68] = 2626, - [BNXT_ULP_CLASS_HID_dc28] = 2627, - [BNXT_ULP_CLASS_HID_e1e8] = 2628, - [BNXT_ULP_CLASS_HID_92fc] = 2629, - [BNXT_ULP_CLASS_HID_b7bc] = 2630, - [BNXT_ULP_CLASS_HID_d97c] = 2631, - [BNXT_ULP_CLASS_HID_fa3c] = 2632, - [BNXT_ULP_CLASS_HID_188fc] = 2633, - [BNXT_ULP_CLASS_HID_1adbc] = 2634, - [BNXT_ULP_CLASS_HID_1cf7c] = 2635, - [BNXT_ULP_CLASS_HID_1f03c] = 2636, - [BNXT_ULP_CLASS_HID_18fa8] = 2637, - [BNXT_ULP_CLASS_HID_1b168] = 2638, - [BNXT_ULP_CLASS_HID_1f228] = 2639, - [BNXT_ULP_CLASS_HID_1f7e8] = 2640, - [BNXT_ULP_CLASS_HID_ba1c] = 2641, - [BNXT_ULP_CLASS_HID_bfdc] = 2642, - [BNXT_ULP_CLASS_HID_e09c] = 2643, - [BNXT_ULP_CLASS_HID_e25c] = 2644, - [BNXT_ULP_CLASS_HID_b760] = 2645, - [BNXT_ULP_CLASS_HID_b820] = 2646, - [BNXT_ULP_CLASS_HID_fde0] = 2647, - [BNXT_ULP_CLASS_HID_fea0] = 2648, - [BNXT_ULP_CLASS_HID_1ad60] = 2649, - [BNXT_ULP_CLASS_HID_1ae20] = 2650, - [BNXT_ULP_CLASS_HID_1d3e0] = 2651, - [BNXT_ULP_CLASS_HID_1f4a0] = 2652, - [BNXT_ULP_CLASS_HID_1d01c] = 2653, - [BNXT_ULP_CLASS_HID_1f5dc] = 2654, - [BNXT_ULP_CLASS_HID_1d69c] = 2655, - [BNXT_ULP_CLASS_HID_1f85c] = 2656, - [BNXT_ULP_CLASS_HID_86c0] = 2657, - [BNXT_ULP_CLASS_HID_ab80] = 2658, - [BNXT_ULP_CLASS_HID_cd40] = 2659, - [BNXT_ULP_CLASS_HID_ee00] = 2660, - [BNXT_ULP_CLASS_HID_8314] = 2661, - [BNXT_ULP_CLASS_HID_a4d4] = 2662, - [BNXT_ULP_CLASS_HID_c994] = 2663, - [BNXT_ULP_CLASS_HID_eb54] = 2664, - [BNXT_ULP_CLASS_HID_1b914] = 2665, - [BNXT_ULP_CLASS_HID_1bad4] = 2666, - [BNXT_ULP_CLASS_HID_1ff94] = 2667, - [BNXT_ULP_CLASS_HID_1e154] = 2668, - [BNXT_ULP_CLASS_HID_1bcc0] = 2669, - [BNXT_ULP_CLASS_HID_1a180] = 2670, - [BNXT_ULP_CLASS_HID_1e340] = 2671, - [BNXT_ULP_CLASS_HID_1e400] = 2672, - [BNXT_ULP_CLASS_HID_aab4] = 2673, - [BNXT_ULP_CLASS_HID_ac74] = 2674, - [BNXT_ULP_CLASS_HID_d134] = 2675, - [BNXT_ULP_CLASS_HID_f2f4] = 2676, - [BNXT_ULP_CLASS_HID_a7f8] = 2677, - [BNXT_ULP_CLASS_HID_a8b8] = 2678, - [BNXT_ULP_CLASS_HID_ea78] = 2679, - [BNXT_ULP_CLASS_HID_ef38] = 2680, - [BNXT_ULP_CLASS_HID_1ddf8] = 2681, - [BNXT_ULP_CLASS_HID_1feb8] = 2682, - [BNXT_ULP_CLASS_HID_1c078] = 2683, - [BNXT_ULP_CLASS_HID_1e538] = 2684, - [BNXT_ULP_CLASS_HID_1c0b4] = 2685, - [BNXT_ULP_CLASS_HID_1e274] = 2686, - [BNXT_ULP_CLASS_HID_1c734] = 2687, - [BNXT_ULP_CLASS_HID_1e8f4] = 2688, - [BNXT_ULP_CLASS_HID_906c] = 2689, - [BNXT_ULP_CLASS_HID_b52c] = 2690, - [BNXT_ULP_CLASS_HID_d6ec] = 2691, - [BNXT_ULP_CLASS_HID_fbac] = 2692, - [BNXT_ULP_CLASS_HID_c86c] = 2693, - [BNXT_ULP_CLASS_HID_ed2c] = 2694, - [BNXT_ULP_CLASS_HID_d330] = 2695, - [BNXT_ULP_CLASS_HID_f4f0] = 2696, - [BNXT_ULP_CLASS_HID_182b0] = 2697, - [BNXT_ULP_CLASS_HID_1a470] = 2698, - [BNXT_ULP_CLASS_HID_1c930] = 2699, - [BNXT_ULP_CLASS_HID_1eaf0] = 2700, - [BNXT_ULP_CLASS_HID_1866c] = 2701, - [BNXT_ULP_CLASS_HID_1ab2c] = 2702, - [BNXT_ULP_CLASS_HID_1ccec] = 2703, - [BNXT_ULP_CLASS_HID_1f1ac] = 2704, - [BNXT_ULP_CLASS_HID_b4d0] = 2705, - [BNXT_ULP_CLASS_HID_b990] = 2706, - [BNXT_ULP_CLASS_HID_fb50] = 2707, - [BNXT_ULP_CLASS_HID_fc10] = 2708, - [BNXT_ULP_CLASS_HID_b124] = 2709, - [BNXT_ULP_CLASS_HID_b2e4] = 2710, - [BNXT_ULP_CLASS_HID_f7a4] = 2711, - [BNXT_ULP_CLASS_HID_f964] = 2712, - [BNXT_ULP_CLASS_HID_1a724] = 2713, - [BNXT_ULP_CLASS_HID_1a8e4] = 2714, - [BNXT_ULP_CLASS_HID_1eda4] = 2715, - [BNXT_ULP_CLASS_HID_1ef64] = 2716, - [BNXT_ULP_CLASS_HID_1aad0] = 2717, - [BNXT_ULP_CLASS_HID_1af90] = 2718, - [BNXT_ULP_CLASS_HID_1d150] = 2719, - [BNXT_ULP_CLASS_HID_1f210] = 2720, - [BNXT_ULP_CLASS_HID_8084] = 2721, - [BNXT_ULP_CLASS_HID_a244] = 2722, - [BNXT_ULP_CLASS_HID_c704] = 2723, - [BNXT_ULP_CLASS_HID_e8c4] = 2724, - [BNXT_ULP_CLASS_HID_9dc8] = 2725, - [BNXT_ULP_CLASS_HID_be88] = 2726, - [BNXT_ULP_CLASS_HID_c048] = 2727, - [BNXT_ULP_CLASS_HID_e508] = 2728, - [BNXT_ULP_CLASS_HID_1b3c8] = 2729, - [BNXT_ULP_CLASS_HID_1b488] = 2730, - [BNXT_ULP_CLASS_HID_1f648] = 2731, - [BNXT_ULP_CLASS_HID_1fb08] = 2732, - [BNXT_ULP_CLASS_HID_1b684] = 2733, - [BNXT_ULP_CLASS_HID_1b844] = 2734, - [BNXT_ULP_CLASS_HID_1fd04] = 2735, - [BNXT_ULP_CLASS_HID_1fec4] = 2736, - [BNXT_ULP_CLASS_HID_a568] = 2737, - [BNXT_ULP_CLASS_HID_a628] = 2738, - [BNXT_ULP_CLASS_HID_ebe8] = 2739, - [BNXT_ULP_CLASS_HID_eca8] = 2740, - [BNXT_ULP_CLASS_HID_a1bc] = 2741, - [BNXT_ULP_CLASS_HID_a37c] = 2742, - [BNXT_ULP_CLASS_HID_e43c] = 2743, - [BNXT_ULP_CLASS_HID_e9fc] = 2744, - [BNXT_ULP_CLASS_HID_1d7bc] = 2745, - [BNXT_ULP_CLASS_HID_1f97c] = 2746, - [BNXT_ULP_CLASS_HID_1da3c] = 2747, - [BNXT_ULP_CLASS_HID_1fffc] = 2748, - [BNXT_ULP_CLASS_HID_1db68] = 2749, - [BNXT_ULP_CLASS_HID_1fc28] = 2750, - [BNXT_ULP_CLASS_HID_1c1e8] = 2751, - [BNXT_ULP_CLASS_HID_1e2a8] = 2752, - [BNXT_ULP_CLASS_HID_9ab8] = 2753, - [BNXT_ULP_CLASS_HID_bc78] = 2754, - [BNXT_ULP_CLASS_HID_c138] = 2755, - [BNXT_ULP_CLASS_HID_e2f8] = 2756, - [BNXT_ULP_CLASS_HID_978c] = 2757, - [BNXT_ULP_CLASS_HID_b94c] = 2758, - [BNXT_ULP_CLASS_HID_da0c] = 2759, - [BNXT_ULP_CLASS_HID_ffcc] = 2760, - [BNXT_ULP_CLASS_HID_18d8c] = 2761, - [BNXT_ULP_CLASS_HID_1af4c] = 2762, - [BNXT_ULP_CLASS_HID_1f00c] = 2763, - [BNXT_ULP_CLASS_HID_1f5cc] = 2764, - [BNXT_ULP_CLASS_HID_1b0b8] = 2765, - [BNXT_ULP_CLASS_HID_1b278] = 2766, - [BNXT_ULP_CLASS_HID_1f738] = 2767, - [BNXT_ULP_CLASS_HID_1f8f8] = 2768, - [BNXT_ULP_CLASS_HID_bf2c] = 2769, - [BNXT_ULP_CLASS_HID_a0ec] = 2770, - [BNXT_ULP_CLASS_HID_e5ac] = 2771, - [BNXT_ULP_CLASS_HID_e76c] = 2772, - [BNXT_ULP_CLASS_HID_b870] = 2773, - [BNXT_ULP_CLASS_HID_bd30] = 2774, - [BNXT_ULP_CLASS_HID_fef0] = 2775, - [BNXT_ULP_CLASS_HID_e3b0] = 2776, - [BNXT_ULP_CLASS_HID_1ae70] = 2777, - [BNXT_ULP_CLASS_HID_1f330] = 2778, - [BNXT_ULP_CLASS_HID_1d4f0] = 2779, - [BNXT_ULP_CLASS_HID_1f9b0] = 2780, - [BNXT_ULP_CLASS_HID_1d52c] = 2781, - [BNXT_ULP_CLASS_HID_1f6ec] = 2782, - [BNXT_ULP_CLASS_HID_1dbac] = 2783, - [BNXT_ULP_CLASS_HID_1fd6c] = 2784, - [BNXT_ULP_CLASS_HID_34d0] = 2785, - [BNXT_ULP_CLASS_HID_3a1c] = 2786, - [BNXT_ULP_CLASS_HID_5e80] = 2787, - [BNXT_ULP_CLASS_HID_07b8] = 2788, - [BNXT_ULP_CLASS_HID_282c] = 2789, - [BNXT_ULP_CLASS_HID_5944] = 2790, - [BNXT_ULP_CLASS_HID_1e7c] = 2791, - [BNXT_ULP_CLASS_HID_22e0] = 2792, - [BNXT_ULP_CLASS_HID_a77c] = 2793, - [BNXT_ULP_CLASS_HID_a8bc] = 2794, - [BNXT_ULP_CLASS_HID_edfc] = 2795, - [BNXT_ULP_CLASS_HID_ef3c] = 2796, - [BNXT_ULP_CLASS_HID_a000] = 2797, - [BNXT_ULP_CLASS_HID_a540] = 2798, - [BNXT_ULP_CLASS_HID_e680] = 2799, - [BNXT_ULP_CLASS_HID_ebc0] = 2800, - [BNXT_ULP_CLASS_HID_1d600] = 2801, - [BNXT_ULP_CLASS_HID_1fb40] = 2802, - [BNXT_ULP_CLASS_HID_1dc80] = 2803, - [BNXT_ULP_CLASS_HID_1e1c0] = 2804, - [BNXT_ULP_CLASS_HID_1dd7c] = 2805, - [BNXT_ULP_CLASS_HID_1febc] = 2806, - [BNXT_ULP_CLASS_HID_1c3fc] = 2807, - [BNXT_ULP_CLASS_HID_1e53c] = 2808, - [BNXT_ULP_CLASS_HID_cbe0] = 2809, - [BNXT_ULP_CLASS_HID_b1f4] = 2810, - [BNXT_ULP_CLASS_HID_d334] = 2811, - [BNXT_ULP_CLASS_HID_f474] = 2812, - [BNXT_ULP_CLASS_HID_c4b4] = 2813, - [BNXT_ULP_CLASS_HID_e9f4] = 2814, - [BNXT_ULP_CLASS_HID_cb34] = 2815, - [BNXT_ULP_CLASS_HID_f138] = 2816, - [BNXT_ULP_CLASS_HID_19f78] = 2817, - [BNXT_ULP_CLASS_HID_1a0b8] = 2818, - [BNXT_ULP_CLASS_HID_1c5f8] = 2819, - [BNXT_ULP_CLASS_HID_1e738] = 2820, - [BNXT_ULP_CLASS_HID_182b4] = 2821, - [BNXT_ULP_CLASS_HID_1a7f4] = 2822, - [BNXT_ULP_CLASS_HID_1c934] = 2823, - [BNXT_ULP_CLASS_HID_1ea74] = 2824, - [BNXT_ULP_CLASS_HID_b0d8] = 2825, - [BNXT_ULP_CLASS_HID_b218] = 2826, - [BNXT_ULP_CLASS_HID_f758] = 2827, - [BNXT_ULP_CLASS_HID_f898] = 2828, - [BNXT_ULP_CLASS_HID_8dec] = 2829, - [BNXT_ULP_CLASS_HID_af2c] = 2830, - [BNXT_ULP_CLASS_HID_f06c] = 2831, - [BNXT_ULP_CLASS_HID_f5ac] = 2832, - [BNXT_ULP_CLASS_HID_1a3ec] = 2833, - [BNXT_ULP_CLASS_HID_1a52c] = 2834, - [BNXT_ULP_CLASS_HID_1e66c] = 2835, - [BNXT_ULP_CLASS_HID_1ebac] = 2836, - [BNXT_ULP_CLASS_HID_1a6d8] = 2837, - [BNXT_ULP_CLASS_HID_1a818] = 2838, - [BNXT_ULP_CLASS_HID_1ed58] = 2839, - [BNXT_ULP_CLASS_HID_1ee98] = 2840, - [BNXT_ULP_CLASS_HID_d54c] = 2841, - [BNXT_ULP_CLASS_HID_f68c] = 2842, - [BNXT_ULP_CLASS_HID_dbcc] = 2843, - [BNXT_ULP_CLASS_HID_fd0c] = 2844, - [BNXT_ULP_CLASS_HID_ae10] = 2845, - [BNXT_ULP_CLASS_HID_f350] = 2846, - [BNXT_ULP_CLASS_HID_d490] = 2847, - [BNXT_ULP_CLASS_HID_f9d0] = 2848, - [BNXT_ULP_CLASS_HID_1c410] = 2849, - [BNXT_ULP_CLASS_HID_1e950] = 2850, - [BNXT_ULP_CLASS_HID_1ca90] = 2851, - [BNXT_ULP_CLASS_HID_1f0e4] = 2852, - [BNXT_ULP_CLASS_HID_1cb4c] = 2853, - [BNXT_ULP_CLASS_HID_1b150] = 2854, - [BNXT_ULP_CLASS_HID_1d290] = 2855, - [BNXT_ULP_CLASS_HID_1f7d0] = 2856, - [BNXT_ULP_CLASS_HID_a1b0] = 2857, - [BNXT_ULP_CLASS_HID_a2f0] = 2858, - [BNXT_ULP_CLASS_HID_e430] = 2859, - [BNXT_ULP_CLASS_HID_e970] = 2860, - [BNXT_ULP_CLASS_HID_ba44] = 2861, - [BNXT_ULP_CLASS_HID_bf84] = 2862, - [BNXT_ULP_CLASS_HID_e0c4] = 2863, - [BNXT_ULP_CLASS_HID_e204] = 2864, - [BNXT_ULP_CLASS_HID_1d044] = 2865, - [BNXT_ULP_CLASS_HID_1f584] = 2866, - [BNXT_ULP_CLASS_HID_1d6c4] = 2867, - [BNXT_ULP_CLASS_HID_1f804] = 2868, - [BNXT_ULP_CLASS_HID_1d7b0] = 2869, - [BNXT_ULP_CLASS_HID_1f8f0] = 2870, - [BNXT_ULP_CLASS_HID_1da30] = 2871, - [BNXT_ULP_CLASS_HID_1ff70] = 2872, - [BNXT_ULP_CLASS_HID_c224] = 2873, - [BNXT_ULP_CLASS_HID_e764] = 2874, - [BNXT_ULP_CLASS_HID_c8a4] = 2875, - [BNXT_ULP_CLASS_HID_ede4] = 2876, - [BNXT_ULP_CLASS_HID_dee8] = 2877, - [BNXT_ULP_CLASS_HID_e028] = 2878, - [BNXT_ULP_CLASS_HID_c568] = 2879, - [BNXT_ULP_CLASS_HID_e6a8] = 2880, - [BNXT_ULP_CLASS_HID_199bc] = 2881, - [BNXT_ULP_CLASS_HID_1bafc] = 2882, - [BNXT_ULP_CLASS_HID_1dc3c] = 2883, - [BNXT_ULP_CLASS_HID_1e17c] = 2884, - [BNXT_ULP_CLASS_HID_19ce8] = 2885, - [BNXT_ULP_CLASS_HID_1be28] = 2886, - [BNXT_ULP_CLASS_HID_1c368] = 2887, - [BNXT_ULP_CLASS_HID_1e4a8] = 2888, - [BNXT_ULP_CLASS_HID_8b1c] = 2889, - [BNXT_ULP_CLASS_HID_ac5c] = 2890, - [BNXT_ULP_CLASS_HID_f19c] = 2891, - [BNXT_ULP_CLASS_HID_f2dc] = 2892, - [BNXT_ULP_CLASS_HID_8420] = 2893, - [BNXT_ULP_CLASS_HID_a960] = 2894, - [BNXT_ULP_CLASS_HID_caa0] = 2895, - [BNXT_ULP_CLASS_HID_efe0] = 2896, - [BNXT_ULP_CLASS_HID_1ba20] = 2897, - [BNXT_ULP_CLASS_HID_1bf60] = 2898, - [BNXT_ULP_CLASS_HID_1e0a0] = 2899, - [BNXT_ULP_CLASS_HID_1e5e0] = 2900, - [BNXT_ULP_CLASS_HID_1a11c] = 2901, - [BNXT_ULP_CLASS_HID_1a25c] = 2902, - [BNXT_ULP_CLASS_HID_1e79c] = 2903, - [BNXT_ULP_CLASS_HID_1e8dc] = 2904, - [BNXT_ULP_CLASS_HID_af80] = 2905, - [BNXT_ULP_CLASS_HID_f0c0] = 2906, - [BNXT_ULP_CLASS_HID_d200] = 2907, - [BNXT_ULP_CLASS_HID_f740] = 2908, - [BNXT_ULP_CLASS_HID_a854] = 2909, - [BNXT_ULP_CLASS_HID_ad94] = 2910, - [BNXT_ULP_CLASS_HID_eed4] = 2911, - [BNXT_ULP_CLASS_HID_f014] = 2912, - [BNXT_ULP_CLASS_HID_1de54] = 2913, - [BNXT_ULP_CLASS_HID_1e394] = 2914, - [BNXT_ULP_CLASS_HID_1c4d4] = 2915, - [BNXT_ULP_CLASS_HID_1e614] = 2916, - [BNXT_ULP_CLASS_HID_1c580] = 2917, - [BNXT_ULP_CLASS_HID_1e6c0] = 2918, - [BNXT_ULP_CLASS_HID_1c800] = 2919, - [BNXT_ULP_CLASS_HID_1ed40] = 2920, - [BNXT_ULP_CLASS_HID_8c6c] = 2921, - [BNXT_ULP_CLASS_HID_b1ac] = 2922, - [BNXT_ULP_CLASS_HID_f2ec] = 2923, - [BNXT_ULP_CLASS_HID_f42c] = 2924, - [BNXT_ULP_CLASS_HID_8930] = 2925, - [BNXT_ULP_CLASS_HID_aa70] = 2926, - [BNXT_ULP_CLASS_HID_cfb0] = 2927, - [BNXT_ULP_CLASS_HID_f0f0] = 2928, - [BNXT_ULP_CLASS_HID_1bf30] = 2929, - [BNXT_ULP_CLASS_HID_1a070] = 2930, - [BNXT_ULP_CLASS_HID_1e5b0] = 2931, - [BNXT_ULP_CLASS_HID_1e6f0] = 2932, - [BNXT_ULP_CLASS_HID_1a26c] = 2933, - [BNXT_ULP_CLASS_HID_1a7ac] = 2934, - [BNXT_ULP_CLASS_HID_1e8ec] = 2935, - [BNXT_ULP_CLASS_HID_1ea2c] = 2936, - [BNXT_ULP_CLASS_HID_d090] = 2937, - [BNXT_ULP_CLASS_HID_f5d0] = 2938, - [BNXT_ULP_CLASS_HID_d710] = 2939, - [BNXT_ULP_CLASS_HID_f850] = 2940, - [BNXT_ULP_CLASS_HID_ada4] = 2941, - [BNXT_ULP_CLASS_HID_aee4] = 2942, - [BNXT_ULP_CLASS_HID_d024] = 2943, - [BNXT_ULP_CLASS_HID_f564] = 2944, - [BNXT_ULP_CLASS_HID_1c3a4] = 2945, - [BNXT_ULP_CLASS_HID_1e4e4] = 2946, - [BNXT_ULP_CLASS_HID_1c624] = 2947, - [BNXT_ULP_CLASS_HID_1eb64] = 2948, - [BNXT_ULP_CLASS_HID_1c690] = 2949, - [BNXT_ULP_CLASS_HID_1ebd0] = 2950, - [BNXT_ULP_CLASS_HID_1cd10] = 2951, - [BNXT_ULP_CLASS_HID_1f364] = 2952, - [BNXT_ULP_CLASS_HID_99c8] = 2953, - [BNXT_ULP_CLASS_HID_bb08] = 2954, - [BNXT_ULP_CLASS_HID_dc48] = 2955, - [BNXT_ULP_CLASS_HID_e188] = 2956, - [BNXT_ULP_CLASS_HID_929c] = 2957, - [BNXT_ULP_CLASS_HID_b7dc] = 2958, - [BNXT_ULP_CLASS_HID_d91c] = 2959, - [BNXT_ULP_CLASS_HID_fa5c] = 2960, - [BNXT_ULP_CLASS_HID_1889c] = 2961, - [BNXT_ULP_CLASS_HID_1addc] = 2962, - [BNXT_ULP_CLASS_HID_1cf1c] = 2963, - [BNXT_ULP_CLASS_HID_1f05c] = 2964, - [BNXT_ULP_CLASS_HID_18fc8] = 2965, - [BNXT_ULP_CLASS_HID_1b108] = 2966, - [BNXT_ULP_CLASS_HID_1f248] = 2967, - [BNXT_ULP_CLASS_HID_1f788] = 2968, - [BNXT_ULP_CLASS_HID_ba7c] = 2969, - [BNXT_ULP_CLASS_HID_bfbc] = 2970, - [BNXT_ULP_CLASS_HID_e0fc] = 2971, - [BNXT_ULP_CLASS_HID_e23c] = 2972, - [BNXT_ULP_CLASS_HID_b700] = 2973, - [BNXT_ULP_CLASS_HID_b840] = 2974, - [BNXT_ULP_CLASS_HID_fd80] = 2975, - [BNXT_ULP_CLASS_HID_fec0] = 2976, - [BNXT_ULP_CLASS_HID_1ad00] = 2977, - [BNXT_ULP_CLASS_HID_1ae40] = 2978, - [BNXT_ULP_CLASS_HID_1d380] = 2979, - [BNXT_ULP_CLASS_HID_1f4c0] = 2980, - [BNXT_ULP_CLASS_HID_1d07c] = 2981, - [BNXT_ULP_CLASS_HID_1f5bc] = 2982, - [BNXT_ULP_CLASS_HID_1d6fc] = 2983, - [BNXT_ULP_CLASS_HID_1f83c] = 2984, - [BNXT_ULP_CLASS_HID_86a0] = 2985, - [BNXT_ULP_CLASS_HID_abe0] = 2986, - [BNXT_ULP_CLASS_HID_cd20] = 2987, - [BNXT_ULP_CLASS_HID_ee60] = 2988, - [BNXT_ULP_CLASS_HID_8374] = 2989, - [BNXT_ULP_CLASS_HID_a4b4] = 2990, - [BNXT_ULP_CLASS_HID_c9f4] = 2991, - [BNXT_ULP_CLASS_HID_eb34] = 2992, - [BNXT_ULP_CLASS_HID_1b974] = 2993, - [BNXT_ULP_CLASS_HID_1bab4] = 2994, - [BNXT_ULP_CLASS_HID_1fff4] = 2995, - [BNXT_ULP_CLASS_HID_1e134] = 2996, - [BNXT_ULP_CLASS_HID_1bca0] = 2997, - [BNXT_ULP_CLASS_HID_1a1e0] = 2998, - [BNXT_ULP_CLASS_HID_1e320] = 2999, - [BNXT_ULP_CLASS_HID_1e460] = 3000, - [BNXT_ULP_CLASS_HID_aad4] = 3001, - [BNXT_ULP_CLASS_HID_ac14] = 3002, - [BNXT_ULP_CLASS_HID_d154] = 3003, - [BNXT_ULP_CLASS_HID_f294] = 3004, - [BNXT_ULP_CLASS_HID_a798] = 3005, - [BNXT_ULP_CLASS_HID_a8d8] = 3006, - [BNXT_ULP_CLASS_HID_ea18] = 3007, - [BNXT_ULP_CLASS_HID_ef58] = 3008, - [BNXT_ULP_CLASS_HID_1dd98] = 3009, - [BNXT_ULP_CLASS_HID_1fed8] = 3010, - [BNXT_ULP_CLASS_HID_1c018] = 3011, - [BNXT_ULP_CLASS_HID_1e558] = 3012, - [BNXT_ULP_CLASS_HID_1c0d4] = 3013, - [BNXT_ULP_CLASS_HID_1e214] = 3014, - [BNXT_ULP_CLASS_HID_1c754] = 3015, - [BNXT_ULP_CLASS_HID_1e894] = 3016, - [BNXT_ULP_CLASS_HID_900c] = 3017, - [BNXT_ULP_CLASS_HID_b54c] = 3018, - [BNXT_ULP_CLASS_HID_d68c] = 3019, - [BNXT_ULP_CLASS_HID_fbcc] = 3020, - [BNXT_ULP_CLASS_HID_c80c] = 3021, - [BNXT_ULP_CLASS_HID_ed4c] = 3022, - [BNXT_ULP_CLASS_HID_d350] = 3023, - [BNXT_ULP_CLASS_HID_f490] = 3024, - [BNXT_ULP_CLASS_HID_182d0] = 3025, - [BNXT_ULP_CLASS_HID_1a410] = 3026, - [BNXT_ULP_CLASS_HID_1c950] = 3027, - [BNXT_ULP_CLASS_HID_1ea90] = 3028, - [BNXT_ULP_CLASS_HID_1860c] = 3029, - [BNXT_ULP_CLASS_HID_1ab4c] = 3030, - [BNXT_ULP_CLASS_HID_1cc8c] = 3031, - [BNXT_ULP_CLASS_HID_1f1cc] = 3032, - [BNXT_ULP_CLASS_HID_b4b0] = 3033, - [BNXT_ULP_CLASS_HID_b9f0] = 3034, - [BNXT_ULP_CLASS_HID_fb30] = 3035, - [BNXT_ULP_CLASS_HID_fc70] = 3036, - [BNXT_ULP_CLASS_HID_b144] = 3037, - [BNXT_ULP_CLASS_HID_b284] = 3038, - [BNXT_ULP_CLASS_HID_f7c4] = 3039, - [BNXT_ULP_CLASS_HID_f904] = 3040, - [BNXT_ULP_CLASS_HID_1a744] = 3041, - [BNXT_ULP_CLASS_HID_1a884] = 3042, - [BNXT_ULP_CLASS_HID_1edc4] = 3043, - [BNXT_ULP_CLASS_HID_1ef04] = 3044, - [BNXT_ULP_CLASS_HID_1aab0] = 3045, - [BNXT_ULP_CLASS_HID_1aff0] = 3046, - [BNXT_ULP_CLASS_HID_1d130] = 3047, - [BNXT_ULP_CLASS_HID_1f270] = 3048, - [BNXT_ULP_CLASS_HID_80e4] = 3049, - [BNXT_ULP_CLASS_HID_a224] = 3050, - [BNXT_ULP_CLASS_HID_c764] = 3051, - [BNXT_ULP_CLASS_HID_e8a4] = 3052, - [BNXT_ULP_CLASS_HID_9da8] = 3053, - [BNXT_ULP_CLASS_HID_bee8] = 3054, - [BNXT_ULP_CLASS_HID_c028] = 3055, - [BNXT_ULP_CLASS_HID_e568] = 3056, - [BNXT_ULP_CLASS_HID_1b3a8] = 3057, - [BNXT_ULP_CLASS_HID_1b4e8] = 3058, - [BNXT_ULP_CLASS_HID_1f628] = 3059, - [BNXT_ULP_CLASS_HID_1fb68] = 3060, - [BNXT_ULP_CLASS_HID_1b6e4] = 3061, - [BNXT_ULP_CLASS_HID_1b824] = 3062, - [BNXT_ULP_CLASS_HID_1fd64] = 3063, - [BNXT_ULP_CLASS_HID_1fea4] = 3064, - [BNXT_ULP_CLASS_HID_a508] = 3065, - [BNXT_ULP_CLASS_HID_a648] = 3066, - [BNXT_ULP_CLASS_HID_eb88] = 3067, - [BNXT_ULP_CLASS_HID_ecc8] = 3068, - [BNXT_ULP_CLASS_HID_a1dc] = 3069, - [BNXT_ULP_CLASS_HID_a31c] = 3070, - [BNXT_ULP_CLASS_HID_e45c] = 3071, - [BNXT_ULP_CLASS_HID_e99c] = 3072, - [BNXT_ULP_CLASS_HID_1d7dc] = 3073, - [BNXT_ULP_CLASS_HID_1f91c] = 3074, - [BNXT_ULP_CLASS_HID_1da5c] = 3075, - [BNXT_ULP_CLASS_HID_1ff9c] = 3076, - [BNXT_ULP_CLASS_HID_1db08] = 3077, - [BNXT_ULP_CLASS_HID_1fc48] = 3078, - [BNXT_ULP_CLASS_HID_1c188] = 3079, - [BNXT_ULP_CLASS_HID_1e2c8] = 3080, - [BNXT_ULP_CLASS_HID_9ad8] = 3081, - [BNXT_ULP_CLASS_HID_bc18] = 3082, - [BNXT_ULP_CLASS_HID_c158] = 3083, - [BNXT_ULP_CLASS_HID_e298] = 3084, - [BNXT_ULP_CLASS_HID_97ec] = 3085, - [BNXT_ULP_CLASS_HID_b92c] = 3086, - [BNXT_ULP_CLASS_HID_da6c] = 3087, - [BNXT_ULP_CLASS_HID_ffac] = 3088, - [BNXT_ULP_CLASS_HID_18dec] = 3089, - [BNXT_ULP_CLASS_HID_1af2c] = 3090, - [BNXT_ULP_CLASS_HID_1f06c] = 3091, - [BNXT_ULP_CLASS_HID_1f5ac] = 3092, - [BNXT_ULP_CLASS_HID_1b0d8] = 3093, - [BNXT_ULP_CLASS_HID_1b218] = 3094, - [BNXT_ULP_CLASS_HID_1f758] = 3095, - [BNXT_ULP_CLASS_HID_1f898] = 3096, - [BNXT_ULP_CLASS_HID_bf4c] = 3097, - [BNXT_ULP_CLASS_HID_a08c] = 3098, - [BNXT_ULP_CLASS_HID_e5cc] = 3099, - [BNXT_ULP_CLASS_HID_e70c] = 3100, - [BNXT_ULP_CLASS_HID_b810] = 3101, - [BNXT_ULP_CLASS_HID_bd50] = 3102, - [BNXT_ULP_CLASS_HID_fe90] = 3103, - [BNXT_ULP_CLASS_HID_e3d0] = 3104, - [BNXT_ULP_CLASS_HID_1ae10] = 3105, - [BNXT_ULP_CLASS_HID_1f350] = 3106, - [BNXT_ULP_CLASS_HID_1d490] = 3107, - [BNXT_ULP_CLASS_HID_1f9d0] = 3108, - [BNXT_ULP_CLASS_HID_1d54c] = 3109, - [BNXT_ULP_CLASS_HID_1f68c] = 3110, - [BNXT_ULP_CLASS_HID_1dbcc] = 3111, - [BNXT_ULP_CLASS_HID_1fd0c] = 3112, - [BNXT_ULP_CLASS_HID_34b0] = 3113, - [BNXT_ULP_CLASS_HID_3a7c] = 3114, - [BNXT_ULP_CLASS_HID_5ee0] = 3115, - [BNXT_ULP_CLASS_HID_07d8] = 3116, - [BNXT_ULP_CLASS_HID_284c] = 3117, - [BNXT_ULP_CLASS_HID_5924] = 3118, - [BNXT_ULP_CLASS_HID_1e1c] = 3119, - [BNXT_ULP_CLASS_HID_2280] = 3120, - [BNXT_ULP_CLASS_HID_24604] = 3121, - [BNXT_ULP_CLASS_HID_255d4] = 3122, - [BNXT_ULP_CLASS_HID_22e08] = 3123, - [BNXT_ULP_CLASS_HID_24378] = 3124, - [BNXT_ULP_CLASS_HID_20fcc] = 3125, - [BNXT_ULP_CLASS_HID_21a9c] = 3126, - [BNXT_ULP_CLASS_HID_217d0] = 3127, - [BNXT_ULP_CLASS_HID_20800] = 3128, - [BNXT_ULP_CLASS_HID_253a0] = 3129, - [BNXT_ULP_CLASS_HID_23f70] = 3130, - [BNXT_ULP_CLASS_HID_23ba4] = 3131, - [BNXT_ULP_CLASS_HID_22c94] = 3132, - [BNXT_ULP_CLASS_HID_21968] = 3133, - [BNXT_ULP_CLASS_HID_243c4] = 3134, - [BNXT_ULP_CLASS_HID_25c38] = 3135, - [BNXT_ULP_CLASS_HID_2125c] = 3136, - [BNXT_ULP_CLASS_HID_240c8] = 3137, - [BNXT_ULP_CLASS_HID_22f98] = 3138, - [BNXT_ULP_CLASS_HID_228cc] = 3139, - [BNXT_ULP_CLASS_HID_25d3c] = 3140, - [BNXT_ULP_CLASS_HID_20990] = 3141, - [BNXT_ULP_CLASS_HID_214a0] = 3142, - [BNXT_ULP_CLASS_HID_21194] = 3143, - [BNXT_ULP_CLASS_HID_202c4] = 3144, - [BNXT_ULP_CLASS_HID_22a64] = 3145, - [BNXT_ULP_CLASS_HID_23934] = 3146, - [BNXT_ULP_CLASS_HID_23268] = 3147, - [BNXT_ULP_CLASS_HID_22758] = 3148, - [BNXT_ULP_CLASS_HID_2132c] = 3149, - [BNXT_ULP_CLASS_HID_25d88] = 3150, - [BNXT_ULP_CLASS_HID_256fc] = 3151, - [BNXT_ULP_CLASS_HID_24b2c] = 3152, - [BNXT_ULP_CLASS_HID_22f14] = 3153, - [BNXT_ULP_CLASS_HID_23a24] = 3154, - [BNXT_ULP_CLASS_HID_23718] = 3155, - [BNXT_ULP_CLASS_HID_22848] = 3156, - [BNXT_ULP_CLASS_HID_214dc] = 3157, - [BNXT_ULP_CLASS_HID_25eb8] = 3158, - [BNXT_ULP_CLASS_HID_25bec] = 3159, - [BNXT_ULP_CLASS_HID_21110] = 3160, - [BNXT_ULP_CLASS_HID_238b0] = 3161, - [BNXT_ULP_CLASS_HID_20440] = 3162, - [BNXT_ULP_CLASS_HID_200b4] = 3163, - [BNXT_ULP_CLASS_HID_235e4] = 3164, - [BNXT_ULP_CLASS_HID_25d04] = 3165, - [BNXT_ULP_CLASS_HID_228d4] = 3166, - [BNXT_ULP_CLASS_HID_22508] = 3167, - [BNXT_ULP_CLASS_HID_25678] = 3168, - [BNXT_ULP_CLASS_HID_229d8] = 3169, - [BNXT_ULP_CLASS_HID_234e8] = 3170, - [BNXT_ULP_CLASS_HID_231dc] = 3171, - [BNXT_ULP_CLASS_HID_2220c] = 3172, - [BNXT_ULP_CLASS_HID_24dac] = 3173, - [BNXT_ULP_CLASS_HID_2597c] = 3174, - [BNXT_ULP_CLASS_HID_255b0] = 3175, - [BNXT_ULP_CLASS_HID_246e0] = 3176, - [BNXT_ULP_CLASS_HID_23374] = 3177, - [BNXT_ULP_CLASS_HID_21e04] = 3178, - [BNXT_ULP_CLASS_HID_21b78] = 3179, - [BNXT_ULP_CLASS_HID_20fa8] = 3180, - [BNXT_ULP_CLASS_HID_257c8] = 3181, - [BNXT_ULP_CLASS_HID_22298] = 3182, - [BNXT_ULP_CLASS_HID_23fcc] = 3183, - [BNXT_ULP_CLASS_HID_2503c] = 3184, - [BNXT_ULP_CLASS_HID_2239c] = 3185, - [BNXT_ULP_CLASS_HID_20eac] = 3186, - [BNXT_ULP_CLASS_HID_20be0] = 3187, - [BNXT_ULP_CLASS_HID_23cd0] = 3188, - [BNXT_ULP_CLASS_HID_24470] = 3189, - [BNXT_ULP_CLASS_HID_25300] = 3190, - [BNXT_ULP_CLASS_HID_22c74] = 3191, - [BNXT_ULP_CLASS_HID_240a4] = 3192, - [BNXT_ULP_CLASS_HID_23da0] = 3193, - [BNXT_ULP_CLASS_HID_20970] = 3194, - [BNXT_ULP_CLASS_HID_205a4] = 3195, - [BNXT_ULP_CLASS_HID_23694] = 3196, - [BNXT_ULP_CLASS_HID_25e34] = 3197, - [BNXT_ULP_CLASS_HID_22dc4] = 3198, - [BNXT_ULP_CLASS_HID_22638] = 3199, - [BNXT_ULP_CLASS_HID_25b68] = 3200, - [BNXT_ULP_CLASS_HID_34c8] = 3201, - [BNXT_ULP_CLASS_HID_3a04] = 3202, - [BNXT_ULP_CLASS_HID_5e98] = 3203, - [BNXT_ULP_CLASS_HID_07a0] = 3204, - [BNXT_ULP_CLASS_HID_2834] = 3205, - [BNXT_ULP_CLASS_HID_595c] = 3206, - [BNXT_ULP_CLASS_HID_1e64] = 3207, - [BNXT_ULP_CLASS_HID_22f8] = 3208, - [BNXT_ULP_CLASS_HID_24664] = 3209, - [BNXT_ULP_CLASS_HID_29418] = 3210, - [BNXT_ULP_CLASS_HID_30118] = 3211, - [BNXT_ULP_CLASS_HID_38a18] = 3212, - [BNXT_ULP_CLASS_HID_255b4] = 3213, - [BNXT_ULP_CLASS_HID_2deb4] = 3214, - [BNXT_ULP_CLASS_HID_34bb4] = 3215, - [BNXT_ULP_CLASS_HID_39968] = 3216, - [BNXT_ULP_CLASS_HID_22e68] = 3217, - [BNXT_ULP_CLASS_HID_2db68] = 3218, - [BNXT_ULP_CLASS_HID_34468] = 3219, - [BNXT_ULP_CLASS_HID_3921c] = 3220, - [BNXT_ULP_CLASS_HID_24318] = 3221, - [BNXT_ULP_CLASS_HID_290cc] = 3222, - [BNXT_ULP_CLASS_HID_31dcc] = 3223, - [BNXT_ULP_CLASS_HID_386cc] = 3224, - [BNXT_ULP_CLASS_HID_20fac] = 3225, - [BNXT_ULP_CLASS_HID_2b8ac] = 3226, - [BNXT_ULP_CLASS_HID_325ac] = 3227, - [BNXT_ULP_CLASS_HID_3aeac] = 3228, - [BNXT_ULP_CLASS_HID_21afc] = 3229, - [BNXT_ULP_CLASS_HID_287fc] = 3230, - [BNXT_ULP_CLASS_HID_330fc] = 3231, - [BNXT_ULP_CLASS_HID_3bdfc] = 3232, - [BNXT_ULP_CLASS_HID_217b0] = 3233, - [BNXT_ULP_CLASS_HID_280b0] = 3234, - [BNXT_ULP_CLASS_HID_30db0] = 3235, - [BNXT_ULP_CLASS_HID_3b6b0] = 3236, - [BNXT_ULP_CLASS_HID_20860] = 3237, - [BNXT_ULP_CLASS_HID_2b560] = 3238, - [BNXT_ULP_CLASS_HID_33e60] = 3239, - [BNXT_ULP_CLASS_HID_3ab60] = 3240, - [BNXT_ULP_CLASS_HID_253c0] = 3241, - [BNXT_ULP_CLASS_HID_2dcc0] = 3242, - [BNXT_ULP_CLASS_HID_349c0] = 3243, - [BNXT_ULP_CLASS_HID_397f4] = 3244, - [BNXT_ULP_CLASS_HID_23f10] = 3245, - [BNXT_ULP_CLASS_HID_2a810] = 3246, - [BNXT_ULP_CLASS_HID_35510] = 3247, - [BNXT_ULP_CLASS_HID_3de10] = 3248, - [BNXT_ULP_CLASS_HID_23bc4] = 3249, - [BNXT_ULP_CLASS_HID_2a4c4] = 3250, - [BNXT_ULP_CLASS_HID_351c4] = 3251, - [BNXT_ULP_CLASS_HID_3dac4] = 3252, - [BNXT_ULP_CLASS_HID_22cf4] = 3253, - [BNXT_ULP_CLASS_HID_2d9f4] = 3254, - [BNXT_ULP_CLASS_HID_342f4] = 3255, - [BNXT_ULP_CLASS_HID_390a8] = 3256, - [BNXT_ULP_CLASS_HID_21908] = 3257, - [BNXT_ULP_CLASS_HID_28208] = 3258, - [BNXT_ULP_CLASS_HID_30f08] = 3259, - [BNXT_ULP_CLASS_HID_3b808] = 3260, - [BNXT_ULP_CLASS_HID_243a4] = 3261, - [BNXT_ULP_CLASS_HID_29158] = 3262, - [BNXT_ULP_CLASS_HID_31a58] = 3263, - [BNXT_ULP_CLASS_HID_38758] = 3264, - [BNXT_ULP_CLASS_HID_25c58] = 3265, - [BNXT_ULP_CLASS_HID_2c958] = 3266, - [BNXT_ULP_CLASS_HID_3170c] = 3267, - [BNXT_ULP_CLASS_HID_3800c] = 3268, - [BNXT_ULP_CLASS_HID_2123c] = 3269, - [BNXT_ULP_CLASS_HID_29f3c] = 3270, - [BNXT_ULP_CLASS_HID_3083c] = 3271, - [BNXT_ULP_CLASS_HID_3b53c] = 3272, - [BNXT_ULP_CLASS_HID_240a8] = 3273, - [BNXT_ULP_CLASS_HID_2cda8] = 3274, - [BNXT_ULP_CLASS_HID_31b5c] = 3275, - [BNXT_ULP_CLASS_HID_3845c] = 3276, - [BNXT_ULP_CLASS_HID_22ff8] = 3277, - [BNXT_ULP_CLASS_HID_2d8f8] = 3278, - [BNXT_ULP_CLASS_HID_345f8] = 3279, - [BNXT_ULP_CLASS_HID_393ac] = 3280, - [BNXT_ULP_CLASS_HID_228ac] = 3281, - [BNXT_ULP_CLASS_HID_2d5ac] = 3282, - [BNXT_ULP_CLASS_HID_35eac] = 3283, - [BNXT_ULP_CLASS_HID_3cbac] = 3284, - [BNXT_ULP_CLASS_HID_25d5c] = 3285, - [BNXT_ULP_CLASS_HID_2c65c] = 3286, - [BNXT_ULP_CLASS_HID_31410] = 3287, - [BNXT_ULP_CLASS_HID_38110] = 3288, - [BNXT_ULP_CLASS_HID_209f0] = 3289, - [BNXT_ULP_CLASS_HID_2b2f0] = 3290, - [BNXT_ULP_CLASS_HID_33ff0] = 3291, - [BNXT_ULP_CLASS_HID_3a8f0] = 3292, - [BNXT_ULP_CLASS_HID_214c0] = 3293, - [BNXT_ULP_CLASS_HID_281c0] = 3294, - [BNXT_ULP_CLASS_HID_30ac0] = 3295, - [BNXT_ULP_CLASS_HID_3b7c0] = 3296, - [BNXT_ULP_CLASS_HID_211f4] = 3297, - [BNXT_ULP_CLASS_HID_29af4] = 3298, - [BNXT_ULP_CLASS_HID_307f4] = 3299, - [BNXT_ULP_CLASS_HID_3b0f4] = 3300, - [BNXT_ULP_CLASS_HID_202a4] = 3301, - [BNXT_ULP_CLASS_HID_28fa4] = 3302, - [BNXT_ULP_CLASS_HID_338a4] = 3303, - [BNXT_ULP_CLASS_HID_3a5a4] = 3304, - [BNXT_ULP_CLASS_HID_22a04] = 3305, - [BNXT_ULP_CLASS_HID_2d704] = 3306, - [BNXT_ULP_CLASS_HID_34004] = 3307, - [BNXT_ULP_CLASS_HID_3cd04] = 3308, - [BNXT_ULP_CLASS_HID_23954] = 3309, - [BNXT_ULP_CLASS_HID_2a254] = 3310, - [BNXT_ULP_CLASS_HID_32f54] = 3311, - [BNXT_ULP_CLASS_HID_3d854] = 3312, - [BNXT_ULP_CLASS_HID_23208] = 3313, - [BNXT_ULP_CLASS_HID_2bf08] = 3314, - [BNXT_ULP_CLASS_HID_32808] = 3315, - [BNXT_ULP_CLASS_HID_3d508] = 3316, - [BNXT_ULP_CLASS_HID_22738] = 3317, - [BNXT_ULP_CLASS_HID_2d038] = 3318, - [BNXT_ULP_CLASS_HID_35d38] = 3319, - [BNXT_ULP_CLASS_HID_3c638] = 3320, - [BNXT_ULP_CLASS_HID_2134c] = 3321, - [BNXT_ULP_CLASS_HID_29c4c] = 3322, - [BNXT_ULP_CLASS_HID_3094c] = 3323, - [BNXT_ULP_CLASS_HID_3b24c] = 3324, - [BNXT_ULP_CLASS_HID_25de8] = 3325, - [BNXT_ULP_CLASS_HID_2c6e8] = 3326, - [BNXT_ULP_CLASS_HID_3149c] = 3327, - [BNXT_ULP_CLASS_HID_3819c] = 3328, - [BNXT_ULP_CLASS_HID_2569c] = 3329, - [BNXT_ULP_CLASS_HID_2c39c] = 3330, - [BNXT_ULP_CLASS_HID_31150] = 3331, - [BNXT_ULP_CLASS_HID_39a50] = 3332, - [BNXT_ULP_CLASS_HID_24b4c] = 3333, - [BNXT_ULP_CLASS_HID_29900] = 3334, - [BNXT_ULP_CLASS_HID_30200] = 3335, - [BNXT_ULP_CLASS_HID_38f00] = 3336, - [BNXT_ULP_CLASS_HID_22f74] = 3337, - [BNXT_ULP_CLASS_HID_2d874] = 3338, - [BNXT_ULP_CLASS_HID_34574] = 3339, - [BNXT_ULP_CLASS_HID_39328] = 3340, - [BNXT_ULP_CLASS_HID_23a44] = 3341, - [BNXT_ULP_CLASS_HID_2a744] = 3342, - [BNXT_ULP_CLASS_HID_35044] = 3343, - [BNXT_ULP_CLASS_HID_3dd44] = 3344, - [BNXT_ULP_CLASS_HID_23778] = 3345, - [BNXT_ULP_CLASS_HID_2a078] = 3346, - [BNXT_ULP_CLASS_HID_32d78] = 3347, - [BNXT_ULP_CLASS_HID_3d678] = 3348, - [BNXT_ULP_CLASS_HID_22828] = 3349, - [BNXT_ULP_CLASS_HID_2d528] = 3350, - [BNXT_ULP_CLASS_HID_35e28] = 3351, - [BNXT_ULP_CLASS_HID_3cb28] = 3352, - [BNXT_ULP_CLASS_HID_214bc] = 3353, - [BNXT_ULP_CLASS_HID_281bc] = 3354, - [BNXT_ULP_CLASS_HID_30abc] = 3355, - [BNXT_ULP_CLASS_HID_3b7bc] = 3356, - [BNXT_ULP_CLASS_HID_25ed8] = 3357, - [BNXT_ULP_CLASS_HID_2cbd8] = 3358, - [BNXT_ULP_CLASS_HID_3198c] = 3359, - [BNXT_ULP_CLASS_HID_3828c] = 3360, - [BNXT_ULP_CLASS_HID_25b8c] = 3361, - [BNXT_ULP_CLASS_HID_2c48c] = 3362, - [BNXT_ULP_CLASS_HID_31240] = 3363, - [BNXT_ULP_CLASS_HID_39f40] = 3364, - [BNXT_ULP_CLASS_HID_21170] = 3365, - [BNXT_ULP_CLASS_HID_29a70] = 3366, - [BNXT_ULP_CLASS_HID_30770] = 3367, - [BNXT_ULP_CLASS_HID_3b070] = 3368, - [BNXT_ULP_CLASS_HID_238d0] = 3369, - [BNXT_ULP_CLASS_HID_2a5d0] = 3370, - [BNXT_ULP_CLASS_HID_32ed0] = 3371, - [BNXT_ULP_CLASS_HID_3dbd0] = 3372, - [BNXT_ULP_CLASS_HID_20420] = 3373, - [BNXT_ULP_CLASS_HID_2b120] = 3374, - [BNXT_ULP_CLASS_HID_33a20] = 3375, - [BNXT_ULP_CLASS_HID_3a720] = 3376, - [BNXT_ULP_CLASS_HID_200d4] = 3377, - [BNXT_ULP_CLASS_HID_28dd4] = 3378, - [BNXT_ULP_CLASS_HID_336d4] = 3379, - [BNXT_ULP_CLASS_HID_3a3d4] = 3380, - [BNXT_ULP_CLASS_HID_23584] = 3381, - [BNXT_ULP_CLASS_HID_2be84] = 3382, - [BNXT_ULP_CLASS_HID_32b84] = 3383, - [BNXT_ULP_CLASS_HID_3d484] = 3384, - [BNXT_ULP_CLASS_HID_25d64] = 3385, - [BNXT_ULP_CLASS_HID_2c664] = 3386, - [BNXT_ULP_CLASS_HID_31418] = 3387, - [BNXT_ULP_CLASS_HID_38118] = 3388, - [BNXT_ULP_CLASS_HID_228b4] = 3389, - [BNXT_ULP_CLASS_HID_2d5b4] = 3390, - [BNXT_ULP_CLASS_HID_35eb4] = 3391, - [BNXT_ULP_CLASS_HID_3cbb4] = 3392, - [BNXT_ULP_CLASS_HID_22568] = 3393, - [BNXT_ULP_CLASS_HID_2ae68] = 3394, - [BNXT_ULP_CLASS_HID_35b68] = 3395, - [BNXT_ULP_CLASS_HID_3c468] = 3396, - [BNXT_ULP_CLASS_HID_25618] = 3397, - [BNXT_ULP_CLASS_HID_2c318] = 3398, - [BNXT_ULP_CLASS_HID_310cc] = 3399, - [BNXT_ULP_CLASS_HID_39dcc] = 3400, - [BNXT_ULP_CLASS_HID_229b8] = 3401, - [BNXT_ULP_CLASS_HID_2d2b8] = 3402, - [BNXT_ULP_CLASS_HID_35fb8] = 3403, - [BNXT_ULP_CLASS_HID_3c8b8] = 3404, - [BNXT_ULP_CLASS_HID_23488] = 3405, - [BNXT_ULP_CLASS_HID_2a188] = 3406, - [BNXT_ULP_CLASS_HID_32a88] = 3407, - [BNXT_ULP_CLASS_HID_3d788] = 3408, - [BNXT_ULP_CLASS_HID_231bc] = 3409, - [BNXT_ULP_CLASS_HID_2babc] = 3410, - [BNXT_ULP_CLASS_HID_327bc] = 3411, - [BNXT_ULP_CLASS_HID_3d0bc] = 3412, - [BNXT_ULP_CLASS_HID_2226c] = 3413, - [BNXT_ULP_CLASS_HID_2af6c] = 3414, - [BNXT_ULP_CLASS_HID_3586c] = 3415, - [BNXT_ULP_CLASS_HID_3c56c] = 3416, - [BNXT_ULP_CLASS_HID_24dcc] = 3417, - [BNXT_ULP_CLASS_HID_29b80] = 3418, - [BNXT_ULP_CLASS_HID_30480] = 3419, - [BNXT_ULP_CLASS_HID_3b180] = 3420, - [BNXT_ULP_CLASS_HID_2591c] = 3421, - [BNXT_ULP_CLASS_HID_2c21c] = 3422, - [BNXT_ULP_CLASS_HID_313d0] = 3423, - [BNXT_ULP_CLASS_HID_39cd0] = 3424, - [BNXT_ULP_CLASS_HID_255d0] = 3425, - [BNXT_ULP_CLASS_HID_2ded0] = 3426, - [BNXT_ULP_CLASS_HID_34bd0] = 3427, - [BNXT_ULP_CLASS_HID_39984] = 3428, - [BNXT_ULP_CLASS_HID_24680] = 3429, - [BNXT_ULP_CLASS_HID_294b4] = 3430, - [BNXT_ULP_CLASS_HID_301b4] = 3431, - [BNXT_ULP_CLASS_HID_38ab4] = 3432, - [BNXT_ULP_CLASS_HID_23314] = 3433, - [BNXT_ULP_CLASS_HID_2bc14] = 3434, - [BNXT_ULP_CLASS_HID_32914] = 3435, - [BNXT_ULP_CLASS_HID_3d214] = 3436, - [BNXT_ULP_CLASS_HID_21e64] = 3437, - [BNXT_ULP_CLASS_HID_28b64] = 3438, - [BNXT_ULP_CLASS_HID_33464] = 3439, - [BNXT_ULP_CLASS_HID_3a164] = 3440, - [BNXT_ULP_CLASS_HID_21b18] = 3441, - [BNXT_ULP_CLASS_HID_28418] = 3442, - [BNXT_ULP_CLASS_HID_33118] = 3443, - [BNXT_ULP_CLASS_HID_3ba18] = 3444, - [BNXT_ULP_CLASS_HID_20fc8] = 3445, - [BNXT_ULP_CLASS_HID_2b8c8] = 3446, - [BNXT_ULP_CLASS_HID_325c8] = 3447, - [BNXT_ULP_CLASS_HID_3aec8] = 3448, - [BNXT_ULP_CLASS_HID_257a8] = 3449, - [BNXT_ULP_CLASS_HID_2c0a8] = 3450, - [BNXT_ULP_CLASS_HID_34da8] = 3451, - [BNXT_ULP_CLASS_HID_39b5c] = 3452, - [BNXT_ULP_CLASS_HID_222f8] = 3453, - [BNXT_ULP_CLASS_HID_2aff8] = 3454, - [BNXT_ULP_CLASS_HID_358f8] = 3455, - [BNXT_ULP_CLASS_HID_3c5f8] = 3456, - [BNXT_ULP_CLASS_HID_23fac] = 3457, - [BNXT_ULP_CLASS_HID_2a8ac] = 3458, - [BNXT_ULP_CLASS_HID_355ac] = 3459, - [BNXT_ULP_CLASS_HID_3deac] = 3460, - [BNXT_ULP_CLASS_HID_2505c] = 3461, - [BNXT_ULP_CLASS_HID_2dd5c] = 3462, - [BNXT_ULP_CLASS_HID_3465c] = 3463, - [BNXT_ULP_CLASS_HID_39410] = 3464, - [BNXT_ULP_CLASS_HID_223fc] = 3465, - [BNXT_ULP_CLASS_HID_2acfc] = 3466, - [BNXT_ULP_CLASS_HID_359fc] = 3467, - [BNXT_ULP_CLASS_HID_3c2fc] = 3468, - [BNXT_ULP_CLASS_HID_20ecc] = 3469, - [BNXT_ULP_CLASS_HID_2bbcc] = 3470, - [BNXT_ULP_CLASS_HID_324cc] = 3471, - [BNXT_ULP_CLASS_HID_3d1cc] = 3472, - [BNXT_ULP_CLASS_HID_20b80] = 3473, - [BNXT_ULP_CLASS_HID_2b480] = 3474, - [BNXT_ULP_CLASS_HID_32180] = 3475, - [BNXT_ULP_CLASS_HID_3aa80] = 3476, - [BNXT_ULP_CLASS_HID_23cb0] = 3477, - [BNXT_ULP_CLASS_HID_2a9b0] = 3478, - [BNXT_ULP_CLASS_HID_352b0] = 3479, - [BNXT_ULP_CLASS_HID_3dfb0] = 3480, - [BNXT_ULP_CLASS_HID_24410] = 3481, - [BNXT_ULP_CLASS_HID_295c4] = 3482, - [BNXT_ULP_CLASS_HID_31ec4] = 3483, - [BNXT_ULP_CLASS_HID_38bc4] = 3484, - [BNXT_ULP_CLASS_HID_25360] = 3485, - [BNXT_ULP_CLASS_HID_2dc60] = 3486, - [BNXT_ULP_CLASS_HID_34960] = 3487, - [BNXT_ULP_CLASS_HID_39714] = 3488, - [BNXT_ULP_CLASS_HID_22c14] = 3489, - [BNXT_ULP_CLASS_HID_2d914] = 3490, - [BNXT_ULP_CLASS_HID_34214] = 3491, - [BNXT_ULP_CLASS_HID_393c8] = 3492, - [BNXT_ULP_CLASS_HID_240c4] = 3493, - [BNXT_ULP_CLASS_HID_2cdc4] = 3494, - [BNXT_ULP_CLASS_HID_31bf8] = 3495, - [BNXT_ULP_CLASS_HID_384f8] = 3496, - [BNXT_ULP_CLASS_HID_23dc0] = 3497, - [BNXT_ULP_CLASS_HID_2a6c0] = 3498, - [BNXT_ULP_CLASS_HID_353c0] = 3499, - [BNXT_ULP_CLASS_HID_3dcc0] = 3500, - [BNXT_ULP_CLASS_HID_20910] = 3501, - [BNXT_ULP_CLASS_HID_2b210] = 3502, - [BNXT_ULP_CLASS_HID_33f10] = 3503, - [BNXT_ULP_CLASS_HID_3a810] = 3504, - [BNXT_ULP_CLASS_HID_205c4] = 3505, - [BNXT_ULP_CLASS_HID_28ec4] = 3506, - [BNXT_ULP_CLASS_HID_33bc4] = 3507, - [BNXT_ULP_CLASS_HID_3a4c4] = 3508, - [BNXT_ULP_CLASS_HID_236f4] = 3509, - [BNXT_ULP_CLASS_HID_2a3f4] = 3510, - [BNXT_ULP_CLASS_HID_32cf4] = 3511, - [BNXT_ULP_CLASS_HID_3d9f4] = 3512, - [BNXT_ULP_CLASS_HID_25e54] = 3513, - [BNXT_ULP_CLASS_HID_2cb54] = 3514, - [BNXT_ULP_CLASS_HID_31908] = 3515, - [BNXT_ULP_CLASS_HID_38208] = 3516, - [BNXT_ULP_CLASS_HID_22da4] = 3517, - [BNXT_ULP_CLASS_HID_2d6a4] = 3518, - [BNXT_ULP_CLASS_HID_343a4] = 3519, - [BNXT_ULP_CLASS_HID_39158] = 3520, - [BNXT_ULP_CLASS_HID_22658] = 3521, - [BNXT_ULP_CLASS_HID_2d358] = 3522, - [BNXT_ULP_CLASS_HID_35c58] = 3523, - [BNXT_ULP_CLASS_HID_3c958] = 3524, - [BNXT_ULP_CLASS_HID_25b08] = 3525, - [BNXT_ULP_CLASS_HID_2c408] = 3526, - [BNXT_ULP_CLASS_HID_3123c] = 3527, - [BNXT_ULP_CLASS_HID_39f3c] = 3528, - [BNXT_ULP_CLASS_HID_34a8] = 3529, - [BNXT_ULP_CLASS_HID_3a64] = 3530, - [BNXT_ULP_CLASS_HID_5ef8] = 3531, - [BNXT_ULP_CLASS_HID_07c0] = 3532, - [BNXT_ULP_CLASS_HID_2854] = 3533, - [BNXT_ULP_CLASS_HID_593c] = 3534, - [BNXT_ULP_CLASS_HID_1e04] = 3535, - [BNXT_ULP_CLASS_HID_2298] = 3536, - [BNXT_ULP_CLASS_HID_24644] = 3537, - [BNXT_ULP_CLASS_HID_29438] = 3538, - [BNXT_ULP_CLASS_HID_30138] = 3539, - [BNXT_ULP_CLASS_HID_38a38] = 3540, - [BNXT_ULP_CLASS_HID_25594] = 3541, - [BNXT_ULP_CLASS_HID_2de94] = 3542, - [BNXT_ULP_CLASS_HID_34b94] = 3543, - [BNXT_ULP_CLASS_HID_39948] = 3544, - [BNXT_ULP_CLASS_HID_22e48] = 3545, - [BNXT_ULP_CLASS_HID_2db48] = 3546, - [BNXT_ULP_CLASS_HID_34448] = 3547, - [BNXT_ULP_CLASS_HID_3923c] = 3548, - [BNXT_ULP_CLASS_HID_24338] = 3549, - [BNXT_ULP_CLASS_HID_290ec] = 3550, - [BNXT_ULP_CLASS_HID_31dec] = 3551, - [BNXT_ULP_CLASS_HID_386ec] = 3552, - [BNXT_ULP_CLASS_HID_20f8c] = 3553, - [BNXT_ULP_CLASS_HID_2b88c] = 3554, - [BNXT_ULP_CLASS_HID_3258c] = 3555, - [BNXT_ULP_CLASS_HID_3ae8c] = 3556, - [BNXT_ULP_CLASS_HID_21adc] = 3557, - [BNXT_ULP_CLASS_HID_287dc] = 3558, - [BNXT_ULP_CLASS_HID_330dc] = 3559, - [BNXT_ULP_CLASS_HID_3bddc] = 3560, - [BNXT_ULP_CLASS_HID_21790] = 3561, - [BNXT_ULP_CLASS_HID_28090] = 3562, - [BNXT_ULP_CLASS_HID_30d90] = 3563, - [BNXT_ULP_CLASS_HID_3b690] = 3564, - [BNXT_ULP_CLASS_HID_20840] = 3565, - [BNXT_ULP_CLASS_HID_2b540] = 3566, - [BNXT_ULP_CLASS_HID_33e40] = 3567, - [BNXT_ULP_CLASS_HID_3ab40] = 3568, - [BNXT_ULP_CLASS_HID_253e0] = 3569, - [BNXT_ULP_CLASS_HID_2dce0] = 3570, - [BNXT_ULP_CLASS_HID_349e0] = 3571, - [BNXT_ULP_CLASS_HID_397d4] = 3572, - [BNXT_ULP_CLASS_HID_23f30] = 3573, - [BNXT_ULP_CLASS_HID_2a830] = 3574, - [BNXT_ULP_CLASS_HID_35530] = 3575, - [BNXT_ULP_CLASS_HID_3de30] = 3576, - [BNXT_ULP_CLASS_HID_23be4] = 3577, - [BNXT_ULP_CLASS_HID_2a4e4] = 3578, - [BNXT_ULP_CLASS_HID_351e4] = 3579, - [BNXT_ULP_CLASS_HID_3dae4] = 3580, - [BNXT_ULP_CLASS_HID_22cd4] = 3581, - [BNXT_ULP_CLASS_HID_2d9d4] = 3582, - [BNXT_ULP_CLASS_HID_342d4] = 3583, - [BNXT_ULP_CLASS_HID_39088] = 3584, - [BNXT_ULP_CLASS_HID_21928] = 3585, - [BNXT_ULP_CLASS_HID_28228] = 3586, - [BNXT_ULP_CLASS_HID_30f28] = 3587, - [BNXT_ULP_CLASS_HID_3b828] = 3588, - [BNXT_ULP_CLASS_HID_24384] = 3589, - [BNXT_ULP_CLASS_HID_29178] = 3590, - [BNXT_ULP_CLASS_HID_31a78] = 3591, - [BNXT_ULP_CLASS_HID_38778] = 3592, - [BNXT_ULP_CLASS_HID_25c78] = 3593, - [BNXT_ULP_CLASS_HID_2c978] = 3594, - [BNXT_ULP_CLASS_HID_3172c] = 3595, - [BNXT_ULP_CLASS_HID_3802c] = 3596, - [BNXT_ULP_CLASS_HID_2121c] = 3597, - [BNXT_ULP_CLASS_HID_29f1c] = 3598, - [BNXT_ULP_CLASS_HID_3081c] = 3599, - [BNXT_ULP_CLASS_HID_3b51c] = 3600, - [BNXT_ULP_CLASS_HID_24088] = 3601, - [BNXT_ULP_CLASS_HID_2cd88] = 3602, - [BNXT_ULP_CLASS_HID_31b7c] = 3603, - [BNXT_ULP_CLASS_HID_3847c] = 3604, - [BNXT_ULP_CLASS_HID_22fd8] = 3605, - [BNXT_ULP_CLASS_HID_2d8d8] = 3606, - [BNXT_ULP_CLASS_HID_345d8] = 3607, - [BNXT_ULP_CLASS_HID_3938c] = 3608, - [BNXT_ULP_CLASS_HID_2288c] = 3609, - [BNXT_ULP_CLASS_HID_2d58c] = 3610, - [BNXT_ULP_CLASS_HID_35e8c] = 3611, - [BNXT_ULP_CLASS_HID_3cb8c] = 3612, - [BNXT_ULP_CLASS_HID_25d7c] = 3613, - [BNXT_ULP_CLASS_HID_2c67c] = 3614, - [BNXT_ULP_CLASS_HID_31430] = 3615, - [BNXT_ULP_CLASS_HID_38130] = 3616, - [BNXT_ULP_CLASS_HID_209d0] = 3617, - [BNXT_ULP_CLASS_HID_2b2d0] = 3618, - [BNXT_ULP_CLASS_HID_33fd0] = 3619, - [BNXT_ULP_CLASS_HID_3a8d0] = 3620, - [BNXT_ULP_CLASS_HID_214e0] = 3621, - [BNXT_ULP_CLASS_HID_281e0] = 3622, - [BNXT_ULP_CLASS_HID_30ae0] = 3623, - [BNXT_ULP_CLASS_HID_3b7e0] = 3624, - [BNXT_ULP_CLASS_HID_211d4] = 3625, - [BNXT_ULP_CLASS_HID_29ad4] = 3626, - [BNXT_ULP_CLASS_HID_307d4] = 3627, - [BNXT_ULP_CLASS_HID_3b0d4] = 3628, - [BNXT_ULP_CLASS_HID_20284] = 3629, - [BNXT_ULP_CLASS_HID_28f84] = 3630, - [BNXT_ULP_CLASS_HID_33884] = 3631, - [BNXT_ULP_CLASS_HID_3a584] = 3632, - [BNXT_ULP_CLASS_HID_22a24] = 3633, - [BNXT_ULP_CLASS_HID_2d724] = 3634, - [BNXT_ULP_CLASS_HID_34024] = 3635, - [BNXT_ULP_CLASS_HID_3cd24] = 3636, - [BNXT_ULP_CLASS_HID_23974] = 3637, - [BNXT_ULP_CLASS_HID_2a274] = 3638, - [BNXT_ULP_CLASS_HID_32f74] = 3639, - [BNXT_ULP_CLASS_HID_3d874] = 3640, - [BNXT_ULP_CLASS_HID_23228] = 3641, - [BNXT_ULP_CLASS_HID_2bf28] = 3642, - [BNXT_ULP_CLASS_HID_32828] = 3643, - [BNXT_ULP_CLASS_HID_3d528] = 3644, - [BNXT_ULP_CLASS_HID_22718] = 3645, - [BNXT_ULP_CLASS_HID_2d018] = 3646, - [BNXT_ULP_CLASS_HID_35d18] = 3647, - [BNXT_ULP_CLASS_HID_3c618] = 3648, - [BNXT_ULP_CLASS_HID_2136c] = 3649, - [BNXT_ULP_CLASS_HID_29c6c] = 3650, - [BNXT_ULP_CLASS_HID_3096c] = 3651, - [BNXT_ULP_CLASS_HID_3b26c] = 3652, - [BNXT_ULP_CLASS_HID_25dc8] = 3653, - [BNXT_ULP_CLASS_HID_2c6c8] = 3654, - [BNXT_ULP_CLASS_HID_314bc] = 3655, - [BNXT_ULP_CLASS_HID_381bc] = 3656, - [BNXT_ULP_CLASS_HID_256bc] = 3657, - [BNXT_ULP_CLASS_HID_2c3bc] = 3658, - [BNXT_ULP_CLASS_HID_31170] = 3659, - [BNXT_ULP_CLASS_HID_39a70] = 3660, - [BNXT_ULP_CLASS_HID_24b6c] = 3661, - [BNXT_ULP_CLASS_HID_29920] = 3662, - [BNXT_ULP_CLASS_HID_30220] = 3663, - [BNXT_ULP_CLASS_HID_38f20] = 3664, - [BNXT_ULP_CLASS_HID_22f54] = 3665, - [BNXT_ULP_CLASS_HID_2d854] = 3666, - [BNXT_ULP_CLASS_HID_34554] = 3667, - [BNXT_ULP_CLASS_HID_39308] = 3668, - [BNXT_ULP_CLASS_HID_23a64] = 3669, - [BNXT_ULP_CLASS_HID_2a764] = 3670, - [BNXT_ULP_CLASS_HID_35064] = 3671, - [BNXT_ULP_CLASS_HID_3dd64] = 3672, - [BNXT_ULP_CLASS_HID_23758] = 3673, - [BNXT_ULP_CLASS_HID_2a058] = 3674, - [BNXT_ULP_CLASS_HID_32d58] = 3675, - [BNXT_ULP_CLASS_HID_3d658] = 3676, - [BNXT_ULP_CLASS_HID_22808] = 3677, - [BNXT_ULP_CLASS_HID_2d508] = 3678, - [BNXT_ULP_CLASS_HID_35e08] = 3679, - [BNXT_ULP_CLASS_HID_3cb08] = 3680, - [BNXT_ULP_CLASS_HID_2149c] = 3681, - [BNXT_ULP_CLASS_HID_2819c] = 3682, - [BNXT_ULP_CLASS_HID_30a9c] = 3683, - [BNXT_ULP_CLASS_HID_3b79c] = 3684, - [BNXT_ULP_CLASS_HID_25ef8] = 3685, - [BNXT_ULP_CLASS_HID_2cbf8] = 3686, - [BNXT_ULP_CLASS_HID_319ac] = 3687, - [BNXT_ULP_CLASS_HID_382ac] = 3688, - [BNXT_ULP_CLASS_HID_25bac] = 3689, - [BNXT_ULP_CLASS_HID_2c4ac] = 3690, - [BNXT_ULP_CLASS_HID_31260] = 3691, - [BNXT_ULP_CLASS_HID_39f60] = 3692, - [BNXT_ULP_CLASS_HID_21150] = 3693, - [BNXT_ULP_CLASS_HID_29a50] = 3694, - [BNXT_ULP_CLASS_HID_30750] = 3695, - [BNXT_ULP_CLASS_HID_3b050] = 3696, - [BNXT_ULP_CLASS_HID_238f0] = 3697, - [BNXT_ULP_CLASS_HID_2a5f0] = 3698, - [BNXT_ULP_CLASS_HID_32ef0] = 3699, - [BNXT_ULP_CLASS_HID_3dbf0] = 3700, - [BNXT_ULP_CLASS_HID_20400] = 3701, - [BNXT_ULP_CLASS_HID_2b100] = 3702, - [BNXT_ULP_CLASS_HID_33a00] = 3703, - [BNXT_ULP_CLASS_HID_3a700] = 3704, - [BNXT_ULP_CLASS_HID_200f4] = 3705, - [BNXT_ULP_CLASS_HID_28df4] = 3706, - [BNXT_ULP_CLASS_HID_336f4] = 3707, - [BNXT_ULP_CLASS_HID_3a3f4] = 3708, - [BNXT_ULP_CLASS_HID_235a4] = 3709, - [BNXT_ULP_CLASS_HID_2bea4] = 3710, - [BNXT_ULP_CLASS_HID_32ba4] = 3711, - [BNXT_ULP_CLASS_HID_3d4a4] = 3712, - [BNXT_ULP_CLASS_HID_25d44] = 3713, - [BNXT_ULP_CLASS_HID_2c644] = 3714, - [BNXT_ULP_CLASS_HID_31438] = 3715, - [BNXT_ULP_CLASS_HID_38138] = 3716, - [BNXT_ULP_CLASS_HID_22894] = 3717, - [BNXT_ULP_CLASS_HID_2d594] = 3718, - [BNXT_ULP_CLASS_HID_35e94] = 3719, - [BNXT_ULP_CLASS_HID_3cb94] = 3720, - [BNXT_ULP_CLASS_HID_22548] = 3721, - [BNXT_ULP_CLASS_HID_2ae48] = 3722, - [BNXT_ULP_CLASS_HID_35b48] = 3723, - [BNXT_ULP_CLASS_HID_3c448] = 3724, - [BNXT_ULP_CLASS_HID_25638] = 3725, - [BNXT_ULP_CLASS_HID_2c338] = 3726, - [BNXT_ULP_CLASS_HID_310ec] = 3727, - [BNXT_ULP_CLASS_HID_39dec] = 3728, - [BNXT_ULP_CLASS_HID_22998] = 3729, - [BNXT_ULP_CLASS_HID_2d298] = 3730, - [BNXT_ULP_CLASS_HID_35f98] = 3731, - [BNXT_ULP_CLASS_HID_3c898] = 3732, - [BNXT_ULP_CLASS_HID_234a8] = 3733, - [BNXT_ULP_CLASS_HID_2a1a8] = 3734, - [BNXT_ULP_CLASS_HID_32aa8] = 3735, - [BNXT_ULP_CLASS_HID_3d7a8] = 3736, - [BNXT_ULP_CLASS_HID_2319c] = 3737, - [BNXT_ULP_CLASS_HID_2ba9c] = 3738, - [BNXT_ULP_CLASS_HID_3279c] = 3739, - [BNXT_ULP_CLASS_HID_3d09c] = 3740, - [BNXT_ULP_CLASS_HID_2224c] = 3741, - [BNXT_ULP_CLASS_HID_2af4c] = 3742, - [BNXT_ULP_CLASS_HID_3584c] = 3743, - [BNXT_ULP_CLASS_HID_3c54c] = 3744, - [BNXT_ULP_CLASS_HID_24dec] = 3745, - [BNXT_ULP_CLASS_HID_29ba0] = 3746, - [BNXT_ULP_CLASS_HID_304a0] = 3747, - [BNXT_ULP_CLASS_HID_3b1a0] = 3748, - [BNXT_ULP_CLASS_HID_2593c] = 3749, - [BNXT_ULP_CLASS_HID_2c23c] = 3750, - [BNXT_ULP_CLASS_HID_313f0] = 3751, - [BNXT_ULP_CLASS_HID_39cf0] = 3752, - [BNXT_ULP_CLASS_HID_255f0] = 3753, - [BNXT_ULP_CLASS_HID_2def0] = 3754, - [BNXT_ULP_CLASS_HID_34bf0] = 3755, - [BNXT_ULP_CLASS_HID_399a4] = 3756, - [BNXT_ULP_CLASS_HID_246a0] = 3757, - [BNXT_ULP_CLASS_HID_29494] = 3758, - [BNXT_ULP_CLASS_HID_30194] = 3759, - [BNXT_ULP_CLASS_HID_38a94] = 3760, - [BNXT_ULP_CLASS_HID_23334] = 3761, - [BNXT_ULP_CLASS_HID_2bc34] = 3762, - [BNXT_ULP_CLASS_HID_32934] = 3763, - [BNXT_ULP_CLASS_HID_3d234] = 3764, - [BNXT_ULP_CLASS_HID_21e44] = 3765, - [BNXT_ULP_CLASS_HID_28b44] = 3766, - [BNXT_ULP_CLASS_HID_33444] = 3767, - [BNXT_ULP_CLASS_HID_3a144] = 3768, - [BNXT_ULP_CLASS_HID_21b38] = 3769, - [BNXT_ULP_CLASS_HID_28438] = 3770, - [BNXT_ULP_CLASS_HID_33138] = 3771, - [BNXT_ULP_CLASS_HID_3ba38] = 3772, - [BNXT_ULP_CLASS_HID_20fe8] = 3773, - [BNXT_ULP_CLASS_HID_2b8e8] = 3774, - [BNXT_ULP_CLASS_HID_325e8] = 3775, - [BNXT_ULP_CLASS_HID_3aee8] = 3776, - [BNXT_ULP_CLASS_HID_25788] = 3777, - [BNXT_ULP_CLASS_HID_2c088] = 3778, - [BNXT_ULP_CLASS_HID_34d88] = 3779, - [BNXT_ULP_CLASS_HID_39b7c] = 3780, - [BNXT_ULP_CLASS_HID_222d8] = 3781, - [BNXT_ULP_CLASS_HID_2afd8] = 3782, - [BNXT_ULP_CLASS_HID_358d8] = 3783, - [BNXT_ULP_CLASS_HID_3c5d8] = 3784, - [BNXT_ULP_CLASS_HID_23f8c] = 3785, - [BNXT_ULP_CLASS_HID_2a88c] = 3786, - [BNXT_ULP_CLASS_HID_3558c] = 3787, - [BNXT_ULP_CLASS_HID_3de8c] = 3788, - [BNXT_ULP_CLASS_HID_2507c] = 3789, - [BNXT_ULP_CLASS_HID_2dd7c] = 3790, - [BNXT_ULP_CLASS_HID_3467c] = 3791, - [BNXT_ULP_CLASS_HID_39430] = 3792, - [BNXT_ULP_CLASS_HID_223dc] = 3793, - [BNXT_ULP_CLASS_HID_2acdc] = 3794, - [BNXT_ULP_CLASS_HID_359dc] = 3795, - [BNXT_ULP_CLASS_HID_3c2dc] = 3796, - [BNXT_ULP_CLASS_HID_20eec] = 3797, - [BNXT_ULP_CLASS_HID_2bbec] = 3798, - [BNXT_ULP_CLASS_HID_324ec] = 3799, - [BNXT_ULP_CLASS_HID_3d1ec] = 3800, - [BNXT_ULP_CLASS_HID_20ba0] = 3801, - [BNXT_ULP_CLASS_HID_2b4a0] = 3802, - [BNXT_ULP_CLASS_HID_321a0] = 3803, - [BNXT_ULP_CLASS_HID_3aaa0] = 3804, - [BNXT_ULP_CLASS_HID_23c90] = 3805, - [BNXT_ULP_CLASS_HID_2a990] = 3806, - [BNXT_ULP_CLASS_HID_35290] = 3807, - [BNXT_ULP_CLASS_HID_3df90] = 3808, - [BNXT_ULP_CLASS_HID_24430] = 3809, - [BNXT_ULP_CLASS_HID_295e4] = 3810, - [BNXT_ULP_CLASS_HID_31ee4] = 3811, - [BNXT_ULP_CLASS_HID_38be4] = 3812, - [BNXT_ULP_CLASS_HID_25340] = 3813, - [BNXT_ULP_CLASS_HID_2dc40] = 3814, - [BNXT_ULP_CLASS_HID_34940] = 3815, - [BNXT_ULP_CLASS_HID_39734] = 3816, - [BNXT_ULP_CLASS_HID_22c34] = 3817, - [BNXT_ULP_CLASS_HID_2d934] = 3818, - [BNXT_ULP_CLASS_HID_34234] = 3819, - [BNXT_ULP_CLASS_HID_393e8] = 3820, - [BNXT_ULP_CLASS_HID_240e4] = 3821, - [BNXT_ULP_CLASS_HID_2cde4] = 3822, - [BNXT_ULP_CLASS_HID_31bd8] = 3823, - [BNXT_ULP_CLASS_HID_384d8] = 3824, - [BNXT_ULP_CLASS_HID_23de0] = 3825, - [BNXT_ULP_CLASS_HID_2a6e0] = 3826, - [BNXT_ULP_CLASS_HID_353e0] = 3827, - [BNXT_ULP_CLASS_HID_3dce0] = 3828, - [BNXT_ULP_CLASS_HID_20930] = 3829, - [BNXT_ULP_CLASS_HID_2b230] = 3830, - [BNXT_ULP_CLASS_HID_33f30] = 3831, - [BNXT_ULP_CLASS_HID_3a830] = 3832, - [BNXT_ULP_CLASS_HID_205e4] = 3833, - [BNXT_ULP_CLASS_HID_28ee4] = 3834, - [BNXT_ULP_CLASS_HID_33be4] = 3835, - [BNXT_ULP_CLASS_HID_3a4e4] = 3836, - [BNXT_ULP_CLASS_HID_236d4] = 3837, - [BNXT_ULP_CLASS_HID_2a3d4] = 3838, - [BNXT_ULP_CLASS_HID_32cd4] = 3839, - [BNXT_ULP_CLASS_HID_3d9d4] = 3840, - [BNXT_ULP_CLASS_HID_25e74] = 3841, - [BNXT_ULP_CLASS_HID_2cb74] = 3842, - [BNXT_ULP_CLASS_HID_31928] = 3843, - [BNXT_ULP_CLASS_HID_38228] = 3844, - [BNXT_ULP_CLASS_HID_22d84] = 3845, - [BNXT_ULP_CLASS_HID_2d684] = 3846, - [BNXT_ULP_CLASS_HID_34384] = 3847, - [BNXT_ULP_CLASS_HID_39178] = 3848, - [BNXT_ULP_CLASS_HID_22678] = 3849, - [BNXT_ULP_CLASS_HID_2d378] = 3850, - [BNXT_ULP_CLASS_HID_35c78] = 3851, - [BNXT_ULP_CLASS_HID_3c978] = 3852, - [BNXT_ULP_CLASS_HID_25b28] = 3853, - [BNXT_ULP_CLASS_HID_2c428] = 3854, - [BNXT_ULP_CLASS_HID_3121c] = 3855, - [BNXT_ULP_CLASS_HID_39f1c] = 3856, - [BNXT_ULP_CLASS_HID_3488] = 3857, - [BNXT_ULP_CLASS_HID_3a44] = 3858, - [BNXT_ULP_CLASS_HID_5ed8] = 3859, - [BNXT_ULP_CLASS_HID_07e0] = 3860, - [BNXT_ULP_CLASS_HID_2874] = 3861, - [BNXT_ULP_CLASS_HID_591c] = 3862, - [BNXT_ULP_CLASS_HID_1e24] = 3863, - [BNXT_ULP_CLASS_HID_22b8] = 3864 + [BNXT_ULP_CLASS_HID_054d] = 27, + [BNXT_ULP_CLASS_HID_5bdd] = 28, + [BNXT_ULP_CLASS_HID_26f1] = 29, + [BNXT_ULP_CLASS_HID_13cf1] = 30, + [BNXT_ULP_CLASS_HID_252f1] = 31, + [BNXT_ULP_CLASS_HID_30c25] = 32, + [BNXT_ULP_CLASS_HID_0051] = 33, + [BNXT_ULP_CLASS_HID_11651] = 34, + [BNXT_ULP_CLASS_HID_22c51] = 35, + [BNXT_ULP_CLASS_HID_34251] = 36, + [BNXT_ULP_CLASS_HID_5385] = 37, + [BNXT_ULP_CLASS_HID_10cc9] = 38, + [BNXT_ULP_CLASS_HID_222c9] = 39, + [BNXT_ULP_CLASS_HID_338c9] = 40, + [BNXT_ULP_CLASS_HID_1d69] = 41, + [BNXT_ULP_CLASS_HID_13369] = 42, + [BNXT_ULP_CLASS_HID_24969] = 43, + [BNXT_ULP_CLASS_HID_3025d] = 44, + [BNXT_ULP_CLASS_HID_20b5] = 45, + [BNXT_ULP_CLASS_HID_136b5] = 46, + [BNXT_ULP_CLASS_HID_24cb5] = 47, + [BNXT_ULP_CLASS_HID_305f9] = 48, + [BNXT_ULP_CLASS_HID_5721] = 49, + [BNXT_ULP_CLASS_HID_11015] = 50, + [BNXT_ULP_CLASS_HID_22615] = 51, + [BNXT_ULP_CLASS_HID_33c15] = 52, + [BNXT_ULP_CLASS_HID_4d59] = 53, + [BNXT_ULP_CLASS_HID_1068d] = 54, + [BNXT_ULP_CLASS_HID_21c8d] = 55, + [BNXT_ULP_CLASS_HID_3328d] = 56, + [BNXT_ULP_CLASS_HID_172d] = 57, + [BNXT_ULP_CLASS_HID_12d2d] = 58, + [BNXT_ULP_CLASS_HID_2432d] = 59, + [BNXT_ULP_CLASS_HID_3592d] = 60, + [BNXT_ULP_CLASS_HID_1a49] = 61, + [BNXT_ULP_CLASS_HID_13049] = 62, + [BNXT_ULP_CLASS_HID_24649] = 63, + [BNXT_ULP_CLASS_HID_35c49] = 64, + [BNXT_ULP_CLASS_HID_50e5] = 65, + [BNXT_ULP_CLASS_HID_10a29] = 66, + [BNXT_ULP_CLASS_HID_22029] = 67, + [BNXT_ULP_CLASS_HID_33629] = 68, + [BNXT_ULP_CLASS_HID_471d] = 69, + [BNXT_ULP_CLASS_HID_10041] = 70, + [BNXT_ULP_CLASS_HID_21641] = 71, + [BNXT_ULP_CLASS_HID_32c41] = 72, + [BNXT_ULP_CLASS_HID_10e1] = 73, + [BNXT_ULP_CLASS_HID_126e1] = 74, + [BNXT_ULP_CLASS_HID_23ce1] = 75, + [BNXT_ULP_CLASS_HID_352e1] = 76, + [BNXT_ULP_CLASS_HID_140d] = 77, + [BNXT_ULP_CLASS_HID_12a0d] = 78, + [BNXT_ULP_CLASS_HID_2400d] = 79, + [BNXT_ULP_CLASS_HID_3560d] = 80, + [BNXT_ULP_CLASS_HID_4ab9] = 81, + [BNXT_ULP_CLASS_HID_103ed] = 82, + [BNXT_ULP_CLASS_HID_219ed] = 83, + [BNXT_ULP_CLASS_HID_32fed] = 84, + [BNXT_ULP_CLASS_HID_40d1] = 85, + [BNXT_ULP_CLASS_HID_156d1] = 86, + [BNXT_ULP_CLASS_HID_21005] = 87, + [BNXT_ULP_CLASS_HID_32605] = 88, + [BNXT_ULP_CLASS_HID_0aa5] = 89, + [BNXT_ULP_CLASS_HID_120a5] = 90, + [BNXT_ULP_CLASS_HID_236a5] = 91, + [BNXT_ULP_CLASS_HID_34ca5] = 92, + [BNXT_ULP_CLASS_HID_0159] = 93, + [BNXT_ULP_CLASS_HID_11759] = 94, + [BNXT_ULP_CLASS_HID_22d59] = 95, + [BNXT_ULP_CLASS_HID_34359] = 96, + [BNXT_ULP_CLASS_HID_37f5] = 97, + [BNXT_ULP_CLASS_HID_14df5] = 98, + [BNXT_ULP_CLASS_HID_20739] = 99, + [BNXT_ULP_CLASS_HID_31d39] = 100, + [BNXT_ULP_CLASS_HID_2e6d] = 101, + [BNXT_ULP_CLASS_HID_1446d] = 102, + [BNXT_ULP_CLASS_HID_25a6d] = 103, + [BNXT_ULP_CLASS_HID_31351] = 104, + [BNXT_ULP_CLASS_HID_548d] = 105, + [BNXT_ULP_CLASS_HID_10df1] = 106, + [BNXT_ULP_CLASS_HID_223f1] = 107, + [BNXT_ULP_CLASS_HID_339f1] = 108, + [BNXT_ULP_CLASS_HID_5829] = 109, + [BNXT_ULP_CLASS_HID_1111d] = 110, + [BNXT_ULP_CLASS_HID_2271d] = 111, + [BNXT_ULP_CLASS_HID_33d1d] = 112, + [BNXT_ULP_CLASS_HID_3189] = 113, + [BNXT_ULP_CLASS_HID_14789] = 114, + [BNXT_ULP_CLASS_HID_200fd] = 115, + [BNXT_ULP_CLASS_HID_316fd] = 116, + [BNXT_ULP_CLASS_HID_2821] = 117, + [BNXT_ULP_CLASS_HID_13e21] = 118, + [BNXT_ULP_CLASS_HID_25421] = 119, + [BNXT_ULP_CLASS_HID_30d15] = 120, + [BNXT_ULP_CLASS_HID_4e41] = 121, + [BNXT_ULP_CLASS_HID_107b5] = 122, + [BNXT_ULP_CLASS_HID_21db5] = 123, + [BNXT_ULP_CLASS_HID_333b5] = 124, + [BNXT_ULP_CLASS_HID_2541] = 125, + [BNXT_ULP_CLASS_HID_2b8d] = 126, + [BNXT_ULP_CLASS_HID_056d] = 127, + [BNXT_ULP_CLASS_HID_5bfd] = 128, + [BNXT_ULP_CLASS_HID_2691] = 129, + [BNXT_ULP_CLASS_HID_13c91] = 130, + [BNXT_ULP_CLASS_HID_25291] = 131, + [BNXT_ULP_CLASS_HID_30c45] = 132, + [BNXT_ULP_CLASS_HID_0031] = 133, + [BNXT_ULP_CLASS_HID_11631] = 134, + [BNXT_ULP_CLASS_HID_22c31] = 135, + [BNXT_ULP_CLASS_HID_34231] = 136, + [BNXT_ULP_CLASS_HID_53e5] = 137, + [BNXT_ULP_CLASS_HID_10ca9] = 138, + [BNXT_ULP_CLASS_HID_222a9] = 139, + [BNXT_ULP_CLASS_HID_338a9] = 140, + [BNXT_ULP_CLASS_HID_1d09] = 141, + [BNXT_ULP_CLASS_HID_13309] = 142, + [BNXT_ULP_CLASS_HID_24909] = 143, + [BNXT_ULP_CLASS_HID_3023d] = 144, + [BNXT_ULP_CLASS_HID_20d5] = 145, + [BNXT_ULP_CLASS_HID_136d5] = 146, + [BNXT_ULP_CLASS_HID_24cd5] = 147, + [BNXT_ULP_CLASS_HID_30599] = 148, + [BNXT_ULP_CLASS_HID_5741] = 149, + [BNXT_ULP_CLASS_HID_11075] = 150, + [BNXT_ULP_CLASS_HID_22675] = 151, + [BNXT_ULP_CLASS_HID_33c75] = 152, + [BNXT_ULP_CLASS_HID_4d39] = 153, + [BNXT_ULP_CLASS_HID_106ed] = 154, + [BNXT_ULP_CLASS_HID_21ced] = 155, + [BNXT_ULP_CLASS_HID_332ed] = 156, + [BNXT_ULP_CLASS_HID_174d] = 157, + [BNXT_ULP_CLASS_HID_12d4d] = 158, + [BNXT_ULP_CLASS_HID_2434d] = 159, + [BNXT_ULP_CLASS_HID_3594d] = 160, + [BNXT_ULP_CLASS_HID_1a29] = 161, + [BNXT_ULP_CLASS_HID_13029] = 162, + [BNXT_ULP_CLASS_HID_24629] = 163, + [BNXT_ULP_CLASS_HID_35c29] = 164, + [BNXT_ULP_CLASS_HID_5085] = 165, + [BNXT_ULP_CLASS_HID_10a49] = 166, + [BNXT_ULP_CLASS_HID_22049] = 167, + [BNXT_ULP_CLASS_HID_33649] = 168, + [BNXT_ULP_CLASS_HID_477d] = 169, + [BNXT_ULP_CLASS_HID_10021] = 170, + [BNXT_ULP_CLASS_HID_21621] = 171, + [BNXT_ULP_CLASS_HID_32c21] = 172, + [BNXT_ULP_CLASS_HID_1081] = 173, + [BNXT_ULP_CLASS_HID_12681] = 174, + [BNXT_ULP_CLASS_HID_23c81] = 175, + [BNXT_ULP_CLASS_HID_35281] = 176, + [BNXT_ULP_CLASS_HID_146d] = 177, + [BNXT_ULP_CLASS_HID_12a6d] = 178, + [BNXT_ULP_CLASS_HID_2406d] = 179, + [BNXT_ULP_CLASS_HID_3566d] = 180, + [BNXT_ULP_CLASS_HID_4ad9] = 181, + [BNXT_ULP_CLASS_HID_1038d] = 182, + [BNXT_ULP_CLASS_HID_2198d] = 183, + [BNXT_ULP_CLASS_HID_32f8d] = 184, + [BNXT_ULP_CLASS_HID_40b1] = 185, + [BNXT_ULP_CLASS_HID_156b1] = 186, + [BNXT_ULP_CLASS_HID_21065] = 187, + [BNXT_ULP_CLASS_HID_32665] = 188, + [BNXT_ULP_CLASS_HID_0ac5] = 189, + [BNXT_ULP_CLASS_HID_120c5] = 190, + [BNXT_ULP_CLASS_HID_236c5] = 191, + [BNXT_ULP_CLASS_HID_34cc5] = 192, + [BNXT_ULP_CLASS_HID_0139] = 193, + [BNXT_ULP_CLASS_HID_11739] = 194, + [BNXT_ULP_CLASS_HID_22d39] = 195, + [BNXT_ULP_CLASS_HID_34339] = 196, + [BNXT_ULP_CLASS_HID_3795] = 197, + [BNXT_ULP_CLASS_HID_14d95] = 198, + [BNXT_ULP_CLASS_HID_20759] = 199, + [BNXT_ULP_CLASS_HID_31d59] = 200, + [BNXT_ULP_CLASS_HID_2e0d] = 201, + [BNXT_ULP_CLASS_HID_1440d] = 202, + [BNXT_ULP_CLASS_HID_25a0d] = 203, + [BNXT_ULP_CLASS_HID_31331] = 204, + [BNXT_ULP_CLASS_HID_54ed] = 205, + [BNXT_ULP_CLASS_HID_10d91] = 206, + [BNXT_ULP_CLASS_HID_22391] = 207, + [BNXT_ULP_CLASS_HID_33991] = 208, + [BNXT_ULP_CLASS_HID_5849] = 209, + [BNXT_ULP_CLASS_HID_1117d] = 210, + [BNXT_ULP_CLASS_HID_2277d] = 211, + [BNXT_ULP_CLASS_HID_33d7d] = 212, + [BNXT_ULP_CLASS_HID_31e9] = 213, + [BNXT_ULP_CLASS_HID_147e9] = 214, + [BNXT_ULP_CLASS_HID_2009d] = 215, + [BNXT_ULP_CLASS_HID_3169d] = 216, + [BNXT_ULP_CLASS_HID_2841] = 217, + [BNXT_ULP_CLASS_HID_13e41] = 218, + [BNXT_ULP_CLASS_HID_25441] = 219, + [BNXT_ULP_CLASS_HID_30d75] = 220, + [BNXT_ULP_CLASS_HID_4e21] = 221, + [BNXT_ULP_CLASS_HID_107d5] = 222, + [BNXT_ULP_CLASS_HID_21dd5] = 223, + [BNXT_ULP_CLASS_HID_333d5] = 224, + [BNXT_ULP_CLASS_HID_2521] = 225, + [BNXT_ULP_CLASS_HID_2bed] = 226, + [BNXT_ULP_CLASS_HID_050d] = 227, + [BNXT_ULP_CLASS_HID_5b9d] = 228, + [BNXT_ULP_CLASS_HID_1865] = 229, + [BNXT_ULP_CLASS_HID_389d] = 230, + [BNXT_ULP_CLASS_HID_123d] = 231, + [BNXT_ULP_CLASS_HID_4ef1] = 232, + [BNXT_ULP_CLASS_HID_1229] = 233, + [BNXT_ULP_CLASS_HID_3241] = 234, + [BNXT_ULP_CLASS_HID_0be1] = 235, + [BNXT_ULP_CLASS_HID_48b5] = 236, + [BNXT_ULP_CLASS_HID_0bed] = 237, + [BNXT_ULP_CLASS_HID_2c05] = 238, + [BNXT_ULP_CLASS_HID_05a5] = 239, + [BNXT_ULP_CLASS_HID_4279] = 240, + [BNXT_ULP_CLASS_HID_05d1] = 241, + [BNXT_ULP_CLASS_HID_25c9] = 242, + [BNXT_ULP_CLASS_HID_5c55] = 243, + [BNXT_ULP_CLASS_HID_3c3d] = 244, + [BNXT_ULP_CLASS_HID_4fc9] = 245, + [BNXT_ULP_CLASS_HID_1335] = 246, + [BNXT_ULP_CLASS_HID_4981] = 247, + [BNXT_ULP_CLASS_HID_2969] = 248, + [BNXT_ULP_CLASS_HID_498d] = 249, + [BNXT_ULP_CLASS_HID_0cf9] = 250, + [BNXT_ULP_CLASS_HID_4345] = 251, + [BNXT_ULP_CLASS_HID_232d] = 252, + [BNXT_ULP_CLASS_HID_2579] = 253, + [BNXT_ULP_CLASS_HID_2bb5] = 254, + [BNXT_ULP_CLASS_HID_4bad] = 255, + [BNXT_ULP_CLASS_HID_4591] = 256, + [BNXT_ULP_CLASS_HID_1845] = 257, + [BNXT_ULP_CLASS_HID_1399] = 258, + [BNXT_ULP_CLASS_HID_0eed] = 259, + [BNXT_ULP_CLASS_HID_0a21] = 260, + [BNXT_ULP_CLASS_HID_38bd] = 261, + [BNXT_ULP_CLASS_HID_33f1] = 262, + [BNXT_ULP_CLASS_HID_2ec5] = 263, + [BNXT_ULP_CLASS_HID_2a19] = 264, + [BNXT_ULP_CLASS_HID_121d] = 265, + [BNXT_ULP_CLASS_HID_0d51] = 266, + [BNXT_ULP_CLASS_HID_08a5] = 267, + [BNXT_ULP_CLASS_HID_03f9] = 268, + [BNXT_ULP_CLASS_HID_4ed1] = 269, + [BNXT_ULP_CLASS_HID_4a25] = 270, + [BNXT_ULP_CLASS_HID_4579] = 271, + [BNXT_ULP_CLASS_HID_404d] = 272, + [BNXT_ULP_CLASS_HID_1209] = 273, + [BNXT_ULP_CLASS_HID_0d5d] = 274, + [BNXT_ULP_CLASS_HID_0891] = 275, + [BNXT_ULP_CLASS_HID_03e5] = 276, + [BNXT_ULP_CLASS_HID_3261] = 277, + [BNXT_ULP_CLASS_HID_2db5] = 278, + [BNXT_ULP_CLASS_HID_2889] = 279, + [BNXT_ULP_CLASS_HID_23dd] = 280, + [BNXT_ULP_CLASS_HID_0bc1] = 281, + [BNXT_ULP_CLASS_HID_0715] = 282, + [BNXT_ULP_CLASS_HID_0269] = 283, + [BNXT_ULP_CLASS_HID_5a69] = 284, + [BNXT_ULP_CLASS_HID_4895] = 285, + [BNXT_ULP_CLASS_HID_43e9] = 286, + [BNXT_ULP_CLASS_HID_3f3d] = 287, + [BNXT_ULP_CLASS_HID_3a71] = 288, + [BNXT_ULP_CLASS_HID_0bcd] = 289, + [BNXT_ULP_CLASS_HID_0701] = 290, + [BNXT_ULP_CLASS_HID_0255] = 291, + [BNXT_ULP_CLASS_HID_5a55] = 292, + [BNXT_ULP_CLASS_HID_2c25] = 293, + [BNXT_ULP_CLASS_HID_2779] = 294, + [BNXT_ULP_CLASS_HID_224d] = 295, + [BNXT_ULP_CLASS_HID_1d81] = 296, + [BNXT_ULP_CLASS_HID_0585] = 297, + [BNXT_ULP_CLASS_HID_00d9] = 298, + [BNXT_ULP_CLASS_HID_58d9] = 299, + [BNXT_ULP_CLASS_HID_542d] = 300, + [BNXT_ULP_CLASS_HID_4259] = 301, + [BNXT_ULP_CLASS_HID_3dad] = 302, + [BNXT_ULP_CLASS_HID_38e1] = 303, + [BNXT_ULP_CLASS_HID_3435] = 304, + [BNXT_ULP_CLASS_HID_05f1] = 305, + [BNXT_ULP_CLASS_HID_00c5] = 306, + [BNXT_ULP_CLASS_HID_58c5] = 307, + [BNXT_ULP_CLASS_HID_5419] = 308, + [BNXT_ULP_CLASS_HID_25e9] = 309, + [BNXT_ULP_CLASS_HID_213d] = 310, + [BNXT_ULP_CLASS_HID_1c71] = 311, + [BNXT_ULP_CLASS_HID_1745] = 312, + [BNXT_ULP_CLASS_HID_5c75] = 313, + [BNXT_ULP_CLASS_HID_5749] = 314, + [BNXT_ULP_CLASS_HID_529d] = 315, + [BNXT_ULP_CLASS_HID_4dd1] = 316, + [BNXT_ULP_CLASS_HID_3c1d] = 317, + [BNXT_ULP_CLASS_HID_3751] = 318, + [BNXT_ULP_CLASS_HID_32a5] = 319, + [BNXT_ULP_CLASS_HID_2df9] = 320, + [BNXT_ULP_CLASS_HID_4fe9] = 321, + [BNXT_ULP_CLASS_HID_4b3d] = 322, + [BNXT_ULP_CLASS_HID_4671] = 323, + [BNXT_ULP_CLASS_HID_4145] = 324, + [BNXT_ULP_CLASS_HID_1315] = 325, + [BNXT_ULP_CLASS_HID_0e69] = 326, + [BNXT_ULP_CLASS_HID_09bd] = 327, + [BNXT_ULP_CLASS_HID_04f1] = 328, + [BNXT_ULP_CLASS_HID_49a1] = 329, + [BNXT_ULP_CLASS_HID_44f5] = 330, + [BNXT_ULP_CLASS_HID_3fc9] = 331, + [BNXT_ULP_CLASS_HID_3b1d] = 332, + [BNXT_ULP_CLASS_HID_2949] = 333, + [BNXT_ULP_CLASS_HID_249d] = 334, + [BNXT_ULP_CLASS_HID_1fd1] = 335, + [BNXT_ULP_CLASS_HID_1b25] = 336, + [BNXT_ULP_CLASS_HID_49ad] = 337, + [BNXT_ULP_CLASS_HID_44e1] = 338, + [BNXT_ULP_CLASS_HID_4035] = 339, + [BNXT_ULP_CLASS_HID_3b09] = 340, + [BNXT_ULP_CLASS_HID_0cd9] = 341, + [BNXT_ULP_CLASS_HID_082d] = 342, + [BNXT_ULP_CLASS_HID_0361] = 343, + [BNXT_ULP_CLASS_HID_5b61] = 344, + [BNXT_ULP_CLASS_HID_4365] = 345, + [BNXT_ULP_CLASS_HID_3eb9] = 346, + [BNXT_ULP_CLASS_HID_398d] = 347, + [BNXT_ULP_CLASS_HID_34c1] = 348, + [BNXT_ULP_CLASS_HID_230d] = 349, + [BNXT_ULP_CLASS_HID_1e41] = 350, + [BNXT_ULP_CLASS_HID_1995] = 351, + [BNXT_ULP_CLASS_HID_14e9] = 352, + [BNXT_ULP_CLASS_HID_2559] = 353, + [BNXT_ULP_CLASS_HID_2b95] = 354, + [BNXT_ULP_CLASS_HID_4b8d] = 355, + [BNXT_ULP_CLASS_HID_45b1] = 356, + [BNXT_ULP_CLASS_HID_1825] = 357, + [BNXT_ULP_CLASS_HID_13f9] = 358, + [BNXT_ULP_CLASS_HID_0e8d] = 359, + [BNXT_ULP_CLASS_HID_0a41] = 360, + [BNXT_ULP_CLASS_HID_38dd] = 361, + [BNXT_ULP_CLASS_HID_3391] = 362, + [BNXT_ULP_CLASS_HID_2ea5] = 363, + [BNXT_ULP_CLASS_HID_2a79] = 364, + [BNXT_ULP_CLASS_HID_127d] = 365, + [BNXT_ULP_CLASS_HID_0d31] = 366, + [BNXT_ULP_CLASS_HID_08c5] = 367, + [BNXT_ULP_CLASS_HID_0399] = 368, + [BNXT_ULP_CLASS_HID_4eb1] = 369, + [BNXT_ULP_CLASS_HID_4a45] = 370, + [BNXT_ULP_CLASS_HID_4519] = 371, + [BNXT_ULP_CLASS_HID_402d] = 372, + [BNXT_ULP_CLASS_HID_1269] = 373, + [BNXT_ULP_CLASS_HID_0d3d] = 374, + [BNXT_ULP_CLASS_HID_08f1] = 375, + [BNXT_ULP_CLASS_HID_0385] = 376, + [BNXT_ULP_CLASS_HID_3201] = 377, + [BNXT_ULP_CLASS_HID_2dd5] = 378, + [BNXT_ULP_CLASS_HID_28e9] = 379, + [BNXT_ULP_CLASS_HID_23bd] = 380, + [BNXT_ULP_CLASS_HID_0ba1] = 381, + [BNXT_ULP_CLASS_HID_0775] = 382, + [BNXT_ULP_CLASS_HID_0209] = 383, + [BNXT_ULP_CLASS_HID_5a09] = 384, + [BNXT_ULP_CLASS_HID_48f5] = 385, + [BNXT_ULP_CLASS_HID_4389] = 386, + [BNXT_ULP_CLASS_HID_3f5d] = 387, + [BNXT_ULP_CLASS_HID_3a11] = 388, + [BNXT_ULP_CLASS_HID_0bad] = 389, + [BNXT_ULP_CLASS_HID_0761] = 390, + [BNXT_ULP_CLASS_HID_0235] = 391, + [BNXT_ULP_CLASS_HID_5a35] = 392, + [BNXT_ULP_CLASS_HID_2c45] = 393, + [BNXT_ULP_CLASS_HID_2719] = 394, + [BNXT_ULP_CLASS_HID_222d] = 395, + [BNXT_ULP_CLASS_HID_1de1] = 396, + [BNXT_ULP_CLASS_HID_05e5] = 397, + [BNXT_ULP_CLASS_HID_00b9] = 398, + [BNXT_ULP_CLASS_HID_58b9] = 399, + [BNXT_ULP_CLASS_HID_544d] = 400, + [BNXT_ULP_CLASS_HID_4239] = 401, + [BNXT_ULP_CLASS_HID_3dcd] = 402, + [BNXT_ULP_CLASS_HID_3881] = 403, + [BNXT_ULP_CLASS_HID_3455] = 404, + [BNXT_ULP_CLASS_HID_0591] = 405, + [BNXT_ULP_CLASS_HID_00a5] = 406, + [BNXT_ULP_CLASS_HID_58a5] = 407, + [BNXT_ULP_CLASS_HID_5479] = 408, + [BNXT_ULP_CLASS_HID_2589] = 409, + [BNXT_ULP_CLASS_HID_215d] = 410, + [BNXT_ULP_CLASS_HID_1c11] = 411, + [BNXT_ULP_CLASS_HID_1725] = 412, + [BNXT_ULP_CLASS_HID_5c15] = 413, + [BNXT_ULP_CLASS_HID_5729] = 414, + [BNXT_ULP_CLASS_HID_52fd] = 415, + [BNXT_ULP_CLASS_HID_4db1] = 416, + [BNXT_ULP_CLASS_HID_3c7d] = 417, + [BNXT_ULP_CLASS_HID_3731] = 418, + [BNXT_ULP_CLASS_HID_32c5] = 419, + [BNXT_ULP_CLASS_HID_2d99] = 420, + [BNXT_ULP_CLASS_HID_4f89] = 421, + [BNXT_ULP_CLASS_HID_4b5d] = 422, + [BNXT_ULP_CLASS_HID_4611] = 423, + [BNXT_ULP_CLASS_HID_4125] = 424, + [BNXT_ULP_CLASS_HID_1375] = 425, + [BNXT_ULP_CLASS_HID_0e09] = 426, + [BNXT_ULP_CLASS_HID_09dd] = 427, + [BNXT_ULP_CLASS_HID_0491] = 428, + [BNXT_ULP_CLASS_HID_49c1] = 429, + [BNXT_ULP_CLASS_HID_4495] = 430, + [BNXT_ULP_CLASS_HID_3fa9] = 431, + [BNXT_ULP_CLASS_HID_3b7d] = 432, + [BNXT_ULP_CLASS_HID_2929] = 433, + [BNXT_ULP_CLASS_HID_24fd] = 434, + [BNXT_ULP_CLASS_HID_1fb1] = 435, + [BNXT_ULP_CLASS_HID_1b45] = 436, + [BNXT_ULP_CLASS_HID_49cd] = 437, + [BNXT_ULP_CLASS_HID_4481] = 438, + [BNXT_ULP_CLASS_HID_4055] = 439, + [BNXT_ULP_CLASS_HID_3b69] = 440, + [BNXT_ULP_CLASS_HID_0cb9] = 441, + [BNXT_ULP_CLASS_HID_084d] = 442, + [BNXT_ULP_CLASS_HID_0301] = 443, + [BNXT_ULP_CLASS_HID_5b01] = 444, + [BNXT_ULP_CLASS_HID_4305] = 445, + [BNXT_ULP_CLASS_HID_3ed9] = 446, + [BNXT_ULP_CLASS_HID_39ed] = 447, + [BNXT_ULP_CLASS_HID_34a1] = 448, + [BNXT_ULP_CLASS_HID_236d] = 449, + [BNXT_ULP_CLASS_HID_1e21] = 450, + [BNXT_ULP_CLASS_HID_19f5] = 451, + [BNXT_ULP_CLASS_HID_1489] = 452, + [BNXT_ULP_CLASS_HID_2539] = 453, + [BNXT_ULP_CLASS_HID_2bf5] = 454, + [BNXT_ULP_CLASS_HID_4bed] = 455, + [BNXT_ULP_CLASS_HID_45d1] = 456, + [BNXT_ULP_CLASS_HID_b6af] = 457, + [BNXT_ULP_CLASS_HID_b1d3] = 458, + [BNXT_ULP_CLASS_HID_1c7d3] = 459, + [BNXT_ULP_CLASS_HID_1ccaf] = 460, + [BNXT_ULP_CLASS_HID_da33] = 461, + [BNXT_ULP_CLASS_HID_d567] = 462, + [BNXT_ULP_CLASS_HID_18eab] = 463, + [BNXT_ULP_CLASS_HID_19367] = 464, + [BNXT_ULP_CLASS_HID_a10b] = 465, + [BNXT_ULP_CLASS_HID_9c3f] = 466, + [BNXT_ULP_CLASS_HID_1b23f] = 467, + [BNXT_ULP_CLASS_HID_1b70b] = 468, + [BNXT_ULP_CLASS_HID_c49f] = 469, + [BNXT_ULP_CLASS_HID_bfc3] = 470, + [BNXT_ULP_CLASS_HID_1d5c3] = 471, + [BNXT_ULP_CLASS_HID_1da9f] = 472, + [BNXT_ULP_CLASS_HID_b063] = 473, + [BNXT_ULP_CLASS_HID_ab97] = 474, + [BNXT_ULP_CLASS_HID_1c197] = 475, + [BNXT_ULP_CLASS_HID_1c663] = 476, + [BNXT_ULP_CLASS_HID_d3f7] = 477, + [BNXT_ULP_CLASS_HID_cf3b] = 478, + [BNXT_ULP_CLASS_HID_1886f] = 479, + [BNXT_ULP_CLASS_HID_18d3b] = 480, + [BNXT_ULP_CLASS_HID_9acf] = 481, + [BNXT_ULP_CLASS_HID_95f3] = 482, + [BNXT_ULP_CLASS_HID_1abf3] = 483, + [BNXT_ULP_CLASS_HID_1b0cf] = 484, + [BNXT_ULP_CLASS_HID_be53] = 485, + [BNXT_ULP_CLASS_HID_b987] = 486, + [BNXT_ULP_CLASS_HID_1cf87] = 487, + [BNXT_ULP_CLASS_HID_1d453] = 488, + [BNXT_ULP_CLASS_HID_aa27] = 489, + [BNXT_ULP_CLASS_HID_a56b] = 490, + [BNXT_ULP_CLASS_HID_1bb6b] = 491, + [BNXT_ULP_CLASS_HID_1c027] = 492, + [BNXT_ULP_CLASS_HID_cdcb] = 493, + [BNXT_ULP_CLASS_HID_c8ff] = 494, + [BNXT_ULP_CLASS_HID_18223] = 495, + [BNXT_ULP_CLASS_HID_186ff] = 496, + [BNXT_ULP_CLASS_HID_9483] = 497, + [BNXT_ULP_CLASS_HID_8fb7] = 498, + [BNXT_ULP_CLASS_HID_1a5b7] = 499, + [BNXT_ULP_CLASS_HID_1aa83] = 500, + [BNXT_ULP_CLASS_HID_b817] = 501, + [BNXT_ULP_CLASS_HID_b35b] = 502, + [BNXT_ULP_CLASS_HID_1c95b] = 503, + [BNXT_ULP_CLASS_HID_1ce17] = 504, + [BNXT_ULP_CLASS_HID_a3fb] = 505, + [BNXT_ULP_CLASS_HID_9f2f] = 506, + [BNXT_ULP_CLASS_HID_1b52f] = 507, + [BNXT_ULP_CLASS_HID_1b9fb] = 508, + [BNXT_ULP_CLASS_HID_c78f] = 509, + [BNXT_ULP_CLASS_HID_c2b3] = 510, + [BNXT_ULP_CLASS_HID_1d8b3] = 511, + [BNXT_ULP_CLASS_HID_180b3] = 512, + [BNXT_ULP_CLASS_HID_8e47] = 513, + [BNXT_ULP_CLASS_HID_898b] = 514, + [BNXT_ULP_CLASS_HID_19f8b] = 515, + [BNXT_ULP_CLASS_HID_1a447] = 516, + [BNXT_ULP_CLASS_HID_b1eb] = 517, + [BNXT_ULP_CLASS_HID_ad1f] = 518, + [BNXT_ULP_CLASS_HID_1c31f] = 519, + [BNXT_ULP_CLASS_HID_1c7eb] = 520, + [BNXT_ULP_CLASS_HID_9137] = 521, + [BNXT_ULP_CLASS_HID_8c7b] = 522, + [BNXT_ULP_CLASS_HID_1a27b] = 523, + [BNXT_ULP_CLASS_HID_1a737] = 524, + [BNXT_ULP_CLASS_HID_b4db] = 525, + [BNXT_ULP_CLASS_HID_b00f] = 526, + [BNXT_ULP_CLASS_HID_1c60f] = 527, + [BNXT_ULP_CLASS_HID_1cadb] = 528, + [BNXT_ULP_CLASS_HID_8b0b] = 529, + [BNXT_ULP_CLASS_HID_863f] = 530, + [BNXT_ULP_CLASS_HID_19c3f] = 531, + [BNXT_ULP_CLASS_HID_1a10b] = 532, + [BNXT_ULP_CLASS_HID_ae9f] = 533, + [BNXT_ULP_CLASS_HID_a9c3] = 534, + [BNXT_ULP_CLASS_HID_1bfc3] = 535, + [BNXT_ULP_CLASS_HID_1c49f] = 536, + [BNXT_ULP_CLASS_HID_2563] = 537, + [BNXT_ULP_CLASS_HID_2baf] = 538, + [BNXT_ULP_CLASS_HID_26d3] = 539, + [BNXT_ULP_CLASS_HID_4f33] = 540, + [BNXT_ULP_CLASS_HID_4a67] = 541, + [BNXT_ULP_CLASS_HID_160b] = 542, + [BNXT_ULP_CLASS_HID_113f] = 543, + [BNXT_ULP_CLASS_HID_399f] = 544, + [BNXT_ULP_CLASS_HID_34c3] = 545, + [BNXT_ULP_CLASS_HID_2097] = 546, + [BNXT_ULP_CLASS_HID_48f7] = 547, + [BNXT_ULP_CLASS_HID_443b] = 548, + [BNXT_ULP_CLASS_HID_0fcf] = 549, + [BNXT_ULP_CLASS_HID_0af3] = 550, + [BNXT_ULP_CLASS_HID_3353] = 551, + [BNXT_ULP_CLASS_HID_2e87] = 552, + [BNXT_ULP_CLASS_HID_b68f] = 553, + [BNXT_ULP_CLASS_HID_b94f] = 554, + [BNXT_ULP_CLASS_HID_fc0f] = 555, + [BNXT_ULP_CLASS_HID_fecf] = 556, + [BNXT_ULP_CLASS_HID_b1f3] = 557, + [BNXT_ULP_CLASS_HID_b4b3] = 558, + [BNXT_ULP_CLASS_HID_f773] = 559, + [BNXT_ULP_CLASS_HID_fa33] = 560, + [BNXT_ULP_CLASS_HID_1c7f3] = 561, + [BNXT_ULP_CLASS_HID_1eab3] = 562, + [BNXT_ULP_CLASS_HID_1cd73] = 563, + [BNXT_ULP_CLASS_HID_1f033] = 564, + [BNXT_ULP_CLASS_HID_1cc8f] = 565, + [BNXT_ULP_CLASS_HID_1ef4f] = 566, + [BNXT_ULP_CLASS_HID_1d20f] = 567, + [BNXT_ULP_CLASS_HID_1f4cf] = 568, + [BNXT_ULP_CLASS_HID_da13] = 569, + [BNXT_ULP_CLASS_HID_a007] = 570, + [BNXT_ULP_CLASS_HID_c2c7] = 571, + [BNXT_ULP_CLASS_HID_e587] = 572, + [BNXT_ULP_CLASS_HID_d547] = 573, + [BNXT_ULP_CLASS_HID_f807] = 574, + [BNXT_ULP_CLASS_HID_dac7] = 575, + [BNXT_ULP_CLASS_HID_e0cb] = 576, + [BNXT_ULP_CLASS_HID_18e8b] = 577, + [BNXT_ULP_CLASS_HID_1b14b] = 578, + [BNXT_ULP_CLASS_HID_1d40b] = 579, + [BNXT_ULP_CLASS_HID_1f6cb] = 580, + [BNXT_ULP_CLASS_HID_19347] = 581, + [BNXT_ULP_CLASS_HID_1b607] = 582, + [BNXT_ULP_CLASS_HID_1d8c7] = 583, + [BNXT_ULP_CLASS_HID_1fb87] = 584, + [BNXT_ULP_CLASS_HID_a12b] = 585, + [BNXT_ULP_CLASS_HID_a3eb] = 586, + [BNXT_ULP_CLASS_HID_e6ab] = 587, + [BNXT_ULP_CLASS_HID_e96b] = 588, + [BNXT_ULP_CLASS_HID_9c1f] = 589, + [BNXT_ULP_CLASS_HID_bedf] = 590, + [BNXT_ULP_CLASS_HID_e19f] = 591, + [BNXT_ULP_CLASS_HID_e45f] = 592, + [BNXT_ULP_CLASS_HID_1b21f] = 593, + [BNXT_ULP_CLASS_HID_1b4df] = 594, + [BNXT_ULP_CLASS_HID_1f79f] = 595, + [BNXT_ULP_CLASS_HID_1fa5f] = 596, + [BNXT_ULP_CLASS_HID_1b72b] = 597, + [BNXT_ULP_CLASS_HID_1b9eb] = 598, + [BNXT_ULP_CLASS_HID_1fcab] = 599, + [BNXT_ULP_CLASS_HID_1ff6b] = 600, + [BNXT_ULP_CLASS_HID_c4bf] = 601, + [BNXT_ULP_CLASS_HID_e77f] = 602, + [BNXT_ULP_CLASS_HID_ca3f] = 603, + [BNXT_ULP_CLASS_HID_ecff] = 604, + [BNXT_ULP_CLASS_HID_bfe3] = 605, + [BNXT_ULP_CLASS_HID_e2a3] = 606, + [BNXT_ULP_CLASS_HID_c563] = 607, + [BNXT_ULP_CLASS_HID_e823] = 608, + [BNXT_ULP_CLASS_HID_1d5e3] = 609, + [BNXT_ULP_CLASS_HID_1f8a3] = 610, + [BNXT_ULP_CLASS_HID_1db63] = 611, + [BNXT_ULP_CLASS_HID_1e117] = 612, + [BNXT_ULP_CLASS_HID_1dabf] = 613, + [BNXT_ULP_CLASS_HID_1a0a3] = 614, + [BNXT_ULP_CLASS_HID_1c363] = 615, + [BNXT_ULP_CLASS_HID_1e623] = 616, + [BNXT_ULP_CLASS_HID_b043] = 617, + [BNXT_ULP_CLASS_HID_b303] = 618, + [BNXT_ULP_CLASS_HID_f5c3] = 619, + [BNXT_ULP_CLASS_HID_f883] = 620, + [BNXT_ULP_CLASS_HID_abb7] = 621, + [BNXT_ULP_CLASS_HID_ae77] = 622, + [BNXT_ULP_CLASS_HID_f137] = 623, + [BNXT_ULP_CLASS_HID_f3f7] = 624, + [BNXT_ULP_CLASS_HID_1c1b7] = 625, + [BNXT_ULP_CLASS_HID_1e477] = 626, + [BNXT_ULP_CLASS_HID_1c737] = 627, + [BNXT_ULP_CLASS_HID_1e9f7] = 628, + [BNXT_ULP_CLASS_HID_1c643] = 629, + [BNXT_ULP_CLASS_HID_1e903] = 630, + [BNXT_ULP_CLASS_HID_1cbc3] = 631, + [BNXT_ULP_CLASS_HID_1ee83] = 632, + [BNXT_ULP_CLASS_HID_d3d7] = 633, + [BNXT_ULP_CLASS_HID_f697] = 634, + [BNXT_ULP_CLASS_HID_d957] = 635, + [BNXT_ULP_CLASS_HID_fc17] = 636, + [BNXT_ULP_CLASS_HID_cf1b] = 637, + [BNXT_ULP_CLASS_HID_f1db] = 638, + [BNXT_ULP_CLASS_HID_d49b] = 639, + [BNXT_ULP_CLASS_HID_f75b] = 640, + [BNXT_ULP_CLASS_HID_1884f] = 641, + [BNXT_ULP_CLASS_HID_1ab0f] = 642, + [BNXT_ULP_CLASS_HID_1cdcf] = 643, + [BNXT_ULP_CLASS_HID_1f08f] = 644, + [BNXT_ULP_CLASS_HID_18d1b] = 645, + [BNXT_ULP_CLASS_HID_1afdb] = 646, + [BNXT_ULP_CLASS_HID_1d29b] = 647, + [BNXT_ULP_CLASS_HID_1f55b] = 648, + [BNXT_ULP_CLASS_HID_9aef] = 649, + [BNXT_ULP_CLASS_HID_bdaf] = 650, + [BNXT_ULP_CLASS_HID_e06f] = 651, + [BNXT_ULP_CLASS_HID_e32f] = 652, + [BNXT_ULP_CLASS_HID_95d3] = 653, + [BNXT_ULP_CLASS_HID_b893] = 654, + [BNXT_ULP_CLASS_HID_db53] = 655, + [BNXT_ULP_CLASS_HID_fe13] = 656, + [BNXT_ULP_CLASS_HID_1abd3] = 657, + [BNXT_ULP_CLASS_HID_1ae93] = 658, + [BNXT_ULP_CLASS_HID_1f153] = 659, + [BNXT_ULP_CLASS_HID_1f413] = 660, + [BNXT_ULP_CLASS_HID_1b0ef] = 661, + [BNXT_ULP_CLASS_HID_1b3af] = 662, + [BNXT_ULP_CLASS_HID_1f66f] = 663, + [BNXT_ULP_CLASS_HID_1f92f] = 664, + [BNXT_ULP_CLASS_HID_be73] = 665, + [BNXT_ULP_CLASS_HID_e133] = 666, + [BNXT_ULP_CLASS_HID_c3f3] = 667, + [BNXT_ULP_CLASS_HID_e6b3] = 668, + [BNXT_ULP_CLASS_HID_b9a7] = 669, + [BNXT_ULP_CLASS_HID_bc67] = 670, + [BNXT_ULP_CLASS_HID_ff27] = 671, + [BNXT_ULP_CLASS_HID_e1e7] = 672, + [BNXT_ULP_CLASS_HID_1cfa7] = 673, + [BNXT_ULP_CLASS_HID_1f267] = 674, + [BNXT_ULP_CLASS_HID_1d527] = 675, + [BNXT_ULP_CLASS_HID_1f7e7] = 676, + [BNXT_ULP_CLASS_HID_1d473] = 677, + [BNXT_ULP_CLASS_HID_1f733] = 678, + [BNXT_ULP_CLASS_HID_1d9f3] = 679, + [BNXT_ULP_CLASS_HID_1fcb3] = 680, + [BNXT_ULP_CLASS_HID_aa07] = 681, + [BNXT_ULP_CLASS_HID_acc7] = 682, + [BNXT_ULP_CLASS_HID_ef87] = 683, + [BNXT_ULP_CLASS_HID_f247] = 684, + [BNXT_ULP_CLASS_HID_a54b] = 685, + [BNXT_ULP_CLASS_HID_a80b] = 686, + [BNXT_ULP_CLASS_HID_eacb] = 687, + [BNXT_ULP_CLASS_HID_ed8b] = 688, + [BNXT_ULP_CLASS_HID_1bb4b] = 689, + [BNXT_ULP_CLASS_HID_1be0b] = 690, + [BNXT_ULP_CLASS_HID_1c0cb] = 691, + [BNXT_ULP_CLASS_HID_1e38b] = 692, + [BNXT_ULP_CLASS_HID_1c007] = 693, + [BNXT_ULP_CLASS_HID_1e2c7] = 694, + [BNXT_ULP_CLASS_HID_1c587] = 695, + [BNXT_ULP_CLASS_HID_1e847] = 696, + [BNXT_ULP_CLASS_HID_cdeb] = 697, + [BNXT_ULP_CLASS_HID_f0ab] = 698, + [BNXT_ULP_CLASS_HID_d36b] = 699, + [BNXT_ULP_CLASS_HID_f62b] = 700, + [BNXT_ULP_CLASS_HID_c8df] = 701, + [BNXT_ULP_CLASS_HID_eb9f] = 702, + [BNXT_ULP_CLASS_HID_ce5f] = 703, + [BNXT_ULP_CLASS_HID_f11f] = 704, + [BNXT_ULP_CLASS_HID_18203] = 705, + [BNXT_ULP_CLASS_HID_1a4c3] = 706, + [BNXT_ULP_CLASS_HID_1c783] = 707, + [BNXT_ULP_CLASS_HID_1ea43] = 708, + [BNXT_ULP_CLASS_HID_186df] = 709, + [BNXT_ULP_CLASS_HID_1a99f] = 710, + [BNXT_ULP_CLASS_HID_1cc5f] = 711, + [BNXT_ULP_CLASS_HID_1ef1f] = 712, + [BNXT_ULP_CLASS_HID_94a3] = 713, + [BNXT_ULP_CLASS_HID_b763] = 714, + [BNXT_ULP_CLASS_HID_da23] = 715, + [BNXT_ULP_CLASS_HID_fce3] = 716, + [BNXT_ULP_CLASS_HID_8f97] = 717, + [BNXT_ULP_CLASS_HID_b257] = 718, + [BNXT_ULP_CLASS_HID_d517] = 719, + [BNXT_ULP_CLASS_HID_f7d7] = 720, + [BNXT_ULP_CLASS_HID_1a597] = 721, + [BNXT_ULP_CLASS_HID_1a857] = 722, + [BNXT_ULP_CLASS_HID_1eb17] = 723, + [BNXT_ULP_CLASS_HID_1edd7] = 724, + [BNXT_ULP_CLASS_HID_1aaa3] = 725, + [BNXT_ULP_CLASS_HID_1ad63] = 726, + [BNXT_ULP_CLASS_HID_1f023] = 727, + [BNXT_ULP_CLASS_HID_1f2e3] = 728, + [BNXT_ULP_CLASS_HID_b837] = 729, + [BNXT_ULP_CLASS_HID_baf7] = 730, + [BNXT_ULP_CLASS_HID_fdb7] = 731, + [BNXT_ULP_CLASS_HID_e077] = 732, + [BNXT_ULP_CLASS_HID_b37b] = 733, + [BNXT_ULP_CLASS_HID_b63b] = 734, + [BNXT_ULP_CLASS_HID_f8fb] = 735, + [BNXT_ULP_CLASS_HID_fbbb] = 736, + [BNXT_ULP_CLASS_HID_1c97b] = 737, + [BNXT_ULP_CLASS_HID_1ec3b] = 738, + [BNXT_ULP_CLASS_HID_1cefb] = 739, + [BNXT_ULP_CLASS_HID_1f1bb] = 740, + [BNXT_ULP_CLASS_HID_1ce37] = 741, + [BNXT_ULP_CLASS_HID_1f0f7] = 742, + [BNXT_ULP_CLASS_HID_1d3b7] = 743, + [BNXT_ULP_CLASS_HID_1f677] = 744, + [BNXT_ULP_CLASS_HID_a3db] = 745, + [BNXT_ULP_CLASS_HID_a69b] = 746, + [BNXT_ULP_CLASS_HID_e95b] = 747, + [BNXT_ULP_CLASS_HID_ec1b] = 748, + [BNXT_ULP_CLASS_HID_9f0f] = 749, + [BNXT_ULP_CLASS_HID_a1cf] = 750, + [BNXT_ULP_CLASS_HID_e48f] = 751, + [BNXT_ULP_CLASS_HID_e74f] = 752, + [BNXT_ULP_CLASS_HID_1b50f] = 753, + [BNXT_ULP_CLASS_HID_1b7cf] = 754, + [BNXT_ULP_CLASS_HID_1fa8f] = 755, + [BNXT_ULP_CLASS_HID_1fd4f] = 756, + [BNXT_ULP_CLASS_HID_1b9db] = 757, + [BNXT_ULP_CLASS_HID_1bc9b] = 758, + [BNXT_ULP_CLASS_HID_1ff5b] = 759, + [BNXT_ULP_CLASS_HID_1e21b] = 760, + [BNXT_ULP_CLASS_HID_c7af] = 761, + [BNXT_ULP_CLASS_HID_ea6f] = 762, + [BNXT_ULP_CLASS_HID_cd2f] = 763, + [BNXT_ULP_CLASS_HID_efef] = 764, + [BNXT_ULP_CLASS_HID_c293] = 765, + [BNXT_ULP_CLASS_HID_e553] = 766, + [BNXT_ULP_CLASS_HID_c813] = 767, + [BNXT_ULP_CLASS_HID_ead3] = 768, + [BNXT_ULP_CLASS_HID_1d893] = 769, + [BNXT_ULP_CLASS_HID_1fb53] = 770, + [BNXT_ULP_CLASS_HID_1c147] = 771, + [BNXT_ULP_CLASS_HID_1e407] = 772, + [BNXT_ULP_CLASS_HID_18093] = 773, + [BNXT_ULP_CLASS_HID_1a353] = 774, + [BNXT_ULP_CLASS_HID_1c613] = 775, + [BNXT_ULP_CLASS_HID_1e8d3] = 776, + [BNXT_ULP_CLASS_HID_8e67] = 777, + [BNXT_ULP_CLASS_HID_b127] = 778, + [BNXT_ULP_CLASS_HID_d3e7] = 779, + [BNXT_ULP_CLASS_HID_f6a7] = 780, + [BNXT_ULP_CLASS_HID_89ab] = 781, + [BNXT_ULP_CLASS_HID_ac6b] = 782, + [BNXT_ULP_CLASS_HID_cf2b] = 783, + [BNXT_ULP_CLASS_HID_f1eb] = 784, + [BNXT_ULP_CLASS_HID_19fab] = 785, + [BNXT_ULP_CLASS_HID_1a26b] = 786, + [BNXT_ULP_CLASS_HID_1e52b] = 787, + [BNXT_ULP_CLASS_HID_1e7eb] = 788, + [BNXT_ULP_CLASS_HID_1a467] = 789, + [BNXT_ULP_CLASS_HID_1a727] = 790, + [BNXT_ULP_CLASS_HID_1e9e7] = 791, + [BNXT_ULP_CLASS_HID_1eca7] = 792, + [BNXT_ULP_CLASS_HID_b1cb] = 793, + [BNXT_ULP_CLASS_HID_b48b] = 794, + [BNXT_ULP_CLASS_HID_f74b] = 795, + [BNXT_ULP_CLASS_HID_fa0b] = 796, + [BNXT_ULP_CLASS_HID_ad3f] = 797, + [BNXT_ULP_CLASS_HID_afff] = 798, + [BNXT_ULP_CLASS_HID_f2bf] = 799, + [BNXT_ULP_CLASS_HID_f57f] = 800, + [BNXT_ULP_CLASS_HID_1c33f] = 801, + [BNXT_ULP_CLASS_HID_1e5ff] = 802, + [BNXT_ULP_CLASS_HID_1c8bf] = 803, + [BNXT_ULP_CLASS_HID_1eb7f] = 804, + [BNXT_ULP_CLASS_HID_1c7cb] = 805, + [BNXT_ULP_CLASS_HID_1ea8b] = 806, + [BNXT_ULP_CLASS_HID_1cd4b] = 807, + [BNXT_ULP_CLASS_HID_1f00b] = 808, + [BNXT_ULP_CLASS_HID_9117] = 809, + [BNXT_ULP_CLASS_HID_b3d7] = 810, + [BNXT_ULP_CLASS_HID_d697] = 811, + [BNXT_ULP_CLASS_HID_f957] = 812, + [BNXT_ULP_CLASS_HID_8c5b] = 813, + [BNXT_ULP_CLASS_HID_af1b] = 814, + [BNXT_ULP_CLASS_HID_d1db] = 815, + [BNXT_ULP_CLASS_HID_f49b] = 816, + [BNXT_ULP_CLASS_HID_1a25b] = 817, + [BNXT_ULP_CLASS_HID_1a51b] = 818, + [BNXT_ULP_CLASS_HID_1e7db] = 819, + [BNXT_ULP_CLASS_HID_1ea9b] = 820, + [BNXT_ULP_CLASS_HID_1a717] = 821, + [BNXT_ULP_CLASS_HID_1a9d7] = 822, + [BNXT_ULP_CLASS_HID_1ec97] = 823, + [BNXT_ULP_CLASS_HID_1ef57] = 824, + [BNXT_ULP_CLASS_HID_b4fb] = 825, + [BNXT_ULP_CLASS_HID_b7bb] = 826, + [BNXT_ULP_CLASS_HID_fa7b] = 827, + [BNXT_ULP_CLASS_HID_fd3b] = 828, + [BNXT_ULP_CLASS_HID_b02f] = 829, + [BNXT_ULP_CLASS_HID_b2ef] = 830, + [BNXT_ULP_CLASS_HID_f5af] = 831, + [BNXT_ULP_CLASS_HID_f86f] = 832, + [BNXT_ULP_CLASS_HID_1c62f] = 833, + [BNXT_ULP_CLASS_HID_1e8ef] = 834, + [BNXT_ULP_CLASS_HID_1cbaf] = 835, + [BNXT_ULP_CLASS_HID_1ee6f] = 836, + [BNXT_ULP_CLASS_HID_1cafb] = 837, + [BNXT_ULP_CLASS_HID_1edbb] = 838, + [BNXT_ULP_CLASS_HID_1d07b] = 839, + [BNXT_ULP_CLASS_HID_1f33b] = 840, + [BNXT_ULP_CLASS_HID_8b2b] = 841, + [BNXT_ULP_CLASS_HID_adeb] = 842, + [BNXT_ULP_CLASS_HID_d0ab] = 843, + [BNXT_ULP_CLASS_HID_f36b] = 844, + [BNXT_ULP_CLASS_HID_861f] = 845, + [BNXT_ULP_CLASS_HID_a8df] = 846, + [BNXT_ULP_CLASS_HID_cb9f] = 847, + [BNXT_ULP_CLASS_HID_ee5f] = 848, + [BNXT_ULP_CLASS_HID_19c1f] = 849, + [BNXT_ULP_CLASS_HID_1bedf] = 850, + [BNXT_ULP_CLASS_HID_1e19f] = 851, + [BNXT_ULP_CLASS_HID_1e45f] = 852, + [BNXT_ULP_CLASS_HID_1a12b] = 853, + [BNXT_ULP_CLASS_HID_1a3eb] = 854, + [BNXT_ULP_CLASS_HID_1e6ab] = 855, + [BNXT_ULP_CLASS_HID_1e96b] = 856, + [BNXT_ULP_CLASS_HID_aebf] = 857, + [BNXT_ULP_CLASS_HID_b17f] = 858, + [BNXT_ULP_CLASS_HID_f43f] = 859, + [BNXT_ULP_CLASS_HID_f6ff] = 860, + [BNXT_ULP_CLASS_HID_a9e3] = 861, + [BNXT_ULP_CLASS_HID_aca3] = 862, + [BNXT_ULP_CLASS_HID_ef63] = 863, + [BNXT_ULP_CLASS_HID_f223] = 864, + [BNXT_ULP_CLASS_HID_1bfe3] = 865, + [BNXT_ULP_CLASS_HID_1e2a3] = 866, + [BNXT_ULP_CLASS_HID_1c563] = 867, + [BNXT_ULP_CLASS_HID_1e823] = 868, + [BNXT_ULP_CLASS_HID_1c4bf] = 869, + [BNXT_ULP_CLASS_HID_1e77f] = 870, + [BNXT_ULP_CLASS_HID_1ca3f] = 871, + [BNXT_ULP_CLASS_HID_1ecff] = 872, + [BNXT_ULP_CLASS_HID_2543] = 873, + [BNXT_ULP_CLASS_HID_2b8f] = 874, + [BNXT_ULP_CLASS_HID_26f3] = 875, + [BNXT_ULP_CLASS_HID_4f13] = 876, + [BNXT_ULP_CLASS_HID_4a47] = 877, + [BNXT_ULP_CLASS_HID_162b] = 878, + [BNXT_ULP_CLASS_HID_111f] = 879, + [BNXT_ULP_CLASS_HID_39bf] = 880, + [BNXT_ULP_CLASS_HID_34e3] = 881, + [BNXT_ULP_CLASS_HID_20b7] = 882, + [BNXT_ULP_CLASS_HID_48d7] = 883, + [BNXT_ULP_CLASS_HID_441b] = 884, + [BNXT_ULP_CLASS_HID_0fef] = 885, + [BNXT_ULP_CLASS_HID_0ad3] = 886, + [BNXT_ULP_CLASS_HID_3373] = 887, + [BNXT_ULP_CLASS_HID_2ea7] = 888, + [BNXT_ULP_CLASS_HID_b6ef] = 889, + [BNXT_ULP_CLASS_HID_b92f] = 890, + [BNXT_ULP_CLASS_HID_fc6f] = 891, + [BNXT_ULP_CLASS_HID_feaf] = 892, + [BNXT_ULP_CLASS_HID_b193] = 893, + [BNXT_ULP_CLASS_HID_b4d3] = 894, + [BNXT_ULP_CLASS_HID_f713] = 895, + [BNXT_ULP_CLASS_HID_fa53] = 896, + [BNXT_ULP_CLASS_HID_1c793] = 897, + [BNXT_ULP_CLASS_HID_1ead3] = 898, + [BNXT_ULP_CLASS_HID_1cd13] = 899, + [BNXT_ULP_CLASS_HID_1f053] = 900, + [BNXT_ULP_CLASS_HID_1ccef] = 901, + [BNXT_ULP_CLASS_HID_1ef2f] = 902, + [BNXT_ULP_CLASS_HID_1d26f] = 903, + [BNXT_ULP_CLASS_HID_1f4af] = 904, + [BNXT_ULP_CLASS_HID_da73] = 905, + [BNXT_ULP_CLASS_HID_a067] = 906, + [BNXT_ULP_CLASS_HID_c2a7] = 907, + [BNXT_ULP_CLASS_HID_e5e7] = 908, + [BNXT_ULP_CLASS_HID_d527] = 909, + [BNXT_ULP_CLASS_HID_f867] = 910, + [BNXT_ULP_CLASS_HID_daa7] = 911, + [BNXT_ULP_CLASS_HID_e0ab] = 912, + [BNXT_ULP_CLASS_HID_18eeb] = 913, + [BNXT_ULP_CLASS_HID_1b12b] = 914, + [BNXT_ULP_CLASS_HID_1d46b] = 915, + [BNXT_ULP_CLASS_HID_1f6ab] = 916, + [BNXT_ULP_CLASS_HID_19327] = 917, + [BNXT_ULP_CLASS_HID_1b667] = 918, + [BNXT_ULP_CLASS_HID_1d8a7] = 919, + [BNXT_ULP_CLASS_HID_1fbe7] = 920, + [BNXT_ULP_CLASS_HID_a14b] = 921, + [BNXT_ULP_CLASS_HID_a38b] = 922, + [BNXT_ULP_CLASS_HID_e6cb] = 923, + [BNXT_ULP_CLASS_HID_e90b] = 924, + [BNXT_ULP_CLASS_HID_9c7f] = 925, + [BNXT_ULP_CLASS_HID_bebf] = 926, + [BNXT_ULP_CLASS_HID_e1ff] = 927, + [BNXT_ULP_CLASS_HID_e43f] = 928, + [BNXT_ULP_CLASS_HID_1b27f] = 929, + [BNXT_ULP_CLASS_HID_1b4bf] = 930, + [BNXT_ULP_CLASS_HID_1f7ff] = 931, + [BNXT_ULP_CLASS_HID_1fa3f] = 932, + [BNXT_ULP_CLASS_HID_1b74b] = 933, + [BNXT_ULP_CLASS_HID_1b98b] = 934, + [BNXT_ULP_CLASS_HID_1fccb] = 935, + [BNXT_ULP_CLASS_HID_1ff0b] = 936, + [BNXT_ULP_CLASS_HID_c4df] = 937, + [BNXT_ULP_CLASS_HID_e71f] = 938, + [BNXT_ULP_CLASS_HID_ca5f] = 939, + [BNXT_ULP_CLASS_HID_ec9f] = 940, + [BNXT_ULP_CLASS_HID_bf83] = 941, + [BNXT_ULP_CLASS_HID_e2c3] = 942, + [BNXT_ULP_CLASS_HID_c503] = 943, + [BNXT_ULP_CLASS_HID_e843] = 944, + [BNXT_ULP_CLASS_HID_1d583] = 945, + [BNXT_ULP_CLASS_HID_1f8c3] = 946, + [BNXT_ULP_CLASS_HID_1db03] = 947, + [BNXT_ULP_CLASS_HID_1e177] = 948, + [BNXT_ULP_CLASS_HID_1dadf] = 949, + [BNXT_ULP_CLASS_HID_1a0c3] = 950, + [BNXT_ULP_CLASS_HID_1c303] = 951, + [BNXT_ULP_CLASS_HID_1e643] = 952, + [BNXT_ULP_CLASS_HID_b023] = 953, + [BNXT_ULP_CLASS_HID_b363] = 954, + [BNXT_ULP_CLASS_HID_f5a3] = 955, + [BNXT_ULP_CLASS_HID_f8e3] = 956, + [BNXT_ULP_CLASS_HID_abd7] = 957, + [BNXT_ULP_CLASS_HID_ae17] = 958, + [BNXT_ULP_CLASS_HID_f157] = 959, + [BNXT_ULP_CLASS_HID_f397] = 960, + [BNXT_ULP_CLASS_HID_1c1d7] = 961, + [BNXT_ULP_CLASS_HID_1e417] = 962, + [BNXT_ULP_CLASS_HID_1c757] = 963, + [BNXT_ULP_CLASS_HID_1e997] = 964, + [BNXT_ULP_CLASS_HID_1c623] = 965, + [BNXT_ULP_CLASS_HID_1e963] = 966, + [BNXT_ULP_CLASS_HID_1cba3] = 967, + [BNXT_ULP_CLASS_HID_1eee3] = 968, + [BNXT_ULP_CLASS_HID_d3b7] = 969, + [BNXT_ULP_CLASS_HID_f6f7] = 970, + [BNXT_ULP_CLASS_HID_d937] = 971, + [BNXT_ULP_CLASS_HID_fc77] = 972, + [BNXT_ULP_CLASS_HID_cf7b] = 973, + [BNXT_ULP_CLASS_HID_f1bb] = 974, + [BNXT_ULP_CLASS_HID_d4fb] = 975, + [BNXT_ULP_CLASS_HID_f73b] = 976, + [BNXT_ULP_CLASS_HID_1882f] = 977, + [BNXT_ULP_CLASS_HID_1ab6f] = 978, + [BNXT_ULP_CLASS_HID_1cdaf] = 979, + [BNXT_ULP_CLASS_HID_1f0ef] = 980, + [BNXT_ULP_CLASS_HID_18d7b] = 981, + [BNXT_ULP_CLASS_HID_1afbb] = 982, + [BNXT_ULP_CLASS_HID_1d2fb] = 983, + [BNXT_ULP_CLASS_HID_1f53b] = 984, + [BNXT_ULP_CLASS_HID_9a8f] = 985, + [BNXT_ULP_CLASS_HID_bdcf] = 986, + [BNXT_ULP_CLASS_HID_e00f] = 987, + [BNXT_ULP_CLASS_HID_e34f] = 988, + [BNXT_ULP_CLASS_HID_95b3] = 989, + [BNXT_ULP_CLASS_HID_b8f3] = 990, + [BNXT_ULP_CLASS_HID_db33] = 991, + [BNXT_ULP_CLASS_HID_fe73] = 992, + [BNXT_ULP_CLASS_HID_1abb3] = 993, + [BNXT_ULP_CLASS_HID_1aef3] = 994, + [BNXT_ULP_CLASS_HID_1f133] = 995, + [BNXT_ULP_CLASS_HID_1f473] = 996, + [BNXT_ULP_CLASS_HID_1b08f] = 997, + [BNXT_ULP_CLASS_HID_1b3cf] = 998, + [BNXT_ULP_CLASS_HID_1f60f] = 999, + [BNXT_ULP_CLASS_HID_1f94f] = 1000, + [BNXT_ULP_CLASS_HID_be13] = 1001, + [BNXT_ULP_CLASS_HID_e153] = 1002, + [BNXT_ULP_CLASS_HID_c393] = 1003, + [BNXT_ULP_CLASS_HID_e6d3] = 1004, + [BNXT_ULP_CLASS_HID_b9c7] = 1005, + [BNXT_ULP_CLASS_HID_bc07] = 1006, + [BNXT_ULP_CLASS_HID_ff47] = 1007, + [BNXT_ULP_CLASS_HID_e187] = 1008, + [BNXT_ULP_CLASS_HID_1cfc7] = 1009, + [BNXT_ULP_CLASS_HID_1f207] = 1010, + [BNXT_ULP_CLASS_HID_1d547] = 1011, + [BNXT_ULP_CLASS_HID_1f787] = 1012, + [BNXT_ULP_CLASS_HID_1d413] = 1013, + [BNXT_ULP_CLASS_HID_1f753] = 1014, + [BNXT_ULP_CLASS_HID_1d993] = 1015, + [BNXT_ULP_CLASS_HID_1fcd3] = 1016, + [BNXT_ULP_CLASS_HID_aa67] = 1017, + [BNXT_ULP_CLASS_HID_aca7] = 1018, + [BNXT_ULP_CLASS_HID_efe7] = 1019, + [BNXT_ULP_CLASS_HID_f227] = 1020, + [BNXT_ULP_CLASS_HID_a52b] = 1021, + [BNXT_ULP_CLASS_HID_a86b] = 1022, + [BNXT_ULP_CLASS_HID_eaab] = 1023, + [BNXT_ULP_CLASS_HID_edeb] = 1024, + [BNXT_ULP_CLASS_HID_1bb2b] = 1025, + [BNXT_ULP_CLASS_HID_1be6b] = 1026, + [BNXT_ULP_CLASS_HID_1c0ab] = 1027, + [BNXT_ULP_CLASS_HID_1e3eb] = 1028, + [BNXT_ULP_CLASS_HID_1c067] = 1029, + [BNXT_ULP_CLASS_HID_1e2a7] = 1030, + [BNXT_ULP_CLASS_HID_1c5e7] = 1031, + [BNXT_ULP_CLASS_HID_1e827] = 1032, + [BNXT_ULP_CLASS_HID_cd8b] = 1033, + [BNXT_ULP_CLASS_HID_f0cb] = 1034, + [BNXT_ULP_CLASS_HID_d30b] = 1035, + [BNXT_ULP_CLASS_HID_f64b] = 1036, + [BNXT_ULP_CLASS_HID_c8bf] = 1037, + [BNXT_ULP_CLASS_HID_ebff] = 1038, + [BNXT_ULP_CLASS_HID_ce3f] = 1039, + [BNXT_ULP_CLASS_HID_f17f] = 1040, + [BNXT_ULP_CLASS_HID_18263] = 1041, + [BNXT_ULP_CLASS_HID_1a4a3] = 1042, + [BNXT_ULP_CLASS_HID_1c7e3] = 1043, + [BNXT_ULP_CLASS_HID_1ea23] = 1044, + [BNXT_ULP_CLASS_HID_186bf] = 1045, + [BNXT_ULP_CLASS_HID_1a9ff] = 1046, + [BNXT_ULP_CLASS_HID_1cc3f] = 1047, + [BNXT_ULP_CLASS_HID_1ef7f] = 1048, + [BNXT_ULP_CLASS_HID_94c3] = 1049, + [BNXT_ULP_CLASS_HID_b703] = 1050, + [BNXT_ULP_CLASS_HID_da43] = 1051, + [BNXT_ULP_CLASS_HID_fc83] = 1052, + [BNXT_ULP_CLASS_HID_8ff7] = 1053, + [BNXT_ULP_CLASS_HID_b237] = 1054, + [BNXT_ULP_CLASS_HID_d577] = 1055, + [BNXT_ULP_CLASS_HID_f7b7] = 1056, + [BNXT_ULP_CLASS_HID_1a5f7] = 1057, + [BNXT_ULP_CLASS_HID_1a837] = 1058, + [BNXT_ULP_CLASS_HID_1eb77] = 1059, + [BNXT_ULP_CLASS_HID_1edb7] = 1060, + [BNXT_ULP_CLASS_HID_1aac3] = 1061, + [BNXT_ULP_CLASS_HID_1ad03] = 1062, + [BNXT_ULP_CLASS_HID_1f043] = 1063, + [BNXT_ULP_CLASS_HID_1f283] = 1064, + [BNXT_ULP_CLASS_HID_b857] = 1065, + [BNXT_ULP_CLASS_HID_ba97] = 1066, + [BNXT_ULP_CLASS_HID_fdd7] = 1067, + [BNXT_ULP_CLASS_HID_e017] = 1068, + [BNXT_ULP_CLASS_HID_b31b] = 1069, + [BNXT_ULP_CLASS_HID_b65b] = 1070, + [BNXT_ULP_CLASS_HID_f89b] = 1071, + [BNXT_ULP_CLASS_HID_fbdb] = 1072, + [BNXT_ULP_CLASS_HID_1c91b] = 1073, + [BNXT_ULP_CLASS_HID_1ec5b] = 1074, + [BNXT_ULP_CLASS_HID_1ce9b] = 1075, + [BNXT_ULP_CLASS_HID_1f1db] = 1076, + [BNXT_ULP_CLASS_HID_1ce57] = 1077, + [BNXT_ULP_CLASS_HID_1f097] = 1078, + [BNXT_ULP_CLASS_HID_1d3d7] = 1079, + [BNXT_ULP_CLASS_HID_1f617] = 1080, + [BNXT_ULP_CLASS_HID_a3bb] = 1081, + [BNXT_ULP_CLASS_HID_a6fb] = 1082, + [BNXT_ULP_CLASS_HID_e93b] = 1083, + [BNXT_ULP_CLASS_HID_ec7b] = 1084, + [BNXT_ULP_CLASS_HID_9f6f] = 1085, + [BNXT_ULP_CLASS_HID_a1af] = 1086, + [BNXT_ULP_CLASS_HID_e4ef] = 1087, + [BNXT_ULP_CLASS_HID_e72f] = 1088, + [BNXT_ULP_CLASS_HID_1b56f] = 1089, + [BNXT_ULP_CLASS_HID_1b7af] = 1090, + [BNXT_ULP_CLASS_HID_1faef] = 1091, + [BNXT_ULP_CLASS_HID_1fd2f] = 1092, + [BNXT_ULP_CLASS_HID_1b9bb] = 1093, + [BNXT_ULP_CLASS_HID_1bcfb] = 1094, + [BNXT_ULP_CLASS_HID_1ff3b] = 1095, + [BNXT_ULP_CLASS_HID_1e27b] = 1096, + [BNXT_ULP_CLASS_HID_c7cf] = 1097, + [BNXT_ULP_CLASS_HID_ea0f] = 1098, + [BNXT_ULP_CLASS_HID_cd4f] = 1099, + [BNXT_ULP_CLASS_HID_ef8f] = 1100, + [BNXT_ULP_CLASS_HID_c2f3] = 1101, + [BNXT_ULP_CLASS_HID_e533] = 1102, + [BNXT_ULP_CLASS_HID_c873] = 1103, + [BNXT_ULP_CLASS_HID_eab3] = 1104, + [BNXT_ULP_CLASS_HID_1d8f3] = 1105, + [BNXT_ULP_CLASS_HID_1fb33] = 1106, + [BNXT_ULP_CLASS_HID_1c127] = 1107, + [BNXT_ULP_CLASS_HID_1e467] = 1108, + [BNXT_ULP_CLASS_HID_180f3] = 1109, + [BNXT_ULP_CLASS_HID_1a333] = 1110, + [BNXT_ULP_CLASS_HID_1c673] = 1111, + [BNXT_ULP_CLASS_HID_1e8b3] = 1112, + [BNXT_ULP_CLASS_HID_8e07] = 1113, + [BNXT_ULP_CLASS_HID_b147] = 1114, + [BNXT_ULP_CLASS_HID_d387] = 1115, + [BNXT_ULP_CLASS_HID_f6c7] = 1116, + [BNXT_ULP_CLASS_HID_89cb] = 1117, + [BNXT_ULP_CLASS_HID_ac0b] = 1118, + [BNXT_ULP_CLASS_HID_cf4b] = 1119, + [BNXT_ULP_CLASS_HID_f18b] = 1120, + [BNXT_ULP_CLASS_HID_19fcb] = 1121, + [BNXT_ULP_CLASS_HID_1a20b] = 1122, + [BNXT_ULP_CLASS_HID_1e54b] = 1123, + [BNXT_ULP_CLASS_HID_1e78b] = 1124, + [BNXT_ULP_CLASS_HID_1a407] = 1125, + [BNXT_ULP_CLASS_HID_1a747] = 1126, + [BNXT_ULP_CLASS_HID_1e987] = 1127, + [BNXT_ULP_CLASS_HID_1ecc7] = 1128, + [BNXT_ULP_CLASS_HID_b1ab] = 1129, + [BNXT_ULP_CLASS_HID_b4eb] = 1130, + [BNXT_ULP_CLASS_HID_f72b] = 1131, + [BNXT_ULP_CLASS_HID_fa6b] = 1132, + [BNXT_ULP_CLASS_HID_ad5f] = 1133, + [BNXT_ULP_CLASS_HID_af9f] = 1134, + [BNXT_ULP_CLASS_HID_f2df] = 1135, + [BNXT_ULP_CLASS_HID_f51f] = 1136, + [BNXT_ULP_CLASS_HID_1c35f] = 1137, + [BNXT_ULP_CLASS_HID_1e59f] = 1138, + [BNXT_ULP_CLASS_HID_1c8df] = 1139, + [BNXT_ULP_CLASS_HID_1eb1f] = 1140, + [BNXT_ULP_CLASS_HID_1c7ab] = 1141, + [BNXT_ULP_CLASS_HID_1eaeb] = 1142, + [BNXT_ULP_CLASS_HID_1cd2b] = 1143, + [BNXT_ULP_CLASS_HID_1f06b] = 1144, + [BNXT_ULP_CLASS_HID_9177] = 1145, + [BNXT_ULP_CLASS_HID_b3b7] = 1146, + [BNXT_ULP_CLASS_HID_d6f7] = 1147, + [BNXT_ULP_CLASS_HID_f937] = 1148, + [BNXT_ULP_CLASS_HID_8c3b] = 1149, + [BNXT_ULP_CLASS_HID_af7b] = 1150, + [BNXT_ULP_CLASS_HID_d1bb] = 1151, + [BNXT_ULP_CLASS_HID_f4fb] = 1152, + [BNXT_ULP_CLASS_HID_1a23b] = 1153, + [BNXT_ULP_CLASS_HID_1a57b] = 1154, + [BNXT_ULP_CLASS_HID_1e7bb] = 1155, + [BNXT_ULP_CLASS_HID_1eafb] = 1156, + [BNXT_ULP_CLASS_HID_1a777] = 1157, + [BNXT_ULP_CLASS_HID_1a9b7] = 1158, + [BNXT_ULP_CLASS_HID_1ecf7] = 1159, + [BNXT_ULP_CLASS_HID_1ef37] = 1160, + [BNXT_ULP_CLASS_HID_b49b] = 1161, + [BNXT_ULP_CLASS_HID_b7db] = 1162, + [BNXT_ULP_CLASS_HID_fa1b] = 1163, + [BNXT_ULP_CLASS_HID_fd5b] = 1164, + [BNXT_ULP_CLASS_HID_b04f] = 1165, + [BNXT_ULP_CLASS_HID_b28f] = 1166, + [BNXT_ULP_CLASS_HID_f5cf] = 1167, + [BNXT_ULP_CLASS_HID_f80f] = 1168, + [BNXT_ULP_CLASS_HID_1c64f] = 1169, + [BNXT_ULP_CLASS_HID_1e88f] = 1170, + [BNXT_ULP_CLASS_HID_1cbcf] = 1171, + [BNXT_ULP_CLASS_HID_1ee0f] = 1172, + [BNXT_ULP_CLASS_HID_1ca9b] = 1173, + [BNXT_ULP_CLASS_HID_1eddb] = 1174, + [BNXT_ULP_CLASS_HID_1d01b] = 1175, + [BNXT_ULP_CLASS_HID_1f35b] = 1176, + [BNXT_ULP_CLASS_HID_8b4b] = 1177, + [BNXT_ULP_CLASS_HID_ad8b] = 1178, + [BNXT_ULP_CLASS_HID_d0cb] = 1179, + [BNXT_ULP_CLASS_HID_f30b] = 1180, + [BNXT_ULP_CLASS_HID_867f] = 1181, + [BNXT_ULP_CLASS_HID_a8bf] = 1182, + [BNXT_ULP_CLASS_HID_cbff] = 1183, + [BNXT_ULP_CLASS_HID_ee3f] = 1184, + [BNXT_ULP_CLASS_HID_19c7f] = 1185, + [BNXT_ULP_CLASS_HID_1bebf] = 1186, + [BNXT_ULP_CLASS_HID_1e1ff] = 1187, + [BNXT_ULP_CLASS_HID_1e43f] = 1188, + [BNXT_ULP_CLASS_HID_1a14b] = 1189, + [BNXT_ULP_CLASS_HID_1a38b] = 1190, + [BNXT_ULP_CLASS_HID_1e6cb] = 1191, + [BNXT_ULP_CLASS_HID_1e90b] = 1192, + [BNXT_ULP_CLASS_HID_aedf] = 1193, + [BNXT_ULP_CLASS_HID_b11f] = 1194, + [BNXT_ULP_CLASS_HID_f45f] = 1195, + [BNXT_ULP_CLASS_HID_f69f] = 1196, + [BNXT_ULP_CLASS_HID_a983] = 1197, + [BNXT_ULP_CLASS_HID_acc3] = 1198, + [BNXT_ULP_CLASS_HID_ef03] = 1199, + [BNXT_ULP_CLASS_HID_f243] = 1200, + [BNXT_ULP_CLASS_HID_1bf83] = 1201, + [BNXT_ULP_CLASS_HID_1e2c3] = 1202, + [BNXT_ULP_CLASS_HID_1c503] = 1203, + [BNXT_ULP_CLASS_HID_1e843] = 1204, + [BNXT_ULP_CLASS_HID_1c4df] = 1205, + [BNXT_ULP_CLASS_HID_1e71f] = 1206, + [BNXT_ULP_CLASS_HID_1ca5f] = 1207, + [BNXT_ULP_CLASS_HID_1ec9f] = 1208, + [BNXT_ULP_CLASS_HID_2523] = 1209, + [BNXT_ULP_CLASS_HID_2bef] = 1210, + [BNXT_ULP_CLASS_HID_2693] = 1211, + [BNXT_ULP_CLASS_HID_4f73] = 1212, + [BNXT_ULP_CLASS_HID_4a27] = 1213, + [BNXT_ULP_CLASS_HID_164b] = 1214, + [BNXT_ULP_CLASS_HID_117f] = 1215, + [BNXT_ULP_CLASS_HID_39df] = 1216, + [BNXT_ULP_CLASS_HID_3483] = 1217, + [BNXT_ULP_CLASS_HID_20d7] = 1218, + [BNXT_ULP_CLASS_HID_48b7] = 1219, + [BNXT_ULP_CLASS_HID_447b] = 1220, + [BNXT_ULP_CLASS_HID_0f8f] = 1221, + [BNXT_ULP_CLASS_HID_0ab3] = 1222, + [BNXT_ULP_CLASS_HID_3313] = 1223, + [BNXT_ULP_CLASS_HID_2ec7] = 1224, + [BNXT_ULP_CLASS_HID_257b7] = 1225, + [BNXT_ULP_CLASS_HID_24467] = 1226, + [BNXT_ULP_CLASS_HID_23fbb] = 1227, + [BNXT_ULP_CLASS_HID_252cb] = 1228, + [BNXT_ULP_CLASS_HID_21e7f] = 1229, + [BNXT_ULP_CLASS_HID_20b2f] = 1230, + [BNXT_ULP_CLASS_HID_20663] = 1231, + [BNXT_ULP_CLASS_HID_219b3] = 1232, + [BNXT_ULP_CLASS_HID_24213] = 1233, + [BNXT_ULP_CLASS_HID_22ec3] = 1234, + [BNXT_ULP_CLASS_HID_22a17] = 1235, + [BNXT_ULP_CLASS_HID_23d27] = 1236, + [BNXT_ULP_CLASS_HID_208db] = 1237, + [BNXT_ULP_CLASS_HID_25277] = 1238, + [BNXT_ULP_CLASS_HID_24d8b] = 1239, + [BNXT_ULP_CLASS_HID_203ef] = 1240, + [BNXT_ULP_CLASS_HID_2517b] = 1241, + [BNXT_ULP_CLASS_HID_23e2b] = 1242, + [BNXT_ULP_CLASS_HID_2397f] = 1243, + [BNXT_ULP_CLASS_HID_24c8f] = 1244, + [BNXT_ULP_CLASS_HID_21823] = 1245, + [BNXT_ULP_CLASS_HID_20513] = 1246, + [BNXT_ULP_CLASS_HID_20027] = 1247, + [BNXT_ULP_CLASS_HID_21377] = 1248, + [BNXT_ULP_CLASS_HID_23bd7] = 1249, + [BNXT_ULP_CLASS_HID_22887] = 1250, + [BNXT_ULP_CLASS_HID_223db] = 1251, + [BNXT_ULP_CLASS_HID_236eb] = 1252, + [BNXT_ULP_CLASS_HID_2029f] = 1253, + [BNXT_ULP_CLASS_HID_24c3b] = 1254, + [BNXT_ULP_CLASS_HID_2474f] = 1255, + [BNXT_ULP_CLASS_HID_25a9f] = 1256, + [BNXT_ULP_CLASS_HID_24b3f] = 1257, + [BNXT_ULP_CLASS_HID_237ef] = 1258, + [BNXT_ULP_CLASS_HID_23323] = 1259, + [BNXT_ULP_CLASS_HID_24673] = 1260, + [BNXT_ULP_CLASS_HID_211e7] = 1261, + [BNXT_ULP_CLASS_HID_25b83] = 1262, + [BNXT_ULP_CLASS_HID_256d7] = 1263, + [BNXT_ULP_CLASS_HID_20d3b] = 1264, + [BNXT_ULP_CLASS_HID_2359b] = 1265, + [BNXT_ULP_CLASS_HID_2224b] = 1266, + [BNXT_ULP_CLASS_HID_21d9f] = 1267, + [BNXT_ULP_CLASS_HID_230af] = 1268, + [BNXT_ULP_CLASS_HID_2590f] = 1269, + [BNXT_ULP_CLASS_HID_245ff] = 1270, + [BNXT_ULP_CLASS_HID_24133] = 1271, + [BNXT_ULP_CLASS_HID_25443] = 1272, + [BNXT_ULP_CLASS_HID_244e3] = 1273, + [BNXT_ULP_CLASS_HID_231d3] = 1274, + [BNXT_ULP_CLASS_HID_22ce7] = 1275, + [BNXT_ULP_CLASS_HID_24037] = 1276, + [BNXT_ULP_CLASS_HID_20bab] = 1277, + [BNXT_ULP_CLASS_HID_25547] = 1278, + [BNXT_ULP_CLASS_HID_2509b] = 1279, + [BNXT_ULP_CLASS_HID_206ff] = 1280, + [BNXT_ULP_CLASS_HID_22f5f] = 1281, + [BNXT_ULP_CLASS_HID_21c0f] = 1282, + [BNXT_ULP_CLASS_HID_21743] = 1283, + [BNXT_ULP_CLASS_HID_22a93] = 1284, + [BNXT_ULP_CLASS_HID_252f3] = 1285, + [BNXT_ULP_CLASS_HID_23fa3] = 1286, + [BNXT_ULP_CLASS_HID_23af7] = 1287, + [BNXT_ULP_CLASS_HID_24e07] = 1288, + [BNXT_ULP_CLASS_HID_2322f] = 1289, + [BNXT_ULP_CLASS_HID_21f1f] = 1290, + [BNXT_ULP_CLASS_HID_21a53] = 1291, + [BNXT_ULP_CLASS_HID_22d63] = 1292, + [BNXT_ULP_CLASS_HID_255c3] = 1293, + [BNXT_ULP_CLASS_HID_242b3] = 1294, + [BNXT_ULP_CLASS_HID_23dc7] = 1295, + [BNXT_ULP_CLASS_HID_25117] = 1296, + [BNXT_ULP_CLASS_HID_22c13] = 1297, + [BNXT_ULP_CLASS_HID_218c3] = 1298, + [BNXT_ULP_CLASS_HID_21417] = 1299, + [BNXT_ULP_CLASS_HID_22727] = 1300, + [BNXT_ULP_CLASS_HID_24f87] = 1301, + [BNXT_ULP_CLASS_HID_23c77] = 1302, + [BNXT_ULP_CLASS_HID_2378b] = 1303, + [BNXT_ULP_CLASS_HID_24adb] = 1304, + [BNXT_ULP_CLASS_HID_257b] = 1305, + [BNXT_ULP_CLASS_HID_2bb7] = 1306, + [BNXT_ULP_CLASS_HID_1867] = 1307, + [BNXT_ULP_CLASS_HID_4f2b] = 1308, + [BNXT_ULP_CLASS_HID_3c1b] = 1309, + [BNXT_ULP_CLASS_HID_1613] = 1310, + [BNXT_ULP_CLASS_HID_02c3] = 1311, + [BNXT_ULP_CLASS_HID_3987] = 1312, + [BNXT_ULP_CLASS_HID_2677] = 1313, + [BNXT_ULP_CLASS_HID_122b] = 1314, + [BNXT_ULP_CLASS_HID_48ef] = 1315, + [BNXT_ULP_CLASS_HID_35df] = 1316, + [BNXT_ULP_CLASS_HID_0fd7] = 1317, + [BNXT_ULP_CLASS_HID_5973] = 1318, + [BNXT_ULP_CLASS_HID_334b] = 1319, + [BNXT_ULP_CLASS_HID_203b] = 1320, + [BNXT_ULP_CLASS_HID_25797] = 1321, + [BNXT_ULP_CLASS_HID_285eb] = 1322, + [BNXT_ULP_CLASS_HID_310eb] = 1323, + [BNXT_ULP_CLASS_HID_39beb] = 1324, + [BNXT_ULP_CLASS_HID_24447] = 1325, + [BNXT_ULP_CLASS_HID_2cf47] = 1326, + [BNXT_ULP_CLASS_HID_35a47] = 1327, + [BNXT_ULP_CLASS_HID_3889b] = 1328, + [BNXT_ULP_CLASS_HID_23f9b] = 1329, + [BNXT_ULP_CLASS_HID_2ca9b] = 1330, + [BNXT_ULP_CLASS_HID_3559b] = 1331, + [BNXT_ULP_CLASS_HID_383ef] = 1332, + [BNXT_ULP_CLASS_HID_252eb] = 1333, + [BNXT_ULP_CLASS_HID_2813f] = 1334, + [BNXT_ULP_CLASS_HID_30c3f] = 1335, + [BNXT_ULP_CLASS_HID_3973f] = 1336, + [BNXT_ULP_CLASS_HID_21e5f] = 1337, + [BNXT_ULP_CLASS_HID_2a95f] = 1338, + [BNXT_ULP_CLASS_HID_3345f] = 1339, + [BNXT_ULP_CLASS_HID_3bf5f] = 1340, + [BNXT_ULP_CLASS_HID_20b0f] = 1341, + [BNXT_ULP_CLASS_HID_2960f] = 1342, + [BNXT_ULP_CLASS_HID_3210f] = 1343, + [BNXT_ULP_CLASS_HID_3ac0f] = 1344, + [BNXT_ULP_CLASS_HID_20643] = 1345, + [BNXT_ULP_CLASS_HID_29143] = 1346, + [BNXT_ULP_CLASS_HID_31c43] = 1347, + [BNXT_ULP_CLASS_HID_3a743] = 1348, + [BNXT_ULP_CLASS_HID_21993] = 1349, + [BNXT_ULP_CLASS_HID_2a493] = 1350, + [BNXT_ULP_CLASS_HID_32f93] = 1351, + [BNXT_ULP_CLASS_HID_3ba93] = 1352, + [BNXT_ULP_CLASS_HID_24233] = 1353, + [BNXT_ULP_CLASS_HID_2cd33] = 1354, + [BNXT_ULP_CLASS_HID_35833] = 1355, + [BNXT_ULP_CLASS_HID_38607] = 1356, + [BNXT_ULP_CLASS_HID_22ee3] = 1357, + [BNXT_ULP_CLASS_HID_2b9e3] = 1358, + [BNXT_ULP_CLASS_HID_344e3] = 1359, + [BNXT_ULP_CLASS_HID_3cfe3] = 1360, + [BNXT_ULP_CLASS_HID_22a37] = 1361, + [BNXT_ULP_CLASS_HID_2b537] = 1362, + [BNXT_ULP_CLASS_HID_34037] = 1363, + [BNXT_ULP_CLASS_HID_3cb37] = 1364, + [BNXT_ULP_CLASS_HID_23d07] = 1365, + [BNXT_ULP_CLASS_HID_2c807] = 1366, + [BNXT_ULP_CLASS_HID_35307] = 1367, + [BNXT_ULP_CLASS_HID_3815b] = 1368, + [BNXT_ULP_CLASS_HID_208fb] = 1369, + [BNXT_ULP_CLASS_HID_293fb] = 1370, + [BNXT_ULP_CLASS_HID_31efb] = 1371, + [BNXT_ULP_CLASS_HID_3a9fb] = 1372, + [BNXT_ULP_CLASS_HID_25257] = 1373, + [BNXT_ULP_CLASS_HID_280ab] = 1374, + [BNXT_ULP_CLASS_HID_30bab] = 1375, + [BNXT_ULP_CLASS_HID_396ab] = 1376, + [BNXT_ULP_CLASS_HID_24dab] = 1377, + [BNXT_ULP_CLASS_HID_2d8ab] = 1378, + [BNXT_ULP_CLASS_HID_306ff] = 1379, + [BNXT_ULP_CLASS_HID_391ff] = 1380, + [BNXT_ULP_CLASS_HID_203cf] = 1381, + [BNXT_ULP_CLASS_HID_28ecf] = 1382, + [BNXT_ULP_CLASS_HID_319cf] = 1383, + [BNXT_ULP_CLASS_HID_3a4cf] = 1384, + [BNXT_ULP_CLASS_HID_2515b] = 1385, + [BNXT_ULP_CLASS_HID_2dc5b] = 1386, + [BNXT_ULP_CLASS_HID_30aaf] = 1387, + [BNXT_ULP_CLASS_HID_395af] = 1388, + [BNXT_ULP_CLASS_HID_23e0b] = 1389, + [BNXT_ULP_CLASS_HID_2c90b] = 1390, + [BNXT_ULP_CLASS_HID_3540b] = 1391, + [BNXT_ULP_CLASS_HID_3825f] = 1392, + [BNXT_ULP_CLASS_HID_2395f] = 1393, + [BNXT_ULP_CLASS_HID_2c45f] = 1394, + [BNXT_ULP_CLASS_HID_34f5f] = 1395, + [BNXT_ULP_CLASS_HID_3da5f] = 1396, + [BNXT_ULP_CLASS_HID_24caf] = 1397, + [BNXT_ULP_CLASS_HID_2d7af] = 1398, + [BNXT_ULP_CLASS_HID_305e3] = 1399, + [BNXT_ULP_CLASS_HID_390e3] = 1400, + [BNXT_ULP_CLASS_HID_21803] = 1401, + [BNXT_ULP_CLASS_HID_2a303] = 1402, + [BNXT_ULP_CLASS_HID_32e03] = 1403, + [BNXT_ULP_CLASS_HID_3b903] = 1404, + [BNXT_ULP_CLASS_HID_20533] = 1405, + [BNXT_ULP_CLASS_HID_29033] = 1406, + [BNXT_ULP_CLASS_HID_31b33] = 1407, + [BNXT_ULP_CLASS_HID_3a633] = 1408, + [BNXT_ULP_CLASS_HID_20007] = 1409, + [BNXT_ULP_CLASS_HID_28b07] = 1410, + [BNXT_ULP_CLASS_HID_31607] = 1411, + [BNXT_ULP_CLASS_HID_3a107] = 1412, + [BNXT_ULP_CLASS_HID_21357] = 1413, + [BNXT_ULP_CLASS_HID_29e57] = 1414, + [BNXT_ULP_CLASS_HID_32957] = 1415, + [BNXT_ULP_CLASS_HID_3b457] = 1416, + [BNXT_ULP_CLASS_HID_23bf7] = 1417, + [BNXT_ULP_CLASS_HID_2c6f7] = 1418, + [BNXT_ULP_CLASS_HID_351f7] = 1419, + [BNXT_ULP_CLASS_HID_3dcf7] = 1420, + [BNXT_ULP_CLASS_HID_228a7] = 1421, + [BNXT_ULP_CLASS_HID_2b3a7] = 1422, + [BNXT_ULP_CLASS_HID_33ea7] = 1423, + [BNXT_ULP_CLASS_HID_3c9a7] = 1424, + [BNXT_ULP_CLASS_HID_223fb] = 1425, + [BNXT_ULP_CLASS_HID_2aefb] = 1426, + [BNXT_ULP_CLASS_HID_339fb] = 1427, + [BNXT_ULP_CLASS_HID_3c4fb] = 1428, + [BNXT_ULP_CLASS_HID_236cb] = 1429, + [BNXT_ULP_CLASS_HID_2c1cb] = 1430, + [BNXT_ULP_CLASS_HID_34ccb] = 1431, + [BNXT_ULP_CLASS_HID_3d7cb] = 1432, + [BNXT_ULP_CLASS_HID_202bf] = 1433, + [BNXT_ULP_CLASS_HID_28dbf] = 1434, + [BNXT_ULP_CLASS_HID_318bf] = 1435, + [BNXT_ULP_CLASS_HID_3a3bf] = 1436, + [BNXT_ULP_CLASS_HID_24c1b] = 1437, + [BNXT_ULP_CLASS_HID_2d71b] = 1438, + [BNXT_ULP_CLASS_HID_3056f] = 1439, + [BNXT_ULP_CLASS_HID_3906f] = 1440, + [BNXT_ULP_CLASS_HID_2476f] = 1441, + [BNXT_ULP_CLASS_HID_2d26f] = 1442, + [BNXT_ULP_CLASS_HID_300a3] = 1443, + [BNXT_ULP_CLASS_HID_38ba3] = 1444, + [BNXT_ULP_CLASS_HID_25abf] = 1445, + [BNXT_ULP_CLASS_HID_288f3] = 1446, + [BNXT_ULP_CLASS_HID_313f3] = 1447, + [BNXT_ULP_CLASS_HID_39ef3] = 1448, + [BNXT_ULP_CLASS_HID_24b1f] = 1449, + [BNXT_ULP_CLASS_HID_2d61f] = 1450, + [BNXT_ULP_CLASS_HID_30453] = 1451, + [BNXT_ULP_CLASS_HID_38f53] = 1452, + [BNXT_ULP_CLASS_HID_237cf] = 1453, + [BNXT_ULP_CLASS_HID_2c2cf] = 1454, + [BNXT_ULP_CLASS_HID_34dcf] = 1455, + [BNXT_ULP_CLASS_HID_3d8cf] = 1456, + [BNXT_ULP_CLASS_HID_23303] = 1457, + [BNXT_ULP_CLASS_HID_2be03] = 1458, + [BNXT_ULP_CLASS_HID_34903] = 1459, + [BNXT_ULP_CLASS_HID_3d403] = 1460, + [BNXT_ULP_CLASS_HID_24653] = 1461, + [BNXT_ULP_CLASS_HID_2d153] = 1462, + [BNXT_ULP_CLASS_HID_35c53] = 1463, + [BNXT_ULP_CLASS_HID_38aa7] = 1464, + [BNXT_ULP_CLASS_HID_211c7] = 1465, + [BNXT_ULP_CLASS_HID_29cc7] = 1466, + [BNXT_ULP_CLASS_HID_327c7] = 1467, + [BNXT_ULP_CLASS_HID_3b2c7] = 1468, + [BNXT_ULP_CLASS_HID_25ba3] = 1469, + [BNXT_ULP_CLASS_HID_289f7] = 1470, + [BNXT_ULP_CLASS_HID_314f7] = 1471, + [BNXT_ULP_CLASS_HID_39ff7] = 1472, + [BNXT_ULP_CLASS_HID_256f7] = 1473, + [BNXT_ULP_CLASS_HID_284cb] = 1474, + [BNXT_ULP_CLASS_HID_30fcb] = 1475, + [BNXT_ULP_CLASS_HID_39acb] = 1476, + [BNXT_ULP_CLASS_HID_20d1b] = 1477, + [BNXT_ULP_CLASS_HID_2981b] = 1478, + [BNXT_ULP_CLASS_HID_3231b] = 1479, + [BNXT_ULP_CLASS_HID_3ae1b] = 1480, + [BNXT_ULP_CLASS_HID_235bb] = 1481, + [BNXT_ULP_CLASS_HID_2c0bb] = 1482, + [BNXT_ULP_CLASS_HID_34bbb] = 1483, + [BNXT_ULP_CLASS_HID_3d6bb] = 1484, + [BNXT_ULP_CLASS_HID_2226b] = 1485, + [BNXT_ULP_CLASS_HID_2ad6b] = 1486, + [BNXT_ULP_CLASS_HID_3386b] = 1487, + [BNXT_ULP_CLASS_HID_3c36b] = 1488, + [BNXT_ULP_CLASS_HID_21dbf] = 1489, + [BNXT_ULP_CLASS_HID_2a8bf] = 1490, + [BNXT_ULP_CLASS_HID_333bf] = 1491, + [BNXT_ULP_CLASS_HID_3bebf] = 1492, + [BNXT_ULP_CLASS_HID_2308f] = 1493, + [BNXT_ULP_CLASS_HID_2bb8f] = 1494, + [BNXT_ULP_CLASS_HID_3468f] = 1495, + [BNXT_ULP_CLASS_HID_3d18f] = 1496, + [BNXT_ULP_CLASS_HID_2592f] = 1497, + [BNXT_ULP_CLASS_HID_28763] = 1498, + [BNXT_ULP_CLASS_HID_31263] = 1499, + [BNXT_ULP_CLASS_HID_39d63] = 1500, + [BNXT_ULP_CLASS_HID_245df] = 1501, + [BNXT_ULP_CLASS_HID_2d0df] = 1502, + [BNXT_ULP_CLASS_HID_35bdf] = 1503, + [BNXT_ULP_CLASS_HID_38a13] = 1504, + [BNXT_ULP_CLASS_HID_24113] = 1505, + [BNXT_ULP_CLASS_HID_2cc13] = 1506, + [BNXT_ULP_CLASS_HID_35713] = 1507, + [BNXT_ULP_CLASS_HID_38567] = 1508, + [BNXT_ULP_CLASS_HID_25463] = 1509, + [BNXT_ULP_CLASS_HID_282b7] = 1510, + [BNXT_ULP_CLASS_HID_30db7] = 1511, + [BNXT_ULP_CLASS_HID_398b7] = 1512, + [BNXT_ULP_CLASS_HID_244c3] = 1513, + [BNXT_ULP_CLASS_HID_2cfc3] = 1514, + [BNXT_ULP_CLASS_HID_35ac3] = 1515, + [BNXT_ULP_CLASS_HID_38917] = 1516, + [BNXT_ULP_CLASS_HID_231f3] = 1517, + [BNXT_ULP_CLASS_HID_2bcf3] = 1518, + [BNXT_ULP_CLASS_HID_347f3] = 1519, + [BNXT_ULP_CLASS_HID_3d2f3] = 1520, + [BNXT_ULP_CLASS_HID_22cc7] = 1521, + [BNXT_ULP_CLASS_HID_2b7c7] = 1522, + [BNXT_ULP_CLASS_HID_342c7] = 1523, + [BNXT_ULP_CLASS_HID_3cdc7] = 1524, + [BNXT_ULP_CLASS_HID_24017] = 1525, + [BNXT_ULP_CLASS_HID_2cb17] = 1526, + [BNXT_ULP_CLASS_HID_35617] = 1527, + [BNXT_ULP_CLASS_HID_3846b] = 1528, + [BNXT_ULP_CLASS_HID_20b8b] = 1529, + [BNXT_ULP_CLASS_HID_2968b] = 1530, + [BNXT_ULP_CLASS_HID_3218b] = 1531, + [BNXT_ULP_CLASS_HID_3ac8b] = 1532, + [BNXT_ULP_CLASS_HID_25567] = 1533, + [BNXT_ULP_CLASS_HID_283bb] = 1534, + [BNXT_ULP_CLASS_HID_30ebb] = 1535, + [BNXT_ULP_CLASS_HID_399bb] = 1536, + [BNXT_ULP_CLASS_HID_250bb] = 1537, + [BNXT_ULP_CLASS_HID_2dbbb] = 1538, + [BNXT_ULP_CLASS_HID_3098f] = 1539, + [BNXT_ULP_CLASS_HID_3948f] = 1540, + [BNXT_ULP_CLASS_HID_206df] = 1541, + [BNXT_ULP_CLASS_HID_291df] = 1542, + [BNXT_ULP_CLASS_HID_31cdf] = 1543, + [BNXT_ULP_CLASS_HID_3a7df] = 1544, + [BNXT_ULP_CLASS_HID_22f7f] = 1545, + [BNXT_ULP_CLASS_HID_2ba7f] = 1546, + [BNXT_ULP_CLASS_HID_3457f] = 1547, + [BNXT_ULP_CLASS_HID_3d07f] = 1548, + [BNXT_ULP_CLASS_HID_21c2f] = 1549, + [BNXT_ULP_CLASS_HID_2a72f] = 1550, + [BNXT_ULP_CLASS_HID_3322f] = 1551, + [BNXT_ULP_CLASS_HID_3bd2f] = 1552, + [BNXT_ULP_CLASS_HID_21763] = 1553, + [BNXT_ULP_CLASS_HID_2a263] = 1554, + [BNXT_ULP_CLASS_HID_32d63] = 1555, + [BNXT_ULP_CLASS_HID_3b863] = 1556, + [BNXT_ULP_CLASS_HID_22ab3] = 1557, + [BNXT_ULP_CLASS_HID_2b5b3] = 1558, + [BNXT_ULP_CLASS_HID_340b3] = 1559, + [BNXT_ULP_CLASS_HID_3cbb3] = 1560, + [BNXT_ULP_CLASS_HID_252d3] = 1561, + [BNXT_ULP_CLASS_HID_28127] = 1562, + [BNXT_ULP_CLASS_HID_30c27] = 1563, + [BNXT_ULP_CLASS_HID_39727] = 1564, + [BNXT_ULP_CLASS_HID_23f83] = 1565, + [BNXT_ULP_CLASS_HID_2ca83] = 1566, + [BNXT_ULP_CLASS_HID_35583] = 1567, + [BNXT_ULP_CLASS_HID_383d7] = 1568, + [BNXT_ULP_CLASS_HID_23ad7] = 1569, + [BNXT_ULP_CLASS_HID_2c5d7] = 1570, + [BNXT_ULP_CLASS_HID_350d7] = 1571, + [BNXT_ULP_CLASS_HID_3dbd7] = 1572, + [BNXT_ULP_CLASS_HID_24e27] = 1573, + [BNXT_ULP_CLASS_HID_2d927] = 1574, + [BNXT_ULP_CLASS_HID_3077b] = 1575, + [BNXT_ULP_CLASS_HID_3927b] = 1576, + [BNXT_ULP_CLASS_HID_2320f] = 1577, + [BNXT_ULP_CLASS_HID_2bd0f] = 1578, + [BNXT_ULP_CLASS_HID_3480f] = 1579, + [BNXT_ULP_CLASS_HID_3d30f] = 1580, + [BNXT_ULP_CLASS_HID_21f3f] = 1581, + [BNXT_ULP_CLASS_HID_2aa3f] = 1582, + [BNXT_ULP_CLASS_HID_3353f] = 1583, + [BNXT_ULP_CLASS_HID_3c03f] = 1584, + [BNXT_ULP_CLASS_HID_21a73] = 1585, + [BNXT_ULP_CLASS_HID_2a573] = 1586, + [BNXT_ULP_CLASS_HID_33073] = 1587, + [BNXT_ULP_CLASS_HID_3bb73] = 1588, + [BNXT_ULP_CLASS_HID_22d43] = 1589, + [BNXT_ULP_CLASS_HID_2b843] = 1590, + [BNXT_ULP_CLASS_HID_34343] = 1591, + [BNXT_ULP_CLASS_HID_3ce43] = 1592, + [BNXT_ULP_CLASS_HID_255e3] = 1593, + [BNXT_ULP_CLASS_HID_28437] = 1594, + [BNXT_ULP_CLASS_HID_30f37] = 1595, + [BNXT_ULP_CLASS_HID_39a37] = 1596, + [BNXT_ULP_CLASS_HID_24293] = 1597, + [BNXT_ULP_CLASS_HID_2cd93] = 1598, + [BNXT_ULP_CLASS_HID_35893] = 1599, + [BNXT_ULP_CLASS_HID_386e7] = 1600, + [BNXT_ULP_CLASS_HID_23de7] = 1601, + [BNXT_ULP_CLASS_HID_2c8e7] = 1602, + [BNXT_ULP_CLASS_HID_353e7] = 1603, + [BNXT_ULP_CLASS_HID_3823b] = 1604, + [BNXT_ULP_CLASS_HID_25137] = 1605, + [BNXT_ULP_CLASS_HID_2dc37] = 1606, + [BNXT_ULP_CLASS_HID_30a0b] = 1607, + [BNXT_ULP_CLASS_HID_3950b] = 1608, + [BNXT_ULP_CLASS_HID_22c33] = 1609, + [BNXT_ULP_CLASS_HID_2b733] = 1610, + [BNXT_ULP_CLASS_HID_34233] = 1611, + [BNXT_ULP_CLASS_HID_3cd33] = 1612, + [BNXT_ULP_CLASS_HID_218e3] = 1613, + [BNXT_ULP_CLASS_HID_2a3e3] = 1614, + [BNXT_ULP_CLASS_HID_32ee3] = 1615, + [BNXT_ULP_CLASS_HID_3b9e3] = 1616, + [BNXT_ULP_CLASS_HID_21437] = 1617, + [BNXT_ULP_CLASS_HID_29f37] = 1618, + [BNXT_ULP_CLASS_HID_32a37] = 1619, + [BNXT_ULP_CLASS_HID_3b537] = 1620, + [BNXT_ULP_CLASS_HID_22707] = 1621, + [BNXT_ULP_CLASS_HID_2b207] = 1622, + [BNXT_ULP_CLASS_HID_33d07] = 1623, + [BNXT_ULP_CLASS_HID_3c807] = 1624, + [BNXT_ULP_CLASS_HID_24fa7] = 1625, + [BNXT_ULP_CLASS_HID_2daa7] = 1626, + [BNXT_ULP_CLASS_HID_308fb] = 1627, + [BNXT_ULP_CLASS_HID_393fb] = 1628, + [BNXT_ULP_CLASS_HID_23c57] = 1629, + [BNXT_ULP_CLASS_HID_2c757] = 1630, + [BNXT_ULP_CLASS_HID_35257] = 1631, + [BNXT_ULP_CLASS_HID_380ab] = 1632, + [BNXT_ULP_CLASS_HID_237ab] = 1633, + [BNXT_ULP_CLASS_HID_2c2ab] = 1634, + [BNXT_ULP_CLASS_HID_34dab] = 1635, + [BNXT_ULP_CLASS_HID_3d8ab] = 1636, + [BNXT_ULP_CLASS_HID_24afb] = 1637, + [BNXT_ULP_CLASS_HID_2d5fb] = 1638, + [BNXT_ULP_CLASS_HID_303cf] = 1639, + [BNXT_ULP_CLASS_HID_38ecf] = 1640, + [BNXT_ULP_CLASS_HID_255b] = 1641, + [BNXT_ULP_CLASS_HID_2b97] = 1642, + [BNXT_ULP_CLASS_HID_1847] = 1643, + [BNXT_ULP_CLASS_HID_4f0b] = 1644, + [BNXT_ULP_CLASS_HID_3c3b] = 1645, + [BNXT_ULP_CLASS_HID_1633] = 1646, + [BNXT_ULP_CLASS_HID_02e3] = 1647, + [BNXT_ULP_CLASS_HID_39a7] = 1648, + [BNXT_ULP_CLASS_HID_2657] = 1649, + [BNXT_ULP_CLASS_HID_120b] = 1650, + [BNXT_ULP_CLASS_HID_48cf] = 1651, + [BNXT_ULP_CLASS_HID_35ff] = 1652, + [BNXT_ULP_CLASS_HID_0ff7] = 1653, + [BNXT_ULP_CLASS_HID_5953] = 1654, + [BNXT_ULP_CLASS_HID_336b] = 1655, + [BNXT_ULP_CLASS_HID_201b] = 1656, + [BNXT_ULP_CLASS_HID_257f7] = 1657, + [BNXT_ULP_CLASS_HID_2858b] = 1658, + [BNXT_ULP_CLASS_HID_3108b] = 1659, + [BNXT_ULP_CLASS_HID_39b8b] = 1660, + [BNXT_ULP_CLASS_HID_24427] = 1661, + [BNXT_ULP_CLASS_HID_2cf27] = 1662, + [BNXT_ULP_CLASS_HID_35a27] = 1663, + [BNXT_ULP_CLASS_HID_388fb] = 1664, + [BNXT_ULP_CLASS_HID_23ffb] = 1665, + [BNXT_ULP_CLASS_HID_2cafb] = 1666, + [BNXT_ULP_CLASS_HID_355fb] = 1667, + [BNXT_ULP_CLASS_HID_3838f] = 1668, + [BNXT_ULP_CLASS_HID_2528b] = 1669, + [BNXT_ULP_CLASS_HID_2815f] = 1670, + [BNXT_ULP_CLASS_HID_30c5f] = 1671, + [BNXT_ULP_CLASS_HID_3975f] = 1672, + [BNXT_ULP_CLASS_HID_21e3f] = 1673, + [BNXT_ULP_CLASS_HID_2a93f] = 1674, + [BNXT_ULP_CLASS_HID_3343f] = 1675, + [BNXT_ULP_CLASS_HID_3bf3f] = 1676, + [BNXT_ULP_CLASS_HID_20b6f] = 1677, + [BNXT_ULP_CLASS_HID_2966f] = 1678, + [BNXT_ULP_CLASS_HID_3216f] = 1679, + [BNXT_ULP_CLASS_HID_3ac6f] = 1680, + [BNXT_ULP_CLASS_HID_20623] = 1681, + [BNXT_ULP_CLASS_HID_29123] = 1682, + [BNXT_ULP_CLASS_HID_31c23] = 1683, + [BNXT_ULP_CLASS_HID_3a723] = 1684, + [BNXT_ULP_CLASS_HID_219f3] = 1685, + [BNXT_ULP_CLASS_HID_2a4f3] = 1686, + [BNXT_ULP_CLASS_HID_32ff3] = 1687, + [BNXT_ULP_CLASS_HID_3baf3] = 1688, + [BNXT_ULP_CLASS_HID_24253] = 1689, + [BNXT_ULP_CLASS_HID_2cd53] = 1690, + [BNXT_ULP_CLASS_HID_35853] = 1691, + [BNXT_ULP_CLASS_HID_38667] = 1692, + [BNXT_ULP_CLASS_HID_22e83] = 1693, + [BNXT_ULP_CLASS_HID_2b983] = 1694, + [BNXT_ULP_CLASS_HID_34483] = 1695, + [BNXT_ULP_CLASS_HID_3cf83] = 1696, + [BNXT_ULP_CLASS_HID_22a57] = 1697, + [BNXT_ULP_CLASS_HID_2b557] = 1698, + [BNXT_ULP_CLASS_HID_34057] = 1699, + [BNXT_ULP_CLASS_HID_3cb57] = 1700, + [BNXT_ULP_CLASS_HID_23d67] = 1701, + [BNXT_ULP_CLASS_HID_2c867] = 1702, + [BNXT_ULP_CLASS_HID_35367] = 1703, + [BNXT_ULP_CLASS_HID_3813b] = 1704, + [BNXT_ULP_CLASS_HID_2089b] = 1705, + [BNXT_ULP_CLASS_HID_2939b] = 1706, + [BNXT_ULP_CLASS_HID_31e9b] = 1707, + [BNXT_ULP_CLASS_HID_3a99b] = 1708, + [BNXT_ULP_CLASS_HID_25237] = 1709, + [BNXT_ULP_CLASS_HID_280cb] = 1710, + [BNXT_ULP_CLASS_HID_30bcb] = 1711, + [BNXT_ULP_CLASS_HID_396cb] = 1712, + [BNXT_ULP_CLASS_HID_24dcb] = 1713, + [BNXT_ULP_CLASS_HID_2d8cb] = 1714, + [BNXT_ULP_CLASS_HID_3069f] = 1715, + [BNXT_ULP_CLASS_HID_3919f] = 1716, + [BNXT_ULP_CLASS_HID_203af] = 1717, + [BNXT_ULP_CLASS_HID_28eaf] = 1718, + [BNXT_ULP_CLASS_HID_319af] = 1719, + [BNXT_ULP_CLASS_HID_3a4af] = 1720, + [BNXT_ULP_CLASS_HID_2513b] = 1721, + [BNXT_ULP_CLASS_HID_2dc3b] = 1722, + [BNXT_ULP_CLASS_HID_30acf] = 1723, + [BNXT_ULP_CLASS_HID_395cf] = 1724, + [BNXT_ULP_CLASS_HID_23e6b] = 1725, + [BNXT_ULP_CLASS_HID_2c96b] = 1726, + [BNXT_ULP_CLASS_HID_3546b] = 1727, + [BNXT_ULP_CLASS_HID_3823f] = 1728, + [BNXT_ULP_CLASS_HID_2393f] = 1729, + [BNXT_ULP_CLASS_HID_2c43f] = 1730, + [BNXT_ULP_CLASS_HID_34f3f] = 1731, + [BNXT_ULP_CLASS_HID_3da3f] = 1732, + [BNXT_ULP_CLASS_HID_24ccf] = 1733, + [BNXT_ULP_CLASS_HID_2d7cf] = 1734, + [BNXT_ULP_CLASS_HID_30583] = 1735, + [BNXT_ULP_CLASS_HID_39083] = 1736, + [BNXT_ULP_CLASS_HID_21863] = 1737, + [BNXT_ULP_CLASS_HID_2a363] = 1738, + [BNXT_ULP_CLASS_HID_32e63] = 1739, + [BNXT_ULP_CLASS_HID_3b963] = 1740, + [BNXT_ULP_CLASS_HID_20553] = 1741, + [BNXT_ULP_CLASS_HID_29053] = 1742, + [BNXT_ULP_CLASS_HID_31b53] = 1743, + [BNXT_ULP_CLASS_HID_3a653] = 1744, + [BNXT_ULP_CLASS_HID_20067] = 1745, + [BNXT_ULP_CLASS_HID_28b67] = 1746, + [BNXT_ULP_CLASS_HID_31667] = 1747, + [BNXT_ULP_CLASS_HID_3a167] = 1748, + [BNXT_ULP_CLASS_HID_21337] = 1749, + [BNXT_ULP_CLASS_HID_29e37] = 1750, + [BNXT_ULP_CLASS_HID_32937] = 1751, + [BNXT_ULP_CLASS_HID_3b437] = 1752, + [BNXT_ULP_CLASS_HID_23b97] = 1753, + [BNXT_ULP_CLASS_HID_2c697] = 1754, + [BNXT_ULP_CLASS_HID_35197] = 1755, + [BNXT_ULP_CLASS_HID_3dc97] = 1756, + [BNXT_ULP_CLASS_HID_228c7] = 1757, + [BNXT_ULP_CLASS_HID_2b3c7] = 1758, + [BNXT_ULP_CLASS_HID_33ec7] = 1759, + [BNXT_ULP_CLASS_HID_3c9c7] = 1760, + [BNXT_ULP_CLASS_HID_2239b] = 1761, + [BNXT_ULP_CLASS_HID_2ae9b] = 1762, + [BNXT_ULP_CLASS_HID_3399b] = 1763, + [BNXT_ULP_CLASS_HID_3c49b] = 1764, + [BNXT_ULP_CLASS_HID_236ab] = 1765, + [BNXT_ULP_CLASS_HID_2c1ab] = 1766, + [BNXT_ULP_CLASS_HID_34cab] = 1767, + [BNXT_ULP_CLASS_HID_3d7ab] = 1768, + [BNXT_ULP_CLASS_HID_202df] = 1769, + [BNXT_ULP_CLASS_HID_28ddf] = 1770, + [BNXT_ULP_CLASS_HID_318df] = 1771, + [BNXT_ULP_CLASS_HID_3a3df] = 1772, + [BNXT_ULP_CLASS_HID_24c7b] = 1773, + [BNXT_ULP_CLASS_HID_2d77b] = 1774, + [BNXT_ULP_CLASS_HID_3050f] = 1775, + [BNXT_ULP_CLASS_HID_3900f] = 1776, + [BNXT_ULP_CLASS_HID_2470f] = 1777, + [BNXT_ULP_CLASS_HID_2d20f] = 1778, + [BNXT_ULP_CLASS_HID_300c3] = 1779, + [BNXT_ULP_CLASS_HID_38bc3] = 1780, + [BNXT_ULP_CLASS_HID_25adf] = 1781, + [BNXT_ULP_CLASS_HID_28893] = 1782, + [BNXT_ULP_CLASS_HID_31393] = 1783, + [BNXT_ULP_CLASS_HID_39e93] = 1784, + [BNXT_ULP_CLASS_HID_24b7f] = 1785, + [BNXT_ULP_CLASS_HID_2d67f] = 1786, + [BNXT_ULP_CLASS_HID_30433] = 1787, + [BNXT_ULP_CLASS_HID_38f33] = 1788, + [BNXT_ULP_CLASS_HID_237af] = 1789, + [BNXT_ULP_CLASS_HID_2c2af] = 1790, + [BNXT_ULP_CLASS_HID_34daf] = 1791, + [BNXT_ULP_CLASS_HID_3d8af] = 1792, + [BNXT_ULP_CLASS_HID_23363] = 1793, + [BNXT_ULP_CLASS_HID_2be63] = 1794, + [BNXT_ULP_CLASS_HID_34963] = 1795, + [BNXT_ULP_CLASS_HID_3d463] = 1796, + [BNXT_ULP_CLASS_HID_24633] = 1797, + [BNXT_ULP_CLASS_HID_2d133] = 1798, + [BNXT_ULP_CLASS_HID_35c33] = 1799, + [BNXT_ULP_CLASS_HID_38ac7] = 1800, + [BNXT_ULP_CLASS_HID_211a7] = 1801, + [BNXT_ULP_CLASS_HID_29ca7] = 1802, + [BNXT_ULP_CLASS_HID_327a7] = 1803, + [BNXT_ULP_CLASS_HID_3b2a7] = 1804, + [BNXT_ULP_CLASS_HID_25bc3] = 1805, + [BNXT_ULP_CLASS_HID_28997] = 1806, + [BNXT_ULP_CLASS_HID_31497] = 1807, + [BNXT_ULP_CLASS_HID_39f97] = 1808, + [BNXT_ULP_CLASS_HID_25697] = 1809, + [BNXT_ULP_CLASS_HID_284ab] = 1810, + [BNXT_ULP_CLASS_HID_30fab] = 1811, + [BNXT_ULP_CLASS_HID_39aab] = 1812, + [BNXT_ULP_CLASS_HID_20d7b] = 1813, + [BNXT_ULP_CLASS_HID_2987b] = 1814, + [BNXT_ULP_CLASS_HID_3237b] = 1815, + [BNXT_ULP_CLASS_HID_3ae7b] = 1816, + [BNXT_ULP_CLASS_HID_235db] = 1817, + [BNXT_ULP_CLASS_HID_2c0db] = 1818, + [BNXT_ULP_CLASS_HID_34bdb] = 1819, + [BNXT_ULP_CLASS_HID_3d6db] = 1820, + [BNXT_ULP_CLASS_HID_2220b] = 1821, + [BNXT_ULP_CLASS_HID_2ad0b] = 1822, + [BNXT_ULP_CLASS_HID_3380b] = 1823, + [BNXT_ULP_CLASS_HID_3c30b] = 1824, + [BNXT_ULP_CLASS_HID_21ddf] = 1825, + [BNXT_ULP_CLASS_HID_2a8df] = 1826, + [BNXT_ULP_CLASS_HID_333df] = 1827, + [BNXT_ULP_CLASS_HID_3bedf] = 1828, + [BNXT_ULP_CLASS_HID_230ef] = 1829, + [BNXT_ULP_CLASS_HID_2bbef] = 1830, + [BNXT_ULP_CLASS_HID_346ef] = 1831, + [BNXT_ULP_CLASS_HID_3d1ef] = 1832, + [BNXT_ULP_CLASS_HID_2594f] = 1833, + [BNXT_ULP_CLASS_HID_28703] = 1834, + [BNXT_ULP_CLASS_HID_31203] = 1835, + [BNXT_ULP_CLASS_HID_39d03] = 1836, + [BNXT_ULP_CLASS_HID_245bf] = 1837, + [BNXT_ULP_CLASS_HID_2d0bf] = 1838, + [BNXT_ULP_CLASS_HID_35bbf] = 1839, + [BNXT_ULP_CLASS_HID_38a73] = 1840, + [BNXT_ULP_CLASS_HID_24173] = 1841, + [BNXT_ULP_CLASS_HID_2cc73] = 1842, + [BNXT_ULP_CLASS_HID_35773] = 1843, + [BNXT_ULP_CLASS_HID_38507] = 1844, + [BNXT_ULP_CLASS_HID_25403] = 1845, + [BNXT_ULP_CLASS_HID_282d7] = 1846, + [BNXT_ULP_CLASS_HID_30dd7] = 1847, + [BNXT_ULP_CLASS_HID_398d7] = 1848, + [BNXT_ULP_CLASS_HID_244a3] = 1849, + [BNXT_ULP_CLASS_HID_2cfa3] = 1850, + [BNXT_ULP_CLASS_HID_35aa3] = 1851, + [BNXT_ULP_CLASS_HID_38977] = 1852, + [BNXT_ULP_CLASS_HID_23193] = 1853, + [BNXT_ULP_CLASS_HID_2bc93] = 1854, + [BNXT_ULP_CLASS_HID_34793] = 1855, + [BNXT_ULP_CLASS_HID_3d293] = 1856, + [BNXT_ULP_CLASS_HID_22ca7] = 1857, + [BNXT_ULP_CLASS_HID_2b7a7] = 1858, + [BNXT_ULP_CLASS_HID_342a7] = 1859, + [BNXT_ULP_CLASS_HID_3cda7] = 1860, + [BNXT_ULP_CLASS_HID_24077] = 1861, + [BNXT_ULP_CLASS_HID_2cb77] = 1862, + [BNXT_ULP_CLASS_HID_35677] = 1863, + [BNXT_ULP_CLASS_HID_3840b] = 1864, + [BNXT_ULP_CLASS_HID_20beb] = 1865, + [BNXT_ULP_CLASS_HID_296eb] = 1866, + [BNXT_ULP_CLASS_HID_321eb] = 1867, + [BNXT_ULP_CLASS_HID_3aceb] = 1868, + [BNXT_ULP_CLASS_HID_25507] = 1869, + [BNXT_ULP_CLASS_HID_283db] = 1870, + [BNXT_ULP_CLASS_HID_30edb] = 1871, + [BNXT_ULP_CLASS_HID_399db] = 1872, + [BNXT_ULP_CLASS_HID_250db] = 1873, + [BNXT_ULP_CLASS_HID_2dbdb] = 1874, + [BNXT_ULP_CLASS_HID_309ef] = 1875, + [BNXT_ULP_CLASS_HID_394ef] = 1876, + [BNXT_ULP_CLASS_HID_206bf] = 1877, + [BNXT_ULP_CLASS_HID_291bf] = 1878, + [BNXT_ULP_CLASS_HID_31cbf] = 1879, + [BNXT_ULP_CLASS_HID_3a7bf] = 1880, + [BNXT_ULP_CLASS_HID_22f1f] = 1881, + [BNXT_ULP_CLASS_HID_2ba1f] = 1882, + [BNXT_ULP_CLASS_HID_3451f] = 1883, + [BNXT_ULP_CLASS_HID_3d01f] = 1884, + [BNXT_ULP_CLASS_HID_21c4f] = 1885, + [BNXT_ULP_CLASS_HID_2a74f] = 1886, + [BNXT_ULP_CLASS_HID_3324f] = 1887, + [BNXT_ULP_CLASS_HID_3bd4f] = 1888, + [BNXT_ULP_CLASS_HID_21703] = 1889, + [BNXT_ULP_CLASS_HID_2a203] = 1890, + [BNXT_ULP_CLASS_HID_32d03] = 1891, + [BNXT_ULP_CLASS_HID_3b803] = 1892, + [BNXT_ULP_CLASS_HID_22ad3] = 1893, + [BNXT_ULP_CLASS_HID_2b5d3] = 1894, + [BNXT_ULP_CLASS_HID_340d3] = 1895, + [BNXT_ULP_CLASS_HID_3cbd3] = 1896, + [BNXT_ULP_CLASS_HID_252b3] = 1897, + [BNXT_ULP_CLASS_HID_28147] = 1898, + [BNXT_ULP_CLASS_HID_30c47] = 1899, + [BNXT_ULP_CLASS_HID_39747] = 1900, + [BNXT_ULP_CLASS_HID_23fe3] = 1901, + [BNXT_ULP_CLASS_HID_2cae3] = 1902, + [BNXT_ULP_CLASS_HID_355e3] = 1903, + [BNXT_ULP_CLASS_HID_383b7] = 1904, + [BNXT_ULP_CLASS_HID_23ab7] = 1905, + [BNXT_ULP_CLASS_HID_2c5b7] = 1906, + [BNXT_ULP_CLASS_HID_350b7] = 1907, + [BNXT_ULP_CLASS_HID_3dbb7] = 1908, + [BNXT_ULP_CLASS_HID_24e47] = 1909, + [BNXT_ULP_CLASS_HID_2d947] = 1910, + [BNXT_ULP_CLASS_HID_3071b] = 1911, + [BNXT_ULP_CLASS_HID_3921b] = 1912, + [BNXT_ULP_CLASS_HID_2326f] = 1913, + [BNXT_ULP_CLASS_HID_2bd6f] = 1914, + [BNXT_ULP_CLASS_HID_3486f] = 1915, + [BNXT_ULP_CLASS_HID_3d36f] = 1916, + [BNXT_ULP_CLASS_HID_21f5f] = 1917, + [BNXT_ULP_CLASS_HID_2aa5f] = 1918, + [BNXT_ULP_CLASS_HID_3355f] = 1919, + [BNXT_ULP_CLASS_HID_3c05f] = 1920, + [BNXT_ULP_CLASS_HID_21a13] = 1921, + [BNXT_ULP_CLASS_HID_2a513] = 1922, + [BNXT_ULP_CLASS_HID_33013] = 1923, + [BNXT_ULP_CLASS_HID_3bb13] = 1924, + [BNXT_ULP_CLASS_HID_22d23] = 1925, + [BNXT_ULP_CLASS_HID_2b823] = 1926, + [BNXT_ULP_CLASS_HID_34323] = 1927, + [BNXT_ULP_CLASS_HID_3ce23] = 1928, + [BNXT_ULP_CLASS_HID_25583] = 1929, + [BNXT_ULP_CLASS_HID_28457] = 1930, + [BNXT_ULP_CLASS_HID_30f57] = 1931, + [BNXT_ULP_CLASS_HID_39a57] = 1932, + [BNXT_ULP_CLASS_HID_242f3] = 1933, + [BNXT_ULP_CLASS_HID_2cdf3] = 1934, + [BNXT_ULP_CLASS_HID_358f3] = 1935, + [BNXT_ULP_CLASS_HID_38687] = 1936, + [BNXT_ULP_CLASS_HID_23d87] = 1937, + [BNXT_ULP_CLASS_HID_2c887] = 1938, + [BNXT_ULP_CLASS_HID_35387] = 1939, + [BNXT_ULP_CLASS_HID_3825b] = 1940, + [BNXT_ULP_CLASS_HID_25157] = 1941, + [BNXT_ULP_CLASS_HID_2dc57] = 1942, + [BNXT_ULP_CLASS_HID_30a6b] = 1943, + [BNXT_ULP_CLASS_HID_3956b] = 1944, + [BNXT_ULP_CLASS_HID_22c53] = 1945, + [BNXT_ULP_CLASS_HID_2b753] = 1946, + [BNXT_ULP_CLASS_HID_34253] = 1947, + [BNXT_ULP_CLASS_HID_3cd53] = 1948, + [BNXT_ULP_CLASS_HID_21883] = 1949, + [BNXT_ULP_CLASS_HID_2a383] = 1950, + [BNXT_ULP_CLASS_HID_32e83] = 1951, + [BNXT_ULP_CLASS_HID_3b983] = 1952, + [BNXT_ULP_CLASS_HID_21457] = 1953, + [BNXT_ULP_CLASS_HID_29f57] = 1954, + [BNXT_ULP_CLASS_HID_32a57] = 1955, + [BNXT_ULP_CLASS_HID_3b557] = 1956, + [BNXT_ULP_CLASS_HID_22767] = 1957, + [BNXT_ULP_CLASS_HID_2b267] = 1958, + [BNXT_ULP_CLASS_HID_33d67] = 1959, + [BNXT_ULP_CLASS_HID_3c867] = 1960, + [BNXT_ULP_CLASS_HID_24fc7] = 1961, + [BNXT_ULP_CLASS_HID_2dac7] = 1962, + [BNXT_ULP_CLASS_HID_3089b] = 1963, + [BNXT_ULP_CLASS_HID_3939b] = 1964, + [BNXT_ULP_CLASS_HID_23c37] = 1965, + [BNXT_ULP_CLASS_HID_2c737] = 1966, + [BNXT_ULP_CLASS_HID_35237] = 1967, + [BNXT_ULP_CLASS_HID_380cb] = 1968, + [BNXT_ULP_CLASS_HID_237cb] = 1969, + [BNXT_ULP_CLASS_HID_2c2cb] = 1970, + [BNXT_ULP_CLASS_HID_34dcb] = 1971, + [BNXT_ULP_CLASS_HID_3d8cb] = 1972, + [BNXT_ULP_CLASS_HID_24a9b] = 1973, + [BNXT_ULP_CLASS_HID_2d59b] = 1974, + [BNXT_ULP_CLASS_HID_303af] = 1975, + [BNXT_ULP_CLASS_HID_38eaf] = 1976, + [BNXT_ULP_CLASS_HID_253b] = 1977, + [BNXT_ULP_CLASS_HID_2bf7] = 1978, + [BNXT_ULP_CLASS_HID_1827] = 1979, + [BNXT_ULP_CLASS_HID_4f6b] = 1980, + [BNXT_ULP_CLASS_HID_3c5b] = 1981, + [BNXT_ULP_CLASS_HID_1653] = 1982, + [BNXT_ULP_CLASS_HID_0283] = 1983, + [BNXT_ULP_CLASS_HID_39c7] = 1984, + [BNXT_ULP_CLASS_HID_2637] = 1985, + [BNXT_ULP_CLASS_HID_126b] = 1986, + [BNXT_ULP_CLASS_HID_48af] = 1987, + [BNXT_ULP_CLASS_HID_359f] = 1988, + [BNXT_ULP_CLASS_HID_0f97] = 1989, + [BNXT_ULP_CLASS_HID_5933] = 1990, + [BNXT_ULP_CLASS_HID_330b] = 1991, + [BNXT_ULP_CLASS_HID_207b] = 1992, + [BNXT_ULP_CLASS_HID_374e] = 1993, + [BNXT_ULP_CLASS_HID_11ee] = 1994, + [BNXT_ULP_CLASS_HID_423a] = 1995, + [BNXT_ULP_CLASS_HID_0cd6] = 1996, + [BNXT_ULP_CLASS_HID_310a] = 1997, + [BNXT_ULP_CLASS_HID_469e] = 1998, + [BNXT_ULP_CLASS_HID_5ce6] = 1999, + [BNXT_ULP_CLASS_HID_0692] = 2000, + [BNXT_ULP_CLASS_HID_1c7e] = 2001, + [BNXT_ULP_CLASS_HID_55c2] = 2002, + [BNXT_ULP_CLASS_HID_2b2a] = 2003, + [BNXT_ULP_CLASS_HID_15c6] = 2004, + [BNXT_ULP_CLASS_HID_163a] = 2005, + [BNXT_ULP_CLASS_HID_2f8e] = 2006, + [BNXT_ULP_CLASS_HID_2516] = 2007, + [BNXT_ULP_CLASS_HID_4b76] = 2008, + [BNXT_ULP_CLASS_HID_10e6] = 2009, + [BNXT_ULP_CLASS_HID_264a] = 2010, + [BNXT_ULP_CLASS_HID_3fd2] = 2011, + [BNXT_ULP_CLASS_HID_4532] = 2012, + [BNXT_ULP_CLASS_HID_4996] = 2013, + [BNXT_ULP_CLASS_HID_2036] = 2014, + [BNXT_ULP_CLASS_HID_399e] = 2015, + [BNXT_ULP_CLASS_HID_5ffe] = 2016, + [BNXT_ULP_CLASS_HID_34fe] = 2017, + [BNXT_ULP_CLASS_HID_3a32] = 2018, + [BNXT_ULP_CLASS_HID_14d2] = 2019, + [BNXT_ULP_CLASS_HID_4a42] = 2020, + [BNXT_ULP_CLASS_HID_376e] = 2021, + [BNXT_ULP_CLASS_HID_12d6e] = 2022, + [BNXT_ULP_CLASS_HID_2436e] = 2023, + [BNXT_ULP_CLASS_HID_31dba] = 2024, + [BNXT_ULP_CLASS_HID_11ce] = 2025, + [BNXT_ULP_CLASS_HID_107ce] = 2026, + [BNXT_ULP_CLASS_HID_23dce] = 2027, + [BNXT_ULP_CLASS_HID_353ce] = 2028, + [BNXT_ULP_CLASS_HID_421a] = 2029, + [BNXT_ULP_CLASS_HID_11d56] = 2030, + [BNXT_ULP_CLASS_HID_23356] = 2031, + [BNXT_ULP_CLASS_HID_32956] = 2032, + [BNXT_ULP_CLASS_HID_0cf6] = 2033, + [BNXT_ULP_CLASS_HID_122f6] = 2034, + [BNXT_ULP_CLASS_HID_258f6] = 2035, + [BNXT_ULP_CLASS_HID_313c2] = 2036, + [BNXT_ULP_CLASS_HID_312a] = 2037, + [BNXT_ULP_CLASS_HID_1272a] = 2038, + [BNXT_ULP_CLASS_HID_25d2a] = 2039, + [BNXT_ULP_CLASS_HID_31466] = 2040, + [BNXT_ULP_CLASS_HID_46be] = 2041, + [BNXT_ULP_CLASS_HID_1018a] = 2042, + [BNXT_ULP_CLASS_HID_2378a] = 2043, + [BNXT_ULP_CLASS_HID_32d8a] = 2044, + [BNXT_ULP_CLASS_HID_5cc6] = 2045, + [BNXT_ULP_CLASS_HID_11712] = 2046, + [BNXT_ULP_CLASS_HID_20d12] = 2047, + [BNXT_ULP_CLASS_HID_32312] = 2048, + [BNXT_ULP_CLASS_HID_06b2] = 2049, + [BNXT_ULP_CLASS_HID_13cb2] = 2050, + [BNXT_ULP_CLASS_HID_252b2] = 2051, + [BNXT_ULP_CLASS_HID_348b2] = 2052, + [BNXT_ULP_CLASS_HID_1c5e] = 2053, + [BNXT_ULP_CLASS_HID_1325e] = 2054, + [BNXT_ULP_CLASS_HID_2285e] = 2055, + [BNXT_ULP_CLASS_HID_35e5e] = 2056, + [BNXT_ULP_CLASS_HID_55e2] = 2057, + [BNXT_ULP_CLASS_HID_14be2] = 2058, + [BNXT_ULP_CLASS_HID_2023e] = 2059, + [BNXT_ULP_CLASS_HID_3383e] = 2060, + [BNXT_ULP_CLASS_HID_2b0a] = 2061, + [BNXT_ULP_CLASS_HID_1410a] = 2062, + [BNXT_ULP_CLASS_HID_21846] = 2063, + [BNXT_ULP_CLASS_HID_30e46] = 2064, + [BNXT_ULP_CLASS_HID_15e6] = 2065, + [BNXT_ULP_CLASS_HID_10be6] = 2066, + [BNXT_ULP_CLASS_HID_221e6] = 2067, + [BNXT_ULP_CLASS_HID_357e6] = 2068, + [BNXT_ULP_CLASS_HID_161a] = 2069, + [BNXT_ULP_CLASS_HID_10c1a] = 2070, + [BNXT_ULP_CLASS_HID_2221a] = 2071, + [BNXT_ULP_CLASS_HID_3581a] = 2072, + [BNXT_ULP_CLASS_HID_2fae] = 2073, + [BNXT_ULP_CLASS_HID_145ae] = 2074, + [BNXT_ULP_CLASS_HID_21cfa] = 2075, + [BNXT_ULP_CLASS_HID_332fa] = 2076, + [BNXT_ULP_CLASS_HID_2536] = 2077, + [BNXT_ULP_CLASS_HID_15b36] = 2078, + [BNXT_ULP_CLASS_HID_21202] = 2079, + [BNXT_ULP_CLASS_HID_30802] = 2080, + [BNXT_ULP_CLASS_HID_4b56] = 2081, + [BNXT_ULP_CLASS_HID_105a2] = 2082, + [BNXT_ULP_CLASS_HID_23ba2] = 2083, + [BNXT_ULP_CLASS_HID_351a2] = 2084, + [BNXT_ULP_CLASS_HID_10c6] = 2085, + [BNXT_ULP_CLASS_HID_106c6] = 2086, + [BNXT_ULP_CLASS_HID_23cc6] = 2087, + [BNXT_ULP_CLASS_HID_352c6] = 2088, + [BNXT_ULP_CLASS_HID_266a] = 2089, + [BNXT_ULP_CLASS_HID_15c6a] = 2090, + [BNXT_ULP_CLASS_HID_216a6] = 2091, + [BNXT_ULP_CLASS_HID_30ca6] = 2092, + [BNXT_ULP_CLASS_HID_3ff2] = 2093, + [BNXT_ULP_CLASS_HID_155f2] = 2094, + [BNXT_ULP_CLASS_HID_24bf2] = 2095, + [BNXT_ULP_CLASS_HID_302ce] = 2096, + [BNXT_ULP_CLASS_HID_4512] = 2097, + [BNXT_ULP_CLASS_HID_11c6e] = 2098, + [BNXT_ULP_CLASS_HID_2326e] = 2099, + [BNXT_ULP_CLASS_HID_3286e] = 2100, + [BNXT_ULP_CLASS_HID_49b6] = 2101, + [BNXT_ULP_CLASS_HID_10082] = 2102, + [BNXT_ULP_CLASS_HID_23682] = 2103, + [BNXT_ULP_CLASS_HID_32c82] = 2104, + [BNXT_ULP_CLASS_HID_2016] = 2105, + [BNXT_ULP_CLASS_HID_15616] = 2106, + [BNXT_ULP_CLASS_HID_21162] = 2107, + [BNXT_ULP_CLASS_HID_30762] = 2108, + [BNXT_ULP_CLASS_HID_39be] = 2109, + [BNXT_ULP_CLASS_HID_12fbe] = 2110, + [BNXT_ULP_CLASS_HID_245be] = 2111, + [BNXT_ULP_CLASS_HID_31c8a] = 2112, + [BNXT_ULP_CLASS_HID_5fde] = 2113, + [BNXT_ULP_CLASS_HID_1162a] = 2114, + [BNXT_ULP_CLASS_HID_20c2a] = 2115, + [BNXT_ULP_CLASS_HID_3222a] = 2116, + [BNXT_ULP_CLASS_HID_34de] = 2117, + [BNXT_ULP_CLASS_HID_3a12] = 2118, + [BNXT_ULP_CLASS_HID_14f2] = 2119, + [BNXT_ULP_CLASS_HID_4a62] = 2120, + [BNXT_ULP_CLASS_HID_370e] = 2121, + [BNXT_ULP_CLASS_HID_12d0e] = 2122, + [BNXT_ULP_CLASS_HID_2430e] = 2123, + [BNXT_ULP_CLASS_HID_31dda] = 2124, + [BNXT_ULP_CLASS_HID_11ae] = 2125, + [BNXT_ULP_CLASS_HID_107ae] = 2126, + [BNXT_ULP_CLASS_HID_23dae] = 2127, + [BNXT_ULP_CLASS_HID_353ae] = 2128, + [BNXT_ULP_CLASS_HID_427a] = 2129, + [BNXT_ULP_CLASS_HID_11d36] = 2130, + [BNXT_ULP_CLASS_HID_23336] = 2131, + [BNXT_ULP_CLASS_HID_32936] = 2132, + [BNXT_ULP_CLASS_HID_0c96] = 2133, + [BNXT_ULP_CLASS_HID_12296] = 2134, + [BNXT_ULP_CLASS_HID_25896] = 2135, + [BNXT_ULP_CLASS_HID_313a2] = 2136, + [BNXT_ULP_CLASS_HID_314a] = 2137, + [BNXT_ULP_CLASS_HID_1274a] = 2138, + [BNXT_ULP_CLASS_HID_25d4a] = 2139, + [BNXT_ULP_CLASS_HID_31406] = 2140, + [BNXT_ULP_CLASS_HID_46de] = 2141, + [BNXT_ULP_CLASS_HID_101ea] = 2142, + [BNXT_ULP_CLASS_HID_237ea] = 2143, + [BNXT_ULP_CLASS_HID_32dea] = 2144, + [BNXT_ULP_CLASS_HID_5ca6] = 2145, + [BNXT_ULP_CLASS_HID_11772] = 2146, + [BNXT_ULP_CLASS_HID_20d72] = 2147, + [BNXT_ULP_CLASS_HID_32372] = 2148, + [BNXT_ULP_CLASS_HID_06d2] = 2149, + [BNXT_ULP_CLASS_HID_13cd2] = 2150, + [BNXT_ULP_CLASS_HID_252d2] = 2151, + [BNXT_ULP_CLASS_HID_348d2] = 2152, + [BNXT_ULP_CLASS_HID_1c3e] = 2153, + [BNXT_ULP_CLASS_HID_1323e] = 2154, + [BNXT_ULP_CLASS_HID_2283e] = 2155, + [BNXT_ULP_CLASS_HID_35e3e] = 2156, + [BNXT_ULP_CLASS_HID_5582] = 2157, + [BNXT_ULP_CLASS_HID_14b82] = 2158, + [BNXT_ULP_CLASS_HID_2025e] = 2159, + [BNXT_ULP_CLASS_HID_3385e] = 2160, + [BNXT_ULP_CLASS_HID_2b6a] = 2161, + [BNXT_ULP_CLASS_HID_1416a] = 2162, + [BNXT_ULP_CLASS_HID_21826] = 2163, + [BNXT_ULP_CLASS_HID_30e26] = 2164, + [BNXT_ULP_CLASS_HID_1586] = 2165, + [BNXT_ULP_CLASS_HID_10b86] = 2166, + [BNXT_ULP_CLASS_HID_22186] = 2167, + [BNXT_ULP_CLASS_HID_35786] = 2168, + [BNXT_ULP_CLASS_HID_167a] = 2169, + [BNXT_ULP_CLASS_HID_10c7a] = 2170, + [BNXT_ULP_CLASS_HID_2227a] = 2171, + [BNXT_ULP_CLASS_HID_3587a] = 2172, + [BNXT_ULP_CLASS_HID_2fce] = 2173, + [BNXT_ULP_CLASS_HID_145ce] = 2174, + [BNXT_ULP_CLASS_HID_21c9a] = 2175, + [BNXT_ULP_CLASS_HID_3329a] = 2176, + [BNXT_ULP_CLASS_HID_2556] = 2177, + [BNXT_ULP_CLASS_HID_15b56] = 2178, + [BNXT_ULP_CLASS_HID_21262] = 2179, + [BNXT_ULP_CLASS_HID_30862] = 2180, + [BNXT_ULP_CLASS_HID_4b36] = 2181, + [BNXT_ULP_CLASS_HID_105c2] = 2182, + [BNXT_ULP_CLASS_HID_23bc2] = 2183, + [BNXT_ULP_CLASS_HID_351c2] = 2184, + [BNXT_ULP_CLASS_HID_10a6] = 2185, + [BNXT_ULP_CLASS_HID_106a6] = 2186, + [BNXT_ULP_CLASS_HID_23ca6] = 2187, + [BNXT_ULP_CLASS_HID_352a6] = 2188, + [BNXT_ULP_CLASS_HID_260a] = 2189, + [BNXT_ULP_CLASS_HID_15c0a] = 2190, + [BNXT_ULP_CLASS_HID_216c6] = 2191, + [BNXT_ULP_CLASS_HID_30cc6] = 2192, + [BNXT_ULP_CLASS_HID_3f92] = 2193, + [BNXT_ULP_CLASS_HID_15592] = 2194, + [BNXT_ULP_CLASS_HID_24b92] = 2195, + [BNXT_ULP_CLASS_HID_302ae] = 2196, + [BNXT_ULP_CLASS_HID_4572] = 2197, + [BNXT_ULP_CLASS_HID_11c0e] = 2198, + [BNXT_ULP_CLASS_HID_2320e] = 2199, + [BNXT_ULP_CLASS_HID_3280e] = 2200, + [BNXT_ULP_CLASS_HID_49d6] = 2201, + [BNXT_ULP_CLASS_HID_100e2] = 2202, + [BNXT_ULP_CLASS_HID_236e2] = 2203, + [BNXT_ULP_CLASS_HID_32ce2] = 2204, + [BNXT_ULP_CLASS_HID_2076] = 2205, + [BNXT_ULP_CLASS_HID_15676] = 2206, + [BNXT_ULP_CLASS_HID_21102] = 2207, + [BNXT_ULP_CLASS_HID_30702] = 2208, + [BNXT_ULP_CLASS_HID_39de] = 2209, + [BNXT_ULP_CLASS_HID_12fde] = 2210, + [BNXT_ULP_CLASS_HID_245de] = 2211, + [BNXT_ULP_CLASS_HID_31cea] = 2212, + [BNXT_ULP_CLASS_HID_5fbe] = 2213, + [BNXT_ULP_CLASS_HID_1164a] = 2214, + [BNXT_ULP_CLASS_HID_20c4a] = 2215, + [BNXT_ULP_CLASS_HID_3224a] = 2216, + [BNXT_ULP_CLASS_HID_34be] = 2217, + [BNXT_ULP_CLASS_HID_3a72] = 2218, + [BNXT_ULP_CLASS_HID_1492] = 2219, + [BNXT_ULP_CLASS_HID_4a02] = 2220, + [BNXT_ULP_CLASS_HID_09ea] = 2221, + [BNXT_ULP_CLASS_HID_2912] = 2222, + [BNXT_ULP_CLASS_HID_03b2] = 2223, + [BNXT_ULP_CLASS_HID_5f7e] = 2224, + [BNXT_ULP_CLASS_HID_03a6] = 2225, + [BNXT_ULP_CLASS_HID_23ce] = 2226, + [BNXT_ULP_CLASS_HID_1a6e] = 2227, + [BNXT_ULP_CLASS_HID_593a] = 2228, + [BNXT_ULP_CLASS_HID_4dce] = 2229, + [BNXT_ULP_CLASS_HID_0e02] = 2230, + [BNXT_ULP_CLASS_HID_4796] = 2231, + [BNXT_ULP_CLASS_HID_246e] = 2232, + [BNXT_ULP_CLASS_HID_478a] = 2233, + [BNXT_ULP_CLASS_HID_08fe] = 2234, + [BNXT_ULP_CLASS_HID_5e52] = 2235, + [BNXT_ULP_CLASS_HID_3e2a] = 2236, + [BNXT_ULP_CLASS_HID_5e46] = 2237, + [BNXT_ULP_CLASS_HID_02ba] = 2238, + [BNXT_ULP_CLASS_HID_580e] = 2239, + [BNXT_ULP_CLASS_HID_38e6] = 2240, + [BNXT_ULP_CLASS_HID_5802] = 2241, + [BNXT_ULP_CLASS_HID_1d76] = 2242, + [BNXT_ULP_CLASS_HID_52ca] = 2243, + [BNXT_ULP_CLASS_HID_32a2] = 2244, + [BNXT_ULP_CLASS_HID_34f6] = 2245, + [BNXT_ULP_CLASS_HID_3a3a] = 2246, + [BNXT_ULP_CLASS_HID_5a22] = 2247, + [BNXT_ULP_CLASS_HID_541e] = 2248, + [BNXT_ULP_CLASS_HID_09ca] = 2249, + [BNXT_ULP_CLASS_HID_0216] = 2250, + [BNXT_ULP_CLASS_HID_1f62] = 2251, + [BNXT_ULP_CLASS_HID_1bae] = 2252, + [BNXT_ULP_CLASS_HID_2932] = 2253, + [BNXT_ULP_CLASS_HID_227e] = 2254, + [BNXT_ULP_CLASS_HID_3f4a] = 2255, + [BNXT_ULP_CLASS_HID_3b96] = 2256, + [BNXT_ULP_CLASS_HID_0392] = 2257, + [BNXT_ULP_CLASS_HID_1cde] = 2258, + [BNXT_ULP_CLASS_HID_192a] = 2259, + [BNXT_ULP_CLASS_HID_1276] = 2260, + [BNXT_ULP_CLASS_HID_5f5e] = 2261, + [BNXT_ULP_CLASS_HID_5baa] = 2262, + [BNXT_ULP_CLASS_HID_54f6] = 2263, + [BNXT_ULP_CLASS_HID_51c2] = 2264, + [BNXT_ULP_CLASS_HID_0386] = 2265, + [BNXT_ULP_CLASS_HID_1cd2] = 2266, + [BNXT_ULP_CLASS_HID_191e] = 2267, + [BNXT_ULP_CLASS_HID_126a] = 2268, + [BNXT_ULP_CLASS_HID_23ee] = 2269, + [BNXT_ULP_CLASS_HID_3c3a] = 2270, + [BNXT_ULP_CLASS_HID_3906] = 2271, + [BNXT_ULP_CLASS_HID_3252] = 2272, + [BNXT_ULP_CLASS_HID_1a4e] = 2273, + [BNXT_ULP_CLASS_HID_169a] = 2274, + [BNXT_ULP_CLASS_HID_13e6] = 2275, + [BNXT_ULP_CLASS_HID_4be6] = 2276, + [BNXT_ULP_CLASS_HID_591a] = 2277, + [BNXT_ULP_CLASS_HID_5266] = 2278, + [BNXT_ULP_CLASS_HID_2eb2] = 2279, + [BNXT_ULP_CLASS_HID_2bfe] = 2280, + [BNXT_ULP_CLASS_HID_4dee] = 2281, + [BNXT_ULP_CLASS_HID_463a] = 2282, + [BNXT_ULP_CLASS_HID_4306] = 2283, + [BNXT_ULP_CLASS_HID_5c52] = 2284, + [BNXT_ULP_CLASS_HID_0e22] = 2285, + [BNXT_ULP_CLASS_HID_0b6e] = 2286, + [BNXT_ULP_CLASS_HID_07ba] = 2287, + [BNXT_ULP_CLASS_HID_0086] = 2288, + [BNXT_ULP_CLASS_HID_47b6] = 2289, + [BNXT_ULP_CLASS_HID_4082] = 2290, + [BNXT_ULP_CLASS_HID_5dce] = 2291, + [BNXT_ULP_CLASS_HID_561a] = 2292, + [BNXT_ULP_CLASS_HID_244e] = 2293, + [BNXT_ULP_CLASS_HID_209a] = 2294, + [BNXT_ULP_CLASS_HID_3de6] = 2295, + [BNXT_ULP_CLASS_HID_3632] = 2296, + [BNXT_ULP_CLASS_HID_47aa] = 2297, + [BNXT_ULP_CLASS_HID_40f6] = 2298, + [BNXT_ULP_CLASS_HID_5dc2] = 2299, + [BNXT_ULP_CLASS_HID_560e] = 2300, + [BNXT_ULP_CLASS_HID_08de] = 2301, + [BNXT_ULP_CLASS_HID_052a] = 2302, + [BNXT_ULP_CLASS_HID_1e76] = 2303, + [BNXT_ULP_CLASS_HID_1b42] = 2304, + [BNXT_ULP_CLASS_HID_5e72] = 2305, + [BNXT_ULP_CLASS_HID_5abe] = 2306, + [BNXT_ULP_CLASS_HID_578a] = 2307, + [BNXT_ULP_CLASS_HID_50d6] = 2308, + [BNXT_ULP_CLASS_HID_3e0a] = 2309, + [BNXT_ULP_CLASS_HID_3b56] = 2310, + [BNXT_ULP_CLASS_HID_37a2] = 2311, + [BNXT_ULP_CLASS_HID_30ee] = 2312, + [BNXT_ULP_CLASS_HID_5e66] = 2313, + [BNXT_ULP_CLASS_HID_5ab2] = 2314, + [BNXT_ULP_CLASS_HID_57fe] = 2315, + [BNXT_ULP_CLASS_HID_50ca] = 2316, + [BNXT_ULP_CLASS_HID_029a] = 2317, + [BNXT_ULP_CLASS_HID_1fe6] = 2318, + [BNXT_ULP_CLASS_HID_1832] = 2319, + [BNXT_ULP_CLASS_HID_157e] = 2320, + [BNXT_ULP_CLASS_HID_582e] = 2321, + [BNXT_ULP_CLASS_HID_557a] = 2322, + [BNXT_ULP_CLASS_HID_2e46] = 2323, + [BNXT_ULP_CLASS_HID_2a92] = 2324, + [BNXT_ULP_CLASS_HID_38c6] = 2325, + [BNXT_ULP_CLASS_HID_3512] = 2326, + [BNXT_ULP_CLASS_HID_0e5e] = 2327, + [BNXT_ULP_CLASS_HID_0aaa] = 2328, + [BNXT_ULP_CLASS_HID_5822] = 2329, + [BNXT_ULP_CLASS_HID_556e] = 2330, + [BNXT_ULP_CLASS_HID_51ba] = 2331, + [BNXT_ULP_CLASS_HID_2a86] = 2332, + [BNXT_ULP_CLASS_HID_1d56] = 2333, + [BNXT_ULP_CLASS_HID_19a2] = 2334, + [BNXT_ULP_CLASS_HID_12ee] = 2335, + [BNXT_ULP_CLASS_HID_4aee] = 2336, + [BNXT_ULP_CLASS_HID_52ea] = 2337, + [BNXT_ULP_CLASS_HID_2f36] = 2338, + [BNXT_ULP_CLASS_HID_2802] = 2339, + [BNXT_ULP_CLASS_HID_254e] = 2340, + [BNXT_ULP_CLASS_HID_3282] = 2341, + [BNXT_ULP_CLASS_HID_0fce] = 2342, + [BNXT_ULP_CLASS_HID_081a] = 2343, + [BNXT_ULP_CLASS_HID_0566] = 2344, + [BNXT_ULP_CLASS_HID_34d6] = 2345, + [BNXT_ULP_CLASS_HID_3a1a] = 2346, + [BNXT_ULP_CLASS_HID_5a02] = 2347, + [BNXT_ULP_CLASS_HID_543e] = 2348, + [BNXT_ULP_CLASS_HID_09aa] = 2349, + [BNXT_ULP_CLASS_HID_0276] = 2350, + [BNXT_ULP_CLASS_HID_1f02] = 2351, + [BNXT_ULP_CLASS_HID_1bce] = 2352, + [BNXT_ULP_CLASS_HID_2952] = 2353, + [BNXT_ULP_CLASS_HID_221e] = 2354, + [BNXT_ULP_CLASS_HID_3f2a] = 2355, + [BNXT_ULP_CLASS_HID_3bf6] = 2356, + [BNXT_ULP_CLASS_HID_03f2] = 2357, + [BNXT_ULP_CLASS_HID_1cbe] = 2358, + [BNXT_ULP_CLASS_HID_194a] = 2359, + [BNXT_ULP_CLASS_HID_1216] = 2360, + [BNXT_ULP_CLASS_HID_5f3e] = 2361, + [BNXT_ULP_CLASS_HID_5bca] = 2362, + [BNXT_ULP_CLASS_HID_5496] = 2363, + [BNXT_ULP_CLASS_HID_51a2] = 2364, + [BNXT_ULP_CLASS_HID_03e6] = 2365, + [BNXT_ULP_CLASS_HID_1cb2] = 2366, + [BNXT_ULP_CLASS_HID_197e] = 2367, + [BNXT_ULP_CLASS_HID_120a] = 2368, + [BNXT_ULP_CLASS_HID_238e] = 2369, + [BNXT_ULP_CLASS_HID_3c5a] = 2370, + [BNXT_ULP_CLASS_HID_3966] = 2371, + [BNXT_ULP_CLASS_HID_3232] = 2372, + [BNXT_ULP_CLASS_HID_1a2e] = 2373, + [BNXT_ULP_CLASS_HID_16fa] = 2374, + [BNXT_ULP_CLASS_HID_1386] = 2375, + [BNXT_ULP_CLASS_HID_4b86] = 2376, + [BNXT_ULP_CLASS_HID_597a] = 2377, + [BNXT_ULP_CLASS_HID_5206] = 2378, + [BNXT_ULP_CLASS_HID_2ed2] = 2379, + [BNXT_ULP_CLASS_HID_2b9e] = 2380, + [BNXT_ULP_CLASS_HID_4d8e] = 2381, + [BNXT_ULP_CLASS_HID_465a] = 2382, + [BNXT_ULP_CLASS_HID_4366] = 2383, + [BNXT_ULP_CLASS_HID_5c32] = 2384, + [BNXT_ULP_CLASS_HID_0e42] = 2385, + [BNXT_ULP_CLASS_HID_0b0e] = 2386, + [BNXT_ULP_CLASS_HID_07da] = 2387, + [BNXT_ULP_CLASS_HID_00e6] = 2388, + [BNXT_ULP_CLASS_HID_47d6] = 2389, + [BNXT_ULP_CLASS_HID_40e2] = 2390, + [BNXT_ULP_CLASS_HID_5dae] = 2391, + [BNXT_ULP_CLASS_HID_567a] = 2392, + [BNXT_ULP_CLASS_HID_242e] = 2393, + [BNXT_ULP_CLASS_HID_20fa] = 2394, + [BNXT_ULP_CLASS_HID_3d86] = 2395, + [BNXT_ULP_CLASS_HID_3652] = 2396, + [BNXT_ULP_CLASS_HID_47ca] = 2397, + [BNXT_ULP_CLASS_HID_4096] = 2398, + [BNXT_ULP_CLASS_HID_5da2] = 2399, + [BNXT_ULP_CLASS_HID_566e] = 2400, + [BNXT_ULP_CLASS_HID_08be] = 2401, + [BNXT_ULP_CLASS_HID_054a] = 2402, + [BNXT_ULP_CLASS_HID_1e16] = 2403, + [BNXT_ULP_CLASS_HID_1b22] = 2404, + [BNXT_ULP_CLASS_HID_5e12] = 2405, + [BNXT_ULP_CLASS_HID_5ade] = 2406, + [BNXT_ULP_CLASS_HID_57ea] = 2407, + [BNXT_ULP_CLASS_HID_50b6] = 2408, + [BNXT_ULP_CLASS_HID_3e6a] = 2409, + [BNXT_ULP_CLASS_HID_3b36] = 2410, + [BNXT_ULP_CLASS_HID_37c2] = 2411, + [BNXT_ULP_CLASS_HID_308e] = 2412, + [BNXT_ULP_CLASS_HID_5e06] = 2413, + [BNXT_ULP_CLASS_HID_5ad2] = 2414, + [BNXT_ULP_CLASS_HID_579e] = 2415, + [BNXT_ULP_CLASS_HID_50aa] = 2416, + [BNXT_ULP_CLASS_HID_02fa] = 2417, + [BNXT_ULP_CLASS_HID_1f86] = 2418, + [BNXT_ULP_CLASS_HID_1852] = 2419, + [BNXT_ULP_CLASS_HID_151e] = 2420, + [BNXT_ULP_CLASS_HID_584e] = 2421, + [BNXT_ULP_CLASS_HID_551a] = 2422, + [BNXT_ULP_CLASS_HID_2e26] = 2423, + [BNXT_ULP_CLASS_HID_2af2] = 2424, + [BNXT_ULP_CLASS_HID_38a6] = 2425, + [BNXT_ULP_CLASS_HID_3572] = 2426, + [BNXT_ULP_CLASS_HID_0e3e] = 2427, + [BNXT_ULP_CLASS_HID_0aca] = 2428, + [BNXT_ULP_CLASS_HID_5842] = 2429, + [BNXT_ULP_CLASS_HID_550e] = 2430, + [BNXT_ULP_CLASS_HID_51da] = 2431, + [BNXT_ULP_CLASS_HID_2ae6] = 2432, + [BNXT_ULP_CLASS_HID_1d36] = 2433, + [BNXT_ULP_CLASS_HID_19c2] = 2434, + [BNXT_ULP_CLASS_HID_128e] = 2435, + [BNXT_ULP_CLASS_HID_4a8e] = 2436, + [BNXT_ULP_CLASS_HID_528a] = 2437, + [BNXT_ULP_CLASS_HID_2f56] = 2438, + [BNXT_ULP_CLASS_HID_2862] = 2439, + [BNXT_ULP_CLASS_HID_252e] = 2440, + [BNXT_ULP_CLASS_HID_32e2] = 2441, + [BNXT_ULP_CLASS_HID_0fae] = 2442, + [BNXT_ULP_CLASS_HID_087a] = 2443, + [BNXT_ULP_CLASS_HID_0506] = 2444, + [BNXT_ULP_CLASS_HID_34b6] = 2445, + [BNXT_ULP_CLASS_HID_3a7a] = 2446, + [BNXT_ULP_CLASS_HID_5a62] = 2447, + [BNXT_ULP_CLASS_HID_545e] = 2448, + [BNXT_ULP_CLASS_HID_a73c] = 2449, + [BNXT_ULP_CLASS_HID_a040] = 2450, + [BNXT_ULP_CLASS_HID_1d640] = 2451, + [BNXT_ULP_CLASS_HID_1dd3c] = 2452, + [BNXT_ULP_CLASS_HID_cba0] = 2453, + [BNXT_ULP_CLASS_HID_c4f4] = 2454, + [BNXT_ULP_CLASS_HID_19f38] = 2455, + [BNXT_ULP_CLASS_HID_182f4] = 2456, + [BNXT_ULP_CLASS_HID_b098] = 2457, + [BNXT_ULP_CLASS_HID_8dac] = 2458, + [BNXT_ULP_CLASS_HID_1a3ac] = 2459, + [BNXT_ULP_CLASS_HID_1a698] = 2460, + [BNXT_ULP_CLASS_HID_d50c] = 2461, + [BNXT_ULP_CLASS_HID_ae50] = 2462, + [BNXT_ULP_CLASS_HID_1c450] = 2463, + [BNXT_ULP_CLASS_HID_1cb0c] = 2464, + [BNXT_ULP_CLASS_HID_a1f0] = 2465, + [BNXT_ULP_CLASS_HID_ba04] = 2466, + [BNXT_ULP_CLASS_HID_1d004] = 2467, + [BNXT_ULP_CLASS_HID_1d7f0] = 2468, + [BNXT_ULP_CLASS_HID_c264] = 2469, + [BNXT_ULP_CLASS_HID_dea8] = 2470, + [BNXT_ULP_CLASS_HID_199fc] = 2471, + [BNXT_ULP_CLASS_HID_19ca8] = 2472, + [BNXT_ULP_CLASS_HID_8b5c] = 2473, + [BNXT_ULP_CLASS_HID_8460] = 2474, + [BNXT_ULP_CLASS_HID_1ba60] = 2475, + [BNXT_ULP_CLASS_HID_1a15c] = 2476, + [BNXT_ULP_CLASS_HID_afc0] = 2477, + [BNXT_ULP_CLASS_HID_a814] = 2478, + [BNXT_ULP_CLASS_HID_1de14] = 2479, + [BNXT_ULP_CLASS_HID_1c5c0] = 2480, + [BNXT_ULP_CLASS_HID_8c2c] = 2481, + [BNXT_ULP_CLASS_HID_8970] = 2482, + [BNXT_ULP_CLASS_HID_1bf70] = 2483, + [BNXT_ULP_CLASS_HID_1a22c] = 2484, + [BNXT_ULP_CLASS_HID_d0d0] = 2485, + [BNXT_ULP_CLASS_HID_ade4] = 2486, + [BNXT_ULP_CLASS_HID_1c3e4] = 2487, + [BNXT_ULP_CLASS_HID_1c6d0] = 2488, + [BNXT_ULP_CLASS_HID_9988] = 2489, + [BNXT_ULP_CLASS_HID_92dc] = 2490, + [BNXT_ULP_CLASS_HID_188dc] = 2491, + [BNXT_ULP_CLASS_HID_18f88] = 2492, + [BNXT_ULP_CLASS_HID_ba3c] = 2493, + [BNXT_ULP_CLASS_HID_b740] = 2494, + [BNXT_ULP_CLASS_HID_1ad40] = 2495, + [BNXT_ULP_CLASS_HID_1d03c] = 2496, + [BNXT_ULP_CLASS_HID_86e0] = 2497, + [BNXT_ULP_CLASS_HID_8334] = 2498, + [BNXT_ULP_CLASS_HID_1b934] = 2499, + [BNXT_ULP_CLASS_HID_1bce0] = 2500, + [BNXT_ULP_CLASS_HID_aa94] = 2501, + [BNXT_ULP_CLASS_HID_a7d8] = 2502, + [BNXT_ULP_CLASS_HID_1ddd8] = 2503, + [BNXT_ULP_CLASS_HID_1c094] = 2504, + [BNXT_ULP_CLASS_HID_904c] = 2505, + [BNXT_ULP_CLASS_HID_c84c] = 2506, + [BNXT_ULP_CLASS_HID_18290] = 2507, + [BNXT_ULP_CLASS_HID_1864c] = 2508, + [BNXT_ULP_CLASS_HID_b4f0] = 2509, + [BNXT_ULP_CLASS_HID_b104] = 2510, + [BNXT_ULP_CLASS_HID_1a704] = 2511, + [BNXT_ULP_CLASS_HID_1aaf0] = 2512, + [BNXT_ULP_CLASS_HID_80a4] = 2513, + [BNXT_ULP_CLASS_HID_9de8] = 2514, + [BNXT_ULP_CLASS_HID_1b3e8] = 2515, + [BNXT_ULP_CLASS_HID_1b6a4] = 2516, + [BNXT_ULP_CLASS_HID_a548] = 2517, + [BNXT_ULP_CLASS_HID_a19c] = 2518, + [BNXT_ULP_CLASS_HID_1d79c] = 2519, + [BNXT_ULP_CLASS_HID_1db48] = 2520, + [BNXT_ULP_CLASS_HID_9a98] = 2521, + [BNXT_ULP_CLASS_HID_97ac] = 2522, + [BNXT_ULP_CLASS_HID_18dac] = 2523, + [BNXT_ULP_CLASS_HID_1b098] = 2524, + [BNXT_ULP_CLASS_HID_bf0c] = 2525, + [BNXT_ULP_CLASS_HID_b850] = 2526, + [BNXT_ULP_CLASS_HID_1ae50] = 2527, + [BNXT_ULP_CLASS_HID_1d50c] = 2528, + [BNXT_ULP_CLASS_HID_34f0] = 2529, + [BNXT_ULP_CLASS_HID_3a3c] = 2530, + [BNXT_ULP_CLASS_HID_3740] = 2531, + [BNXT_ULP_CLASS_HID_5ea0] = 2532, + [BNXT_ULP_CLASS_HID_5bf4] = 2533, + [BNXT_ULP_CLASS_HID_0798] = 2534, + [BNXT_ULP_CLASS_HID_00ac] = 2535, + [BNXT_ULP_CLASS_HID_280c] = 2536, + [BNXT_ULP_CLASS_HID_2550] = 2537, + [BNXT_ULP_CLASS_HID_3104] = 2538, + [BNXT_ULP_CLASS_HID_5964] = 2539, + [BNXT_ULP_CLASS_HID_55a8] = 2540, + [BNXT_ULP_CLASS_HID_1e5c] = 2541, + [BNXT_ULP_CLASS_HID_1b60] = 2542, + [BNXT_ULP_CLASS_HID_22c0] = 2543, + [BNXT_ULP_CLASS_HID_3f14] = 2544, + [BNXT_ULP_CLASS_HID_a71c] = 2545, + [BNXT_ULP_CLASS_HID_a8dc] = 2546, + [BNXT_ULP_CLASS_HID_ed9c] = 2547, + [BNXT_ULP_CLASS_HID_ef5c] = 2548, + [BNXT_ULP_CLASS_HID_a060] = 2549, + [BNXT_ULP_CLASS_HID_a520] = 2550, + [BNXT_ULP_CLASS_HID_e6e0] = 2551, + [BNXT_ULP_CLASS_HID_eba0] = 2552, + [BNXT_ULP_CLASS_HID_1d660] = 2553, + [BNXT_ULP_CLASS_HID_1fb20] = 2554, + [BNXT_ULP_CLASS_HID_1dce0] = 2555, + [BNXT_ULP_CLASS_HID_1e1a0] = 2556, + [BNXT_ULP_CLASS_HID_1dd1c] = 2557, + [BNXT_ULP_CLASS_HID_1fedc] = 2558, + [BNXT_ULP_CLASS_HID_1c39c] = 2559, + [BNXT_ULP_CLASS_HID_1e55c] = 2560, + [BNXT_ULP_CLASS_HID_cb80] = 2561, + [BNXT_ULP_CLASS_HID_b194] = 2562, + [BNXT_ULP_CLASS_HID_d354] = 2563, + [BNXT_ULP_CLASS_HID_f414] = 2564, + [BNXT_ULP_CLASS_HID_c4d4] = 2565, + [BNXT_ULP_CLASS_HID_e994] = 2566, + [BNXT_ULP_CLASS_HID_cb54] = 2567, + [BNXT_ULP_CLASS_HID_f158] = 2568, + [BNXT_ULP_CLASS_HID_19f18] = 2569, + [BNXT_ULP_CLASS_HID_1a0d8] = 2570, + [BNXT_ULP_CLASS_HID_1c598] = 2571, + [BNXT_ULP_CLASS_HID_1e758] = 2572, + [BNXT_ULP_CLASS_HID_182d4] = 2573, + [BNXT_ULP_CLASS_HID_1a794] = 2574, + [BNXT_ULP_CLASS_HID_1c954] = 2575, + [BNXT_ULP_CLASS_HID_1ea14] = 2576, + [BNXT_ULP_CLASS_HID_b0b8] = 2577, + [BNXT_ULP_CLASS_HID_b278] = 2578, + [BNXT_ULP_CLASS_HID_f738] = 2579, + [BNXT_ULP_CLASS_HID_f8f8] = 2580, + [BNXT_ULP_CLASS_HID_8d8c] = 2581, + [BNXT_ULP_CLASS_HID_af4c] = 2582, + [BNXT_ULP_CLASS_HID_f00c] = 2583, + [BNXT_ULP_CLASS_HID_f5cc] = 2584, + [BNXT_ULP_CLASS_HID_1a38c] = 2585, + [BNXT_ULP_CLASS_HID_1a54c] = 2586, + [BNXT_ULP_CLASS_HID_1e60c] = 2587, + [BNXT_ULP_CLASS_HID_1ebcc] = 2588, + [BNXT_ULP_CLASS_HID_1a6b8] = 2589, + [BNXT_ULP_CLASS_HID_1a878] = 2590, + [BNXT_ULP_CLASS_HID_1ed38] = 2591, + [BNXT_ULP_CLASS_HID_1eef8] = 2592, + [BNXT_ULP_CLASS_HID_d52c] = 2593, + [BNXT_ULP_CLASS_HID_f6ec] = 2594, + [BNXT_ULP_CLASS_HID_dbac] = 2595, + [BNXT_ULP_CLASS_HID_fd6c] = 2596, + [BNXT_ULP_CLASS_HID_ae70] = 2597, + [BNXT_ULP_CLASS_HID_f330] = 2598, + [BNXT_ULP_CLASS_HID_d4f0] = 2599, + [BNXT_ULP_CLASS_HID_f9b0] = 2600, + [BNXT_ULP_CLASS_HID_1c470] = 2601, + [BNXT_ULP_CLASS_HID_1e930] = 2602, + [BNXT_ULP_CLASS_HID_1caf0] = 2603, + [BNXT_ULP_CLASS_HID_1f084] = 2604, + [BNXT_ULP_CLASS_HID_1cb2c] = 2605, + [BNXT_ULP_CLASS_HID_1b130] = 2606, + [BNXT_ULP_CLASS_HID_1d2f0] = 2607, + [BNXT_ULP_CLASS_HID_1f7b0] = 2608, + [BNXT_ULP_CLASS_HID_a1d0] = 2609, + [BNXT_ULP_CLASS_HID_a290] = 2610, + [BNXT_ULP_CLASS_HID_e450] = 2611, + [BNXT_ULP_CLASS_HID_e910] = 2612, + [BNXT_ULP_CLASS_HID_ba24] = 2613, + [BNXT_ULP_CLASS_HID_bfe4] = 2614, + [BNXT_ULP_CLASS_HID_e0a4] = 2615, + [BNXT_ULP_CLASS_HID_e264] = 2616, + [BNXT_ULP_CLASS_HID_1d024] = 2617, + [BNXT_ULP_CLASS_HID_1f5e4] = 2618, + [BNXT_ULP_CLASS_HID_1d6a4] = 2619, + [BNXT_ULP_CLASS_HID_1f864] = 2620, + [BNXT_ULP_CLASS_HID_1d7d0] = 2621, + [BNXT_ULP_CLASS_HID_1f890] = 2622, + [BNXT_ULP_CLASS_HID_1da50] = 2623, + [BNXT_ULP_CLASS_HID_1ff10] = 2624, + [BNXT_ULP_CLASS_HID_c244] = 2625, + [BNXT_ULP_CLASS_HID_e704] = 2626, + [BNXT_ULP_CLASS_HID_c8c4] = 2627, + [BNXT_ULP_CLASS_HID_ed84] = 2628, + [BNXT_ULP_CLASS_HID_de88] = 2629, + [BNXT_ULP_CLASS_HID_e048] = 2630, + [BNXT_ULP_CLASS_HID_c508] = 2631, + [BNXT_ULP_CLASS_HID_e6c8] = 2632, + [BNXT_ULP_CLASS_HID_199dc] = 2633, + [BNXT_ULP_CLASS_HID_1ba9c] = 2634, + [BNXT_ULP_CLASS_HID_1dc5c] = 2635, + [BNXT_ULP_CLASS_HID_1e11c] = 2636, + [BNXT_ULP_CLASS_HID_19c88] = 2637, + [BNXT_ULP_CLASS_HID_1be48] = 2638, + [BNXT_ULP_CLASS_HID_1c308] = 2639, + [BNXT_ULP_CLASS_HID_1e4c8] = 2640, + [BNXT_ULP_CLASS_HID_8b7c] = 2641, + [BNXT_ULP_CLASS_HID_ac3c] = 2642, + [BNXT_ULP_CLASS_HID_f1fc] = 2643, + [BNXT_ULP_CLASS_HID_f2bc] = 2644, + [BNXT_ULP_CLASS_HID_8440] = 2645, + [BNXT_ULP_CLASS_HID_a900] = 2646, + [BNXT_ULP_CLASS_HID_cac0] = 2647, + [BNXT_ULP_CLASS_HID_ef80] = 2648, + [BNXT_ULP_CLASS_HID_1ba40] = 2649, + [BNXT_ULP_CLASS_HID_1bf00] = 2650, + [BNXT_ULP_CLASS_HID_1e0c0] = 2651, + [BNXT_ULP_CLASS_HID_1e580] = 2652, + [BNXT_ULP_CLASS_HID_1a17c] = 2653, + [BNXT_ULP_CLASS_HID_1a23c] = 2654, + [BNXT_ULP_CLASS_HID_1e7fc] = 2655, + [BNXT_ULP_CLASS_HID_1e8bc] = 2656, + [BNXT_ULP_CLASS_HID_afe0] = 2657, + [BNXT_ULP_CLASS_HID_f0a0] = 2658, + [BNXT_ULP_CLASS_HID_d260] = 2659, + [BNXT_ULP_CLASS_HID_f720] = 2660, + [BNXT_ULP_CLASS_HID_a834] = 2661, + [BNXT_ULP_CLASS_HID_adf4] = 2662, + [BNXT_ULP_CLASS_HID_eeb4] = 2663, + [BNXT_ULP_CLASS_HID_f074] = 2664, + [BNXT_ULP_CLASS_HID_1de34] = 2665, + [BNXT_ULP_CLASS_HID_1e3f4] = 2666, + [BNXT_ULP_CLASS_HID_1c4b4] = 2667, + [BNXT_ULP_CLASS_HID_1e674] = 2668, + [BNXT_ULP_CLASS_HID_1c5e0] = 2669, + [BNXT_ULP_CLASS_HID_1e6a0] = 2670, + [BNXT_ULP_CLASS_HID_1c860] = 2671, + [BNXT_ULP_CLASS_HID_1ed20] = 2672, + [BNXT_ULP_CLASS_HID_8c0c] = 2673, + [BNXT_ULP_CLASS_HID_b1cc] = 2674, + [BNXT_ULP_CLASS_HID_f28c] = 2675, + [BNXT_ULP_CLASS_HID_f44c] = 2676, + [BNXT_ULP_CLASS_HID_8950] = 2677, + [BNXT_ULP_CLASS_HID_aa10] = 2678, + [BNXT_ULP_CLASS_HID_cfd0] = 2679, + [BNXT_ULP_CLASS_HID_f090] = 2680, + [BNXT_ULP_CLASS_HID_1bf50] = 2681, + [BNXT_ULP_CLASS_HID_1a010] = 2682, + [BNXT_ULP_CLASS_HID_1e5d0] = 2683, + [BNXT_ULP_CLASS_HID_1e690] = 2684, + [BNXT_ULP_CLASS_HID_1a20c] = 2685, + [BNXT_ULP_CLASS_HID_1a7cc] = 2686, + [BNXT_ULP_CLASS_HID_1e88c] = 2687, + [BNXT_ULP_CLASS_HID_1ea4c] = 2688, + [BNXT_ULP_CLASS_HID_d0f0] = 2689, + [BNXT_ULP_CLASS_HID_f5b0] = 2690, + [BNXT_ULP_CLASS_HID_d770] = 2691, + [BNXT_ULP_CLASS_HID_f830] = 2692, + [BNXT_ULP_CLASS_HID_adc4] = 2693, + [BNXT_ULP_CLASS_HID_ae84] = 2694, + [BNXT_ULP_CLASS_HID_d044] = 2695, + [BNXT_ULP_CLASS_HID_f504] = 2696, + [BNXT_ULP_CLASS_HID_1c3c4] = 2697, + [BNXT_ULP_CLASS_HID_1e484] = 2698, + [BNXT_ULP_CLASS_HID_1c644] = 2699, + [BNXT_ULP_CLASS_HID_1eb04] = 2700, + [BNXT_ULP_CLASS_HID_1c6f0] = 2701, + [BNXT_ULP_CLASS_HID_1ebb0] = 2702, + [BNXT_ULP_CLASS_HID_1cd70] = 2703, + [BNXT_ULP_CLASS_HID_1f304] = 2704, + [BNXT_ULP_CLASS_HID_99a8] = 2705, + [BNXT_ULP_CLASS_HID_bb68] = 2706, + [BNXT_ULP_CLASS_HID_dc28] = 2707, + [BNXT_ULP_CLASS_HID_e1e8] = 2708, + [BNXT_ULP_CLASS_HID_92fc] = 2709, + [BNXT_ULP_CLASS_HID_b7bc] = 2710, + [BNXT_ULP_CLASS_HID_d97c] = 2711, + [BNXT_ULP_CLASS_HID_fa3c] = 2712, + [BNXT_ULP_CLASS_HID_188fc] = 2713, + [BNXT_ULP_CLASS_HID_1adbc] = 2714, + [BNXT_ULP_CLASS_HID_1cf7c] = 2715, + [BNXT_ULP_CLASS_HID_1f03c] = 2716, + [BNXT_ULP_CLASS_HID_18fa8] = 2717, + [BNXT_ULP_CLASS_HID_1b168] = 2718, + [BNXT_ULP_CLASS_HID_1f228] = 2719, + [BNXT_ULP_CLASS_HID_1f7e8] = 2720, + [BNXT_ULP_CLASS_HID_ba1c] = 2721, + [BNXT_ULP_CLASS_HID_bfdc] = 2722, + [BNXT_ULP_CLASS_HID_e09c] = 2723, + [BNXT_ULP_CLASS_HID_e25c] = 2724, + [BNXT_ULP_CLASS_HID_b760] = 2725, + [BNXT_ULP_CLASS_HID_b820] = 2726, + [BNXT_ULP_CLASS_HID_fde0] = 2727, + [BNXT_ULP_CLASS_HID_fea0] = 2728, + [BNXT_ULP_CLASS_HID_1ad60] = 2729, + [BNXT_ULP_CLASS_HID_1ae20] = 2730, + [BNXT_ULP_CLASS_HID_1d3e0] = 2731, + [BNXT_ULP_CLASS_HID_1f4a0] = 2732, + [BNXT_ULP_CLASS_HID_1d01c] = 2733, + [BNXT_ULP_CLASS_HID_1f5dc] = 2734, + [BNXT_ULP_CLASS_HID_1d69c] = 2735, + [BNXT_ULP_CLASS_HID_1f85c] = 2736, + [BNXT_ULP_CLASS_HID_86c0] = 2737, + [BNXT_ULP_CLASS_HID_ab80] = 2738, + [BNXT_ULP_CLASS_HID_cd40] = 2739, + [BNXT_ULP_CLASS_HID_ee00] = 2740, + [BNXT_ULP_CLASS_HID_8314] = 2741, + [BNXT_ULP_CLASS_HID_a4d4] = 2742, + [BNXT_ULP_CLASS_HID_c994] = 2743, + [BNXT_ULP_CLASS_HID_eb54] = 2744, + [BNXT_ULP_CLASS_HID_1b914] = 2745, + [BNXT_ULP_CLASS_HID_1bad4] = 2746, + [BNXT_ULP_CLASS_HID_1ff94] = 2747, + [BNXT_ULP_CLASS_HID_1e154] = 2748, + [BNXT_ULP_CLASS_HID_1bcc0] = 2749, + [BNXT_ULP_CLASS_HID_1a180] = 2750, + [BNXT_ULP_CLASS_HID_1e340] = 2751, + [BNXT_ULP_CLASS_HID_1e400] = 2752, + [BNXT_ULP_CLASS_HID_aab4] = 2753, + [BNXT_ULP_CLASS_HID_ac74] = 2754, + [BNXT_ULP_CLASS_HID_d134] = 2755, + [BNXT_ULP_CLASS_HID_f2f4] = 2756, + [BNXT_ULP_CLASS_HID_a7f8] = 2757, + [BNXT_ULP_CLASS_HID_a8b8] = 2758, + [BNXT_ULP_CLASS_HID_ea78] = 2759, + [BNXT_ULP_CLASS_HID_ef38] = 2760, + [BNXT_ULP_CLASS_HID_1ddf8] = 2761, + [BNXT_ULP_CLASS_HID_1feb8] = 2762, + [BNXT_ULP_CLASS_HID_1c078] = 2763, + [BNXT_ULP_CLASS_HID_1e538] = 2764, + [BNXT_ULP_CLASS_HID_1c0b4] = 2765, + [BNXT_ULP_CLASS_HID_1e274] = 2766, + [BNXT_ULP_CLASS_HID_1c734] = 2767, + [BNXT_ULP_CLASS_HID_1e8f4] = 2768, + [BNXT_ULP_CLASS_HID_906c] = 2769, + [BNXT_ULP_CLASS_HID_b52c] = 2770, + [BNXT_ULP_CLASS_HID_d6ec] = 2771, + [BNXT_ULP_CLASS_HID_fbac] = 2772, + [BNXT_ULP_CLASS_HID_c86c] = 2773, + [BNXT_ULP_CLASS_HID_ed2c] = 2774, + [BNXT_ULP_CLASS_HID_d330] = 2775, + [BNXT_ULP_CLASS_HID_f4f0] = 2776, + [BNXT_ULP_CLASS_HID_182b0] = 2777, + [BNXT_ULP_CLASS_HID_1a470] = 2778, + [BNXT_ULP_CLASS_HID_1c930] = 2779, + [BNXT_ULP_CLASS_HID_1eaf0] = 2780, + [BNXT_ULP_CLASS_HID_1866c] = 2781, + [BNXT_ULP_CLASS_HID_1ab2c] = 2782, + [BNXT_ULP_CLASS_HID_1ccec] = 2783, + [BNXT_ULP_CLASS_HID_1f1ac] = 2784, + [BNXT_ULP_CLASS_HID_b4d0] = 2785, + [BNXT_ULP_CLASS_HID_b990] = 2786, + [BNXT_ULP_CLASS_HID_fb50] = 2787, + [BNXT_ULP_CLASS_HID_fc10] = 2788, + [BNXT_ULP_CLASS_HID_b124] = 2789, + [BNXT_ULP_CLASS_HID_b2e4] = 2790, + [BNXT_ULP_CLASS_HID_f7a4] = 2791, + [BNXT_ULP_CLASS_HID_f964] = 2792, + [BNXT_ULP_CLASS_HID_1a724] = 2793, + [BNXT_ULP_CLASS_HID_1a8e4] = 2794, + [BNXT_ULP_CLASS_HID_1eda4] = 2795, + [BNXT_ULP_CLASS_HID_1ef64] = 2796, + [BNXT_ULP_CLASS_HID_1aad0] = 2797, + [BNXT_ULP_CLASS_HID_1af90] = 2798, + [BNXT_ULP_CLASS_HID_1d150] = 2799, + [BNXT_ULP_CLASS_HID_1f210] = 2800, + [BNXT_ULP_CLASS_HID_8084] = 2801, + [BNXT_ULP_CLASS_HID_a244] = 2802, + [BNXT_ULP_CLASS_HID_c704] = 2803, + [BNXT_ULP_CLASS_HID_e8c4] = 2804, + [BNXT_ULP_CLASS_HID_9dc8] = 2805, + [BNXT_ULP_CLASS_HID_be88] = 2806, + [BNXT_ULP_CLASS_HID_c048] = 2807, + [BNXT_ULP_CLASS_HID_e508] = 2808, + [BNXT_ULP_CLASS_HID_1b3c8] = 2809, + [BNXT_ULP_CLASS_HID_1b488] = 2810, + [BNXT_ULP_CLASS_HID_1f648] = 2811, + [BNXT_ULP_CLASS_HID_1fb08] = 2812, + [BNXT_ULP_CLASS_HID_1b684] = 2813, + [BNXT_ULP_CLASS_HID_1b844] = 2814, + [BNXT_ULP_CLASS_HID_1fd04] = 2815, + [BNXT_ULP_CLASS_HID_1fec4] = 2816, + [BNXT_ULP_CLASS_HID_a568] = 2817, + [BNXT_ULP_CLASS_HID_a628] = 2818, + [BNXT_ULP_CLASS_HID_ebe8] = 2819, + [BNXT_ULP_CLASS_HID_eca8] = 2820, + [BNXT_ULP_CLASS_HID_a1bc] = 2821, + [BNXT_ULP_CLASS_HID_a37c] = 2822, + [BNXT_ULP_CLASS_HID_e43c] = 2823, + [BNXT_ULP_CLASS_HID_e9fc] = 2824, + [BNXT_ULP_CLASS_HID_1d7bc] = 2825, + [BNXT_ULP_CLASS_HID_1f97c] = 2826, + [BNXT_ULP_CLASS_HID_1da3c] = 2827, + [BNXT_ULP_CLASS_HID_1fffc] = 2828, + [BNXT_ULP_CLASS_HID_1db68] = 2829, + [BNXT_ULP_CLASS_HID_1fc28] = 2830, + [BNXT_ULP_CLASS_HID_1c1e8] = 2831, + [BNXT_ULP_CLASS_HID_1e2a8] = 2832, + [BNXT_ULP_CLASS_HID_9ab8] = 2833, + [BNXT_ULP_CLASS_HID_bc78] = 2834, + [BNXT_ULP_CLASS_HID_c138] = 2835, + [BNXT_ULP_CLASS_HID_e2f8] = 2836, + [BNXT_ULP_CLASS_HID_978c] = 2837, + [BNXT_ULP_CLASS_HID_b94c] = 2838, + [BNXT_ULP_CLASS_HID_da0c] = 2839, + [BNXT_ULP_CLASS_HID_ffcc] = 2840, + [BNXT_ULP_CLASS_HID_18d8c] = 2841, + [BNXT_ULP_CLASS_HID_1af4c] = 2842, + [BNXT_ULP_CLASS_HID_1f00c] = 2843, + [BNXT_ULP_CLASS_HID_1f5cc] = 2844, + [BNXT_ULP_CLASS_HID_1b0b8] = 2845, + [BNXT_ULP_CLASS_HID_1b278] = 2846, + [BNXT_ULP_CLASS_HID_1f738] = 2847, + [BNXT_ULP_CLASS_HID_1f8f8] = 2848, + [BNXT_ULP_CLASS_HID_bf2c] = 2849, + [BNXT_ULP_CLASS_HID_a0ec] = 2850, + [BNXT_ULP_CLASS_HID_e5ac] = 2851, + [BNXT_ULP_CLASS_HID_e76c] = 2852, + [BNXT_ULP_CLASS_HID_b870] = 2853, + [BNXT_ULP_CLASS_HID_bd30] = 2854, + [BNXT_ULP_CLASS_HID_fef0] = 2855, + [BNXT_ULP_CLASS_HID_e3b0] = 2856, + [BNXT_ULP_CLASS_HID_1ae70] = 2857, + [BNXT_ULP_CLASS_HID_1f330] = 2858, + [BNXT_ULP_CLASS_HID_1d4f0] = 2859, + [BNXT_ULP_CLASS_HID_1f9b0] = 2860, + [BNXT_ULP_CLASS_HID_1d52c] = 2861, + [BNXT_ULP_CLASS_HID_1f6ec] = 2862, + [BNXT_ULP_CLASS_HID_1dbac] = 2863, + [BNXT_ULP_CLASS_HID_1fd6c] = 2864, + [BNXT_ULP_CLASS_HID_34d0] = 2865, + [BNXT_ULP_CLASS_HID_3a1c] = 2866, + [BNXT_ULP_CLASS_HID_3760] = 2867, + [BNXT_ULP_CLASS_HID_5e80] = 2868, + [BNXT_ULP_CLASS_HID_5bd4] = 2869, + [BNXT_ULP_CLASS_HID_07b8] = 2870, + [BNXT_ULP_CLASS_HID_008c] = 2871, + [BNXT_ULP_CLASS_HID_282c] = 2872, + [BNXT_ULP_CLASS_HID_2570] = 2873, + [BNXT_ULP_CLASS_HID_3124] = 2874, + [BNXT_ULP_CLASS_HID_5944] = 2875, + [BNXT_ULP_CLASS_HID_5588] = 2876, + [BNXT_ULP_CLASS_HID_1e7c] = 2877, + [BNXT_ULP_CLASS_HID_1b40] = 2878, + [BNXT_ULP_CLASS_HID_22e0] = 2879, + [BNXT_ULP_CLASS_HID_3f34] = 2880, + [BNXT_ULP_CLASS_HID_a77c] = 2881, + [BNXT_ULP_CLASS_HID_a8bc] = 2882, + [BNXT_ULP_CLASS_HID_edfc] = 2883, + [BNXT_ULP_CLASS_HID_ef3c] = 2884, + [BNXT_ULP_CLASS_HID_a000] = 2885, + [BNXT_ULP_CLASS_HID_a540] = 2886, + [BNXT_ULP_CLASS_HID_e680] = 2887, + [BNXT_ULP_CLASS_HID_ebc0] = 2888, + [BNXT_ULP_CLASS_HID_1d600] = 2889, + [BNXT_ULP_CLASS_HID_1fb40] = 2890, + [BNXT_ULP_CLASS_HID_1dc80] = 2891, + [BNXT_ULP_CLASS_HID_1e1c0] = 2892, + [BNXT_ULP_CLASS_HID_1dd7c] = 2893, + [BNXT_ULP_CLASS_HID_1febc] = 2894, + [BNXT_ULP_CLASS_HID_1c3fc] = 2895, + [BNXT_ULP_CLASS_HID_1e53c] = 2896, + [BNXT_ULP_CLASS_HID_cbe0] = 2897, + [BNXT_ULP_CLASS_HID_b1f4] = 2898, + [BNXT_ULP_CLASS_HID_d334] = 2899, + [BNXT_ULP_CLASS_HID_f474] = 2900, + [BNXT_ULP_CLASS_HID_c4b4] = 2901, + [BNXT_ULP_CLASS_HID_e9f4] = 2902, + [BNXT_ULP_CLASS_HID_cb34] = 2903, + [BNXT_ULP_CLASS_HID_f138] = 2904, + [BNXT_ULP_CLASS_HID_19f78] = 2905, + [BNXT_ULP_CLASS_HID_1a0b8] = 2906, + [BNXT_ULP_CLASS_HID_1c5f8] = 2907, + [BNXT_ULP_CLASS_HID_1e738] = 2908, + [BNXT_ULP_CLASS_HID_182b4] = 2909, + [BNXT_ULP_CLASS_HID_1a7f4] = 2910, + [BNXT_ULP_CLASS_HID_1c934] = 2911, + [BNXT_ULP_CLASS_HID_1ea74] = 2912, + [BNXT_ULP_CLASS_HID_b0d8] = 2913, + [BNXT_ULP_CLASS_HID_b218] = 2914, + [BNXT_ULP_CLASS_HID_f758] = 2915, + [BNXT_ULP_CLASS_HID_f898] = 2916, + [BNXT_ULP_CLASS_HID_8dec] = 2917, + [BNXT_ULP_CLASS_HID_af2c] = 2918, + [BNXT_ULP_CLASS_HID_f06c] = 2919, + [BNXT_ULP_CLASS_HID_f5ac] = 2920, + [BNXT_ULP_CLASS_HID_1a3ec] = 2921, + [BNXT_ULP_CLASS_HID_1a52c] = 2922, + [BNXT_ULP_CLASS_HID_1e66c] = 2923, + [BNXT_ULP_CLASS_HID_1ebac] = 2924, + [BNXT_ULP_CLASS_HID_1a6d8] = 2925, + [BNXT_ULP_CLASS_HID_1a818] = 2926, + [BNXT_ULP_CLASS_HID_1ed58] = 2927, + [BNXT_ULP_CLASS_HID_1ee98] = 2928, + [BNXT_ULP_CLASS_HID_d54c] = 2929, + [BNXT_ULP_CLASS_HID_f68c] = 2930, + [BNXT_ULP_CLASS_HID_dbcc] = 2931, + [BNXT_ULP_CLASS_HID_fd0c] = 2932, + [BNXT_ULP_CLASS_HID_ae10] = 2933, + [BNXT_ULP_CLASS_HID_f350] = 2934, + [BNXT_ULP_CLASS_HID_d490] = 2935, + [BNXT_ULP_CLASS_HID_f9d0] = 2936, + [BNXT_ULP_CLASS_HID_1c410] = 2937, + [BNXT_ULP_CLASS_HID_1e950] = 2938, + [BNXT_ULP_CLASS_HID_1ca90] = 2939, + [BNXT_ULP_CLASS_HID_1f0e4] = 2940, + [BNXT_ULP_CLASS_HID_1cb4c] = 2941, + [BNXT_ULP_CLASS_HID_1b150] = 2942, + [BNXT_ULP_CLASS_HID_1d290] = 2943, + [BNXT_ULP_CLASS_HID_1f7d0] = 2944, + [BNXT_ULP_CLASS_HID_a1b0] = 2945, + [BNXT_ULP_CLASS_HID_a2f0] = 2946, + [BNXT_ULP_CLASS_HID_e430] = 2947, + [BNXT_ULP_CLASS_HID_e970] = 2948, + [BNXT_ULP_CLASS_HID_ba44] = 2949, + [BNXT_ULP_CLASS_HID_bf84] = 2950, + [BNXT_ULP_CLASS_HID_e0c4] = 2951, + [BNXT_ULP_CLASS_HID_e204] = 2952, + [BNXT_ULP_CLASS_HID_1d044] = 2953, + [BNXT_ULP_CLASS_HID_1f584] = 2954, + [BNXT_ULP_CLASS_HID_1d6c4] = 2955, + [BNXT_ULP_CLASS_HID_1f804] = 2956, + [BNXT_ULP_CLASS_HID_1d7b0] = 2957, + [BNXT_ULP_CLASS_HID_1f8f0] = 2958, + [BNXT_ULP_CLASS_HID_1da30] = 2959, + [BNXT_ULP_CLASS_HID_1ff70] = 2960, + [BNXT_ULP_CLASS_HID_c224] = 2961, + [BNXT_ULP_CLASS_HID_e764] = 2962, + [BNXT_ULP_CLASS_HID_c8a4] = 2963, + [BNXT_ULP_CLASS_HID_ede4] = 2964, + [BNXT_ULP_CLASS_HID_dee8] = 2965, + [BNXT_ULP_CLASS_HID_e028] = 2966, + [BNXT_ULP_CLASS_HID_c568] = 2967, + [BNXT_ULP_CLASS_HID_e6a8] = 2968, + [BNXT_ULP_CLASS_HID_199bc] = 2969, + [BNXT_ULP_CLASS_HID_1bafc] = 2970, + [BNXT_ULP_CLASS_HID_1dc3c] = 2971, + [BNXT_ULP_CLASS_HID_1e17c] = 2972, + [BNXT_ULP_CLASS_HID_19ce8] = 2973, + [BNXT_ULP_CLASS_HID_1be28] = 2974, + [BNXT_ULP_CLASS_HID_1c368] = 2975, + [BNXT_ULP_CLASS_HID_1e4a8] = 2976, + [BNXT_ULP_CLASS_HID_8b1c] = 2977, + [BNXT_ULP_CLASS_HID_ac5c] = 2978, + [BNXT_ULP_CLASS_HID_f19c] = 2979, + [BNXT_ULP_CLASS_HID_f2dc] = 2980, + [BNXT_ULP_CLASS_HID_8420] = 2981, + [BNXT_ULP_CLASS_HID_a960] = 2982, + [BNXT_ULP_CLASS_HID_caa0] = 2983, + [BNXT_ULP_CLASS_HID_efe0] = 2984, + [BNXT_ULP_CLASS_HID_1ba20] = 2985, + [BNXT_ULP_CLASS_HID_1bf60] = 2986, + [BNXT_ULP_CLASS_HID_1e0a0] = 2987, + [BNXT_ULP_CLASS_HID_1e5e0] = 2988, + [BNXT_ULP_CLASS_HID_1a11c] = 2989, + [BNXT_ULP_CLASS_HID_1a25c] = 2990, + [BNXT_ULP_CLASS_HID_1e79c] = 2991, + [BNXT_ULP_CLASS_HID_1e8dc] = 2992, + [BNXT_ULP_CLASS_HID_af80] = 2993, + [BNXT_ULP_CLASS_HID_f0c0] = 2994, + [BNXT_ULP_CLASS_HID_d200] = 2995, + [BNXT_ULP_CLASS_HID_f740] = 2996, + [BNXT_ULP_CLASS_HID_a854] = 2997, + [BNXT_ULP_CLASS_HID_ad94] = 2998, + [BNXT_ULP_CLASS_HID_eed4] = 2999, + [BNXT_ULP_CLASS_HID_f014] = 3000, + [BNXT_ULP_CLASS_HID_1de54] = 3001, + [BNXT_ULP_CLASS_HID_1e394] = 3002, + [BNXT_ULP_CLASS_HID_1c4d4] = 3003, + [BNXT_ULP_CLASS_HID_1e614] = 3004, + [BNXT_ULP_CLASS_HID_1c580] = 3005, + [BNXT_ULP_CLASS_HID_1e6c0] = 3006, + [BNXT_ULP_CLASS_HID_1c800] = 3007, + [BNXT_ULP_CLASS_HID_1ed40] = 3008, + [BNXT_ULP_CLASS_HID_8c6c] = 3009, + [BNXT_ULP_CLASS_HID_b1ac] = 3010, + [BNXT_ULP_CLASS_HID_f2ec] = 3011, + [BNXT_ULP_CLASS_HID_f42c] = 3012, + [BNXT_ULP_CLASS_HID_8930] = 3013, + [BNXT_ULP_CLASS_HID_aa70] = 3014, + [BNXT_ULP_CLASS_HID_cfb0] = 3015, + [BNXT_ULP_CLASS_HID_f0f0] = 3016, + [BNXT_ULP_CLASS_HID_1bf30] = 3017, + [BNXT_ULP_CLASS_HID_1a070] = 3018, + [BNXT_ULP_CLASS_HID_1e5b0] = 3019, + [BNXT_ULP_CLASS_HID_1e6f0] = 3020, + [BNXT_ULP_CLASS_HID_1a26c] = 3021, + [BNXT_ULP_CLASS_HID_1a7ac] = 3022, + [BNXT_ULP_CLASS_HID_1e8ec] = 3023, + [BNXT_ULP_CLASS_HID_1ea2c] = 3024, + [BNXT_ULP_CLASS_HID_d090] = 3025, + [BNXT_ULP_CLASS_HID_f5d0] = 3026, + [BNXT_ULP_CLASS_HID_d710] = 3027, + [BNXT_ULP_CLASS_HID_f850] = 3028, + [BNXT_ULP_CLASS_HID_ada4] = 3029, + [BNXT_ULP_CLASS_HID_aee4] = 3030, + [BNXT_ULP_CLASS_HID_d024] = 3031, + [BNXT_ULP_CLASS_HID_f564] = 3032, + [BNXT_ULP_CLASS_HID_1c3a4] = 3033, + [BNXT_ULP_CLASS_HID_1e4e4] = 3034, + [BNXT_ULP_CLASS_HID_1c624] = 3035, + [BNXT_ULP_CLASS_HID_1eb64] = 3036, + [BNXT_ULP_CLASS_HID_1c690] = 3037, + [BNXT_ULP_CLASS_HID_1ebd0] = 3038, + [BNXT_ULP_CLASS_HID_1cd10] = 3039, + [BNXT_ULP_CLASS_HID_1f364] = 3040, + [BNXT_ULP_CLASS_HID_99c8] = 3041, + [BNXT_ULP_CLASS_HID_bb08] = 3042, + [BNXT_ULP_CLASS_HID_dc48] = 3043, + [BNXT_ULP_CLASS_HID_e188] = 3044, + [BNXT_ULP_CLASS_HID_929c] = 3045, + [BNXT_ULP_CLASS_HID_b7dc] = 3046, + [BNXT_ULP_CLASS_HID_d91c] = 3047, + [BNXT_ULP_CLASS_HID_fa5c] = 3048, + [BNXT_ULP_CLASS_HID_1889c] = 3049, + [BNXT_ULP_CLASS_HID_1addc] = 3050, + [BNXT_ULP_CLASS_HID_1cf1c] = 3051, + [BNXT_ULP_CLASS_HID_1f05c] = 3052, + [BNXT_ULP_CLASS_HID_18fc8] = 3053, + [BNXT_ULP_CLASS_HID_1b108] = 3054, + [BNXT_ULP_CLASS_HID_1f248] = 3055, + [BNXT_ULP_CLASS_HID_1f788] = 3056, + [BNXT_ULP_CLASS_HID_ba7c] = 3057, + [BNXT_ULP_CLASS_HID_bfbc] = 3058, + [BNXT_ULP_CLASS_HID_e0fc] = 3059, + [BNXT_ULP_CLASS_HID_e23c] = 3060, + [BNXT_ULP_CLASS_HID_b700] = 3061, + [BNXT_ULP_CLASS_HID_b840] = 3062, + [BNXT_ULP_CLASS_HID_fd80] = 3063, + [BNXT_ULP_CLASS_HID_fec0] = 3064, + [BNXT_ULP_CLASS_HID_1ad00] = 3065, + [BNXT_ULP_CLASS_HID_1ae40] = 3066, + [BNXT_ULP_CLASS_HID_1d380] = 3067, + [BNXT_ULP_CLASS_HID_1f4c0] = 3068, + [BNXT_ULP_CLASS_HID_1d07c] = 3069, + [BNXT_ULP_CLASS_HID_1f5bc] = 3070, + [BNXT_ULP_CLASS_HID_1d6fc] = 3071, + [BNXT_ULP_CLASS_HID_1f83c] = 3072, + [BNXT_ULP_CLASS_HID_86a0] = 3073, + [BNXT_ULP_CLASS_HID_abe0] = 3074, + [BNXT_ULP_CLASS_HID_cd20] = 3075, + [BNXT_ULP_CLASS_HID_ee60] = 3076, + [BNXT_ULP_CLASS_HID_8374] = 3077, + [BNXT_ULP_CLASS_HID_a4b4] = 3078, + [BNXT_ULP_CLASS_HID_c9f4] = 3079, + [BNXT_ULP_CLASS_HID_eb34] = 3080, + [BNXT_ULP_CLASS_HID_1b974] = 3081, + [BNXT_ULP_CLASS_HID_1bab4] = 3082, + [BNXT_ULP_CLASS_HID_1fff4] = 3083, + [BNXT_ULP_CLASS_HID_1e134] = 3084, + [BNXT_ULP_CLASS_HID_1bca0] = 3085, + [BNXT_ULP_CLASS_HID_1a1e0] = 3086, + [BNXT_ULP_CLASS_HID_1e320] = 3087, + [BNXT_ULP_CLASS_HID_1e460] = 3088, + [BNXT_ULP_CLASS_HID_aad4] = 3089, + [BNXT_ULP_CLASS_HID_ac14] = 3090, + [BNXT_ULP_CLASS_HID_d154] = 3091, + [BNXT_ULP_CLASS_HID_f294] = 3092, + [BNXT_ULP_CLASS_HID_a798] = 3093, + [BNXT_ULP_CLASS_HID_a8d8] = 3094, + [BNXT_ULP_CLASS_HID_ea18] = 3095, + [BNXT_ULP_CLASS_HID_ef58] = 3096, + [BNXT_ULP_CLASS_HID_1dd98] = 3097, + [BNXT_ULP_CLASS_HID_1fed8] = 3098, + [BNXT_ULP_CLASS_HID_1c018] = 3099, + [BNXT_ULP_CLASS_HID_1e558] = 3100, + [BNXT_ULP_CLASS_HID_1c0d4] = 3101, + [BNXT_ULP_CLASS_HID_1e214] = 3102, + [BNXT_ULP_CLASS_HID_1c754] = 3103, + [BNXT_ULP_CLASS_HID_1e894] = 3104, + [BNXT_ULP_CLASS_HID_900c] = 3105, + [BNXT_ULP_CLASS_HID_b54c] = 3106, + [BNXT_ULP_CLASS_HID_d68c] = 3107, + [BNXT_ULP_CLASS_HID_fbcc] = 3108, + [BNXT_ULP_CLASS_HID_c80c] = 3109, + [BNXT_ULP_CLASS_HID_ed4c] = 3110, + [BNXT_ULP_CLASS_HID_d350] = 3111, + [BNXT_ULP_CLASS_HID_f490] = 3112, + [BNXT_ULP_CLASS_HID_182d0] = 3113, + [BNXT_ULP_CLASS_HID_1a410] = 3114, + [BNXT_ULP_CLASS_HID_1c950] = 3115, + [BNXT_ULP_CLASS_HID_1ea90] = 3116, + [BNXT_ULP_CLASS_HID_1860c] = 3117, + [BNXT_ULP_CLASS_HID_1ab4c] = 3118, + [BNXT_ULP_CLASS_HID_1cc8c] = 3119, + [BNXT_ULP_CLASS_HID_1f1cc] = 3120, + [BNXT_ULP_CLASS_HID_b4b0] = 3121, + [BNXT_ULP_CLASS_HID_b9f0] = 3122, + [BNXT_ULP_CLASS_HID_fb30] = 3123, + [BNXT_ULP_CLASS_HID_fc70] = 3124, + [BNXT_ULP_CLASS_HID_b144] = 3125, + [BNXT_ULP_CLASS_HID_b284] = 3126, + [BNXT_ULP_CLASS_HID_f7c4] = 3127, + [BNXT_ULP_CLASS_HID_f904] = 3128, + [BNXT_ULP_CLASS_HID_1a744] = 3129, + [BNXT_ULP_CLASS_HID_1a884] = 3130, + [BNXT_ULP_CLASS_HID_1edc4] = 3131, + [BNXT_ULP_CLASS_HID_1ef04] = 3132, + [BNXT_ULP_CLASS_HID_1aab0] = 3133, + [BNXT_ULP_CLASS_HID_1aff0] = 3134, + [BNXT_ULP_CLASS_HID_1d130] = 3135, + [BNXT_ULP_CLASS_HID_1f270] = 3136, + [BNXT_ULP_CLASS_HID_80e4] = 3137, + [BNXT_ULP_CLASS_HID_a224] = 3138, + [BNXT_ULP_CLASS_HID_c764] = 3139, + [BNXT_ULP_CLASS_HID_e8a4] = 3140, + [BNXT_ULP_CLASS_HID_9da8] = 3141, + [BNXT_ULP_CLASS_HID_bee8] = 3142, + [BNXT_ULP_CLASS_HID_c028] = 3143, + [BNXT_ULP_CLASS_HID_e568] = 3144, + [BNXT_ULP_CLASS_HID_1b3a8] = 3145, + [BNXT_ULP_CLASS_HID_1b4e8] = 3146, + [BNXT_ULP_CLASS_HID_1f628] = 3147, + [BNXT_ULP_CLASS_HID_1fb68] = 3148, + [BNXT_ULP_CLASS_HID_1b6e4] = 3149, + [BNXT_ULP_CLASS_HID_1b824] = 3150, + [BNXT_ULP_CLASS_HID_1fd64] = 3151, + [BNXT_ULP_CLASS_HID_1fea4] = 3152, + [BNXT_ULP_CLASS_HID_a508] = 3153, + [BNXT_ULP_CLASS_HID_a648] = 3154, + [BNXT_ULP_CLASS_HID_eb88] = 3155, + [BNXT_ULP_CLASS_HID_ecc8] = 3156, + [BNXT_ULP_CLASS_HID_a1dc] = 3157, + [BNXT_ULP_CLASS_HID_a31c] = 3158, + [BNXT_ULP_CLASS_HID_e45c] = 3159, + [BNXT_ULP_CLASS_HID_e99c] = 3160, + [BNXT_ULP_CLASS_HID_1d7dc] = 3161, + [BNXT_ULP_CLASS_HID_1f91c] = 3162, + [BNXT_ULP_CLASS_HID_1da5c] = 3163, + [BNXT_ULP_CLASS_HID_1ff9c] = 3164, + [BNXT_ULP_CLASS_HID_1db08] = 3165, + [BNXT_ULP_CLASS_HID_1fc48] = 3166, + [BNXT_ULP_CLASS_HID_1c188] = 3167, + [BNXT_ULP_CLASS_HID_1e2c8] = 3168, + [BNXT_ULP_CLASS_HID_9ad8] = 3169, + [BNXT_ULP_CLASS_HID_bc18] = 3170, + [BNXT_ULP_CLASS_HID_c158] = 3171, + [BNXT_ULP_CLASS_HID_e298] = 3172, + [BNXT_ULP_CLASS_HID_97ec] = 3173, + [BNXT_ULP_CLASS_HID_b92c] = 3174, + [BNXT_ULP_CLASS_HID_da6c] = 3175, + [BNXT_ULP_CLASS_HID_ffac] = 3176, + [BNXT_ULP_CLASS_HID_18dec] = 3177, + [BNXT_ULP_CLASS_HID_1af2c] = 3178, + [BNXT_ULP_CLASS_HID_1f06c] = 3179, + [BNXT_ULP_CLASS_HID_1f5ac] = 3180, + [BNXT_ULP_CLASS_HID_1b0d8] = 3181, + [BNXT_ULP_CLASS_HID_1b218] = 3182, + [BNXT_ULP_CLASS_HID_1f758] = 3183, + [BNXT_ULP_CLASS_HID_1f898] = 3184, + [BNXT_ULP_CLASS_HID_bf4c] = 3185, + [BNXT_ULP_CLASS_HID_a08c] = 3186, + [BNXT_ULP_CLASS_HID_e5cc] = 3187, + [BNXT_ULP_CLASS_HID_e70c] = 3188, + [BNXT_ULP_CLASS_HID_b810] = 3189, + [BNXT_ULP_CLASS_HID_bd50] = 3190, + [BNXT_ULP_CLASS_HID_fe90] = 3191, + [BNXT_ULP_CLASS_HID_e3d0] = 3192, + [BNXT_ULP_CLASS_HID_1ae10] = 3193, + [BNXT_ULP_CLASS_HID_1f350] = 3194, + [BNXT_ULP_CLASS_HID_1d490] = 3195, + [BNXT_ULP_CLASS_HID_1f9d0] = 3196, + [BNXT_ULP_CLASS_HID_1d54c] = 3197, + [BNXT_ULP_CLASS_HID_1f68c] = 3198, + [BNXT_ULP_CLASS_HID_1dbcc] = 3199, + [BNXT_ULP_CLASS_HID_1fd0c] = 3200, + [BNXT_ULP_CLASS_HID_34b0] = 3201, + [BNXT_ULP_CLASS_HID_3a7c] = 3202, + [BNXT_ULP_CLASS_HID_3700] = 3203, + [BNXT_ULP_CLASS_HID_5ee0] = 3204, + [BNXT_ULP_CLASS_HID_5bb4] = 3205, + [BNXT_ULP_CLASS_HID_07d8] = 3206, + [BNXT_ULP_CLASS_HID_00ec] = 3207, + [BNXT_ULP_CLASS_HID_284c] = 3208, + [BNXT_ULP_CLASS_HID_2510] = 3209, + [BNXT_ULP_CLASS_HID_3144] = 3210, + [BNXT_ULP_CLASS_HID_5924] = 3211, + [BNXT_ULP_CLASS_HID_55e8] = 3212, + [BNXT_ULP_CLASS_HID_1e1c] = 3213, + [BNXT_ULP_CLASS_HID_1b20] = 3214, + [BNXT_ULP_CLASS_HID_2280] = 3215, + [BNXT_ULP_CLASS_HID_3f54] = 3216, + [BNXT_ULP_CLASS_HID_24604] = 3217, + [BNXT_ULP_CLASS_HID_255d4] = 3218, + [BNXT_ULP_CLASS_HID_22e08] = 3219, + [BNXT_ULP_CLASS_HID_24378] = 3220, + [BNXT_ULP_CLASS_HID_20fcc] = 3221, + [BNXT_ULP_CLASS_HID_21a9c] = 3222, + [BNXT_ULP_CLASS_HID_217d0] = 3223, + [BNXT_ULP_CLASS_HID_20800] = 3224, + [BNXT_ULP_CLASS_HID_253a0] = 3225, + [BNXT_ULP_CLASS_HID_23f70] = 3226, + [BNXT_ULP_CLASS_HID_23ba4] = 3227, + [BNXT_ULP_CLASS_HID_22c94] = 3228, + [BNXT_ULP_CLASS_HID_21968] = 3229, + [BNXT_ULP_CLASS_HID_243c4] = 3230, + [BNXT_ULP_CLASS_HID_25c38] = 3231, + [BNXT_ULP_CLASS_HID_2125c] = 3232, + [BNXT_ULP_CLASS_HID_240c8] = 3233, + [BNXT_ULP_CLASS_HID_22f98] = 3234, + [BNXT_ULP_CLASS_HID_228cc] = 3235, + [BNXT_ULP_CLASS_HID_25d3c] = 3236, + [BNXT_ULP_CLASS_HID_20990] = 3237, + [BNXT_ULP_CLASS_HID_214a0] = 3238, + [BNXT_ULP_CLASS_HID_21194] = 3239, + [BNXT_ULP_CLASS_HID_202c4] = 3240, + [BNXT_ULP_CLASS_HID_22a64] = 3241, + [BNXT_ULP_CLASS_HID_23934] = 3242, + [BNXT_ULP_CLASS_HID_23268] = 3243, + [BNXT_ULP_CLASS_HID_22758] = 3244, + [BNXT_ULP_CLASS_HID_2132c] = 3245, + [BNXT_ULP_CLASS_HID_25d88] = 3246, + [BNXT_ULP_CLASS_HID_256fc] = 3247, + [BNXT_ULP_CLASS_HID_24b2c] = 3248, + [BNXT_ULP_CLASS_HID_22f14] = 3249, + [BNXT_ULP_CLASS_HID_23a24] = 3250, + [BNXT_ULP_CLASS_HID_23718] = 3251, + [BNXT_ULP_CLASS_HID_22848] = 3252, + [BNXT_ULP_CLASS_HID_214dc] = 3253, + [BNXT_ULP_CLASS_HID_25eb8] = 3254, + [BNXT_ULP_CLASS_HID_25bec] = 3255, + [BNXT_ULP_CLASS_HID_21110] = 3256, + [BNXT_ULP_CLASS_HID_238b0] = 3257, + [BNXT_ULP_CLASS_HID_20440] = 3258, + [BNXT_ULP_CLASS_HID_200b4] = 3259, + [BNXT_ULP_CLASS_HID_235e4] = 3260, + [BNXT_ULP_CLASS_HID_25d04] = 3261, + [BNXT_ULP_CLASS_HID_228d4] = 3262, + [BNXT_ULP_CLASS_HID_22508] = 3263, + [BNXT_ULP_CLASS_HID_25678] = 3264, + [BNXT_ULP_CLASS_HID_229d8] = 3265, + [BNXT_ULP_CLASS_HID_234e8] = 3266, + [BNXT_ULP_CLASS_HID_231dc] = 3267, + [BNXT_ULP_CLASS_HID_2220c] = 3268, + [BNXT_ULP_CLASS_HID_24dac] = 3269, + [BNXT_ULP_CLASS_HID_2597c] = 3270, + [BNXT_ULP_CLASS_HID_255b0] = 3271, + [BNXT_ULP_CLASS_HID_246e0] = 3272, + [BNXT_ULP_CLASS_HID_23374] = 3273, + [BNXT_ULP_CLASS_HID_21e04] = 3274, + [BNXT_ULP_CLASS_HID_21b78] = 3275, + [BNXT_ULP_CLASS_HID_20fa8] = 3276, + [BNXT_ULP_CLASS_HID_257c8] = 3277, + [BNXT_ULP_CLASS_HID_22298] = 3278, + [BNXT_ULP_CLASS_HID_23fcc] = 3279, + [BNXT_ULP_CLASS_HID_2503c] = 3280, + [BNXT_ULP_CLASS_HID_2239c] = 3281, + [BNXT_ULP_CLASS_HID_20eac] = 3282, + [BNXT_ULP_CLASS_HID_20be0] = 3283, + [BNXT_ULP_CLASS_HID_23cd0] = 3284, + [BNXT_ULP_CLASS_HID_24470] = 3285, + [BNXT_ULP_CLASS_HID_25300] = 3286, + [BNXT_ULP_CLASS_HID_22c74] = 3287, + [BNXT_ULP_CLASS_HID_240a4] = 3288, + [BNXT_ULP_CLASS_HID_23da0] = 3289, + [BNXT_ULP_CLASS_HID_20970] = 3290, + [BNXT_ULP_CLASS_HID_205a4] = 3291, + [BNXT_ULP_CLASS_HID_23694] = 3292, + [BNXT_ULP_CLASS_HID_25e34] = 3293, + [BNXT_ULP_CLASS_HID_22dc4] = 3294, + [BNXT_ULP_CLASS_HID_22638] = 3295, + [BNXT_ULP_CLASS_HID_25b68] = 3296, + [BNXT_ULP_CLASS_HID_34c8] = 3297, + [BNXT_ULP_CLASS_HID_3a04] = 3298, + [BNXT_ULP_CLASS_HID_09d4] = 3299, + [BNXT_ULP_CLASS_HID_5e98] = 3300, + [BNXT_ULP_CLASS_HID_2da8] = 3301, + [BNXT_ULP_CLASS_HID_07a0] = 3302, + [BNXT_ULP_CLASS_HID_1370] = 3303, + [BNXT_ULP_CLASS_HID_2834] = 3304, + [BNXT_ULP_CLASS_HID_37c4] = 3305, + [BNXT_ULP_CLASS_HID_0398] = 3306, + [BNXT_ULP_CLASS_HID_595c] = 3307, + [BNXT_ULP_CLASS_HID_246c] = 3308, + [BNXT_ULP_CLASS_HID_1e64] = 3309, + [BNXT_ULP_CLASS_HID_48c0] = 3310, + [BNXT_ULP_CLASS_HID_22f8] = 3311, + [BNXT_ULP_CLASS_HID_3188] = 3312, + [BNXT_ULP_CLASS_HID_24664] = 3313, + [BNXT_ULP_CLASS_HID_29418] = 3314, + [BNXT_ULP_CLASS_HID_30118] = 3315, + [BNXT_ULP_CLASS_HID_38a18] = 3316, + [BNXT_ULP_CLASS_HID_255b4] = 3317, + [BNXT_ULP_CLASS_HID_2deb4] = 3318, + [BNXT_ULP_CLASS_HID_34bb4] = 3319, + [BNXT_ULP_CLASS_HID_39968] = 3320, + [BNXT_ULP_CLASS_HID_22e68] = 3321, + [BNXT_ULP_CLASS_HID_2db68] = 3322, + [BNXT_ULP_CLASS_HID_34468] = 3323, + [BNXT_ULP_CLASS_HID_3921c] = 3324, + [BNXT_ULP_CLASS_HID_24318] = 3325, + [BNXT_ULP_CLASS_HID_290cc] = 3326, + [BNXT_ULP_CLASS_HID_31dcc] = 3327, + [BNXT_ULP_CLASS_HID_386cc] = 3328, + [BNXT_ULP_CLASS_HID_20fac] = 3329, + [BNXT_ULP_CLASS_HID_2b8ac] = 3330, + [BNXT_ULP_CLASS_HID_325ac] = 3331, + [BNXT_ULP_CLASS_HID_3aeac] = 3332, + [BNXT_ULP_CLASS_HID_21afc] = 3333, + [BNXT_ULP_CLASS_HID_287fc] = 3334, + [BNXT_ULP_CLASS_HID_330fc] = 3335, + [BNXT_ULP_CLASS_HID_3bdfc] = 3336, + [BNXT_ULP_CLASS_HID_217b0] = 3337, + [BNXT_ULP_CLASS_HID_280b0] = 3338, + [BNXT_ULP_CLASS_HID_30db0] = 3339, + [BNXT_ULP_CLASS_HID_3b6b0] = 3340, + [BNXT_ULP_CLASS_HID_20860] = 3341, + [BNXT_ULP_CLASS_HID_2b560] = 3342, + [BNXT_ULP_CLASS_HID_33e60] = 3343, + [BNXT_ULP_CLASS_HID_3ab60] = 3344, + [BNXT_ULP_CLASS_HID_253c0] = 3345, + [BNXT_ULP_CLASS_HID_2dcc0] = 3346, + [BNXT_ULP_CLASS_HID_349c0] = 3347, + [BNXT_ULP_CLASS_HID_397f4] = 3348, + [BNXT_ULP_CLASS_HID_23f10] = 3349, + [BNXT_ULP_CLASS_HID_2a810] = 3350, + [BNXT_ULP_CLASS_HID_35510] = 3351, + [BNXT_ULP_CLASS_HID_3de10] = 3352, + [BNXT_ULP_CLASS_HID_23bc4] = 3353, + [BNXT_ULP_CLASS_HID_2a4c4] = 3354, + [BNXT_ULP_CLASS_HID_351c4] = 3355, + [BNXT_ULP_CLASS_HID_3dac4] = 3356, + [BNXT_ULP_CLASS_HID_22cf4] = 3357, + [BNXT_ULP_CLASS_HID_2d9f4] = 3358, + [BNXT_ULP_CLASS_HID_342f4] = 3359, + [BNXT_ULP_CLASS_HID_390a8] = 3360, + [BNXT_ULP_CLASS_HID_21908] = 3361, + [BNXT_ULP_CLASS_HID_28208] = 3362, + [BNXT_ULP_CLASS_HID_30f08] = 3363, + [BNXT_ULP_CLASS_HID_3b808] = 3364, + [BNXT_ULP_CLASS_HID_243a4] = 3365, + [BNXT_ULP_CLASS_HID_29158] = 3366, + [BNXT_ULP_CLASS_HID_31a58] = 3367, + [BNXT_ULP_CLASS_HID_38758] = 3368, + [BNXT_ULP_CLASS_HID_25c58] = 3369, + [BNXT_ULP_CLASS_HID_2c958] = 3370, + [BNXT_ULP_CLASS_HID_3170c] = 3371, + [BNXT_ULP_CLASS_HID_3800c] = 3372, + [BNXT_ULP_CLASS_HID_2123c] = 3373, + [BNXT_ULP_CLASS_HID_29f3c] = 3374, + [BNXT_ULP_CLASS_HID_3083c] = 3375, + [BNXT_ULP_CLASS_HID_3b53c] = 3376, + [BNXT_ULP_CLASS_HID_240a8] = 3377, + [BNXT_ULP_CLASS_HID_2cda8] = 3378, + [BNXT_ULP_CLASS_HID_31b5c] = 3379, + [BNXT_ULP_CLASS_HID_3845c] = 3380, + [BNXT_ULP_CLASS_HID_22ff8] = 3381, + [BNXT_ULP_CLASS_HID_2d8f8] = 3382, + [BNXT_ULP_CLASS_HID_345f8] = 3383, + [BNXT_ULP_CLASS_HID_393ac] = 3384, + [BNXT_ULP_CLASS_HID_228ac] = 3385, + [BNXT_ULP_CLASS_HID_2d5ac] = 3386, + [BNXT_ULP_CLASS_HID_35eac] = 3387, + [BNXT_ULP_CLASS_HID_3cbac] = 3388, + [BNXT_ULP_CLASS_HID_25d5c] = 3389, + [BNXT_ULP_CLASS_HID_2c65c] = 3390, + [BNXT_ULP_CLASS_HID_31410] = 3391, + [BNXT_ULP_CLASS_HID_38110] = 3392, + [BNXT_ULP_CLASS_HID_209f0] = 3393, + [BNXT_ULP_CLASS_HID_2b2f0] = 3394, + [BNXT_ULP_CLASS_HID_33ff0] = 3395, + [BNXT_ULP_CLASS_HID_3a8f0] = 3396, + [BNXT_ULP_CLASS_HID_214c0] = 3397, + [BNXT_ULP_CLASS_HID_281c0] = 3398, + [BNXT_ULP_CLASS_HID_30ac0] = 3399, + [BNXT_ULP_CLASS_HID_3b7c0] = 3400, + [BNXT_ULP_CLASS_HID_211f4] = 3401, + [BNXT_ULP_CLASS_HID_29af4] = 3402, + [BNXT_ULP_CLASS_HID_307f4] = 3403, + [BNXT_ULP_CLASS_HID_3b0f4] = 3404, + [BNXT_ULP_CLASS_HID_202a4] = 3405, + [BNXT_ULP_CLASS_HID_28fa4] = 3406, + [BNXT_ULP_CLASS_HID_338a4] = 3407, + [BNXT_ULP_CLASS_HID_3a5a4] = 3408, + [BNXT_ULP_CLASS_HID_22a04] = 3409, + [BNXT_ULP_CLASS_HID_2d704] = 3410, + [BNXT_ULP_CLASS_HID_34004] = 3411, + [BNXT_ULP_CLASS_HID_3cd04] = 3412, + [BNXT_ULP_CLASS_HID_23954] = 3413, + [BNXT_ULP_CLASS_HID_2a254] = 3414, + [BNXT_ULP_CLASS_HID_32f54] = 3415, + [BNXT_ULP_CLASS_HID_3d854] = 3416, + [BNXT_ULP_CLASS_HID_23208] = 3417, + [BNXT_ULP_CLASS_HID_2bf08] = 3418, + [BNXT_ULP_CLASS_HID_32808] = 3419, + [BNXT_ULP_CLASS_HID_3d508] = 3420, + [BNXT_ULP_CLASS_HID_22738] = 3421, + [BNXT_ULP_CLASS_HID_2d038] = 3422, + [BNXT_ULP_CLASS_HID_35d38] = 3423, + [BNXT_ULP_CLASS_HID_3c638] = 3424, + [BNXT_ULP_CLASS_HID_2134c] = 3425, + [BNXT_ULP_CLASS_HID_29c4c] = 3426, + [BNXT_ULP_CLASS_HID_3094c] = 3427, + [BNXT_ULP_CLASS_HID_3b24c] = 3428, + [BNXT_ULP_CLASS_HID_25de8] = 3429, + [BNXT_ULP_CLASS_HID_2c6e8] = 3430, + [BNXT_ULP_CLASS_HID_3149c] = 3431, + [BNXT_ULP_CLASS_HID_3819c] = 3432, + [BNXT_ULP_CLASS_HID_2569c] = 3433, + [BNXT_ULP_CLASS_HID_2c39c] = 3434, + [BNXT_ULP_CLASS_HID_31150] = 3435, + [BNXT_ULP_CLASS_HID_39a50] = 3436, + [BNXT_ULP_CLASS_HID_24b4c] = 3437, + [BNXT_ULP_CLASS_HID_29900] = 3438, + [BNXT_ULP_CLASS_HID_30200] = 3439, + [BNXT_ULP_CLASS_HID_38f00] = 3440, + [BNXT_ULP_CLASS_HID_22f74] = 3441, + [BNXT_ULP_CLASS_HID_2d874] = 3442, + [BNXT_ULP_CLASS_HID_34574] = 3443, + [BNXT_ULP_CLASS_HID_39328] = 3444, + [BNXT_ULP_CLASS_HID_23a44] = 3445, + [BNXT_ULP_CLASS_HID_2a744] = 3446, + [BNXT_ULP_CLASS_HID_35044] = 3447, + [BNXT_ULP_CLASS_HID_3dd44] = 3448, + [BNXT_ULP_CLASS_HID_23778] = 3449, + [BNXT_ULP_CLASS_HID_2a078] = 3450, + [BNXT_ULP_CLASS_HID_32d78] = 3451, + [BNXT_ULP_CLASS_HID_3d678] = 3452, + [BNXT_ULP_CLASS_HID_22828] = 3453, + [BNXT_ULP_CLASS_HID_2d528] = 3454, + [BNXT_ULP_CLASS_HID_35e28] = 3455, + [BNXT_ULP_CLASS_HID_3cb28] = 3456, + [BNXT_ULP_CLASS_HID_214bc] = 3457, + [BNXT_ULP_CLASS_HID_281bc] = 3458, + [BNXT_ULP_CLASS_HID_30abc] = 3459, + [BNXT_ULP_CLASS_HID_3b7bc] = 3460, + [BNXT_ULP_CLASS_HID_25ed8] = 3461, + [BNXT_ULP_CLASS_HID_2cbd8] = 3462, + [BNXT_ULP_CLASS_HID_3198c] = 3463, + [BNXT_ULP_CLASS_HID_3828c] = 3464, + [BNXT_ULP_CLASS_HID_25b8c] = 3465, + [BNXT_ULP_CLASS_HID_2c48c] = 3466, + [BNXT_ULP_CLASS_HID_31240] = 3467, + [BNXT_ULP_CLASS_HID_39f40] = 3468, + [BNXT_ULP_CLASS_HID_21170] = 3469, + [BNXT_ULP_CLASS_HID_29a70] = 3470, + [BNXT_ULP_CLASS_HID_30770] = 3471, + [BNXT_ULP_CLASS_HID_3b070] = 3472, + [BNXT_ULP_CLASS_HID_238d0] = 3473, + [BNXT_ULP_CLASS_HID_2a5d0] = 3474, + [BNXT_ULP_CLASS_HID_32ed0] = 3475, + [BNXT_ULP_CLASS_HID_3dbd0] = 3476, + [BNXT_ULP_CLASS_HID_20420] = 3477, + [BNXT_ULP_CLASS_HID_2b120] = 3478, + [BNXT_ULP_CLASS_HID_33a20] = 3479, + [BNXT_ULP_CLASS_HID_3a720] = 3480, + [BNXT_ULP_CLASS_HID_200d4] = 3481, + [BNXT_ULP_CLASS_HID_28dd4] = 3482, + [BNXT_ULP_CLASS_HID_336d4] = 3483, + [BNXT_ULP_CLASS_HID_3a3d4] = 3484, + [BNXT_ULP_CLASS_HID_23584] = 3485, + [BNXT_ULP_CLASS_HID_2be84] = 3486, + [BNXT_ULP_CLASS_HID_32b84] = 3487, + [BNXT_ULP_CLASS_HID_3d484] = 3488, + [BNXT_ULP_CLASS_HID_25d64] = 3489, + [BNXT_ULP_CLASS_HID_2c664] = 3490, + [BNXT_ULP_CLASS_HID_31418] = 3491, + [BNXT_ULP_CLASS_HID_38118] = 3492, + [BNXT_ULP_CLASS_HID_228b4] = 3493, + [BNXT_ULP_CLASS_HID_2d5b4] = 3494, + [BNXT_ULP_CLASS_HID_35eb4] = 3495, + [BNXT_ULP_CLASS_HID_3cbb4] = 3496, + [BNXT_ULP_CLASS_HID_22568] = 3497, + [BNXT_ULP_CLASS_HID_2ae68] = 3498, + [BNXT_ULP_CLASS_HID_35b68] = 3499, + [BNXT_ULP_CLASS_HID_3c468] = 3500, + [BNXT_ULP_CLASS_HID_25618] = 3501, + [BNXT_ULP_CLASS_HID_2c318] = 3502, + [BNXT_ULP_CLASS_HID_310cc] = 3503, + [BNXT_ULP_CLASS_HID_39dcc] = 3504, + [BNXT_ULP_CLASS_HID_229b8] = 3505, + [BNXT_ULP_CLASS_HID_2d2b8] = 3506, + [BNXT_ULP_CLASS_HID_35fb8] = 3507, + [BNXT_ULP_CLASS_HID_3c8b8] = 3508, + [BNXT_ULP_CLASS_HID_23488] = 3509, + [BNXT_ULP_CLASS_HID_2a188] = 3510, + [BNXT_ULP_CLASS_HID_32a88] = 3511, + [BNXT_ULP_CLASS_HID_3d788] = 3512, + [BNXT_ULP_CLASS_HID_231bc] = 3513, + [BNXT_ULP_CLASS_HID_2babc] = 3514, + [BNXT_ULP_CLASS_HID_327bc] = 3515, + [BNXT_ULP_CLASS_HID_3d0bc] = 3516, + [BNXT_ULP_CLASS_HID_2226c] = 3517, + [BNXT_ULP_CLASS_HID_2af6c] = 3518, + [BNXT_ULP_CLASS_HID_3586c] = 3519, + [BNXT_ULP_CLASS_HID_3c56c] = 3520, + [BNXT_ULP_CLASS_HID_24dcc] = 3521, + [BNXT_ULP_CLASS_HID_29b80] = 3522, + [BNXT_ULP_CLASS_HID_30480] = 3523, + [BNXT_ULP_CLASS_HID_3b180] = 3524, + [BNXT_ULP_CLASS_HID_2591c] = 3525, + [BNXT_ULP_CLASS_HID_2c21c] = 3526, + [BNXT_ULP_CLASS_HID_313d0] = 3527, + [BNXT_ULP_CLASS_HID_39cd0] = 3528, + [BNXT_ULP_CLASS_HID_255d0] = 3529, + [BNXT_ULP_CLASS_HID_2ded0] = 3530, + [BNXT_ULP_CLASS_HID_34bd0] = 3531, + [BNXT_ULP_CLASS_HID_39984] = 3532, + [BNXT_ULP_CLASS_HID_24680] = 3533, + [BNXT_ULP_CLASS_HID_294b4] = 3534, + [BNXT_ULP_CLASS_HID_301b4] = 3535, + [BNXT_ULP_CLASS_HID_38ab4] = 3536, + [BNXT_ULP_CLASS_HID_23314] = 3537, + [BNXT_ULP_CLASS_HID_2bc14] = 3538, + [BNXT_ULP_CLASS_HID_32914] = 3539, + [BNXT_ULP_CLASS_HID_3d214] = 3540, + [BNXT_ULP_CLASS_HID_21e64] = 3541, + [BNXT_ULP_CLASS_HID_28b64] = 3542, + [BNXT_ULP_CLASS_HID_33464] = 3543, + [BNXT_ULP_CLASS_HID_3a164] = 3544, + [BNXT_ULP_CLASS_HID_21b18] = 3545, + [BNXT_ULP_CLASS_HID_28418] = 3546, + [BNXT_ULP_CLASS_HID_33118] = 3547, + [BNXT_ULP_CLASS_HID_3ba18] = 3548, + [BNXT_ULP_CLASS_HID_20fc8] = 3549, + [BNXT_ULP_CLASS_HID_2b8c8] = 3550, + [BNXT_ULP_CLASS_HID_325c8] = 3551, + [BNXT_ULP_CLASS_HID_3aec8] = 3552, + [BNXT_ULP_CLASS_HID_257a8] = 3553, + [BNXT_ULP_CLASS_HID_2c0a8] = 3554, + [BNXT_ULP_CLASS_HID_34da8] = 3555, + [BNXT_ULP_CLASS_HID_39b5c] = 3556, + [BNXT_ULP_CLASS_HID_222f8] = 3557, + [BNXT_ULP_CLASS_HID_2aff8] = 3558, + [BNXT_ULP_CLASS_HID_358f8] = 3559, + [BNXT_ULP_CLASS_HID_3c5f8] = 3560, + [BNXT_ULP_CLASS_HID_23fac] = 3561, + [BNXT_ULP_CLASS_HID_2a8ac] = 3562, + [BNXT_ULP_CLASS_HID_355ac] = 3563, + [BNXT_ULP_CLASS_HID_3deac] = 3564, + [BNXT_ULP_CLASS_HID_2505c] = 3565, + [BNXT_ULP_CLASS_HID_2dd5c] = 3566, + [BNXT_ULP_CLASS_HID_3465c] = 3567, + [BNXT_ULP_CLASS_HID_39410] = 3568, + [BNXT_ULP_CLASS_HID_223fc] = 3569, + [BNXT_ULP_CLASS_HID_2acfc] = 3570, + [BNXT_ULP_CLASS_HID_359fc] = 3571, + [BNXT_ULP_CLASS_HID_3c2fc] = 3572, + [BNXT_ULP_CLASS_HID_20ecc] = 3573, + [BNXT_ULP_CLASS_HID_2bbcc] = 3574, + [BNXT_ULP_CLASS_HID_324cc] = 3575, + [BNXT_ULP_CLASS_HID_3d1cc] = 3576, + [BNXT_ULP_CLASS_HID_20b80] = 3577, + [BNXT_ULP_CLASS_HID_2b480] = 3578, + [BNXT_ULP_CLASS_HID_32180] = 3579, + [BNXT_ULP_CLASS_HID_3aa80] = 3580, + [BNXT_ULP_CLASS_HID_23cb0] = 3581, + [BNXT_ULP_CLASS_HID_2a9b0] = 3582, + [BNXT_ULP_CLASS_HID_352b0] = 3583, + [BNXT_ULP_CLASS_HID_3dfb0] = 3584, + [BNXT_ULP_CLASS_HID_24410] = 3585, + [BNXT_ULP_CLASS_HID_295c4] = 3586, + [BNXT_ULP_CLASS_HID_31ec4] = 3587, + [BNXT_ULP_CLASS_HID_38bc4] = 3588, + [BNXT_ULP_CLASS_HID_25360] = 3589, + [BNXT_ULP_CLASS_HID_2dc60] = 3590, + [BNXT_ULP_CLASS_HID_34960] = 3591, + [BNXT_ULP_CLASS_HID_39714] = 3592, + [BNXT_ULP_CLASS_HID_22c14] = 3593, + [BNXT_ULP_CLASS_HID_2d914] = 3594, + [BNXT_ULP_CLASS_HID_34214] = 3595, + [BNXT_ULP_CLASS_HID_393c8] = 3596, + [BNXT_ULP_CLASS_HID_240c4] = 3597, + [BNXT_ULP_CLASS_HID_2cdc4] = 3598, + [BNXT_ULP_CLASS_HID_31bf8] = 3599, + [BNXT_ULP_CLASS_HID_384f8] = 3600, + [BNXT_ULP_CLASS_HID_23dc0] = 3601, + [BNXT_ULP_CLASS_HID_2a6c0] = 3602, + [BNXT_ULP_CLASS_HID_353c0] = 3603, + [BNXT_ULP_CLASS_HID_3dcc0] = 3604, + [BNXT_ULP_CLASS_HID_20910] = 3605, + [BNXT_ULP_CLASS_HID_2b210] = 3606, + [BNXT_ULP_CLASS_HID_33f10] = 3607, + [BNXT_ULP_CLASS_HID_3a810] = 3608, + [BNXT_ULP_CLASS_HID_205c4] = 3609, + [BNXT_ULP_CLASS_HID_28ec4] = 3610, + [BNXT_ULP_CLASS_HID_33bc4] = 3611, + [BNXT_ULP_CLASS_HID_3a4c4] = 3612, + [BNXT_ULP_CLASS_HID_236f4] = 3613, + [BNXT_ULP_CLASS_HID_2a3f4] = 3614, + [BNXT_ULP_CLASS_HID_32cf4] = 3615, + [BNXT_ULP_CLASS_HID_3d9f4] = 3616, + [BNXT_ULP_CLASS_HID_25e54] = 3617, + [BNXT_ULP_CLASS_HID_2cb54] = 3618, + [BNXT_ULP_CLASS_HID_31908] = 3619, + [BNXT_ULP_CLASS_HID_38208] = 3620, + [BNXT_ULP_CLASS_HID_22da4] = 3621, + [BNXT_ULP_CLASS_HID_2d6a4] = 3622, + [BNXT_ULP_CLASS_HID_343a4] = 3623, + [BNXT_ULP_CLASS_HID_39158] = 3624, + [BNXT_ULP_CLASS_HID_22658] = 3625, + [BNXT_ULP_CLASS_HID_2d358] = 3626, + [BNXT_ULP_CLASS_HID_35c58] = 3627, + [BNXT_ULP_CLASS_HID_3c958] = 3628, + [BNXT_ULP_CLASS_HID_25b08] = 3629, + [BNXT_ULP_CLASS_HID_2c408] = 3630, + [BNXT_ULP_CLASS_HID_3123c] = 3631, + [BNXT_ULP_CLASS_HID_39f3c] = 3632, + [BNXT_ULP_CLASS_HID_34a8] = 3633, + [BNXT_ULP_CLASS_HID_3a64] = 3634, + [BNXT_ULP_CLASS_HID_09b4] = 3635, + [BNXT_ULP_CLASS_HID_5ef8] = 3636, + [BNXT_ULP_CLASS_HID_2dc8] = 3637, + [BNXT_ULP_CLASS_HID_07c0] = 3638, + [BNXT_ULP_CLASS_HID_1310] = 3639, + [BNXT_ULP_CLASS_HID_2854] = 3640, + [BNXT_ULP_CLASS_HID_37a4] = 3641, + [BNXT_ULP_CLASS_HID_03f8] = 3642, + [BNXT_ULP_CLASS_HID_593c] = 3643, + [BNXT_ULP_CLASS_HID_240c] = 3644, + [BNXT_ULP_CLASS_HID_1e04] = 3645, + [BNXT_ULP_CLASS_HID_48a0] = 3646, + [BNXT_ULP_CLASS_HID_2298] = 3647, + [BNXT_ULP_CLASS_HID_31e8] = 3648, + [BNXT_ULP_CLASS_HID_24644] = 3649, + [BNXT_ULP_CLASS_HID_29438] = 3650, + [BNXT_ULP_CLASS_HID_30138] = 3651, + [BNXT_ULP_CLASS_HID_38a38] = 3652, + [BNXT_ULP_CLASS_HID_25594] = 3653, + [BNXT_ULP_CLASS_HID_2de94] = 3654, + [BNXT_ULP_CLASS_HID_34b94] = 3655, + [BNXT_ULP_CLASS_HID_39948] = 3656, + [BNXT_ULP_CLASS_HID_22e48] = 3657, + [BNXT_ULP_CLASS_HID_2db48] = 3658, + [BNXT_ULP_CLASS_HID_34448] = 3659, + [BNXT_ULP_CLASS_HID_3923c] = 3660, + [BNXT_ULP_CLASS_HID_24338] = 3661, + [BNXT_ULP_CLASS_HID_290ec] = 3662, + [BNXT_ULP_CLASS_HID_31dec] = 3663, + [BNXT_ULP_CLASS_HID_386ec] = 3664, + [BNXT_ULP_CLASS_HID_20f8c] = 3665, + [BNXT_ULP_CLASS_HID_2b88c] = 3666, + [BNXT_ULP_CLASS_HID_3258c] = 3667, + [BNXT_ULP_CLASS_HID_3ae8c] = 3668, + [BNXT_ULP_CLASS_HID_21adc] = 3669, + [BNXT_ULP_CLASS_HID_287dc] = 3670, + [BNXT_ULP_CLASS_HID_330dc] = 3671, + [BNXT_ULP_CLASS_HID_3bddc] = 3672, + [BNXT_ULP_CLASS_HID_21790] = 3673, + [BNXT_ULP_CLASS_HID_28090] = 3674, + [BNXT_ULP_CLASS_HID_30d90] = 3675, + [BNXT_ULP_CLASS_HID_3b690] = 3676, + [BNXT_ULP_CLASS_HID_20840] = 3677, + [BNXT_ULP_CLASS_HID_2b540] = 3678, + [BNXT_ULP_CLASS_HID_33e40] = 3679, + [BNXT_ULP_CLASS_HID_3ab40] = 3680, + [BNXT_ULP_CLASS_HID_253e0] = 3681, + [BNXT_ULP_CLASS_HID_2dce0] = 3682, + [BNXT_ULP_CLASS_HID_349e0] = 3683, + [BNXT_ULP_CLASS_HID_397d4] = 3684, + [BNXT_ULP_CLASS_HID_23f30] = 3685, + [BNXT_ULP_CLASS_HID_2a830] = 3686, + [BNXT_ULP_CLASS_HID_35530] = 3687, + [BNXT_ULP_CLASS_HID_3de30] = 3688, + [BNXT_ULP_CLASS_HID_23be4] = 3689, + [BNXT_ULP_CLASS_HID_2a4e4] = 3690, + [BNXT_ULP_CLASS_HID_351e4] = 3691, + [BNXT_ULP_CLASS_HID_3dae4] = 3692, + [BNXT_ULP_CLASS_HID_22cd4] = 3693, + [BNXT_ULP_CLASS_HID_2d9d4] = 3694, + [BNXT_ULP_CLASS_HID_342d4] = 3695, + [BNXT_ULP_CLASS_HID_39088] = 3696, + [BNXT_ULP_CLASS_HID_21928] = 3697, + [BNXT_ULP_CLASS_HID_28228] = 3698, + [BNXT_ULP_CLASS_HID_30f28] = 3699, + [BNXT_ULP_CLASS_HID_3b828] = 3700, + [BNXT_ULP_CLASS_HID_24384] = 3701, + [BNXT_ULP_CLASS_HID_29178] = 3702, + [BNXT_ULP_CLASS_HID_31a78] = 3703, + [BNXT_ULP_CLASS_HID_38778] = 3704, + [BNXT_ULP_CLASS_HID_25c78] = 3705, + [BNXT_ULP_CLASS_HID_2c978] = 3706, + [BNXT_ULP_CLASS_HID_3172c] = 3707, + [BNXT_ULP_CLASS_HID_3802c] = 3708, + [BNXT_ULP_CLASS_HID_2121c] = 3709, + [BNXT_ULP_CLASS_HID_29f1c] = 3710, + [BNXT_ULP_CLASS_HID_3081c] = 3711, + [BNXT_ULP_CLASS_HID_3b51c] = 3712, + [BNXT_ULP_CLASS_HID_24088] = 3713, + [BNXT_ULP_CLASS_HID_2cd88] = 3714, + [BNXT_ULP_CLASS_HID_31b7c] = 3715, + [BNXT_ULP_CLASS_HID_3847c] = 3716, + [BNXT_ULP_CLASS_HID_22fd8] = 3717, + [BNXT_ULP_CLASS_HID_2d8d8] = 3718, + [BNXT_ULP_CLASS_HID_345d8] = 3719, + [BNXT_ULP_CLASS_HID_3938c] = 3720, + [BNXT_ULP_CLASS_HID_2288c] = 3721, + [BNXT_ULP_CLASS_HID_2d58c] = 3722, + [BNXT_ULP_CLASS_HID_35e8c] = 3723, + [BNXT_ULP_CLASS_HID_3cb8c] = 3724, + [BNXT_ULP_CLASS_HID_25d7c] = 3725, + [BNXT_ULP_CLASS_HID_2c67c] = 3726, + [BNXT_ULP_CLASS_HID_31430] = 3727, + [BNXT_ULP_CLASS_HID_38130] = 3728, + [BNXT_ULP_CLASS_HID_209d0] = 3729, + [BNXT_ULP_CLASS_HID_2b2d0] = 3730, + [BNXT_ULP_CLASS_HID_33fd0] = 3731, + [BNXT_ULP_CLASS_HID_3a8d0] = 3732, + [BNXT_ULP_CLASS_HID_214e0] = 3733, + [BNXT_ULP_CLASS_HID_281e0] = 3734, + [BNXT_ULP_CLASS_HID_30ae0] = 3735, + [BNXT_ULP_CLASS_HID_3b7e0] = 3736, + [BNXT_ULP_CLASS_HID_211d4] = 3737, + [BNXT_ULP_CLASS_HID_29ad4] = 3738, + [BNXT_ULP_CLASS_HID_307d4] = 3739, + [BNXT_ULP_CLASS_HID_3b0d4] = 3740, + [BNXT_ULP_CLASS_HID_20284] = 3741, + [BNXT_ULP_CLASS_HID_28f84] = 3742, + [BNXT_ULP_CLASS_HID_33884] = 3743, + [BNXT_ULP_CLASS_HID_3a584] = 3744, + [BNXT_ULP_CLASS_HID_22a24] = 3745, + [BNXT_ULP_CLASS_HID_2d724] = 3746, + [BNXT_ULP_CLASS_HID_34024] = 3747, + [BNXT_ULP_CLASS_HID_3cd24] = 3748, + [BNXT_ULP_CLASS_HID_23974] = 3749, + [BNXT_ULP_CLASS_HID_2a274] = 3750, + [BNXT_ULP_CLASS_HID_32f74] = 3751, + [BNXT_ULP_CLASS_HID_3d874] = 3752, + [BNXT_ULP_CLASS_HID_23228] = 3753, + [BNXT_ULP_CLASS_HID_2bf28] = 3754, + [BNXT_ULP_CLASS_HID_32828] = 3755, + [BNXT_ULP_CLASS_HID_3d528] = 3756, + [BNXT_ULP_CLASS_HID_22718] = 3757, + [BNXT_ULP_CLASS_HID_2d018] = 3758, + [BNXT_ULP_CLASS_HID_35d18] = 3759, + [BNXT_ULP_CLASS_HID_3c618] = 3760, + [BNXT_ULP_CLASS_HID_2136c] = 3761, + [BNXT_ULP_CLASS_HID_29c6c] = 3762, + [BNXT_ULP_CLASS_HID_3096c] = 3763, + [BNXT_ULP_CLASS_HID_3b26c] = 3764, + [BNXT_ULP_CLASS_HID_25dc8] = 3765, + [BNXT_ULP_CLASS_HID_2c6c8] = 3766, + [BNXT_ULP_CLASS_HID_314bc] = 3767, + [BNXT_ULP_CLASS_HID_381bc] = 3768, + [BNXT_ULP_CLASS_HID_256bc] = 3769, + [BNXT_ULP_CLASS_HID_2c3bc] = 3770, + [BNXT_ULP_CLASS_HID_31170] = 3771, + [BNXT_ULP_CLASS_HID_39a70] = 3772, + [BNXT_ULP_CLASS_HID_24b6c] = 3773, + [BNXT_ULP_CLASS_HID_29920] = 3774, + [BNXT_ULP_CLASS_HID_30220] = 3775, + [BNXT_ULP_CLASS_HID_38f20] = 3776, + [BNXT_ULP_CLASS_HID_22f54] = 3777, + [BNXT_ULP_CLASS_HID_2d854] = 3778, + [BNXT_ULP_CLASS_HID_34554] = 3779, + [BNXT_ULP_CLASS_HID_39308] = 3780, + [BNXT_ULP_CLASS_HID_23a64] = 3781, + [BNXT_ULP_CLASS_HID_2a764] = 3782, + [BNXT_ULP_CLASS_HID_35064] = 3783, + [BNXT_ULP_CLASS_HID_3dd64] = 3784, + [BNXT_ULP_CLASS_HID_23758] = 3785, + [BNXT_ULP_CLASS_HID_2a058] = 3786, + [BNXT_ULP_CLASS_HID_32d58] = 3787, + [BNXT_ULP_CLASS_HID_3d658] = 3788, + [BNXT_ULP_CLASS_HID_22808] = 3789, + [BNXT_ULP_CLASS_HID_2d508] = 3790, + [BNXT_ULP_CLASS_HID_35e08] = 3791, + [BNXT_ULP_CLASS_HID_3cb08] = 3792, + [BNXT_ULP_CLASS_HID_2149c] = 3793, + [BNXT_ULP_CLASS_HID_2819c] = 3794, + [BNXT_ULP_CLASS_HID_30a9c] = 3795, + [BNXT_ULP_CLASS_HID_3b79c] = 3796, + [BNXT_ULP_CLASS_HID_25ef8] = 3797, + [BNXT_ULP_CLASS_HID_2cbf8] = 3798, + [BNXT_ULP_CLASS_HID_319ac] = 3799, + [BNXT_ULP_CLASS_HID_382ac] = 3800, + [BNXT_ULP_CLASS_HID_25bac] = 3801, + [BNXT_ULP_CLASS_HID_2c4ac] = 3802, + [BNXT_ULP_CLASS_HID_31260] = 3803, + [BNXT_ULP_CLASS_HID_39f60] = 3804, + [BNXT_ULP_CLASS_HID_21150] = 3805, + [BNXT_ULP_CLASS_HID_29a50] = 3806, + [BNXT_ULP_CLASS_HID_30750] = 3807, + [BNXT_ULP_CLASS_HID_3b050] = 3808, + [BNXT_ULP_CLASS_HID_238f0] = 3809, + [BNXT_ULP_CLASS_HID_2a5f0] = 3810, + [BNXT_ULP_CLASS_HID_32ef0] = 3811, + [BNXT_ULP_CLASS_HID_3dbf0] = 3812, + [BNXT_ULP_CLASS_HID_20400] = 3813, + [BNXT_ULP_CLASS_HID_2b100] = 3814, + [BNXT_ULP_CLASS_HID_33a00] = 3815, + [BNXT_ULP_CLASS_HID_3a700] = 3816, + [BNXT_ULP_CLASS_HID_200f4] = 3817, + [BNXT_ULP_CLASS_HID_28df4] = 3818, + [BNXT_ULP_CLASS_HID_336f4] = 3819, + [BNXT_ULP_CLASS_HID_3a3f4] = 3820, + [BNXT_ULP_CLASS_HID_235a4] = 3821, + [BNXT_ULP_CLASS_HID_2bea4] = 3822, + [BNXT_ULP_CLASS_HID_32ba4] = 3823, + [BNXT_ULP_CLASS_HID_3d4a4] = 3824, + [BNXT_ULP_CLASS_HID_25d44] = 3825, + [BNXT_ULP_CLASS_HID_2c644] = 3826, + [BNXT_ULP_CLASS_HID_31438] = 3827, + [BNXT_ULP_CLASS_HID_38138] = 3828, + [BNXT_ULP_CLASS_HID_22894] = 3829, + [BNXT_ULP_CLASS_HID_2d594] = 3830, + [BNXT_ULP_CLASS_HID_35e94] = 3831, + [BNXT_ULP_CLASS_HID_3cb94] = 3832, + [BNXT_ULP_CLASS_HID_22548] = 3833, + [BNXT_ULP_CLASS_HID_2ae48] = 3834, + [BNXT_ULP_CLASS_HID_35b48] = 3835, + [BNXT_ULP_CLASS_HID_3c448] = 3836, + [BNXT_ULP_CLASS_HID_25638] = 3837, + [BNXT_ULP_CLASS_HID_2c338] = 3838, + [BNXT_ULP_CLASS_HID_310ec] = 3839, + [BNXT_ULP_CLASS_HID_39dec] = 3840, + [BNXT_ULP_CLASS_HID_22998] = 3841, + [BNXT_ULP_CLASS_HID_2d298] = 3842, + [BNXT_ULP_CLASS_HID_35f98] = 3843, + [BNXT_ULP_CLASS_HID_3c898] = 3844, + [BNXT_ULP_CLASS_HID_234a8] = 3845, + [BNXT_ULP_CLASS_HID_2a1a8] = 3846, + [BNXT_ULP_CLASS_HID_32aa8] = 3847, + [BNXT_ULP_CLASS_HID_3d7a8] = 3848, + [BNXT_ULP_CLASS_HID_2319c] = 3849, + [BNXT_ULP_CLASS_HID_2ba9c] = 3850, + [BNXT_ULP_CLASS_HID_3279c] = 3851, + [BNXT_ULP_CLASS_HID_3d09c] = 3852, + [BNXT_ULP_CLASS_HID_2224c] = 3853, + [BNXT_ULP_CLASS_HID_2af4c] = 3854, + [BNXT_ULP_CLASS_HID_3584c] = 3855, + [BNXT_ULP_CLASS_HID_3c54c] = 3856, + [BNXT_ULP_CLASS_HID_24dec] = 3857, + [BNXT_ULP_CLASS_HID_29ba0] = 3858, + [BNXT_ULP_CLASS_HID_304a0] = 3859, + [BNXT_ULP_CLASS_HID_3b1a0] = 3860, + [BNXT_ULP_CLASS_HID_2593c] = 3861, + [BNXT_ULP_CLASS_HID_2c23c] = 3862, + [BNXT_ULP_CLASS_HID_313f0] = 3863, + [BNXT_ULP_CLASS_HID_39cf0] = 3864, + [BNXT_ULP_CLASS_HID_255f0] = 3865, + [BNXT_ULP_CLASS_HID_2def0] = 3866, + [BNXT_ULP_CLASS_HID_34bf0] = 3867, + [BNXT_ULP_CLASS_HID_399a4] = 3868, + [BNXT_ULP_CLASS_HID_246a0] = 3869, + [BNXT_ULP_CLASS_HID_29494] = 3870, + [BNXT_ULP_CLASS_HID_30194] = 3871, + [BNXT_ULP_CLASS_HID_38a94] = 3872, + [BNXT_ULP_CLASS_HID_23334] = 3873, + [BNXT_ULP_CLASS_HID_2bc34] = 3874, + [BNXT_ULP_CLASS_HID_32934] = 3875, + [BNXT_ULP_CLASS_HID_3d234] = 3876, + [BNXT_ULP_CLASS_HID_21e44] = 3877, + [BNXT_ULP_CLASS_HID_28b44] = 3878, + [BNXT_ULP_CLASS_HID_33444] = 3879, + [BNXT_ULP_CLASS_HID_3a144] = 3880, + [BNXT_ULP_CLASS_HID_21b38] = 3881, + [BNXT_ULP_CLASS_HID_28438] = 3882, + [BNXT_ULP_CLASS_HID_33138] = 3883, + [BNXT_ULP_CLASS_HID_3ba38] = 3884, + [BNXT_ULP_CLASS_HID_20fe8] = 3885, + [BNXT_ULP_CLASS_HID_2b8e8] = 3886, + [BNXT_ULP_CLASS_HID_325e8] = 3887, + [BNXT_ULP_CLASS_HID_3aee8] = 3888, + [BNXT_ULP_CLASS_HID_25788] = 3889, + [BNXT_ULP_CLASS_HID_2c088] = 3890, + [BNXT_ULP_CLASS_HID_34d88] = 3891, + [BNXT_ULP_CLASS_HID_39b7c] = 3892, + [BNXT_ULP_CLASS_HID_222d8] = 3893, + [BNXT_ULP_CLASS_HID_2afd8] = 3894, + [BNXT_ULP_CLASS_HID_358d8] = 3895, + [BNXT_ULP_CLASS_HID_3c5d8] = 3896, + [BNXT_ULP_CLASS_HID_23f8c] = 3897, + [BNXT_ULP_CLASS_HID_2a88c] = 3898, + [BNXT_ULP_CLASS_HID_3558c] = 3899, + [BNXT_ULP_CLASS_HID_3de8c] = 3900, + [BNXT_ULP_CLASS_HID_2507c] = 3901, + [BNXT_ULP_CLASS_HID_2dd7c] = 3902, + [BNXT_ULP_CLASS_HID_3467c] = 3903, + [BNXT_ULP_CLASS_HID_39430] = 3904, + [BNXT_ULP_CLASS_HID_223dc] = 3905, + [BNXT_ULP_CLASS_HID_2acdc] = 3906, + [BNXT_ULP_CLASS_HID_359dc] = 3907, + [BNXT_ULP_CLASS_HID_3c2dc] = 3908, + [BNXT_ULP_CLASS_HID_20eec] = 3909, + [BNXT_ULP_CLASS_HID_2bbec] = 3910, + [BNXT_ULP_CLASS_HID_324ec] = 3911, + [BNXT_ULP_CLASS_HID_3d1ec] = 3912, + [BNXT_ULP_CLASS_HID_20ba0] = 3913, + [BNXT_ULP_CLASS_HID_2b4a0] = 3914, + [BNXT_ULP_CLASS_HID_321a0] = 3915, + [BNXT_ULP_CLASS_HID_3aaa0] = 3916, + [BNXT_ULP_CLASS_HID_23c90] = 3917, + [BNXT_ULP_CLASS_HID_2a990] = 3918, + [BNXT_ULP_CLASS_HID_35290] = 3919, + [BNXT_ULP_CLASS_HID_3df90] = 3920, + [BNXT_ULP_CLASS_HID_24430] = 3921, + [BNXT_ULP_CLASS_HID_295e4] = 3922, + [BNXT_ULP_CLASS_HID_31ee4] = 3923, + [BNXT_ULP_CLASS_HID_38be4] = 3924, + [BNXT_ULP_CLASS_HID_25340] = 3925, + [BNXT_ULP_CLASS_HID_2dc40] = 3926, + [BNXT_ULP_CLASS_HID_34940] = 3927, + [BNXT_ULP_CLASS_HID_39734] = 3928, + [BNXT_ULP_CLASS_HID_22c34] = 3929, + [BNXT_ULP_CLASS_HID_2d934] = 3930, + [BNXT_ULP_CLASS_HID_34234] = 3931, + [BNXT_ULP_CLASS_HID_393e8] = 3932, + [BNXT_ULP_CLASS_HID_240e4] = 3933, + [BNXT_ULP_CLASS_HID_2cde4] = 3934, + [BNXT_ULP_CLASS_HID_31bd8] = 3935, + [BNXT_ULP_CLASS_HID_384d8] = 3936, + [BNXT_ULP_CLASS_HID_23de0] = 3937, + [BNXT_ULP_CLASS_HID_2a6e0] = 3938, + [BNXT_ULP_CLASS_HID_353e0] = 3939, + [BNXT_ULP_CLASS_HID_3dce0] = 3940, + [BNXT_ULP_CLASS_HID_20930] = 3941, + [BNXT_ULP_CLASS_HID_2b230] = 3942, + [BNXT_ULP_CLASS_HID_33f30] = 3943, + [BNXT_ULP_CLASS_HID_3a830] = 3944, + [BNXT_ULP_CLASS_HID_205e4] = 3945, + [BNXT_ULP_CLASS_HID_28ee4] = 3946, + [BNXT_ULP_CLASS_HID_33be4] = 3947, + [BNXT_ULP_CLASS_HID_3a4e4] = 3948, + [BNXT_ULP_CLASS_HID_236d4] = 3949, + [BNXT_ULP_CLASS_HID_2a3d4] = 3950, + [BNXT_ULP_CLASS_HID_32cd4] = 3951, + [BNXT_ULP_CLASS_HID_3d9d4] = 3952, + [BNXT_ULP_CLASS_HID_25e74] = 3953, + [BNXT_ULP_CLASS_HID_2cb74] = 3954, + [BNXT_ULP_CLASS_HID_31928] = 3955, + [BNXT_ULP_CLASS_HID_38228] = 3956, + [BNXT_ULP_CLASS_HID_22d84] = 3957, + [BNXT_ULP_CLASS_HID_2d684] = 3958, + [BNXT_ULP_CLASS_HID_34384] = 3959, + [BNXT_ULP_CLASS_HID_39178] = 3960, + [BNXT_ULP_CLASS_HID_22678] = 3961, + [BNXT_ULP_CLASS_HID_2d378] = 3962, + [BNXT_ULP_CLASS_HID_35c78] = 3963, + [BNXT_ULP_CLASS_HID_3c978] = 3964, + [BNXT_ULP_CLASS_HID_25b28] = 3965, + [BNXT_ULP_CLASS_HID_2c428] = 3966, + [BNXT_ULP_CLASS_HID_3121c] = 3967, + [BNXT_ULP_CLASS_HID_39f1c] = 3968, + [BNXT_ULP_CLASS_HID_3488] = 3969, + [BNXT_ULP_CLASS_HID_3a44] = 3970, + [BNXT_ULP_CLASS_HID_0994] = 3971, + [BNXT_ULP_CLASS_HID_5ed8] = 3972, + [BNXT_ULP_CLASS_HID_2de8] = 3973, + [BNXT_ULP_CLASS_HID_07e0] = 3974, + [BNXT_ULP_CLASS_HID_1330] = 3975, + [BNXT_ULP_CLASS_HID_2874] = 3976, + [BNXT_ULP_CLASS_HID_3784] = 3977, + [BNXT_ULP_CLASS_HID_03d8] = 3978, + [BNXT_ULP_CLASS_HID_591c] = 3979, + [BNXT_ULP_CLASS_HID_242c] = 3980, + [BNXT_ULP_CLASS_HID_1e24] = 3981, + [BNXT_ULP_CLASS_HID_4880] = 3982, + [BNXT_ULP_CLASS_HID_22b8] = 3983, + [BNXT_ULP_CLASS_HID_31c8] = 3984 }; /* Array for the proto matcher list */ @@ -4312,6 +4432,39 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [27] = { + .class_hid = BNXT_ULP_CLASS_HID_054d, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 7, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [28] = { + .class_hid = BNXT_ULP_CLASS_HID_5bdd, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 7, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [29] = { .class_hid = BNXT_ULP_CLASS_HID_26f1, .class_tid = 1, .hdr_sig_id = 1, @@ -4329,7 +4482,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [28] = { + [30] = { .class_hid = BNXT_ULP_CLASS_HID_13cf1, .class_tid = 1, .hdr_sig_id = 1, @@ -4348,7 +4501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [29] = { + [31] = { .class_hid = BNXT_ULP_CLASS_HID_252f1, .class_tid = 1, .hdr_sig_id = 1, @@ -4367,7 +4520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [30] = { + [32] = { .class_hid = BNXT_ULP_CLASS_HID_30c25, .class_tid = 1, .hdr_sig_id = 1, @@ -4387,7 +4540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [31] = { + [33] = { .class_hid = BNXT_ULP_CLASS_HID_0051, .class_tid = 1, .hdr_sig_id = 1, @@ -4406,7 +4559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [32] = { + [34] = { .class_hid = BNXT_ULP_CLASS_HID_11651, .class_tid = 1, .hdr_sig_id = 1, @@ -4426,7 +4579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [33] = { + [35] = { .class_hid = BNXT_ULP_CLASS_HID_22c51, .class_tid = 1, .hdr_sig_id = 1, @@ -4446,7 +4599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [34] = { + [36] = { .class_hid = BNXT_ULP_CLASS_HID_34251, .class_tid = 1, .hdr_sig_id = 1, @@ -4467,7 +4620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [35] = { + [37] = { .class_hid = BNXT_ULP_CLASS_HID_5385, .class_tid = 1, .hdr_sig_id = 1, @@ -4487,7 +4640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [36] = { + [38] = { .class_hid = BNXT_ULP_CLASS_HID_10cc9, .class_tid = 1, .hdr_sig_id = 1, @@ -4508,7 +4661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [37] = { + [39] = { .class_hid = BNXT_ULP_CLASS_HID_222c9, .class_tid = 1, .hdr_sig_id = 1, @@ -4529,7 +4682,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [38] = { + [40] = { .class_hid = BNXT_ULP_CLASS_HID_338c9, .class_tid = 1, .hdr_sig_id = 1, @@ -4551,7 +4704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [39] = { + [41] = { .class_hid = BNXT_ULP_CLASS_HID_1d69, .class_tid = 1, .hdr_sig_id = 1, @@ -4570,7 +4723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [40] = { + [42] = { .class_hid = BNXT_ULP_CLASS_HID_13369, .class_tid = 1, .hdr_sig_id = 1, @@ -4590,7 +4743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [41] = { + [43] = { .class_hid = BNXT_ULP_CLASS_HID_24969, .class_tid = 1, .hdr_sig_id = 1, @@ -4610,7 +4763,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [42] = { + [44] = { .class_hid = BNXT_ULP_CLASS_HID_3025d, .class_tid = 1, .hdr_sig_id = 1, @@ -4631,7 +4784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [43] = { + [45] = { .class_hid = BNXT_ULP_CLASS_HID_20b5, .class_tid = 1, .hdr_sig_id = 1, @@ -4648,7 +4801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [44] = { + [46] = { .class_hid = BNXT_ULP_CLASS_HID_136b5, .class_tid = 1, .hdr_sig_id = 1, @@ -4666,7 +4819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [45] = { + [47] = { .class_hid = BNXT_ULP_CLASS_HID_24cb5, .class_tid = 1, .hdr_sig_id = 1, @@ -4684,7 +4837,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [46] = { + [48] = { .class_hid = BNXT_ULP_CLASS_HID_305f9, .class_tid = 1, .hdr_sig_id = 1, @@ -4703,7 +4856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [47] = { + [49] = { .class_hid = BNXT_ULP_CLASS_HID_5721, .class_tid = 1, .hdr_sig_id = 1, @@ -4721,7 +4874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [48] = { + [50] = { .class_hid = BNXT_ULP_CLASS_HID_11015, .class_tid = 1, .hdr_sig_id = 1, @@ -4740,7 +4893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [49] = { + [51] = { .class_hid = BNXT_ULP_CLASS_HID_22615, .class_tid = 1, .hdr_sig_id = 1, @@ -4759,7 +4912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [50] = { + [52] = { .class_hid = BNXT_ULP_CLASS_HID_33c15, .class_tid = 1, .hdr_sig_id = 1, @@ -4779,7 +4932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [51] = { + [53] = { .class_hid = BNXT_ULP_CLASS_HID_4d59, .class_tid = 1, .hdr_sig_id = 1, @@ -4798,7 +4951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [52] = { + [54] = { .class_hid = BNXT_ULP_CLASS_HID_1068d, .class_tid = 1, .hdr_sig_id = 1, @@ -4818,7 +4971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [53] = { + [55] = { .class_hid = BNXT_ULP_CLASS_HID_21c8d, .class_tid = 1, .hdr_sig_id = 1, @@ -4838,7 +4991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [54] = { + [56] = { .class_hid = BNXT_ULP_CLASS_HID_3328d, .class_tid = 1, .hdr_sig_id = 1, @@ -4859,7 +5012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [55] = { + [57] = { .class_hid = BNXT_ULP_CLASS_HID_172d, .class_tid = 1, .hdr_sig_id = 1, @@ -4877,7 +5030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [56] = { + [58] = { .class_hid = BNXT_ULP_CLASS_HID_12d2d, .class_tid = 1, .hdr_sig_id = 1, @@ -4896,7 +5049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [57] = { + [59] = { .class_hid = BNXT_ULP_CLASS_HID_2432d, .class_tid = 1, .hdr_sig_id = 1, @@ -4915,7 +5068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [58] = { + [60] = { .class_hid = BNXT_ULP_CLASS_HID_3592d, .class_tid = 1, .hdr_sig_id = 1, @@ -4935,7 +5088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [59] = { + [61] = { .class_hid = BNXT_ULP_CLASS_HID_1a49, .class_tid = 1, .hdr_sig_id = 1, @@ -4952,7 +5105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [60] = { + [62] = { .class_hid = BNXT_ULP_CLASS_HID_13049, .class_tid = 1, .hdr_sig_id = 1, @@ -4970,7 +5123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [61] = { + [63] = { .class_hid = BNXT_ULP_CLASS_HID_24649, .class_tid = 1, .hdr_sig_id = 1, @@ -4988,7 +5141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [62] = { + [64] = { .class_hid = BNXT_ULP_CLASS_HID_35c49, .class_tid = 1, .hdr_sig_id = 1, @@ -5007,7 +5160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [63] = { + [65] = { .class_hid = BNXT_ULP_CLASS_HID_50e5, .class_tid = 1, .hdr_sig_id = 1, @@ -5025,7 +5178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [64] = { + [66] = { .class_hid = BNXT_ULP_CLASS_HID_10a29, .class_tid = 1, .hdr_sig_id = 1, @@ -5044,7 +5197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [65] = { + [67] = { .class_hid = BNXT_ULP_CLASS_HID_22029, .class_tid = 1, .hdr_sig_id = 1, @@ -5063,7 +5216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [66] = { + [68] = { .class_hid = BNXT_ULP_CLASS_HID_33629, .class_tid = 1, .hdr_sig_id = 1, @@ -5083,7 +5236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [67] = { + [69] = { .class_hid = BNXT_ULP_CLASS_HID_471d, .class_tid = 1, .hdr_sig_id = 1, @@ -5102,7 +5255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [68] = { + [70] = { .class_hid = BNXT_ULP_CLASS_HID_10041, .class_tid = 1, .hdr_sig_id = 1, @@ -5122,7 +5275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [69] = { + [71] = { .class_hid = BNXT_ULP_CLASS_HID_21641, .class_tid = 1, .hdr_sig_id = 1, @@ -5142,7 +5295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [70] = { + [72] = { .class_hid = BNXT_ULP_CLASS_HID_32c41, .class_tid = 1, .hdr_sig_id = 1, @@ -5163,7 +5316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [71] = { + [73] = { .class_hid = BNXT_ULP_CLASS_HID_10e1, .class_tid = 1, .hdr_sig_id = 1, @@ -5181,7 +5334,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [72] = { + [74] = { .class_hid = BNXT_ULP_CLASS_HID_126e1, .class_tid = 1, .hdr_sig_id = 1, @@ -5200,7 +5353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [73] = { + [75] = { .class_hid = BNXT_ULP_CLASS_HID_23ce1, .class_tid = 1, .hdr_sig_id = 1, @@ -5219,7 +5372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [74] = { + [76] = { .class_hid = BNXT_ULP_CLASS_HID_352e1, .class_tid = 1, .hdr_sig_id = 1, @@ -5239,7 +5392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [75] = { + [77] = { .class_hid = BNXT_ULP_CLASS_HID_140d, .class_tid = 1, .hdr_sig_id = 1, @@ -5255,7 +5408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [76] = { + [78] = { .class_hid = BNXT_ULP_CLASS_HID_12a0d, .class_tid = 1, .hdr_sig_id = 1, @@ -5272,7 +5425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [77] = { + [79] = { .class_hid = BNXT_ULP_CLASS_HID_2400d, .class_tid = 1, .hdr_sig_id = 1, @@ -5289,7 +5442,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [78] = { + [80] = { .class_hid = BNXT_ULP_CLASS_HID_3560d, .class_tid = 1, .hdr_sig_id = 1, @@ -5307,7 +5460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [79] = { + [81] = { .class_hid = BNXT_ULP_CLASS_HID_4ab9, .class_tid = 1, .hdr_sig_id = 1, @@ -5324,7 +5477,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [80] = { + [82] = { .class_hid = BNXT_ULP_CLASS_HID_103ed, .class_tid = 1, .hdr_sig_id = 1, @@ -5342,7 +5495,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [81] = { + [83] = { .class_hid = BNXT_ULP_CLASS_HID_219ed, .class_tid = 1, .hdr_sig_id = 1, @@ -5360,7 +5513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [82] = { + [84] = { .class_hid = BNXT_ULP_CLASS_HID_32fed, .class_tid = 1, .hdr_sig_id = 1, @@ -5379,7 +5532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [83] = { + [85] = { .class_hid = BNXT_ULP_CLASS_HID_40d1, .class_tid = 1, .hdr_sig_id = 1, @@ -5397,7 +5550,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [84] = { + [86] = { .class_hid = BNXT_ULP_CLASS_HID_156d1, .class_tid = 1, .hdr_sig_id = 1, @@ -5416,7 +5569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [85] = { + [87] = { .class_hid = BNXT_ULP_CLASS_HID_21005, .class_tid = 1, .hdr_sig_id = 1, @@ -5435,7 +5588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [86] = { + [88] = { .class_hid = BNXT_ULP_CLASS_HID_32605, .class_tid = 1, .hdr_sig_id = 1, @@ -5455,7 +5608,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [87] = { + [89] = { .class_hid = BNXT_ULP_CLASS_HID_0aa5, .class_tid = 1, .hdr_sig_id = 1, @@ -5472,7 +5625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [88] = { + [90] = { .class_hid = BNXT_ULP_CLASS_HID_120a5, .class_tid = 1, .hdr_sig_id = 1, @@ -5490,7 +5643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [89] = { + [91] = { .class_hid = BNXT_ULP_CLASS_HID_236a5, .class_tid = 1, .hdr_sig_id = 1, @@ -5508,7 +5661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [90] = { + [92] = { .class_hid = BNXT_ULP_CLASS_HID_34ca5, .class_tid = 1, .hdr_sig_id = 1, @@ -5527,7 +5680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [91] = { + [93] = { .class_hid = BNXT_ULP_CLASS_HID_0159, .class_tid = 1, .hdr_sig_id = 1, @@ -5543,7 +5696,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [92] = { + [94] = { .class_hid = BNXT_ULP_CLASS_HID_11759, .class_tid = 1, .hdr_sig_id = 1, @@ -5560,7 +5713,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [93] = { + [95] = { .class_hid = BNXT_ULP_CLASS_HID_22d59, .class_tid = 1, .hdr_sig_id = 1, @@ -5577,7 +5730,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [94] = { + [96] = { .class_hid = BNXT_ULP_CLASS_HID_34359, .class_tid = 1, .hdr_sig_id = 1, @@ -5595,7 +5748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [95] = { + [97] = { .class_hid = BNXT_ULP_CLASS_HID_37f5, .class_tid = 1, .hdr_sig_id = 1, @@ -5612,7 +5765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [96] = { + [98] = { .class_hid = BNXT_ULP_CLASS_HID_14df5, .class_tid = 1, .hdr_sig_id = 1, @@ -5630,7 +5783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [97] = { + [99] = { .class_hid = BNXT_ULP_CLASS_HID_20739, .class_tid = 1, .hdr_sig_id = 1, @@ -5648,7 +5801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [98] = { + [100] = { .class_hid = BNXT_ULP_CLASS_HID_31d39, .class_tid = 1, .hdr_sig_id = 1, @@ -5667,7 +5820,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [99] = { + [101] = { .class_hid = BNXT_ULP_CLASS_HID_2e6d, .class_tid = 1, .hdr_sig_id = 1, @@ -5685,7 +5838,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [100] = { + [102] = { .class_hid = BNXT_ULP_CLASS_HID_1446d, .class_tid = 1, .hdr_sig_id = 1, @@ -5704,7 +5857,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [101] = { + [103] = { .class_hid = BNXT_ULP_CLASS_HID_25a6d, .class_tid = 1, .hdr_sig_id = 1, @@ -5723,7 +5876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [102] = { + [104] = { .class_hid = BNXT_ULP_CLASS_HID_31351, .class_tid = 1, .hdr_sig_id = 1, @@ -5743,7 +5896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [103] = { + [105] = { .class_hid = BNXT_ULP_CLASS_HID_548d, .class_tid = 1, .hdr_sig_id = 1, @@ -5760,7 +5913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [104] = { + [106] = { .class_hid = BNXT_ULP_CLASS_HID_10df1, .class_tid = 1, .hdr_sig_id = 1, @@ -5778,7 +5931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [105] = { + [107] = { .class_hid = BNXT_ULP_CLASS_HID_223f1, .class_tid = 1, .hdr_sig_id = 1, @@ -5796,7 +5949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [106] = { + [108] = { .class_hid = BNXT_ULP_CLASS_HID_339f1, .class_tid = 1, .hdr_sig_id = 1, @@ -5815,7 +5968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [107] = { + [109] = { .class_hid = BNXT_ULP_CLASS_HID_5829, .class_tid = 1, .hdr_sig_id = 1, @@ -5830,7 +5983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [108] = { + [110] = { .class_hid = BNXT_ULP_CLASS_HID_1111d, .class_tid = 1, .hdr_sig_id = 1, @@ -5846,7 +5999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [109] = { + [111] = { .class_hid = BNXT_ULP_CLASS_HID_2271d, .class_tid = 1, .hdr_sig_id = 1, @@ -5862,7 +6015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [110] = { + [112] = { .class_hid = BNXT_ULP_CLASS_HID_33d1d, .class_tid = 1, .hdr_sig_id = 1, @@ -5879,7 +6032,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [111] = { + [113] = { .class_hid = BNXT_ULP_CLASS_HID_3189, .class_tid = 1, .hdr_sig_id = 1, @@ -5895,7 +6048,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [112] = { + [114] = { .class_hid = BNXT_ULP_CLASS_HID_14789, .class_tid = 1, .hdr_sig_id = 1, @@ -5912,7 +6065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [113] = { + [115] = { .class_hid = BNXT_ULP_CLASS_HID_200fd, .class_tid = 1, .hdr_sig_id = 1, @@ -5929,7 +6082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [114] = { + [116] = { .class_hid = BNXT_ULP_CLASS_HID_316fd, .class_tid = 1, .hdr_sig_id = 1, @@ -5947,7 +6100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [115] = { + [117] = { .class_hid = BNXT_ULP_CLASS_HID_2821, .class_tid = 1, .hdr_sig_id = 1, @@ -5964,7 +6117,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [116] = { + [118] = { .class_hid = BNXT_ULP_CLASS_HID_13e21, .class_tid = 1, .hdr_sig_id = 1, @@ -5982,7 +6135,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [117] = { + [119] = { .class_hid = BNXT_ULP_CLASS_HID_25421, .class_tid = 1, .hdr_sig_id = 1, @@ -6000,7 +6153,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [118] = { + [120] = { .class_hid = BNXT_ULP_CLASS_HID_30d15, .class_tid = 1, .hdr_sig_id = 1, @@ -6019,7 +6172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [119] = { + [121] = { .class_hid = BNXT_ULP_CLASS_HID_4e41, .class_tid = 1, .hdr_sig_id = 1, @@ -6035,7 +6188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [120] = { + [122] = { .class_hid = BNXT_ULP_CLASS_HID_107b5, .class_tid = 1, .hdr_sig_id = 1, @@ -6052,7 +6205,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [121] = { + [123] = { .class_hid = BNXT_ULP_CLASS_HID_21db5, .class_tid = 1, .hdr_sig_id = 1, @@ -6069,7 +6222,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [122] = { + [124] = { .class_hid = BNXT_ULP_CLASS_HID_333b5, .class_tid = 1, .hdr_sig_id = 1, @@ -6087,7 +6240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [123] = { + [125] = { .class_hid = BNXT_ULP_CLASS_HID_2541, .class_tid = 1, .hdr_sig_id = 1, @@ -6103,7 +6256,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [124] = { + [126] = { .class_hid = BNXT_ULP_CLASS_HID_2b8d, .class_tid = 1, .hdr_sig_id = 1, @@ -6120,7 +6273,42 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [125] = { + [127] = { + .class_hid = BNXT_ULP_CLASS_HID_056d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [128] = { + .class_hid = BNXT_ULP_CLASS_HID_5bfd, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 25, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [129] = { .class_hid = BNXT_ULP_CLASS_HID_2691, .class_tid = 1, .hdr_sig_id = 2, @@ -6138,7 +6326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [126] = { + [130] = { .class_hid = BNXT_ULP_CLASS_HID_13c91, .class_tid = 1, .hdr_sig_id = 2, @@ -6157,7 +6345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [127] = { + [131] = { .class_hid = BNXT_ULP_CLASS_HID_25291, .class_tid = 1, .hdr_sig_id = 2, @@ -6176,7 +6364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [128] = { + [132] = { .class_hid = BNXT_ULP_CLASS_HID_30c45, .class_tid = 1, .hdr_sig_id = 2, @@ -6196,7 +6384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [129] = { + [133] = { .class_hid = BNXT_ULP_CLASS_HID_0031, .class_tid = 1, .hdr_sig_id = 2, @@ -6215,7 +6403,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [130] = { + [134] = { .class_hid = BNXT_ULP_CLASS_HID_11631, .class_tid = 1, .hdr_sig_id = 2, @@ -6235,7 +6423,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [131] = { + [135] = { .class_hid = BNXT_ULP_CLASS_HID_22c31, .class_tid = 1, .hdr_sig_id = 2, @@ -6255,7 +6443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [132] = { + [136] = { .class_hid = BNXT_ULP_CLASS_HID_34231, .class_tid = 1, .hdr_sig_id = 2, @@ -6276,7 +6464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [133] = { + [137] = { .class_hid = BNXT_ULP_CLASS_HID_53e5, .class_tid = 1, .hdr_sig_id = 2, @@ -6296,7 +6484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [134] = { + [138] = { .class_hid = BNXT_ULP_CLASS_HID_10ca9, .class_tid = 1, .hdr_sig_id = 2, @@ -6317,7 +6505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [135] = { + [139] = { .class_hid = BNXT_ULP_CLASS_HID_222a9, .class_tid = 1, .hdr_sig_id = 2, @@ -6338,7 +6526,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [136] = { + [140] = { .class_hid = BNXT_ULP_CLASS_HID_338a9, .class_tid = 1, .hdr_sig_id = 2, @@ -6360,7 +6548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [137] = { + [141] = { .class_hid = BNXT_ULP_CLASS_HID_1d09, .class_tid = 1, .hdr_sig_id = 2, @@ -6379,7 +6567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [138] = { + [142] = { .class_hid = BNXT_ULP_CLASS_HID_13309, .class_tid = 1, .hdr_sig_id = 2, @@ -6399,7 +6587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [139] = { + [143] = { .class_hid = BNXT_ULP_CLASS_HID_24909, .class_tid = 1, .hdr_sig_id = 2, @@ -6419,7 +6607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [140] = { + [144] = { .class_hid = BNXT_ULP_CLASS_HID_3023d, .class_tid = 1, .hdr_sig_id = 2, @@ -6440,7 +6628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [141] = { + [145] = { .class_hid = BNXT_ULP_CLASS_HID_20d5, .class_tid = 1, .hdr_sig_id = 2, @@ -6457,7 +6645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [142] = { + [146] = { .class_hid = BNXT_ULP_CLASS_HID_136d5, .class_tid = 1, .hdr_sig_id = 2, @@ -6475,7 +6663,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [143] = { + [147] = { .class_hid = BNXT_ULP_CLASS_HID_24cd5, .class_tid = 1, .hdr_sig_id = 2, @@ -6493,7 +6681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [144] = { + [148] = { .class_hid = BNXT_ULP_CLASS_HID_30599, .class_tid = 1, .hdr_sig_id = 2, @@ -6512,7 +6700,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [145] = { + [149] = { .class_hid = BNXT_ULP_CLASS_HID_5741, .class_tid = 1, .hdr_sig_id = 2, @@ -6530,7 +6718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [146] = { + [150] = { .class_hid = BNXT_ULP_CLASS_HID_11075, .class_tid = 1, .hdr_sig_id = 2, @@ -6549,7 +6737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [147] = { + [151] = { .class_hid = BNXT_ULP_CLASS_HID_22675, .class_tid = 1, .hdr_sig_id = 2, @@ -6568,7 +6756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [148] = { + [152] = { .class_hid = BNXT_ULP_CLASS_HID_33c75, .class_tid = 1, .hdr_sig_id = 2, @@ -6588,7 +6776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [149] = { + [153] = { .class_hid = BNXT_ULP_CLASS_HID_4d39, .class_tid = 1, .hdr_sig_id = 2, @@ -6607,7 +6795,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [150] = { + [154] = { .class_hid = BNXT_ULP_CLASS_HID_106ed, .class_tid = 1, .hdr_sig_id = 2, @@ -6627,7 +6815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [151] = { + [155] = { .class_hid = BNXT_ULP_CLASS_HID_21ced, .class_tid = 1, .hdr_sig_id = 2, @@ -6647,7 +6835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [152] = { + [156] = { .class_hid = BNXT_ULP_CLASS_HID_332ed, .class_tid = 1, .hdr_sig_id = 2, @@ -6668,7 +6856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [153] = { + [157] = { .class_hid = BNXT_ULP_CLASS_HID_174d, .class_tid = 1, .hdr_sig_id = 2, @@ -6686,7 +6874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [154] = { + [158] = { .class_hid = BNXT_ULP_CLASS_HID_12d4d, .class_tid = 1, .hdr_sig_id = 2, @@ -6705,7 +6893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [155] = { + [159] = { .class_hid = BNXT_ULP_CLASS_HID_2434d, .class_tid = 1, .hdr_sig_id = 2, @@ -6724,7 +6912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [156] = { + [160] = { .class_hid = BNXT_ULP_CLASS_HID_3594d, .class_tid = 1, .hdr_sig_id = 2, @@ -6744,7 +6932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [157] = { + [161] = { .class_hid = BNXT_ULP_CLASS_HID_1a29, .class_tid = 1, .hdr_sig_id = 2, @@ -6761,7 +6949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [158] = { + [162] = { .class_hid = BNXT_ULP_CLASS_HID_13029, .class_tid = 1, .hdr_sig_id = 2, @@ -6779,7 +6967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [159] = { + [163] = { .class_hid = BNXT_ULP_CLASS_HID_24629, .class_tid = 1, .hdr_sig_id = 2, @@ -6797,7 +6985,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [160] = { + [164] = { .class_hid = BNXT_ULP_CLASS_HID_35c29, .class_tid = 1, .hdr_sig_id = 2, @@ -6816,7 +7004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [161] = { + [165] = { .class_hid = BNXT_ULP_CLASS_HID_5085, .class_tid = 1, .hdr_sig_id = 2, @@ -6834,7 +7022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [162] = { + [166] = { .class_hid = BNXT_ULP_CLASS_HID_10a49, .class_tid = 1, .hdr_sig_id = 2, @@ -6853,7 +7041,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [163] = { + [167] = { .class_hid = BNXT_ULP_CLASS_HID_22049, .class_tid = 1, .hdr_sig_id = 2, @@ -6872,7 +7060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [164] = { + [168] = { .class_hid = BNXT_ULP_CLASS_HID_33649, .class_tid = 1, .hdr_sig_id = 2, @@ -6892,7 +7080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [165] = { + [169] = { .class_hid = BNXT_ULP_CLASS_HID_477d, .class_tid = 1, .hdr_sig_id = 2, @@ -6911,7 +7099,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [166] = { + [170] = { .class_hid = BNXT_ULP_CLASS_HID_10021, .class_tid = 1, .hdr_sig_id = 2, @@ -6931,7 +7119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [167] = { + [171] = { .class_hid = BNXT_ULP_CLASS_HID_21621, .class_tid = 1, .hdr_sig_id = 2, @@ -6951,7 +7139,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [168] = { + [172] = { .class_hid = BNXT_ULP_CLASS_HID_32c21, .class_tid = 1, .hdr_sig_id = 2, @@ -6972,7 +7160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [169] = { + [173] = { .class_hid = BNXT_ULP_CLASS_HID_1081, .class_tid = 1, .hdr_sig_id = 2, @@ -6990,7 +7178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [170] = { + [174] = { .class_hid = BNXT_ULP_CLASS_HID_12681, .class_tid = 1, .hdr_sig_id = 2, @@ -7009,7 +7197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [171] = { + [175] = { .class_hid = BNXT_ULP_CLASS_HID_23c81, .class_tid = 1, .hdr_sig_id = 2, @@ -7028,7 +7216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [172] = { + [176] = { .class_hid = BNXT_ULP_CLASS_HID_35281, .class_tid = 1, .hdr_sig_id = 2, @@ -7048,7 +7236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [173] = { + [177] = { .class_hid = BNXT_ULP_CLASS_HID_146d, .class_tid = 1, .hdr_sig_id = 2, @@ -7064,7 +7252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [174] = { + [178] = { .class_hid = BNXT_ULP_CLASS_HID_12a6d, .class_tid = 1, .hdr_sig_id = 2, @@ -7081,7 +7269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [175] = { + [179] = { .class_hid = BNXT_ULP_CLASS_HID_2406d, .class_tid = 1, .hdr_sig_id = 2, @@ -7098,7 +7286,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [176] = { + [180] = { .class_hid = BNXT_ULP_CLASS_HID_3566d, .class_tid = 1, .hdr_sig_id = 2, @@ -7116,7 +7304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [177] = { + [181] = { .class_hid = BNXT_ULP_CLASS_HID_4ad9, .class_tid = 1, .hdr_sig_id = 2, @@ -7133,7 +7321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [178] = { + [182] = { .class_hid = BNXT_ULP_CLASS_HID_1038d, .class_tid = 1, .hdr_sig_id = 2, @@ -7151,7 +7339,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [179] = { + [183] = { .class_hid = BNXT_ULP_CLASS_HID_2198d, .class_tid = 1, .hdr_sig_id = 2, @@ -7169,7 +7357,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [180] = { + [184] = { .class_hid = BNXT_ULP_CLASS_HID_32f8d, .class_tid = 1, .hdr_sig_id = 2, @@ -7188,7 +7376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [181] = { + [185] = { .class_hid = BNXT_ULP_CLASS_HID_40b1, .class_tid = 1, .hdr_sig_id = 2, @@ -7206,7 +7394,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [182] = { + [186] = { .class_hid = BNXT_ULP_CLASS_HID_156b1, .class_tid = 1, .hdr_sig_id = 2, @@ -7225,7 +7413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [183] = { + [187] = { .class_hid = BNXT_ULP_CLASS_HID_21065, .class_tid = 1, .hdr_sig_id = 2, @@ -7244,7 +7432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [184] = { + [188] = { .class_hid = BNXT_ULP_CLASS_HID_32665, .class_tid = 1, .hdr_sig_id = 2, @@ -7264,7 +7452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [185] = { + [189] = { .class_hid = BNXT_ULP_CLASS_HID_0ac5, .class_tid = 1, .hdr_sig_id = 2, @@ -7281,7 +7469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [186] = { + [190] = { .class_hid = BNXT_ULP_CLASS_HID_120c5, .class_tid = 1, .hdr_sig_id = 2, @@ -7299,7 +7487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [187] = { + [191] = { .class_hid = BNXT_ULP_CLASS_HID_236c5, .class_tid = 1, .hdr_sig_id = 2, @@ -7317,7 +7505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [188] = { + [192] = { .class_hid = BNXT_ULP_CLASS_HID_34cc5, .class_tid = 1, .hdr_sig_id = 2, @@ -7336,7 +7524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [189] = { + [193] = { .class_hid = BNXT_ULP_CLASS_HID_0139, .class_tid = 1, .hdr_sig_id = 2, @@ -7352,7 +7540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [190] = { + [194] = { .class_hid = BNXT_ULP_CLASS_HID_11739, .class_tid = 1, .hdr_sig_id = 2, @@ -7369,7 +7557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [191] = { + [195] = { .class_hid = BNXT_ULP_CLASS_HID_22d39, .class_tid = 1, .hdr_sig_id = 2, @@ -7386,7 +7574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [192] = { + [196] = { .class_hid = BNXT_ULP_CLASS_HID_34339, .class_tid = 1, .hdr_sig_id = 2, @@ -7404,7 +7592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [193] = { + [197] = { .class_hid = BNXT_ULP_CLASS_HID_3795, .class_tid = 1, .hdr_sig_id = 2, @@ -7421,7 +7609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [194] = { + [198] = { .class_hid = BNXT_ULP_CLASS_HID_14d95, .class_tid = 1, .hdr_sig_id = 2, @@ -7439,7 +7627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [195] = { + [199] = { .class_hid = BNXT_ULP_CLASS_HID_20759, .class_tid = 1, .hdr_sig_id = 2, @@ -7457,7 +7645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [196] = { + [200] = { .class_hid = BNXT_ULP_CLASS_HID_31d59, .class_tid = 1, .hdr_sig_id = 2, @@ -7476,7 +7664,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [197] = { + [201] = { .class_hid = BNXT_ULP_CLASS_HID_2e0d, .class_tid = 1, .hdr_sig_id = 2, @@ -7494,7 +7682,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [198] = { + [202] = { .class_hid = BNXT_ULP_CLASS_HID_1440d, .class_tid = 1, .hdr_sig_id = 2, @@ -7513,7 +7701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [199] = { + [203] = { .class_hid = BNXT_ULP_CLASS_HID_25a0d, .class_tid = 1, .hdr_sig_id = 2, @@ -7532,7 +7720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [200] = { + [204] = { .class_hid = BNXT_ULP_CLASS_HID_31331, .class_tid = 1, .hdr_sig_id = 2, @@ -7552,7 +7740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [201] = { + [205] = { .class_hid = BNXT_ULP_CLASS_HID_54ed, .class_tid = 1, .hdr_sig_id = 2, @@ -7569,7 +7757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [202] = { + [206] = { .class_hid = BNXT_ULP_CLASS_HID_10d91, .class_tid = 1, .hdr_sig_id = 2, @@ -7587,7 +7775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [203] = { + [207] = { .class_hid = BNXT_ULP_CLASS_HID_22391, .class_tid = 1, .hdr_sig_id = 2, @@ -7605,7 +7793,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [204] = { + [208] = { .class_hid = BNXT_ULP_CLASS_HID_33991, .class_tid = 1, .hdr_sig_id = 2, @@ -7624,7 +7812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [205] = { + [209] = { .class_hid = BNXT_ULP_CLASS_HID_5849, .class_tid = 1, .hdr_sig_id = 2, @@ -7639,7 +7827,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [206] = { + [210] = { .class_hid = BNXT_ULP_CLASS_HID_1117d, .class_tid = 1, .hdr_sig_id = 2, @@ -7655,7 +7843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [207] = { + [211] = { .class_hid = BNXT_ULP_CLASS_HID_2277d, .class_tid = 1, .hdr_sig_id = 2, @@ -7671,7 +7859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [208] = { + [212] = { .class_hid = BNXT_ULP_CLASS_HID_33d7d, .class_tid = 1, .hdr_sig_id = 2, @@ -7688,7 +7876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [209] = { + [213] = { .class_hid = BNXT_ULP_CLASS_HID_31e9, .class_tid = 1, .hdr_sig_id = 2, @@ -7704,7 +7892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [210] = { + [214] = { .class_hid = BNXT_ULP_CLASS_HID_147e9, .class_tid = 1, .hdr_sig_id = 2, @@ -7721,7 +7909,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [211] = { + [215] = { .class_hid = BNXT_ULP_CLASS_HID_2009d, .class_tid = 1, .hdr_sig_id = 2, @@ -7738,7 +7926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [212] = { + [216] = { .class_hid = BNXT_ULP_CLASS_HID_3169d, .class_tid = 1, .hdr_sig_id = 2, @@ -7756,7 +7944,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [213] = { + [217] = { .class_hid = BNXT_ULP_CLASS_HID_2841, .class_tid = 1, .hdr_sig_id = 2, @@ -7773,7 +7961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [214] = { + [218] = { .class_hid = BNXT_ULP_CLASS_HID_13e41, .class_tid = 1, .hdr_sig_id = 2, @@ -7791,7 +7979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [215] = { + [219] = { .class_hid = BNXT_ULP_CLASS_HID_25441, .class_tid = 1, .hdr_sig_id = 2, @@ -7809,7 +7997,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [216] = { + [220] = { .class_hid = BNXT_ULP_CLASS_HID_30d75, .class_tid = 1, .hdr_sig_id = 2, @@ -7828,7 +8016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [217] = { + [221] = { .class_hid = BNXT_ULP_CLASS_HID_4e21, .class_tid = 1, .hdr_sig_id = 2, @@ -7844,7 +8032,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [218] = { + [222] = { .class_hid = BNXT_ULP_CLASS_HID_107d5, .class_tid = 1, .hdr_sig_id = 2, @@ -7861,7 +8049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [219] = { + [223] = { .class_hid = BNXT_ULP_CLASS_HID_21dd5, .class_tid = 1, .hdr_sig_id = 2, @@ -7878,7 +8066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [220] = { + [224] = { .class_hid = BNXT_ULP_CLASS_HID_333d5, .class_tid = 1, .hdr_sig_id = 2, @@ -7896,7 +8084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [221] = { + [225] = { .class_hid = BNXT_ULP_CLASS_HID_2521, .class_tid = 1, .hdr_sig_id = 2, @@ -7912,7 +8100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [222] = { + [226] = { .class_hid = BNXT_ULP_CLASS_HID_2bed, .class_tid = 1, .hdr_sig_id = 2, @@ -7929,7 +8117,42 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [223] = { + [227] = { + .class_hid = BNXT_ULP_CLASS_HID_050d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [228] = { + .class_hid = BNXT_ULP_CLASS_HID_5b9d, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 43, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [229] = { .class_hid = BNXT_ULP_CLASS_HID_1865, .class_tid = 1, .hdr_sig_id = 3, @@ -7946,7 +8169,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [224] = { + [230] = { .class_hid = BNXT_ULP_CLASS_HID_389d, .class_tid = 1, .hdr_sig_id = 3, @@ -7964,7 +8187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [225] = { + [231] = { .class_hid = BNXT_ULP_CLASS_HID_123d, .class_tid = 1, .hdr_sig_id = 3, @@ -7983,7 +8206,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [226] = { + [232] = { .class_hid = BNXT_ULP_CLASS_HID_4ef1, .class_tid = 1, .hdr_sig_id = 3, @@ -8001,7 +8224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [227] = { + [233] = { .class_hid = BNXT_ULP_CLASS_HID_1229, .class_tid = 1, .hdr_sig_id = 3, @@ -8017,7 +8240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [228] = { + [234] = { .class_hid = BNXT_ULP_CLASS_HID_3241, .class_tid = 1, .hdr_sig_id = 3, @@ -8034,7 +8257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [229] = { + [235] = { .class_hid = BNXT_ULP_CLASS_HID_0be1, .class_tid = 1, .hdr_sig_id = 3, @@ -8052,7 +8275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [230] = { + [236] = { .class_hid = BNXT_ULP_CLASS_HID_48b5, .class_tid = 1, .hdr_sig_id = 3, @@ -8069,7 +8292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [231] = { + [237] = { .class_hid = BNXT_ULP_CLASS_HID_0bed, .class_tid = 1, .hdr_sig_id = 3, @@ -8085,7 +8308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [232] = { + [238] = { .class_hid = BNXT_ULP_CLASS_HID_2c05, .class_tid = 1, .hdr_sig_id = 3, @@ -8102,7 +8325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [233] = { + [239] = { .class_hid = BNXT_ULP_CLASS_HID_05a5, .class_tid = 1, .hdr_sig_id = 3, @@ -8120,7 +8343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [234] = { + [240] = { .class_hid = BNXT_ULP_CLASS_HID_4279, .class_tid = 1, .hdr_sig_id = 3, @@ -8137,7 +8360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [235] = { + [241] = { .class_hid = BNXT_ULP_CLASS_HID_05d1, .class_tid = 1, .hdr_sig_id = 3, @@ -8152,7 +8375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [236] = { + [242] = { .class_hid = BNXT_ULP_CLASS_HID_25c9, .class_tid = 1, .hdr_sig_id = 3, @@ -8168,7 +8391,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [237] = { + [243] = { .class_hid = BNXT_ULP_CLASS_HID_5c55, .class_tid = 1, .hdr_sig_id = 3, @@ -8185,7 +8408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [238] = { + [244] = { .class_hid = BNXT_ULP_CLASS_HID_3c3d, .class_tid = 1, .hdr_sig_id = 3, @@ -8201,7 +8424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [239] = { + [245] = { .class_hid = BNXT_ULP_CLASS_HID_4fc9, .class_tid = 1, .hdr_sig_id = 3, @@ -8216,7 +8439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [240] = { + [246] = { .class_hid = BNXT_ULP_CLASS_HID_1335, .class_tid = 1, .hdr_sig_id = 3, @@ -8232,7 +8455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [241] = { + [247] = { .class_hid = BNXT_ULP_CLASS_HID_4981, .class_tid = 1, .hdr_sig_id = 3, @@ -8249,7 +8472,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [242] = { + [248] = { .class_hid = BNXT_ULP_CLASS_HID_2969, .class_tid = 1, .hdr_sig_id = 3, @@ -8265,7 +8488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [243] = { + [249] = { .class_hid = BNXT_ULP_CLASS_HID_498d, .class_tid = 1, .hdr_sig_id = 3, @@ -8279,7 +8502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [244] = { + [250] = { .class_hid = BNXT_ULP_CLASS_HID_0cf9, .class_tid = 1, .hdr_sig_id = 3, @@ -8294,7 +8517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [245] = { + [251] = { .class_hid = BNXT_ULP_CLASS_HID_4345, .class_tid = 1, .hdr_sig_id = 3, @@ -8310,7 +8533,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [246] = { + [252] = { .class_hid = BNXT_ULP_CLASS_HID_232d, .class_tid = 1, .hdr_sig_id = 3, @@ -8325,7 +8548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [247] = { + [253] = { .class_hid = BNXT_ULP_CLASS_HID_2579, .class_tid = 1, .hdr_sig_id = 3, @@ -8340,7 +8563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [248] = { + [254] = { .class_hid = BNXT_ULP_CLASS_HID_2bb5, .class_tid = 1, .hdr_sig_id = 3, @@ -8356,7 +8579,40 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [249] = { + [255] = { + .class_hid = BNXT_ULP_CLASS_HID_4bad, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [256] = { + .class_hid = BNXT_ULP_CLASS_HID_4591, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 49, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [257] = { .class_hid = BNXT_ULP_CLASS_HID_1845, .class_tid = 1, .hdr_sig_id = 4, @@ -8374,7 +8630,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [250] = { + [258] = { .class_hid = BNXT_ULP_CLASS_HID_1399, .class_tid = 1, .hdr_sig_id = 4, @@ -8393,7 +8649,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [251] = { + [259] = { .class_hid = BNXT_ULP_CLASS_HID_0eed, .class_tid = 1, .hdr_sig_id = 4, @@ -8412,7 +8668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [252] = { + [260] = { .class_hid = BNXT_ULP_CLASS_HID_0a21, .class_tid = 1, .hdr_sig_id = 4, @@ -8432,7 +8688,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [253] = { + [261] = { .class_hid = BNXT_ULP_CLASS_HID_38bd, .class_tid = 1, .hdr_sig_id = 4, @@ -8451,7 +8707,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [254] = { + [262] = { .class_hid = BNXT_ULP_CLASS_HID_33f1, .class_tid = 1, .hdr_sig_id = 4, @@ -8471,7 +8727,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [255] = { + [263] = { .class_hid = BNXT_ULP_CLASS_HID_2ec5, .class_tid = 1, .hdr_sig_id = 4, @@ -8491,7 +8747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [256] = { + [264] = { .class_hid = BNXT_ULP_CLASS_HID_2a19, .class_tid = 1, .hdr_sig_id = 4, @@ -8512,7 +8768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [257] = { + [265] = { .class_hid = BNXT_ULP_CLASS_HID_121d, .class_tid = 1, .hdr_sig_id = 4, @@ -8532,7 +8788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [258] = { + [266] = { .class_hid = BNXT_ULP_CLASS_HID_0d51, .class_tid = 1, .hdr_sig_id = 4, @@ -8553,7 +8809,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [259] = { + [267] = { .class_hid = BNXT_ULP_CLASS_HID_08a5, .class_tid = 1, .hdr_sig_id = 4, @@ -8574,7 +8830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [260] = { + [268] = { .class_hid = BNXT_ULP_CLASS_HID_03f9, .class_tid = 1, .hdr_sig_id = 4, @@ -8596,7 +8852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [261] = { + [269] = { .class_hid = BNXT_ULP_CLASS_HID_4ed1, .class_tid = 1, .hdr_sig_id = 4, @@ -8615,7 +8871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [262] = { + [270] = { .class_hid = BNXT_ULP_CLASS_HID_4a25, .class_tid = 1, .hdr_sig_id = 4, @@ -8635,7 +8891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [263] = { + [271] = { .class_hid = BNXT_ULP_CLASS_HID_4579, .class_tid = 1, .hdr_sig_id = 4, @@ -8655,7 +8911,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [264] = { + [272] = { .class_hid = BNXT_ULP_CLASS_HID_404d, .class_tid = 1, .hdr_sig_id = 4, @@ -8676,7 +8932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [265] = { + [273] = { .class_hid = BNXT_ULP_CLASS_HID_1209, .class_tid = 1, .hdr_sig_id = 4, @@ -8693,7 +8949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [266] = { + [274] = { .class_hid = BNXT_ULP_CLASS_HID_0d5d, .class_tid = 1, .hdr_sig_id = 4, @@ -8711,7 +8967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [267] = { + [275] = { .class_hid = BNXT_ULP_CLASS_HID_0891, .class_tid = 1, .hdr_sig_id = 4, @@ -8729,7 +8985,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [268] = { + [276] = { .class_hid = BNXT_ULP_CLASS_HID_03e5, .class_tid = 1, .hdr_sig_id = 4, @@ -8748,7 +9004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [269] = { + [277] = { .class_hid = BNXT_ULP_CLASS_HID_3261, .class_tid = 1, .hdr_sig_id = 4, @@ -8766,7 +9022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [270] = { + [278] = { .class_hid = BNXT_ULP_CLASS_HID_2db5, .class_tid = 1, .hdr_sig_id = 4, @@ -8785,7 +9041,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [271] = { + [279] = { .class_hid = BNXT_ULP_CLASS_HID_2889, .class_tid = 1, .hdr_sig_id = 4, @@ -8804,7 +9060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [272] = { + [280] = { .class_hid = BNXT_ULP_CLASS_HID_23dd, .class_tid = 1, .hdr_sig_id = 4, @@ -8824,7 +9080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [273] = { + [281] = { .class_hid = BNXT_ULP_CLASS_HID_0bc1, .class_tid = 1, .hdr_sig_id = 4, @@ -8843,7 +9099,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [274] = { + [282] = { .class_hid = BNXT_ULP_CLASS_HID_0715, .class_tid = 1, .hdr_sig_id = 4, @@ -8863,7 +9119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [275] = { + [283] = { .class_hid = BNXT_ULP_CLASS_HID_0269, .class_tid = 1, .hdr_sig_id = 4, @@ -8883,7 +9139,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [276] = { + [284] = { .class_hid = BNXT_ULP_CLASS_HID_5a69, .class_tid = 1, .hdr_sig_id = 4, @@ -8904,7 +9160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [277] = { + [285] = { .class_hid = BNXT_ULP_CLASS_HID_4895, .class_tid = 1, .hdr_sig_id = 4, @@ -8922,7 +9178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [278] = { + [286] = { .class_hid = BNXT_ULP_CLASS_HID_43e9, .class_tid = 1, .hdr_sig_id = 4, @@ -8941,7 +9197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [279] = { + [287] = { .class_hid = BNXT_ULP_CLASS_HID_3f3d, .class_tid = 1, .hdr_sig_id = 4, @@ -8960,7 +9216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [280] = { + [288] = { .class_hid = BNXT_ULP_CLASS_HID_3a71, .class_tid = 1, .hdr_sig_id = 4, @@ -8980,7 +9236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [281] = { + [289] = { .class_hid = BNXT_ULP_CLASS_HID_0bcd, .class_tid = 1, .hdr_sig_id = 4, @@ -8997,7 +9253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [282] = { + [290] = { .class_hid = BNXT_ULP_CLASS_HID_0701, .class_tid = 1, .hdr_sig_id = 4, @@ -9015,7 +9271,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [283] = { + [291] = { .class_hid = BNXT_ULP_CLASS_HID_0255, .class_tid = 1, .hdr_sig_id = 4, @@ -9033,7 +9289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [284] = { + [292] = { .class_hid = BNXT_ULP_CLASS_HID_5a55, .class_tid = 1, .hdr_sig_id = 4, @@ -9052,7 +9308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [285] = { + [293] = { .class_hid = BNXT_ULP_CLASS_HID_2c25, .class_tid = 1, .hdr_sig_id = 4, @@ -9070,7 +9326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [286] = { + [294] = { .class_hid = BNXT_ULP_CLASS_HID_2779, .class_tid = 1, .hdr_sig_id = 4, @@ -9089,7 +9345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [287] = { + [295] = { .class_hid = BNXT_ULP_CLASS_HID_224d, .class_tid = 1, .hdr_sig_id = 4, @@ -9108,7 +9364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [288] = { + [296] = { .class_hid = BNXT_ULP_CLASS_HID_1d81, .class_tid = 1, .hdr_sig_id = 4, @@ -9128,7 +9384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [289] = { + [297] = { .class_hid = BNXT_ULP_CLASS_HID_0585, .class_tid = 1, .hdr_sig_id = 4, @@ -9147,7 +9403,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [290] = { + [298] = { .class_hid = BNXT_ULP_CLASS_HID_00d9, .class_tid = 1, .hdr_sig_id = 4, @@ -9167,7 +9423,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [291] = { + [299] = { .class_hid = BNXT_ULP_CLASS_HID_58d9, .class_tid = 1, .hdr_sig_id = 4, @@ -9187,7 +9443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [292] = { + [300] = { .class_hid = BNXT_ULP_CLASS_HID_542d, .class_tid = 1, .hdr_sig_id = 4, @@ -9208,7 +9464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [293] = { + [301] = { .class_hid = BNXT_ULP_CLASS_HID_4259, .class_tid = 1, .hdr_sig_id = 4, @@ -9226,7 +9482,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [294] = { + [302] = { .class_hid = BNXT_ULP_CLASS_HID_3dad, .class_tid = 1, .hdr_sig_id = 4, @@ -9245,7 +9501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [295] = { + [303] = { .class_hid = BNXT_ULP_CLASS_HID_38e1, .class_tid = 1, .hdr_sig_id = 4, @@ -9264,7 +9520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [296] = { + [304] = { .class_hid = BNXT_ULP_CLASS_HID_3435, .class_tid = 1, .hdr_sig_id = 4, @@ -9284,7 +9540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [297] = { + [305] = { .class_hid = BNXT_ULP_CLASS_HID_05f1, .class_tid = 1, .hdr_sig_id = 4, @@ -9300,7 +9556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [298] = { + [306] = { .class_hid = BNXT_ULP_CLASS_HID_00c5, .class_tid = 1, .hdr_sig_id = 4, @@ -9317,7 +9573,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [299] = { + [307] = { .class_hid = BNXT_ULP_CLASS_HID_58c5, .class_tid = 1, .hdr_sig_id = 4, @@ -9334,7 +9590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [300] = { + [308] = { .class_hid = BNXT_ULP_CLASS_HID_5419, .class_tid = 1, .hdr_sig_id = 4, @@ -9352,7 +9608,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [301] = { + [309] = { .class_hid = BNXT_ULP_CLASS_HID_25e9, .class_tid = 1, .hdr_sig_id = 4, @@ -9369,7 +9625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [302] = { + [310] = { .class_hid = BNXT_ULP_CLASS_HID_213d, .class_tid = 1, .hdr_sig_id = 4, @@ -9387,7 +9643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [303] = { + [311] = { .class_hid = BNXT_ULP_CLASS_HID_1c71, .class_tid = 1, .hdr_sig_id = 4, @@ -9405,7 +9661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [304] = { + [312] = { .class_hid = BNXT_ULP_CLASS_HID_1745, .class_tid = 1, .hdr_sig_id = 4, @@ -9424,7 +9680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [305] = { + [313] = { .class_hid = BNXT_ULP_CLASS_HID_5c75, .class_tid = 1, .hdr_sig_id = 4, @@ -9442,7 +9698,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [306] = { + [314] = { .class_hid = BNXT_ULP_CLASS_HID_5749, .class_tid = 1, .hdr_sig_id = 4, @@ -9461,7 +9717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [307] = { + [315] = { .class_hid = BNXT_ULP_CLASS_HID_529d, .class_tid = 1, .hdr_sig_id = 4, @@ -9480,7 +9736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [308] = { + [316] = { .class_hid = BNXT_ULP_CLASS_HID_4dd1, .class_tid = 1, .hdr_sig_id = 4, @@ -9500,7 +9756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [309] = { + [317] = { .class_hid = BNXT_ULP_CLASS_HID_3c1d, .class_tid = 1, .hdr_sig_id = 4, @@ -9517,7 +9773,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [310] = { + [318] = { .class_hid = BNXT_ULP_CLASS_HID_3751, .class_tid = 1, .hdr_sig_id = 4, @@ -9535,7 +9791,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [311] = { + [319] = { .class_hid = BNXT_ULP_CLASS_HID_32a5, .class_tid = 1, .hdr_sig_id = 4, @@ -9553,7 +9809,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [312] = { + [320] = { .class_hid = BNXT_ULP_CLASS_HID_2df9, .class_tid = 1, .hdr_sig_id = 4, @@ -9572,7 +9828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [313] = { + [321] = { .class_hid = BNXT_ULP_CLASS_HID_4fe9, .class_tid = 1, .hdr_sig_id = 4, @@ -9588,7 +9844,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [314] = { + [322] = { .class_hid = BNXT_ULP_CLASS_HID_4b3d, .class_tid = 1, .hdr_sig_id = 4, @@ -9605,7 +9861,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [315] = { + [323] = { .class_hid = BNXT_ULP_CLASS_HID_4671, .class_tid = 1, .hdr_sig_id = 4, @@ -9622,7 +9878,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [316] = { + [324] = { .class_hid = BNXT_ULP_CLASS_HID_4145, .class_tid = 1, .hdr_sig_id = 4, @@ -9640,7 +9896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [317] = { + [325] = { .class_hid = BNXT_ULP_CLASS_HID_1315, .class_tid = 1, .hdr_sig_id = 4, @@ -9657,7 +9913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [318] = { + [326] = { .class_hid = BNXT_ULP_CLASS_HID_0e69, .class_tid = 1, .hdr_sig_id = 4, @@ -9675,7 +9931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [319] = { + [327] = { .class_hid = BNXT_ULP_CLASS_HID_09bd, .class_tid = 1, .hdr_sig_id = 4, @@ -9693,7 +9949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [320] = { + [328] = { .class_hid = BNXT_ULP_CLASS_HID_04f1, .class_tid = 1, .hdr_sig_id = 4, @@ -9712,7 +9968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [321] = { + [329] = { .class_hid = BNXT_ULP_CLASS_HID_49a1, .class_tid = 1, .hdr_sig_id = 4, @@ -9730,7 +9986,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [322] = { + [330] = { .class_hid = BNXT_ULP_CLASS_HID_44f5, .class_tid = 1, .hdr_sig_id = 4, @@ -9749,7 +10005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [323] = { + [331] = { .class_hid = BNXT_ULP_CLASS_HID_3fc9, .class_tid = 1, .hdr_sig_id = 4, @@ -9768,7 +10024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [324] = { + [332] = { .class_hid = BNXT_ULP_CLASS_HID_3b1d, .class_tid = 1, .hdr_sig_id = 4, @@ -9788,7 +10044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [325] = { + [333] = { .class_hid = BNXT_ULP_CLASS_HID_2949, .class_tid = 1, .hdr_sig_id = 4, @@ -9805,7 +10061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [326] = { + [334] = { .class_hid = BNXT_ULP_CLASS_HID_249d, .class_tid = 1, .hdr_sig_id = 4, @@ -9823,7 +10079,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [327] = { + [335] = { .class_hid = BNXT_ULP_CLASS_HID_1fd1, .class_tid = 1, .hdr_sig_id = 4, @@ -9841,7 +10097,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [328] = { + [336] = { .class_hid = BNXT_ULP_CLASS_HID_1b25, .class_tid = 1, .hdr_sig_id = 4, @@ -9860,7 +10116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [329] = { + [337] = { .class_hid = BNXT_ULP_CLASS_HID_49ad, .class_tid = 1, .hdr_sig_id = 4, @@ -9875,7 +10131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [330] = { + [338] = { .class_hid = BNXT_ULP_CLASS_HID_44e1, .class_tid = 1, .hdr_sig_id = 4, @@ -9891,7 +10147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [331] = { + [339] = { .class_hid = BNXT_ULP_CLASS_HID_4035, .class_tid = 1, .hdr_sig_id = 4, @@ -9907,7 +10163,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [332] = { + [340] = { .class_hid = BNXT_ULP_CLASS_HID_3b09, .class_tid = 1, .hdr_sig_id = 4, @@ -9924,7 +10180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [333] = { + [341] = { .class_hid = BNXT_ULP_CLASS_HID_0cd9, .class_tid = 1, .hdr_sig_id = 4, @@ -9940,7 +10196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [334] = { + [342] = { .class_hid = BNXT_ULP_CLASS_HID_082d, .class_tid = 1, .hdr_sig_id = 4, @@ -9957,7 +10213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [335] = { + [343] = { .class_hid = BNXT_ULP_CLASS_HID_0361, .class_tid = 1, .hdr_sig_id = 4, @@ -9974,7 +10230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [336] = { + [344] = { .class_hid = BNXT_ULP_CLASS_HID_5b61, .class_tid = 1, .hdr_sig_id = 4, @@ -9992,7 +10248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [337] = { + [345] = { .class_hid = BNXT_ULP_CLASS_HID_4365, .class_tid = 1, .hdr_sig_id = 4, @@ -10009,7 +10265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [338] = { + [346] = { .class_hid = BNXT_ULP_CLASS_HID_3eb9, .class_tid = 1, .hdr_sig_id = 4, @@ -10027,7 +10283,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [339] = { + [347] = { .class_hid = BNXT_ULP_CLASS_HID_398d, .class_tid = 1, .hdr_sig_id = 4, @@ -10045,7 +10301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [340] = { + [348] = { .class_hid = BNXT_ULP_CLASS_HID_34c1, .class_tid = 1, .hdr_sig_id = 4, @@ -10064,7 +10320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [341] = { + [349] = { .class_hid = BNXT_ULP_CLASS_HID_230d, .class_tid = 1, .hdr_sig_id = 4, @@ -10080,7 +10336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [342] = { + [350] = { .class_hid = BNXT_ULP_CLASS_HID_1e41, .class_tid = 1, .hdr_sig_id = 4, @@ -10097,7 +10353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [343] = { + [351] = { .class_hid = BNXT_ULP_CLASS_HID_1995, .class_tid = 1, .hdr_sig_id = 4, @@ -10114,7 +10370,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [344] = { + [352] = { .class_hid = BNXT_ULP_CLASS_HID_14e9, .class_tid = 1, .hdr_sig_id = 4, @@ -10132,7 +10388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [345] = { + [353] = { .class_hid = BNXT_ULP_CLASS_HID_2559, .class_tid = 1, .hdr_sig_id = 4, @@ -10148,7 +10404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [346] = { + [354] = { .class_hid = BNXT_ULP_CLASS_HID_2b95, .class_tid = 1, .hdr_sig_id = 4, @@ -10165,7 +10421,42 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [347] = { + [355] = { + .class_hid = BNXT_ULP_CLASS_HID_4b8d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [356] = { + .class_hid = BNXT_ULP_CLASS_HID_45b1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 67, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [357] = { .class_hid = BNXT_ULP_CLASS_HID_1825, .class_tid = 1, .hdr_sig_id = 5, @@ -10183,7 +10474,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [348] = { + [358] = { .class_hid = BNXT_ULP_CLASS_HID_13f9, .class_tid = 1, .hdr_sig_id = 5, @@ -10202,7 +10493,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [349] = { + [359] = { .class_hid = BNXT_ULP_CLASS_HID_0e8d, .class_tid = 1, .hdr_sig_id = 5, @@ -10221,7 +10512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [350] = { + [360] = { .class_hid = BNXT_ULP_CLASS_HID_0a41, .class_tid = 1, .hdr_sig_id = 5, @@ -10241,7 +10532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [351] = { + [361] = { .class_hid = BNXT_ULP_CLASS_HID_38dd, .class_tid = 1, .hdr_sig_id = 5, @@ -10260,7 +10551,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [352] = { + [362] = { .class_hid = BNXT_ULP_CLASS_HID_3391, .class_tid = 1, .hdr_sig_id = 5, @@ -10280,7 +10571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [353] = { + [363] = { .class_hid = BNXT_ULP_CLASS_HID_2ea5, .class_tid = 1, .hdr_sig_id = 5, @@ -10300,7 +10591,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [354] = { + [364] = { .class_hid = BNXT_ULP_CLASS_HID_2a79, .class_tid = 1, .hdr_sig_id = 5, @@ -10321,7 +10612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [355] = { + [365] = { .class_hid = BNXT_ULP_CLASS_HID_127d, .class_tid = 1, .hdr_sig_id = 5, @@ -10341,7 +10632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [356] = { + [366] = { .class_hid = BNXT_ULP_CLASS_HID_0d31, .class_tid = 1, .hdr_sig_id = 5, @@ -10362,7 +10653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [357] = { + [367] = { .class_hid = BNXT_ULP_CLASS_HID_08c5, .class_tid = 1, .hdr_sig_id = 5, @@ -10383,7 +10674,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [358] = { + [368] = { .class_hid = BNXT_ULP_CLASS_HID_0399, .class_tid = 1, .hdr_sig_id = 5, @@ -10405,7 +10696,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [359] = { + [369] = { .class_hid = BNXT_ULP_CLASS_HID_4eb1, .class_tid = 1, .hdr_sig_id = 5, @@ -10424,7 +10715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [360] = { + [370] = { .class_hid = BNXT_ULP_CLASS_HID_4a45, .class_tid = 1, .hdr_sig_id = 5, @@ -10444,7 +10735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [361] = { + [371] = { .class_hid = BNXT_ULP_CLASS_HID_4519, .class_tid = 1, .hdr_sig_id = 5, @@ -10464,7 +10755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [362] = { + [372] = { .class_hid = BNXT_ULP_CLASS_HID_402d, .class_tid = 1, .hdr_sig_id = 5, @@ -10485,7 +10776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [363] = { + [373] = { .class_hid = BNXT_ULP_CLASS_HID_1269, .class_tid = 1, .hdr_sig_id = 5, @@ -10502,7 +10793,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [364] = { + [374] = { .class_hid = BNXT_ULP_CLASS_HID_0d3d, .class_tid = 1, .hdr_sig_id = 5, @@ -10520,7 +10811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [365] = { + [375] = { .class_hid = BNXT_ULP_CLASS_HID_08f1, .class_tid = 1, .hdr_sig_id = 5, @@ -10538,7 +10829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [366] = { + [376] = { .class_hid = BNXT_ULP_CLASS_HID_0385, .class_tid = 1, .hdr_sig_id = 5, @@ -10557,7 +10848,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [367] = { + [377] = { .class_hid = BNXT_ULP_CLASS_HID_3201, .class_tid = 1, .hdr_sig_id = 5, @@ -10575,7 +10866,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [368] = { + [378] = { .class_hid = BNXT_ULP_CLASS_HID_2dd5, .class_tid = 1, .hdr_sig_id = 5, @@ -10594,7 +10885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [369] = { + [379] = { .class_hid = BNXT_ULP_CLASS_HID_28e9, .class_tid = 1, .hdr_sig_id = 5, @@ -10613,7 +10904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [370] = { + [380] = { .class_hid = BNXT_ULP_CLASS_HID_23bd, .class_tid = 1, .hdr_sig_id = 5, @@ -10633,7 +10924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [371] = { + [381] = { .class_hid = BNXT_ULP_CLASS_HID_0ba1, .class_tid = 1, .hdr_sig_id = 5, @@ -10652,7 +10943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [372] = { + [382] = { .class_hid = BNXT_ULP_CLASS_HID_0775, .class_tid = 1, .hdr_sig_id = 5, @@ -10672,7 +10963,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [373] = { + [383] = { .class_hid = BNXT_ULP_CLASS_HID_0209, .class_tid = 1, .hdr_sig_id = 5, @@ -10692,7 +10983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [374] = { + [384] = { .class_hid = BNXT_ULP_CLASS_HID_5a09, .class_tid = 1, .hdr_sig_id = 5, @@ -10713,7 +11004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [375] = { + [385] = { .class_hid = BNXT_ULP_CLASS_HID_48f5, .class_tid = 1, .hdr_sig_id = 5, @@ -10731,7 +11022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [376] = { + [386] = { .class_hid = BNXT_ULP_CLASS_HID_4389, .class_tid = 1, .hdr_sig_id = 5, @@ -10750,7 +11041,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [377] = { + [387] = { .class_hid = BNXT_ULP_CLASS_HID_3f5d, .class_tid = 1, .hdr_sig_id = 5, @@ -10769,7 +11060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [378] = { + [388] = { .class_hid = BNXT_ULP_CLASS_HID_3a11, .class_tid = 1, .hdr_sig_id = 5, @@ -10789,7 +11080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [379] = { + [389] = { .class_hid = BNXT_ULP_CLASS_HID_0bad, .class_tid = 1, .hdr_sig_id = 5, @@ -10806,7 +11097,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [380] = { + [390] = { .class_hid = BNXT_ULP_CLASS_HID_0761, .class_tid = 1, .hdr_sig_id = 5, @@ -10824,7 +11115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [381] = { + [391] = { .class_hid = BNXT_ULP_CLASS_HID_0235, .class_tid = 1, .hdr_sig_id = 5, @@ -10842,7 +11133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [382] = { + [392] = { .class_hid = BNXT_ULP_CLASS_HID_5a35, .class_tid = 1, .hdr_sig_id = 5, @@ -10861,7 +11152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [383] = { + [393] = { .class_hid = BNXT_ULP_CLASS_HID_2c45, .class_tid = 1, .hdr_sig_id = 5, @@ -10879,7 +11170,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [384] = { + [394] = { .class_hid = BNXT_ULP_CLASS_HID_2719, .class_tid = 1, .hdr_sig_id = 5, @@ -10898,7 +11189,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [385] = { + [395] = { .class_hid = BNXT_ULP_CLASS_HID_222d, .class_tid = 1, .hdr_sig_id = 5, @@ -10917,7 +11208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [386] = { + [396] = { .class_hid = BNXT_ULP_CLASS_HID_1de1, .class_tid = 1, .hdr_sig_id = 5, @@ -10937,7 +11228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [387] = { + [397] = { .class_hid = BNXT_ULP_CLASS_HID_05e5, .class_tid = 1, .hdr_sig_id = 5, @@ -10956,7 +11247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [388] = { + [398] = { .class_hid = BNXT_ULP_CLASS_HID_00b9, .class_tid = 1, .hdr_sig_id = 5, @@ -10976,7 +11267,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [389] = { + [399] = { .class_hid = BNXT_ULP_CLASS_HID_58b9, .class_tid = 1, .hdr_sig_id = 5, @@ -10996,7 +11287,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [390] = { + [400] = { .class_hid = BNXT_ULP_CLASS_HID_544d, .class_tid = 1, .hdr_sig_id = 5, @@ -11017,7 +11308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [391] = { + [401] = { .class_hid = BNXT_ULP_CLASS_HID_4239, .class_tid = 1, .hdr_sig_id = 5, @@ -11035,7 +11326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [392] = { + [402] = { .class_hid = BNXT_ULP_CLASS_HID_3dcd, .class_tid = 1, .hdr_sig_id = 5, @@ -11054,7 +11345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [393] = { + [403] = { .class_hid = BNXT_ULP_CLASS_HID_3881, .class_tid = 1, .hdr_sig_id = 5, @@ -11073,7 +11364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [394] = { + [404] = { .class_hid = BNXT_ULP_CLASS_HID_3455, .class_tid = 1, .hdr_sig_id = 5, @@ -11093,7 +11384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [395] = { + [405] = { .class_hid = BNXT_ULP_CLASS_HID_0591, .class_tid = 1, .hdr_sig_id = 5, @@ -11109,7 +11400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [396] = { + [406] = { .class_hid = BNXT_ULP_CLASS_HID_00a5, .class_tid = 1, .hdr_sig_id = 5, @@ -11126,7 +11417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [397] = { + [407] = { .class_hid = BNXT_ULP_CLASS_HID_58a5, .class_tid = 1, .hdr_sig_id = 5, @@ -11143,7 +11434,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [398] = { + [408] = { .class_hid = BNXT_ULP_CLASS_HID_5479, .class_tid = 1, .hdr_sig_id = 5, @@ -11161,7 +11452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [399] = { + [409] = { .class_hid = BNXT_ULP_CLASS_HID_2589, .class_tid = 1, .hdr_sig_id = 5, @@ -11178,7 +11469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [400] = { + [410] = { .class_hid = BNXT_ULP_CLASS_HID_215d, .class_tid = 1, .hdr_sig_id = 5, @@ -11196,7 +11487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [401] = { + [411] = { .class_hid = BNXT_ULP_CLASS_HID_1c11, .class_tid = 1, .hdr_sig_id = 5, @@ -11214,7 +11505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [402] = { + [412] = { .class_hid = BNXT_ULP_CLASS_HID_1725, .class_tid = 1, .hdr_sig_id = 5, @@ -11233,7 +11524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [403] = { + [413] = { .class_hid = BNXT_ULP_CLASS_HID_5c15, .class_tid = 1, .hdr_sig_id = 5, @@ -11251,7 +11542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [404] = { + [414] = { .class_hid = BNXT_ULP_CLASS_HID_5729, .class_tid = 1, .hdr_sig_id = 5, @@ -11270,7 +11561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [405] = { + [415] = { .class_hid = BNXT_ULP_CLASS_HID_52fd, .class_tid = 1, .hdr_sig_id = 5, @@ -11289,7 +11580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [406] = { + [416] = { .class_hid = BNXT_ULP_CLASS_HID_4db1, .class_tid = 1, .hdr_sig_id = 5, @@ -11309,7 +11600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [407] = { + [417] = { .class_hid = BNXT_ULP_CLASS_HID_3c7d, .class_tid = 1, .hdr_sig_id = 5, @@ -11326,7 +11617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [408] = { + [418] = { .class_hid = BNXT_ULP_CLASS_HID_3731, .class_tid = 1, .hdr_sig_id = 5, @@ -11344,7 +11635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [409] = { + [419] = { .class_hid = BNXT_ULP_CLASS_HID_32c5, .class_tid = 1, .hdr_sig_id = 5, @@ -11362,7 +11653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [410] = { + [420] = { .class_hid = BNXT_ULP_CLASS_HID_2d99, .class_tid = 1, .hdr_sig_id = 5, @@ -11381,7 +11672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [411] = { + [421] = { .class_hid = BNXT_ULP_CLASS_HID_4f89, .class_tid = 1, .hdr_sig_id = 5, @@ -11397,7 +11688,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [412] = { + [422] = { .class_hid = BNXT_ULP_CLASS_HID_4b5d, .class_tid = 1, .hdr_sig_id = 5, @@ -11414,7 +11705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [413] = { + [423] = { .class_hid = BNXT_ULP_CLASS_HID_4611, .class_tid = 1, .hdr_sig_id = 5, @@ -11431,7 +11722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [414] = { + [424] = { .class_hid = BNXT_ULP_CLASS_HID_4125, .class_tid = 1, .hdr_sig_id = 5, @@ -11449,7 +11740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [415] = { + [425] = { .class_hid = BNXT_ULP_CLASS_HID_1375, .class_tid = 1, .hdr_sig_id = 5, @@ -11466,7 +11757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [416] = { + [426] = { .class_hid = BNXT_ULP_CLASS_HID_0e09, .class_tid = 1, .hdr_sig_id = 5, @@ -11484,7 +11775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [417] = { + [427] = { .class_hid = BNXT_ULP_CLASS_HID_09dd, .class_tid = 1, .hdr_sig_id = 5, @@ -11502,7 +11793,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [418] = { + [428] = { .class_hid = BNXT_ULP_CLASS_HID_0491, .class_tid = 1, .hdr_sig_id = 5, @@ -11521,7 +11812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [419] = { + [429] = { .class_hid = BNXT_ULP_CLASS_HID_49c1, .class_tid = 1, .hdr_sig_id = 5, @@ -11539,7 +11830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [420] = { + [430] = { .class_hid = BNXT_ULP_CLASS_HID_4495, .class_tid = 1, .hdr_sig_id = 5, @@ -11558,7 +11849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [421] = { + [431] = { .class_hid = BNXT_ULP_CLASS_HID_3fa9, .class_tid = 1, .hdr_sig_id = 5, @@ -11577,7 +11868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [422] = { + [432] = { .class_hid = BNXT_ULP_CLASS_HID_3b7d, .class_tid = 1, .hdr_sig_id = 5, @@ -11597,7 +11888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [423] = { + [433] = { .class_hid = BNXT_ULP_CLASS_HID_2929, .class_tid = 1, .hdr_sig_id = 5, @@ -11614,7 +11905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [424] = { + [434] = { .class_hid = BNXT_ULP_CLASS_HID_24fd, .class_tid = 1, .hdr_sig_id = 5, @@ -11632,7 +11923,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [425] = { + [435] = { .class_hid = BNXT_ULP_CLASS_HID_1fb1, .class_tid = 1, .hdr_sig_id = 5, @@ -11650,7 +11941,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [426] = { + [436] = { .class_hid = BNXT_ULP_CLASS_HID_1b45, .class_tid = 1, .hdr_sig_id = 5, @@ -11669,7 +11960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [427] = { + [437] = { .class_hid = BNXT_ULP_CLASS_HID_49cd, .class_tid = 1, .hdr_sig_id = 5, @@ -11684,7 +11975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [428] = { + [438] = { .class_hid = BNXT_ULP_CLASS_HID_4481, .class_tid = 1, .hdr_sig_id = 5, @@ -11700,7 +11991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [429] = { + [439] = { .class_hid = BNXT_ULP_CLASS_HID_4055, .class_tid = 1, .hdr_sig_id = 5, @@ -11716,7 +12007,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [430] = { + [440] = { .class_hid = BNXT_ULP_CLASS_HID_3b69, .class_tid = 1, .hdr_sig_id = 5, @@ -11733,7 +12024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [431] = { + [441] = { .class_hid = BNXT_ULP_CLASS_HID_0cb9, .class_tid = 1, .hdr_sig_id = 5, @@ -11749,7 +12040,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [432] = { + [442] = { .class_hid = BNXT_ULP_CLASS_HID_084d, .class_tid = 1, .hdr_sig_id = 5, @@ -11766,7 +12057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [433] = { + [443] = { .class_hid = BNXT_ULP_CLASS_HID_0301, .class_tid = 1, .hdr_sig_id = 5, @@ -11783,7 +12074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [434] = { + [444] = { .class_hid = BNXT_ULP_CLASS_HID_5b01, .class_tid = 1, .hdr_sig_id = 5, @@ -11801,7 +12092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [435] = { + [445] = { .class_hid = BNXT_ULP_CLASS_HID_4305, .class_tid = 1, .hdr_sig_id = 5, @@ -11818,7 +12109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [436] = { + [446] = { .class_hid = BNXT_ULP_CLASS_HID_3ed9, .class_tid = 1, .hdr_sig_id = 5, @@ -11836,7 +12127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [437] = { + [447] = { .class_hid = BNXT_ULP_CLASS_HID_39ed, .class_tid = 1, .hdr_sig_id = 5, @@ -11854,7 +12145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [438] = { + [448] = { .class_hid = BNXT_ULP_CLASS_HID_34a1, .class_tid = 1, .hdr_sig_id = 5, @@ -11873,7 +12164,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [439] = { + [449] = { .class_hid = BNXT_ULP_CLASS_HID_236d, .class_tid = 1, .hdr_sig_id = 5, @@ -11889,7 +12180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [440] = { + [450] = { .class_hid = BNXT_ULP_CLASS_HID_1e21, .class_tid = 1, .hdr_sig_id = 5, @@ -11906,7 +12197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [441] = { + [451] = { .class_hid = BNXT_ULP_CLASS_HID_19f5, .class_tid = 1, .hdr_sig_id = 5, @@ -11923,7 +12214,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [442] = { + [452] = { .class_hid = BNXT_ULP_CLASS_HID_1489, .class_tid = 1, .hdr_sig_id = 5, @@ -11941,7 +12232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [443] = { + [453] = { .class_hid = BNXT_ULP_CLASS_HID_2539, .class_tid = 1, .hdr_sig_id = 5, @@ -11957,7 +12248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [444] = { + [454] = { .class_hid = BNXT_ULP_CLASS_HID_2bf5, .class_tid = 1, .hdr_sig_id = 5, @@ -11974,7 +12265,42 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [445] = { + [455] = { + .class_hid = BNXT_ULP_CLASS_HID_4bed, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [456] = { + .class_hid = BNXT_ULP_CLASS_HID_45d1, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 85, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [457] = { .class_hid = BNXT_ULP_CLASS_HID_b6af, .class_tid = 1, .hdr_sig_id = 6, @@ -11992,7 +12318,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [446] = { + [458] = { .class_hid = BNXT_ULP_CLASS_HID_b1d3, .class_tid = 1, .hdr_sig_id = 6, @@ -12011,7 +12337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [447] = { + [459] = { .class_hid = BNXT_ULP_CLASS_HID_1c7d3, .class_tid = 1, .hdr_sig_id = 6, @@ -12031,7 +12357,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [448] = { + [460] = { .class_hid = BNXT_ULP_CLASS_HID_1ccaf, .class_tid = 1, .hdr_sig_id = 6, @@ -12050,7 +12376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [449] = { + [461] = { .class_hid = BNXT_ULP_CLASS_HID_da33, .class_tid = 1, .hdr_sig_id = 6, @@ -12069,7 +12395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [450] = { + [462] = { .class_hid = BNXT_ULP_CLASS_HID_d567, .class_tid = 1, .hdr_sig_id = 6, @@ -12089,7 +12415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [451] = { + [463] = { .class_hid = BNXT_ULP_CLASS_HID_18eab, .class_tid = 1, .hdr_sig_id = 6, @@ -12110,7 +12436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [452] = { + [464] = { .class_hid = BNXT_ULP_CLASS_HID_19367, .class_tid = 1, .hdr_sig_id = 6, @@ -12130,7 +12456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [453] = { + [465] = { .class_hid = BNXT_ULP_CLASS_HID_a10b, .class_tid = 1, .hdr_sig_id = 6, @@ -12149,7 +12475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [454] = { + [466] = { .class_hid = BNXT_ULP_CLASS_HID_9c3f, .class_tid = 1, .hdr_sig_id = 6, @@ -12169,7 +12495,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [455] = { + [467] = { .class_hid = BNXT_ULP_CLASS_HID_1b23f, .class_tid = 1, .hdr_sig_id = 6, @@ -12190,7 +12516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [456] = { + [468] = { .class_hid = BNXT_ULP_CLASS_HID_1b70b, .class_tid = 1, .hdr_sig_id = 6, @@ -12210,7 +12536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [457] = { + [469] = { .class_hid = BNXT_ULP_CLASS_HID_c49f, .class_tid = 1, .hdr_sig_id = 6, @@ -12230,7 +12556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [458] = { + [470] = { .class_hid = BNXT_ULP_CLASS_HID_bfc3, .class_tid = 1, .hdr_sig_id = 6, @@ -12251,7 +12577,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [459] = { + [471] = { .class_hid = BNXT_ULP_CLASS_HID_1d5c3, .class_tid = 1, .hdr_sig_id = 6, @@ -12273,7 +12599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [460] = { + [472] = { .class_hid = BNXT_ULP_CLASS_HID_1da9f, .class_tid = 1, .hdr_sig_id = 6, @@ -12294,7 +12620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [461] = { + [473] = { .class_hid = BNXT_ULP_CLASS_HID_b063, .class_tid = 1, .hdr_sig_id = 6, @@ -12311,7 +12637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [462] = { + [474] = { .class_hid = BNXT_ULP_CLASS_HID_ab97, .class_tid = 1, .hdr_sig_id = 6, @@ -12329,7 +12655,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [463] = { + [475] = { .class_hid = BNXT_ULP_CLASS_HID_1c197, .class_tid = 1, .hdr_sig_id = 6, @@ -12348,7 +12674,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [464] = { + [476] = { .class_hid = BNXT_ULP_CLASS_HID_1c663, .class_tid = 1, .hdr_sig_id = 6, @@ -12366,7 +12692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [465] = { + [477] = { .class_hid = BNXT_ULP_CLASS_HID_d3f7, .class_tid = 1, .hdr_sig_id = 6, @@ -12384,7 +12710,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [466] = { + [478] = { .class_hid = BNXT_ULP_CLASS_HID_cf3b, .class_tid = 1, .hdr_sig_id = 6, @@ -12403,7 +12729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [467] = { + [479] = { .class_hid = BNXT_ULP_CLASS_HID_1886f, .class_tid = 1, .hdr_sig_id = 6, @@ -12423,7 +12749,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [468] = { + [480] = { .class_hid = BNXT_ULP_CLASS_HID_18d3b, .class_tid = 1, .hdr_sig_id = 6, @@ -12442,7 +12768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [469] = { + [481] = { .class_hid = BNXT_ULP_CLASS_HID_9acf, .class_tid = 1, .hdr_sig_id = 6, @@ -12460,7 +12786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [470] = { + [482] = { .class_hid = BNXT_ULP_CLASS_HID_95f3, .class_tid = 1, .hdr_sig_id = 6, @@ -12479,7 +12805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [471] = { + [483] = { .class_hid = BNXT_ULP_CLASS_HID_1abf3, .class_tid = 1, .hdr_sig_id = 6, @@ -12499,7 +12825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [472] = { + [484] = { .class_hid = BNXT_ULP_CLASS_HID_1b0cf, .class_tid = 1, .hdr_sig_id = 6, @@ -12518,7 +12844,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [473] = { + [485] = { .class_hid = BNXT_ULP_CLASS_HID_be53, .class_tid = 1, .hdr_sig_id = 6, @@ -12537,7 +12863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [474] = { + [486] = { .class_hid = BNXT_ULP_CLASS_HID_b987, .class_tid = 1, .hdr_sig_id = 6, @@ -12557,7 +12883,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [475] = { + [487] = { .class_hid = BNXT_ULP_CLASS_HID_1cf87, .class_tid = 1, .hdr_sig_id = 6, @@ -12578,7 +12904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [476] = { + [488] = { .class_hid = BNXT_ULP_CLASS_HID_1d453, .class_tid = 1, .hdr_sig_id = 6, @@ -12598,7 +12924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [477] = { + [489] = { .class_hid = BNXT_ULP_CLASS_HID_aa27, .class_tid = 1, .hdr_sig_id = 6, @@ -12615,7 +12941,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [478] = { + [490] = { .class_hid = BNXT_ULP_CLASS_HID_a56b, .class_tid = 1, .hdr_sig_id = 6, @@ -12633,7 +12959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [479] = { + [491] = { .class_hid = BNXT_ULP_CLASS_HID_1bb6b, .class_tid = 1, .hdr_sig_id = 6, @@ -12652,7 +12978,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [480] = { + [492] = { .class_hid = BNXT_ULP_CLASS_HID_1c027, .class_tid = 1, .hdr_sig_id = 6, @@ -12670,7 +12996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [481] = { + [493] = { .class_hid = BNXT_ULP_CLASS_HID_cdcb, .class_tid = 1, .hdr_sig_id = 6, @@ -12688,7 +13014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [482] = { + [494] = { .class_hid = BNXT_ULP_CLASS_HID_c8ff, .class_tid = 1, .hdr_sig_id = 6, @@ -12707,7 +13033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [483] = { + [495] = { .class_hid = BNXT_ULP_CLASS_HID_18223, .class_tid = 1, .hdr_sig_id = 6, @@ -12727,7 +13053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [484] = { + [496] = { .class_hid = BNXT_ULP_CLASS_HID_186ff, .class_tid = 1, .hdr_sig_id = 6, @@ -12746,7 +13072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [485] = { + [497] = { .class_hid = BNXT_ULP_CLASS_HID_9483, .class_tid = 1, .hdr_sig_id = 6, @@ -12764,7 +13090,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [486] = { + [498] = { .class_hid = BNXT_ULP_CLASS_HID_8fb7, .class_tid = 1, .hdr_sig_id = 6, @@ -12783,7 +13109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [487] = { + [499] = { .class_hid = BNXT_ULP_CLASS_HID_1a5b7, .class_tid = 1, .hdr_sig_id = 6, @@ -12803,7 +13129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [488] = { + [500] = { .class_hid = BNXT_ULP_CLASS_HID_1aa83, .class_tid = 1, .hdr_sig_id = 6, @@ -12822,7 +13148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [489] = { + [501] = { .class_hid = BNXT_ULP_CLASS_HID_b817, .class_tid = 1, .hdr_sig_id = 6, @@ -12841,7 +13167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [490] = { + [502] = { .class_hid = BNXT_ULP_CLASS_HID_b35b, .class_tid = 1, .hdr_sig_id = 6, @@ -12861,7 +13187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [491] = { + [503] = { .class_hid = BNXT_ULP_CLASS_HID_1c95b, .class_tid = 1, .hdr_sig_id = 6, @@ -12882,7 +13208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [492] = { + [504] = { .class_hid = BNXT_ULP_CLASS_HID_1ce17, .class_tid = 1, .hdr_sig_id = 6, @@ -12902,7 +13228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [493] = { + [505] = { .class_hid = BNXT_ULP_CLASS_HID_a3fb, .class_tid = 1, .hdr_sig_id = 6, @@ -12918,7 +13244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [494] = { + [506] = { .class_hid = BNXT_ULP_CLASS_HID_9f2f, .class_tid = 1, .hdr_sig_id = 6, @@ -12935,7 +13261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [495] = { + [507] = { .class_hid = BNXT_ULP_CLASS_HID_1b52f, .class_tid = 1, .hdr_sig_id = 6, @@ -12953,7 +13279,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [496] = { + [508] = { .class_hid = BNXT_ULP_CLASS_HID_1b9fb, .class_tid = 1, .hdr_sig_id = 6, @@ -12970,7 +13296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [497] = { + [509] = { .class_hid = BNXT_ULP_CLASS_HID_c78f, .class_tid = 1, .hdr_sig_id = 6, @@ -12987,7 +13313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [498] = { + [510] = { .class_hid = BNXT_ULP_CLASS_HID_c2b3, .class_tid = 1, .hdr_sig_id = 6, @@ -13005,7 +13331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [499] = { + [511] = { .class_hid = BNXT_ULP_CLASS_HID_1d8b3, .class_tid = 1, .hdr_sig_id = 6, @@ -13024,7 +13350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [500] = { + [512] = { .class_hid = BNXT_ULP_CLASS_HID_180b3, .class_tid = 1, .hdr_sig_id = 6, @@ -13042,7 +13368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [501] = { + [513] = { .class_hid = BNXT_ULP_CLASS_HID_8e47, .class_tid = 1, .hdr_sig_id = 6, @@ -13059,7 +13385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [502] = { + [514] = { .class_hid = BNXT_ULP_CLASS_HID_898b, .class_tid = 1, .hdr_sig_id = 6, @@ -13077,7 +13403,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [503] = { + [515] = { .class_hid = BNXT_ULP_CLASS_HID_19f8b, .class_tid = 1, .hdr_sig_id = 6, @@ -13096,7 +13422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [504] = { + [516] = { .class_hid = BNXT_ULP_CLASS_HID_1a447, .class_tid = 1, .hdr_sig_id = 6, @@ -13114,7 +13440,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [505] = { + [517] = { .class_hid = BNXT_ULP_CLASS_HID_b1eb, .class_tid = 1, .hdr_sig_id = 6, @@ -13132,7 +13458,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [506] = { + [518] = { .class_hid = BNXT_ULP_CLASS_HID_ad1f, .class_tid = 1, .hdr_sig_id = 6, @@ -13151,7 +13477,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [507] = { + [519] = { .class_hid = BNXT_ULP_CLASS_HID_1c31f, .class_tid = 1, .hdr_sig_id = 6, @@ -13171,7 +13497,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [508] = { + [520] = { .class_hid = BNXT_ULP_CLASS_HID_1c7eb, .class_tid = 1, .hdr_sig_id = 6, @@ -13190,7 +13516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [509] = { + [521] = { .class_hid = BNXT_ULP_CLASS_HID_9137, .class_tid = 1, .hdr_sig_id = 6, @@ -13206,7 +13532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [510] = { + [522] = { .class_hid = BNXT_ULP_CLASS_HID_8c7b, .class_tid = 1, .hdr_sig_id = 6, @@ -13223,7 +13549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [511] = { + [523] = { .class_hid = BNXT_ULP_CLASS_HID_1a27b, .class_tid = 1, .hdr_sig_id = 6, @@ -13241,7 +13567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [512] = { + [524] = { .class_hid = BNXT_ULP_CLASS_HID_1a737, .class_tid = 1, .hdr_sig_id = 6, @@ -13258,7 +13584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [513] = { + [525] = { .class_hid = BNXT_ULP_CLASS_HID_b4db, .class_tid = 1, .hdr_sig_id = 6, @@ -13275,7 +13601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [514] = { + [526] = { .class_hid = BNXT_ULP_CLASS_HID_b00f, .class_tid = 1, .hdr_sig_id = 6, @@ -13293,7 +13619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [515] = { + [527] = { .class_hid = BNXT_ULP_CLASS_HID_1c60f, .class_tid = 1, .hdr_sig_id = 6, @@ -13312,7 +13638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [516] = { + [528] = { .class_hid = BNXT_ULP_CLASS_HID_1cadb, .class_tid = 1, .hdr_sig_id = 6, @@ -13330,7 +13656,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [517] = { + [529] = { .class_hid = BNXT_ULP_CLASS_HID_8b0b, .class_tid = 1, .hdr_sig_id = 6, @@ -13345,7 +13671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [518] = { + [530] = { .class_hid = BNXT_ULP_CLASS_HID_863f, .class_tid = 1, .hdr_sig_id = 6, @@ -13361,7 +13687,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [519] = { + [531] = { .class_hid = BNXT_ULP_CLASS_HID_19c3f, .class_tid = 1, .hdr_sig_id = 6, @@ -13378,7 +13704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [520] = { + [532] = { .class_hid = BNXT_ULP_CLASS_HID_1a10b, .class_tid = 1, .hdr_sig_id = 6, @@ -13394,7 +13720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [521] = { + [533] = { .class_hid = BNXT_ULP_CLASS_HID_ae9f, .class_tid = 1, .hdr_sig_id = 6, @@ -13410,7 +13736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [522] = { + [534] = { .class_hid = BNXT_ULP_CLASS_HID_a9c3, .class_tid = 1, .hdr_sig_id = 6, @@ -13427,7 +13753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [523] = { + [535] = { .class_hid = BNXT_ULP_CLASS_HID_1bfc3, .class_tid = 1, .hdr_sig_id = 6, @@ -13445,7 +13771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [524] = { + [536] = { .class_hid = BNXT_ULP_CLASS_HID_1c49f, .class_tid = 1, .hdr_sig_id = 6, @@ -13462,7 +13788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [525] = { + [537] = { .class_hid = BNXT_ULP_CLASS_HID_2563, .class_tid = 1, .hdr_sig_id = 6, @@ -13478,7 +13804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [526] = { + [538] = { .class_hid = BNXT_ULP_CLASS_HID_2baf, .class_tid = 1, .hdr_sig_id = 6, @@ -13495,7 +13821,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [527] = { + [539] = { + .class_hid = BNXT_ULP_CLASS_HID_26d3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [540] = { .class_hid = BNXT_ULP_CLASS_HID_4f33, .class_tid = 1, .hdr_sig_id = 6, @@ -13513,7 +13857,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [528] = { + [541] = { + .class_hid = BNXT_ULP_CLASS_HID_4a67, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 89, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [542] = { .class_hid = BNXT_ULP_CLASS_HID_160b, .class_tid = 1, .hdr_sig_id = 6, @@ -13531,7 +13894,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [529] = { + [543] = { + .class_hid = BNXT_ULP_CLASS_HID_113f, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [544] = { .class_hid = BNXT_ULP_CLASS_HID_399f, .class_tid = 1, .hdr_sig_id = 6, @@ -13550,7 +13932,44 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [530] = { + [545] = { + .class_hid = BNXT_ULP_CLASS_HID_34c3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [546] = { + .class_hid = BNXT_ULP_CLASS_HID_2097, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [547] = { .class_hid = BNXT_ULP_CLASS_HID_48f7, .class_tid = 1, .hdr_sig_id = 6, @@ -13567,7 +13986,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [531] = { + [548] = { + .class_hid = BNXT_ULP_CLASS_HID_443b, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [549] = { .class_hid = BNXT_ULP_CLASS_HID_0fcf, .class_tid = 1, .hdr_sig_id = 6, @@ -13584,7 +14021,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [532] = { + [550] = { + .class_hid = BNXT_ULP_CLASS_HID_0af3, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [551] = { .class_hid = BNXT_ULP_CLASS_HID_3353, .class_tid = 1, .hdr_sig_id = 6, @@ -13602,7 +14057,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [533] = { + [552] = { + .class_hid = BNXT_ULP_CLASS_HID_2e87, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 90, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [553] = { .class_hid = BNXT_ULP_CLASS_HID_b68f, .class_tid = 1, .hdr_sig_id = 7, @@ -13621,7 +14095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [534] = { + [554] = { .class_hid = BNXT_ULP_CLASS_HID_b94f, .class_tid = 1, .hdr_sig_id = 7, @@ -13641,7 +14115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [535] = { + [555] = { .class_hid = BNXT_ULP_CLASS_HID_fc0f, .class_tid = 1, .hdr_sig_id = 7, @@ -13661,7 +14135,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [536] = { + [556] = { .class_hid = BNXT_ULP_CLASS_HID_fecf, .class_tid = 1, .hdr_sig_id = 7, @@ -13682,7 +14156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [537] = { + [557] = { .class_hid = BNXT_ULP_CLASS_HID_b1f3, .class_tid = 1, .hdr_sig_id = 7, @@ -13702,7 +14176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [538] = { + [558] = { .class_hid = BNXT_ULP_CLASS_HID_b4b3, .class_tid = 1, .hdr_sig_id = 7, @@ -13723,7 +14197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [539] = { + [559] = { .class_hid = BNXT_ULP_CLASS_HID_f773, .class_tid = 1, .hdr_sig_id = 7, @@ -13744,7 +14218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [540] = { + [560] = { .class_hid = BNXT_ULP_CLASS_HID_fa33, .class_tid = 1, .hdr_sig_id = 7, @@ -13766,7 +14240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [541] = { + [561] = { .class_hid = BNXT_ULP_CLASS_HID_1c7f3, .class_tid = 1, .hdr_sig_id = 7, @@ -13787,7 +14261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [542] = { + [562] = { .class_hid = BNXT_ULP_CLASS_HID_1eab3, .class_tid = 1, .hdr_sig_id = 7, @@ -13809,7 +14283,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [543] = { + [563] = { .class_hid = BNXT_ULP_CLASS_HID_1cd73, .class_tid = 1, .hdr_sig_id = 7, @@ -13831,7 +14305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [544] = { + [564] = { .class_hid = BNXT_ULP_CLASS_HID_1f033, .class_tid = 1, .hdr_sig_id = 7, @@ -13854,7 +14328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [545] = { + [565] = { .class_hid = BNXT_ULP_CLASS_HID_1cc8f, .class_tid = 1, .hdr_sig_id = 7, @@ -13874,7 +14348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [546] = { + [566] = { .class_hid = BNXT_ULP_CLASS_HID_1ef4f, .class_tid = 1, .hdr_sig_id = 7, @@ -13895,7 +14369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [547] = { + [567] = { .class_hid = BNXT_ULP_CLASS_HID_1d20f, .class_tid = 1, .hdr_sig_id = 7, @@ -13916,7 +14390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [548] = { + [568] = { .class_hid = BNXT_ULP_CLASS_HID_1f4cf, .class_tid = 1, .hdr_sig_id = 7, @@ -13938,7 +14412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [549] = { + [569] = { .class_hid = BNXT_ULP_CLASS_HID_da13, .class_tid = 1, .hdr_sig_id = 7, @@ -13958,7 +14432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [550] = { + [570] = { .class_hid = BNXT_ULP_CLASS_HID_a007, .class_tid = 1, .hdr_sig_id = 7, @@ -13979,7 +14453,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [551] = { + [571] = { .class_hid = BNXT_ULP_CLASS_HID_c2c7, .class_tid = 1, .hdr_sig_id = 7, @@ -14000,7 +14474,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [552] = { + [572] = { .class_hid = BNXT_ULP_CLASS_HID_e587, .class_tid = 1, .hdr_sig_id = 7, @@ -14022,7 +14496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [553] = { + [573] = { .class_hid = BNXT_ULP_CLASS_HID_d547, .class_tid = 1, .hdr_sig_id = 7, @@ -14043,7 +14517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [554] = { + [574] = { .class_hid = BNXT_ULP_CLASS_HID_f807, .class_tid = 1, .hdr_sig_id = 7, @@ -14065,7 +14539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [555] = { + [575] = { .class_hid = BNXT_ULP_CLASS_HID_dac7, .class_tid = 1, .hdr_sig_id = 7, @@ -14087,7 +14561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [556] = { + [576] = { .class_hid = BNXT_ULP_CLASS_HID_e0cb, .class_tid = 1, .hdr_sig_id = 7, @@ -14110,7 +14584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [557] = { + [577] = { .class_hid = BNXT_ULP_CLASS_HID_18e8b, .class_tid = 1, .hdr_sig_id = 7, @@ -14132,7 +14606,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [558] = { + [578] = { .class_hid = BNXT_ULP_CLASS_HID_1b14b, .class_tid = 1, .hdr_sig_id = 7, @@ -14155,7 +14629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [559] = { + [579] = { .class_hid = BNXT_ULP_CLASS_HID_1d40b, .class_tid = 1, .hdr_sig_id = 7, @@ -14178,7 +14652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [560] = { + [580] = { .class_hid = BNXT_ULP_CLASS_HID_1f6cb, .class_tid = 1, .hdr_sig_id = 7, @@ -14202,7 +14676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [561] = { + [581] = { .class_hid = BNXT_ULP_CLASS_HID_19347, .class_tid = 1, .hdr_sig_id = 7, @@ -14223,7 +14697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [562] = { + [582] = { .class_hid = BNXT_ULP_CLASS_HID_1b607, .class_tid = 1, .hdr_sig_id = 7, @@ -14245,7 +14719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [563] = { + [583] = { .class_hid = BNXT_ULP_CLASS_HID_1d8c7, .class_tid = 1, .hdr_sig_id = 7, @@ -14267,7 +14741,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [564] = { + [584] = { .class_hid = BNXT_ULP_CLASS_HID_1fb87, .class_tid = 1, .hdr_sig_id = 7, @@ -14290,7 +14764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [565] = { + [585] = { .class_hid = BNXT_ULP_CLASS_HID_a12b, .class_tid = 1, .hdr_sig_id = 7, @@ -14310,7 +14784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [566] = { + [586] = { .class_hid = BNXT_ULP_CLASS_HID_a3eb, .class_tid = 1, .hdr_sig_id = 7, @@ -14331,7 +14805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [567] = { + [587] = { .class_hid = BNXT_ULP_CLASS_HID_e6ab, .class_tid = 1, .hdr_sig_id = 7, @@ -14352,7 +14826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [568] = { + [588] = { .class_hid = BNXT_ULP_CLASS_HID_e96b, .class_tid = 1, .hdr_sig_id = 7, @@ -14374,7 +14848,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [569] = { + [589] = { .class_hid = BNXT_ULP_CLASS_HID_9c1f, .class_tid = 1, .hdr_sig_id = 7, @@ -14395,7 +14869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [570] = { + [590] = { .class_hid = BNXT_ULP_CLASS_HID_bedf, .class_tid = 1, .hdr_sig_id = 7, @@ -14417,7 +14891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [571] = { + [591] = { .class_hid = BNXT_ULP_CLASS_HID_e19f, .class_tid = 1, .hdr_sig_id = 7, @@ -14439,7 +14913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [572] = { + [592] = { .class_hid = BNXT_ULP_CLASS_HID_e45f, .class_tid = 1, .hdr_sig_id = 7, @@ -14462,7 +14936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [573] = { + [593] = { .class_hid = BNXT_ULP_CLASS_HID_1b21f, .class_tid = 1, .hdr_sig_id = 7, @@ -14484,7 +14958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [574] = { + [594] = { .class_hid = BNXT_ULP_CLASS_HID_1b4df, .class_tid = 1, .hdr_sig_id = 7, @@ -14507,7 +14981,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [575] = { + [595] = { .class_hid = BNXT_ULP_CLASS_HID_1f79f, .class_tid = 1, .hdr_sig_id = 7, @@ -14530,7 +15004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [576] = { + [596] = { .class_hid = BNXT_ULP_CLASS_HID_1fa5f, .class_tid = 1, .hdr_sig_id = 7, @@ -14554,7 +15028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [577] = { + [597] = { .class_hid = BNXT_ULP_CLASS_HID_1b72b, .class_tid = 1, .hdr_sig_id = 7, @@ -14575,7 +15049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [578] = { + [598] = { .class_hid = BNXT_ULP_CLASS_HID_1b9eb, .class_tid = 1, .hdr_sig_id = 7, @@ -14597,7 +15071,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [579] = { + [599] = { .class_hid = BNXT_ULP_CLASS_HID_1fcab, .class_tid = 1, .hdr_sig_id = 7, @@ -14619,7 +15093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [580] = { + [600] = { .class_hid = BNXT_ULP_CLASS_HID_1ff6b, .class_tid = 1, .hdr_sig_id = 7, @@ -14642,7 +15116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [581] = { + [601] = { .class_hid = BNXT_ULP_CLASS_HID_c4bf, .class_tid = 1, .hdr_sig_id = 7, @@ -14663,7 +15137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [582] = { + [602] = { .class_hid = BNXT_ULP_CLASS_HID_e77f, .class_tid = 1, .hdr_sig_id = 7, @@ -14685,7 +15159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [583] = { + [603] = { .class_hid = BNXT_ULP_CLASS_HID_ca3f, .class_tid = 1, .hdr_sig_id = 7, @@ -14707,7 +15181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [584] = { + [604] = { .class_hid = BNXT_ULP_CLASS_HID_ecff, .class_tid = 1, .hdr_sig_id = 7, @@ -14730,7 +15204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [585] = { + [605] = { .class_hid = BNXT_ULP_CLASS_HID_bfe3, .class_tid = 1, .hdr_sig_id = 7, @@ -14752,7 +15226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [586] = { + [606] = { .class_hid = BNXT_ULP_CLASS_HID_e2a3, .class_tid = 1, .hdr_sig_id = 7, @@ -14775,7 +15249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [587] = { + [607] = { .class_hid = BNXT_ULP_CLASS_HID_c563, .class_tid = 1, .hdr_sig_id = 7, @@ -14798,7 +15272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [588] = { + [608] = { .class_hid = BNXT_ULP_CLASS_HID_e823, .class_tid = 1, .hdr_sig_id = 7, @@ -14822,7 +15296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [589] = { + [609] = { .class_hid = BNXT_ULP_CLASS_HID_1d5e3, .class_tid = 1, .hdr_sig_id = 7, @@ -14845,7 +15319,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [590] = { + [610] = { .class_hid = BNXT_ULP_CLASS_HID_1f8a3, .class_tid = 1, .hdr_sig_id = 7, @@ -14869,7 +15343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [591] = { + [611] = { .class_hid = BNXT_ULP_CLASS_HID_1db63, .class_tid = 1, .hdr_sig_id = 7, @@ -14893,7 +15367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [592] = { + [612] = { .class_hid = BNXT_ULP_CLASS_HID_1e117, .class_tid = 1, .hdr_sig_id = 7, @@ -14918,7 +15392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [593] = { + [613] = { .class_hid = BNXT_ULP_CLASS_HID_1dabf, .class_tid = 1, .hdr_sig_id = 7, @@ -14940,7 +15414,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [594] = { + [614] = { .class_hid = BNXT_ULP_CLASS_HID_1a0a3, .class_tid = 1, .hdr_sig_id = 7, @@ -14963,7 +15437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [595] = { + [615] = { .class_hid = BNXT_ULP_CLASS_HID_1c363, .class_tid = 1, .hdr_sig_id = 7, @@ -14986,7 +15460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [596] = { + [616] = { .class_hid = BNXT_ULP_CLASS_HID_1e623, .class_tid = 1, .hdr_sig_id = 7, @@ -15010,7 +15484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [597] = { + [617] = { .class_hid = BNXT_ULP_CLASS_HID_b043, .class_tid = 1, .hdr_sig_id = 7, @@ -15028,7 +15502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [598] = { + [618] = { .class_hid = BNXT_ULP_CLASS_HID_b303, .class_tid = 1, .hdr_sig_id = 7, @@ -15047,7 +15521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [599] = { + [619] = { .class_hid = BNXT_ULP_CLASS_HID_f5c3, .class_tid = 1, .hdr_sig_id = 7, @@ -15066,7 +15540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [600] = { + [620] = { .class_hid = BNXT_ULP_CLASS_HID_f883, .class_tid = 1, .hdr_sig_id = 7, @@ -15086,7 +15560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [601] = { + [621] = { .class_hid = BNXT_ULP_CLASS_HID_abb7, .class_tid = 1, .hdr_sig_id = 7, @@ -15105,7 +15579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [602] = { + [622] = { .class_hid = BNXT_ULP_CLASS_HID_ae77, .class_tid = 1, .hdr_sig_id = 7, @@ -15125,7 +15599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [603] = { + [623] = { .class_hid = BNXT_ULP_CLASS_HID_f137, .class_tid = 1, .hdr_sig_id = 7, @@ -15145,7 +15619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [604] = { + [624] = { .class_hid = BNXT_ULP_CLASS_HID_f3f7, .class_tid = 1, .hdr_sig_id = 7, @@ -15166,7 +15640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [605] = { + [625] = { .class_hid = BNXT_ULP_CLASS_HID_1c1b7, .class_tid = 1, .hdr_sig_id = 7, @@ -15186,7 +15660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [606] = { + [626] = { .class_hid = BNXT_ULP_CLASS_HID_1e477, .class_tid = 1, .hdr_sig_id = 7, @@ -15207,7 +15681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [607] = { + [627] = { .class_hid = BNXT_ULP_CLASS_HID_1c737, .class_tid = 1, .hdr_sig_id = 7, @@ -15228,7 +15702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [608] = { + [628] = { .class_hid = BNXT_ULP_CLASS_HID_1e9f7, .class_tid = 1, .hdr_sig_id = 7, @@ -15250,7 +15724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [609] = { + [629] = { .class_hid = BNXT_ULP_CLASS_HID_1c643, .class_tid = 1, .hdr_sig_id = 7, @@ -15269,7 +15743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [610] = { + [630] = { .class_hid = BNXT_ULP_CLASS_HID_1e903, .class_tid = 1, .hdr_sig_id = 7, @@ -15289,7 +15763,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [611] = { + [631] = { .class_hid = BNXT_ULP_CLASS_HID_1cbc3, .class_tid = 1, .hdr_sig_id = 7, @@ -15309,7 +15783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [612] = { + [632] = { .class_hid = BNXT_ULP_CLASS_HID_1ee83, .class_tid = 1, .hdr_sig_id = 7, @@ -15330,7 +15804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [613] = { + [633] = { .class_hid = BNXT_ULP_CLASS_HID_d3d7, .class_tid = 1, .hdr_sig_id = 7, @@ -15349,7 +15823,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [614] = { + [634] = { .class_hid = BNXT_ULP_CLASS_HID_f697, .class_tid = 1, .hdr_sig_id = 7, @@ -15369,7 +15843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [615] = { + [635] = { .class_hid = BNXT_ULP_CLASS_HID_d957, .class_tid = 1, .hdr_sig_id = 7, @@ -15389,7 +15863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [616] = { + [636] = { .class_hid = BNXT_ULP_CLASS_HID_fc17, .class_tid = 1, .hdr_sig_id = 7, @@ -15410,7 +15884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [617] = { + [637] = { .class_hid = BNXT_ULP_CLASS_HID_cf1b, .class_tid = 1, .hdr_sig_id = 7, @@ -15430,7 +15904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [618] = { + [638] = { .class_hid = BNXT_ULP_CLASS_HID_f1db, .class_tid = 1, .hdr_sig_id = 7, @@ -15451,7 +15925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [619] = { + [639] = { .class_hid = BNXT_ULP_CLASS_HID_d49b, .class_tid = 1, .hdr_sig_id = 7, @@ -15472,7 +15946,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [620] = { + [640] = { .class_hid = BNXT_ULP_CLASS_HID_f75b, .class_tid = 1, .hdr_sig_id = 7, @@ -15494,7 +15968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [621] = { + [641] = { .class_hid = BNXT_ULP_CLASS_HID_1884f, .class_tid = 1, .hdr_sig_id = 7, @@ -15515,7 +15989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [622] = { + [642] = { .class_hid = BNXT_ULP_CLASS_HID_1ab0f, .class_tid = 1, .hdr_sig_id = 7, @@ -15537,7 +16011,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [623] = { + [643] = { .class_hid = BNXT_ULP_CLASS_HID_1cdcf, .class_tid = 1, .hdr_sig_id = 7, @@ -15559,7 +16033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [624] = { + [644] = { .class_hid = BNXT_ULP_CLASS_HID_1f08f, .class_tid = 1, .hdr_sig_id = 7, @@ -15582,7 +16056,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [625] = { + [645] = { .class_hid = BNXT_ULP_CLASS_HID_18d1b, .class_tid = 1, .hdr_sig_id = 7, @@ -15602,7 +16076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [626] = { + [646] = { .class_hid = BNXT_ULP_CLASS_HID_1afdb, .class_tid = 1, .hdr_sig_id = 7, @@ -15623,7 +16097,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [627] = { + [647] = { .class_hid = BNXT_ULP_CLASS_HID_1d29b, .class_tid = 1, .hdr_sig_id = 7, @@ -15644,7 +16118,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [628] = { + [648] = { .class_hid = BNXT_ULP_CLASS_HID_1f55b, .class_tid = 1, .hdr_sig_id = 7, @@ -15666,7 +16140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [629] = { + [649] = { .class_hid = BNXT_ULP_CLASS_HID_9aef, .class_tid = 1, .hdr_sig_id = 7, @@ -15685,7 +16159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [630] = { + [650] = { .class_hid = BNXT_ULP_CLASS_HID_bdaf, .class_tid = 1, .hdr_sig_id = 7, @@ -15705,7 +16179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [631] = { + [651] = { .class_hid = BNXT_ULP_CLASS_HID_e06f, .class_tid = 1, .hdr_sig_id = 7, @@ -15725,7 +16199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [632] = { + [652] = { .class_hid = BNXT_ULP_CLASS_HID_e32f, .class_tid = 1, .hdr_sig_id = 7, @@ -15746,7 +16220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [633] = { + [653] = { .class_hid = BNXT_ULP_CLASS_HID_95d3, .class_tid = 1, .hdr_sig_id = 7, @@ -15766,7 +16240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [634] = { + [654] = { .class_hid = BNXT_ULP_CLASS_HID_b893, .class_tid = 1, .hdr_sig_id = 7, @@ -15787,7 +16261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [635] = { + [655] = { .class_hid = BNXT_ULP_CLASS_HID_db53, .class_tid = 1, .hdr_sig_id = 7, @@ -15808,7 +16282,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [636] = { + [656] = { .class_hid = BNXT_ULP_CLASS_HID_fe13, .class_tid = 1, .hdr_sig_id = 7, @@ -15830,7 +16304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [637] = { + [657] = { .class_hid = BNXT_ULP_CLASS_HID_1abd3, .class_tid = 1, .hdr_sig_id = 7, @@ -15851,7 +16325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [638] = { + [658] = { .class_hid = BNXT_ULP_CLASS_HID_1ae93, .class_tid = 1, .hdr_sig_id = 7, @@ -15873,7 +16347,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [639] = { + [659] = { .class_hid = BNXT_ULP_CLASS_HID_1f153, .class_tid = 1, .hdr_sig_id = 7, @@ -15895,7 +16369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [640] = { + [660] = { .class_hid = BNXT_ULP_CLASS_HID_1f413, .class_tid = 1, .hdr_sig_id = 7, @@ -15918,7 +16392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [641] = { + [661] = { .class_hid = BNXT_ULP_CLASS_HID_1b0ef, .class_tid = 1, .hdr_sig_id = 7, @@ -15938,7 +16412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [642] = { + [662] = { .class_hid = BNXT_ULP_CLASS_HID_1b3af, .class_tid = 1, .hdr_sig_id = 7, @@ -15959,7 +16433,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [643] = { + [663] = { .class_hid = BNXT_ULP_CLASS_HID_1f66f, .class_tid = 1, .hdr_sig_id = 7, @@ -15980,7 +16454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [644] = { + [664] = { .class_hid = BNXT_ULP_CLASS_HID_1f92f, .class_tid = 1, .hdr_sig_id = 7, @@ -16002,7 +16476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [645] = { + [665] = { .class_hid = BNXT_ULP_CLASS_HID_be73, .class_tid = 1, .hdr_sig_id = 7, @@ -16022,7 +16496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [646] = { + [666] = { .class_hid = BNXT_ULP_CLASS_HID_e133, .class_tid = 1, .hdr_sig_id = 7, @@ -16043,7 +16517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [647] = { + [667] = { .class_hid = BNXT_ULP_CLASS_HID_c3f3, .class_tid = 1, .hdr_sig_id = 7, @@ -16064,7 +16538,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [648] = { + [668] = { .class_hid = BNXT_ULP_CLASS_HID_e6b3, .class_tid = 1, .hdr_sig_id = 7, @@ -16086,7 +16560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [649] = { + [669] = { .class_hid = BNXT_ULP_CLASS_HID_b9a7, .class_tid = 1, .hdr_sig_id = 7, @@ -16107,7 +16581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [650] = { + [670] = { .class_hid = BNXT_ULP_CLASS_HID_bc67, .class_tid = 1, .hdr_sig_id = 7, @@ -16129,7 +16603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [651] = { + [671] = { .class_hid = BNXT_ULP_CLASS_HID_ff27, .class_tid = 1, .hdr_sig_id = 7, @@ -16151,7 +16625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [652] = { + [672] = { .class_hid = BNXT_ULP_CLASS_HID_e1e7, .class_tid = 1, .hdr_sig_id = 7, @@ -16174,7 +16648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [653] = { + [673] = { .class_hid = BNXT_ULP_CLASS_HID_1cfa7, .class_tid = 1, .hdr_sig_id = 7, @@ -16196,7 +16670,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [654] = { + [674] = { .class_hid = BNXT_ULP_CLASS_HID_1f267, .class_tid = 1, .hdr_sig_id = 7, @@ -16219,7 +16693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [655] = { + [675] = { .class_hid = BNXT_ULP_CLASS_HID_1d527, .class_tid = 1, .hdr_sig_id = 7, @@ -16242,7 +16716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [656] = { + [676] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e7, .class_tid = 1, .hdr_sig_id = 7, @@ -16266,7 +16740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [657] = { + [677] = { .class_hid = BNXT_ULP_CLASS_HID_1d473, .class_tid = 1, .hdr_sig_id = 7, @@ -16287,7 +16761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [658] = { + [678] = { .class_hid = BNXT_ULP_CLASS_HID_1f733, .class_tid = 1, .hdr_sig_id = 7, @@ -16309,7 +16783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [659] = { + [679] = { .class_hid = BNXT_ULP_CLASS_HID_1d9f3, .class_tid = 1, .hdr_sig_id = 7, @@ -16331,7 +16805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [660] = { + [680] = { .class_hid = BNXT_ULP_CLASS_HID_1fcb3, .class_tid = 1, .hdr_sig_id = 7, @@ -16354,7 +16828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [661] = { + [681] = { .class_hid = BNXT_ULP_CLASS_HID_aa07, .class_tid = 1, .hdr_sig_id = 7, @@ -16372,7 +16846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [662] = { + [682] = { .class_hid = BNXT_ULP_CLASS_HID_acc7, .class_tid = 1, .hdr_sig_id = 7, @@ -16391,7 +16865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [663] = { + [683] = { .class_hid = BNXT_ULP_CLASS_HID_ef87, .class_tid = 1, .hdr_sig_id = 7, @@ -16410,7 +16884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [664] = { + [684] = { .class_hid = BNXT_ULP_CLASS_HID_f247, .class_tid = 1, .hdr_sig_id = 7, @@ -16430,7 +16904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [665] = { + [685] = { .class_hid = BNXT_ULP_CLASS_HID_a54b, .class_tid = 1, .hdr_sig_id = 7, @@ -16449,7 +16923,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [666] = { + [686] = { .class_hid = BNXT_ULP_CLASS_HID_a80b, .class_tid = 1, .hdr_sig_id = 7, @@ -16469,7 +16943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [667] = { + [687] = { .class_hid = BNXT_ULP_CLASS_HID_eacb, .class_tid = 1, .hdr_sig_id = 7, @@ -16489,7 +16963,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [668] = { + [688] = { .class_hid = BNXT_ULP_CLASS_HID_ed8b, .class_tid = 1, .hdr_sig_id = 7, @@ -16510,7 +16984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [669] = { + [689] = { .class_hid = BNXT_ULP_CLASS_HID_1bb4b, .class_tid = 1, .hdr_sig_id = 7, @@ -16530,7 +17004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [670] = { + [690] = { .class_hid = BNXT_ULP_CLASS_HID_1be0b, .class_tid = 1, .hdr_sig_id = 7, @@ -16551,7 +17025,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [671] = { + [691] = { .class_hid = BNXT_ULP_CLASS_HID_1c0cb, .class_tid = 1, .hdr_sig_id = 7, @@ -16572,7 +17046,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [672] = { + [692] = { .class_hid = BNXT_ULP_CLASS_HID_1e38b, .class_tid = 1, .hdr_sig_id = 7, @@ -16594,7 +17068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [673] = { + [693] = { .class_hid = BNXT_ULP_CLASS_HID_1c007, .class_tid = 1, .hdr_sig_id = 7, @@ -16613,7 +17087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [674] = { + [694] = { .class_hid = BNXT_ULP_CLASS_HID_1e2c7, .class_tid = 1, .hdr_sig_id = 7, @@ -16633,7 +17107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [675] = { + [695] = { .class_hid = BNXT_ULP_CLASS_HID_1c587, .class_tid = 1, .hdr_sig_id = 7, @@ -16653,7 +17127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [676] = { + [696] = { .class_hid = BNXT_ULP_CLASS_HID_1e847, .class_tid = 1, .hdr_sig_id = 7, @@ -16674,7 +17148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [677] = { + [697] = { .class_hid = BNXT_ULP_CLASS_HID_cdeb, .class_tid = 1, .hdr_sig_id = 7, @@ -16693,7 +17167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [678] = { + [698] = { .class_hid = BNXT_ULP_CLASS_HID_f0ab, .class_tid = 1, .hdr_sig_id = 7, @@ -16713,7 +17187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [679] = { + [699] = { .class_hid = BNXT_ULP_CLASS_HID_d36b, .class_tid = 1, .hdr_sig_id = 7, @@ -16733,7 +17207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [680] = { + [700] = { .class_hid = BNXT_ULP_CLASS_HID_f62b, .class_tid = 1, .hdr_sig_id = 7, @@ -16754,7 +17228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [681] = { + [701] = { .class_hid = BNXT_ULP_CLASS_HID_c8df, .class_tid = 1, .hdr_sig_id = 7, @@ -16774,7 +17248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [682] = { + [702] = { .class_hid = BNXT_ULP_CLASS_HID_eb9f, .class_tid = 1, .hdr_sig_id = 7, @@ -16795,7 +17269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [683] = { + [703] = { .class_hid = BNXT_ULP_CLASS_HID_ce5f, .class_tid = 1, .hdr_sig_id = 7, @@ -16816,7 +17290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [684] = { + [704] = { .class_hid = BNXT_ULP_CLASS_HID_f11f, .class_tid = 1, .hdr_sig_id = 7, @@ -16838,7 +17312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [685] = { + [705] = { .class_hid = BNXT_ULP_CLASS_HID_18203, .class_tid = 1, .hdr_sig_id = 7, @@ -16859,7 +17333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [686] = { + [706] = { .class_hid = BNXT_ULP_CLASS_HID_1a4c3, .class_tid = 1, .hdr_sig_id = 7, @@ -16881,7 +17355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [687] = { + [707] = { .class_hid = BNXT_ULP_CLASS_HID_1c783, .class_tid = 1, .hdr_sig_id = 7, @@ -16903,7 +17377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [688] = { + [708] = { .class_hid = BNXT_ULP_CLASS_HID_1ea43, .class_tid = 1, .hdr_sig_id = 7, @@ -16926,7 +17400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [689] = { + [709] = { .class_hid = BNXT_ULP_CLASS_HID_186df, .class_tid = 1, .hdr_sig_id = 7, @@ -16946,7 +17420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [690] = { + [710] = { .class_hid = BNXT_ULP_CLASS_HID_1a99f, .class_tid = 1, .hdr_sig_id = 7, @@ -16967,7 +17441,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [691] = { + [711] = { .class_hid = BNXT_ULP_CLASS_HID_1cc5f, .class_tid = 1, .hdr_sig_id = 7, @@ -16988,7 +17462,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [692] = { + [712] = { .class_hid = BNXT_ULP_CLASS_HID_1ef1f, .class_tid = 1, .hdr_sig_id = 7, @@ -17010,7 +17484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [693] = { + [713] = { .class_hid = BNXT_ULP_CLASS_HID_94a3, .class_tid = 1, .hdr_sig_id = 7, @@ -17029,7 +17503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [694] = { + [714] = { .class_hid = BNXT_ULP_CLASS_HID_b763, .class_tid = 1, .hdr_sig_id = 7, @@ -17049,7 +17523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [695] = { + [715] = { .class_hid = BNXT_ULP_CLASS_HID_da23, .class_tid = 1, .hdr_sig_id = 7, @@ -17069,7 +17543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [696] = { + [716] = { .class_hid = BNXT_ULP_CLASS_HID_fce3, .class_tid = 1, .hdr_sig_id = 7, @@ -17090,7 +17564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [697] = { + [717] = { .class_hid = BNXT_ULP_CLASS_HID_8f97, .class_tid = 1, .hdr_sig_id = 7, @@ -17110,7 +17584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [698] = { + [718] = { .class_hid = BNXT_ULP_CLASS_HID_b257, .class_tid = 1, .hdr_sig_id = 7, @@ -17131,7 +17605,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [699] = { + [719] = { .class_hid = BNXT_ULP_CLASS_HID_d517, .class_tid = 1, .hdr_sig_id = 7, @@ -17152,7 +17626,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [700] = { + [720] = { .class_hid = BNXT_ULP_CLASS_HID_f7d7, .class_tid = 1, .hdr_sig_id = 7, @@ -17174,7 +17648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [701] = { + [721] = { .class_hid = BNXT_ULP_CLASS_HID_1a597, .class_tid = 1, .hdr_sig_id = 7, @@ -17195,7 +17669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [702] = { + [722] = { .class_hid = BNXT_ULP_CLASS_HID_1a857, .class_tid = 1, .hdr_sig_id = 7, @@ -17217,7 +17691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [703] = { + [723] = { .class_hid = BNXT_ULP_CLASS_HID_1eb17, .class_tid = 1, .hdr_sig_id = 7, @@ -17239,7 +17713,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [704] = { + [724] = { .class_hid = BNXT_ULP_CLASS_HID_1edd7, .class_tid = 1, .hdr_sig_id = 7, @@ -17262,7 +17736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [705] = { + [725] = { .class_hid = BNXT_ULP_CLASS_HID_1aaa3, .class_tid = 1, .hdr_sig_id = 7, @@ -17282,7 +17756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [706] = { + [726] = { .class_hid = BNXT_ULP_CLASS_HID_1ad63, .class_tid = 1, .hdr_sig_id = 7, @@ -17303,7 +17777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [707] = { + [727] = { .class_hid = BNXT_ULP_CLASS_HID_1f023, .class_tid = 1, .hdr_sig_id = 7, @@ -17324,7 +17798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [708] = { + [728] = { .class_hid = BNXT_ULP_CLASS_HID_1f2e3, .class_tid = 1, .hdr_sig_id = 7, @@ -17346,7 +17820,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [709] = { + [729] = { .class_hid = BNXT_ULP_CLASS_HID_b837, .class_tid = 1, .hdr_sig_id = 7, @@ -17366,7 +17840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [710] = { + [730] = { .class_hid = BNXT_ULP_CLASS_HID_baf7, .class_tid = 1, .hdr_sig_id = 7, @@ -17387,7 +17861,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [711] = { + [731] = { .class_hid = BNXT_ULP_CLASS_HID_fdb7, .class_tid = 1, .hdr_sig_id = 7, @@ -17408,7 +17882,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [712] = { + [732] = { .class_hid = BNXT_ULP_CLASS_HID_e077, .class_tid = 1, .hdr_sig_id = 7, @@ -17430,7 +17904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [713] = { + [733] = { .class_hid = BNXT_ULP_CLASS_HID_b37b, .class_tid = 1, .hdr_sig_id = 7, @@ -17451,7 +17925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [714] = { + [734] = { .class_hid = BNXT_ULP_CLASS_HID_b63b, .class_tid = 1, .hdr_sig_id = 7, @@ -17473,7 +17947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [715] = { + [735] = { .class_hid = BNXT_ULP_CLASS_HID_f8fb, .class_tid = 1, .hdr_sig_id = 7, @@ -17495,7 +17969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [716] = { + [736] = { .class_hid = BNXT_ULP_CLASS_HID_fbbb, .class_tid = 1, .hdr_sig_id = 7, @@ -17518,7 +17992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [717] = { + [737] = { .class_hid = BNXT_ULP_CLASS_HID_1c97b, .class_tid = 1, .hdr_sig_id = 7, @@ -17540,7 +18014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [718] = { + [738] = { .class_hid = BNXT_ULP_CLASS_HID_1ec3b, .class_tid = 1, .hdr_sig_id = 7, @@ -17563,7 +18037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [719] = { + [739] = { .class_hid = BNXT_ULP_CLASS_HID_1cefb, .class_tid = 1, .hdr_sig_id = 7, @@ -17586,7 +18060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [720] = { + [740] = { .class_hid = BNXT_ULP_CLASS_HID_1f1bb, .class_tid = 1, .hdr_sig_id = 7, @@ -17610,7 +18084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [721] = { + [741] = { .class_hid = BNXT_ULP_CLASS_HID_1ce37, .class_tid = 1, .hdr_sig_id = 7, @@ -17631,7 +18105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [722] = { + [742] = { .class_hid = BNXT_ULP_CLASS_HID_1f0f7, .class_tid = 1, .hdr_sig_id = 7, @@ -17653,7 +18127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [723] = { + [743] = { .class_hid = BNXT_ULP_CLASS_HID_1d3b7, .class_tid = 1, .hdr_sig_id = 7, @@ -17675,7 +18149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [724] = { + [744] = { .class_hid = BNXT_ULP_CLASS_HID_1f677, .class_tid = 1, .hdr_sig_id = 7, @@ -17698,7 +18172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [725] = { + [745] = { .class_hid = BNXT_ULP_CLASS_HID_a3db, .class_tid = 1, .hdr_sig_id = 7, @@ -17715,7 +18189,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [726] = { + [746] = { .class_hid = BNXT_ULP_CLASS_HID_a69b, .class_tid = 1, .hdr_sig_id = 7, @@ -17733,7 +18207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [727] = { + [747] = { .class_hid = BNXT_ULP_CLASS_HID_e95b, .class_tid = 1, .hdr_sig_id = 7, @@ -17751,7 +18225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [728] = { + [748] = { .class_hid = BNXT_ULP_CLASS_HID_ec1b, .class_tid = 1, .hdr_sig_id = 7, @@ -17770,7 +18244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [729] = { + [749] = { .class_hid = BNXT_ULP_CLASS_HID_9f0f, .class_tid = 1, .hdr_sig_id = 7, @@ -17788,7 +18262,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [730] = { + [750] = { .class_hid = BNXT_ULP_CLASS_HID_a1cf, .class_tid = 1, .hdr_sig_id = 7, @@ -17807,7 +18281,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [731] = { + [751] = { .class_hid = BNXT_ULP_CLASS_HID_e48f, .class_tid = 1, .hdr_sig_id = 7, @@ -17826,7 +18300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [732] = { + [752] = { .class_hid = BNXT_ULP_CLASS_HID_e74f, .class_tid = 1, .hdr_sig_id = 7, @@ -17846,7 +18320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [733] = { + [753] = { .class_hid = BNXT_ULP_CLASS_HID_1b50f, .class_tid = 1, .hdr_sig_id = 7, @@ -17865,7 +18339,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [734] = { + [754] = { .class_hid = BNXT_ULP_CLASS_HID_1b7cf, .class_tid = 1, .hdr_sig_id = 7, @@ -17885,7 +18359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [735] = { + [755] = { .class_hid = BNXT_ULP_CLASS_HID_1fa8f, .class_tid = 1, .hdr_sig_id = 7, @@ -17905,7 +18379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [736] = { + [756] = { .class_hid = BNXT_ULP_CLASS_HID_1fd4f, .class_tid = 1, .hdr_sig_id = 7, @@ -17926,7 +18400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [737] = { + [757] = { .class_hid = BNXT_ULP_CLASS_HID_1b9db, .class_tid = 1, .hdr_sig_id = 7, @@ -17944,7 +18418,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [738] = { + [758] = { .class_hid = BNXT_ULP_CLASS_HID_1bc9b, .class_tid = 1, .hdr_sig_id = 7, @@ -17963,7 +18437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [739] = { + [759] = { .class_hid = BNXT_ULP_CLASS_HID_1ff5b, .class_tid = 1, .hdr_sig_id = 7, @@ -17982,7 +18456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [740] = { + [760] = { .class_hid = BNXT_ULP_CLASS_HID_1e21b, .class_tid = 1, .hdr_sig_id = 7, @@ -18002,7 +18476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [741] = { + [761] = { .class_hid = BNXT_ULP_CLASS_HID_c7af, .class_tid = 1, .hdr_sig_id = 7, @@ -18020,7 +18494,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [742] = { + [762] = { .class_hid = BNXT_ULP_CLASS_HID_ea6f, .class_tid = 1, .hdr_sig_id = 7, @@ -18039,7 +18513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [743] = { + [763] = { .class_hid = BNXT_ULP_CLASS_HID_cd2f, .class_tid = 1, .hdr_sig_id = 7, @@ -18058,7 +18532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [744] = { + [764] = { .class_hid = BNXT_ULP_CLASS_HID_efef, .class_tid = 1, .hdr_sig_id = 7, @@ -18078,7 +18552,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [745] = { + [765] = { .class_hid = BNXT_ULP_CLASS_HID_c293, .class_tid = 1, .hdr_sig_id = 7, @@ -18097,7 +18571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [746] = { + [766] = { .class_hid = BNXT_ULP_CLASS_HID_e553, .class_tid = 1, .hdr_sig_id = 7, @@ -18117,7 +18591,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [747] = { + [767] = { .class_hid = BNXT_ULP_CLASS_HID_c813, .class_tid = 1, .hdr_sig_id = 7, @@ -18137,7 +18611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [748] = { + [768] = { .class_hid = BNXT_ULP_CLASS_HID_ead3, .class_tid = 1, .hdr_sig_id = 7, @@ -18158,7 +18632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [749] = { + [769] = { .class_hid = BNXT_ULP_CLASS_HID_1d893, .class_tid = 1, .hdr_sig_id = 7, @@ -18178,7 +18652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [750] = { + [770] = { .class_hid = BNXT_ULP_CLASS_HID_1fb53, .class_tid = 1, .hdr_sig_id = 7, @@ -18199,7 +18673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [751] = { + [771] = { .class_hid = BNXT_ULP_CLASS_HID_1c147, .class_tid = 1, .hdr_sig_id = 7, @@ -18220,7 +18694,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [752] = { + [772] = { .class_hid = BNXT_ULP_CLASS_HID_1e407, .class_tid = 1, .hdr_sig_id = 7, @@ -18242,7 +18716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [753] = { + [773] = { .class_hid = BNXT_ULP_CLASS_HID_18093, .class_tid = 1, .hdr_sig_id = 7, @@ -18261,7 +18735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [754] = { + [774] = { .class_hid = BNXT_ULP_CLASS_HID_1a353, .class_tid = 1, .hdr_sig_id = 7, @@ -18281,7 +18755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [755] = { + [775] = { .class_hid = BNXT_ULP_CLASS_HID_1c613, .class_tid = 1, .hdr_sig_id = 7, @@ -18301,7 +18775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [756] = { + [776] = { .class_hid = BNXT_ULP_CLASS_HID_1e8d3, .class_tid = 1, .hdr_sig_id = 7, @@ -18322,7 +18796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [757] = { + [777] = { .class_hid = BNXT_ULP_CLASS_HID_8e67, .class_tid = 1, .hdr_sig_id = 7, @@ -18340,7 +18814,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [758] = { + [778] = { .class_hid = BNXT_ULP_CLASS_HID_b127, .class_tid = 1, .hdr_sig_id = 7, @@ -18359,7 +18833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [759] = { + [779] = { .class_hid = BNXT_ULP_CLASS_HID_d3e7, .class_tid = 1, .hdr_sig_id = 7, @@ -18378,7 +18852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [760] = { + [780] = { .class_hid = BNXT_ULP_CLASS_HID_f6a7, .class_tid = 1, .hdr_sig_id = 7, @@ -18398,7 +18872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [761] = { + [781] = { .class_hid = BNXT_ULP_CLASS_HID_89ab, .class_tid = 1, .hdr_sig_id = 7, @@ -18417,7 +18891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [762] = { + [782] = { .class_hid = BNXT_ULP_CLASS_HID_ac6b, .class_tid = 1, .hdr_sig_id = 7, @@ -18437,7 +18911,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [763] = { + [783] = { .class_hid = BNXT_ULP_CLASS_HID_cf2b, .class_tid = 1, .hdr_sig_id = 7, @@ -18457,7 +18931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [764] = { + [784] = { .class_hid = BNXT_ULP_CLASS_HID_f1eb, .class_tid = 1, .hdr_sig_id = 7, @@ -18478,7 +18952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [765] = { + [785] = { .class_hid = BNXT_ULP_CLASS_HID_19fab, .class_tid = 1, .hdr_sig_id = 7, @@ -18498,7 +18972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [766] = { + [786] = { .class_hid = BNXT_ULP_CLASS_HID_1a26b, .class_tid = 1, .hdr_sig_id = 7, @@ -18519,7 +18993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [767] = { + [787] = { .class_hid = BNXT_ULP_CLASS_HID_1e52b, .class_tid = 1, .hdr_sig_id = 7, @@ -18540,7 +19014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [768] = { + [788] = { .class_hid = BNXT_ULP_CLASS_HID_1e7eb, .class_tid = 1, .hdr_sig_id = 7, @@ -18562,7 +19036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [769] = { + [789] = { .class_hid = BNXT_ULP_CLASS_HID_1a467, .class_tid = 1, .hdr_sig_id = 7, @@ -18581,7 +19055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [770] = { + [790] = { .class_hid = BNXT_ULP_CLASS_HID_1a727, .class_tid = 1, .hdr_sig_id = 7, @@ -18601,7 +19075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [771] = { + [791] = { .class_hid = BNXT_ULP_CLASS_HID_1e9e7, .class_tid = 1, .hdr_sig_id = 7, @@ -18621,7 +19095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [772] = { + [792] = { .class_hid = BNXT_ULP_CLASS_HID_1eca7, .class_tid = 1, .hdr_sig_id = 7, @@ -18642,7 +19116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [773] = { + [793] = { .class_hid = BNXT_ULP_CLASS_HID_b1cb, .class_tid = 1, .hdr_sig_id = 7, @@ -18661,7 +19135,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [774] = { + [794] = { .class_hid = BNXT_ULP_CLASS_HID_b48b, .class_tid = 1, .hdr_sig_id = 7, @@ -18681,7 +19155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [775] = { + [795] = { .class_hid = BNXT_ULP_CLASS_HID_f74b, .class_tid = 1, .hdr_sig_id = 7, @@ -18701,7 +19175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [776] = { + [796] = { .class_hid = BNXT_ULP_CLASS_HID_fa0b, .class_tid = 1, .hdr_sig_id = 7, @@ -18722,7 +19196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [777] = { + [797] = { .class_hid = BNXT_ULP_CLASS_HID_ad3f, .class_tid = 1, .hdr_sig_id = 7, @@ -18742,7 +19216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [778] = { + [798] = { .class_hid = BNXT_ULP_CLASS_HID_afff, .class_tid = 1, .hdr_sig_id = 7, @@ -18763,7 +19237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [779] = { + [799] = { .class_hid = BNXT_ULP_CLASS_HID_f2bf, .class_tid = 1, .hdr_sig_id = 7, @@ -18784,7 +19258,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [780] = { + [800] = { .class_hid = BNXT_ULP_CLASS_HID_f57f, .class_tid = 1, .hdr_sig_id = 7, @@ -18806,7 +19280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [781] = { + [801] = { .class_hid = BNXT_ULP_CLASS_HID_1c33f, .class_tid = 1, .hdr_sig_id = 7, @@ -18827,7 +19301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [782] = { + [802] = { .class_hid = BNXT_ULP_CLASS_HID_1e5ff, .class_tid = 1, .hdr_sig_id = 7, @@ -18849,7 +19323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [783] = { + [803] = { .class_hid = BNXT_ULP_CLASS_HID_1c8bf, .class_tid = 1, .hdr_sig_id = 7, @@ -18871,7 +19345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [784] = { + [804] = { .class_hid = BNXT_ULP_CLASS_HID_1eb7f, .class_tid = 1, .hdr_sig_id = 7, @@ -18894,7 +19368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [785] = { + [805] = { .class_hid = BNXT_ULP_CLASS_HID_1c7cb, .class_tid = 1, .hdr_sig_id = 7, @@ -18914,7 +19388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [786] = { + [806] = { .class_hid = BNXT_ULP_CLASS_HID_1ea8b, .class_tid = 1, .hdr_sig_id = 7, @@ -18935,7 +19409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [787] = { + [807] = { .class_hid = BNXT_ULP_CLASS_HID_1cd4b, .class_tid = 1, .hdr_sig_id = 7, @@ -18956,7 +19430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [788] = { + [808] = { .class_hid = BNXT_ULP_CLASS_HID_1f00b, .class_tid = 1, .hdr_sig_id = 7, @@ -18978,7 +19452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [789] = { + [809] = { .class_hid = BNXT_ULP_CLASS_HID_9117, .class_tid = 1, .hdr_sig_id = 7, @@ -18995,7 +19469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [790] = { + [810] = { .class_hid = BNXT_ULP_CLASS_HID_b3d7, .class_tid = 1, .hdr_sig_id = 7, @@ -19013,7 +19487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [791] = { + [811] = { .class_hid = BNXT_ULP_CLASS_HID_d697, .class_tid = 1, .hdr_sig_id = 7, @@ -19031,7 +19505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [792] = { + [812] = { .class_hid = BNXT_ULP_CLASS_HID_f957, .class_tid = 1, .hdr_sig_id = 7, @@ -19050,7 +19524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [793] = { + [813] = { .class_hid = BNXT_ULP_CLASS_HID_8c5b, .class_tid = 1, .hdr_sig_id = 7, @@ -19068,7 +19542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [794] = { + [814] = { .class_hid = BNXT_ULP_CLASS_HID_af1b, .class_tid = 1, .hdr_sig_id = 7, @@ -19087,7 +19561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [795] = { + [815] = { .class_hid = BNXT_ULP_CLASS_HID_d1db, .class_tid = 1, .hdr_sig_id = 7, @@ -19106,7 +19580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [796] = { + [816] = { .class_hid = BNXT_ULP_CLASS_HID_f49b, .class_tid = 1, .hdr_sig_id = 7, @@ -19126,7 +19600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [797] = { + [817] = { .class_hid = BNXT_ULP_CLASS_HID_1a25b, .class_tid = 1, .hdr_sig_id = 7, @@ -19145,7 +19619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [798] = { + [818] = { .class_hid = BNXT_ULP_CLASS_HID_1a51b, .class_tid = 1, .hdr_sig_id = 7, @@ -19165,7 +19639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [799] = { + [819] = { .class_hid = BNXT_ULP_CLASS_HID_1e7db, .class_tid = 1, .hdr_sig_id = 7, @@ -19185,7 +19659,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [800] = { + [820] = { .class_hid = BNXT_ULP_CLASS_HID_1ea9b, .class_tid = 1, .hdr_sig_id = 7, @@ -19206,7 +19680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [801] = { + [821] = { .class_hid = BNXT_ULP_CLASS_HID_1a717, .class_tid = 1, .hdr_sig_id = 7, @@ -19224,7 +19698,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [802] = { + [822] = { .class_hid = BNXT_ULP_CLASS_HID_1a9d7, .class_tid = 1, .hdr_sig_id = 7, @@ -19243,7 +19717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [803] = { + [823] = { .class_hid = BNXT_ULP_CLASS_HID_1ec97, .class_tid = 1, .hdr_sig_id = 7, @@ -19262,7 +19736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [804] = { + [824] = { .class_hid = BNXT_ULP_CLASS_HID_1ef57, .class_tid = 1, .hdr_sig_id = 7, @@ -19282,7 +19756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [805] = { + [825] = { .class_hid = BNXT_ULP_CLASS_HID_b4fb, .class_tid = 1, .hdr_sig_id = 7, @@ -19300,7 +19774,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [806] = { + [826] = { .class_hid = BNXT_ULP_CLASS_HID_b7bb, .class_tid = 1, .hdr_sig_id = 7, @@ -19319,7 +19793,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [807] = { + [827] = { .class_hid = BNXT_ULP_CLASS_HID_fa7b, .class_tid = 1, .hdr_sig_id = 7, @@ -19338,7 +19812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [808] = { + [828] = { .class_hid = BNXT_ULP_CLASS_HID_fd3b, .class_tid = 1, .hdr_sig_id = 7, @@ -19358,7 +19832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [809] = { + [829] = { .class_hid = BNXT_ULP_CLASS_HID_b02f, .class_tid = 1, .hdr_sig_id = 7, @@ -19377,7 +19851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [810] = { + [830] = { .class_hid = BNXT_ULP_CLASS_HID_b2ef, .class_tid = 1, .hdr_sig_id = 7, @@ -19397,7 +19871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [811] = { + [831] = { .class_hid = BNXT_ULP_CLASS_HID_f5af, .class_tid = 1, .hdr_sig_id = 7, @@ -19417,7 +19891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [812] = { + [832] = { .class_hid = BNXT_ULP_CLASS_HID_f86f, .class_tid = 1, .hdr_sig_id = 7, @@ -19438,7 +19912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [813] = { + [833] = { .class_hid = BNXT_ULP_CLASS_HID_1c62f, .class_tid = 1, .hdr_sig_id = 7, @@ -19458,7 +19932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [814] = { + [834] = { .class_hid = BNXT_ULP_CLASS_HID_1e8ef, .class_tid = 1, .hdr_sig_id = 7, @@ -19479,7 +19953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [815] = { + [835] = { .class_hid = BNXT_ULP_CLASS_HID_1cbaf, .class_tid = 1, .hdr_sig_id = 7, @@ -19500,7 +19974,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [816] = { + [836] = { .class_hid = BNXT_ULP_CLASS_HID_1ee6f, .class_tid = 1, .hdr_sig_id = 7, @@ -19522,7 +19996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [817] = { + [837] = { .class_hid = BNXT_ULP_CLASS_HID_1cafb, .class_tid = 1, .hdr_sig_id = 7, @@ -19541,7 +20015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [818] = { + [838] = { .class_hid = BNXT_ULP_CLASS_HID_1edbb, .class_tid = 1, .hdr_sig_id = 7, @@ -19561,7 +20035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [819] = { + [839] = { .class_hid = BNXT_ULP_CLASS_HID_1d07b, .class_tid = 1, .hdr_sig_id = 7, @@ -19581,7 +20055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [820] = { + [840] = { .class_hid = BNXT_ULP_CLASS_HID_1f33b, .class_tid = 1, .hdr_sig_id = 7, @@ -19602,7 +20076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [821] = { + [841] = { .class_hid = BNXT_ULP_CLASS_HID_8b2b, .class_tid = 1, .hdr_sig_id = 7, @@ -19618,7 +20092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [822] = { + [842] = { .class_hid = BNXT_ULP_CLASS_HID_adeb, .class_tid = 1, .hdr_sig_id = 7, @@ -19635,7 +20109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [823] = { + [843] = { .class_hid = BNXT_ULP_CLASS_HID_d0ab, .class_tid = 1, .hdr_sig_id = 7, @@ -19652,7 +20126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [824] = { + [844] = { .class_hid = BNXT_ULP_CLASS_HID_f36b, .class_tid = 1, .hdr_sig_id = 7, @@ -19670,7 +20144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [825] = { + [845] = { .class_hid = BNXT_ULP_CLASS_HID_861f, .class_tid = 1, .hdr_sig_id = 7, @@ -19687,7 +20161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [826] = { + [846] = { .class_hid = BNXT_ULP_CLASS_HID_a8df, .class_tid = 1, .hdr_sig_id = 7, @@ -19705,7 +20179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [827] = { + [847] = { .class_hid = BNXT_ULP_CLASS_HID_cb9f, .class_tid = 1, .hdr_sig_id = 7, @@ -19723,7 +20197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [828] = { + [848] = { .class_hid = BNXT_ULP_CLASS_HID_ee5f, .class_tid = 1, .hdr_sig_id = 7, @@ -19742,7 +20216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [829] = { + [849] = { .class_hid = BNXT_ULP_CLASS_HID_19c1f, .class_tid = 1, .hdr_sig_id = 7, @@ -19760,7 +20234,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [830] = { + [850] = { .class_hid = BNXT_ULP_CLASS_HID_1bedf, .class_tid = 1, .hdr_sig_id = 7, @@ -19779,7 +20253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [831] = { + [851] = { .class_hid = BNXT_ULP_CLASS_HID_1e19f, .class_tid = 1, .hdr_sig_id = 7, @@ -19798,7 +20272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [832] = { + [852] = { .class_hid = BNXT_ULP_CLASS_HID_1e45f, .class_tid = 1, .hdr_sig_id = 7, @@ -19818,7 +20292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [833] = { + [853] = { .class_hid = BNXT_ULP_CLASS_HID_1a12b, .class_tid = 1, .hdr_sig_id = 7, @@ -19835,7 +20309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [834] = { + [854] = { .class_hid = BNXT_ULP_CLASS_HID_1a3eb, .class_tid = 1, .hdr_sig_id = 7, @@ -19853,7 +20327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [835] = { + [855] = { .class_hid = BNXT_ULP_CLASS_HID_1e6ab, .class_tid = 1, .hdr_sig_id = 7, @@ -19871,7 +20345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [836] = { + [856] = { .class_hid = BNXT_ULP_CLASS_HID_1e96b, .class_tid = 1, .hdr_sig_id = 7, @@ -19890,7 +20364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [837] = { + [857] = { .class_hid = BNXT_ULP_CLASS_HID_aebf, .class_tid = 1, .hdr_sig_id = 7, @@ -19907,7 +20381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [838] = { + [858] = { .class_hid = BNXT_ULP_CLASS_HID_b17f, .class_tid = 1, .hdr_sig_id = 7, @@ -19925,7 +20399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [839] = { + [859] = { .class_hid = BNXT_ULP_CLASS_HID_f43f, .class_tid = 1, .hdr_sig_id = 7, @@ -19943,7 +20417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [840] = { + [860] = { .class_hid = BNXT_ULP_CLASS_HID_f6ff, .class_tid = 1, .hdr_sig_id = 7, @@ -19962,7 +20436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [841] = { + [861] = { .class_hid = BNXT_ULP_CLASS_HID_a9e3, .class_tid = 1, .hdr_sig_id = 7, @@ -19980,7 +20454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [842] = { + [862] = { .class_hid = BNXT_ULP_CLASS_HID_aca3, .class_tid = 1, .hdr_sig_id = 7, @@ -19999,7 +20473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [843] = { + [863] = { .class_hid = BNXT_ULP_CLASS_HID_ef63, .class_tid = 1, .hdr_sig_id = 7, @@ -20018,7 +20492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [844] = { + [864] = { .class_hid = BNXT_ULP_CLASS_HID_f223, .class_tid = 1, .hdr_sig_id = 7, @@ -20038,7 +20512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [845] = { + [865] = { .class_hid = BNXT_ULP_CLASS_HID_1bfe3, .class_tid = 1, .hdr_sig_id = 7, @@ -20057,7 +20531,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [846] = { + [866] = { .class_hid = BNXT_ULP_CLASS_HID_1e2a3, .class_tid = 1, .hdr_sig_id = 7, @@ -20077,7 +20551,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [847] = { + [867] = { .class_hid = BNXT_ULP_CLASS_HID_1c563, .class_tid = 1, .hdr_sig_id = 7, @@ -20097,7 +20571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [848] = { + [868] = { .class_hid = BNXT_ULP_CLASS_HID_1e823, .class_tid = 1, .hdr_sig_id = 7, @@ -20118,7 +20592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [849] = { + [869] = { .class_hid = BNXT_ULP_CLASS_HID_1c4bf, .class_tid = 1, .hdr_sig_id = 7, @@ -20136,7 +20610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [850] = { + [870] = { .class_hid = BNXT_ULP_CLASS_HID_1e77f, .class_tid = 1, .hdr_sig_id = 7, @@ -20155,7 +20629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [851] = { + [871] = { .class_hid = BNXT_ULP_CLASS_HID_1ca3f, .class_tid = 1, .hdr_sig_id = 7, @@ -20174,7 +20648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [852] = { + [872] = { .class_hid = BNXT_ULP_CLASS_HID_1ecff, .class_tid = 1, .hdr_sig_id = 7, @@ -20194,7 +20668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [853] = { + [873] = { .class_hid = BNXT_ULP_CLASS_HID_2543, .class_tid = 1, .hdr_sig_id = 7, @@ -20211,7 +20685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [854] = { + [874] = { .class_hid = BNXT_ULP_CLASS_HID_2b8f, .class_tid = 1, .hdr_sig_id = 7, @@ -20229,7 +20703,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [855] = { + [875] = { + .class_hid = BNXT_ULP_CLASS_HID_26f3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [876] = { .class_hid = BNXT_ULP_CLASS_HID_4f13, .class_tid = 1, .hdr_sig_id = 7, @@ -20248,7 +20741,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [856] = { + [877] = { + .class_hid = BNXT_ULP_CLASS_HID_4a47, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [878] = { .class_hid = BNXT_ULP_CLASS_HID_162b, .class_tid = 1, .hdr_sig_id = 7, @@ -20267,7 +20780,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [857] = { + [879] = { + .class_hid = BNXT_ULP_CLASS_HID_111f, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [880] = { .class_hid = BNXT_ULP_CLASS_HID_39bf, .class_tid = 1, .hdr_sig_id = 7, @@ -20287,7 +20820,46 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [858] = { + [881] = { + .class_hid = BNXT_ULP_CLASS_HID_34e3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [882] = { + .class_hid = BNXT_ULP_CLASS_HID_20b7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [883] = { .class_hid = BNXT_ULP_CLASS_HID_48d7, .class_tid = 1, .hdr_sig_id = 7, @@ -20305,7 +20877,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [859] = { + [884] = { + .class_hid = BNXT_ULP_CLASS_HID_441b, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [885] = { .class_hid = BNXT_ULP_CLASS_HID_0fef, .class_tid = 1, .hdr_sig_id = 7, @@ -20323,7 +20914,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [860] = { + [886] = { + .class_hid = BNXT_ULP_CLASS_HID_0ad3, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [887] = { .class_hid = BNXT_ULP_CLASS_HID_3373, .class_tid = 1, .hdr_sig_id = 7, @@ -20342,7 +20952,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [861] = { + [888] = { + .class_hid = BNXT_ULP_CLASS_HID_2ea7, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 102, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [889] = { .class_hid = BNXT_ULP_CLASS_HID_b6ef, .class_tid = 1, .hdr_sig_id = 8, @@ -20361,7 +20991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [862] = { + [890] = { .class_hid = BNXT_ULP_CLASS_HID_b92f, .class_tid = 1, .hdr_sig_id = 8, @@ -20381,7 +21011,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [863] = { + [891] = { .class_hid = BNXT_ULP_CLASS_HID_fc6f, .class_tid = 1, .hdr_sig_id = 8, @@ -20401,7 +21031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [864] = { + [892] = { .class_hid = BNXT_ULP_CLASS_HID_feaf, .class_tid = 1, .hdr_sig_id = 8, @@ -20422,7 +21052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [865] = { + [893] = { .class_hid = BNXT_ULP_CLASS_HID_b193, .class_tid = 1, .hdr_sig_id = 8, @@ -20442,7 +21072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [866] = { + [894] = { .class_hid = BNXT_ULP_CLASS_HID_b4d3, .class_tid = 1, .hdr_sig_id = 8, @@ -20463,7 +21093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [867] = { + [895] = { .class_hid = BNXT_ULP_CLASS_HID_f713, .class_tid = 1, .hdr_sig_id = 8, @@ -20484,7 +21114,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [868] = { + [896] = { .class_hid = BNXT_ULP_CLASS_HID_fa53, .class_tid = 1, .hdr_sig_id = 8, @@ -20506,7 +21136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [869] = { + [897] = { .class_hid = BNXT_ULP_CLASS_HID_1c793, .class_tid = 1, .hdr_sig_id = 8, @@ -20527,7 +21157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [870] = { + [898] = { .class_hid = BNXT_ULP_CLASS_HID_1ead3, .class_tid = 1, .hdr_sig_id = 8, @@ -20549,7 +21179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [871] = { + [899] = { .class_hid = BNXT_ULP_CLASS_HID_1cd13, .class_tid = 1, .hdr_sig_id = 8, @@ -20571,7 +21201,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [872] = { + [900] = { .class_hid = BNXT_ULP_CLASS_HID_1f053, .class_tid = 1, .hdr_sig_id = 8, @@ -20594,7 +21224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [873] = { + [901] = { .class_hid = BNXT_ULP_CLASS_HID_1ccef, .class_tid = 1, .hdr_sig_id = 8, @@ -20614,7 +21244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [874] = { + [902] = { .class_hid = BNXT_ULP_CLASS_HID_1ef2f, .class_tid = 1, .hdr_sig_id = 8, @@ -20635,7 +21265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [875] = { + [903] = { .class_hid = BNXT_ULP_CLASS_HID_1d26f, .class_tid = 1, .hdr_sig_id = 8, @@ -20656,7 +21286,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [876] = { + [904] = { .class_hid = BNXT_ULP_CLASS_HID_1f4af, .class_tid = 1, .hdr_sig_id = 8, @@ -20678,7 +21308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [877] = { + [905] = { .class_hid = BNXT_ULP_CLASS_HID_da73, .class_tid = 1, .hdr_sig_id = 8, @@ -20698,7 +21328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [878] = { + [906] = { .class_hid = BNXT_ULP_CLASS_HID_a067, .class_tid = 1, .hdr_sig_id = 8, @@ -20719,7 +21349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [879] = { + [907] = { .class_hid = BNXT_ULP_CLASS_HID_c2a7, .class_tid = 1, .hdr_sig_id = 8, @@ -20740,7 +21370,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [880] = { + [908] = { .class_hid = BNXT_ULP_CLASS_HID_e5e7, .class_tid = 1, .hdr_sig_id = 8, @@ -20762,7 +21392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [881] = { + [909] = { .class_hid = BNXT_ULP_CLASS_HID_d527, .class_tid = 1, .hdr_sig_id = 8, @@ -20783,7 +21413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [882] = { + [910] = { .class_hid = BNXT_ULP_CLASS_HID_f867, .class_tid = 1, .hdr_sig_id = 8, @@ -20805,7 +21435,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [883] = { + [911] = { .class_hid = BNXT_ULP_CLASS_HID_daa7, .class_tid = 1, .hdr_sig_id = 8, @@ -20827,7 +21457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [884] = { + [912] = { .class_hid = BNXT_ULP_CLASS_HID_e0ab, .class_tid = 1, .hdr_sig_id = 8, @@ -20850,7 +21480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [885] = { + [913] = { .class_hid = BNXT_ULP_CLASS_HID_18eeb, .class_tid = 1, .hdr_sig_id = 8, @@ -20872,7 +21502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [886] = { + [914] = { .class_hid = BNXT_ULP_CLASS_HID_1b12b, .class_tid = 1, .hdr_sig_id = 8, @@ -20895,7 +21525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [887] = { + [915] = { .class_hid = BNXT_ULP_CLASS_HID_1d46b, .class_tid = 1, .hdr_sig_id = 8, @@ -20918,7 +21548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [888] = { + [916] = { .class_hid = BNXT_ULP_CLASS_HID_1f6ab, .class_tid = 1, .hdr_sig_id = 8, @@ -20942,7 +21572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [889] = { + [917] = { .class_hid = BNXT_ULP_CLASS_HID_19327, .class_tid = 1, .hdr_sig_id = 8, @@ -20963,7 +21593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [890] = { + [918] = { .class_hid = BNXT_ULP_CLASS_HID_1b667, .class_tid = 1, .hdr_sig_id = 8, @@ -20985,7 +21615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [891] = { + [919] = { .class_hid = BNXT_ULP_CLASS_HID_1d8a7, .class_tid = 1, .hdr_sig_id = 8, @@ -21007,7 +21637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [892] = { + [920] = { .class_hid = BNXT_ULP_CLASS_HID_1fbe7, .class_tid = 1, .hdr_sig_id = 8, @@ -21030,7 +21660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [893] = { + [921] = { .class_hid = BNXT_ULP_CLASS_HID_a14b, .class_tid = 1, .hdr_sig_id = 8, @@ -21050,7 +21680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [894] = { + [922] = { .class_hid = BNXT_ULP_CLASS_HID_a38b, .class_tid = 1, .hdr_sig_id = 8, @@ -21071,7 +21701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [895] = { + [923] = { .class_hid = BNXT_ULP_CLASS_HID_e6cb, .class_tid = 1, .hdr_sig_id = 8, @@ -21092,7 +21722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [896] = { + [924] = { .class_hid = BNXT_ULP_CLASS_HID_e90b, .class_tid = 1, .hdr_sig_id = 8, @@ -21114,7 +21744,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [897] = { + [925] = { .class_hid = BNXT_ULP_CLASS_HID_9c7f, .class_tid = 1, .hdr_sig_id = 8, @@ -21135,7 +21765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [898] = { + [926] = { .class_hid = BNXT_ULP_CLASS_HID_bebf, .class_tid = 1, .hdr_sig_id = 8, @@ -21157,7 +21787,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [899] = { + [927] = { .class_hid = BNXT_ULP_CLASS_HID_e1ff, .class_tid = 1, .hdr_sig_id = 8, @@ -21179,7 +21809,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [900] = { + [928] = { .class_hid = BNXT_ULP_CLASS_HID_e43f, .class_tid = 1, .hdr_sig_id = 8, @@ -21202,7 +21832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [901] = { + [929] = { .class_hid = BNXT_ULP_CLASS_HID_1b27f, .class_tid = 1, .hdr_sig_id = 8, @@ -21224,7 +21854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [902] = { + [930] = { .class_hid = BNXT_ULP_CLASS_HID_1b4bf, .class_tid = 1, .hdr_sig_id = 8, @@ -21247,7 +21877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [903] = { + [931] = { .class_hid = BNXT_ULP_CLASS_HID_1f7ff, .class_tid = 1, .hdr_sig_id = 8, @@ -21270,7 +21900,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [904] = { + [932] = { .class_hid = BNXT_ULP_CLASS_HID_1fa3f, .class_tid = 1, .hdr_sig_id = 8, @@ -21294,7 +21924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [905] = { + [933] = { .class_hid = BNXT_ULP_CLASS_HID_1b74b, .class_tid = 1, .hdr_sig_id = 8, @@ -21315,7 +21945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [906] = { + [934] = { .class_hid = BNXT_ULP_CLASS_HID_1b98b, .class_tid = 1, .hdr_sig_id = 8, @@ -21337,7 +21967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [907] = { + [935] = { .class_hid = BNXT_ULP_CLASS_HID_1fccb, .class_tid = 1, .hdr_sig_id = 8, @@ -21359,7 +21989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [908] = { + [936] = { .class_hid = BNXT_ULP_CLASS_HID_1ff0b, .class_tid = 1, .hdr_sig_id = 8, @@ -21382,7 +22012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [909] = { + [937] = { .class_hid = BNXT_ULP_CLASS_HID_c4df, .class_tid = 1, .hdr_sig_id = 8, @@ -21403,7 +22033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [910] = { + [938] = { .class_hid = BNXT_ULP_CLASS_HID_e71f, .class_tid = 1, .hdr_sig_id = 8, @@ -21425,7 +22055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [911] = { + [939] = { .class_hid = BNXT_ULP_CLASS_HID_ca5f, .class_tid = 1, .hdr_sig_id = 8, @@ -21447,7 +22077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [912] = { + [940] = { .class_hid = BNXT_ULP_CLASS_HID_ec9f, .class_tid = 1, .hdr_sig_id = 8, @@ -21470,7 +22100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [913] = { + [941] = { .class_hid = BNXT_ULP_CLASS_HID_bf83, .class_tid = 1, .hdr_sig_id = 8, @@ -21492,7 +22122,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [914] = { + [942] = { .class_hid = BNXT_ULP_CLASS_HID_e2c3, .class_tid = 1, .hdr_sig_id = 8, @@ -21515,7 +22145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [915] = { + [943] = { .class_hid = BNXT_ULP_CLASS_HID_c503, .class_tid = 1, .hdr_sig_id = 8, @@ -21538,7 +22168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [916] = { + [944] = { .class_hid = BNXT_ULP_CLASS_HID_e843, .class_tid = 1, .hdr_sig_id = 8, @@ -21562,7 +22192,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [917] = { + [945] = { .class_hid = BNXT_ULP_CLASS_HID_1d583, .class_tid = 1, .hdr_sig_id = 8, @@ -21585,7 +22215,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [918] = { + [946] = { .class_hid = BNXT_ULP_CLASS_HID_1f8c3, .class_tid = 1, .hdr_sig_id = 8, @@ -21609,7 +22239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [919] = { + [947] = { .class_hid = BNXT_ULP_CLASS_HID_1db03, .class_tid = 1, .hdr_sig_id = 8, @@ -21633,7 +22263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [920] = { + [948] = { .class_hid = BNXT_ULP_CLASS_HID_1e177, .class_tid = 1, .hdr_sig_id = 8, @@ -21658,7 +22288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [921] = { + [949] = { .class_hid = BNXT_ULP_CLASS_HID_1dadf, .class_tid = 1, .hdr_sig_id = 8, @@ -21680,7 +22310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [922] = { + [950] = { .class_hid = BNXT_ULP_CLASS_HID_1a0c3, .class_tid = 1, .hdr_sig_id = 8, @@ -21703,7 +22333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [923] = { + [951] = { .class_hid = BNXT_ULP_CLASS_HID_1c303, .class_tid = 1, .hdr_sig_id = 8, @@ -21726,7 +22356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [924] = { + [952] = { .class_hid = BNXT_ULP_CLASS_HID_1e643, .class_tid = 1, .hdr_sig_id = 8, @@ -21750,7 +22380,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [925] = { + [953] = { .class_hid = BNXT_ULP_CLASS_HID_b023, .class_tid = 1, .hdr_sig_id = 8, @@ -21768,7 +22398,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [926] = { + [954] = { .class_hid = BNXT_ULP_CLASS_HID_b363, .class_tid = 1, .hdr_sig_id = 8, @@ -21787,7 +22417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [927] = { + [955] = { .class_hid = BNXT_ULP_CLASS_HID_f5a3, .class_tid = 1, .hdr_sig_id = 8, @@ -21806,7 +22436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [928] = { + [956] = { .class_hid = BNXT_ULP_CLASS_HID_f8e3, .class_tid = 1, .hdr_sig_id = 8, @@ -21826,7 +22456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [929] = { + [957] = { .class_hid = BNXT_ULP_CLASS_HID_abd7, .class_tid = 1, .hdr_sig_id = 8, @@ -21845,7 +22475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [930] = { + [958] = { .class_hid = BNXT_ULP_CLASS_HID_ae17, .class_tid = 1, .hdr_sig_id = 8, @@ -21865,7 +22495,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [931] = { + [959] = { .class_hid = BNXT_ULP_CLASS_HID_f157, .class_tid = 1, .hdr_sig_id = 8, @@ -21885,7 +22515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [932] = { + [960] = { .class_hid = BNXT_ULP_CLASS_HID_f397, .class_tid = 1, .hdr_sig_id = 8, @@ -21906,7 +22536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [933] = { + [961] = { .class_hid = BNXT_ULP_CLASS_HID_1c1d7, .class_tid = 1, .hdr_sig_id = 8, @@ -21926,7 +22556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [934] = { + [962] = { .class_hid = BNXT_ULP_CLASS_HID_1e417, .class_tid = 1, .hdr_sig_id = 8, @@ -21947,7 +22577,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [935] = { + [963] = { .class_hid = BNXT_ULP_CLASS_HID_1c757, .class_tid = 1, .hdr_sig_id = 8, @@ -21968,7 +22598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [936] = { + [964] = { .class_hid = BNXT_ULP_CLASS_HID_1e997, .class_tid = 1, .hdr_sig_id = 8, @@ -21990,7 +22620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [937] = { + [965] = { .class_hid = BNXT_ULP_CLASS_HID_1c623, .class_tid = 1, .hdr_sig_id = 8, @@ -22009,7 +22639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [938] = { + [966] = { .class_hid = BNXT_ULP_CLASS_HID_1e963, .class_tid = 1, .hdr_sig_id = 8, @@ -22029,7 +22659,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [939] = { + [967] = { .class_hid = BNXT_ULP_CLASS_HID_1cba3, .class_tid = 1, .hdr_sig_id = 8, @@ -22049,7 +22679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [940] = { + [968] = { .class_hid = BNXT_ULP_CLASS_HID_1eee3, .class_tid = 1, .hdr_sig_id = 8, @@ -22070,7 +22700,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [941] = { + [969] = { .class_hid = BNXT_ULP_CLASS_HID_d3b7, .class_tid = 1, .hdr_sig_id = 8, @@ -22089,7 +22719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [942] = { + [970] = { .class_hid = BNXT_ULP_CLASS_HID_f6f7, .class_tid = 1, .hdr_sig_id = 8, @@ -22109,7 +22739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [943] = { + [971] = { .class_hid = BNXT_ULP_CLASS_HID_d937, .class_tid = 1, .hdr_sig_id = 8, @@ -22129,7 +22759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [944] = { + [972] = { .class_hid = BNXT_ULP_CLASS_HID_fc77, .class_tid = 1, .hdr_sig_id = 8, @@ -22150,7 +22780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [945] = { + [973] = { .class_hid = BNXT_ULP_CLASS_HID_cf7b, .class_tid = 1, .hdr_sig_id = 8, @@ -22170,7 +22800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [946] = { + [974] = { .class_hid = BNXT_ULP_CLASS_HID_f1bb, .class_tid = 1, .hdr_sig_id = 8, @@ -22191,7 +22821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [947] = { + [975] = { .class_hid = BNXT_ULP_CLASS_HID_d4fb, .class_tid = 1, .hdr_sig_id = 8, @@ -22212,7 +22842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [948] = { + [976] = { .class_hid = BNXT_ULP_CLASS_HID_f73b, .class_tid = 1, .hdr_sig_id = 8, @@ -22234,7 +22864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [949] = { + [977] = { .class_hid = BNXT_ULP_CLASS_HID_1882f, .class_tid = 1, .hdr_sig_id = 8, @@ -22255,7 +22885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [950] = { + [978] = { .class_hid = BNXT_ULP_CLASS_HID_1ab6f, .class_tid = 1, .hdr_sig_id = 8, @@ -22277,7 +22907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [951] = { + [979] = { .class_hid = BNXT_ULP_CLASS_HID_1cdaf, .class_tid = 1, .hdr_sig_id = 8, @@ -22299,7 +22929,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [952] = { + [980] = { .class_hid = BNXT_ULP_CLASS_HID_1f0ef, .class_tid = 1, .hdr_sig_id = 8, @@ -22322,7 +22952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [953] = { + [981] = { .class_hid = BNXT_ULP_CLASS_HID_18d7b, .class_tid = 1, .hdr_sig_id = 8, @@ -22342,7 +22972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [954] = { + [982] = { .class_hid = BNXT_ULP_CLASS_HID_1afbb, .class_tid = 1, .hdr_sig_id = 8, @@ -22363,7 +22993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [955] = { + [983] = { .class_hid = BNXT_ULP_CLASS_HID_1d2fb, .class_tid = 1, .hdr_sig_id = 8, @@ -22384,7 +23014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [956] = { + [984] = { .class_hid = BNXT_ULP_CLASS_HID_1f53b, .class_tid = 1, .hdr_sig_id = 8, @@ -22406,7 +23036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [957] = { + [985] = { .class_hid = BNXT_ULP_CLASS_HID_9a8f, .class_tid = 1, .hdr_sig_id = 8, @@ -22425,7 +23055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [958] = { + [986] = { .class_hid = BNXT_ULP_CLASS_HID_bdcf, .class_tid = 1, .hdr_sig_id = 8, @@ -22445,7 +23075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [959] = { + [987] = { .class_hid = BNXT_ULP_CLASS_HID_e00f, .class_tid = 1, .hdr_sig_id = 8, @@ -22465,7 +23095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [960] = { + [988] = { .class_hid = BNXT_ULP_CLASS_HID_e34f, .class_tid = 1, .hdr_sig_id = 8, @@ -22486,7 +23116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [961] = { + [989] = { .class_hid = BNXT_ULP_CLASS_HID_95b3, .class_tid = 1, .hdr_sig_id = 8, @@ -22506,7 +23136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [962] = { + [990] = { .class_hid = BNXT_ULP_CLASS_HID_b8f3, .class_tid = 1, .hdr_sig_id = 8, @@ -22527,7 +23157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [963] = { + [991] = { .class_hid = BNXT_ULP_CLASS_HID_db33, .class_tid = 1, .hdr_sig_id = 8, @@ -22548,7 +23178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [964] = { + [992] = { .class_hid = BNXT_ULP_CLASS_HID_fe73, .class_tid = 1, .hdr_sig_id = 8, @@ -22570,7 +23200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [965] = { + [993] = { .class_hid = BNXT_ULP_CLASS_HID_1abb3, .class_tid = 1, .hdr_sig_id = 8, @@ -22591,7 +23221,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [966] = { + [994] = { .class_hid = BNXT_ULP_CLASS_HID_1aef3, .class_tid = 1, .hdr_sig_id = 8, @@ -22613,7 +23243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [967] = { + [995] = { .class_hid = BNXT_ULP_CLASS_HID_1f133, .class_tid = 1, .hdr_sig_id = 8, @@ -22635,7 +23265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [968] = { + [996] = { .class_hid = BNXT_ULP_CLASS_HID_1f473, .class_tid = 1, .hdr_sig_id = 8, @@ -22658,7 +23288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [969] = { + [997] = { .class_hid = BNXT_ULP_CLASS_HID_1b08f, .class_tid = 1, .hdr_sig_id = 8, @@ -22678,7 +23308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [970] = { + [998] = { .class_hid = BNXT_ULP_CLASS_HID_1b3cf, .class_tid = 1, .hdr_sig_id = 8, @@ -22699,7 +23329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [971] = { + [999] = { .class_hid = BNXT_ULP_CLASS_HID_1f60f, .class_tid = 1, .hdr_sig_id = 8, @@ -22720,7 +23350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [972] = { + [1000] = { .class_hid = BNXT_ULP_CLASS_HID_1f94f, .class_tid = 1, .hdr_sig_id = 8, @@ -22742,7 +23372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [973] = { + [1001] = { .class_hid = BNXT_ULP_CLASS_HID_be13, .class_tid = 1, .hdr_sig_id = 8, @@ -22762,7 +23392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [974] = { + [1002] = { .class_hid = BNXT_ULP_CLASS_HID_e153, .class_tid = 1, .hdr_sig_id = 8, @@ -22783,7 +23413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [975] = { + [1003] = { .class_hid = BNXT_ULP_CLASS_HID_c393, .class_tid = 1, .hdr_sig_id = 8, @@ -22804,7 +23434,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [976] = { + [1004] = { .class_hid = BNXT_ULP_CLASS_HID_e6d3, .class_tid = 1, .hdr_sig_id = 8, @@ -22826,7 +23456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [977] = { + [1005] = { .class_hid = BNXT_ULP_CLASS_HID_b9c7, .class_tid = 1, .hdr_sig_id = 8, @@ -22847,7 +23477,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [978] = { + [1006] = { .class_hid = BNXT_ULP_CLASS_HID_bc07, .class_tid = 1, .hdr_sig_id = 8, @@ -22869,7 +23499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [979] = { + [1007] = { .class_hid = BNXT_ULP_CLASS_HID_ff47, .class_tid = 1, .hdr_sig_id = 8, @@ -22891,7 +23521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [980] = { + [1008] = { .class_hid = BNXT_ULP_CLASS_HID_e187, .class_tid = 1, .hdr_sig_id = 8, @@ -22914,7 +23544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [981] = { + [1009] = { .class_hid = BNXT_ULP_CLASS_HID_1cfc7, .class_tid = 1, .hdr_sig_id = 8, @@ -22936,7 +23566,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [982] = { + [1010] = { .class_hid = BNXT_ULP_CLASS_HID_1f207, .class_tid = 1, .hdr_sig_id = 8, @@ -22959,7 +23589,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [983] = { + [1011] = { .class_hid = BNXT_ULP_CLASS_HID_1d547, .class_tid = 1, .hdr_sig_id = 8, @@ -22982,7 +23612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [984] = { + [1012] = { .class_hid = BNXT_ULP_CLASS_HID_1f787, .class_tid = 1, .hdr_sig_id = 8, @@ -23006,7 +23636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [985] = { + [1013] = { .class_hid = BNXT_ULP_CLASS_HID_1d413, .class_tid = 1, .hdr_sig_id = 8, @@ -23027,7 +23657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [986] = { + [1014] = { .class_hid = BNXT_ULP_CLASS_HID_1f753, .class_tid = 1, .hdr_sig_id = 8, @@ -23049,7 +23679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [987] = { + [1015] = { .class_hid = BNXT_ULP_CLASS_HID_1d993, .class_tid = 1, .hdr_sig_id = 8, @@ -23071,7 +23701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [988] = { + [1016] = { .class_hid = BNXT_ULP_CLASS_HID_1fcd3, .class_tid = 1, .hdr_sig_id = 8, @@ -23094,7 +23724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [989] = { + [1017] = { .class_hid = BNXT_ULP_CLASS_HID_aa67, .class_tid = 1, .hdr_sig_id = 8, @@ -23112,7 +23742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [990] = { + [1018] = { .class_hid = BNXT_ULP_CLASS_HID_aca7, .class_tid = 1, .hdr_sig_id = 8, @@ -23131,7 +23761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [991] = { + [1019] = { .class_hid = BNXT_ULP_CLASS_HID_efe7, .class_tid = 1, .hdr_sig_id = 8, @@ -23150,7 +23780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [992] = { + [1020] = { .class_hid = BNXT_ULP_CLASS_HID_f227, .class_tid = 1, .hdr_sig_id = 8, @@ -23170,7 +23800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [993] = { + [1021] = { .class_hid = BNXT_ULP_CLASS_HID_a52b, .class_tid = 1, .hdr_sig_id = 8, @@ -23189,7 +23819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [994] = { + [1022] = { .class_hid = BNXT_ULP_CLASS_HID_a86b, .class_tid = 1, .hdr_sig_id = 8, @@ -23209,7 +23839,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [995] = { + [1023] = { .class_hid = BNXT_ULP_CLASS_HID_eaab, .class_tid = 1, .hdr_sig_id = 8, @@ -23229,7 +23859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [996] = { + [1024] = { .class_hid = BNXT_ULP_CLASS_HID_edeb, .class_tid = 1, .hdr_sig_id = 8, @@ -23250,7 +23880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [997] = { + [1025] = { .class_hid = BNXT_ULP_CLASS_HID_1bb2b, .class_tid = 1, .hdr_sig_id = 8, @@ -23270,7 +23900,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [998] = { + [1026] = { .class_hid = BNXT_ULP_CLASS_HID_1be6b, .class_tid = 1, .hdr_sig_id = 8, @@ -23291,7 +23921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [999] = { + [1027] = { .class_hid = BNXT_ULP_CLASS_HID_1c0ab, .class_tid = 1, .hdr_sig_id = 8, @@ -23312,7 +23942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1000] = { + [1028] = { .class_hid = BNXT_ULP_CLASS_HID_1e3eb, .class_tid = 1, .hdr_sig_id = 8, @@ -23334,7 +23964,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1001] = { + [1029] = { .class_hid = BNXT_ULP_CLASS_HID_1c067, .class_tid = 1, .hdr_sig_id = 8, @@ -23353,7 +23983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1002] = { + [1030] = { .class_hid = BNXT_ULP_CLASS_HID_1e2a7, .class_tid = 1, .hdr_sig_id = 8, @@ -23373,7 +24003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1003] = { + [1031] = { .class_hid = BNXT_ULP_CLASS_HID_1c5e7, .class_tid = 1, .hdr_sig_id = 8, @@ -23393,7 +24023,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1004] = { + [1032] = { .class_hid = BNXT_ULP_CLASS_HID_1e827, .class_tid = 1, .hdr_sig_id = 8, @@ -23414,7 +24044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1005] = { + [1033] = { .class_hid = BNXT_ULP_CLASS_HID_cd8b, .class_tid = 1, .hdr_sig_id = 8, @@ -23433,7 +24063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1006] = { + [1034] = { .class_hid = BNXT_ULP_CLASS_HID_f0cb, .class_tid = 1, .hdr_sig_id = 8, @@ -23453,7 +24083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1007] = { + [1035] = { .class_hid = BNXT_ULP_CLASS_HID_d30b, .class_tid = 1, .hdr_sig_id = 8, @@ -23473,7 +24103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1008] = { + [1036] = { .class_hid = BNXT_ULP_CLASS_HID_f64b, .class_tid = 1, .hdr_sig_id = 8, @@ -23494,7 +24124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1009] = { + [1037] = { .class_hid = BNXT_ULP_CLASS_HID_c8bf, .class_tid = 1, .hdr_sig_id = 8, @@ -23514,7 +24144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1010] = { + [1038] = { .class_hid = BNXT_ULP_CLASS_HID_ebff, .class_tid = 1, .hdr_sig_id = 8, @@ -23535,7 +24165,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1011] = { + [1039] = { .class_hid = BNXT_ULP_CLASS_HID_ce3f, .class_tid = 1, .hdr_sig_id = 8, @@ -23556,7 +24186,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1012] = { + [1040] = { .class_hid = BNXT_ULP_CLASS_HID_f17f, .class_tid = 1, .hdr_sig_id = 8, @@ -23578,7 +24208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1013] = { + [1041] = { .class_hid = BNXT_ULP_CLASS_HID_18263, .class_tid = 1, .hdr_sig_id = 8, @@ -23599,7 +24229,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1014] = { + [1042] = { .class_hid = BNXT_ULP_CLASS_HID_1a4a3, .class_tid = 1, .hdr_sig_id = 8, @@ -23621,7 +24251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1015] = { + [1043] = { .class_hid = BNXT_ULP_CLASS_HID_1c7e3, .class_tid = 1, .hdr_sig_id = 8, @@ -23643,7 +24273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1016] = { + [1044] = { .class_hid = BNXT_ULP_CLASS_HID_1ea23, .class_tid = 1, .hdr_sig_id = 8, @@ -23666,7 +24296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1017] = { + [1045] = { .class_hid = BNXT_ULP_CLASS_HID_186bf, .class_tid = 1, .hdr_sig_id = 8, @@ -23686,7 +24316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1018] = { + [1046] = { .class_hid = BNXT_ULP_CLASS_HID_1a9ff, .class_tid = 1, .hdr_sig_id = 8, @@ -23707,7 +24337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1019] = { + [1047] = { .class_hid = BNXT_ULP_CLASS_HID_1cc3f, .class_tid = 1, .hdr_sig_id = 8, @@ -23728,7 +24358,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1020] = { + [1048] = { .class_hid = BNXT_ULP_CLASS_HID_1ef7f, .class_tid = 1, .hdr_sig_id = 8, @@ -23750,7 +24380,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1021] = { + [1049] = { .class_hid = BNXT_ULP_CLASS_HID_94c3, .class_tid = 1, .hdr_sig_id = 8, @@ -23769,7 +24399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1022] = { + [1050] = { .class_hid = BNXT_ULP_CLASS_HID_b703, .class_tid = 1, .hdr_sig_id = 8, @@ -23789,7 +24419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1023] = { + [1051] = { .class_hid = BNXT_ULP_CLASS_HID_da43, .class_tid = 1, .hdr_sig_id = 8, @@ -23809,7 +24439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1024] = { + [1052] = { .class_hid = BNXT_ULP_CLASS_HID_fc83, .class_tid = 1, .hdr_sig_id = 8, @@ -23830,7 +24460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1025] = { + [1053] = { .class_hid = BNXT_ULP_CLASS_HID_8ff7, .class_tid = 1, .hdr_sig_id = 8, @@ -23850,7 +24480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1026] = { + [1054] = { .class_hid = BNXT_ULP_CLASS_HID_b237, .class_tid = 1, .hdr_sig_id = 8, @@ -23871,7 +24501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1027] = { + [1055] = { .class_hid = BNXT_ULP_CLASS_HID_d577, .class_tid = 1, .hdr_sig_id = 8, @@ -23892,7 +24522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1028] = { + [1056] = { .class_hid = BNXT_ULP_CLASS_HID_f7b7, .class_tid = 1, .hdr_sig_id = 8, @@ -23914,7 +24544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1029] = { + [1057] = { .class_hid = BNXT_ULP_CLASS_HID_1a5f7, .class_tid = 1, .hdr_sig_id = 8, @@ -23935,7 +24565,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1030] = { + [1058] = { .class_hid = BNXT_ULP_CLASS_HID_1a837, .class_tid = 1, .hdr_sig_id = 8, @@ -23957,7 +24587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1031] = { + [1059] = { .class_hid = BNXT_ULP_CLASS_HID_1eb77, .class_tid = 1, .hdr_sig_id = 8, @@ -23979,7 +24609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1032] = { + [1060] = { .class_hid = BNXT_ULP_CLASS_HID_1edb7, .class_tid = 1, .hdr_sig_id = 8, @@ -24002,7 +24632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1033] = { + [1061] = { .class_hid = BNXT_ULP_CLASS_HID_1aac3, .class_tid = 1, .hdr_sig_id = 8, @@ -24022,7 +24652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1034] = { + [1062] = { .class_hid = BNXT_ULP_CLASS_HID_1ad03, .class_tid = 1, .hdr_sig_id = 8, @@ -24043,7 +24673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1035] = { + [1063] = { .class_hid = BNXT_ULP_CLASS_HID_1f043, .class_tid = 1, .hdr_sig_id = 8, @@ -24064,7 +24694,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1036] = { + [1064] = { .class_hid = BNXT_ULP_CLASS_HID_1f283, .class_tid = 1, .hdr_sig_id = 8, @@ -24086,7 +24716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1037] = { + [1065] = { .class_hid = BNXT_ULP_CLASS_HID_b857, .class_tid = 1, .hdr_sig_id = 8, @@ -24106,7 +24736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1038] = { + [1066] = { .class_hid = BNXT_ULP_CLASS_HID_ba97, .class_tid = 1, .hdr_sig_id = 8, @@ -24127,7 +24757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1039] = { + [1067] = { .class_hid = BNXT_ULP_CLASS_HID_fdd7, .class_tid = 1, .hdr_sig_id = 8, @@ -24148,7 +24778,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1040] = { + [1068] = { .class_hid = BNXT_ULP_CLASS_HID_e017, .class_tid = 1, .hdr_sig_id = 8, @@ -24170,7 +24800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1041] = { + [1069] = { .class_hid = BNXT_ULP_CLASS_HID_b31b, .class_tid = 1, .hdr_sig_id = 8, @@ -24191,7 +24821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1042] = { + [1070] = { .class_hid = BNXT_ULP_CLASS_HID_b65b, .class_tid = 1, .hdr_sig_id = 8, @@ -24213,7 +24843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1043] = { + [1071] = { .class_hid = BNXT_ULP_CLASS_HID_f89b, .class_tid = 1, .hdr_sig_id = 8, @@ -24235,7 +24865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1044] = { + [1072] = { .class_hid = BNXT_ULP_CLASS_HID_fbdb, .class_tid = 1, .hdr_sig_id = 8, @@ -24258,7 +24888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1045] = { + [1073] = { .class_hid = BNXT_ULP_CLASS_HID_1c91b, .class_tid = 1, .hdr_sig_id = 8, @@ -24280,7 +24910,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1046] = { + [1074] = { .class_hid = BNXT_ULP_CLASS_HID_1ec5b, .class_tid = 1, .hdr_sig_id = 8, @@ -24303,7 +24933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1047] = { + [1075] = { .class_hid = BNXT_ULP_CLASS_HID_1ce9b, .class_tid = 1, .hdr_sig_id = 8, @@ -24326,7 +24956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1048] = { + [1076] = { .class_hid = BNXT_ULP_CLASS_HID_1f1db, .class_tid = 1, .hdr_sig_id = 8, @@ -24350,7 +24980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1049] = { + [1077] = { .class_hid = BNXT_ULP_CLASS_HID_1ce57, .class_tid = 1, .hdr_sig_id = 8, @@ -24371,7 +25001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1050] = { + [1078] = { .class_hid = BNXT_ULP_CLASS_HID_1f097, .class_tid = 1, .hdr_sig_id = 8, @@ -24393,7 +25023,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1051] = { + [1079] = { .class_hid = BNXT_ULP_CLASS_HID_1d3d7, .class_tid = 1, .hdr_sig_id = 8, @@ -24415,7 +25045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1052] = { + [1080] = { .class_hid = BNXT_ULP_CLASS_HID_1f617, .class_tid = 1, .hdr_sig_id = 8, @@ -24438,7 +25068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1053] = { + [1081] = { .class_hid = BNXT_ULP_CLASS_HID_a3bb, .class_tid = 1, .hdr_sig_id = 8, @@ -24455,7 +25085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1054] = { + [1082] = { .class_hid = BNXT_ULP_CLASS_HID_a6fb, .class_tid = 1, .hdr_sig_id = 8, @@ -24473,7 +25103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1055] = { + [1083] = { .class_hid = BNXT_ULP_CLASS_HID_e93b, .class_tid = 1, .hdr_sig_id = 8, @@ -24491,7 +25121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1056] = { + [1084] = { .class_hid = BNXT_ULP_CLASS_HID_ec7b, .class_tid = 1, .hdr_sig_id = 8, @@ -24510,7 +25140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1057] = { + [1085] = { .class_hid = BNXT_ULP_CLASS_HID_9f6f, .class_tid = 1, .hdr_sig_id = 8, @@ -24528,7 +25158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1058] = { + [1086] = { .class_hid = BNXT_ULP_CLASS_HID_a1af, .class_tid = 1, .hdr_sig_id = 8, @@ -24547,7 +25177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1059] = { + [1087] = { .class_hid = BNXT_ULP_CLASS_HID_e4ef, .class_tid = 1, .hdr_sig_id = 8, @@ -24566,7 +25196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1060] = { + [1088] = { .class_hid = BNXT_ULP_CLASS_HID_e72f, .class_tid = 1, .hdr_sig_id = 8, @@ -24586,7 +25216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1061] = { + [1089] = { .class_hid = BNXT_ULP_CLASS_HID_1b56f, .class_tid = 1, .hdr_sig_id = 8, @@ -24605,7 +25235,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1062] = { + [1090] = { .class_hid = BNXT_ULP_CLASS_HID_1b7af, .class_tid = 1, .hdr_sig_id = 8, @@ -24625,7 +25255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1063] = { + [1091] = { .class_hid = BNXT_ULP_CLASS_HID_1faef, .class_tid = 1, .hdr_sig_id = 8, @@ -24645,7 +25275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1064] = { + [1092] = { .class_hid = BNXT_ULP_CLASS_HID_1fd2f, .class_tid = 1, .hdr_sig_id = 8, @@ -24666,7 +25296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1065] = { + [1093] = { .class_hid = BNXT_ULP_CLASS_HID_1b9bb, .class_tid = 1, .hdr_sig_id = 8, @@ -24684,7 +25314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1066] = { + [1094] = { .class_hid = BNXT_ULP_CLASS_HID_1bcfb, .class_tid = 1, .hdr_sig_id = 8, @@ -24703,7 +25333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1067] = { + [1095] = { .class_hid = BNXT_ULP_CLASS_HID_1ff3b, .class_tid = 1, .hdr_sig_id = 8, @@ -24722,7 +25352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1068] = { + [1096] = { .class_hid = BNXT_ULP_CLASS_HID_1e27b, .class_tid = 1, .hdr_sig_id = 8, @@ -24742,7 +25372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1069] = { + [1097] = { .class_hid = BNXT_ULP_CLASS_HID_c7cf, .class_tid = 1, .hdr_sig_id = 8, @@ -24760,7 +25390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1070] = { + [1098] = { .class_hid = BNXT_ULP_CLASS_HID_ea0f, .class_tid = 1, .hdr_sig_id = 8, @@ -24779,7 +25409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1071] = { + [1099] = { .class_hid = BNXT_ULP_CLASS_HID_cd4f, .class_tid = 1, .hdr_sig_id = 8, @@ -24798,7 +25428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1072] = { + [1100] = { .class_hid = BNXT_ULP_CLASS_HID_ef8f, .class_tid = 1, .hdr_sig_id = 8, @@ -24818,7 +25448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1073] = { + [1101] = { .class_hid = BNXT_ULP_CLASS_HID_c2f3, .class_tid = 1, .hdr_sig_id = 8, @@ -24837,7 +25467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1074] = { + [1102] = { .class_hid = BNXT_ULP_CLASS_HID_e533, .class_tid = 1, .hdr_sig_id = 8, @@ -24857,7 +25487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1075] = { + [1103] = { .class_hid = BNXT_ULP_CLASS_HID_c873, .class_tid = 1, .hdr_sig_id = 8, @@ -24877,7 +25507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1076] = { + [1104] = { .class_hid = BNXT_ULP_CLASS_HID_eab3, .class_tid = 1, .hdr_sig_id = 8, @@ -24898,7 +25528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1077] = { + [1105] = { .class_hid = BNXT_ULP_CLASS_HID_1d8f3, .class_tid = 1, .hdr_sig_id = 8, @@ -24918,7 +25548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1078] = { + [1106] = { .class_hid = BNXT_ULP_CLASS_HID_1fb33, .class_tid = 1, .hdr_sig_id = 8, @@ -24939,7 +25569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1079] = { + [1107] = { .class_hid = BNXT_ULP_CLASS_HID_1c127, .class_tid = 1, .hdr_sig_id = 8, @@ -24960,7 +25590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1080] = { + [1108] = { .class_hid = BNXT_ULP_CLASS_HID_1e467, .class_tid = 1, .hdr_sig_id = 8, @@ -24982,7 +25612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1081] = { + [1109] = { .class_hid = BNXT_ULP_CLASS_HID_180f3, .class_tid = 1, .hdr_sig_id = 8, @@ -25001,7 +25631,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1082] = { + [1110] = { .class_hid = BNXT_ULP_CLASS_HID_1a333, .class_tid = 1, .hdr_sig_id = 8, @@ -25021,7 +25651,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1083] = { + [1111] = { .class_hid = BNXT_ULP_CLASS_HID_1c673, .class_tid = 1, .hdr_sig_id = 8, @@ -25041,7 +25671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1084] = { + [1112] = { .class_hid = BNXT_ULP_CLASS_HID_1e8b3, .class_tid = 1, .hdr_sig_id = 8, @@ -25062,7 +25692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1085] = { + [1113] = { .class_hid = BNXT_ULP_CLASS_HID_8e07, .class_tid = 1, .hdr_sig_id = 8, @@ -25080,7 +25710,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1086] = { + [1114] = { .class_hid = BNXT_ULP_CLASS_HID_b147, .class_tid = 1, .hdr_sig_id = 8, @@ -25099,7 +25729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1087] = { + [1115] = { .class_hid = BNXT_ULP_CLASS_HID_d387, .class_tid = 1, .hdr_sig_id = 8, @@ -25118,7 +25748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1088] = { + [1116] = { .class_hid = BNXT_ULP_CLASS_HID_f6c7, .class_tid = 1, .hdr_sig_id = 8, @@ -25138,7 +25768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1089] = { + [1117] = { .class_hid = BNXT_ULP_CLASS_HID_89cb, .class_tid = 1, .hdr_sig_id = 8, @@ -25157,7 +25787,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1090] = { + [1118] = { .class_hid = BNXT_ULP_CLASS_HID_ac0b, .class_tid = 1, .hdr_sig_id = 8, @@ -25177,7 +25807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1091] = { + [1119] = { .class_hid = BNXT_ULP_CLASS_HID_cf4b, .class_tid = 1, .hdr_sig_id = 8, @@ -25197,7 +25827,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1092] = { + [1120] = { .class_hid = BNXT_ULP_CLASS_HID_f18b, .class_tid = 1, .hdr_sig_id = 8, @@ -25218,7 +25848,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1093] = { + [1121] = { .class_hid = BNXT_ULP_CLASS_HID_19fcb, .class_tid = 1, .hdr_sig_id = 8, @@ -25238,7 +25868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1094] = { + [1122] = { .class_hid = BNXT_ULP_CLASS_HID_1a20b, .class_tid = 1, .hdr_sig_id = 8, @@ -25259,7 +25889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1095] = { + [1123] = { .class_hid = BNXT_ULP_CLASS_HID_1e54b, .class_tid = 1, .hdr_sig_id = 8, @@ -25280,7 +25910,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1096] = { + [1124] = { .class_hid = BNXT_ULP_CLASS_HID_1e78b, .class_tid = 1, .hdr_sig_id = 8, @@ -25302,7 +25932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1097] = { + [1125] = { .class_hid = BNXT_ULP_CLASS_HID_1a407, .class_tid = 1, .hdr_sig_id = 8, @@ -25321,7 +25951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1098] = { + [1126] = { .class_hid = BNXT_ULP_CLASS_HID_1a747, .class_tid = 1, .hdr_sig_id = 8, @@ -25341,7 +25971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1099] = { + [1127] = { .class_hid = BNXT_ULP_CLASS_HID_1e987, .class_tid = 1, .hdr_sig_id = 8, @@ -25361,7 +25991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1100] = { + [1128] = { .class_hid = BNXT_ULP_CLASS_HID_1ecc7, .class_tid = 1, .hdr_sig_id = 8, @@ -25382,7 +26012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1101] = { + [1129] = { .class_hid = BNXT_ULP_CLASS_HID_b1ab, .class_tid = 1, .hdr_sig_id = 8, @@ -25401,7 +26031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1102] = { + [1130] = { .class_hid = BNXT_ULP_CLASS_HID_b4eb, .class_tid = 1, .hdr_sig_id = 8, @@ -25421,7 +26051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1103] = { + [1131] = { .class_hid = BNXT_ULP_CLASS_HID_f72b, .class_tid = 1, .hdr_sig_id = 8, @@ -25441,7 +26071,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1104] = { + [1132] = { .class_hid = BNXT_ULP_CLASS_HID_fa6b, .class_tid = 1, .hdr_sig_id = 8, @@ -25462,7 +26092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1105] = { + [1133] = { .class_hid = BNXT_ULP_CLASS_HID_ad5f, .class_tid = 1, .hdr_sig_id = 8, @@ -25482,7 +26112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1106] = { + [1134] = { .class_hid = BNXT_ULP_CLASS_HID_af9f, .class_tid = 1, .hdr_sig_id = 8, @@ -25503,7 +26133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1107] = { + [1135] = { .class_hid = BNXT_ULP_CLASS_HID_f2df, .class_tid = 1, .hdr_sig_id = 8, @@ -25524,7 +26154,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1108] = { + [1136] = { .class_hid = BNXT_ULP_CLASS_HID_f51f, .class_tid = 1, .hdr_sig_id = 8, @@ -25546,7 +26176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1109] = { + [1137] = { .class_hid = BNXT_ULP_CLASS_HID_1c35f, .class_tid = 1, .hdr_sig_id = 8, @@ -25567,7 +26197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1110] = { + [1138] = { .class_hid = BNXT_ULP_CLASS_HID_1e59f, .class_tid = 1, .hdr_sig_id = 8, @@ -25589,7 +26219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1111] = { + [1139] = { .class_hid = BNXT_ULP_CLASS_HID_1c8df, .class_tid = 1, .hdr_sig_id = 8, @@ -25611,7 +26241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1112] = { + [1140] = { .class_hid = BNXT_ULP_CLASS_HID_1eb1f, .class_tid = 1, .hdr_sig_id = 8, @@ -25634,7 +26264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1113] = { + [1141] = { .class_hid = BNXT_ULP_CLASS_HID_1c7ab, .class_tid = 1, .hdr_sig_id = 8, @@ -25654,7 +26284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1114] = { + [1142] = { .class_hid = BNXT_ULP_CLASS_HID_1eaeb, .class_tid = 1, .hdr_sig_id = 8, @@ -25675,7 +26305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1115] = { + [1143] = { .class_hid = BNXT_ULP_CLASS_HID_1cd2b, .class_tid = 1, .hdr_sig_id = 8, @@ -25696,7 +26326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1116] = { + [1144] = { .class_hid = BNXT_ULP_CLASS_HID_1f06b, .class_tid = 1, .hdr_sig_id = 8, @@ -25718,7 +26348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1117] = { + [1145] = { .class_hid = BNXT_ULP_CLASS_HID_9177, .class_tid = 1, .hdr_sig_id = 8, @@ -25735,7 +26365,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1118] = { + [1146] = { .class_hid = BNXT_ULP_CLASS_HID_b3b7, .class_tid = 1, .hdr_sig_id = 8, @@ -25753,7 +26383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1119] = { + [1147] = { .class_hid = BNXT_ULP_CLASS_HID_d6f7, .class_tid = 1, .hdr_sig_id = 8, @@ -25771,7 +26401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1120] = { + [1148] = { .class_hid = BNXT_ULP_CLASS_HID_f937, .class_tid = 1, .hdr_sig_id = 8, @@ -25790,7 +26420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1121] = { + [1149] = { .class_hid = BNXT_ULP_CLASS_HID_8c3b, .class_tid = 1, .hdr_sig_id = 8, @@ -25808,7 +26438,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1122] = { + [1150] = { .class_hid = BNXT_ULP_CLASS_HID_af7b, .class_tid = 1, .hdr_sig_id = 8, @@ -25827,7 +26457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1123] = { + [1151] = { .class_hid = BNXT_ULP_CLASS_HID_d1bb, .class_tid = 1, .hdr_sig_id = 8, @@ -25846,7 +26476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1124] = { + [1152] = { .class_hid = BNXT_ULP_CLASS_HID_f4fb, .class_tid = 1, .hdr_sig_id = 8, @@ -25866,7 +26496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1125] = { + [1153] = { .class_hid = BNXT_ULP_CLASS_HID_1a23b, .class_tid = 1, .hdr_sig_id = 8, @@ -25885,7 +26515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1126] = { + [1154] = { .class_hid = BNXT_ULP_CLASS_HID_1a57b, .class_tid = 1, .hdr_sig_id = 8, @@ -25905,7 +26535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1127] = { + [1155] = { .class_hid = BNXT_ULP_CLASS_HID_1e7bb, .class_tid = 1, .hdr_sig_id = 8, @@ -25925,7 +26555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1128] = { + [1156] = { .class_hid = BNXT_ULP_CLASS_HID_1eafb, .class_tid = 1, .hdr_sig_id = 8, @@ -25946,7 +26576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1129] = { + [1157] = { .class_hid = BNXT_ULP_CLASS_HID_1a777, .class_tid = 1, .hdr_sig_id = 8, @@ -25964,7 +26594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1130] = { + [1158] = { .class_hid = BNXT_ULP_CLASS_HID_1a9b7, .class_tid = 1, .hdr_sig_id = 8, @@ -25983,7 +26613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1131] = { + [1159] = { .class_hid = BNXT_ULP_CLASS_HID_1ecf7, .class_tid = 1, .hdr_sig_id = 8, @@ -26002,7 +26632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1132] = { + [1160] = { .class_hid = BNXT_ULP_CLASS_HID_1ef37, .class_tid = 1, .hdr_sig_id = 8, @@ -26022,7 +26652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1133] = { + [1161] = { .class_hid = BNXT_ULP_CLASS_HID_b49b, .class_tid = 1, .hdr_sig_id = 8, @@ -26040,7 +26670,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1134] = { + [1162] = { .class_hid = BNXT_ULP_CLASS_HID_b7db, .class_tid = 1, .hdr_sig_id = 8, @@ -26059,7 +26689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1135] = { + [1163] = { .class_hid = BNXT_ULP_CLASS_HID_fa1b, .class_tid = 1, .hdr_sig_id = 8, @@ -26078,7 +26708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1136] = { + [1164] = { .class_hid = BNXT_ULP_CLASS_HID_fd5b, .class_tid = 1, .hdr_sig_id = 8, @@ -26098,7 +26728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1137] = { + [1165] = { .class_hid = BNXT_ULP_CLASS_HID_b04f, .class_tid = 1, .hdr_sig_id = 8, @@ -26117,7 +26747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1138] = { + [1166] = { .class_hid = BNXT_ULP_CLASS_HID_b28f, .class_tid = 1, .hdr_sig_id = 8, @@ -26137,7 +26767,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1139] = { + [1167] = { .class_hid = BNXT_ULP_CLASS_HID_f5cf, .class_tid = 1, .hdr_sig_id = 8, @@ -26157,7 +26787,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1140] = { + [1168] = { .class_hid = BNXT_ULP_CLASS_HID_f80f, .class_tid = 1, .hdr_sig_id = 8, @@ -26178,7 +26808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1141] = { + [1169] = { .class_hid = BNXT_ULP_CLASS_HID_1c64f, .class_tid = 1, .hdr_sig_id = 8, @@ -26198,7 +26828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1142] = { + [1170] = { .class_hid = BNXT_ULP_CLASS_HID_1e88f, .class_tid = 1, .hdr_sig_id = 8, @@ -26219,7 +26849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1143] = { + [1171] = { .class_hid = BNXT_ULP_CLASS_HID_1cbcf, .class_tid = 1, .hdr_sig_id = 8, @@ -26240,7 +26870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1144] = { + [1172] = { .class_hid = BNXT_ULP_CLASS_HID_1ee0f, .class_tid = 1, .hdr_sig_id = 8, @@ -26262,7 +26892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1145] = { + [1173] = { .class_hid = BNXT_ULP_CLASS_HID_1ca9b, .class_tid = 1, .hdr_sig_id = 8, @@ -26281,7 +26911,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1146] = { + [1174] = { .class_hid = BNXT_ULP_CLASS_HID_1eddb, .class_tid = 1, .hdr_sig_id = 8, @@ -26301,7 +26931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1147] = { + [1175] = { .class_hid = BNXT_ULP_CLASS_HID_1d01b, .class_tid = 1, .hdr_sig_id = 8, @@ -26321,7 +26951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1148] = { + [1176] = { .class_hid = BNXT_ULP_CLASS_HID_1f35b, .class_tid = 1, .hdr_sig_id = 8, @@ -26342,7 +26972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1149] = { + [1177] = { .class_hid = BNXT_ULP_CLASS_HID_8b4b, .class_tid = 1, .hdr_sig_id = 8, @@ -26358,7 +26988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1150] = { + [1178] = { .class_hid = BNXT_ULP_CLASS_HID_ad8b, .class_tid = 1, .hdr_sig_id = 8, @@ -26375,7 +27005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1151] = { + [1179] = { .class_hid = BNXT_ULP_CLASS_HID_d0cb, .class_tid = 1, .hdr_sig_id = 8, @@ -26392,7 +27022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1152] = { + [1180] = { .class_hid = BNXT_ULP_CLASS_HID_f30b, .class_tid = 1, .hdr_sig_id = 8, @@ -26410,7 +27040,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1153] = { + [1181] = { .class_hid = BNXT_ULP_CLASS_HID_867f, .class_tid = 1, .hdr_sig_id = 8, @@ -26427,7 +27057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1154] = { + [1182] = { .class_hid = BNXT_ULP_CLASS_HID_a8bf, .class_tid = 1, .hdr_sig_id = 8, @@ -26445,7 +27075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1155] = { + [1183] = { .class_hid = BNXT_ULP_CLASS_HID_cbff, .class_tid = 1, .hdr_sig_id = 8, @@ -26463,7 +27093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1156] = { + [1184] = { .class_hid = BNXT_ULP_CLASS_HID_ee3f, .class_tid = 1, .hdr_sig_id = 8, @@ -26482,7 +27112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1157] = { + [1185] = { .class_hid = BNXT_ULP_CLASS_HID_19c7f, .class_tid = 1, .hdr_sig_id = 8, @@ -26500,7 +27130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1158] = { + [1186] = { .class_hid = BNXT_ULP_CLASS_HID_1bebf, .class_tid = 1, .hdr_sig_id = 8, @@ -26519,7 +27149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1159] = { + [1187] = { .class_hid = BNXT_ULP_CLASS_HID_1e1ff, .class_tid = 1, .hdr_sig_id = 8, @@ -26538,7 +27168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1160] = { + [1188] = { .class_hid = BNXT_ULP_CLASS_HID_1e43f, .class_tid = 1, .hdr_sig_id = 8, @@ -26558,7 +27188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1161] = { + [1189] = { .class_hid = BNXT_ULP_CLASS_HID_1a14b, .class_tid = 1, .hdr_sig_id = 8, @@ -26575,7 +27205,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1162] = { + [1190] = { .class_hid = BNXT_ULP_CLASS_HID_1a38b, .class_tid = 1, .hdr_sig_id = 8, @@ -26593,7 +27223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1163] = { + [1191] = { .class_hid = BNXT_ULP_CLASS_HID_1e6cb, .class_tid = 1, .hdr_sig_id = 8, @@ -26611,7 +27241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1164] = { + [1192] = { .class_hid = BNXT_ULP_CLASS_HID_1e90b, .class_tid = 1, .hdr_sig_id = 8, @@ -26630,7 +27260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1165] = { + [1193] = { .class_hid = BNXT_ULP_CLASS_HID_aedf, .class_tid = 1, .hdr_sig_id = 8, @@ -26647,7 +27277,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1166] = { + [1194] = { .class_hid = BNXT_ULP_CLASS_HID_b11f, .class_tid = 1, .hdr_sig_id = 8, @@ -26665,7 +27295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1167] = { + [1195] = { .class_hid = BNXT_ULP_CLASS_HID_f45f, .class_tid = 1, .hdr_sig_id = 8, @@ -26683,7 +27313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1168] = { + [1196] = { .class_hid = BNXT_ULP_CLASS_HID_f69f, .class_tid = 1, .hdr_sig_id = 8, @@ -26702,7 +27332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1169] = { + [1197] = { .class_hid = BNXT_ULP_CLASS_HID_a983, .class_tid = 1, .hdr_sig_id = 8, @@ -26720,7 +27350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1170] = { + [1198] = { .class_hid = BNXT_ULP_CLASS_HID_acc3, .class_tid = 1, .hdr_sig_id = 8, @@ -26739,7 +27369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1171] = { + [1199] = { .class_hid = BNXT_ULP_CLASS_HID_ef03, .class_tid = 1, .hdr_sig_id = 8, @@ -26758,7 +27388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1172] = { + [1200] = { .class_hid = BNXT_ULP_CLASS_HID_f243, .class_tid = 1, .hdr_sig_id = 8, @@ -26778,7 +27408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1173] = { + [1201] = { .class_hid = BNXT_ULP_CLASS_HID_1bf83, .class_tid = 1, .hdr_sig_id = 8, @@ -26797,7 +27427,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1174] = { + [1202] = { .class_hid = BNXT_ULP_CLASS_HID_1e2c3, .class_tid = 1, .hdr_sig_id = 8, @@ -26817,7 +27447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1175] = { + [1203] = { .class_hid = BNXT_ULP_CLASS_HID_1c503, .class_tid = 1, .hdr_sig_id = 8, @@ -26837,7 +27467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1176] = { + [1204] = { .class_hid = BNXT_ULP_CLASS_HID_1e843, .class_tid = 1, .hdr_sig_id = 8, @@ -26858,7 +27488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1177] = { + [1205] = { .class_hid = BNXT_ULP_CLASS_HID_1c4df, .class_tid = 1, .hdr_sig_id = 8, @@ -26876,7 +27506,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1178] = { + [1206] = { .class_hid = BNXT_ULP_CLASS_HID_1e71f, .class_tid = 1, .hdr_sig_id = 8, @@ -26895,7 +27525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1179] = { + [1207] = { .class_hid = BNXT_ULP_CLASS_HID_1ca5f, .class_tid = 1, .hdr_sig_id = 8, @@ -26914,7 +27544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1180] = { + [1208] = { .class_hid = BNXT_ULP_CLASS_HID_1ec9f, .class_tid = 1, .hdr_sig_id = 8, @@ -26934,7 +27564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1181] = { + [1209] = { .class_hid = BNXT_ULP_CLASS_HID_2523, .class_tid = 1, .hdr_sig_id = 8, @@ -26951,7 +27581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1182] = { + [1210] = { .class_hid = BNXT_ULP_CLASS_HID_2bef, .class_tid = 1, .hdr_sig_id = 8, @@ -26969,7 +27599,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1183] = { + [1211] = { + .class_hid = BNXT_ULP_CLASS_HID_2693, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1212] = { .class_hid = BNXT_ULP_CLASS_HID_4f73, .class_tid = 1, .hdr_sig_id = 8, @@ -26988,7 +27637,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1184] = { + [1213] = { + .class_hid = BNXT_ULP_CLASS_HID_4a27, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1214] = { .class_hid = BNXT_ULP_CLASS_HID_164b, .class_tid = 1, .hdr_sig_id = 8, @@ -27007,7 +27676,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1185] = { + [1215] = { + .class_hid = BNXT_ULP_CLASS_HID_117f, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1216] = { .class_hid = BNXT_ULP_CLASS_HID_39df, .class_tid = 1, .hdr_sig_id = 8, @@ -27027,7 +27716,46 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1186] = { + [1217] = { + .class_hid = BNXT_ULP_CLASS_HID_3483, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1218] = { + .class_hid = BNXT_ULP_CLASS_HID_20d7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1219] = { .class_hid = BNXT_ULP_CLASS_HID_48b7, .class_tid = 1, .hdr_sig_id = 8, @@ -27045,7 +27773,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1187] = { + [1220] = { + .class_hid = BNXT_ULP_CLASS_HID_447b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1221] = { .class_hid = BNXT_ULP_CLASS_HID_0f8f, .class_tid = 1, .hdr_sig_id = 8, @@ -27063,7 +27810,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1188] = { + [1222] = { + .class_hid = BNXT_ULP_CLASS_HID_0ab3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1223] = { .class_hid = BNXT_ULP_CLASS_HID_3313, .class_tid = 1, .hdr_sig_id = 8, @@ -27082,7 +27848,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1189] = { + [1224] = { + .class_hid = BNXT_ULP_CLASS_HID_2ec7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1225] = { .class_hid = BNXT_ULP_CLASS_HID_257b7, .class_tid = 1, .hdr_sig_id = 9, @@ -27100,7 +27886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1190] = { + [1226] = { .class_hid = BNXT_ULP_CLASS_HID_24467, .class_tid = 1, .hdr_sig_id = 9, @@ -27119,7 +27905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1191] = { + [1227] = { .class_hid = BNXT_ULP_CLASS_HID_23fbb, .class_tid = 1, .hdr_sig_id = 9, @@ -27139,7 +27925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1192] = { + [1228] = { .class_hid = BNXT_ULP_CLASS_HID_252cb, .class_tid = 1, .hdr_sig_id = 9, @@ -27158,7 +27944,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1193] = { + [1229] = { .class_hid = BNXT_ULP_CLASS_HID_21e7f, .class_tid = 1, .hdr_sig_id = 9, @@ -27177,7 +27963,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1194] = { + [1230] = { .class_hid = BNXT_ULP_CLASS_HID_20b2f, .class_tid = 1, .hdr_sig_id = 9, @@ -27197,7 +27983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1195] = { + [1231] = { .class_hid = BNXT_ULP_CLASS_HID_20663, .class_tid = 1, .hdr_sig_id = 9, @@ -27218,7 +28004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1196] = { + [1232] = { .class_hid = BNXT_ULP_CLASS_HID_219b3, .class_tid = 1, .hdr_sig_id = 9, @@ -27238,7 +28024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1197] = { + [1233] = { .class_hid = BNXT_ULP_CLASS_HID_24213, .class_tid = 1, .hdr_sig_id = 9, @@ -27257,7 +28043,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1198] = { + [1234] = { .class_hid = BNXT_ULP_CLASS_HID_22ec3, .class_tid = 1, .hdr_sig_id = 9, @@ -27277,7 +28063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1199] = { + [1235] = { .class_hid = BNXT_ULP_CLASS_HID_22a17, .class_tid = 1, .hdr_sig_id = 9, @@ -27298,7 +28084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1200] = { + [1236] = { .class_hid = BNXT_ULP_CLASS_HID_23d27, .class_tid = 1, .hdr_sig_id = 9, @@ -27318,7 +28104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1201] = { + [1237] = { .class_hid = BNXT_ULP_CLASS_HID_208db, .class_tid = 1, .hdr_sig_id = 9, @@ -27338,7 +28124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1202] = { + [1238] = { .class_hid = BNXT_ULP_CLASS_HID_25277, .class_tid = 1, .hdr_sig_id = 9, @@ -27359,7 +28145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1203] = { + [1239] = { .class_hid = BNXT_ULP_CLASS_HID_24d8b, .class_tid = 1, .hdr_sig_id = 9, @@ -27381,7 +28167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1204] = { + [1240] = { .class_hid = BNXT_ULP_CLASS_HID_203ef, .class_tid = 1, .hdr_sig_id = 9, @@ -27402,7 +28188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1205] = { + [1241] = { .class_hid = BNXT_ULP_CLASS_HID_2517b, .class_tid = 1, .hdr_sig_id = 9, @@ -27419,7 +28205,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1206] = { + [1242] = { .class_hid = BNXT_ULP_CLASS_HID_23e2b, .class_tid = 1, .hdr_sig_id = 9, @@ -27437,7 +28223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1207] = { + [1243] = { .class_hid = BNXT_ULP_CLASS_HID_2397f, .class_tid = 1, .hdr_sig_id = 9, @@ -27456,7 +28242,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1208] = { + [1244] = { .class_hid = BNXT_ULP_CLASS_HID_24c8f, .class_tid = 1, .hdr_sig_id = 9, @@ -27474,7 +28260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1209] = { + [1245] = { .class_hid = BNXT_ULP_CLASS_HID_21823, .class_tid = 1, .hdr_sig_id = 9, @@ -27492,7 +28278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1210] = { + [1246] = { .class_hid = BNXT_ULP_CLASS_HID_20513, .class_tid = 1, .hdr_sig_id = 9, @@ -27511,7 +28297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1211] = { + [1247] = { .class_hid = BNXT_ULP_CLASS_HID_20027, .class_tid = 1, .hdr_sig_id = 9, @@ -27531,7 +28317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1212] = { + [1248] = { .class_hid = BNXT_ULP_CLASS_HID_21377, .class_tid = 1, .hdr_sig_id = 9, @@ -27550,7 +28336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1213] = { + [1249] = { .class_hid = BNXT_ULP_CLASS_HID_23bd7, .class_tid = 1, .hdr_sig_id = 9, @@ -27568,7 +28354,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1214] = { + [1250] = { .class_hid = BNXT_ULP_CLASS_HID_22887, .class_tid = 1, .hdr_sig_id = 9, @@ -27587,7 +28373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1215] = { + [1251] = { .class_hid = BNXT_ULP_CLASS_HID_223db, .class_tid = 1, .hdr_sig_id = 9, @@ -27607,7 +28393,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1216] = { + [1252] = { .class_hid = BNXT_ULP_CLASS_HID_236eb, .class_tid = 1, .hdr_sig_id = 9, @@ -27626,7 +28412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1217] = { + [1253] = { .class_hid = BNXT_ULP_CLASS_HID_2029f, .class_tid = 1, .hdr_sig_id = 9, @@ -27645,7 +28431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1218] = { + [1254] = { .class_hid = BNXT_ULP_CLASS_HID_24c3b, .class_tid = 1, .hdr_sig_id = 9, @@ -27665,7 +28451,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1219] = { + [1255] = { .class_hid = BNXT_ULP_CLASS_HID_2474f, .class_tid = 1, .hdr_sig_id = 9, @@ -27686,7 +28472,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1220] = { + [1256] = { .class_hid = BNXT_ULP_CLASS_HID_25a9f, .class_tid = 1, .hdr_sig_id = 9, @@ -27706,7 +28492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1221] = { + [1257] = { .class_hid = BNXT_ULP_CLASS_HID_24b3f, .class_tid = 1, .hdr_sig_id = 9, @@ -27723,7 +28509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1222] = { + [1258] = { .class_hid = BNXT_ULP_CLASS_HID_237ef, .class_tid = 1, .hdr_sig_id = 9, @@ -27741,7 +28527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1223] = { + [1259] = { .class_hid = BNXT_ULP_CLASS_HID_23323, .class_tid = 1, .hdr_sig_id = 9, @@ -27760,7 +28546,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1224] = { + [1260] = { .class_hid = BNXT_ULP_CLASS_HID_24673, .class_tid = 1, .hdr_sig_id = 9, @@ -27778,7 +28564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1225] = { + [1261] = { .class_hid = BNXT_ULP_CLASS_HID_211e7, .class_tid = 1, .hdr_sig_id = 9, @@ -27796,7 +28582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1226] = { + [1262] = { .class_hid = BNXT_ULP_CLASS_HID_25b83, .class_tid = 1, .hdr_sig_id = 9, @@ -27815,7 +28601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1227] = { + [1263] = { .class_hid = BNXT_ULP_CLASS_HID_256d7, .class_tid = 1, .hdr_sig_id = 9, @@ -27835,7 +28621,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1228] = { + [1264] = { .class_hid = BNXT_ULP_CLASS_HID_20d3b, .class_tid = 1, .hdr_sig_id = 9, @@ -27854,7 +28640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1229] = { + [1265] = { .class_hid = BNXT_ULP_CLASS_HID_2359b, .class_tid = 1, .hdr_sig_id = 9, @@ -27872,7 +28658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1230] = { + [1266] = { .class_hid = BNXT_ULP_CLASS_HID_2224b, .class_tid = 1, .hdr_sig_id = 9, @@ -27891,7 +28677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1231] = { + [1267] = { .class_hid = BNXT_ULP_CLASS_HID_21d9f, .class_tid = 1, .hdr_sig_id = 9, @@ -27911,7 +28697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1232] = { + [1268] = { .class_hid = BNXT_ULP_CLASS_HID_230af, .class_tid = 1, .hdr_sig_id = 9, @@ -27930,7 +28716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1233] = { + [1269] = { .class_hid = BNXT_ULP_CLASS_HID_2590f, .class_tid = 1, .hdr_sig_id = 9, @@ -27949,7 +28735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1234] = { + [1270] = { .class_hid = BNXT_ULP_CLASS_HID_245ff, .class_tid = 1, .hdr_sig_id = 9, @@ -27969,7 +28755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1235] = { + [1271] = { .class_hid = BNXT_ULP_CLASS_HID_24133, .class_tid = 1, .hdr_sig_id = 9, @@ -27990,7 +28776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1236] = { + [1272] = { .class_hid = BNXT_ULP_CLASS_HID_25443, .class_tid = 1, .hdr_sig_id = 9, @@ -28010,7 +28796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1237] = { + [1273] = { .class_hid = BNXT_ULP_CLASS_HID_244e3, .class_tid = 1, .hdr_sig_id = 9, @@ -28026,7 +28812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1238] = { + [1274] = { .class_hid = BNXT_ULP_CLASS_HID_231d3, .class_tid = 1, .hdr_sig_id = 9, @@ -28043,7 +28829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1239] = { + [1275] = { .class_hid = BNXT_ULP_CLASS_HID_22ce7, .class_tid = 1, .hdr_sig_id = 9, @@ -28061,7 +28847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1240] = { + [1276] = { .class_hid = BNXT_ULP_CLASS_HID_24037, .class_tid = 1, .hdr_sig_id = 9, @@ -28078,7 +28864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1241] = { + [1277] = { .class_hid = BNXT_ULP_CLASS_HID_20bab, .class_tid = 1, .hdr_sig_id = 9, @@ -28095,7 +28881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1242] = { + [1278] = { .class_hid = BNXT_ULP_CLASS_HID_25547, .class_tid = 1, .hdr_sig_id = 9, @@ -28113,7 +28899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1243] = { + [1279] = { .class_hid = BNXT_ULP_CLASS_HID_2509b, .class_tid = 1, .hdr_sig_id = 9, @@ -28132,7 +28918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1244] = { + [1280] = { .class_hid = BNXT_ULP_CLASS_HID_206ff, .class_tid = 1, .hdr_sig_id = 9, @@ -28150,7 +28936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1245] = { + [1281] = { .class_hid = BNXT_ULP_CLASS_HID_22f5f, .class_tid = 1, .hdr_sig_id = 9, @@ -28167,7 +28953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1246] = { + [1282] = { .class_hid = BNXT_ULP_CLASS_HID_21c0f, .class_tid = 1, .hdr_sig_id = 9, @@ -28185,7 +28971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1247] = { + [1283] = { .class_hid = BNXT_ULP_CLASS_HID_21743, .class_tid = 1, .hdr_sig_id = 9, @@ -28204,7 +28990,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1248] = { + [1284] = { .class_hid = BNXT_ULP_CLASS_HID_22a93, .class_tid = 1, .hdr_sig_id = 9, @@ -28222,7 +29008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1249] = { + [1285] = { .class_hid = BNXT_ULP_CLASS_HID_252f3, .class_tid = 1, .hdr_sig_id = 9, @@ -28240,7 +29026,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1250] = { + [1286] = { .class_hid = BNXT_ULP_CLASS_HID_23fa3, .class_tid = 1, .hdr_sig_id = 9, @@ -28259,7 +29045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1251] = { + [1287] = { .class_hid = BNXT_ULP_CLASS_HID_23af7, .class_tid = 1, .hdr_sig_id = 9, @@ -28279,7 +29065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1252] = { + [1288] = { .class_hid = BNXT_ULP_CLASS_HID_24e07, .class_tid = 1, .hdr_sig_id = 9, @@ -28298,7 +29084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1253] = { + [1289] = { .class_hid = BNXT_ULP_CLASS_HID_2322f, .class_tid = 1, .hdr_sig_id = 9, @@ -28314,7 +29100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1254] = { + [1290] = { .class_hid = BNXT_ULP_CLASS_HID_21f1f, .class_tid = 1, .hdr_sig_id = 9, @@ -28331,7 +29117,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1255] = { + [1291] = { .class_hid = BNXT_ULP_CLASS_HID_21a53, .class_tid = 1, .hdr_sig_id = 9, @@ -28349,7 +29135,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1256] = { + [1292] = { .class_hid = BNXT_ULP_CLASS_HID_22d63, .class_tid = 1, .hdr_sig_id = 9, @@ -28366,7 +29152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1257] = { + [1293] = { .class_hid = BNXT_ULP_CLASS_HID_255c3, .class_tid = 1, .hdr_sig_id = 9, @@ -28383,7 +29169,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1258] = { + [1294] = { .class_hid = BNXT_ULP_CLASS_HID_242b3, .class_tid = 1, .hdr_sig_id = 9, @@ -28401,7 +29187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1259] = { + [1295] = { .class_hid = BNXT_ULP_CLASS_HID_23dc7, .class_tid = 1, .hdr_sig_id = 9, @@ -28420,7 +29206,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1260] = { + [1296] = { .class_hid = BNXT_ULP_CLASS_HID_25117, .class_tid = 1, .hdr_sig_id = 9, @@ -28438,7 +29224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1261] = { + [1297] = { .class_hid = BNXT_ULP_CLASS_HID_22c13, .class_tid = 1, .hdr_sig_id = 9, @@ -28453,7 +29239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1262] = { + [1298] = { .class_hid = BNXT_ULP_CLASS_HID_218c3, .class_tid = 1, .hdr_sig_id = 9, @@ -28469,7 +29255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1263] = { + [1299] = { .class_hid = BNXT_ULP_CLASS_HID_21417, .class_tid = 1, .hdr_sig_id = 9, @@ -28486,7 +29272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1264] = { + [1300] = { .class_hid = BNXT_ULP_CLASS_HID_22727, .class_tid = 1, .hdr_sig_id = 9, @@ -28502,7 +29288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1265] = { + [1301] = { .class_hid = BNXT_ULP_CLASS_HID_24f87, .class_tid = 1, .hdr_sig_id = 9, @@ -28518,7 +29304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1266] = { + [1302] = { .class_hid = BNXT_ULP_CLASS_HID_23c77, .class_tid = 1, .hdr_sig_id = 9, @@ -28535,7 +29321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1267] = { + [1303] = { .class_hid = BNXT_ULP_CLASS_HID_2378b, .class_tid = 1, .hdr_sig_id = 9, @@ -28553,7 +29339,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1268] = { + [1304] = { .class_hid = BNXT_ULP_CLASS_HID_24adb, .class_tid = 1, .hdr_sig_id = 9, @@ -28570,7 +29356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1269] = { + [1305] = { .class_hid = BNXT_ULP_CLASS_HID_257b, .class_tid = 1, .hdr_sig_id = 9, @@ -28586,7 +29372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1270] = { + [1306] = { .class_hid = BNXT_ULP_CLASS_HID_2bb7, .class_tid = 1, .hdr_sig_id = 9, @@ -28603,7 +29389,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1271] = { + [1307] = { + .class_hid = BNXT_ULP_CLASS_HID_1867, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1308] = { .class_hid = BNXT_ULP_CLASS_HID_4f2b, .class_tid = 1, .hdr_sig_id = 9, @@ -28621,7 +29425,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1272] = { + [1309] = { + .class_hid = BNXT_ULP_CLASS_HID_3c1b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1310] = { .class_hid = BNXT_ULP_CLASS_HID_1613, .class_tid = 1, .hdr_sig_id = 9, @@ -28639,7 +29462,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1273] = { + [1311] = { + .class_hid = BNXT_ULP_CLASS_HID_02c3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1312] = { .class_hid = BNXT_ULP_CLASS_HID_3987, .class_tid = 1, .hdr_sig_id = 9, @@ -28658,7 +29500,44 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1274] = { + [1313] = { + .class_hid = BNXT_ULP_CLASS_HID_2677, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1314] = { + .class_hid = BNXT_ULP_CLASS_HID_122b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1315] = { .class_hid = BNXT_ULP_CLASS_HID_48ef, .class_tid = 1, .hdr_sig_id = 9, @@ -28675,7 +29554,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1275] = { + [1316] = { + .class_hid = BNXT_ULP_CLASS_HID_35df, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1317] = { .class_hid = BNXT_ULP_CLASS_HID_0fd7, .class_tid = 1, .hdr_sig_id = 9, @@ -28692,7 +29589,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1276] = { + [1318] = { + .class_hid = BNXT_ULP_CLASS_HID_5973, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1319] = { .class_hid = BNXT_ULP_CLASS_HID_334b, .class_tid = 1, .hdr_sig_id = 9, @@ -28710,7 +29625,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1277] = { + [1320] = { + .class_hid = BNXT_ULP_CLASS_HID_203b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 118, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1321] = { .class_hid = BNXT_ULP_CLASS_HID_25797, .class_tid = 1, .hdr_sig_id = 10, @@ -28729,7 +29663,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1278] = { + [1322] = { .class_hid = BNXT_ULP_CLASS_HID_285eb, .class_tid = 1, .hdr_sig_id = 10, @@ -28749,7 +29683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1279] = { + [1323] = { .class_hid = BNXT_ULP_CLASS_HID_310eb, .class_tid = 1, .hdr_sig_id = 10, @@ -28769,7 +29703,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1280] = { + [1324] = { .class_hid = BNXT_ULP_CLASS_HID_39beb, .class_tid = 1, .hdr_sig_id = 10, @@ -28790,7 +29724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1281] = { + [1325] = { .class_hid = BNXT_ULP_CLASS_HID_24447, .class_tid = 1, .hdr_sig_id = 10, @@ -28810,7 +29744,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1282] = { + [1326] = { .class_hid = BNXT_ULP_CLASS_HID_2cf47, .class_tid = 1, .hdr_sig_id = 10, @@ -28831,7 +29765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1283] = { + [1327] = { .class_hid = BNXT_ULP_CLASS_HID_35a47, .class_tid = 1, .hdr_sig_id = 10, @@ -28852,7 +29786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1284] = { + [1328] = { .class_hid = BNXT_ULP_CLASS_HID_3889b, .class_tid = 1, .hdr_sig_id = 10, @@ -28874,7 +29808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1285] = { + [1329] = { .class_hid = BNXT_ULP_CLASS_HID_23f9b, .class_tid = 1, .hdr_sig_id = 10, @@ -28895,7 +29829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1286] = { + [1330] = { .class_hid = BNXT_ULP_CLASS_HID_2ca9b, .class_tid = 1, .hdr_sig_id = 10, @@ -28917,7 +29851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1287] = { + [1331] = { .class_hid = BNXT_ULP_CLASS_HID_3559b, .class_tid = 1, .hdr_sig_id = 10, @@ -28939,7 +29873,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1288] = { + [1332] = { .class_hid = BNXT_ULP_CLASS_HID_383ef, .class_tid = 1, .hdr_sig_id = 10, @@ -28962,7 +29896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1289] = { + [1333] = { .class_hid = BNXT_ULP_CLASS_HID_252eb, .class_tid = 1, .hdr_sig_id = 10, @@ -28982,7 +29916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1290] = { + [1334] = { .class_hid = BNXT_ULP_CLASS_HID_2813f, .class_tid = 1, .hdr_sig_id = 10, @@ -29003,7 +29937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1291] = { + [1335] = { .class_hid = BNXT_ULP_CLASS_HID_30c3f, .class_tid = 1, .hdr_sig_id = 10, @@ -29024,7 +29958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1292] = { + [1336] = { .class_hid = BNXT_ULP_CLASS_HID_3973f, .class_tid = 1, .hdr_sig_id = 10, @@ -29046,7 +29980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1293] = { + [1337] = { .class_hid = BNXT_ULP_CLASS_HID_21e5f, .class_tid = 1, .hdr_sig_id = 10, @@ -29066,7 +30000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1294] = { + [1338] = { .class_hid = BNXT_ULP_CLASS_HID_2a95f, .class_tid = 1, .hdr_sig_id = 10, @@ -29087,7 +30021,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1295] = { + [1339] = { .class_hid = BNXT_ULP_CLASS_HID_3345f, .class_tid = 1, .hdr_sig_id = 10, @@ -29108,7 +30042,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1296] = { + [1340] = { .class_hid = BNXT_ULP_CLASS_HID_3bf5f, .class_tid = 1, .hdr_sig_id = 10, @@ -29130,7 +30064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1297] = { + [1341] = { .class_hid = BNXT_ULP_CLASS_HID_20b0f, .class_tid = 1, .hdr_sig_id = 10, @@ -29151,7 +30085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1298] = { + [1342] = { .class_hid = BNXT_ULP_CLASS_HID_2960f, .class_tid = 1, .hdr_sig_id = 10, @@ -29173,7 +30107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1299] = { + [1343] = { .class_hid = BNXT_ULP_CLASS_HID_3210f, .class_tid = 1, .hdr_sig_id = 10, @@ -29195,7 +30129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1300] = { + [1344] = { .class_hid = BNXT_ULP_CLASS_HID_3ac0f, .class_tid = 1, .hdr_sig_id = 10, @@ -29218,7 +30152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1301] = { + [1345] = { .class_hid = BNXT_ULP_CLASS_HID_20643, .class_tid = 1, .hdr_sig_id = 10, @@ -29240,7 +30174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1302] = { + [1346] = { .class_hid = BNXT_ULP_CLASS_HID_29143, .class_tid = 1, .hdr_sig_id = 10, @@ -29263,7 +30197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1303] = { + [1347] = { .class_hid = BNXT_ULP_CLASS_HID_31c43, .class_tid = 1, .hdr_sig_id = 10, @@ -29286,7 +30220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1304] = { + [1348] = { .class_hid = BNXT_ULP_CLASS_HID_3a743, .class_tid = 1, .hdr_sig_id = 10, @@ -29310,7 +30244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1305] = { + [1349] = { .class_hid = BNXT_ULP_CLASS_HID_21993, .class_tid = 1, .hdr_sig_id = 10, @@ -29331,7 +30265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1306] = { + [1350] = { .class_hid = BNXT_ULP_CLASS_HID_2a493, .class_tid = 1, .hdr_sig_id = 10, @@ -29353,7 +30287,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1307] = { + [1351] = { .class_hid = BNXT_ULP_CLASS_HID_32f93, .class_tid = 1, .hdr_sig_id = 10, @@ -29375,7 +30309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1308] = { + [1352] = { .class_hid = BNXT_ULP_CLASS_HID_3ba93, .class_tid = 1, .hdr_sig_id = 10, @@ -29398,7 +30332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1309] = { + [1353] = { .class_hid = BNXT_ULP_CLASS_HID_24233, .class_tid = 1, .hdr_sig_id = 10, @@ -29418,7 +30352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1310] = { + [1354] = { .class_hid = BNXT_ULP_CLASS_HID_2cd33, .class_tid = 1, .hdr_sig_id = 10, @@ -29439,7 +30373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1311] = { + [1355] = { .class_hid = BNXT_ULP_CLASS_HID_35833, .class_tid = 1, .hdr_sig_id = 10, @@ -29460,7 +30394,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1312] = { + [1356] = { .class_hid = BNXT_ULP_CLASS_HID_38607, .class_tid = 1, .hdr_sig_id = 10, @@ -29482,7 +30416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1313] = { + [1357] = { .class_hid = BNXT_ULP_CLASS_HID_22ee3, .class_tid = 1, .hdr_sig_id = 10, @@ -29503,7 +30437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1314] = { + [1358] = { .class_hid = BNXT_ULP_CLASS_HID_2b9e3, .class_tid = 1, .hdr_sig_id = 10, @@ -29525,7 +30459,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1315] = { + [1359] = { .class_hid = BNXT_ULP_CLASS_HID_344e3, .class_tid = 1, .hdr_sig_id = 10, @@ -29547,7 +30481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1316] = { + [1360] = { .class_hid = BNXT_ULP_CLASS_HID_3cfe3, .class_tid = 1, .hdr_sig_id = 10, @@ -29570,7 +30504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1317] = { + [1361] = { .class_hid = BNXT_ULP_CLASS_HID_22a37, .class_tid = 1, .hdr_sig_id = 10, @@ -29592,7 +30526,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1318] = { + [1362] = { .class_hid = BNXT_ULP_CLASS_HID_2b537, .class_tid = 1, .hdr_sig_id = 10, @@ -29615,7 +30549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1319] = { + [1363] = { .class_hid = BNXT_ULP_CLASS_HID_34037, .class_tid = 1, .hdr_sig_id = 10, @@ -29638,7 +30572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1320] = { + [1364] = { .class_hid = BNXT_ULP_CLASS_HID_3cb37, .class_tid = 1, .hdr_sig_id = 10, @@ -29662,7 +30596,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1321] = { + [1365] = { .class_hid = BNXT_ULP_CLASS_HID_23d07, .class_tid = 1, .hdr_sig_id = 10, @@ -29683,7 +30617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1322] = { + [1366] = { .class_hid = BNXT_ULP_CLASS_HID_2c807, .class_tid = 1, .hdr_sig_id = 10, @@ -29705,7 +30639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1323] = { + [1367] = { .class_hid = BNXT_ULP_CLASS_HID_35307, .class_tid = 1, .hdr_sig_id = 10, @@ -29727,7 +30661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1324] = { + [1368] = { .class_hid = BNXT_ULP_CLASS_HID_3815b, .class_tid = 1, .hdr_sig_id = 10, @@ -29750,7 +30684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1325] = { + [1369] = { .class_hid = BNXT_ULP_CLASS_HID_208fb, .class_tid = 1, .hdr_sig_id = 10, @@ -29771,7 +30705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1326] = { + [1370] = { .class_hid = BNXT_ULP_CLASS_HID_293fb, .class_tid = 1, .hdr_sig_id = 10, @@ -29793,7 +30727,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1327] = { + [1371] = { .class_hid = BNXT_ULP_CLASS_HID_31efb, .class_tid = 1, .hdr_sig_id = 10, @@ -29815,7 +30749,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1328] = { + [1372] = { .class_hid = BNXT_ULP_CLASS_HID_3a9fb, .class_tid = 1, .hdr_sig_id = 10, @@ -29838,7 +30772,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1329] = { + [1373] = { .class_hid = BNXT_ULP_CLASS_HID_25257, .class_tid = 1, .hdr_sig_id = 10, @@ -29860,7 +30794,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1330] = { + [1374] = { .class_hid = BNXT_ULP_CLASS_HID_280ab, .class_tid = 1, .hdr_sig_id = 10, @@ -29883,7 +30817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1331] = { + [1375] = { .class_hid = BNXT_ULP_CLASS_HID_30bab, .class_tid = 1, .hdr_sig_id = 10, @@ -29906,7 +30840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1332] = { + [1376] = { .class_hid = BNXT_ULP_CLASS_HID_396ab, .class_tid = 1, .hdr_sig_id = 10, @@ -29930,7 +30864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1333] = { + [1377] = { .class_hid = BNXT_ULP_CLASS_HID_24dab, .class_tid = 1, .hdr_sig_id = 10, @@ -29953,7 +30887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1334] = { + [1378] = { .class_hid = BNXT_ULP_CLASS_HID_2d8ab, .class_tid = 1, .hdr_sig_id = 10, @@ -29977,7 +30911,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1335] = { + [1379] = { .class_hid = BNXT_ULP_CLASS_HID_306ff, .class_tid = 1, .hdr_sig_id = 10, @@ -30001,7 +30935,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1336] = { + [1380] = { .class_hid = BNXT_ULP_CLASS_HID_391ff, .class_tid = 1, .hdr_sig_id = 10, @@ -30026,7 +30960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1337] = { + [1381] = { .class_hid = BNXT_ULP_CLASS_HID_203cf, .class_tid = 1, .hdr_sig_id = 10, @@ -30048,7 +30982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1338] = { + [1382] = { .class_hid = BNXT_ULP_CLASS_HID_28ecf, .class_tid = 1, .hdr_sig_id = 10, @@ -30071,7 +31005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1339] = { + [1383] = { .class_hid = BNXT_ULP_CLASS_HID_319cf, .class_tid = 1, .hdr_sig_id = 10, @@ -30094,7 +31028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1340] = { + [1384] = { .class_hid = BNXT_ULP_CLASS_HID_3a4cf, .class_tid = 1, .hdr_sig_id = 10, @@ -30118,7 +31052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1341] = { + [1385] = { .class_hid = BNXT_ULP_CLASS_HID_2515b, .class_tid = 1, .hdr_sig_id = 10, @@ -30136,7 +31070,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1342] = { + [1386] = { .class_hid = BNXT_ULP_CLASS_HID_2dc5b, .class_tid = 1, .hdr_sig_id = 10, @@ -30155,7 +31089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1343] = { + [1387] = { .class_hid = BNXT_ULP_CLASS_HID_30aaf, .class_tid = 1, .hdr_sig_id = 10, @@ -30174,7 +31108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1344] = { + [1388] = { .class_hid = BNXT_ULP_CLASS_HID_395af, .class_tid = 1, .hdr_sig_id = 10, @@ -30194,7 +31128,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1345] = { + [1389] = { .class_hid = BNXT_ULP_CLASS_HID_23e0b, .class_tid = 1, .hdr_sig_id = 10, @@ -30213,7 +31147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1346] = { + [1390] = { .class_hid = BNXT_ULP_CLASS_HID_2c90b, .class_tid = 1, .hdr_sig_id = 10, @@ -30233,7 +31167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1347] = { + [1391] = { .class_hid = BNXT_ULP_CLASS_HID_3540b, .class_tid = 1, .hdr_sig_id = 10, @@ -30253,7 +31187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1348] = { + [1392] = { .class_hid = BNXT_ULP_CLASS_HID_3825f, .class_tid = 1, .hdr_sig_id = 10, @@ -30274,7 +31208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1349] = { + [1393] = { .class_hid = BNXT_ULP_CLASS_HID_2395f, .class_tid = 1, .hdr_sig_id = 10, @@ -30294,7 +31228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1350] = { + [1394] = { .class_hid = BNXT_ULP_CLASS_HID_2c45f, .class_tid = 1, .hdr_sig_id = 10, @@ -30315,7 +31249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1351] = { + [1395] = { .class_hid = BNXT_ULP_CLASS_HID_34f5f, .class_tid = 1, .hdr_sig_id = 10, @@ -30336,7 +31270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1352] = { + [1396] = { .class_hid = BNXT_ULP_CLASS_HID_3da5f, .class_tid = 1, .hdr_sig_id = 10, @@ -30358,7 +31292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1353] = { + [1397] = { .class_hid = BNXT_ULP_CLASS_HID_24caf, .class_tid = 1, .hdr_sig_id = 10, @@ -30377,7 +31311,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1354] = { + [1398] = { .class_hid = BNXT_ULP_CLASS_HID_2d7af, .class_tid = 1, .hdr_sig_id = 10, @@ -30397,7 +31331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1355] = { + [1399] = { .class_hid = BNXT_ULP_CLASS_HID_305e3, .class_tid = 1, .hdr_sig_id = 10, @@ -30417,7 +31351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1356] = { + [1400] = { .class_hid = BNXT_ULP_CLASS_HID_390e3, .class_tid = 1, .hdr_sig_id = 10, @@ -30438,7 +31372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1357] = { + [1401] = { .class_hid = BNXT_ULP_CLASS_HID_21803, .class_tid = 1, .hdr_sig_id = 10, @@ -30457,7 +31391,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1358] = { + [1402] = { .class_hid = BNXT_ULP_CLASS_HID_2a303, .class_tid = 1, .hdr_sig_id = 10, @@ -30477,7 +31411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1359] = { + [1403] = { .class_hid = BNXT_ULP_CLASS_HID_32e03, .class_tid = 1, .hdr_sig_id = 10, @@ -30497,7 +31431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1360] = { + [1404] = { .class_hid = BNXT_ULP_CLASS_HID_3b903, .class_tid = 1, .hdr_sig_id = 10, @@ -30518,7 +31452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1361] = { + [1405] = { .class_hid = BNXT_ULP_CLASS_HID_20533, .class_tid = 1, .hdr_sig_id = 10, @@ -30538,7 +31472,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1362] = { + [1406] = { .class_hid = BNXT_ULP_CLASS_HID_29033, .class_tid = 1, .hdr_sig_id = 10, @@ -30559,7 +31493,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1363] = { + [1407] = { .class_hid = BNXT_ULP_CLASS_HID_31b33, .class_tid = 1, .hdr_sig_id = 10, @@ -30580,7 +31514,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1364] = { + [1408] = { .class_hid = BNXT_ULP_CLASS_HID_3a633, .class_tid = 1, .hdr_sig_id = 10, @@ -30602,7 +31536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1365] = { + [1409] = { .class_hid = BNXT_ULP_CLASS_HID_20007, .class_tid = 1, .hdr_sig_id = 10, @@ -30623,7 +31557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1366] = { + [1410] = { .class_hid = BNXT_ULP_CLASS_HID_28b07, .class_tid = 1, .hdr_sig_id = 10, @@ -30645,7 +31579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1367] = { + [1411] = { .class_hid = BNXT_ULP_CLASS_HID_31607, .class_tid = 1, .hdr_sig_id = 10, @@ -30667,7 +31601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1368] = { + [1412] = { .class_hid = BNXT_ULP_CLASS_HID_3a107, .class_tid = 1, .hdr_sig_id = 10, @@ -30690,7 +31624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1369] = { + [1413] = { .class_hid = BNXT_ULP_CLASS_HID_21357, .class_tid = 1, .hdr_sig_id = 10, @@ -30710,7 +31644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1370] = { + [1414] = { .class_hid = BNXT_ULP_CLASS_HID_29e57, .class_tid = 1, .hdr_sig_id = 10, @@ -30731,7 +31665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1371] = { + [1415] = { .class_hid = BNXT_ULP_CLASS_HID_32957, .class_tid = 1, .hdr_sig_id = 10, @@ -30752,7 +31686,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1372] = { + [1416] = { .class_hid = BNXT_ULP_CLASS_HID_3b457, .class_tid = 1, .hdr_sig_id = 10, @@ -30774,7 +31708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1373] = { + [1417] = { .class_hid = BNXT_ULP_CLASS_HID_23bf7, .class_tid = 1, .hdr_sig_id = 10, @@ -30793,7 +31727,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1374] = { + [1418] = { .class_hid = BNXT_ULP_CLASS_HID_2c6f7, .class_tid = 1, .hdr_sig_id = 10, @@ -30813,7 +31747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1375] = { + [1419] = { .class_hid = BNXT_ULP_CLASS_HID_351f7, .class_tid = 1, .hdr_sig_id = 10, @@ -30833,7 +31767,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1376] = { + [1420] = { .class_hid = BNXT_ULP_CLASS_HID_3dcf7, .class_tid = 1, .hdr_sig_id = 10, @@ -30854,7 +31788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1377] = { + [1421] = { .class_hid = BNXT_ULP_CLASS_HID_228a7, .class_tid = 1, .hdr_sig_id = 10, @@ -30874,7 +31808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1378] = { + [1422] = { .class_hid = BNXT_ULP_CLASS_HID_2b3a7, .class_tid = 1, .hdr_sig_id = 10, @@ -30895,7 +31829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1379] = { + [1423] = { .class_hid = BNXT_ULP_CLASS_HID_33ea7, .class_tid = 1, .hdr_sig_id = 10, @@ -30916,7 +31850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1380] = { + [1424] = { .class_hid = BNXT_ULP_CLASS_HID_3c9a7, .class_tid = 1, .hdr_sig_id = 10, @@ -30938,7 +31872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1381] = { + [1425] = { .class_hid = BNXT_ULP_CLASS_HID_223fb, .class_tid = 1, .hdr_sig_id = 10, @@ -30959,7 +31893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1382] = { + [1426] = { .class_hid = BNXT_ULP_CLASS_HID_2aefb, .class_tid = 1, .hdr_sig_id = 10, @@ -30981,7 +31915,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1383] = { + [1427] = { .class_hid = BNXT_ULP_CLASS_HID_339fb, .class_tid = 1, .hdr_sig_id = 10, @@ -31003,7 +31937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1384] = { + [1428] = { .class_hid = BNXT_ULP_CLASS_HID_3c4fb, .class_tid = 1, .hdr_sig_id = 10, @@ -31026,7 +31960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1385] = { + [1429] = { .class_hid = BNXT_ULP_CLASS_HID_236cb, .class_tid = 1, .hdr_sig_id = 10, @@ -31046,7 +31980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1386] = { + [1430] = { .class_hid = BNXT_ULP_CLASS_HID_2c1cb, .class_tid = 1, .hdr_sig_id = 10, @@ -31067,7 +32001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1387] = { + [1431] = { .class_hid = BNXT_ULP_CLASS_HID_34ccb, .class_tid = 1, .hdr_sig_id = 10, @@ -31088,7 +32022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1388] = { + [1432] = { .class_hid = BNXT_ULP_CLASS_HID_3d7cb, .class_tid = 1, .hdr_sig_id = 10, @@ -31110,7 +32044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1389] = { + [1433] = { .class_hid = BNXT_ULP_CLASS_HID_202bf, .class_tid = 1, .hdr_sig_id = 10, @@ -31130,7 +32064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1390] = { + [1434] = { .class_hid = BNXT_ULP_CLASS_HID_28dbf, .class_tid = 1, .hdr_sig_id = 10, @@ -31151,7 +32085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1391] = { + [1435] = { .class_hid = BNXT_ULP_CLASS_HID_318bf, .class_tid = 1, .hdr_sig_id = 10, @@ -31172,7 +32106,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1392] = { + [1436] = { .class_hid = BNXT_ULP_CLASS_HID_3a3bf, .class_tid = 1, .hdr_sig_id = 10, @@ -31194,7 +32128,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1393] = { + [1437] = { .class_hid = BNXT_ULP_CLASS_HID_24c1b, .class_tid = 1, .hdr_sig_id = 10, @@ -31215,7 +32149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1394] = { + [1438] = { .class_hid = BNXT_ULP_CLASS_HID_2d71b, .class_tid = 1, .hdr_sig_id = 10, @@ -31237,7 +32171,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1395] = { + [1439] = { .class_hid = BNXT_ULP_CLASS_HID_3056f, .class_tid = 1, .hdr_sig_id = 10, @@ -31259,7 +32193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1396] = { + [1440] = { .class_hid = BNXT_ULP_CLASS_HID_3906f, .class_tid = 1, .hdr_sig_id = 10, @@ -31282,7 +32216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1397] = { + [1441] = { .class_hid = BNXT_ULP_CLASS_HID_2476f, .class_tid = 1, .hdr_sig_id = 10, @@ -31304,7 +32238,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1398] = { + [1442] = { .class_hid = BNXT_ULP_CLASS_HID_2d26f, .class_tid = 1, .hdr_sig_id = 10, @@ -31327,7 +32261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1399] = { + [1443] = { .class_hid = BNXT_ULP_CLASS_HID_300a3, .class_tid = 1, .hdr_sig_id = 10, @@ -31350,7 +32284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1400] = { + [1444] = { .class_hid = BNXT_ULP_CLASS_HID_38ba3, .class_tid = 1, .hdr_sig_id = 10, @@ -31374,7 +32308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1401] = { + [1445] = { .class_hid = BNXT_ULP_CLASS_HID_25abf, .class_tid = 1, .hdr_sig_id = 10, @@ -31395,7 +32329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1402] = { + [1446] = { .class_hid = BNXT_ULP_CLASS_HID_288f3, .class_tid = 1, .hdr_sig_id = 10, @@ -31417,7 +32351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1403] = { + [1447] = { .class_hid = BNXT_ULP_CLASS_HID_313f3, .class_tid = 1, .hdr_sig_id = 10, @@ -31439,7 +32373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1404] = { + [1448] = { .class_hid = BNXT_ULP_CLASS_HID_39ef3, .class_tid = 1, .hdr_sig_id = 10, @@ -31462,7 +32396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1405] = { + [1449] = { .class_hid = BNXT_ULP_CLASS_HID_24b1f, .class_tid = 1, .hdr_sig_id = 10, @@ -31480,7 +32414,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1406] = { + [1450] = { .class_hid = BNXT_ULP_CLASS_HID_2d61f, .class_tid = 1, .hdr_sig_id = 10, @@ -31499,7 +32433,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1407] = { + [1451] = { .class_hid = BNXT_ULP_CLASS_HID_30453, .class_tid = 1, .hdr_sig_id = 10, @@ -31518,7 +32452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1408] = { + [1452] = { .class_hid = BNXT_ULP_CLASS_HID_38f53, .class_tid = 1, .hdr_sig_id = 10, @@ -31538,7 +32472,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1409] = { + [1453] = { .class_hid = BNXT_ULP_CLASS_HID_237cf, .class_tid = 1, .hdr_sig_id = 10, @@ -31557,7 +32491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1410] = { + [1454] = { .class_hid = BNXT_ULP_CLASS_HID_2c2cf, .class_tid = 1, .hdr_sig_id = 10, @@ -31577,7 +32511,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1411] = { + [1455] = { .class_hid = BNXT_ULP_CLASS_HID_34dcf, .class_tid = 1, .hdr_sig_id = 10, @@ -31597,7 +32531,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1412] = { + [1456] = { .class_hid = BNXT_ULP_CLASS_HID_3d8cf, .class_tid = 1, .hdr_sig_id = 10, @@ -31618,7 +32552,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1413] = { + [1457] = { .class_hid = BNXT_ULP_CLASS_HID_23303, .class_tid = 1, .hdr_sig_id = 10, @@ -31638,7 +32572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1414] = { + [1458] = { .class_hid = BNXT_ULP_CLASS_HID_2be03, .class_tid = 1, .hdr_sig_id = 10, @@ -31659,7 +32593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1415] = { + [1459] = { .class_hid = BNXT_ULP_CLASS_HID_34903, .class_tid = 1, .hdr_sig_id = 10, @@ -31680,7 +32614,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1416] = { + [1460] = { .class_hid = BNXT_ULP_CLASS_HID_3d403, .class_tid = 1, .hdr_sig_id = 10, @@ -31702,7 +32636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1417] = { + [1461] = { .class_hid = BNXT_ULP_CLASS_HID_24653, .class_tid = 1, .hdr_sig_id = 10, @@ -31721,7 +32655,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1418] = { + [1462] = { .class_hid = BNXT_ULP_CLASS_HID_2d153, .class_tid = 1, .hdr_sig_id = 10, @@ -31741,7 +32675,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1419] = { + [1463] = { .class_hid = BNXT_ULP_CLASS_HID_35c53, .class_tid = 1, .hdr_sig_id = 10, @@ -31761,7 +32695,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1420] = { + [1464] = { .class_hid = BNXT_ULP_CLASS_HID_38aa7, .class_tid = 1, .hdr_sig_id = 10, @@ -31782,7 +32716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1421] = { + [1465] = { .class_hid = BNXT_ULP_CLASS_HID_211c7, .class_tid = 1, .hdr_sig_id = 10, @@ -31801,7 +32735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1422] = { + [1466] = { .class_hid = BNXT_ULP_CLASS_HID_29cc7, .class_tid = 1, .hdr_sig_id = 10, @@ -31821,7 +32755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1423] = { + [1467] = { .class_hid = BNXT_ULP_CLASS_HID_327c7, .class_tid = 1, .hdr_sig_id = 10, @@ -31841,7 +32775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1424] = { + [1468] = { .class_hid = BNXT_ULP_CLASS_HID_3b2c7, .class_tid = 1, .hdr_sig_id = 10, @@ -31862,7 +32796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1425] = { + [1469] = { .class_hid = BNXT_ULP_CLASS_HID_25ba3, .class_tid = 1, .hdr_sig_id = 10, @@ -31882,7 +32816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1426] = { + [1470] = { .class_hid = BNXT_ULP_CLASS_HID_289f7, .class_tid = 1, .hdr_sig_id = 10, @@ -31903,7 +32837,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1427] = { + [1471] = { .class_hid = BNXT_ULP_CLASS_HID_314f7, .class_tid = 1, .hdr_sig_id = 10, @@ -31924,7 +32858,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1428] = { + [1472] = { .class_hid = BNXT_ULP_CLASS_HID_39ff7, .class_tid = 1, .hdr_sig_id = 10, @@ -31946,7 +32880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1429] = { + [1473] = { .class_hid = BNXT_ULP_CLASS_HID_256f7, .class_tid = 1, .hdr_sig_id = 10, @@ -31967,7 +32901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1430] = { + [1474] = { .class_hid = BNXT_ULP_CLASS_HID_284cb, .class_tid = 1, .hdr_sig_id = 10, @@ -31989,7 +32923,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1431] = { + [1475] = { .class_hid = BNXT_ULP_CLASS_HID_30fcb, .class_tid = 1, .hdr_sig_id = 10, @@ -32011,7 +32945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1432] = { + [1476] = { .class_hid = BNXT_ULP_CLASS_HID_39acb, .class_tid = 1, .hdr_sig_id = 10, @@ -32034,7 +32968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1433] = { + [1477] = { .class_hid = BNXT_ULP_CLASS_HID_20d1b, .class_tid = 1, .hdr_sig_id = 10, @@ -32054,7 +32988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1434] = { + [1478] = { .class_hid = BNXT_ULP_CLASS_HID_2981b, .class_tid = 1, .hdr_sig_id = 10, @@ -32075,7 +33009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1435] = { + [1479] = { .class_hid = BNXT_ULP_CLASS_HID_3231b, .class_tid = 1, .hdr_sig_id = 10, @@ -32096,7 +33030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1436] = { + [1480] = { .class_hid = BNXT_ULP_CLASS_HID_3ae1b, .class_tid = 1, .hdr_sig_id = 10, @@ -32118,7 +33052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1437] = { + [1481] = { .class_hid = BNXT_ULP_CLASS_HID_235bb, .class_tid = 1, .hdr_sig_id = 10, @@ -32137,7 +33071,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1438] = { + [1482] = { .class_hid = BNXT_ULP_CLASS_HID_2c0bb, .class_tid = 1, .hdr_sig_id = 10, @@ -32157,7 +33091,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1439] = { + [1483] = { .class_hid = BNXT_ULP_CLASS_HID_34bbb, .class_tid = 1, .hdr_sig_id = 10, @@ -32177,7 +33111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1440] = { + [1484] = { .class_hid = BNXT_ULP_CLASS_HID_3d6bb, .class_tid = 1, .hdr_sig_id = 10, @@ -32198,7 +33132,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1441] = { + [1485] = { .class_hid = BNXT_ULP_CLASS_HID_2226b, .class_tid = 1, .hdr_sig_id = 10, @@ -32218,7 +33152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1442] = { + [1486] = { .class_hid = BNXT_ULP_CLASS_HID_2ad6b, .class_tid = 1, .hdr_sig_id = 10, @@ -32239,7 +33173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1443] = { + [1487] = { .class_hid = BNXT_ULP_CLASS_HID_3386b, .class_tid = 1, .hdr_sig_id = 10, @@ -32260,7 +33194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1444] = { + [1488] = { .class_hid = BNXT_ULP_CLASS_HID_3c36b, .class_tid = 1, .hdr_sig_id = 10, @@ -32282,7 +33216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1445] = { + [1489] = { .class_hid = BNXT_ULP_CLASS_HID_21dbf, .class_tid = 1, .hdr_sig_id = 10, @@ -32303,7 +33237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1446] = { + [1490] = { .class_hid = BNXT_ULP_CLASS_HID_2a8bf, .class_tid = 1, .hdr_sig_id = 10, @@ -32325,7 +33259,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1447] = { + [1491] = { .class_hid = BNXT_ULP_CLASS_HID_333bf, .class_tid = 1, .hdr_sig_id = 10, @@ -32347,7 +33281,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1448] = { + [1492] = { .class_hid = BNXT_ULP_CLASS_HID_3bebf, .class_tid = 1, .hdr_sig_id = 10, @@ -32370,7 +33304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1449] = { + [1493] = { .class_hid = BNXT_ULP_CLASS_HID_2308f, .class_tid = 1, .hdr_sig_id = 10, @@ -32390,7 +33324,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1450] = { + [1494] = { .class_hid = BNXT_ULP_CLASS_HID_2bb8f, .class_tid = 1, .hdr_sig_id = 10, @@ -32411,7 +33345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1451] = { + [1495] = { .class_hid = BNXT_ULP_CLASS_HID_3468f, .class_tid = 1, .hdr_sig_id = 10, @@ -32432,7 +33366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1452] = { + [1496] = { .class_hid = BNXT_ULP_CLASS_HID_3d18f, .class_tid = 1, .hdr_sig_id = 10, @@ -32454,7 +33388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1453] = { + [1497] = { .class_hid = BNXT_ULP_CLASS_HID_2592f, .class_tid = 1, .hdr_sig_id = 10, @@ -32474,7 +33408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1454] = { + [1498] = { .class_hid = BNXT_ULP_CLASS_HID_28763, .class_tid = 1, .hdr_sig_id = 10, @@ -32495,7 +33429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1455] = { + [1499] = { .class_hid = BNXT_ULP_CLASS_HID_31263, .class_tid = 1, .hdr_sig_id = 10, @@ -32516,7 +33450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1456] = { + [1500] = { .class_hid = BNXT_ULP_CLASS_HID_39d63, .class_tid = 1, .hdr_sig_id = 10, @@ -32538,7 +33472,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1457] = { + [1501] = { .class_hid = BNXT_ULP_CLASS_HID_245df, .class_tid = 1, .hdr_sig_id = 10, @@ -32559,7 +33493,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1458] = { + [1502] = { .class_hid = BNXT_ULP_CLASS_HID_2d0df, .class_tid = 1, .hdr_sig_id = 10, @@ -32581,7 +33515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1459] = { + [1503] = { .class_hid = BNXT_ULP_CLASS_HID_35bdf, .class_tid = 1, .hdr_sig_id = 10, @@ -32603,7 +33537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1460] = { + [1504] = { .class_hid = BNXT_ULP_CLASS_HID_38a13, .class_tid = 1, .hdr_sig_id = 10, @@ -32626,7 +33560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1461] = { + [1505] = { .class_hid = BNXT_ULP_CLASS_HID_24113, .class_tid = 1, .hdr_sig_id = 10, @@ -32648,7 +33582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1462] = { + [1506] = { .class_hid = BNXT_ULP_CLASS_HID_2cc13, .class_tid = 1, .hdr_sig_id = 10, @@ -32671,7 +33605,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1463] = { + [1507] = { .class_hid = BNXT_ULP_CLASS_HID_35713, .class_tid = 1, .hdr_sig_id = 10, @@ -32694,7 +33628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1464] = { + [1508] = { .class_hid = BNXT_ULP_CLASS_HID_38567, .class_tid = 1, .hdr_sig_id = 10, @@ -32718,7 +33652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1465] = { + [1509] = { .class_hid = BNXT_ULP_CLASS_HID_25463, .class_tid = 1, .hdr_sig_id = 10, @@ -32739,7 +33673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1466] = { + [1510] = { .class_hid = BNXT_ULP_CLASS_HID_282b7, .class_tid = 1, .hdr_sig_id = 10, @@ -32761,7 +33695,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1467] = { + [1511] = { .class_hid = BNXT_ULP_CLASS_HID_30db7, .class_tid = 1, .hdr_sig_id = 10, @@ -32783,7 +33717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1468] = { + [1512] = { .class_hid = BNXT_ULP_CLASS_HID_398b7, .class_tid = 1, .hdr_sig_id = 10, @@ -32806,7 +33740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1469] = { + [1513] = { .class_hid = BNXT_ULP_CLASS_HID_244c3, .class_tid = 1, .hdr_sig_id = 10, @@ -32823,7 +33757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1470] = { + [1514] = { .class_hid = BNXT_ULP_CLASS_HID_2cfc3, .class_tid = 1, .hdr_sig_id = 10, @@ -32841,7 +33775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1471] = { + [1515] = { .class_hid = BNXT_ULP_CLASS_HID_35ac3, .class_tid = 1, .hdr_sig_id = 10, @@ -32859,7 +33793,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1472] = { + [1516] = { .class_hid = BNXT_ULP_CLASS_HID_38917, .class_tid = 1, .hdr_sig_id = 10, @@ -32878,7 +33812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1473] = { + [1517] = { .class_hid = BNXT_ULP_CLASS_HID_231f3, .class_tid = 1, .hdr_sig_id = 10, @@ -32896,7 +33830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1474] = { + [1518] = { .class_hid = BNXT_ULP_CLASS_HID_2bcf3, .class_tid = 1, .hdr_sig_id = 10, @@ -32915,7 +33849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1475] = { + [1519] = { .class_hid = BNXT_ULP_CLASS_HID_347f3, .class_tid = 1, .hdr_sig_id = 10, @@ -32934,7 +33868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1476] = { + [1520] = { .class_hid = BNXT_ULP_CLASS_HID_3d2f3, .class_tid = 1, .hdr_sig_id = 10, @@ -32954,7 +33888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1477] = { + [1521] = { .class_hid = BNXT_ULP_CLASS_HID_22cc7, .class_tid = 1, .hdr_sig_id = 10, @@ -32973,7 +33907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1478] = { + [1522] = { .class_hid = BNXT_ULP_CLASS_HID_2b7c7, .class_tid = 1, .hdr_sig_id = 10, @@ -32993,7 +33927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1479] = { + [1523] = { .class_hid = BNXT_ULP_CLASS_HID_342c7, .class_tid = 1, .hdr_sig_id = 10, @@ -33013,7 +33947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1480] = { + [1524] = { .class_hid = BNXT_ULP_CLASS_HID_3cdc7, .class_tid = 1, .hdr_sig_id = 10, @@ -33034,7 +33968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1481] = { + [1525] = { .class_hid = BNXT_ULP_CLASS_HID_24017, .class_tid = 1, .hdr_sig_id = 10, @@ -33052,7 +33986,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1482] = { + [1526] = { .class_hid = BNXT_ULP_CLASS_HID_2cb17, .class_tid = 1, .hdr_sig_id = 10, @@ -33071,7 +34005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1483] = { + [1527] = { .class_hid = BNXT_ULP_CLASS_HID_35617, .class_tid = 1, .hdr_sig_id = 10, @@ -33090,7 +34024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1484] = { + [1528] = { .class_hid = BNXT_ULP_CLASS_HID_3846b, .class_tid = 1, .hdr_sig_id = 10, @@ -33110,7 +34044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1485] = { + [1529] = { .class_hid = BNXT_ULP_CLASS_HID_20b8b, .class_tid = 1, .hdr_sig_id = 10, @@ -33128,7 +34062,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1486] = { + [1530] = { .class_hid = BNXT_ULP_CLASS_HID_2968b, .class_tid = 1, .hdr_sig_id = 10, @@ -33147,7 +34081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1487] = { + [1531] = { .class_hid = BNXT_ULP_CLASS_HID_3218b, .class_tid = 1, .hdr_sig_id = 10, @@ -33166,7 +34100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1488] = { + [1532] = { .class_hid = BNXT_ULP_CLASS_HID_3ac8b, .class_tid = 1, .hdr_sig_id = 10, @@ -33186,7 +34120,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1489] = { + [1533] = { .class_hid = BNXT_ULP_CLASS_HID_25567, .class_tid = 1, .hdr_sig_id = 10, @@ -33205,7 +34139,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1490] = { + [1534] = { .class_hid = BNXT_ULP_CLASS_HID_283bb, .class_tid = 1, .hdr_sig_id = 10, @@ -33225,7 +34159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1491] = { + [1535] = { .class_hid = BNXT_ULP_CLASS_HID_30ebb, .class_tid = 1, .hdr_sig_id = 10, @@ -33245,7 +34179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1492] = { + [1536] = { .class_hid = BNXT_ULP_CLASS_HID_399bb, .class_tid = 1, .hdr_sig_id = 10, @@ -33266,7 +34200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1493] = { + [1537] = { .class_hid = BNXT_ULP_CLASS_HID_250bb, .class_tid = 1, .hdr_sig_id = 10, @@ -33286,7 +34220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1494] = { + [1538] = { .class_hid = BNXT_ULP_CLASS_HID_2dbbb, .class_tid = 1, .hdr_sig_id = 10, @@ -33307,7 +34241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1495] = { + [1539] = { .class_hid = BNXT_ULP_CLASS_HID_3098f, .class_tid = 1, .hdr_sig_id = 10, @@ -33328,7 +34262,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1496] = { + [1540] = { .class_hid = BNXT_ULP_CLASS_HID_3948f, .class_tid = 1, .hdr_sig_id = 10, @@ -33350,7 +34284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1497] = { + [1541] = { .class_hid = BNXT_ULP_CLASS_HID_206df, .class_tid = 1, .hdr_sig_id = 10, @@ -33369,7 +34303,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1498] = { + [1542] = { .class_hid = BNXT_ULP_CLASS_HID_291df, .class_tid = 1, .hdr_sig_id = 10, @@ -33389,7 +34323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1499] = { + [1543] = { .class_hid = BNXT_ULP_CLASS_HID_31cdf, .class_tid = 1, .hdr_sig_id = 10, @@ -33409,7 +34343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1500] = { + [1544] = { .class_hid = BNXT_ULP_CLASS_HID_3a7df, .class_tid = 1, .hdr_sig_id = 10, @@ -33430,7 +34364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1501] = { + [1545] = { .class_hid = BNXT_ULP_CLASS_HID_22f7f, .class_tid = 1, .hdr_sig_id = 10, @@ -33448,7 +34382,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1502] = { + [1546] = { .class_hid = BNXT_ULP_CLASS_HID_2ba7f, .class_tid = 1, .hdr_sig_id = 10, @@ -33467,7 +34401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1503] = { + [1547] = { .class_hid = BNXT_ULP_CLASS_HID_3457f, .class_tid = 1, .hdr_sig_id = 10, @@ -33486,7 +34420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1504] = { + [1548] = { .class_hid = BNXT_ULP_CLASS_HID_3d07f, .class_tid = 1, .hdr_sig_id = 10, @@ -33506,7 +34440,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1505] = { + [1549] = { .class_hid = BNXT_ULP_CLASS_HID_21c2f, .class_tid = 1, .hdr_sig_id = 10, @@ -33525,7 +34459,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1506] = { + [1550] = { .class_hid = BNXT_ULP_CLASS_HID_2a72f, .class_tid = 1, .hdr_sig_id = 10, @@ -33545,7 +34479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1507] = { + [1551] = { .class_hid = BNXT_ULP_CLASS_HID_3322f, .class_tid = 1, .hdr_sig_id = 10, @@ -33565,7 +34499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1508] = { + [1552] = { .class_hid = BNXT_ULP_CLASS_HID_3bd2f, .class_tid = 1, .hdr_sig_id = 10, @@ -33586,7 +34520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1509] = { + [1553] = { .class_hid = BNXT_ULP_CLASS_HID_21763, .class_tid = 1, .hdr_sig_id = 10, @@ -33606,7 +34540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1510] = { + [1554] = { .class_hid = BNXT_ULP_CLASS_HID_2a263, .class_tid = 1, .hdr_sig_id = 10, @@ -33627,7 +34561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1511] = { + [1555] = { .class_hid = BNXT_ULP_CLASS_HID_32d63, .class_tid = 1, .hdr_sig_id = 10, @@ -33648,7 +34582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1512] = { + [1556] = { .class_hid = BNXT_ULP_CLASS_HID_3b863, .class_tid = 1, .hdr_sig_id = 10, @@ -33670,7 +34604,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1513] = { + [1557] = { .class_hid = BNXT_ULP_CLASS_HID_22ab3, .class_tid = 1, .hdr_sig_id = 10, @@ -33689,7 +34623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1514] = { + [1558] = { .class_hid = BNXT_ULP_CLASS_HID_2b5b3, .class_tid = 1, .hdr_sig_id = 10, @@ -33709,7 +34643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1515] = { + [1559] = { .class_hid = BNXT_ULP_CLASS_HID_340b3, .class_tid = 1, .hdr_sig_id = 10, @@ -33729,7 +34663,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1516] = { + [1560] = { .class_hid = BNXT_ULP_CLASS_HID_3cbb3, .class_tid = 1, .hdr_sig_id = 10, @@ -33750,7 +34684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1517] = { + [1561] = { .class_hid = BNXT_ULP_CLASS_HID_252d3, .class_tid = 1, .hdr_sig_id = 10, @@ -33769,7 +34703,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1518] = { + [1562] = { .class_hid = BNXT_ULP_CLASS_HID_28127, .class_tid = 1, .hdr_sig_id = 10, @@ -33789,7 +34723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1519] = { + [1563] = { .class_hid = BNXT_ULP_CLASS_HID_30c27, .class_tid = 1, .hdr_sig_id = 10, @@ -33809,7 +34743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1520] = { + [1564] = { .class_hid = BNXT_ULP_CLASS_HID_39727, .class_tid = 1, .hdr_sig_id = 10, @@ -33830,7 +34764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1521] = { + [1565] = { .class_hid = BNXT_ULP_CLASS_HID_23f83, .class_tid = 1, .hdr_sig_id = 10, @@ -33850,7 +34784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1522] = { + [1566] = { .class_hid = BNXT_ULP_CLASS_HID_2ca83, .class_tid = 1, .hdr_sig_id = 10, @@ -33871,7 +34805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1523] = { + [1567] = { .class_hid = BNXT_ULP_CLASS_HID_35583, .class_tid = 1, .hdr_sig_id = 10, @@ -33892,7 +34826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1524] = { + [1568] = { .class_hid = BNXT_ULP_CLASS_HID_383d7, .class_tid = 1, .hdr_sig_id = 10, @@ -33914,7 +34848,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1525] = { + [1569] = { .class_hid = BNXT_ULP_CLASS_HID_23ad7, .class_tid = 1, .hdr_sig_id = 10, @@ -33935,7 +34869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1526] = { + [1570] = { .class_hid = BNXT_ULP_CLASS_HID_2c5d7, .class_tid = 1, .hdr_sig_id = 10, @@ -33957,7 +34891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1527] = { + [1571] = { .class_hid = BNXT_ULP_CLASS_HID_350d7, .class_tid = 1, .hdr_sig_id = 10, @@ -33979,7 +34913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1528] = { + [1572] = { .class_hid = BNXT_ULP_CLASS_HID_3dbd7, .class_tid = 1, .hdr_sig_id = 10, @@ -34002,7 +34936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1529] = { + [1573] = { .class_hid = BNXT_ULP_CLASS_HID_24e27, .class_tid = 1, .hdr_sig_id = 10, @@ -34022,7 +34956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1530] = { + [1574] = { .class_hid = BNXT_ULP_CLASS_HID_2d927, .class_tid = 1, .hdr_sig_id = 10, @@ -34043,7 +34977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1531] = { + [1575] = { .class_hid = BNXT_ULP_CLASS_HID_3077b, .class_tid = 1, .hdr_sig_id = 10, @@ -34064,7 +34998,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1532] = { + [1576] = { .class_hid = BNXT_ULP_CLASS_HID_3927b, .class_tid = 1, .hdr_sig_id = 10, @@ -34086,7 +35020,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1533] = { + [1577] = { .class_hid = BNXT_ULP_CLASS_HID_2320f, .class_tid = 1, .hdr_sig_id = 10, @@ -34103,7 +35037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1534] = { + [1578] = { .class_hid = BNXT_ULP_CLASS_HID_2bd0f, .class_tid = 1, .hdr_sig_id = 10, @@ -34121,7 +35055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1535] = { + [1579] = { .class_hid = BNXT_ULP_CLASS_HID_3480f, .class_tid = 1, .hdr_sig_id = 10, @@ -34139,7 +35073,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1536] = { + [1580] = { .class_hid = BNXT_ULP_CLASS_HID_3d30f, .class_tid = 1, .hdr_sig_id = 10, @@ -34158,7 +35092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1537] = { + [1581] = { .class_hid = BNXT_ULP_CLASS_HID_21f3f, .class_tid = 1, .hdr_sig_id = 10, @@ -34176,7 +35110,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1538] = { + [1582] = { .class_hid = BNXT_ULP_CLASS_HID_2aa3f, .class_tid = 1, .hdr_sig_id = 10, @@ -34195,7 +35129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1539] = { + [1583] = { .class_hid = BNXT_ULP_CLASS_HID_3353f, .class_tid = 1, .hdr_sig_id = 10, @@ -34214,7 +35148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1540] = { + [1584] = { .class_hid = BNXT_ULP_CLASS_HID_3c03f, .class_tid = 1, .hdr_sig_id = 10, @@ -34234,7 +35168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1541] = { + [1585] = { .class_hid = BNXT_ULP_CLASS_HID_21a73, .class_tid = 1, .hdr_sig_id = 10, @@ -34253,7 +35187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1542] = { + [1586] = { .class_hid = BNXT_ULP_CLASS_HID_2a573, .class_tid = 1, .hdr_sig_id = 10, @@ -34273,7 +35207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1543] = { + [1587] = { .class_hid = BNXT_ULP_CLASS_HID_33073, .class_tid = 1, .hdr_sig_id = 10, @@ -34293,7 +35227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1544] = { + [1588] = { .class_hid = BNXT_ULP_CLASS_HID_3bb73, .class_tid = 1, .hdr_sig_id = 10, @@ -34314,7 +35248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1545] = { + [1589] = { .class_hid = BNXT_ULP_CLASS_HID_22d43, .class_tid = 1, .hdr_sig_id = 10, @@ -34332,7 +35266,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1546] = { + [1590] = { .class_hid = BNXT_ULP_CLASS_HID_2b843, .class_tid = 1, .hdr_sig_id = 10, @@ -34351,7 +35285,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1547] = { + [1591] = { .class_hid = BNXT_ULP_CLASS_HID_34343, .class_tid = 1, .hdr_sig_id = 10, @@ -34370,7 +35304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1548] = { + [1592] = { .class_hid = BNXT_ULP_CLASS_HID_3ce43, .class_tid = 1, .hdr_sig_id = 10, @@ -34390,7 +35324,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1549] = { + [1593] = { .class_hid = BNXT_ULP_CLASS_HID_255e3, .class_tid = 1, .hdr_sig_id = 10, @@ -34408,7 +35342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1550] = { + [1594] = { .class_hid = BNXT_ULP_CLASS_HID_28437, .class_tid = 1, .hdr_sig_id = 10, @@ -34427,7 +35361,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1551] = { + [1595] = { .class_hid = BNXT_ULP_CLASS_HID_30f37, .class_tid = 1, .hdr_sig_id = 10, @@ -34446,7 +35380,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1552] = { + [1596] = { .class_hid = BNXT_ULP_CLASS_HID_39a37, .class_tid = 1, .hdr_sig_id = 10, @@ -34466,7 +35400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1553] = { + [1597] = { .class_hid = BNXT_ULP_CLASS_HID_24293, .class_tid = 1, .hdr_sig_id = 10, @@ -34485,7 +35419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1554] = { + [1598] = { .class_hid = BNXT_ULP_CLASS_HID_2cd93, .class_tid = 1, .hdr_sig_id = 10, @@ -34505,7 +35439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1555] = { + [1599] = { .class_hid = BNXT_ULP_CLASS_HID_35893, .class_tid = 1, .hdr_sig_id = 10, @@ -34525,7 +35459,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1556] = { + [1600] = { .class_hid = BNXT_ULP_CLASS_HID_386e7, .class_tid = 1, .hdr_sig_id = 10, @@ -34546,7 +35480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1557] = { + [1601] = { .class_hid = BNXT_ULP_CLASS_HID_23de7, .class_tid = 1, .hdr_sig_id = 10, @@ -34566,7 +35500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1558] = { + [1602] = { .class_hid = BNXT_ULP_CLASS_HID_2c8e7, .class_tid = 1, .hdr_sig_id = 10, @@ -34587,7 +35521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1559] = { + [1603] = { .class_hid = BNXT_ULP_CLASS_HID_353e7, .class_tid = 1, .hdr_sig_id = 10, @@ -34608,7 +35542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1560] = { + [1604] = { .class_hid = BNXT_ULP_CLASS_HID_3823b, .class_tid = 1, .hdr_sig_id = 10, @@ -34630,7 +35564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1561] = { + [1605] = { .class_hid = BNXT_ULP_CLASS_HID_25137, .class_tid = 1, .hdr_sig_id = 10, @@ -34649,7 +35583,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1562] = { + [1606] = { .class_hid = BNXT_ULP_CLASS_HID_2dc37, .class_tid = 1, .hdr_sig_id = 10, @@ -34669,7 +35603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1563] = { + [1607] = { .class_hid = BNXT_ULP_CLASS_HID_30a0b, .class_tid = 1, .hdr_sig_id = 10, @@ -34689,7 +35623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1564] = { + [1608] = { .class_hid = BNXT_ULP_CLASS_HID_3950b, .class_tid = 1, .hdr_sig_id = 10, @@ -34710,7 +35644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1565] = { + [1609] = { .class_hid = BNXT_ULP_CLASS_HID_22c33, .class_tid = 1, .hdr_sig_id = 10, @@ -34726,7 +35660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1566] = { + [1610] = { .class_hid = BNXT_ULP_CLASS_HID_2b733, .class_tid = 1, .hdr_sig_id = 10, @@ -34743,7 +35677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1567] = { + [1611] = { .class_hid = BNXT_ULP_CLASS_HID_34233, .class_tid = 1, .hdr_sig_id = 10, @@ -34760,7 +35694,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1568] = { + [1612] = { .class_hid = BNXT_ULP_CLASS_HID_3cd33, .class_tid = 1, .hdr_sig_id = 10, @@ -34778,7 +35712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1569] = { + [1613] = { .class_hid = BNXT_ULP_CLASS_HID_218e3, .class_tid = 1, .hdr_sig_id = 10, @@ -34795,7 +35729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1570] = { + [1614] = { .class_hid = BNXT_ULP_CLASS_HID_2a3e3, .class_tid = 1, .hdr_sig_id = 10, @@ -34813,7 +35747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1571] = { + [1615] = { .class_hid = BNXT_ULP_CLASS_HID_32ee3, .class_tid = 1, .hdr_sig_id = 10, @@ -34831,7 +35765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1572] = { + [1616] = { .class_hid = BNXT_ULP_CLASS_HID_3b9e3, .class_tid = 1, .hdr_sig_id = 10, @@ -34850,7 +35784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1573] = { + [1617] = { .class_hid = BNXT_ULP_CLASS_HID_21437, .class_tid = 1, .hdr_sig_id = 10, @@ -34868,7 +35802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1574] = { + [1618] = { .class_hid = BNXT_ULP_CLASS_HID_29f37, .class_tid = 1, .hdr_sig_id = 10, @@ -34887,7 +35821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1575] = { + [1619] = { .class_hid = BNXT_ULP_CLASS_HID_32a37, .class_tid = 1, .hdr_sig_id = 10, @@ -34906,7 +35840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1576] = { + [1620] = { .class_hid = BNXT_ULP_CLASS_HID_3b537, .class_tid = 1, .hdr_sig_id = 10, @@ -34926,7 +35860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1577] = { + [1621] = { .class_hid = BNXT_ULP_CLASS_HID_22707, .class_tid = 1, .hdr_sig_id = 10, @@ -34943,7 +35877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1578] = { + [1622] = { .class_hid = BNXT_ULP_CLASS_HID_2b207, .class_tid = 1, .hdr_sig_id = 10, @@ -34961,7 +35895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1579] = { + [1623] = { .class_hid = BNXT_ULP_CLASS_HID_33d07, .class_tid = 1, .hdr_sig_id = 10, @@ -34979,7 +35913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1580] = { + [1624] = { .class_hid = BNXT_ULP_CLASS_HID_3c807, .class_tid = 1, .hdr_sig_id = 10, @@ -34998,7 +35932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1581] = { + [1625] = { .class_hid = BNXT_ULP_CLASS_HID_24fa7, .class_tid = 1, .hdr_sig_id = 10, @@ -35015,7 +35949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1582] = { + [1626] = { .class_hid = BNXT_ULP_CLASS_HID_2daa7, .class_tid = 1, .hdr_sig_id = 10, @@ -35033,7 +35967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1583] = { + [1627] = { .class_hid = BNXT_ULP_CLASS_HID_308fb, .class_tid = 1, .hdr_sig_id = 10, @@ -35051,7 +35985,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1584] = { + [1628] = { .class_hid = BNXT_ULP_CLASS_HID_393fb, .class_tid = 1, .hdr_sig_id = 10, @@ -35070,7 +36004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1585] = { + [1629] = { .class_hid = BNXT_ULP_CLASS_HID_23c57, .class_tid = 1, .hdr_sig_id = 10, @@ -35088,7 +36022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1586] = { + [1630] = { .class_hid = BNXT_ULP_CLASS_HID_2c757, .class_tid = 1, .hdr_sig_id = 10, @@ -35107,7 +36041,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1587] = { + [1631] = { .class_hid = BNXT_ULP_CLASS_HID_35257, .class_tid = 1, .hdr_sig_id = 10, @@ -35126,7 +36060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1588] = { + [1632] = { .class_hid = BNXT_ULP_CLASS_HID_380ab, .class_tid = 1, .hdr_sig_id = 10, @@ -35146,7 +36080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1589] = { + [1633] = { .class_hid = BNXT_ULP_CLASS_HID_237ab, .class_tid = 1, .hdr_sig_id = 10, @@ -35165,7 +36099,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1590] = { + [1634] = { .class_hid = BNXT_ULP_CLASS_HID_2c2ab, .class_tid = 1, .hdr_sig_id = 10, @@ -35185,7 +36119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1591] = { + [1635] = { .class_hid = BNXT_ULP_CLASS_HID_34dab, .class_tid = 1, .hdr_sig_id = 10, @@ -35205,7 +36139,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1592] = { + [1636] = { .class_hid = BNXT_ULP_CLASS_HID_3d8ab, .class_tid = 1, .hdr_sig_id = 10, @@ -35226,7 +36160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1593] = { + [1637] = { .class_hid = BNXT_ULP_CLASS_HID_24afb, .class_tid = 1, .hdr_sig_id = 10, @@ -35244,7 +36178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1594] = { + [1638] = { .class_hid = BNXT_ULP_CLASS_HID_2d5fb, .class_tid = 1, .hdr_sig_id = 10, @@ -35263,7 +36197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1595] = { + [1639] = { .class_hid = BNXT_ULP_CLASS_HID_303cf, .class_tid = 1, .hdr_sig_id = 10, @@ -35282,7 +36216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1596] = { + [1640] = { .class_hid = BNXT_ULP_CLASS_HID_38ecf, .class_tid = 1, .hdr_sig_id = 10, @@ -35302,7 +36236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1597] = { + [1641] = { .class_hid = BNXT_ULP_CLASS_HID_255b, .class_tid = 1, .hdr_sig_id = 10, @@ -35319,7 +36253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1598] = { + [1642] = { .class_hid = BNXT_ULP_CLASS_HID_2b97, .class_tid = 1, .hdr_sig_id = 10, @@ -35337,7 +36271,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1599] = { + [1643] = { + .class_hid = BNXT_ULP_CLASS_HID_1847, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1644] = { .class_hid = BNXT_ULP_CLASS_HID_4f0b, .class_tid = 1, .hdr_sig_id = 10, @@ -35356,7 +36309,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1600] = { + [1645] = { + .class_hid = BNXT_ULP_CLASS_HID_3c3b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1646] = { .class_hid = BNXT_ULP_CLASS_HID_1633, .class_tid = 1, .hdr_sig_id = 10, @@ -35375,7 +36348,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1601] = { + [1647] = { + .class_hid = BNXT_ULP_CLASS_HID_02e3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1648] = { .class_hid = BNXT_ULP_CLASS_HID_39a7, .class_tid = 1, .hdr_sig_id = 10, @@ -35395,7 +36388,46 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1602] = { + [1649] = { + .class_hid = BNXT_ULP_CLASS_HID_2657, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1650] = { + .class_hid = BNXT_ULP_CLASS_HID_120b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1651] = { .class_hid = BNXT_ULP_CLASS_HID_48cf, .class_tid = 1, .hdr_sig_id = 10, @@ -35413,7 +36445,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1603] = { + [1652] = { + .class_hid = BNXT_ULP_CLASS_HID_35ff, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1653] = { .class_hid = BNXT_ULP_CLASS_HID_0ff7, .class_tid = 1, .hdr_sig_id = 10, @@ -35431,7 +36482,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1604] = { + [1654] = { + .class_hid = BNXT_ULP_CLASS_HID_5953, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1655] = { .class_hid = BNXT_ULP_CLASS_HID_336b, .class_tid = 1, .hdr_sig_id = 10, @@ -35450,7 +36520,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1605] = { + [1656] = { + .class_hid = BNXT_ULP_CLASS_HID_201b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 130, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1657] = { .class_hid = BNXT_ULP_CLASS_HID_257f7, .class_tid = 1, .hdr_sig_id = 11, @@ -35469,7 +36559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1606] = { + [1658] = { .class_hid = BNXT_ULP_CLASS_HID_2858b, .class_tid = 1, .hdr_sig_id = 11, @@ -35489,7 +36579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1607] = { + [1659] = { .class_hid = BNXT_ULP_CLASS_HID_3108b, .class_tid = 1, .hdr_sig_id = 11, @@ -35509,7 +36599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1608] = { + [1660] = { .class_hid = BNXT_ULP_CLASS_HID_39b8b, .class_tid = 1, .hdr_sig_id = 11, @@ -35530,7 +36620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1609] = { + [1661] = { .class_hid = BNXT_ULP_CLASS_HID_24427, .class_tid = 1, .hdr_sig_id = 11, @@ -35550,7 +36640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1610] = { + [1662] = { .class_hid = BNXT_ULP_CLASS_HID_2cf27, .class_tid = 1, .hdr_sig_id = 11, @@ -35571,7 +36661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1611] = { + [1663] = { .class_hid = BNXT_ULP_CLASS_HID_35a27, .class_tid = 1, .hdr_sig_id = 11, @@ -35592,7 +36682,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1612] = { + [1664] = { .class_hid = BNXT_ULP_CLASS_HID_388fb, .class_tid = 1, .hdr_sig_id = 11, @@ -35614,7 +36704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1613] = { + [1665] = { .class_hid = BNXT_ULP_CLASS_HID_23ffb, .class_tid = 1, .hdr_sig_id = 11, @@ -35635,7 +36725,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1614] = { + [1666] = { .class_hid = BNXT_ULP_CLASS_HID_2cafb, .class_tid = 1, .hdr_sig_id = 11, @@ -35657,7 +36747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1615] = { + [1667] = { .class_hid = BNXT_ULP_CLASS_HID_355fb, .class_tid = 1, .hdr_sig_id = 11, @@ -35679,7 +36769,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1616] = { + [1668] = { .class_hid = BNXT_ULP_CLASS_HID_3838f, .class_tid = 1, .hdr_sig_id = 11, @@ -35702,7 +36792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1617] = { + [1669] = { .class_hid = BNXT_ULP_CLASS_HID_2528b, .class_tid = 1, .hdr_sig_id = 11, @@ -35722,7 +36812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1618] = { + [1670] = { .class_hid = BNXT_ULP_CLASS_HID_2815f, .class_tid = 1, .hdr_sig_id = 11, @@ -35743,7 +36833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1619] = { + [1671] = { .class_hid = BNXT_ULP_CLASS_HID_30c5f, .class_tid = 1, .hdr_sig_id = 11, @@ -35764,7 +36854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1620] = { + [1672] = { .class_hid = BNXT_ULP_CLASS_HID_3975f, .class_tid = 1, .hdr_sig_id = 11, @@ -35786,7 +36876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1621] = { + [1673] = { .class_hid = BNXT_ULP_CLASS_HID_21e3f, .class_tid = 1, .hdr_sig_id = 11, @@ -35806,7 +36896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1622] = { + [1674] = { .class_hid = BNXT_ULP_CLASS_HID_2a93f, .class_tid = 1, .hdr_sig_id = 11, @@ -35827,7 +36917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1623] = { + [1675] = { .class_hid = BNXT_ULP_CLASS_HID_3343f, .class_tid = 1, .hdr_sig_id = 11, @@ -35848,7 +36938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1624] = { + [1676] = { .class_hid = BNXT_ULP_CLASS_HID_3bf3f, .class_tid = 1, .hdr_sig_id = 11, @@ -35870,7 +36960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1625] = { + [1677] = { .class_hid = BNXT_ULP_CLASS_HID_20b6f, .class_tid = 1, .hdr_sig_id = 11, @@ -35891,7 +36981,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1626] = { + [1678] = { .class_hid = BNXT_ULP_CLASS_HID_2966f, .class_tid = 1, .hdr_sig_id = 11, @@ -35913,7 +37003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1627] = { + [1679] = { .class_hid = BNXT_ULP_CLASS_HID_3216f, .class_tid = 1, .hdr_sig_id = 11, @@ -35935,7 +37025,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1628] = { + [1680] = { .class_hid = BNXT_ULP_CLASS_HID_3ac6f, .class_tid = 1, .hdr_sig_id = 11, @@ -35958,7 +37048,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1629] = { + [1681] = { .class_hid = BNXT_ULP_CLASS_HID_20623, .class_tid = 1, .hdr_sig_id = 11, @@ -35980,7 +37070,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1630] = { + [1682] = { .class_hid = BNXT_ULP_CLASS_HID_29123, .class_tid = 1, .hdr_sig_id = 11, @@ -36003,7 +37093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1631] = { + [1683] = { .class_hid = BNXT_ULP_CLASS_HID_31c23, .class_tid = 1, .hdr_sig_id = 11, @@ -36026,7 +37116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1632] = { + [1684] = { .class_hid = BNXT_ULP_CLASS_HID_3a723, .class_tid = 1, .hdr_sig_id = 11, @@ -36050,7 +37140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1633] = { + [1685] = { .class_hid = BNXT_ULP_CLASS_HID_219f3, .class_tid = 1, .hdr_sig_id = 11, @@ -36071,7 +37161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1634] = { + [1686] = { .class_hid = BNXT_ULP_CLASS_HID_2a4f3, .class_tid = 1, .hdr_sig_id = 11, @@ -36093,7 +37183,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1635] = { + [1687] = { .class_hid = BNXT_ULP_CLASS_HID_32ff3, .class_tid = 1, .hdr_sig_id = 11, @@ -36115,7 +37205,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1636] = { + [1688] = { .class_hid = BNXT_ULP_CLASS_HID_3baf3, .class_tid = 1, .hdr_sig_id = 11, @@ -36138,7 +37228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1637] = { + [1689] = { .class_hid = BNXT_ULP_CLASS_HID_24253, .class_tid = 1, .hdr_sig_id = 11, @@ -36158,7 +37248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1638] = { + [1690] = { .class_hid = BNXT_ULP_CLASS_HID_2cd53, .class_tid = 1, .hdr_sig_id = 11, @@ -36179,7 +37269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1639] = { + [1691] = { .class_hid = BNXT_ULP_CLASS_HID_35853, .class_tid = 1, .hdr_sig_id = 11, @@ -36200,7 +37290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1640] = { + [1692] = { .class_hid = BNXT_ULP_CLASS_HID_38667, .class_tid = 1, .hdr_sig_id = 11, @@ -36222,7 +37312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1641] = { + [1693] = { .class_hid = BNXT_ULP_CLASS_HID_22e83, .class_tid = 1, .hdr_sig_id = 11, @@ -36243,7 +37333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1642] = { + [1694] = { .class_hid = BNXT_ULP_CLASS_HID_2b983, .class_tid = 1, .hdr_sig_id = 11, @@ -36265,7 +37355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1643] = { + [1695] = { .class_hid = BNXT_ULP_CLASS_HID_34483, .class_tid = 1, .hdr_sig_id = 11, @@ -36287,7 +37377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1644] = { + [1696] = { .class_hid = BNXT_ULP_CLASS_HID_3cf83, .class_tid = 1, .hdr_sig_id = 11, @@ -36310,7 +37400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1645] = { + [1697] = { .class_hid = BNXT_ULP_CLASS_HID_22a57, .class_tid = 1, .hdr_sig_id = 11, @@ -36332,7 +37422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1646] = { + [1698] = { .class_hid = BNXT_ULP_CLASS_HID_2b557, .class_tid = 1, .hdr_sig_id = 11, @@ -36355,7 +37445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1647] = { + [1699] = { .class_hid = BNXT_ULP_CLASS_HID_34057, .class_tid = 1, .hdr_sig_id = 11, @@ -36378,7 +37468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1648] = { + [1700] = { .class_hid = BNXT_ULP_CLASS_HID_3cb57, .class_tid = 1, .hdr_sig_id = 11, @@ -36402,7 +37492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1649] = { + [1701] = { .class_hid = BNXT_ULP_CLASS_HID_23d67, .class_tid = 1, .hdr_sig_id = 11, @@ -36423,7 +37513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1650] = { + [1702] = { .class_hid = BNXT_ULP_CLASS_HID_2c867, .class_tid = 1, .hdr_sig_id = 11, @@ -36445,7 +37535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1651] = { + [1703] = { .class_hid = BNXT_ULP_CLASS_HID_35367, .class_tid = 1, .hdr_sig_id = 11, @@ -36467,7 +37557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1652] = { + [1704] = { .class_hid = BNXT_ULP_CLASS_HID_3813b, .class_tid = 1, .hdr_sig_id = 11, @@ -36490,7 +37580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1653] = { + [1705] = { .class_hid = BNXT_ULP_CLASS_HID_2089b, .class_tid = 1, .hdr_sig_id = 11, @@ -36511,7 +37601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1654] = { + [1706] = { .class_hid = BNXT_ULP_CLASS_HID_2939b, .class_tid = 1, .hdr_sig_id = 11, @@ -36533,7 +37623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1655] = { + [1707] = { .class_hid = BNXT_ULP_CLASS_HID_31e9b, .class_tid = 1, .hdr_sig_id = 11, @@ -36555,7 +37645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1656] = { + [1708] = { .class_hid = BNXT_ULP_CLASS_HID_3a99b, .class_tid = 1, .hdr_sig_id = 11, @@ -36578,7 +37668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1657] = { + [1709] = { .class_hid = BNXT_ULP_CLASS_HID_25237, .class_tid = 1, .hdr_sig_id = 11, @@ -36600,7 +37690,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1658] = { + [1710] = { .class_hid = BNXT_ULP_CLASS_HID_280cb, .class_tid = 1, .hdr_sig_id = 11, @@ -36623,7 +37713,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1659] = { + [1711] = { .class_hid = BNXT_ULP_CLASS_HID_30bcb, .class_tid = 1, .hdr_sig_id = 11, @@ -36646,7 +37736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1660] = { + [1712] = { .class_hid = BNXT_ULP_CLASS_HID_396cb, .class_tid = 1, .hdr_sig_id = 11, @@ -36670,7 +37760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1661] = { + [1713] = { .class_hid = BNXT_ULP_CLASS_HID_24dcb, .class_tid = 1, .hdr_sig_id = 11, @@ -36693,7 +37783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1662] = { + [1714] = { .class_hid = BNXT_ULP_CLASS_HID_2d8cb, .class_tid = 1, .hdr_sig_id = 11, @@ -36717,7 +37807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1663] = { + [1715] = { .class_hid = BNXT_ULP_CLASS_HID_3069f, .class_tid = 1, .hdr_sig_id = 11, @@ -36741,7 +37831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1664] = { + [1716] = { .class_hid = BNXT_ULP_CLASS_HID_3919f, .class_tid = 1, .hdr_sig_id = 11, @@ -36766,7 +37856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1665] = { + [1717] = { .class_hid = BNXT_ULP_CLASS_HID_203af, .class_tid = 1, .hdr_sig_id = 11, @@ -36788,7 +37878,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1666] = { + [1718] = { .class_hid = BNXT_ULP_CLASS_HID_28eaf, .class_tid = 1, .hdr_sig_id = 11, @@ -36811,7 +37901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1667] = { + [1719] = { .class_hid = BNXT_ULP_CLASS_HID_319af, .class_tid = 1, .hdr_sig_id = 11, @@ -36834,7 +37924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1668] = { + [1720] = { .class_hid = BNXT_ULP_CLASS_HID_3a4af, .class_tid = 1, .hdr_sig_id = 11, @@ -36858,7 +37948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1669] = { + [1721] = { .class_hid = BNXT_ULP_CLASS_HID_2513b, .class_tid = 1, .hdr_sig_id = 11, @@ -36876,7 +37966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1670] = { + [1722] = { .class_hid = BNXT_ULP_CLASS_HID_2dc3b, .class_tid = 1, .hdr_sig_id = 11, @@ -36895,7 +37985,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1671] = { + [1723] = { .class_hid = BNXT_ULP_CLASS_HID_30acf, .class_tid = 1, .hdr_sig_id = 11, @@ -36914,7 +38004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1672] = { + [1724] = { .class_hid = BNXT_ULP_CLASS_HID_395cf, .class_tid = 1, .hdr_sig_id = 11, @@ -36934,7 +38024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1673] = { + [1725] = { .class_hid = BNXT_ULP_CLASS_HID_23e6b, .class_tid = 1, .hdr_sig_id = 11, @@ -36953,7 +38043,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1674] = { + [1726] = { .class_hid = BNXT_ULP_CLASS_HID_2c96b, .class_tid = 1, .hdr_sig_id = 11, @@ -36973,7 +38063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1675] = { + [1727] = { .class_hid = BNXT_ULP_CLASS_HID_3546b, .class_tid = 1, .hdr_sig_id = 11, @@ -36993,7 +38083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1676] = { + [1728] = { .class_hid = BNXT_ULP_CLASS_HID_3823f, .class_tid = 1, .hdr_sig_id = 11, @@ -37014,7 +38104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1677] = { + [1729] = { .class_hid = BNXT_ULP_CLASS_HID_2393f, .class_tid = 1, .hdr_sig_id = 11, @@ -37034,7 +38124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1678] = { + [1730] = { .class_hid = BNXT_ULP_CLASS_HID_2c43f, .class_tid = 1, .hdr_sig_id = 11, @@ -37055,7 +38145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1679] = { + [1731] = { .class_hid = BNXT_ULP_CLASS_HID_34f3f, .class_tid = 1, .hdr_sig_id = 11, @@ -37076,7 +38166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1680] = { + [1732] = { .class_hid = BNXT_ULP_CLASS_HID_3da3f, .class_tid = 1, .hdr_sig_id = 11, @@ -37098,7 +38188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1681] = { + [1733] = { .class_hid = BNXT_ULP_CLASS_HID_24ccf, .class_tid = 1, .hdr_sig_id = 11, @@ -37117,7 +38207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1682] = { + [1734] = { .class_hid = BNXT_ULP_CLASS_HID_2d7cf, .class_tid = 1, .hdr_sig_id = 11, @@ -37137,7 +38227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1683] = { + [1735] = { .class_hid = BNXT_ULP_CLASS_HID_30583, .class_tid = 1, .hdr_sig_id = 11, @@ -37157,7 +38247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1684] = { + [1736] = { .class_hid = BNXT_ULP_CLASS_HID_39083, .class_tid = 1, .hdr_sig_id = 11, @@ -37178,7 +38268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1685] = { + [1737] = { .class_hid = BNXT_ULP_CLASS_HID_21863, .class_tid = 1, .hdr_sig_id = 11, @@ -37197,7 +38287,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1686] = { + [1738] = { .class_hid = BNXT_ULP_CLASS_HID_2a363, .class_tid = 1, .hdr_sig_id = 11, @@ -37217,7 +38307,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1687] = { + [1739] = { .class_hid = BNXT_ULP_CLASS_HID_32e63, .class_tid = 1, .hdr_sig_id = 11, @@ -37237,7 +38327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1688] = { + [1740] = { .class_hid = BNXT_ULP_CLASS_HID_3b963, .class_tid = 1, .hdr_sig_id = 11, @@ -37258,7 +38348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1689] = { + [1741] = { .class_hid = BNXT_ULP_CLASS_HID_20553, .class_tid = 1, .hdr_sig_id = 11, @@ -37278,7 +38368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1690] = { + [1742] = { .class_hid = BNXT_ULP_CLASS_HID_29053, .class_tid = 1, .hdr_sig_id = 11, @@ -37299,7 +38389,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1691] = { + [1743] = { .class_hid = BNXT_ULP_CLASS_HID_31b53, .class_tid = 1, .hdr_sig_id = 11, @@ -37320,7 +38410,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1692] = { + [1744] = { .class_hid = BNXT_ULP_CLASS_HID_3a653, .class_tid = 1, .hdr_sig_id = 11, @@ -37342,7 +38432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1693] = { + [1745] = { .class_hid = BNXT_ULP_CLASS_HID_20067, .class_tid = 1, .hdr_sig_id = 11, @@ -37363,7 +38453,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1694] = { + [1746] = { .class_hid = BNXT_ULP_CLASS_HID_28b67, .class_tid = 1, .hdr_sig_id = 11, @@ -37385,7 +38475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1695] = { + [1747] = { .class_hid = BNXT_ULP_CLASS_HID_31667, .class_tid = 1, .hdr_sig_id = 11, @@ -37407,7 +38497,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1696] = { + [1748] = { .class_hid = BNXT_ULP_CLASS_HID_3a167, .class_tid = 1, .hdr_sig_id = 11, @@ -37430,7 +38520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1697] = { + [1749] = { .class_hid = BNXT_ULP_CLASS_HID_21337, .class_tid = 1, .hdr_sig_id = 11, @@ -37450,7 +38540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1698] = { + [1750] = { .class_hid = BNXT_ULP_CLASS_HID_29e37, .class_tid = 1, .hdr_sig_id = 11, @@ -37471,7 +38561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1699] = { + [1751] = { .class_hid = BNXT_ULP_CLASS_HID_32937, .class_tid = 1, .hdr_sig_id = 11, @@ -37492,7 +38582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1700] = { + [1752] = { .class_hid = BNXT_ULP_CLASS_HID_3b437, .class_tid = 1, .hdr_sig_id = 11, @@ -37514,7 +38604,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1701] = { + [1753] = { .class_hid = BNXT_ULP_CLASS_HID_23b97, .class_tid = 1, .hdr_sig_id = 11, @@ -37533,7 +38623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1702] = { + [1754] = { .class_hid = BNXT_ULP_CLASS_HID_2c697, .class_tid = 1, .hdr_sig_id = 11, @@ -37553,7 +38643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1703] = { + [1755] = { .class_hid = BNXT_ULP_CLASS_HID_35197, .class_tid = 1, .hdr_sig_id = 11, @@ -37573,7 +38663,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1704] = { + [1756] = { .class_hid = BNXT_ULP_CLASS_HID_3dc97, .class_tid = 1, .hdr_sig_id = 11, @@ -37594,7 +38684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1705] = { + [1757] = { .class_hid = BNXT_ULP_CLASS_HID_228c7, .class_tid = 1, .hdr_sig_id = 11, @@ -37614,7 +38704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1706] = { + [1758] = { .class_hid = BNXT_ULP_CLASS_HID_2b3c7, .class_tid = 1, .hdr_sig_id = 11, @@ -37635,7 +38725,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1707] = { + [1759] = { .class_hid = BNXT_ULP_CLASS_HID_33ec7, .class_tid = 1, .hdr_sig_id = 11, @@ -37656,7 +38746,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1708] = { + [1760] = { .class_hid = BNXT_ULP_CLASS_HID_3c9c7, .class_tid = 1, .hdr_sig_id = 11, @@ -37678,7 +38768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1709] = { + [1761] = { .class_hid = BNXT_ULP_CLASS_HID_2239b, .class_tid = 1, .hdr_sig_id = 11, @@ -37699,7 +38789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1710] = { + [1762] = { .class_hid = BNXT_ULP_CLASS_HID_2ae9b, .class_tid = 1, .hdr_sig_id = 11, @@ -37721,7 +38811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1711] = { + [1763] = { .class_hid = BNXT_ULP_CLASS_HID_3399b, .class_tid = 1, .hdr_sig_id = 11, @@ -37743,7 +38833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1712] = { + [1764] = { .class_hid = BNXT_ULP_CLASS_HID_3c49b, .class_tid = 1, .hdr_sig_id = 11, @@ -37766,7 +38856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1713] = { + [1765] = { .class_hid = BNXT_ULP_CLASS_HID_236ab, .class_tid = 1, .hdr_sig_id = 11, @@ -37786,7 +38876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1714] = { + [1766] = { .class_hid = BNXT_ULP_CLASS_HID_2c1ab, .class_tid = 1, .hdr_sig_id = 11, @@ -37807,7 +38897,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1715] = { + [1767] = { .class_hid = BNXT_ULP_CLASS_HID_34cab, .class_tid = 1, .hdr_sig_id = 11, @@ -37828,7 +38918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1716] = { + [1768] = { .class_hid = BNXT_ULP_CLASS_HID_3d7ab, .class_tid = 1, .hdr_sig_id = 11, @@ -37850,7 +38940,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1717] = { + [1769] = { .class_hid = BNXT_ULP_CLASS_HID_202df, .class_tid = 1, .hdr_sig_id = 11, @@ -37870,7 +38960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1718] = { + [1770] = { .class_hid = BNXT_ULP_CLASS_HID_28ddf, .class_tid = 1, .hdr_sig_id = 11, @@ -37891,7 +38981,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1719] = { + [1771] = { .class_hid = BNXT_ULP_CLASS_HID_318df, .class_tid = 1, .hdr_sig_id = 11, @@ -37912,7 +39002,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1720] = { + [1772] = { .class_hid = BNXT_ULP_CLASS_HID_3a3df, .class_tid = 1, .hdr_sig_id = 11, @@ -37934,7 +39024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1721] = { + [1773] = { .class_hid = BNXT_ULP_CLASS_HID_24c7b, .class_tid = 1, .hdr_sig_id = 11, @@ -37955,7 +39045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1722] = { + [1774] = { .class_hid = BNXT_ULP_CLASS_HID_2d77b, .class_tid = 1, .hdr_sig_id = 11, @@ -37977,7 +39067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1723] = { + [1775] = { .class_hid = BNXT_ULP_CLASS_HID_3050f, .class_tid = 1, .hdr_sig_id = 11, @@ -37999,7 +39089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1724] = { + [1776] = { .class_hid = BNXT_ULP_CLASS_HID_3900f, .class_tid = 1, .hdr_sig_id = 11, @@ -38022,7 +39112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1725] = { + [1777] = { .class_hid = BNXT_ULP_CLASS_HID_2470f, .class_tid = 1, .hdr_sig_id = 11, @@ -38044,7 +39134,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1726] = { + [1778] = { .class_hid = BNXT_ULP_CLASS_HID_2d20f, .class_tid = 1, .hdr_sig_id = 11, @@ -38067,7 +39157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1727] = { + [1779] = { .class_hid = BNXT_ULP_CLASS_HID_300c3, .class_tid = 1, .hdr_sig_id = 11, @@ -38090,7 +39180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1728] = { + [1780] = { .class_hid = BNXT_ULP_CLASS_HID_38bc3, .class_tid = 1, .hdr_sig_id = 11, @@ -38114,7 +39204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1729] = { + [1781] = { .class_hid = BNXT_ULP_CLASS_HID_25adf, .class_tid = 1, .hdr_sig_id = 11, @@ -38135,7 +39225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1730] = { + [1782] = { .class_hid = BNXT_ULP_CLASS_HID_28893, .class_tid = 1, .hdr_sig_id = 11, @@ -38157,7 +39247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1731] = { + [1783] = { .class_hid = BNXT_ULP_CLASS_HID_31393, .class_tid = 1, .hdr_sig_id = 11, @@ -38179,7 +39269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1732] = { + [1784] = { .class_hid = BNXT_ULP_CLASS_HID_39e93, .class_tid = 1, .hdr_sig_id = 11, @@ -38202,7 +39292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1733] = { + [1785] = { .class_hid = BNXT_ULP_CLASS_HID_24b7f, .class_tid = 1, .hdr_sig_id = 11, @@ -38220,7 +39310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1734] = { + [1786] = { .class_hid = BNXT_ULP_CLASS_HID_2d67f, .class_tid = 1, .hdr_sig_id = 11, @@ -38239,7 +39329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1735] = { + [1787] = { .class_hid = BNXT_ULP_CLASS_HID_30433, .class_tid = 1, .hdr_sig_id = 11, @@ -38258,7 +39348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1736] = { + [1788] = { .class_hid = BNXT_ULP_CLASS_HID_38f33, .class_tid = 1, .hdr_sig_id = 11, @@ -38278,7 +39368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1737] = { + [1789] = { .class_hid = BNXT_ULP_CLASS_HID_237af, .class_tid = 1, .hdr_sig_id = 11, @@ -38297,7 +39387,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1738] = { + [1790] = { .class_hid = BNXT_ULP_CLASS_HID_2c2af, .class_tid = 1, .hdr_sig_id = 11, @@ -38317,7 +39407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1739] = { + [1791] = { .class_hid = BNXT_ULP_CLASS_HID_34daf, .class_tid = 1, .hdr_sig_id = 11, @@ -38337,7 +39427,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1740] = { + [1792] = { .class_hid = BNXT_ULP_CLASS_HID_3d8af, .class_tid = 1, .hdr_sig_id = 11, @@ -38358,7 +39448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1741] = { + [1793] = { .class_hid = BNXT_ULP_CLASS_HID_23363, .class_tid = 1, .hdr_sig_id = 11, @@ -38378,7 +39468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1742] = { + [1794] = { .class_hid = BNXT_ULP_CLASS_HID_2be63, .class_tid = 1, .hdr_sig_id = 11, @@ -38399,7 +39489,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1743] = { + [1795] = { .class_hid = BNXT_ULP_CLASS_HID_34963, .class_tid = 1, .hdr_sig_id = 11, @@ -38420,7 +39510,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1744] = { + [1796] = { .class_hid = BNXT_ULP_CLASS_HID_3d463, .class_tid = 1, .hdr_sig_id = 11, @@ -38442,7 +39532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1745] = { + [1797] = { .class_hid = BNXT_ULP_CLASS_HID_24633, .class_tid = 1, .hdr_sig_id = 11, @@ -38461,7 +39551,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1746] = { + [1798] = { .class_hid = BNXT_ULP_CLASS_HID_2d133, .class_tid = 1, .hdr_sig_id = 11, @@ -38481,7 +39571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1747] = { + [1799] = { .class_hid = BNXT_ULP_CLASS_HID_35c33, .class_tid = 1, .hdr_sig_id = 11, @@ -38501,7 +39591,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1748] = { + [1800] = { .class_hid = BNXT_ULP_CLASS_HID_38ac7, .class_tid = 1, .hdr_sig_id = 11, @@ -38522,7 +39612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1749] = { + [1801] = { .class_hid = BNXT_ULP_CLASS_HID_211a7, .class_tid = 1, .hdr_sig_id = 11, @@ -38541,7 +39631,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1750] = { + [1802] = { .class_hid = BNXT_ULP_CLASS_HID_29ca7, .class_tid = 1, .hdr_sig_id = 11, @@ -38561,7 +39651,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1751] = { + [1803] = { .class_hid = BNXT_ULP_CLASS_HID_327a7, .class_tid = 1, .hdr_sig_id = 11, @@ -38581,7 +39671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1752] = { + [1804] = { .class_hid = BNXT_ULP_CLASS_HID_3b2a7, .class_tid = 1, .hdr_sig_id = 11, @@ -38602,7 +39692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1753] = { + [1805] = { .class_hid = BNXT_ULP_CLASS_HID_25bc3, .class_tid = 1, .hdr_sig_id = 11, @@ -38622,7 +39712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1754] = { + [1806] = { .class_hid = BNXT_ULP_CLASS_HID_28997, .class_tid = 1, .hdr_sig_id = 11, @@ -38643,7 +39733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1755] = { + [1807] = { .class_hid = BNXT_ULP_CLASS_HID_31497, .class_tid = 1, .hdr_sig_id = 11, @@ -38664,7 +39754,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1756] = { + [1808] = { .class_hid = BNXT_ULP_CLASS_HID_39f97, .class_tid = 1, .hdr_sig_id = 11, @@ -38686,7 +39776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1757] = { + [1809] = { .class_hid = BNXT_ULP_CLASS_HID_25697, .class_tid = 1, .hdr_sig_id = 11, @@ -38707,7 +39797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1758] = { + [1810] = { .class_hid = BNXT_ULP_CLASS_HID_284ab, .class_tid = 1, .hdr_sig_id = 11, @@ -38729,7 +39819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1759] = { + [1811] = { .class_hid = BNXT_ULP_CLASS_HID_30fab, .class_tid = 1, .hdr_sig_id = 11, @@ -38751,7 +39841,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1760] = { + [1812] = { .class_hid = BNXT_ULP_CLASS_HID_39aab, .class_tid = 1, .hdr_sig_id = 11, @@ -38774,7 +39864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1761] = { + [1813] = { .class_hid = BNXT_ULP_CLASS_HID_20d7b, .class_tid = 1, .hdr_sig_id = 11, @@ -38794,7 +39884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1762] = { + [1814] = { .class_hid = BNXT_ULP_CLASS_HID_2987b, .class_tid = 1, .hdr_sig_id = 11, @@ -38815,7 +39905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1763] = { + [1815] = { .class_hid = BNXT_ULP_CLASS_HID_3237b, .class_tid = 1, .hdr_sig_id = 11, @@ -38836,7 +39926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1764] = { + [1816] = { .class_hid = BNXT_ULP_CLASS_HID_3ae7b, .class_tid = 1, .hdr_sig_id = 11, @@ -38858,7 +39948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1765] = { + [1817] = { .class_hid = BNXT_ULP_CLASS_HID_235db, .class_tid = 1, .hdr_sig_id = 11, @@ -38877,7 +39967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1766] = { + [1818] = { .class_hid = BNXT_ULP_CLASS_HID_2c0db, .class_tid = 1, .hdr_sig_id = 11, @@ -38897,7 +39987,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1767] = { + [1819] = { .class_hid = BNXT_ULP_CLASS_HID_34bdb, .class_tid = 1, .hdr_sig_id = 11, @@ -38917,7 +40007,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1768] = { + [1820] = { .class_hid = BNXT_ULP_CLASS_HID_3d6db, .class_tid = 1, .hdr_sig_id = 11, @@ -38938,7 +40028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1769] = { + [1821] = { .class_hid = BNXT_ULP_CLASS_HID_2220b, .class_tid = 1, .hdr_sig_id = 11, @@ -38958,7 +40048,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1770] = { + [1822] = { .class_hid = BNXT_ULP_CLASS_HID_2ad0b, .class_tid = 1, .hdr_sig_id = 11, @@ -38979,7 +40069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1771] = { + [1823] = { .class_hid = BNXT_ULP_CLASS_HID_3380b, .class_tid = 1, .hdr_sig_id = 11, @@ -39000,7 +40090,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1772] = { + [1824] = { .class_hid = BNXT_ULP_CLASS_HID_3c30b, .class_tid = 1, .hdr_sig_id = 11, @@ -39022,7 +40112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1773] = { + [1825] = { .class_hid = BNXT_ULP_CLASS_HID_21ddf, .class_tid = 1, .hdr_sig_id = 11, @@ -39043,7 +40133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1774] = { + [1826] = { .class_hid = BNXT_ULP_CLASS_HID_2a8df, .class_tid = 1, .hdr_sig_id = 11, @@ -39065,7 +40155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1775] = { + [1827] = { .class_hid = BNXT_ULP_CLASS_HID_333df, .class_tid = 1, .hdr_sig_id = 11, @@ -39087,7 +40177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1776] = { + [1828] = { .class_hid = BNXT_ULP_CLASS_HID_3bedf, .class_tid = 1, .hdr_sig_id = 11, @@ -39110,7 +40200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1777] = { + [1829] = { .class_hid = BNXT_ULP_CLASS_HID_230ef, .class_tid = 1, .hdr_sig_id = 11, @@ -39130,7 +40220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1778] = { + [1830] = { .class_hid = BNXT_ULP_CLASS_HID_2bbef, .class_tid = 1, .hdr_sig_id = 11, @@ -39151,7 +40241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1779] = { + [1831] = { .class_hid = BNXT_ULP_CLASS_HID_346ef, .class_tid = 1, .hdr_sig_id = 11, @@ -39172,7 +40262,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1780] = { + [1832] = { .class_hid = BNXT_ULP_CLASS_HID_3d1ef, .class_tid = 1, .hdr_sig_id = 11, @@ -39194,7 +40284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1781] = { + [1833] = { .class_hid = BNXT_ULP_CLASS_HID_2594f, .class_tid = 1, .hdr_sig_id = 11, @@ -39214,7 +40304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1782] = { + [1834] = { .class_hid = BNXT_ULP_CLASS_HID_28703, .class_tid = 1, .hdr_sig_id = 11, @@ -39235,7 +40325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1783] = { + [1835] = { .class_hid = BNXT_ULP_CLASS_HID_31203, .class_tid = 1, .hdr_sig_id = 11, @@ -39256,7 +40346,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1784] = { + [1836] = { .class_hid = BNXT_ULP_CLASS_HID_39d03, .class_tid = 1, .hdr_sig_id = 11, @@ -39278,7 +40368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1785] = { + [1837] = { .class_hid = BNXT_ULP_CLASS_HID_245bf, .class_tid = 1, .hdr_sig_id = 11, @@ -39299,7 +40389,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1786] = { + [1838] = { .class_hid = BNXT_ULP_CLASS_HID_2d0bf, .class_tid = 1, .hdr_sig_id = 11, @@ -39321,7 +40411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1787] = { + [1839] = { .class_hid = BNXT_ULP_CLASS_HID_35bbf, .class_tid = 1, .hdr_sig_id = 11, @@ -39343,7 +40433,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1788] = { + [1840] = { .class_hid = BNXT_ULP_CLASS_HID_38a73, .class_tid = 1, .hdr_sig_id = 11, @@ -39366,7 +40456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1789] = { + [1841] = { .class_hid = BNXT_ULP_CLASS_HID_24173, .class_tid = 1, .hdr_sig_id = 11, @@ -39388,7 +40478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1790] = { + [1842] = { .class_hid = BNXT_ULP_CLASS_HID_2cc73, .class_tid = 1, .hdr_sig_id = 11, @@ -39411,7 +40501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1791] = { + [1843] = { .class_hid = BNXT_ULP_CLASS_HID_35773, .class_tid = 1, .hdr_sig_id = 11, @@ -39434,7 +40524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1792] = { + [1844] = { .class_hid = BNXT_ULP_CLASS_HID_38507, .class_tid = 1, .hdr_sig_id = 11, @@ -39458,7 +40548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1793] = { + [1845] = { .class_hid = BNXT_ULP_CLASS_HID_25403, .class_tid = 1, .hdr_sig_id = 11, @@ -39479,7 +40569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1794] = { + [1846] = { .class_hid = BNXT_ULP_CLASS_HID_282d7, .class_tid = 1, .hdr_sig_id = 11, @@ -39501,7 +40591,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1795] = { + [1847] = { .class_hid = BNXT_ULP_CLASS_HID_30dd7, .class_tid = 1, .hdr_sig_id = 11, @@ -39523,7 +40613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1796] = { + [1848] = { .class_hid = BNXT_ULP_CLASS_HID_398d7, .class_tid = 1, .hdr_sig_id = 11, @@ -39546,7 +40636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1797] = { + [1849] = { .class_hid = BNXT_ULP_CLASS_HID_244a3, .class_tid = 1, .hdr_sig_id = 11, @@ -39563,7 +40653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1798] = { + [1850] = { .class_hid = BNXT_ULP_CLASS_HID_2cfa3, .class_tid = 1, .hdr_sig_id = 11, @@ -39581,7 +40671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1799] = { + [1851] = { .class_hid = BNXT_ULP_CLASS_HID_35aa3, .class_tid = 1, .hdr_sig_id = 11, @@ -39599,7 +40689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1800] = { + [1852] = { .class_hid = BNXT_ULP_CLASS_HID_38977, .class_tid = 1, .hdr_sig_id = 11, @@ -39618,7 +40708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1801] = { + [1853] = { .class_hid = BNXT_ULP_CLASS_HID_23193, .class_tid = 1, .hdr_sig_id = 11, @@ -39636,7 +40726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1802] = { + [1854] = { .class_hid = BNXT_ULP_CLASS_HID_2bc93, .class_tid = 1, .hdr_sig_id = 11, @@ -39655,7 +40745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1803] = { + [1855] = { .class_hid = BNXT_ULP_CLASS_HID_34793, .class_tid = 1, .hdr_sig_id = 11, @@ -39674,7 +40764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1804] = { + [1856] = { .class_hid = BNXT_ULP_CLASS_HID_3d293, .class_tid = 1, .hdr_sig_id = 11, @@ -39694,7 +40784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1805] = { + [1857] = { .class_hid = BNXT_ULP_CLASS_HID_22ca7, .class_tid = 1, .hdr_sig_id = 11, @@ -39713,7 +40803,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1806] = { + [1858] = { .class_hid = BNXT_ULP_CLASS_HID_2b7a7, .class_tid = 1, .hdr_sig_id = 11, @@ -39733,7 +40823,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1807] = { + [1859] = { .class_hid = BNXT_ULP_CLASS_HID_342a7, .class_tid = 1, .hdr_sig_id = 11, @@ -39753,7 +40843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1808] = { + [1860] = { .class_hid = BNXT_ULP_CLASS_HID_3cda7, .class_tid = 1, .hdr_sig_id = 11, @@ -39774,7 +40864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1809] = { + [1861] = { .class_hid = BNXT_ULP_CLASS_HID_24077, .class_tid = 1, .hdr_sig_id = 11, @@ -39792,7 +40882,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1810] = { + [1862] = { .class_hid = BNXT_ULP_CLASS_HID_2cb77, .class_tid = 1, .hdr_sig_id = 11, @@ -39811,7 +40901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1811] = { + [1863] = { .class_hid = BNXT_ULP_CLASS_HID_35677, .class_tid = 1, .hdr_sig_id = 11, @@ -39830,7 +40920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1812] = { + [1864] = { .class_hid = BNXT_ULP_CLASS_HID_3840b, .class_tid = 1, .hdr_sig_id = 11, @@ -39850,7 +40940,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1813] = { + [1865] = { .class_hid = BNXT_ULP_CLASS_HID_20beb, .class_tid = 1, .hdr_sig_id = 11, @@ -39868,7 +40958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1814] = { + [1866] = { .class_hid = BNXT_ULP_CLASS_HID_296eb, .class_tid = 1, .hdr_sig_id = 11, @@ -39887,7 +40977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1815] = { + [1867] = { .class_hid = BNXT_ULP_CLASS_HID_321eb, .class_tid = 1, .hdr_sig_id = 11, @@ -39906,7 +40996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1816] = { + [1868] = { .class_hid = BNXT_ULP_CLASS_HID_3aceb, .class_tid = 1, .hdr_sig_id = 11, @@ -39926,7 +41016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1817] = { + [1869] = { .class_hid = BNXT_ULP_CLASS_HID_25507, .class_tid = 1, .hdr_sig_id = 11, @@ -39945,7 +41035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1818] = { + [1870] = { .class_hid = BNXT_ULP_CLASS_HID_283db, .class_tid = 1, .hdr_sig_id = 11, @@ -39965,7 +41055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1819] = { + [1871] = { .class_hid = BNXT_ULP_CLASS_HID_30edb, .class_tid = 1, .hdr_sig_id = 11, @@ -39985,7 +41075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1820] = { + [1872] = { .class_hid = BNXT_ULP_CLASS_HID_399db, .class_tid = 1, .hdr_sig_id = 11, @@ -40006,7 +41096,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1821] = { + [1873] = { .class_hid = BNXT_ULP_CLASS_HID_250db, .class_tid = 1, .hdr_sig_id = 11, @@ -40026,7 +41116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1822] = { + [1874] = { .class_hid = BNXT_ULP_CLASS_HID_2dbdb, .class_tid = 1, .hdr_sig_id = 11, @@ -40047,7 +41137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1823] = { + [1875] = { .class_hid = BNXT_ULP_CLASS_HID_309ef, .class_tid = 1, .hdr_sig_id = 11, @@ -40068,7 +41158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1824] = { + [1876] = { .class_hid = BNXT_ULP_CLASS_HID_394ef, .class_tid = 1, .hdr_sig_id = 11, @@ -40090,7 +41180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1825] = { + [1877] = { .class_hid = BNXT_ULP_CLASS_HID_206bf, .class_tid = 1, .hdr_sig_id = 11, @@ -40109,7 +41199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1826] = { + [1878] = { .class_hid = BNXT_ULP_CLASS_HID_291bf, .class_tid = 1, .hdr_sig_id = 11, @@ -40129,7 +41219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1827] = { + [1879] = { .class_hid = BNXT_ULP_CLASS_HID_31cbf, .class_tid = 1, .hdr_sig_id = 11, @@ -40149,7 +41239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1828] = { + [1880] = { .class_hid = BNXT_ULP_CLASS_HID_3a7bf, .class_tid = 1, .hdr_sig_id = 11, @@ -40170,7 +41260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1829] = { + [1881] = { .class_hid = BNXT_ULP_CLASS_HID_22f1f, .class_tid = 1, .hdr_sig_id = 11, @@ -40188,7 +41278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1830] = { + [1882] = { .class_hid = BNXT_ULP_CLASS_HID_2ba1f, .class_tid = 1, .hdr_sig_id = 11, @@ -40207,7 +41297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1831] = { + [1883] = { .class_hid = BNXT_ULP_CLASS_HID_3451f, .class_tid = 1, .hdr_sig_id = 11, @@ -40226,7 +41316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1832] = { + [1884] = { .class_hid = BNXT_ULP_CLASS_HID_3d01f, .class_tid = 1, .hdr_sig_id = 11, @@ -40246,7 +41336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1833] = { + [1885] = { .class_hid = BNXT_ULP_CLASS_HID_21c4f, .class_tid = 1, .hdr_sig_id = 11, @@ -40265,7 +41355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1834] = { + [1886] = { .class_hid = BNXT_ULP_CLASS_HID_2a74f, .class_tid = 1, .hdr_sig_id = 11, @@ -40285,7 +41375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1835] = { + [1887] = { .class_hid = BNXT_ULP_CLASS_HID_3324f, .class_tid = 1, .hdr_sig_id = 11, @@ -40305,7 +41395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1836] = { + [1888] = { .class_hid = BNXT_ULP_CLASS_HID_3bd4f, .class_tid = 1, .hdr_sig_id = 11, @@ -40326,7 +41416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1837] = { + [1889] = { .class_hid = BNXT_ULP_CLASS_HID_21703, .class_tid = 1, .hdr_sig_id = 11, @@ -40346,7 +41436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1838] = { + [1890] = { .class_hid = BNXT_ULP_CLASS_HID_2a203, .class_tid = 1, .hdr_sig_id = 11, @@ -40367,7 +41457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1839] = { + [1891] = { .class_hid = BNXT_ULP_CLASS_HID_32d03, .class_tid = 1, .hdr_sig_id = 11, @@ -40388,7 +41478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1840] = { + [1892] = { .class_hid = BNXT_ULP_CLASS_HID_3b803, .class_tid = 1, .hdr_sig_id = 11, @@ -40410,7 +41500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1841] = { + [1893] = { .class_hid = BNXT_ULP_CLASS_HID_22ad3, .class_tid = 1, .hdr_sig_id = 11, @@ -40429,7 +41519,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1842] = { + [1894] = { .class_hid = BNXT_ULP_CLASS_HID_2b5d3, .class_tid = 1, .hdr_sig_id = 11, @@ -40449,7 +41539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1843] = { + [1895] = { .class_hid = BNXT_ULP_CLASS_HID_340d3, .class_tid = 1, .hdr_sig_id = 11, @@ -40469,7 +41559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1844] = { + [1896] = { .class_hid = BNXT_ULP_CLASS_HID_3cbd3, .class_tid = 1, .hdr_sig_id = 11, @@ -40490,7 +41580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1845] = { + [1897] = { .class_hid = BNXT_ULP_CLASS_HID_252b3, .class_tid = 1, .hdr_sig_id = 11, @@ -40509,7 +41599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1846] = { + [1898] = { .class_hid = BNXT_ULP_CLASS_HID_28147, .class_tid = 1, .hdr_sig_id = 11, @@ -40529,7 +41619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1847] = { + [1899] = { .class_hid = BNXT_ULP_CLASS_HID_30c47, .class_tid = 1, .hdr_sig_id = 11, @@ -40549,7 +41639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1848] = { + [1900] = { .class_hid = BNXT_ULP_CLASS_HID_39747, .class_tid = 1, .hdr_sig_id = 11, @@ -40570,7 +41660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1849] = { + [1901] = { .class_hid = BNXT_ULP_CLASS_HID_23fe3, .class_tid = 1, .hdr_sig_id = 11, @@ -40590,7 +41680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1850] = { + [1902] = { .class_hid = BNXT_ULP_CLASS_HID_2cae3, .class_tid = 1, .hdr_sig_id = 11, @@ -40611,7 +41701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1851] = { + [1903] = { .class_hid = BNXT_ULP_CLASS_HID_355e3, .class_tid = 1, .hdr_sig_id = 11, @@ -40632,7 +41722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1852] = { + [1904] = { .class_hid = BNXT_ULP_CLASS_HID_383b7, .class_tid = 1, .hdr_sig_id = 11, @@ -40654,7 +41744,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1853] = { + [1905] = { .class_hid = BNXT_ULP_CLASS_HID_23ab7, .class_tid = 1, .hdr_sig_id = 11, @@ -40675,7 +41765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1854] = { + [1906] = { .class_hid = BNXT_ULP_CLASS_HID_2c5b7, .class_tid = 1, .hdr_sig_id = 11, @@ -40697,7 +41787,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1855] = { + [1907] = { .class_hid = BNXT_ULP_CLASS_HID_350b7, .class_tid = 1, .hdr_sig_id = 11, @@ -40719,7 +41809,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1856] = { + [1908] = { .class_hid = BNXT_ULP_CLASS_HID_3dbb7, .class_tid = 1, .hdr_sig_id = 11, @@ -40742,7 +41832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1857] = { + [1909] = { .class_hid = BNXT_ULP_CLASS_HID_24e47, .class_tid = 1, .hdr_sig_id = 11, @@ -40762,7 +41852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1858] = { + [1910] = { .class_hid = BNXT_ULP_CLASS_HID_2d947, .class_tid = 1, .hdr_sig_id = 11, @@ -40783,7 +41873,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1859] = { + [1911] = { .class_hid = BNXT_ULP_CLASS_HID_3071b, .class_tid = 1, .hdr_sig_id = 11, @@ -40804,7 +41894,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1860] = { + [1912] = { .class_hid = BNXT_ULP_CLASS_HID_3921b, .class_tid = 1, .hdr_sig_id = 11, @@ -40826,7 +41916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1861] = { + [1913] = { .class_hid = BNXT_ULP_CLASS_HID_2326f, .class_tid = 1, .hdr_sig_id = 11, @@ -40843,7 +41933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1862] = { + [1914] = { .class_hid = BNXT_ULP_CLASS_HID_2bd6f, .class_tid = 1, .hdr_sig_id = 11, @@ -40861,7 +41951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1863] = { + [1915] = { .class_hid = BNXT_ULP_CLASS_HID_3486f, .class_tid = 1, .hdr_sig_id = 11, @@ -40879,7 +41969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1864] = { + [1916] = { .class_hid = BNXT_ULP_CLASS_HID_3d36f, .class_tid = 1, .hdr_sig_id = 11, @@ -40898,7 +41988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1865] = { + [1917] = { .class_hid = BNXT_ULP_CLASS_HID_21f5f, .class_tid = 1, .hdr_sig_id = 11, @@ -40916,7 +42006,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1866] = { + [1918] = { .class_hid = BNXT_ULP_CLASS_HID_2aa5f, .class_tid = 1, .hdr_sig_id = 11, @@ -40935,7 +42025,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1867] = { + [1919] = { .class_hid = BNXT_ULP_CLASS_HID_3355f, .class_tid = 1, .hdr_sig_id = 11, @@ -40954,7 +42044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1868] = { + [1920] = { .class_hid = BNXT_ULP_CLASS_HID_3c05f, .class_tid = 1, .hdr_sig_id = 11, @@ -40974,7 +42064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1869] = { + [1921] = { .class_hid = BNXT_ULP_CLASS_HID_21a13, .class_tid = 1, .hdr_sig_id = 11, @@ -40993,7 +42083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1870] = { + [1922] = { .class_hid = BNXT_ULP_CLASS_HID_2a513, .class_tid = 1, .hdr_sig_id = 11, @@ -41013,7 +42103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1871] = { + [1923] = { .class_hid = BNXT_ULP_CLASS_HID_33013, .class_tid = 1, .hdr_sig_id = 11, @@ -41033,7 +42123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1872] = { + [1924] = { .class_hid = BNXT_ULP_CLASS_HID_3bb13, .class_tid = 1, .hdr_sig_id = 11, @@ -41054,7 +42144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1873] = { + [1925] = { .class_hid = BNXT_ULP_CLASS_HID_22d23, .class_tid = 1, .hdr_sig_id = 11, @@ -41072,7 +42162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1874] = { + [1926] = { .class_hid = BNXT_ULP_CLASS_HID_2b823, .class_tid = 1, .hdr_sig_id = 11, @@ -41091,7 +42181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1875] = { + [1927] = { .class_hid = BNXT_ULP_CLASS_HID_34323, .class_tid = 1, .hdr_sig_id = 11, @@ -41110,7 +42200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1876] = { + [1928] = { .class_hid = BNXT_ULP_CLASS_HID_3ce23, .class_tid = 1, .hdr_sig_id = 11, @@ -41130,7 +42220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1877] = { + [1929] = { .class_hid = BNXT_ULP_CLASS_HID_25583, .class_tid = 1, .hdr_sig_id = 11, @@ -41148,7 +42238,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1878] = { + [1930] = { .class_hid = BNXT_ULP_CLASS_HID_28457, .class_tid = 1, .hdr_sig_id = 11, @@ -41167,7 +42257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1879] = { + [1931] = { .class_hid = BNXT_ULP_CLASS_HID_30f57, .class_tid = 1, .hdr_sig_id = 11, @@ -41186,7 +42276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1880] = { + [1932] = { .class_hid = BNXT_ULP_CLASS_HID_39a57, .class_tid = 1, .hdr_sig_id = 11, @@ -41206,7 +42296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1881] = { + [1933] = { .class_hid = BNXT_ULP_CLASS_HID_242f3, .class_tid = 1, .hdr_sig_id = 11, @@ -41225,7 +42315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1882] = { + [1934] = { .class_hid = BNXT_ULP_CLASS_HID_2cdf3, .class_tid = 1, .hdr_sig_id = 11, @@ -41245,7 +42335,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1883] = { + [1935] = { .class_hid = BNXT_ULP_CLASS_HID_358f3, .class_tid = 1, .hdr_sig_id = 11, @@ -41265,7 +42355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1884] = { + [1936] = { .class_hid = BNXT_ULP_CLASS_HID_38687, .class_tid = 1, .hdr_sig_id = 11, @@ -41286,7 +42376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1885] = { + [1937] = { .class_hid = BNXT_ULP_CLASS_HID_23d87, .class_tid = 1, .hdr_sig_id = 11, @@ -41306,7 +42396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1886] = { + [1938] = { .class_hid = BNXT_ULP_CLASS_HID_2c887, .class_tid = 1, .hdr_sig_id = 11, @@ -41327,7 +42417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1887] = { + [1939] = { .class_hid = BNXT_ULP_CLASS_HID_35387, .class_tid = 1, .hdr_sig_id = 11, @@ -41348,7 +42438,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1888] = { + [1940] = { .class_hid = BNXT_ULP_CLASS_HID_3825b, .class_tid = 1, .hdr_sig_id = 11, @@ -41370,7 +42460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1889] = { + [1941] = { .class_hid = BNXT_ULP_CLASS_HID_25157, .class_tid = 1, .hdr_sig_id = 11, @@ -41389,7 +42479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1890] = { + [1942] = { .class_hid = BNXT_ULP_CLASS_HID_2dc57, .class_tid = 1, .hdr_sig_id = 11, @@ -41409,7 +42499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1891] = { + [1943] = { .class_hid = BNXT_ULP_CLASS_HID_30a6b, .class_tid = 1, .hdr_sig_id = 11, @@ -41429,7 +42519,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1892] = { + [1944] = { .class_hid = BNXT_ULP_CLASS_HID_3956b, .class_tid = 1, .hdr_sig_id = 11, @@ -41450,7 +42540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1893] = { + [1945] = { .class_hid = BNXT_ULP_CLASS_HID_22c53, .class_tid = 1, .hdr_sig_id = 11, @@ -41466,7 +42556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1894] = { + [1946] = { .class_hid = BNXT_ULP_CLASS_HID_2b753, .class_tid = 1, .hdr_sig_id = 11, @@ -41483,7 +42573,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1895] = { + [1947] = { .class_hid = BNXT_ULP_CLASS_HID_34253, .class_tid = 1, .hdr_sig_id = 11, @@ -41500,7 +42590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1896] = { + [1948] = { .class_hid = BNXT_ULP_CLASS_HID_3cd53, .class_tid = 1, .hdr_sig_id = 11, @@ -41518,7 +42608,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1897] = { + [1949] = { .class_hid = BNXT_ULP_CLASS_HID_21883, .class_tid = 1, .hdr_sig_id = 11, @@ -41535,7 +42625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1898] = { + [1950] = { .class_hid = BNXT_ULP_CLASS_HID_2a383, .class_tid = 1, .hdr_sig_id = 11, @@ -41553,7 +42643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1899] = { + [1951] = { .class_hid = BNXT_ULP_CLASS_HID_32e83, .class_tid = 1, .hdr_sig_id = 11, @@ -41571,7 +42661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1900] = { + [1952] = { .class_hid = BNXT_ULP_CLASS_HID_3b983, .class_tid = 1, .hdr_sig_id = 11, @@ -41590,7 +42680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1901] = { + [1953] = { .class_hid = BNXT_ULP_CLASS_HID_21457, .class_tid = 1, .hdr_sig_id = 11, @@ -41608,7 +42698,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1902] = { + [1954] = { .class_hid = BNXT_ULP_CLASS_HID_29f57, .class_tid = 1, .hdr_sig_id = 11, @@ -41627,7 +42717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1903] = { + [1955] = { .class_hid = BNXT_ULP_CLASS_HID_32a57, .class_tid = 1, .hdr_sig_id = 11, @@ -41646,7 +42736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1904] = { + [1956] = { .class_hid = BNXT_ULP_CLASS_HID_3b557, .class_tid = 1, .hdr_sig_id = 11, @@ -41666,7 +42756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1905] = { + [1957] = { .class_hid = BNXT_ULP_CLASS_HID_22767, .class_tid = 1, .hdr_sig_id = 11, @@ -41683,7 +42773,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1906] = { + [1958] = { .class_hid = BNXT_ULP_CLASS_HID_2b267, .class_tid = 1, .hdr_sig_id = 11, @@ -41701,7 +42791,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1907] = { + [1959] = { .class_hid = BNXT_ULP_CLASS_HID_33d67, .class_tid = 1, .hdr_sig_id = 11, @@ -41719,7 +42809,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1908] = { + [1960] = { .class_hid = BNXT_ULP_CLASS_HID_3c867, .class_tid = 1, .hdr_sig_id = 11, @@ -41738,7 +42828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1909] = { + [1961] = { .class_hid = BNXT_ULP_CLASS_HID_24fc7, .class_tid = 1, .hdr_sig_id = 11, @@ -41755,7 +42845,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1910] = { + [1962] = { .class_hid = BNXT_ULP_CLASS_HID_2dac7, .class_tid = 1, .hdr_sig_id = 11, @@ -41773,7 +42863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1911] = { + [1963] = { .class_hid = BNXT_ULP_CLASS_HID_3089b, .class_tid = 1, .hdr_sig_id = 11, @@ -41791,7 +42881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1912] = { + [1964] = { .class_hid = BNXT_ULP_CLASS_HID_3939b, .class_tid = 1, .hdr_sig_id = 11, @@ -41810,7 +42900,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1913] = { + [1965] = { .class_hid = BNXT_ULP_CLASS_HID_23c37, .class_tid = 1, .hdr_sig_id = 11, @@ -41828,7 +42918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1914] = { + [1966] = { .class_hid = BNXT_ULP_CLASS_HID_2c737, .class_tid = 1, .hdr_sig_id = 11, @@ -41847,7 +42937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1915] = { + [1967] = { .class_hid = BNXT_ULP_CLASS_HID_35237, .class_tid = 1, .hdr_sig_id = 11, @@ -41866,7 +42956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1916] = { + [1968] = { .class_hid = BNXT_ULP_CLASS_HID_380cb, .class_tid = 1, .hdr_sig_id = 11, @@ -41886,7 +42976,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1917] = { + [1969] = { .class_hid = BNXT_ULP_CLASS_HID_237cb, .class_tid = 1, .hdr_sig_id = 11, @@ -41905,7 +42995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1918] = { + [1970] = { .class_hid = BNXT_ULP_CLASS_HID_2c2cb, .class_tid = 1, .hdr_sig_id = 11, @@ -41925,7 +43015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1919] = { + [1971] = { .class_hid = BNXT_ULP_CLASS_HID_34dcb, .class_tid = 1, .hdr_sig_id = 11, @@ -41945,7 +43035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1920] = { + [1972] = { .class_hid = BNXT_ULP_CLASS_HID_3d8cb, .class_tid = 1, .hdr_sig_id = 11, @@ -41966,7 +43056,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1921] = { + [1973] = { .class_hid = BNXT_ULP_CLASS_HID_24a9b, .class_tid = 1, .hdr_sig_id = 11, @@ -41984,7 +43074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1922] = { + [1974] = { .class_hid = BNXT_ULP_CLASS_HID_2d59b, .class_tid = 1, .hdr_sig_id = 11, @@ -42003,7 +43093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1923] = { + [1975] = { .class_hid = BNXT_ULP_CLASS_HID_303af, .class_tid = 1, .hdr_sig_id = 11, @@ -42022,7 +43112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1924] = { + [1976] = { .class_hid = BNXT_ULP_CLASS_HID_38eaf, .class_tid = 1, .hdr_sig_id = 11, @@ -42042,7 +43132,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1925] = { + [1977] = { .class_hid = BNXT_ULP_CLASS_HID_253b, .class_tid = 1, .hdr_sig_id = 11, @@ -42059,7 +43149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1926] = { + [1978] = { .class_hid = BNXT_ULP_CLASS_HID_2bf7, .class_tid = 1, .hdr_sig_id = 11, @@ -42077,7 +43167,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1927] = { + [1979] = { + .class_hid = BNXT_ULP_CLASS_HID_1827, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1980] = { .class_hid = BNXT_ULP_CLASS_HID_4f6b, .class_tid = 1, .hdr_sig_id = 11, @@ -42096,7 +43205,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1928] = { + [1981] = { + .class_hid = BNXT_ULP_CLASS_HID_3c5b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1982] = { .class_hid = BNXT_ULP_CLASS_HID_1653, .class_tid = 1, .hdr_sig_id = 11, @@ -42115,7 +43244,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1929] = { + [1983] = { + .class_hid = BNXT_ULP_CLASS_HID_0283, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1984] = { .class_hid = BNXT_ULP_CLASS_HID_39c7, .class_tid = 1, .hdr_sig_id = 11, @@ -42135,7 +43284,46 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1930] = { + [1985] = { + .class_hid = BNXT_ULP_CLASS_HID_2637, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1986] = { + .class_hid = BNXT_ULP_CLASS_HID_126b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1987] = { .class_hid = BNXT_ULP_CLASS_HID_48af, .class_tid = 1, .hdr_sig_id = 11, @@ -42153,7 +43341,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1931] = { + [1988] = { + .class_hid = BNXT_ULP_CLASS_HID_359f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1989] = { .class_hid = BNXT_ULP_CLASS_HID_0f97, .class_tid = 1, .hdr_sig_id = 11, @@ -42171,7 +43378,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1932] = { + [1990] = { + .class_hid = BNXT_ULP_CLASS_HID_5933, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1991] = { .class_hid = BNXT_ULP_CLASS_HID_330b, .class_tid = 1, .hdr_sig_id = 11, @@ -42190,7 +43416,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1933] = { + [1992] = { + .class_hid = BNXT_ULP_CLASS_HID_207b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 142, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [1993] = { .class_hid = BNXT_ULP_CLASS_HID_374e, .class_tid = 2, .hdr_sig_id = 0, @@ -42207,7 +43453,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1934] = { + [1994] = { .class_hid = BNXT_ULP_CLASS_HID_11ee, .class_tid = 2, .hdr_sig_id = 0, @@ -42225,7 +43471,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1935] = { + [1995] = { .class_hid = BNXT_ULP_CLASS_HID_423a, .class_tid = 2, .hdr_sig_id = 0, @@ -42244,7 +43490,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1936] = { + [1996] = { .class_hid = BNXT_ULP_CLASS_HID_0cd6, .class_tid = 2, .hdr_sig_id = 0, @@ -42262,7 +43508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1937] = { + [1997] = { .class_hid = BNXT_ULP_CLASS_HID_310a, .class_tid = 2, .hdr_sig_id = 0, @@ -42278,7 +43524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1938] = { + [1998] = { .class_hid = BNXT_ULP_CLASS_HID_469e, .class_tid = 2, .hdr_sig_id = 0, @@ -42295,7 +43541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1939] = { + [1999] = { .class_hid = BNXT_ULP_CLASS_HID_5ce6, .class_tid = 2, .hdr_sig_id = 0, @@ -42313,7 +43559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1940] = { + [2000] = { .class_hid = BNXT_ULP_CLASS_HID_0692, .class_tid = 2, .hdr_sig_id = 0, @@ -42330,7 +43576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1941] = { + [2001] = { .class_hid = BNXT_ULP_CLASS_HID_1c7e, .class_tid = 2, .hdr_sig_id = 0, @@ -42346,7 +43592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1942] = { + [2002] = { .class_hid = BNXT_ULP_CLASS_HID_55c2, .class_tid = 2, .hdr_sig_id = 0, @@ -42363,7 +43609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1943] = { + [2003] = { .class_hid = BNXT_ULP_CLASS_HID_2b2a, .class_tid = 2, .hdr_sig_id = 0, @@ -42381,7 +43627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1944] = { + [2004] = { .class_hid = BNXT_ULP_CLASS_HID_15c6, .class_tid = 2, .hdr_sig_id = 0, @@ -42398,7 +43644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1945] = { + [2005] = { .class_hid = BNXT_ULP_CLASS_HID_163a, .class_tid = 2, .hdr_sig_id = 0, @@ -42413,7 +43659,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1946] = { + [2006] = { .class_hid = BNXT_ULP_CLASS_HID_2f8e, .class_tid = 2, .hdr_sig_id = 0, @@ -42429,7 +43675,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1947] = { + [2007] = { .class_hid = BNXT_ULP_CLASS_HID_2516, .class_tid = 2, .hdr_sig_id = 0, @@ -42446,7 +43692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1948] = { + [2008] = { .class_hid = BNXT_ULP_CLASS_HID_4b76, .class_tid = 2, .hdr_sig_id = 0, @@ -42462,7 +43708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1949] = { + [2009] = { .class_hid = BNXT_ULP_CLASS_HID_10e6, .class_tid = 2, .hdr_sig_id = 0, @@ -42477,7 +43723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1950] = { + [2010] = { .class_hid = BNXT_ULP_CLASS_HID_264a, .class_tid = 2, .hdr_sig_id = 0, @@ -42493,7 +43739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1951] = { + [2011] = { .class_hid = BNXT_ULP_CLASS_HID_3fd2, .class_tid = 2, .hdr_sig_id = 0, @@ -42510,7 +43756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1952] = { + [2012] = { .class_hid = BNXT_ULP_CLASS_HID_4532, .class_tid = 2, .hdr_sig_id = 0, @@ -42526,7 +43772,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1953] = { + [2013] = { .class_hid = BNXT_ULP_CLASS_HID_4996, .class_tid = 2, .hdr_sig_id = 0, @@ -42540,7 +43786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1954] = { + [2014] = { .class_hid = BNXT_ULP_CLASS_HID_2036, .class_tid = 2, .hdr_sig_id = 0, @@ -42555,7 +43801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1955] = { + [2015] = { .class_hid = BNXT_ULP_CLASS_HID_399e, .class_tid = 2, .hdr_sig_id = 0, @@ -42571,7 +43817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1956] = { + [2016] = { .class_hid = BNXT_ULP_CLASS_HID_5ffe, .class_tid = 2, .hdr_sig_id = 0, @@ -42586,7 +43832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1957] = { + [2017] = { .class_hid = BNXT_ULP_CLASS_HID_34fe, .class_tid = 2, .hdr_sig_id = 0, @@ -42601,7 +43847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1958] = { + [2018] = { .class_hid = BNXT_ULP_CLASS_HID_3a32, .class_tid = 2, .hdr_sig_id = 0, @@ -42617,7 +43863,40 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1959] = { + [2019] = { + .class_hid = BNXT_ULP_CLASS_HID_14d2, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 149, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2020] = { + .class_hid = BNXT_ULP_CLASS_HID_4a42, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 149, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2021] = { .class_hid = BNXT_ULP_CLASS_HID_376e, .class_tid = 2, .hdr_sig_id = 1, @@ -42635,7 +43914,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1960] = { + [2022] = { .class_hid = BNXT_ULP_CLASS_HID_12d6e, .class_tid = 2, .hdr_sig_id = 1, @@ -42654,7 +43933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1961] = { + [2023] = { .class_hid = BNXT_ULP_CLASS_HID_2436e, .class_tid = 2, .hdr_sig_id = 1, @@ -42673,7 +43952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1962] = { + [2024] = { .class_hid = BNXT_ULP_CLASS_HID_31dba, .class_tid = 2, .hdr_sig_id = 1, @@ -42693,7 +43972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1963] = { + [2025] = { .class_hid = BNXT_ULP_CLASS_HID_11ce, .class_tid = 2, .hdr_sig_id = 1, @@ -42712,7 +43991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1964] = { + [2026] = { .class_hid = BNXT_ULP_CLASS_HID_107ce, .class_tid = 2, .hdr_sig_id = 1, @@ -42732,7 +44011,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1965] = { + [2027] = { .class_hid = BNXT_ULP_CLASS_HID_23dce, .class_tid = 2, .hdr_sig_id = 1, @@ -42752,7 +44031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1966] = { + [2028] = { .class_hid = BNXT_ULP_CLASS_HID_353ce, .class_tid = 2, .hdr_sig_id = 1, @@ -42773,7 +44052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1967] = { + [2029] = { .class_hid = BNXT_ULP_CLASS_HID_421a, .class_tid = 2, .hdr_sig_id = 1, @@ -42793,7 +44072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1968] = { + [2030] = { .class_hid = BNXT_ULP_CLASS_HID_11d56, .class_tid = 2, .hdr_sig_id = 1, @@ -42814,7 +44093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1969] = { + [2031] = { .class_hid = BNXT_ULP_CLASS_HID_23356, .class_tid = 2, .hdr_sig_id = 1, @@ -42835,7 +44114,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1970] = { + [2032] = { .class_hid = BNXT_ULP_CLASS_HID_32956, .class_tid = 2, .hdr_sig_id = 1, @@ -42857,7 +44136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1971] = { + [2033] = { .class_hid = BNXT_ULP_CLASS_HID_0cf6, .class_tid = 2, .hdr_sig_id = 1, @@ -42876,7 +44155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1972] = { + [2034] = { .class_hid = BNXT_ULP_CLASS_HID_122f6, .class_tid = 2, .hdr_sig_id = 1, @@ -42896,7 +44175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1973] = { + [2035] = { .class_hid = BNXT_ULP_CLASS_HID_258f6, .class_tid = 2, .hdr_sig_id = 1, @@ -42916,7 +44195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1974] = { + [2036] = { .class_hid = BNXT_ULP_CLASS_HID_313c2, .class_tid = 2, .hdr_sig_id = 1, @@ -42937,7 +44216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1975] = { + [2037] = { .class_hid = BNXT_ULP_CLASS_HID_312a, .class_tid = 2, .hdr_sig_id = 1, @@ -42954,7 +44233,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1976] = { + [2038] = { .class_hid = BNXT_ULP_CLASS_HID_1272a, .class_tid = 2, .hdr_sig_id = 1, @@ -42972,7 +44251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1977] = { + [2039] = { .class_hid = BNXT_ULP_CLASS_HID_25d2a, .class_tid = 2, .hdr_sig_id = 1, @@ -42990,7 +44269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1978] = { + [2040] = { .class_hid = BNXT_ULP_CLASS_HID_31466, .class_tid = 2, .hdr_sig_id = 1, @@ -43009,7 +44288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1979] = { + [2041] = { .class_hid = BNXT_ULP_CLASS_HID_46be, .class_tid = 2, .hdr_sig_id = 1, @@ -43027,7 +44306,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1980] = { + [2042] = { .class_hid = BNXT_ULP_CLASS_HID_1018a, .class_tid = 2, .hdr_sig_id = 1, @@ -43046,7 +44325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1981] = { + [2043] = { .class_hid = BNXT_ULP_CLASS_HID_2378a, .class_tid = 2, .hdr_sig_id = 1, @@ -43065,7 +44344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1982] = { + [2044] = { .class_hid = BNXT_ULP_CLASS_HID_32d8a, .class_tid = 2, .hdr_sig_id = 1, @@ -43085,7 +44364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1983] = { + [2045] = { .class_hid = BNXT_ULP_CLASS_HID_5cc6, .class_tid = 2, .hdr_sig_id = 1, @@ -43104,7 +44383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1984] = { + [2046] = { .class_hid = BNXT_ULP_CLASS_HID_11712, .class_tid = 2, .hdr_sig_id = 1, @@ -43124,7 +44403,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1985] = { + [2047] = { .class_hid = BNXT_ULP_CLASS_HID_20d12, .class_tid = 2, .hdr_sig_id = 1, @@ -43144,7 +44423,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1986] = { + [2048] = { .class_hid = BNXT_ULP_CLASS_HID_32312, .class_tid = 2, .hdr_sig_id = 1, @@ -43165,7 +44444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1987] = { + [2049] = { .class_hid = BNXT_ULP_CLASS_HID_06b2, .class_tid = 2, .hdr_sig_id = 1, @@ -43183,7 +44462,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1988] = { + [2050] = { .class_hid = BNXT_ULP_CLASS_HID_13cb2, .class_tid = 2, .hdr_sig_id = 1, @@ -43202,7 +44481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1989] = { + [2051] = { .class_hid = BNXT_ULP_CLASS_HID_252b2, .class_tid = 2, .hdr_sig_id = 1, @@ -43221,7 +44500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1990] = { + [2052] = { .class_hid = BNXT_ULP_CLASS_HID_348b2, .class_tid = 2, .hdr_sig_id = 1, @@ -43241,7 +44520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1991] = { + [2053] = { .class_hid = BNXT_ULP_CLASS_HID_1c5e, .class_tid = 2, .hdr_sig_id = 1, @@ -43258,7 +44537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1992] = { + [2054] = { .class_hid = BNXT_ULP_CLASS_HID_1325e, .class_tid = 2, .hdr_sig_id = 1, @@ -43276,7 +44555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1993] = { + [2055] = { .class_hid = BNXT_ULP_CLASS_HID_2285e, .class_tid = 2, .hdr_sig_id = 1, @@ -43294,7 +44573,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1994] = { + [2056] = { .class_hid = BNXT_ULP_CLASS_HID_35e5e, .class_tid = 2, .hdr_sig_id = 1, @@ -43313,7 +44592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1995] = { + [2057] = { .class_hid = BNXT_ULP_CLASS_HID_55e2, .class_tid = 2, .hdr_sig_id = 1, @@ -43331,7 +44610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1996] = { + [2058] = { .class_hid = BNXT_ULP_CLASS_HID_14be2, .class_tid = 2, .hdr_sig_id = 1, @@ -43350,7 +44629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1997] = { + [2059] = { .class_hid = BNXT_ULP_CLASS_HID_2023e, .class_tid = 2, .hdr_sig_id = 1, @@ -43369,7 +44648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1998] = { + [2060] = { .class_hid = BNXT_ULP_CLASS_HID_3383e, .class_tid = 2, .hdr_sig_id = 1, @@ -43389,7 +44668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [1999] = { + [2061] = { .class_hid = BNXT_ULP_CLASS_HID_2b0a, .class_tid = 2, .hdr_sig_id = 1, @@ -43408,7 +44687,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2000] = { + [2062] = { .class_hid = BNXT_ULP_CLASS_HID_1410a, .class_tid = 2, .hdr_sig_id = 1, @@ -43428,7 +44707,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2001] = { + [2063] = { .class_hid = BNXT_ULP_CLASS_HID_21846, .class_tid = 2, .hdr_sig_id = 1, @@ -43448,7 +44727,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2002] = { + [2064] = { .class_hid = BNXT_ULP_CLASS_HID_30e46, .class_tid = 2, .hdr_sig_id = 1, @@ -43469,7 +44748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2003] = { + [2065] = { .class_hid = BNXT_ULP_CLASS_HID_15e6, .class_tid = 2, .hdr_sig_id = 1, @@ -43487,7 +44766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2004] = { + [2066] = { .class_hid = BNXT_ULP_CLASS_HID_10be6, .class_tid = 2, .hdr_sig_id = 1, @@ -43506,7 +44785,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2005] = { + [2067] = { .class_hid = BNXT_ULP_CLASS_HID_221e6, .class_tid = 2, .hdr_sig_id = 1, @@ -43525,7 +44804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2006] = { + [2068] = { .class_hid = BNXT_ULP_CLASS_HID_357e6, .class_tid = 2, .hdr_sig_id = 1, @@ -43545,7 +44824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2007] = { + [2069] = { .class_hid = BNXT_ULP_CLASS_HID_161a, .class_tid = 2, .hdr_sig_id = 1, @@ -43561,7 +44840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2008] = { + [2070] = { .class_hid = BNXT_ULP_CLASS_HID_10c1a, .class_tid = 2, .hdr_sig_id = 1, @@ -43578,7 +44857,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2009] = { + [2071] = { .class_hid = BNXT_ULP_CLASS_HID_2221a, .class_tid = 2, .hdr_sig_id = 1, @@ -43595,7 +44874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2010] = { + [2072] = { .class_hid = BNXT_ULP_CLASS_HID_3581a, .class_tid = 2, .hdr_sig_id = 1, @@ -43613,7 +44892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2011] = { + [2073] = { .class_hid = BNXT_ULP_CLASS_HID_2fae, .class_tid = 2, .hdr_sig_id = 1, @@ -43630,7 +44909,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2012] = { + [2074] = { .class_hid = BNXT_ULP_CLASS_HID_145ae, .class_tid = 2, .hdr_sig_id = 1, @@ -43648,7 +44927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2013] = { + [2075] = { .class_hid = BNXT_ULP_CLASS_HID_21cfa, .class_tid = 2, .hdr_sig_id = 1, @@ -43666,7 +44945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2014] = { + [2076] = { .class_hid = BNXT_ULP_CLASS_HID_332fa, .class_tid = 2, .hdr_sig_id = 1, @@ -43685,7 +44964,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2015] = { + [2077] = { .class_hid = BNXT_ULP_CLASS_HID_2536, .class_tid = 2, .hdr_sig_id = 1, @@ -43703,7 +44982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2016] = { + [2078] = { .class_hid = BNXT_ULP_CLASS_HID_15b36, .class_tid = 2, .hdr_sig_id = 1, @@ -43722,7 +45001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2017] = { + [2079] = { .class_hid = BNXT_ULP_CLASS_HID_21202, .class_tid = 2, .hdr_sig_id = 1, @@ -43741,7 +45020,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2018] = { + [2080] = { .class_hid = BNXT_ULP_CLASS_HID_30802, .class_tid = 2, .hdr_sig_id = 1, @@ -43761,7 +45040,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2019] = { + [2081] = { .class_hid = BNXT_ULP_CLASS_HID_4b56, .class_tid = 2, .hdr_sig_id = 1, @@ -43778,7 +45057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2020] = { + [2082] = { .class_hid = BNXT_ULP_CLASS_HID_105a2, .class_tid = 2, .hdr_sig_id = 1, @@ -43796,7 +45075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2021] = { + [2083] = { .class_hid = BNXT_ULP_CLASS_HID_23ba2, .class_tid = 2, .hdr_sig_id = 1, @@ -43814,7 +45093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2022] = { + [2084] = { .class_hid = BNXT_ULP_CLASS_HID_351a2, .class_tid = 2, .hdr_sig_id = 1, @@ -43833,7 +45112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2023] = { + [2085] = { .class_hid = BNXT_ULP_CLASS_HID_10c6, .class_tid = 2, .hdr_sig_id = 1, @@ -43849,7 +45128,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2024] = { + [2086] = { .class_hid = BNXT_ULP_CLASS_HID_106c6, .class_tid = 2, .hdr_sig_id = 1, @@ -43866,7 +45145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2025] = { + [2087] = { .class_hid = BNXT_ULP_CLASS_HID_23cc6, .class_tid = 2, .hdr_sig_id = 1, @@ -43883,7 +45162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2026] = { + [2088] = { .class_hid = BNXT_ULP_CLASS_HID_352c6, .class_tid = 2, .hdr_sig_id = 1, @@ -43901,7 +45180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2027] = { + [2089] = { .class_hid = BNXT_ULP_CLASS_HID_266a, .class_tid = 2, .hdr_sig_id = 1, @@ -43918,7 +45197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2028] = { + [2090] = { .class_hid = BNXT_ULP_CLASS_HID_15c6a, .class_tid = 2, .hdr_sig_id = 1, @@ -43936,7 +45215,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2029] = { + [2091] = { .class_hid = BNXT_ULP_CLASS_HID_216a6, .class_tid = 2, .hdr_sig_id = 1, @@ -43954,7 +45233,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2030] = { + [2092] = { .class_hid = BNXT_ULP_CLASS_HID_30ca6, .class_tid = 2, .hdr_sig_id = 1, @@ -43973,7 +45252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2031] = { + [2093] = { .class_hid = BNXT_ULP_CLASS_HID_3ff2, .class_tid = 2, .hdr_sig_id = 1, @@ -43991,7 +45270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2032] = { + [2094] = { .class_hid = BNXT_ULP_CLASS_HID_155f2, .class_tid = 2, .hdr_sig_id = 1, @@ -44010,7 +45289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2033] = { + [2095] = { .class_hid = BNXT_ULP_CLASS_HID_24bf2, .class_tid = 2, .hdr_sig_id = 1, @@ -44029,7 +45308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2034] = { + [2096] = { .class_hid = BNXT_ULP_CLASS_HID_302ce, .class_tid = 2, .hdr_sig_id = 1, @@ -44049,7 +45328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2035] = { + [2097] = { .class_hid = BNXT_ULP_CLASS_HID_4512, .class_tid = 2, .hdr_sig_id = 1, @@ -44066,7 +45345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2036] = { + [2098] = { .class_hid = BNXT_ULP_CLASS_HID_11c6e, .class_tid = 2, .hdr_sig_id = 1, @@ -44084,7 +45363,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2037] = { + [2099] = { .class_hid = BNXT_ULP_CLASS_HID_2326e, .class_tid = 2, .hdr_sig_id = 1, @@ -44102,7 +45381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2038] = { + [2100] = { .class_hid = BNXT_ULP_CLASS_HID_3286e, .class_tid = 2, .hdr_sig_id = 1, @@ -44121,7 +45400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2039] = { + [2101] = { .class_hid = BNXT_ULP_CLASS_HID_49b6, .class_tid = 2, .hdr_sig_id = 1, @@ -44136,7 +45415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2040] = { + [2102] = { .class_hid = BNXT_ULP_CLASS_HID_10082, .class_tid = 2, .hdr_sig_id = 1, @@ -44152,7 +45431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2041] = { + [2103] = { .class_hid = BNXT_ULP_CLASS_HID_23682, .class_tid = 2, .hdr_sig_id = 1, @@ -44168,7 +45447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2042] = { + [2104] = { .class_hid = BNXT_ULP_CLASS_HID_32c82, .class_tid = 2, .hdr_sig_id = 1, @@ -44185,7 +45464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2043] = { + [2105] = { .class_hid = BNXT_ULP_CLASS_HID_2016, .class_tid = 2, .hdr_sig_id = 1, @@ -44201,7 +45480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2044] = { + [2106] = { .class_hid = BNXT_ULP_CLASS_HID_15616, .class_tid = 2, .hdr_sig_id = 1, @@ -44218,7 +45497,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2045] = { + [2107] = { .class_hid = BNXT_ULP_CLASS_HID_21162, .class_tid = 2, .hdr_sig_id = 1, @@ -44235,7 +45514,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2046] = { + [2108] = { .class_hid = BNXT_ULP_CLASS_HID_30762, .class_tid = 2, .hdr_sig_id = 1, @@ -44253,7 +45532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2047] = { + [2109] = { .class_hid = BNXT_ULP_CLASS_HID_39be, .class_tid = 2, .hdr_sig_id = 1, @@ -44270,7 +45549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2048] = { + [2110] = { .class_hid = BNXT_ULP_CLASS_HID_12fbe, .class_tid = 2, .hdr_sig_id = 1, @@ -44288,7 +45567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2049] = { + [2111] = { .class_hid = BNXT_ULP_CLASS_HID_245be, .class_tid = 2, .hdr_sig_id = 1, @@ -44306,7 +45585,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2050] = { + [2112] = { .class_hid = BNXT_ULP_CLASS_HID_31c8a, .class_tid = 2, .hdr_sig_id = 1, @@ -44325,7 +45604,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2051] = { + [2113] = { .class_hid = BNXT_ULP_CLASS_HID_5fde, .class_tid = 2, .hdr_sig_id = 1, @@ -44341,7 +45620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2052] = { + [2114] = { .class_hid = BNXT_ULP_CLASS_HID_1162a, .class_tid = 2, .hdr_sig_id = 1, @@ -44358,7 +45637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2053] = { + [2115] = { .class_hid = BNXT_ULP_CLASS_HID_20c2a, .class_tid = 2, .hdr_sig_id = 1, @@ -44375,7 +45654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2054] = { + [2116] = { .class_hid = BNXT_ULP_CLASS_HID_3222a, .class_tid = 2, .hdr_sig_id = 1, @@ -44393,7 +45672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2055] = { + [2117] = { .class_hid = BNXT_ULP_CLASS_HID_34de, .class_tid = 2, .hdr_sig_id = 1, @@ -44409,7 +45688,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2056] = { + [2118] = { .class_hid = BNXT_ULP_CLASS_HID_3a12, .class_tid = 2, .hdr_sig_id = 1, @@ -44426,7 +45705,42 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2057] = { + [2119] = { + .class_hid = BNXT_ULP_CLASS_HID_14f2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2120] = { + .class_hid = BNXT_ULP_CLASS_HID_4a62, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 167, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2121] = { .class_hid = BNXT_ULP_CLASS_HID_370e, .class_tid = 2, .hdr_sig_id = 2, @@ -44444,7 +45758,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2058] = { + [2122] = { .class_hid = BNXT_ULP_CLASS_HID_12d0e, .class_tid = 2, .hdr_sig_id = 2, @@ -44463,7 +45777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2059] = { + [2123] = { .class_hid = BNXT_ULP_CLASS_HID_2430e, .class_tid = 2, .hdr_sig_id = 2, @@ -44482,7 +45796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2060] = { + [2124] = { .class_hid = BNXT_ULP_CLASS_HID_31dda, .class_tid = 2, .hdr_sig_id = 2, @@ -44502,7 +45816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2061] = { + [2125] = { .class_hid = BNXT_ULP_CLASS_HID_11ae, .class_tid = 2, .hdr_sig_id = 2, @@ -44521,7 +45835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2062] = { + [2126] = { .class_hid = BNXT_ULP_CLASS_HID_107ae, .class_tid = 2, .hdr_sig_id = 2, @@ -44541,7 +45855,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2063] = { + [2127] = { .class_hid = BNXT_ULP_CLASS_HID_23dae, .class_tid = 2, .hdr_sig_id = 2, @@ -44561,7 +45875,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2064] = { + [2128] = { .class_hid = BNXT_ULP_CLASS_HID_353ae, .class_tid = 2, .hdr_sig_id = 2, @@ -44582,7 +45896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2065] = { + [2129] = { .class_hid = BNXT_ULP_CLASS_HID_427a, .class_tid = 2, .hdr_sig_id = 2, @@ -44602,7 +45916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2066] = { + [2130] = { .class_hid = BNXT_ULP_CLASS_HID_11d36, .class_tid = 2, .hdr_sig_id = 2, @@ -44623,7 +45937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2067] = { + [2131] = { .class_hid = BNXT_ULP_CLASS_HID_23336, .class_tid = 2, .hdr_sig_id = 2, @@ -44644,7 +45958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2068] = { + [2132] = { .class_hid = BNXT_ULP_CLASS_HID_32936, .class_tid = 2, .hdr_sig_id = 2, @@ -44666,7 +45980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2069] = { + [2133] = { .class_hid = BNXT_ULP_CLASS_HID_0c96, .class_tid = 2, .hdr_sig_id = 2, @@ -44685,7 +45999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2070] = { + [2134] = { .class_hid = BNXT_ULP_CLASS_HID_12296, .class_tid = 2, .hdr_sig_id = 2, @@ -44705,7 +46019,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2071] = { + [2135] = { .class_hid = BNXT_ULP_CLASS_HID_25896, .class_tid = 2, .hdr_sig_id = 2, @@ -44725,7 +46039,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2072] = { + [2136] = { .class_hid = BNXT_ULP_CLASS_HID_313a2, .class_tid = 2, .hdr_sig_id = 2, @@ -44746,7 +46060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2073] = { + [2137] = { .class_hid = BNXT_ULP_CLASS_HID_314a, .class_tid = 2, .hdr_sig_id = 2, @@ -44763,7 +46077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2074] = { + [2138] = { .class_hid = BNXT_ULP_CLASS_HID_1274a, .class_tid = 2, .hdr_sig_id = 2, @@ -44781,7 +46095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2075] = { + [2139] = { .class_hid = BNXT_ULP_CLASS_HID_25d4a, .class_tid = 2, .hdr_sig_id = 2, @@ -44799,7 +46113,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2076] = { + [2140] = { .class_hid = BNXT_ULP_CLASS_HID_31406, .class_tid = 2, .hdr_sig_id = 2, @@ -44818,7 +46132,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2077] = { + [2141] = { .class_hid = BNXT_ULP_CLASS_HID_46de, .class_tid = 2, .hdr_sig_id = 2, @@ -44836,7 +46150,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2078] = { + [2142] = { .class_hid = BNXT_ULP_CLASS_HID_101ea, .class_tid = 2, .hdr_sig_id = 2, @@ -44855,7 +46169,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2079] = { + [2143] = { .class_hid = BNXT_ULP_CLASS_HID_237ea, .class_tid = 2, .hdr_sig_id = 2, @@ -44874,7 +46188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2080] = { + [2144] = { .class_hid = BNXT_ULP_CLASS_HID_32dea, .class_tid = 2, .hdr_sig_id = 2, @@ -44894,7 +46208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2081] = { + [2145] = { .class_hid = BNXT_ULP_CLASS_HID_5ca6, .class_tid = 2, .hdr_sig_id = 2, @@ -44913,7 +46227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2082] = { + [2146] = { .class_hid = BNXT_ULP_CLASS_HID_11772, .class_tid = 2, .hdr_sig_id = 2, @@ -44933,7 +46247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2083] = { + [2147] = { .class_hid = BNXT_ULP_CLASS_HID_20d72, .class_tid = 2, .hdr_sig_id = 2, @@ -44953,7 +46267,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2084] = { + [2148] = { .class_hid = BNXT_ULP_CLASS_HID_32372, .class_tid = 2, .hdr_sig_id = 2, @@ -44974,7 +46288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2085] = { + [2149] = { .class_hid = BNXT_ULP_CLASS_HID_06d2, .class_tid = 2, .hdr_sig_id = 2, @@ -44992,7 +46306,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2086] = { + [2150] = { .class_hid = BNXT_ULP_CLASS_HID_13cd2, .class_tid = 2, .hdr_sig_id = 2, @@ -45011,7 +46325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2087] = { + [2151] = { .class_hid = BNXT_ULP_CLASS_HID_252d2, .class_tid = 2, .hdr_sig_id = 2, @@ -45030,7 +46344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2088] = { + [2152] = { .class_hid = BNXT_ULP_CLASS_HID_348d2, .class_tid = 2, .hdr_sig_id = 2, @@ -45050,7 +46364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2089] = { + [2153] = { .class_hid = BNXT_ULP_CLASS_HID_1c3e, .class_tid = 2, .hdr_sig_id = 2, @@ -45067,7 +46381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2090] = { + [2154] = { .class_hid = BNXT_ULP_CLASS_HID_1323e, .class_tid = 2, .hdr_sig_id = 2, @@ -45085,7 +46399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2091] = { + [2155] = { .class_hid = BNXT_ULP_CLASS_HID_2283e, .class_tid = 2, .hdr_sig_id = 2, @@ -45103,7 +46417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2092] = { + [2156] = { .class_hid = BNXT_ULP_CLASS_HID_35e3e, .class_tid = 2, .hdr_sig_id = 2, @@ -45122,7 +46436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2093] = { + [2157] = { .class_hid = BNXT_ULP_CLASS_HID_5582, .class_tid = 2, .hdr_sig_id = 2, @@ -45140,7 +46454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2094] = { + [2158] = { .class_hid = BNXT_ULP_CLASS_HID_14b82, .class_tid = 2, .hdr_sig_id = 2, @@ -45159,7 +46473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2095] = { + [2159] = { .class_hid = BNXT_ULP_CLASS_HID_2025e, .class_tid = 2, .hdr_sig_id = 2, @@ -45178,7 +46492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2096] = { + [2160] = { .class_hid = BNXT_ULP_CLASS_HID_3385e, .class_tid = 2, .hdr_sig_id = 2, @@ -45198,7 +46512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2097] = { + [2161] = { .class_hid = BNXT_ULP_CLASS_HID_2b6a, .class_tid = 2, .hdr_sig_id = 2, @@ -45217,7 +46531,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2098] = { + [2162] = { .class_hid = BNXT_ULP_CLASS_HID_1416a, .class_tid = 2, .hdr_sig_id = 2, @@ -45237,7 +46551,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2099] = { + [2163] = { .class_hid = BNXT_ULP_CLASS_HID_21826, .class_tid = 2, .hdr_sig_id = 2, @@ -45257,7 +46571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2100] = { + [2164] = { .class_hid = BNXT_ULP_CLASS_HID_30e26, .class_tid = 2, .hdr_sig_id = 2, @@ -45278,7 +46592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2101] = { + [2165] = { .class_hid = BNXT_ULP_CLASS_HID_1586, .class_tid = 2, .hdr_sig_id = 2, @@ -45296,7 +46610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2102] = { + [2166] = { .class_hid = BNXT_ULP_CLASS_HID_10b86, .class_tid = 2, .hdr_sig_id = 2, @@ -45315,7 +46629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2103] = { + [2167] = { .class_hid = BNXT_ULP_CLASS_HID_22186, .class_tid = 2, .hdr_sig_id = 2, @@ -45334,7 +46648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2104] = { + [2168] = { .class_hid = BNXT_ULP_CLASS_HID_35786, .class_tid = 2, .hdr_sig_id = 2, @@ -45354,7 +46668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2105] = { + [2169] = { .class_hid = BNXT_ULP_CLASS_HID_167a, .class_tid = 2, .hdr_sig_id = 2, @@ -45370,7 +46684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2106] = { + [2170] = { .class_hid = BNXT_ULP_CLASS_HID_10c7a, .class_tid = 2, .hdr_sig_id = 2, @@ -45387,7 +46701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2107] = { + [2171] = { .class_hid = BNXT_ULP_CLASS_HID_2227a, .class_tid = 2, .hdr_sig_id = 2, @@ -45404,7 +46718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2108] = { + [2172] = { .class_hid = BNXT_ULP_CLASS_HID_3587a, .class_tid = 2, .hdr_sig_id = 2, @@ -45422,7 +46736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2109] = { + [2173] = { .class_hid = BNXT_ULP_CLASS_HID_2fce, .class_tid = 2, .hdr_sig_id = 2, @@ -45439,7 +46753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2110] = { + [2174] = { .class_hid = BNXT_ULP_CLASS_HID_145ce, .class_tid = 2, .hdr_sig_id = 2, @@ -45457,7 +46771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2111] = { + [2175] = { .class_hid = BNXT_ULP_CLASS_HID_21c9a, .class_tid = 2, .hdr_sig_id = 2, @@ -45475,7 +46789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2112] = { + [2176] = { .class_hid = BNXT_ULP_CLASS_HID_3329a, .class_tid = 2, .hdr_sig_id = 2, @@ -45494,7 +46808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2113] = { + [2177] = { .class_hid = BNXT_ULP_CLASS_HID_2556, .class_tid = 2, .hdr_sig_id = 2, @@ -45512,7 +46826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2114] = { + [2178] = { .class_hid = BNXT_ULP_CLASS_HID_15b56, .class_tid = 2, .hdr_sig_id = 2, @@ -45531,7 +46845,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2115] = { + [2179] = { .class_hid = BNXT_ULP_CLASS_HID_21262, .class_tid = 2, .hdr_sig_id = 2, @@ -45550,7 +46864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2116] = { + [2180] = { .class_hid = BNXT_ULP_CLASS_HID_30862, .class_tid = 2, .hdr_sig_id = 2, @@ -45570,7 +46884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2117] = { + [2181] = { .class_hid = BNXT_ULP_CLASS_HID_4b36, .class_tid = 2, .hdr_sig_id = 2, @@ -45587,7 +46901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2118] = { + [2182] = { .class_hid = BNXT_ULP_CLASS_HID_105c2, .class_tid = 2, .hdr_sig_id = 2, @@ -45605,7 +46919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2119] = { + [2183] = { .class_hid = BNXT_ULP_CLASS_HID_23bc2, .class_tid = 2, .hdr_sig_id = 2, @@ -45623,7 +46937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2120] = { + [2184] = { .class_hid = BNXT_ULP_CLASS_HID_351c2, .class_tid = 2, .hdr_sig_id = 2, @@ -45642,7 +46956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2121] = { + [2185] = { .class_hid = BNXT_ULP_CLASS_HID_10a6, .class_tid = 2, .hdr_sig_id = 2, @@ -45658,7 +46972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2122] = { + [2186] = { .class_hid = BNXT_ULP_CLASS_HID_106a6, .class_tid = 2, .hdr_sig_id = 2, @@ -45675,7 +46989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2123] = { + [2187] = { .class_hid = BNXT_ULP_CLASS_HID_23ca6, .class_tid = 2, .hdr_sig_id = 2, @@ -45692,7 +47006,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2124] = { + [2188] = { .class_hid = BNXT_ULP_CLASS_HID_352a6, .class_tid = 2, .hdr_sig_id = 2, @@ -45710,7 +47024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2125] = { + [2189] = { .class_hid = BNXT_ULP_CLASS_HID_260a, .class_tid = 2, .hdr_sig_id = 2, @@ -45727,7 +47041,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2126] = { + [2190] = { .class_hid = BNXT_ULP_CLASS_HID_15c0a, .class_tid = 2, .hdr_sig_id = 2, @@ -45745,7 +47059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2127] = { + [2191] = { .class_hid = BNXT_ULP_CLASS_HID_216c6, .class_tid = 2, .hdr_sig_id = 2, @@ -45763,7 +47077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2128] = { + [2192] = { .class_hid = BNXT_ULP_CLASS_HID_30cc6, .class_tid = 2, .hdr_sig_id = 2, @@ -45782,7 +47096,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2129] = { + [2193] = { .class_hid = BNXT_ULP_CLASS_HID_3f92, .class_tid = 2, .hdr_sig_id = 2, @@ -45800,7 +47114,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2130] = { + [2194] = { .class_hid = BNXT_ULP_CLASS_HID_15592, .class_tid = 2, .hdr_sig_id = 2, @@ -45819,7 +47133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2131] = { + [2195] = { .class_hid = BNXT_ULP_CLASS_HID_24b92, .class_tid = 2, .hdr_sig_id = 2, @@ -45838,7 +47152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2132] = { + [2196] = { .class_hid = BNXT_ULP_CLASS_HID_302ae, .class_tid = 2, .hdr_sig_id = 2, @@ -45858,7 +47172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2133] = { + [2197] = { .class_hid = BNXT_ULP_CLASS_HID_4572, .class_tid = 2, .hdr_sig_id = 2, @@ -45875,7 +47189,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2134] = { + [2198] = { .class_hid = BNXT_ULP_CLASS_HID_11c0e, .class_tid = 2, .hdr_sig_id = 2, @@ -45893,7 +47207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2135] = { + [2199] = { .class_hid = BNXT_ULP_CLASS_HID_2320e, .class_tid = 2, .hdr_sig_id = 2, @@ -45911,7 +47225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2136] = { + [2200] = { .class_hid = BNXT_ULP_CLASS_HID_3280e, .class_tid = 2, .hdr_sig_id = 2, @@ -45930,7 +47244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2137] = { + [2201] = { .class_hid = BNXT_ULP_CLASS_HID_49d6, .class_tid = 2, .hdr_sig_id = 2, @@ -45945,7 +47259,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2138] = { + [2202] = { .class_hid = BNXT_ULP_CLASS_HID_100e2, .class_tid = 2, .hdr_sig_id = 2, @@ -45961,7 +47275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2139] = { + [2203] = { .class_hid = BNXT_ULP_CLASS_HID_236e2, .class_tid = 2, .hdr_sig_id = 2, @@ -45977,7 +47291,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2140] = { + [2204] = { .class_hid = BNXT_ULP_CLASS_HID_32ce2, .class_tid = 2, .hdr_sig_id = 2, @@ -45994,7 +47308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2141] = { + [2205] = { .class_hid = BNXT_ULP_CLASS_HID_2076, .class_tid = 2, .hdr_sig_id = 2, @@ -46010,7 +47324,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2142] = { + [2206] = { .class_hid = BNXT_ULP_CLASS_HID_15676, .class_tid = 2, .hdr_sig_id = 2, @@ -46027,7 +47341,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2143] = { + [2207] = { .class_hid = BNXT_ULP_CLASS_HID_21102, .class_tid = 2, .hdr_sig_id = 2, @@ -46044,7 +47358,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2144] = { + [2208] = { .class_hid = BNXT_ULP_CLASS_HID_30702, .class_tid = 2, .hdr_sig_id = 2, @@ -46062,7 +47376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2145] = { + [2209] = { .class_hid = BNXT_ULP_CLASS_HID_39de, .class_tid = 2, .hdr_sig_id = 2, @@ -46079,7 +47393,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2146] = { + [2210] = { .class_hid = BNXT_ULP_CLASS_HID_12fde, .class_tid = 2, .hdr_sig_id = 2, @@ -46097,7 +47411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2147] = { + [2211] = { .class_hid = BNXT_ULP_CLASS_HID_245de, .class_tid = 2, .hdr_sig_id = 2, @@ -46115,7 +47429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2148] = { + [2212] = { .class_hid = BNXT_ULP_CLASS_HID_31cea, .class_tid = 2, .hdr_sig_id = 2, @@ -46134,7 +47448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2149] = { + [2213] = { .class_hid = BNXT_ULP_CLASS_HID_5fbe, .class_tid = 2, .hdr_sig_id = 2, @@ -46150,7 +47464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2150] = { + [2214] = { .class_hid = BNXT_ULP_CLASS_HID_1164a, .class_tid = 2, .hdr_sig_id = 2, @@ -46167,7 +47481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2151] = { + [2215] = { .class_hid = BNXT_ULP_CLASS_HID_20c4a, .class_tid = 2, .hdr_sig_id = 2, @@ -46184,7 +47498,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2152] = { + [2216] = { .class_hid = BNXT_ULP_CLASS_HID_3224a, .class_tid = 2, .hdr_sig_id = 2, @@ -46202,7 +47516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2153] = { + [2217] = { .class_hid = BNXT_ULP_CLASS_HID_34be, .class_tid = 2, .hdr_sig_id = 2, @@ -46218,7 +47532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2154] = { + [2218] = { .class_hid = BNXT_ULP_CLASS_HID_3a72, .class_tid = 2, .hdr_sig_id = 2, @@ -46235,7 +47549,42 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2155] = { + [2219] = { + .class_hid = BNXT_ULP_CLASS_HID_1492, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2220] = { + .class_hid = BNXT_ULP_CLASS_HID_4a02, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 185, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2221] = { .class_hid = BNXT_ULP_CLASS_HID_09ea, .class_tid = 2, .hdr_sig_id = 3, @@ -46252,7 +47601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2156] = { + [2222] = { .class_hid = BNXT_ULP_CLASS_HID_2912, .class_tid = 2, .hdr_sig_id = 3, @@ -46270,7 +47619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2157] = { + [2223] = { .class_hid = BNXT_ULP_CLASS_HID_03b2, .class_tid = 2, .hdr_sig_id = 3, @@ -46289,7 +47638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2158] = { + [2224] = { .class_hid = BNXT_ULP_CLASS_HID_5f7e, .class_tid = 2, .hdr_sig_id = 3, @@ -46307,7 +47656,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2159] = { + [2225] = { .class_hid = BNXT_ULP_CLASS_HID_03a6, .class_tid = 2, .hdr_sig_id = 3, @@ -46323,7 +47672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2160] = { + [2226] = { .class_hid = BNXT_ULP_CLASS_HID_23ce, .class_tid = 2, .hdr_sig_id = 3, @@ -46340,7 +47689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2161] = { + [2227] = { .class_hid = BNXT_ULP_CLASS_HID_1a6e, .class_tid = 2, .hdr_sig_id = 3, @@ -46358,7 +47707,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2162] = { + [2228] = { .class_hid = BNXT_ULP_CLASS_HID_593a, .class_tid = 2, .hdr_sig_id = 3, @@ -46375,7 +47724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2163] = { + [2229] = { .class_hid = BNXT_ULP_CLASS_HID_4dce, .class_tid = 2, .hdr_sig_id = 3, @@ -46391,7 +47740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2164] = { + [2230] = { .class_hid = BNXT_ULP_CLASS_HID_0e02, .class_tid = 2, .hdr_sig_id = 3, @@ -46408,7 +47757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2165] = { + [2231] = { .class_hid = BNXT_ULP_CLASS_HID_4796, .class_tid = 2, .hdr_sig_id = 3, @@ -46426,7 +47775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2166] = { + [2232] = { .class_hid = BNXT_ULP_CLASS_HID_246e, .class_tid = 2, .hdr_sig_id = 3, @@ -46443,7 +47792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2167] = { + [2233] = { .class_hid = BNXT_ULP_CLASS_HID_478a, .class_tid = 2, .hdr_sig_id = 3, @@ -46458,7 +47807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2168] = { + [2234] = { .class_hid = BNXT_ULP_CLASS_HID_08fe, .class_tid = 2, .hdr_sig_id = 3, @@ -46474,7 +47823,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2169] = { + [2235] = { .class_hid = BNXT_ULP_CLASS_HID_5e52, .class_tid = 2, .hdr_sig_id = 3, @@ -46491,7 +47840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2170] = { + [2236] = { .class_hid = BNXT_ULP_CLASS_HID_3e2a, .class_tid = 2, .hdr_sig_id = 3, @@ -46507,7 +47856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2171] = { + [2237] = { .class_hid = BNXT_ULP_CLASS_HID_5e46, .class_tid = 2, .hdr_sig_id = 3, @@ -46522,7 +47871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2172] = { + [2238] = { .class_hid = BNXT_ULP_CLASS_HID_02ba, .class_tid = 2, .hdr_sig_id = 3, @@ -46538,7 +47887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2173] = { + [2239] = { .class_hid = BNXT_ULP_CLASS_HID_580e, .class_tid = 2, .hdr_sig_id = 3, @@ -46555,7 +47904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2174] = { + [2240] = { .class_hid = BNXT_ULP_CLASS_HID_38e6, .class_tid = 2, .hdr_sig_id = 3, @@ -46571,7 +47920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2175] = { + [2241] = { .class_hid = BNXT_ULP_CLASS_HID_5802, .class_tid = 2, .hdr_sig_id = 3, @@ -46585,7 +47934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2176] = { + [2242] = { .class_hid = BNXT_ULP_CLASS_HID_1d76, .class_tid = 2, .hdr_sig_id = 3, @@ -46600,7 +47949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2177] = { + [2243] = { .class_hid = BNXT_ULP_CLASS_HID_52ca, .class_tid = 2, .hdr_sig_id = 3, @@ -46616,7 +47965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2178] = { + [2244] = { .class_hid = BNXT_ULP_CLASS_HID_32a2, .class_tid = 2, .hdr_sig_id = 3, @@ -46631,7 +47980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2179] = { + [2245] = { .class_hid = BNXT_ULP_CLASS_HID_34f6, .class_tid = 2, .hdr_sig_id = 3, @@ -46646,7 +47995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2180] = { + [2246] = { .class_hid = BNXT_ULP_CLASS_HID_3a3a, .class_tid = 2, .hdr_sig_id = 3, @@ -46662,7 +48011,40 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2181] = { + [2247] = { + .class_hid = BNXT_ULP_CLASS_HID_5a22, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2248] = { + .class_hid = BNXT_ULP_CLASS_HID_541e, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 191, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2249] = { .class_hid = BNXT_ULP_CLASS_HID_09ca, .class_tid = 2, .hdr_sig_id = 4, @@ -46680,7 +48062,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2182] = { + [2250] = { .class_hid = BNXT_ULP_CLASS_HID_0216, .class_tid = 2, .hdr_sig_id = 4, @@ -46699,7 +48081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2183] = { + [2251] = { .class_hid = BNXT_ULP_CLASS_HID_1f62, .class_tid = 2, .hdr_sig_id = 4, @@ -46718,7 +48100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2184] = { + [2252] = { .class_hid = BNXT_ULP_CLASS_HID_1bae, .class_tid = 2, .hdr_sig_id = 4, @@ -46738,7 +48120,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2185] = { + [2253] = { .class_hid = BNXT_ULP_CLASS_HID_2932, .class_tid = 2, .hdr_sig_id = 4, @@ -46757,7 +48139,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2186] = { + [2254] = { .class_hid = BNXT_ULP_CLASS_HID_227e, .class_tid = 2, .hdr_sig_id = 4, @@ -46777,7 +48159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2187] = { + [2255] = { .class_hid = BNXT_ULP_CLASS_HID_3f4a, .class_tid = 2, .hdr_sig_id = 4, @@ -46797,7 +48179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2188] = { + [2256] = { .class_hid = BNXT_ULP_CLASS_HID_3b96, .class_tid = 2, .hdr_sig_id = 4, @@ -46818,7 +48200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2189] = { + [2257] = { .class_hid = BNXT_ULP_CLASS_HID_0392, .class_tid = 2, .hdr_sig_id = 4, @@ -46838,7 +48220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2190] = { + [2258] = { .class_hid = BNXT_ULP_CLASS_HID_1cde, .class_tid = 2, .hdr_sig_id = 4, @@ -46859,7 +48241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2191] = { + [2259] = { .class_hid = BNXT_ULP_CLASS_HID_192a, .class_tid = 2, .hdr_sig_id = 4, @@ -46880,7 +48262,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2192] = { + [2260] = { .class_hid = BNXT_ULP_CLASS_HID_1276, .class_tid = 2, .hdr_sig_id = 4, @@ -46902,7 +48284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2193] = { + [2261] = { .class_hid = BNXT_ULP_CLASS_HID_5f5e, .class_tid = 2, .hdr_sig_id = 4, @@ -46921,7 +48303,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2194] = { + [2262] = { .class_hid = BNXT_ULP_CLASS_HID_5baa, .class_tid = 2, .hdr_sig_id = 4, @@ -46941,7 +48323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2195] = { + [2263] = { .class_hid = BNXT_ULP_CLASS_HID_54f6, .class_tid = 2, .hdr_sig_id = 4, @@ -46961,7 +48343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2196] = { + [2264] = { .class_hid = BNXT_ULP_CLASS_HID_51c2, .class_tid = 2, .hdr_sig_id = 4, @@ -46982,7 +48364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2197] = { + [2265] = { .class_hid = BNXT_ULP_CLASS_HID_0386, .class_tid = 2, .hdr_sig_id = 4, @@ -46999,7 +48381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2198] = { + [2266] = { .class_hid = BNXT_ULP_CLASS_HID_1cd2, .class_tid = 2, .hdr_sig_id = 4, @@ -47017,7 +48399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2199] = { + [2267] = { .class_hid = BNXT_ULP_CLASS_HID_191e, .class_tid = 2, .hdr_sig_id = 4, @@ -47035,7 +48417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2200] = { + [2268] = { .class_hid = BNXT_ULP_CLASS_HID_126a, .class_tid = 2, .hdr_sig_id = 4, @@ -47054,7 +48436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2201] = { + [2269] = { .class_hid = BNXT_ULP_CLASS_HID_23ee, .class_tid = 2, .hdr_sig_id = 4, @@ -47072,7 +48454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2202] = { + [2270] = { .class_hid = BNXT_ULP_CLASS_HID_3c3a, .class_tid = 2, .hdr_sig_id = 4, @@ -47091,7 +48473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2203] = { + [2271] = { .class_hid = BNXT_ULP_CLASS_HID_3906, .class_tid = 2, .hdr_sig_id = 4, @@ -47110,7 +48492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2204] = { + [2272] = { .class_hid = BNXT_ULP_CLASS_HID_3252, .class_tid = 2, .hdr_sig_id = 4, @@ -47130,7 +48512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2205] = { + [2273] = { .class_hid = BNXT_ULP_CLASS_HID_1a4e, .class_tid = 2, .hdr_sig_id = 4, @@ -47149,7 +48531,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2206] = { + [2274] = { .class_hid = BNXT_ULP_CLASS_HID_169a, .class_tid = 2, .hdr_sig_id = 4, @@ -47169,7 +48551,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2207] = { + [2275] = { .class_hid = BNXT_ULP_CLASS_HID_13e6, .class_tid = 2, .hdr_sig_id = 4, @@ -47189,7 +48571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2208] = { + [2276] = { .class_hid = BNXT_ULP_CLASS_HID_4be6, .class_tid = 2, .hdr_sig_id = 4, @@ -47210,7 +48592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2209] = { + [2277] = { .class_hid = BNXT_ULP_CLASS_HID_591a, .class_tid = 2, .hdr_sig_id = 4, @@ -47228,7 +48610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2210] = { + [2278] = { .class_hid = BNXT_ULP_CLASS_HID_5266, .class_tid = 2, .hdr_sig_id = 4, @@ -47247,7 +48629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2211] = { + [2279] = { .class_hid = BNXT_ULP_CLASS_HID_2eb2, .class_tid = 2, .hdr_sig_id = 4, @@ -47266,7 +48648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2212] = { + [2280] = { .class_hid = BNXT_ULP_CLASS_HID_2bfe, .class_tid = 2, .hdr_sig_id = 4, @@ -47286,7 +48668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2213] = { + [2281] = { .class_hid = BNXT_ULP_CLASS_HID_4dee, .class_tid = 2, .hdr_sig_id = 4, @@ -47303,7 +48685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2214] = { + [2282] = { .class_hid = BNXT_ULP_CLASS_HID_463a, .class_tid = 2, .hdr_sig_id = 4, @@ -47321,7 +48703,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2215] = { + [2283] = { .class_hid = BNXT_ULP_CLASS_HID_4306, .class_tid = 2, .hdr_sig_id = 4, @@ -47339,7 +48721,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2216] = { + [2284] = { .class_hid = BNXT_ULP_CLASS_HID_5c52, .class_tid = 2, .hdr_sig_id = 4, @@ -47358,7 +48740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2217] = { + [2285] = { .class_hid = BNXT_ULP_CLASS_HID_0e22, .class_tid = 2, .hdr_sig_id = 4, @@ -47376,7 +48758,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2218] = { + [2286] = { .class_hid = BNXT_ULP_CLASS_HID_0b6e, .class_tid = 2, .hdr_sig_id = 4, @@ -47395,7 +48777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2219] = { + [2287] = { .class_hid = BNXT_ULP_CLASS_HID_07ba, .class_tid = 2, .hdr_sig_id = 4, @@ -47414,7 +48796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2220] = { + [2288] = { .class_hid = BNXT_ULP_CLASS_HID_0086, .class_tid = 2, .hdr_sig_id = 4, @@ -47434,7 +48816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2221] = { + [2289] = { .class_hid = BNXT_ULP_CLASS_HID_47b6, .class_tid = 2, .hdr_sig_id = 4, @@ -47453,7 +48835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2222] = { + [2290] = { .class_hid = BNXT_ULP_CLASS_HID_4082, .class_tid = 2, .hdr_sig_id = 4, @@ -47473,7 +48855,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2223] = { + [2291] = { .class_hid = BNXT_ULP_CLASS_HID_5dce, .class_tid = 2, .hdr_sig_id = 4, @@ -47493,7 +48875,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2224] = { + [2292] = { .class_hid = BNXT_ULP_CLASS_HID_561a, .class_tid = 2, .hdr_sig_id = 4, @@ -47514,7 +48896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2225] = { + [2293] = { .class_hid = BNXT_ULP_CLASS_HID_244e, .class_tid = 2, .hdr_sig_id = 4, @@ -47532,7 +48914,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2226] = { + [2294] = { .class_hid = BNXT_ULP_CLASS_HID_209a, .class_tid = 2, .hdr_sig_id = 4, @@ -47551,7 +48933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2227] = { + [2295] = { .class_hid = BNXT_ULP_CLASS_HID_3de6, .class_tid = 2, .hdr_sig_id = 4, @@ -47570,7 +48952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2228] = { + [2296] = { .class_hid = BNXT_ULP_CLASS_HID_3632, .class_tid = 2, .hdr_sig_id = 4, @@ -47590,7 +48972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2229] = { + [2297] = { .class_hid = BNXT_ULP_CLASS_HID_47aa, .class_tid = 2, .hdr_sig_id = 4, @@ -47606,7 +48988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2230] = { + [2298] = { .class_hid = BNXT_ULP_CLASS_HID_40f6, .class_tid = 2, .hdr_sig_id = 4, @@ -47623,7 +49005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2231] = { + [2299] = { .class_hid = BNXT_ULP_CLASS_HID_5dc2, .class_tid = 2, .hdr_sig_id = 4, @@ -47640,7 +49022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2232] = { + [2300] = { .class_hid = BNXT_ULP_CLASS_HID_560e, .class_tid = 2, .hdr_sig_id = 4, @@ -47658,7 +49040,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2233] = { + [2301] = { .class_hid = BNXT_ULP_CLASS_HID_08de, .class_tid = 2, .hdr_sig_id = 4, @@ -47675,7 +49057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2234] = { + [2302] = { .class_hid = BNXT_ULP_CLASS_HID_052a, .class_tid = 2, .hdr_sig_id = 4, @@ -47693,7 +49075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2235] = { + [2303] = { .class_hid = BNXT_ULP_CLASS_HID_1e76, .class_tid = 2, .hdr_sig_id = 4, @@ -47711,7 +49093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2236] = { + [2304] = { .class_hid = BNXT_ULP_CLASS_HID_1b42, .class_tid = 2, .hdr_sig_id = 4, @@ -47730,7 +49112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2237] = { + [2305] = { .class_hid = BNXT_ULP_CLASS_HID_5e72, .class_tid = 2, .hdr_sig_id = 4, @@ -47748,7 +49130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2238] = { + [2306] = { .class_hid = BNXT_ULP_CLASS_HID_5abe, .class_tid = 2, .hdr_sig_id = 4, @@ -47767,7 +49149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2239] = { + [2307] = { .class_hid = BNXT_ULP_CLASS_HID_578a, .class_tid = 2, .hdr_sig_id = 4, @@ -47786,7 +49168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2240] = { + [2308] = { .class_hid = BNXT_ULP_CLASS_HID_50d6, .class_tid = 2, .hdr_sig_id = 4, @@ -47806,7 +49188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2241] = { + [2309] = { .class_hid = BNXT_ULP_CLASS_HID_3e0a, .class_tid = 2, .hdr_sig_id = 4, @@ -47823,7 +49205,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2242] = { + [2310] = { .class_hid = BNXT_ULP_CLASS_HID_3b56, .class_tid = 2, .hdr_sig_id = 4, @@ -47841,7 +49223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2243] = { + [2311] = { .class_hid = BNXT_ULP_CLASS_HID_37a2, .class_tid = 2, .hdr_sig_id = 4, @@ -47859,7 +49241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2244] = { + [2312] = { .class_hid = BNXT_ULP_CLASS_HID_30ee, .class_tid = 2, .hdr_sig_id = 4, @@ -47878,7 +49260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2245] = { + [2313] = { .class_hid = BNXT_ULP_CLASS_HID_5e66, .class_tid = 2, .hdr_sig_id = 4, @@ -47894,7 +49276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2246] = { + [2314] = { .class_hid = BNXT_ULP_CLASS_HID_5ab2, .class_tid = 2, .hdr_sig_id = 4, @@ -47911,7 +49293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2247] = { + [2315] = { .class_hid = BNXT_ULP_CLASS_HID_57fe, .class_tid = 2, .hdr_sig_id = 4, @@ -47928,7 +49310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2248] = { + [2316] = { .class_hid = BNXT_ULP_CLASS_HID_50ca, .class_tid = 2, .hdr_sig_id = 4, @@ -47946,7 +49328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2249] = { + [2317] = { .class_hid = BNXT_ULP_CLASS_HID_029a, .class_tid = 2, .hdr_sig_id = 4, @@ -47963,7 +49345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2250] = { + [2318] = { .class_hid = BNXT_ULP_CLASS_HID_1fe6, .class_tid = 2, .hdr_sig_id = 4, @@ -47981,7 +49363,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2251] = { + [2319] = { .class_hid = BNXT_ULP_CLASS_HID_1832, .class_tid = 2, .hdr_sig_id = 4, @@ -47999,7 +49381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2252] = { + [2320] = { .class_hid = BNXT_ULP_CLASS_HID_157e, .class_tid = 2, .hdr_sig_id = 4, @@ -48018,7 +49400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2253] = { + [2321] = { .class_hid = BNXT_ULP_CLASS_HID_582e, .class_tid = 2, .hdr_sig_id = 4, @@ -48036,7 +49418,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2254] = { + [2322] = { .class_hid = BNXT_ULP_CLASS_HID_557a, .class_tid = 2, .hdr_sig_id = 4, @@ -48055,7 +49437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2255] = { + [2323] = { .class_hid = BNXT_ULP_CLASS_HID_2e46, .class_tid = 2, .hdr_sig_id = 4, @@ -48074,7 +49456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2256] = { + [2324] = { .class_hid = BNXT_ULP_CLASS_HID_2a92, .class_tid = 2, .hdr_sig_id = 4, @@ -48094,7 +49476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2257] = { + [2325] = { .class_hid = BNXT_ULP_CLASS_HID_38c6, .class_tid = 2, .hdr_sig_id = 4, @@ -48111,7 +49493,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2258] = { + [2326] = { .class_hid = BNXT_ULP_CLASS_HID_3512, .class_tid = 2, .hdr_sig_id = 4, @@ -48129,7 +49511,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2259] = { + [2327] = { .class_hid = BNXT_ULP_CLASS_HID_0e5e, .class_tid = 2, .hdr_sig_id = 4, @@ -48147,7 +49529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2260] = { + [2328] = { .class_hid = BNXT_ULP_CLASS_HID_0aaa, .class_tid = 2, .hdr_sig_id = 4, @@ -48166,7 +49548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2261] = { + [2329] = { .class_hid = BNXT_ULP_CLASS_HID_5822, .class_tid = 2, .hdr_sig_id = 4, @@ -48181,7 +49563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2262] = { + [2330] = { .class_hid = BNXT_ULP_CLASS_HID_556e, .class_tid = 2, .hdr_sig_id = 4, @@ -48197,7 +49579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2263] = { + [2331] = { .class_hid = BNXT_ULP_CLASS_HID_51ba, .class_tid = 2, .hdr_sig_id = 4, @@ -48213,7 +49595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2264] = { + [2332] = { .class_hid = BNXT_ULP_CLASS_HID_2a86, .class_tid = 2, .hdr_sig_id = 4, @@ -48230,7 +49612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2265] = { + [2333] = { .class_hid = BNXT_ULP_CLASS_HID_1d56, .class_tid = 2, .hdr_sig_id = 4, @@ -48246,7 +49628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2266] = { + [2334] = { .class_hid = BNXT_ULP_CLASS_HID_19a2, .class_tid = 2, .hdr_sig_id = 4, @@ -48263,7 +49645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2267] = { + [2335] = { .class_hid = BNXT_ULP_CLASS_HID_12ee, .class_tid = 2, .hdr_sig_id = 4, @@ -48280,7 +49662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2268] = { + [2336] = { .class_hid = BNXT_ULP_CLASS_HID_4aee, .class_tid = 2, .hdr_sig_id = 4, @@ -48298,7 +49680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2269] = { + [2337] = { .class_hid = BNXT_ULP_CLASS_HID_52ea, .class_tid = 2, .hdr_sig_id = 4, @@ -48315,7 +49697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2270] = { + [2338] = { .class_hid = BNXT_ULP_CLASS_HID_2f36, .class_tid = 2, .hdr_sig_id = 4, @@ -48333,7 +49715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2271] = { + [2339] = { .class_hid = BNXT_ULP_CLASS_HID_2802, .class_tid = 2, .hdr_sig_id = 4, @@ -48351,7 +49733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2272] = { + [2340] = { .class_hid = BNXT_ULP_CLASS_HID_254e, .class_tid = 2, .hdr_sig_id = 4, @@ -48370,7 +49752,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2273] = { + [2341] = { .class_hid = BNXT_ULP_CLASS_HID_3282, .class_tid = 2, .hdr_sig_id = 4, @@ -48386,7 +49768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2274] = { + [2342] = { .class_hid = BNXT_ULP_CLASS_HID_0fce, .class_tid = 2, .hdr_sig_id = 4, @@ -48403,7 +49785,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2275] = { + [2343] = { .class_hid = BNXT_ULP_CLASS_HID_081a, .class_tid = 2, .hdr_sig_id = 4, @@ -48420,7 +49802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2276] = { + [2344] = { .class_hid = BNXT_ULP_CLASS_HID_0566, .class_tid = 2, .hdr_sig_id = 4, @@ -48438,7 +49820,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2277] = { + [2345] = { .class_hid = BNXT_ULP_CLASS_HID_34d6, .class_tid = 2, .hdr_sig_id = 4, @@ -48454,7 +49836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2278] = { + [2346] = { .class_hid = BNXT_ULP_CLASS_HID_3a1a, .class_tid = 2, .hdr_sig_id = 4, @@ -48471,7 +49853,42 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2279] = { + [2347] = { + .class_hid = BNXT_ULP_CLASS_HID_5a02, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2348] = { + .class_hid = BNXT_ULP_CLASS_HID_543e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 209, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2349] = { .class_hid = BNXT_ULP_CLASS_HID_09aa, .class_tid = 2, .hdr_sig_id = 5, @@ -48489,7 +49906,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2280] = { + [2350] = { .class_hid = BNXT_ULP_CLASS_HID_0276, .class_tid = 2, .hdr_sig_id = 5, @@ -48508,7 +49925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2281] = { + [2351] = { .class_hid = BNXT_ULP_CLASS_HID_1f02, .class_tid = 2, .hdr_sig_id = 5, @@ -48527,7 +49944,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2282] = { + [2352] = { .class_hid = BNXT_ULP_CLASS_HID_1bce, .class_tid = 2, .hdr_sig_id = 5, @@ -48547,7 +49964,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2283] = { + [2353] = { .class_hid = BNXT_ULP_CLASS_HID_2952, .class_tid = 2, .hdr_sig_id = 5, @@ -48566,7 +49983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2284] = { + [2354] = { .class_hid = BNXT_ULP_CLASS_HID_221e, .class_tid = 2, .hdr_sig_id = 5, @@ -48586,7 +50003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2285] = { + [2355] = { .class_hid = BNXT_ULP_CLASS_HID_3f2a, .class_tid = 2, .hdr_sig_id = 5, @@ -48606,7 +50023,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2286] = { + [2356] = { .class_hid = BNXT_ULP_CLASS_HID_3bf6, .class_tid = 2, .hdr_sig_id = 5, @@ -48627,7 +50044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2287] = { + [2357] = { .class_hid = BNXT_ULP_CLASS_HID_03f2, .class_tid = 2, .hdr_sig_id = 5, @@ -48647,7 +50064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2288] = { + [2358] = { .class_hid = BNXT_ULP_CLASS_HID_1cbe, .class_tid = 2, .hdr_sig_id = 5, @@ -48668,7 +50085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2289] = { + [2359] = { .class_hid = BNXT_ULP_CLASS_HID_194a, .class_tid = 2, .hdr_sig_id = 5, @@ -48689,7 +50106,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2290] = { + [2360] = { .class_hid = BNXT_ULP_CLASS_HID_1216, .class_tid = 2, .hdr_sig_id = 5, @@ -48711,7 +50128,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2291] = { + [2361] = { .class_hid = BNXT_ULP_CLASS_HID_5f3e, .class_tid = 2, .hdr_sig_id = 5, @@ -48730,7 +50147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2292] = { + [2362] = { .class_hid = BNXT_ULP_CLASS_HID_5bca, .class_tid = 2, .hdr_sig_id = 5, @@ -48750,7 +50167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2293] = { + [2363] = { .class_hid = BNXT_ULP_CLASS_HID_5496, .class_tid = 2, .hdr_sig_id = 5, @@ -48770,7 +50187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2294] = { + [2364] = { .class_hid = BNXT_ULP_CLASS_HID_51a2, .class_tid = 2, .hdr_sig_id = 5, @@ -48791,7 +50208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2295] = { + [2365] = { .class_hid = BNXT_ULP_CLASS_HID_03e6, .class_tid = 2, .hdr_sig_id = 5, @@ -48808,7 +50225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2296] = { + [2366] = { .class_hid = BNXT_ULP_CLASS_HID_1cb2, .class_tid = 2, .hdr_sig_id = 5, @@ -48826,7 +50243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2297] = { + [2367] = { .class_hid = BNXT_ULP_CLASS_HID_197e, .class_tid = 2, .hdr_sig_id = 5, @@ -48844,7 +50261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2298] = { + [2368] = { .class_hid = BNXT_ULP_CLASS_HID_120a, .class_tid = 2, .hdr_sig_id = 5, @@ -48863,7 +50280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2299] = { + [2369] = { .class_hid = BNXT_ULP_CLASS_HID_238e, .class_tid = 2, .hdr_sig_id = 5, @@ -48881,7 +50298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2300] = { + [2370] = { .class_hid = BNXT_ULP_CLASS_HID_3c5a, .class_tid = 2, .hdr_sig_id = 5, @@ -48900,7 +50317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2301] = { + [2371] = { .class_hid = BNXT_ULP_CLASS_HID_3966, .class_tid = 2, .hdr_sig_id = 5, @@ -48919,7 +50336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2302] = { + [2372] = { .class_hid = BNXT_ULP_CLASS_HID_3232, .class_tid = 2, .hdr_sig_id = 5, @@ -48939,7 +50356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2303] = { + [2373] = { .class_hid = BNXT_ULP_CLASS_HID_1a2e, .class_tid = 2, .hdr_sig_id = 5, @@ -48958,7 +50375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2304] = { + [2374] = { .class_hid = BNXT_ULP_CLASS_HID_16fa, .class_tid = 2, .hdr_sig_id = 5, @@ -48978,7 +50395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2305] = { + [2375] = { .class_hid = BNXT_ULP_CLASS_HID_1386, .class_tid = 2, .hdr_sig_id = 5, @@ -48998,7 +50415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2306] = { + [2376] = { .class_hid = BNXT_ULP_CLASS_HID_4b86, .class_tid = 2, .hdr_sig_id = 5, @@ -49019,7 +50436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2307] = { + [2377] = { .class_hid = BNXT_ULP_CLASS_HID_597a, .class_tid = 2, .hdr_sig_id = 5, @@ -49037,7 +50454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2308] = { + [2378] = { .class_hid = BNXT_ULP_CLASS_HID_5206, .class_tid = 2, .hdr_sig_id = 5, @@ -49056,7 +50473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2309] = { + [2379] = { .class_hid = BNXT_ULP_CLASS_HID_2ed2, .class_tid = 2, .hdr_sig_id = 5, @@ -49075,7 +50492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2310] = { + [2380] = { .class_hid = BNXT_ULP_CLASS_HID_2b9e, .class_tid = 2, .hdr_sig_id = 5, @@ -49095,7 +50512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2311] = { + [2381] = { .class_hid = BNXT_ULP_CLASS_HID_4d8e, .class_tid = 2, .hdr_sig_id = 5, @@ -49112,7 +50529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2312] = { + [2382] = { .class_hid = BNXT_ULP_CLASS_HID_465a, .class_tid = 2, .hdr_sig_id = 5, @@ -49130,7 +50547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2313] = { + [2383] = { .class_hid = BNXT_ULP_CLASS_HID_4366, .class_tid = 2, .hdr_sig_id = 5, @@ -49148,7 +50565,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2314] = { + [2384] = { .class_hid = BNXT_ULP_CLASS_HID_5c32, .class_tid = 2, .hdr_sig_id = 5, @@ -49167,7 +50584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2315] = { + [2385] = { .class_hid = BNXT_ULP_CLASS_HID_0e42, .class_tid = 2, .hdr_sig_id = 5, @@ -49185,7 +50602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2316] = { + [2386] = { .class_hid = BNXT_ULP_CLASS_HID_0b0e, .class_tid = 2, .hdr_sig_id = 5, @@ -49204,7 +50621,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2317] = { + [2387] = { .class_hid = BNXT_ULP_CLASS_HID_07da, .class_tid = 2, .hdr_sig_id = 5, @@ -49223,7 +50640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2318] = { + [2388] = { .class_hid = BNXT_ULP_CLASS_HID_00e6, .class_tid = 2, .hdr_sig_id = 5, @@ -49243,7 +50660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2319] = { + [2389] = { .class_hid = BNXT_ULP_CLASS_HID_47d6, .class_tid = 2, .hdr_sig_id = 5, @@ -49262,7 +50679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2320] = { + [2390] = { .class_hid = BNXT_ULP_CLASS_HID_40e2, .class_tid = 2, .hdr_sig_id = 5, @@ -49282,7 +50699,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2321] = { + [2391] = { .class_hid = BNXT_ULP_CLASS_HID_5dae, .class_tid = 2, .hdr_sig_id = 5, @@ -49302,7 +50719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2322] = { + [2392] = { .class_hid = BNXT_ULP_CLASS_HID_567a, .class_tid = 2, .hdr_sig_id = 5, @@ -49323,7 +50740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2323] = { + [2393] = { .class_hid = BNXT_ULP_CLASS_HID_242e, .class_tid = 2, .hdr_sig_id = 5, @@ -49341,7 +50758,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2324] = { + [2394] = { .class_hid = BNXT_ULP_CLASS_HID_20fa, .class_tid = 2, .hdr_sig_id = 5, @@ -49360,7 +50777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2325] = { + [2395] = { .class_hid = BNXT_ULP_CLASS_HID_3d86, .class_tid = 2, .hdr_sig_id = 5, @@ -49379,7 +50796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2326] = { + [2396] = { .class_hid = BNXT_ULP_CLASS_HID_3652, .class_tid = 2, .hdr_sig_id = 5, @@ -49399,7 +50816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2327] = { + [2397] = { .class_hid = BNXT_ULP_CLASS_HID_47ca, .class_tid = 2, .hdr_sig_id = 5, @@ -49415,7 +50832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2328] = { + [2398] = { .class_hid = BNXT_ULP_CLASS_HID_4096, .class_tid = 2, .hdr_sig_id = 5, @@ -49432,7 +50849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2329] = { + [2399] = { .class_hid = BNXT_ULP_CLASS_HID_5da2, .class_tid = 2, .hdr_sig_id = 5, @@ -49449,7 +50866,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2330] = { + [2400] = { .class_hid = BNXT_ULP_CLASS_HID_566e, .class_tid = 2, .hdr_sig_id = 5, @@ -49467,7 +50884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2331] = { + [2401] = { .class_hid = BNXT_ULP_CLASS_HID_08be, .class_tid = 2, .hdr_sig_id = 5, @@ -49484,7 +50901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2332] = { + [2402] = { .class_hid = BNXT_ULP_CLASS_HID_054a, .class_tid = 2, .hdr_sig_id = 5, @@ -49502,7 +50919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2333] = { + [2403] = { .class_hid = BNXT_ULP_CLASS_HID_1e16, .class_tid = 2, .hdr_sig_id = 5, @@ -49520,7 +50937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2334] = { + [2404] = { .class_hid = BNXT_ULP_CLASS_HID_1b22, .class_tid = 2, .hdr_sig_id = 5, @@ -49539,7 +50956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2335] = { + [2405] = { .class_hid = BNXT_ULP_CLASS_HID_5e12, .class_tid = 2, .hdr_sig_id = 5, @@ -49557,7 +50974,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2336] = { + [2406] = { .class_hid = BNXT_ULP_CLASS_HID_5ade, .class_tid = 2, .hdr_sig_id = 5, @@ -49576,7 +50993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2337] = { + [2407] = { .class_hid = BNXT_ULP_CLASS_HID_57ea, .class_tid = 2, .hdr_sig_id = 5, @@ -49595,7 +51012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2338] = { + [2408] = { .class_hid = BNXT_ULP_CLASS_HID_50b6, .class_tid = 2, .hdr_sig_id = 5, @@ -49615,7 +51032,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2339] = { + [2409] = { .class_hid = BNXT_ULP_CLASS_HID_3e6a, .class_tid = 2, .hdr_sig_id = 5, @@ -49632,7 +51049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2340] = { + [2410] = { .class_hid = BNXT_ULP_CLASS_HID_3b36, .class_tid = 2, .hdr_sig_id = 5, @@ -49650,7 +51067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2341] = { + [2411] = { .class_hid = BNXT_ULP_CLASS_HID_37c2, .class_tid = 2, .hdr_sig_id = 5, @@ -49668,7 +51085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2342] = { + [2412] = { .class_hid = BNXT_ULP_CLASS_HID_308e, .class_tid = 2, .hdr_sig_id = 5, @@ -49687,7 +51104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2343] = { + [2413] = { .class_hid = BNXT_ULP_CLASS_HID_5e06, .class_tid = 2, .hdr_sig_id = 5, @@ -49703,7 +51120,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2344] = { + [2414] = { .class_hid = BNXT_ULP_CLASS_HID_5ad2, .class_tid = 2, .hdr_sig_id = 5, @@ -49720,7 +51137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2345] = { + [2415] = { .class_hid = BNXT_ULP_CLASS_HID_579e, .class_tid = 2, .hdr_sig_id = 5, @@ -49737,7 +51154,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2346] = { + [2416] = { .class_hid = BNXT_ULP_CLASS_HID_50aa, .class_tid = 2, .hdr_sig_id = 5, @@ -49755,7 +51172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2347] = { + [2417] = { .class_hid = BNXT_ULP_CLASS_HID_02fa, .class_tid = 2, .hdr_sig_id = 5, @@ -49772,7 +51189,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2348] = { + [2418] = { .class_hid = BNXT_ULP_CLASS_HID_1f86, .class_tid = 2, .hdr_sig_id = 5, @@ -49790,7 +51207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2349] = { + [2419] = { .class_hid = BNXT_ULP_CLASS_HID_1852, .class_tid = 2, .hdr_sig_id = 5, @@ -49808,7 +51225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2350] = { + [2420] = { .class_hid = BNXT_ULP_CLASS_HID_151e, .class_tid = 2, .hdr_sig_id = 5, @@ -49827,7 +51244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2351] = { + [2421] = { .class_hid = BNXT_ULP_CLASS_HID_584e, .class_tid = 2, .hdr_sig_id = 5, @@ -49845,7 +51262,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2352] = { + [2422] = { .class_hid = BNXT_ULP_CLASS_HID_551a, .class_tid = 2, .hdr_sig_id = 5, @@ -49864,7 +51281,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2353] = { + [2423] = { .class_hid = BNXT_ULP_CLASS_HID_2e26, .class_tid = 2, .hdr_sig_id = 5, @@ -49883,7 +51300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2354] = { + [2424] = { .class_hid = BNXT_ULP_CLASS_HID_2af2, .class_tid = 2, .hdr_sig_id = 5, @@ -49903,7 +51320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2355] = { + [2425] = { .class_hid = BNXT_ULP_CLASS_HID_38a6, .class_tid = 2, .hdr_sig_id = 5, @@ -49920,7 +51337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2356] = { + [2426] = { .class_hid = BNXT_ULP_CLASS_HID_3572, .class_tid = 2, .hdr_sig_id = 5, @@ -49938,7 +51355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2357] = { + [2427] = { .class_hid = BNXT_ULP_CLASS_HID_0e3e, .class_tid = 2, .hdr_sig_id = 5, @@ -49956,7 +51373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2358] = { + [2428] = { .class_hid = BNXT_ULP_CLASS_HID_0aca, .class_tid = 2, .hdr_sig_id = 5, @@ -49975,7 +51392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2359] = { + [2429] = { .class_hid = BNXT_ULP_CLASS_HID_5842, .class_tid = 2, .hdr_sig_id = 5, @@ -49990,7 +51407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2360] = { + [2430] = { .class_hid = BNXT_ULP_CLASS_HID_550e, .class_tid = 2, .hdr_sig_id = 5, @@ -50006,7 +51423,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2361] = { + [2431] = { .class_hid = BNXT_ULP_CLASS_HID_51da, .class_tid = 2, .hdr_sig_id = 5, @@ -50022,7 +51439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2362] = { + [2432] = { .class_hid = BNXT_ULP_CLASS_HID_2ae6, .class_tid = 2, .hdr_sig_id = 5, @@ -50039,7 +51456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2363] = { + [2433] = { .class_hid = BNXT_ULP_CLASS_HID_1d36, .class_tid = 2, .hdr_sig_id = 5, @@ -50055,7 +51472,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2364] = { + [2434] = { .class_hid = BNXT_ULP_CLASS_HID_19c2, .class_tid = 2, .hdr_sig_id = 5, @@ -50072,7 +51489,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2365] = { + [2435] = { .class_hid = BNXT_ULP_CLASS_HID_128e, .class_tid = 2, .hdr_sig_id = 5, @@ -50089,7 +51506,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2366] = { + [2436] = { .class_hid = BNXT_ULP_CLASS_HID_4a8e, .class_tid = 2, .hdr_sig_id = 5, @@ -50107,7 +51524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2367] = { + [2437] = { .class_hid = BNXT_ULP_CLASS_HID_528a, .class_tid = 2, .hdr_sig_id = 5, @@ -50124,7 +51541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2368] = { + [2438] = { .class_hid = BNXT_ULP_CLASS_HID_2f56, .class_tid = 2, .hdr_sig_id = 5, @@ -50142,7 +51559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2369] = { + [2439] = { .class_hid = BNXT_ULP_CLASS_HID_2862, .class_tid = 2, .hdr_sig_id = 5, @@ -50160,7 +51577,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2370] = { + [2440] = { .class_hid = BNXT_ULP_CLASS_HID_252e, .class_tid = 2, .hdr_sig_id = 5, @@ -50179,7 +51596,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2371] = { + [2441] = { .class_hid = BNXT_ULP_CLASS_HID_32e2, .class_tid = 2, .hdr_sig_id = 5, @@ -50195,7 +51612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2372] = { + [2442] = { .class_hid = BNXT_ULP_CLASS_HID_0fae, .class_tid = 2, .hdr_sig_id = 5, @@ -50212,7 +51629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2373] = { + [2443] = { .class_hid = BNXT_ULP_CLASS_HID_087a, .class_tid = 2, .hdr_sig_id = 5, @@ -50229,7 +51646,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2374] = { + [2444] = { .class_hid = BNXT_ULP_CLASS_HID_0506, .class_tid = 2, .hdr_sig_id = 5, @@ -50247,7 +51664,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2375] = { + [2445] = { .class_hid = BNXT_ULP_CLASS_HID_34b6, .class_tid = 2, .hdr_sig_id = 5, @@ -50263,7 +51680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2376] = { + [2446] = { .class_hid = BNXT_ULP_CLASS_HID_3a7a, .class_tid = 2, .hdr_sig_id = 5, @@ -50280,7 +51697,42 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2377] = { + [2447] = { + .class_hid = BNXT_ULP_CLASS_HID_5a62, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2448] = { + .class_hid = BNXT_ULP_CLASS_HID_545e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 227, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2449] = { .class_hid = BNXT_ULP_CLASS_HID_a73c, .class_tid = 2, .hdr_sig_id = 6, @@ -50298,7 +51750,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2378] = { + [2450] = { .class_hid = BNXT_ULP_CLASS_HID_a040, .class_tid = 2, .hdr_sig_id = 6, @@ -50317,7 +51769,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2379] = { + [2451] = { .class_hid = BNXT_ULP_CLASS_HID_1d640, .class_tid = 2, .hdr_sig_id = 6, @@ -50337,7 +51789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2380] = { + [2452] = { .class_hid = BNXT_ULP_CLASS_HID_1dd3c, .class_tid = 2, .hdr_sig_id = 6, @@ -50356,7 +51808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2381] = { + [2453] = { .class_hid = BNXT_ULP_CLASS_HID_cba0, .class_tid = 2, .hdr_sig_id = 6, @@ -50375,7 +51827,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2382] = { + [2454] = { .class_hid = BNXT_ULP_CLASS_HID_c4f4, .class_tid = 2, .hdr_sig_id = 6, @@ -50395,7 +51847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2383] = { + [2455] = { .class_hid = BNXT_ULP_CLASS_HID_19f38, .class_tid = 2, .hdr_sig_id = 6, @@ -50416,7 +51868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2384] = { + [2456] = { .class_hid = BNXT_ULP_CLASS_HID_182f4, .class_tid = 2, .hdr_sig_id = 6, @@ -50436,7 +51888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2385] = { + [2457] = { .class_hid = BNXT_ULP_CLASS_HID_b098, .class_tid = 2, .hdr_sig_id = 6, @@ -50455,7 +51907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2386] = { + [2458] = { .class_hid = BNXT_ULP_CLASS_HID_8dac, .class_tid = 2, .hdr_sig_id = 6, @@ -50475,7 +51927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2387] = { + [2459] = { .class_hid = BNXT_ULP_CLASS_HID_1a3ac, .class_tid = 2, .hdr_sig_id = 6, @@ -50496,7 +51948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2388] = { + [2460] = { .class_hid = BNXT_ULP_CLASS_HID_1a698, .class_tid = 2, .hdr_sig_id = 6, @@ -50516,7 +51968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2389] = { + [2461] = { .class_hid = BNXT_ULP_CLASS_HID_d50c, .class_tid = 2, .hdr_sig_id = 6, @@ -50536,7 +51988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2390] = { + [2462] = { .class_hid = BNXT_ULP_CLASS_HID_ae50, .class_tid = 2, .hdr_sig_id = 6, @@ -50557,7 +52009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2391] = { + [2463] = { .class_hid = BNXT_ULP_CLASS_HID_1c450, .class_tid = 2, .hdr_sig_id = 6, @@ -50579,7 +52031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2392] = { + [2464] = { .class_hid = BNXT_ULP_CLASS_HID_1cb0c, .class_tid = 2, .hdr_sig_id = 6, @@ -50600,7 +52052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2393] = { + [2465] = { .class_hid = BNXT_ULP_CLASS_HID_a1f0, .class_tid = 2, .hdr_sig_id = 6, @@ -50617,7 +52069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2394] = { + [2466] = { .class_hid = BNXT_ULP_CLASS_HID_ba04, .class_tid = 2, .hdr_sig_id = 6, @@ -50635,7 +52087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2395] = { + [2467] = { .class_hid = BNXT_ULP_CLASS_HID_1d004, .class_tid = 2, .hdr_sig_id = 6, @@ -50654,7 +52106,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2396] = { + [2468] = { .class_hid = BNXT_ULP_CLASS_HID_1d7f0, .class_tid = 2, .hdr_sig_id = 6, @@ -50672,7 +52124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2397] = { + [2469] = { .class_hid = BNXT_ULP_CLASS_HID_c264, .class_tid = 2, .hdr_sig_id = 6, @@ -50690,7 +52142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2398] = { + [2470] = { .class_hid = BNXT_ULP_CLASS_HID_dea8, .class_tid = 2, .hdr_sig_id = 6, @@ -50709,7 +52161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2399] = { + [2471] = { .class_hid = BNXT_ULP_CLASS_HID_199fc, .class_tid = 2, .hdr_sig_id = 6, @@ -50729,7 +52181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2400] = { + [2472] = { .class_hid = BNXT_ULP_CLASS_HID_19ca8, .class_tid = 2, .hdr_sig_id = 6, @@ -50748,7 +52200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2401] = { + [2473] = { .class_hid = BNXT_ULP_CLASS_HID_8b5c, .class_tid = 2, .hdr_sig_id = 6, @@ -50766,7 +52218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2402] = { + [2474] = { .class_hid = BNXT_ULP_CLASS_HID_8460, .class_tid = 2, .hdr_sig_id = 6, @@ -50785,7 +52237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2403] = { + [2475] = { .class_hid = BNXT_ULP_CLASS_HID_1ba60, .class_tid = 2, .hdr_sig_id = 6, @@ -50805,7 +52257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2404] = { + [2476] = { .class_hid = BNXT_ULP_CLASS_HID_1a15c, .class_tid = 2, .hdr_sig_id = 6, @@ -50824,7 +52276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2405] = { + [2477] = { .class_hid = BNXT_ULP_CLASS_HID_afc0, .class_tid = 2, .hdr_sig_id = 6, @@ -50843,7 +52295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2406] = { + [2478] = { .class_hid = BNXT_ULP_CLASS_HID_a814, .class_tid = 2, .hdr_sig_id = 6, @@ -50863,7 +52315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2407] = { + [2479] = { .class_hid = BNXT_ULP_CLASS_HID_1de14, .class_tid = 2, .hdr_sig_id = 6, @@ -50884,7 +52336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2408] = { + [2480] = { .class_hid = BNXT_ULP_CLASS_HID_1c5c0, .class_tid = 2, .hdr_sig_id = 6, @@ -50904,7 +52356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2409] = { + [2481] = { .class_hid = BNXT_ULP_CLASS_HID_8c2c, .class_tid = 2, .hdr_sig_id = 6, @@ -50921,7 +52373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2410] = { + [2482] = { .class_hid = BNXT_ULP_CLASS_HID_8970, .class_tid = 2, .hdr_sig_id = 6, @@ -50939,7 +52391,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2411] = { + [2483] = { .class_hid = BNXT_ULP_CLASS_HID_1bf70, .class_tid = 2, .hdr_sig_id = 6, @@ -50958,7 +52410,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2412] = { + [2484] = { .class_hid = BNXT_ULP_CLASS_HID_1a22c, .class_tid = 2, .hdr_sig_id = 6, @@ -50976,7 +52428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2413] = { + [2485] = { .class_hid = BNXT_ULP_CLASS_HID_d0d0, .class_tid = 2, .hdr_sig_id = 6, @@ -50994,7 +52446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2414] = { + [2486] = { .class_hid = BNXT_ULP_CLASS_HID_ade4, .class_tid = 2, .hdr_sig_id = 6, @@ -51013,7 +52465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2415] = { + [2487] = { .class_hid = BNXT_ULP_CLASS_HID_1c3e4, .class_tid = 2, .hdr_sig_id = 6, @@ -51033,7 +52485,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2416] = { + [2488] = { .class_hid = BNXT_ULP_CLASS_HID_1c6d0, .class_tid = 2, .hdr_sig_id = 6, @@ -51052,7 +52504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2417] = { + [2489] = { .class_hid = BNXT_ULP_CLASS_HID_9988, .class_tid = 2, .hdr_sig_id = 6, @@ -51070,7 +52522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2418] = { + [2490] = { .class_hid = BNXT_ULP_CLASS_HID_92dc, .class_tid = 2, .hdr_sig_id = 6, @@ -51089,7 +52541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2419] = { + [2491] = { .class_hid = BNXT_ULP_CLASS_HID_188dc, .class_tid = 2, .hdr_sig_id = 6, @@ -51109,7 +52561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2420] = { + [2492] = { .class_hid = BNXT_ULP_CLASS_HID_18f88, .class_tid = 2, .hdr_sig_id = 6, @@ -51128,7 +52580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2421] = { + [2493] = { .class_hid = BNXT_ULP_CLASS_HID_ba3c, .class_tid = 2, .hdr_sig_id = 6, @@ -51147,7 +52599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2422] = { + [2494] = { .class_hid = BNXT_ULP_CLASS_HID_b740, .class_tid = 2, .hdr_sig_id = 6, @@ -51167,7 +52619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2423] = { + [2495] = { .class_hid = BNXT_ULP_CLASS_HID_1ad40, .class_tid = 2, .hdr_sig_id = 6, @@ -51188,7 +52640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2424] = { + [2496] = { .class_hid = BNXT_ULP_CLASS_HID_1d03c, .class_tid = 2, .hdr_sig_id = 6, @@ -51208,7 +52660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2425] = { + [2497] = { .class_hid = BNXT_ULP_CLASS_HID_86e0, .class_tid = 2, .hdr_sig_id = 6, @@ -51224,7 +52676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2426] = { + [2498] = { .class_hid = BNXT_ULP_CLASS_HID_8334, .class_tid = 2, .hdr_sig_id = 6, @@ -51241,7 +52693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2427] = { + [2499] = { .class_hid = BNXT_ULP_CLASS_HID_1b934, .class_tid = 2, .hdr_sig_id = 6, @@ -51259,7 +52711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2428] = { + [2500] = { .class_hid = BNXT_ULP_CLASS_HID_1bce0, .class_tid = 2, .hdr_sig_id = 6, @@ -51276,7 +52728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2429] = { + [2501] = { .class_hid = BNXT_ULP_CLASS_HID_aa94, .class_tid = 2, .hdr_sig_id = 6, @@ -51293,7 +52745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2430] = { + [2502] = { .class_hid = BNXT_ULP_CLASS_HID_a7d8, .class_tid = 2, .hdr_sig_id = 6, @@ -51311,7 +52763,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2431] = { + [2503] = { .class_hid = BNXT_ULP_CLASS_HID_1ddd8, .class_tid = 2, .hdr_sig_id = 6, @@ -51330,7 +52782,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2432] = { + [2504] = { .class_hid = BNXT_ULP_CLASS_HID_1c094, .class_tid = 2, .hdr_sig_id = 6, @@ -51348,7 +52800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2433] = { + [2505] = { .class_hid = BNXT_ULP_CLASS_HID_904c, .class_tid = 2, .hdr_sig_id = 6, @@ -51365,7 +52817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2434] = { + [2506] = { .class_hid = BNXT_ULP_CLASS_HID_c84c, .class_tid = 2, .hdr_sig_id = 6, @@ -51383,7 +52835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2435] = { + [2507] = { .class_hid = BNXT_ULP_CLASS_HID_18290, .class_tid = 2, .hdr_sig_id = 6, @@ -51402,7 +52854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2436] = { + [2508] = { .class_hid = BNXT_ULP_CLASS_HID_1864c, .class_tid = 2, .hdr_sig_id = 6, @@ -51420,7 +52872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2437] = { + [2509] = { .class_hid = BNXT_ULP_CLASS_HID_b4f0, .class_tid = 2, .hdr_sig_id = 6, @@ -51438,7 +52890,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2438] = { + [2510] = { .class_hid = BNXT_ULP_CLASS_HID_b104, .class_tid = 2, .hdr_sig_id = 6, @@ -51457,7 +52909,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2439] = { + [2511] = { .class_hid = BNXT_ULP_CLASS_HID_1a704, .class_tid = 2, .hdr_sig_id = 6, @@ -51477,7 +52929,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2440] = { + [2512] = { .class_hid = BNXT_ULP_CLASS_HID_1aaf0, .class_tid = 2, .hdr_sig_id = 6, @@ -51496,7 +52948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2441] = { + [2513] = { .class_hid = BNXT_ULP_CLASS_HID_80a4, .class_tid = 2, .hdr_sig_id = 6, @@ -51512,7 +52964,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2442] = { + [2514] = { .class_hid = BNXT_ULP_CLASS_HID_9de8, .class_tid = 2, .hdr_sig_id = 6, @@ -51529,7 +52981,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2443] = { + [2515] = { .class_hid = BNXT_ULP_CLASS_HID_1b3e8, .class_tid = 2, .hdr_sig_id = 6, @@ -51547,7 +52999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2444] = { + [2516] = { .class_hid = BNXT_ULP_CLASS_HID_1b6a4, .class_tid = 2, .hdr_sig_id = 6, @@ -51564,7 +53016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2445] = { + [2517] = { .class_hid = BNXT_ULP_CLASS_HID_a548, .class_tid = 2, .hdr_sig_id = 6, @@ -51581,7 +53033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2446] = { + [2518] = { .class_hid = BNXT_ULP_CLASS_HID_a19c, .class_tid = 2, .hdr_sig_id = 6, @@ -51599,7 +53051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2447] = { + [2519] = { .class_hid = BNXT_ULP_CLASS_HID_1d79c, .class_tid = 2, .hdr_sig_id = 6, @@ -51618,7 +53070,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2448] = { + [2520] = { .class_hid = BNXT_ULP_CLASS_HID_1db48, .class_tid = 2, .hdr_sig_id = 6, @@ -51636,7 +53088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2449] = { + [2521] = { .class_hid = BNXT_ULP_CLASS_HID_9a98, .class_tid = 2, .hdr_sig_id = 6, @@ -51651,7 +53103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2450] = { + [2522] = { .class_hid = BNXT_ULP_CLASS_HID_97ac, .class_tid = 2, .hdr_sig_id = 6, @@ -51667,7 +53119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2451] = { + [2523] = { .class_hid = BNXT_ULP_CLASS_HID_18dac, .class_tid = 2, .hdr_sig_id = 6, @@ -51684,7 +53136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2452] = { + [2524] = { .class_hid = BNXT_ULP_CLASS_HID_1b098, .class_tid = 2, .hdr_sig_id = 6, @@ -51700,7 +53152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2453] = { + [2525] = { .class_hid = BNXT_ULP_CLASS_HID_bf0c, .class_tid = 2, .hdr_sig_id = 6, @@ -51716,7 +53168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2454] = { + [2526] = { .class_hid = BNXT_ULP_CLASS_HID_b850, .class_tid = 2, .hdr_sig_id = 6, @@ -51733,7 +53185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2455] = { + [2527] = { .class_hid = BNXT_ULP_CLASS_HID_1ae50, .class_tid = 2, .hdr_sig_id = 6, @@ -51751,7 +53203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2456] = { + [2528] = { .class_hid = BNXT_ULP_CLASS_HID_1d50c, .class_tid = 2, .hdr_sig_id = 6, @@ -51768,7 +53220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2457] = { + [2529] = { .class_hid = BNXT_ULP_CLASS_HID_34f0, .class_tid = 2, .hdr_sig_id = 6, @@ -51784,7 +53236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2458] = { + [2530] = { .class_hid = BNXT_ULP_CLASS_HID_3a3c, .class_tid = 2, .hdr_sig_id = 6, @@ -51801,7 +53253,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2459] = { + [2531] = { + .class_hid = BNXT_ULP_CLASS_HID_3740, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2532] = { .class_hid = BNXT_ULP_CLASS_HID_5ea0, .class_tid = 2, .hdr_sig_id = 6, @@ -51819,7 +53289,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2460] = { + [2533] = { + .class_hid = BNXT_ULP_CLASS_HID_5bf4, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 231, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2534] = { .class_hid = BNXT_ULP_CLASS_HID_0798, .class_tid = 2, .hdr_sig_id = 6, @@ -51837,7 +53326,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2461] = { + [2535] = { + .class_hid = BNXT_ULP_CLASS_HID_00ac, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2536] = { .class_hid = BNXT_ULP_CLASS_HID_280c, .class_tid = 2, .hdr_sig_id = 6, @@ -51856,7 +53364,44 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2462] = { + [2537] = { + .class_hid = BNXT_ULP_CLASS_HID_2550, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2538] = { + .class_hid = BNXT_ULP_CLASS_HID_3104, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2539] = { .class_hid = BNXT_ULP_CLASS_HID_5964, .class_tid = 2, .hdr_sig_id = 6, @@ -51873,7 +53418,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2463] = { + [2540] = { + .class_hid = BNXT_ULP_CLASS_HID_55a8, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2541] = { .class_hid = BNXT_ULP_CLASS_HID_1e5c, .class_tid = 2, .hdr_sig_id = 6, @@ -51890,7 +53453,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2464] = { + [2542] = { + .class_hid = BNXT_ULP_CLASS_HID_1b60, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2543] = { .class_hid = BNXT_ULP_CLASS_HID_22c0, .class_tid = 2, .hdr_sig_id = 6, @@ -51908,7 +53489,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2465] = { + [2544] = { + .class_hid = BNXT_ULP_CLASS_HID_3f14, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 232, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2545] = { .class_hid = BNXT_ULP_CLASS_HID_a71c, .class_tid = 2, .hdr_sig_id = 7, @@ -51927,7 +53527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2466] = { + [2546] = { .class_hid = BNXT_ULP_CLASS_HID_a8dc, .class_tid = 2, .hdr_sig_id = 7, @@ -51947,7 +53547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2467] = { + [2547] = { .class_hid = BNXT_ULP_CLASS_HID_ed9c, .class_tid = 2, .hdr_sig_id = 7, @@ -51967,7 +53567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2468] = { + [2548] = { .class_hid = BNXT_ULP_CLASS_HID_ef5c, .class_tid = 2, .hdr_sig_id = 7, @@ -51988,7 +53588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2469] = { + [2549] = { .class_hid = BNXT_ULP_CLASS_HID_a060, .class_tid = 2, .hdr_sig_id = 7, @@ -52008,7 +53608,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2470] = { + [2550] = { .class_hid = BNXT_ULP_CLASS_HID_a520, .class_tid = 2, .hdr_sig_id = 7, @@ -52029,7 +53629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2471] = { + [2551] = { .class_hid = BNXT_ULP_CLASS_HID_e6e0, .class_tid = 2, .hdr_sig_id = 7, @@ -52050,7 +53650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2472] = { + [2552] = { .class_hid = BNXT_ULP_CLASS_HID_eba0, .class_tid = 2, .hdr_sig_id = 7, @@ -52072,7 +53672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2473] = { + [2553] = { .class_hid = BNXT_ULP_CLASS_HID_1d660, .class_tid = 2, .hdr_sig_id = 7, @@ -52093,7 +53693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2474] = { + [2554] = { .class_hid = BNXT_ULP_CLASS_HID_1fb20, .class_tid = 2, .hdr_sig_id = 7, @@ -52115,7 +53715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2475] = { + [2555] = { .class_hid = BNXT_ULP_CLASS_HID_1dce0, .class_tid = 2, .hdr_sig_id = 7, @@ -52137,7 +53737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2476] = { + [2556] = { .class_hid = BNXT_ULP_CLASS_HID_1e1a0, .class_tid = 2, .hdr_sig_id = 7, @@ -52160,7 +53760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2477] = { + [2557] = { .class_hid = BNXT_ULP_CLASS_HID_1dd1c, .class_tid = 2, .hdr_sig_id = 7, @@ -52180,7 +53780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2478] = { + [2558] = { .class_hid = BNXT_ULP_CLASS_HID_1fedc, .class_tid = 2, .hdr_sig_id = 7, @@ -52201,7 +53801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2479] = { + [2559] = { .class_hid = BNXT_ULP_CLASS_HID_1c39c, .class_tid = 2, .hdr_sig_id = 7, @@ -52222,7 +53822,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2480] = { + [2560] = { .class_hid = BNXT_ULP_CLASS_HID_1e55c, .class_tid = 2, .hdr_sig_id = 7, @@ -52244,7 +53844,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2481] = { + [2561] = { .class_hid = BNXT_ULP_CLASS_HID_cb80, .class_tid = 2, .hdr_sig_id = 7, @@ -52264,7 +53864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2482] = { + [2562] = { .class_hid = BNXT_ULP_CLASS_HID_b194, .class_tid = 2, .hdr_sig_id = 7, @@ -52285,7 +53885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2483] = { + [2563] = { .class_hid = BNXT_ULP_CLASS_HID_d354, .class_tid = 2, .hdr_sig_id = 7, @@ -52306,7 +53906,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2484] = { + [2564] = { .class_hid = BNXT_ULP_CLASS_HID_f414, .class_tid = 2, .hdr_sig_id = 7, @@ -52328,7 +53928,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2485] = { + [2565] = { .class_hid = BNXT_ULP_CLASS_HID_c4d4, .class_tid = 2, .hdr_sig_id = 7, @@ -52349,7 +53949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2486] = { + [2566] = { .class_hid = BNXT_ULP_CLASS_HID_e994, .class_tid = 2, .hdr_sig_id = 7, @@ -52371,7 +53971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2487] = { + [2567] = { .class_hid = BNXT_ULP_CLASS_HID_cb54, .class_tid = 2, .hdr_sig_id = 7, @@ -52393,7 +53993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2488] = { + [2568] = { .class_hid = BNXT_ULP_CLASS_HID_f158, .class_tid = 2, .hdr_sig_id = 7, @@ -52416,7 +54016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2489] = { + [2569] = { .class_hid = BNXT_ULP_CLASS_HID_19f18, .class_tid = 2, .hdr_sig_id = 7, @@ -52438,7 +54038,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2490] = { + [2570] = { .class_hid = BNXT_ULP_CLASS_HID_1a0d8, .class_tid = 2, .hdr_sig_id = 7, @@ -52461,7 +54061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2491] = { + [2571] = { .class_hid = BNXT_ULP_CLASS_HID_1c598, .class_tid = 2, .hdr_sig_id = 7, @@ -52484,7 +54084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2492] = { + [2572] = { .class_hid = BNXT_ULP_CLASS_HID_1e758, .class_tid = 2, .hdr_sig_id = 7, @@ -52508,7 +54108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2493] = { + [2573] = { .class_hid = BNXT_ULP_CLASS_HID_182d4, .class_tid = 2, .hdr_sig_id = 7, @@ -52529,7 +54129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2494] = { + [2574] = { .class_hid = BNXT_ULP_CLASS_HID_1a794, .class_tid = 2, .hdr_sig_id = 7, @@ -52551,7 +54151,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2495] = { + [2575] = { .class_hid = BNXT_ULP_CLASS_HID_1c954, .class_tid = 2, .hdr_sig_id = 7, @@ -52573,7 +54173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2496] = { + [2576] = { .class_hid = BNXT_ULP_CLASS_HID_1ea14, .class_tid = 2, .hdr_sig_id = 7, @@ -52596,7 +54196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2497] = { + [2577] = { .class_hid = BNXT_ULP_CLASS_HID_b0b8, .class_tid = 2, .hdr_sig_id = 7, @@ -52616,7 +54216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2498] = { + [2578] = { .class_hid = BNXT_ULP_CLASS_HID_b278, .class_tid = 2, .hdr_sig_id = 7, @@ -52637,7 +54237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2499] = { + [2579] = { .class_hid = BNXT_ULP_CLASS_HID_f738, .class_tid = 2, .hdr_sig_id = 7, @@ -52658,7 +54258,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2500] = { + [2580] = { .class_hid = BNXT_ULP_CLASS_HID_f8f8, .class_tid = 2, .hdr_sig_id = 7, @@ -52680,7 +54280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2501] = { + [2581] = { .class_hid = BNXT_ULP_CLASS_HID_8d8c, .class_tid = 2, .hdr_sig_id = 7, @@ -52701,7 +54301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2502] = { + [2582] = { .class_hid = BNXT_ULP_CLASS_HID_af4c, .class_tid = 2, .hdr_sig_id = 7, @@ -52723,7 +54323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2503] = { + [2583] = { .class_hid = BNXT_ULP_CLASS_HID_f00c, .class_tid = 2, .hdr_sig_id = 7, @@ -52745,7 +54345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2504] = { + [2584] = { .class_hid = BNXT_ULP_CLASS_HID_f5cc, .class_tid = 2, .hdr_sig_id = 7, @@ -52768,7 +54368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2505] = { + [2585] = { .class_hid = BNXT_ULP_CLASS_HID_1a38c, .class_tid = 2, .hdr_sig_id = 7, @@ -52790,7 +54390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2506] = { + [2586] = { .class_hid = BNXT_ULP_CLASS_HID_1a54c, .class_tid = 2, .hdr_sig_id = 7, @@ -52813,7 +54413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2507] = { + [2587] = { .class_hid = BNXT_ULP_CLASS_HID_1e60c, .class_tid = 2, .hdr_sig_id = 7, @@ -52836,7 +54436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2508] = { + [2588] = { .class_hid = BNXT_ULP_CLASS_HID_1ebcc, .class_tid = 2, .hdr_sig_id = 7, @@ -52860,7 +54460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2509] = { + [2589] = { .class_hid = BNXT_ULP_CLASS_HID_1a6b8, .class_tid = 2, .hdr_sig_id = 7, @@ -52881,7 +54481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2510] = { + [2590] = { .class_hid = BNXT_ULP_CLASS_HID_1a878, .class_tid = 2, .hdr_sig_id = 7, @@ -52903,7 +54503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2511] = { + [2591] = { .class_hid = BNXT_ULP_CLASS_HID_1ed38, .class_tid = 2, .hdr_sig_id = 7, @@ -52925,7 +54525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2512] = { + [2592] = { .class_hid = BNXT_ULP_CLASS_HID_1eef8, .class_tid = 2, .hdr_sig_id = 7, @@ -52948,7 +54548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2513] = { + [2593] = { .class_hid = BNXT_ULP_CLASS_HID_d52c, .class_tid = 2, .hdr_sig_id = 7, @@ -52969,7 +54569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2514] = { + [2594] = { .class_hid = BNXT_ULP_CLASS_HID_f6ec, .class_tid = 2, .hdr_sig_id = 7, @@ -52991,7 +54591,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2515] = { + [2595] = { .class_hid = BNXT_ULP_CLASS_HID_dbac, .class_tid = 2, .hdr_sig_id = 7, @@ -53013,7 +54613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2516] = { + [2596] = { .class_hid = BNXT_ULP_CLASS_HID_fd6c, .class_tid = 2, .hdr_sig_id = 7, @@ -53036,7 +54636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2517] = { + [2597] = { .class_hid = BNXT_ULP_CLASS_HID_ae70, .class_tid = 2, .hdr_sig_id = 7, @@ -53058,7 +54658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2518] = { + [2598] = { .class_hid = BNXT_ULP_CLASS_HID_f330, .class_tid = 2, .hdr_sig_id = 7, @@ -53081,7 +54681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2519] = { + [2599] = { .class_hid = BNXT_ULP_CLASS_HID_d4f0, .class_tid = 2, .hdr_sig_id = 7, @@ -53104,7 +54704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2520] = { + [2600] = { .class_hid = BNXT_ULP_CLASS_HID_f9b0, .class_tid = 2, .hdr_sig_id = 7, @@ -53128,7 +54728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2521] = { + [2601] = { .class_hid = BNXT_ULP_CLASS_HID_1c470, .class_tid = 2, .hdr_sig_id = 7, @@ -53151,7 +54751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2522] = { + [2602] = { .class_hid = BNXT_ULP_CLASS_HID_1e930, .class_tid = 2, .hdr_sig_id = 7, @@ -53175,7 +54775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2523] = { + [2603] = { .class_hid = BNXT_ULP_CLASS_HID_1caf0, .class_tid = 2, .hdr_sig_id = 7, @@ -53199,7 +54799,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2524] = { + [2604] = { .class_hid = BNXT_ULP_CLASS_HID_1f084, .class_tid = 2, .hdr_sig_id = 7, @@ -53224,7 +54824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2525] = { + [2605] = { .class_hid = BNXT_ULP_CLASS_HID_1cb2c, .class_tid = 2, .hdr_sig_id = 7, @@ -53246,7 +54846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2526] = { + [2606] = { .class_hid = BNXT_ULP_CLASS_HID_1b130, .class_tid = 2, .hdr_sig_id = 7, @@ -53269,7 +54869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2527] = { + [2607] = { .class_hid = BNXT_ULP_CLASS_HID_1d2f0, .class_tid = 2, .hdr_sig_id = 7, @@ -53292,7 +54892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2528] = { + [2608] = { .class_hid = BNXT_ULP_CLASS_HID_1f7b0, .class_tid = 2, .hdr_sig_id = 7, @@ -53316,7 +54916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2529] = { + [2609] = { .class_hid = BNXT_ULP_CLASS_HID_a1d0, .class_tid = 2, .hdr_sig_id = 7, @@ -53334,7 +54934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2530] = { + [2610] = { .class_hid = BNXT_ULP_CLASS_HID_a290, .class_tid = 2, .hdr_sig_id = 7, @@ -53353,7 +54953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2531] = { + [2611] = { .class_hid = BNXT_ULP_CLASS_HID_e450, .class_tid = 2, .hdr_sig_id = 7, @@ -53372,7 +54972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2532] = { + [2612] = { .class_hid = BNXT_ULP_CLASS_HID_e910, .class_tid = 2, .hdr_sig_id = 7, @@ -53392,7 +54992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2533] = { + [2613] = { .class_hid = BNXT_ULP_CLASS_HID_ba24, .class_tid = 2, .hdr_sig_id = 7, @@ -53411,7 +55011,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2534] = { + [2614] = { .class_hid = BNXT_ULP_CLASS_HID_bfe4, .class_tid = 2, .hdr_sig_id = 7, @@ -53431,7 +55031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2535] = { + [2615] = { .class_hid = BNXT_ULP_CLASS_HID_e0a4, .class_tid = 2, .hdr_sig_id = 7, @@ -53451,7 +55051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2536] = { + [2616] = { .class_hid = BNXT_ULP_CLASS_HID_e264, .class_tid = 2, .hdr_sig_id = 7, @@ -53472,7 +55072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2537] = { + [2617] = { .class_hid = BNXT_ULP_CLASS_HID_1d024, .class_tid = 2, .hdr_sig_id = 7, @@ -53492,7 +55092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2538] = { + [2618] = { .class_hid = BNXT_ULP_CLASS_HID_1f5e4, .class_tid = 2, .hdr_sig_id = 7, @@ -53513,7 +55113,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2539] = { + [2619] = { .class_hid = BNXT_ULP_CLASS_HID_1d6a4, .class_tid = 2, .hdr_sig_id = 7, @@ -53534,7 +55134,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2540] = { + [2620] = { .class_hid = BNXT_ULP_CLASS_HID_1f864, .class_tid = 2, .hdr_sig_id = 7, @@ -53556,7 +55156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2541] = { + [2621] = { .class_hid = BNXT_ULP_CLASS_HID_1d7d0, .class_tid = 2, .hdr_sig_id = 7, @@ -53575,7 +55175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2542] = { + [2622] = { .class_hid = BNXT_ULP_CLASS_HID_1f890, .class_tid = 2, .hdr_sig_id = 7, @@ -53595,7 +55195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2543] = { + [2623] = { .class_hid = BNXT_ULP_CLASS_HID_1da50, .class_tid = 2, .hdr_sig_id = 7, @@ -53615,7 +55215,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2544] = { + [2624] = { .class_hid = BNXT_ULP_CLASS_HID_1ff10, .class_tid = 2, .hdr_sig_id = 7, @@ -53636,7 +55236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2545] = { + [2625] = { .class_hid = BNXT_ULP_CLASS_HID_c244, .class_tid = 2, .hdr_sig_id = 7, @@ -53655,7 +55255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2546] = { + [2626] = { .class_hid = BNXT_ULP_CLASS_HID_e704, .class_tid = 2, .hdr_sig_id = 7, @@ -53675,7 +55275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2547] = { + [2627] = { .class_hid = BNXT_ULP_CLASS_HID_c8c4, .class_tid = 2, .hdr_sig_id = 7, @@ -53695,7 +55295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2548] = { + [2628] = { .class_hid = BNXT_ULP_CLASS_HID_ed84, .class_tid = 2, .hdr_sig_id = 7, @@ -53716,7 +55316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2549] = { + [2629] = { .class_hid = BNXT_ULP_CLASS_HID_de88, .class_tid = 2, .hdr_sig_id = 7, @@ -53736,7 +55336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2550] = { + [2630] = { .class_hid = BNXT_ULP_CLASS_HID_e048, .class_tid = 2, .hdr_sig_id = 7, @@ -53757,7 +55357,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2551] = { + [2631] = { .class_hid = BNXT_ULP_CLASS_HID_c508, .class_tid = 2, .hdr_sig_id = 7, @@ -53778,7 +55378,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2552] = { + [2632] = { .class_hid = BNXT_ULP_CLASS_HID_e6c8, .class_tid = 2, .hdr_sig_id = 7, @@ -53800,7 +55400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2553] = { + [2633] = { .class_hid = BNXT_ULP_CLASS_HID_199dc, .class_tid = 2, .hdr_sig_id = 7, @@ -53821,7 +55421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2554] = { + [2634] = { .class_hid = BNXT_ULP_CLASS_HID_1ba9c, .class_tid = 2, .hdr_sig_id = 7, @@ -53843,7 +55443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2555] = { + [2635] = { .class_hid = BNXT_ULP_CLASS_HID_1dc5c, .class_tid = 2, .hdr_sig_id = 7, @@ -53865,7 +55465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2556] = { + [2636] = { .class_hid = BNXT_ULP_CLASS_HID_1e11c, .class_tid = 2, .hdr_sig_id = 7, @@ -53888,7 +55488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2557] = { + [2637] = { .class_hid = BNXT_ULP_CLASS_HID_19c88, .class_tid = 2, .hdr_sig_id = 7, @@ -53908,7 +55508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2558] = { + [2638] = { .class_hid = BNXT_ULP_CLASS_HID_1be48, .class_tid = 2, .hdr_sig_id = 7, @@ -53929,7 +55529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2559] = { + [2639] = { .class_hid = BNXT_ULP_CLASS_HID_1c308, .class_tid = 2, .hdr_sig_id = 7, @@ -53950,7 +55550,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2560] = { + [2640] = { .class_hid = BNXT_ULP_CLASS_HID_1e4c8, .class_tid = 2, .hdr_sig_id = 7, @@ -53972,7 +55572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2561] = { + [2641] = { .class_hid = BNXT_ULP_CLASS_HID_8b7c, .class_tid = 2, .hdr_sig_id = 7, @@ -53991,7 +55591,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2562] = { + [2642] = { .class_hid = BNXT_ULP_CLASS_HID_ac3c, .class_tid = 2, .hdr_sig_id = 7, @@ -54011,7 +55611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2563] = { + [2643] = { .class_hid = BNXT_ULP_CLASS_HID_f1fc, .class_tid = 2, .hdr_sig_id = 7, @@ -54031,7 +55631,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2564] = { + [2644] = { .class_hid = BNXT_ULP_CLASS_HID_f2bc, .class_tid = 2, .hdr_sig_id = 7, @@ -54052,7 +55652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2565] = { + [2645] = { .class_hid = BNXT_ULP_CLASS_HID_8440, .class_tid = 2, .hdr_sig_id = 7, @@ -54072,7 +55672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2566] = { + [2646] = { .class_hid = BNXT_ULP_CLASS_HID_a900, .class_tid = 2, .hdr_sig_id = 7, @@ -54093,7 +55693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2567] = { + [2647] = { .class_hid = BNXT_ULP_CLASS_HID_cac0, .class_tid = 2, .hdr_sig_id = 7, @@ -54114,7 +55714,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2568] = { + [2648] = { .class_hid = BNXT_ULP_CLASS_HID_ef80, .class_tid = 2, .hdr_sig_id = 7, @@ -54136,7 +55736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2569] = { + [2649] = { .class_hid = BNXT_ULP_CLASS_HID_1ba40, .class_tid = 2, .hdr_sig_id = 7, @@ -54157,7 +55757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2570] = { + [2650] = { .class_hid = BNXT_ULP_CLASS_HID_1bf00, .class_tid = 2, .hdr_sig_id = 7, @@ -54179,7 +55779,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2571] = { + [2651] = { .class_hid = BNXT_ULP_CLASS_HID_1e0c0, .class_tid = 2, .hdr_sig_id = 7, @@ -54201,7 +55801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2572] = { + [2652] = { .class_hid = BNXT_ULP_CLASS_HID_1e580, .class_tid = 2, .hdr_sig_id = 7, @@ -54224,7 +55824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2573] = { + [2653] = { .class_hid = BNXT_ULP_CLASS_HID_1a17c, .class_tid = 2, .hdr_sig_id = 7, @@ -54244,7 +55844,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2574] = { + [2654] = { .class_hid = BNXT_ULP_CLASS_HID_1a23c, .class_tid = 2, .hdr_sig_id = 7, @@ -54265,7 +55865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2575] = { + [2655] = { .class_hid = BNXT_ULP_CLASS_HID_1e7fc, .class_tid = 2, .hdr_sig_id = 7, @@ -54286,7 +55886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2576] = { + [2656] = { .class_hid = BNXT_ULP_CLASS_HID_1e8bc, .class_tid = 2, .hdr_sig_id = 7, @@ -54308,7 +55908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2577] = { + [2657] = { .class_hid = BNXT_ULP_CLASS_HID_afe0, .class_tid = 2, .hdr_sig_id = 7, @@ -54328,7 +55928,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2578] = { + [2658] = { .class_hid = BNXT_ULP_CLASS_HID_f0a0, .class_tid = 2, .hdr_sig_id = 7, @@ -54349,7 +55949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2579] = { + [2659] = { .class_hid = BNXT_ULP_CLASS_HID_d260, .class_tid = 2, .hdr_sig_id = 7, @@ -54370,7 +55970,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2580] = { + [2660] = { .class_hid = BNXT_ULP_CLASS_HID_f720, .class_tid = 2, .hdr_sig_id = 7, @@ -54392,7 +55992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2581] = { + [2661] = { .class_hid = BNXT_ULP_CLASS_HID_a834, .class_tid = 2, .hdr_sig_id = 7, @@ -54413,7 +56013,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2582] = { + [2662] = { .class_hid = BNXT_ULP_CLASS_HID_adf4, .class_tid = 2, .hdr_sig_id = 7, @@ -54435,7 +56035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2583] = { + [2663] = { .class_hid = BNXT_ULP_CLASS_HID_eeb4, .class_tid = 2, .hdr_sig_id = 7, @@ -54457,7 +56057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2584] = { + [2664] = { .class_hid = BNXT_ULP_CLASS_HID_f074, .class_tid = 2, .hdr_sig_id = 7, @@ -54480,7 +56080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2585] = { + [2665] = { .class_hid = BNXT_ULP_CLASS_HID_1de34, .class_tid = 2, .hdr_sig_id = 7, @@ -54502,7 +56102,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2586] = { + [2666] = { .class_hid = BNXT_ULP_CLASS_HID_1e3f4, .class_tid = 2, .hdr_sig_id = 7, @@ -54525,7 +56125,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2587] = { + [2667] = { .class_hid = BNXT_ULP_CLASS_HID_1c4b4, .class_tid = 2, .hdr_sig_id = 7, @@ -54548,7 +56148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2588] = { + [2668] = { .class_hid = BNXT_ULP_CLASS_HID_1e674, .class_tid = 2, .hdr_sig_id = 7, @@ -54572,7 +56172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2589] = { + [2669] = { .class_hid = BNXT_ULP_CLASS_HID_1c5e0, .class_tid = 2, .hdr_sig_id = 7, @@ -54593,7 +56193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2590] = { + [2670] = { .class_hid = BNXT_ULP_CLASS_HID_1e6a0, .class_tid = 2, .hdr_sig_id = 7, @@ -54615,7 +56215,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2591] = { + [2671] = { .class_hid = BNXT_ULP_CLASS_HID_1c860, .class_tid = 2, .hdr_sig_id = 7, @@ -54637,7 +56237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2592] = { + [2672] = { .class_hid = BNXT_ULP_CLASS_HID_1ed20, .class_tid = 2, .hdr_sig_id = 7, @@ -54660,7 +56260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2593] = { + [2673] = { .class_hid = BNXT_ULP_CLASS_HID_8c0c, .class_tid = 2, .hdr_sig_id = 7, @@ -54678,7 +56278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2594] = { + [2674] = { .class_hid = BNXT_ULP_CLASS_HID_b1cc, .class_tid = 2, .hdr_sig_id = 7, @@ -54697,7 +56297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2595] = { + [2675] = { .class_hid = BNXT_ULP_CLASS_HID_f28c, .class_tid = 2, .hdr_sig_id = 7, @@ -54716,7 +56316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2596] = { + [2676] = { .class_hid = BNXT_ULP_CLASS_HID_f44c, .class_tid = 2, .hdr_sig_id = 7, @@ -54736,7 +56336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2597] = { + [2677] = { .class_hid = BNXT_ULP_CLASS_HID_8950, .class_tid = 2, .hdr_sig_id = 7, @@ -54755,7 +56355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2598] = { + [2678] = { .class_hid = BNXT_ULP_CLASS_HID_aa10, .class_tid = 2, .hdr_sig_id = 7, @@ -54775,7 +56375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2599] = { + [2679] = { .class_hid = BNXT_ULP_CLASS_HID_cfd0, .class_tid = 2, .hdr_sig_id = 7, @@ -54795,7 +56395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2600] = { + [2680] = { .class_hid = BNXT_ULP_CLASS_HID_f090, .class_tid = 2, .hdr_sig_id = 7, @@ -54816,7 +56416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2601] = { + [2681] = { .class_hid = BNXT_ULP_CLASS_HID_1bf50, .class_tid = 2, .hdr_sig_id = 7, @@ -54836,7 +56436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2602] = { + [2682] = { .class_hid = BNXT_ULP_CLASS_HID_1a010, .class_tid = 2, .hdr_sig_id = 7, @@ -54857,7 +56457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2603] = { + [2683] = { .class_hid = BNXT_ULP_CLASS_HID_1e5d0, .class_tid = 2, .hdr_sig_id = 7, @@ -54878,7 +56478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2604] = { + [2684] = { .class_hid = BNXT_ULP_CLASS_HID_1e690, .class_tid = 2, .hdr_sig_id = 7, @@ -54900,7 +56500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2605] = { + [2685] = { .class_hid = BNXT_ULP_CLASS_HID_1a20c, .class_tid = 2, .hdr_sig_id = 7, @@ -54919,7 +56519,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2606] = { + [2686] = { .class_hid = BNXT_ULP_CLASS_HID_1a7cc, .class_tid = 2, .hdr_sig_id = 7, @@ -54939,7 +56539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2607] = { + [2687] = { .class_hid = BNXT_ULP_CLASS_HID_1e88c, .class_tid = 2, .hdr_sig_id = 7, @@ -54959,7 +56559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2608] = { + [2688] = { .class_hid = BNXT_ULP_CLASS_HID_1ea4c, .class_tid = 2, .hdr_sig_id = 7, @@ -54980,7 +56580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2609] = { + [2689] = { .class_hid = BNXT_ULP_CLASS_HID_d0f0, .class_tid = 2, .hdr_sig_id = 7, @@ -54999,7 +56599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2610] = { + [2690] = { .class_hid = BNXT_ULP_CLASS_HID_f5b0, .class_tid = 2, .hdr_sig_id = 7, @@ -55019,7 +56619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2611] = { + [2691] = { .class_hid = BNXT_ULP_CLASS_HID_d770, .class_tid = 2, .hdr_sig_id = 7, @@ -55039,7 +56639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2612] = { + [2692] = { .class_hid = BNXT_ULP_CLASS_HID_f830, .class_tid = 2, .hdr_sig_id = 7, @@ -55060,7 +56660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2613] = { + [2693] = { .class_hid = BNXT_ULP_CLASS_HID_adc4, .class_tid = 2, .hdr_sig_id = 7, @@ -55080,7 +56680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2614] = { + [2694] = { .class_hid = BNXT_ULP_CLASS_HID_ae84, .class_tid = 2, .hdr_sig_id = 7, @@ -55101,7 +56701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2615] = { + [2695] = { .class_hid = BNXT_ULP_CLASS_HID_d044, .class_tid = 2, .hdr_sig_id = 7, @@ -55122,7 +56722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2616] = { + [2696] = { .class_hid = BNXT_ULP_CLASS_HID_f504, .class_tid = 2, .hdr_sig_id = 7, @@ -55144,7 +56744,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2617] = { + [2697] = { .class_hid = BNXT_ULP_CLASS_HID_1c3c4, .class_tid = 2, .hdr_sig_id = 7, @@ -55165,7 +56765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2618] = { + [2698] = { .class_hid = BNXT_ULP_CLASS_HID_1e484, .class_tid = 2, .hdr_sig_id = 7, @@ -55187,7 +56787,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2619] = { + [2699] = { .class_hid = BNXT_ULP_CLASS_HID_1c644, .class_tid = 2, .hdr_sig_id = 7, @@ -55209,7 +56809,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2620] = { + [2700] = { .class_hid = BNXT_ULP_CLASS_HID_1eb04, .class_tid = 2, .hdr_sig_id = 7, @@ -55232,7 +56832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2621] = { + [2701] = { .class_hid = BNXT_ULP_CLASS_HID_1c6f0, .class_tid = 2, .hdr_sig_id = 7, @@ -55252,7 +56852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2622] = { + [2702] = { .class_hid = BNXT_ULP_CLASS_HID_1ebb0, .class_tid = 2, .hdr_sig_id = 7, @@ -55273,7 +56873,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2623] = { + [2703] = { .class_hid = BNXT_ULP_CLASS_HID_1cd70, .class_tid = 2, .hdr_sig_id = 7, @@ -55294,7 +56894,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2624] = { + [2704] = { .class_hid = BNXT_ULP_CLASS_HID_1f304, .class_tid = 2, .hdr_sig_id = 7, @@ -55316,7 +56916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2625] = { + [2705] = { .class_hid = BNXT_ULP_CLASS_HID_99a8, .class_tid = 2, .hdr_sig_id = 7, @@ -55335,7 +56935,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2626] = { + [2706] = { .class_hid = BNXT_ULP_CLASS_HID_bb68, .class_tid = 2, .hdr_sig_id = 7, @@ -55355,7 +56955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2627] = { + [2707] = { .class_hid = BNXT_ULP_CLASS_HID_dc28, .class_tid = 2, .hdr_sig_id = 7, @@ -55375,7 +56975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2628] = { + [2708] = { .class_hid = BNXT_ULP_CLASS_HID_e1e8, .class_tid = 2, .hdr_sig_id = 7, @@ -55396,7 +56996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2629] = { + [2709] = { .class_hid = BNXT_ULP_CLASS_HID_92fc, .class_tid = 2, .hdr_sig_id = 7, @@ -55416,7 +57016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2630] = { + [2710] = { .class_hid = BNXT_ULP_CLASS_HID_b7bc, .class_tid = 2, .hdr_sig_id = 7, @@ -55437,7 +57037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2631] = { + [2711] = { .class_hid = BNXT_ULP_CLASS_HID_d97c, .class_tid = 2, .hdr_sig_id = 7, @@ -55458,7 +57058,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2632] = { + [2712] = { .class_hid = BNXT_ULP_CLASS_HID_fa3c, .class_tid = 2, .hdr_sig_id = 7, @@ -55480,7 +57080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2633] = { + [2713] = { .class_hid = BNXT_ULP_CLASS_HID_188fc, .class_tid = 2, .hdr_sig_id = 7, @@ -55501,7 +57101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2634] = { + [2714] = { .class_hid = BNXT_ULP_CLASS_HID_1adbc, .class_tid = 2, .hdr_sig_id = 7, @@ -55523,7 +57123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2635] = { + [2715] = { .class_hid = BNXT_ULP_CLASS_HID_1cf7c, .class_tid = 2, .hdr_sig_id = 7, @@ -55545,7 +57145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2636] = { + [2716] = { .class_hid = BNXT_ULP_CLASS_HID_1f03c, .class_tid = 2, .hdr_sig_id = 7, @@ -55568,7 +57168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2637] = { + [2717] = { .class_hid = BNXT_ULP_CLASS_HID_18fa8, .class_tid = 2, .hdr_sig_id = 7, @@ -55588,7 +57188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2638] = { + [2718] = { .class_hid = BNXT_ULP_CLASS_HID_1b168, .class_tid = 2, .hdr_sig_id = 7, @@ -55609,7 +57209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2639] = { + [2719] = { .class_hid = BNXT_ULP_CLASS_HID_1f228, .class_tid = 2, .hdr_sig_id = 7, @@ -55630,7 +57230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2640] = { + [2720] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e8, .class_tid = 2, .hdr_sig_id = 7, @@ -55652,7 +57252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2641] = { + [2721] = { .class_hid = BNXT_ULP_CLASS_HID_ba1c, .class_tid = 2, .hdr_sig_id = 7, @@ -55672,7 +57272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2642] = { + [2722] = { .class_hid = BNXT_ULP_CLASS_HID_bfdc, .class_tid = 2, .hdr_sig_id = 7, @@ -55693,7 +57293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2643] = { + [2723] = { .class_hid = BNXT_ULP_CLASS_HID_e09c, .class_tid = 2, .hdr_sig_id = 7, @@ -55714,7 +57314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2644] = { + [2724] = { .class_hid = BNXT_ULP_CLASS_HID_e25c, .class_tid = 2, .hdr_sig_id = 7, @@ -55736,7 +57336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2645] = { + [2725] = { .class_hid = BNXT_ULP_CLASS_HID_b760, .class_tid = 2, .hdr_sig_id = 7, @@ -55757,7 +57357,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2646] = { + [2726] = { .class_hid = BNXT_ULP_CLASS_HID_b820, .class_tid = 2, .hdr_sig_id = 7, @@ -55779,7 +57379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2647] = { + [2727] = { .class_hid = BNXT_ULP_CLASS_HID_fde0, .class_tid = 2, .hdr_sig_id = 7, @@ -55801,7 +57401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2648] = { + [2728] = { .class_hid = BNXT_ULP_CLASS_HID_fea0, .class_tid = 2, .hdr_sig_id = 7, @@ -55824,7 +57424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2649] = { + [2729] = { .class_hid = BNXT_ULP_CLASS_HID_1ad60, .class_tid = 2, .hdr_sig_id = 7, @@ -55846,7 +57446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2650] = { + [2730] = { .class_hid = BNXT_ULP_CLASS_HID_1ae20, .class_tid = 2, .hdr_sig_id = 7, @@ -55869,7 +57469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2651] = { + [2731] = { .class_hid = BNXT_ULP_CLASS_HID_1d3e0, .class_tid = 2, .hdr_sig_id = 7, @@ -55892,7 +57492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2652] = { + [2732] = { .class_hid = BNXT_ULP_CLASS_HID_1f4a0, .class_tid = 2, .hdr_sig_id = 7, @@ -55916,7 +57516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2653] = { + [2733] = { .class_hid = BNXT_ULP_CLASS_HID_1d01c, .class_tid = 2, .hdr_sig_id = 7, @@ -55937,7 +57537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2654] = { + [2734] = { .class_hid = BNXT_ULP_CLASS_HID_1f5dc, .class_tid = 2, .hdr_sig_id = 7, @@ -55959,7 +57559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2655] = { + [2735] = { .class_hid = BNXT_ULP_CLASS_HID_1d69c, .class_tid = 2, .hdr_sig_id = 7, @@ -55981,7 +57581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2656] = { + [2736] = { .class_hid = BNXT_ULP_CLASS_HID_1f85c, .class_tid = 2, .hdr_sig_id = 7, @@ -56004,7 +57604,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2657] = { + [2737] = { .class_hid = BNXT_ULP_CLASS_HID_86c0, .class_tid = 2, .hdr_sig_id = 7, @@ -56021,7 +57621,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2658] = { + [2738] = { .class_hid = BNXT_ULP_CLASS_HID_ab80, .class_tid = 2, .hdr_sig_id = 7, @@ -56039,7 +57639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2659] = { + [2739] = { .class_hid = BNXT_ULP_CLASS_HID_cd40, .class_tid = 2, .hdr_sig_id = 7, @@ -56057,7 +57657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2660] = { + [2740] = { .class_hid = BNXT_ULP_CLASS_HID_ee00, .class_tid = 2, .hdr_sig_id = 7, @@ -56076,7 +57676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2661] = { + [2741] = { .class_hid = BNXT_ULP_CLASS_HID_8314, .class_tid = 2, .hdr_sig_id = 7, @@ -56094,7 +57694,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2662] = { + [2742] = { .class_hid = BNXT_ULP_CLASS_HID_a4d4, .class_tid = 2, .hdr_sig_id = 7, @@ -56113,7 +57713,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2663] = { + [2743] = { .class_hid = BNXT_ULP_CLASS_HID_c994, .class_tid = 2, .hdr_sig_id = 7, @@ -56132,7 +57732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2664] = { + [2744] = { .class_hid = BNXT_ULP_CLASS_HID_eb54, .class_tid = 2, .hdr_sig_id = 7, @@ -56152,7 +57752,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2665] = { + [2745] = { .class_hid = BNXT_ULP_CLASS_HID_1b914, .class_tid = 2, .hdr_sig_id = 7, @@ -56171,7 +57771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2666] = { + [2746] = { .class_hid = BNXT_ULP_CLASS_HID_1bad4, .class_tid = 2, .hdr_sig_id = 7, @@ -56191,7 +57791,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2667] = { + [2747] = { .class_hid = BNXT_ULP_CLASS_HID_1ff94, .class_tid = 2, .hdr_sig_id = 7, @@ -56211,7 +57811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2668] = { + [2748] = { .class_hid = BNXT_ULP_CLASS_HID_1e154, .class_tid = 2, .hdr_sig_id = 7, @@ -56232,7 +57832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2669] = { + [2749] = { .class_hid = BNXT_ULP_CLASS_HID_1bcc0, .class_tid = 2, .hdr_sig_id = 7, @@ -56250,7 +57850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2670] = { + [2750] = { .class_hid = BNXT_ULP_CLASS_HID_1a180, .class_tid = 2, .hdr_sig_id = 7, @@ -56269,7 +57869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2671] = { + [2751] = { .class_hid = BNXT_ULP_CLASS_HID_1e340, .class_tid = 2, .hdr_sig_id = 7, @@ -56288,7 +57888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2672] = { + [2752] = { .class_hid = BNXT_ULP_CLASS_HID_1e400, .class_tid = 2, .hdr_sig_id = 7, @@ -56308,7 +57908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2673] = { + [2753] = { .class_hid = BNXT_ULP_CLASS_HID_aab4, .class_tid = 2, .hdr_sig_id = 7, @@ -56326,7 +57926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2674] = { + [2754] = { .class_hid = BNXT_ULP_CLASS_HID_ac74, .class_tid = 2, .hdr_sig_id = 7, @@ -56345,7 +57945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2675] = { + [2755] = { .class_hid = BNXT_ULP_CLASS_HID_d134, .class_tid = 2, .hdr_sig_id = 7, @@ -56364,7 +57964,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2676] = { + [2756] = { .class_hid = BNXT_ULP_CLASS_HID_f2f4, .class_tid = 2, .hdr_sig_id = 7, @@ -56384,7 +57984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2677] = { + [2757] = { .class_hid = BNXT_ULP_CLASS_HID_a7f8, .class_tid = 2, .hdr_sig_id = 7, @@ -56403,7 +58003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2678] = { + [2758] = { .class_hid = BNXT_ULP_CLASS_HID_a8b8, .class_tid = 2, .hdr_sig_id = 7, @@ -56423,7 +58023,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2679] = { + [2759] = { .class_hid = BNXT_ULP_CLASS_HID_ea78, .class_tid = 2, .hdr_sig_id = 7, @@ -56443,7 +58043,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2680] = { + [2760] = { .class_hid = BNXT_ULP_CLASS_HID_ef38, .class_tid = 2, .hdr_sig_id = 7, @@ -56464,7 +58064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2681] = { + [2761] = { .class_hid = BNXT_ULP_CLASS_HID_1ddf8, .class_tid = 2, .hdr_sig_id = 7, @@ -56484,7 +58084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2682] = { + [2762] = { .class_hid = BNXT_ULP_CLASS_HID_1feb8, .class_tid = 2, .hdr_sig_id = 7, @@ -56505,7 +58105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2683] = { + [2763] = { .class_hid = BNXT_ULP_CLASS_HID_1c078, .class_tid = 2, .hdr_sig_id = 7, @@ -56526,7 +58126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2684] = { + [2764] = { .class_hid = BNXT_ULP_CLASS_HID_1e538, .class_tid = 2, .hdr_sig_id = 7, @@ -56548,7 +58148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2685] = { + [2765] = { .class_hid = BNXT_ULP_CLASS_HID_1c0b4, .class_tid = 2, .hdr_sig_id = 7, @@ -56567,7 +58167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2686] = { + [2766] = { .class_hid = BNXT_ULP_CLASS_HID_1e274, .class_tid = 2, .hdr_sig_id = 7, @@ -56587,7 +58187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2687] = { + [2767] = { .class_hid = BNXT_ULP_CLASS_HID_1c734, .class_tid = 2, .hdr_sig_id = 7, @@ -56607,7 +58207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2688] = { + [2768] = { .class_hid = BNXT_ULP_CLASS_HID_1e8f4, .class_tid = 2, .hdr_sig_id = 7, @@ -56628,7 +58228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2689] = { + [2769] = { .class_hid = BNXT_ULP_CLASS_HID_906c, .class_tid = 2, .hdr_sig_id = 7, @@ -56646,7 +58246,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2690] = { + [2770] = { .class_hid = BNXT_ULP_CLASS_HID_b52c, .class_tid = 2, .hdr_sig_id = 7, @@ -56665,7 +58265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2691] = { + [2771] = { .class_hid = BNXT_ULP_CLASS_HID_d6ec, .class_tid = 2, .hdr_sig_id = 7, @@ -56684,7 +58284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2692] = { + [2772] = { .class_hid = BNXT_ULP_CLASS_HID_fbac, .class_tid = 2, .hdr_sig_id = 7, @@ -56704,7 +58304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2693] = { + [2773] = { .class_hid = BNXT_ULP_CLASS_HID_c86c, .class_tid = 2, .hdr_sig_id = 7, @@ -56723,7 +58323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2694] = { + [2774] = { .class_hid = BNXT_ULP_CLASS_HID_ed2c, .class_tid = 2, .hdr_sig_id = 7, @@ -56743,7 +58343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2695] = { + [2775] = { .class_hid = BNXT_ULP_CLASS_HID_d330, .class_tid = 2, .hdr_sig_id = 7, @@ -56763,7 +58363,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2696] = { + [2776] = { .class_hid = BNXT_ULP_CLASS_HID_f4f0, .class_tid = 2, .hdr_sig_id = 7, @@ -56784,7 +58384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2697] = { + [2777] = { .class_hid = BNXT_ULP_CLASS_HID_182b0, .class_tid = 2, .hdr_sig_id = 7, @@ -56804,7 +58404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2698] = { + [2778] = { .class_hid = BNXT_ULP_CLASS_HID_1a470, .class_tid = 2, .hdr_sig_id = 7, @@ -56825,7 +58425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2699] = { + [2779] = { .class_hid = BNXT_ULP_CLASS_HID_1c930, .class_tid = 2, .hdr_sig_id = 7, @@ -56846,7 +58446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2700] = { + [2780] = { .class_hid = BNXT_ULP_CLASS_HID_1eaf0, .class_tid = 2, .hdr_sig_id = 7, @@ -56868,7 +58468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2701] = { + [2781] = { .class_hid = BNXT_ULP_CLASS_HID_1866c, .class_tid = 2, .hdr_sig_id = 7, @@ -56887,7 +58487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2702] = { + [2782] = { .class_hid = BNXT_ULP_CLASS_HID_1ab2c, .class_tid = 2, .hdr_sig_id = 7, @@ -56907,7 +58507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2703] = { + [2783] = { .class_hid = BNXT_ULP_CLASS_HID_1ccec, .class_tid = 2, .hdr_sig_id = 7, @@ -56927,7 +58527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2704] = { + [2784] = { .class_hid = BNXT_ULP_CLASS_HID_1f1ac, .class_tid = 2, .hdr_sig_id = 7, @@ -56948,7 +58548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2705] = { + [2785] = { .class_hid = BNXT_ULP_CLASS_HID_b4d0, .class_tid = 2, .hdr_sig_id = 7, @@ -56967,7 +58567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2706] = { + [2786] = { .class_hid = BNXT_ULP_CLASS_HID_b990, .class_tid = 2, .hdr_sig_id = 7, @@ -56987,7 +58587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2707] = { + [2787] = { .class_hid = BNXT_ULP_CLASS_HID_fb50, .class_tid = 2, .hdr_sig_id = 7, @@ -57007,7 +58607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2708] = { + [2788] = { .class_hid = BNXT_ULP_CLASS_HID_fc10, .class_tid = 2, .hdr_sig_id = 7, @@ -57028,7 +58628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2709] = { + [2789] = { .class_hid = BNXT_ULP_CLASS_HID_b124, .class_tid = 2, .hdr_sig_id = 7, @@ -57048,7 +58648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2710] = { + [2790] = { .class_hid = BNXT_ULP_CLASS_HID_b2e4, .class_tid = 2, .hdr_sig_id = 7, @@ -57069,7 +58669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2711] = { + [2791] = { .class_hid = BNXT_ULP_CLASS_HID_f7a4, .class_tid = 2, .hdr_sig_id = 7, @@ -57090,7 +58690,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2712] = { + [2792] = { .class_hid = BNXT_ULP_CLASS_HID_f964, .class_tid = 2, .hdr_sig_id = 7, @@ -57112,7 +58712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2713] = { + [2793] = { .class_hid = BNXT_ULP_CLASS_HID_1a724, .class_tid = 2, .hdr_sig_id = 7, @@ -57133,7 +58733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2714] = { + [2794] = { .class_hid = BNXT_ULP_CLASS_HID_1a8e4, .class_tid = 2, .hdr_sig_id = 7, @@ -57155,7 +58755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2715] = { + [2795] = { .class_hid = BNXT_ULP_CLASS_HID_1eda4, .class_tid = 2, .hdr_sig_id = 7, @@ -57177,7 +58777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2716] = { + [2796] = { .class_hid = BNXT_ULP_CLASS_HID_1ef64, .class_tid = 2, .hdr_sig_id = 7, @@ -57200,7 +58800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2717] = { + [2797] = { .class_hid = BNXT_ULP_CLASS_HID_1aad0, .class_tid = 2, .hdr_sig_id = 7, @@ -57220,7 +58820,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2718] = { + [2798] = { .class_hid = BNXT_ULP_CLASS_HID_1af90, .class_tid = 2, .hdr_sig_id = 7, @@ -57241,7 +58841,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2719] = { + [2799] = { .class_hid = BNXT_ULP_CLASS_HID_1d150, .class_tid = 2, .hdr_sig_id = 7, @@ -57262,7 +58862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2720] = { + [2800] = { .class_hid = BNXT_ULP_CLASS_HID_1f210, .class_tid = 2, .hdr_sig_id = 7, @@ -57284,7 +58884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2721] = { + [2801] = { .class_hid = BNXT_ULP_CLASS_HID_8084, .class_tid = 2, .hdr_sig_id = 7, @@ -57301,7 +58901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2722] = { + [2802] = { .class_hid = BNXT_ULP_CLASS_HID_a244, .class_tid = 2, .hdr_sig_id = 7, @@ -57319,7 +58919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2723] = { + [2803] = { .class_hid = BNXT_ULP_CLASS_HID_c704, .class_tid = 2, .hdr_sig_id = 7, @@ -57337,7 +58937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2724] = { + [2804] = { .class_hid = BNXT_ULP_CLASS_HID_e8c4, .class_tid = 2, .hdr_sig_id = 7, @@ -57356,7 +58956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2725] = { + [2805] = { .class_hid = BNXT_ULP_CLASS_HID_9dc8, .class_tid = 2, .hdr_sig_id = 7, @@ -57374,7 +58974,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2726] = { + [2806] = { .class_hid = BNXT_ULP_CLASS_HID_be88, .class_tid = 2, .hdr_sig_id = 7, @@ -57393,7 +58993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2727] = { + [2807] = { .class_hid = BNXT_ULP_CLASS_HID_c048, .class_tid = 2, .hdr_sig_id = 7, @@ -57412,7 +59012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2728] = { + [2808] = { .class_hid = BNXT_ULP_CLASS_HID_e508, .class_tid = 2, .hdr_sig_id = 7, @@ -57432,7 +59032,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2729] = { + [2809] = { .class_hid = BNXT_ULP_CLASS_HID_1b3c8, .class_tid = 2, .hdr_sig_id = 7, @@ -57451,7 +59051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2730] = { + [2810] = { .class_hid = BNXT_ULP_CLASS_HID_1b488, .class_tid = 2, .hdr_sig_id = 7, @@ -57471,7 +59071,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2731] = { + [2811] = { .class_hid = BNXT_ULP_CLASS_HID_1f648, .class_tid = 2, .hdr_sig_id = 7, @@ -57491,7 +59091,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2732] = { + [2812] = { .class_hid = BNXT_ULP_CLASS_HID_1fb08, .class_tid = 2, .hdr_sig_id = 7, @@ -57512,7 +59112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2733] = { + [2813] = { .class_hid = BNXT_ULP_CLASS_HID_1b684, .class_tid = 2, .hdr_sig_id = 7, @@ -57530,7 +59130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2734] = { + [2814] = { .class_hid = BNXT_ULP_CLASS_HID_1b844, .class_tid = 2, .hdr_sig_id = 7, @@ -57549,7 +59149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2735] = { + [2815] = { .class_hid = BNXT_ULP_CLASS_HID_1fd04, .class_tid = 2, .hdr_sig_id = 7, @@ -57568,7 +59168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2736] = { + [2816] = { .class_hid = BNXT_ULP_CLASS_HID_1fec4, .class_tid = 2, .hdr_sig_id = 7, @@ -57588,7 +59188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2737] = { + [2817] = { .class_hid = BNXT_ULP_CLASS_HID_a568, .class_tid = 2, .hdr_sig_id = 7, @@ -57606,7 +59206,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2738] = { + [2818] = { .class_hid = BNXT_ULP_CLASS_HID_a628, .class_tid = 2, .hdr_sig_id = 7, @@ -57625,7 +59225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2739] = { + [2819] = { .class_hid = BNXT_ULP_CLASS_HID_ebe8, .class_tid = 2, .hdr_sig_id = 7, @@ -57644,7 +59244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2740] = { + [2820] = { .class_hid = BNXT_ULP_CLASS_HID_eca8, .class_tid = 2, .hdr_sig_id = 7, @@ -57664,7 +59264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2741] = { + [2821] = { .class_hid = BNXT_ULP_CLASS_HID_a1bc, .class_tid = 2, .hdr_sig_id = 7, @@ -57683,7 +59283,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2742] = { + [2822] = { .class_hid = BNXT_ULP_CLASS_HID_a37c, .class_tid = 2, .hdr_sig_id = 7, @@ -57703,7 +59303,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2743] = { + [2823] = { .class_hid = BNXT_ULP_CLASS_HID_e43c, .class_tid = 2, .hdr_sig_id = 7, @@ -57723,7 +59323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2744] = { + [2824] = { .class_hid = BNXT_ULP_CLASS_HID_e9fc, .class_tid = 2, .hdr_sig_id = 7, @@ -57744,7 +59344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2745] = { + [2825] = { .class_hid = BNXT_ULP_CLASS_HID_1d7bc, .class_tid = 2, .hdr_sig_id = 7, @@ -57764,7 +59364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2746] = { + [2826] = { .class_hid = BNXT_ULP_CLASS_HID_1f97c, .class_tid = 2, .hdr_sig_id = 7, @@ -57785,7 +59385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2747] = { + [2827] = { .class_hid = BNXT_ULP_CLASS_HID_1da3c, .class_tid = 2, .hdr_sig_id = 7, @@ -57806,7 +59406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2748] = { + [2828] = { .class_hid = BNXT_ULP_CLASS_HID_1fffc, .class_tid = 2, .hdr_sig_id = 7, @@ -57828,7 +59428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2749] = { + [2829] = { .class_hid = BNXT_ULP_CLASS_HID_1db68, .class_tid = 2, .hdr_sig_id = 7, @@ -57847,7 +59447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2750] = { + [2830] = { .class_hid = BNXT_ULP_CLASS_HID_1fc28, .class_tid = 2, .hdr_sig_id = 7, @@ -57867,7 +59467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2751] = { + [2831] = { .class_hid = BNXT_ULP_CLASS_HID_1c1e8, .class_tid = 2, .hdr_sig_id = 7, @@ -57887,7 +59487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2752] = { + [2832] = { .class_hid = BNXT_ULP_CLASS_HID_1e2a8, .class_tid = 2, .hdr_sig_id = 7, @@ -57908,7 +59508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2753] = { + [2833] = { .class_hid = BNXT_ULP_CLASS_HID_9ab8, .class_tid = 2, .hdr_sig_id = 7, @@ -57924,7 +59524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2754] = { + [2834] = { .class_hid = BNXT_ULP_CLASS_HID_bc78, .class_tid = 2, .hdr_sig_id = 7, @@ -57941,7 +59541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2755] = { + [2835] = { .class_hid = BNXT_ULP_CLASS_HID_c138, .class_tid = 2, .hdr_sig_id = 7, @@ -57958,7 +59558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2756] = { + [2836] = { .class_hid = BNXT_ULP_CLASS_HID_e2f8, .class_tid = 2, .hdr_sig_id = 7, @@ -57976,7 +59576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2757] = { + [2837] = { .class_hid = BNXT_ULP_CLASS_HID_978c, .class_tid = 2, .hdr_sig_id = 7, @@ -57993,7 +59593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2758] = { + [2838] = { .class_hid = BNXT_ULP_CLASS_HID_b94c, .class_tid = 2, .hdr_sig_id = 7, @@ -58011,7 +59611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2759] = { + [2839] = { .class_hid = BNXT_ULP_CLASS_HID_da0c, .class_tid = 2, .hdr_sig_id = 7, @@ -58029,7 +59629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2760] = { + [2840] = { .class_hid = BNXT_ULP_CLASS_HID_ffcc, .class_tid = 2, .hdr_sig_id = 7, @@ -58048,7 +59648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2761] = { + [2841] = { .class_hid = BNXT_ULP_CLASS_HID_18d8c, .class_tid = 2, .hdr_sig_id = 7, @@ -58066,7 +59666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2762] = { + [2842] = { .class_hid = BNXT_ULP_CLASS_HID_1af4c, .class_tid = 2, .hdr_sig_id = 7, @@ -58085,7 +59685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2763] = { + [2843] = { .class_hid = BNXT_ULP_CLASS_HID_1f00c, .class_tid = 2, .hdr_sig_id = 7, @@ -58104,7 +59704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2764] = { + [2844] = { .class_hid = BNXT_ULP_CLASS_HID_1f5cc, .class_tid = 2, .hdr_sig_id = 7, @@ -58124,7 +59724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2765] = { + [2845] = { .class_hid = BNXT_ULP_CLASS_HID_1b0b8, .class_tid = 2, .hdr_sig_id = 7, @@ -58141,7 +59741,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2766] = { + [2846] = { .class_hid = BNXT_ULP_CLASS_HID_1b278, .class_tid = 2, .hdr_sig_id = 7, @@ -58159,7 +59759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2767] = { + [2847] = { .class_hid = BNXT_ULP_CLASS_HID_1f738, .class_tid = 2, .hdr_sig_id = 7, @@ -58177,7 +59777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2768] = { + [2848] = { .class_hid = BNXT_ULP_CLASS_HID_1f8f8, .class_tid = 2, .hdr_sig_id = 7, @@ -58196,7 +59796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2769] = { + [2849] = { .class_hid = BNXT_ULP_CLASS_HID_bf2c, .class_tid = 2, .hdr_sig_id = 7, @@ -58213,7 +59813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2770] = { + [2850] = { .class_hid = BNXT_ULP_CLASS_HID_a0ec, .class_tid = 2, .hdr_sig_id = 7, @@ -58231,7 +59831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2771] = { + [2851] = { .class_hid = BNXT_ULP_CLASS_HID_e5ac, .class_tid = 2, .hdr_sig_id = 7, @@ -58249,7 +59849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2772] = { + [2852] = { .class_hid = BNXT_ULP_CLASS_HID_e76c, .class_tid = 2, .hdr_sig_id = 7, @@ -58268,7 +59868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2773] = { + [2853] = { .class_hid = BNXT_ULP_CLASS_HID_b870, .class_tid = 2, .hdr_sig_id = 7, @@ -58286,7 +59886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2774] = { + [2854] = { .class_hid = BNXT_ULP_CLASS_HID_bd30, .class_tid = 2, .hdr_sig_id = 7, @@ -58305,7 +59905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2775] = { + [2855] = { .class_hid = BNXT_ULP_CLASS_HID_fef0, .class_tid = 2, .hdr_sig_id = 7, @@ -58324,7 +59924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2776] = { + [2856] = { .class_hid = BNXT_ULP_CLASS_HID_e3b0, .class_tid = 2, .hdr_sig_id = 7, @@ -58344,7 +59944,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2777] = { + [2857] = { .class_hid = BNXT_ULP_CLASS_HID_1ae70, .class_tid = 2, .hdr_sig_id = 7, @@ -58363,7 +59963,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2778] = { + [2858] = { .class_hid = BNXT_ULP_CLASS_HID_1f330, .class_tid = 2, .hdr_sig_id = 7, @@ -58383,7 +59983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2779] = { + [2859] = { .class_hid = BNXT_ULP_CLASS_HID_1d4f0, .class_tid = 2, .hdr_sig_id = 7, @@ -58403,7 +60003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2780] = { + [2860] = { .class_hid = BNXT_ULP_CLASS_HID_1f9b0, .class_tid = 2, .hdr_sig_id = 7, @@ -58424,7 +60024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2781] = { + [2861] = { .class_hid = BNXT_ULP_CLASS_HID_1d52c, .class_tid = 2, .hdr_sig_id = 7, @@ -58442,7 +60042,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2782] = { + [2862] = { .class_hid = BNXT_ULP_CLASS_HID_1f6ec, .class_tid = 2, .hdr_sig_id = 7, @@ -58461,7 +60061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2783] = { + [2863] = { .class_hid = BNXT_ULP_CLASS_HID_1dbac, .class_tid = 2, .hdr_sig_id = 7, @@ -58480,7 +60080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2784] = { + [2864] = { .class_hid = BNXT_ULP_CLASS_HID_1fd6c, .class_tid = 2, .hdr_sig_id = 7, @@ -58500,7 +60100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2785] = { + [2865] = { .class_hid = BNXT_ULP_CLASS_HID_34d0, .class_tid = 2, .hdr_sig_id = 7, @@ -58517,7 +60117,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2786] = { + [2866] = { .class_hid = BNXT_ULP_CLASS_HID_3a1c, .class_tid = 2, .hdr_sig_id = 7, @@ -58535,7 +60135,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2787] = { + [2867] = { + .class_hid = BNXT_ULP_CLASS_HID_3760, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2868] = { .class_hid = BNXT_ULP_CLASS_HID_5e80, .class_tid = 2, .hdr_sig_id = 7, @@ -58554,7 +60173,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2788] = { + [2869] = { + .class_hid = BNXT_ULP_CLASS_HID_5bd4, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2870] = { .class_hid = BNXT_ULP_CLASS_HID_07b8, .class_tid = 2, .hdr_sig_id = 7, @@ -58573,7 +60212,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2789] = { + [2871] = { + .class_hid = BNXT_ULP_CLASS_HID_008c, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2872] = { .class_hid = BNXT_ULP_CLASS_HID_282c, .class_tid = 2, .hdr_sig_id = 7, @@ -58593,7 +60252,46 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2790] = { + [2873] = { + .class_hid = BNXT_ULP_CLASS_HID_2570, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2874] = { + .class_hid = BNXT_ULP_CLASS_HID_3124, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2875] = { .class_hid = BNXT_ULP_CLASS_HID_5944, .class_tid = 2, .hdr_sig_id = 7, @@ -58611,7 +60309,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2791] = { + [2876] = { + .class_hid = BNXT_ULP_CLASS_HID_5588, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2877] = { .class_hid = BNXT_ULP_CLASS_HID_1e7c, .class_tid = 2, .hdr_sig_id = 7, @@ -58629,7 +60346,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2792] = { + [2878] = { + .class_hid = BNXT_ULP_CLASS_HID_1b40, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2879] = { .class_hid = BNXT_ULP_CLASS_HID_22e0, .class_tid = 2, .hdr_sig_id = 7, @@ -58648,7 +60384,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2793] = { + [2880] = { + .class_hid = BNXT_ULP_CLASS_HID_3f34, + .class_tid = 2, + .hdr_sig_id = 7, + .flow_sig_id = 244, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2881] = { .class_hid = BNXT_ULP_CLASS_HID_a77c, .class_tid = 2, .hdr_sig_id = 8, @@ -58667,7 +60423,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2794] = { + [2882] = { .class_hid = BNXT_ULP_CLASS_HID_a8bc, .class_tid = 2, .hdr_sig_id = 8, @@ -58687,7 +60443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2795] = { + [2883] = { .class_hid = BNXT_ULP_CLASS_HID_edfc, .class_tid = 2, .hdr_sig_id = 8, @@ -58707,7 +60463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2796] = { + [2884] = { .class_hid = BNXT_ULP_CLASS_HID_ef3c, .class_tid = 2, .hdr_sig_id = 8, @@ -58728,7 +60484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2797] = { + [2885] = { .class_hid = BNXT_ULP_CLASS_HID_a000, .class_tid = 2, .hdr_sig_id = 8, @@ -58748,7 +60504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2798] = { + [2886] = { .class_hid = BNXT_ULP_CLASS_HID_a540, .class_tid = 2, .hdr_sig_id = 8, @@ -58769,7 +60525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2799] = { + [2887] = { .class_hid = BNXT_ULP_CLASS_HID_e680, .class_tid = 2, .hdr_sig_id = 8, @@ -58790,7 +60546,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2800] = { + [2888] = { .class_hid = BNXT_ULP_CLASS_HID_ebc0, .class_tid = 2, .hdr_sig_id = 8, @@ -58812,7 +60568,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2801] = { + [2889] = { .class_hid = BNXT_ULP_CLASS_HID_1d600, .class_tid = 2, .hdr_sig_id = 8, @@ -58833,7 +60589,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2802] = { + [2890] = { .class_hid = BNXT_ULP_CLASS_HID_1fb40, .class_tid = 2, .hdr_sig_id = 8, @@ -58855,7 +60611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2803] = { + [2891] = { .class_hid = BNXT_ULP_CLASS_HID_1dc80, .class_tid = 2, .hdr_sig_id = 8, @@ -58877,7 +60633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2804] = { + [2892] = { .class_hid = BNXT_ULP_CLASS_HID_1e1c0, .class_tid = 2, .hdr_sig_id = 8, @@ -58900,7 +60656,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2805] = { + [2893] = { .class_hid = BNXT_ULP_CLASS_HID_1dd7c, .class_tid = 2, .hdr_sig_id = 8, @@ -58920,7 +60676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2806] = { + [2894] = { .class_hid = BNXT_ULP_CLASS_HID_1febc, .class_tid = 2, .hdr_sig_id = 8, @@ -58941,7 +60697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2807] = { + [2895] = { .class_hid = BNXT_ULP_CLASS_HID_1c3fc, .class_tid = 2, .hdr_sig_id = 8, @@ -58962,7 +60718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2808] = { + [2896] = { .class_hid = BNXT_ULP_CLASS_HID_1e53c, .class_tid = 2, .hdr_sig_id = 8, @@ -58984,7 +60740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2809] = { + [2897] = { .class_hid = BNXT_ULP_CLASS_HID_cbe0, .class_tid = 2, .hdr_sig_id = 8, @@ -59004,7 +60760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2810] = { + [2898] = { .class_hid = BNXT_ULP_CLASS_HID_b1f4, .class_tid = 2, .hdr_sig_id = 8, @@ -59025,7 +60781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2811] = { + [2899] = { .class_hid = BNXT_ULP_CLASS_HID_d334, .class_tid = 2, .hdr_sig_id = 8, @@ -59046,7 +60802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2812] = { + [2900] = { .class_hid = BNXT_ULP_CLASS_HID_f474, .class_tid = 2, .hdr_sig_id = 8, @@ -59068,7 +60824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2813] = { + [2901] = { .class_hid = BNXT_ULP_CLASS_HID_c4b4, .class_tid = 2, .hdr_sig_id = 8, @@ -59089,7 +60845,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2814] = { + [2902] = { .class_hid = BNXT_ULP_CLASS_HID_e9f4, .class_tid = 2, .hdr_sig_id = 8, @@ -59111,7 +60867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2815] = { + [2903] = { .class_hid = BNXT_ULP_CLASS_HID_cb34, .class_tid = 2, .hdr_sig_id = 8, @@ -59133,7 +60889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2816] = { + [2904] = { .class_hid = BNXT_ULP_CLASS_HID_f138, .class_tid = 2, .hdr_sig_id = 8, @@ -59156,7 +60912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2817] = { + [2905] = { .class_hid = BNXT_ULP_CLASS_HID_19f78, .class_tid = 2, .hdr_sig_id = 8, @@ -59178,7 +60934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2818] = { + [2906] = { .class_hid = BNXT_ULP_CLASS_HID_1a0b8, .class_tid = 2, .hdr_sig_id = 8, @@ -59201,7 +60957,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2819] = { + [2907] = { .class_hid = BNXT_ULP_CLASS_HID_1c5f8, .class_tid = 2, .hdr_sig_id = 8, @@ -59224,7 +60980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2820] = { + [2908] = { .class_hid = BNXT_ULP_CLASS_HID_1e738, .class_tid = 2, .hdr_sig_id = 8, @@ -59248,7 +61004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2821] = { + [2909] = { .class_hid = BNXT_ULP_CLASS_HID_182b4, .class_tid = 2, .hdr_sig_id = 8, @@ -59269,7 +61025,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2822] = { + [2910] = { .class_hid = BNXT_ULP_CLASS_HID_1a7f4, .class_tid = 2, .hdr_sig_id = 8, @@ -59291,7 +61047,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2823] = { + [2911] = { .class_hid = BNXT_ULP_CLASS_HID_1c934, .class_tid = 2, .hdr_sig_id = 8, @@ -59313,7 +61069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2824] = { + [2912] = { .class_hid = BNXT_ULP_CLASS_HID_1ea74, .class_tid = 2, .hdr_sig_id = 8, @@ -59336,7 +61092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2825] = { + [2913] = { .class_hid = BNXT_ULP_CLASS_HID_b0d8, .class_tid = 2, .hdr_sig_id = 8, @@ -59356,7 +61112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2826] = { + [2914] = { .class_hid = BNXT_ULP_CLASS_HID_b218, .class_tid = 2, .hdr_sig_id = 8, @@ -59377,7 +61133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2827] = { + [2915] = { .class_hid = BNXT_ULP_CLASS_HID_f758, .class_tid = 2, .hdr_sig_id = 8, @@ -59398,7 +61154,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2828] = { + [2916] = { .class_hid = BNXT_ULP_CLASS_HID_f898, .class_tid = 2, .hdr_sig_id = 8, @@ -59420,7 +61176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2829] = { + [2917] = { .class_hid = BNXT_ULP_CLASS_HID_8dec, .class_tid = 2, .hdr_sig_id = 8, @@ -59441,7 +61197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2830] = { + [2918] = { .class_hid = BNXT_ULP_CLASS_HID_af2c, .class_tid = 2, .hdr_sig_id = 8, @@ -59463,7 +61219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2831] = { + [2919] = { .class_hid = BNXT_ULP_CLASS_HID_f06c, .class_tid = 2, .hdr_sig_id = 8, @@ -59485,7 +61241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2832] = { + [2920] = { .class_hid = BNXT_ULP_CLASS_HID_f5ac, .class_tid = 2, .hdr_sig_id = 8, @@ -59508,7 +61264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2833] = { + [2921] = { .class_hid = BNXT_ULP_CLASS_HID_1a3ec, .class_tid = 2, .hdr_sig_id = 8, @@ -59530,7 +61286,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2834] = { + [2922] = { .class_hid = BNXT_ULP_CLASS_HID_1a52c, .class_tid = 2, .hdr_sig_id = 8, @@ -59553,7 +61309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2835] = { + [2923] = { .class_hid = BNXT_ULP_CLASS_HID_1e66c, .class_tid = 2, .hdr_sig_id = 8, @@ -59576,7 +61332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2836] = { + [2924] = { .class_hid = BNXT_ULP_CLASS_HID_1ebac, .class_tid = 2, .hdr_sig_id = 8, @@ -59600,7 +61356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2837] = { + [2925] = { .class_hid = BNXT_ULP_CLASS_HID_1a6d8, .class_tid = 2, .hdr_sig_id = 8, @@ -59621,7 +61377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2838] = { + [2926] = { .class_hid = BNXT_ULP_CLASS_HID_1a818, .class_tid = 2, .hdr_sig_id = 8, @@ -59643,7 +61399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2839] = { + [2927] = { .class_hid = BNXT_ULP_CLASS_HID_1ed58, .class_tid = 2, .hdr_sig_id = 8, @@ -59665,7 +61421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2840] = { + [2928] = { .class_hid = BNXT_ULP_CLASS_HID_1ee98, .class_tid = 2, .hdr_sig_id = 8, @@ -59688,7 +61444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2841] = { + [2929] = { .class_hid = BNXT_ULP_CLASS_HID_d54c, .class_tid = 2, .hdr_sig_id = 8, @@ -59709,7 +61465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2842] = { + [2930] = { .class_hid = BNXT_ULP_CLASS_HID_f68c, .class_tid = 2, .hdr_sig_id = 8, @@ -59731,7 +61487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2843] = { + [2931] = { .class_hid = BNXT_ULP_CLASS_HID_dbcc, .class_tid = 2, .hdr_sig_id = 8, @@ -59753,7 +61509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2844] = { + [2932] = { .class_hid = BNXT_ULP_CLASS_HID_fd0c, .class_tid = 2, .hdr_sig_id = 8, @@ -59776,7 +61532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2845] = { + [2933] = { .class_hid = BNXT_ULP_CLASS_HID_ae10, .class_tid = 2, .hdr_sig_id = 8, @@ -59798,7 +61554,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2846] = { + [2934] = { .class_hid = BNXT_ULP_CLASS_HID_f350, .class_tid = 2, .hdr_sig_id = 8, @@ -59821,7 +61577,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2847] = { + [2935] = { .class_hid = BNXT_ULP_CLASS_HID_d490, .class_tid = 2, .hdr_sig_id = 8, @@ -59844,7 +61600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2848] = { + [2936] = { .class_hid = BNXT_ULP_CLASS_HID_f9d0, .class_tid = 2, .hdr_sig_id = 8, @@ -59868,7 +61624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2849] = { + [2937] = { .class_hid = BNXT_ULP_CLASS_HID_1c410, .class_tid = 2, .hdr_sig_id = 8, @@ -59891,7 +61647,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2850] = { + [2938] = { .class_hid = BNXT_ULP_CLASS_HID_1e950, .class_tid = 2, .hdr_sig_id = 8, @@ -59915,7 +61671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2851] = { + [2939] = { .class_hid = BNXT_ULP_CLASS_HID_1ca90, .class_tid = 2, .hdr_sig_id = 8, @@ -59939,7 +61695,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2852] = { + [2940] = { .class_hid = BNXT_ULP_CLASS_HID_1f0e4, .class_tid = 2, .hdr_sig_id = 8, @@ -59964,7 +61720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2853] = { + [2941] = { .class_hid = BNXT_ULP_CLASS_HID_1cb4c, .class_tid = 2, .hdr_sig_id = 8, @@ -59986,7 +61742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2854] = { + [2942] = { .class_hid = BNXT_ULP_CLASS_HID_1b150, .class_tid = 2, .hdr_sig_id = 8, @@ -60009,7 +61765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2855] = { + [2943] = { .class_hid = BNXT_ULP_CLASS_HID_1d290, .class_tid = 2, .hdr_sig_id = 8, @@ -60032,7 +61788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2856] = { + [2944] = { .class_hid = BNXT_ULP_CLASS_HID_1f7d0, .class_tid = 2, .hdr_sig_id = 8, @@ -60056,7 +61812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2857] = { + [2945] = { .class_hid = BNXT_ULP_CLASS_HID_a1b0, .class_tid = 2, .hdr_sig_id = 8, @@ -60074,7 +61830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2858] = { + [2946] = { .class_hid = BNXT_ULP_CLASS_HID_a2f0, .class_tid = 2, .hdr_sig_id = 8, @@ -60093,7 +61849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2859] = { + [2947] = { .class_hid = BNXT_ULP_CLASS_HID_e430, .class_tid = 2, .hdr_sig_id = 8, @@ -60112,7 +61868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2860] = { + [2948] = { .class_hid = BNXT_ULP_CLASS_HID_e970, .class_tid = 2, .hdr_sig_id = 8, @@ -60132,7 +61888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2861] = { + [2949] = { .class_hid = BNXT_ULP_CLASS_HID_ba44, .class_tid = 2, .hdr_sig_id = 8, @@ -60151,7 +61907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2862] = { + [2950] = { .class_hid = BNXT_ULP_CLASS_HID_bf84, .class_tid = 2, .hdr_sig_id = 8, @@ -60171,7 +61927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2863] = { + [2951] = { .class_hid = BNXT_ULP_CLASS_HID_e0c4, .class_tid = 2, .hdr_sig_id = 8, @@ -60191,7 +61947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2864] = { + [2952] = { .class_hid = BNXT_ULP_CLASS_HID_e204, .class_tid = 2, .hdr_sig_id = 8, @@ -60212,7 +61968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2865] = { + [2953] = { .class_hid = BNXT_ULP_CLASS_HID_1d044, .class_tid = 2, .hdr_sig_id = 8, @@ -60232,7 +61988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2866] = { + [2954] = { .class_hid = BNXT_ULP_CLASS_HID_1f584, .class_tid = 2, .hdr_sig_id = 8, @@ -60253,7 +62009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2867] = { + [2955] = { .class_hid = BNXT_ULP_CLASS_HID_1d6c4, .class_tid = 2, .hdr_sig_id = 8, @@ -60274,7 +62030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2868] = { + [2956] = { .class_hid = BNXT_ULP_CLASS_HID_1f804, .class_tid = 2, .hdr_sig_id = 8, @@ -60296,7 +62052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2869] = { + [2957] = { .class_hid = BNXT_ULP_CLASS_HID_1d7b0, .class_tid = 2, .hdr_sig_id = 8, @@ -60315,7 +62071,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2870] = { + [2958] = { .class_hid = BNXT_ULP_CLASS_HID_1f8f0, .class_tid = 2, .hdr_sig_id = 8, @@ -60335,7 +62091,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2871] = { + [2959] = { .class_hid = BNXT_ULP_CLASS_HID_1da30, .class_tid = 2, .hdr_sig_id = 8, @@ -60355,7 +62111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2872] = { + [2960] = { .class_hid = BNXT_ULP_CLASS_HID_1ff70, .class_tid = 2, .hdr_sig_id = 8, @@ -60376,7 +62132,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2873] = { + [2961] = { .class_hid = BNXT_ULP_CLASS_HID_c224, .class_tid = 2, .hdr_sig_id = 8, @@ -60395,7 +62151,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2874] = { + [2962] = { .class_hid = BNXT_ULP_CLASS_HID_e764, .class_tid = 2, .hdr_sig_id = 8, @@ -60415,7 +62171,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2875] = { + [2963] = { .class_hid = BNXT_ULP_CLASS_HID_c8a4, .class_tid = 2, .hdr_sig_id = 8, @@ -60435,7 +62191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2876] = { + [2964] = { .class_hid = BNXT_ULP_CLASS_HID_ede4, .class_tid = 2, .hdr_sig_id = 8, @@ -60456,7 +62212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2877] = { + [2965] = { .class_hid = BNXT_ULP_CLASS_HID_dee8, .class_tid = 2, .hdr_sig_id = 8, @@ -60476,7 +62232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2878] = { + [2966] = { .class_hid = BNXT_ULP_CLASS_HID_e028, .class_tid = 2, .hdr_sig_id = 8, @@ -60497,7 +62253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2879] = { + [2967] = { .class_hid = BNXT_ULP_CLASS_HID_c568, .class_tid = 2, .hdr_sig_id = 8, @@ -60518,7 +62274,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2880] = { + [2968] = { .class_hid = BNXT_ULP_CLASS_HID_e6a8, .class_tid = 2, .hdr_sig_id = 8, @@ -60540,7 +62296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2881] = { + [2969] = { .class_hid = BNXT_ULP_CLASS_HID_199bc, .class_tid = 2, .hdr_sig_id = 8, @@ -60561,7 +62317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2882] = { + [2970] = { .class_hid = BNXT_ULP_CLASS_HID_1bafc, .class_tid = 2, .hdr_sig_id = 8, @@ -60583,7 +62339,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2883] = { + [2971] = { .class_hid = BNXT_ULP_CLASS_HID_1dc3c, .class_tid = 2, .hdr_sig_id = 8, @@ -60605,7 +62361,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2884] = { + [2972] = { .class_hid = BNXT_ULP_CLASS_HID_1e17c, .class_tid = 2, .hdr_sig_id = 8, @@ -60628,7 +62384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2885] = { + [2973] = { .class_hid = BNXT_ULP_CLASS_HID_19ce8, .class_tid = 2, .hdr_sig_id = 8, @@ -60648,7 +62404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2886] = { + [2974] = { .class_hid = BNXT_ULP_CLASS_HID_1be28, .class_tid = 2, .hdr_sig_id = 8, @@ -60669,7 +62425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2887] = { + [2975] = { .class_hid = BNXT_ULP_CLASS_HID_1c368, .class_tid = 2, .hdr_sig_id = 8, @@ -60690,7 +62446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2888] = { + [2976] = { .class_hid = BNXT_ULP_CLASS_HID_1e4a8, .class_tid = 2, .hdr_sig_id = 8, @@ -60712,7 +62468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2889] = { + [2977] = { .class_hid = BNXT_ULP_CLASS_HID_8b1c, .class_tid = 2, .hdr_sig_id = 8, @@ -60731,7 +62487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2890] = { + [2978] = { .class_hid = BNXT_ULP_CLASS_HID_ac5c, .class_tid = 2, .hdr_sig_id = 8, @@ -60751,7 +62507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2891] = { + [2979] = { .class_hid = BNXT_ULP_CLASS_HID_f19c, .class_tid = 2, .hdr_sig_id = 8, @@ -60771,7 +62527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2892] = { + [2980] = { .class_hid = BNXT_ULP_CLASS_HID_f2dc, .class_tid = 2, .hdr_sig_id = 8, @@ -60792,7 +62548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2893] = { + [2981] = { .class_hid = BNXT_ULP_CLASS_HID_8420, .class_tid = 2, .hdr_sig_id = 8, @@ -60812,7 +62568,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2894] = { + [2982] = { .class_hid = BNXT_ULP_CLASS_HID_a960, .class_tid = 2, .hdr_sig_id = 8, @@ -60833,7 +62589,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2895] = { + [2983] = { .class_hid = BNXT_ULP_CLASS_HID_caa0, .class_tid = 2, .hdr_sig_id = 8, @@ -60854,7 +62610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2896] = { + [2984] = { .class_hid = BNXT_ULP_CLASS_HID_efe0, .class_tid = 2, .hdr_sig_id = 8, @@ -60876,7 +62632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2897] = { + [2985] = { .class_hid = BNXT_ULP_CLASS_HID_1ba20, .class_tid = 2, .hdr_sig_id = 8, @@ -60897,7 +62653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2898] = { + [2986] = { .class_hid = BNXT_ULP_CLASS_HID_1bf60, .class_tid = 2, .hdr_sig_id = 8, @@ -60919,7 +62675,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2899] = { + [2987] = { .class_hid = BNXT_ULP_CLASS_HID_1e0a0, .class_tid = 2, .hdr_sig_id = 8, @@ -60941,7 +62697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2900] = { + [2988] = { .class_hid = BNXT_ULP_CLASS_HID_1e5e0, .class_tid = 2, .hdr_sig_id = 8, @@ -60964,7 +62720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2901] = { + [2989] = { .class_hid = BNXT_ULP_CLASS_HID_1a11c, .class_tid = 2, .hdr_sig_id = 8, @@ -60984,7 +62740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2902] = { + [2990] = { .class_hid = BNXT_ULP_CLASS_HID_1a25c, .class_tid = 2, .hdr_sig_id = 8, @@ -61005,7 +62761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2903] = { + [2991] = { .class_hid = BNXT_ULP_CLASS_HID_1e79c, .class_tid = 2, .hdr_sig_id = 8, @@ -61026,7 +62782,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2904] = { + [2992] = { .class_hid = BNXT_ULP_CLASS_HID_1e8dc, .class_tid = 2, .hdr_sig_id = 8, @@ -61048,7 +62804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2905] = { + [2993] = { .class_hid = BNXT_ULP_CLASS_HID_af80, .class_tid = 2, .hdr_sig_id = 8, @@ -61068,7 +62824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2906] = { + [2994] = { .class_hid = BNXT_ULP_CLASS_HID_f0c0, .class_tid = 2, .hdr_sig_id = 8, @@ -61089,7 +62845,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2907] = { + [2995] = { .class_hid = BNXT_ULP_CLASS_HID_d200, .class_tid = 2, .hdr_sig_id = 8, @@ -61110,7 +62866,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2908] = { + [2996] = { .class_hid = BNXT_ULP_CLASS_HID_f740, .class_tid = 2, .hdr_sig_id = 8, @@ -61132,7 +62888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2909] = { + [2997] = { .class_hid = BNXT_ULP_CLASS_HID_a854, .class_tid = 2, .hdr_sig_id = 8, @@ -61153,7 +62909,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2910] = { + [2998] = { .class_hid = BNXT_ULP_CLASS_HID_ad94, .class_tid = 2, .hdr_sig_id = 8, @@ -61175,7 +62931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2911] = { + [2999] = { .class_hid = BNXT_ULP_CLASS_HID_eed4, .class_tid = 2, .hdr_sig_id = 8, @@ -61197,7 +62953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2912] = { + [3000] = { .class_hid = BNXT_ULP_CLASS_HID_f014, .class_tid = 2, .hdr_sig_id = 8, @@ -61220,7 +62976,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2913] = { + [3001] = { .class_hid = BNXT_ULP_CLASS_HID_1de54, .class_tid = 2, .hdr_sig_id = 8, @@ -61242,7 +62998,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2914] = { + [3002] = { .class_hid = BNXT_ULP_CLASS_HID_1e394, .class_tid = 2, .hdr_sig_id = 8, @@ -61265,7 +63021,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2915] = { + [3003] = { .class_hid = BNXT_ULP_CLASS_HID_1c4d4, .class_tid = 2, .hdr_sig_id = 8, @@ -61288,7 +63044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2916] = { + [3004] = { .class_hid = BNXT_ULP_CLASS_HID_1e614, .class_tid = 2, .hdr_sig_id = 8, @@ -61312,7 +63068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2917] = { + [3005] = { .class_hid = BNXT_ULP_CLASS_HID_1c580, .class_tid = 2, .hdr_sig_id = 8, @@ -61333,7 +63089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2918] = { + [3006] = { .class_hid = BNXT_ULP_CLASS_HID_1e6c0, .class_tid = 2, .hdr_sig_id = 8, @@ -61355,7 +63111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2919] = { + [3007] = { .class_hid = BNXT_ULP_CLASS_HID_1c800, .class_tid = 2, .hdr_sig_id = 8, @@ -61377,7 +63133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2920] = { + [3008] = { .class_hid = BNXT_ULP_CLASS_HID_1ed40, .class_tid = 2, .hdr_sig_id = 8, @@ -61400,7 +63156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2921] = { + [3009] = { .class_hid = BNXT_ULP_CLASS_HID_8c6c, .class_tid = 2, .hdr_sig_id = 8, @@ -61418,7 +63174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2922] = { + [3010] = { .class_hid = BNXT_ULP_CLASS_HID_b1ac, .class_tid = 2, .hdr_sig_id = 8, @@ -61437,7 +63193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2923] = { + [3011] = { .class_hid = BNXT_ULP_CLASS_HID_f2ec, .class_tid = 2, .hdr_sig_id = 8, @@ -61456,7 +63212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2924] = { + [3012] = { .class_hid = BNXT_ULP_CLASS_HID_f42c, .class_tid = 2, .hdr_sig_id = 8, @@ -61476,7 +63232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2925] = { + [3013] = { .class_hid = BNXT_ULP_CLASS_HID_8930, .class_tid = 2, .hdr_sig_id = 8, @@ -61495,7 +63251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2926] = { + [3014] = { .class_hid = BNXT_ULP_CLASS_HID_aa70, .class_tid = 2, .hdr_sig_id = 8, @@ -61515,7 +63271,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2927] = { + [3015] = { .class_hid = BNXT_ULP_CLASS_HID_cfb0, .class_tid = 2, .hdr_sig_id = 8, @@ -61535,7 +63291,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2928] = { + [3016] = { .class_hid = BNXT_ULP_CLASS_HID_f0f0, .class_tid = 2, .hdr_sig_id = 8, @@ -61556,7 +63312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2929] = { + [3017] = { .class_hid = BNXT_ULP_CLASS_HID_1bf30, .class_tid = 2, .hdr_sig_id = 8, @@ -61576,7 +63332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2930] = { + [3018] = { .class_hid = BNXT_ULP_CLASS_HID_1a070, .class_tid = 2, .hdr_sig_id = 8, @@ -61597,7 +63353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2931] = { + [3019] = { .class_hid = BNXT_ULP_CLASS_HID_1e5b0, .class_tid = 2, .hdr_sig_id = 8, @@ -61618,7 +63374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2932] = { + [3020] = { .class_hid = BNXT_ULP_CLASS_HID_1e6f0, .class_tid = 2, .hdr_sig_id = 8, @@ -61640,7 +63396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2933] = { + [3021] = { .class_hid = BNXT_ULP_CLASS_HID_1a26c, .class_tid = 2, .hdr_sig_id = 8, @@ -61659,7 +63415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2934] = { + [3022] = { .class_hid = BNXT_ULP_CLASS_HID_1a7ac, .class_tid = 2, .hdr_sig_id = 8, @@ -61679,7 +63435,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2935] = { + [3023] = { .class_hid = BNXT_ULP_CLASS_HID_1e8ec, .class_tid = 2, .hdr_sig_id = 8, @@ -61699,7 +63455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2936] = { + [3024] = { .class_hid = BNXT_ULP_CLASS_HID_1ea2c, .class_tid = 2, .hdr_sig_id = 8, @@ -61720,7 +63476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2937] = { + [3025] = { .class_hid = BNXT_ULP_CLASS_HID_d090, .class_tid = 2, .hdr_sig_id = 8, @@ -61739,7 +63495,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2938] = { + [3026] = { .class_hid = BNXT_ULP_CLASS_HID_f5d0, .class_tid = 2, .hdr_sig_id = 8, @@ -61759,7 +63515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2939] = { + [3027] = { .class_hid = BNXT_ULP_CLASS_HID_d710, .class_tid = 2, .hdr_sig_id = 8, @@ -61779,7 +63535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2940] = { + [3028] = { .class_hid = BNXT_ULP_CLASS_HID_f850, .class_tid = 2, .hdr_sig_id = 8, @@ -61800,7 +63556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2941] = { + [3029] = { .class_hid = BNXT_ULP_CLASS_HID_ada4, .class_tid = 2, .hdr_sig_id = 8, @@ -61820,7 +63576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2942] = { + [3030] = { .class_hid = BNXT_ULP_CLASS_HID_aee4, .class_tid = 2, .hdr_sig_id = 8, @@ -61841,7 +63597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2943] = { + [3031] = { .class_hid = BNXT_ULP_CLASS_HID_d024, .class_tid = 2, .hdr_sig_id = 8, @@ -61862,7 +63618,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2944] = { + [3032] = { .class_hid = BNXT_ULP_CLASS_HID_f564, .class_tid = 2, .hdr_sig_id = 8, @@ -61884,7 +63640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2945] = { + [3033] = { .class_hid = BNXT_ULP_CLASS_HID_1c3a4, .class_tid = 2, .hdr_sig_id = 8, @@ -61905,7 +63661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2946] = { + [3034] = { .class_hid = BNXT_ULP_CLASS_HID_1e4e4, .class_tid = 2, .hdr_sig_id = 8, @@ -61927,7 +63683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2947] = { + [3035] = { .class_hid = BNXT_ULP_CLASS_HID_1c624, .class_tid = 2, .hdr_sig_id = 8, @@ -61949,7 +63705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2948] = { + [3036] = { .class_hid = BNXT_ULP_CLASS_HID_1eb64, .class_tid = 2, .hdr_sig_id = 8, @@ -61972,7 +63728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2949] = { + [3037] = { .class_hid = BNXT_ULP_CLASS_HID_1c690, .class_tid = 2, .hdr_sig_id = 8, @@ -61992,7 +63748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2950] = { + [3038] = { .class_hid = BNXT_ULP_CLASS_HID_1ebd0, .class_tid = 2, .hdr_sig_id = 8, @@ -62013,7 +63769,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2951] = { + [3039] = { .class_hid = BNXT_ULP_CLASS_HID_1cd10, .class_tid = 2, .hdr_sig_id = 8, @@ -62034,7 +63790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2952] = { + [3040] = { .class_hid = BNXT_ULP_CLASS_HID_1f364, .class_tid = 2, .hdr_sig_id = 8, @@ -62056,7 +63812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2953] = { + [3041] = { .class_hid = BNXT_ULP_CLASS_HID_99c8, .class_tid = 2, .hdr_sig_id = 8, @@ -62075,7 +63831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2954] = { + [3042] = { .class_hid = BNXT_ULP_CLASS_HID_bb08, .class_tid = 2, .hdr_sig_id = 8, @@ -62095,7 +63851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2955] = { + [3043] = { .class_hid = BNXT_ULP_CLASS_HID_dc48, .class_tid = 2, .hdr_sig_id = 8, @@ -62115,7 +63871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2956] = { + [3044] = { .class_hid = BNXT_ULP_CLASS_HID_e188, .class_tid = 2, .hdr_sig_id = 8, @@ -62136,7 +63892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2957] = { + [3045] = { .class_hid = BNXT_ULP_CLASS_HID_929c, .class_tid = 2, .hdr_sig_id = 8, @@ -62156,7 +63912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2958] = { + [3046] = { .class_hid = BNXT_ULP_CLASS_HID_b7dc, .class_tid = 2, .hdr_sig_id = 8, @@ -62177,7 +63933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2959] = { + [3047] = { .class_hid = BNXT_ULP_CLASS_HID_d91c, .class_tid = 2, .hdr_sig_id = 8, @@ -62198,7 +63954,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2960] = { + [3048] = { .class_hid = BNXT_ULP_CLASS_HID_fa5c, .class_tid = 2, .hdr_sig_id = 8, @@ -62220,7 +63976,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2961] = { + [3049] = { .class_hid = BNXT_ULP_CLASS_HID_1889c, .class_tid = 2, .hdr_sig_id = 8, @@ -62241,7 +63997,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2962] = { + [3050] = { .class_hid = BNXT_ULP_CLASS_HID_1addc, .class_tid = 2, .hdr_sig_id = 8, @@ -62263,7 +64019,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2963] = { + [3051] = { .class_hid = BNXT_ULP_CLASS_HID_1cf1c, .class_tid = 2, .hdr_sig_id = 8, @@ -62285,7 +64041,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2964] = { + [3052] = { .class_hid = BNXT_ULP_CLASS_HID_1f05c, .class_tid = 2, .hdr_sig_id = 8, @@ -62308,7 +64064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2965] = { + [3053] = { .class_hid = BNXT_ULP_CLASS_HID_18fc8, .class_tid = 2, .hdr_sig_id = 8, @@ -62328,7 +64084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2966] = { + [3054] = { .class_hid = BNXT_ULP_CLASS_HID_1b108, .class_tid = 2, .hdr_sig_id = 8, @@ -62349,7 +64105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2967] = { + [3055] = { .class_hid = BNXT_ULP_CLASS_HID_1f248, .class_tid = 2, .hdr_sig_id = 8, @@ -62370,7 +64126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2968] = { + [3056] = { .class_hid = BNXT_ULP_CLASS_HID_1f788, .class_tid = 2, .hdr_sig_id = 8, @@ -62392,7 +64148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2969] = { + [3057] = { .class_hid = BNXT_ULP_CLASS_HID_ba7c, .class_tid = 2, .hdr_sig_id = 8, @@ -62412,7 +64168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2970] = { + [3058] = { .class_hid = BNXT_ULP_CLASS_HID_bfbc, .class_tid = 2, .hdr_sig_id = 8, @@ -62433,7 +64189,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2971] = { + [3059] = { .class_hid = BNXT_ULP_CLASS_HID_e0fc, .class_tid = 2, .hdr_sig_id = 8, @@ -62454,7 +64210,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2972] = { + [3060] = { .class_hid = BNXT_ULP_CLASS_HID_e23c, .class_tid = 2, .hdr_sig_id = 8, @@ -62476,7 +64232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2973] = { + [3061] = { .class_hid = BNXT_ULP_CLASS_HID_b700, .class_tid = 2, .hdr_sig_id = 8, @@ -62497,7 +64253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2974] = { + [3062] = { .class_hid = BNXT_ULP_CLASS_HID_b840, .class_tid = 2, .hdr_sig_id = 8, @@ -62519,7 +64275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2975] = { + [3063] = { .class_hid = BNXT_ULP_CLASS_HID_fd80, .class_tid = 2, .hdr_sig_id = 8, @@ -62541,7 +64297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2976] = { + [3064] = { .class_hid = BNXT_ULP_CLASS_HID_fec0, .class_tid = 2, .hdr_sig_id = 8, @@ -62564,7 +64320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2977] = { + [3065] = { .class_hid = BNXT_ULP_CLASS_HID_1ad00, .class_tid = 2, .hdr_sig_id = 8, @@ -62586,7 +64342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2978] = { + [3066] = { .class_hid = BNXT_ULP_CLASS_HID_1ae40, .class_tid = 2, .hdr_sig_id = 8, @@ -62609,7 +64365,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2979] = { + [3067] = { .class_hid = BNXT_ULP_CLASS_HID_1d380, .class_tid = 2, .hdr_sig_id = 8, @@ -62632,7 +64388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2980] = { + [3068] = { .class_hid = BNXT_ULP_CLASS_HID_1f4c0, .class_tid = 2, .hdr_sig_id = 8, @@ -62656,7 +64412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2981] = { + [3069] = { .class_hid = BNXT_ULP_CLASS_HID_1d07c, .class_tid = 2, .hdr_sig_id = 8, @@ -62677,7 +64433,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2982] = { + [3070] = { .class_hid = BNXT_ULP_CLASS_HID_1f5bc, .class_tid = 2, .hdr_sig_id = 8, @@ -62699,7 +64455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2983] = { + [3071] = { .class_hid = BNXT_ULP_CLASS_HID_1d6fc, .class_tid = 2, .hdr_sig_id = 8, @@ -62721,7 +64477,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2984] = { + [3072] = { .class_hid = BNXT_ULP_CLASS_HID_1f83c, .class_tid = 2, .hdr_sig_id = 8, @@ -62744,7 +64500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2985] = { + [3073] = { .class_hid = BNXT_ULP_CLASS_HID_86a0, .class_tid = 2, .hdr_sig_id = 8, @@ -62761,7 +64517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2986] = { + [3074] = { .class_hid = BNXT_ULP_CLASS_HID_abe0, .class_tid = 2, .hdr_sig_id = 8, @@ -62779,7 +64535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2987] = { + [3075] = { .class_hid = BNXT_ULP_CLASS_HID_cd20, .class_tid = 2, .hdr_sig_id = 8, @@ -62797,7 +64553,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2988] = { + [3076] = { .class_hid = BNXT_ULP_CLASS_HID_ee60, .class_tid = 2, .hdr_sig_id = 8, @@ -62816,7 +64572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2989] = { + [3077] = { .class_hid = BNXT_ULP_CLASS_HID_8374, .class_tid = 2, .hdr_sig_id = 8, @@ -62834,7 +64590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2990] = { + [3078] = { .class_hid = BNXT_ULP_CLASS_HID_a4b4, .class_tid = 2, .hdr_sig_id = 8, @@ -62853,7 +64609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2991] = { + [3079] = { .class_hid = BNXT_ULP_CLASS_HID_c9f4, .class_tid = 2, .hdr_sig_id = 8, @@ -62872,7 +64628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2992] = { + [3080] = { .class_hid = BNXT_ULP_CLASS_HID_eb34, .class_tid = 2, .hdr_sig_id = 8, @@ -62892,7 +64648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2993] = { + [3081] = { .class_hid = BNXT_ULP_CLASS_HID_1b974, .class_tid = 2, .hdr_sig_id = 8, @@ -62911,7 +64667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2994] = { + [3082] = { .class_hid = BNXT_ULP_CLASS_HID_1bab4, .class_tid = 2, .hdr_sig_id = 8, @@ -62931,7 +64687,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2995] = { + [3083] = { .class_hid = BNXT_ULP_CLASS_HID_1fff4, .class_tid = 2, .hdr_sig_id = 8, @@ -62951,7 +64707,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2996] = { + [3084] = { .class_hid = BNXT_ULP_CLASS_HID_1e134, .class_tid = 2, .hdr_sig_id = 8, @@ -62972,7 +64728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2997] = { + [3085] = { .class_hid = BNXT_ULP_CLASS_HID_1bca0, .class_tid = 2, .hdr_sig_id = 8, @@ -62990,7 +64746,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2998] = { + [3086] = { .class_hid = BNXT_ULP_CLASS_HID_1a1e0, .class_tid = 2, .hdr_sig_id = 8, @@ -63009,7 +64765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2999] = { + [3087] = { .class_hid = BNXT_ULP_CLASS_HID_1e320, .class_tid = 2, .hdr_sig_id = 8, @@ -63028,7 +64784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3000] = { + [3088] = { .class_hid = BNXT_ULP_CLASS_HID_1e460, .class_tid = 2, .hdr_sig_id = 8, @@ -63048,7 +64804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3001] = { + [3089] = { .class_hid = BNXT_ULP_CLASS_HID_aad4, .class_tid = 2, .hdr_sig_id = 8, @@ -63066,7 +64822,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3002] = { + [3090] = { .class_hid = BNXT_ULP_CLASS_HID_ac14, .class_tid = 2, .hdr_sig_id = 8, @@ -63085,7 +64841,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3003] = { + [3091] = { .class_hid = BNXT_ULP_CLASS_HID_d154, .class_tid = 2, .hdr_sig_id = 8, @@ -63104,7 +64860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3004] = { + [3092] = { .class_hid = BNXT_ULP_CLASS_HID_f294, .class_tid = 2, .hdr_sig_id = 8, @@ -63124,7 +64880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3005] = { + [3093] = { .class_hid = BNXT_ULP_CLASS_HID_a798, .class_tid = 2, .hdr_sig_id = 8, @@ -63143,7 +64899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3006] = { + [3094] = { .class_hid = BNXT_ULP_CLASS_HID_a8d8, .class_tid = 2, .hdr_sig_id = 8, @@ -63163,7 +64919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3007] = { + [3095] = { .class_hid = BNXT_ULP_CLASS_HID_ea18, .class_tid = 2, .hdr_sig_id = 8, @@ -63183,7 +64939,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3008] = { + [3096] = { .class_hid = BNXT_ULP_CLASS_HID_ef58, .class_tid = 2, .hdr_sig_id = 8, @@ -63204,7 +64960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3009] = { + [3097] = { .class_hid = BNXT_ULP_CLASS_HID_1dd98, .class_tid = 2, .hdr_sig_id = 8, @@ -63224,7 +64980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3010] = { + [3098] = { .class_hid = BNXT_ULP_CLASS_HID_1fed8, .class_tid = 2, .hdr_sig_id = 8, @@ -63245,7 +65001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3011] = { + [3099] = { .class_hid = BNXT_ULP_CLASS_HID_1c018, .class_tid = 2, .hdr_sig_id = 8, @@ -63266,7 +65022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3012] = { + [3100] = { .class_hid = BNXT_ULP_CLASS_HID_1e558, .class_tid = 2, .hdr_sig_id = 8, @@ -63288,7 +65044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3013] = { + [3101] = { .class_hid = BNXT_ULP_CLASS_HID_1c0d4, .class_tid = 2, .hdr_sig_id = 8, @@ -63307,7 +65063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3014] = { + [3102] = { .class_hid = BNXT_ULP_CLASS_HID_1e214, .class_tid = 2, .hdr_sig_id = 8, @@ -63327,7 +65083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3015] = { + [3103] = { .class_hid = BNXT_ULP_CLASS_HID_1c754, .class_tid = 2, .hdr_sig_id = 8, @@ -63347,7 +65103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3016] = { + [3104] = { .class_hid = BNXT_ULP_CLASS_HID_1e894, .class_tid = 2, .hdr_sig_id = 8, @@ -63368,7 +65124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3017] = { + [3105] = { .class_hid = BNXT_ULP_CLASS_HID_900c, .class_tid = 2, .hdr_sig_id = 8, @@ -63386,7 +65142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3018] = { + [3106] = { .class_hid = BNXT_ULP_CLASS_HID_b54c, .class_tid = 2, .hdr_sig_id = 8, @@ -63405,7 +65161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3019] = { + [3107] = { .class_hid = BNXT_ULP_CLASS_HID_d68c, .class_tid = 2, .hdr_sig_id = 8, @@ -63424,7 +65180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3020] = { + [3108] = { .class_hid = BNXT_ULP_CLASS_HID_fbcc, .class_tid = 2, .hdr_sig_id = 8, @@ -63444,7 +65200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3021] = { + [3109] = { .class_hid = BNXT_ULP_CLASS_HID_c80c, .class_tid = 2, .hdr_sig_id = 8, @@ -63463,7 +65219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3022] = { + [3110] = { .class_hid = BNXT_ULP_CLASS_HID_ed4c, .class_tid = 2, .hdr_sig_id = 8, @@ -63483,7 +65239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3023] = { + [3111] = { .class_hid = BNXT_ULP_CLASS_HID_d350, .class_tid = 2, .hdr_sig_id = 8, @@ -63503,7 +65259,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3024] = { + [3112] = { .class_hid = BNXT_ULP_CLASS_HID_f490, .class_tid = 2, .hdr_sig_id = 8, @@ -63524,7 +65280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3025] = { + [3113] = { .class_hid = BNXT_ULP_CLASS_HID_182d0, .class_tid = 2, .hdr_sig_id = 8, @@ -63544,7 +65300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3026] = { + [3114] = { .class_hid = BNXT_ULP_CLASS_HID_1a410, .class_tid = 2, .hdr_sig_id = 8, @@ -63565,7 +65321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3027] = { + [3115] = { .class_hid = BNXT_ULP_CLASS_HID_1c950, .class_tid = 2, .hdr_sig_id = 8, @@ -63586,7 +65342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3028] = { + [3116] = { .class_hid = BNXT_ULP_CLASS_HID_1ea90, .class_tid = 2, .hdr_sig_id = 8, @@ -63608,7 +65364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3029] = { + [3117] = { .class_hid = BNXT_ULP_CLASS_HID_1860c, .class_tid = 2, .hdr_sig_id = 8, @@ -63627,7 +65383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3030] = { + [3118] = { .class_hid = BNXT_ULP_CLASS_HID_1ab4c, .class_tid = 2, .hdr_sig_id = 8, @@ -63647,7 +65403,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3031] = { + [3119] = { .class_hid = BNXT_ULP_CLASS_HID_1cc8c, .class_tid = 2, .hdr_sig_id = 8, @@ -63667,7 +65423,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3032] = { + [3120] = { .class_hid = BNXT_ULP_CLASS_HID_1f1cc, .class_tid = 2, .hdr_sig_id = 8, @@ -63688,7 +65444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3033] = { + [3121] = { .class_hid = BNXT_ULP_CLASS_HID_b4b0, .class_tid = 2, .hdr_sig_id = 8, @@ -63707,7 +65463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3034] = { + [3122] = { .class_hid = BNXT_ULP_CLASS_HID_b9f0, .class_tid = 2, .hdr_sig_id = 8, @@ -63727,7 +65483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3035] = { + [3123] = { .class_hid = BNXT_ULP_CLASS_HID_fb30, .class_tid = 2, .hdr_sig_id = 8, @@ -63747,7 +65503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3036] = { + [3124] = { .class_hid = BNXT_ULP_CLASS_HID_fc70, .class_tid = 2, .hdr_sig_id = 8, @@ -63768,7 +65524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3037] = { + [3125] = { .class_hid = BNXT_ULP_CLASS_HID_b144, .class_tid = 2, .hdr_sig_id = 8, @@ -63788,7 +65544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3038] = { + [3126] = { .class_hid = BNXT_ULP_CLASS_HID_b284, .class_tid = 2, .hdr_sig_id = 8, @@ -63809,7 +65565,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3039] = { + [3127] = { .class_hid = BNXT_ULP_CLASS_HID_f7c4, .class_tid = 2, .hdr_sig_id = 8, @@ -63830,7 +65586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3040] = { + [3128] = { .class_hid = BNXT_ULP_CLASS_HID_f904, .class_tid = 2, .hdr_sig_id = 8, @@ -63852,7 +65608,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3041] = { + [3129] = { .class_hid = BNXT_ULP_CLASS_HID_1a744, .class_tid = 2, .hdr_sig_id = 8, @@ -63873,7 +65629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3042] = { + [3130] = { .class_hid = BNXT_ULP_CLASS_HID_1a884, .class_tid = 2, .hdr_sig_id = 8, @@ -63895,7 +65651,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3043] = { + [3131] = { .class_hid = BNXT_ULP_CLASS_HID_1edc4, .class_tid = 2, .hdr_sig_id = 8, @@ -63917,7 +65673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3044] = { + [3132] = { .class_hid = BNXT_ULP_CLASS_HID_1ef04, .class_tid = 2, .hdr_sig_id = 8, @@ -63940,7 +65696,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3045] = { + [3133] = { .class_hid = BNXT_ULP_CLASS_HID_1aab0, .class_tid = 2, .hdr_sig_id = 8, @@ -63960,7 +65716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3046] = { + [3134] = { .class_hid = BNXT_ULP_CLASS_HID_1aff0, .class_tid = 2, .hdr_sig_id = 8, @@ -63981,7 +65737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3047] = { + [3135] = { .class_hid = BNXT_ULP_CLASS_HID_1d130, .class_tid = 2, .hdr_sig_id = 8, @@ -64002,7 +65758,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3048] = { + [3136] = { .class_hid = BNXT_ULP_CLASS_HID_1f270, .class_tid = 2, .hdr_sig_id = 8, @@ -64024,7 +65780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3049] = { + [3137] = { .class_hid = BNXT_ULP_CLASS_HID_80e4, .class_tid = 2, .hdr_sig_id = 8, @@ -64041,7 +65797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3050] = { + [3138] = { .class_hid = BNXT_ULP_CLASS_HID_a224, .class_tid = 2, .hdr_sig_id = 8, @@ -64059,7 +65815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3051] = { + [3139] = { .class_hid = BNXT_ULP_CLASS_HID_c764, .class_tid = 2, .hdr_sig_id = 8, @@ -64077,7 +65833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3052] = { + [3140] = { .class_hid = BNXT_ULP_CLASS_HID_e8a4, .class_tid = 2, .hdr_sig_id = 8, @@ -64096,7 +65852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3053] = { + [3141] = { .class_hid = BNXT_ULP_CLASS_HID_9da8, .class_tid = 2, .hdr_sig_id = 8, @@ -64114,7 +65870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3054] = { + [3142] = { .class_hid = BNXT_ULP_CLASS_HID_bee8, .class_tid = 2, .hdr_sig_id = 8, @@ -64133,7 +65889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3055] = { + [3143] = { .class_hid = BNXT_ULP_CLASS_HID_c028, .class_tid = 2, .hdr_sig_id = 8, @@ -64152,7 +65908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3056] = { + [3144] = { .class_hid = BNXT_ULP_CLASS_HID_e568, .class_tid = 2, .hdr_sig_id = 8, @@ -64172,7 +65928,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3057] = { + [3145] = { .class_hid = BNXT_ULP_CLASS_HID_1b3a8, .class_tid = 2, .hdr_sig_id = 8, @@ -64191,7 +65947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3058] = { + [3146] = { .class_hid = BNXT_ULP_CLASS_HID_1b4e8, .class_tid = 2, .hdr_sig_id = 8, @@ -64211,7 +65967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3059] = { + [3147] = { .class_hid = BNXT_ULP_CLASS_HID_1f628, .class_tid = 2, .hdr_sig_id = 8, @@ -64231,7 +65987,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3060] = { + [3148] = { .class_hid = BNXT_ULP_CLASS_HID_1fb68, .class_tid = 2, .hdr_sig_id = 8, @@ -64252,7 +66008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3061] = { + [3149] = { .class_hid = BNXT_ULP_CLASS_HID_1b6e4, .class_tid = 2, .hdr_sig_id = 8, @@ -64270,7 +66026,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3062] = { + [3150] = { .class_hid = BNXT_ULP_CLASS_HID_1b824, .class_tid = 2, .hdr_sig_id = 8, @@ -64289,7 +66045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3063] = { + [3151] = { .class_hid = BNXT_ULP_CLASS_HID_1fd64, .class_tid = 2, .hdr_sig_id = 8, @@ -64308,7 +66064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3064] = { + [3152] = { .class_hid = BNXT_ULP_CLASS_HID_1fea4, .class_tid = 2, .hdr_sig_id = 8, @@ -64328,7 +66084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3065] = { + [3153] = { .class_hid = BNXT_ULP_CLASS_HID_a508, .class_tid = 2, .hdr_sig_id = 8, @@ -64346,7 +66102,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3066] = { + [3154] = { .class_hid = BNXT_ULP_CLASS_HID_a648, .class_tid = 2, .hdr_sig_id = 8, @@ -64365,7 +66121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3067] = { + [3155] = { .class_hid = BNXT_ULP_CLASS_HID_eb88, .class_tid = 2, .hdr_sig_id = 8, @@ -64384,7 +66140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3068] = { + [3156] = { .class_hid = BNXT_ULP_CLASS_HID_ecc8, .class_tid = 2, .hdr_sig_id = 8, @@ -64404,7 +66160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3069] = { + [3157] = { .class_hid = BNXT_ULP_CLASS_HID_a1dc, .class_tid = 2, .hdr_sig_id = 8, @@ -64423,7 +66179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3070] = { + [3158] = { .class_hid = BNXT_ULP_CLASS_HID_a31c, .class_tid = 2, .hdr_sig_id = 8, @@ -64443,7 +66199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3071] = { + [3159] = { .class_hid = BNXT_ULP_CLASS_HID_e45c, .class_tid = 2, .hdr_sig_id = 8, @@ -64463,7 +66219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3072] = { + [3160] = { .class_hid = BNXT_ULP_CLASS_HID_e99c, .class_tid = 2, .hdr_sig_id = 8, @@ -64484,7 +66240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3073] = { + [3161] = { .class_hid = BNXT_ULP_CLASS_HID_1d7dc, .class_tid = 2, .hdr_sig_id = 8, @@ -64504,7 +66260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3074] = { + [3162] = { .class_hid = BNXT_ULP_CLASS_HID_1f91c, .class_tid = 2, .hdr_sig_id = 8, @@ -64525,7 +66281,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3075] = { + [3163] = { .class_hid = BNXT_ULP_CLASS_HID_1da5c, .class_tid = 2, .hdr_sig_id = 8, @@ -64546,7 +66302,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3076] = { + [3164] = { .class_hid = BNXT_ULP_CLASS_HID_1ff9c, .class_tid = 2, .hdr_sig_id = 8, @@ -64568,7 +66324,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3077] = { + [3165] = { .class_hid = BNXT_ULP_CLASS_HID_1db08, .class_tid = 2, .hdr_sig_id = 8, @@ -64587,7 +66343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3078] = { + [3166] = { .class_hid = BNXT_ULP_CLASS_HID_1fc48, .class_tid = 2, .hdr_sig_id = 8, @@ -64607,7 +66363,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3079] = { + [3167] = { .class_hid = BNXT_ULP_CLASS_HID_1c188, .class_tid = 2, .hdr_sig_id = 8, @@ -64627,7 +66383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3080] = { + [3168] = { .class_hid = BNXT_ULP_CLASS_HID_1e2c8, .class_tid = 2, .hdr_sig_id = 8, @@ -64648,7 +66404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3081] = { + [3169] = { .class_hid = BNXT_ULP_CLASS_HID_9ad8, .class_tid = 2, .hdr_sig_id = 8, @@ -64664,7 +66420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3082] = { + [3170] = { .class_hid = BNXT_ULP_CLASS_HID_bc18, .class_tid = 2, .hdr_sig_id = 8, @@ -64681,7 +66437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3083] = { + [3171] = { .class_hid = BNXT_ULP_CLASS_HID_c158, .class_tid = 2, .hdr_sig_id = 8, @@ -64698,7 +66454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3084] = { + [3172] = { .class_hid = BNXT_ULP_CLASS_HID_e298, .class_tid = 2, .hdr_sig_id = 8, @@ -64716,7 +66472,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3085] = { + [3173] = { .class_hid = BNXT_ULP_CLASS_HID_97ec, .class_tid = 2, .hdr_sig_id = 8, @@ -64733,7 +66489,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3086] = { + [3174] = { .class_hid = BNXT_ULP_CLASS_HID_b92c, .class_tid = 2, .hdr_sig_id = 8, @@ -64751,7 +66507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3087] = { + [3175] = { .class_hid = BNXT_ULP_CLASS_HID_da6c, .class_tid = 2, .hdr_sig_id = 8, @@ -64769,7 +66525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3088] = { + [3176] = { .class_hid = BNXT_ULP_CLASS_HID_ffac, .class_tid = 2, .hdr_sig_id = 8, @@ -64788,7 +66544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3089] = { + [3177] = { .class_hid = BNXT_ULP_CLASS_HID_18dec, .class_tid = 2, .hdr_sig_id = 8, @@ -64806,7 +66562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3090] = { + [3178] = { .class_hid = BNXT_ULP_CLASS_HID_1af2c, .class_tid = 2, .hdr_sig_id = 8, @@ -64825,7 +66581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3091] = { + [3179] = { .class_hid = BNXT_ULP_CLASS_HID_1f06c, .class_tid = 2, .hdr_sig_id = 8, @@ -64844,7 +66600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3092] = { + [3180] = { .class_hid = BNXT_ULP_CLASS_HID_1f5ac, .class_tid = 2, .hdr_sig_id = 8, @@ -64864,7 +66620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3093] = { + [3181] = { .class_hid = BNXT_ULP_CLASS_HID_1b0d8, .class_tid = 2, .hdr_sig_id = 8, @@ -64881,7 +66637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3094] = { + [3182] = { .class_hid = BNXT_ULP_CLASS_HID_1b218, .class_tid = 2, .hdr_sig_id = 8, @@ -64899,7 +66655,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3095] = { + [3183] = { .class_hid = BNXT_ULP_CLASS_HID_1f758, .class_tid = 2, .hdr_sig_id = 8, @@ -64917,7 +66673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3096] = { + [3184] = { .class_hid = BNXT_ULP_CLASS_HID_1f898, .class_tid = 2, .hdr_sig_id = 8, @@ -64936,7 +66692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3097] = { + [3185] = { .class_hid = BNXT_ULP_CLASS_HID_bf4c, .class_tid = 2, .hdr_sig_id = 8, @@ -64953,7 +66709,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3098] = { + [3186] = { .class_hid = BNXT_ULP_CLASS_HID_a08c, .class_tid = 2, .hdr_sig_id = 8, @@ -64971,7 +66727,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3099] = { + [3187] = { .class_hid = BNXT_ULP_CLASS_HID_e5cc, .class_tid = 2, .hdr_sig_id = 8, @@ -64989,7 +66745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3100] = { + [3188] = { .class_hid = BNXT_ULP_CLASS_HID_e70c, .class_tid = 2, .hdr_sig_id = 8, @@ -65008,7 +66764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3101] = { + [3189] = { .class_hid = BNXT_ULP_CLASS_HID_b810, .class_tid = 2, .hdr_sig_id = 8, @@ -65026,7 +66782,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3102] = { + [3190] = { .class_hid = BNXT_ULP_CLASS_HID_bd50, .class_tid = 2, .hdr_sig_id = 8, @@ -65045,7 +66801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3103] = { + [3191] = { .class_hid = BNXT_ULP_CLASS_HID_fe90, .class_tid = 2, .hdr_sig_id = 8, @@ -65064,7 +66820,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3104] = { + [3192] = { .class_hid = BNXT_ULP_CLASS_HID_e3d0, .class_tid = 2, .hdr_sig_id = 8, @@ -65084,7 +66840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3105] = { + [3193] = { .class_hid = BNXT_ULP_CLASS_HID_1ae10, .class_tid = 2, .hdr_sig_id = 8, @@ -65103,7 +66859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3106] = { + [3194] = { .class_hid = BNXT_ULP_CLASS_HID_1f350, .class_tid = 2, .hdr_sig_id = 8, @@ -65123,7 +66879,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3107] = { + [3195] = { .class_hid = BNXT_ULP_CLASS_HID_1d490, .class_tid = 2, .hdr_sig_id = 8, @@ -65143,7 +66899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3108] = { + [3196] = { .class_hid = BNXT_ULP_CLASS_HID_1f9d0, .class_tid = 2, .hdr_sig_id = 8, @@ -65164,7 +66920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3109] = { + [3197] = { .class_hid = BNXT_ULP_CLASS_HID_1d54c, .class_tid = 2, .hdr_sig_id = 8, @@ -65182,7 +66938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3110] = { + [3198] = { .class_hid = BNXT_ULP_CLASS_HID_1f68c, .class_tid = 2, .hdr_sig_id = 8, @@ -65201,7 +66957,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3111] = { + [3199] = { .class_hid = BNXT_ULP_CLASS_HID_1dbcc, .class_tid = 2, .hdr_sig_id = 8, @@ -65220,7 +66976,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3112] = { + [3200] = { .class_hid = BNXT_ULP_CLASS_HID_1fd0c, .class_tid = 2, .hdr_sig_id = 8, @@ -65240,7 +66996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3113] = { + [3201] = { .class_hid = BNXT_ULP_CLASS_HID_34b0, .class_tid = 2, .hdr_sig_id = 8, @@ -65257,7 +67013,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3114] = { + [3202] = { .class_hid = BNXT_ULP_CLASS_HID_3a7c, .class_tid = 2, .hdr_sig_id = 8, @@ -65275,7 +67031,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3115] = { + [3203] = { + .class_hid = BNXT_ULP_CLASS_HID_3700, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3204] = { .class_hid = BNXT_ULP_CLASS_HID_5ee0, .class_tid = 2, .hdr_sig_id = 8, @@ -65294,7 +67069,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3116] = { + [3205] = { + .class_hid = BNXT_ULP_CLASS_HID_5bb4, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3206] = { .class_hid = BNXT_ULP_CLASS_HID_07d8, .class_tid = 2, .hdr_sig_id = 8, @@ -65313,7 +67108,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3117] = { + [3207] = { + .class_hid = BNXT_ULP_CLASS_HID_00ec, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3208] = { .class_hid = BNXT_ULP_CLASS_HID_284c, .class_tid = 2, .hdr_sig_id = 8, @@ -65333,7 +67148,46 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3118] = { + [3209] = { + .class_hid = BNXT_ULP_CLASS_HID_2510, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3210] = { + .class_hid = BNXT_ULP_CLASS_HID_3144, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3211] = { .class_hid = BNXT_ULP_CLASS_HID_5924, .class_tid = 2, .hdr_sig_id = 8, @@ -65351,7 +67205,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3119] = { + [3212] = { + .class_hid = BNXT_ULP_CLASS_HID_55e8, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3213] = { .class_hid = BNXT_ULP_CLASS_HID_1e1c, .class_tid = 2, .hdr_sig_id = 8, @@ -65369,7 +67242,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3120] = { + [3214] = { + .class_hid = BNXT_ULP_CLASS_HID_1b20, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3215] = { .class_hid = BNXT_ULP_CLASS_HID_2280, .class_tid = 2, .hdr_sig_id = 8, @@ -65388,7 +67280,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3121] = { + [3216] = { + .class_hid = BNXT_ULP_CLASS_HID_3f54, + .class_tid = 2, + .hdr_sig_id = 8, + .flow_sig_id = 256, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3217] = { .class_hid = BNXT_ULP_CLASS_HID_24604, .class_tid = 2, .hdr_sig_id = 9, @@ -65406,7 +67318,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3122] = { + [3218] = { .class_hid = BNXT_ULP_CLASS_HID_255d4, .class_tid = 2, .hdr_sig_id = 9, @@ -65425,7 +67337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3123] = { + [3219] = { .class_hid = BNXT_ULP_CLASS_HID_22e08, .class_tid = 2, .hdr_sig_id = 9, @@ -65445,7 +67357,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3124] = { + [3220] = { .class_hid = BNXT_ULP_CLASS_HID_24378, .class_tid = 2, .hdr_sig_id = 9, @@ -65464,7 +67376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3125] = { + [3221] = { .class_hid = BNXT_ULP_CLASS_HID_20fcc, .class_tid = 2, .hdr_sig_id = 9, @@ -65483,7 +67395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3126] = { + [3222] = { .class_hid = BNXT_ULP_CLASS_HID_21a9c, .class_tid = 2, .hdr_sig_id = 9, @@ -65503,7 +67415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3127] = { + [3223] = { .class_hid = BNXT_ULP_CLASS_HID_217d0, .class_tid = 2, .hdr_sig_id = 9, @@ -65524,7 +67436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3128] = { + [3224] = { .class_hid = BNXT_ULP_CLASS_HID_20800, .class_tid = 2, .hdr_sig_id = 9, @@ -65544,7 +67456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3129] = { + [3225] = { .class_hid = BNXT_ULP_CLASS_HID_253a0, .class_tid = 2, .hdr_sig_id = 9, @@ -65563,7 +67475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3130] = { + [3226] = { .class_hid = BNXT_ULP_CLASS_HID_23f70, .class_tid = 2, .hdr_sig_id = 9, @@ -65583,7 +67495,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3131] = { + [3227] = { .class_hid = BNXT_ULP_CLASS_HID_23ba4, .class_tid = 2, .hdr_sig_id = 9, @@ -65604,7 +67516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3132] = { + [3228] = { .class_hid = BNXT_ULP_CLASS_HID_22c94, .class_tid = 2, .hdr_sig_id = 9, @@ -65624,7 +67536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3133] = { + [3229] = { .class_hid = BNXT_ULP_CLASS_HID_21968, .class_tid = 2, .hdr_sig_id = 9, @@ -65644,7 +67556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3134] = { + [3230] = { .class_hid = BNXT_ULP_CLASS_HID_243c4, .class_tid = 2, .hdr_sig_id = 9, @@ -65665,7 +67577,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3135] = { + [3231] = { .class_hid = BNXT_ULP_CLASS_HID_25c38, .class_tid = 2, .hdr_sig_id = 9, @@ -65687,7 +67599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3136] = { + [3232] = { .class_hid = BNXT_ULP_CLASS_HID_2125c, .class_tid = 2, .hdr_sig_id = 9, @@ -65708,7 +67620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3137] = { + [3233] = { .class_hid = BNXT_ULP_CLASS_HID_240c8, .class_tid = 2, .hdr_sig_id = 9, @@ -65725,7 +67637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3138] = { + [3234] = { .class_hid = BNXT_ULP_CLASS_HID_22f98, .class_tid = 2, .hdr_sig_id = 9, @@ -65743,7 +67655,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3139] = { + [3235] = { .class_hid = BNXT_ULP_CLASS_HID_228cc, .class_tid = 2, .hdr_sig_id = 9, @@ -65762,7 +67674,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3140] = { + [3236] = { .class_hid = BNXT_ULP_CLASS_HID_25d3c, .class_tid = 2, .hdr_sig_id = 9, @@ -65780,7 +67692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3141] = { + [3237] = { .class_hid = BNXT_ULP_CLASS_HID_20990, .class_tid = 2, .hdr_sig_id = 9, @@ -65798,7 +67710,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3142] = { + [3238] = { .class_hid = BNXT_ULP_CLASS_HID_214a0, .class_tid = 2, .hdr_sig_id = 9, @@ -65817,7 +67729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3143] = { + [3239] = { .class_hid = BNXT_ULP_CLASS_HID_21194, .class_tid = 2, .hdr_sig_id = 9, @@ -65837,7 +67749,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3144] = { + [3240] = { .class_hid = BNXT_ULP_CLASS_HID_202c4, .class_tid = 2, .hdr_sig_id = 9, @@ -65856,7 +67768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3145] = { + [3241] = { .class_hid = BNXT_ULP_CLASS_HID_22a64, .class_tid = 2, .hdr_sig_id = 9, @@ -65874,7 +67786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3146] = { + [3242] = { .class_hid = BNXT_ULP_CLASS_HID_23934, .class_tid = 2, .hdr_sig_id = 9, @@ -65893,7 +67805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3147] = { + [3243] = { .class_hid = BNXT_ULP_CLASS_HID_23268, .class_tid = 2, .hdr_sig_id = 9, @@ -65913,7 +67825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3148] = { + [3244] = { .class_hid = BNXT_ULP_CLASS_HID_22758, .class_tid = 2, .hdr_sig_id = 9, @@ -65932,7 +67844,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3149] = { + [3245] = { .class_hid = BNXT_ULP_CLASS_HID_2132c, .class_tid = 2, .hdr_sig_id = 9, @@ -65951,7 +67863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3150] = { + [3246] = { .class_hid = BNXT_ULP_CLASS_HID_25d88, .class_tid = 2, .hdr_sig_id = 9, @@ -65971,7 +67883,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3151] = { + [3247] = { .class_hid = BNXT_ULP_CLASS_HID_256fc, .class_tid = 2, .hdr_sig_id = 9, @@ -65992,7 +67904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3152] = { + [3248] = { .class_hid = BNXT_ULP_CLASS_HID_24b2c, .class_tid = 2, .hdr_sig_id = 9, @@ -66012,7 +67924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3153] = { + [3249] = { .class_hid = BNXT_ULP_CLASS_HID_22f14, .class_tid = 2, .hdr_sig_id = 9, @@ -66029,7 +67941,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3154] = { + [3250] = { .class_hid = BNXT_ULP_CLASS_HID_23a24, .class_tid = 2, .hdr_sig_id = 9, @@ -66047,7 +67959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3155] = { + [3251] = { .class_hid = BNXT_ULP_CLASS_HID_23718, .class_tid = 2, .hdr_sig_id = 9, @@ -66066,7 +67978,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3156] = { + [3252] = { .class_hid = BNXT_ULP_CLASS_HID_22848, .class_tid = 2, .hdr_sig_id = 9, @@ -66084,7 +67996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3157] = { + [3253] = { .class_hid = BNXT_ULP_CLASS_HID_214dc, .class_tid = 2, .hdr_sig_id = 9, @@ -66102,7 +68014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3158] = { + [3254] = { .class_hid = BNXT_ULP_CLASS_HID_25eb8, .class_tid = 2, .hdr_sig_id = 9, @@ -66121,7 +68033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3159] = { + [3255] = { .class_hid = BNXT_ULP_CLASS_HID_25bec, .class_tid = 2, .hdr_sig_id = 9, @@ -66141,7 +68053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3160] = { + [3256] = { .class_hid = BNXT_ULP_CLASS_HID_21110, .class_tid = 2, .hdr_sig_id = 9, @@ -66160,7 +68072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3161] = { + [3257] = { .class_hid = BNXT_ULP_CLASS_HID_238b0, .class_tid = 2, .hdr_sig_id = 9, @@ -66178,7 +68090,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3162] = { + [3258] = { .class_hid = BNXT_ULP_CLASS_HID_20440, .class_tid = 2, .hdr_sig_id = 9, @@ -66197,7 +68109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3163] = { + [3259] = { .class_hid = BNXT_ULP_CLASS_HID_200b4, .class_tid = 2, .hdr_sig_id = 9, @@ -66217,7 +68129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3164] = { + [3260] = { .class_hid = BNXT_ULP_CLASS_HID_235e4, .class_tid = 2, .hdr_sig_id = 9, @@ -66236,7 +68148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3165] = { + [3261] = { .class_hid = BNXT_ULP_CLASS_HID_25d04, .class_tid = 2, .hdr_sig_id = 9, @@ -66255,7 +68167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3166] = { + [3262] = { .class_hid = BNXT_ULP_CLASS_HID_228d4, .class_tid = 2, .hdr_sig_id = 9, @@ -66275,7 +68187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3167] = { + [3263] = { .class_hid = BNXT_ULP_CLASS_HID_22508, .class_tid = 2, .hdr_sig_id = 9, @@ -66296,7 +68208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3168] = { + [3264] = { .class_hid = BNXT_ULP_CLASS_HID_25678, .class_tid = 2, .hdr_sig_id = 9, @@ -66316,7 +68228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3169] = { + [3265] = { .class_hid = BNXT_ULP_CLASS_HID_229d8, .class_tid = 2, .hdr_sig_id = 9, @@ -66332,7 +68244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3170] = { + [3266] = { .class_hid = BNXT_ULP_CLASS_HID_234e8, .class_tid = 2, .hdr_sig_id = 9, @@ -66349,7 +68261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3171] = { + [3267] = { .class_hid = BNXT_ULP_CLASS_HID_231dc, .class_tid = 2, .hdr_sig_id = 9, @@ -66367,7 +68279,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3172] = { + [3268] = { .class_hid = BNXT_ULP_CLASS_HID_2220c, .class_tid = 2, .hdr_sig_id = 9, @@ -66384,7 +68296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3173] = { + [3269] = { .class_hid = BNXT_ULP_CLASS_HID_24dac, .class_tid = 2, .hdr_sig_id = 9, @@ -66401,7 +68313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3174] = { + [3270] = { .class_hid = BNXT_ULP_CLASS_HID_2597c, .class_tid = 2, .hdr_sig_id = 9, @@ -66419,7 +68331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3175] = { + [3271] = { .class_hid = BNXT_ULP_CLASS_HID_255b0, .class_tid = 2, .hdr_sig_id = 9, @@ -66438,7 +68350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3176] = { + [3272] = { .class_hid = BNXT_ULP_CLASS_HID_246e0, .class_tid = 2, .hdr_sig_id = 9, @@ -66456,7 +68368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3177] = { + [3273] = { .class_hid = BNXT_ULP_CLASS_HID_23374, .class_tid = 2, .hdr_sig_id = 9, @@ -66473,7 +68385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3178] = { + [3274] = { .class_hid = BNXT_ULP_CLASS_HID_21e04, .class_tid = 2, .hdr_sig_id = 9, @@ -66491,7 +68403,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3179] = { + [3275] = { .class_hid = BNXT_ULP_CLASS_HID_21b78, .class_tid = 2, .hdr_sig_id = 9, @@ -66510,7 +68422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3180] = { + [3276] = { .class_hid = BNXT_ULP_CLASS_HID_20fa8, .class_tid = 2, .hdr_sig_id = 9, @@ -66528,7 +68440,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3181] = { + [3277] = { .class_hid = BNXT_ULP_CLASS_HID_257c8, .class_tid = 2, .hdr_sig_id = 9, @@ -66546,7 +68458,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3182] = { + [3278] = { .class_hid = BNXT_ULP_CLASS_HID_22298, .class_tid = 2, .hdr_sig_id = 9, @@ -66565,7 +68477,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3183] = { + [3279] = { .class_hid = BNXT_ULP_CLASS_HID_23fcc, .class_tid = 2, .hdr_sig_id = 9, @@ -66585,7 +68497,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3184] = { + [3280] = { .class_hid = BNXT_ULP_CLASS_HID_2503c, .class_tid = 2, .hdr_sig_id = 9, @@ -66604,7 +68516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3185] = { + [3281] = { .class_hid = BNXT_ULP_CLASS_HID_2239c, .class_tid = 2, .hdr_sig_id = 9, @@ -66620,7 +68532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3186] = { + [3282] = { .class_hid = BNXT_ULP_CLASS_HID_20eac, .class_tid = 2, .hdr_sig_id = 9, @@ -66637,7 +68549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3187] = { + [3283] = { .class_hid = BNXT_ULP_CLASS_HID_20be0, .class_tid = 2, .hdr_sig_id = 9, @@ -66655,7 +68567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3188] = { + [3284] = { .class_hid = BNXT_ULP_CLASS_HID_23cd0, .class_tid = 2, .hdr_sig_id = 9, @@ -66672,7 +68584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3189] = { + [3285] = { .class_hid = BNXT_ULP_CLASS_HID_24470, .class_tid = 2, .hdr_sig_id = 9, @@ -66689,7 +68601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3190] = { + [3286] = { .class_hid = BNXT_ULP_CLASS_HID_25300, .class_tid = 2, .hdr_sig_id = 9, @@ -66707,7 +68619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3191] = { + [3287] = { .class_hid = BNXT_ULP_CLASS_HID_22c74, .class_tid = 2, .hdr_sig_id = 9, @@ -66726,7 +68638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3192] = { + [3288] = { .class_hid = BNXT_ULP_CLASS_HID_240a4, .class_tid = 2, .hdr_sig_id = 9, @@ -66744,7 +68656,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3193] = { + [3289] = { .class_hid = BNXT_ULP_CLASS_HID_23da0, .class_tid = 2, .hdr_sig_id = 9, @@ -66759,7 +68671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3194] = { + [3290] = { .class_hid = BNXT_ULP_CLASS_HID_20970, .class_tid = 2, .hdr_sig_id = 9, @@ -66775,7 +68687,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3195] = { + [3291] = { .class_hid = BNXT_ULP_CLASS_HID_205a4, .class_tid = 2, .hdr_sig_id = 9, @@ -66792,7 +68704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3196] = { + [3292] = { .class_hid = BNXT_ULP_CLASS_HID_23694, .class_tid = 2, .hdr_sig_id = 9, @@ -66808,7 +68720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3197] = { + [3293] = { .class_hid = BNXT_ULP_CLASS_HID_25e34, .class_tid = 2, .hdr_sig_id = 9, @@ -66824,7 +68736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3198] = { + [3294] = { .class_hid = BNXT_ULP_CLASS_HID_22dc4, .class_tid = 2, .hdr_sig_id = 9, @@ -66841,7 +68753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3199] = { + [3295] = { .class_hid = BNXT_ULP_CLASS_HID_22638, .class_tid = 2, .hdr_sig_id = 9, @@ -66859,7 +68771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3200] = { + [3296] = { .class_hid = BNXT_ULP_CLASS_HID_25b68, .class_tid = 2, .hdr_sig_id = 9, @@ -66876,7 +68788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3201] = { + [3297] = { .class_hid = BNXT_ULP_CLASS_HID_34c8, .class_tid = 2, .hdr_sig_id = 9, @@ -66892,7 +68804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3202] = { + [3298] = { .class_hid = BNXT_ULP_CLASS_HID_3a04, .class_tid = 2, .hdr_sig_id = 9, @@ -66909,7 +68821,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3203] = { + [3299] = { + .class_hid = BNXT_ULP_CLASS_HID_09d4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3300] = { .class_hid = BNXT_ULP_CLASS_HID_5e98, .class_tid = 2, .hdr_sig_id = 9, @@ -66927,7 +68857,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3204] = { + [3301] = { + .class_hid = BNXT_ULP_CLASS_HID_2da8, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3302] = { .class_hid = BNXT_ULP_CLASS_HID_07a0, .class_tid = 2, .hdr_sig_id = 9, @@ -66945,7 +68894,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3205] = { + [3303] = { + .class_hid = BNXT_ULP_CLASS_HID_1370, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3304] = { .class_hid = BNXT_ULP_CLASS_HID_2834, .class_tid = 2, .hdr_sig_id = 9, @@ -66964,7 +68932,44 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3206] = { + [3305] = { + .class_hid = BNXT_ULP_CLASS_HID_37c4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3306] = { + .class_hid = BNXT_ULP_CLASS_HID_0398, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3307] = { .class_hid = BNXT_ULP_CLASS_HID_595c, .class_tid = 2, .hdr_sig_id = 9, @@ -66981,7 +68986,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3207] = { + [3308] = { + .class_hid = BNXT_ULP_CLASS_HID_246c, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3309] = { .class_hid = BNXT_ULP_CLASS_HID_1e64, .class_tid = 2, .hdr_sig_id = 9, @@ -66998,7 +69021,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3208] = { + [3310] = { + .class_hid = BNXT_ULP_CLASS_HID_48c0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3311] = { .class_hid = BNXT_ULP_CLASS_HID_22f8, .class_tid = 2, .hdr_sig_id = 9, @@ -67016,7 +69057,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3209] = { + [3312] = { + .class_hid = BNXT_ULP_CLASS_HID_3188, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 260, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3313] = { .class_hid = BNXT_ULP_CLASS_HID_24664, .class_tid = 2, .hdr_sig_id = 10, @@ -67035,7 +69095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3210] = { + [3314] = { .class_hid = BNXT_ULP_CLASS_HID_29418, .class_tid = 2, .hdr_sig_id = 10, @@ -67055,7 +69115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3211] = { + [3315] = { .class_hid = BNXT_ULP_CLASS_HID_30118, .class_tid = 2, .hdr_sig_id = 10, @@ -67075,7 +69135,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3212] = { + [3316] = { .class_hid = BNXT_ULP_CLASS_HID_38a18, .class_tid = 2, .hdr_sig_id = 10, @@ -67096,7 +69156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3213] = { + [3317] = { .class_hid = BNXT_ULP_CLASS_HID_255b4, .class_tid = 2, .hdr_sig_id = 10, @@ -67116,7 +69176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3214] = { + [3318] = { .class_hid = BNXT_ULP_CLASS_HID_2deb4, .class_tid = 2, .hdr_sig_id = 10, @@ -67137,7 +69197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3215] = { + [3319] = { .class_hid = BNXT_ULP_CLASS_HID_34bb4, .class_tid = 2, .hdr_sig_id = 10, @@ -67158,7 +69218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3216] = { + [3320] = { .class_hid = BNXT_ULP_CLASS_HID_39968, .class_tid = 2, .hdr_sig_id = 10, @@ -67180,7 +69240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3217] = { + [3321] = { .class_hid = BNXT_ULP_CLASS_HID_22e68, .class_tid = 2, .hdr_sig_id = 10, @@ -67201,7 +69261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3218] = { + [3322] = { .class_hid = BNXT_ULP_CLASS_HID_2db68, .class_tid = 2, .hdr_sig_id = 10, @@ -67223,7 +69283,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3219] = { + [3323] = { .class_hid = BNXT_ULP_CLASS_HID_34468, .class_tid = 2, .hdr_sig_id = 10, @@ -67245,7 +69305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3220] = { + [3324] = { .class_hid = BNXT_ULP_CLASS_HID_3921c, .class_tid = 2, .hdr_sig_id = 10, @@ -67268,7 +69328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3221] = { + [3325] = { .class_hid = BNXT_ULP_CLASS_HID_24318, .class_tid = 2, .hdr_sig_id = 10, @@ -67288,7 +69348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3222] = { + [3326] = { .class_hid = BNXT_ULP_CLASS_HID_290cc, .class_tid = 2, .hdr_sig_id = 10, @@ -67309,7 +69369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3223] = { + [3327] = { .class_hid = BNXT_ULP_CLASS_HID_31dcc, .class_tid = 2, .hdr_sig_id = 10, @@ -67330,7 +69390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3224] = { + [3328] = { .class_hid = BNXT_ULP_CLASS_HID_386cc, .class_tid = 2, .hdr_sig_id = 10, @@ -67352,7 +69412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3225] = { + [3329] = { .class_hid = BNXT_ULP_CLASS_HID_20fac, .class_tid = 2, .hdr_sig_id = 10, @@ -67372,7 +69432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3226] = { + [3330] = { .class_hid = BNXT_ULP_CLASS_HID_2b8ac, .class_tid = 2, .hdr_sig_id = 10, @@ -67393,7 +69453,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3227] = { + [3331] = { .class_hid = BNXT_ULP_CLASS_HID_325ac, .class_tid = 2, .hdr_sig_id = 10, @@ -67414,7 +69474,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3228] = { + [3332] = { .class_hid = BNXT_ULP_CLASS_HID_3aeac, .class_tid = 2, .hdr_sig_id = 10, @@ -67436,7 +69496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3229] = { + [3333] = { .class_hid = BNXT_ULP_CLASS_HID_21afc, .class_tid = 2, .hdr_sig_id = 10, @@ -67457,7 +69517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3230] = { + [3334] = { .class_hid = BNXT_ULP_CLASS_HID_287fc, .class_tid = 2, .hdr_sig_id = 10, @@ -67479,7 +69539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3231] = { + [3335] = { .class_hid = BNXT_ULP_CLASS_HID_330fc, .class_tid = 2, .hdr_sig_id = 10, @@ -67501,7 +69561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3232] = { + [3336] = { .class_hid = BNXT_ULP_CLASS_HID_3bdfc, .class_tid = 2, .hdr_sig_id = 10, @@ -67524,7 +69584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3233] = { + [3337] = { .class_hid = BNXT_ULP_CLASS_HID_217b0, .class_tid = 2, .hdr_sig_id = 10, @@ -67546,7 +69606,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3234] = { + [3338] = { .class_hid = BNXT_ULP_CLASS_HID_280b0, .class_tid = 2, .hdr_sig_id = 10, @@ -67569,7 +69629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3235] = { + [3339] = { .class_hid = BNXT_ULP_CLASS_HID_30db0, .class_tid = 2, .hdr_sig_id = 10, @@ -67592,7 +69652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3236] = { + [3340] = { .class_hid = BNXT_ULP_CLASS_HID_3b6b0, .class_tid = 2, .hdr_sig_id = 10, @@ -67616,7 +69676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3237] = { + [3341] = { .class_hid = BNXT_ULP_CLASS_HID_20860, .class_tid = 2, .hdr_sig_id = 10, @@ -67637,7 +69697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3238] = { + [3342] = { .class_hid = BNXT_ULP_CLASS_HID_2b560, .class_tid = 2, .hdr_sig_id = 10, @@ -67659,7 +69719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3239] = { + [3343] = { .class_hid = BNXT_ULP_CLASS_HID_33e60, .class_tid = 2, .hdr_sig_id = 10, @@ -67681,7 +69741,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3240] = { + [3344] = { .class_hid = BNXT_ULP_CLASS_HID_3ab60, .class_tid = 2, .hdr_sig_id = 10, @@ -67704,7 +69764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3241] = { + [3345] = { .class_hid = BNXT_ULP_CLASS_HID_253c0, .class_tid = 2, .hdr_sig_id = 10, @@ -67724,7 +69784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3242] = { + [3346] = { .class_hid = BNXT_ULP_CLASS_HID_2dcc0, .class_tid = 2, .hdr_sig_id = 10, @@ -67745,7 +69805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3243] = { + [3347] = { .class_hid = BNXT_ULP_CLASS_HID_349c0, .class_tid = 2, .hdr_sig_id = 10, @@ -67766,7 +69826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3244] = { + [3348] = { .class_hid = BNXT_ULP_CLASS_HID_397f4, .class_tid = 2, .hdr_sig_id = 10, @@ -67788,7 +69848,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3245] = { + [3349] = { .class_hid = BNXT_ULP_CLASS_HID_23f10, .class_tid = 2, .hdr_sig_id = 10, @@ -67809,7 +69869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3246] = { + [3350] = { .class_hid = BNXT_ULP_CLASS_HID_2a810, .class_tid = 2, .hdr_sig_id = 10, @@ -67831,7 +69891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3247] = { + [3351] = { .class_hid = BNXT_ULP_CLASS_HID_35510, .class_tid = 2, .hdr_sig_id = 10, @@ -67853,7 +69913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3248] = { + [3352] = { .class_hid = BNXT_ULP_CLASS_HID_3de10, .class_tid = 2, .hdr_sig_id = 10, @@ -67876,7 +69936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3249] = { + [3353] = { .class_hid = BNXT_ULP_CLASS_HID_23bc4, .class_tid = 2, .hdr_sig_id = 10, @@ -67898,7 +69958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3250] = { + [3354] = { .class_hid = BNXT_ULP_CLASS_HID_2a4c4, .class_tid = 2, .hdr_sig_id = 10, @@ -67921,7 +69981,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3251] = { + [3355] = { .class_hid = BNXT_ULP_CLASS_HID_351c4, .class_tid = 2, .hdr_sig_id = 10, @@ -67944,7 +70004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3252] = { + [3356] = { .class_hid = BNXT_ULP_CLASS_HID_3dac4, .class_tid = 2, .hdr_sig_id = 10, @@ -67968,7 +70028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3253] = { + [3357] = { .class_hid = BNXT_ULP_CLASS_HID_22cf4, .class_tid = 2, .hdr_sig_id = 10, @@ -67989,7 +70049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3254] = { + [3358] = { .class_hid = BNXT_ULP_CLASS_HID_2d9f4, .class_tid = 2, .hdr_sig_id = 10, @@ -68011,7 +70071,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3255] = { + [3359] = { .class_hid = BNXT_ULP_CLASS_HID_342f4, .class_tid = 2, .hdr_sig_id = 10, @@ -68033,7 +70093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3256] = { + [3360] = { .class_hid = BNXT_ULP_CLASS_HID_390a8, .class_tid = 2, .hdr_sig_id = 10, @@ -68056,7 +70116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3257] = { + [3361] = { .class_hid = BNXT_ULP_CLASS_HID_21908, .class_tid = 2, .hdr_sig_id = 10, @@ -68077,7 +70137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3258] = { + [3362] = { .class_hid = BNXT_ULP_CLASS_HID_28208, .class_tid = 2, .hdr_sig_id = 10, @@ -68099,7 +70159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3259] = { + [3363] = { .class_hid = BNXT_ULP_CLASS_HID_30f08, .class_tid = 2, .hdr_sig_id = 10, @@ -68121,7 +70181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3260] = { + [3364] = { .class_hid = BNXT_ULP_CLASS_HID_3b808, .class_tid = 2, .hdr_sig_id = 10, @@ -68144,7 +70204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3261] = { + [3365] = { .class_hid = BNXT_ULP_CLASS_HID_243a4, .class_tid = 2, .hdr_sig_id = 10, @@ -68166,7 +70226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3262] = { + [3366] = { .class_hid = BNXT_ULP_CLASS_HID_29158, .class_tid = 2, .hdr_sig_id = 10, @@ -68189,7 +70249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3263] = { + [3367] = { .class_hid = BNXT_ULP_CLASS_HID_31a58, .class_tid = 2, .hdr_sig_id = 10, @@ -68212,7 +70272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3264] = { + [3368] = { .class_hid = BNXT_ULP_CLASS_HID_38758, .class_tid = 2, .hdr_sig_id = 10, @@ -68236,7 +70296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3265] = { + [3369] = { .class_hid = BNXT_ULP_CLASS_HID_25c58, .class_tid = 2, .hdr_sig_id = 10, @@ -68259,7 +70319,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3266] = { + [3370] = { .class_hid = BNXT_ULP_CLASS_HID_2c958, .class_tid = 2, .hdr_sig_id = 10, @@ -68283,7 +70343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3267] = { + [3371] = { .class_hid = BNXT_ULP_CLASS_HID_3170c, .class_tid = 2, .hdr_sig_id = 10, @@ -68307,7 +70367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3268] = { + [3372] = { .class_hid = BNXT_ULP_CLASS_HID_3800c, .class_tid = 2, .hdr_sig_id = 10, @@ -68332,7 +70392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3269] = { + [3373] = { .class_hid = BNXT_ULP_CLASS_HID_2123c, .class_tid = 2, .hdr_sig_id = 10, @@ -68354,7 +70414,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3270] = { + [3374] = { .class_hid = BNXT_ULP_CLASS_HID_29f3c, .class_tid = 2, .hdr_sig_id = 10, @@ -68377,7 +70437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3271] = { + [3375] = { .class_hid = BNXT_ULP_CLASS_HID_3083c, .class_tid = 2, .hdr_sig_id = 10, @@ -68400,7 +70460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3272] = { + [3376] = { .class_hid = BNXT_ULP_CLASS_HID_3b53c, .class_tid = 2, .hdr_sig_id = 10, @@ -68424,7 +70484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3273] = { + [3377] = { .class_hid = BNXT_ULP_CLASS_HID_240a8, .class_tid = 2, .hdr_sig_id = 10, @@ -68442,7 +70502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3274] = { + [3378] = { .class_hid = BNXT_ULP_CLASS_HID_2cda8, .class_tid = 2, .hdr_sig_id = 10, @@ -68461,7 +70521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3275] = { + [3379] = { .class_hid = BNXT_ULP_CLASS_HID_31b5c, .class_tid = 2, .hdr_sig_id = 10, @@ -68480,7 +70540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3276] = { + [3380] = { .class_hid = BNXT_ULP_CLASS_HID_3845c, .class_tid = 2, .hdr_sig_id = 10, @@ -68500,7 +70560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3277] = { + [3381] = { .class_hid = BNXT_ULP_CLASS_HID_22ff8, .class_tid = 2, .hdr_sig_id = 10, @@ -68519,7 +70579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3278] = { + [3382] = { .class_hid = BNXT_ULP_CLASS_HID_2d8f8, .class_tid = 2, .hdr_sig_id = 10, @@ -68539,7 +70599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3279] = { + [3383] = { .class_hid = BNXT_ULP_CLASS_HID_345f8, .class_tid = 2, .hdr_sig_id = 10, @@ -68559,7 +70619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3280] = { + [3384] = { .class_hid = BNXT_ULP_CLASS_HID_393ac, .class_tid = 2, .hdr_sig_id = 10, @@ -68580,7 +70640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3281] = { + [3385] = { .class_hid = BNXT_ULP_CLASS_HID_228ac, .class_tid = 2, .hdr_sig_id = 10, @@ -68600,7 +70660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3282] = { + [3386] = { .class_hid = BNXT_ULP_CLASS_HID_2d5ac, .class_tid = 2, .hdr_sig_id = 10, @@ -68621,7 +70681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3283] = { + [3387] = { .class_hid = BNXT_ULP_CLASS_HID_35eac, .class_tid = 2, .hdr_sig_id = 10, @@ -68642,7 +70702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3284] = { + [3388] = { .class_hid = BNXT_ULP_CLASS_HID_3cbac, .class_tid = 2, .hdr_sig_id = 10, @@ -68664,7 +70724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3285] = { + [3389] = { .class_hid = BNXT_ULP_CLASS_HID_25d5c, .class_tid = 2, .hdr_sig_id = 10, @@ -68683,7 +70743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3286] = { + [3390] = { .class_hid = BNXT_ULP_CLASS_HID_2c65c, .class_tid = 2, .hdr_sig_id = 10, @@ -68703,7 +70763,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3287] = { + [3391] = { .class_hid = BNXT_ULP_CLASS_HID_31410, .class_tid = 2, .hdr_sig_id = 10, @@ -68723,7 +70783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3288] = { + [3392] = { .class_hid = BNXT_ULP_CLASS_HID_38110, .class_tid = 2, .hdr_sig_id = 10, @@ -68744,7 +70804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3289] = { + [3393] = { .class_hid = BNXT_ULP_CLASS_HID_209f0, .class_tid = 2, .hdr_sig_id = 10, @@ -68763,7 +70823,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3290] = { + [3394] = { .class_hid = BNXT_ULP_CLASS_HID_2b2f0, .class_tid = 2, .hdr_sig_id = 10, @@ -68783,7 +70843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3291] = { + [3395] = { .class_hid = BNXT_ULP_CLASS_HID_33ff0, .class_tid = 2, .hdr_sig_id = 10, @@ -68803,7 +70863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3292] = { + [3396] = { .class_hid = BNXT_ULP_CLASS_HID_3a8f0, .class_tid = 2, .hdr_sig_id = 10, @@ -68824,7 +70884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3293] = { + [3397] = { .class_hid = BNXT_ULP_CLASS_HID_214c0, .class_tid = 2, .hdr_sig_id = 10, @@ -68844,7 +70904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3294] = { + [3398] = { .class_hid = BNXT_ULP_CLASS_HID_281c0, .class_tid = 2, .hdr_sig_id = 10, @@ -68865,7 +70925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3295] = { + [3399] = { .class_hid = BNXT_ULP_CLASS_HID_30ac0, .class_tid = 2, .hdr_sig_id = 10, @@ -68886,7 +70946,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3296] = { + [3400] = { .class_hid = BNXT_ULP_CLASS_HID_3b7c0, .class_tid = 2, .hdr_sig_id = 10, @@ -68908,7 +70968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3297] = { + [3401] = { .class_hid = BNXT_ULP_CLASS_HID_211f4, .class_tid = 2, .hdr_sig_id = 10, @@ -68929,7 +70989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3298] = { + [3402] = { .class_hid = BNXT_ULP_CLASS_HID_29af4, .class_tid = 2, .hdr_sig_id = 10, @@ -68951,7 +71011,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3299] = { + [3403] = { .class_hid = BNXT_ULP_CLASS_HID_307f4, .class_tid = 2, .hdr_sig_id = 10, @@ -68973,7 +71033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3300] = { + [3404] = { .class_hid = BNXT_ULP_CLASS_HID_3b0f4, .class_tid = 2, .hdr_sig_id = 10, @@ -68996,7 +71056,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3301] = { + [3405] = { .class_hid = BNXT_ULP_CLASS_HID_202a4, .class_tid = 2, .hdr_sig_id = 10, @@ -69016,7 +71076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3302] = { + [3406] = { .class_hid = BNXT_ULP_CLASS_HID_28fa4, .class_tid = 2, .hdr_sig_id = 10, @@ -69037,7 +71097,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3303] = { + [3407] = { .class_hid = BNXT_ULP_CLASS_HID_338a4, .class_tid = 2, .hdr_sig_id = 10, @@ -69058,7 +71118,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3304] = { + [3408] = { .class_hid = BNXT_ULP_CLASS_HID_3a5a4, .class_tid = 2, .hdr_sig_id = 10, @@ -69080,7 +71140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3305] = { + [3409] = { .class_hid = BNXT_ULP_CLASS_HID_22a04, .class_tid = 2, .hdr_sig_id = 10, @@ -69099,7 +71159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3306] = { + [3410] = { .class_hid = BNXT_ULP_CLASS_HID_2d704, .class_tid = 2, .hdr_sig_id = 10, @@ -69119,7 +71179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3307] = { + [3411] = { .class_hid = BNXT_ULP_CLASS_HID_34004, .class_tid = 2, .hdr_sig_id = 10, @@ -69139,7 +71199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3308] = { + [3412] = { .class_hid = BNXT_ULP_CLASS_HID_3cd04, .class_tid = 2, .hdr_sig_id = 10, @@ -69160,7 +71220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3309] = { + [3413] = { .class_hid = BNXT_ULP_CLASS_HID_23954, .class_tid = 2, .hdr_sig_id = 10, @@ -69180,7 +71240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3310] = { + [3414] = { .class_hid = BNXT_ULP_CLASS_HID_2a254, .class_tid = 2, .hdr_sig_id = 10, @@ -69201,7 +71261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3311] = { + [3415] = { .class_hid = BNXT_ULP_CLASS_HID_32f54, .class_tid = 2, .hdr_sig_id = 10, @@ -69222,7 +71282,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3312] = { + [3416] = { .class_hid = BNXT_ULP_CLASS_HID_3d854, .class_tid = 2, .hdr_sig_id = 10, @@ -69244,7 +71304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3313] = { + [3417] = { .class_hid = BNXT_ULP_CLASS_HID_23208, .class_tid = 2, .hdr_sig_id = 10, @@ -69265,7 +71325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3314] = { + [3418] = { .class_hid = BNXT_ULP_CLASS_HID_2bf08, .class_tid = 2, .hdr_sig_id = 10, @@ -69287,7 +71347,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3315] = { + [3419] = { .class_hid = BNXT_ULP_CLASS_HID_32808, .class_tid = 2, .hdr_sig_id = 10, @@ -69309,7 +71369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3316] = { + [3420] = { .class_hid = BNXT_ULP_CLASS_HID_3d508, .class_tid = 2, .hdr_sig_id = 10, @@ -69332,7 +71392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3317] = { + [3421] = { .class_hid = BNXT_ULP_CLASS_HID_22738, .class_tid = 2, .hdr_sig_id = 10, @@ -69352,7 +71412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3318] = { + [3422] = { .class_hid = BNXT_ULP_CLASS_HID_2d038, .class_tid = 2, .hdr_sig_id = 10, @@ -69373,7 +71433,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3319] = { + [3423] = { .class_hid = BNXT_ULP_CLASS_HID_35d38, .class_tid = 2, .hdr_sig_id = 10, @@ -69394,7 +71454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3320] = { + [3424] = { .class_hid = BNXT_ULP_CLASS_HID_3c638, .class_tid = 2, .hdr_sig_id = 10, @@ -69416,7 +71476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3321] = { + [3425] = { .class_hid = BNXT_ULP_CLASS_HID_2134c, .class_tid = 2, .hdr_sig_id = 10, @@ -69436,7 +71496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3322] = { + [3426] = { .class_hid = BNXT_ULP_CLASS_HID_29c4c, .class_tid = 2, .hdr_sig_id = 10, @@ -69457,7 +71517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3323] = { + [3427] = { .class_hid = BNXT_ULP_CLASS_HID_3094c, .class_tid = 2, .hdr_sig_id = 10, @@ -69478,7 +71538,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3324] = { + [3428] = { .class_hid = BNXT_ULP_CLASS_HID_3b24c, .class_tid = 2, .hdr_sig_id = 10, @@ -69500,7 +71560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3325] = { + [3429] = { .class_hid = BNXT_ULP_CLASS_HID_25de8, .class_tid = 2, .hdr_sig_id = 10, @@ -69521,7 +71581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3326] = { + [3430] = { .class_hid = BNXT_ULP_CLASS_HID_2c6e8, .class_tid = 2, .hdr_sig_id = 10, @@ -69543,7 +71603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3327] = { + [3431] = { .class_hid = BNXT_ULP_CLASS_HID_3149c, .class_tid = 2, .hdr_sig_id = 10, @@ -69565,7 +71625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3328] = { + [3432] = { .class_hid = BNXT_ULP_CLASS_HID_3819c, .class_tid = 2, .hdr_sig_id = 10, @@ -69588,7 +71648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3329] = { + [3433] = { .class_hid = BNXT_ULP_CLASS_HID_2569c, .class_tid = 2, .hdr_sig_id = 10, @@ -69610,7 +71670,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3330] = { + [3434] = { .class_hid = BNXT_ULP_CLASS_HID_2c39c, .class_tid = 2, .hdr_sig_id = 10, @@ -69633,7 +71693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3331] = { + [3435] = { .class_hid = BNXT_ULP_CLASS_HID_31150, .class_tid = 2, .hdr_sig_id = 10, @@ -69656,7 +71716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3332] = { + [3436] = { .class_hid = BNXT_ULP_CLASS_HID_39a50, .class_tid = 2, .hdr_sig_id = 10, @@ -69680,7 +71740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3333] = { + [3437] = { .class_hid = BNXT_ULP_CLASS_HID_24b4c, .class_tid = 2, .hdr_sig_id = 10, @@ -69701,7 +71761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3334] = { + [3438] = { .class_hid = BNXT_ULP_CLASS_HID_29900, .class_tid = 2, .hdr_sig_id = 10, @@ -69723,7 +71783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3335] = { + [3439] = { .class_hid = BNXT_ULP_CLASS_HID_30200, .class_tid = 2, .hdr_sig_id = 10, @@ -69745,7 +71805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3336] = { + [3440] = { .class_hid = BNXT_ULP_CLASS_HID_38f00, .class_tid = 2, .hdr_sig_id = 10, @@ -69768,7 +71828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3337] = { + [3441] = { .class_hid = BNXT_ULP_CLASS_HID_22f74, .class_tid = 2, .hdr_sig_id = 10, @@ -69786,7 +71846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3338] = { + [3442] = { .class_hid = BNXT_ULP_CLASS_HID_2d874, .class_tid = 2, .hdr_sig_id = 10, @@ -69805,7 +71865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3339] = { + [3443] = { .class_hid = BNXT_ULP_CLASS_HID_34574, .class_tid = 2, .hdr_sig_id = 10, @@ -69824,7 +71884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3340] = { + [3444] = { .class_hid = BNXT_ULP_CLASS_HID_39328, .class_tid = 2, .hdr_sig_id = 10, @@ -69844,7 +71904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3341] = { + [3445] = { .class_hid = BNXT_ULP_CLASS_HID_23a44, .class_tid = 2, .hdr_sig_id = 10, @@ -69863,7 +71923,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3342] = { + [3446] = { .class_hid = BNXT_ULP_CLASS_HID_2a744, .class_tid = 2, .hdr_sig_id = 10, @@ -69883,7 +71943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3343] = { + [3447] = { .class_hid = BNXT_ULP_CLASS_HID_35044, .class_tid = 2, .hdr_sig_id = 10, @@ -69903,7 +71963,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3344] = { + [3448] = { .class_hid = BNXT_ULP_CLASS_HID_3dd44, .class_tid = 2, .hdr_sig_id = 10, @@ -69924,7 +71984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3345] = { + [3449] = { .class_hid = BNXT_ULP_CLASS_HID_23778, .class_tid = 2, .hdr_sig_id = 10, @@ -69944,7 +72004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3346] = { + [3450] = { .class_hid = BNXT_ULP_CLASS_HID_2a078, .class_tid = 2, .hdr_sig_id = 10, @@ -69965,7 +72025,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3347] = { + [3451] = { .class_hid = BNXT_ULP_CLASS_HID_32d78, .class_tid = 2, .hdr_sig_id = 10, @@ -69986,7 +72046,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3348] = { + [3452] = { .class_hid = BNXT_ULP_CLASS_HID_3d678, .class_tid = 2, .hdr_sig_id = 10, @@ -70008,7 +72068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3349] = { + [3453] = { .class_hid = BNXT_ULP_CLASS_HID_22828, .class_tid = 2, .hdr_sig_id = 10, @@ -70027,7 +72087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3350] = { + [3454] = { .class_hid = BNXT_ULP_CLASS_HID_2d528, .class_tid = 2, .hdr_sig_id = 10, @@ -70047,7 +72107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3351] = { + [3455] = { .class_hid = BNXT_ULP_CLASS_HID_35e28, .class_tid = 2, .hdr_sig_id = 10, @@ -70067,7 +72127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3352] = { + [3456] = { .class_hid = BNXT_ULP_CLASS_HID_3cb28, .class_tid = 2, .hdr_sig_id = 10, @@ -70088,7 +72148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3353] = { + [3457] = { .class_hid = BNXT_ULP_CLASS_HID_214bc, .class_tid = 2, .hdr_sig_id = 10, @@ -70107,7 +72167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3354] = { + [3458] = { .class_hid = BNXT_ULP_CLASS_HID_281bc, .class_tid = 2, .hdr_sig_id = 10, @@ -70127,7 +72187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3355] = { + [3459] = { .class_hid = BNXT_ULP_CLASS_HID_30abc, .class_tid = 2, .hdr_sig_id = 10, @@ -70147,7 +72207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3356] = { + [3460] = { .class_hid = BNXT_ULP_CLASS_HID_3b7bc, .class_tid = 2, .hdr_sig_id = 10, @@ -70168,7 +72228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3357] = { + [3461] = { .class_hid = BNXT_ULP_CLASS_HID_25ed8, .class_tid = 2, .hdr_sig_id = 10, @@ -70188,7 +72248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3358] = { + [3462] = { .class_hid = BNXT_ULP_CLASS_HID_2cbd8, .class_tid = 2, .hdr_sig_id = 10, @@ -70209,7 +72269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3359] = { + [3463] = { .class_hid = BNXT_ULP_CLASS_HID_3198c, .class_tid = 2, .hdr_sig_id = 10, @@ -70230,7 +72290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3360] = { + [3464] = { .class_hid = BNXT_ULP_CLASS_HID_3828c, .class_tid = 2, .hdr_sig_id = 10, @@ -70252,7 +72312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3361] = { + [3465] = { .class_hid = BNXT_ULP_CLASS_HID_25b8c, .class_tid = 2, .hdr_sig_id = 10, @@ -70273,7 +72333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3362] = { + [3466] = { .class_hid = BNXT_ULP_CLASS_HID_2c48c, .class_tid = 2, .hdr_sig_id = 10, @@ -70295,7 +72355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3363] = { + [3467] = { .class_hid = BNXT_ULP_CLASS_HID_31240, .class_tid = 2, .hdr_sig_id = 10, @@ -70317,7 +72377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3364] = { + [3468] = { .class_hid = BNXT_ULP_CLASS_HID_39f40, .class_tid = 2, .hdr_sig_id = 10, @@ -70340,7 +72400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3365] = { + [3469] = { .class_hid = BNXT_ULP_CLASS_HID_21170, .class_tid = 2, .hdr_sig_id = 10, @@ -70360,7 +72420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3366] = { + [3470] = { .class_hid = BNXT_ULP_CLASS_HID_29a70, .class_tid = 2, .hdr_sig_id = 10, @@ -70381,7 +72441,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3367] = { + [3471] = { .class_hid = BNXT_ULP_CLASS_HID_30770, .class_tid = 2, .hdr_sig_id = 10, @@ -70402,7 +72462,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3368] = { + [3472] = { .class_hid = BNXT_ULP_CLASS_HID_3b070, .class_tid = 2, .hdr_sig_id = 10, @@ -70424,7 +72484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3369] = { + [3473] = { .class_hid = BNXT_ULP_CLASS_HID_238d0, .class_tid = 2, .hdr_sig_id = 10, @@ -70443,7 +72503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3370] = { + [3474] = { .class_hid = BNXT_ULP_CLASS_HID_2a5d0, .class_tid = 2, .hdr_sig_id = 10, @@ -70463,7 +72523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3371] = { + [3475] = { .class_hid = BNXT_ULP_CLASS_HID_32ed0, .class_tid = 2, .hdr_sig_id = 10, @@ -70483,7 +72543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3372] = { + [3476] = { .class_hid = BNXT_ULP_CLASS_HID_3dbd0, .class_tid = 2, .hdr_sig_id = 10, @@ -70504,7 +72564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3373] = { + [3477] = { .class_hid = BNXT_ULP_CLASS_HID_20420, .class_tid = 2, .hdr_sig_id = 10, @@ -70524,7 +72584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3374] = { + [3478] = { .class_hid = BNXT_ULP_CLASS_HID_2b120, .class_tid = 2, .hdr_sig_id = 10, @@ -70545,7 +72605,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3375] = { + [3479] = { .class_hid = BNXT_ULP_CLASS_HID_33a20, .class_tid = 2, .hdr_sig_id = 10, @@ -70566,7 +72626,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3376] = { + [3480] = { .class_hid = BNXT_ULP_CLASS_HID_3a720, .class_tid = 2, .hdr_sig_id = 10, @@ -70588,7 +72648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3377] = { + [3481] = { .class_hid = BNXT_ULP_CLASS_HID_200d4, .class_tid = 2, .hdr_sig_id = 10, @@ -70609,7 +72669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3378] = { + [3482] = { .class_hid = BNXT_ULP_CLASS_HID_28dd4, .class_tid = 2, .hdr_sig_id = 10, @@ -70631,7 +72691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3379] = { + [3483] = { .class_hid = BNXT_ULP_CLASS_HID_336d4, .class_tid = 2, .hdr_sig_id = 10, @@ -70653,7 +72713,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3380] = { + [3484] = { .class_hid = BNXT_ULP_CLASS_HID_3a3d4, .class_tid = 2, .hdr_sig_id = 10, @@ -70676,7 +72736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3381] = { + [3485] = { .class_hid = BNXT_ULP_CLASS_HID_23584, .class_tid = 2, .hdr_sig_id = 10, @@ -70696,7 +72756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3382] = { + [3486] = { .class_hid = BNXT_ULP_CLASS_HID_2be84, .class_tid = 2, .hdr_sig_id = 10, @@ -70717,7 +72777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3383] = { + [3487] = { .class_hid = BNXT_ULP_CLASS_HID_32b84, .class_tid = 2, .hdr_sig_id = 10, @@ -70738,7 +72798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3384] = { + [3488] = { .class_hid = BNXT_ULP_CLASS_HID_3d484, .class_tid = 2, .hdr_sig_id = 10, @@ -70760,7 +72820,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3385] = { + [3489] = { .class_hid = BNXT_ULP_CLASS_HID_25d64, .class_tid = 2, .hdr_sig_id = 10, @@ -70780,7 +72840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3386] = { + [3490] = { .class_hid = BNXT_ULP_CLASS_HID_2c664, .class_tid = 2, .hdr_sig_id = 10, @@ -70801,7 +72861,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3387] = { + [3491] = { .class_hid = BNXT_ULP_CLASS_HID_31418, .class_tid = 2, .hdr_sig_id = 10, @@ -70822,7 +72882,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3388] = { + [3492] = { .class_hid = BNXT_ULP_CLASS_HID_38118, .class_tid = 2, .hdr_sig_id = 10, @@ -70844,7 +72904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3389] = { + [3493] = { .class_hid = BNXT_ULP_CLASS_HID_228b4, .class_tid = 2, .hdr_sig_id = 10, @@ -70865,7 +72925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3390] = { + [3494] = { .class_hid = BNXT_ULP_CLASS_HID_2d5b4, .class_tid = 2, .hdr_sig_id = 10, @@ -70887,7 +72947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3391] = { + [3495] = { .class_hid = BNXT_ULP_CLASS_HID_35eb4, .class_tid = 2, .hdr_sig_id = 10, @@ -70909,7 +72969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3392] = { + [3496] = { .class_hid = BNXT_ULP_CLASS_HID_3cbb4, .class_tid = 2, .hdr_sig_id = 10, @@ -70932,7 +72992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3393] = { + [3497] = { .class_hid = BNXT_ULP_CLASS_HID_22568, .class_tid = 2, .hdr_sig_id = 10, @@ -70954,7 +73014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3394] = { + [3498] = { .class_hid = BNXT_ULP_CLASS_HID_2ae68, .class_tid = 2, .hdr_sig_id = 10, @@ -70977,7 +73037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3395] = { + [3499] = { .class_hid = BNXT_ULP_CLASS_HID_35b68, .class_tid = 2, .hdr_sig_id = 10, @@ -71000,7 +73060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3396] = { + [3500] = { .class_hid = BNXT_ULP_CLASS_HID_3c468, .class_tid = 2, .hdr_sig_id = 10, @@ -71024,7 +73084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3397] = { + [3501] = { .class_hid = BNXT_ULP_CLASS_HID_25618, .class_tid = 2, .hdr_sig_id = 10, @@ -71045,7 +73105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3398] = { + [3502] = { .class_hid = BNXT_ULP_CLASS_HID_2c318, .class_tid = 2, .hdr_sig_id = 10, @@ -71067,7 +73127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3399] = { + [3503] = { .class_hid = BNXT_ULP_CLASS_HID_310cc, .class_tid = 2, .hdr_sig_id = 10, @@ -71089,7 +73149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3400] = { + [3504] = { .class_hid = BNXT_ULP_CLASS_HID_39dcc, .class_tid = 2, .hdr_sig_id = 10, @@ -71112,7 +73172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3401] = { + [3505] = { .class_hid = BNXT_ULP_CLASS_HID_229b8, .class_tid = 2, .hdr_sig_id = 10, @@ -71129,7 +73189,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3402] = { + [3506] = { .class_hid = BNXT_ULP_CLASS_HID_2d2b8, .class_tid = 2, .hdr_sig_id = 10, @@ -71147,7 +73207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3403] = { + [3507] = { .class_hid = BNXT_ULP_CLASS_HID_35fb8, .class_tid = 2, .hdr_sig_id = 10, @@ -71165,7 +73225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3404] = { + [3508] = { .class_hid = BNXT_ULP_CLASS_HID_3c8b8, .class_tid = 2, .hdr_sig_id = 10, @@ -71184,7 +73244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3405] = { + [3509] = { .class_hid = BNXT_ULP_CLASS_HID_23488, .class_tid = 2, .hdr_sig_id = 10, @@ -71202,7 +73262,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3406] = { + [3510] = { .class_hid = BNXT_ULP_CLASS_HID_2a188, .class_tid = 2, .hdr_sig_id = 10, @@ -71221,7 +73281,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3407] = { + [3511] = { .class_hid = BNXT_ULP_CLASS_HID_32a88, .class_tid = 2, .hdr_sig_id = 10, @@ -71240,7 +73300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3408] = { + [3512] = { .class_hid = BNXT_ULP_CLASS_HID_3d788, .class_tid = 2, .hdr_sig_id = 10, @@ -71260,7 +73320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3409] = { + [3513] = { .class_hid = BNXT_ULP_CLASS_HID_231bc, .class_tid = 2, .hdr_sig_id = 10, @@ -71279,7 +73339,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3410] = { + [3514] = { .class_hid = BNXT_ULP_CLASS_HID_2babc, .class_tid = 2, .hdr_sig_id = 10, @@ -71299,7 +73359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3411] = { + [3515] = { .class_hid = BNXT_ULP_CLASS_HID_327bc, .class_tid = 2, .hdr_sig_id = 10, @@ -71319,7 +73379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3412] = { + [3516] = { .class_hid = BNXT_ULP_CLASS_HID_3d0bc, .class_tid = 2, .hdr_sig_id = 10, @@ -71340,7 +73400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3413] = { + [3517] = { .class_hid = BNXT_ULP_CLASS_HID_2226c, .class_tid = 2, .hdr_sig_id = 10, @@ -71358,7 +73418,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3414] = { + [3518] = { .class_hid = BNXT_ULP_CLASS_HID_2af6c, .class_tid = 2, .hdr_sig_id = 10, @@ -71377,7 +73437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3415] = { + [3519] = { .class_hid = BNXT_ULP_CLASS_HID_3586c, .class_tid = 2, .hdr_sig_id = 10, @@ -71396,7 +73456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3416] = { + [3520] = { .class_hid = BNXT_ULP_CLASS_HID_3c56c, .class_tid = 2, .hdr_sig_id = 10, @@ -71416,7 +73476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3417] = { + [3521] = { .class_hid = BNXT_ULP_CLASS_HID_24dcc, .class_tid = 2, .hdr_sig_id = 10, @@ -71434,7 +73494,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3418] = { + [3522] = { .class_hid = BNXT_ULP_CLASS_HID_29b80, .class_tid = 2, .hdr_sig_id = 10, @@ -71453,7 +73513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3419] = { + [3523] = { .class_hid = BNXT_ULP_CLASS_HID_30480, .class_tid = 2, .hdr_sig_id = 10, @@ -71472,7 +73532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3420] = { + [3524] = { .class_hid = BNXT_ULP_CLASS_HID_3b180, .class_tid = 2, .hdr_sig_id = 10, @@ -71492,7 +73552,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3421] = { + [3525] = { .class_hid = BNXT_ULP_CLASS_HID_2591c, .class_tid = 2, .hdr_sig_id = 10, @@ -71511,7 +73571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3422] = { + [3526] = { .class_hid = BNXT_ULP_CLASS_HID_2c21c, .class_tid = 2, .hdr_sig_id = 10, @@ -71531,7 +73591,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3423] = { + [3527] = { .class_hid = BNXT_ULP_CLASS_HID_313d0, .class_tid = 2, .hdr_sig_id = 10, @@ -71551,7 +73611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3424] = { + [3528] = { .class_hid = BNXT_ULP_CLASS_HID_39cd0, .class_tid = 2, .hdr_sig_id = 10, @@ -71572,7 +73632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3425] = { + [3529] = { .class_hid = BNXT_ULP_CLASS_HID_255d0, .class_tid = 2, .hdr_sig_id = 10, @@ -71592,7 +73652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3426] = { + [3530] = { .class_hid = BNXT_ULP_CLASS_HID_2ded0, .class_tid = 2, .hdr_sig_id = 10, @@ -71613,7 +73673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3427] = { + [3531] = { .class_hid = BNXT_ULP_CLASS_HID_34bd0, .class_tid = 2, .hdr_sig_id = 10, @@ -71634,7 +73694,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3428] = { + [3532] = { .class_hid = BNXT_ULP_CLASS_HID_39984, .class_tid = 2, .hdr_sig_id = 10, @@ -71656,7 +73716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3429] = { + [3533] = { .class_hid = BNXT_ULP_CLASS_HID_24680, .class_tid = 2, .hdr_sig_id = 10, @@ -71675,7 +73735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3430] = { + [3534] = { .class_hid = BNXT_ULP_CLASS_HID_294b4, .class_tid = 2, .hdr_sig_id = 10, @@ -71695,7 +73755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3431] = { + [3535] = { .class_hid = BNXT_ULP_CLASS_HID_301b4, .class_tid = 2, .hdr_sig_id = 10, @@ -71715,7 +73775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3432] = { + [3536] = { .class_hid = BNXT_ULP_CLASS_HID_38ab4, .class_tid = 2, .hdr_sig_id = 10, @@ -71736,7 +73796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3433] = { + [3537] = { .class_hid = BNXT_ULP_CLASS_HID_23314, .class_tid = 2, .hdr_sig_id = 10, @@ -71754,7 +73814,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3434] = { + [3538] = { .class_hid = BNXT_ULP_CLASS_HID_2bc14, .class_tid = 2, .hdr_sig_id = 10, @@ -71773,7 +73833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3435] = { + [3539] = { .class_hid = BNXT_ULP_CLASS_HID_32914, .class_tid = 2, .hdr_sig_id = 10, @@ -71792,7 +73852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3436] = { + [3540] = { .class_hid = BNXT_ULP_CLASS_HID_3d214, .class_tid = 2, .hdr_sig_id = 10, @@ -71812,7 +73872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3437] = { + [3541] = { .class_hid = BNXT_ULP_CLASS_HID_21e64, .class_tid = 2, .hdr_sig_id = 10, @@ -71831,7 +73891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3438] = { + [3542] = { .class_hid = BNXT_ULP_CLASS_HID_28b64, .class_tid = 2, .hdr_sig_id = 10, @@ -71851,7 +73911,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3439] = { + [3543] = { .class_hid = BNXT_ULP_CLASS_HID_33464, .class_tid = 2, .hdr_sig_id = 10, @@ -71871,7 +73931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3440] = { + [3544] = { .class_hid = BNXT_ULP_CLASS_HID_3a164, .class_tid = 2, .hdr_sig_id = 10, @@ -71892,7 +73952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3441] = { + [3545] = { .class_hid = BNXT_ULP_CLASS_HID_21b18, .class_tid = 2, .hdr_sig_id = 10, @@ -71912,7 +73972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3442] = { + [3546] = { .class_hid = BNXT_ULP_CLASS_HID_28418, .class_tid = 2, .hdr_sig_id = 10, @@ -71933,7 +73993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3443] = { + [3547] = { .class_hid = BNXT_ULP_CLASS_HID_33118, .class_tid = 2, .hdr_sig_id = 10, @@ -71954,7 +74014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3444] = { + [3548] = { .class_hid = BNXT_ULP_CLASS_HID_3ba18, .class_tid = 2, .hdr_sig_id = 10, @@ -71976,7 +74036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3445] = { + [3549] = { .class_hid = BNXT_ULP_CLASS_HID_20fc8, .class_tid = 2, .hdr_sig_id = 10, @@ -71995,7 +74055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3446] = { + [3550] = { .class_hid = BNXT_ULP_CLASS_HID_2b8c8, .class_tid = 2, .hdr_sig_id = 10, @@ -72015,7 +74075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3447] = { + [3551] = { .class_hid = BNXT_ULP_CLASS_HID_325c8, .class_tid = 2, .hdr_sig_id = 10, @@ -72035,7 +74095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3448] = { + [3552] = { .class_hid = BNXT_ULP_CLASS_HID_3aec8, .class_tid = 2, .hdr_sig_id = 10, @@ -72056,7 +74116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3449] = { + [3553] = { .class_hid = BNXT_ULP_CLASS_HID_257a8, .class_tid = 2, .hdr_sig_id = 10, @@ -72075,7 +74135,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3450] = { + [3554] = { .class_hid = BNXT_ULP_CLASS_HID_2c0a8, .class_tid = 2, .hdr_sig_id = 10, @@ -72095,7 +74155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3451] = { + [3555] = { .class_hid = BNXT_ULP_CLASS_HID_34da8, .class_tid = 2, .hdr_sig_id = 10, @@ -72115,7 +74175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3452] = { + [3556] = { .class_hid = BNXT_ULP_CLASS_HID_39b5c, .class_tid = 2, .hdr_sig_id = 10, @@ -72136,7 +74196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3453] = { + [3557] = { .class_hid = BNXT_ULP_CLASS_HID_222f8, .class_tid = 2, .hdr_sig_id = 10, @@ -72156,7 +74216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3454] = { + [3558] = { .class_hid = BNXT_ULP_CLASS_HID_2aff8, .class_tid = 2, .hdr_sig_id = 10, @@ -72177,7 +74237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3455] = { + [3559] = { .class_hid = BNXT_ULP_CLASS_HID_358f8, .class_tid = 2, .hdr_sig_id = 10, @@ -72198,7 +74258,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3456] = { + [3560] = { .class_hid = BNXT_ULP_CLASS_HID_3c5f8, .class_tid = 2, .hdr_sig_id = 10, @@ -72220,7 +74280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3457] = { + [3561] = { .class_hid = BNXT_ULP_CLASS_HID_23fac, .class_tid = 2, .hdr_sig_id = 10, @@ -72241,7 +74301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3458] = { + [3562] = { .class_hid = BNXT_ULP_CLASS_HID_2a8ac, .class_tid = 2, .hdr_sig_id = 10, @@ -72263,7 +74323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3459] = { + [3563] = { .class_hid = BNXT_ULP_CLASS_HID_355ac, .class_tid = 2, .hdr_sig_id = 10, @@ -72285,7 +74345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3460] = { + [3564] = { .class_hid = BNXT_ULP_CLASS_HID_3deac, .class_tid = 2, .hdr_sig_id = 10, @@ -72308,7 +74368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3461] = { + [3565] = { .class_hid = BNXT_ULP_CLASS_HID_2505c, .class_tid = 2, .hdr_sig_id = 10, @@ -72328,7 +74388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3462] = { + [3566] = { .class_hid = BNXT_ULP_CLASS_HID_2dd5c, .class_tid = 2, .hdr_sig_id = 10, @@ -72349,7 +74409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3463] = { + [3567] = { .class_hid = BNXT_ULP_CLASS_HID_3465c, .class_tid = 2, .hdr_sig_id = 10, @@ -72370,7 +74430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3464] = { + [3568] = { .class_hid = BNXT_ULP_CLASS_HID_39410, .class_tid = 2, .hdr_sig_id = 10, @@ -72392,7 +74452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3465] = { + [3569] = { .class_hid = BNXT_ULP_CLASS_HID_223fc, .class_tid = 2, .hdr_sig_id = 10, @@ -72409,7 +74469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3466] = { + [3570] = { .class_hid = BNXT_ULP_CLASS_HID_2acfc, .class_tid = 2, .hdr_sig_id = 10, @@ -72427,7 +74487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3467] = { + [3571] = { .class_hid = BNXT_ULP_CLASS_HID_359fc, .class_tid = 2, .hdr_sig_id = 10, @@ -72445,7 +74505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3468] = { + [3572] = { .class_hid = BNXT_ULP_CLASS_HID_3c2fc, .class_tid = 2, .hdr_sig_id = 10, @@ -72464,7 +74524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3469] = { + [3573] = { .class_hid = BNXT_ULP_CLASS_HID_20ecc, .class_tid = 2, .hdr_sig_id = 10, @@ -72482,7 +74542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3470] = { + [3574] = { .class_hid = BNXT_ULP_CLASS_HID_2bbcc, .class_tid = 2, .hdr_sig_id = 10, @@ -72501,7 +74561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3471] = { + [3575] = { .class_hid = BNXT_ULP_CLASS_HID_324cc, .class_tid = 2, .hdr_sig_id = 10, @@ -72520,7 +74580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3472] = { + [3576] = { .class_hid = BNXT_ULP_CLASS_HID_3d1cc, .class_tid = 2, .hdr_sig_id = 10, @@ -72540,7 +74600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3473] = { + [3577] = { .class_hid = BNXT_ULP_CLASS_HID_20b80, .class_tid = 2, .hdr_sig_id = 10, @@ -72559,7 +74619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3474] = { + [3578] = { .class_hid = BNXT_ULP_CLASS_HID_2b480, .class_tid = 2, .hdr_sig_id = 10, @@ -72579,7 +74639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3475] = { + [3579] = { .class_hid = BNXT_ULP_CLASS_HID_32180, .class_tid = 2, .hdr_sig_id = 10, @@ -72599,7 +74659,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3476] = { + [3580] = { .class_hid = BNXT_ULP_CLASS_HID_3aa80, .class_tid = 2, .hdr_sig_id = 10, @@ -72620,7 +74680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3477] = { + [3581] = { .class_hid = BNXT_ULP_CLASS_HID_23cb0, .class_tid = 2, .hdr_sig_id = 10, @@ -72638,7 +74698,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3478] = { + [3582] = { .class_hid = BNXT_ULP_CLASS_HID_2a9b0, .class_tid = 2, .hdr_sig_id = 10, @@ -72657,7 +74717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3479] = { + [3583] = { .class_hid = BNXT_ULP_CLASS_HID_352b0, .class_tid = 2, .hdr_sig_id = 10, @@ -72676,7 +74736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3480] = { + [3584] = { .class_hid = BNXT_ULP_CLASS_HID_3dfb0, .class_tid = 2, .hdr_sig_id = 10, @@ -72696,7 +74756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3481] = { + [3585] = { .class_hid = BNXT_ULP_CLASS_HID_24410, .class_tid = 2, .hdr_sig_id = 10, @@ -72714,7 +74774,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3482] = { + [3586] = { .class_hid = BNXT_ULP_CLASS_HID_295c4, .class_tid = 2, .hdr_sig_id = 10, @@ -72733,7 +74793,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3483] = { + [3587] = { .class_hid = BNXT_ULP_CLASS_HID_31ec4, .class_tid = 2, .hdr_sig_id = 10, @@ -72752,7 +74812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3484] = { + [3588] = { .class_hid = BNXT_ULP_CLASS_HID_38bc4, .class_tid = 2, .hdr_sig_id = 10, @@ -72772,7 +74832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3485] = { + [3589] = { .class_hid = BNXT_ULP_CLASS_HID_25360, .class_tid = 2, .hdr_sig_id = 10, @@ -72791,7 +74851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3486] = { + [3590] = { .class_hid = BNXT_ULP_CLASS_HID_2dc60, .class_tid = 2, .hdr_sig_id = 10, @@ -72811,7 +74871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3487] = { + [3591] = { .class_hid = BNXT_ULP_CLASS_HID_34960, .class_tid = 2, .hdr_sig_id = 10, @@ -72831,7 +74891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3488] = { + [3592] = { .class_hid = BNXT_ULP_CLASS_HID_39714, .class_tid = 2, .hdr_sig_id = 10, @@ -72852,7 +74912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3489] = { + [3593] = { .class_hid = BNXT_ULP_CLASS_HID_22c14, .class_tid = 2, .hdr_sig_id = 10, @@ -72872,7 +74932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3490] = { + [3594] = { .class_hid = BNXT_ULP_CLASS_HID_2d914, .class_tid = 2, .hdr_sig_id = 10, @@ -72893,7 +74953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3491] = { + [3595] = { .class_hid = BNXT_ULP_CLASS_HID_34214, .class_tid = 2, .hdr_sig_id = 10, @@ -72914,7 +74974,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3492] = { + [3596] = { .class_hid = BNXT_ULP_CLASS_HID_393c8, .class_tid = 2, .hdr_sig_id = 10, @@ -72936,7 +74996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3493] = { + [3597] = { .class_hid = BNXT_ULP_CLASS_HID_240c4, .class_tid = 2, .hdr_sig_id = 10, @@ -72955,7 +75015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3494] = { + [3598] = { .class_hid = BNXT_ULP_CLASS_HID_2cdc4, .class_tid = 2, .hdr_sig_id = 10, @@ -72975,7 +75035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3495] = { + [3599] = { .class_hid = BNXT_ULP_CLASS_HID_31bf8, .class_tid = 2, .hdr_sig_id = 10, @@ -72995,7 +75055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3496] = { + [3600] = { .class_hid = BNXT_ULP_CLASS_HID_384f8, .class_tid = 2, .hdr_sig_id = 10, @@ -73016,7 +75076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3497] = { + [3601] = { .class_hid = BNXT_ULP_CLASS_HID_23dc0, .class_tid = 2, .hdr_sig_id = 10, @@ -73032,7 +75092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3498] = { + [3602] = { .class_hid = BNXT_ULP_CLASS_HID_2a6c0, .class_tid = 2, .hdr_sig_id = 10, @@ -73049,7 +75109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3499] = { + [3603] = { .class_hid = BNXT_ULP_CLASS_HID_353c0, .class_tid = 2, .hdr_sig_id = 10, @@ -73066,7 +75126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3500] = { + [3604] = { .class_hid = BNXT_ULP_CLASS_HID_3dcc0, .class_tid = 2, .hdr_sig_id = 10, @@ -73084,7 +75144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3501] = { + [3605] = { .class_hid = BNXT_ULP_CLASS_HID_20910, .class_tid = 2, .hdr_sig_id = 10, @@ -73101,7 +75161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3502] = { + [3606] = { .class_hid = BNXT_ULP_CLASS_HID_2b210, .class_tid = 2, .hdr_sig_id = 10, @@ -73119,7 +75179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3503] = { + [3607] = { .class_hid = BNXT_ULP_CLASS_HID_33f10, .class_tid = 2, .hdr_sig_id = 10, @@ -73137,7 +75197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3504] = { + [3608] = { .class_hid = BNXT_ULP_CLASS_HID_3a810, .class_tid = 2, .hdr_sig_id = 10, @@ -73156,7 +75216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3505] = { + [3609] = { .class_hid = BNXT_ULP_CLASS_HID_205c4, .class_tid = 2, .hdr_sig_id = 10, @@ -73174,7 +75234,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3506] = { + [3610] = { .class_hid = BNXT_ULP_CLASS_HID_28ec4, .class_tid = 2, .hdr_sig_id = 10, @@ -73193,7 +75253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3507] = { + [3611] = { .class_hid = BNXT_ULP_CLASS_HID_33bc4, .class_tid = 2, .hdr_sig_id = 10, @@ -73212,7 +75272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3508] = { + [3612] = { .class_hid = BNXT_ULP_CLASS_HID_3a4c4, .class_tid = 2, .hdr_sig_id = 10, @@ -73232,7 +75292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3509] = { + [3613] = { .class_hid = BNXT_ULP_CLASS_HID_236f4, .class_tid = 2, .hdr_sig_id = 10, @@ -73249,7 +75309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3510] = { + [3614] = { .class_hid = BNXT_ULP_CLASS_HID_2a3f4, .class_tid = 2, .hdr_sig_id = 10, @@ -73267,7 +75327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3511] = { + [3615] = { .class_hid = BNXT_ULP_CLASS_HID_32cf4, .class_tid = 2, .hdr_sig_id = 10, @@ -73285,7 +75345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3512] = { + [3616] = { .class_hid = BNXT_ULP_CLASS_HID_3d9f4, .class_tid = 2, .hdr_sig_id = 10, @@ -73304,7 +75364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3513] = { + [3617] = { .class_hid = BNXT_ULP_CLASS_HID_25e54, .class_tid = 2, .hdr_sig_id = 10, @@ -73321,7 +75381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3514] = { + [3618] = { .class_hid = BNXT_ULP_CLASS_HID_2cb54, .class_tid = 2, .hdr_sig_id = 10, @@ -73339,7 +75399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3515] = { + [3619] = { .class_hid = BNXT_ULP_CLASS_HID_31908, .class_tid = 2, .hdr_sig_id = 10, @@ -73357,7 +75417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3516] = { + [3620] = { .class_hid = BNXT_ULP_CLASS_HID_38208, .class_tid = 2, .hdr_sig_id = 10, @@ -73376,7 +75436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3517] = { + [3621] = { .class_hid = BNXT_ULP_CLASS_HID_22da4, .class_tid = 2, .hdr_sig_id = 10, @@ -73394,7 +75454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3518] = { + [3622] = { .class_hid = BNXT_ULP_CLASS_HID_2d6a4, .class_tid = 2, .hdr_sig_id = 10, @@ -73413,7 +75473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3519] = { + [3623] = { .class_hid = BNXT_ULP_CLASS_HID_343a4, .class_tid = 2, .hdr_sig_id = 10, @@ -73432,7 +75492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3520] = { + [3624] = { .class_hid = BNXT_ULP_CLASS_HID_39158, .class_tid = 2, .hdr_sig_id = 10, @@ -73452,7 +75512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3521] = { + [3625] = { .class_hid = BNXT_ULP_CLASS_HID_22658, .class_tid = 2, .hdr_sig_id = 10, @@ -73471,7 +75531,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3522] = { + [3626] = { .class_hid = BNXT_ULP_CLASS_HID_2d358, .class_tid = 2, .hdr_sig_id = 10, @@ -73491,7 +75551,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3523] = { + [3627] = { .class_hid = BNXT_ULP_CLASS_HID_35c58, .class_tid = 2, .hdr_sig_id = 10, @@ -73511,7 +75571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3524] = { + [3628] = { .class_hid = BNXT_ULP_CLASS_HID_3c958, .class_tid = 2, .hdr_sig_id = 10, @@ -73532,7 +75592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3525] = { + [3629] = { .class_hid = BNXT_ULP_CLASS_HID_25b08, .class_tid = 2, .hdr_sig_id = 10, @@ -73550,7 +75610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3526] = { + [3630] = { .class_hid = BNXT_ULP_CLASS_HID_2c408, .class_tid = 2, .hdr_sig_id = 10, @@ -73569,7 +75629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3527] = { + [3631] = { .class_hid = BNXT_ULP_CLASS_HID_3123c, .class_tid = 2, .hdr_sig_id = 10, @@ -73588,7 +75648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3528] = { + [3632] = { .class_hid = BNXT_ULP_CLASS_HID_39f3c, .class_tid = 2, .hdr_sig_id = 10, @@ -73608,7 +75668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3529] = { + [3633] = { .class_hid = BNXT_ULP_CLASS_HID_34a8, .class_tid = 2, .hdr_sig_id = 10, @@ -73625,7 +75685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3530] = { + [3634] = { .class_hid = BNXT_ULP_CLASS_HID_3a64, .class_tid = 2, .hdr_sig_id = 10, @@ -73643,7 +75703,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3531] = { + [3635] = { + .class_hid = BNXT_ULP_CLASS_HID_09b4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3636] = { .class_hid = BNXT_ULP_CLASS_HID_5ef8, .class_tid = 2, .hdr_sig_id = 10, @@ -73662,7 +75741,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3532] = { + [3637] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3638] = { .class_hid = BNXT_ULP_CLASS_HID_07c0, .class_tid = 2, .hdr_sig_id = 10, @@ -73681,7 +75780,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3533] = { + [3639] = { + .class_hid = BNXT_ULP_CLASS_HID_1310, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3640] = { .class_hid = BNXT_ULP_CLASS_HID_2854, .class_tid = 2, .hdr_sig_id = 10, @@ -73701,7 +75820,46 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3534] = { + [3641] = { + .class_hid = BNXT_ULP_CLASS_HID_37a4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3642] = { + .class_hid = BNXT_ULP_CLASS_HID_03f8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3643] = { .class_hid = BNXT_ULP_CLASS_HID_593c, .class_tid = 2, .hdr_sig_id = 10, @@ -73719,7 +75877,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3535] = { + [3644] = { + .class_hid = BNXT_ULP_CLASS_HID_240c, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3645] = { .class_hid = BNXT_ULP_CLASS_HID_1e04, .class_tid = 2, .hdr_sig_id = 10, @@ -73737,7 +75914,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3536] = { + [3646] = { + .class_hid = BNXT_ULP_CLASS_HID_48a0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3647] = { .class_hid = BNXT_ULP_CLASS_HID_2298, .class_tid = 2, .hdr_sig_id = 10, @@ -73756,7 +75952,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3537] = { + [3648] = { + .class_hid = BNXT_ULP_CLASS_HID_31e8, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 272, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3649] = { .class_hid = BNXT_ULP_CLASS_HID_24644, .class_tid = 2, .hdr_sig_id = 11, @@ -73775,7 +75991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3538] = { + [3650] = { .class_hid = BNXT_ULP_CLASS_HID_29438, .class_tid = 2, .hdr_sig_id = 11, @@ -73795,7 +76011,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3539] = { + [3651] = { .class_hid = BNXT_ULP_CLASS_HID_30138, .class_tid = 2, .hdr_sig_id = 11, @@ -73815,7 +76031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3540] = { + [3652] = { .class_hid = BNXT_ULP_CLASS_HID_38a38, .class_tid = 2, .hdr_sig_id = 11, @@ -73836,7 +76052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3541] = { + [3653] = { .class_hid = BNXT_ULP_CLASS_HID_25594, .class_tid = 2, .hdr_sig_id = 11, @@ -73856,7 +76072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3542] = { + [3654] = { .class_hid = BNXT_ULP_CLASS_HID_2de94, .class_tid = 2, .hdr_sig_id = 11, @@ -73877,7 +76093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3543] = { + [3655] = { .class_hid = BNXT_ULP_CLASS_HID_34b94, .class_tid = 2, .hdr_sig_id = 11, @@ -73898,7 +76114,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3544] = { + [3656] = { .class_hid = BNXT_ULP_CLASS_HID_39948, .class_tid = 2, .hdr_sig_id = 11, @@ -73920,7 +76136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3545] = { + [3657] = { .class_hid = BNXT_ULP_CLASS_HID_22e48, .class_tid = 2, .hdr_sig_id = 11, @@ -73941,7 +76157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3546] = { + [3658] = { .class_hid = BNXT_ULP_CLASS_HID_2db48, .class_tid = 2, .hdr_sig_id = 11, @@ -73963,7 +76179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3547] = { + [3659] = { .class_hid = BNXT_ULP_CLASS_HID_34448, .class_tid = 2, .hdr_sig_id = 11, @@ -73985,7 +76201,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3548] = { + [3660] = { .class_hid = BNXT_ULP_CLASS_HID_3923c, .class_tid = 2, .hdr_sig_id = 11, @@ -74008,7 +76224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3549] = { + [3661] = { .class_hid = BNXT_ULP_CLASS_HID_24338, .class_tid = 2, .hdr_sig_id = 11, @@ -74028,7 +76244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3550] = { + [3662] = { .class_hid = BNXT_ULP_CLASS_HID_290ec, .class_tid = 2, .hdr_sig_id = 11, @@ -74049,7 +76265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3551] = { + [3663] = { .class_hid = BNXT_ULP_CLASS_HID_31dec, .class_tid = 2, .hdr_sig_id = 11, @@ -74070,7 +76286,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3552] = { + [3664] = { .class_hid = BNXT_ULP_CLASS_HID_386ec, .class_tid = 2, .hdr_sig_id = 11, @@ -74092,7 +76308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3553] = { + [3665] = { .class_hid = BNXT_ULP_CLASS_HID_20f8c, .class_tid = 2, .hdr_sig_id = 11, @@ -74112,7 +76328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3554] = { + [3666] = { .class_hid = BNXT_ULP_CLASS_HID_2b88c, .class_tid = 2, .hdr_sig_id = 11, @@ -74133,7 +76349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3555] = { + [3667] = { .class_hid = BNXT_ULP_CLASS_HID_3258c, .class_tid = 2, .hdr_sig_id = 11, @@ -74154,7 +76370,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3556] = { + [3668] = { .class_hid = BNXT_ULP_CLASS_HID_3ae8c, .class_tid = 2, .hdr_sig_id = 11, @@ -74176,7 +76392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3557] = { + [3669] = { .class_hid = BNXT_ULP_CLASS_HID_21adc, .class_tid = 2, .hdr_sig_id = 11, @@ -74197,7 +76413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3558] = { + [3670] = { .class_hid = BNXT_ULP_CLASS_HID_287dc, .class_tid = 2, .hdr_sig_id = 11, @@ -74219,7 +76435,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3559] = { + [3671] = { .class_hid = BNXT_ULP_CLASS_HID_330dc, .class_tid = 2, .hdr_sig_id = 11, @@ -74241,7 +76457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3560] = { + [3672] = { .class_hid = BNXT_ULP_CLASS_HID_3bddc, .class_tid = 2, .hdr_sig_id = 11, @@ -74264,7 +76480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3561] = { + [3673] = { .class_hid = BNXT_ULP_CLASS_HID_21790, .class_tid = 2, .hdr_sig_id = 11, @@ -74286,7 +76502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3562] = { + [3674] = { .class_hid = BNXT_ULP_CLASS_HID_28090, .class_tid = 2, .hdr_sig_id = 11, @@ -74309,7 +76525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3563] = { + [3675] = { .class_hid = BNXT_ULP_CLASS_HID_30d90, .class_tid = 2, .hdr_sig_id = 11, @@ -74332,7 +76548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3564] = { + [3676] = { .class_hid = BNXT_ULP_CLASS_HID_3b690, .class_tid = 2, .hdr_sig_id = 11, @@ -74356,7 +76572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3565] = { + [3677] = { .class_hid = BNXT_ULP_CLASS_HID_20840, .class_tid = 2, .hdr_sig_id = 11, @@ -74377,7 +76593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3566] = { + [3678] = { .class_hid = BNXT_ULP_CLASS_HID_2b540, .class_tid = 2, .hdr_sig_id = 11, @@ -74399,7 +76615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3567] = { + [3679] = { .class_hid = BNXT_ULP_CLASS_HID_33e40, .class_tid = 2, .hdr_sig_id = 11, @@ -74421,7 +76637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3568] = { + [3680] = { .class_hid = BNXT_ULP_CLASS_HID_3ab40, .class_tid = 2, .hdr_sig_id = 11, @@ -74444,7 +76660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3569] = { + [3681] = { .class_hid = BNXT_ULP_CLASS_HID_253e0, .class_tid = 2, .hdr_sig_id = 11, @@ -74464,7 +76680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3570] = { + [3682] = { .class_hid = BNXT_ULP_CLASS_HID_2dce0, .class_tid = 2, .hdr_sig_id = 11, @@ -74485,7 +76701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3571] = { + [3683] = { .class_hid = BNXT_ULP_CLASS_HID_349e0, .class_tid = 2, .hdr_sig_id = 11, @@ -74506,7 +76722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3572] = { + [3684] = { .class_hid = BNXT_ULP_CLASS_HID_397d4, .class_tid = 2, .hdr_sig_id = 11, @@ -74528,7 +76744,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3573] = { + [3685] = { .class_hid = BNXT_ULP_CLASS_HID_23f30, .class_tid = 2, .hdr_sig_id = 11, @@ -74549,7 +76765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3574] = { + [3686] = { .class_hid = BNXT_ULP_CLASS_HID_2a830, .class_tid = 2, .hdr_sig_id = 11, @@ -74571,7 +76787,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3575] = { + [3687] = { .class_hid = BNXT_ULP_CLASS_HID_35530, .class_tid = 2, .hdr_sig_id = 11, @@ -74593,7 +76809,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3576] = { + [3688] = { .class_hid = BNXT_ULP_CLASS_HID_3de30, .class_tid = 2, .hdr_sig_id = 11, @@ -74616,7 +76832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3577] = { + [3689] = { .class_hid = BNXT_ULP_CLASS_HID_23be4, .class_tid = 2, .hdr_sig_id = 11, @@ -74638,7 +76854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3578] = { + [3690] = { .class_hid = BNXT_ULP_CLASS_HID_2a4e4, .class_tid = 2, .hdr_sig_id = 11, @@ -74661,7 +76877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3579] = { + [3691] = { .class_hid = BNXT_ULP_CLASS_HID_351e4, .class_tid = 2, .hdr_sig_id = 11, @@ -74684,7 +76900,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3580] = { + [3692] = { .class_hid = BNXT_ULP_CLASS_HID_3dae4, .class_tid = 2, .hdr_sig_id = 11, @@ -74708,7 +76924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3581] = { + [3693] = { .class_hid = BNXT_ULP_CLASS_HID_22cd4, .class_tid = 2, .hdr_sig_id = 11, @@ -74729,7 +76945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3582] = { + [3694] = { .class_hid = BNXT_ULP_CLASS_HID_2d9d4, .class_tid = 2, .hdr_sig_id = 11, @@ -74751,7 +76967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3583] = { + [3695] = { .class_hid = BNXT_ULP_CLASS_HID_342d4, .class_tid = 2, .hdr_sig_id = 11, @@ -74773,7 +76989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3584] = { + [3696] = { .class_hid = BNXT_ULP_CLASS_HID_39088, .class_tid = 2, .hdr_sig_id = 11, @@ -74796,7 +77012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3585] = { + [3697] = { .class_hid = BNXT_ULP_CLASS_HID_21928, .class_tid = 2, .hdr_sig_id = 11, @@ -74817,7 +77033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3586] = { + [3698] = { .class_hid = BNXT_ULP_CLASS_HID_28228, .class_tid = 2, .hdr_sig_id = 11, @@ -74839,7 +77055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3587] = { + [3699] = { .class_hid = BNXT_ULP_CLASS_HID_30f28, .class_tid = 2, .hdr_sig_id = 11, @@ -74861,7 +77077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3588] = { + [3700] = { .class_hid = BNXT_ULP_CLASS_HID_3b828, .class_tid = 2, .hdr_sig_id = 11, @@ -74884,7 +77100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3589] = { + [3701] = { .class_hid = BNXT_ULP_CLASS_HID_24384, .class_tid = 2, .hdr_sig_id = 11, @@ -74906,7 +77122,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3590] = { + [3702] = { .class_hid = BNXT_ULP_CLASS_HID_29178, .class_tid = 2, .hdr_sig_id = 11, @@ -74929,7 +77145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3591] = { + [3703] = { .class_hid = BNXT_ULP_CLASS_HID_31a78, .class_tid = 2, .hdr_sig_id = 11, @@ -74952,7 +77168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3592] = { + [3704] = { .class_hid = BNXT_ULP_CLASS_HID_38778, .class_tid = 2, .hdr_sig_id = 11, @@ -74976,7 +77192,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3593] = { + [3705] = { .class_hid = BNXT_ULP_CLASS_HID_25c78, .class_tid = 2, .hdr_sig_id = 11, @@ -74999,7 +77215,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3594] = { + [3706] = { .class_hid = BNXT_ULP_CLASS_HID_2c978, .class_tid = 2, .hdr_sig_id = 11, @@ -75023,7 +77239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3595] = { + [3707] = { .class_hid = BNXT_ULP_CLASS_HID_3172c, .class_tid = 2, .hdr_sig_id = 11, @@ -75047,7 +77263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3596] = { + [3708] = { .class_hid = BNXT_ULP_CLASS_HID_3802c, .class_tid = 2, .hdr_sig_id = 11, @@ -75072,7 +77288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3597] = { + [3709] = { .class_hid = BNXT_ULP_CLASS_HID_2121c, .class_tid = 2, .hdr_sig_id = 11, @@ -75094,7 +77310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3598] = { + [3710] = { .class_hid = BNXT_ULP_CLASS_HID_29f1c, .class_tid = 2, .hdr_sig_id = 11, @@ -75117,7 +77333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3599] = { + [3711] = { .class_hid = BNXT_ULP_CLASS_HID_3081c, .class_tid = 2, .hdr_sig_id = 11, @@ -75140,7 +77356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3600] = { + [3712] = { .class_hid = BNXT_ULP_CLASS_HID_3b51c, .class_tid = 2, .hdr_sig_id = 11, @@ -75164,7 +77380,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3601] = { + [3713] = { .class_hid = BNXT_ULP_CLASS_HID_24088, .class_tid = 2, .hdr_sig_id = 11, @@ -75182,7 +77398,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3602] = { + [3714] = { .class_hid = BNXT_ULP_CLASS_HID_2cd88, .class_tid = 2, .hdr_sig_id = 11, @@ -75201,7 +77417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3603] = { + [3715] = { .class_hid = BNXT_ULP_CLASS_HID_31b7c, .class_tid = 2, .hdr_sig_id = 11, @@ -75220,7 +77436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3604] = { + [3716] = { .class_hid = BNXT_ULP_CLASS_HID_3847c, .class_tid = 2, .hdr_sig_id = 11, @@ -75240,7 +77456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3605] = { + [3717] = { .class_hid = BNXT_ULP_CLASS_HID_22fd8, .class_tid = 2, .hdr_sig_id = 11, @@ -75259,7 +77475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3606] = { + [3718] = { .class_hid = BNXT_ULP_CLASS_HID_2d8d8, .class_tid = 2, .hdr_sig_id = 11, @@ -75279,7 +77495,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3607] = { + [3719] = { .class_hid = BNXT_ULP_CLASS_HID_345d8, .class_tid = 2, .hdr_sig_id = 11, @@ -75299,7 +77515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3608] = { + [3720] = { .class_hid = BNXT_ULP_CLASS_HID_3938c, .class_tid = 2, .hdr_sig_id = 11, @@ -75320,7 +77536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3609] = { + [3721] = { .class_hid = BNXT_ULP_CLASS_HID_2288c, .class_tid = 2, .hdr_sig_id = 11, @@ -75340,7 +77556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3610] = { + [3722] = { .class_hid = BNXT_ULP_CLASS_HID_2d58c, .class_tid = 2, .hdr_sig_id = 11, @@ -75361,7 +77577,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3611] = { + [3723] = { .class_hid = BNXT_ULP_CLASS_HID_35e8c, .class_tid = 2, .hdr_sig_id = 11, @@ -75382,7 +77598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3612] = { + [3724] = { .class_hid = BNXT_ULP_CLASS_HID_3cb8c, .class_tid = 2, .hdr_sig_id = 11, @@ -75404,7 +77620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3613] = { + [3725] = { .class_hid = BNXT_ULP_CLASS_HID_25d7c, .class_tid = 2, .hdr_sig_id = 11, @@ -75423,7 +77639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3614] = { + [3726] = { .class_hid = BNXT_ULP_CLASS_HID_2c67c, .class_tid = 2, .hdr_sig_id = 11, @@ -75443,7 +77659,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3615] = { + [3727] = { .class_hid = BNXT_ULP_CLASS_HID_31430, .class_tid = 2, .hdr_sig_id = 11, @@ -75463,7 +77679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3616] = { + [3728] = { .class_hid = BNXT_ULP_CLASS_HID_38130, .class_tid = 2, .hdr_sig_id = 11, @@ -75484,7 +77700,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3617] = { + [3729] = { .class_hid = BNXT_ULP_CLASS_HID_209d0, .class_tid = 2, .hdr_sig_id = 11, @@ -75503,7 +77719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3618] = { + [3730] = { .class_hid = BNXT_ULP_CLASS_HID_2b2d0, .class_tid = 2, .hdr_sig_id = 11, @@ -75523,7 +77739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3619] = { + [3731] = { .class_hid = BNXT_ULP_CLASS_HID_33fd0, .class_tid = 2, .hdr_sig_id = 11, @@ -75543,7 +77759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3620] = { + [3732] = { .class_hid = BNXT_ULP_CLASS_HID_3a8d0, .class_tid = 2, .hdr_sig_id = 11, @@ -75564,7 +77780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3621] = { + [3733] = { .class_hid = BNXT_ULP_CLASS_HID_214e0, .class_tid = 2, .hdr_sig_id = 11, @@ -75584,7 +77800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3622] = { + [3734] = { .class_hid = BNXT_ULP_CLASS_HID_281e0, .class_tid = 2, .hdr_sig_id = 11, @@ -75605,7 +77821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3623] = { + [3735] = { .class_hid = BNXT_ULP_CLASS_HID_30ae0, .class_tid = 2, .hdr_sig_id = 11, @@ -75626,7 +77842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3624] = { + [3736] = { .class_hid = BNXT_ULP_CLASS_HID_3b7e0, .class_tid = 2, .hdr_sig_id = 11, @@ -75648,7 +77864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3625] = { + [3737] = { .class_hid = BNXT_ULP_CLASS_HID_211d4, .class_tid = 2, .hdr_sig_id = 11, @@ -75669,7 +77885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3626] = { + [3738] = { .class_hid = BNXT_ULP_CLASS_HID_29ad4, .class_tid = 2, .hdr_sig_id = 11, @@ -75691,7 +77907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3627] = { + [3739] = { .class_hid = BNXT_ULP_CLASS_HID_307d4, .class_tid = 2, .hdr_sig_id = 11, @@ -75713,7 +77929,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3628] = { + [3740] = { .class_hid = BNXT_ULP_CLASS_HID_3b0d4, .class_tid = 2, .hdr_sig_id = 11, @@ -75736,7 +77952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3629] = { + [3741] = { .class_hid = BNXT_ULP_CLASS_HID_20284, .class_tid = 2, .hdr_sig_id = 11, @@ -75756,7 +77972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3630] = { + [3742] = { .class_hid = BNXT_ULP_CLASS_HID_28f84, .class_tid = 2, .hdr_sig_id = 11, @@ -75777,7 +77993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3631] = { + [3743] = { .class_hid = BNXT_ULP_CLASS_HID_33884, .class_tid = 2, .hdr_sig_id = 11, @@ -75798,7 +78014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3632] = { + [3744] = { .class_hid = BNXT_ULP_CLASS_HID_3a584, .class_tid = 2, .hdr_sig_id = 11, @@ -75820,7 +78036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3633] = { + [3745] = { .class_hid = BNXT_ULP_CLASS_HID_22a24, .class_tid = 2, .hdr_sig_id = 11, @@ -75839,7 +78055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3634] = { + [3746] = { .class_hid = BNXT_ULP_CLASS_HID_2d724, .class_tid = 2, .hdr_sig_id = 11, @@ -75859,7 +78075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3635] = { + [3747] = { .class_hid = BNXT_ULP_CLASS_HID_34024, .class_tid = 2, .hdr_sig_id = 11, @@ -75879,7 +78095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3636] = { + [3748] = { .class_hid = BNXT_ULP_CLASS_HID_3cd24, .class_tid = 2, .hdr_sig_id = 11, @@ -75900,7 +78116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3637] = { + [3749] = { .class_hid = BNXT_ULP_CLASS_HID_23974, .class_tid = 2, .hdr_sig_id = 11, @@ -75920,7 +78136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3638] = { + [3750] = { .class_hid = BNXT_ULP_CLASS_HID_2a274, .class_tid = 2, .hdr_sig_id = 11, @@ -75941,7 +78157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3639] = { + [3751] = { .class_hid = BNXT_ULP_CLASS_HID_32f74, .class_tid = 2, .hdr_sig_id = 11, @@ -75962,7 +78178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3640] = { + [3752] = { .class_hid = BNXT_ULP_CLASS_HID_3d874, .class_tid = 2, .hdr_sig_id = 11, @@ -75984,7 +78200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3641] = { + [3753] = { .class_hid = BNXT_ULP_CLASS_HID_23228, .class_tid = 2, .hdr_sig_id = 11, @@ -76005,7 +78221,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3642] = { + [3754] = { .class_hid = BNXT_ULP_CLASS_HID_2bf28, .class_tid = 2, .hdr_sig_id = 11, @@ -76027,7 +78243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3643] = { + [3755] = { .class_hid = BNXT_ULP_CLASS_HID_32828, .class_tid = 2, .hdr_sig_id = 11, @@ -76049,7 +78265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3644] = { + [3756] = { .class_hid = BNXT_ULP_CLASS_HID_3d528, .class_tid = 2, .hdr_sig_id = 11, @@ -76072,7 +78288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3645] = { + [3757] = { .class_hid = BNXT_ULP_CLASS_HID_22718, .class_tid = 2, .hdr_sig_id = 11, @@ -76092,7 +78308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3646] = { + [3758] = { .class_hid = BNXT_ULP_CLASS_HID_2d018, .class_tid = 2, .hdr_sig_id = 11, @@ -76113,7 +78329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3647] = { + [3759] = { .class_hid = BNXT_ULP_CLASS_HID_35d18, .class_tid = 2, .hdr_sig_id = 11, @@ -76134,7 +78350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3648] = { + [3760] = { .class_hid = BNXT_ULP_CLASS_HID_3c618, .class_tid = 2, .hdr_sig_id = 11, @@ -76156,7 +78372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3649] = { + [3761] = { .class_hid = BNXT_ULP_CLASS_HID_2136c, .class_tid = 2, .hdr_sig_id = 11, @@ -76176,7 +78392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3650] = { + [3762] = { .class_hid = BNXT_ULP_CLASS_HID_29c6c, .class_tid = 2, .hdr_sig_id = 11, @@ -76197,7 +78413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3651] = { + [3763] = { .class_hid = BNXT_ULP_CLASS_HID_3096c, .class_tid = 2, .hdr_sig_id = 11, @@ -76218,7 +78434,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3652] = { + [3764] = { .class_hid = BNXT_ULP_CLASS_HID_3b26c, .class_tid = 2, .hdr_sig_id = 11, @@ -76240,7 +78456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3653] = { + [3765] = { .class_hid = BNXT_ULP_CLASS_HID_25dc8, .class_tid = 2, .hdr_sig_id = 11, @@ -76261,7 +78477,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3654] = { + [3766] = { .class_hid = BNXT_ULP_CLASS_HID_2c6c8, .class_tid = 2, .hdr_sig_id = 11, @@ -76283,7 +78499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3655] = { + [3767] = { .class_hid = BNXT_ULP_CLASS_HID_314bc, .class_tid = 2, .hdr_sig_id = 11, @@ -76305,7 +78521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3656] = { + [3768] = { .class_hid = BNXT_ULP_CLASS_HID_381bc, .class_tid = 2, .hdr_sig_id = 11, @@ -76328,7 +78544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3657] = { + [3769] = { .class_hid = BNXT_ULP_CLASS_HID_256bc, .class_tid = 2, .hdr_sig_id = 11, @@ -76350,7 +78566,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3658] = { + [3770] = { .class_hid = BNXT_ULP_CLASS_HID_2c3bc, .class_tid = 2, .hdr_sig_id = 11, @@ -76373,7 +78589,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3659] = { + [3771] = { .class_hid = BNXT_ULP_CLASS_HID_31170, .class_tid = 2, .hdr_sig_id = 11, @@ -76396,7 +78612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3660] = { + [3772] = { .class_hid = BNXT_ULP_CLASS_HID_39a70, .class_tid = 2, .hdr_sig_id = 11, @@ -76420,7 +78636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3661] = { + [3773] = { .class_hid = BNXT_ULP_CLASS_HID_24b6c, .class_tid = 2, .hdr_sig_id = 11, @@ -76441,7 +78657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3662] = { + [3774] = { .class_hid = BNXT_ULP_CLASS_HID_29920, .class_tid = 2, .hdr_sig_id = 11, @@ -76463,7 +78679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3663] = { + [3775] = { .class_hid = BNXT_ULP_CLASS_HID_30220, .class_tid = 2, .hdr_sig_id = 11, @@ -76485,7 +78701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3664] = { + [3776] = { .class_hid = BNXT_ULP_CLASS_HID_38f20, .class_tid = 2, .hdr_sig_id = 11, @@ -76508,7 +78724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3665] = { + [3777] = { .class_hid = BNXT_ULP_CLASS_HID_22f54, .class_tid = 2, .hdr_sig_id = 11, @@ -76526,7 +78742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3666] = { + [3778] = { .class_hid = BNXT_ULP_CLASS_HID_2d854, .class_tid = 2, .hdr_sig_id = 11, @@ -76545,7 +78761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3667] = { + [3779] = { .class_hid = BNXT_ULP_CLASS_HID_34554, .class_tid = 2, .hdr_sig_id = 11, @@ -76564,7 +78780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3668] = { + [3780] = { .class_hid = BNXT_ULP_CLASS_HID_39308, .class_tid = 2, .hdr_sig_id = 11, @@ -76584,7 +78800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3669] = { + [3781] = { .class_hid = BNXT_ULP_CLASS_HID_23a64, .class_tid = 2, .hdr_sig_id = 11, @@ -76603,7 +78819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3670] = { + [3782] = { .class_hid = BNXT_ULP_CLASS_HID_2a764, .class_tid = 2, .hdr_sig_id = 11, @@ -76623,7 +78839,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3671] = { + [3783] = { .class_hid = BNXT_ULP_CLASS_HID_35064, .class_tid = 2, .hdr_sig_id = 11, @@ -76643,7 +78859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3672] = { + [3784] = { .class_hid = BNXT_ULP_CLASS_HID_3dd64, .class_tid = 2, .hdr_sig_id = 11, @@ -76664,7 +78880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3673] = { + [3785] = { .class_hid = BNXT_ULP_CLASS_HID_23758, .class_tid = 2, .hdr_sig_id = 11, @@ -76684,7 +78900,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3674] = { + [3786] = { .class_hid = BNXT_ULP_CLASS_HID_2a058, .class_tid = 2, .hdr_sig_id = 11, @@ -76705,7 +78921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3675] = { + [3787] = { .class_hid = BNXT_ULP_CLASS_HID_32d58, .class_tid = 2, .hdr_sig_id = 11, @@ -76726,7 +78942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3676] = { + [3788] = { .class_hid = BNXT_ULP_CLASS_HID_3d658, .class_tid = 2, .hdr_sig_id = 11, @@ -76748,7 +78964,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3677] = { + [3789] = { .class_hid = BNXT_ULP_CLASS_HID_22808, .class_tid = 2, .hdr_sig_id = 11, @@ -76767,7 +78983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3678] = { + [3790] = { .class_hid = BNXT_ULP_CLASS_HID_2d508, .class_tid = 2, .hdr_sig_id = 11, @@ -76787,7 +79003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3679] = { + [3791] = { .class_hid = BNXT_ULP_CLASS_HID_35e08, .class_tid = 2, .hdr_sig_id = 11, @@ -76807,7 +79023,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3680] = { + [3792] = { .class_hid = BNXT_ULP_CLASS_HID_3cb08, .class_tid = 2, .hdr_sig_id = 11, @@ -76828,7 +79044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3681] = { + [3793] = { .class_hid = BNXT_ULP_CLASS_HID_2149c, .class_tid = 2, .hdr_sig_id = 11, @@ -76847,7 +79063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3682] = { + [3794] = { .class_hid = BNXT_ULP_CLASS_HID_2819c, .class_tid = 2, .hdr_sig_id = 11, @@ -76867,7 +79083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3683] = { + [3795] = { .class_hid = BNXT_ULP_CLASS_HID_30a9c, .class_tid = 2, .hdr_sig_id = 11, @@ -76887,7 +79103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3684] = { + [3796] = { .class_hid = BNXT_ULP_CLASS_HID_3b79c, .class_tid = 2, .hdr_sig_id = 11, @@ -76908,7 +79124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3685] = { + [3797] = { .class_hid = BNXT_ULP_CLASS_HID_25ef8, .class_tid = 2, .hdr_sig_id = 11, @@ -76928,7 +79144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3686] = { + [3798] = { .class_hid = BNXT_ULP_CLASS_HID_2cbf8, .class_tid = 2, .hdr_sig_id = 11, @@ -76949,7 +79165,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3687] = { + [3799] = { .class_hid = BNXT_ULP_CLASS_HID_319ac, .class_tid = 2, .hdr_sig_id = 11, @@ -76970,7 +79186,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3688] = { + [3800] = { .class_hid = BNXT_ULP_CLASS_HID_382ac, .class_tid = 2, .hdr_sig_id = 11, @@ -76992,7 +79208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3689] = { + [3801] = { .class_hid = BNXT_ULP_CLASS_HID_25bac, .class_tid = 2, .hdr_sig_id = 11, @@ -77013,7 +79229,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3690] = { + [3802] = { .class_hid = BNXT_ULP_CLASS_HID_2c4ac, .class_tid = 2, .hdr_sig_id = 11, @@ -77035,7 +79251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3691] = { + [3803] = { .class_hid = BNXT_ULP_CLASS_HID_31260, .class_tid = 2, .hdr_sig_id = 11, @@ -77057,7 +79273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3692] = { + [3804] = { .class_hid = BNXT_ULP_CLASS_HID_39f60, .class_tid = 2, .hdr_sig_id = 11, @@ -77080,7 +79296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3693] = { + [3805] = { .class_hid = BNXT_ULP_CLASS_HID_21150, .class_tid = 2, .hdr_sig_id = 11, @@ -77100,7 +79316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3694] = { + [3806] = { .class_hid = BNXT_ULP_CLASS_HID_29a50, .class_tid = 2, .hdr_sig_id = 11, @@ -77121,7 +79337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3695] = { + [3807] = { .class_hid = BNXT_ULP_CLASS_HID_30750, .class_tid = 2, .hdr_sig_id = 11, @@ -77142,7 +79358,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3696] = { + [3808] = { .class_hid = BNXT_ULP_CLASS_HID_3b050, .class_tid = 2, .hdr_sig_id = 11, @@ -77164,7 +79380,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3697] = { + [3809] = { .class_hid = BNXT_ULP_CLASS_HID_238f0, .class_tid = 2, .hdr_sig_id = 11, @@ -77183,7 +79399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3698] = { + [3810] = { .class_hid = BNXT_ULP_CLASS_HID_2a5f0, .class_tid = 2, .hdr_sig_id = 11, @@ -77203,7 +79419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3699] = { + [3811] = { .class_hid = BNXT_ULP_CLASS_HID_32ef0, .class_tid = 2, .hdr_sig_id = 11, @@ -77223,7 +79439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3700] = { + [3812] = { .class_hid = BNXT_ULP_CLASS_HID_3dbf0, .class_tid = 2, .hdr_sig_id = 11, @@ -77244,7 +79460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3701] = { + [3813] = { .class_hid = BNXT_ULP_CLASS_HID_20400, .class_tid = 2, .hdr_sig_id = 11, @@ -77264,7 +79480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3702] = { + [3814] = { .class_hid = BNXT_ULP_CLASS_HID_2b100, .class_tid = 2, .hdr_sig_id = 11, @@ -77285,7 +79501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3703] = { + [3815] = { .class_hid = BNXT_ULP_CLASS_HID_33a00, .class_tid = 2, .hdr_sig_id = 11, @@ -77306,7 +79522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3704] = { + [3816] = { .class_hid = BNXT_ULP_CLASS_HID_3a700, .class_tid = 2, .hdr_sig_id = 11, @@ -77328,7 +79544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3705] = { + [3817] = { .class_hid = BNXT_ULP_CLASS_HID_200f4, .class_tid = 2, .hdr_sig_id = 11, @@ -77349,7 +79565,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3706] = { + [3818] = { .class_hid = BNXT_ULP_CLASS_HID_28df4, .class_tid = 2, .hdr_sig_id = 11, @@ -77371,7 +79587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3707] = { + [3819] = { .class_hid = BNXT_ULP_CLASS_HID_336f4, .class_tid = 2, .hdr_sig_id = 11, @@ -77393,7 +79609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3708] = { + [3820] = { .class_hid = BNXT_ULP_CLASS_HID_3a3f4, .class_tid = 2, .hdr_sig_id = 11, @@ -77416,7 +79632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3709] = { + [3821] = { .class_hid = BNXT_ULP_CLASS_HID_235a4, .class_tid = 2, .hdr_sig_id = 11, @@ -77436,7 +79652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3710] = { + [3822] = { .class_hid = BNXT_ULP_CLASS_HID_2bea4, .class_tid = 2, .hdr_sig_id = 11, @@ -77457,7 +79673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3711] = { + [3823] = { .class_hid = BNXT_ULP_CLASS_HID_32ba4, .class_tid = 2, .hdr_sig_id = 11, @@ -77478,7 +79694,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3712] = { + [3824] = { .class_hid = BNXT_ULP_CLASS_HID_3d4a4, .class_tid = 2, .hdr_sig_id = 11, @@ -77500,7 +79716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3713] = { + [3825] = { .class_hid = BNXT_ULP_CLASS_HID_25d44, .class_tid = 2, .hdr_sig_id = 11, @@ -77520,7 +79736,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3714] = { + [3826] = { .class_hid = BNXT_ULP_CLASS_HID_2c644, .class_tid = 2, .hdr_sig_id = 11, @@ -77541,7 +79757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3715] = { + [3827] = { .class_hid = BNXT_ULP_CLASS_HID_31438, .class_tid = 2, .hdr_sig_id = 11, @@ -77562,7 +79778,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3716] = { + [3828] = { .class_hid = BNXT_ULP_CLASS_HID_38138, .class_tid = 2, .hdr_sig_id = 11, @@ -77584,7 +79800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3717] = { + [3829] = { .class_hid = BNXT_ULP_CLASS_HID_22894, .class_tid = 2, .hdr_sig_id = 11, @@ -77605,7 +79821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3718] = { + [3830] = { .class_hid = BNXT_ULP_CLASS_HID_2d594, .class_tid = 2, .hdr_sig_id = 11, @@ -77627,7 +79843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3719] = { + [3831] = { .class_hid = BNXT_ULP_CLASS_HID_35e94, .class_tid = 2, .hdr_sig_id = 11, @@ -77649,7 +79865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3720] = { + [3832] = { .class_hid = BNXT_ULP_CLASS_HID_3cb94, .class_tid = 2, .hdr_sig_id = 11, @@ -77672,7 +79888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3721] = { + [3833] = { .class_hid = BNXT_ULP_CLASS_HID_22548, .class_tid = 2, .hdr_sig_id = 11, @@ -77694,7 +79910,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3722] = { + [3834] = { .class_hid = BNXT_ULP_CLASS_HID_2ae48, .class_tid = 2, .hdr_sig_id = 11, @@ -77717,7 +79933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3723] = { + [3835] = { .class_hid = BNXT_ULP_CLASS_HID_35b48, .class_tid = 2, .hdr_sig_id = 11, @@ -77740,7 +79956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3724] = { + [3836] = { .class_hid = BNXT_ULP_CLASS_HID_3c448, .class_tid = 2, .hdr_sig_id = 11, @@ -77764,7 +79980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3725] = { + [3837] = { .class_hid = BNXT_ULP_CLASS_HID_25638, .class_tid = 2, .hdr_sig_id = 11, @@ -77785,7 +80001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3726] = { + [3838] = { .class_hid = BNXT_ULP_CLASS_HID_2c338, .class_tid = 2, .hdr_sig_id = 11, @@ -77807,7 +80023,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3727] = { + [3839] = { .class_hid = BNXT_ULP_CLASS_HID_310ec, .class_tid = 2, .hdr_sig_id = 11, @@ -77829,7 +80045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3728] = { + [3840] = { .class_hid = BNXT_ULP_CLASS_HID_39dec, .class_tid = 2, .hdr_sig_id = 11, @@ -77852,7 +80068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3729] = { + [3841] = { .class_hid = BNXT_ULP_CLASS_HID_22998, .class_tid = 2, .hdr_sig_id = 11, @@ -77869,7 +80085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3730] = { + [3842] = { .class_hid = BNXT_ULP_CLASS_HID_2d298, .class_tid = 2, .hdr_sig_id = 11, @@ -77887,7 +80103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3731] = { + [3843] = { .class_hid = BNXT_ULP_CLASS_HID_35f98, .class_tid = 2, .hdr_sig_id = 11, @@ -77905,7 +80121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3732] = { + [3844] = { .class_hid = BNXT_ULP_CLASS_HID_3c898, .class_tid = 2, .hdr_sig_id = 11, @@ -77924,7 +80140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3733] = { + [3845] = { .class_hid = BNXT_ULP_CLASS_HID_234a8, .class_tid = 2, .hdr_sig_id = 11, @@ -77942,7 +80158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3734] = { + [3846] = { .class_hid = BNXT_ULP_CLASS_HID_2a1a8, .class_tid = 2, .hdr_sig_id = 11, @@ -77961,7 +80177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3735] = { + [3847] = { .class_hid = BNXT_ULP_CLASS_HID_32aa8, .class_tid = 2, .hdr_sig_id = 11, @@ -77980,7 +80196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3736] = { + [3848] = { .class_hid = BNXT_ULP_CLASS_HID_3d7a8, .class_tid = 2, .hdr_sig_id = 11, @@ -78000,7 +80216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3737] = { + [3849] = { .class_hid = BNXT_ULP_CLASS_HID_2319c, .class_tid = 2, .hdr_sig_id = 11, @@ -78019,7 +80235,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3738] = { + [3850] = { .class_hid = BNXT_ULP_CLASS_HID_2ba9c, .class_tid = 2, .hdr_sig_id = 11, @@ -78039,7 +80255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3739] = { + [3851] = { .class_hid = BNXT_ULP_CLASS_HID_3279c, .class_tid = 2, .hdr_sig_id = 11, @@ -78059,7 +80275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3740] = { + [3852] = { .class_hid = BNXT_ULP_CLASS_HID_3d09c, .class_tid = 2, .hdr_sig_id = 11, @@ -78080,7 +80296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3741] = { + [3853] = { .class_hid = BNXT_ULP_CLASS_HID_2224c, .class_tid = 2, .hdr_sig_id = 11, @@ -78098,7 +80314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3742] = { + [3854] = { .class_hid = BNXT_ULP_CLASS_HID_2af4c, .class_tid = 2, .hdr_sig_id = 11, @@ -78117,7 +80333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3743] = { + [3855] = { .class_hid = BNXT_ULP_CLASS_HID_3584c, .class_tid = 2, .hdr_sig_id = 11, @@ -78136,7 +80352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3744] = { + [3856] = { .class_hid = BNXT_ULP_CLASS_HID_3c54c, .class_tid = 2, .hdr_sig_id = 11, @@ -78156,7 +80372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3745] = { + [3857] = { .class_hid = BNXT_ULP_CLASS_HID_24dec, .class_tid = 2, .hdr_sig_id = 11, @@ -78174,7 +80390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3746] = { + [3858] = { .class_hid = BNXT_ULP_CLASS_HID_29ba0, .class_tid = 2, .hdr_sig_id = 11, @@ -78193,7 +80409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3747] = { + [3859] = { .class_hid = BNXT_ULP_CLASS_HID_304a0, .class_tid = 2, .hdr_sig_id = 11, @@ -78212,7 +80428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3748] = { + [3860] = { .class_hid = BNXT_ULP_CLASS_HID_3b1a0, .class_tid = 2, .hdr_sig_id = 11, @@ -78232,7 +80448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3749] = { + [3861] = { .class_hid = BNXT_ULP_CLASS_HID_2593c, .class_tid = 2, .hdr_sig_id = 11, @@ -78251,7 +80467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3750] = { + [3862] = { .class_hid = BNXT_ULP_CLASS_HID_2c23c, .class_tid = 2, .hdr_sig_id = 11, @@ -78271,7 +80487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3751] = { + [3863] = { .class_hid = BNXT_ULP_CLASS_HID_313f0, .class_tid = 2, .hdr_sig_id = 11, @@ -78291,7 +80507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3752] = { + [3864] = { .class_hid = BNXT_ULP_CLASS_HID_39cf0, .class_tid = 2, .hdr_sig_id = 11, @@ -78312,7 +80528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3753] = { + [3865] = { .class_hid = BNXT_ULP_CLASS_HID_255f0, .class_tid = 2, .hdr_sig_id = 11, @@ -78332,7 +80548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3754] = { + [3866] = { .class_hid = BNXT_ULP_CLASS_HID_2def0, .class_tid = 2, .hdr_sig_id = 11, @@ -78353,7 +80569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3755] = { + [3867] = { .class_hid = BNXT_ULP_CLASS_HID_34bf0, .class_tid = 2, .hdr_sig_id = 11, @@ -78374,7 +80590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3756] = { + [3868] = { .class_hid = BNXT_ULP_CLASS_HID_399a4, .class_tid = 2, .hdr_sig_id = 11, @@ -78396,7 +80612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3757] = { + [3869] = { .class_hid = BNXT_ULP_CLASS_HID_246a0, .class_tid = 2, .hdr_sig_id = 11, @@ -78415,7 +80631,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3758] = { + [3870] = { .class_hid = BNXT_ULP_CLASS_HID_29494, .class_tid = 2, .hdr_sig_id = 11, @@ -78435,7 +80651,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3759] = { + [3871] = { .class_hid = BNXT_ULP_CLASS_HID_30194, .class_tid = 2, .hdr_sig_id = 11, @@ -78455,7 +80671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3760] = { + [3872] = { .class_hid = BNXT_ULP_CLASS_HID_38a94, .class_tid = 2, .hdr_sig_id = 11, @@ -78476,7 +80692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3761] = { + [3873] = { .class_hid = BNXT_ULP_CLASS_HID_23334, .class_tid = 2, .hdr_sig_id = 11, @@ -78494,7 +80710,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3762] = { + [3874] = { .class_hid = BNXT_ULP_CLASS_HID_2bc34, .class_tid = 2, .hdr_sig_id = 11, @@ -78513,7 +80729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3763] = { + [3875] = { .class_hid = BNXT_ULP_CLASS_HID_32934, .class_tid = 2, .hdr_sig_id = 11, @@ -78532,7 +80748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3764] = { + [3876] = { .class_hid = BNXT_ULP_CLASS_HID_3d234, .class_tid = 2, .hdr_sig_id = 11, @@ -78552,7 +80768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3765] = { + [3877] = { .class_hid = BNXT_ULP_CLASS_HID_21e44, .class_tid = 2, .hdr_sig_id = 11, @@ -78571,7 +80787,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3766] = { + [3878] = { .class_hid = BNXT_ULP_CLASS_HID_28b44, .class_tid = 2, .hdr_sig_id = 11, @@ -78591,7 +80807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3767] = { + [3879] = { .class_hid = BNXT_ULP_CLASS_HID_33444, .class_tid = 2, .hdr_sig_id = 11, @@ -78611,7 +80827,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3768] = { + [3880] = { .class_hid = BNXT_ULP_CLASS_HID_3a144, .class_tid = 2, .hdr_sig_id = 11, @@ -78632,7 +80848,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3769] = { + [3881] = { .class_hid = BNXT_ULP_CLASS_HID_21b38, .class_tid = 2, .hdr_sig_id = 11, @@ -78652,7 +80868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3770] = { + [3882] = { .class_hid = BNXT_ULP_CLASS_HID_28438, .class_tid = 2, .hdr_sig_id = 11, @@ -78673,7 +80889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3771] = { + [3883] = { .class_hid = BNXT_ULP_CLASS_HID_33138, .class_tid = 2, .hdr_sig_id = 11, @@ -78694,7 +80910,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3772] = { + [3884] = { .class_hid = BNXT_ULP_CLASS_HID_3ba38, .class_tid = 2, .hdr_sig_id = 11, @@ -78716,7 +80932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3773] = { + [3885] = { .class_hid = BNXT_ULP_CLASS_HID_20fe8, .class_tid = 2, .hdr_sig_id = 11, @@ -78735,7 +80951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3774] = { + [3886] = { .class_hid = BNXT_ULP_CLASS_HID_2b8e8, .class_tid = 2, .hdr_sig_id = 11, @@ -78755,7 +80971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3775] = { + [3887] = { .class_hid = BNXT_ULP_CLASS_HID_325e8, .class_tid = 2, .hdr_sig_id = 11, @@ -78775,7 +80991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3776] = { + [3888] = { .class_hid = BNXT_ULP_CLASS_HID_3aee8, .class_tid = 2, .hdr_sig_id = 11, @@ -78796,7 +81012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3777] = { + [3889] = { .class_hid = BNXT_ULP_CLASS_HID_25788, .class_tid = 2, .hdr_sig_id = 11, @@ -78815,7 +81031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3778] = { + [3890] = { .class_hid = BNXT_ULP_CLASS_HID_2c088, .class_tid = 2, .hdr_sig_id = 11, @@ -78835,7 +81051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3779] = { + [3891] = { .class_hid = BNXT_ULP_CLASS_HID_34d88, .class_tid = 2, .hdr_sig_id = 11, @@ -78855,7 +81071,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3780] = { + [3892] = { .class_hid = BNXT_ULP_CLASS_HID_39b7c, .class_tid = 2, .hdr_sig_id = 11, @@ -78876,7 +81092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3781] = { + [3893] = { .class_hid = BNXT_ULP_CLASS_HID_222d8, .class_tid = 2, .hdr_sig_id = 11, @@ -78896,7 +81112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3782] = { + [3894] = { .class_hid = BNXT_ULP_CLASS_HID_2afd8, .class_tid = 2, .hdr_sig_id = 11, @@ -78917,7 +81133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3783] = { + [3895] = { .class_hid = BNXT_ULP_CLASS_HID_358d8, .class_tid = 2, .hdr_sig_id = 11, @@ -78938,7 +81154,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3784] = { + [3896] = { .class_hid = BNXT_ULP_CLASS_HID_3c5d8, .class_tid = 2, .hdr_sig_id = 11, @@ -78960,7 +81176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3785] = { + [3897] = { .class_hid = BNXT_ULP_CLASS_HID_23f8c, .class_tid = 2, .hdr_sig_id = 11, @@ -78981,7 +81197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3786] = { + [3898] = { .class_hid = BNXT_ULP_CLASS_HID_2a88c, .class_tid = 2, .hdr_sig_id = 11, @@ -79003,7 +81219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3787] = { + [3899] = { .class_hid = BNXT_ULP_CLASS_HID_3558c, .class_tid = 2, .hdr_sig_id = 11, @@ -79025,7 +81241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3788] = { + [3900] = { .class_hid = BNXT_ULP_CLASS_HID_3de8c, .class_tid = 2, .hdr_sig_id = 11, @@ -79048,7 +81264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3789] = { + [3901] = { .class_hid = BNXT_ULP_CLASS_HID_2507c, .class_tid = 2, .hdr_sig_id = 11, @@ -79068,7 +81284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3790] = { + [3902] = { .class_hid = BNXT_ULP_CLASS_HID_2dd7c, .class_tid = 2, .hdr_sig_id = 11, @@ -79089,7 +81305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3791] = { + [3903] = { .class_hid = BNXT_ULP_CLASS_HID_3467c, .class_tid = 2, .hdr_sig_id = 11, @@ -79110,7 +81326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3792] = { + [3904] = { .class_hid = BNXT_ULP_CLASS_HID_39430, .class_tid = 2, .hdr_sig_id = 11, @@ -79132,7 +81348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3793] = { + [3905] = { .class_hid = BNXT_ULP_CLASS_HID_223dc, .class_tid = 2, .hdr_sig_id = 11, @@ -79149,7 +81365,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3794] = { + [3906] = { .class_hid = BNXT_ULP_CLASS_HID_2acdc, .class_tid = 2, .hdr_sig_id = 11, @@ -79167,7 +81383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3795] = { + [3907] = { .class_hid = BNXT_ULP_CLASS_HID_359dc, .class_tid = 2, .hdr_sig_id = 11, @@ -79185,7 +81401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3796] = { + [3908] = { .class_hid = BNXT_ULP_CLASS_HID_3c2dc, .class_tid = 2, .hdr_sig_id = 11, @@ -79204,7 +81420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3797] = { + [3909] = { .class_hid = BNXT_ULP_CLASS_HID_20eec, .class_tid = 2, .hdr_sig_id = 11, @@ -79222,7 +81438,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3798] = { + [3910] = { .class_hid = BNXT_ULP_CLASS_HID_2bbec, .class_tid = 2, .hdr_sig_id = 11, @@ -79241,7 +81457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3799] = { + [3911] = { .class_hid = BNXT_ULP_CLASS_HID_324ec, .class_tid = 2, .hdr_sig_id = 11, @@ -79260,7 +81476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3800] = { + [3912] = { .class_hid = BNXT_ULP_CLASS_HID_3d1ec, .class_tid = 2, .hdr_sig_id = 11, @@ -79280,7 +81496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3801] = { + [3913] = { .class_hid = BNXT_ULP_CLASS_HID_20ba0, .class_tid = 2, .hdr_sig_id = 11, @@ -79299,7 +81515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3802] = { + [3914] = { .class_hid = BNXT_ULP_CLASS_HID_2b4a0, .class_tid = 2, .hdr_sig_id = 11, @@ -79319,7 +81535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3803] = { + [3915] = { .class_hid = BNXT_ULP_CLASS_HID_321a0, .class_tid = 2, .hdr_sig_id = 11, @@ -79339,7 +81555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3804] = { + [3916] = { .class_hid = BNXT_ULP_CLASS_HID_3aaa0, .class_tid = 2, .hdr_sig_id = 11, @@ -79360,7 +81576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3805] = { + [3917] = { .class_hid = BNXT_ULP_CLASS_HID_23c90, .class_tid = 2, .hdr_sig_id = 11, @@ -79378,7 +81594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3806] = { + [3918] = { .class_hid = BNXT_ULP_CLASS_HID_2a990, .class_tid = 2, .hdr_sig_id = 11, @@ -79397,7 +81613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3807] = { + [3919] = { .class_hid = BNXT_ULP_CLASS_HID_35290, .class_tid = 2, .hdr_sig_id = 11, @@ -79416,7 +81632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3808] = { + [3920] = { .class_hid = BNXT_ULP_CLASS_HID_3df90, .class_tid = 2, .hdr_sig_id = 11, @@ -79436,7 +81652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3809] = { + [3921] = { .class_hid = BNXT_ULP_CLASS_HID_24430, .class_tid = 2, .hdr_sig_id = 11, @@ -79454,7 +81670,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3810] = { + [3922] = { .class_hid = BNXT_ULP_CLASS_HID_295e4, .class_tid = 2, .hdr_sig_id = 11, @@ -79473,7 +81689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3811] = { + [3923] = { .class_hid = BNXT_ULP_CLASS_HID_31ee4, .class_tid = 2, .hdr_sig_id = 11, @@ -79492,7 +81708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3812] = { + [3924] = { .class_hid = BNXT_ULP_CLASS_HID_38be4, .class_tid = 2, .hdr_sig_id = 11, @@ -79512,7 +81728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3813] = { + [3925] = { .class_hid = BNXT_ULP_CLASS_HID_25340, .class_tid = 2, .hdr_sig_id = 11, @@ -79531,7 +81747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3814] = { + [3926] = { .class_hid = BNXT_ULP_CLASS_HID_2dc40, .class_tid = 2, .hdr_sig_id = 11, @@ -79551,7 +81767,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3815] = { + [3927] = { .class_hid = BNXT_ULP_CLASS_HID_34940, .class_tid = 2, .hdr_sig_id = 11, @@ -79571,7 +81787,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3816] = { + [3928] = { .class_hid = BNXT_ULP_CLASS_HID_39734, .class_tid = 2, .hdr_sig_id = 11, @@ -79592,7 +81808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3817] = { + [3929] = { .class_hid = BNXT_ULP_CLASS_HID_22c34, .class_tid = 2, .hdr_sig_id = 11, @@ -79612,7 +81828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3818] = { + [3930] = { .class_hid = BNXT_ULP_CLASS_HID_2d934, .class_tid = 2, .hdr_sig_id = 11, @@ -79633,7 +81849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3819] = { + [3931] = { .class_hid = BNXT_ULP_CLASS_HID_34234, .class_tid = 2, .hdr_sig_id = 11, @@ -79654,7 +81870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3820] = { + [3932] = { .class_hid = BNXT_ULP_CLASS_HID_393e8, .class_tid = 2, .hdr_sig_id = 11, @@ -79676,7 +81892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3821] = { + [3933] = { .class_hid = BNXT_ULP_CLASS_HID_240e4, .class_tid = 2, .hdr_sig_id = 11, @@ -79695,7 +81911,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3822] = { + [3934] = { .class_hid = BNXT_ULP_CLASS_HID_2cde4, .class_tid = 2, .hdr_sig_id = 11, @@ -79715,7 +81931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3823] = { + [3935] = { .class_hid = BNXT_ULP_CLASS_HID_31bd8, .class_tid = 2, .hdr_sig_id = 11, @@ -79735,7 +81951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3824] = { + [3936] = { .class_hid = BNXT_ULP_CLASS_HID_384d8, .class_tid = 2, .hdr_sig_id = 11, @@ -79756,7 +81972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3825] = { + [3937] = { .class_hid = BNXT_ULP_CLASS_HID_23de0, .class_tid = 2, .hdr_sig_id = 11, @@ -79772,7 +81988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3826] = { + [3938] = { .class_hid = BNXT_ULP_CLASS_HID_2a6e0, .class_tid = 2, .hdr_sig_id = 11, @@ -79789,7 +82005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3827] = { + [3939] = { .class_hid = BNXT_ULP_CLASS_HID_353e0, .class_tid = 2, .hdr_sig_id = 11, @@ -79806,7 +82022,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3828] = { + [3940] = { .class_hid = BNXT_ULP_CLASS_HID_3dce0, .class_tid = 2, .hdr_sig_id = 11, @@ -79824,7 +82040,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3829] = { + [3941] = { .class_hid = BNXT_ULP_CLASS_HID_20930, .class_tid = 2, .hdr_sig_id = 11, @@ -79841,7 +82057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3830] = { + [3942] = { .class_hid = BNXT_ULP_CLASS_HID_2b230, .class_tid = 2, .hdr_sig_id = 11, @@ -79859,7 +82075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3831] = { + [3943] = { .class_hid = BNXT_ULP_CLASS_HID_33f30, .class_tid = 2, .hdr_sig_id = 11, @@ -79877,7 +82093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3832] = { + [3944] = { .class_hid = BNXT_ULP_CLASS_HID_3a830, .class_tid = 2, .hdr_sig_id = 11, @@ -79896,7 +82112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3833] = { + [3945] = { .class_hid = BNXT_ULP_CLASS_HID_205e4, .class_tid = 2, .hdr_sig_id = 11, @@ -79914,7 +82130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3834] = { + [3946] = { .class_hid = BNXT_ULP_CLASS_HID_28ee4, .class_tid = 2, .hdr_sig_id = 11, @@ -79933,7 +82149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3835] = { + [3947] = { .class_hid = BNXT_ULP_CLASS_HID_33be4, .class_tid = 2, .hdr_sig_id = 11, @@ -79952,7 +82168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3836] = { + [3948] = { .class_hid = BNXT_ULP_CLASS_HID_3a4e4, .class_tid = 2, .hdr_sig_id = 11, @@ -79972,7 +82188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3837] = { + [3949] = { .class_hid = BNXT_ULP_CLASS_HID_236d4, .class_tid = 2, .hdr_sig_id = 11, @@ -79989,7 +82205,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3838] = { + [3950] = { .class_hid = BNXT_ULP_CLASS_HID_2a3d4, .class_tid = 2, .hdr_sig_id = 11, @@ -80007,7 +82223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3839] = { + [3951] = { .class_hid = BNXT_ULP_CLASS_HID_32cd4, .class_tid = 2, .hdr_sig_id = 11, @@ -80025,7 +82241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3840] = { + [3952] = { .class_hid = BNXT_ULP_CLASS_HID_3d9d4, .class_tid = 2, .hdr_sig_id = 11, @@ -80044,7 +82260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3841] = { + [3953] = { .class_hid = BNXT_ULP_CLASS_HID_25e74, .class_tid = 2, .hdr_sig_id = 11, @@ -80061,7 +82277,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3842] = { + [3954] = { .class_hid = BNXT_ULP_CLASS_HID_2cb74, .class_tid = 2, .hdr_sig_id = 11, @@ -80079,7 +82295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3843] = { + [3955] = { .class_hid = BNXT_ULP_CLASS_HID_31928, .class_tid = 2, .hdr_sig_id = 11, @@ -80097,7 +82313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3844] = { + [3956] = { .class_hid = BNXT_ULP_CLASS_HID_38228, .class_tid = 2, .hdr_sig_id = 11, @@ -80116,7 +82332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3845] = { + [3957] = { .class_hid = BNXT_ULP_CLASS_HID_22d84, .class_tid = 2, .hdr_sig_id = 11, @@ -80134,7 +82350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3846] = { + [3958] = { .class_hid = BNXT_ULP_CLASS_HID_2d684, .class_tid = 2, .hdr_sig_id = 11, @@ -80153,7 +82369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3847] = { + [3959] = { .class_hid = BNXT_ULP_CLASS_HID_34384, .class_tid = 2, .hdr_sig_id = 11, @@ -80172,7 +82388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3848] = { + [3960] = { .class_hid = BNXT_ULP_CLASS_HID_39178, .class_tid = 2, .hdr_sig_id = 11, @@ -80192,7 +82408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3849] = { + [3961] = { .class_hid = BNXT_ULP_CLASS_HID_22678, .class_tid = 2, .hdr_sig_id = 11, @@ -80211,7 +82427,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3850] = { + [3962] = { .class_hid = BNXT_ULP_CLASS_HID_2d378, .class_tid = 2, .hdr_sig_id = 11, @@ -80231,7 +82447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3851] = { + [3963] = { .class_hid = BNXT_ULP_CLASS_HID_35c78, .class_tid = 2, .hdr_sig_id = 11, @@ -80251,7 +82467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3852] = { + [3964] = { .class_hid = BNXT_ULP_CLASS_HID_3c978, .class_tid = 2, .hdr_sig_id = 11, @@ -80272,7 +82488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3853] = { + [3965] = { .class_hid = BNXT_ULP_CLASS_HID_25b28, .class_tid = 2, .hdr_sig_id = 11, @@ -80290,7 +82506,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3854] = { + [3966] = { .class_hid = BNXT_ULP_CLASS_HID_2c428, .class_tid = 2, .hdr_sig_id = 11, @@ -80309,7 +82525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3855] = { + [3967] = { .class_hid = BNXT_ULP_CLASS_HID_3121c, .class_tid = 2, .hdr_sig_id = 11, @@ -80328,7 +82544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3856] = { + [3968] = { .class_hid = BNXT_ULP_CLASS_HID_39f1c, .class_tid = 2, .hdr_sig_id = 11, @@ -80348,7 +82564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3857] = { + [3969] = { .class_hid = BNXT_ULP_CLASS_HID_3488, .class_tid = 2, .hdr_sig_id = 11, @@ -80365,7 +82581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3858] = { + [3970] = { .class_hid = BNXT_ULP_CLASS_HID_3a44, .class_tid = 2, .hdr_sig_id = 11, @@ -80383,7 +82599,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3859] = { + [3971] = { + .class_hid = BNXT_ULP_CLASS_HID_0994, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3972] = { .class_hid = BNXT_ULP_CLASS_HID_5ed8, .class_tid = 2, .hdr_sig_id = 11, @@ -80402,7 +82637,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3860] = { + [3973] = { + .class_hid = BNXT_ULP_CLASS_HID_2de8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3974] = { .class_hid = BNXT_ULP_CLASS_HID_07e0, .class_tid = 2, .hdr_sig_id = 11, @@ -80421,7 +82676,27 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3861] = { + [3975] = { + .class_hid = BNXT_ULP_CLASS_HID_1330, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3976] = { .class_hid = BNXT_ULP_CLASS_HID_2874, .class_tid = 2, .hdr_sig_id = 11, @@ -80441,7 +82716,46 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3862] = { + [3977] = { + .class_hid = BNXT_ULP_CLASS_HID_3784, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3978] = { + .class_hid = BNXT_ULP_CLASS_HID_03d8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3979] = { .class_hid = BNXT_ULP_CLASS_HID_591c, .class_tid = 2, .hdr_sig_id = 11, @@ -80459,7 +82773,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3863] = { + [3980] = { + .class_hid = BNXT_ULP_CLASS_HID_242c, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3981] = { .class_hid = BNXT_ULP_CLASS_HID_1e24, .class_tid = 2, .hdr_sig_id = 11, @@ -80477,7 +82810,26 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3864] = { + [3982] = { + .class_hid = BNXT_ULP_CLASS_HID_4880, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3983] = { .class_hid = BNXT_ULP_CLASS_HID_22b8, .class_tid = 2, .hdr_sig_id = 11, @@ -80495,5 +82847,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [3984] = { + .class_hid = BNXT_ULP_CLASS_HID_31c8, + .class_tid = 2, + .hdr_sig_id = 11, + .flow_sig_id = 284, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 0223296480..a6da4729b9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jan 26 15:51:49 2021 */ +/* date: Fri Jan 29 09:44:41 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -11,9 +11,9 @@ #define BNXT_ULP_REGFILE_MAX_SZ 34 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 6 +#define BNXT_ULP_GEN_TBL_MAX_SZ 8 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 262144 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 3865 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 3985 #define BNXT_ULP_CLASS_HID_LOW_PRIME 5939 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7669 #define BNXT_ULP_CLASS_HID_SHFTR 31 @@ -32,11 +32,11 @@ #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 #define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595 #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 63 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 410 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 69 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 418 #define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 17 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 503 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 18 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 519 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 20 #define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7 #define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38 #define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192 @@ -290,6 +290,12 @@ enum bnxt_ulp_field_src { BNXT_ULP_FIELD_SRC_LAST = 15 }; +enum bnxt_ulp_generic_tbl_lkup_type { + BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX = 0, + BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH = 1, + BNXT_ULP_GENERIC_TBL_LKUP_TYPE_LAST = 2 +}; + enum bnxt_ulp_generic_tbl_opc { BNXT_ULP_GENERIC_TBL_OPC_NOT_USED = 0, BNXT_ULP_GENERIC_TBL_OPC_READ = 1, @@ -304,7 +310,8 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 3, BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4, BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5, - BNXT_ULP_GLB_RF_IDX_LAST = 6 + BNXT_ULP_GLB_RF_IDX_DEFAULT_ING_AREC_PTR = 6, + BNXT_ULP_GLB_RF_IDX_LAST = 7 }; enum bnxt_ulp_hdr_type { @@ -409,7 +416,7 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0 = 23, BNXT_ULP_RF_IDX_WC_TCAM_INDEX_1 = 24, BNXT_ULP_RF_IDX_SRC_PROPERTY_PTR = 25, - BNXT_ULP_RF_IDX_GENERIC_TBL_HIT = 26, + BNXT_ULP_RF_IDX_GENERIC_TBL_MISS = 26, BNXT_ULP_RF_IDX_MIRROR_PTR_0 = 27, BNXT_ULP_RF_IDX_MIRROR_ID_0 = 28, BNXT_ULP_RF_IDX_HDR_SIG_ID = 29, @@ -424,7 +431,9 @@ enum bnxt_ulp_tcam_tbl_opc { BNXT_ULP_TCAM_TBL_OPC_NOT_USED = 0, BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE = 1, BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2, - BNXT_ULP_TCAM_TBL_OPC_LAST = 3 + BNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3, + BNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4, + BNXT_ULP_TCAM_TBL_OPC_LAST = 5 }; enum bnxt_ulp_template_type { @@ -473,7 +482,8 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT = 4, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM = 0, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3 }; enum bnxt_ulp_act_prop_sz { @@ -569,6 +579,11 @@ enum bnxt_ulp_act_prop_idx { }; enum ulp_wp_sym { + ULP_WP_SYM_CTXT_OPCODE_BYPASS_CFA = 0, + ULP_WP_SYM_CTXT_OPCODE_BYPASS_LKUP = 0, + ULP_WP_SYM_CTXT_OPCODE_META_UPDATE = 0, + ULP_WP_SYM_CTXT_OPCODE_NORMAL_FLOW = 0, + ULP_WP_SYM_CTXT_OPCODE_DROP = 0, ULP_WP_SYM_PKT_TYPE_IGNORE = 0, ULP_WP_SYM_PKT_TYPE_L2 = 0, ULP_WP_SYM_PKT_TYPE_0_IGNORE = 0, @@ -1031,6 +1046,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_4e61 = 0x4e61, BNXT_ULP_CLASS_HID_2561 = 0x2561, BNXT_ULP_CLASS_HID_2bad = 0x2bad, + BNXT_ULP_CLASS_HID_054d = 0x054d, + BNXT_ULP_CLASS_HID_5bdd = 0x5bdd, BNXT_ULP_CLASS_HID_26f1 = 0x26f1, BNXT_ULP_CLASS_HID_13cf1 = 0x13cf1, BNXT_ULP_CLASS_HID_252f1 = 0x252f1, @@ -1129,6 +1146,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_333b5 = 0x333b5, BNXT_ULP_CLASS_HID_2541 = 0x2541, BNXT_ULP_CLASS_HID_2b8d = 0x2b8d, + BNXT_ULP_CLASS_HID_056d = 0x056d, + BNXT_ULP_CLASS_HID_5bfd = 0x5bfd, BNXT_ULP_CLASS_HID_2691 = 0x2691, BNXT_ULP_CLASS_HID_13c91 = 0x13c91, BNXT_ULP_CLASS_HID_25291 = 0x25291, @@ -1227,6 +1246,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_333d5 = 0x333d5, BNXT_ULP_CLASS_HID_2521 = 0x2521, BNXT_ULP_CLASS_HID_2bed = 0x2bed, + BNXT_ULP_CLASS_HID_050d = 0x050d, + BNXT_ULP_CLASS_HID_5b9d = 0x5b9d, BNXT_ULP_CLASS_HID_1865 = 0x1865, BNXT_ULP_CLASS_HID_389d = 0x389d, BNXT_ULP_CLASS_HID_123d = 0x123d, @@ -1253,6 +1274,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_232d = 0x232d, BNXT_ULP_CLASS_HID_2579 = 0x2579, BNXT_ULP_CLASS_HID_2bb5 = 0x2bb5, + BNXT_ULP_CLASS_HID_4bad = 0x4bad, + BNXT_ULP_CLASS_HID_4591 = 0x4591, BNXT_ULP_CLASS_HID_1845 = 0x1845, BNXT_ULP_CLASS_HID_1399 = 0x1399, BNXT_ULP_CLASS_HID_0eed = 0x0eed, @@ -1351,6 +1374,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_14e9 = 0x14e9, BNXT_ULP_CLASS_HID_2559 = 0x2559, BNXT_ULP_CLASS_HID_2b95 = 0x2b95, + BNXT_ULP_CLASS_HID_4b8d = 0x4b8d, + BNXT_ULP_CLASS_HID_45b1 = 0x45b1, BNXT_ULP_CLASS_HID_1825 = 0x1825, BNXT_ULP_CLASS_HID_13f9 = 0x13f9, BNXT_ULP_CLASS_HID_0e8d = 0x0e8d, @@ -1449,6 +1474,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_1489 = 0x1489, BNXT_ULP_CLASS_HID_2539 = 0x2539, BNXT_ULP_CLASS_HID_2bf5 = 0x2bf5, + BNXT_ULP_CLASS_HID_4bed = 0x4bed, + BNXT_ULP_CLASS_HID_45d1 = 0x45d1, BNXT_ULP_CLASS_HID_b6af = 0xb6af, BNXT_ULP_CLASS_HID_b1d3 = 0xb1d3, BNXT_ULP_CLASS_HID_1c7d3 = 0x1c7d3, @@ -1531,12 +1558,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_1c49f = 0x1c49f, BNXT_ULP_CLASS_HID_2563 = 0x2563, BNXT_ULP_CLASS_HID_2baf = 0x2baf, + BNXT_ULP_CLASS_HID_26d3 = 0x26d3, BNXT_ULP_CLASS_HID_4f33 = 0x4f33, + BNXT_ULP_CLASS_HID_4a67 = 0x4a67, BNXT_ULP_CLASS_HID_160b = 0x160b, + BNXT_ULP_CLASS_HID_113f = 0x113f, BNXT_ULP_CLASS_HID_399f = 0x399f, + BNXT_ULP_CLASS_HID_34c3 = 0x34c3, + BNXT_ULP_CLASS_HID_2097 = 0x2097, BNXT_ULP_CLASS_HID_48f7 = 0x48f7, + BNXT_ULP_CLASS_HID_443b = 0x443b, BNXT_ULP_CLASS_HID_0fcf = 0x0fcf, + BNXT_ULP_CLASS_HID_0af3 = 0x0af3, BNXT_ULP_CLASS_HID_3353 = 0x3353, + BNXT_ULP_CLASS_HID_2e87 = 0x2e87, BNXT_ULP_CLASS_HID_b68f = 0xb68f, BNXT_ULP_CLASS_HID_b94f = 0xb94f, BNXT_ULP_CLASS_HID_fc0f = 0xfc0f, @@ -1859,12 +1894,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_1ecff = 0x1ecff, BNXT_ULP_CLASS_HID_2543 = 0x2543, BNXT_ULP_CLASS_HID_2b8f = 0x2b8f, + BNXT_ULP_CLASS_HID_26f3 = 0x26f3, BNXT_ULP_CLASS_HID_4f13 = 0x4f13, + BNXT_ULP_CLASS_HID_4a47 = 0x4a47, BNXT_ULP_CLASS_HID_162b = 0x162b, + BNXT_ULP_CLASS_HID_111f = 0x111f, BNXT_ULP_CLASS_HID_39bf = 0x39bf, + BNXT_ULP_CLASS_HID_34e3 = 0x34e3, + BNXT_ULP_CLASS_HID_20b7 = 0x20b7, BNXT_ULP_CLASS_HID_48d7 = 0x48d7, + BNXT_ULP_CLASS_HID_441b = 0x441b, BNXT_ULP_CLASS_HID_0fef = 0x0fef, + BNXT_ULP_CLASS_HID_0ad3 = 0x0ad3, BNXT_ULP_CLASS_HID_3373 = 0x3373, + BNXT_ULP_CLASS_HID_2ea7 = 0x2ea7, BNXT_ULP_CLASS_HID_b6ef = 0xb6ef, BNXT_ULP_CLASS_HID_b92f = 0xb92f, BNXT_ULP_CLASS_HID_fc6f = 0xfc6f, @@ -2187,12 +2230,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_1ec9f = 0x1ec9f, BNXT_ULP_CLASS_HID_2523 = 0x2523, BNXT_ULP_CLASS_HID_2bef = 0x2bef, + BNXT_ULP_CLASS_HID_2693 = 0x2693, BNXT_ULP_CLASS_HID_4f73 = 0x4f73, + BNXT_ULP_CLASS_HID_4a27 = 0x4a27, BNXT_ULP_CLASS_HID_164b = 0x164b, + BNXT_ULP_CLASS_HID_117f = 0x117f, BNXT_ULP_CLASS_HID_39df = 0x39df, + BNXT_ULP_CLASS_HID_3483 = 0x3483, + BNXT_ULP_CLASS_HID_20d7 = 0x20d7, BNXT_ULP_CLASS_HID_48b7 = 0x48b7, + BNXT_ULP_CLASS_HID_447b = 0x447b, BNXT_ULP_CLASS_HID_0f8f = 0x0f8f, + BNXT_ULP_CLASS_HID_0ab3 = 0x0ab3, BNXT_ULP_CLASS_HID_3313 = 0x3313, + BNXT_ULP_CLASS_HID_2ec7 = 0x2ec7, BNXT_ULP_CLASS_HID_257b7 = 0x257b7, BNXT_ULP_CLASS_HID_24467 = 0x24467, BNXT_ULP_CLASS_HID_23fbb = 0x23fbb, @@ -2275,12 +2326,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_24adb = 0x24adb, BNXT_ULP_CLASS_HID_257b = 0x257b, BNXT_ULP_CLASS_HID_2bb7 = 0x2bb7, + BNXT_ULP_CLASS_HID_1867 = 0x1867, BNXT_ULP_CLASS_HID_4f2b = 0x4f2b, + BNXT_ULP_CLASS_HID_3c1b = 0x3c1b, BNXT_ULP_CLASS_HID_1613 = 0x1613, + BNXT_ULP_CLASS_HID_02c3 = 0x02c3, BNXT_ULP_CLASS_HID_3987 = 0x3987, + BNXT_ULP_CLASS_HID_2677 = 0x2677, + BNXT_ULP_CLASS_HID_122b = 0x122b, BNXT_ULP_CLASS_HID_48ef = 0x48ef, + BNXT_ULP_CLASS_HID_35df = 0x35df, BNXT_ULP_CLASS_HID_0fd7 = 0x0fd7, + BNXT_ULP_CLASS_HID_5973 = 0x5973, BNXT_ULP_CLASS_HID_334b = 0x334b, + BNXT_ULP_CLASS_HID_203b = 0x203b, BNXT_ULP_CLASS_HID_25797 = 0x25797, BNXT_ULP_CLASS_HID_285eb = 0x285eb, BNXT_ULP_CLASS_HID_310eb = 0x310eb, @@ -2603,12 +2662,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_38ecf = 0x38ecf, BNXT_ULP_CLASS_HID_255b = 0x255b, BNXT_ULP_CLASS_HID_2b97 = 0x2b97, + BNXT_ULP_CLASS_HID_1847 = 0x1847, BNXT_ULP_CLASS_HID_4f0b = 0x4f0b, + BNXT_ULP_CLASS_HID_3c3b = 0x3c3b, BNXT_ULP_CLASS_HID_1633 = 0x1633, + BNXT_ULP_CLASS_HID_02e3 = 0x02e3, BNXT_ULP_CLASS_HID_39a7 = 0x39a7, + BNXT_ULP_CLASS_HID_2657 = 0x2657, + BNXT_ULP_CLASS_HID_120b = 0x120b, BNXT_ULP_CLASS_HID_48cf = 0x48cf, + BNXT_ULP_CLASS_HID_35ff = 0x35ff, BNXT_ULP_CLASS_HID_0ff7 = 0x0ff7, + BNXT_ULP_CLASS_HID_5953 = 0x5953, BNXT_ULP_CLASS_HID_336b = 0x336b, + BNXT_ULP_CLASS_HID_201b = 0x201b, BNXT_ULP_CLASS_HID_257f7 = 0x257f7, BNXT_ULP_CLASS_HID_2858b = 0x2858b, BNXT_ULP_CLASS_HID_3108b = 0x3108b, @@ -2931,12 +2998,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_38eaf = 0x38eaf, BNXT_ULP_CLASS_HID_253b = 0x253b, BNXT_ULP_CLASS_HID_2bf7 = 0x2bf7, + BNXT_ULP_CLASS_HID_1827 = 0x1827, BNXT_ULP_CLASS_HID_4f6b = 0x4f6b, + BNXT_ULP_CLASS_HID_3c5b = 0x3c5b, BNXT_ULP_CLASS_HID_1653 = 0x1653, + BNXT_ULP_CLASS_HID_0283 = 0x0283, BNXT_ULP_CLASS_HID_39c7 = 0x39c7, + BNXT_ULP_CLASS_HID_2637 = 0x2637, + BNXT_ULP_CLASS_HID_126b = 0x126b, BNXT_ULP_CLASS_HID_48af = 0x48af, + BNXT_ULP_CLASS_HID_359f = 0x359f, BNXT_ULP_CLASS_HID_0f97 = 0x0f97, + BNXT_ULP_CLASS_HID_5933 = 0x5933, BNXT_ULP_CLASS_HID_330b = 0x330b, + BNXT_ULP_CLASS_HID_207b = 0x207b, BNXT_ULP_CLASS_HID_374e = 0x374e, BNXT_ULP_CLASS_HID_11ee = 0x11ee, BNXT_ULP_CLASS_HID_423a = 0x423a, @@ -2963,6 +3038,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_5ffe = 0x5ffe, BNXT_ULP_CLASS_HID_34fe = 0x34fe, BNXT_ULP_CLASS_HID_3a32 = 0x3a32, + BNXT_ULP_CLASS_HID_14d2 = 0x14d2, + BNXT_ULP_CLASS_HID_4a42 = 0x4a42, BNXT_ULP_CLASS_HID_376e = 0x376e, BNXT_ULP_CLASS_HID_12d6e = 0x12d6e, BNXT_ULP_CLASS_HID_2436e = 0x2436e, @@ -3061,6 +3138,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_3222a = 0x3222a, BNXT_ULP_CLASS_HID_34de = 0x34de, BNXT_ULP_CLASS_HID_3a12 = 0x3a12, + BNXT_ULP_CLASS_HID_14f2 = 0x14f2, + BNXT_ULP_CLASS_HID_4a62 = 0x4a62, BNXT_ULP_CLASS_HID_370e = 0x370e, BNXT_ULP_CLASS_HID_12d0e = 0x12d0e, BNXT_ULP_CLASS_HID_2430e = 0x2430e, @@ -3159,6 +3238,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_3224a = 0x3224a, BNXT_ULP_CLASS_HID_34be = 0x34be, BNXT_ULP_CLASS_HID_3a72 = 0x3a72, + BNXT_ULP_CLASS_HID_1492 = 0x1492, + BNXT_ULP_CLASS_HID_4a02 = 0x4a02, BNXT_ULP_CLASS_HID_09ea = 0x09ea, BNXT_ULP_CLASS_HID_2912 = 0x2912, BNXT_ULP_CLASS_HID_03b2 = 0x03b2, @@ -3185,6 +3266,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_32a2 = 0x32a2, BNXT_ULP_CLASS_HID_34f6 = 0x34f6, BNXT_ULP_CLASS_HID_3a3a = 0x3a3a, + BNXT_ULP_CLASS_HID_5a22 = 0x5a22, + BNXT_ULP_CLASS_HID_541e = 0x541e, BNXT_ULP_CLASS_HID_09ca = 0x09ca, BNXT_ULP_CLASS_HID_0216 = 0x0216, BNXT_ULP_CLASS_HID_1f62 = 0x1f62, @@ -3283,6 +3366,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_0566 = 0x0566, BNXT_ULP_CLASS_HID_34d6 = 0x34d6, BNXT_ULP_CLASS_HID_3a1a = 0x3a1a, + BNXT_ULP_CLASS_HID_5a02 = 0x5a02, + BNXT_ULP_CLASS_HID_543e = 0x543e, BNXT_ULP_CLASS_HID_09aa = 0x09aa, BNXT_ULP_CLASS_HID_0276 = 0x0276, BNXT_ULP_CLASS_HID_1f02 = 0x1f02, @@ -3381,6 +3466,8 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_0506 = 0x0506, BNXT_ULP_CLASS_HID_34b6 = 0x34b6, BNXT_ULP_CLASS_HID_3a7a = 0x3a7a, + BNXT_ULP_CLASS_HID_5a62 = 0x5a62, + BNXT_ULP_CLASS_HID_545e = 0x545e, BNXT_ULP_CLASS_HID_a73c = 0xa73c, BNXT_ULP_CLASS_HID_a040 = 0xa040, BNXT_ULP_CLASS_HID_1d640 = 0x1d640, @@ -3463,12 +3550,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_1d50c = 0x1d50c, BNXT_ULP_CLASS_HID_34f0 = 0x34f0, BNXT_ULP_CLASS_HID_3a3c = 0x3a3c, + BNXT_ULP_CLASS_HID_3740 = 0x3740, BNXT_ULP_CLASS_HID_5ea0 = 0x5ea0, + BNXT_ULP_CLASS_HID_5bf4 = 0x5bf4, BNXT_ULP_CLASS_HID_0798 = 0x0798, + BNXT_ULP_CLASS_HID_00ac = 0x00ac, BNXT_ULP_CLASS_HID_280c = 0x280c, + BNXT_ULP_CLASS_HID_2550 = 0x2550, + BNXT_ULP_CLASS_HID_3104 = 0x3104, BNXT_ULP_CLASS_HID_5964 = 0x5964, + BNXT_ULP_CLASS_HID_55a8 = 0x55a8, BNXT_ULP_CLASS_HID_1e5c = 0x1e5c, + BNXT_ULP_CLASS_HID_1b60 = 0x1b60, BNXT_ULP_CLASS_HID_22c0 = 0x22c0, + BNXT_ULP_CLASS_HID_3f14 = 0x3f14, BNXT_ULP_CLASS_HID_a71c = 0xa71c, BNXT_ULP_CLASS_HID_a8dc = 0xa8dc, BNXT_ULP_CLASS_HID_ed9c = 0xed9c, @@ -3791,12 +3886,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_1fd6c = 0x1fd6c, BNXT_ULP_CLASS_HID_34d0 = 0x34d0, BNXT_ULP_CLASS_HID_3a1c = 0x3a1c, + BNXT_ULP_CLASS_HID_3760 = 0x3760, BNXT_ULP_CLASS_HID_5e80 = 0x5e80, + BNXT_ULP_CLASS_HID_5bd4 = 0x5bd4, BNXT_ULP_CLASS_HID_07b8 = 0x07b8, + BNXT_ULP_CLASS_HID_008c = 0x008c, BNXT_ULP_CLASS_HID_282c = 0x282c, + BNXT_ULP_CLASS_HID_2570 = 0x2570, + BNXT_ULP_CLASS_HID_3124 = 0x3124, BNXT_ULP_CLASS_HID_5944 = 0x5944, + BNXT_ULP_CLASS_HID_5588 = 0x5588, BNXT_ULP_CLASS_HID_1e7c = 0x1e7c, + BNXT_ULP_CLASS_HID_1b40 = 0x1b40, BNXT_ULP_CLASS_HID_22e0 = 0x22e0, + BNXT_ULP_CLASS_HID_3f34 = 0x3f34, BNXT_ULP_CLASS_HID_a77c = 0xa77c, BNXT_ULP_CLASS_HID_a8bc = 0xa8bc, BNXT_ULP_CLASS_HID_edfc = 0xedfc, @@ -4119,12 +4222,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_1fd0c = 0x1fd0c, BNXT_ULP_CLASS_HID_34b0 = 0x34b0, BNXT_ULP_CLASS_HID_3a7c = 0x3a7c, + BNXT_ULP_CLASS_HID_3700 = 0x3700, BNXT_ULP_CLASS_HID_5ee0 = 0x5ee0, + BNXT_ULP_CLASS_HID_5bb4 = 0x5bb4, BNXT_ULP_CLASS_HID_07d8 = 0x07d8, + BNXT_ULP_CLASS_HID_00ec = 0x00ec, BNXT_ULP_CLASS_HID_284c = 0x284c, + BNXT_ULP_CLASS_HID_2510 = 0x2510, + BNXT_ULP_CLASS_HID_3144 = 0x3144, BNXT_ULP_CLASS_HID_5924 = 0x5924, + BNXT_ULP_CLASS_HID_55e8 = 0x55e8, BNXT_ULP_CLASS_HID_1e1c = 0x1e1c, + BNXT_ULP_CLASS_HID_1b20 = 0x1b20, BNXT_ULP_CLASS_HID_2280 = 0x2280, + BNXT_ULP_CLASS_HID_3f54 = 0x3f54, BNXT_ULP_CLASS_HID_24604 = 0x24604, BNXT_ULP_CLASS_HID_255d4 = 0x255d4, BNXT_ULP_CLASS_HID_22e08 = 0x22e08, @@ -4207,12 +4318,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_25b68 = 0x25b68, BNXT_ULP_CLASS_HID_34c8 = 0x34c8, BNXT_ULP_CLASS_HID_3a04 = 0x3a04, + BNXT_ULP_CLASS_HID_09d4 = 0x09d4, BNXT_ULP_CLASS_HID_5e98 = 0x5e98, + BNXT_ULP_CLASS_HID_2da8 = 0x2da8, BNXT_ULP_CLASS_HID_07a0 = 0x07a0, + BNXT_ULP_CLASS_HID_1370 = 0x1370, BNXT_ULP_CLASS_HID_2834 = 0x2834, + BNXT_ULP_CLASS_HID_37c4 = 0x37c4, + BNXT_ULP_CLASS_HID_0398 = 0x0398, BNXT_ULP_CLASS_HID_595c = 0x595c, + BNXT_ULP_CLASS_HID_246c = 0x246c, BNXT_ULP_CLASS_HID_1e64 = 0x1e64, + BNXT_ULP_CLASS_HID_48c0 = 0x48c0, BNXT_ULP_CLASS_HID_22f8 = 0x22f8, + BNXT_ULP_CLASS_HID_3188 = 0x3188, BNXT_ULP_CLASS_HID_24664 = 0x24664, BNXT_ULP_CLASS_HID_29418 = 0x29418, BNXT_ULP_CLASS_HID_30118 = 0x30118, @@ -4535,12 +4654,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_39f3c = 0x39f3c, BNXT_ULP_CLASS_HID_34a8 = 0x34a8, BNXT_ULP_CLASS_HID_3a64 = 0x3a64, + BNXT_ULP_CLASS_HID_09b4 = 0x09b4, BNXT_ULP_CLASS_HID_5ef8 = 0x5ef8, + BNXT_ULP_CLASS_HID_2dc8 = 0x2dc8, BNXT_ULP_CLASS_HID_07c0 = 0x07c0, + BNXT_ULP_CLASS_HID_1310 = 0x1310, BNXT_ULP_CLASS_HID_2854 = 0x2854, + BNXT_ULP_CLASS_HID_37a4 = 0x37a4, + BNXT_ULP_CLASS_HID_03f8 = 0x03f8, BNXT_ULP_CLASS_HID_593c = 0x593c, + BNXT_ULP_CLASS_HID_240c = 0x240c, BNXT_ULP_CLASS_HID_1e04 = 0x1e04, + BNXT_ULP_CLASS_HID_48a0 = 0x48a0, BNXT_ULP_CLASS_HID_2298 = 0x2298, + BNXT_ULP_CLASS_HID_31e8 = 0x31e8, BNXT_ULP_CLASS_HID_24644 = 0x24644, BNXT_ULP_CLASS_HID_29438 = 0x29438, BNXT_ULP_CLASS_HID_30138 = 0x30138, @@ -4863,12 +4990,20 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_39f1c = 0x39f1c, BNXT_ULP_CLASS_HID_3488 = 0x3488, BNXT_ULP_CLASS_HID_3a44 = 0x3a44, + BNXT_ULP_CLASS_HID_0994 = 0x0994, BNXT_ULP_CLASS_HID_5ed8 = 0x5ed8, + BNXT_ULP_CLASS_HID_2de8 = 0x2de8, BNXT_ULP_CLASS_HID_07e0 = 0x07e0, + BNXT_ULP_CLASS_HID_1330 = 0x1330, BNXT_ULP_CLASS_HID_2874 = 0x2874, + BNXT_ULP_CLASS_HID_3784 = 0x3784, + BNXT_ULP_CLASS_HID_03d8 = 0x03d8, BNXT_ULP_CLASS_HID_591c = 0x591c, + BNXT_ULP_CLASS_HID_242c = 0x242c, BNXT_ULP_CLASS_HID_1e24 = 0x1e24, - BNXT_ULP_CLASS_HID_22b8 = 0x22b8 + BNXT_ULP_CLASS_HID_4880 = 0x4880, + BNXT_ULP_CLASS_HID_22b8 = 0x22b8, + BNXT_ULP_CLASS_HID_31c8 = 0x31c8 }; enum bnxt_ulp_act_hid { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c index 320a89a5d9..c2cb452770 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c @@ -916,7 +916,7 @@ struct bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[] = { }, { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, @@ -940,7 +940,7 @@ struct bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[] = { }, { .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, { .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, @@ -948,7 +948,7 @@ struct bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[] = { }, { .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 26e0ddfb1e..fd4ceb226c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Dec 16 16:03:45 2020 */ +/* date: Fri Jan 29 11:27:48 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -14,38 +14,82 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .result_num_entries = 16384, - .result_num_bytes = 16, + .name = "INGRESS GENERIC_TABLE_L2_CNTXT_TCAM", + .result_num_entries = 256, + .result_num_bytes = 8, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .result_num_entries = 16384, - .result_num_bytes = 16, + .name = "EGRESS GENERIC_TABLE_L2_CNTXT_TCAM", + .result_num_entries = 256, + .result_num_bytes = 8, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_PROFILE_TCAM", .result_num_entries = 16384, .result_num_bytes = 16, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PROFILE_TCAM", .result_num_entries = 16384, .result_num_bytes = 16, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SHARED_MIRROR", .result_num_entries = 16, .result_num_bytes = 16, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SHARED_MIRROR", .result_num_entries = 16, .result_num_bytes = 16, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE", + .result_num_entries = 256, + .result_num_bytes = 8, + .key_num_bytes = 7, + .num_buckets = 8, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE", + .result_num_entries = 256, + .result_num_bytes = 8, + .key_num_bytes = 7, + .num_buckets = 8, + .hash_tbl_entries = 1024, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 8b672ab63c..9483e29323 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -88,6 +88,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .key_start_idx = 0, @@ -326,6 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .key_start_idx = 1, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 973ba39f82..84f3900141 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jan 26 15:51:49 2021 */ +/* date: Fri Jan 29 09:44:41 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 11, + .num_tbls = 14, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -25,61 +25,61 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 2, wh_plus, egress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 11, - .start_tbl_idx = 11, + .num_tbls = 14, + .start_tbl_idx = 14, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 5, + .cond_start_idx = 6, .cond_nums = 0 } }, /* class_tid: 3, wh_plus, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 8, - .start_tbl_idx = 22, + .start_tbl_idx = 28, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 } }, /* class_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 14, - .start_tbl_idx = 30, + .start_tbl_idx = 36, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 } }, /* class_tid: 5, wh_plus, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 9, - .start_tbl_idx = 44, + .start_tbl_idx = 50, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 } }, /* class_tid: 6, wh_plus, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 9, - .start_tbl_idx = 53, + .start_tbl_idx = 59, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 } }, /* class_tid: 7, wh_plus, egress */ [7] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 1, - .start_tbl_idx = 62, + .start_tbl_idx = 68, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 } } }; @@ -92,12 +92,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 2, + .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 0, @@ -107,6 +108,42 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 0, .ident_nums = 1 }, + { /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 1, + .blob_key_bit_size = 56, + .key_bit_size = 56, + .key_num_fields = 2, + .result_start_idx = 0, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 1, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 1, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, @@ -115,24 +152,47 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 1, + .key_start_idx = 3, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 0, + .result_start_idx = 4, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 1, .ident_nums = 1 }, + { /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 16, + .blob_key_bit_size = 56, + .key_bit_size = 56, + .key_num_fields = 2, + .result_start_idx = 17, + .result_bit_size = 62, + .result_num_fields = 4 + }, { /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, @@ -143,26 +203,27 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 14, + .key_start_idx = 18, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, .ident_start_idx = 2, .ident_nums = 3 }, - { /* class_tid: 1, wh_plus, table: control.0 */ + { /* class_tid: 1, wh_plus, table: control.1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -176,7 +237,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -185,11 +246,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 17, + .key_start_idx = 21, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 13, + .result_start_idx = 21, .result_bit_size = 38, .result_num_fields = 17, .ident_start_idx = 5, @@ -203,7 +264,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -212,11 +273,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 60, + .key_start_idx = 64, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 30, + .result_start_idx = 38, .result_bit_size = 38, .result_num_fields = 17, .ident_start_idx = 6, @@ -232,17 +293,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 103, + .key_start_idx = 107, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 47, - .result_bit_size = 66, + .result_start_idx = 55, + .result_bit_size = 74, .result_num_fields = 5 }, { /* class_tid: 1, wh_plus, table: em.ipv4 */ @@ -254,17 +316,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 3, + .cond_start_idx = 4, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 106, + .key_start_idx = 110, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, - .result_start_idx = 52, + .result_start_idx = 60, .result_bit_size = 64, .result_num_fields = 9 }, @@ -277,17 +339,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 4, + .cond_start_idx = 5, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 116, + .key_start_idx = 120, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, - .result_start_idx = 61, + .result_start_idx = 69, .result_bit_size = 64, .result_num_fields = 9 }, @@ -300,17 +362,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 5, + .cond_start_idx = 6, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 126, + .key_start_idx = 130, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, - .result_start_idx = 70, + .result_start_idx = 78, .result_bit_size = 64, .result_num_fields = 9 }, @@ -322,42 +384,78 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 5, + .cond_start_idx = 6, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 137, + .key_start_idx = 141, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, - .result_start_idx = 79, + .result_start_idx = 87, .result_bit_size = 64, .result_num_fields = 9 }, { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 2, + .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 5, + .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 148, + .key_start_idx = 152, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, .ident_start_idx = 7, .ident_nums = 1 }, + { /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 7, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 153, + .blob_key_bit_size = 56, + .key_bit_size = 56, + .key_num_fields = 2, + .result_start_idx = 96, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 2, wh_plus, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 7, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, @@ -366,27 +464,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, + .cond_start_idx = 8, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 149, + .key_start_idx = 155, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 88, + .result_start_idx = 100, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 8, .ident_nums = 1 }, + { /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 8, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 168, + .blob_key_bit_size = 56, + .key_bit_size = 56, + .key_num_fields = 2, + .result_start_idx = 113, + .result_bit_size = 62, + .result_num_fields = 4 + }, { /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, @@ -394,26 +515,27 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, + .cond_start_idx = 8, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 162, + .key_start_idx = 170, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, .ident_start_idx = 9, .ident_nums = 3 }, - { /* class_tid: 2, wh_plus, table: control.0 */ + { /* class_tid: 2, wh_plus, table: control.1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 6, + .cond_start_idx = 8, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -427,7 +549,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 7, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -436,11 +558,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 165, + .key_start_idx = 173, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 101, + .result_start_idx = 117, .result_bit_size = 38, .result_num_fields = 17, .ident_start_idx = 12, @@ -454,7 +576,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -463,11 +585,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 208, + .key_start_idx = 216, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 118, + .result_start_idx = 134, .result_bit_size = 38, .result_num_fields = 17, .ident_start_idx = 13, @@ -475,7 +597,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }, { /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, @@ -483,17 +604,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 251, + .key_start_idx = 259, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 135, - .result_bit_size = 66, + .result_start_idx = 151, + .result_bit_size = 74, .result_num_fields = 5 }, { /* class_tid: 2, wh_plus, table: em.ipv4 */ @@ -505,17 +627,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 8, + .cond_start_idx = 10, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 254, + .key_start_idx = 262, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, - .result_start_idx = 140, + .result_start_idx = 156, .result_bit_size = 64, .result_num_fields = 9 }, @@ -528,17 +650,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 9, + .cond_start_idx = 11, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 264, + .key_start_idx = 272, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, - .result_start_idx = 149, + .result_start_idx = 165, .result_bit_size = 64, .result_num_fields = 9 }, @@ -551,17 +673,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 274, + .key_start_idx = 282, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, - .result_start_idx = 158, + .result_start_idx = 174, .result_bit_size = 64, .result_num_fields = 9 }, @@ -573,17 +695,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 285, + .key_start_idx = 293, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, - .result_start_idx = 167, + .result_start_idx = 183, .result_bit_size = 64, .result_num_fields = 9 }, @@ -597,20 +719,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 176, + .result_start_idx = 192, .result_bit_size = 128, .result_num_fields = 26 }, { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, @@ -618,12 +739,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 296, + .key_start_idx = 304, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -637,7 +759,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -651,7 +773,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -662,11 +784,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 297, + .key_start_idx = 305, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 202, + .result_start_idx = 218, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 14, @@ -674,7 +796,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }, { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, @@ -682,16 +803,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 310, + .key_start_idx = 318, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 215, + .result_start_idx = 231, .result_bit_size = 62, .result_num_fields = 4 }, @@ -703,13 +825,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 219, + .result_start_idx = 235, .result_bit_size = 32, .result_num_fields = 1 }, @@ -721,13 +843,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 220, + .result_start_idx = 236, .result_bit_size = 32, .result_num_fields = 1 }, @@ -739,13 +861,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 221, + .result_start_idx = 237, .result_bit_size = 32, .result_num_fields = 1 }, @@ -756,7 +878,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 11, + .cond_start_idx = 13, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP @@ -771,21 +893,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 222, + .result_start_idx = 238, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -793,12 +914,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 311, + .key_start_idx = 319, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -812,7 +934,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -826,7 +948,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -835,11 +957,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 312, + .key_start_idx = 320, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 248, + .result_start_idx = 264, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 15, @@ -847,7 +969,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }, { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -855,22 +976,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 325, + .key_start_idx = 333, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 261, + .result_start_idx = 277, .result_bit_size = 62, .result_num_fields = 4 }, { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -878,12 +999,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 326, + .key_start_idx = 334, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -897,7 +1019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -911,7 +1033,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -920,11 +1042,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 327, + .key_start_idx = 335, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 265, + .result_start_idx = 281, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 15, @@ -932,7 +1054,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }, { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -940,16 +1061,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 340, + .key_start_idx = 348, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 278, + .result_start_idx = 294, .result_bit_size = 62, .result_num_fields = 4 }, @@ -963,14 +1085,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 282, + .result_start_idx = 298, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -983,13 +1105,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 308, + .result_start_idx = 324, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1001,13 +1123,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 309, + .result_start_idx = 325, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1019,19 +1141,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 310, + .result_start_idx = 326, .result_bit_size = 32, .result_num_fields = 1 }, { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -1039,12 +1160,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 341, + .key_start_idx = 349, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1058,7 +1180,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -1072,7 +1194,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1081,11 +1203,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 342, + .key_start_idx = 350, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 311, + .result_start_idx = 327, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 16, @@ -1093,7 +1215,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }, { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -1101,16 +1222,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 355, + .key_start_idx = 363, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 324, + .result_start_idx = 340, .result_bit_size = 62, .result_num_fields = 4 }, @@ -1124,14 +1246,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 328, + .result_start_idx = 344, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12 @@ -1146,14 +1268,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 340, + .result_start_idx = 356, .result_bit_size = 128, .result_num_fields = 26 }, @@ -1167,14 +1289,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 366, + .result_start_idx = 382, .result_bit_size = 128, .result_num_fields = 26 }, @@ -1186,7 +1308,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1196,11 +1318,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 356, + .key_start_idx = 364, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 392, + .result_start_idx = 408, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 16, @@ -1214,7 +1336,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1224,11 +1346,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 369, + .key_start_idx = 377, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 405, + .result_start_idx = 421, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 16, @@ -1236,7 +1358,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }, { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -1244,12 +1365,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 382, + .key_start_idx = 390, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1263,7 +1385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 17, + .cond_start_idx = 19, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, @@ -1277,7 +1399,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1286,11 +1408,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 383, + .key_start_idx = 391, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 418, + .result_start_idx = 434, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 16, @@ -1298,7 +1420,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { }, { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -1306,16 +1427,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 396, + .key_start_idx = 404, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 431, + .result_start_idx = 447, .result_bit_size = 62, .result_num_fields = 4 }, @@ -1327,13 +1449,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 435, + .result_start_idx = 451, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1345,13 +1467,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 436, + .result_start_idx = 452, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1363,13 +1485,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 437, + .result_start_idx = 453, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1383,14 +1505,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, - .result_start_idx = 438, + .result_start_idx = 454, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -1403,7 +1525,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1413,11 +1535,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 397, + .key_start_idx = 405, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 464, + .result_start_idx = 480, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 17, @@ -1433,14 +1555,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 477, + .result_start_idx = 493, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -1455,8 +1577,13 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 1, control.0 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, control.1 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, /* cond_execute: class_tid: 1, profile_tcam.ipv4 */ { @@ -1480,8 +1607,13 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 2, control.0 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, control.1 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, /* cond_execute: class_tid: 2, profile_tcam.ipv4 */ { @@ -1500,8 +1632,8 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 3, control.0 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, /* cond_execute: class_tid: 4, control.0 */ { @@ -1510,13 +1642,13 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 4, control.1 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, /* cond_execute: class_tid: 4, control.2 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.wr */ { @@ -1524,18 +1656,18 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, /* cond_execute: class_tid: 5, control.0 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, /* cond_execute: class_tid: 6, control.0 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS } }; @@ -1563,6 +1695,51 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, + /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } + }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .field_info_mask = { @@ -1769,36 +1946,81 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ @@ -4548,6 +4770,51 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, + /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + } + }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .field_info_mask = { @@ -4786,6 +5053,51 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, + /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + } + }, /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ { .field_info_mask = { @@ -9521,6 +9833,38 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }; struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { + /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -9624,6 +9968,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ { .description = "wc_key_id", @@ -9952,7 +10334,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }, { .description = "flow_sig_id", - .field_bit_size = 8, + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, @@ -10256,6 +10638,38 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, + /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -10368,6 +10782,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ { .description = "wc_key_id", @@ -10696,7 +11148,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }, { .description = "flow_sig_id", - .field_bit_size = 8, + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, @@ -13518,7 +13970,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 8, + .ident_bit_size = 16, .ident_bit_pos = 58 }, { @@ -13571,7 +14023,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 8, + .ident_bit_size = 16, .ident_bit_pos = 58 }, { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 6e2c48e7b6..6e4d4d3ff3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -254,6 +254,7 @@ struct bnxt_ulp_mapper_tbl_info { /* Table opcode for table operations */ uint32_t tbl_opcode; uint32_t tbl_operand; + enum bnxt_ulp_generic_tbl_lkup_type gen_tbl_lkup_type; /* FDB table opcode */ enum bnxt_ulp_fdb_opc fdb_opcode; @@ -300,9 +301,13 @@ struct bnxt_ulp_cache_tbl_params { }; struct bnxt_ulp_generic_tbl_params { + const char *name; uint16_t result_num_entries; uint16_t result_num_bytes; enum bnxt_ulp_byte_order result_byte_order; + uint32_t hash_tbl_entries; + uint16_t num_buckets; + uint16_t key_num_bytes; }; struct bnxt_ulp_shared_act_info { diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index 8e3a920ab4..095a66a0c7 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -923,3 +923,11 @@ uint32_t ulp_bitmap_notzero(uint8_t *bitmap, int32_t size) } return 0; } + +/* returns 0 if input is power of 2 */ +int32_t ulp_util_is_power_of_2(uint64_t x) +{ + if (((x - 1) & x)) + return -1; + return 0; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h index caad5628c9..2d62b25060 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.h +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h @@ -461,4 +461,7 @@ uint32_t ulp_bitmap_is_ones(uint8_t *bitmap, int32_t size); /* Function to check if bitmap is not zero. Return 1 on success */ uint32_t ulp_bitmap_notzero(uint8_t *bitmap, int32_t size); +/* returns 0 if input is power of 2 */ +int32_t ulp_util_is_power_of_2(uint64_t x); + #endif /* _ULP_UTILS_H_ */ From patchwork Sun May 30 08:59:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93696 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9A36A0524; Tue, 1 Jun 2021 09:42:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9675041140; Tue, 1 Jun 2021 09:40:07 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 4040F41103 for ; Sun, 30 May 2021 11:01:50 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id D3AB47DAF; Sun, 30 May 2021 02:01:45 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com D3AB47DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365309; bh=yD36qtJR6lXERsKb0v63B6JK18mKahNAE359OLxj4SU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B1JZpIM4lJEs3y8LLGtD+tqoWAfj+7pRhCt+A7Y/EY5LhBFGfop1NYXibok7xxRM5 +y5mRboO/B16awA2R9viXG1X8U0k0u+9N9uRnGP2iait2b+HYgf2r6aNXwUu9kYj/8 uwilJBy6jH69mglMqvd+CHqVoGPIps/PfayhyE9M= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:17 +0530 Message-Id: <20210530085929.29695-47-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:54 +0200 Subject: [dpdk-dev] [PATCH 46/58] net/bnxt: add support for Thor platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha 1. Add templates to support Thor platform. 2. Flow counter manager is not enabled if no flow counters are configured. 3. Mark database is not enabled if mark action is not supported. 4. Removed application to port default flow. 5. Add allocate and write for the global registry file. 6. Multiple default flow templates are combined to one. 7. Remove default loopback action record, this is required in order to support multiple platforms. 8. Enable port table support in the generic table. 9. remove global template table in orderto support multiple platforms. 10. Add support to get parent VNIC from port table database. 11. VF representor action mark is made optional since not all configurations need representor support. 12. Add layer 4 ports to computational fields. 13. Update templates to support the above changes. 14. Add support for wildcard. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/meson.build | 2 + drivers/net/bnxt/tf_core/tf_core.h | 8 - drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 4 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 101 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 6 +- drivers/net/bnxt/tf_ulp/meson.build | 4 +- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 67 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 18 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 9 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 26 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 14 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 414 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 7 + drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 12 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_matcher.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_matcher.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 88 +- drivers/net/bnxt/tf_ulp/ulp_port_db.h | 31 +- drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 18 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 152 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 7 +- drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 2 +- .../net/bnxt/tf_ulp/ulp_template_db_class.c | 99772 +++++++++------- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 8943 +- .../net/bnxt/tf_ulp/ulp_template_db_field.h | 579 +- .../tf_ulp/ulp_template_db_stingray_act.c | 709 - drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 752 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h | 44 +- .../bnxt/tf_ulp/ulp_template_db_thor_act.c | 229 + ...y_class.c => ulp_template_db_thor_class.c} | 5954 +- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 75 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 5403 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 12 + drivers/net/bnxt/tf_ulp/ulp_tun.h | 4 - drivers/net/bnxt/tf_ulp/ulp_utils.c | 187 +- drivers/net/bnxt/tf_ulp/ulp_utils.h | 66 +- 39 files changed, 68795 insertions(+), 54941 deletions(-) delete mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c rename drivers/net/bnxt/tf_ulp/{ulp_template_db_stingray_class.c => ulp_template_db_thor_class.c} (55%) diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build index f7a4e7a013..71a3b669dd 100644 --- a/drivers/net/bnxt/meson.build +++ b/drivers/net/bnxt/meson.build @@ -8,7 +8,9 @@ if is_windows subdir_done() endif +headers = files('rte_pmd_bnxt.h') cflags_options = [ + '-DRTE_LIBRTE_BNXT_TF', '-DSUPPORT_CFA_HW_ALL=1', ] diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 0b06bb2bb5..be5725a66a 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -1104,10 +1104,6 @@ struct tf_alloc_tbl_scope_parms { * [in] Number of flows * 1000. If set, rx_mem_size_in_mb must equal 0. */ uint32_t rx_num_flows_in_k; - /** - * [in] SR2 only receive table access interface id - */ - uint32_t rx_tbl_if_id; /** * [in] All Maximum key size required. */ @@ -1126,10 +1122,6 @@ struct tf_alloc_tbl_scope_parms { * [in] Number of flows * 1000 */ uint32_t tx_num_flows_in_k; - /** - * [in] SR2 only receive table access interface id - */ - uint32_t tx_tbl_if_id; /** * [in] Flush pending HW cached flows every 1/10th of value * set in seconds, both idle and active flows are flushed diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h index b2629e47b6..f59da41e54 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2019 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -23,12 +23,10 @@ #define BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY 256 #define BNXT_ULP_DFLT_RX_MEM 0 #define BNXT_ULP_RX_NUM_FLOWS 32 -#define BNXT_ULP_RX_TBL_IF_ID 0 #define BNXT_ULP_DFLT_TX_MAX_KEY 512 #define BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY 256 #define BNXT_ULP_DFLT_TX_MEM 0 #define BNXT_ULP_TX_NUM_FLOWS 32 -#define BNXT_ULP_TX_TBL_IF_ID 0 enum bnxt_tf_rc { BNXT_TF_RC_PARSE_ERR = -2, diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index d68cc889c6..141bc0c784 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2020 Broadcom + * Copyright(c) 2019-2021 Broadcom * All rights reserved. */ @@ -22,6 +22,7 @@ #include "ulp_flow_db.h" #include "ulp_mapper.h" #include "ulp_port_db.h" +#include "ulp_tun.h" /* Linked list of all TF sessions. */ STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list = @@ -52,8 +53,11 @@ static int32_t bnxt_ulp_devid_get(struct bnxt *bp, enum bnxt_ulp_device_id *ulp_dev_id) { - if (BNXT_CHIP_P5(bp)) - return -EINVAL; + if (BNXT_CHIP_P5(bp)) { + /* TBD: needs to accommodate even SR2 */ + *ulp_dev_id = BNXT_ULP_DEVICE_ID_THOR; + return 0; + } if (BNXT_STINGRAY(bp)) *ulp_dev_id = BNXT_ULP_DEVICE_ID_STINGRAY; @@ -70,6 +74,7 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp, { uint32_t dev_id; int32_t rc; + uint16_t *tmp_cnt; rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id); if (rc) { @@ -113,6 +118,8 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp, /* SP */ res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 255; + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1; + /** TX **/ /* Identifiers */ res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 292; @@ -148,6 +155,9 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp, /* SP */ res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488; res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 511; + + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1; + break; case BNXT_ULP_DEVICE_ID_STINGRAY: /** RX **/ @@ -219,6 +229,73 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp, /* SP */ res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488; res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 512; + break; + case BNXT_ULP_DEVICE_ID_THOR: + /** RX **/ + /* Identifiers */ + res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 26; + res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 6; + res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 32; + res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 32; + res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 32; + + /* Table Types */ + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 1024; + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 512; + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 14; + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_EM_FKB] = 32; + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_WC_FKB] = 32; + + /* ENCAP */ + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 64; + + /* TCAMs */ + tmp_cnt = &res->tcam_cnt[TF_DIR_RX].cnt[0]; + tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = 300; + tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = 6; + res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 128; + res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 112; + + /* EM */ + res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13200; + + /* SP */ + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 64; + + /** TX **/ + /* Identifiers */ + res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 26; + res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 26; + res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 32; + res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 63; + res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 32; + + /* Table Types */ + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 1024; + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 512; + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 14; + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_EM_FKB] = 32; + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_WC_FKB] = 32; + + /* ENCAP */ + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 64; + + /* TCAMs */ + tmp_cnt = &res->tcam_cnt[TF_DIR_TX].cnt[0]; + + tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = 200; + tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = 110; + res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 128; + res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 128; + + /* EM */ + res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 15232; + + /* SP */ + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 100; + + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1; + break; default: return -EINVAL; @@ -273,6 +350,9 @@ ulp_ctx_session_open(struct bnxt *bp, case BNXT_ULP_DEVICE_ID_STINGRAY: params.device_type = TF_DEVICE_TYPE_SR; break; + case BNXT_ULP_DEVICE_ID_THOR: + params.device_type = TF_DEVICE_TYPE_THOR; + break; default: BNXT_TF_DBG(ERR, "Unable to determine device for " "opening session.\n"); @@ -346,14 +426,12 @@ bnxt_init_tbl_scope_parms(struct bnxt *bp, BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY; params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM; params->rx_num_flows_in_k = BNXT_ULP_RX_NUM_FLOWS; - params->rx_tbl_if_id = BNXT_ULP_RX_TBL_IF_ID; params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY; params->tx_max_action_entry_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY; params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM; params->tx_num_flows_in_k = BNXT_ULP_TX_NUM_FLOWS; - params->tx_tbl_if_id = BNXT_ULP_TX_TBL_IF_ID; } else { params->rx_max_key_sz_in_bits = BNXT_ULP_DFLT_RX_MAX_KEY; params->rx_max_action_entry_sz_in_bits = @@ -361,7 +439,6 @@ bnxt_init_tbl_scope_parms(struct bnxt *bp, params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM; params->rx_num_flows_in_k = dparms->ext_flow_db_num_entries / 1024; - params->rx_tbl_if_id = BNXT_ULP_RX_TBL_IF_ID; params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY; params->tx_max_action_entry_sz_in_bits = @@ -369,7 +446,6 @@ bnxt_init_tbl_scope_parms(struct bnxt *bp, params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM; params->tx_num_flows_in_k = dparms->ext_flow_db_num_entries / 1024; - params->tx_tbl_if_id = BNXT_ULP_TX_TBL_IF_ID; } BNXT_TF_DBG(INFO, "Table Scope initialized with %uK flows.\n", params->rx_num_flows_in_k); @@ -530,6 +606,8 @@ ulp_ctx_init(struct bnxt *bp, if (rc) goto error_deinit; + ulp_tun_tbl_init(ulp_data->tun_tbl); + bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp); return rc; @@ -827,8 +905,7 @@ bnxt_ulp_destroy_vfr_default_rules(struct bnxt *bp, bool global) continue; /* Destroy the flows */ - ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id); - ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id); + ulp_default_flow_destroy(bp->eth_dev, info->vfr_flow_id); /* Clean up the tx action pointer */ vfr_eth_dev = &rte_eth_devices[port_id]; if (vfr_eth_dev) { @@ -1071,7 +1148,11 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } /* create the default rules */ - bnxt_ulp_create_df_rules(bp); + rc = bnxt_ulp_create_df_rules(bp); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to create default flow\n"); + goto jump_to_error; + } if (BNXT_ACCUM_STATS_EN(bp)) bp->ulp_ctx->cfg_data->accum_stats = true; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 47c9c802e2..854eca24c3 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2020 Broadcom + * Copyright(c) 2019-2021 Broadcom * All rights reserved. */ @@ -10,6 +10,7 @@ #include #include +#include "rte_version.h" #include "rte_ethdev.h" #include "ulp_template_db_enum.h" @@ -38,14 +39,12 @@ enum bnxt_ulp_flow_mem_type { }; struct bnxt_ulp_df_rule_info { - uint32_t port_to_app_flow_id; - uint32_t app_to_port_flow_id; + uint32_t def_port_flow_id; uint8_t valid; }; struct bnxt_ulp_vfr_rule_info { - uint32_t rep2vf_flow_id; - uint32_t vf2rep_flow_id; + uint32_t vfr_flow_id; uint16_t parent_port_id; uint8_t valid; }; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 59d75bc496..63fb4b5973 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -70,8 +70,10 @@ bnxt_ulp_set_dir_attributes(struct ulp_rte_parser_params *params, params->dir_attr |= BNXT_ULP_FLOW_ATTR_EGRESS; if (attr->ingress) params->dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS; +#if RTE_VERSION_NUM(17, 11, 10, 16) < RTE_VERSION if (attr->transfer) params->dir_attr |= BNXT_ULP_FLOW_ATTR_TRANSFER; +#endif } void @@ -79,6 +81,7 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, struct ulp_rte_parser_params *params, enum bnxt_ulp_fdb_type flow_type) { + memset(mapper_cparms, 0, sizeof(*mapper_cparms)); mapper_cparms->flow_type = flow_type; mapper_cparms->app_priority = params->priority; mapper_cparms->dir_attr = params->dir_attr; @@ -186,6 +189,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, params.fid = fid; params.func_id = func_id; params.priority = attr->priority; + params.port_id = dev->data->port_id; /* Perform the rte flow post process */ ret = bnxt_ulp_rte_parser_post_process(¶ms); if (ret == BNXT_TF_RC_ERROR) diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build index c7ec5a3161..1bb93d4938 100644 --- a/drivers/net/bnxt/tf_ulp/meson.build +++ b/drivers/net/bnxt/tf_ulp/meson.build @@ -27,5 +27,5 @@ sources += files( 'ulp_rte_handler_tbl.c', 'ulp_template_db_wh_plus_act.c', 'ulp_template_db_wh_plus_class.c', - 'ulp_template_db_stingray_act.c', - 'ulp_template_db_stingray_class.c') + 'ulp_template_db_thor_act.c', + 'ulp_template_db_thor_class.c') diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index ce8bfdc61f..b688288a62 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2020 Broadcom + * Copyright(c) 2019-2021 Broadcom * All rights reserved. */ @@ -457,9 +457,7 @@ bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) return; ulp_default_flow_destroy(bp->eth_dev, - info->port_to_app_flow_id); - ulp_default_flow_destroy(bp->eth_dev, - info->app_to_port_flow_id); + info->def_port_flow_id); memset(info, 0, sizeof(struct bnxt_ulp_df_rule_info)); return; } @@ -471,9 +469,7 @@ bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) continue; ulp_default_flow_destroy(bp->eth_dev, - info->port_to_app_flow_id); - ulp_default_flow_destroy(bp->eth_dev, - info->app_to_port_flow_id); + info->def_port_flow_id); memset(info, 0, sizeof(struct bnxt_ulp_df_rule_info)); } } @@ -496,6 +492,10 @@ bnxt_create_port_app_df_rule(struct bnxt *bp, uint8_t flow_type, } }; + if (!flow_type) { + *flow_id = 0; + return 0; + } return ulp_default_flow_create(bp->eth_dev, param_list, flow_type, flow_id); } @@ -505,7 +505,7 @@ bnxt_ulp_create_df_rules(struct bnxt *bp) { struct bnxt_ulp_df_rule_info *info; uint8_t port_id; - int rc; + int rc = 0; if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev) || !bp->ulp_ctx) @@ -513,39 +513,22 @@ bnxt_ulp_create_df_rules(struct bnxt *bp) port_id = bp->eth_dev->data->port_id; info = &bp->ulp_ctx->cfg_data->df_rule_info[port_id]; - rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_PORT_TO_VS, - &info->port_to_app_flow_id); + rc = bnxt_create_port_app_df_rule(bp, + BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT, + &info->def_port_flow_id); if (rc) { BNXT_TF_DBG(ERR, "Failed to create port to app default rule\n"); return rc; } - bp->tx_cfa_action = 0; - rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_VS_TO_PORT, - &info->app_to_port_flow_id); - if (rc) { - BNXT_TF_DBG(ERR, - "Failed to create app to port default rule\n"); - goto port_to_app_free; - } - rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx, - info->app_to_port_flow_id, + info->def_port_flow_id, &bp->tx_cfa_action); if (rc) - goto app_to_port_free; - + bp->tx_cfa_action = 0; info->valid = true; return 0; - -app_to_port_free: - ulp_default_flow_destroy(bp->eth_dev, info->app_to_port_flow_id); -port_to_app_free: - ulp_default_flow_destroy(bp->eth_dev, info->port_to_app_flow_id); - info->valid = false; - - return rc; } static int32_t @@ -598,22 +581,15 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) } memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info)); - rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_VFREP_TO_VF, - vfr_port_id, - &info->rep2vf_flow_id); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to create VFREP to VF default rule\n"); - goto error; - } - rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_VF_TO_VFREP, + rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_DEFAULT_VFR, vfr_port_id, - &info->vf2rep_flow_id); + &info->vfr_flow_id); if (rc) { - BNXT_TF_DBG(ERR, "Failed to create VF to VFREP default rule\n"); + BNXT_TF_DBG(ERR, "Failed to create VFR default rule\n"); goto error; } rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx, - info->rep2vf_flow_id, + info->vfr_flow_id, &vfr->vfr_tx_cfa_action); if (rc) { BNXT_TF_DBG(ERR, "Failed to get the tx cfa action\n"); @@ -626,10 +602,8 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) return 0; error: - if (info->rep2vf_flow_id) - ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id); - if (info->vf2rep_flow_id) - ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id); + if (info->vfr_flow_id) + ulp_default_flow_destroy(bp->eth_dev, info->vfr_flow_id); return rc; } @@ -653,8 +627,7 @@ bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr) BNXT_TF_DBG(ERR, "VFR already freed\n"); return -EINVAL; } - ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id); - ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id); + ulp_default_flow_destroy(bp->eth_dev, info->vfr_flow_id); vfr->vfr_tx_cfa_action = 0; memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info)); return 0; diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 65029139e6..a25893c63c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -80,6 +80,12 @@ ulp_fc_mgr_init(struct bnxt_ulp_context *ctxt) return -EINVAL; } + if (!dparms->flow_count_db_entries) { + BNXT_TF_DBG(DEBUG, "flow counter support is not enabled\n"); + bnxt_ulp_cntxt_ptr2_fc_info_set(ctxt, NULL); + return 0; + } + ulp_fc_info = rte_zmalloc("ulp_fc_info", sizeof(*ulp_fc_info), 0); if (!ulp_fc_info) goto error; @@ -169,7 +175,10 @@ bool ulp_fc_mgr_thread_isstarted(struct bnxt_ulp_context *ctxt) ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt); - return !!(ulp_fc_info->flags & ULP_FLAG_FC_THREAD); + if (ulp_fc_info) + return !!(ulp_fc_info->flags & ULP_FLAG_FC_THREAD); + + return false; } /* @@ -186,7 +195,7 @@ ulp_fc_mgr_thread_start(struct bnxt_ulp_context *ctxt) ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt); - if (!(ulp_fc_info->flags & ULP_FLAG_FC_THREAD)) { + if (ulp_fc_info && !(ulp_fc_info->flags & ULP_FLAG_FC_THREAD)) { rte_eal_alarm_set(US_PER_S * ULP_FC_TIMER, ulp_fc_mgr_alarm_cb, (void *)ctxt); @@ -459,7 +468,10 @@ bool ulp_fc_mgr_start_idx_isset(struct bnxt_ulp_context *ctxt, enum tf_dir dir) ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt); - return ulp_fc_info->shadow_hw_tbl[dir].start_idx_is_set; + if (ulp_fc_info) + return ulp_fc_info->shadow_hw_tbl[dir].start_idx_is_set; + + return false; } /* diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h index de4d3dfe95..04cb86bea2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2019 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 47c8c48456..8a6a925559 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -522,7 +522,9 @@ ulp_flow_db_init(struct bnxt_ulp_context *ulp_ctxt) bnxt_ulp_cntxt_ptr2_flow_db_set(ulp_ctxt, flow_db); /* Determine the number of flows based on EM type */ - bnxt_ulp_cntxt_mem_type_get(ulp_ctxt, &mtype); + if (bnxt_ulp_cntxt_mem_type_get(ulp_ctxt, &mtype)) + goto error_free; + if (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) num_flows = dparms->int_flow_db_num_entries; else @@ -676,6 +678,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, struct bnxt_ulp_flow_db *flow_db; struct bnxt_ulp_flow_tbl *flow_tbl; struct ulp_fdb_resource_info *resource, *fid_resource; + struct bnxt_ulp_fc_info *ulp_fc_info; uint32_t idx; flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); @@ -728,9 +731,11 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, ulp_flow_db_res_params_to_info(fid_resource, params); } + ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ulp_ctxt); if (params->resource_type == TF_TBL_TYPE_ACT_STATS_64 && params->resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT && + ulp_fc_info) { /* Store the first HW counter ID for this table */ if (!ulp_fc_mgr_start_idx_isset(ulp_ctxt, params->direction)) ulp_fc_mgr_start_idx_set(ulp_ctxt, params->direction, diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c index 0b91520930..5c94e2f5d0 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -246,8 +246,28 @@ ulp_mapper_gen_tbl_entry_data_get(struct ulp_mapper_gen_tbl_entry *entry, return 0; } -/* - * Free the generic table list entry +/* Free the generic table list entry + * + * ulp_ctx [in] - Pointer to the ulp context + * tbl_idx [in] - Index of the generic table + * ckey [in] - Key for the entry in the table + * + * returns 0 on success + */ +int32_t +ulp_mapper_gen_tbl_entry_free(struct bnxt_ulp_context *ulp_ctx, + uint32_t tbl_idx, uint32_t ckey) +{ + struct ulp_flow_db_res_params res; + + res.direction = tbl_idx & 0x1; + res.resource_sub_type = tbl_idx >> 1; + res.resource_hndl = ckey; + + return ulp_mapper_gen_tbl_res_free(ulp_ctx, &res); +} + +/* Free the generic table list resource * * ulp_ctx [in] - Pointer to the ulp context * res [in] - Pointer to flow db resource entry diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h index 7f4a877e9a..f245825142 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h @@ -131,7 +131,7 @@ ulp_mapper_gen_tbl_entry_data_get(struct ulp_mapper_gen_tbl_entry *entry, uint32_t data_size); /* - * Free the generic table list entry + * Free the generic table list resource * * ulp_ctx [in] - Pointer to the ulp context * res [in] - Pointer to flow db resource entry @@ -142,6 +142,18 @@ int32_t ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, struct ulp_flow_db_res_params *res); +/* Free the generic table list entry + * + * ulp_ctx [in] - Pointer to the ulp context + * tbl_idx [in] - Index of the generic table + * ckey [in] - Key for the entry in the table + * + * returns 0 on success + */ +int32_t +ulp_mapper_gen_tbl_entry_free(struct bnxt_ulp_context *ulp_ctx, + uint32_t tbl_idx, uint32_t ckey); + /* * Write the generic table list hash entry * diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 996b80ebbf..90ba38d05b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -133,7 +133,7 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx, rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval); if (rc) { BNXT_TF_DBG(ERR, "Failed to write to global resource id\n"); - /* Free the identifer when update failed */ + /* Free the identifier when update failed */ fparms.dir = iparms.dir; fparms.ident_type = iparms.ident_type; fparms.id = iparms.id; @@ -190,7 +190,7 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval); if (rc) { BNXT_TF_DBG(ERR, "Failed to write to global resource id\n"); - /* Free the identifer when update failed */ + /* Free the identifier when update failed */ free_parms.dir = aparms.dir; free_parms.type = aparms.type; free_parms.idx = aparms.idx; @@ -200,16 +200,6 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, return rc; } -/* Retrieve the global template table */ -static uint32_t * -ulp_mapper_glb_template_table_get(uint32_t *num_entries) -{ - if (!num_entries) - return NULL; - *num_entries = BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ; - return ulp_glb_template_tbl; -} - static int32_t ulp_mapper_glb_field_tbl_get(struct bnxt_ulp_mapper_parms *parms, uint32_t operand, @@ -896,6 +886,20 @@ ulp_mapper_field_port_db_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } break; + case BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC: + if (ulp_port_db_drv_mac_addr_get(parms->ulp_ctx, port_id, + val)) { + BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id); + return -EINVAL; + } + break; + case BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC: + if (ulp_port_db_parent_vnic_get(parms->ulp_ctx, port_id, + val)) { + BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id); + return -EINVAL; + } + break; default: BNXT_TF_DBG(ERR, "Invalid port_data %s\n", fld->description); return -EINVAL; @@ -1676,18 +1680,11 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, sparms.dir = tbl->direction; sparms.tcam_tbl_type = tbl->resource_type; sparms.idx = idx; - /* Already verified the key/mask lengths */ sparms.key = ulp_blob_data_get(key, &tmplen); + sparms.key_sz_in_bits = tmplen; sparms.mask = ulp_blob_data_get(mask, &tmplen); - sparms.key_sz_in_bits = tbl->key_bit_size; sparms.result = ulp_blob_data_get(data, &tmplen); - - if (tbl->result_bit_size != tmplen) { - BNXT_TF_DBG(ERR, "Result len (%d) != Expected (%d)\n", - tmplen, tbl->result_bit_size); - return -EINVAL; - } - sparms.result_sz_in_bits = tbl->result_bit_size; + sparms.result_sz_in_bits = tmplen; if (tf_set_tcam_entry(tfp, &sparms)) { BNXT_TF_DBG(ERR, "tcam[%s][%s][%x] write failed.\n", tf_tcam_tbl_2_str(sparms.tcam_tbl_type), @@ -1705,6 +1702,103 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, return rc; } +/* + * internal function to post process key/mask blobs for dynamic pad WC tcam tbl + * + * parms [in] The mappers parms with data related to the flow. + * + * key [in] The original key to be transformed + * + * mask [in] The original mask to be transformed + * + * tkey [in/out] The transformed key + * + * tmask [in/out] The transformed mask + * + * returns zero on success, non-zero on failure + */ +static uint32_t +ulp_mapper_wc_tcam_tbl_dyn_post_process(struct bnxt_ulp_device_params *dparms, + struct ulp_blob *key, + struct ulp_blob *mask, + struct ulp_blob *tkey, + struct ulp_blob *tmask) +{ + uint16_t tlen, blen, clen, slice_width, num_slices, max_slices, offset; + uint32_t cword, i, rc; + int32_t pad; + uint8_t *val; + + slice_width = dparms->wc_slice_width; + clen = dparms->wc_ctl_size_bits; + max_slices = dparms->wc_max_slices; + blen = ulp_blob_data_len_get(key); + + /* Get the length of the key based on number of slices and width */ + num_slices = 1; + tlen = slice_width; + while (tlen < blen && + num_slices <= max_slices) { + num_slices = num_slices << 1; + tlen = tlen << 1; + } + + if (num_slices > max_slices) { + BNXT_TF_DBG(ERR, "Key size (%d) too large for WC\n", blen); + return -EINVAL; + } + + /* The key/mask may not be on a natural slice boundary, pad it */ + pad = tlen - blen; + if (ulp_blob_pad_push(key, pad) < 0 || + ulp_blob_pad_push(mask, pad) < 0) { + BNXT_TF_DBG(ERR, "Unable to pad key/mask\n"); + return -EINVAL; + } + + /* The new length accounts for the ctrl word length and num slices */ + tlen = tlen + clen * num_slices; + if (!ulp_blob_init(tkey, tlen, key->byte_order) || + !ulp_blob_init(tmask, tlen, mask->byte_order)) { + BNXT_TF_DBG(ERR, "Unable to post process wc tcam entry\n"); + return -EINVAL; + } + + /* Build the transformed key/mask */ + cword = dparms->wc_mode_list[num_slices - 1]; + cword = tfp_cpu_to_be_32(cword); + offset = 0; + for (i = 0; i < num_slices; i++) { + val = ulp_blob_push_32(tkey, &cword, clen); + if (!val) { + BNXT_TF_DBG(ERR, "Key ctrl word push failed\n"); + return -EINVAL; + } + val = ulp_blob_push_32(tmask, &cword, clen); + if (!val) { + BNXT_TF_DBG(ERR, "Mask ctrl word push failed\n"); + return -EINVAL; + } + rc = ulp_blob_append(tkey, key, offset, slice_width); + if (rc) { + BNXT_TF_DBG(ERR, "Key blob append failed\n"); + return rc; + } + rc = ulp_blob_append(tmask, mask, offset, slice_width); + if (rc) { + BNXT_TF_DBG(ERR, "Mask blob append failed\n"); + return rc; + } + offset += slice_width; + } + + /* The key/mask are byte reversed on every 4 byte chunk */ + ulp_blob_perform_byte_reverse(tkey, 4); + ulp_blob_perform_byte_reverse(tmask, 4); + + return 0; +} + /* internal function to post process the key/mask blobs for wildcard tcam tbl */ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob) { @@ -1717,10 +1811,13 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct bnxt_ulp_mapper_tbl_info *tbl) { struct bnxt_ulp_mapper_key_info *kflds; - struct ulp_blob key, mask, data, update_data; + struct ulp_blob okey, omask, data, update_data; + struct ulp_blob tkey, tmask; /* transform key and mask */ + struct ulp_blob *key, *mask; uint32_t i, num_kflds; struct tf *tfp; int32_t rc, trc; + struct bnxt_ulp_device_params *dparms = parms->device_params; struct tf_alloc_tcam_entry_parms aparms = { 0 }; struct tf_search_tcam_entry_parms searchparms = { 0 }; struct ulp_flow_db_res_params fid_parms = { 0 }; @@ -1729,6 +1826,10 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, uint16_t tmplen = 0; uint16_t idx; + /* Set the key and mask to the original key and mask. */ + key = &okey; + mask = &omask; + /* Skip this if table opcode is NOP */ if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_NOT_USED || tbl->tbl_opcode >= BNXT_ULP_TCAM_TBL_OPC_LAST) { @@ -1749,23 +1850,15 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } - if (!ulp_blob_init(&key, tbl->blob_key_bit_size, - parms->device_params->byte_order) || - !ulp_blob_init(&mask, tbl->blob_key_bit_size, - parms->device_params->byte_order) || - !ulp_blob_init(&data, tbl->result_bit_size, - parms->device_params->byte_order) || + if (!ulp_blob_init(key, tbl->blob_key_bit_size, tbl->byte_order) || + !ulp_blob_init(mask, tbl->blob_key_bit_size, tbl->byte_order) || + !ulp_blob_init(&data, tbl->result_bit_size, dparms->byte_order) || !ulp_blob_init(&update_data, tbl->result_bit_size, - parms->device_params->byte_order)) { + dparms->byte_order)) { BNXT_TF_DBG(ERR, "blob inits failed.\n"); return -EINVAL; } - if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) { - key.byte_order = BNXT_ULP_BYTE_ORDER_BE; - mask.byte_order = BNXT_ULP_BYTE_ORDER_BE; - } - /* create the key/mask */ /* * NOTE: The WC table will require some kind of flag to handle the @@ -1775,7 +1868,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* Setup the key */ rc = ulp_mapper_field_process(parms, tbl->direction, &kflds[i].field_info_spec, - &key, 1, "TCAM Key"); + key, 1, "TCAM Key"); if (rc) { BNXT_TF_DBG(ERR, "Key field set failed %s\n", kflds[i].field_info_spec.description); @@ -1785,7 +1878,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* Setup the mask */ rc = ulp_mapper_field_process(parms, tbl->direction, &kflds[i].field_info_mask, - &mask, 0, "TCAM Mask"); + mask, 0, "TCAM Mask"); if (rc) { BNXT_TF_DBG(ERR, "Mask field set failed %s\n", kflds[i].field_info_mask.description); @@ -1795,28 +1888,34 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* For wild card tcam perform the post process to swap the blob */ if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) { - ulp_mapper_wc_tcam_tbl_post_process(&key); - ulp_mapper_wc_tcam_tbl_post_process(&mask); + if (dparms->dynamic_pad_en) { + /* Sets up the slices for writing to the WC TCAM */ + rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms, + key, mask, + &tkey, + &tmask); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed to post proc WC entry.\n"); + return rc; + } + /* Now need to use the transform Key/Mask */ + key = &tkey; + mask = &tmask; + } else { + ulp_mapper_wc_tcam_tbl_post_process(key); + ulp_mapper_wc_tcam_tbl_post_process(mask); + } + } if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE) { /* allocate the tcam index */ aparms.dir = tbl->direction; aparms.tcam_tbl_type = tbl->resource_type; - aparms.key = ulp_blob_data_get(&key, &tmplen); + aparms.key = ulp_blob_data_get(key, &tmplen); aparms.key_sz_in_bits = tmplen; - if (tbl->blob_key_bit_size != tmplen) { - BNXT_TF_DBG(ERR, "Key len (%d) != Expected (%d)\n", - tmplen, tbl->blob_key_bit_size); - return -EINVAL; - } - - aparms.mask = ulp_blob_data_get(&mask, &tmplen); - if (tbl->blob_key_bit_size != tmplen) { - BNXT_TF_DBG(ERR, "Mask len (%d) != Expected (%d)\n", - tmplen, tbl->blob_key_bit_size); - return -EINVAL; - } + aparms.mask = ulp_blob_data_get(mask, &tmplen); /* calculate the entry priority */ rc = ulp_mapper_priority_opc_process(parms, tbl, @@ -1840,9 +1939,9 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, */ searchparms.dir = tbl->direction; searchparms.tcam_tbl_type = tbl->resource_type; - searchparms.key = ulp_blob_data_get(&key, &tmplen); + searchparms.key = ulp_blob_data_get(key, &tmplen); searchparms.key_sz_in_bits = tbl->key_bit_size; - searchparms.mask = ulp_blob_data_get(&mask, &tmplen); + searchparms.mask = ulp_blob_data_get(mask, &tmplen); searchparms.alloc = 1; searchparms.result = ulp_blob_data_get(&data, &tmplen); searchparms.result_sz_in_bits = tbl->result_bit_size; @@ -1890,8 +1989,8 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, "TCAM Result"); /* write the tcam entry */ if (!rc) - rc = ulp_mapper_tcam_tbl_entry_write(parms, tbl, &key, - &mask, &data, idx); + rc = ulp_mapper_tcam_tbl_entry_write(parms, tbl, key, + mask, &data, idx); } else { /*Scan identifier list, extract identifier and update regfile*/ rc = ulp_mapper_tcam_tbl_scan_ident_extract(parms, tbl, &data); @@ -1938,8 +2037,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct tf_insert_em_entry_parms iparms = { 0 }; struct tf_delete_em_entry_parms free_parms = { 0 }; enum bnxt_ulp_flow_mem_type mtype; + struct bnxt_ulp_device_params *dparms = parms->device_params; int32_t trc; int32_t rc = 0; + int32_t pad = 0; rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype); if (rc) { @@ -1955,9 +2056,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* Initialize the key/result blobs */ if (!ulp_blob_init(&key, tbl->blob_key_bit_size, - parms->device_params->byte_order) || + tbl->byte_order) || !ulp_blob_init(&data, tbl->result_bit_size, - parms->device_params->byte_order)) { + tbl->byte_order)) { BNXT_TF_DBG(ERR, "blob inits failed.\n"); return -EINVAL; } @@ -1974,10 +2075,19 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, } } - /* - * TBD: Normally should process identifiers in case of using recycle or - * loopback. Not supporting recycle for now. - */ + /* if dynamic padding is enabled then add padding to result data */ + if (dparms->dynamic_pad_en) { + /* add padding to make sure key is at byte boundary */ + ulp_blob_pad_align(&key, ULP_BUFFER_ALIGN_8_BITS); + + /* add the pad */ + pad = dparms->em_blk_align_bits - dparms->em_blk_size_bits; + if (pad < 0) { + BNXT_TF_DBG(ERR, "Invalid em blk size and align\n"); + return -EINVAL; + } + ulp_blob_pad_push(&data, (uint32_t)pad); + } /* Create the result data blob */ rc = ulp_mapper_tbl_result_build(parms, tbl, &data, "EM Result"); @@ -1985,9 +2095,33 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, BNXT_TF_DBG(ERR, "Failed to build the result blob\n"); return rc; } + if (dparms->dynamic_pad_en) { + uint32_t abits = dparms->em_blk_align_bits; + + /* when dynamic padding is enabled merge result + key */ + rc = ulp_blob_block_merge(&data, &key, abits, pad); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to merge the result blob\n"); + return rc; + } + + /* add padding to make sure merged result is at slice boundary*/ + ulp_blob_pad_align(&data, abits); + + ulp_blob_perform_byte_reverse(&data, ULP_BITS_2_BYTE(abits)); + } + /* do the transpose for the internal EM keys */ - if (tbl->resource_type == TF_MEM_INTERNAL) - ulp_blob_perform_byte_reverse(&key); + if (tbl->resource_type == TF_MEM_INTERNAL) { + if (dparms->em_key_align_bytes) { + int32_t b = ULP_BYTE_2_BITS(dparms->em_key_align_bytes); + + tmplen = ulp_blob_data_len_get(&key); + ulp_blob_pad_push(&key, b - tmplen); + } + tmplen = ulp_blob_data_len_get(&key); + ulp_blob_perform_byte_reverse(&key, ULP_BITS_2_BYTE(tmplen)); + } rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, &iparms.tbl_scope_id); @@ -2006,7 +2140,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, iparms.key = ulp_blob_data_get(&key, &tmplen); iparms.key_sz_in_bits = tbl->key_bit_size; iparms.em_record = ulp_blob_data_get(&data, &tmplen); - iparms.em_record_sz_in_bits = tbl->result_bit_size; + if (tbl->result_bit_size) + iparms.em_record_sz_in_bits = tbl->result_bit_size; + else + iparms.em_record_sz_in_bits = tmplen; rc = tf_insert_em_entry(tfp, &iparms); if (rc) { @@ -2064,19 +2201,19 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct ulp_blob data; uint64_t regval = 0; uint16_t tmplen; - uint32_t index, hit; + uint32_t index; int32_t rc = 0, trc = 0; struct tf_alloc_tbl_entry_parms aparms = { 0 }; - struct tf_search_tbl_entry_parms srchparms = { 0 }; struct tf_set_tbl_entry_parms sparms = { 0 }; struct tf_get_tbl_entry_parms gparms = { 0 }; struct tf_free_tbl_entry_parms free_parms = { 0 }; uint32_t tbl_scope_id; struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); + struct bnxt_ulp_glb_resource_info glb_res; uint16_t bit_size; bool alloc = false; bool write = false; - bool search = false; + bool global = false; uint64_t act_rec_size; /* use the max size if encap is enabled */ @@ -2111,21 +2248,6 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, alloc = true; write = true; break; - case BNXT_ULP_INDEX_TBL_OPC_SRCH_ALLOC_WR_REGFILE: - if (tbl->resource_type == TF_TBL_TYPE_EXT) { - /* Not currently supporting with EXT */ - BNXT_TF_DBG(ERR, - "Ext Table Search Opcode not supported.\n"); - return -EINVAL; - } - /* - * Search for the entry in the tf core. If it is hit, save the - * index in the regfile. If it is a miss, Build the entry, - * alloc an index, write the table, and store the data in the - * regfile (same as ALLOC_WR). - */ - search = true; - break; case BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE: /* * get the index to write to from the regfile and then write @@ -2146,6 +2268,19 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, write = true; break; + case BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE: + /* + * Build the entry, alloc an index, write the table, and store + * the data in the global regfile. + */ + alloc = true; + global = true; + write = true; + glb_res.direction = tbl->direction; + glb_res.resource_func = tbl->resource_func; + glb_res.resource_type = tbl->resource_type; + glb_res.glb_regfile_index = tbl->tbl_operand; + break; case BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE: if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) { BNXT_TF_DBG(ERR, "Template error, wrong fdb opcode\n"); @@ -2222,7 +2357,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } - if (write || search) { + if (write) { /* Get the result fields list */ rc = ulp_mapper_tbl_result_build(parms, tbl, @@ -2234,36 +2369,6 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, } } - if (search) { - /* Use the result blob to perform a search */ - memset(&srchparms, 0, sizeof(srchparms)); - srchparms.dir = tbl->direction; - srchparms.type = tbl->resource_type; - srchparms.alloc = 1; - srchparms.result = ulp_blob_data_get(&data, &tmplen); - srchparms.result_sz_in_bytes = ULP_BITS_2_BYTE(tmplen); - srchparms.tbl_scope_id = tbl_scope_id; - rc = tf_search_tbl_entry(tfp, &srchparms); - if (rc) { - BNXT_TF_DBG(ERR, "Alloc table[%s][%s] failed rc=%d\n", - tf_tbl_type_2_str(tbl->resource_type), - tf_dir_2_str(tbl->direction), rc); - return rc; - } - if (srchparms.search_status == REJECT) { - BNXT_TF_DBG(ERR, "Alloc table[%s][%s] rejected.\n", - tf_tbl_type_2_str(tbl->resource_type), - tf_dir_2_str(tbl->direction)); - return -ENOMEM; - } - index = srchparms.idx; - hit = srchparms.hit; - if (hit) - write = false; - else - write = true; - } - if (alloc) { aparms.dir = tbl->direction; aparms.type = tbl->resource_type; @@ -2278,9 +2383,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } index = aparms.idx; - } - if (search || alloc) { /* * Store the index in the regfile since we either allocated it * or it was a hit. @@ -2294,12 +2397,19 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, regval = TF_ACT_REC_OFFSET_2_PTR(index); else regval = index; + regval = tfp_cpu_to_be_64(regval); - rc = ulp_regfile_write(parms->regfile, - tbl->tbl_operand, - tfp_cpu_to_be_64(regval)); + if (global) { + rc = ulp_mapper_glb_resource_write(parms->mapper_data, + &glb_res, regval); + } else { + rc = ulp_regfile_write(parms->regfile, + tbl->tbl_operand, regval); + } if (rc) { - BNXT_TF_DBG(ERR, "Failed to write regfile[%d] rc=%d\n", + BNXT_TF_DBG(ERR, + "Failed to write %s regfile[%d] rc=%d\n", + (global) ? "global" : "reg", tbl->tbl_operand, rc); goto error; } @@ -2476,7 +2586,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* * TBD: Need to look at the need to store idx in flow db for restore - * the table to its orginial state on deletion of this entry. + * the table to its original state on deletion of this entry. */ return rc; } @@ -3312,62 +3422,6 @@ ulp_mapper_flow_destroy(struct bnxt_ulp_context *ulp_ctx, return rc; } -/* Function to handle the default global templates that are allocated during - * the startup and reused later. - */ -static int32_t -ulp_mapper_glb_template_table_init(struct bnxt_ulp_context *ulp_ctx) -{ - uint32_t *glbl_tmpl_list; - uint32_t num_glb_tmpls, idx, dev_id; - struct bnxt_ulp_mapper_parms parms; - struct bnxt_ulp_mapper_data *mapper_data; - int32_t rc = 0; - - glbl_tmpl_list = ulp_mapper_glb_template_table_get(&num_glb_tmpls); - if (!glbl_tmpl_list || !num_glb_tmpls) - return rc; /* No global templates to process */ - - /* Get the device id from the ulp context */ - if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id)) { - BNXT_TF_DBG(ERR, "Invalid ulp context\n"); - return -EINVAL; - } - - mapper_data = bnxt_ulp_cntxt_ptr2_mapper_data_get(ulp_ctx); - if (!mapper_data) { - BNXT_TF_DBG(ERR, "Failed to get the ulp mapper data\n"); - return -EINVAL; - } - - /* Iterate the global resources and process each one */ - for (idx = 0; idx < num_glb_tmpls; idx++) { - /* Initialize the parms structure */ - memset(&parms, 0, sizeof(parms)); - parms.tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); - parms.ulp_ctx = ulp_ctx; - parms.dev_id = dev_id; - parms.mapper_data = mapper_data; - parms.flow_type = BNXT_ULP_FDB_TYPE_DEFAULT; - parms.tmpl_type = BNXT_ULP_TEMPLATE_TYPE_CLASS; - - /* Get the class table entry from dev id and class id */ - parms.class_tid = glbl_tmpl_list[idx]; - - parms.device_params = bnxt_ulp_device_params_get(parms.dev_id); - if (!parms.device_params) { - BNXT_TF_DBG(ERR, "No device for device id %d\n", - parms.dev_id); - return -EINVAL; - } - - rc = ulp_mapper_tbls_process(&parms, parms.class_tid); - if (rc) - return rc; - } - return rc; -} - /* Function to handle the mapping of the Flow to be compatible * with the underlying hardware. */ @@ -3442,6 +3496,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, rc = ulp_mapper_tbls_process(&parms, parms.act_tid); if (rc) goto flow_error; + cparms->shared_hndl = parms.shared_hndl; } if (parms.class_tid) { @@ -3520,13 +3575,6 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx) goto error; } - /* Allocate global template table entries */ - rc = ulp_mapper_glb_template_table_init(ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to initialize global templates\n"); - goto error; - } - return 0; error: /* Ignore the return code in favor of returning the original error. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 8f0b894d39..8652dd203c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -82,6 +82,7 @@ struct bnxt_ulp_mapper_create_parms { /* if set then create a parent flow */ uint32_t parent_flow; uint8_t tun_idx; + uint64_t shared_hndl; /* support pattern based rejection */ uint32_t flow_pattern_id; @@ -120,4 +121,10 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx, enum bnxt_ulp_fdb_type flow_type, uint32_t fid); +int32_t +ulp_mapper_get_shared_fid(struct bnxt_ulp_context *ulp, + uint32_t id, + uint16_t key, + uint32_t *fid); + #endif /* _ULP_MAPPER_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c index 8b8dccf9f1..271520e1d3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -73,6 +73,12 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt) return -EINVAL; } + if (!dparms->mark_db_lfid_entries || !dparms->mark_db_gfid_entries) { + BNXT_TF_DBG(DEBUG, "mark Table is not allocated\n"); + bnxt_ulp_cntxt_ptr2_mark_db_set(ctxt, NULL); + return 0; + } + mark_tbl = rte_zmalloc("ulp_rx_mark_tbl_ptr", sizeof(struct bnxt_ulp_mark_tbl), 0); if (!mark_tbl) @@ -182,10 +188,8 @@ ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt, return -EINVAL; mtbl = bnxt_ulp_cntxt_ptr2_mark_db_get(ctxt); - if (!mtbl) { - BNXT_TF_DBG(ERR, "Unable to get Mark Table\n"); + if (!mtbl) return -EINVAL; - } idx = ulp_mark_db_idx_get(is_gfid, fid, mtbl); diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h index 9696730cc2..d9d82d4644 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2019 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c index 21eb97b7eb..46ac57ac00 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h index a582188252..dc2487889c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.h +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 2ee79ea3fe..96fc456d4c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -8,6 +8,7 @@ #include "bnxt_vnic.h" #include "bnxt_tf_common.h" #include "ulp_port_db.h" +#include "tfp.h" static uint32_t ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db) @@ -186,6 +187,7 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt, * the kernel. And to send it to the kernel, we need the PF's vnic id. */ func->func_parent_vnic = bnxt_get_parent_vnic_id(port_id, intf->type); + func->func_parent_vnic = tfp_cpu_to_be_16(func->func_parent_vnic); bnxt_get_iface_mac(port_id, intf->type, func->func_mac, func->func_parent_mac); @@ -587,11 +589,32 @@ ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt, return 0; } +/* internal function to get the */ +static struct ulp_func_if_info* +ulp_port_db_func_if_info_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id) +{ + struct bnxt_ulp_port_db *port_db; + uint16_t func_id; + + port_db = bnxt_ulp_cntxt_ptr2_port_db_get(ulp_ctxt); + if (ulp_port_db_port_func_id_get(ulp_ctxt, port_id, &func_id)) { + BNXT_TF_DBG(ERR, "Invalid port_id %x\n", port_id); + return NULL; + } + + if (!port_db->ulp_func_id_tbl[func_id].func_valid) { + BNXT_TF_DBG(ERR, "Invalid func_id %x\n", func_id); + return NULL; + } + return &port_db->ulp_func_id_tbl[func_id]; +} + /* * Api to get the parent mac address for a given port id. * * ulp_ctxt [in] Ptr to ulp context - * port_id [in].device port id + * port_id [in] device port id * mac_addr [out] mac address * * Returns 0 on success or negative number on failure. @@ -600,19 +623,58 @@ int32_t ulp_port_db_parent_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t port_id, uint8_t **mac_addr) { - struct bnxt_ulp_port_db *port_db; - uint16_t func_id; + struct ulp_func_if_info *info; - port_db = bnxt_ulp_cntxt_ptr2_port_db_get(ulp_ctxt); - if (ulp_port_db_port_func_id_get(ulp_ctxt, port_id, &func_id)) { - BNXT_TF_DBG(ERR, "Invalid port_id %x\n", port_id); - return -EINVAL; + info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id); + if (info) { + *mac_addr = info->func_parent_mac; + return 0; } + return -EINVAL; +} - if (!port_db->ulp_func_id_tbl[func_id].func_valid) { - BNXT_TF_DBG(ERR, "Invalid func_id %x\n", func_id); - return -ENOENT; +/* + * Api to get the mac address for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * mac_addr [out] mac address + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_drv_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint8_t **mac_addr) +{ + struct ulp_func_if_info *info; + + info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id); + if (info) { + *mac_addr = info->func_mac; + return 0; } - *mac_addr = port_db->ulp_func_id_tbl[func_id].func_parent_mac; - return 0; + return -EINVAL; +} + +/* + * Api to get the parent vnic for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * vnic [out] parent vnic + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint8_t **vnic) +{ + struct ulp_func_if_info *info; + + info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id); + if (info) { + *vnic = (uint8_t *)&info->func_parent_vnic; + return 0; + } + return -EINVAL; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h index b10a7ea58c..740c186e12 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2019 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -279,7 +279,7 @@ ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt, * Api to get the parent mac address for a given port id. * * ulp_ctxt [in] Ptr to ulp context - * port_id [in].device port id + * port_id [in] device port id * mac_addr [out] mac address * * Returns 0 on success or negative number on failure. @@ -287,4 +287,31 @@ ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt, int32_t ulp_port_db_parent_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t port_id, uint8_t **mac_addr); + +/* + * Api to get the mac address for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * mac_addr [out] mac address + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_drv_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint8_t **mac_addr); + +/* + * Api to get the parent vnic for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * vnic [out] parent vnic + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint8_t **vnic); + #endif /* _ULP_PORT_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c index 8e466255d9..7bd499faa6 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -208,6 +208,10 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = { [RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = { .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, .proto_act_func = NULL + }, + [RTE_FLOW_ACTION_TYPE_SAMPLE] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_sample_act_handler } }; @@ -230,8 +234,8 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ANY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_item_any_handler }, [RTE_FLOW_ITEM_TYPE_PF] = { .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, @@ -270,8 +274,8 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { .proto_hdr_func = ulp_rte_ipv6_hdr_handler }, [RTE_FLOW_ITEM_TYPE_ICMP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_icmp_hdr_handler }, [RTE_FLOW_ITEM_TYPE_UDP] = { .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, @@ -302,8 +306,8 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_GRE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_gre_hdr_handler }, [RTE_FLOW_ITEM_TYPE_FUZZY] = { .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 1522328a5d..0e585e502e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -874,6 +874,32 @@ ulp_rte_l3_proto_type_update(struct ulp_rte_parser_params *param, BNXT_ULP_HDR_BIT_O_TCP); ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L4, 1); } + } else if (proto == IPPROTO_GRE) { + ULP_BITMAP_SET(param->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_GRE); + } else if (proto == IPPROTO_ICMP) { + if (ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_L3_TUN)) + ULP_BITMAP_SET(param->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_I_ICMP); + else + ULP_BITMAP_SET(param->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_O_ICMP); + } + if (proto) { + if (in_flag) { + ULP_COMP_FLD_IDX_WR(param, + BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID, + 1); + ULP_COMP_FLD_IDX_WR(param, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID, + proto); + } else { + ULP_COMP_FLD_IDX_WR(param, + BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID, + 1); + ULP_COMP_FLD_IDX_WR(param, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID, + proto); + } } } @@ -1022,9 +1048,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, if (ipv4_mask) proto &= ipv4_mask->hdr.next_proto_id; - if (proto == IPPROTO_GRE) - ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); - /* Update the field protocol hdr bitmap */ ulp_rte_l3_proto_type_update(params, proto, inner_flag); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); @@ -1170,9 +1193,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, if (ipv6_mask) proto &= ipv6_mask->hdr.proto; - if (proto == IPPROTO_GRE) - ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); - /* Update the field protocol hdr bitmap */ ulp_rte_l3_proto_type_update(params, proto, inner_flag); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); @@ -1185,11 +1205,16 @@ static void ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param, uint16_t dst_port) { - if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) { + if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) ULP_BITMAP_SET(param->hdr_fp_bit.bits, BNXT_ULP_HDR_BIT_T_VXLAN); + + if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_T_VXLAN) || + ULP_BITMAP_ISSET(param->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_T_GRE)) ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1); - } + } /* Function to handle the parsing of RTE Flow item UDP Header. */ @@ -1203,7 +1228,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; uint32_t size; - uint16_t dport = 0; + uint16_t dport = 0, sport = 0; uint32_t cnt; cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT); @@ -1221,6 +1246,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], &udp_spec->hdr.src_port, size); + sport = udp_spec->hdr.src_port; size = sizeof(udp_spec->hdr.dst_port); field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dst_port, @@ -1258,6 +1284,14 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT, + (uint32_t)rte_be_to_cpu_16(sport)); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT, + (uint32_t)rte_be_to_cpu_16(dport)); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID, + 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID, + IPPROTO_UDP); if (udp_mask && udp_mask->hdr.src_port) ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT, @@ -1266,10 +1300,17 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT, 1); - } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT, + (uint32_t)rte_be_to_cpu_16(sport)); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT, + (uint32_t)rte_be_to_cpu_16(dport)); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID, + 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID, + IPPROTO_UDP); if (udp_mask && udp_mask->hdr.src_port) ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT, @@ -1296,6 +1337,7 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; + uint16_t dport = 0, sport = 0; uint32_t size; uint32_t cnt; @@ -1310,10 +1352,12 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, * header fields */ if (tcp_spec) { + sport = tcp_spec->hdr.src_port; size = sizeof(tcp_spec->hdr.src_port); field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], &tcp_spec->hdr.src_port, size); + dport = tcp_spec->hdr.dst_port; size = sizeof(tcp_spec->hdr.dst_port); field = ulp_rte_parser_fld_copy(field, &tcp_spec->hdr.dst_port, @@ -1387,6 +1431,14 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT, + (uint32_t)rte_be_to_cpu_16(sport)); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT, + (uint32_t)rte_be_to_cpu_16(dport)); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID, + 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID, + IPPROTO_TCP); if (tcp_mask && tcp_mask->hdr.src_port) ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT, @@ -1398,6 +1450,14 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT, + (uint32_t)rte_be_to_cpu_16(sport)); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT, + (uint32_t)rte_be_to_cpu_16(dport)); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID, + 1); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID, + IPPROTO_TCP); if (tcp_mask && tcp_mask->hdr.src_port) ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT, @@ -1464,6 +1524,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item, /* Update the hdr_bitmap with vxlan */ ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN); + ulp_rte_l4_proto_type_update(params, 0); return BNXT_TF_RC_SUCCESS; } @@ -1479,11 +1540,6 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item, uint32_t size; struct ulp_rte_hdr_field *field; - if (!gre_spec && !gre_mask) { - BNXT_TF_DBG(ERR, "Parse Error: GRE item is invalid\n"); - return BNXT_TF_RC_ERROR; - } - if (gre_spec) { size = sizeof(gre_spec->c_rsvd0_ver); field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], @@ -1507,6 +1563,7 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item, /* Update the hdr_bitmap with GRE */ ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); + ulp_rte_l4_proto_type_update(params, 0); return BNXT_TF_RC_SUCCESS; } @@ -1518,6 +1575,68 @@ ulp_rte_item_any_handler(const struct rte_flow_item *item __rte_unused, return BNXT_TF_RC_SUCCESS; } +/* Function to handle the parsing of RTE Flow item ICMP Header. */ +int32_t +ulp_rte_icmp_hdr_handler(const struct rte_flow_item *item, + struct ulp_rte_parser_params *params) +{ + const struct rte_flow_item_icmp *icmp_spec = item->spec; + const struct rte_flow_item_icmp *icmp_mask = item->mask; + struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; + uint32_t idx = params->field_idx; + uint32_t size; + struct ulp_rte_hdr_field *field; + + if (icmp_spec) { + size = sizeof(icmp_spec->hdr.icmp_type); + field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], + &icmp_spec->hdr.icmp_type, + size); + size = sizeof(icmp_spec->hdr.icmp_code); + field = ulp_rte_parser_fld_copy(field, + &icmp_spec->hdr.icmp_code, + size); + size = sizeof(icmp_spec->hdr.icmp_cksum); + field = ulp_rte_parser_fld_copy(field, + &icmp_spec->hdr.icmp_cksum, + size); + size = sizeof(icmp_spec->hdr.icmp_ident); + field = ulp_rte_parser_fld_copy(field, + &icmp_spec->hdr.icmp_ident, + size); + size = sizeof(icmp_spec->hdr.icmp_seq_nb); + field = ulp_rte_parser_fld_copy(field, + &icmp_spec->hdr.icmp_seq_nb, + size); + } + if (icmp_mask) { + ulp_rte_prsr_mask_copy(params, &idx, + &icmp_mask->hdr.icmp_type, + sizeof(icmp_mask->hdr.icmp_type)); + ulp_rte_prsr_mask_copy(params, &idx, + &icmp_mask->hdr.icmp_code, + sizeof(icmp_mask->hdr.icmp_code)); + ulp_rte_prsr_mask_copy(params, &idx, + &icmp_mask->hdr.icmp_cksum, + sizeof(icmp_mask->hdr.icmp_cksum)); + ulp_rte_prsr_mask_copy(params, &idx, + &icmp_mask->hdr.icmp_ident, + sizeof(icmp_mask->hdr.icmp_ident)); + ulp_rte_prsr_mask_copy(params, &idx, + &icmp_mask->hdr.icmp_seq_nb, + sizeof(icmp_mask->hdr.icmp_seq_nb)); + } + /* Add number of GRE header elements */ + params->field_idx += BNXT_ULP_PROTO_HDR_ICMP_NUM; + + /* Update the hdr_bitmap with ICMP */ + if (ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) + ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_ICMP); + else + ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ICMP); + return BNXT_TF_RC_SUCCESS; +} + /* Function to handle the parsing of RTE Flow item void Header */ int32_t ulp_rte_void_hdr_handler(const struct rte_flow_item *item __rte_unused, @@ -1872,7 +1991,6 @@ ulp_rte_drop_act_handler(const struct rte_flow_action *action_item __rte_unused, int32_t ulp_rte_count_act_handler(const struct rte_flow_action *action_item, struct ulp_rte_parser_params *params) - { const struct rte_flow_action_count *act_count; struct ulp_rte_act_prop *act_prop = ¶ms->act_prop; diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index 48a20e84b1..664878401a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -135,6 +135,11 @@ int32_t ulp_rte_item_any_handler(const struct rte_flow_item *item __rte_unused, struct ulp_rte_parser_params *params __rte_unused); +/* Function to handle the parsing of RTE Flow item ICMP Header. */ +int32_t +ulp_rte_icmp_hdr_handler(const struct rte_flow_item *item, + struct ulp_rte_parser_params *params); + /* Function to handle the parsing of RTE Flow item void Header. */ int32_t ulp_rte_void_hdr_handler(const struct rte_flow_item *item, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index c848b70777..500bf215d9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index 5c7b95bd08..e9e7feb64c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ -/* date: Fri Jan 29 09:44:41 2021 */ +/* date: Wed Mar 3 12:15:37 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -16,16643 +16,17795 @@ * maps hash id to ulp_class_match_list[] index */ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_26d1] = 1, - [BNXT_ULP_CLASS_HID_0071] = 2, - [BNXT_ULP_CLASS_HID_53a5] = 3, - [BNXT_ULP_CLASS_HID_1d49] = 4, - [BNXT_ULP_CLASS_HID_2095] = 5, - [BNXT_ULP_CLASS_HID_5701] = 6, - [BNXT_ULP_CLASS_HID_4d79] = 7, - [BNXT_ULP_CLASS_HID_170d] = 8, - [BNXT_ULP_CLASS_HID_1a69] = 9, - [BNXT_ULP_CLASS_HID_50c5] = 10, - [BNXT_ULP_CLASS_HID_473d] = 11, - [BNXT_ULP_CLASS_HID_10c1] = 12, - [BNXT_ULP_CLASS_HID_142d] = 13, - [BNXT_ULP_CLASS_HID_4a99] = 14, - [BNXT_ULP_CLASS_HID_40f1] = 15, - [BNXT_ULP_CLASS_HID_0a85] = 16, - [BNXT_ULP_CLASS_HID_0179] = 17, - [BNXT_ULP_CLASS_HID_37d5] = 18, - [BNXT_ULP_CLASS_HID_2e4d] = 19, - [BNXT_ULP_CLASS_HID_54ad] = 20, - [BNXT_ULP_CLASS_HID_5809] = 21, - [BNXT_ULP_CLASS_HID_31a9] = 22, - [BNXT_ULP_CLASS_HID_2801] = 23, - [BNXT_ULP_CLASS_HID_4e61] = 24, - [BNXT_ULP_CLASS_HID_2561] = 25, - [BNXT_ULP_CLASS_HID_2bad] = 26, - [BNXT_ULP_CLASS_HID_054d] = 27, - [BNXT_ULP_CLASS_HID_5bdd] = 28, - [BNXT_ULP_CLASS_HID_26f1] = 29, - [BNXT_ULP_CLASS_HID_13cf1] = 30, - [BNXT_ULP_CLASS_HID_252f1] = 31, - [BNXT_ULP_CLASS_HID_30c25] = 32, - [BNXT_ULP_CLASS_HID_0051] = 33, - [BNXT_ULP_CLASS_HID_11651] = 34, - [BNXT_ULP_CLASS_HID_22c51] = 35, - [BNXT_ULP_CLASS_HID_34251] = 36, - [BNXT_ULP_CLASS_HID_5385] = 37, - [BNXT_ULP_CLASS_HID_10cc9] = 38, - [BNXT_ULP_CLASS_HID_222c9] = 39, - [BNXT_ULP_CLASS_HID_338c9] = 40, - [BNXT_ULP_CLASS_HID_1d69] = 41, - [BNXT_ULP_CLASS_HID_13369] = 42, - [BNXT_ULP_CLASS_HID_24969] = 43, - [BNXT_ULP_CLASS_HID_3025d] = 44, - [BNXT_ULP_CLASS_HID_20b5] = 45, - [BNXT_ULP_CLASS_HID_136b5] = 46, - [BNXT_ULP_CLASS_HID_24cb5] = 47, - [BNXT_ULP_CLASS_HID_305f9] = 48, - [BNXT_ULP_CLASS_HID_5721] = 49, - [BNXT_ULP_CLASS_HID_11015] = 50, - [BNXT_ULP_CLASS_HID_22615] = 51, - [BNXT_ULP_CLASS_HID_33c15] = 52, - [BNXT_ULP_CLASS_HID_4d59] = 53, - [BNXT_ULP_CLASS_HID_1068d] = 54, - [BNXT_ULP_CLASS_HID_21c8d] = 55, - [BNXT_ULP_CLASS_HID_3328d] = 56, - [BNXT_ULP_CLASS_HID_172d] = 57, - [BNXT_ULP_CLASS_HID_12d2d] = 58, - [BNXT_ULP_CLASS_HID_2432d] = 59, - [BNXT_ULP_CLASS_HID_3592d] = 60, - [BNXT_ULP_CLASS_HID_1a49] = 61, - [BNXT_ULP_CLASS_HID_13049] = 62, - [BNXT_ULP_CLASS_HID_24649] = 63, - [BNXT_ULP_CLASS_HID_35c49] = 64, - [BNXT_ULP_CLASS_HID_50e5] = 65, - [BNXT_ULP_CLASS_HID_10a29] = 66, - [BNXT_ULP_CLASS_HID_22029] = 67, - [BNXT_ULP_CLASS_HID_33629] = 68, - [BNXT_ULP_CLASS_HID_471d] = 69, - [BNXT_ULP_CLASS_HID_10041] = 70, - [BNXT_ULP_CLASS_HID_21641] = 71, - [BNXT_ULP_CLASS_HID_32c41] = 72, - [BNXT_ULP_CLASS_HID_10e1] = 73, - [BNXT_ULP_CLASS_HID_126e1] = 74, - [BNXT_ULP_CLASS_HID_23ce1] = 75, - [BNXT_ULP_CLASS_HID_352e1] = 76, - [BNXT_ULP_CLASS_HID_140d] = 77, - [BNXT_ULP_CLASS_HID_12a0d] = 78, - [BNXT_ULP_CLASS_HID_2400d] = 79, - [BNXT_ULP_CLASS_HID_3560d] = 80, - [BNXT_ULP_CLASS_HID_4ab9] = 81, - [BNXT_ULP_CLASS_HID_103ed] = 82, - [BNXT_ULP_CLASS_HID_219ed] = 83, - [BNXT_ULP_CLASS_HID_32fed] = 84, - [BNXT_ULP_CLASS_HID_40d1] = 85, - [BNXT_ULP_CLASS_HID_156d1] = 86, - [BNXT_ULP_CLASS_HID_21005] = 87, - [BNXT_ULP_CLASS_HID_32605] = 88, - [BNXT_ULP_CLASS_HID_0aa5] = 89, - [BNXT_ULP_CLASS_HID_120a5] = 90, - [BNXT_ULP_CLASS_HID_236a5] = 91, - [BNXT_ULP_CLASS_HID_34ca5] = 92, - [BNXT_ULP_CLASS_HID_0159] = 93, - [BNXT_ULP_CLASS_HID_11759] = 94, - [BNXT_ULP_CLASS_HID_22d59] = 95, - [BNXT_ULP_CLASS_HID_34359] = 96, - [BNXT_ULP_CLASS_HID_37f5] = 97, - [BNXT_ULP_CLASS_HID_14df5] = 98, - [BNXT_ULP_CLASS_HID_20739] = 99, - [BNXT_ULP_CLASS_HID_31d39] = 100, - [BNXT_ULP_CLASS_HID_2e6d] = 101, - [BNXT_ULP_CLASS_HID_1446d] = 102, - [BNXT_ULP_CLASS_HID_25a6d] = 103, - [BNXT_ULP_CLASS_HID_31351] = 104, - [BNXT_ULP_CLASS_HID_548d] = 105, - [BNXT_ULP_CLASS_HID_10df1] = 106, - [BNXT_ULP_CLASS_HID_223f1] = 107, - [BNXT_ULP_CLASS_HID_339f1] = 108, - [BNXT_ULP_CLASS_HID_5829] = 109, - [BNXT_ULP_CLASS_HID_1111d] = 110, - [BNXT_ULP_CLASS_HID_2271d] = 111, - [BNXT_ULP_CLASS_HID_33d1d] = 112, - [BNXT_ULP_CLASS_HID_3189] = 113, - [BNXT_ULP_CLASS_HID_14789] = 114, - [BNXT_ULP_CLASS_HID_200fd] = 115, - [BNXT_ULP_CLASS_HID_316fd] = 116, - [BNXT_ULP_CLASS_HID_2821] = 117, - [BNXT_ULP_CLASS_HID_13e21] = 118, - [BNXT_ULP_CLASS_HID_25421] = 119, - [BNXT_ULP_CLASS_HID_30d15] = 120, - [BNXT_ULP_CLASS_HID_4e41] = 121, - [BNXT_ULP_CLASS_HID_107b5] = 122, - [BNXT_ULP_CLASS_HID_21db5] = 123, - [BNXT_ULP_CLASS_HID_333b5] = 124, - [BNXT_ULP_CLASS_HID_2541] = 125, - [BNXT_ULP_CLASS_HID_2b8d] = 126, - [BNXT_ULP_CLASS_HID_056d] = 127, - [BNXT_ULP_CLASS_HID_5bfd] = 128, - [BNXT_ULP_CLASS_HID_2691] = 129, - [BNXT_ULP_CLASS_HID_13c91] = 130, - [BNXT_ULP_CLASS_HID_25291] = 131, - [BNXT_ULP_CLASS_HID_30c45] = 132, - [BNXT_ULP_CLASS_HID_0031] = 133, - [BNXT_ULP_CLASS_HID_11631] = 134, - [BNXT_ULP_CLASS_HID_22c31] = 135, - [BNXT_ULP_CLASS_HID_34231] = 136, - [BNXT_ULP_CLASS_HID_53e5] = 137, - [BNXT_ULP_CLASS_HID_10ca9] = 138, - [BNXT_ULP_CLASS_HID_222a9] = 139, - [BNXT_ULP_CLASS_HID_338a9] = 140, - [BNXT_ULP_CLASS_HID_1d09] = 141, - [BNXT_ULP_CLASS_HID_13309] = 142, - [BNXT_ULP_CLASS_HID_24909] = 143, - [BNXT_ULP_CLASS_HID_3023d] = 144, - [BNXT_ULP_CLASS_HID_20d5] = 145, - [BNXT_ULP_CLASS_HID_136d5] = 146, - [BNXT_ULP_CLASS_HID_24cd5] = 147, - [BNXT_ULP_CLASS_HID_30599] = 148, - [BNXT_ULP_CLASS_HID_5741] = 149, - [BNXT_ULP_CLASS_HID_11075] = 150, - [BNXT_ULP_CLASS_HID_22675] = 151, - [BNXT_ULP_CLASS_HID_33c75] = 152, - [BNXT_ULP_CLASS_HID_4d39] = 153, - [BNXT_ULP_CLASS_HID_106ed] = 154, - [BNXT_ULP_CLASS_HID_21ced] = 155, - [BNXT_ULP_CLASS_HID_332ed] = 156, - [BNXT_ULP_CLASS_HID_174d] = 157, - [BNXT_ULP_CLASS_HID_12d4d] = 158, - [BNXT_ULP_CLASS_HID_2434d] = 159, - [BNXT_ULP_CLASS_HID_3594d] = 160, - [BNXT_ULP_CLASS_HID_1a29] = 161, - [BNXT_ULP_CLASS_HID_13029] = 162, - [BNXT_ULP_CLASS_HID_24629] = 163, - [BNXT_ULP_CLASS_HID_35c29] = 164, - [BNXT_ULP_CLASS_HID_5085] = 165, - [BNXT_ULP_CLASS_HID_10a49] = 166, - [BNXT_ULP_CLASS_HID_22049] = 167, - [BNXT_ULP_CLASS_HID_33649] = 168, - [BNXT_ULP_CLASS_HID_477d] = 169, - [BNXT_ULP_CLASS_HID_10021] = 170, - [BNXT_ULP_CLASS_HID_21621] = 171, - [BNXT_ULP_CLASS_HID_32c21] = 172, - [BNXT_ULP_CLASS_HID_1081] = 173, - [BNXT_ULP_CLASS_HID_12681] = 174, - [BNXT_ULP_CLASS_HID_23c81] = 175, - [BNXT_ULP_CLASS_HID_35281] = 176, - [BNXT_ULP_CLASS_HID_146d] = 177, - [BNXT_ULP_CLASS_HID_12a6d] = 178, - [BNXT_ULP_CLASS_HID_2406d] = 179, - [BNXT_ULP_CLASS_HID_3566d] = 180, - [BNXT_ULP_CLASS_HID_4ad9] = 181, - [BNXT_ULP_CLASS_HID_1038d] = 182, - [BNXT_ULP_CLASS_HID_2198d] = 183, - [BNXT_ULP_CLASS_HID_32f8d] = 184, - [BNXT_ULP_CLASS_HID_40b1] = 185, - [BNXT_ULP_CLASS_HID_156b1] = 186, - [BNXT_ULP_CLASS_HID_21065] = 187, - [BNXT_ULP_CLASS_HID_32665] = 188, - [BNXT_ULP_CLASS_HID_0ac5] = 189, - [BNXT_ULP_CLASS_HID_120c5] = 190, - [BNXT_ULP_CLASS_HID_236c5] = 191, - [BNXT_ULP_CLASS_HID_34cc5] = 192, - [BNXT_ULP_CLASS_HID_0139] = 193, - [BNXT_ULP_CLASS_HID_11739] = 194, - [BNXT_ULP_CLASS_HID_22d39] = 195, - [BNXT_ULP_CLASS_HID_34339] = 196, - [BNXT_ULP_CLASS_HID_3795] = 197, - [BNXT_ULP_CLASS_HID_14d95] = 198, - [BNXT_ULP_CLASS_HID_20759] = 199, - [BNXT_ULP_CLASS_HID_31d59] = 200, - [BNXT_ULP_CLASS_HID_2e0d] = 201, - [BNXT_ULP_CLASS_HID_1440d] = 202, - [BNXT_ULP_CLASS_HID_25a0d] = 203, - [BNXT_ULP_CLASS_HID_31331] = 204, - [BNXT_ULP_CLASS_HID_54ed] = 205, - [BNXT_ULP_CLASS_HID_10d91] = 206, - [BNXT_ULP_CLASS_HID_22391] = 207, - [BNXT_ULP_CLASS_HID_33991] = 208, - [BNXT_ULP_CLASS_HID_5849] = 209, - [BNXT_ULP_CLASS_HID_1117d] = 210, - [BNXT_ULP_CLASS_HID_2277d] = 211, - [BNXT_ULP_CLASS_HID_33d7d] = 212, - [BNXT_ULP_CLASS_HID_31e9] = 213, - [BNXT_ULP_CLASS_HID_147e9] = 214, - [BNXT_ULP_CLASS_HID_2009d] = 215, - [BNXT_ULP_CLASS_HID_3169d] = 216, - [BNXT_ULP_CLASS_HID_2841] = 217, - [BNXT_ULP_CLASS_HID_13e41] = 218, - [BNXT_ULP_CLASS_HID_25441] = 219, - [BNXT_ULP_CLASS_HID_30d75] = 220, - [BNXT_ULP_CLASS_HID_4e21] = 221, - [BNXT_ULP_CLASS_HID_107d5] = 222, - [BNXT_ULP_CLASS_HID_21dd5] = 223, - [BNXT_ULP_CLASS_HID_333d5] = 224, - [BNXT_ULP_CLASS_HID_2521] = 225, - [BNXT_ULP_CLASS_HID_2bed] = 226, - [BNXT_ULP_CLASS_HID_050d] = 227, - [BNXT_ULP_CLASS_HID_5b9d] = 228, - [BNXT_ULP_CLASS_HID_1865] = 229, - [BNXT_ULP_CLASS_HID_389d] = 230, - [BNXT_ULP_CLASS_HID_123d] = 231, - [BNXT_ULP_CLASS_HID_4ef1] = 232, - [BNXT_ULP_CLASS_HID_1229] = 233, - [BNXT_ULP_CLASS_HID_3241] = 234, - [BNXT_ULP_CLASS_HID_0be1] = 235, - [BNXT_ULP_CLASS_HID_48b5] = 236, - [BNXT_ULP_CLASS_HID_0bed] = 237, - [BNXT_ULP_CLASS_HID_2c05] = 238, - [BNXT_ULP_CLASS_HID_05a5] = 239, - [BNXT_ULP_CLASS_HID_4279] = 240, - [BNXT_ULP_CLASS_HID_05d1] = 241, - [BNXT_ULP_CLASS_HID_25c9] = 242, - [BNXT_ULP_CLASS_HID_5c55] = 243, - [BNXT_ULP_CLASS_HID_3c3d] = 244, - [BNXT_ULP_CLASS_HID_4fc9] = 245, - [BNXT_ULP_CLASS_HID_1335] = 246, - [BNXT_ULP_CLASS_HID_4981] = 247, - [BNXT_ULP_CLASS_HID_2969] = 248, - [BNXT_ULP_CLASS_HID_498d] = 249, - [BNXT_ULP_CLASS_HID_0cf9] = 250, - [BNXT_ULP_CLASS_HID_4345] = 251, - [BNXT_ULP_CLASS_HID_232d] = 252, - [BNXT_ULP_CLASS_HID_2579] = 253, - [BNXT_ULP_CLASS_HID_2bb5] = 254, - [BNXT_ULP_CLASS_HID_4bad] = 255, - [BNXT_ULP_CLASS_HID_4591] = 256, - [BNXT_ULP_CLASS_HID_1845] = 257, - [BNXT_ULP_CLASS_HID_1399] = 258, - [BNXT_ULP_CLASS_HID_0eed] = 259, - [BNXT_ULP_CLASS_HID_0a21] = 260, - [BNXT_ULP_CLASS_HID_38bd] = 261, - [BNXT_ULP_CLASS_HID_33f1] = 262, - [BNXT_ULP_CLASS_HID_2ec5] = 263, - [BNXT_ULP_CLASS_HID_2a19] = 264, - [BNXT_ULP_CLASS_HID_121d] = 265, - [BNXT_ULP_CLASS_HID_0d51] = 266, - [BNXT_ULP_CLASS_HID_08a5] = 267, - [BNXT_ULP_CLASS_HID_03f9] = 268, - [BNXT_ULP_CLASS_HID_4ed1] = 269, - [BNXT_ULP_CLASS_HID_4a25] = 270, - [BNXT_ULP_CLASS_HID_4579] = 271, - [BNXT_ULP_CLASS_HID_404d] = 272, - [BNXT_ULP_CLASS_HID_1209] = 273, - [BNXT_ULP_CLASS_HID_0d5d] = 274, - [BNXT_ULP_CLASS_HID_0891] = 275, - [BNXT_ULP_CLASS_HID_03e5] = 276, - [BNXT_ULP_CLASS_HID_3261] = 277, - [BNXT_ULP_CLASS_HID_2db5] = 278, - [BNXT_ULP_CLASS_HID_2889] = 279, - [BNXT_ULP_CLASS_HID_23dd] = 280, - [BNXT_ULP_CLASS_HID_0bc1] = 281, - [BNXT_ULP_CLASS_HID_0715] = 282, - [BNXT_ULP_CLASS_HID_0269] = 283, - [BNXT_ULP_CLASS_HID_5a69] = 284, - [BNXT_ULP_CLASS_HID_4895] = 285, - [BNXT_ULP_CLASS_HID_43e9] = 286, - [BNXT_ULP_CLASS_HID_3f3d] = 287, - [BNXT_ULP_CLASS_HID_3a71] = 288, - [BNXT_ULP_CLASS_HID_0bcd] = 289, - [BNXT_ULP_CLASS_HID_0701] = 290, - [BNXT_ULP_CLASS_HID_0255] = 291, - [BNXT_ULP_CLASS_HID_5a55] = 292, - [BNXT_ULP_CLASS_HID_2c25] = 293, - [BNXT_ULP_CLASS_HID_2779] = 294, - [BNXT_ULP_CLASS_HID_224d] = 295, - [BNXT_ULP_CLASS_HID_1d81] = 296, - [BNXT_ULP_CLASS_HID_0585] = 297, - [BNXT_ULP_CLASS_HID_00d9] = 298, - [BNXT_ULP_CLASS_HID_58d9] = 299, - [BNXT_ULP_CLASS_HID_542d] = 300, - [BNXT_ULP_CLASS_HID_4259] = 301, - [BNXT_ULP_CLASS_HID_3dad] = 302, - [BNXT_ULP_CLASS_HID_38e1] = 303, - [BNXT_ULP_CLASS_HID_3435] = 304, - [BNXT_ULP_CLASS_HID_05f1] = 305, - [BNXT_ULP_CLASS_HID_00c5] = 306, - [BNXT_ULP_CLASS_HID_58c5] = 307, - [BNXT_ULP_CLASS_HID_5419] = 308, - [BNXT_ULP_CLASS_HID_25e9] = 309, - [BNXT_ULP_CLASS_HID_213d] = 310, - [BNXT_ULP_CLASS_HID_1c71] = 311, - [BNXT_ULP_CLASS_HID_1745] = 312, - [BNXT_ULP_CLASS_HID_5c75] = 313, - [BNXT_ULP_CLASS_HID_5749] = 314, - [BNXT_ULP_CLASS_HID_529d] = 315, - [BNXT_ULP_CLASS_HID_4dd1] = 316, - [BNXT_ULP_CLASS_HID_3c1d] = 317, - [BNXT_ULP_CLASS_HID_3751] = 318, - [BNXT_ULP_CLASS_HID_32a5] = 319, - [BNXT_ULP_CLASS_HID_2df9] = 320, - [BNXT_ULP_CLASS_HID_4fe9] = 321, - [BNXT_ULP_CLASS_HID_4b3d] = 322, - [BNXT_ULP_CLASS_HID_4671] = 323, - [BNXT_ULP_CLASS_HID_4145] = 324, - [BNXT_ULP_CLASS_HID_1315] = 325, - [BNXT_ULP_CLASS_HID_0e69] = 326, - [BNXT_ULP_CLASS_HID_09bd] = 327, - [BNXT_ULP_CLASS_HID_04f1] = 328, - [BNXT_ULP_CLASS_HID_49a1] = 329, - [BNXT_ULP_CLASS_HID_44f5] = 330, - [BNXT_ULP_CLASS_HID_3fc9] = 331, - [BNXT_ULP_CLASS_HID_3b1d] = 332, - [BNXT_ULP_CLASS_HID_2949] = 333, - [BNXT_ULP_CLASS_HID_249d] = 334, - [BNXT_ULP_CLASS_HID_1fd1] = 335, - [BNXT_ULP_CLASS_HID_1b25] = 336, - [BNXT_ULP_CLASS_HID_49ad] = 337, - [BNXT_ULP_CLASS_HID_44e1] = 338, - [BNXT_ULP_CLASS_HID_4035] = 339, - [BNXT_ULP_CLASS_HID_3b09] = 340, - [BNXT_ULP_CLASS_HID_0cd9] = 341, - [BNXT_ULP_CLASS_HID_082d] = 342, - [BNXT_ULP_CLASS_HID_0361] = 343, - [BNXT_ULP_CLASS_HID_5b61] = 344, - [BNXT_ULP_CLASS_HID_4365] = 345, - [BNXT_ULP_CLASS_HID_3eb9] = 346, - [BNXT_ULP_CLASS_HID_398d] = 347, - [BNXT_ULP_CLASS_HID_34c1] = 348, - [BNXT_ULP_CLASS_HID_230d] = 349, - [BNXT_ULP_CLASS_HID_1e41] = 350, - [BNXT_ULP_CLASS_HID_1995] = 351, - [BNXT_ULP_CLASS_HID_14e9] = 352, - [BNXT_ULP_CLASS_HID_2559] = 353, - [BNXT_ULP_CLASS_HID_2b95] = 354, - [BNXT_ULP_CLASS_HID_4b8d] = 355, - [BNXT_ULP_CLASS_HID_45b1] = 356, - [BNXT_ULP_CLASS_HID_1825] = 357, - [BNXT_ULP_CLASS_HID_13f9] = 358, - [BNXT_ULP_CLASS_HID_0e8d] = 359, - [BNXT_ULP_CLASS_HID_0a41] = 360, - [BNXT_ULP_CLASS_HID_38dd] = 361, - [BNXT_ULP_CLASS_HID_3391] = 362, - [BNXT_ULP_CLASS_HID_2ea5] = 363, - [BNXT_ULP_CLASS_HID_2a79] = 364, - [BNXT_ULP_CLASS_HID_127d] = 365, - [BNXT_ULP_CLASS_HID_0d31] = 366, - [BNXT_ULP_CLASS_HID_08c5] = 367, - [BNXT_ULP_CLASS_HID_0399] = 368, - [BNXT_ULP_CLASS_HID_4eb1] = 369, - [BNXT_ULP_CLASS_HID_4a45] = 370, - [BNXT_ULP_CLASS_HID_4519] = 371, - [BNXT_ULP_CLASS_HID_402d] = 372, - [BNXT_ULP_CLASS_HID_1269] = 373, - [BNXT_ULP_CLASS_HID_0d3d] = 374, - [BNXT_ULP_CLASS_HID_08f1] = 375, - [BNXT_ULP_CLASS_HID_0385] = 376, - [BNXT_ULP_CLASS_HID_3201] = 377, - [BNXT_ULP_CLASS_HID_2dd5] = 378, - [BNXT_ULP_CLASS_HID_28e9] = 379, - [BNXT_ULP_CLASS_HID_23bd] = 380, - [BNXT_ULP_CLASS_HID_0ba1] = 381, - [BNXT_ULP_CLASS_HID_0775] = 382, - [BNXT_ULP_CLASS_HID_0209] = 383, - [BNXT_ULP_CLASS_HID_5a09] = 384, - [BNXT_ULP_CLASS_HID_48f5] = 385, - [BNXT_ULP_CLASS_HID_4389] = 386, - [BNXT_ULP_CLASS_HID_3f5d] = 387, - [BNXT_ULP_CLASS_HID_3a11] = 388, - [BNXT_ULP_CLASS_HID_0bad] = 389, - [BNXT_ULP_CLASS_HID_0761] = 390, - [BNXT_ULP_CLASS_HID_0235] = 391, - [BNXT_ULP_CLASS_HID_5a35] = 392, - [BNXT_ULP_CLASS_HID_2c45] = 393, - [BNXT_ULP_CLASS_HID_2719] = 394, - [BNXT_ULP_CLASS_HID_222d] = 395, - [BNXT_ULP_CLASS_HID_1de1] = 396, - [BNXT_ULP_CLASS_HID_05e5] = 397, - [BNXT_ULP_CLASS_HID_00b9] = 398, - [BNXT_ULP_CLASS_HID_58b9] = 399, - [BNXT_ULP_CLASS_HID_544d] = 400, - [BNXT_ULP_CLASS_HID_4239] = 401, - [BNXT_ULP_CLASS_HID_3dcd] = 402, - [BNXT_ULP_CLASS_HID_3881] = 403, - [BNXT_ULP_CLASS_HID_3455] = 404, - [BNXT_ULP_CLASS_HID_0591] = 405, - [BNXT_ULP_CLASS_HID_00a5] = 406, - [BNXT_ULP_CLASS_HID_58a5] = 407, - [BNXT_ULP_CLASS_HID_5479] = 408, - [BNXT_ULP_CLASS_HID_2589] = 409, - [BNXT_ULP_CLASS_HID_215d] = 410, - [BNXT_ULP_CLASS_HID_1c11] = 411, - [BNXT_ULP_CLASS_HID_1725] = 412, - [BNXT_ULP_CLASS_HID_5c15] = 413, - [BNXT_ULP_CLASS_HID_5729] = 414, - [BNXT_ULP_CLASS_HID_52fd] = 415, - [BNXT_ULP_CLASS_HID_4db1] = 416, - [BNXT_ULP_CLASS_HID_3c7d] = 417, - [BNXT_ULP_CLASS_HID_3731] = 418, - [BNXT_ULP_CLASS_HID_32c5] = 419, - [BNXT_ULP_CLASS_HID_2d99] = 420, - [BNXT_ULP_CLASS_HID_4f89] = 421, - [BNXT_ULP_CLASS_HID_4b5d] = 422, - [BNXT_ULP_CLASS_HID_4611] = 423, - [BNXT_ULP_CLASS_HID_4125] = 424, - [BNXT_ULP_CLASS_HID_1375] = 425, - [BNXT_ULP_CLASS_HID_0e09] = 426, - [BNXT_ULP_CLASS_HID_09dd] = 427, - [BNXT_ULP_CLASS_HID_0491] = 428, - [BNXT_ULP_CLASS_HID_49c1] = 429, - [BNXT_ULP_CLASS_HID_4495] = 430, - [BNXT_ULP_CLASS_HID_3fa9] = 431, - [BNXT_ULP_CLASS_HID_3b7d] = 432, - [BNXT_ULP_CLASS_HID_2929] = 433, - [BNXT_ULP_CLASS_HID_24fd] = 434, - [BNXT_ULP_CLASS_HID_1fb1] = 435, - [BNXT_ULP_CLASS_HID_1b45] = 436, - [BNXT_ULP_CLASS_HID_49cd] = 437, - [BNXT_ULP_CLASS_HID_4481] = 438, - [BNXT_ULP_CLASS_HID_4055] = 439, - [BNXT_ULP_CLASS_HID_3b69] = 440, - [BNXT_ULP_CLASS_HID_0cb9] = 441, - [BNXT_ULP_CLASS_HID_084d] = 442, - [BNXT_ULP_CLASS_HID_0301] = 443, - [BNXT_ULP_CLASS_HID_5b01] = 444, - [BNXT_ULP_CLASS_HID_4305] = 445, - [BNXT_ULP_CLASS_HID_3ed9] = 446, - [BNXT_ULP_CLASS_HID_39ed] = 447, - [BNXT_ULP_CLASS_HID_34a1] = 448, - [BNXT_ULP_CLASS_HID_236d] = 449, - [BNXT_ULP_CLASS_HID_1e21] = 450, - [BNXT_ULP_CLASS_HID_19f5] = 451, - [BNXT_ULP_CLASS_HID_1489] = 452, - [BNXT_ULP_CLASS_HID_2539] = 453, - [BNXT_ULP_CLASS_HID_2bf5] = 454, - [BNXT_ULP_CLASS_HID_4bed] = 455, - [BNXT_ULP_CLASS_HID_45d1] = 456, - [BNXT_ULP_CLASS_HID_b6af] = 457, - [BNXT_ULP_CLASS_HID_b1d3] = 458, - [BNXT_ULP_CLASS_HID_1c7d3] = 459, - [BNXT_ULP_CLASS_HID_1ccaf] = 460, - [BNXT_ULP_CLASS_HID_da33] = 461, - [BNXT_ULP_CLASS_HID_d567] = 462, - [BNXT_ULP_CLASS_HID_18eab] = 463, - [BNXT_ULP_CLASS_HID_19367] = 464, - [BNXT_ULP_CLASS_HID_a10b] = 465, - [BNXT_ULP_CLASS_HID_9c3f] = 466, - [BNXT_ULP_CLASS_HID_1b23f] = 467, - [BNXT_ULP_CLASS_HID_1b70b] = 468, - [BNXT_ULP_CLASS_HID_c49f] = 469, - [BNXT_ULP_CLASS_HID_bfc3] = 470, - [BNXT_ULP_CLASS_HID_1d5c3] = 471, - [BNXT_ULP_CLASS_HID_1da9f] = 472, - [BNXT_ULP_CLASS_HID_b063] = 473, - [BNXT_ULP_CLASS_HID_ab97] = 474, - [BNXT_ULP_CLASS_HID_1c197] = 475, - [BNXT_ULP_CLASS_HID_1c663] = 476, - [BNXT_ULP_CLASS_HID_d3f7] = 477, - [BNXT_ULP_CLASS_HID_cf3b] = 478, - [BNXT_ULP_CLASS_HID_1886f] = 479, - [BNXT_ULP_CLASS_HID_18d3b] = 480, - [BNXT_ULP_CLASS_HID_9acf] = 481, - [BNXT_ULP_CLASS_HID_95f3] = 482, - [BNXT_ULP_CLASS_HID_1abf3] = 483, - [BNXT_ULP_CLASS_HID_1b0cf] = 484, - [BNXT_ULP_CLASS_HID_be53] = 485, - [BNXT_ULP_CLASS_HID_b987] = 486, - [BNXT_ULP_CLASS_HID_1cf87] = 487, - [BNXT_ULP_CLASS_HID_1d453] = 488, - [BNXT_ULP_CLASS_HID_aa27] = 489, - [BNXT_ULP_CLASS_HID_a56b] = 490, - [BNXT_ULP_CLASS_HID_1bb6b] = 491, - [BNXT_ULP_CLASS_HID_1c027] = 492, - [BNXT_ULP_CLASS_HID_cdcb] = 493, - [BNXT_ULP_CLASS_HID_c8ff] = 494, - [BNXT_ULP_CLASS_HID_18223] = 495, - [BNXT_ULP_CLASS_HID_186ff] = 496, - [BNXT_ULP_CLASS_HID_9483] = 497, - [BNXT_ULP_CLASS_HID_8fb7] = 498, - [BNXT_ULP_CLASS_HID_1a5b7] = 499, - [BNXT_ULP_CLASS_HID_1aa83] = 500, - [BNXT_ULP_CLASS_HID_b817] = 501, - [BNXT_ULP_CLASS_HID_b35b] = 502, - [BNXT_ULP_CLASS_HID_1c95b] = 503, - [BNXT_ULP_CLASS_HID_1ce17] = 504, - [BNXT_ULP_CLASS_HID_a3fb] = 505, - [BNXT_ULP_CLASS_HID_9f2f] = 506, - [BNXT_ULP_CLASS_HID_1b52f] = 507, - [BNXT_ULP_CLASS_HID_1b9fb] = 508, - [BNXT_ULP_CLASS_HID_c78f] = 509, - [BNXT_ULP_CLASS_HID_c2b3] = 510, - [BNXT_ULP_CLASS_HID_1d8b3] = 511, - [BNXT_ULP_CLASS_HID_180b3] = 512, - [BNXT_ULP_CLASS_HID_8e47] = 513, - [BNXT_ULP_CLASS_HID_898b] = 514, - [BNXT_ULP_CLASS_HID_19f8b] = 515, - [BNXT_ULP_CLASS_HID_1a447] = 516, - [BNXT_ULP_CLASS_HID_b1eb] = 517, - [BNXT_ULP_CLASS_HID_ad1f] = 518, - [BNXT_ULP_CLASS_HID_1c31f] = 519, - [BNXT_ULP_CLASS_HID_1c7eb] = 520, - [BNXT_ULP_CLASS_HID_9137] = 521, - [BNXT_ULP_CLASS_HID_8c7b] = 522, - [BNXT_ULP_CLASS_HID_1a27b] = 523, - [BNXT_ULP_CLASS_HID_1a737] = 524, - [BNXT_ULP_CLASS_HID_b4db] = 525, - [BNXT_ULP_CLASS_HID_b00f] = 526, - [BNXT_ULP_CLASS_HID_1c60f] = 527, - [BNXT_ULP_CLASS_HID_1cadb] = 528, - [BNXT_ULP_CLASS_HID_8b0b] = 529, - [BNXT_ULP_CLASS_HID_863f] = 530, - [BNXT_ULP_CLASS_HID_19c3f] = 531, - [BNXT_ULP_CLASS_HID_1a10b] = 532, - [BNXT_ULP_CLASS_HID_ae9f] = 533, - [BNXT_ULP_CLASS_HID_a9c3] = 534, - [BNXT_ULP_CLASS_HID_1bfc3] = 535, - [BNXT_ULP_CLASS_HID_1c49f] = 536, - [BNXT_ULP_CLASS_HID_2563] = 537, - [BNXT_ULP_CLASS_HID_2baf] = 538, - [BNXT_ULP_CLASS_HID_26d3] = 539, - [BNXT_ULP_CLASS_HID_4f33] = 540, - [BNXT_ULP_CLASS_HID_4a67] = 541, - [BNXT_ULP_CLASS_HID_160b] = 542, - [BNXT_ULP_CLASS_HID_113f] = 543, - [BNXT_ULP_CLASS_HID_399f] = 544, - [BNXT_ULP_CLASS_HID_34c3] = 545, - [BNXT_ULP_CLASS_HID_2097] = 546, - [BNXT_ULP_CLASS_HID_48f7] = 547, - [BNXT_ULP_CLASS_HID_443b] = 548, - [BNXT_ULP_CLASS_HID_0fcf] = 549, - [BNXT_ULP_CLASS_HID_0af3] = 550, - [BNXT_ULP_CLASS_HID_3353] = 551, - [BNXT_ULP_CLASS_HID_2e87] = 552, - [BNXT_ULP_CLASS_HID_b68f] = 553, - [BNXT_ULP_CLASS_HID_b94f] = 554, - [BNXT_ULP_CLASS_HID_fc0f] = 555, - [BNXT_ULP_CLASS_HID_fecf] = 556, - [BNXT_ULP_CLASS_HID_b1f3] = 557, - [BNXT_ULP_CLASS_HID_b4b3] = 558, - [BNXT_ULP_CLASS_HID_f773] = 559, - [BNXT_ULP_CLASS_HID_fa33] = 560, - [BNXT_ULP_CLASS_HID_1c7f3] = 561, - [BNXT_ULP_CLASS_HID_1eab3] = 562, - [BNXT_ULP_CLASS_HID_1cd73] = 563, - [BNXT_ULP_CLASS_HID_1f033] = 564, - [BNXT_ULP_CLASS_HID_1cc8f] = 565, - [BNXT_ULP_CLASS_HID_1ef4f] = 566, - [BNXT_ULP_CLASS_HID_1d20f] = 567, - [BNXT_ULP_CLASS_HID_1f4cf] = 568, - [BNXT_ULP_CLASS_HID_da13] = 569, - [BNXT_ULP_CLASS_HID_a007] = 570, - [BNXT_ULP_CLASS_HID_c2c7] = 571, - [BNXT_ULP_CLASS_HID_e587] = 572, - [BNXT_ULP_CLASS_HID_d547] = 573, - [BNXT_ULP_CLASS_HID_f807] = 574, - [BNXT_ULP_CLASS_HID_dac7] = 575, - [BNXT_ULP_CLASS_HID_e0cb] = 576, - [BNXT_ULP_CLASS_HID_18e8b] = 577, - [BNXT_ULP_CLASS_HID_1b14b] = 578, - [BNXT_ULP_CLASS_HID_1d40b] = 579, - [BNXT_ULP_CLASS_HID_1f6cb] = 580, - [BNXT_ULP_CLASS_HID_19347] = 581, - [BNXT_ULP_CLASS_HID_1b607] = 582, - [BNXT_ULP_CLASS_HID_1d8c7] = 583, - [BNXT_ULP_CLASS_HID_1fb87] = 584, - [BNXT_ULP_CLASS_HID_a12b] = 585, - [BNXT_ULP_CLASS_HID_a3eb] = 586, - [BNXT_ULP_CLASS_HID_e6ab] = 587, - [BNXT_ULP_CLASS_HID_e96b] = 588, - [BNXT_ULP_CLASS_HID_9c1f] = 589, - [BNXT_ULP_CLASS_HID_bedf] = 590, - [BNXT_ULP_CLASS_HID_e19f] = 591, - [BNXT_ULP_CLASS_HID_e45f] = 592, - [BNXT_ULP_CLASS_HID_1b21f] = 593, - [BNXT_ULP_CLASS_HID_1b4df] = 594, - [BNXT_ULP_CLASS_HID_1f79f] = 595, - [BNXT_ULP_CLASS_HID_1fa5f] = 596, - [BNXT_ULP_CLASS_HID_1b72b] = 597, - [BNXT_ULP_CLASS_HID_1b9eb] = 598, - [BNXT_ULP_CLASS_HID_1fcab] = 599, - [BNXT_ULP_CLASS_HID_1ff6b] = 600, - [BNXT_ULP_CLASS_HID_c4bf] = 601, - [BNXT_ULP_CLASS_HID_e77f] = 602, - [BNXT_ULP_CLASS_HID_ca3f] = 603, - [BNXT_ULP_CLASS_HID_ecff] = 604, - [BNXT_ULP_CLASS_HID_bfe3] = 605, - [BNXT_ULP_CLASS_HID_e2a3] = 606, - [BNXT_ULP_CLASS_HID_c563] = 607, - [BNXT_ULP_CLASS_HID_e823] = 608, - [BNXT_ULP_CLASS_HID_1d5e3] = 609, - [BNXT_ULP_CLASS_HID_1f8a3] = 610, - [BNXT_ULP_CLASS_HID_1db63] = 611, - [BNXT_ULP_CLASS_HID_1e117] = 612, - [BNXT_ULP_CLASS_HID_1dabf] = 613, - [BNXT_ULP_CLASS_HID_1a0a3] = 614, - [BNXT_ULP_CLASS_HID_1c363] = 615, - [BNXT_ULP_CLASS_HID_1e623] = 616, - [BNXT_ULP_CLASS_HID_b043] = 617, - [BNXT_ULP_CLASS_HID_b303] = 618, - [BNXT_ULP_CLASS_HID_f5c3] = 619, - [BNXT_ULP_CLASS_HID_f883] = 620, - [BNXT_ULP_CLASS_HID_abb7] = 621, - [BNXT_ULP_CLASS_HID_ae77] = 622, - [BNXT_ULP_CLASS_HID_f137] = 623, - [BNXT_ULP_CLASS_HID_f3f7] = 624, - [BNXT_ULP_CLASS_HID_1c1b7] = 625, - [BNXT_ULP_CLASS_HID_1e477] = 626, - [BNXT_ULP_CLASS_HID_1c737] = 627, - [BNXT_ULP_CLASS_HID_1e9f7] = 628, - [BNXT_ULP_CLASS_HID_1c643] = 629, - [BNXT_ULP_CLASS_HID_1e903] = 630, - [BNXT_ULP_CLASS_HID_1cbc3] = 631, - [BNXT_ULP_CLASS_HID_1ee83] = 632, - [BNXT_ULP_CLASS_HID_d3d7] = 633, - [BNXT_ULP_CLASS_HID_f697] = 634, - [BNXT_ULP_CLASS_HID_d957] = 635, - [BNXT_ULP_CLASS_HID_fc17] = 636, - [BNXT_ULP_CLASS_HID_cf1b] = 637, - [BNXT_ULP_CLASS_HID_f1db] = 638, - [BNXT_ULP_CLASS_HID_d49b] = 639, - [BNXT_ULP_CLASS_HID_f75b] = 640, - [BNXT_ULP_CLASS_HID_1884f] = 641, - [BNXT_ULP_CLASS_HID_1ab0f] = 642, - [BNXT_ULP_CLASS_HID_1cdcf] = 643, - [BNXT_ULP_CLASS_HID_1f08f] = 644, - [BNXT_ULP_CLASS_HID_18d1b] = 645, - [BNXT_ULP_CLASS_HID_1afdb] = 646, - [BNXT_ULP_CLASS_HID_1d29b] = 647, - [BNXT_ULP_CLASS_HID_1f55b] = 648, - [BNXT_ULP_CLASS_HID_9aef] = 649, - [BNXT_ULP_CLASS_HID_bdaf] = 650, - [BNXT_ULP_CLASS_HID_e06f] = 651, - [BNXT_ULP_CLASS_HID_e32f] = 652, - [BNXT_ULP_CLASS_HID_95d3] = 653, - [BNXT_ULP_CLASS_HID_b893] = 654, - [BNXT_ULP_CLASS_HID_db53] = 655, - [BNXT_ULP_CLASS_HID_fe13] = 656, - [BNXT_ULP_CLASS_HID_1abd3] = 657, - [BNXT_ULP_CLASS_HID_1ae93] = 658, - [BNXT_ULP_CLASS_HID_1f153] = 659, - [BNXT_ULP_CLASS_HID_1f413] = 660, - [BNXT_ULP_CLASS_HID_1b0ef] = 661, - [BNXT_ULP_CLASS_HID_1b3af] = 662, - [BNXT_ULP_CLASS_HID_1f66f] = 663, - [BNXT_ULP_CLASS_HID_1f92f] = 664, - [BNXT_ULP_CLASS_HID_be73] = 665, - [BNXT_ULP_CLASS_HID_e133] = 666, - [BNXT_ULP_CLASS_HID_c3f3] = 667, - [BNXT_ULP_CLASS_HID_e6b3] = 668, - [BNXT_ULP_CLASS_HID_b9a7] = 669, - [BNXT_ULP_CLASS_HID_bc67] = 670, - [BNXT_ULP_CLASS_HID_ff27] = 671, - [BNXT_ULP_CLASS_HID_e1e7] = 672, - [BNXT_ULP_CLASS_HID_1cfa7] = 673, - [BNXT_ULP_CLASS_HID_1f267] = 674, - [BNXT_ULP_CLASS_HID_1d527] = 675, - [BNXT_ULP_CLASS_HID_1f7e7] = 676, - [BNXT_ULP_CLASS_HID_1d473] = 677, - [BNXT_ULP_CLASS_HID_1f733] = 678, - [BNXT_ULP_CLASS_HID_1d9f3] = 679, - [BNXT_ULP_CLASS_HID_1fcb3] = 680, - [BNXT_ULP_CLASS_HID_aa07] = 681, - [BNXT_ULP_CLASS_HID_acc7] = 682, - [BNXT_ULP_CLASS_HID_ef87] = 683, - [BNXT_ULP_CLASS_HID_f247] = 684, - [BNXT_ULP_CLASS_HID_a54b] = 685, - [BNXT_ULP_CLASS_HID_a80b] = 686, - [BNXT_ULP_CLASS_HID_eacb] = 687, - [BNXT_ULP_CLASS_HID_ed8b] = 688, - [BNXT_ULP_CLASS_HID_1bb4b] = 689, - [BNXT_ULP_CLASS_HID_1be0b] = 690, - [BNXT_ULP_CLASS_HID_1c0cb] = 691, - [BNXT_ULP_CLASS_HID_1e38b] = 692, - [BNXT_ULP_CLASS_HID_1c007] = 693, - [BNXT_ULP_CLASS_HID_1e2c7] = 694, - [BNXT_ULP_CLASS_HID_1c587] = 695, - [BNXT_ULP_CLASS_HID_1e847] = 696, - [BNXT_ULP_CLASS_HID_cdeb] = 697, - [BNXT_ULP_CLASS_HID_f0ab] = 698, - [BNXT_ULP_CLASS_HID_d36b] = 699, - [BNXT_ULP_CLASS_HID_f62b] = 700, - [BNXT_ULP_CLASS_HID_c8df] = 701, - [BNXT_ULP_CLASS_HID_eb9f] = 702, - [BNXT_ULP_CLASS_HID_ce5f] = 703, - [BNXT_ULP_CLASS_HID_f11f] = 704, - [BNXT_ULP_CLASS_HID_18203] = 705, - [BNXT_ULP_CLASS_HID_1a4c3] = 706, - [BNXT_ULP_CLASS_HID_1c783] = 707, - [BNXT_ULP_CLASS_HID_1ea43] = 708, - [BNXT_ULP_CLASS_HID_186df] = 709, - [BNXT_ULP_CLASS_HID_1a99f] = 710, - [BNXT_ULP_CLASS_HID_1cc5f] = 711, - [BNXT_ULP_CLASS_HID_1ef1f] = 712, - [BNXT_ULP_CLASS_HID_94a3] = 713, - [BNXT_ULP_CLASS_HID_b763] = 714, - [BNXT_ULP_CLASS_HID_da23] = 715, - [BNXT_ULP_CLASS_HID_fce3] = 716, - [BNXT_ULP_CLASS_HID_8f97] = 717, - [BNXT_ULP_CLASS_HID_b257] = 718, - [BNXT_ULP_CLASS_HID_d517] = 719, - [BNXT_ULP_CLASS_HID_f7d7] = 720, - [BNXT_ULP_CLASS_HID_1a597] = 721, - [BNXT_ULP_CLASS_HID_1a857] = 722, - [BNXT_ULP_CLASS_HID_1eb17] = 723, - [BNXT_ULP_CLASS_HID_1edd7] = 724, - [BNXT_ULP_CLASS_HID_1aaa3] = 725, - [BNXT_ULP_CLASS_HID_1ad63] = 726, - [BNXT_ULP_CLASS_HID_1f023] = 727, - [BNXT_ULP_CLASS_HID_1f2e3] = 728, - [BNXT_ULP_CLASS_HID_b837] = 729, - [BNXT_ULP_CLASS_HID_baf7] = 730, - [BNXT_ULP_CLASS_HID_fdb7] = 731, - [BNXT_ULP_CLASS_HID_e077] = 732, - [BNXT_ULP_CLASS_HID_b37b] = 733, - [BNXT_ULP_CLASS_HID_b63b] = 734, - [BNXT_ULP_CLASS_HID_f8fb] = 735, - [BNXT_ULP_CLASS_HID_fbbb] = 736, - [BNXT_ULP_CLASS_HID_1c97b] = 737, - [BNXT_ULP_CLASS_HID_1ec3b] = 738, - [BNXT_ULP_CLASS_HID_1cefb] = 739, - [BNXT_ULP_CLASS_HID_1f1bb] = 740, - [BNXT_ULP_CLASS_HID_1ce37] = 741, - [BNXT_ULP_CLASS_HID_1f0f7] = 742, - [BNXT_ULP_CLASS_HID_1d3b7] = 743, - [BNXT_ULP_CLASS_HID_1f677] = 744, - [BNXT_ULP_CLASS_HID_a3db] = 745, - [BNXT_ULP_CLASS_HID_a69b] = 746, - [BNXT_ULP_CLASS_HID_e95b] = 747, - [BNXT_ULP_CLASS_HID_ec1b] = 748, - [BNXT_ULP_CLASS_HID_9f0f] = 749, - [BNXT_ULP_CLASS_HID_a1cf] = 750, - [BNXT_ULP_CLASS_HID_e48f] = 751, - [BNXT_ULP_CLASS_HID_e74f] = 752, - [BNXT_ULP_CLASS_HID_1b50f] = 753, - [BNXT_ULP_CLASS_HID_1b7cf] = 754, - [BNXT_ULP_CLASS_HID_1fa8f] = 755, - [BNXT_ULP_CLASS_HID_1fd4f] = 756, - [BNXT_ULP_CLASS_HID_1b9db] = 757, - [BNXT_ULP_CLASS_HID_1bc9b] = 758, - [BNXT_ULP_CLASS_HID_1ff5b] = 759, - [BNXT_ULP_CLASS_HID_1e21b] = 760, - [BNXT_ULP_CLASS_HID_c7af] = 761, - [BNXT_ULP_CLASS_HID_ea6f] = 762, - [BNXT_ULP_CLASS_HID_cd2f] = 763, - [BNXT_ULP_CLASS_HID_efef] = 764, - [BNXT_ULP_CLASS_HID_c293] = 765, - [BNXT_ULP_CLASS_HID_e553] = 766, - [BNXT_ULP_CLASS_HID_c813] = 767, - [BNXT_ULP_CLASS_HID_ead3] = 768, - [BNXT_ULP_CLASS_HID_1d893] = 769, - [BNXT_ULP_CLASS_HID_1fb53] = 770, - [BNXT_ULP_CLASS_HID_1c147] = 771, - [BNXT_ULP_CLASS_HID_1e407] = 772, - [BNXT_ULP_CLASS_HID_18093] = 773, - [BNXT_ULP_CLASS_HID_1a353] = 774, - [BNXT_ULP_CLASS_HID_1c613] = 775, - [BNXT_ULP_CLASS_HID_1e8d3] = 776, - [BNXT_ULP_CLASS_HID_8e67] = 777, - [BNXT_ULP_CLASS_HID_b127] = 778, - [BNXT_ULP_CLASS_HID_d3e7] = 779, - [BNXT_ULP_CLASS_HID_f6a7] = 780, - [BNXT_ULP_CLASS_HID_89ab] = 781, - [BNXT_ULP_CLASS_HID_ac6b] = 782, - [BNXT_ULP_CLASS_HID_cf2b] = 783, - [BNXT_ULP_CLASS_HID_f1eb] = 784, - [BNXT_ULP_CLASS_HID_19fab] = 785, - [BNXT_ULP_CLASS_HID_1a26b] = 786, - [BNXT_ULP_CLASS_HID_1e52b] = 787, - [BNXT_ULP_CLASS_HID_1e7eb] = 788, - [BNXT_ULP_CLASS_HID_1a467] = 789, - [BNXT_ULP_CLASS_HID_1a727] = 790, - [BNXT_ULP_CLASS_HID_1e9e7] = 791, - [BNXT_ULP_CLASS_HID_1eca7] = 792, - [BNXT_ULP_CLASS_HID_b1cb] = 793, - [BNXT_ULP_CLASS_HID_b48b] = 794, - [BNXT_ULP_CLASS_HID_f74b] = 795, - [BNXT_ULP_CLASS_HID_fa0b] = 796, - [BNXT_ULP_CLASS_HID_ad3f] = 797, - [BNXT_ULP_CLASS_HID_afff] = 798, - [BNXT_ULP_CLASS_HID_f2bf] = 799, - [BNXT_ULP_CLASS_HID_f57f] = 800, - [BNXT_ULP_CLASS_HID_1c33f] = 801, - [BNXT_ULP_CLASS_HID_1e5ff] = 802, - [BNXT_ULP_CLASS_HID_1c8bf] = 803, - [BNXT_ULP_CLASS_HID_1eb7f] = 804, - [BNXT_ULP_CLASS_HID_1c7cb] = 805, - [BNXT_ULP_CLASS_HID_1ea8b] = 806, - [BNXT_ULP_CLASS_HID_1cd4b] = 807, - [BNXT_ULP_CLASS_HID_1f00b] = 808, - [BNXT_ULP_CLASS_HID_9117] = 809, - [BNXT_ULP_CLASS_HID_b3d7] = 810, - [BNXT_ULP_CLASS_HID_d697] = 811, - [BNXT_ULP_CLASS_HID_f957] = 812, - [BNXT_ULP_CLASS_HID_8c5b] = 813, - [BNXT_ULP_CLASS_HID_af1b] = 814, - [BNXT_ULP_CLASS_HID_d1db] = 815, - [BNXT_ULP_CLASS_HID_f49b] = 816, - [BNXT_ULP_CLASS_HID_1a25b] = 817, - [BNXT_ULP_CLASS_HID_1a51b] = 818, - [BNXT_ULP_CLASS_HID_1e7db] = 819, - [BNXT_ULP_CLASS_HID_1ea9b] = 820, - [BNXT_ULP_CLASS_HID_1a717] = 821, - [BNXT_ULP_CLASS_HID_1a9d7] = 822, - [BNXT_ULP_CLASS_HID_1ec97] = 823, - [BNXT_ULP_CLASS_HID_1ef57] = 824, - [BNXT_ULP_CLASS_HID_b4fb] = 825, - [BNXT_ULP_CLASS_HID_b7bb] = 826, - [BNXT_ULP_CLASS_HID_fa7b] = 827, - [BNXT_ULP_CLASS_HID_fd3b] = 828, - [BNXT_ULP_CLASS_HID_b02f] = 829, - [BNXT_ULP_CLASS_HID_b2ef] = 830, - [BNXT_ULP_CLASS_HID_f5af] = 831, - [BNXT_ULP_CLASS_HID_f86f] = 832, - [BNXT_ULP_CLASS_HID_1c62f] = 833, - [BNXT_ULP_CLASS_HID_1e8ef] = 834, - [BNXT_ULP_CLASS_HID_1cbaf] = 835, - [BNXT_ULP_CLASS_HID_1ee6f] = 836, - [BNXT_ULP_CLASS_HID_1cafb] = 837, - [BNXT_ULP_CLASS_HID_1edbb] = 838, - [BNXT_ULP_CLASS_HID_1d07b] = 839, - [BNXT_ULP_CLASS_HID_1f33b] = 840, - [BNXT_ULP_CLASS_HID_8b2b] = 841, - [BNXT_ULP_CLASS_HID_adeb] = 842, - [BNXT_ULP_CLASS_HID_d0ab] = 843, - [BNXT_ULP_CLASS_HID_f36b] = 844, - [BNXT_ULP_CLASS_HID_861f] = 845, - [BNXT_ULP_CLASS_HID_a8df] = 846, - [BNXT_ULP_CLASS_HID_cb9f] = 847, - [BNXT_ULP_CLASS_HID_ee5f] = 848, - [BNXT_ULP_CLASS_HID_19c1f] = 849, - [BNXT_ULP_CLASS_HID_1bedf] = 850, - [BNXT_ULP_CLASS_HID_1e19f] = 851, - [BNXT_ULP_CLASS_HID_1e45f] = 852, - [BNXT_ULP_CLASS_HID_1a12b] = 853, - [BNXT_ULP_CLASS_HID_1a3eb] = 854, - [BNXT_ULP_CLASS_HID_1e6ab] = 855, - [BNXT_ULP_CLASS_HID_1e96b] = 856, - [BNXT_ULP_CLASS_HID_aebf] = 857, - [BNXT_ULP_CLASS_HID_b17f] = 858, - [BNXT_ULP_CLASS_HID_f43f] = 859, - [BNXT_ULP_CLASS_HID_f6ff] = 860, - [BNXT_ULP_CLASS_HID_a9e3] = 861, - [BNXT_ULP_CLASS_HID_aca3] = 862, - [BNXT_ULP_CLASS_HID_ef63] = 863, - [BNXT_ULP_CLASS_HID_f223] = 864, - [BNXT_ULP_CLASS_HID_1bfe3] = 865, - [BNXT_ULP_CLASS_HID_1e2a3] = 866, - [BNXT_ULP_CLASS_HID_1c563] = 867, - [BNXT_ULP_CLASS_HID_1e823] = 868, - [BNXT_ULP_CLASS_HID_1c4bf] = 869, - [BNXT_ULP_CLASS_HID_1e77f] = 870, - [BNXT_ULP_CLASS_HID_1ca3f] = 871, - [BNXT_ULP_CLASS_HID_1ecff] = 872, - [BNXT_ULP_CLASS_HID_2543] = 873, - [BNXT_ULP_CLASS_HID_2b8f] = 874, - [BNXT_ULP_CLASS_HID_26f3] = 875, - [BNXT_ULP_CLASS_HID_4f13] = 876, - [BNXT_ULP_CLASS_HID_4a47] = 877, - [BNXT_ULP_CLASS_HID_162b] = 878, - [BNXT_ULP_CLASS_HID_111f] = 879, - [BNXT_ULP_CLASS_HID_39bf] = 880, - [BNXT_ULP_CLASS_HID_34e3] = 881, - [BNXT_ULP_CLASS_HID_20b7] = 882, - [BNXT_ULP_CLASS_HID_48d7] = 883, - [BNXT_ULP_CLASS_HID_441b] = 884, - [BNXT_ULP_CLASS_HID_0fef] = 885, - [BNXT_ULP_CLASS_HID_0ad3] = 886, - [BNXT_ULP_CLASS_HID_3373] = 887, - [BNXT_ULP_CLASS_HID_2ea7] = 888, - [BNXT_ULP_CLASS_HID_b6ef] = 889, - [BNXT_ULP_CLASS_HID_b92f] = 890, - [BNXT_ULP_CLASS_HID_fc6f] = 891, - [BNXT_ULP_CLASS_HID_feaf] = 892, - [BNXT_ULP_CLASS_HID_b193] = 893, - [BNXT_ULP_CLASS_HID_b4d3] = 894, - [BNXT_ULP_CLASS_HID_f713] = 895, - [BNXT_ULP_CLASS_HID_fa53] = 896, - [BNXT_ULP_CLASS_HID_1c793] = 897, - [BNXT_ULP_CLASS_HID_1ead3] = 898, - [BNXT_ULP_CLASS_HID_1cd13] = 899, - [BNXT_ULP_CLASS_HID_1f053] = 900, - [BNXT_ULP_CLASS_HID_1ccef] = 901, - [BNXT_ULP_CLASS_HID_1ef2f] = 902, - [BNXT_ULP_CLASS_HID_1d26f] = 903, - [BNXT_ULP_CLASS_HID_1f4af] = 904, - [BNXT_ULP_CLASS_HID_da73] = 905, - [BNXT_ULP_CLASS_HID_a067] = 906, - [BNXT_ULP_CLASS_HID_c2a7] = 907, - [BNXT_ULP_CLASS_HID_e5e7] = 908, - [BNXT_ULP_CLASS_HID_d527] = 909, - [BNXT_ULP_CLASS_HID_f867] = 910, - [BNXT_ULP_CLASS_HID_daa7] = 911, - [BNXT_ULP_CLASS_HID_e0ab] = 912, - [BNXT_ULP_CLASS_HID_18eeb] = 913, - [BNXT_ULP_CLASS_HID_1b12b] = 914, - [BNXT_ULP_CLASS_HID_1d46b] = 915, - [BNXT_ULP_CLASS_HID_1f6ab] = 916, - [BNXT_ULP_CLASS_HID_19327] = 917, - [BNXT_ULP_CLASS_HID_1b667] = 918, - [BNXT_ULP_CLASS_HID_1d8a7] = 919, - [BNXT_ULP_CLASS_HID_1fbe7] = 920, - [BNXT_ULP_CLASS_HID_a14b] = 921, - [BNXT_ULP_CLASS_HID_a38b] = 922, - [BNXT_ULP_CLASS_HID_e6cb] = 923, - [BNXT_ULP_CLASS_HID_e90b] = 924, - [BNXT_ULP_CLASS_HID_9c7f] = 925, - [BNXT_ULP_CLASS_HID_bebf] = 926, - [BNXT_ULP_CLASS_HID_e1ff] = 927, - [BNXT_ULP_CLASS_HID_e43f] = 928, - [BNXT_ULP_CLASS_HID_1b27f] = 929, - [BNXT_ULP_CLASS_HID_1b4bf] = 930, - [BNXT_ULP_CLASS_HID_1f7ff] = 931, - [BNXT_ULP_CLASS_HID_1fa3f] = 932, - [BNXT_ULP_CLASS_HID_1b74b] = 933, - [BNXT_ULP_CLASS_HID_1b98b] = 934, - [BNXT_ULP_CLASS_HID_1fccb] = 935, - [BNXT_ULP_CLASS_HID_1ff0b] = 936, - [BNXT_ULP_CLASS_HID_c4df] = 937, - [BNXT_ULP_CLASS_HID_e71f] = 938, - [BNXT_ULP_CLASS_HID_ca5f] = 939, - [BNXT_ULP_CLASS_HID_ec9f] = 940, - [BNXT_ULP_CLASS_HID_bf83] = 941, - [BNXT_ULP_CLASS_HID_e2c3] = 942, - [BNXT_ULP_CLASS_HID_c503] = 943, - [BNXT_ULP_CLASS_HID_e843] = 944, - [BNXT_ULP_CLASS_HID_1d583] = 945, - [BNXT_ULP_CLASS_HID_1f8c3] = 946, - [BNXT_ULP_CLASS_HID_1db03] = 947, - [BNXT_ULP_CLASS_HID_1e177] = 948, - [BNXT_ULP_CLASS_HID_1dadf] = 949, - [BNXT_ULP_CLASS_HID_1a0c3] = 950, - [BNXT_ULP_CLASS_HID_1c303] = 951, - [BNXT_ULP_CLASS_HID_1e643] = 952, - [BNXT_ULP_CLASS_HID_b023] = 953, - [BNXT_ULP_CLASS_HID_b363] = 954, - [BNXT_ULP_CLASS_HID_f5a3] = 955, - [BNXT_ULP_CLASS_HID_f8e3] = 956, - [BNXT_ULP_CLASS_HID_abd7] = 957, - [BNXT_ULP_CLASS_HID_ae17] = 958, - [BNXT_ULP_CLASS_HID_f157] = 959, - [BNXT_ULP_CLASS_HID_f397] = 960, - [BNXT_ULP_CLASS_HID_1c1d7] = 961, - [BNXT_ULP_CLASS_HID_1e417] = 962, - [BNXT_ULP_CLASS_HID_1c757] = 963, - [BNXT_ULP_CLASS_HID_1e997] = 964, - [BNXT_ULP_CLASS_HID_1c623] = 965, - [BNXT_ULP_CLASS_HID_1e963] = 966, - [BNXT_ULP_CLASS_HID_1cba3] = 967, - [BNXT_ULP_CLASS_HID_1eee3] = 968, - [BNXT_ULP_CLASS_HID_d3b7] = 969, - [BNXT_ULP_CLASS_HID_f6f7] = 970, - [BNXT_ULP_CLASS_HID_d937] = 971, - [BNXT_ULP_CLASS_HID_fc77] = 972, - [BNXT_ULP_CLASS_HID_cf7b] = 973, - [BNXT_ULP_CLASS_HID_f1bb] = 974, - [BNXT_ULP_CLASS_HID_d4fb] = 975, - [BNXT_ULP_CLASS_HID_f73b] = 976, - [BNXT_ULP_CLASS_HID_1882f] = 977, - [BNXT_ULP_CLASS_HID_1ab6f] = 978, - [BNXT_ULP_CLASS_HID_1cdaf] = 979, - [BNXT_ULP_CLASS_HID_1f0ef] = 980, - [BNXT_ULP_CLASS_HID_18d7b] = 981, - [BNXT_ULP_CLASS_HID_1afbb] = 982, - [BNXT_ULP_CLASS_HID_1d2fb] = 983, - [BNXT_ULP_CLASS_HID_1f53b] = 984, - [BNXT_ULP_CLASS_HID_9a8f] = 985, - [BNXT_ULP_CLASS_HID_bdcf] = 986, - [BNXT_ULP_CLASS_HID_e00f] = 987, - [BNXT_ULP_CLASS_HID_e34f] = 988, - [BNXT_ULP_CLASS_HID_95b3] = 989, - [BNXT_ULP_CLASS_HID_b8f3] = 990, - [BNXT_ULP_CLASS_HID_db33] = 991, - [BNXT_ULP_CLASS_HID_fe73] = 992, - [BNXT_ULP_CLASS_HID_1abb3] = 993, - [BNXT_ULP_CLASS_HID_1aef3] = 994, - [BNXT_ULP_CLASS_HID_1f133] = 995, - [BNXT_ULP_CLASS_HID_1f473] = 996, - [BNXT_ULP_CLASS_HID_1b08f] = 997, - [BNXT_ULP_CLASS_HID_1b3cf] = 998, - [BNXT_ULP_CLASS_HID_1f60f] = 999, - [BNXT_ULP_CLASS_HID_1f94f] = 1000, - [BNXT_ULP_CLASS_HID_be13] = 1001, - [BNXT_ULP_CLASS_HID_e153] = 1002, - [BNXT_ULP_CLASS_HID_c393] = 1003, - [BNXT_ULP_CLASS_HID_e6d3] = 1004, - [BNXT_ULP_CLASS_HID_b9c7] = 1005, - [BNXT_ULP_CLASS_HID_bc07] = 1006, - [BNXT_ULP_CLASS_HID_ff47] = 1007, - [BNXT_ULP_CLASS_HID_e187] = 1008, - [BNXT_ULP_CLASS_HID_1cfc7] = 1009, - [BNXT_ULP_CLASS_HID_1f207] = 1010, - [BNXT_ULP_CLASS_HID_1d547] = 1011, - [BNXT_ULP_CLASS_HID_1f787] = 1012, - [BNXT_ULP_CLASS_HID_1d413] = 1013, - [BNXT_ULP_CLASS_HID_1f753] = 1014, - [BNXT_ULP_CLASS_HID_1d993] = 1015, - [BNXT_ULP_CLASS_HID_1fcd3] = 1016, - [BNXT_ULP_CLASS_HID_aa67] = 1017, - [BNXT_ULP_CLASS_HID_aca7] = 1018, - [BNXT_ULP_CLASS_HID_efe7] = 1019, - [BNXT_ULP_CLASS_HID_f227] = 1020, - [BNXT_ULP_CLASS_HID_a52b] = 1021, - [BNXT_ULP_CLASS_HID_a86b] = 1022, - [BNXT_ULP_CLASS_HID_eaab] = 1023, - [BNXT_ULP_CLASS_HID_edeb] = 1024, - [BNXT_ULP_CLASS_HID_1bb2b] = 1025, - [BNXT_ULP_CLASS_HID_1be6b] = 1026, - [BNXT_ULP_CLASS_HID_1c0ab] = 1027, - [BNXT_ULP_CLASS_HID_1e3eb] = 1028, - [BNXT_ULP_CLASS_HID_1c067] = 1029, - [BNXT_ULP_CLASS_HID_1e2a7] = 1030, - [BNXT_ULP_CLASS_HID_1c5e7] = 1031, - [BNXT_ULP_CLASS_HID_1e827] = 1032, - [BNXT_ULP_CLASS_HID_cd8b] = 1033, - [BNXT_ULP_CLASS_HID_f0cb] = 1034, - [BNXT_ULP_CLASS_HID_d30b] = 1035, - [BNXT_ULP_CLASS_HID_f64b] = 1036, - [BNXT_ULP_CLASS_HID_c8bf] = 1037, - [BNXT_ULP_CLASS_HID_ebff] = 1038, - [BNXT_ULP_CLASS_HID_ce3f] = 1039, - [BNXT_ULP_CLASS_HID_f17f] = 1040, - [BNXT_ULP_CLASS_HID_18263] = 1041, - [BNXT_ULP_CLASS_HID_1a4a3] = 1042, - [BNXT_ULP_CLASS_HID_1c7e3] = 1043, - [BNXT_ULP_CLASS_HID_1ea23] = 1044, - [BNXT_ULP_CLASS_HID_186bf] = 1045, - [BNXT_ULP_CLASS_HID_1a9ff] = 1046, - [BNXT_ULP_CLASS_HID_1cc3f] = 1047, - [BNXT_ULP_CLASS_HID_1ef7f] = 1048, - [BNXT_ULP_CLASS_HID_94c3] = 1049, - [BNXT_ULP_CLASS_HID_b703] = 1050, - [BNXT_ULP_CLASS_HID_da43] = 1051, - [BNXT_ULP_CLASS_HID_fc83] = 1052, - [BNXT_ULP_CLASS_HID_8ff7] = 1053, - [BNXT_ULP_CLASS_HID_b237] = 1054, - [BNXT_ULP_CLASS_HID_d577] = 1055, - [BNXT_ULP_CLASS_HID_f7b7] = 1056, - [BNXT_ULP_CLASS_HID_1a5f7] = 1057, - [BNXT_ULP_CLASS_HID_1a837] = 1058, - [BNXT_ULP_CLASS_HID_1eb77] = 1059, - [BNXT_ULP_CLASS_HID_1edb7] = 1060, - [BNXT_ULP_CLASS_HID_1aac3] = 1061, - [BNXT_ULP_CLASS_HID_1ad03] = 1062, - [BNXT_ULP_CLASS_HID_1f043] = 1063, - [BNXT_ULP_CLASS_HID_1f283] = 1064, - [BNXT_ULP_CLASS_HID_b857] = 1065, - [BNXT_ULP_CLASS_HID_ba97] = 1066, - [BNXT_ULP_CLASS_HID_fdd7] = 1067, - [BNXT_ULP_CLASS_HID_e017] = 1068, - [BNXT_ULP_CLASS_HID_b31b] = 1069, - [BNXT_ULP_CLASS_HID_b65b] = 1070, - [BNXT_ULP_CLASS_HID_f89b] = 1071, - [BNXT_ULP_CLASS_HID_fbdb] = 1072, - [BNXT_ULP_CLASS_HID_1c91b] = 1073, - [BNXT_ULP_CLASS_HID_1ec5b] = 1074, - [BNXT_ULP_CLASS_HID_1ce9b] = 1075, - [BNXT_ULP_CLASS_HID_1f1db] = 1076, - [BNXT_ULP_CLASS_HID_1ce57] = 1077, - [BNXT_ULP_CLASS_HID_1f097] = 1078, - [BNXT_ULP_CLASS_HID_1d3d7] = 1079, - [BNXT_ULP_CLASS_HID_1f617] = 1080, - [BNXT_ULP_CLASS_HID_a3bb] = 1081, - [BNXT_ULP_CLASS_HID_a6fb] = 1082, - [BNXT_ULP_CLASS_HID_e93b] = 1083, - [BNXT_ULP_CLASS_HID_ec7b] = 1084, - [BNXT_ULP_CLASS_HID_9f6f] = 1085, - [BNXT_ULP_CLASS_HID_a1af] = 1086, - [BNXT_ULP_CLASS_HID_e4ef] = 1087, - [BNXT_ULP_CLASS_HID_e72f] = 1088, - [BNXT_ULP_CLASS_HID_1b56f] = 1089, - [BNXT_ULP_CLASS_HID_1b7af] = 1090, - [BNXT_ULP_CLASS_HID_1faef] = 1091, - [BNXT_ULP_CLASS_HID_1fd2f] = 1092, - [BNXT_ULP_CLASS_HID_1b9bb] = 1093, - [BNXT_ULP_CLASS_HID_1bcfb] = 1094, - [BNXT_ULP_CLASS_HID_1ff3b] = 1095, - [BNXT_ULP_CLASS_HID_1e27b] = 1096, - [BNXT_ULP_CLASS_HID_c7cf] = 1097, - [BNXT_ULP_CLASS_HID_ea0f] = 1098, - [BNXT_ULP_CLASS_HID_cd4f] = 1099, - [BNXT_ULP_CLASS_HID_ef8f] = 1100, - [BNXT_ULP_CLASS_HID_c2f3] = 1101, - [BNXT_ULP_CLASS_HID_e533] = 1102, - [BNXT_ULP_CLASS_HID_c873] = 1103, - [BNXT_ULP_CLASS_HID_eab3] = 1104, - [BNXT_ULP_CLASS_HID_1d8f3] = 1105, - [BNXT_ULP_CLASS_HID_1fb33] = 1106, - [BNXT_ULP_CLASS_HID_1c127] = 1107, - [BNXT_ULP_CLASS_HID_1e467] = 1108, - [BNXT_ULP_CLASS_HID_180f3] = 1109, - [BNXT_ULP_CLASS_HID_1a333] = 1110, - [BNXT_ULP_CLASS_HID_1c673] = 1111, - [BNXT_ULP_CLASS_HID_1e8b3] = 1112, - [BNXT_ULP_CLASS_HID_8e07] = 1113, - [BNXT_ULP_CLASS_HID_b147] = 1114, - [BNXT_ULP_CLASS_HID_d387] = 1115, - [BNXT_ULP_CLASS_HID_f6c7] = 1116, - [BNXT_ULP_CLASS_HID_89cb] = 1117, - [BNXT_ULP_CLASS_HID_ac0b] = 1118, - [BNXT_ULP_CLASS_HID_cf4b] = 1119, - [BNXT_ULP_CLASS_HID_f18b] = 1120, - [BNXT_ULP_CLASS_HID_19fcb] = 1121, - [BNXT_ULP_CLASS_HID_1a20b] = 1122, - [BNXT_ULP_CLASS_HID_1e54b] = 1123, - [BNXT_ULP_CLASS_HID_1e78b] = 1124, - [BNXT_ULP_CLASS_HID_1a407] = 1125, - [BNXT_ULP_CLASS_HID_1a747] = 1126, - [BNXT_ULP_CLASS_HID_1e987] = 1127, - [BNXT_ULP_CLASS_HID_1ecc7] = 1128, - [BNXT_ULP_CLASS_HID_b1ab] = 1129, - [BNXT_ULP_CLASS_HID_b4eb] = 1130, - [BNXT_ULP_CLASS_HID_f72b] = 1131, - [BNXT_ULP_CLASS_HID_fa6b] = 1132, - [BNXT_ULP_CLASS_HID_ad5f] = 1133, - [BNXT_ULP_CLASS_HID_af9f] = 1134, - [BNXT_ULP_CLASS_HID_f2df] = 1135, - [BNXT_ULP_CLASS_HID_f51f] = 1136, - [BNXT_ULP_CLASS_HID_1c35f] = 1137, - [BNXT_ULP_CLASS_HID_1e59f] = 1138, - [BNXT_ULP_CLASS_HID_1c8df] = 1139, - [BNXT_ULP_CLASS_HID_1eb1f] = 1140, - [BNXT_ULP_CLASS_HID_1c7ab] = 1141, - [BNXT_ULP_CLASS_HID_1eaeb] = 1142, - [BNXT_ULP_CLASS_HID_1cd2b] = 1143, - [BNXT_ULP_CLASS_HID_1f06b] = 1144, - [BNXT_ULP_CLASS_HID_9177] = 1145, - [BNXT_ULP_CLASS_HID_b3b7] = 1146, - [BNXT_ULP_CLASS_HID_d6f7] = 1147, - [BNXT_ULP_CLASS_HID_f937] = 1148, - [BNXT_ULP_CLASS_HID_8c3b] = 1149, - [BNXT_ULP_CLASS_HID_af7b] = 1150, - [BNXT_ULP_CLASS_HID_d1bb] = 1151, - [BNXT_ULP_CLASS_HID_f4fb] = 1152, - [BNXT_ULP_CLASS_HID_1a23b] = 1153, - [BNXT_ULP_CLASS_HID_1a57b] = 1154, - [BNXT_ULP_CLASS_HID_1e7bb] = 1155, - [BNXT_ULP_CLASS_HID_1eafb] = 1156, - [BNXT_ULP_CLASS_HID_1a777] = 1157, - [BNXT_ULP_CLASS_HID_1a9b7] = 1158, - [BNXT_ULP_CLASS_HID_1ecf7] = 1159, - [BNXT_ULP_CLASS_HID_1ef37] = 1160, - [BNXT_ULP_CLASS_HID_b49b] = 1161, - [BNXT_ULP_CLASS_HID_b7db] = 1162, - [BNXT_ULP_CLASS_HID_fa1b] = 1163, - [BNXT_ULP_CLASS_HID_fd5b] = 1164, - [BNXT_ULP_CLASS_HID_b04f] = 1165, - [BNXT_ULP_CLASS_HID_b28f] = 1166, - [BNXT_ULP_CLASS_HID_f5cf] = 1167, - [BNXT_ULP_CLASS_HID_f80f] = 1168, - [BNXT_ULP_CLASS_HID_1c64f] = 1169, - [BNXT_ULP_CLASS_HID_1e88f] = 1170, - [BNXT_ULP_CLASS_HID_1cbcf] = 1171, - [BNXT_ULP_CLASS_HID_1ee0f] = 1172, - [BNXT_ULP_CLASS_HID_1ca9b] = 1173, - [BNXT_ULP_CLASS_HID_1eddb] = 1174, - [BNXT_ULP_CLASS_HID_1d01b] = 1175, - [BNXT_ULP_CLASS_HID_1f35b] = 1176, - [BNXT_ULP_CLASS_HID_8b4b] = 1177, - [BNXT_ULP_CLASS_HID_ad8b] = 1178, - [BNXT_ULP_CLASS_HID_d0cb] = 1179, - [BNXT_ULP_CLASS_HID_f30b] = 1180, - [BNXT_ULP_CLASS_HID_867f] = 1181, - [BNXT_ULP_CLASS_HID_a8bf] = 1182, - [BNXT_ULP_CLASS_HID_cbff] = 1183, - [BNXT_ULP_CLASS_HID_ee3f] = 1184, - [BNXT_ULP_CLASS_HID_19c7f] = 1185, - [BNXT_ULP_CLASS_HID_1bebf] = 1186, - [BNXT_ULP_CLASS_HID_1e1ff] = 1187, - [BNXT_ULP_CLASS_HID_1e43f] = 1188, - [BNXT_ULP_CLASS_HID_1a14b] = 1189, - [BNXT_ULP_CLASS_HID_1a38b] = 1190, - [BNXT_ULP_CLASS_HID_1e6cb] = 1191, - [BNXT_ULP_CLASS_HID_1e90b] = 1192, - [BNXT_ULP_CLASS_HID_aedf] = 1193, - [BNXT_ULP_CLASS_HID_b11f] = 1194, - [BNXT_ULP_CLASS_HID_f45f] = 1195, - [BNXT_ULP_CLASS_HID_f69f] = 1196, - [BNXT_ULP_CLASS_HID_a983] = 1197, - [BNXT_ULP_CLASS_HID_acc3] = 1198, - [BNXT_ULP_CLASS_HID_ef03] = 1199, - [BNXT_ULP_CLASS_HID_f243] = 1200, - [BNXT_ULP_CLASS_HID_1bf83] = 1201, - [BNXT_ULP_CLASS_HID_1e2c3] = 1202, - [BNXT_ULP_CLASS_HID_1c503] = 1203, - [BNXT_ULP_CLASS_HID_1e843] = 1204, - [BNXT_ULP_CLASS_HID_1c4df] = 1205, - [BNXT_ULP_CLASS_HID_1e71f] = 1206, - [BNXT_ULP_CLASS_HID_1ca5f] = 1207, - [BNXT_ULP_CLASS_HID_1ec9f] = 1208, - [BNXT_ULP_CLASS_HID_2523] = 1209, - [BNXT_ULP_CLASS_HID_2bef] = 1210, - [BNXT_ULP_CLASS_HID_2693] = 1211, - [BNXT_ULP_CLASS_HID_4f73] = 1212, - [BNXT_ULP_CLASS_HID_4a27] = 1213, - [BNXT_ULP_CLASS_HID_164b] = 1214, - [BNXT_ULP_CLASS_HID_117f] = 1215, - [BNXT_ULP_CLASS_HID_39df] = 1216, - [BNXT_ULP_CLASS_HID_3483] = 1217, - [BNXT_ULP_CLASS_HID_20d7] = 1218, - [BNXT_ULP_CLASS_HID_48b7] = 1219, - [BNXT_ULP_CLASS_HID_447b] = 1220, - [BNXT_ULP_CLASS_HID_0f8f] = 1221, - [BNXT_ULP_CLASS_HID_0ab3] = 1222, - [BNXT_ULP_CLASS_HID_3313] = 1223, - [BNXT_ULP_CLASS_HID_2ec7] = 1224, - [BNXT_ULP_CLASS_HID_257b7] = 1225, - [BNXT_ULP_CLASS_HID_24467] = 1226, - [BNXT_ULP_CLASS_HID_23fbb] = 1227, - [BNXT_ULP_CLASS_HID_252cb] = 1228, - [BNXT_ULP_CLASS_HID_21e7f] = 1229, - [BNXT_ULP_CLASS_HID_20b2f] = 1230, - [BNXT_ULP_CLASS_HID_20663] = 1231, - [BNXT_ULP_CLASS_HID_219b3] = 1232, - [BNXT_ULP_CLASS_HID_24213] = 1233, - [BNXT_ULP_CLASS_HID_22ec3] = 1234, - [BNXT_ULP_CLASS_HID_22a17] = 1235, - [BNXT_ULP_CLASS_HID_23d27] = 1236, - [BNXT_ULP_CLASS_HID_208db] = 1237, - [BNXT_ULP_CLASS_HID_25277] = 1238, - [BNXT_ULP_CLASS_HID_24d8b] = 1239, - [BNXT_ULP_CLASS_HID_203ef] = 1240, - [BNXT_ULP_CLASS_HID_2517b] = 1241, - [BNXT_ULP_CLASS_HID_23e2b] = 1242, - [BNXT_ULP_CLASS_HID_2397f] = 1243, - [BNXT_ULP_CLASS_HID_24c8f] = 1244, - [BNXT_ULP_CLASS_HID_21823] = 1245, - [BNXT_ULP_CLASS_HID_20513] = 1246, - [BNXT_ULP_CLASS_HID_20027] = 1247, - [BNXT_ULP_CLASS_HID_21377] = 1248, - [BNXT_ULP_CLASS_HID_23bd7] = 1249, - [BNXT_ULP_CLASS_HID_22887] = 1250, - [BNXT_ULP_CLASS_HID_223db] = 1251, - [BNXT_ULP_CLASS_HID_236eb] = 1252, - [BNXT_ULP_CLASS_HID_2029f] = 1253, - [BNXT_ULP_CLASS_HID_24c3b] = 1254, - [BNXT_ULP_CLASS_HID_2474f] = 1255, - [BNXT_ULP_CLASS_HID_25a9f] = 1256, - [BNXT_ULP_CLASS_HID_24b3f] = 1257, - [BNXT_ULP_CLASS_HID_237ef] = 1258, - [BNXT_ULP_CLASS_HID_23323] = 1259, - [BNXT_ULP_CLASS_HID_24673] = 1260, - [BNXT_ULP_CLASS_HID_211e7] = 1261, - [BNXT_ULP_CLASS_HID_25b83] = 1262, - [BNXT_ULP_CLASS_HID_256d7] = 1263, - [BNXT_ULP_CLASS_HID_20d3b] = 1264, - [BNXT_ULP_CLASS_HID_2359b] = 1265, - [BNXT_ULP_CLASS_HID_2224b] = 1266, - [BNXT_ULP_CLASS_HID_21d9f] = 1267, - [BNXT_ULP_CLASS_HID_230af] = 1268, - [BNXT_ULP_CLASS_HID_2590f] = 1269, - [BNXT_ULP_CLASS_HID_245ff] = 1270, - [BNXT_ULP_CLASS_HID_24133] = 1271, - [BNXT_ULP_CLASS_HID_25443] = 1272, - [BNXT_ULP_CLASS_HID_244e3] = 1273, - [BNXT_ULP_CLASS_HID_231d3] = 1274, - [BNXT_ULP_CLASS_HID_22ce7] = 1275, - [BNXT_ULP_CLASS_HID_24037] = 1276, - [BNXT_ULP_CLASS_HID_20bab] = 1277, - [BNXT_ULP_CLASS_HID_25547] = 1278, - [BNXT_ULP_CLASS_HID_2509b] = 1279, - [BNXT_ULP_CLASS_HID_206ff] = 1280, - [BNXT_ULP_CLASS_HID_22f5f] = 1281, - [BNXT_ULP_CLASS_HID_21c0f] = 1282, - [BNXT_ULP_CLASS_HID_21743] = 1283, - [BNXT_ULP_CLASS_HID_22a93] = 1284, - [BNXT_ULP_CLASS_HID_252f3] = 1285, - [BNXT_ULP_CLASS_HID_23fa3] = 1286, - [BNXT_ULP_CLASS_HID_23af7] = 1287, - [BNXT_ULP_CLASS_HID_24e07] = 1288, - [BNXT_ULP_CLASS_HID_2322f] = 1289, - [BNXT_ULP_CLASS_HID_21f1f] = 1290, - [BNXT_ULP_CLASS_HID_21a53] = 1291, - [BNXT_ULP_CLASS_HID_22d63] = 1292, - [BNXT_ULP_CLASS_HID_255c3] = 1293, - [BNXT_ULP_CLASS_HID_242b3] = 1294, - [BNXT_ULP_CLASS_HID_23dc7] = 1295, - [BNXT_ULP_CLASS_HID_25117] = 1296, - [BNXT_ULP_CLASS_HID_22c13] = 1297, - [BNXT_ULP_CLASS_HID_218c3] = 1298, - [BNXT_ULP_CLASS_HID_21417] = 1299, - [BNXT_ULP_CLASS_HID_22727] = 1300, - [BNXT_ULP_CLASS_HID_24f87] = 1301, - [BNXT_ULP_CLASS_HID_23c77] = 1302, - [BNXT_ULP_CLASS_HID_2378b] = 1303, - [BNXT_ULP_CLASS_HID_24adb] = 1304, - [BNXT_ULP_CLASS_HID_257b] = 1305, - [BNXT_ULP_CLASS_HID_2bb7] = 1306, - [BNXT_ULP_CLASS_HID_1867] = 1307, - [BNXT_ULP_CLASS_HID_4f2b] = 1308, - [BNXT_ULP_CLASS_HID_3c1b] = 1309, - [BNXT_ULP_CLASS_HID_1613] = 1310, - [BNXT_ULP_CLASS_HID_02c3] = 1311, - [BNXT_ULP_CLASS_HID_3987] = 1312, - [BNXT_ULP_CLASS_HID_2677] = 1313, - [BNXT_ULP_CLASS_HID_122b] = 1314, - [BNXT_ULP_CLASS_HID_48ef] = 1315, - [BNXT_ULP_CLASS_HID_35df] = 1316, - [BNXT_ULP_CLASS_HID_0fd7] = 1317, - [BNXT_ULP_CLASS_HID_5973] = 1318, - [BNXT_ULP_CLASS_HID_334b] = 1319, - [BNXT_ULP_CLASS_HID_203b] = 1320, - [BNXT_ULP_CLASS_HID_25797] = 1321, - [BNXT_ULP_CLASS_HID_285eb] = 1322, - [BNXT_ULP_CLASS_HID_310eb] = 1323, - [BNXT_ULP_CLASS_HID_39beb] = 1324, - [BNXT_ULP_CLASS_HID_24447] = 1325, - [BNXT_ULP_CLASS_HID_2cf47] = 1326, - [BNXT_ULP_CLASS_HID_35a47] = 1327, - [BNXT_ULP_CLASS_HID_3889b] = 1328, - [BNXT_ULP_CLASS_HID_23f9b] = 1329, - [BNXT_ULP_CLASS_HID_2ca9b] = 1330, - [BNXT_ULP_CLASS_HID_3559b] = 1331, - [BNXT_ULP_CLASS_HID_383ef] = 1332, - [BNXT_ULP_CLASS_HID_252eb] = 1333, - [BNXT_ULP_CLASS_HID_2813f] = 1334, - [BNXT_ULP_CLASS_HID_30c3f] = 1335, - [BNXT_ULP_CLASS_HID_3973f] = 1336, - [BNXT_ULP_CLASS_HID_21e5f] = 1337, - [BNXT_ULP_CLASS_HID_2a95f] = 1338, - [BNXT_ULP_CLASS_HID_3345f] = 1339, - [BNXT_ULP_CLASS_HID_3bf5f] = 1340, - [BNXT_ULP_CLASS_HID_20b0f] = 1341, - [BNXT_ULP_CLASS_HID_2960f] = 1342, - [BNXT_ULP_CLASS_HID_3210f] = 1343, - [BNXT_ULP_CLASS_HID_3ac0f] = 1344, - [BNXT_ULP_CLASS_HID_20643] = 1345, - [BNXT_ULP_CLASS_HID_29143] = 1346, - [BNXT_ULP_CLASS_HID_31c43] = 1347, - [BNXT_ULP_CLASS_HID_3a743] = 1348, - [BNXT_ULP_CLASS_HID_21993] = 1349, - [BNXT_ULP_CLASS_HID_2a493] = 1350, - [BNXT_ULP_CLASS_HID_32f93] = 1351, - [BNXT_ULP_CLASS_HID_3ba93] = 1352, - [BNXT_ULP_CLASS_HID_24233] = 1353, - [BNXT_ULP_CLASS_HID_2cd33] = 1354, - [BNXT_ULP_CLASS_HID_35833] = 1355, - [BNXT_ULP_CLASS_HID_38607] = 1356, - [BNXT_ULP_CLASS_HID_22ee3] = 1357, - [BNXT_ULP_CLASS_HID_2b9e3] = 1358, - [BNXT_ULP_CLASS_HID_344e3] = 1359, - [BNXT_ULP_CLASS_HID_3cfe3] = 1360, - [BNXT_ULP_CLASS_HID_22a37] = 1361, - [BNXT_ULP_CLASS_HID_2b537] = 1362, - [BNXT_ULP_CLASS_HID_34037] = 1363, - [BNXT_ULP_CLASS_HID_3cb37] = 1364, - [BNXT_ULP_CLASS_HID_23d07] = 1365, - [BNXT_ULP_CLASS_HID_2c807] = 1366, - [BNXT_ULP_CLASS_HID_35307] = 1367, - [BNXT_ULP_CLASS_HID_3815b] = 1368, - [BNXT_ULP_CLASS_HID_208fb] = 1369, - [BNXT_ULP_CLASS_HID_293fb] = 1370, - [BNXT_ULP_CLASS_HID_31efb] = 1371, - [BNXT_ULP_CLASS_HID_3a9fb] = 1372, - [BNXT_ULP_CLASS_HID_25257] = 1373, - [BNXT_ULP_CLASS_HID_280ab] = 1374, - [BNXT_ULP_CLASS_HID_30bab] = 1375, - [BNXT_ULP_CLASS_HID_396ab] = 1376, - [BNXT_ULP_CLASS_HID_24dab] = 1377, - [BNXT_ULP_CLASS_HID_2d8ab] = 1378, - [BNXT_ULP_CLASS_HID_306ff] = 1379, - [BNXT_ULP_CLASS_HID_391ff] = 1380, - [BNXT_ULP_CLASS_HID_203cf] = 1381, - [BNXT_ULP_CLASS_HID_28ecf] = 1382, - [BNXT_ULP_CLASS_HID_319cf] = 1383, - [BNXT_ULP_CLASS_HID_3a4cf] = 1384, - [BNXT_ULP_CLASS_HID_2515b] = 1385, - [BNXT_ULP_CLASS_HID_2dc5b] = 1386, - [BNXT_ULP_CLASS_HID_30aaf] = 1387, - [BNXT_ULP_CLASS_HID_395af] = 1388, - [BNXT_ULP_CLASS_HID_23e0b] = 1389, - [BNXT_ULP_CLASS_HID_2c90b] = 1390, - [BNXT_ULP_CLASS_HID_3540b] = 1391, - [BNXT_ULP_CLASS_HID_3825f] = 1392, - [BNXT_ULP_CLASS_HID_2395f] = 1393, - [BNXT_ULP_CLASS_HID_2c45f] = 1394, - [BNXT_ULP_CLASS_HID_34f5f] = 1395, - [BNXT_ULP_CLASS_HID_3da5f] = 1396, - [BNXT_ULP_CLASS_HID_24caf] = 1397, - [BNXT_ULP_CLASS_HID_2d7af] = 1398, - [BNXT_ULP_CLASS_HID_305e3] = 1399, - [BNXT_ULP_CLASS_HID_390e3] = 1400, - [BNXT_ULP_CLASS_HID_21803] = 1401, - [BNXT_ULP_CLASS_HID_2a303] = 1402, - [BNXT_ULP_CLASS_HID_32e03] = 1403, - [BNXT_ULP_CLASS_HID_3b903] = 1404, - [BNXT_ULP_CLASS_HID_20533] = 1405, - [BNXT_ULP_CLASS_HID_29033] = 1406, - [BNXT_ULP_CLASS_HID_31b33] = 1407, - [BNXT_ULP_CLASS_HID_3a633] = 1408, - [BNXT_ULP_CLASS_HID_20007] = 1409, - [BNXT_ULP_CLASS_HID_28b07] = 1410, - [BNXT_ULP_CLASS_HID_31607] = 1411, - [BNXT_ULP_CLASS_HID_3a107] = 1412, - [BNXT_ULP_CLASS_HID_21357] = 1413, - [BNXT_ULP_CLASS_HID_29e57] = 1414, - [BNXT_ULP_CLASS_HID_32957] = 1415, - [BNXT_ULP_CLASS_HID_3b457] = 1416, - [BNXT_ULP_CLASS_HID_23bf7] = 1417, - [BNXT_ULP_CLASS_HID_2c6f7] = 1418, - [BNXT_ULP_CLASS_HID_351f7] = 1419, - [BNXT_ULP_CLASS_HID_3dcf7] = 1420, - [BNXT_ULP_CLASS_HID_228a7] = 1421, - [BNXT_ULP_CLASS_HID_2b3a7] = 1422, - [BNXT_ULP_CLASS_HID_33ea7] = 1423, - [BNXT_ULP_CLASS_HID_3c9a7] = 1424, - [BNXT_ULP_CLASS_HID_223fb] = 1425, - [BNXT_ULP_CLASS_HID_2aefb] = 1426, - [BNXT_ULP_CLASS_HID_339fb] = 1427, - [BNXT_ULP_CLASS_HID_3c4fb] = 1428, - [BNXT_ULP_CLASS_HID_236cb] = 1429, - [BNXT_ULP_CLASS_HID_2c1cb] = 1430, - [BNXT_ULP_CLASS_HID_34ccb] = 1431, - [BNXT_ULP_CLASS_HID_3d7cb] = 1432, - [BNXT_ULP_CLASS_HID_202bf] = 1433, - [BNXT_ULP_CLASS_HID_28dbf] = 1434, - [BNXT_ULP_CLASS_HID_318bf] = 1435, - [BNXT_ULP_CLASS_HID_3a3bf] = 1436, - [BNXT_ULP_CLASS_HID_24c1b] = 1437, - [BNXT_ULP_CLASS_HID_2d71b] = 1438, - [BNXT_ULP_CLASS_HID_3056f] = 1439, - [BNXT_ULP_CLASS_HID_3906f] = 1440, - [BNXT_ULP_CLASS_HID_2476f] = 1441, - [BNXT_ULP_CLASS_HID_2d26f] = 1442, - [BNXT_ULP_CLASS_HID_300a3] = 1443, - [BNXT_ULP_CLASS_HID_38ba3] = 1444, - [BNXT_ULP_CLASS_HID_25abf] = 1445, - [BNXT_ULP_CLASS_HID_288f3] = 1446, - [BNXT_ULP_CLASS_HID_313f3] = 1447, - [BNXT_ULP_CLASS_HID_39ef3] = 1448, - [BNXT_ULP_CLASS_HID_24b1f] = 1449, - [BNXT_ULP_CLASS_HID_2d61f] = 1450, - [BNXT_ULP_CLASS_HID_30453] = 1451, - [BNXT_ULP_CLASS_HID_38f53] = 1452, - [BNXT_ULP_CLASS_HID_237cf] = 1453, - [BNXT_ULP_CLASS_HID_2c2cf] = 1454, - [BNXT_ULP_CLASS_HID_34dcf] = 1455, - [BNXT_ULP_CLASS_HID_3d8cf] = 1456, - [BNXT_ULP_CLASS_HID_23303] = 1457, - [BNXT_ULP_CLASS_HID_2be03] = 1458, - [BNXT_ULP_CLASS_HID_34903] = 1459, - [BNXT_ULP_CLASS_HID_3d403] = 1460, - [BNXT_ULP_CLASS_HID_24653] = 1461, - [BNXT_ULP_CLASS_HID_2d153] = 1462, - [BNXT_ULP_CLASS_HID_35c53] = 1463, - [BNXT_ULP_CLASS_HID_38aa7] = 1464, - [BNXT_ULP_CLASS_HID_211c7] = 1465, - [BNXT_ULP_CLASS_HID_29cc7] = 1466, - [BNXT_ULP_CLASS_HID_327c7] = 1467, - [BNXT_ULP_CLASS_HID_3b2c7] = 1468, - [BNXT_ULP_CLASS_HID_25ba3] = 1469, - [BNXT_ULP_CLASS_HID_289f7] = 1470, - [BNXT_ULP_CLASS_HID_314f7] = 1471, - [BNXT_ULP_CLASS_HID_39ff7] = 1472, - [BNXT_ULP_CLASS_HID_256f7] = 1473, - [BNXT_ULP_CLASS_HID_284cb] = 1474, - [BNXT_ULP_CLASS_HID_30fcb] = 1475, - [BNXT_ULP_CLASS_HID_39acb] = 1476, - [BNXT_ULP_CLASS_HID_20d1b] = 1477, - [BNXT_ULP_CLASS_HID_2981b] = 1478, - [BNXT_ULP_CLASS_HID_3231b] = 1479, - [BNXT_ULP_CLASS_HID_3ae1b] = 1480, - [BNXT_ULP_CLASS_HID_235bb] = 1481, - [BNXT_ULP_CLASS_HID_2c0bb] = 1482, - [BNXT_ULP_CLASS_HID_34bbb] = 1483, - [BNXT_ULP_CLASS_HID_3d6bb] = 1484, - [BNXT_ULP_CLASS_HID_2226b] = 1485, - [BNXT_ULP_CLASS_HID_2ad6b] = 1486, - [BNXT_ULP_CLASS_HID_3386b] = 1487, - [BNXT_ULP_CLASS_HID_3c36b] = 1488, - [BNXT_ULP_CLASS_HID_21dbf] = 1489, - [BNXT_ULP_CLASS_HID_2a8bf] = 1490, - [BNXT_ULP_CLASS_HID_333bf] = 1491, - [BNXT_ULP_CLASS_HID_3bebf] = 1492, - [BNXT_ULP_CLASS_HID_2308f] = 1493, - [BNXT_ULP_CLASS_HID_2bb8f] = 1494, - [BNXT_ULP_CLASS_HID_3468f] = 1495, - [BNXT_ULP_CLASS_HID_3d18f] = 1496, - [BNXT_ULP_CLASS_HID_2592f] = 1497, - [BNXT_ULP_CLASS_HID_28763] = 1498, - [BNXT_ULP_CLASS_HID_31263] = 1499, - [BNXT_ULP_CLASS_HID_39d63] = 1500, - [BNXT_ULP_CLASS_HID_245df] = 1501, - [BNXT_ULP_CLASS_HID_2d0df] = 1502, - [BNXT_ULP_CLASS_HID_35bdf] = 1503, - [BNXT_ULP_CLASS_HID_38a13] = 1504, - [BNXT_ULP_CLASS_HID_24113] = 1505, - [BNXT_ULP_CLASS_HID_2cc13] = 1506, - [BNXT_ULP_CLASS_HID_35713] = 1507, - [BNXT_ULP_CLASS_HID_38567] = 1508, - [BNXT_ULP_CLASS_HID_25463] = 1509, - [BNXT_ULP_CLASS_HID_282b7] = 1510, - [BNXT_ULP_CLASS_HID_30db7] = 1511, - [BNXT_ULP_CLASS_HID_398b7] = 1512, - [BNXT_ULP_CLASS_HID_244c3] = 1513, - [BNXT_ULP_CLASS_HID_2cfc3] = 1514, - [BNXT_ULP_CLASS_HID_35ac3] = 1515, - [BNXT_ULP_CLASS_HID_38917] = 1516, - [BNXT_ULP_CLASS_HID_231f3] = 1517, - [BNXT_ULP_CLASS_HID_2bcf3] = 1518, - [BNXT_ULP_CLASS_HID_347f3] = 1519, - [BNXT_ULP_CLASS_HID_3d2f3] = 1520, - [BNXT_ULP_CLASS_HID_22cc7] = 1521, - [BNXT_ULP_CLASS_HID_2b7c7] = 1522, - [BNXT_ULP_CLASS_HID_342c7] = 1523, - [BNXT_ULP_CLASS_HID_3cdc7] = 1524, - [BNXT_ULP_CLASS_HID_24017] = 1525, - [BNXT_ULP_CLASS_HID_2cb17] = 1526, - [BNXT_ULP_CLASS_HID_35617] = 1527, - [BNXT_ULP_CLASS_HID_3846b] = 1528, - [BNXT_ULP_CLASS_HID_20b8b] = 1529, - [BNXT_ULP_CLASS_HID_2968b] = 1530, - [BNXT_ULP_CLASS_HID_3218b] = 1531, - [BNXT_ULP_CLASS_HID_3ac8b] = 1532, - [BNXT_ULP_CLASS_HID_25567] = 1533, - [BNXT_ULP_CLASS_HID_283bb] = 1534, - [BNXT_ULP_CLASS_HID_30ebb] = 1535, - [BNXT_ULP_CLASS_HID_399bb] = 1536, - [BNXT_ULP_CLASS_HID_250bb] = 1537, - [BNXT_ULP_CLASS_HID_2dbbb] = 1538, - [BNXT_ULP_CLASS_HID_3098f] = 1539, - [BNXT_ULP_CLASS_HID_3948f] = 1540, - [BNXT_ULP_CLASS_HID_206df] = 1541, - [BNXT_ULP_CLASS_HID_291df] = 1542, - [BNXT_ULP_CLASS_HID_31cdf] = 1543, - [BNXT_ULP_CLASS_HID_3a7df] = 1544, - [BNXT_ULP_CLASS_HID_22f7f] = 1545, - [BNXT_ULP_CLASS_HID_2ba7f] = 1546, - [BNXT_ULP_CLASS_HID_3457f] = 1547, - [BNXT_ULP_CLASS_HID_3d07f] = 1548, - [BNXT_ULP_CLASS_HID_21c2f] = 1549, - [BNXT_ULP_CLASS_HID_2a72f] = 1550, - [BNXT_ULP_CLASS_HID_3322f] = 1551, - [BNXT_ULP_CLASS_HID_3bd2f] = 1552, - [BNXT_ULP_CLASS_HID_21763] = 1553, - [BNXT_ULP_CLASS_HID_2a263] = 1554, - [BNXT_ULP_CLASS_HID_32d63] = 1555, - [BNXT_ULP_CLASS_HID_3b863] = 1556, - [BNXT_ULP_CLASS_HID_22ab3] = 1557, - [BNXT_ULP_CLASS_HID_2b5b3] = 1558, - [BNXT_ULP_CLASS_HID_340b3] = 1559, - [BNXT_ULP_CLASS_HID_3cbb3] = 1560, - [BNXT_ULP_CLASS_HID_252d3] = 1561, - [BNXT_ULP_CLASS_HID_28127] = 1562, - [BNXT_ULP_CLASS_HID_30c27] = 1563, - [BNXT_ULP_CLASS_HID_39727] = 1564, - [BNXT_ULP_CLASS_HID_23f83] = 1565, - [BNXT_ULP_CLASS_HID_2ca83] = 1566, - [BNXT_ULP_CLASS_HID_35583] = 1567, - [BNXT_ULP_CLASS_HID_383d7] = 1568, - [BNXT_ULP_CLASS_HID_23ad7] = 1569, - [BNXT_ULP_CLASS_HID_2c5d7] = 1570, - [BNXT_ULP_CLASS_HID_350d7] = 1571, - [BNXT_ULP_CLASS_HID_3dbd7] = 1572, - [BNXT_ULP_CLASS_HID_24e27] = 1573, - [BNXT_ULP_CLASS_HID_2d927] = 1574, - [BNXT_ULP_CLASS_HID_3077b] = 1575, - [BNXT_ULP_CLASS_HID_3927b] = 1576, - [BNXT_ULP_CLASS_HID_2320f] = 1577, - [BNXT_ULP_CLASS_HID_2bd0f] = 1578, - [BNXT_ULP_CLASS_HID_3480f] = 1579, - [BNXT_ULP_CLASS_HID_3d30f] = 1580, - [BNXT_ULP_CLASS_HID_21f3f] = 1581, - [BNXT_ULP_CLASS_HID_2aa3f] = 1582, - [BNXT_ULP_CLASS_HID_3353f] = 1583, - [BNXT_ULP_CLASS_HID_3c03f] = 1584, - [BNXT_ULP_CLASS_HID_21a73] = 1585, - [BNXT_ULP_CLASS_HID_2a573] = 1586, - [BNXT_ULP_CLASS_HID_33073] = 1587, - [BNXT_ULP_CLASS_HID_3bb73] = 1588, - [BNXT_ULP_CLASS_HID_22d43] = 1589, - [BNXT_ULP_CLASS_HID_2b843] = 1590, - [BNXT_ULP_CLASS_HID_34343] = 1591, - [BNXT_ULP_CLASS_HID_3ce43] = 1592, - [BNXT_ULP_CLASS_HID_255e3] = 1593, - [BNXT_ULP_CLASS_HID_28437] = 1594, - [BNXT_ULP_CLASS_HID_30f37] = 1595, - [BNXT_ULP_CLASS_HID_39a37] = 1596, - [BNXT_ULP_CLASS_HID_24293] = 1597, - [BNXT_ULP_CLASS_HID_2cd93] = 1598, - [BNXT_ULP_CLASS_HID_35893] = 1599, - [BNXT_ULP_CLASS_HID_386e7] = 1600, - [BNXT_ULP_CLASS_HID_23de7] = 1601, - [BNXT_ULP_CLASS_HID_2c8e7] = 1602, - [BNXT_ULP_CLASS_HID_353e7] = 1603, - [BNXT_ULP_CLASS_HID_3823b] = 1604, - [BNXT_ULP_CLASS_HID_25137] = 1605, - [BNXT_ULP_CLASS_HID_2dc37] = 1606, - [BNXT_ULP_CLASS_HID_30a0b] = 1607, - [BNXT_ULP_CLASS_HID_3950b] = 1608, - [BNXT_ULP_CLASS_HID_22c33] = 1609, - [BNXT_ULP_CLASS_HID_2b733] = 1610, - [BNXT_ULP_CLASS_HID_34233] = 1611, - [BNXT_ULP_CLASS_HID_3cd33] = 1612, - [BNXT_ULP_CLASS_HID_218e3] = 1613, - [BNXT_ULP_CLASS_HID_2a3e3] = 1614, - [BNXT_ULP_CLASS_HID_32ee3] = 1615, - [BNXT_ULP_CLASS_HID_3b9e3] = 1616, - [BNXT_ULP_CLASS_HID_21437] = 1617, - [BNXT_ULP_CLASS_HID_29f37] = 1618, - [BNXT_ULP_CLASS_HID_32a37] = 1619, - [BNXT_ULP_CLASS_HID_3b537] = 1620, - [BNXT_ULP_CLASS_HID_22707] = 1621, - [BNXT_ULP_CLASS_HID_2b207] = 1622, - [BNXT_ULP_CLASS_HID_33d07] = 1623, - [BNXT_ULP_CLASS_HID_3c807] = 1624, - [BNXT_ULP_CLASS_HID_24fa7] = 1625, - [BNXT_ULP_CLASS_HID_2daa7] = 1626, - [BNXT_ULP_CLASS_HID_308fb] = 1627, - [BNXT_ULP_CLASS_HID_393fb] = 1628, - [BNXT_ULP_CLASS_HID_23c57] = 1629, - [BNXT_ULP_CLASS_HID_2c757] = 1630, - [BNXT_ULP_CLASS_HID_35257] = 1631, - [BNXT_ULP_CLASS_HID_380ab] = 1632, - [BNXT_ULP_CLASS_HID_237ab] = 1633, - [BNXT_ULP_CLASS_HID_2c2ab] = 1634, - [BNXT_ULP_CLASS_HID_34dab] = 1635, - [BNXT_ULP_CLASS_HID_3d8ab] = 1636, - [BNXT_ULP_CLASS_HID_24afb] = 1637, - [BNXT_ULP_CLASS_HID_2d5fb] = 1638, - [BNXT_ULP_CLASS_HID_303cf] = 1639, - [BNXT_ULP_CLASS_HID_38ecf] = 1640, - [BNXT_ULP_CLASS_HID_255b] = 1641, - [BNXT_ULP_CLASS_HID_2b97] = 1642, - [BNXT_ULP_CLASS_HID_1847] = 1643, - [BNXT_ULP_CLASS_HID_4f0b] = 1644, - [BNXT_ULP_CLASS_HID_3c3b] = 1645, - [BNXT_ULP_CLASS_HID_1633] = 1646, - [BNXT_ULP_CLASS_HID_02e3] = 1647, - [BNXT_ULP_CLASS_HID_39a7] = 1648, - [BNXT_ULP_CLASS_HID_2657] = 1649, - [BNXT_ULP_CLASS_HID_120b] = 1650, - [BNXT_ULP_CLASS_HID_48cf] = 1651, - [BNXT_ULP_CLASS_HID_35ff] = 1652, - [BNXT_ULP_CLASS_HID_0ff7] = 1653, - [BNXT_ULP_CLASS_HID_5953] = 1654, - [BNXT_ULP_CLASS_HID_336b] = 1655, - [BNXT_ULP_CLASS_HID_201b] = 1656, - [BNXT_ULP_CLASS_HID_257f7] = 1657, - [BNXT_ULP_CLASS_HID_2858b] = 1658, - [BNXT_ULP_CLASS_HID_3108b] = 1659, - [BNXT_ULP_CLASS_HID_39b8b] = 1660, - [BNXT_ULP_CLASS_HID_24427] = 1661, - [BNXT_ULP_CLASS_HID_2cf27] = 1662, - [BNXT_ULP_CLASS_HID_35a27] = 1663, - [BNXT_ULP_CLASS_HID_388fb] = 1664, - [BNXT_ULP_CLASS_HID_23ffb] = 1665, - [BNXT_ULP_CLASS_HID_2cafb] = 1666, - [BNXT_ULP_CLASS_HID_355fb] = 1667, - [BNXT_ULP_CLASS_HID_3838f] = 1668, - [BNXT_ULP_CLASS_HID_2528b] = 1669, - [BNXT_ULP_CLASS_HID_2815f] = 1670, - [BNXT_ULP_CLASS_HID_30c5f] = 1671, - [BNXT_ULP_CLASS_HID_3975f] = 1672, - [BNXT_ULP_CLASS_HID_21e3f] = 1673, - [BNXT_ULP_CLASS_HID_2a93f] = 1674, - [BNXT_ULP_CLASS_HID_3343f] = 1675, - [BNXT_ULP_CLASS_HID_3bf3f] = 1676, - [BNXT_ULP_CLASS_HID_20b6f] = 1677, - [BNXT_ULP_CLASS_HID_2966f] = 1678, - [BNXT_ULP_CLASS_HID_3216f] = 1679, - [BNXT_ULP_CLASS_HID_3ac6f] = 1680, - [BNXT_ULP_CLASS_HID_20623] = 1681, - [BNXT_ULP_CLASS_HID_29123] = 1682, - [BNXT_ULP_CLASS_HID_31c23] = 1683, - [BNXT_ULP_CLASS_HID_3a723] = 1684, - [BNXT_ULP_CLASS_HID_219f3] = 1685, - [BNXT_ULP_CLASS_HID_2a4f3] = 1686, - [BNXT_ULP_CLASS_HID_32ff3] = 1687, - [BNXT_ULP_CLASS_HID_3baf3] = 1688, - [BNXT_ULP_CLASS_HID_24253] = 1689, - [BNXT_ULP_CLASS_HID_2cd53] = 1690, - [BNXT_ULP_CLASS_HID_35853] = 1691, - [BNXT_ULP_CLASS_HID_38667] = 1692, - [BNXT_ULP_CLASS_HID_22e83] = 1693, - [BNXT_ULP_CLASS_HID_2b983] = 1694, - [BNXT_ULP_CLASS_HID_34483] = 1695, - [BNXT_ULP_CLASS_HID_3cf83] = 1696, - [BNXT_ULP_CLASS_HID_22a57] = 1697, - [BNXT_ULP_CLASS_HID_2b557] = 1698, - [BNXT_ULP_CLASS_HID_34057] = 1699, - [BNXT_ULP_CLASS_HID_3cb57] = 1700, - [BNXT_ULP_CLASS_HID_23d67] = 1701, - [BNXT_ULP_CLASS_HID_2c867] = 1702, - [BNXT_ULP_CLASS_HID_35367] = 1703, - [BNXT_ULP_CLASS_HID_3813b] = 1704, - [BNXT_ULP_CLASS_HID_2089b] = 1705, - [BNXT_ULP_CLASS_HID_2939b] = 1706, - [BNXT_ULP_CLASS_HID_31e9b] = 1707, - [BNXT_ULP_CLASS_HID_3a99b] = 1708, - [BNXT_ULP_CLASS_HID_25237] = 1709, - [BNXT_ULP_CLASS_HID_280cb] = 1710, - [BNXT_ULP_CLASS_HID_30bcb] = 1711, - [BNXT_ULP_CLASS_HID_396cb] = 1712, - [BNXT_ULP_CLASS_HID_24dcb] = 1713, - [BNXT_ULP_CLASS_HID_2d8cb] = 1714, - [BNXT_ULP_CLASS_HID_3069f] = 1715, - [BNXT_ULP_CLASS_HID_3919f] = 1716, - [BNXT_ULP_CLASS_HID_203af] = 1717, - [BNXT_ULP_CLASS_HID_28eaf] = 1718, - [BNXT_ULP_CLASS_HID_319af] = 1719, - [BNXT_ULP_CLASS_HID_3a4af] = 1720, - [BNXT_ULP_CLASS_HID_2513b] = 1721, - [BNXT_ULP_CLASS_HID_2dc3b] = 1722, - [BNXT_ULP_CLASS_HID_30acf] = 1723, - [BNXT_ULP_CLASS_HID_395cf] = 1724, - [BNXT_ULP_CLASS_HID_23e6b] = 1725, - [BNXT_ULP_CLASS_HID_2c96b] = 1726, - [BNXT_ULP_CLASS_HID_3546b] = 1727, - [BNXT_ULP_CLASS_HID_3823f] = 1728, - [BNXT_ULP_CLASS_HID_2393f] = 1729, - [BNXT_ULP_CLASS_HID_2c43f] = 1730, - [BNXT_ULP_CLASS_HID_34f3f] = 1731, - [BNXT_ULP_CLASS_HID_3da3f] = 1732, - [BNXT_ULP_CLASS_HID_24ccf] = 1733, - [BNXT_ULP_CLASS_HID_2d7cf] = 1734, - [BNXT_ULP_CLASS_HID_30583] = 1735, - [BNXT_ULP_CLASS_HID_39083] = 1736, - [BNXT_ULP_CLASS_HID_21863] = 1737, - [BNXT_ULP_CLASS_HID_2a363] = 1738, - [BNXT_ULP_CLASS_HID_32e63] = 1739, - [BNXT_ULP_CLASS_HID_3b963] = 1740, - [BNXT_ULP_CLASS_HID_20553] = 1741, - [BNXT_ULP_CLASS_HID_29053] = 1742, - [BNXT_ULP_CLASS_HID_31b53] = 1743, - [BNXT_ULP_CLASS_HID_3a653] = 1744, - [BNXT_ULP_CLASS_HID_20067] = 1745, - [BNXT_ULP_CLASS_HID_28b67] = 1746, - [BNXT_ULP_CLASS_HID_31667] = 1747, - [BNXT_ULP_CLASS_HID_3a167] = 1748, - [BNXT_ULP_CLASS_HID_21337] = 1749, - [BNXT_ULP_CLASS_HID_29e37] = 1750, - [BNXT_ULP_CLASS_HID_32937] = 1751, - [BNXT_ULP_CLASS_HID_3b437] = 1752, - [BNXT_ULP_CLASS_HID_23b97] = 1753, - [BNXT_ULP_CLASS_HID_2c697] = 1754, - [BNXT_ULP_CLASS_HID_35197] = 1755, - [BNXT_ULP_CLASS_HID_3dc97] = 1756, - [BNXT_ULP_CLASS_HID_228c7] = 1757, - [BNXT_ULP_CLASS_HID_2b3c7] = 1758, - [BNXT_ULP_CLASS_HID_33ec7] = 1759, - [BNXT_ULP_CLASS_HID_3c9c7] = 1760, - [BNXT_ULP_CLASS_HID_2239b] = 1761, - [BNXT_ULP_CLASS_HID_2ae9b] = 1762, - [BNXT_ULP_CLASS_HID_3399b] = 1763, - [BNXT_ULP_CLASS_HID_3c49b] = 1764, - [BNXT_ULP_CLASS_HID_236ab] = 1765, - [BNXT_ULP_CLASS_HID_2c1ab] = 1766, - [BNXT_ULP_CLASS_HID_34cab] = 1767, - [BNXT_ULP_CLASS_HID_3d7ab] = 1768, - [BNXT_ULP_CLASS_HID_202df] = 1769, - [BNXT_ULP_CLASS_HID_28ddf] = 1770, - [BNXT_ULP_CLASS_HID_318df] = 1771, - [BNXT_ULP_CLASS_HID_3a3df] = 1772, - [BNXT_ULP_CLASS_HID_24c7b] = 1773, - [BNXT_ULP_CLASS_HID_2d77b] = 1774, - [BNXT_ULP_CLASS_HID_3050f] = 1775, - [BNXT_ULP_CLASS_HID_3900f] = 1776, - [BNXT_ULP_CLASS_HID_2470f] = 1777, - [BNXT_ULP_CLASS_HID_2d20f] = 1778, - [BNXT_ULP_CLASS_HID_300c3] = 1779, - [BNXT_ULP_CLASS_HID_38bc3] = 1780, - [BNXT_ULP_CLASS_HID_25adf] = 1781, - [BNXT_ULP_CLASS_HID_28893] = 1782, - [BNXT_ULP_CLASS_HID_31393] = 1783, - [BNXT_ULP_CLASS_HID_39e93] = 1784, - [BNXT_ULP_CLASS_HID_24b7f] = 1785, - [BNXT_ULP_CLASS_HID_2d67f] = 1786, - [BNXT_ULP_CLASS_HID_30433] = 1787, - [BNXT_ULP_CLASS_HID_38f33] = 1788, - [BNXT_ULP_CLASS_HID_237af] = 1789, - [BNXT_ULP_CLASS_HID_2c2af] = 1790, - [BNXT_ULP_CLASS_HID_34daf] = 1791, - [BNXT_ULP_CLASS_HID_3d8af] = 1792, - [BNXT_ULP_CLASS_HID_23363] = 1793, - [BNXT_ULP_CLASS_HID_2be63] = 1794, - [BNXT_ULP_CLASS_HID_34963] = 1795, - [BNXT_ULP_CLASS_HID_3d463] = 1796, - [BNXT_ULP_CLASS_HID_24633] = 1797, - [BNXT_ULP_CLASS_HID_2d133] = 1798, - [BNXT_ULP_CLASS_HID_35c33] = 1799, - [BNXT_ULP_CLASS_HID_38ac7] = 1800, - [BNXT_ULP_CLASS_HID_211a7] = 1801, - [BNXT_ULP_CLASS_HID_29ca7] = 1802, - [BNXT_ULP_CLASS_HID_327a7] = 1803, - [BNXT_ULP_CLASS_HID_3b2a7] = 1804, - [BNXT_ULP_CLASS_HID_25bc3] = 1805, - [BNXT_ULP_CLASS_HID_28997] = 1806, - [BNXT_ULP_CLASS_HID_31497] = 1807, - [BNXT_ULP_CLASS_HID_39f97] = 1808, - [BNXT_ULP_CLASS_HID_25697] = 1809, - [BNXT_ULP_CLASS_HID_284ab] = 1810, - [BNXT_ULP_CLASS_HID_30fab] = 1811, - [BNXT_ULP_CLASS_HID_39aab] = 1812, - [BNXT_ULP_CLASS_HID_20d7b] = 1813, - [BNXT_ULP_CLASS_HID_2987b] = 1814, - [BNXT_ULP_CLASS_HID_3237b] = 1815, - [BNXT_ULP_CLASS_HID_3ae7b] = 1816, - [BNXT_ULP_CLASS_HID_235db] = 1817, - [BNXT_ULP_CLASS_HID_2c0db] = 1818, - [BNXT_ULP_CLASS_HID_34bdb] = 1819, - [BNXT_ULP_CLASS_HID_3d6db] = 1820, - [BNXT_ULP_CLASS_HID_2220b] = 1821, - [BNXT_ULP_CLASS_HID_2ad0b] = 1822, - [BNXT_ULP_CLASS_HID_3380b] = 1823, - [BNXT_ULP_CLASS_HID_3c30b] = 1824, - [BNXT_ULP_CLASS_HID_21ddf] = 1825, - [BNXT_ULP_CLASS_HID_2a8df] = 1826, - [BNXT_ULP_CLASS_HID_333df] = 1827, - [BNXT_ULP_CLASS_HID_3bedf] = 1828, - [BNXT_ULP_CLASS_HID_230ef] = 1829, - [BNXT_ULP_CLASS_HID_2bbef] = 1830, - [BNXT_ULP_CLASS_HID_346ef] = 1831, - [BNXT_ULP_CLASS_HID_3d1ef] = 1832, - [BNXT_ULP_CLASS_HID_2594f] = 1833, - [BNXT_ULP_CLASS_HID_28703] = 1834, - [BNXT_ULP_CLASS_HID_31203] = 1835, - [BNXT_ULP_CLASS_HID_39d03] = 1836, - [BNXT_ULP_CLASS_HID_245bf] = 1837, - [BNXT_ULP_CLASS_HID_2d0bf] = 1838, - [BNXT_ULP_CLASS_HID_35bbf] = 1839, - [BNXT_ULP_CLASS_HID_38a73] = 1840, - [BNXT_ULP_CLASS_HID_24173] = 1841, - [BNXT_ULP_CLASS_HID_2cc73] = 1842, - [BNXT_ULP_CLASS_HID_35773] = 1843, - [BNXT_ULP_CLASS_HID_38507] = 1844, - [BNXT_ULP_CLASS_HID_25403] = 1845, - [BNXT_ULP_CLASS_HID_282d7] = 1846, - [BNXT_ULP_CLASS_HID_30dd7] = 1847, - [BNXT_ULP_CLASS_HID_398d7] = 1848, - [BNXT_ULP_CLASS_HID_244a3] = 1849, - [BNXT_ULP_CLASS_HID_2cfa3] = 1850, - [BNXT_ULP_CLASS_HID_35aa3] = 1851, - [BNXT_ULP_CLASS_HID_38977] = 1852, - [BNXT_ULP_CLASS_HID_23193] = 1853, - [BNXT_ULP_CLASS_HID_2bc93] = 1854, - [BNXT_ULP_CLASS_HID_34793] = 1855, - [BNXT_ULP_CLASS_HID_3d293] = 1856, - [BNXT_ULP_CLASS_HID_22ca7] = 1857, - [BNXT_ULP_CLASS_HID_2b7a7] = 1858, - [BNXT_ULP_CLASS_HID_342a7] = 1859, - [BNXT_ULP_CLASS_HID_3cda7] = 1860, - [BNXT_ULP_CLASS_HID_24077] = 1861, - [BNXT_ULP_CLASS_HID_2cb77] = 1862, - [BNXT_ULP_CLASS_HID_35677] = 1863, - [BNXT_ULP_CLASS_HID_3840b] = 1864, - [BNXT_ULP_CLASS_HID_20beb] = 1865, - [BNXT_ULP_CLASS_HID_296eb] = 1866, - [BNXT_ULP_CLASS_HID_321eb] = 1867, - [BNXT_ULP_CLASS_HID_3aceb] = 1868, - [BNXT_ULP_CLASS_HID_25507] = 1869, - [BNXT_ULP_CLASS_HID_283db] = 1870, - [BNXT_ULP_CLASS_HID_30edb] = 1871, - [BNXT_ULP_CLASS_HID_399db] = 1872, - [BNXT_ULP_CLASS_HID_250db] = 1873, - [BNXT_ULP_CLASS_HID_2dbdb] = 1874, - [BNXT_ULP_CLASS_HID_309ef] = 1875, - [BNXT_ULP_CLASS_HID_394ef] = 1876, - [BNXT_ULP_CLASS_HID_206bf] = 1877, - [BNXT_ULP_CLASS_HID_291bf] = 1878, - [BNXT_ULP_CLASS_HID_31cbf] = 1879, - [BNXT_ULP_CLASS_HID_3a7bf] = 1880, - [BNXT_ULP_CLASS_HID_22f1f] = 1881, - [BNXT_ULP_CLASS_HID_2ba1f] = 1882, - [BNXT_ULP_CLASS_HID_3451f] = 1883, - [BNXT_ULP_CLASS_HID_3d01f] = 1884, - [BNXT_ULP_CLASS_HID_21c4f] = 1885, - [BNXT_ULP_CLASS_HID_2a74f] = 1886, - [BNXT_ULP_CLASS_HID_3324f] = 1887, - [BNXT_ULP_CLASS_HID_3bd4f] = 1888, - [BNXT_ULP_CLASS_HID_21703] = 1889, - [BNXT_ULP_CLASS_HID_2a203] = 1890, - [BNXT_ULP_CLASS_HID_32d03] = 1891, - [BNXT_ULP_CLASS_HID_3b803] = 1892, - [BNXT_ULP_CLASS_HID_22ad3] = 1893, - [BNXT_ULP_CLASS_HID_2b5d3] = 1894, - [BNXT_ULP_CLASS_HID_340d3] = 1895, - [BNXT_ULP_CLASS_HID_3cbd3] = 1896, - [BNXT_ULP_CLASS_HID_252b3] = 1897, - [BNXT_ULP_CLASS_HID_28147] = 1898, - [BNXT_ULP_CLASS_HID_30c47] = 1899, - [BNXT_ULP_CLASS_HID_39747] = 1900, - [BNXT_ULP_CLASS_HID_23fe3] = 1901, - [BNXT_ULP_CLASS_HID_2cae3] = 1902, - [BNXT_ULP_CLASS_HID_355e3] = 1903, - [BNXT_ULP_CLASS_HID_383b7] = 1904, - [BNXT_ULP_CLASS_HID_23ab7] = 1905, - [BNXT_ULP_CLASS_HID_2c5b7] = 1906, - [BNXT_ULP_CLASS_HID_350b7] = 1907, - [BNXT_ULP_CLASS_HID_3dbb7] = 1908, - [BNXT_ULP_CLASS_HID_24e47] = 1909, - [BNXT_ULP_CLASS_HID_2d947] = 1910, - [BNXT_ULP_CLASS_HID_3071b] = 1911, - [BNXT_ULP_CLASS_HID_3921b] = 1912, - [BNXT_ULP_CLASS_HID_2326f] = 1913, - [BNXT_ULP_CLASS_HID_2bd6f] = 1914, - [BNXT_ULP_CLASS_HID_3486f] = 1915, - [BNXT_ULP_CLASS_HID_3d36f] = 1916, - [BNXT_ULP_CLASS_HID_21f5f] = 1917, - [BNXT_ULP_CLASS_HID_2aa5f] = 1918, - [BNXT_ULP_CLASS_HID_3355f] = 1919, - [BNXT_ULP_CLASS_HID_3c05f] = 1920, - [BNXT_ULP_CLASS_HID_21a13] = 1921, - [BNXT_ULP_CLASS_HID_2a513] = 1922, - [BNXT_ULP_CLASS_HID_33013] = 1923, - [BNXT_ULP_CLASS_HID_3bb13] = 1924, - [BNXT_ULP_CLASS_HID_22d23] = 1925, - [BNXT_ULP_CLASS_HID_2b823] = 1926, - [BNXT_ULP_CLASS_HID_34323] = 1927, - [BNXT_ULP_CLASS_HID_3ce23] = 1928, - [BNXT_ULP_CLASS_HID_25583] = 1929, - [BNXT_ULP_CLASS_HID_28457] = 1930, - [BNXT_ULP_CLASS_HID_30f57] = 1931, - [BNXT_ULP_CLASS_HID_39a57] = 1932, - [BNXT_ULP_CLASS_HID_242f3] = 1933, - [BNXT_ULP_CLASS_HID_2cdf3] = 1934, - [BNXT_ULP_CLASS_HID_358f3] = 1935, - [BNXT_ULP_CLASS_HID_38687] = 1936, - [BNXT_ULP_CLASS_HID_23d87] = 1937, - [BNXT_ULP_CLASS_HID_2c887] = 1938, - [BNXT_ULP_CLASS_HID_35387] = 1939, - [BNXT_ULP_CLASS_HID_3825b] = 1940, - [BNXT_ULP_CLASS_HID_25157] = 1941, - [BNXT_ULP_CLASS_HID_2dc57] = 1942, - [BNXT_ULP_CLASS_HID_30a6b] = 1943, - [BNXT_ULP_CLASS_HID_3956b] = 1944, - [BNXT_ULP_CLASS_HID_22c53] = 1945, - [BNXT_ULP_CLASS_HID_2b753] = 1946, - [BNXT_ULP_CLASS_HID_34253] = 1947, - [BNXT_ULP_CLASS_HID_3cd53] = 1948, - [BNXT_ULP_CLASS_HID_21883] = 1949, - [BNXT_ULP_CLASS_HID_2a383] = 1950, - [BNXT_ULP_CLASS_HID_32e83] = 1951, - [BNXT_ULP_CLASS_HID_3b983] = 1952, - [BNXT_ULP_CLASS_HID_21457] = 1953, - [BNXT_ULP_CLASS_HID_29f57] = 1954, - [BNXT_ULP_CLASS_HID_32a57] = 1955, - [BNXT_ULP_CLASS_HID_3b557] = 1956, - [BNXT_ULP_CLASS_HID_22767] = 1957, - [BNXT_ULP_CLASS_HID_2b267] = 1958, - [BNXT_ULP_CLASS_HID_33d67] = 1959, - [BNXT_ULP_CLASS_HID_3c867] = 1960, - [BNXT_ULP_CLASS_HID_24fc7] = 1961, - [BNXT_ULP_CLASS_HID_2dac7] = 1962, - [BNXT_ULP_CLASS_HID_3089b] = 1963, - [BNXT_ULP_CLASS_HID_3939b] = 1964, - [BNXT_ULP_CLASS_HID_23c37] = 1965, - [BNXT_ULP_CLASS_HID_2c737] = 1966, - [BNXT_ULP_CLASS_HID_35237] = 1967, - [BNXT_ULP_CLASS_HID_380cb] = 1968, - [BNXT_ULP_CLASS_HID_237cb] = 1969, - [BNXT_ULP_CLASS_HID_2c2cb] = 1970, - [BNXT_ULP_CLASS_HID_34dcb] = 1971, - [BNXT_ULP_CLASS_HID_3d8cb] = 1972, - [BNXT_ULP_CLASS_HID_24a9b] = 1973, - [BNXT_ULP_CLASS_HID_2d59b] = 1974, - [BNXT_ULP_CLASS_HID_303af] = 1975, - [BNXT_ULP_CLASS_HID_38eaf] = 1976, - [BNXT_ULP_CLASS_HID_253b] = 1977, - [BNXT_ULP_CLASS_HID_2bf7] = 1978, - [BNXT_ULP_CLASS_HID_1827] = 1979, - [BNXT_ULP_CLASS_HID_4f6b] = 1980, - [BNXT_ULP_CLASS_HID_3c5b] = 1981, - [BNXT_ULP_CLASS_HID_1653] = 1982, - [BNXT_ULP_CLASS_HID_0283] = 1983, - [BNXT_ULP_CLASS_HID_39c7] = 1984, - [BNXT_ULP_CLASS_HID_2637] = 1985, - [BNXT_ULP_CLASS_HID_126b] = 1986, - [BNXT_ULP_CLASS_HID_48af] = 1987, - [BNXT_ULP_CLASS_HID_359f] = 1988, - [BNXT_ULP_CLASS_HID_0f97] = 1989, - [BNXT_ULP_CLASS_HID_5933] = 1990, - [BNXT_ULP_CLASS_HID_330b] = 1991, - [BNXT_ULP_CLASS_HID_207b] = 1992, - [BNXT_ULP_CLASS_HID_374e] = 1993, - [BNXT_ULP_CLASS_HID_11ee] = 1994, - [BNXT_ULP_CLASS_HID_423a] = 1995, - [BNXT_ULP_CLASS_HID_0cd6] = 1996, - [BNXT_ULP_CLASS_HID_310a] = 1997, - [BNXT_ULP_CLASS_HID_469e] = 1998, - [BNXT_ULP_CLASS_HID_5ce6] = 1999, - [BNXT_ULP_CLASS_HID_0692] = 2000, - [BNXT_ULP_CLASS_HID_1c7e] = 2001, - [BNXT_ULP_CLASS_HID_55c2] = 2002, - [BNXT_ULP_CLASS_HID_2b2a] = 2003, - [BNXT_ULP_CLASS_HID_15c6] = 2004, - [BNXT_ULP_CLASS_HID_163a] = 2005, - [BNXT_ULP_CLASS_HID_2f8e] = 2006, - [BNXT_ULP_CLASS_HID_2516] = 2007, - [BNXT_ULP_CLASS_HID_4b76] = 2008, - [BNXT_ULP_CLASS_HID_10e6] = 2009, - [BNXT_ULP_CLASS_HID_264a] = 2010, - [BNXT_ULP_CLASS_HID_3fd2] = 2011, - [BNXT_ULP_CLASS_HID_4532] = 2012, - [BNXT_ULP_CLASS_HID_4996] = 2013, - [BNXT_ULP_CLASS_HID_2036] = 2014, - [BNXT_ULP_CLASS_HID_399e] = 2015, - [BNXT_ULP_CLASS_HID_5ffe] = 2016, - [BNXT_ULP_CLASS_HID_34fe] = 2017, - [BNXT_ULP_CLASS_HID_3a32] = 2018, - [BNXT_ULP_CLASS_HID_14d2] = 2019, - [BNXT_ULP_CLASS_HID_4a42] = 2020, - [BNXT_ULP_CLASS_HID_376e] = 2021, - [BNXT_ULP_CLASS_HID_12d6e] = 2022, - [BNXT_ULP_CLASS_HID_2436e] = 2023, - [BNXT_ULP_CLASS_HID_31dba] = 2024, - [BNXT_ULP_CLASS_HID_11ce] = 2025, - [BNXT_ULP_CLASS_HID_107ce] = 2026, - [BNXT_ULP_CLASS_HID_23dce] = 2027, - [BNXT_ULP_CLASS_HID_353ce] = 2028, - [BNXT_ULP_CLASS_HID_421a] = 2029, - [BNXT_ULP_CLASS_HID_11d56] = 2030, - [BNXT_ULP_CLASS_HID_23356] = 2031, - [BNXT_ULP_CLASS_HID_32956] = 2032, - [BNXT_ULP_CLASS_HID_0cf6] = 2033, - [BNXT_ULP_CLASS_HID_122f6] = 2034, - [BNXT_ULP_CLASS_HID_258f6] = 2035, - [BNXT_ULP_CLASS_HID_313c2] = 2036, - [BNXT_ULP_CLASS_HID_312a] = 2037, - [BNXT_ULP_CLASS_HID_1272a] = 2038, - [BNXT_ULP_CLASS_HID_25d2a] = 2039, - [BNXT_ULP_CLASS_HID_31466] = 2040, - [BNXT_ULP_CLASS_HID_46be] = 2041, - [BNXT_ULP_CLASS_HID_1018a] = 2042, - [BNXT_ULP_CLASS_HID_2378a] = 2043, - [BNXT_ULP_CLASS_HID_32d8a] = 2044, - [BNXT_ULP_CLASS_HID_5cc6] = 2045, - [BNXT_ULP_CLASS_HID_11712] = 2046, - [BNXT_ULP_CLASS_HID_20d12] = 2047, - [BNXT_ULP_CLASS_HID_32312] = 2048, - [BNXT_ULP_CLASS_HID_06b2] = 2049, - [BNXT_ULP_CLASS_HID_13cb2] = 2050, - [BNXT_ULP_CLASS_HID_252b2] = 2051, - [BNXT_ULP_CLASS_HID_348b2] = 2052, - [BNXT_ULP_CLASS_HID_1c5e] = 2053, - [BNXT_ULP_CLASS_HID_1325e] = 2054, - [BNXT_ULP_CLASS_HID_2285e] = 2055, - [BNXT_ULP_CLASS_HID_35e5e] = 2056, - [BNXT_ULP_CLASS_HID_55e2] = 2057, - [BNXT_ULP_CLASS_HID_14be2] = 2058, - [BNXT_ULP_CLASS_HID_2023e] = 2059, - [BNXT_ULP_CLASS_HID_3383e] = 2060, - [BNXT_ULP_CLASS_HID_2b0a] = 2061, - [BNXT_ULP_CLASS_HID_1410a] = 2062, - [BNXT_ULP_CLASS_HID_21846] = 2063, - [BNXT_ULP_CLASS_HID_30e46] = 2064, - [BNXT_ULP_CLASS_HID_15e6] = 2065, - [BNXT_ULP_CLASS_HID_10be6] = 2066, - [BNXT_ULP_CLASS_HID_221e6] = 2067, - [BNXT_ULP_CLASS_HID_357e6] = 2068, - [BNXT_ULP_CLASS_HID_161a] = 2069, - [BNXT_ULP_CLASS_HID_10c1a] = 2070, - [BNXT_ULP_CLASS_HID_2221a] = 2071, - [BNXT_ULP_CLASS_HID_3581a] = 2072, - [BNXT_ULP_CLASS_HID_2fae] = 2073, - [BNXT_ULP_CLASS_HID_145ae] = 2074, - [BNXT_ULP_CLASS_HID_21cfa] = 2075, - [BNXT_ULP_CLASS_HID_332fa] = 2076, - [BNXT_ULP_CLASS_HID_2536] = 2077, - [BNXT_ULP_CLASS_HID_15b36] = 2078, - [BNXT_ULP_CLASS_HID_21202] = 2079, - [BNXT_ULP_CLASS_HID_30802] = 2080, - [BNXT_ULP_CLASS_HID_4b56] = 2081, - [BNXT_ULP_CLASS_HID_105a2] = 2082, - [BNXT_ULP_CLASS_HID_23ba2] = 2083, - [BNXT_ULP_CLASS_HID_351a2] = 2084, - [BNXT_ULP_CLASS_HID_10c6] = 2085, - [BNXT_ULP_CLASS_HID_106c6] = 2086, - [BNXT_ULP_CLASS_HID_23cc6] = 2087, - [BNXT_ULP_CLASS_HID_352c6] = 2088, - [BNXT_ULP_CLASS_HID_266a] = 2089, - [BNXT_ULP_CLASS_HID_15c6a] = 2090, - [BNXT_ULP_CLASS_HID_216a6] = 2091, - [BNXT_ULP_CLASS_HID_30ca6] = 2092, - [BNXT_ULP_CLASS_HID_3ff2] = 2093, - [BNXT_ULP_CLASS_HID_155f2] = 2094, - [BNXT_ULP_CLASS_HID_24bf2] = 2095, - [BNXT_ULP_CLASS_HID_302ce] = 2096, - [BNXT_ULP_CLASS_HID_4512] = 2097, - [BNXT_ULP_CLASS_HID_11c6e] = 2098, - [BNXT_ULP_CLASS_HID_2326e] = 2099, - [BNXT_ULP_CLASS_HID_3286e] = 2100, - [BNXT_ULP_CLASS_HID_49b6] = 2101, - [BNXT_ULP_CLASS_HID_10082] = 2102, - [BNXT_ULP_CLASS_HID_23682] = 2103, - [BNXT_ULP_CLASS_HID_32c82] = 2104, - [BNXT_ULP_CLASS_HID_2016] = 2105, - [BNXT_ULP_CLASS_HID_15616] = 2106, - [BNXT_ULP_CLASS_HID_21162] = 2107, - [BNXT_ULP_CLASS_HID_30762] = 2108, - [BNXT_ULP_CLASS_HID_39be] = 2109, - [BNXT_ULP_CLASS_HID_12fbe] = 2110, - [BNXT_ULP_CLASS_HID_245be] = 2111, - [BNXT_ULP_CLASS_HID_31c8a] = 2112, - [BNXT_ULP_CLASS_HID_5fde] = 2113, - [BNXT_ULP_CLASS_HID_1162a] = 2114, - [BNXT_ULP_CLASS_HID_20c2a] = 2115, - [BNXT_ULP_CLASS_HID_3222a] = 2116, - [BNXT_ULP_CLASS_HID_34de] = 2117, - [BNXT_ULP_CLASS_HID_3a12] = 2118, - [BNXT_ULP_CLASS_HID_14f2] = 2119, - [BNXT_ULP_CLASS_HID_4a62] = 2120, - [BNXT_ULP_CLASS_HID_370e] = 2121, - [BNXT_ULP_CLASS_HID_12d0e] = 2122, - [BNXT_ULP_CLASS_HID_2430e] = 2123, - [BNXT_ULP_CLASS_HID_31dda] = 2124, - [BNXT_ULP_CLASS_HID_11ae] = 2125, - [BNXT_ULP_CLASS_HID_107ae] = 2126, - [BNXT_ULP_CLASS_HID_23dae] = 2127, - [BNXT_ULP_CLASS_HID_353ae] = 2128, - [BNXT_ULP_CLASS_HID_427a] = 2129, - [BNXT_ULP_CLASS_HID_11d36] = 2130, - [BNXT_ULP_CLASS_HID_23336] = 2131, - [BNXT_ULP_CLASS_HID_32936] = 2132, - [BNXT_ULP_CLASS_HID_0c96] = 2133, - [BNXT_ULP_CLASS_HID_12296] = 2134, - [BNXT_ULP_CLASS_HID_25896] = 2135, - [BNXT_ULP_CLASS_HID_313a2] = 2136, - [BNXT_ULP_CLASS_HID_314a] = 2137, - [BNXT_ULP_CLASS_HID_1274a] = 2138, - [BNXT_ULP_CLASS_HID_25d4a] = 2139, - [BNXT_ULP_CLASS_HID_31406] = 2140, - [BNXT_ULP_CLASS_HID_46de] = 2141, - [BNXT_ULP_CLASS_HID_101ea] = 2142, - [BNXT_ULP_CLASS_HID_237ea] = 2143, - [BNXT_ULP_CLASS_HID_32dea] = 2144, - [BNXT_ULP_CLASS_HID_5ca6] = 2145, - [BNXT_ULP_CLASS_HID_11772] = 2146, - [BNXT_ULP_CLASS_HID_20d72] = 2147, - [BNXT_ULP_CLASS_HID_32372] = 2148, - [BNXT_ULP_CLASS_HID_06d2] = 2149, - [BNXT_ULP_CLASS_HID_13cd2] = 2150, - [BNXT_ULP_CLASS_HID_252d2] = 2151, - [BNXT_ULP_CLASS_HID_348d2] = 2152, - [BNXT_ULP_CLASS_HID_1c3e] = 2153, - [BNXT_ULP_CLASS_HID_1323e] = 2154, - [BNXT_ULP_CLASS_HID_2283e] = 2155, - [BNXT_ULP_CLASS_HID_35e3e] = 2156, - [BNXT_ULP_CLASS_HID_5582] = 2157, - [BNXT_ULP_CLASS_HID_14b82] = 2158, - [BNXT_ULP_CLASS_HID_2025e] = 2159, - [BNXT_ULP_CLASS_HID_3385e] = 2160, - [BNXT_ULP_CLASS_HID_2b6a] = 2161, - [BNXT_ULP_CLASS_HID_1416a] = 2162, - [BNXT_ULP_CLASS_HID_21826] = 2163, - [BNXT_ULP_CLASS_HID_30e26] = 2164, - [BNXT_ULP_CLASS_HID_1586] = 2165, - [BNXT_ULP_CLASS_HID_10b86] = 2166, - [BNXT_ULP_CLASS_HID_22186] = 2167, - [BNXT_ULP_CLASS_HID_35786] = 2168, - [BNXT_ULP_CLASS_HID_167a] = 2169, - [BNXT_ULP_CLASS_HID_10c7a] = 2170, - [BNXT_ULP_CLASS_HID_2227a] = 2171, - [BNXT_ULP_CLASS_HID_3587a] = 2172, - [BNXT_ULP_CLASS_HID_2fce] = 2173, - [BNXT_ULP_CLASS_HID_145ce] = 2174, - [BNXT_ULP_CLASS_HID_21c9a] = 2175, - [BNXT_ULP_CLASS_HID_3329a] = 2176, - [BNXT_ULP_CLASS_HID_2556] = 2177, - [BNXT_ULP_CLASS_HID_15b56] = 2178, - [BNXT_ULP_CLASS_HID_21262] = 2179, - [BNXT_ULP_CLASS_HID_30862] = 2180, - [BNXT_ULP_CLASS_HID_4b36] = 2181, - [BNXT_ULP_CLASS_HID_105c2] = 2182, - [BNXT_ULP_CLASS_HID_23bc2] = 2183, - [BNXT_ULP_CLASS_HID_351c2] = 2184, - [BNXT_ULP_CLASS_HID_10a6] = 2185, - [BNXT_ULP_CLASS_HID_106a6] = 2186, - [BNXT_ULP_CLASS_HID_23ca6] = 2187, - [BNXT_ULP_CLASS_HID_352a6] = 2188, - [BNXT_ULP_CLASS_HID_260a] = 2189, - [BNXT_ULP_CLASS_HID_15c0a] = 2190, - [BNXT_ULP_CLASS_HID_216c6] = 2191, - [BNXT_ULP_CLASS_HID_30cc6] = 2192, - [BNXT_ULP_CLASS_HID_3f92] = 2193, - [BNXT_ULP_CLASS_HID_15592] = 2194, - [BNXT_ULP_CLASS_HID_24b92] = 2195, - [BNXT_ULP_CLASS_HID_302ae] = 2196, - [BNXT_ULP_CLASS_HID_4572] = 2197, - [BNXT_ULP_CLASS_HID_11c0e] = 2198, - [BNXT_ULP_CLASS_HID_2320e] = 2199, - [BNXT_ULP_CLASS_HID_3280e] = 2200, - [BNXT_ULP_CLASS_HID_49d6] = 2201, - [BNXT_ULP_CLASS_HID_100e2] = 2202, - [BNXT_ULP_CLASS_HID_236e2] = 2203, - [BNXT_ULP_CLASS_HID_32ce2] = 2204, - [BNXT_ULP_CLASS_HID_2076] = 2205, - [BNXT_ULP_CLASS_HID_15676] = 2206, - [BNXT_ULP_CLASS_HID_21102] = 2207, - [BNXT_ULP_CLASS_HID_30702] = 2208, - [BNXT_ULP_CLASS_HID_39de] = 2209, - [BNXT_ULP_CLASS_HID_12fde] = 2210, - [BNXT_ULP_CLASS_HID_245de] = 2211, - [BNXT_ULP_CLASS_HID_31cea] = 2212, - [BNXT_ULP_CLASS_HID_5fbe] = 2213, - [BNXT_ULP_CLASS_HID_1164a] = 2214, - [BNXT_ULP_CLASS_HID_20c4a] = 2215, - [BNXT_ULP_CLASS_HID_3224a] = 2216, - [BNXT_ULP_CLASS_HID_34be] = 2217, - [BNXT_ULP_CLASS_HID_3a72] = 2218, - [BNXT_ULP_CLASS_HID_1492] = 2219, - [BNXT_ULP_CLASS_HID_4a02] = 2220, - [BNXT_ULP_CLASS_HID_09ea] = 2221, - [BNXT_ULP_CLASS_HID_2912] = 2222, - [BNXT_ULP_CLASS_HID_03b2] = 2223, - [BNXT_ULP_CLASS_HID_5f7e] = 2224, - [BNXT_ULP_CLASS_HID_03a6] = 2225, - [BNXT_ULP_CLASS_HID_23ce] = 2226, - [BNXT_ULP_CLASS_HID_1a6e] = 2227, - [BNXT_ULP_CLASS_HID_593a] = 2228, - [BNXT_ULP_CLASS_HID_4dce] = 2229, - [BNXT_ULP_CLASS_HID_0e02] = 2230, - [BNXT_ULP_CLASS_HID_4796] = 2231, - [BNXT_ULP_CLASS_HID_246e] = 2232, - [BNXT_ULP_CLASS_HID_478a] = 2233, - [BNXT_ULP_CLASS_HID_08fe] = 2234, - [BNXT_ULP_CLASS_HID_5e52] = 2235, - [BNXT_ULP_CLASS_HID_3e2a] = 2236, - [BNXT_ULP_CLASS_HID_5e46] = 2237, - [BNXT_ULP_CLASS_HID_02ba] = 2238, - [BNXT_ULP_CLASS_HID_580e] = 2239, - [BNXT_ULP_CLASS_HID_38e6] = 2240, - [BNXT_ULP_CLASS_HID_5802] = 2241, - [BNXT_ULP_CLASS_HID_1d76] = 2242, - [BNXT_ULP_CLASS_HID_52ca] = 2243, - [BNXT_ULP_CLASS_HID_32a2] = 2244, - [BNXT_ULP_CLASS_HID_34f6] = 2245, - [BNXT_ULP_CLASS_HID_3a3a] = 2246, - [BNXT_ULP_CLASS_HID_5a22] = 2247, - [BNXT_ULP_CLASS_HID_541e] = 2248, - [BNXT_ULP_CLASS_HID_09ca] = 2249, - [BNXT_ULP_CLASS_HID_0216] = 2250, - [BNXT_ULP_CLASS_HID_1f62] = 2251, - [BNXT_ULP_CLASS_HID_1bae] = 2252, - [BNXT_ULP_CLASS_HID_2932] = 2253, - [BNXT_ULP_CLASS_HID_227e] = 2254, - [BNXT_ULP_CLASS_HID_3f4a] = 2255, - [BNXT_ULP_CLASS_HID_3b96] = 2256, - [BNXT_ULP_CLASS_HID_0392] = 2257, - [BNXT_ULP_CLASS_HID_1cde] = 2258, - [BNXT_ULP_CLASS_HID_192a] = 2259, - [BNXT_ULP_CLASS_HID_1276] = 2260, - [BNXT_ULP_CLASS_HID_5f5e] = 2261, - [BNXT_ULP_CLASS_HID_5baa] = 2262, - [BNXT_ULP_CLASS_HID_54f6] = 2263, - [BNXT_ULP_CLASS_HID_51c2] = 2264, - [BNXT_ULP_CLASS_HID_0386] = 2265, - [BNXT_ULP_CLASS_HID_1cd2] = 2266, - [BNXT_ULP_CLASS_HID_191e] = 2267, - [BNXT_ULP_CLASS_HID_126a] = 2268, - [BNXT_ULP_CLASS_HID_23ee] = 2269, - [BNXT_ULP_CLASS_HID_3c3a] = 2270, - [BNXT_ULP_CLASS_HID_3906] = 2271, - [BNXT_ULP_CLASS_HID_3252] = 2272, - [BNXT_ULP_CLASS_HID_1a4e] = 2273, - [BNXT_ULP_CLASS_HID_169a] = 2274, - [BNXT_ULP_CLASS_HID_13e6] = 2275, - [BNXT_ULP_CLASS_HID_4be6] = 2276, - [BNXT_ULP_CLASS_HID_591a] = 2277, - [BNXT_ULP_CLASS_HID_5266] = 2278, - [BNXT_ULP_CLASS_HID_2eb2] = 2279, - [BNXT_ULP_CLASS_HID_2bfe] = 2280, - [BNXT_ULP_CLASS_HID_4dee] = 2281, - [BNXT_ULP_CLASS_HID_463a] = 2282, - [BNXT_ULP_CLASS_HID_4306] = 2283, - [BNXT_ULP_CLASS_HID_5c52] = 2284, - [BNXT_ULP_CLASS_HID_0e22] = 2285, - [BNXT_ULP_CLASS_HID_0b6e] = 2286, - [BNXT_ULP_CLASS_HID_07ba] = 2287, - [BNXT_ULP_CLASS_HID_0086] = 2288, - [BNXT_ULP_CLASS_HID_47b6] = 2289, - [BNXT_ULP_CLASS_HID_4082] = 2290, - [BNXT_ULP_CLASS_HID_5dce] = 2291, - [BNXT_ULP_CLASS_HID_561a] = 2292, - [BNXT_ULP_CLASS_HID_244e] = 2293, - [BNXT_ULP_CLASS_HID_209a] = 2294, - [BNXT_ULP_CLASS_HID_3de6] = 2295, - [BNXT_ULP_CLASS_HID_3632] = 2296, - [BNXT_ULP_CLASS_HID_47aa] = 2297, - [BNXT_ULP_CLASS_HID_40f6] = 2298, - [BNXT_ULP_CLASS_HID_5dc2] = 2299, - [BNXT_ULP_CLASS_HID_560e] = 2300, - [BNXT_ULP_CLASS_HID_08de] = 2301, - [BNXT_ULP_CLASS_HID_052a] = 2302, - [BNXT_ULP_CLASS_HID_1e76] = 2303, - [BNXT_ULP_CLASS_HID_1b42] = 2304, - [BNXT_ULP_CLASS_HID_5e72] = 2305, - [BNXT_ULP_CLASS_HID_5abe] = 2306, - [BNXT_ULP_CLASS_HID_578a] = 2307, - [BNXT_ULP_CLASS_HID_50d6] = 2308, - [BNXT_ULP_CLASS_HID_3e0a] = 2309, - [BNXT_ULP_CLASS_HID_3b56] = 2310, - [BNXT_ULP_CLASS_HID_37a2] = 2311, - [BNXT_ULP_CLASS_HID_30ee] = 2312, - [BNXT_ULP_CLASS_HID_5e66] = 2313, - [BNXT_ULP_CLASS_HID_5ab2] = 2314, - [BNXT_ULP_CLASS_HID_57fe] = 2315, - [BNXT_ULP_CLASS_HID_50ca] = 2316, - [BNXT_ULP_CLASS_HID_029a] = 2317, - [BNXT_ULP_CLASS_HID_1fe6] = 2318, - [BNXT_ULP_CLASS_HID_1832] = 2319, - [BNXT_ULP_CLASS_HID_157e] = 2320, - [BNXT_ULP_CLASS_HID_582e] = 2321, - [BNXT_ULP_CLASS_HID_557a] = 2322, - [BNXT_ULP_CLASS_HID_2e46] = 2323, - [BNXT_ULP_CLASS_HID_2a92] = 2324, - [BNXT_ULP_CLASS_HID_38c6] = 2325, - [BNXT_ULP_CLASS_HID_3512] = 2326, - [BNXT_ULP_CLASS_HID_0e5e] = 2327, - [BNXT_ULP_CLASS_HID_0aaa] = 2328, - [BNXT_ULP_CLASS_HID_5822] = 2329, - [BNXT_ULP_CLASS_HID_556e] = 2330, - [BNXT_ULP_CLASS_HID_51ba] = 2331, - [BNXT_ULP_CLASS_HID_2a86] = 2332, - [BNXT_ULP_CLASS_HID_1d56] = 2333, - [BNXT_ULP_CLASS_HID_19a2] = 2334, - [BNXT_ULP_CLASS_HID_12ee] = 2335, - [BNXT_ULP_CLASS_HID_4aee] = 2336, - [BNXT_ULP_CLASS_HID_52ea] = 2337, - [BNXT_ULP_CLASS_HID_2f36] = 2338, - [BNXT_ULP_CLASS_HID_2802] = 2339, - [BNXT_ULP_CLASS_HID_254e] = 2340, - [BNXT_ULP_CLASS_HID_3282] = 2341, - [BNXT_ULP_CLASS_HID_0fce] = 2342, - [BNXT_ULP_CLASS_HID_081a] = 2343, - [BNXT_ULP_CLASS_HID_0566] = 2344, - [BNXT_ULP_CLASS_HID_34d6] = 2345, - [BNXT_ULP_CLASS_HID_3a1a] = 2346, - [BNXT_ULP_CLASS_HID_5a02] = 2347, - [BNXT_ULP_CLASS_HID_543e] = 2348, - [BNXT_ULP_CLASS_HID_09aa] = 2349, - [BNXT_ULP_CLASS_HID_0276] = 2350, - [BNXT_ULP_CLASS_HID_1f02] = 2351, - [BNXT_ULP_CLASS_HID_1bce] = 2352, - [BNXT_ULP_CLASS_HID_2952] = 2353, - [BNXT_ULP_CLASS_HID_221e] = 2354, - [BNXT_ULP_CLASS_HID_3f2a] = 2355, - [BNXT_ULP_CLASS_HID_3bf6] = 2356, - [BNXT_ULP_CLASS_HID_03f2] = 2357, - [BNXT_ULP_CLASS_HID_1cbe] = 2358, - [BNXT_ULP_CLASS_HID_194a] = 2359, - [BNXT_ULP_CLASS_HID_1216] = 2360, - [BNXT_ULP_CLASS_HID_5f3e] = 2361, - [BNXT_ULP_CLASS_HID_5bca] = 2362, - [BNXT_ULP_CLASS_HID_5496] = 2363, - [BNXT_ULP_CLASS_HID_51a2] = 2364, - [BNXT_ULP_CLASS_HID_03e6] = 2365, - [BNXT_ULP_CLASS_HID_1cb2] = 2366, - [BNXT_ULP_CLASS_HID_197e] = 2367, - [BNXT_ULP_CLASS_HID_120a] = 2368, - [BNXT_ULP_CLASS_HID_238e] = 2369, - [BNXT_ULP_CLASS_HID_3c5a] = 2370, - [BNXT_ULP_CLASS_HID_3966] = 2371, - [BNXT_ULP_CLASS_HID_3232] = 2372, - [BNXT_ULP_CLASS_HID_1a2e] = 2373, - [BNXT_ULP_CLASS_HID_16fa] = 2374, - [BNXT_ULP_CLASS_HID_1386] = 2375, - [BNXT_ULP_CLASS_HID_4b86] = 2376, - [BNXT_ULP_CLASS_HID_597a] = 2377, - [BNXT_ULP_CLASS_HID_5206] = 2378, - [BNXT_ULP_CLASS_HID_2ed2] = 2379, - [BNXT_ULP_CLASS_HID_2b9e] = 2380, - [BNXT_ULP_CLASS_HID_4d8e] = 2381, - [BNXT_ULP_CLASS_HID_465a] = 2382, - [BNXT_ULP_CLASS_HID_4366] = 2383, - [BNXT_ULP_CLASS_HID_5c32] = 2384, - [BNXT_ULP_CLASS_HID_0e42] = 2385, - [BNXT_ULP_CLASS_HID_0b0e] = 2386, - [BNXT_ULP_CLASS_HID_07da] = 2387, - [BNXT_ULP_CLASS_HID_00e6] = 2388, - [BNXT_ULP_CLASS_HID_47d6] = 2389, - [BNXT_ULP_CLASS_HID_40e2] = 2390, - [BNXT_ULP_CLASS_HID_5dae] = 2391, - [BNXT_ULP_CLASS_HID_567a] = 2392, - [BNXT_ULP_CLASS_HID_242e] = 2393, - [BNXT_ULP_CLASS_HID_20fa] = 2394, - [BNXT_ULP_CLASS_HID_3d86] = 2395, - [BNXT_ULP_CLASS_HID_3652] = 2396, - [BNXT_ULP_CLASS_HID_47ca] = 2397, - [BNXT_ULP_CLASS_HID_4096] = 2398, - [BNXT_ULP_CLASS_HID_5da2] = 2399, - [BNXT_ULP_CLASS_HID_566e] = 2400, - [BNXT_ULP_CLASS_HID_08be] = 2401, - [BNXT_ULP_CLASS_HID_054a] = 2402, - [BNXT_ULP_CLASS_HID_1e16] = 2403, - [BNXT_ULP_CLASS_HID_1b22] = 2404, - [BNXT_ULP_CLASS_HID_5e12] = 2405, - [BNXT_ULP_CLASS_HID_5ade] = 2406, - [BNXT_ULP_CLASS_HID_57ea] = 2407, - [BNXT_ULP_CLASS_HID_50b6] = 2408, - [BNXT_ULP_CLASS_HID_3e6a] = 2409, - [BNXT_ULP_CLASS_HID_3b36] = 2410, - [BNXT_ULP_CLASS_HID_37c2] = 2411, - [BNXT_ULP_CLASS_HID_308e] = 2412, - [BNXT_ULP_CLASS_HID_5e06] = 2413, - [BNXT_ULP_CLASS_HID_5ad2] = 2414, - [BNXT_ULP_CLASS_HID_579e] = 2415, - [BNXT_ULP_CLASS_HID_50aa] = 2416, - [BNXT_ULP_CLASS_HID_02fa] = 2417, - [BNXT_ULP_CLASS_HID_1f86] = 2418, - [BNXT_ULP_CLASS_HID_1852] = 2419, - [BNXT_ULP_CLASS_HID_151e] = 2420, - [BNXT_ULP_CLASS_HID_584e] = 2421, - [BNXT_ULP_CLASS_HID_551a] = 2422, - [BNXT_ULP_CLASS_HID_2e26] = 2423, - [BNXT_ULP_CLASS_HID_2af2] = 2424, - [BNXT_ULP_CLASS_HID_38a6] = 2425, - [BNXT_ULP_CLASS_HID_3572] = 2426, - [BNXT_ULP_CLASS_HID_0e3e] = 2427, - [BNXT_ULP_CLASS_HID_0aca] = 2428, - [BNXT_ULP_CLASS_HID_5842] = 2429, - [BNXT_ULP_CLASS_HID_550e] = 2430, - [BNXT_ULP_CLASS_HID_51da] = 2431, - [BNXT_ULP_CLASS_HID_2ae6] = 2432, - [BNXT_ULP_CLASS_HID_1d36] = 2433, - [BNXT_ULP_CLASS_HID_19c2] = 2434, - [BNXT_ULP_CLASS_HID_128e] = 2435, - [BNXT_ULP_CLASS_HID_4a8e] = 2436, - [BNXT_ULP_CLASS_HID_528a] = 2437, - [BNXT_ULP_CLASS_HID_2f56] = 2438, - [BNXT_ULP_CLASS_HID_2862] = 2439, - [BNXT_ULP_CLASS_HID_252e] = 2440, - [BNXT_ULP_CLASS_HID_32e2] = 2441, - [BNXT_ULP_CLASS_HID_0fae] = 2442, - [BNXT_ULP_CLASS_HID_087a] = 2443, - [BNXT_ULP_CLASS_HID_0506] = 2444, - [BNXT_ULP_CLASS_HID_34b6] = 2445, - [BNXT_ULP_CLASS_HID_3a7a] = 2446, - [BNXT_ULP_CLASS_HID_5a62] = 2447, - [BNXT_ULP_CLASS_HID_545e] = 2448, - [BNXT_ULP_CLASS_HID_a73c] = 2449, - [BNXT_ULP_CLASS_HID_a040] = 2450, - [BNXT_ULP_CLASS_HID_1d640] = 2451, - [BNXT_ULP_CLASS_HID_1dd3c] = 2452, - [BNXT_ULP_CLASS_HID_cba0] = 2453, - [BNXT_ULP_CLASS_HID_c4f4] = 2454, - [BNXT_ULP_CLASS_HID_19f38] = 2455, - [BNXT_ULP_CLASS_HID_182f4] = 2456, - [BNXT_ULP_CLASS_HID_b098] = 2457, - [BNXT_ULP_CLASS_HID_8dac] = 2458, - [BNXT_ULP_CLASS_HID_1a3ac] = 2459, - [BNXT_ULP_CLASS_HID_1a698] = 2460, - [BNXT_ULP_CLASS_HID_d50c] = 2461, - [BNXT_ULP_CLASS_HID_ae50] = 2462, - [BNXT_ULP_CLASS_HID_1c450] = 2463, - [BNXT_ULP_CLASS_HID_1cb0c] = 2464, - [BNXT_ULP_CLASS_HID_a1f0] = 2465, - [BNXT_ULP_CLASS_HID_ba04] = 2466, - [BNXT_ULP_CLASS_HID_1d004] = 2467, - [BNXT_ULP_CLASS_HID_1d7f0] = 2468, - [BNXT_ULP_CLASS_HID_c264] = 2469, - [BNXT_ULP_CLASS_HID_dea8] = 2470, - [BNXT_ULP_CLASS_HID_199fc] = 2471, - [BNXT_ULP_CLASS_HID_19ca8] = 2472, - [BNXT_ULP_CLASS_HID_8b5c] = 2473, - [BNXT_ULP_CLASS_HID_8460] = 2474, - [BNXT_ULP_CLASS_HID_1ba60] = 2475, - [BNXT_ULP_CLASS_HID_1a15c] = 2476, - [BNXT_ULP_CLASS_HID_afc0] = 2477, - [BNXT_ULP_CLASS_HID_a814] = 2478, - [BNXT_ULP_CLASS_HID_1de14] = 2479, - [BNXT_ULP_CLASS_HID_1c5c0] = 2480, - [BNXT_ULP_CLASS_HID_8c2c] = 2481, - [BNXT_ULP_CLASS_HID_8970] = 2482, - [BNXT_ULP_CLASS_HID_1bf70] = 2483, - [BNXT_ULP_CLASS_HID_1a22c] = 2484, - [BNXT_ULP_CLASS_HID_d0d0] = 2485, - [BNXT_ULP_CLASS_HID_ade4] = 2486, - [BNXT_ULP_CLASS_HID_1c3e4] = 2487, - [BNXT_ULP_CLASS_HID_1c6d0] = 2488, - [BNXT_ULP_CLASS_HID_9988] = 2489, - [BNXT_ULP_CLASS_HID_92dc] = 2490, - [BNXT_ULP_CLASS_HID_188dc] = 2491, - [BNXT_ULP_CLASS_HID_18f88] = 2492, - [BNXT_ULP_CLASS_HID_ba3c] = 2493, - [BNXT_ULP_CLASS_HID_b740] = 2494, - [BNXT_ULP_CLASS_HID_1ad40] = 2495, - [BNXT_ULP_CLASS_HID_1d03c] = 2496, - [BNXT_ULP_CLASS_HID_86e0] = 2497, - [BNXT_ULP_CLASS_HID_8334] = 2498, - [BNXT_ULP_CLASS_HID_1b934] = 2499, - [BNXT_ULP_CLASS_HID_1bce0] = 2500, - [BNXT_ULP_CLASS_HID_aa94] = 2501, - [BNXT_ULP_CLASS_HID_a7d8] = 2502, - [BNXT_ULP_CLASS_HID_1ddd8] = 2503, - [BNXT_ULP_CLASS_HID_1c094] = 2504, - [BNXT_ULP_CLASS_HID_904c] = 2505, - [BNXT_ULP_CLASS_HID_c84c] = 2506, - [BNXT_ULP_CLASS_HID_18290] = 2507, - [BNXT_ULP_CLASS_HID_1864c] = 2508, - [BNXT_ULP_CLASS_HID_b4f0] = 2509, - [BNXT_ULP_CLASS_HID_b104] = 2510, - [BNXT_ULP_CLASS_HID_1a704] = 2511, - [BNXT_ULP_CLASS_HID_1aaf0] = 2512, - [BNXT_ULP_CLASS_HID_80a4] = 2513, - [BNXT_ULP_CLASS_HID_9de8] = 2514, - [BNXT_ULP_CLASS_HID_1b3e8] = 2515, - [BNXT_ULP_CLASS_HID_1b6a4] = 2516, - [BNXT_ULP_CLASS_HID_a548] = 2517, - [BNXT_ULP_CLASS_HID_a19c] = 2518, - [BNXT_ULP_CLASS_HID_1d79c] = 2519, - [BNXT_ULP_CLASS_HID_1db48] = 2520, - [BNXT_ULP_CLASS_HID_9a98] = 2521, - [BNXT_ULP_CLASS_HID_97ac] = 2522, - [BNXT_ULP_CLASS_HID_18dac] = 2523, - [BNXT_ULP_CLASS_HID_1b098] = 2524, - [BNXT_ULP_CLASS_HID_bf0c] = 2525, - [BNXT_ULP_CLASS_HID_b850] = 2526, - [BNXT_ULP_CLASS_HID_1ae50] = 2527, - [BNXT_ULP_CLASS_HID_1d50c] = 2528, - [BNXT_ULP_CLASS_HID_34f0] = 2529, - [BNXT_ULP_CLASS_HID_3a3c] = 2530, - [BNXT_ULP_CLASS_HID_3740] = 2531, - [BNXT_ULP_CLASS_HID_5ea0] = 2532, - [BNXT_ULP_CLASS_HID_5bf4] = 2533, - [BNXT_ULP_CLASS_HID_0798] = 2534, - [BNXT_ULP_CLASS_HID_00ac] = 2535, - [BNXT_ULP_CLASS_HID_280c] = 2536, - [BNXT_ULP_CLASS_HID_2550] = 2537, - [BNXT_ULP_CLASS_HID_3104] = 2538, - [BNXT_ULP_CLASS_HID_5964] = 2539, - [BNXT_ULP_CLASS_HID_55a8] = 2540, - [BNXT_ULP_CLASS_HID_1e5c] = 2541, - [BNXT_ULP_CLASS_HID_1b60] = 2542, - [BNXT_ULP_CLASS_HID_22c0] = 2543, - [BNXT_ULP_CLASS_HID_3f14] = 2544, - [BNXT_ULP_CLASS_HID_a71c] = 2545, - [BNXT_ULP_CLASS_HID_a8dc] = 2546, - [BNXT_ULP_CLASS_HID_ed9c] = 2547, - [BNXT_ULP_CLASS_HID_ef5c] = 2548, - [BNXT_ULP_CLASS_HID_a060] = 2549, - [BNXT_ULP_CLASS_HID_a520] = 2550, - [BNXT_ULP_CLASS_HID_e6e0] = 2551, - [BNXT_ULP_CLASS_HID_eba0] = 2552, - [BNXT_ULP_CLASS_HID_1d660] = 2553, - [BNXT_ULP_CLASS_HID_1fb20] = 2554, - [BNXT_ULP_CLASS_HID_1dce0] = 2555, - [BNXT_ULP_CLASS_HID_1e1a0] = 2556, - [BNXT_ULP_CLASS_HID_1dd1c] = 2557, - [BNXT_ULP_CLASS_HID_1fedc] = 2558, - [BNXT_ULP_CLASS_HID_1c39c] = 2559, - [BNXT_ULP_CLASS_HID_1e55c] = 2560, - [BNXT_ULP_CLASS_HID_cb80] = 2561, - [BNXT_ULP_CLASS_HID_b194] = 2562, - [BNXT_ULP_CLASS_HID_d354] = 2563, - [BNXT_ULP_CLASS_HID_f414] = 2564, - [BNXT_ULP_CLASS_HID_c4d4] = 2565, - [BNXT_ULP_CLASS_HID_e994] = 2566, - [BNXT_ULP_CLASS_HID_cb54] = 2567, - [BNXT_ULP_CLASS_HID_f158] = 2568, - [BNXT_ULP_CLASS_HID_19f18] = 2569, - [BNXT_ULP_CLASS_HID_1a0d8] = 2570, - [BNXT_ULP_CLASS_HID_1c598] = 2571, - [BNXT_ULP_CLASS_HID_1e758] = 2572, - [BNXT_ULP_CLASS_HID_182d4] = 2573, - [BNXT_ULP_CLASS_HID_1a794] = 2574, - [BNXT_ULP_CLASS_HID_1c954] = 2575, - [BNXT_ULP_CLASS_HID_1ea14] = 2576, - [BNXT_ULP_CLASS_HID_b0b8] = 2577, - [BNXT_ULP_CLASS_HID_b278] = 2578, - [BNXT_ULP_CLASS_HID_f738] = 2579, - [BNXT_ULP_CLASS_HID_f8f8] = 2580, - [BNXT_ULP_CLASS_HID_8d8c] = 2581, - [BNXT_ULP_CLASS_HID_af4c] = 2582, - [BNXT_ULP_CLASS_HID_f00c] = 2583, - [BNXT_ULP_CLASS_HID_f5cc] = 2584, - [BNXT_ULP_CLASS_HID_1a38c] = 2585, - [BNXT_ULP_CLASS_HID_1a54c] = 2586, - [BNXT_ULP_CLASS_HID_1e60c] = 2587, - [BNXT_ULP_CLASS_HID_1ebcc] = 2588, - [BNXT_ULP_CLASS_HID_1a6b8] = 2589, - [BNXT_ULP_CLASS_HID_1a878] = 2590, - [BNXT_ULP_CLASS_HID_1ed38] = 2591, - [BNXT_ULP_CLASS_HID_1eef8] = 2592, - [BNXT_ULP_CLASS_HID_d52c] = 2593, - [BNXT_ULP_CLASS_HID_f6ec] = 2594, - [BNXT_ULP_CLASS_HID_dbac] = 2595, - [BNXT_ULP_CLASS_HID_fd6c] = 2596, - [BNXT_ULP_CLASS_HID_ae70] = 2597, - [BNXT_ULP_CLASS_HID_f330] = 2598, - [BNXT_ULP_CLASS_HID_d4f0] = 2599, - [BNXT_ULP_CLASS_HID_f9b0] = 2600, - [BNXT_ULP_CLASS_HID_1c470] = 2601, - [BNXT_ULP_CLASS_HID_1e930] = 2602, - [BNXT_ULP_CLASS_HID_1caf0] = 2603, - [BNXT_ULP_CLASS_HID_1f084] = 2604, - [BNXT_ULP_CLASS_HID_1cb2c] = 2605, - [BNXT_ULP_CLASS_HID_1b130] = 2606, - [BNXT_ULP_CLASS_HID_1d2f0] = 2607, - [BNXT_ULP_CLASS_HID_1f7b0] = 2608, - [BNXT_ULP_CLASS_HID_a1d0] = 2609, - [BNXT_ULP_CLASS_HID_a290] = 2610, - [BNXT_ULP_CLASS_HID_e450] = 2611, - [BNXT_ULP_CLASS_HID_e910] = 2612, - [BNXT_ULP_CLASS_HID_ba24] = 2613, - [BNXT_ULP_CLASS_HID_bfe4] = 2614, - [BNXT_ULP_CLASS_HID_e0a4] = 2615, - [BNXT_ULP_CLASS_HID_e264] = 2616, - [BNXT_ULP_CLASS_HID_1d024] = 2617, - [BNXT_ULP_CLASS_HID_1f5e4] = 2618, - [BNXT_ULP_CLASS_HID_1d6a4] = 2619, - [BNXT_ULP_CLASS_HID_1f864] = 2620, - [BNXT_ULP_CLASS_HID_1d7d0] = 2621, - [BNXT_ULP_CLASS_HID_1f890] = 2622, - [BNXT_ULP_CLASS_HID_1da50] = 2623, - [BNXT_ULP_CLASS_HID_1ff10] = 2624, - [BNXT_ULP_CLASS_HID_c244] = 2625, - [BNXT_ULP_CLASS_HID_e704] = 2626, - [BNXT_ULP_CLASS_HID_c8c4] = 2627, - [BNXT_ULP_CLASS_HID_ed84] = 2628, - [BNXT_ULP_CLASS_HID_de88] = 2629, - [BNXT_ULP_CLASS_HID_e048] = 2630, - [BNXT_ULP_CLASS_HID_c508] = 2631, - [BNXT_ULP_CLASS_HID_e6c8] = 2632, - [BNXT_ULP_CLASS_HID_199dc] = 2633, - [BNXT_ULP_CLASS_HID_1ba9c] = 2634, - [BNXT_ULP_CLASS_HID_1dc5c] = 2635, - [BNXT_ULP_CLASS_HID_1e11c] = 2636, - [BNXT_ULP_CLASS_HID_19c88] = 2637, - [BNXT_ULP_CLASS_HID_1be48] = 2638, - [BNXT_ULP_CLASS_HID_1c308] = 2639, - [BNXT_ULP_CLASS_HID_1e4c8] = 2640, - [BNXT_ULP_CLASS_HID_8b7c] = 2641, - [BNXT_ULP_CLASS_HID_ac3c] = 2642, - [BNXT_ULP_CLASS_HID_f1fc] = 2643, - [BNXT_ULP_CLASS_HID_f2bc] = 2644, - [BNXT_ULP_CLASS_HID_8440] = 2645, - [BNXT_ULP_CLASS_HID_a900] = 2646, - [BNXT_ULP_CLASS_HID_cac0] = 2647, - [BNXT_ULP_CLASS_HID_ef80] = 2648, - [BNXT_ULP_CLASS_HID_1ba40] = 2649, - [BNXT_ULP_CLASS_HID_1bf00] = 2650, - [BNXT_ULP_CLASS_HID_1e0c0] = 2651, - [BNXT_ULP_CLASS_HID_1e580] = 2652, - [BNXT_ULP_CLASS_HID_1a17c] = 2653, - [BNXT_ULP_CLASS_HID_1a23c] = 2654, - [BNXT_ULP_CLASS_HID_1e7fc] = 2655, - [BNXT_ULP_CLASS_HID_1e8bc] = 2656, - [BNXT_ULP_CLASS_HID_afe0] = 2657, - [BNXT_ULP_CLASS_HID_f0a0] = 2658, - [BNXT_ULP_CLASS_HID_d260] = 2659, - [BNXT_ULP_CLASS_HID_f720] = 2660, - [BNXT_ULP_CLASS_HID_a834] = 2661, - [BNXT_ULP_CLASS_HID_adf4] = 2662, - [BNXT_ULP_CLASS_HID_eeb4] = 2663, - [BNXT_ULP_CLASS_HID_f074] = 2664, - [BNXT_ULP_CLASS_HID_1de34] = 2665, - [BNXT_ULP_CLASS_HID_1e3f4] = 2666, - [BNXT_ULP_CLASS_HID_1c4b4] = 2667, - [BNXT_ULP_CLASS_HID_1e674] = 2668, - [BNXT_ULP_CLASS_HID_1c5e0] = 2669, - [BNXT_ULP_CLASS_HID_1e6a0] = 2670, - [BNXT_ULP_CLASS_HID_1c860] = 2671, - [BNXT_ULP_CLASS_HID_1ed20] = 2672, - [BNXT_ULP_CLASS_HID_8c0c] = 2673, - [BNXT_ULP_CLASS_HID_b1cc] = 2674, - [BNXT_ULP_CLASS_HID_f28c] = 2675, - [BNXT_ULP_CLASS_HID_f44c] = 2676, - [BNXT_ULP_CLASS_HID_8950] = 2677, - [BNXT_ULP_CLASS_HID_aa10] = 2678, - [BNXT_ULP_CLASS_HID_cfd0] = 2679, - [BNXT_ULP_CLASS_HID_f090] = 2680, - [BNXT_ULP_CLASS_HID_1bf50] = 2681, - [BNXT_ULP_CLASS_HID_1a010] = 2682, - [BNXT_ULP_CLASS_HID_1e5d0] = 2683, - [BNXT_ULP_CLASS_HID_1e690] = 2684, - [BNXT_ULP_CLASS_HID_1a20c] = 2685, - [BNXT_ULP_CLASS_HID_1a7cc] = 2686, - [BNXT_ULP_CLASS_HID_1e88c] = 2687, - [BNXT_ULP_CLASS_HID_1ea4c] = 2688, - [BNXT_ULP_CLASS_HID_d0f0] = 2689, - [BNXT_ULP_CLASS_HID_f5b0] = 2690, - [BNXT_ULP_CLASS_HID_d770] = 2691, - [BNXT_ULP_CLASS_HID_f830] = 2692, - [BNXT_ULP_CLASS_HID_adc4] = 2693, - [BNXT_ULP_CLASS_HID_ae84] = 2694, - [BNXT_ULP_CLASS_HID_d044] = 2695, - [BNXT_ULP_CLASS_HID_f504] = 2696, - [BNXT_ULP_CLASS_HID_1c3c4] = 2697, - [BNXT_ULP_CLASS_HID_1e484] = 2698, - [BNXT_ULP_CLASS_HID_1c644] = 2699, - [BNXT_ULP_CLASS_HID_1eb04] = 2700, - [BNXT_ULP_CLASS_HID_1c6f0] = 2701, - [BNXT_ULP_CLASS_HID_1ebb0] = 2702, - [BNXT_ULP_CLASS_HID_1cd70] = 2703, - [BNXT_ULP_CLASS_HID_1f304] = 2704, - [BNXT_ULP_CLASS_HID_99a8] = 2705, - [BNXT_ULP_CLASS_HID_bb68] = 2706, - [BNXT_ULP_CLASS_HID_dc28] = 2707, - [BNXT_ULP_CLASS_HID_e1e8] = 2708, - [BNXT_ULP_CLASS_HID_92fc] = 2709, - [BNXT_ULP_CLASS_HID_b7bc] = 2710, - [BNXT_ULP_CLASS_HID_d97c] = 2711, - [BNXT_ULP_CLASS_HID_fa3c] = 2712, - [BNXT_ULP_CLASS_HID_188fc] = 2713, - [BNXT_ULP_CLASS_HID_1adbc] = 2714, - [BNXT_ULP_CLASS_HID_1cf7c] = 2715, - [BNXT_ULP_CLASS_HID_1f03c] = 2716, - [BNXT_ULP_CLASS_HID_18fa8] = 2717, - [BNXT_ULP_CLASS_HID_1b168] = 2718, - [BNXT_ULP_CLASS_HID_1f228] = 2719, - [BNXT_ULP_CLASS_HID_1f7e8] = 2720, - [BNXT_ULP_CLASS_HID_ba1c] = 2721, - [BNXT_ULP_CLASS_HID_bfdc] = 2722, - [BNXT_ULP_CLASS_HID_e09c] = 2723, - [BNXT_ULP_CLASS_HID_e25c] = 2724, - [BNXT_ULP_CLASS_HID_b760] = 2725, - [BNXT_ULP_CLASS_HID_b820] = 2726, - [BNXT_ULP_CLASS_HID_fde0] = 2727, - [BNXT_ULP_CLASS_HID_fea0] = 2728, - [BNXT_ULP_CLASS_HID_1ad60] = 2729, - [BNXT_ULP_CLASS_HID_1ae20] = 2730, - [BNXT_ULP_CLASS_HID_1d3e0] = 2731, - [BNXT_ULP_CLASS_HID_1f4a0] = 2732, - [BNXT_ULP_CLASS_HID_1d01c] = 2733, - [BNXT_ULP_CLASS_HID_1f5dc] = 2734, - [BNXT_ULP_CLASS_HID_1d69c] = 2735, - [BNXT_ULP_CLASS_HID_1f85c] = 2736, - [BNXT_ULP_CLASS_HID_86c0] = 2737, - [BNXT_ULP_CLASS_HID_ab80] = 2738, - [BNXT_ULP_CLASS_HID_cd40] = 2739, - [BNXT_ULP_CLASS_HID_ee00] = 2740, - [BNXT_ULP_CLASS_HID_8314] = 2741, - [BNXT_ULP_CLASS_HID_a4d4] = 2742, - [BNXT_ULP_CLASS_HID_c994] = 2743, - [BNXT_ULP_CLASS_HID_eb54] = 2744, - [BNXT_ULP_CLASS_HID_1b914] = 2745, - [BNXT_ULP_CLASS_HID_1bad4] = 2746, - [BNXT_ULP_CLASS_HID_1ff94] = 2747, - [BNXT_ULP_CLASS_HID_1e154] = 2748, - [BNXT_ULP_CLASS_HID_1bcc0] = 2749, - [BNXT_ULP_CLASS_HID_1a180] = 2750, - [BNXT_ULP_CLASS_HID_1e340] = 2751, - [BNXT_ULP_CLASS_HID_1e400] = 2752, - [BNXT_ULP_CLASS_HID_aab4] = 2753, - [BNXT_ULP_CLASS_HID_ac74] = 2754, - [BNXT_ULP_CLASS_HID_d134] = 2755, - [BNXT_ULP_CLASS_HID_f2f4] = 2756, - [BNXT_ULP_CLASS_HID_a7f8] = 2757, - [BNXT_ULP_CLASS_HID_a8b8] = 2758, - [BNXT_ULP_CLASS_HID_ea78] = 2759, - [BNXT_ULP_CLASS_HID_ef38] = 2760, - [BNXT_ULP_CLASS_HID_1ddf8] = 2761, - [BNXT_ULP_CLASS_HID_1feb8] = 2762, - [BNXT_ULP_CLASS_HID_1c078] = 2763, - [BNXT_ULP_CLASS_HID_1e538] = 2764, - [BNXT_ULP_CLASS_HID_1c0b4] = 2765, - [BNXT_ULP_CLASS_HID_1e274] = 2766, - [BNXT_ULP_CLASS_HID_1c734] = 2767, - [BNXT_ULP_CLASS_HID_1e8f4] = 2768, - [BNXT_ULP_CLASS_HID_906c] = 2769, - [BNXT_ULP_CLASS_HID_b52c] = 2770, - [BNXT_ULP_CLASS_HID_d6ec] = 2771, - [BNXT_ULP_CLASS_HID_fbac] = 2772, - [BNXT_ULP_CLASS_HID_c86c] = 2773, - [BNXT_ULP_CLASS_HID_ed2c] = 2774, - [BNXT_ULP_CLASS_HID_d330] = 2775, - [BNXT_ULP_CLASS_HID_f4f0] = 2776, - [BNXT_ULP_CLASS_HID_182b0] = 2777, - [BNXT_ULP_CLASS_HID_1a470] = 2778, - [BNXT_ULP_CLASS_HID_1c930] = 2779, - [BNXT_ULP_CLASS_HID_1eaf0] = 2780, - [BNXT_ULP_CLASS_HID_1866c] = 2781, - [BNXT_ULP_CLASS_HID_1ab2c] = 2782, - [BNXT_ULP_CLASS_HID_1ccec] = 2783, - [BNXT_ULP_CLASS_HID_1f1ac] = 2784, - [BNXT_ULP_CLASS_HID_b4d0] = 2785, - [BNXT_ULP_CLASS_HID_b990] = 2786, - [BNXT_ULP_CLASS_HID_fb50] = 2787, - [BNXT_ULP_CLASS_HID_fc10] = 2788, - [BNXT_ULP_CLASS_HID_b124] = 2789, - [BNXT_ULP_CLASS_HID_b2e4] = 2790, - [BNXT_ULP_CLASS_HID_f7a4] = 2791, - [BNXT_ULP_CLASS_HID_f964] = 2792, - [BNXT_ULP_CLASS_HID_1a724] = 2793, - [BNXT_ULP_CLASS_HID_1a8e4] = 2794, - [BNXT_ULP_CLASS_HID_1eda4] = 2795, - [BNXT_ULP_CLASS_HID_1ef64] = 2796, - [BNXT_ULP_CLASS_HID_1aad0] = 2797, - [BNXT_ULP_CLASS_HID_1af90] = 2798, - [BNXT_ULP_CLASS_HID_1d150] = 2799, - [BNXT_ULP_CLASS_HID_1f210] = 2800, - [BNXT_ULP_CLASS_HID_8084] = 2801, - [BNXT_ULP_CLASS_HID_a244] = 2802, - [BNXT_ULP_CLASS_HID_c704] = 2803, - [BNXT_ULP_CLASS_HID_e8c4] = 2804, - [BNXT_ULP_CLASS_HID_9dc8] = 2805, - [BNXT_ULP_CLASS_HID_be88] = 2806, - [BNXT_ULP_CLASS_HID_c048] = 2807, - [BNXT_ULP_CLASS_HID_e508] = 2808, - [BNXT_ULP_CLASS_HID_1b3c8] = 2809, - [BNXT_ULP_CLASS_HID_1b488] = 2810, - [BNXT_ULP_CLASS_HID_1f648] = 2811, - [BNXT_ULP_CLASS_HID_1fb08] = 2812, - [BNXT_ULP_CLASS_HID_1b684] = 2813, - [BNXT_ULP_CLASS_HID_1b844] = 2814, - [BNXT_ULP_CLASS_HID_1fd04] = 2815, - [BNXT_ULP_CLASS_HID_1fec4] = 2816, - [BNXT_ULP_CLASS_HID_a568] = 2817, - [BNXT_ULP_CLASS_HID_a628] = 2818, - [BNXT_ULP_CLASS_HID_ebe8] = 2819, - [BNXT_ULP_CLASS_HID_eca8] = 2820, - [BNXT_ULP_CLASS_HID_a1bc] = 2821, - [BNXT_ULP_CLASS_HID_a37c] = 2822, - [BNXT_ULP_CLASS_HID_e43c] = 2823, - [BNXT_ULP_CLASS_HID_e9fc] = 2824, - [BNXT_ULP_CLASS_HID_1d7bc] = 2825, - [BNXT_ULP_CLASS_HID_1f97c] = 2826, - [BNXT_ULP_CLASS_HID_1da3c] = 2827, - [BNXT_ULP_CLASS_HID_1fffc] = 2828, - [BNXT_ULP_CLASS_HID_1db68] = 2829, - [BNXT_ULP_CLASS_HID_1fc28] = 2830, - [BNXT_ULP_CLASS_HID_1c1e8] = 2831, - [BNXT_ULP_CLASS_HID_1e2a8] = 2832, - [BNXT_ULP_CLASS_HID_9ab8] = 2833, - [BNXT_ULP_CLASS_HID_bc78] = 2834, - [BNXT_ULP_CLASS_HID_c138] = 2835, - [BNXT_ULP_CLASS_HID_e2f8] = 2836, - [BNXT_ULP_CLASS_HID_978c] = 2837, - [BNXT_ULP_CLASS_HID_b94c] = 2838, - [BNXT_ULP_CLASS_HID_da0c] = 2839, - [BNXT_ULP_CLASS_HID_ffcc] = 2840, - [BNXT_ULP_CLASS_HID_18d8c] = 2841, - [BNXT_ULP_CLASS_HID_1af4c] = 2842, - [BNXT_ULP_CLASS_HID_1f00c] = 2843, - [BNXT_ULP_CLASS_HID_1f5cc] = 2844, - [BNXT_ULP_CLASS_HID_1b0b8] = 2845, - [BNXT_ULP_CLASS_HID_1b278] = 2846, - [BNXT_ULP_CLASS_HID_1f738] = 2847, - [BNXT_ULP_CLASS_HID_1f8f8] = 2848, - [BNXT_ULP_CLASS_HID_bf2c] = 2849, - [BNXT_ULP_CLASS_HID_a0ec] = 2850, - [BNXT_ULP_CLASS_HID_e5ac] = 2851, - [BNXT_ULP_CLASS_HID_e76c] = 2852, - [BNXT_ULP_CLASS_HID_b870] = 2853, - [BNXT_ULP_CLASS_HID_bd30] = 2854, - [BNXT_ULP_CLASS_HID_fef0] = 2855, - [BNXT_ULP_CLASS_HID_e3b0] = 2856, - [BNXT_ULP_CLASS_HID_1ae70] = 2857, - [BNXT_ULP_CLASS_HID_1f330] = 2858, - [BNXT_ULP_CLASS_HID_1d4f0] = 2859, - [BNXT_ULP_CLASS_HID_1f9b0] = 2860, - [BNXT_ULP_CLASS_HID_1d52c] = 2861, - [BNXT_ULP_CLASS_HID_1f6ec] = 2862, - [BNXT_ULP_CLASS_HID_1dbac] = 2863, - [BNXT_ULP_CLASS_HID_1fd6c] = 2864, - [BNXT_ULP_CLASS_HID_34d0] = 2865, - [BNXT_ULP_CLASS_HID_3a1c] = 2866, - [BNXT_ULP_CLASS_HID_3760] = 2867, - [BNXT_ULP_CLASS_HID_5e80] = 2868, - [BNXT_ULP_CLASS_HID_5bd4] = 2869, - [BNXT_ULP_CLASS_HID_07b8] = 2870, - [BNXT_ULP_CLASS_HID_008c] = 2871, - [BNXT_ULP_CLASS_HID_282c] = 2872, - [BNXT_ULP_CLASS_HID_2570] = 2873, - [BNXT_ULP_CLASS_HID_3124] = 2874, - [BNXT_ULP_CLASS_HID_5944] = 2875, - [BNXT_ULP_CLASS_HID_5588] = 2876, - [BNXT_ULP_CLASS_HID_1e7c] = 2877, - [BNXT_ULP_CLASS_HID_1b40] = 2878, - [BNXT_ULP_CLASS_HID_22e0] = 2879, - [BNXT_ULP_CLASS_HID_3f34] = 2880, - [BNXT_ULP_CLASS_HID_a77c] = 2881, - [BNXT_ULP_CLASS_HID_a8bc] = 2882, - [BNXT_ULP_CLASS_HID_edfc] = 2883, - [BNXT_ULP_CLASS_HID_ef3c] = 2884, - [BNXT_ULP_CLASS_HID_a000] = 2885, - [BNXT_ULP_CLASS_HID_a540] = 2886, - [BNXT_ULP_CLASS_HID_e680] = 2887, - [BNXT_ULP_CLASS_HID_ebc0] = 2888, - [BNXT_ULP_CLASS_HID_1d600] = 2889, - [BNXT_ULP_CLASS_HID_1fb40] = 2890, - [BNXT_ULP_CLASS_HID_1dc80] = 2891, - [BNXT_ULP_CLASS_HID_1e1c0] = 2892, - [BNXT_ULP_CLASS_HID_1dd7c] = 2893, - [BNXT_ULP_CLASS_HID_1febc] = 2894, - [BNXT_ULP_CLASS_HID_1c3fc] = 2895, - [BNXT_ULP_CLASS_HID_1e53c] = 2896, - [BNXT_ULP_CLASS_HID_cbe0] = 2897, - [BNXT_ULP_CLASS_HID_b1f4] = 2898, - [BNXT_ULP_CLASS_HID_d334] = 2899, - [BNXT_ULP_CLASS_HID_f474] = 2900, - [BNXT_ULP_CLASS_HID_c4b4] = 2901, - [BNXT_ULP_CLASS_HID_e9f4] = 2902, - [BNXT_ULP_CLASS_HID_cb34] = 2903, - [BNXT_ULP_CLASS_HID_f138] = 2904, - [BNXT_ULP_CLASS_HID_19f78] = 2905, - [BNXT_ULP_CLASS_HID_1a0b8] = 2906, - [BNXT_ULP_CLASS_HID_1c5f8] = 2907, - [BNXT_ULP_CLASS_HID_1e738] = 2908, - [BNXT_ULP_CLASS_HID_182b4] = 2909, - [BNXT_ULP_CLASS_HID_1a7f4] = 2910, - [BNXT_ULP_CLASS_HID_1c934] = 2911, - [BNXT_ULP_CLASS_HID_1ea74] = 2912, - [BNXT_ULP_CLASS_HID_b0d8] = 2913, - [BNXT_ULP_CLASS_HID_b218] = 2914, - [BNXT_ULP_CLASS_HID_f758] = 2915, - [BNXT_ULP_CLASS_HID_f898] = 2916, - [BNXT_ULP_CLASS_HID_8dec] = 2917, - [BNXT_ULP_CLASS_HID_af2c] = 2918, - [BNXT_ULP_CLASS_HID_f06c] = 2919, - [BNXT_ULP_CLASS_HID_f5ac] = 2920, - [BNXT_ULP_CLASS_HID_1a3ec] = 2921, - [BNXT_ULP_CLASS_HID_1a52c] = 2922, - [BNXT_ULP_CLASS_HID_1e66c] = 2923, - [BNXT_ULP_CLASS_HID_1ebac] = 2924, - [BNXT_ULP_CLASS_HID_1a6d8] = 2925, - [BNXT_ULP_CLASS_HID_1a818] = 2926, - [BNXT_ULP_CLASS_HID_1ed58] = 2927, - [BNXT_ULP_CLASS_HID_1ee98] = 2928, - [BNXT_ULP_CLASS_HID_d54c] = 2929, - [BNXT_ULP_CLASS_HID_f68c] = 2930, - [BNXT_ULP_CLASS_HID_dbcc] = 2931, - [BNXT_ULP_CLASS_HID_fd0c] = 2932, - [BNXT_ULP_CLASS_HID_ae10] = 2933, - [BNXT_ULP_CLASS_HID_f350] = 2934, - [BNXT_ULP_CLASS_HID_d490] = 2935, - [BNXT_ULP_CLASS_HID_f9d0] = 2936, - [BNXT_ULP_CLASS_HID_1c410] = 2937, - [BNXT_ULP_CLASS_HID_1e950] = 2938, - [BNXT_ULP_CLASS_HID_1ca90] = 2939, - [BNXT_ULP_CLASS_HID_1f0e4] = 2940, - [BNXT_ULP_CLASS_HID_1cb4c] = 2941, - [BNXT_ULP_CLASS_HID_1b150] = 2942, - [BNXT_ULP_CLASS_HID_1d290] = 2943, - [BNXT_ULP_CLASS_HID_1f7d0] = 2944, - [BNXT_ULP_CLASS_HID_a1b0] = 2945, - [BNXT_ULP_CLASS_HID_a2f0] = 2946, - [BNXT_ULP_CLASS_HID_e430] = 2947, - [BNXT_ULP_CLASS_HID_e970] = 2948, - [BNXT_ULP_CLASS_HID_ba44] = 2949, - [BNXT_ULP_CLASS_HID_bf84] = 2950, - [BNXT_ULP_CLASS_HID_e0c4] = 2951, - [BNXT_ULP_CLASS_HID_e204] = 2952, - [BNXT_ULP_CLASS_HID_1d044] = 2953, - [BNXT_ULP_CLASS_HID_1f584] = 2954, - [BNXT_ULP_CLASS_HID_1d6c4] = 2955, - [BNXT_ULP_CLASS_HID_1f804] = 2956, - [BNXT_ULP_CLASS_HID_1d7b0] = 2957, - [BNXT_ULP_CLASS_HID_1f8f0] = 2958, - [BNXT_ULP_CLASS_HID_1da30] = 2959, - [BNXT_ULP_CLASS_HID_1ff70] = 2960, - [BNXT_ULP_CLASS_HID_c224] = 2961, - [BNXT_ULP_CLASS_HID_e764] = 2962, - [BNXT_ULP_CLASS_HID_c8a4] = 2963, - [BNXT_ULP_CLASS_HID_ede4] = 2964, - [BNXT_ULP_CLASS_HID_dee8] = 2965, - [BNXT_ULP_CLASS_HID_e028] = 2966, - [BNXT_ULP_CLASS_HID_c568] = 2967, - [BNXT_ULP_CLASS_HID_e6a8] = 2968, - [BNXT_ULP_CLASS_HID_199bc] = 2969, - [BNXT_ULP_CLASS_HID_1bafc] = 2970, - [BNXT_ULP_CLASS_HID_1dc3c] = 2971, - [BNXT_ULP_CLASS_HID_1e17c] = 2972, - [BNXT_ULP_CLASS_HID_19ce8] = 2973, - [BNXT_ULP_CLASS_HID_1be28] = 2974, - [BNXT_ULP_CLASS_HID_1c368] = 2975, - [BNXT_ULP_CLASS_HID_1e4a8] = 2976, - [BNXT_ULP_CLASS_HID_8b1c] = 2977, - [BNXT_ULP_CLASS_HID_ac5c] = 2978, - [BNXT_ULP_CLASS_HID_f19c] = 2979, - [BNXT_ULP_CLASS_HID_f2dc] = 2980, - [BNXT_ULP_CLASS_HID_8420] = 2981, - [BNXT_ULP_CLASS_HID_a960] = 2982, - [BNXT_ULP_CLASS_HID_caa0] = 2983, - [BNXT_ULP_CLASS_HID_efe0] = 2984, - [BNXT_ULP_CLASS_HID_1ba20] = 2985, - [BNXT_ULP_CLASS_HID_1bf60] = 2986, - [BNXT_ULP_CLASS_HID_1e0a0] = 2987, - [BNXT_ULP_CLASS_HID_1e5e0] = 2988, - [BNXT_ULP_CLASS_HID_1a11c] = 2989, - [BNXT_ULP_CLASS_HID_1a25c] = 2990, - [BNXT_ULP_CLASS_HID_1e79c] = 2991, - [BNXT_ULP_CLASS_HID_1e8dc] = 2992, - [BNXT_ULP_CLASS_HID_af80] = 2993, - [BNXT_ULP_CLASS_HID_f0c0] = 2994, - [BNXT_ULP_CLASS_HID_d200] = 2995, - [BNXT_ULP_CLASS_HID_f740] = 2996, - [BNXT_ULP_CLASS_HID_a854] = 2997, - [BNXT_ULP_CLASS_HID_ad94] = 2998, - [BNXT_ULP_CLASS_HID_eed4] = 2999, - [BNXT_ULP_CLASS_HID_f014] = 3000, - [BNXT_ULP_CLASS_HID_1de54] = 3001, - [BNXT_ULP_CLASS_HID_1e394] = 3002, - [BNXT_ULP_CLASS_HID_1c4d4] = 3003, - [BNXT_ULP_CLASS_HID_1e614] = 3004, - [BNXT_ULP_CLASS_HID_1c580] = 3005, - [BNXT_ULP_CLASS_HID_1e6c0] = 3006, - [BNXT_ULP_CLASS_HID_1c800] = 3007, - [BNXT_ULP_CLASS_HID_1ed40] = 3008, - [BNXT_ULP_CLASS_HID_8c6c] = 3009, - [BNXT_ULP_CLASS_HID_b1ac] = 3010, - [BNXT_ULP_CLASS_HID_f2ec] = 3011, - [BNXT_ULP_CLASS_HID_f42c] = 3012, - [BNXT_ULP_CLASS_HID_8930] = 3013, - [BNXT_ULP_CLASS_HID_aa70] = 3014, - [BNXT_ULP_CLASS_HID_cfb0] = 3015, - [BNXT_ULP_CLASS_HID_f0f0] = 3016, - [BNXT_ULP_CLASS_HID_1bf30] = 3017, - [BNXT_ULP_CLASS_HID_1a070] = 3018, - [BNXT_ULP_CLASS_HID_1e5b0] = 3019, - [BNXT_ULP_CLASS_HID_1e6f0] = 3020, - [BNXT_ULP_CLASS_HID_1a26c] = 3021, - [BNXT_ULP_CLASS_HID_1a7ac] = 3022, - [BNXT_ULP_CLASS_HID_1e8ec] = 3023, - [BNXT_ULP_CLASS_HID_1ea2c] = 3024, - [BNXT_ULP_CLASS_HID_d090] = 3025, - [BNXT_ULP_CLASS_HID_f5d0] = 3026, - [BNXT_ULP_CLASS_HID_d710] = 3027, - [BNXT_ULP_CLASS_HID_f850] = 3028, - [BNXT_ULP_CLASS_HID_ada4] = 3029, - [BNXT_ULP_CLASS_HID_aee4] = 3030, - [BNXT_ULP_CLASS_HID_d024] = 3031, - [BNXT_ULP_CLASS_HID_f564] = 3032, - [BNXT_ULP_CLASS_HID_1c3a4] = 3033, - [BNXT_ULP_CLASS_HID_1e4e4] = 3034, - [BNXT_ULP_CLASS_HID_1c624] = 3035, - [BNXT_ULP_CLASS_HID_1eb64] = 3036, - [BNXT_ULP_CLASS_HID_1c690] = 3037, - [BNXT_ULP_CLASS_HID_1ebd0] = 3038, - [BNXT_ULP_CLASS_HID_1cd10] = 3039, - [BNXT_ULP_CLASS_HID_1f364] = 3040, - [BNXT_ULP_CLASS_HID_99c8] = 3041, - [BNXT_ULP_CLASS_HID_bb08] = 3042, - [BNXT_ULP_CLASS_HID_dc48] = 3043, - [BNXT_ULP_CLASS_HID_e188] = 3044, - [BNXT_ULP_CLASS_HID_929c] = 3045, - [BNXT_ULP_CLASS_HID_b7dc] = 3046, - [BNXT_ULP_CLASS_HID_d91c] = 3047, - [BNXT_ULP_CLASS_HID_fa5c] = 3048, - [BNXT_ULP_CLASS_HID_1889c] = 3049, - [BNXT_ULP_CLASS_HID_1addc] = 3050, - [BNXT_ULP_CLASS_HID_1cf1c] = 3051, - [BNXT_ULP_CLASS_HID_1f05c] = 3052, - [BNXT_ULP_CLASS_HID_18fc8] = 3053, - [BNXT_ULP_CLASS_HID_1b108] = 3054, - [BNXT_ULP_CLASS_HID_1f248] = 3055, - [BNXT_ULP_CLASS_HID_1f788] = 3056, - [BNXT_ULP_CLASS_HID_ba7c] = 3057, - [BNXT_ULP_CLASS_HID_bfbc] = 3058, - [BNXT_ULP_CLASS_HID_e0fc] = 3059, - [BNXT_ULP_CLASS_HID_e23c] = 3060, - [BNXT_ULP_CLASS_HID_b700] = 3061, - [BNXT_ULP_CLASS_HID_b840] = 3062, - [BNXT_ULP_CLASS_HID_fd80] = 3063, - [BNXT_ULP_CLASS_HID_fec0] = 3064, - [BNXT_ULP_CLASS_HID_1ad00] = 3065, - [BNXT_ULP_CLASS_HID_1ae40] = 3066, - [BNXT_ULP_CLASS_HID_1d380] = 3067, - [BNXT_ULP_CLASS_HID_1f4c0] = 3068, - [BNXT_ULP_CLASS_HID_1d07c] = 3069, - [BNXT_ULP_CLASS_HID_1f5bc] = 3070, - [BNXT_ULP_CLASS_HID_1d6fc] = 3071, - [BNXT_ULP_CLASS_HID_1f83c] = 3072, - [BNXT_ULP_CLASS_HID_86a0] = 3073, - [BNXT_ULP_CLASS_HID_abe0] = 3074, - [BNXT_ULP_CLASS_HID_cd20] = 3075, - [BNXT_ULP_CLASS_HID_ee60] = 3076, - [BNXT_ULP_CLASS_HID_8374] = 3077, - [BNXT_ULP_CLASS_HID_a4b4] = 3078, - [BNXT_ULP_CLASS_HID_c9f4] = 3079, - [BNXT_ULP_CLASS_HID_eb34] = 3080, - [BNXT_ULP_CLASS_HID_1b974] = 3081, - [BNXT_ULP_CLASS_HID_1bab4] = 3082, - [BNXT_ULP_CLASS_HID_1fff4] = 3083, - [BNXT_ULP_CLASS_HID_1e134] = 3084, - [BNXT_ULP_CLASS_HID_1bca0] = 3085, - [BNXT_ULP_CLASS_HID_1a1e0] = 3086, - [BNXT_ULP_CLASS_HID_1e320] = 3087, - [BNXT_ULP_CLASS_HID_1e460] = 3088, - [BNXT_ULP_CLASS_HID_aad4] = 3089, - [BNXT_ULP_CLASS_HID_ac14] = 3090, - [BNXT_ULP_CLASS_HID_d154] = 3091, - [BNXT_ULP_CLASS_HID_f294] = 3092, - [BNXT_ULP_CLASS_HID_a798] = 3093, - [BNXT_ULP_CLASS_HID_a8d8] = 3094, - [BNXT_ULP_CLASS_HID_ea18] = 3095, - [BNXT_ULP_CLASS_HID_ef58] = 3096, - [BNXT_ULP_CLASS_HID_1dd98] = 3097, - [BNXT_ULP_CLASS_HID_1fed8] = 3098, - [BNXT_ULP_CLASS_HID_1c018] = 3099, - [BNXT_ULP_CLASS_HID_1e558] = 3100, - [BNXT_ULP_CLASS_HID_1c0d4] = 3101, - [BNXT_ULP_CLASS_HID_1e214] = 3102, - [BNXT_ULP_CLASS_HID_1c754] = 3103, - [BNXT_ULP_CLASS_HID_1e894] = 3104, - [BNXT_ULP_CLASS_HID_900c] = 3105, - [BNXT_ULP_CLASS_HID_b54c] = 3106, - [BNXT_ULP_CLASS_HID_d68c] = 3107, - [BNXT_ULP_CLASS_HID_fbcc] = 3108, - [BNXT_ULP_CLASS_HID_c80c] = 3109, - [BNXT_ULP_CLASS_HID_ed4c] = 3110, - [BNXT_ULP_CLASS_HID_d350] = 3111, - [BNXT_ULP_CLASS_HID_f490] = 3112, - [BNXT_ULP_CLASS_HID_182d0] = 3113, - [BNXT_ULP_CLASS_HID_1a410] = 3114, - [BNXT_ULP_CLASS_HID_1c950] = 3115, - [BNXT_ULP_CLASS_HID_1ea90] = 3116, - [BNXT_ULP_CLASS_HID_1860c] = 3117, - [BNXT_ULP_CLASS_HID_1ab4c] = 3118, - [BNXT_ULP_CLASS_HID_1cc8c] = 3119, - [BNXT_ULP_CLASS_HID_1f1cc] = 3120, - [BNXT_ULP_CLASS_HID_b4b0] = 3121, - [BNXT_ULP_CLASS_HID_b9f0] = 3122, - [BNXT_ULP_CLASS_HID_fb30] = 3123, - [BNXT_ULP_CLASS_HID_fc70] = 3124, - [BNXT_ULP_CLASS_HID_b144] = 3125, - [BNXT_ULP_CLASS_HID_b284] = 3126, - [BNXT_ULP_CLASS_HID_f7c4] = 3127, - [BNXT_ULP_CLASS_HID_f904] = 3128, - [BNXT_ULP_CLASS_HID_1a744] = 3129, - [BNXT_ULP_CLASS_HID_1a884] = 3130, - [BNXT_ULP_CLASS_HID_1edc4] = 3131, - [BNXT_ULP_CLASS_HID_1ef04] = 3132, - [BNXT_ULP_CLASS_HID_1aab0] = 3133, - [BNXT_ULP_CLASS_HID_1aff0] = 3134, - [BNXT_ULP_CLASS_HID_1d130] = 3135, - [BNXT_ULP_CLASS_HID_1f270] = 3136, - [BNXT_ULP_CLASS_HID_80e4] = 3137, - [BNXT_ULP_CLASS_HID_a224] = 3138, - [BNXT_ULP_CLASS_HID_c764] = 3139, - [BNXT_ULP_CLASS_HID_e8a4] = 3140, - [BNXT_ULP_CLASS_HID_9da8] = 3141, - [BNXT_ULP_CLASS_HID_bee8] = 3142, - [BNXT_ULP_CLASS_HID_c028] = 3143, - [BNXT_ULP_CLASS_HID_e568] = 3144, - [BNXT_ULP_CLASS_HID_1b3a8] = 3145, - [BNXT_ULP_CLASS_HID_1b4e8] = 3146, - [BNXT_ULP_CLASS_HID_1f628] = 3147, - [BNXT_ULP_CLASS_HID_1fb68] = 3148, - [BNXT_ULP_CLASS_HID_1b6e4] = 3149, - [BNXT_ULP_CLASS_HID_1b824] = 3150, - [BNXT_ULP_CLASS_HID_1fd64] = 3151, - [BNXT_ULP_CLASS_HID_1fea4] = 3152, - [BNXT_ULP_CLASS_HID_a508] = 3153, - [BNXT_ULP_CLASS_HID_a648] = 3154, - [BNXT_ULP_CLASS_HID_eb88] = 3155, - [BNXT_ULP_CLASS_HID_ecc8] = 3156, - [BNXT_ULP_CLASS_HID_a1dc] = 3157, - [BNXT_ULP_CLASS_HID_a31c] = 3158, - [BNXT_ULP_CLASS_HID_e45c] = 3159, - [BNXT_ULP_CLASS_HID_e99c] = 3160, - [BNXT_ULP_CLASS_HID_1d7dc] = 3161, - [BNXT_ULP_CLASS_HID_1f91c] = 3162, - [BNXT_ULP_CLASS_HID_1da5c] = 3163, - [BNXT_ULP_CLASS_HID_1ff9c] = 3164, - [BNXT_ULP_CLASS_HID_1db08] = 3165, - [BNXT_ULP_CLASS_HID_1fc48] = 3166, - [BNXT_ULP_CLASS_HID_1c188] = 3167, - [BNXT_ULP_CLASS_HID_1e2c8] = 3168, - [BNXT_ULP_CLASS_HID_9ad8] = 3169, - [BNXT_ULP_CLASS_HID_bc18] = 3170, - [BNXT_ULP_CLASS_HID_c158] = 3171, - [BNXT_ULP_CLASS_HID_e298] = 3172, - [BNXT_ULP_CLASS_HID_97ec] = 3173, - [BNXT_ULP_CLASS_HID_b92c] = 3174, - [BNXT_ULP_CLASS_HID_da6c] = 3175, - [BNXT_ULP_CLASS_HID_ffac] = 3176, - [BNXT_ULP_CLASS_HID_18dec] = 3177, - [BNXT_ULP_CLASS_HID_1af2c] = 3178, - [BNXT_ULP_CLASS_HID_1f06c] = 3179, - [BNXT_ULP_CLASS_HID_1f5ac] = 3180, - [BNXT_ULP_CLASS_HID_1b0d8] = 3181, - [BNXT_ULP_CLASS_HID_1b218] = 3182, - [BNXT_ULP_CLASS_HID_1f758] = 3183, - [BNXT_ULP_CLASS_HID_1f898] = 3184, - [BNXT_ULP_CLASS_HID_bf4c] = 3185, - [BNXT_ULP_CLASS_HID_a08c] = 3186, - [BNXT_ULP_CLASS_HID_e5cc] = 3187, - [BNXT_ULP_CLASS_HID_e70c] = 3188, - [BNXT_ULP_CLASS_HID_b810] = 3189, - [BNXT_ULP_CLASS_HID_bd50] = 3190, - [BNXT_ULP_CLASS_HID_fe90] = 3191, - [BNXT_ULP_CLASS_HID_e3d0] = 3192, - [BNXT_ULP_CLASS_HID_1ae10] = 3193, - [BNXT_ULP_CLASS_HID_1f350] = 3194, - [BNXT_ULP_CLASS_HID_1d490] = 3195, - [BNXT_ULP_CLASS_HID_1f9d0] = 3196, - [BNXT_ULP_CLASS_HID_1d54c] = 3197, - [BNXT_ULP_CLASS_HID_1f68c] = 3198, - [BNXT_ULP_CLASS_HID_1dbcc] = 3199, - [BNXT_ULP_CLASS_HID_1fd0c] = 3200, - [BNXT_ULP_CLASS_HID_34b0] = 3201, - [BNXT_ULP_CLASS_HID_3a7c] = 3202, - [BNXT_ULP_CLASS_HID_3700] = 3203, - [BNXT_ULP_CLASS_HID_5ee0] = 3204, - [BNXT_ULP_CLASS_HID_5bb4] = 3205, - [BNXT_ULP_CLASS_HID_07d8] = 3206, - [BNXT_ULP_CLASS_HID_00ec] = 3207, - [BNXT_ULP_CLASS_HID_284c] = 3208, - [BNXT_ULP_CLASS_HID_2510] = 3209, - [BNXT_ULP_CLASS_HID_3144] = 3210, - [BNXT_ULP_CLASS_HID_5924] = 3211, - [BNXT_ULP_CLASS_HID_55e8] = 3212, - [BNXT_ULP_CLASS_HID_1e1c] = 3213, - [BNXT_ULP_CLASS_HID_1b20] = 3214, - [BNXT_ULP_CLASS_HID_2280] = 3215, - [BNXT_ULP_CLASS_HID_3f54] = 3216, - [BNXT_ULP_CLASS_HID_24604] = 3217, - [BNXT_ULP_CLASS_HID_255d4] = 3218, - [BNXT_ULP_CLASS_HID_22e08] = 3219, - [BNXT_ULP_CLASS_HID_24378] = 3220, - [BNXT_ULP_CLASS_HID_20fcc] = 3221, - [BNXT_ULP_CLASS_HID_21a9c] = 3222, - [BNXT_ULP_CLASS_HID_217d0] = 3223, - [BNXT_ULP_CLASS_HID_20800] = 3224, - [BNXT_ULP_CLASS_HID_253a0] = 3225, - [BNXT_ULP_CLASS_HID_23f70] = 3226, - [BNXT_ULP_CLASS_HID_23ba4] = 3227, - [BNXT_ULP_CLASS_HID_22c94] = 3228, - [BNXT_ULP_CLASS_HID_21968] = 3229, - [BNXT_ULP_CLASS_HID_243c4] = 3230, - [BNXT_ULP_CLASS_HID_25c38] = 3231, - [BNXT_ULP_CLASS_HID_2125c] = 3232, - [BNXT_ULP_CLASS_HID_240c8] = 3233, - [BNXT_ULP_CLASS_HID_22f98] = 3234, - [BNXT_ULP_CLASS_HID_228cc] = 3235, - [BNXT_ULP_CLASS_HID_25d3c] = 3236, - [BNXT_ULP_CLASS_HID_20990] = 3237, - [BNXT_ULP_CLASS_HID_214a0] = 3238, - [BNXT_ULP_CLASS_HID_21194] = 3239, - [BNXT_ULP_CLASS_HID_202c4] = 3240, - [BNXT_ULP_CLASS_HID_22a64] = 3241, - [BNXT_ULP_CLASS_HID_23934] = 3242, - [BNXT_ULP_CLASS_HID_23268] = 3243, - [BNXT_ULP_CLASS_HID_22758] = 3244, - [BNXT_ULP_CLASS_HID_2132c] = 3245, - [BNXT_ULP_CLASS_HID_25d88] = 3246, - [BNXT_ULP_CLASS_HID_256fc] = 3247, - [BNXT_ULP_CLASS_HID_24b2c] = 3248, - [BNXT_ULP_CLASS_HID_22f14] = 3249, - [BNXT_ULP_CLASS_HID_23a24] = 3250, - [BNXT_ULP_CLASS_HID_23718] = 3251, - [BNXT_ULP_CLASS_HID_22848] = 3252, - [BNXT_ULP_CLASS_HID_214dc] = 3253, - [BNXT_ULP_CLASS_HID_25eb8] = 3254, - [BNXT_ULP_CLASS_HID_25bec] = 3255, - [BNXT_ULP_CLASS_HID_21110] = 3256, - [BNXT_ULP_CLASS_HID_238b0] = 3257, - [BNXT_ULP_CLASS_HID_20440] = 3258, - [BNXT_ULP_CLASS_HID_200b4] = 3259, - [BNXT_ULP_CLASS_HID_235e4] = 3260, - [BNXT_ULP_CLASS_HID_25d04] = 3261, - [BNXT_ULP_CLASS_HID_228d4] = 3262, - [BNXT_ULP_CLASS_HID_22508] = 3263, - [BNXT_ULP_CLASS_HID_25678] = 3264, - [BNXT_ULP_CLASS_HID_229d8] = 3265, - [BNXT_ULP_CLASS_HID_234e8] = 3266, - [BNXT_ULP_CLASS_HID_231dc] = 3267, - [BNXT_ULP_CLASS_HID_2220c] = 3268, - [BNXT_ULP_CLASS_HID_24dac] = 3269, - [BNXT_ULP_CLASS_HID_2597c] = 3270, - [BNXT_ULP_CLASS_HID_255b0] = 3271, - [BNXT_ULP_CLASS_HID_246e0] = 3272, - [BNXT_ULP_CLASS_HID_23374] = 3273, - [BNXT_ULP_CLASS_HID_21e04] = 3274, - [BNXT_ULP_CLASS_HID_21b78] = 3275, - [BNXT_ULP_CLASS_HID_20fa8] = 3276, - [BNXT_ULP_CLASS_HID_257c8] = 3277, - [BNXT_ULP_CLASS_HID_22298] = 3278, - [BNXT_ULP_CLASS_HID_23fcc] = 3279, - [BNXT_ULP_CLASS_HID_2503c] = 3280, - [BNXT_ULP_CLASS_HID_2239c] = 3281, - [BNXT_ULP_CLASS_HID_20eac] = 3282, - [BNXT_ULP_CLASS_HID_20be0] = 3283, - [BNXT_ULP_CLASS_HID_23cd0] = 3284, - [BNXT_ULP_CLASS_HID_24470] = 3285, - [BNXT_ULP_CLASS_HID_25300] = 3286, - [BNXT_ULP_CLASS_HID_22c74] = 3287, - [BNXT_ULP_CLASS_HID_240a4] = 3288, - [BNXT_ULP_CLASS_HID_23da0] = 3289, - [BNXT_ULP_CLASS_HID_20970] = 3290, - [BNXT_ULP_CLASS_HID_205a4] = 3291, - [BNXT_ULP_CLASS_HID_23694] = 3292, - [BNXT_ULP_CLASS_HID_25e34] = 3293, - [BNXT_ULP_CLASS_HID_22dc4] = 3294, - [BNXT_ULP_CLASS_HID_22638] = 3295, - [BNXT_ULP_CLASS_HID_25b68] = 3296, - [BNXT_ULP_CLASS_HID_34c8] = 3297, - [BNXT_ULP_CLASS_HID_3a04] = 3298, - [BNXT_ULP_CLASS_HID_09d4] = 3299, - [BNXT_ULP_CLASS_HID_5e98] = 3300, - [BNXT_ULP_CLASS_HID_2da8] = 3301, - [BNXT_ULP_CLASS_HID_07a0] = 3302, - [BNXT_ULP_CLASS_HID_1370] = 3303, - [BNXT_ULP_CLASS_HID_2834] = 3304, - [BNXT_ULP_CLASS_HID_37c4] = 3305, - [BNXT_ULP_CLASS_HID_0398] = 3306, - [BNXT_ULP_CLASS_HID_595c] = 3307, - [BNXT_ULP_CLASS_HID_246c] = 3308, - [BNXT_ULP_CLASS_HID_1e64] = 3309, - [BNXT_ULP_CLASS_HID_48c0] = 3310, - [BNXT_ULP_CLASS_HID_22f8] = 3311, - [BNXT_ULP_CLASS_HID_3188] = 3312, - [BNXT_ULP_CLASS_HID_24664] = 3313, - [BNXT_ULP_CLASS_HID_29418] = 3314, - [BNXT_ULP_CLASS_HID_30118] = 3315, - [BNXT_ULP_CLASS_HID_38a18] = 3316, - [BNXT_ULP_CLASS_HID_255b4] = 3317, - [BNXT_ULP_CLASS_HID_2deb4] = 3318, - [BNXT_ULP_CLASS_HID_34bb4] = 3319, - [BNXT_ULP_CLASS_HID_39968] = 3320, - [BNXT_ULP_CLASS_HID_22e68] = 3321, - [BNXT_ULP_CLASS_HID_2db68] = 3322, - [BNXT_ULP_CLASS_HID_34468] = 3323, - [BNXT_ULP_CLASS_HID_3921c] = 3324, - [BNXT_ULP_CLASS_HID_24318] = 3325, - [BNXT_ULP_CLASS_HID_290cc] = 3326, - [BNXT_ULP_CLASS_HID_31dcc] = 3327, - [BNXT_ULP_CLASS_HID_386cc] = 3328, - [BNXT_ULP_CLASS_HID_20fac] = 3329, - [BNXT_ULP_CLASS_HID_2b8ac] = 3330, - [BNXT_ULP_CLASS_HID_325ac] = 3331, - [BNXT_ULP_CLASS_HID_3aeac] = 3332, - [BNXT_ULP_CLASS_HID_21afc] = 3333, - [BNXT_ULP_CLASS_HID_287fc] = 3334, - [BNXT_ULP_CLASS_HID_330fc] = 3335, - [BNXT_ULP_CLASS_HID_3bdfc] = 3336, - [BNXT_ULP_CLASS_HID_217b0] = 3337, - [BNXT_ULP_CLASS_HID_280b0] = 3338, - [BNXT_ULP_CLASS_HID_30db0] = 3339, - [BNXT_ULP_CLASS_HID_3b6b0] = 3340, - [BNXT_ULP_CLASS_HID_20860] = 3341, - [BNXT_ULP_CLASS_HID_2b560] = 3342, - [BNXT_ULP_CLASS_HID_33e60] = 3343, - [BNXT_ULP_CLASS_HID_3ab60] = 3344, - [BNXT_ULP_CLASS_HID_253c0] = 3345, - [BNXT_ULP_CLASS_HID_2dcc0] = 3346, - [BNXT_ULP_CLASS_HID_349c0] = 3347, - [BNXT_ULP_CLASS_HID_397f4] = 3348, - [BNXT_ULP_CLASS_HID_23f10] = 3349, - [BNXT_ULP_CLASS_HID_2a810] = 3350, - [BNXT_ULP_CLASS_HID_35510] = 3351, - [BNXT_ULP_CLASS_HID_3de10] = 3352, - [BNXT_ULP_CLASS_HID_23bc4] = 3353, - [BNXT_ULP_CLASS_HID_2a4c4] = 3354, - [BNXT_ULP_CLASS_HID_351c4] = 3355, - [BNXT_ULP_CLASS_HID_3dac4] = 3356, - [BNXT_ULP_CLASS_HID_22cf4] = 3357, - [BNXT_ULP_CLASS_HID_2d9f4] = 3358, - [BNXT_ULP_CLASS_HID_342f4] = 3359, - [BNXT_ULP_CLASS_HID_390a8] = 3360, - [BNXT_ULP_CLASS_HID_21908] = 3361, - [BNXT_ULP_CLASS_HID_28208] = 3362, - [BNXT_ULP_CLASS_HID_30f08] = 3363, - [BNXT_ULP_CLASS_HID_3b808] = 3364, - [BNXT_ULP_CLASS_HID_243a4] = 3365, - [BNXT_ULP_CLASS_HID_29158] = 3366, - [BNXT_ULP_CLASS_HID_31a58] = 3367, - [BNXT_ULP_CLASS_HID_38758] = 3368, - [BNXT_ULP_CLASS_HID_25c58] = 3369, - [BNXT_ULP_CLASS_HID_2c958] = 3370, - [BNXT_ULP_CLASS_HID_3170c] = 3371, - [BNXT_ULP_CLASS_HID_3800c] = 3372, - [BNXT_ULP_CLASS_HID_2123c] = 3373, - [BNXT_ULP_CLASS_HID_29f3c] = 3374, - [BNXT_ULP_CLASS_HID_3083c] = 3375, - [BNXT_ULP_CLASS_HID_3b53c] = 3376, - [BNXT_ULP_CLASS_HID_240a8] = 3377, - [BNXT_ULP_CLASS_HID_2cda8] = 3378, - [BNXT_ULP_CLASS_HID_31b5c] = 3379, - [BNXT_ULP_CLASS_HID_3845c] = 3380, - [BNXT_ULP_CLASS_HID_22ff8] = 3381, - [BNXT_ULP_CLASS_HID_2d8f8] = 3382, - [BNXT_ULP_CLASS_HID_345f8] = 3383, - [BNXT_ULP_CLASS_HID_393ac] = 3384, - [BNXT_ULP_CLASS_HID_228ac] = 3385, - [BNXT_ULP_CLASS_HID_2d5ac] = 3386, - [BNXT_ULP_CLASS_HID_35eac] = 3387, - [BNXT_ULP_CLASS_HID_3cbac] = 3388, - [BNXT_ULP_CLASS_HID_25d5c] = 3389, - [BNXT_ULP_CLASS_HID_2c65c] = 3390, - [BNXT_ULP_CLASS_HID_31410] = 3391, - [BNXT_ULP_CLASS_HID_38110] = 3392, - [BNXT_ULP_CLASS_HID_209f0] = 3393, - [BNXT_ULP_CLASS_HID_2b2f0] = 3394, - [BNXT_ULP_CLASS_HID_33ff0] = 3395, - [BNXT_ULP_CLASS_HID_3a8f0] = 3396, - [BNXT_ULP_CLASS_HID_214c0] = 3397, - [BNXT_ULP_CLASS_HID_281c0] = 3398, - [BNXT_ULP_CLASS_HID_30ac0] = 3399, - [BNXT_ULP_CLASS_HID_3b7c0] = 3400, - [BNXT_ULP_CLASS_HID_211f4] = 3401, - [BNXT_ULP_CLASS_HID_29af4] = 3402, - [BNXT_ULP_CLASS_HID_307f4] = 3403, - [BNXT_ULP_CLASS_HID_3b0f4] = 3404, - [BNXT_ULP_CLASS_HID_202a4] = 3405, - [BNXT_ULP_CLASS_HID_28fa4] = 3406, - [BNXT_ULP_CLASS_HID_338a4] = 3407, - [BNXT_ULP_CLASS_HID_3a5a4] = 3408, - [BNXT_ULP_CLASS_HID_22a04] = 3409, - [BNXT_ULP_CLASS_HID_2d704] = 3410, - [BNXT_ULP_CLASS_HID_34004] = 3411, - [BNXT_ULP_CLASS_HID_3cd04] = 3412, - [BNXT_ULP_CLASS_HID_23954] = 3413, - [BNXT_ULP_CLASS_HID_2a254] = 3414, - [BNXT_ULP_CLASS_HID_32f54] = 3415, - [BNXT_ULP_CLASS_HID_3d854] = 3416, - [BNXT_ULP_CLASS_HID_23208] = 3417, - [BNXT_ULP_CLASS_HID_2bf08] = 3418, - [BNXT_ULP_CLASS_HID_32808] = 3419, - [BNXT_ULP_CLASS_HID_3d508] = 3420, - [BNXT_ULP_CLASS_HID_22738] = 3421, - [BNXT_ULP_CLASS_HID_2d038] = 3422, - [BNXT_ULP_CLASS_HID_35d38] = 3423, - [BNXT_ULP_CLASS_HID_3c638] = 3424, - [BNXT_ULP_CLASS_HID_2134c] = 3425, - [BNXT_ULP_CLASS_HID_29c4c] = 3426, - [BNXT_ULP_CLASS_HID_3094c] = 3427, - [BNXT_ULP_CLASS_HID_3b24c] = 3428, - [BNXT_ULP_CLASS_HID_25de8] = 3429, - [BNXT_ULP_CLASS_HID_2c6e8] = 3430, - [BNXT_ULP_CLASS_HID_3149c] = 3431, - [BNXT_ULP_CLASS_HID_3819c] = 3432, - [BNXT_ULP_CLASS_HID_2569c] = 3433, - [BNXT_ULP_CLASS_HID_2c39c] = 3434, - [BNXT_ULP_CLASS_HID_31150] = 3435, - [BNXT_ULP_CLASS_HID_39a50] = 3436, - [BNXT_ULP_CLASS_HID_24b4c] = 3437, - [BNXT_ULP_CLASS_HID_29900] = 3438, - [BNXT_ULP_CLASS_HID_30200] = 3439, - [BNXT_ULP_CLASS_HID_38f00] = 3440, - [BNXT_ULP_CLASS_HID_22f74] = 3441, - [BNXT_ULP_CLASS_HID_2d874] = 3442, - [BNXT_ULP_CLASS_HID_34574] = 3443, - [BNXT_ULP_CLASS_HID_39328] = 3444, - [BNXT_ULP_CLASS_HID_23a44] = 3445, - [BNXT_ULP_CLASS_HID_2a744] = 3446, - [BNXT_ULP_CLASS_HID_35044] = 3447, - [BNXT_ULP_CLASS_HID_3dd44] = 3448, - [BNXT_ULP_CLASS_HID_23778] = 3449, - [BNXT_ULP_CLASS_HID_2a078] = 3450, - [BNXT_ULP_CLASS_HID_32d78] = 3451, - [BNXT_ULP_CLASS_HID_3d678] = 3452, - [BNXT_ULP_CLASS_HID_22828] = 3453, - [BNXT_ULP_CLASS_HID_2d528] = 3454, - [BNXT_ULP_CLASS_HID_35e28] = 3455, - [BNXT_ULP_CLASS_HID_3cb28] = 3456, - [BNXT_ULP_CLASS_HID_214bc] = 3457, - [BNXT_ULP_CLASS_HID_281bc] = 3458, - [BNXT_ULP_CLASS_HID_30abc] = 3459, - [BNXT_ULP_CLASS_HID_3b7bc] = 3460, - [BNXT_ULP_CLASS_HID_25ed8] = 3461, - [BNXT_ULP_CLASS_HID_2cbd8] = 3462, - [BNXT_ULP_CLASS_HID_3198c] = 3463, - [BNXT_ULP_CLASS_HID_3828c] = 3464, - [BNXT_ULP_CLASS_HID_25b8c] = 3465, - [BNXT_ULP_CLASS_HID_2c48c] = 3466, - [BNXT_ULP_CLASS_HID_31240] = 3467, - [BNXT_ULP_CLASS_HID_39f40] = 3468, - [BNXT_ULP_CLASS_HID_21170] = 3469, - [BNXT_ULP_CLASS_HID_29a70] = 3470, - [BNXT_ULP_CLASS_HID_30770] = 3471, - [BNXT_ULP_CLASS_HID_3b070] = 3472, - [BNXT_ULP_CLASS_HID_238d0] = 3473, - [BNXT_ULP_CLASS_HID_2a5d0] = 3474, - [BNXT_ULP_CLASS_HID_32ed0] = 3475, - [BNXT_ULP_CLASS_HID_3dbd0] = 3476, - [BNXT_ULP_CLASS_HID_20420] = 3477, - [BNXT_ULP_CLASS_HID_2b120] = 3478, - [BNXT_ULP_CLASS_HID_33a20] = 3479, - [BNXT_ULP_CLASS_HID_3a720] = 3480, - [BNXT_ULP_CLASS_HID_200d4] = 3481, - [BNXT_ULP_CLASS_HID_28dd4] = 3482, - [BNXT_ULP_CLASS_HID_336d4] = 3483, - [BNXT_ULP_CLASS_HID_3a3d4] = 3484, - [BNXT_ULP_CLASS_HID_23584] = 3485, - [BNXT_ULP_CLASS_HID_2be84] = 3486, - [BNXT_ULP_CLASS_HID_32b84] = 3487, - [BNXT_ULP_CLASS_HID_3d484] = 3488, - [BNXT_ULP_CLASS_HID_25d64] = 3489, - [BNXT_ULP_CLASS_HID_2c664] = 3490, - [BNXT_ULP_CLASS_HID_31418] = 3491, - [BNXT_ULP_CLASS_HID_38118] = 3492, - [BNXT_ULP_CLASS_HID_228b4] = 3493, - [BNXT_ULP_CLASS_HID_2d5b4] = 3494, - [BNXT_ULP_CLASS_HID_35eb4] = 3495, - [BNXT_ULP_CLASS_HID_3cbb4] = 3496, - [BNXT_ULP_CLASS_HID_22568] = 3497, - [BNXT_ULP_CLASS_HID_2ae68] = 3498, - [BNXT_ULP_CLASS_HID_35b68] = 3499, - [BNXT_ULP_CLASS_HID_3c468] = 3500, - [BNXT_ULP_CLASS_HID_25618] = 3501, - [BNXT_ULP_CLASS_HID_2c318] = 3502, - [BNXT_ULP_CLASS_HID_310cc] = 3503, - [BNXT_ULP_CLASS_HID_39dcc] = 3504, - [BNXT_ULP_CLASS_HID_229b8] = 3505, - [BNXT_ULP_CLASS_HID_2d2b8] = 3506, - [BNXT_ULP_CLASS_HID_35fb8] = 3507, - [BNXT_ULP_CLASS_HID_3c8b8] = 3508, - [BNXT_ULP_CLASS_HID_23488] = 3509, - [BNXT_ULP_CLASS_HID_2a188] = 3510, - [BNXT_ULP_CLASS_HID_32a88] = 3511, - [BNXT_ULP_CLASS_HID_3d788] = 3512, - [BNXT_ULP_CLASS_HID_231bc] = 3513, - [BNXT_ULP_CLASS_HID_2babc] = 3514, - [BNXT_ULP_CLASS_HID_327bc] = 3515, - [BNXT_ULP_CLASS_HID_3d0bc] = 3516, - [BNXT_ULP_CLASS_HID_2226c] = 3517, - [BNXT_ULP_CLASS_HID_2af6c] = 3518, - [BNXT_ULP_CLASS_HID_3586c] = 3519, - [BNXT_ULP_CLASS_HID_3c56c] = 3520, - [BNXT_ULP_CLASS_HID_24dcc] = 3521, - [BNXT_ULP_CLASS_HID_29b80] = 3522, - [BNXT_ULP_CLASS_HID_30480] = 3523, - [BNXT_ULP_CLASS_HID_3b180] = 3524, - [BNXT_ULP_CLASS_HID_2591c] = 3525, - [BNXT_ULP_CLASS_HID_2c21c] = 3526, - [BNXT_ULP_CLASS_HID_313d0] = 3527, - [BNXT_ULP_CLASS_HID_39cd0] = 3528, - [BNXT_ULP_CLASS_HID_255d0] = 3529, - [BNXT_ULP_CLASS_HID_2ded0] = 3530, - [BNXT_ULP_CLASS_HID_34bd0] = 3531, - [BNXT_ULP_CLASS_HID_39984] = 3532, - [BNXT_ULP_CLASS_HID_24680] = 3533, - [BNXT_ULP_CLASS_HID_294b4] = 3534, - [BNXT_ULP_CLASS_HID_301b4] = 3535, - [BNXT_ULP_CLASS_HID_38ab4] = 3536, - [BNXT_ULP_CLASS_HID_23314] = 3537, - [BNXT_ULP_CLASS_HID_2bc14] = 3538, - [BNXT_ULP_CLASS_HID_32914] = 3539, - [BNXT_ULP_CLASS_HID_3d214] = 3540, - [BNXT_ULP_CLASS_HID_21e64] = 3541, - [BNXT_ULP_CLASS_HID_28b64] = 3542, - [BNXT_ULP_CLASS_HID_33464] = 3543, - [BNXT_ULP_CLASS_HID_3a164] = 3544, - [BNXT_ULP_CLASS_HID_21b18] = 3545, - [BNXT_ULP_CLASS_HID_28418] = 3546, - [BNXT_ULP_CLASS_HID_33118] = 3547, - [BNXT_ULP_CLASS_HID_3ba18] = 3548, - [BNXT_ULP_CLASS_HID_20fc8] = 3549, - [BNXT_ULP_CLASS_HID_2b8c8] = 3550, - [BNXT_ULP_CLASS_HID_325c8] = 3551, - [BNXT_ULP_CLASS_HID_3aec8] = 3552, - [BNXT_ULP_CLASS_HID_257a8] = 3553, - [BNXT_ULP_CLASS_HID_2c0a8] = 3554, - [BNXT_ULP_CLASS_HID_34da8] = 3555, - [BNXT_ULP_CLASS_HID_39b5c] = 3556, - [BNXT_ULP_CLASS_HID_222f8] = 3557, - [BNXT_ULP_CLASS_HID_2aff8] = 3558, - [BNXT_ULP_CLASS_HID_358f8] = 3559, - [BNXT_ULP_CLASS_HID_3c5f8] = 3560, - [BNXT_ULP_CLASS_HID_23fac] = 3561, - [BNXT_ULP_CLASS_HID_2a8ac] = 3562, - [BNXT_ULP_CLASS_HID_355ac] = 3563, - [BNXT_ULP_CLASS_HID_3deac] = 3564, - [BNXT_ULP_CLASS_HID_2505c] = 3565, - [BNXT_ULP_CLASS_HID_2dd5c] = 3566, - [BNXT_ULP_CLASS_HID_3465c] = 3567, - [BNXT_ULP_CLASS_HID_39410] = 3568, - [BNXT_ULP_CLASS_HID_223fc] = 3569, - [BNXT_ULP_CLASS_HID_2acfc] = 3570, - [BNXT_ULP_CLASS_HID_359fc] = 3571, - [BNXT_ULP_CLASS_HID_3c2fc] = 3572, - [BNXT_ULP_CLASS_HID_20ecc] = 3573, - [BNXT_ULP_CLASS_HID_2bbcc] = 3574, - [BNXT_ULP_CLASS_HID_324cc] = 3575, - [BNXT_ULP_CLASS_HID_3d1cc] = 3576, - [BNXT_ULP_CLASS_HID_20b80] = 3577, - [BNXT_ULP_CLASS_HID_2b480] = 3578, - [BNXT_ULP_CLASS_HID_32180] = 3579, - [BNXT_ULP_CLASS_HID_3aa80] = 3580, - [BNXT_ULP_CLASS_HID_23cb0] = 3581, - [BNXT_ULP_CLASS_HID_2a9b0] = 3582, - [BNXT_ULP_CLASS_HID_352b0] = 3583, - [BNXT_ULP_CLASS_HID_3dfb0] = 3584, - [BNXT_ULP_CLASS_HID_24410] = 3585, - [BNXT_ULP_CLASS_HID_295c4] = 3586, - [BNXT_ULP_CLASS_HID_31ec4] = 3587, - [BNXT_ULP_CLASS_HID_38bc4] = 3588, - [BNXT_ULP_CLASS_HID_25360] = 3589, - [BNXT_ULP_CLASS_HID_2dc60] = 3590, - [BNXT_ULP_CLASS_HID_34960] = 3591, - [BNXT_ULP_CLASS_HID_39714] = 3592, - [BNXT_ULP_CLASS_HID_22c14] = 3593, - [BNXT_ULP_CLASS_HID_2d914] = 3594, - [BNXT_ULP_CLASS_HID_34214] = 3595, - [BNXT_ULP_CLASS_HID_393c8] = 3596, - [BNXT_ULP_CLASS_HID_240c4] = 3597, - [BNXT_ULP_CLASS_HID_2cdc4] = 3598, - [BNXT_ULP_CLASS_HID_31bf8] = 3599, - [BNXT_ULP_CLASS_HID_384f8] = 3600, - [BNXT_ULP_CLASS_HID_23dc0] = 3601, - [BNXT_ULP_CLASS_HID_2a6c0] = 3602, - [BNXT_ULP_CLASS_HID_353c0] = 3603, - [BNXT_ULP_CLASS_HID_3dcc0] = 3604, - [BNXT_ULP_CLASS_HID_20910] = 3605, - [BNXT_ULP_CLASS_HID_2b210] = 3606, - [BNXT_ULP_CLASS_HID_33f10] = 3607, - [BNXT_ULP_CLASS_HID_3a810] = 3608, - [BNXT_ULP_CLASS_HID_205c4] = 3609, - [BNXT_ULP_CLASS_HID_28ec4] = 3610, - [BNXT_ULP_CLASS_HID_33bc4] = 3611, - [BNXT_ULP_CLASS_HID_3a4c4] = 3612, - [BNXT_ULP_CLASS_HID_236f4] = 3613, - [BNXT_ULP_CLASS_HID_2a3f4] = 3614, - [BNXT_ULP_CLASS_HID_32cf4] = 3615, - [BNXT_ULP_CLASS_HID_3d9f4] = 3616, - [BNXT_ULP_CLASS_HID_25e54] = 3617, - [BNXT_ULP_CLASS_HID_2cb54] = 3618, - [BNXT_ULP_CLASS_HID_31908] = 3619, - [BNXT_ULP_CLASS_HID_38208] = 3620, - [BNXT_ULP_CLASS_HID_22da4] = 3621, - [BNXT_ULP_CLASS_HID_2d6a4] = 3622, - [BNXT_ULP_CLASS_HID_343a4] = 3623, - [BNXT_ULP_CLASS_HID_39158] = 3624, - [BNXT_ULP_CLASS_HID_22658] = 3625, - [BNXT_ULP_CLASS_HID_2d358] = 3626, - [BNXT_ULP_CLASS_HID_35c58] = 3627, - [BNXT_ULP_CLASS_HID_3c958] = 3628, - [BNXT_ULP_CLASS_HID_25b08] = 3629, - [BNXT_ULP_CLASS_HID_2c408] = 3630, - [BNXT_ULP_CLASS_HID_3123c] = 3631, - [BNXT_ULP_CLASS_HID_39f3c] = 3632, - [BNXT_ULP_CLASS_HID_34a8] = 3633, - [BNXT_ULP_CLASS_HID_3a64] = 3634, - [BNXT_ULP_CLASS_HID_09b4] = 3635, - [BNXT_ULP_CLASS_HID_5ef8] = 3636, - [BNXT_ULP_CLASS_HID_2dc8] = 3637, - [BNXT_ULP_CLASS_HID_07c0] = 3638, - [BNXT_ULP_CLASS_HID_1310] = 3639, - [BNXT_ULP_CLASS_HID_2854] = 3640, - [BNXT_ULP_CLASS_HID_37a4] = 3641, - [BNXT_ULP_CLASS_HID_03f8] = 3642, - [BNXT_ULP_CLASS_HID_593c] = 3643, - [BNXT_ULP_CLASS_HID_240c] = 3644, - [BNXT_ULP_CLASS_HID_1e04] = 3645, - [BNXT_ULP_CLASS_HID_48a0] = 3646, - [BNXT_ULP_CLASS_HID_2298] = 3647, - [BNXT_ULP_CLASS_HID_31e8] = 3648, - [BNXT_ULP_CLASS_HID_24644] = 3649, - [BNXT_ULP_CLASS_HID_29438] = 3650, - [BNXT_ULP_CLASS_HID_30138] = 3651, - [BNXT_ULP_CLASS_HID_38a38] = 3652, - [BNXT_ULP_CLASS_HID_25594] = 3653, - [BNXT_ULP_CLASS_HID_2de94] = 3654, - [BNXT_ULP_CLASS_HID_34b94] = 3655, - [BNXT_ULP_CLASS_HID_39948] = 3656, - [BNXT_ULP_CLASS_HID_22e48] = 3657, - [BNXT_ULP_CLASS_HID_2db48] = 3658, - [BNXT_ULP_CLASS_HID_34448] = 3659, - [BNXT_ULP_CLASS_HID_3923c] = 3660, - [BNXT_ULP_CLASS_HID_24338] = 3661, - [BNXT_ULP_CLASS_HID_290ec] = 3662, - [BNXT_ULP_CLASS_HID_31dec] = 3663, - [BNXT_ULP_CLASS_HID_386ec] = 3664, - [BNXT_ULP_CLASS_HID_20f8c] = 3665, - [BNXT_ULP_CLASS_HID_2b88c] = 3666, - [BNXT_ULP_CLASS_HID_3258c] = 3667, - [BNXT_ULP_CLASS_HID_3ae8c] = 3668, - [BNXT_ULP_CLASS_HID_21adc] = 3669, - [BNXT_ULP_CLASS_HID_287dc] = 3670, - [BNXT_ULP_CLASS_HID_330dc] = 3671, - [BNXT_ULP_CLASS_HID_3bddc] = 3672, - [BNXT_ULP_CLASS_HID_21790] = 3673, - [BNXT_ULP_CLASS_HID_28090] = 3674, - [BNXT_ULP_CLASS_HID_30d90] = 3675, - [BNXT_ULP_CLASS_HID_3b690] = 3676, - [BNXT_ULP_CLASS_HID_20840] = 3677, - [BNXT_ULP_CLASS_HID_2b540] = 3678, - [BNXT_ULP_CLASS_HID_33e40] = 3679, - [BNXT_ULP_CLASS_HID_3ab40] = 3680, - [BNXT_ULP_CLASS_HID_253e0] = 3681, - [BNXT_ULP_CLASS_HID_2dce0] = 3682, - [BNXT_ULP_CLASS_HID_349e0] = 3683, - [BNXT_ULP_CLASS_HID_397d4] = 3684, - [BNXT_ULP_CLASS_HID_23f30] = 3685, - [BNXT_ULP_CLASS_HID_2a830] = 3686, - [BNXT_ULP_CLASS_HID_35530] = 3687, - [BNXT_ULP_CLASS_HID_3de30] = 3688, - [BNXT_ULP_CLASS_HID_23be4] = 3689, - [BNXT_ULP_CLASS_HID_2a4e4] = 3690, - [BNXT_ULP_CLASS_HID_351e4] = 3691, - [BNXT_ULP_CLASS_HID_3dae4] = 3692, - [BNXT_ULP_CLASS_HID_22cd4] = 3693, - [BNXT_ULP_CLASS_HID_2d9d4] = 3694, - [BNXT_ULP_CLASS_HID_342d4] = 3695, - [BNXT_ULP_CLASS_HID_39088] = 3696, - [BNXT_ULP_CLASS_HID_21928] = 3697, - [BNXT_ULP_CLASS_HID_28228] = 3698, - [BNXT_ULP_CLASS_HID_30f28] = 3699, - [BNXT_ULP_CLASS_HID_3b828] = 3700, - [BNXT_ULP_CLASS_HID_24384] = 3701, - [BNXT_ULP_CLASS_HID_29178] = 3702, - [BNXT_ULP_CLASS_HID_31a78] = 3703, - [BNXT_ULP_CLASS_HID_38778] = 3704, - [BNXT_ULP_CLASS_HID_25c78] = 3705, - [BNXT_ULP_CLASS_HID_2c978] = 3706, - [BNXT_ULP_CLASS_HID_3172c] = 3707, - [BNXT_ULP_CLASS_HID_3802c] = 3708, - [BNXT_ULP_CLASS_HID_2121c] = 3709, - [BNXT_ULP_CLASS_HID_29f1c] = 3710, - [BNXT_ULP_CLASS_HID_3081c] = 3711, - [BNXT_ULP_CLASS_HID_3b51c] = 3712, - [BNXT_ULP_CLASS_HID_24088] = 3713, - [BNXT_ULP_CLASS_HID_2cd88] = 3714, - [BNXT_ULP_CLASS_HID_31b7c] = 3715, - [BNXT_ULP_CLASS_HID_3847c] = 3716, - [BNXT_ULP_CLASS_HID_22fd8] = 3717, - [BNXT_ULP_CLASS_HID_2d8d8] = 3718, - [BNXT_ULP_CLASS_HID_345d8] = 3719, - [BNXT_ULP_CLASS_HID_3938c] = 3720, - [BNXT_ULP_CLASS_HID_2288c] = 3721, - [BNXT_ULP_CLASS_HID_2d58c] = 3722, - [BNXT_ULP_CLASS_HID_35e8c] = 3723, - [BNXT_ULP_CLASS_HID_3cb8c] = 3724, - [BNXT_ULP_CLASS_HID_25d7c] = 3725, - [BNXT_ULP_CLASS_HID_2c67c] = 3726, - [BNXT_ULP_CLASS_HID_31430] = 3727, - [BNXT_ULP_CLASS_HID_38130] = 3728, - [BNXT_ULP_CLASS_HID_209d0] = 3729, - [BNXT_ULP_CLASS_HID_2b2d0] = 3730, - [BNXT_ULP_CLASS_HID_33fd0] = 3731, - [BNXT_ULP_CLASS_HID_3a8d0] = 3732, - [BNXT_ULP_CLASS_HID_214e0] = 3733, - [BNXT_ULP_CLASS_HID_281e0] = 3734, - [BNXT_ULP_CLASS_HID_30ae0] = 3735, - [BNXT_ULP_CLASS_HID_3b7e0] = 3736, - [BNXT_ULP_CLASS_HID_211d4] = 3737, - [BNXT_ULP_CLASS_HID_29ad4] = 3738, - [BNXT_ULP_CLASS_HID_307d4] = 3739, - [BNXT_ULP_CLASS_HID_3b0d4] = 3740, - [BNXT_ULP_CLASS_HID_20284] = 3741, - [BNXT_ULP_CLASS_HID_28f84] = 3742, - [BNXT_ULP_CLASS_HID_33884] = 3743, - [BNXT_ULP_CLASS_HID_3a584] = 3744, - [BNXT_ULP_CLASS_HID_22a24] = 3745, - [BNXT_ULP_CLASS_HID_2d724] = 3746, - [BNXT_ULP_CLASS_HID_34024] = 3747, - [BNXT_ULP_CLASS_HID_3cd24] = 3748, - [BNXT_ULP_CLASS_HID_23974] = 3749, - [BNXT_ULP_CLASS_HID_2a274] = 3750, - [BNXT_ULP_CLASS_HID_32f74] = 3751, - [BNXT_ULP_CLASS_HID_3d874] = 3752, - [BNXT_ULP_CLASS_HID_23228] = 3753, - [BNXT_ULP_CLASS_HID_2bf28] = 3754, - [BNXT_ULP_CLASS_HID_32828] = 3755, - [BNXT_ULP_CLASS_HID_3d528] = 3756, - [BNXT_ULP_CLASS_HID_22718] = 3757, - [BNXT_ULP_CLASS_HID_2d018] = 3758, - [BNXT_ULP_CLASS_HID_35d18] = 3759, - [BNXT_ULP_CLASS_HID_3c618] = 3760, - [BNXT_ULP_CLASS_HID_2136c] = 3761, - [BNXT_ULP_CLASS_HID_29c6c] = 3762, - [BNXT_ULP_CLASS_HID_3096c] = 3763, - [BNXT_ULP_CLASS_HID_3b26c] = 3764, - [BNXT_ULP_CLASS_HID_25dc8] = 3765, - [BNXT_ULP_CLASS_HID_2c6c8] = 3766, - [BNXT_ULP_CLASS_HID_314bc] = 3767, - [BNXT_ULP_CLASS_HID_381bc] = 3768, - [BNXT_ULP_CLASS_HID_256bc] = 3769, - [BNXT_ULP_CLASS_HID_2c3bc] = 3770, - [BNXT_ULP_CLASS_HID_31170] = 3771, - [BNXT_ULP_CLASS_HID_39a70] = 3772, - [BNXT_ULP_CLASS_HID_24b6c] = 3773, - [BNXT_ULP_CLASS_HID_29920] = 3774, - [BNXT_ULP_CLASS_HID_30220] = 3775, - [BNXT_ULP_CLASS_HID_38f20] = 3776, - [BNXT_ULP_CLASS_HID_22f54] = 3777, - [BNXT_ULP_CLASS_HID_2d854] = 3778, - [BNXT_ULP_CLASS_HID_34554] = 3779, - [BNXT_ULP_CLASS_HID_39308] = 3780, - [BNXT_ULP_CLASS_HID_23a64] = 3781, - [BNXT_ULP_CLASS_HID_2a764] = 3782, - [BNXT_ULP_CLASS_HID_35064] = 3783, - [BNXT_ULP_CLASS_HID_3dd64] = 3784, - [BNXT_ULP_CLASS_HID_23758] = 3785, - [BNXT_ULP_CLASS_HID_2a058] = 3786, - [BNXT_ULP_CLASS_HID_32d58] = 3787, - [BNXT_ULP_CLASS_HID_3d658] = 3788, - [BNXT_ULP_CLASS_HID_22808] = 3789, - [BNXT_ULP_CLASS_HID_2d508] = 3790, - [BNXT_ULP_CLASS_HID_35e08] = 3791, - [BNXT_ULP_CLASS_HID_3cb08] = 3792, - [BNXT_ULP_CLASS_HID_2149c] = 3793, - [BNXT_ULP_CLASS_HID_2819c] = 3794, - [BNXT_ULP_CLASS_HID_30a9c] = 3795, - [BNXT_ULP_CLASS_HID_3b79c] = 3796, - [BNXT_ULP_CLASS_HID_25ef8] = 3797, - [BNXT_ULP_CLASS_HID_2cbf8] = 3798, - [BNXT_ULP_CLASS_HID_319ac] = 3799, - [BNXT_ULP_CLASS_HID_382ac] = 3800, - [BNXT_ULP_CLASS_HID_25bac] = 3801, - [BNXT_ULP_CLASS_HID_2c4ac] = 3802, - [BNXT_ULP_CLASS_HID_31260] = 3803, - [BNXT_ULP_CLASS_HID_39f60] = 3804, - [BNXT_ULP_CLASS_HID_21150] = 3805, - [BNXT_ULP_CLASS_HID_29a50] = 3806, - [BNXT_ULP_CLASS_HID_30750] = 3807, - [BNXT_ULP_CLASS_HID_3b050] = 3808, - [BNXT_ULP_CLASS_HID_238f0] = 3809, - [BNXT_ULP_CLASS_HID_2a5f0] = 3810, - [BNXT_ULP_CLASS_HID_32ef0] = 3811, - [BNXT_ULP_CLASS_HID_3dbf0] = 3812, - [BNXT_ULP_CLASS_HID_20400] = 3813, - [BNXT_ULP_CLASS_HID_2b100] = 3814, - [BNXT_ULP_CLASS_HID_33a00] = 3815, - [BNXT_ULP_CLASS_HID_3a700] = 3816, - [BNXT_ULP_CLASS_HID_200f4] = 3817, - [BNXT_ULP_CLASS_HID_28df4] = 3818, - [BNXT_ULP_CLASS_HID_336f4] = 3819, - [BNXT_ULP_CLASS_HID_3a3f4] = 3820, - [BNXT_ULP_CLASS_HID_235a4] = 3821, - [BNXT_ULP_CLASS_HID_2bea4] = 3822, - [BNXT_ULP_CLASS_HID_32ba4] = 3823, - [BNXT_ULP_CLASS_HID_3d4a4] = 3824, - [BNXT_ULP_CLASS_HID_25d44] = 3825, - [BNXT_ULP_CLASS_HID_2c644] = 3826, - [BNXT_ULP_CLASS_HID_31438] = 3827, - [BNXT_ULP_CLASS_HID_38138] = 3828, - [BNXT_ULP_CLASS_HID_22894] = 3829, - [BNXT_ULP_CLASS_HID_2d594] = 3830, - [BNXT_ULP_CLASS_HID_35e94] = 3831, - [BNXT_ULP_CLASS_HID_3cb94] = 3832, - [BNXT_ULP_CLASS_HID_22548] = 3833, - [BNXT_ULP_CLASS_HID_2ae48] = 3834, - [BNXT_ULP_CLASS_HID_35b48] = 3835, - [BNXT_ULP_CLASS_HID_3c448] = 3836, - [BNXT_ULP_CLASS_HID_25638] = 3837, - [BNXT_ULP_CLASS_HID_2c338] = 3838, - [BNXT_ULP_CLASS_HID_310ec] = 3839, - [BNXT_ULP_CLASS_HID_39dec] = 3840, - [BNXT_ULP_CLASS_HID_22998] = 3841, - [BNXT_ULP_CLASS_HID_2d298] = 3842, - [BNXT_ULP_CLASS_HID_35f98] = 3843, - [BNXT_ULP_CLASS_HID_3c898] = 3844, - [BNXT_ULP_CLASS_HID_234a8] = 3845, - [BNXT_ULP_CLASS_HID_2a1a8] = 3846, - [BNXT_ULP_CLASS_HID_32aa8] = 3847, - [BNXT_ULP_CLASS_HID_3d7a8] = 3848, - [BNXT_ULP_CLASS_HID_2319c] = 3849, - [BNXT_ULP_CLASS_HID_2ba9c] = 3850, - [BNXT_ULP_CLASS_HID_3279c] = 3851, - [BNXT_ULP_CLASS_HID_3d09c] = 3852, - [BNXT_ULP_CLASS_HID_2224c] = 3853, - [BNXT_ULP_CLASS_HID_2af4c] = 3854, - [BNXT_ULP_CLASS_HID_3584c] = 3855, - [BNXT_ULP_CLASS_HID_3c54c] = 3856, - [BNXT_ULP_CLASS_HID_24dec] = 3857, - [BNXT_ULP_CLASS_HID_29ba0] = 3858, - [BNXT_ULP_CLASS_HID_304a0] = 3859, - [BNXT_ULP_CLASS_HID_3b1a0] = 3860, - [BNXT_ULP_CLASS_HID_2593c] = 3861, - [BNXT_ULP_CLASS_HID_2c23c] = 3862, - [BNXT_ULP_CLASS_HID_313f0] = 3863, - [BNXT_ULP_CLASS_HID_39cf0] = 3864, - [BNXT_ULP_CLASS_HID_255f0] = 3865, - [BNXT_ULP_CLASS_HID_2def0] = 3866, - [BNXT_ULP_CLASS_HID_34bf0] = 3867, - [BNXT_ULP_CLASS_HID_399a4] = 3868, - [BNXT_ULP_CLASS_HID_246a0] = 3869, - [BNXT_ULP_CLASS_HID_29494] = 3870, - [BNXT_ULP_CLASS_HID_30194] = 3871, - [BNXT_ULP_CLASS_HID_38a94] = 3872, - [BNXT_ULP_CLASS_HID_23334] = 3873, - [BNXT_ULP_CLASS_HID_2bc34] = 3874, - [BNXT_ULP_CLASS_HID_32934] = 3875, - [BNXT_ULP_CLASS_HID_3d234] = 3876, - [BNXT_ULP_CLASS_HID_21e44] = 3877, - [BNXT_ULP_CLASS_HID_28b44] = 3878, - [BNXT_ULP_CLASS_HID_33444] = 3879, - [BNXT_ULP_CLASS_HID_3a144] = 3880, - [BNXT_ULP_CLASS_HID_21b38] = 3881, - [BNXT_ULP_CLASS_HID_28438] = 3882, - [BNXT_ULP_CLASS_HID_33138] = 3883, - [BNXT_ULP_CLASS_HID_3ba38] = 3884, - [BNXT_ULP_CLASS_HID_20fe8] = 3885, - [BNXT_ULP_CLASS_HID_2b8e8] = 3886, - [BNXT_ULP_CLASS_HID_325e8] = 3887, - [BNXT_ULP_CLASS_HID_3aee8] = 3888, - [BNXT_ULP_CLASS_HID_25788] = 3889, - [BNXT_ULP_CLASS_HID_2c088] = 3890, - [BNXT_ULP_CLASS_HID_34d88] = 3891, - [BNXT_ULP_CLASS_HID_39b7c] = 3892, - [BNXT_ULP_CLASS_HID_222d8] = 3893, - [BNXT_ULP_CLASS_HID_2afd8] = 3894, - [BNXT_ULP_CLASS_HID_358d8] = 3895, - [BNXT_ULP_CLASS_HID_3c5d8] = 3896, - [BNXT_ULP_CLASS_HID_23f8c] = 3897, - [BNXT_ULP_CLASS_HID_2a88c] = 3898, - [BNXT_ULP_CLASS_HID_3558c] = 3899, - [BNXT_ULP_CLASS_HID_3de8c] = 3900, - [BNXT_ULP_CLASS_HID_2507c] = 3901, - [BNXT_ULP_CLASS_HID_2dd7c] = 3902, - [BNXT_ULP_CLASS_HID_3467c] = 3903, - [BNXT_ULP_CLASS_HID_39430] = 3904, - [BNXT_ULP_CLASS_HID_223dc] = 3905, - [BNXT_ULP_CLASS_HID_2acdc] = 3906, - [BNXT_ULP_CLASS_HID_359dc] = 3907, - [BNXT_ULP_CLASS_HID_3c2dc] = 3908, - [BNXT_ULP_CLASS_HID_20eec] = 3909, - [BNXT_ULP_CLASS_HID_2bbec] = 3910, - [BNXT_ULP_CLASS_HID_324ec] = 3911, - [BNXT_ULP_CLASS_HID_3d1ec] = 3912, - [BNXT_ULP_CLASS_HID_20ba0] = 3913, - [BNXT_ULP_CLASS_HID_2b4a0] = 3914, - [BNXT_ULP_CLASS_HID_321a0] = 3915, - [BNXT_ULP_CLASS_HID_3aaa0] = 3916, - [BNXT_ULP_CLASS_HID_23c90] = 3917, - [BNXT_ULP_CLASS_HID_2a990] = 3918, - [BNXT_ULP_CLASS_HID_35290] = 3919, - [BNXT_ULP_CLASS_HID_3df90] = 3920, - [BNXT_ULP_CLASS_HID_24430] = 3921, - [BNXT_ULP_CLASS_HID_295e4] = 3922, - [BNXT_ULP_CLASS_HID_31ee4] = 3923, - [BNXT_ULP_CLASS_HID_38be4] = 3924, - [BNXT_ULP_CLASS_HID_25340] = 3925, - [BNXT_ULP_CLASS_HID_2dc40] = 3926, - [BNXT_ULP_CLASS_HID_34940] = 3927, - [BNXT_ULP_CLASS_HID_39734] = 3928, - [BNXT_ULP_CLASS_HID_22c34] = 3929, - [BNXT_ULP_CLASS_HID_2d934] = 3930, - [BNXT_ULP_CLASS_HID_34234] = 3931, - [BNXT_ULP_CLASS_HID_393e8] = 3932, - [BNXT_ULP_CLASS_HID_240e4] = 3933, - [BNXT_ULP_CLASS_HID_2cde4] = 3934, - [BNXT_ULP_CLASS_HID_31bd8] = 3935, - [BNXT_ULP_CLASS_HID_384d8] = 3936, - [BNXT_ULP_CLASS_HID_23de0] = 3937, - [BNXT_ULP_CLASS_HID_2a6e0] = 3938, - [BNXT_ULP_CLASS_HID_353e0] = 3939, - [BNXT_ULP_CLASS_HID_3dce0] = 3940, - [BNXT_ULP_CLASS_HID_20930] = 3941, - [BNXT_ULP_CLASS_HID_2b230] = 3942, - [BNXT_ULP_CLASS_HID_33f30] = 3943, - [BNXT_ULP_CLASS_HID_3a830] = 3944, - [BNXT_ULP_CLASS_HID_205e4] = 3945, - [BNXT_ULP_CLASS_HID_28ee4] = 3946, - [BNXT_ULP_CLASS_HID_33be4] = 3947, - [BNXT_ULP_CLASS_HID_3a4e4] = 3948, - [BNXT_ULP_CLASS_HID_236d4] = 3949, - [BNXT_ULP_CLASS_HID_2a3d4] = 3950, - [BNXT_ULP_CLASS_HID_32cd4] = 3951, - [BNXT_ULP_CLASS_HID_3d9d4] = 3952, - [BNXT_ULP_CLASS_HID_25e74] = 3953, - [BNXT_ULP_CLASS_HID_2cb74] = 3954, - [BNXT_ULP_CLASS_HID_31928] = 3955, - [BNXT_ULP_CLASS_HID_38228] = 3956, - [BNXT_ULP_CLASS_HID_22d84] = 3957, - [BNXT_ULP_CLASS_HID_2d684] = 3958, - [BNXT_ULP_CLASS_HID_34384] = 3959, - [BNXT_ULP_CLASS_HID_39178] = 3960, - [BNXT_ULP_CLASS_HID_22678] = 3961, - [BNXT_ULP_CLASS_HID_2d378] = 3962, - [BNXT_ULP_CLASS_HID_35c78] = 3963, - [BNXT_ULP_CLASS_HID_3c978] = 3964, - [BNXT_ULP_CLASS_HID_25b28] = 3965, - [BNXT_ULP_CLASS_HID_2c428] = 3966, - [BNXT_ULP_CLASS_HID_3121c] = 3967, - [BNXT_ULP_CLASS_HID_39f1c] = 3968, - [BNXT_ULP_CLASS_HID_3488] = 3969, - [BNXT_ULP_CLASS_HID_3a44] = 3970, - [BNXT_ULP_CLASS_HID_0994] = 3971, - [BNXT_ULP_CLASS_HID_5ed8] = 3972, - [BNXT_ULP_CLASS_HID_2de8] = 3973, - [BNXT_ULP_CLASS_HID_07e0] = 3974, - [BNXT_ULP_CLASS_HID_1330] = 3975, - [BNXT_ULP_CLASS_HID_2874] = 3976, - [BNXT_ULP_CLASS_HID_3784] = 3977, - [BNXT_ULP_CLASS_HID_03d8] = 3978, - [BNXT_ULP_CLASS_HID_591c] = 3979, - [BNXT_ULP_CLASS_HID_242c] = 3980, - [BNXT_ULP_CLASS_HID_1e24] = 3981, - [BNXT_ULP_CLASS_HID_4880] = 3982, - [BNXT_ULP_CLASS_HID_22b8] = 3983, - [BNXT_ULP_CLASS_HID_31c8] = 3984 + [BNXT_ULP_CLASS_HID_05d1] = 1, + [BNXT_ULP_CLASS_HID_1229] = 2, + [BNXT_ULP_CLASS_HID_0bed] = 3, + [BNXT_ULP_CLASS_HID_1865] = 4, + [BNXT_ULP_CLASS_HID_25c9] = 5, + [BNXT_ULP_CLASS_HID_3241] = 6, + [BNXT_ULP_CLASS_HID_2c05] = 7, + [BNXT_ULP_CLASS_HID_389d] = 8, + [BNXT_ULP_CLASS_HID_3c3d] = 9, + [BNXT_ULP_CLASS_HID_48b5] = 10, + [BNXT_ULP_CLASS_HID_4279] = 11, + [BNXT_ULP_CLASS_HID_4ef1] = 12, + [BNXT_ULP_CLASS_HID_5c55] = 13, + [BNXT_ULP_CLASS_HID_0be1] = 14, + [BNXT_ULP_CLASS_HID_05a5] = 15, + [BNXT_ULP_CLASS_HID_123d] = 16, + [BNXT_ULP_CLASS_HID_4142d] = 17, + [BNXT_ULP_CLASS_HID_42095] = 18, + [BNXT_ULP_CLASS_HID_41a69] = 19, + [BNXT_ULP_CLASS_HID_426d1] = 20, + [BNXT_ULP_CLASS_HID_44a99] = 21, + [BNXT_ULP_CLASS_HID_45701] = 22, + [BNXT_ULP_CLASS_HID_450c5] = 23, + [BNXT_ULP_CLASS_HID_40071] = 24, + [BNXT_ULP_CLASS_HID_40a85] = 25, + [BNXT_ULP_CLASS_HID_4170d] = 26, + [BNXT_ULP_CLASS_HID_410c1] = 27, + [BNXT_ULP_CLASS_HID_41d49] = 28, + [BNXT_ULP_CLASS_HID_440f1] = 29, + [BNXT_ULP_CLASS_HID_44d79] = 30, + [BNXT_ULP_CLASS_HID_4473d] = 31, + [BNXT_ULP_CLASS_HID_453a5] = 32, + [BNXT_ULP_CLASS_HID_244e3] = 33, + [BNXT_ULP_CLASS_HID_2517b] = 34, + [BNXT_ULP_CLASS_HID_24b3f] = 35, + [BNXT_ULP_CLASS_HID_257b7] = 36, + [BNXT_ULP_CLASS_HID_22f5f] = 37, + [BNXT_ULP_CLASS_HID_23bd7] = 38, + [BNXT_ULP_CLASS_HID_2359b] = 39, + [BNXT_ULP_CLASS_HID_24213] = 40, + [BNXT_ULP_CLASS_HID_20bab] = 41, + [BNXT_ULP_CLASS_HID_21823] = 42, + [BNXT_ULP_CLASS_HID_211e7] = 43, + [BNXT_ULP_CLASS_HID_21e7f] = 44, + [BNXT_ULP_CLASS_HID_252f3] = 45, + [BNXT_ULP_CLASS_HID_2029f] = 46, + [BNXT_ULP_CLASS_HID_2590f] = 47, + [BNXT_ULP_CLASS_HID_208db] = 48, + [BNXT_ULP_CLASS_HID_231d3] = 49, + [BNXT_ULP_CLASS_HID_23e2b] = 50, + [BNXT_ULP_CLASS_HID_237ef] = 51, + [BNXT_ULP_CLASS_HID_24467] = 52, + [BNXT_ULP_CLASS_HID_21c0f] = 53, + [BNXT_ULP_CLASS_HID_22887] = 54, + [BNXT_ULP_CLASS_HID_2224b] = 55, + [BNXT_ULP_CLASS_HID_22ec3] = 56, + [BNXT_ULP_CLASS_HID_25547] = 57, + [BNXT_ULP_CLASS_HID_20513] = 58, + [BNXT_ULP_CLASS_HID_25b83] = 59, + [BNXT_ULP_CLASS_HID_20b2f] = 60, + [BNXT_ULP_CLASS_HID_23fa3] = 61, + [BNXT_ULP_CLASS_HID_24c3b] = 62, + [BNXT_ULP_CLASS_HID_245ff] = 63, + [BNXT_ULP_CLASS_HID_25277] = 64, + [BNXT_ULP_CLASS_HID_64037] = 65, + [BNXT_ULP_CLASS_HID_64c8f] = 66, + [BNXT_ULP_CLASS_HID_64673] = 67, + [BNXT_ULP_CLASS_HID_652cb] = 68, + [BNXT_ULP_CLASS_HID_62a93] = 69, + [BNXT_ULP_CLASS_HID_636eb] = 70, + [BNXT_ULP_CLASS_HID_630af] = 71, + [BNXT_ULP_CLASS_HID_63d27] = 72, + [BNXT_ULP_CLASS_HID_606ff] = 73, + [BNXT_ULP_CLASS_HID_61377] = 74, + [BNXT_ULP_CLASS_HID_60d3b] = 75, + [BNXT_ULP_CLASS_HID_619b3] = 76, + [BNXT_ULP_CLASS_HID_64e07] = 77, + [BNXT_ULP_CLASS_HID_65a9f] = 78, + [BNXT_ULP_CLASS_HID_65443] = 79, + [BNXT_ULP_CLASS_HID_603ef] = 80, + [BNXT_ULP_CLASS_HID_62ce7] = 81, + [BNXT_ULP_CLASS_HID_6397f] = 82, + [BNXT_ULP_CLASS_HID_63323] = 83, + [BNXT_ULP_CLASS_HID_63fbb] = 84, + [BNXT_ULP_CLASS_HID_61743] = 85, + [BNXT_ULP_CLASS_HID_623db] = 86, + [BNXT_ULP_CLASS_HID_61d9f] = 87, + [BNXT_ULP_CLASS_HID_62a17] = 88, + [BNXT_ULP_CLASS_HID_6509b] = 89, + [BNXT_ULP_CLASS_HID_60027] = 90, + [BNXT_ULP_CLASS_HID_656d7] = 91, + [BNXT_ULP_CLASS_HID_60663] = 92, + [BNXT_ULP_CLASS_HID_63af7] = 93, + [BNXT_ULP_CLASS_HID_6474f] = 94, + [BNXT_ULP_CLASS_HID_64133] = 95, + [BNXT_ULP_CLASS_HID_64d8b] = 96, + [BNXT_ULP_CLASS_HID_a3fb] = 97, + [BNXT_ULP_CLASS_HID_b063] = 98, + [BNXT_ULP_CLASS_HID_aa27] = 99, + [BNXT_ULP_CLASS_HID_b6af] = 100, + [BNXT_ULP_CLASS_HID_8e47] = 101, + [BNXT_ULP_CLASS_HID_9acf] = 102, + [BNXT_ULP_CLASS_HID_9483] = 103, + [BNXT_ULP_CLASS_HID_a10b] = 104, + [BNXT_ULP_CLASS_HID_c78f] = 105, + [BNXT_ULP_CLASS_HID_d3f7] = 106, + [BNXT_ULP_CLASS_HID_cdcb] = 107, + [BNXT_ULP_CLASS_HID_da33] = 108, + [BNXT_ULP_CLASS_HID_b1eb] = 109, + [BNXT_ULP_CLASS_HID_be53] = 110, + [BNXT_ULP_CLASS_HID_b817] = 111, + [BNXT_ULP_CLASS_HID_c49f] = 112, + [BNXT_ULP_CLASS_HID_49f2f] = 113, + [BNXT_ULP_CLASS_HID_4ab97] = 114, + [BNXT_ULP_CLASS_HID_4a56b] = 115, + [BNXT_ULP_CLASS_HID_4b1d3] = 116, + [BNXT_ULP_CLASS_HID_4898b] = 117, + [BNXT_ULP_CLASS_HID_495f3] = 118, + [BNXT_ULP_CLASS_HID_48fb7] = 119, + [BNXT_ULP_CLASS_HID_49c3f] = 120, + [BNXT_ULP_CLASS_HID_4c2b3] = 121, + [BNXT_ULP_CLASS_HID_4cf3b] = 122, + [BNXT_ULP_CLASS_HID_4c8ff] = 123, + [BNXT_ULP_CLASS_HID_4d567] = 124, + [BNXT_ULP_CLASS_HID_4ad1f] = 125, + [BNXT_ULP_CLASS_HID_4b987] = 126, + [BNXT_ULP_CLASS_HID_4b35b] = 127, + [BNXT_ULP_CLASS_HID_4bfc3] = 128, + [BNXT_ULP_CLASS_HID_1b9fb] = 129, + [BNXT_ULP_CLASS_HID_1c663] = 130, + [BNXT_ULP_CLASS_HID_1c027] = 131, + [BNXT_ULP_CLASS_HID_1ccaf] = 132, + [BNXT_ULP_CLASS_HID_1a447] = 133, + [BNXT_ULP_CLASS_HID_1b0cf] = 134, + [BNXT_ULP_CLASS_HID_1aa83] = 135, + [BNXT_ULP_CLASS_HID_1b70b] = 136, + [BNXT_ULP_CLASS_HID_180b3] = 137, + [BNXT_ULP_CLASS_HID_18d3b] = 138, + [BNXT_ULP_CLASS_HID_186ff] = 139, + [BNXT_ULP_CLASS_HID_19367] = 140, + [BNXT_ULP_CLASS_HID_1c7eb] = 141, + [BNXT_ULP_CLASS_HID_1d453] = 142, + [BNXT_ULP_CLASS_HID_1ce17] = 143, + [BNXT_ULP_CLASS_HID_1da9f] = 144, + [BNXT_ULP_CLASS_HID_5b52f] = 145, + [BNXT_ULP_CLASS_HID_5c197] = 146, + [BNXT_ULP_CLASS_HID_5bb6b] = 147, + [BNXT_ULP_CLASS_HID_5c7d3] = 148, + [BNXT_ULP_CLASS_HID_59f8b] = 149, + [BNXT_ULP_CLASS_HID_5abf3] = 150, + [BNXT_ULP_CLASS_HID_5a5b7] = 151, + [BNXT_ULP_CLASS_HID_5b23f] = 152, + [BNXT_ULP_CLASS_HID_5d8b3] = 153, + [BNXT_ULP_CLASS_HID_5886f] = 154, + [BNXT_ULP_CLASS_HID_58223] = 155, + [BNXT_ULP_CLASS_HID_58eab] = 156, + [BNXT_ULP_CLASS_HID_5c31f] = 157, + [BNXT_ULP_CLASS_HID_5cf87] = 158, + [BNXT_ULP_CLASS_HID_5c95b] = 159, + [BNXT_ULP_CLASS_HID_5d5c3] = 160, + [BNXT_ULP_CLASS_HID_05f1] = 161, + [BNXT_ULP_CLASS_HID_1209] = 162, + [BNXT_ULP_CLASS_HID_0bcd] = 163, + [BNXT_ULP_CLASS_HID_1845] = 164, + [BNXT_ULP_CLASS_HID_25e9] = 165, + [BNXT_ULP_CLASS_HID_3261] = 166, + [BNXT_ULP_CLASS_HID_2c25] = 167, + [BNXT_ULP_CLASS_HID_38bd] = 168, + [BNXT_ULP_CLASS_HID_3c1d] = 169, + [BNXT_ULP_CLASS_HID_4895] = 170, + [BNXT_ULP_CLASS_HID_4259] = 171, + [BNXT_ULP_CLASS_HID_4ed1] = 172, + [BNXT_ULP_CLASS_HID_5c75] = 173, + [BNXT_ULP_CLASS_HID_0bc1] = 174, + [BNXT_ULP_CLASS_HID_0585] = 175, + [BNXT_ULP_CLASS_HID_121d] = 176, + [BNXT_ULP_CLASS_HID_58c5] = 177, + [BNXT_ULP_CLASS_HID_0891] = 178, + [BNXT_ULP_CLASS_HID_0255] = 179, + [BNXT_ULP_CLASS_HID_0eed] = 180, + [BNXT_ULP_CLASS_HID_1c71] = 181, + [BNXT_ULP_CLASS_HID_2889] = 182, + [BNXT_ULP_CLASS_HID_224d] = 183, + [BNXT_ULP_CLASS_HID_2ec5] = 184, + [BNXT_ULP_CLASS_HID_32a5] = 185, + [BNXT_ULP_CLASS_HID_3f3d] = 186, + [BNXT_ULP_CLASS_HID_38e1] = 187, + [BNXT_ULP_CLASS_HID_4579] = 188, + [BNXT_ULP_CLASS_HID_529d] = 189, + [BNXT_ULP_CLASS_HID_0269] = 190, + [BNXT_ULP_CLASS_HID_58d9] = 191, + [BNXT_ULP_CLASS_HID_08a5] = 192, + [BNXT_ULP_CLASS_HID_400c5] = 193, + [BNXT_ULP_CLASS_HID_40d5d] = 194, + [BNXT_ULP_CLASS_HID_40701] = 195, + [BNXT_ULP_CLASS_HID_41399] = 196, + [BNXT_ULP_CLASS_HID_4213d] = 197, + [BNXT_ULP_CLASS_HID_42db5] = 198, + [BNXT_ULP_CLASS_HID_42779] = 199, + [BNXT_ULP_CLASS_HID_433f1] = 200, + [BNXT_ULP_CLASS_HID_43751] = 201, + [BNXT_ULP_CLASS_HID_443e9] = 202, + [BNXT_ULP_CLASS_HID_43dad] = 203, + [BNXT_ULP_CLASS_HID_44a25] = 204, + [BNXT_ULP_CLASS_HID_45749] = 205, + [BNXT_ULP_CLASS_HID_40715] = 206, + [BNXT_ULP_CLASS_HID_400d9] = 207, + [BNXT_ULP_CLASS_HID_40d51] = 208, + [BNXT_ULP_CLASS_HID_45419] = 209, + [BNXT_ULP_CLASS_HID_403e5] = 210, + [BNXT_ULP_CLASS_HID_45a55] = 211, + [BNXT_ULP_CLASS_HID_40a21] = 212, + [BNXT_ULP_CLASS_HID_41745] = 213, + [BNXT_ULP_CLASS_HID_423dd] = 214, + [BNXT_ULP_CLASS_HID_41d81] = 215, + [BNXT_ULP_CLASS_HID_42a19] = 216, + [BNXT_ULP_CLASS_HID_42df9] = 217, + [BNXT_ULP_CLASS_HID_43a71] = 218, + [BNXT_ULP_CLASS_HID_43435] = 219, + [BNXT_ULP_CLASS_HID_4404d] = 220, + [BNXT_ULP_CLASS_HID_44dd1] = 221, + [BNXT_ULP_CLASS_HID_45a69] = 222, + [BNXT_ULP_CLASS_HID_4542d] = 223, + [BNXT_ULP_CLASS_HID_403f9] = 224, + [BNXT_ULP_CLASS_HID_4140d] = 225, + [BNXT_ULP_CLASS_HID_420b5] = 226, + [BNXT_ULP_CLASS_HID_41a49] = 227, + [BNXT_ULP_CLASS_HID_426f1] = 228, + [BNXT_ULP_CLASS_HID_44ab9] = 229, + [BNXT_ULP_CLASS_HID_45721] = 230, + [BNXT_ULP_CLASS_HID_450e5] = 231, + [BNXT_ULP_CLASS_HID_40051] = 232, + [BNXT_ULP_CLASS_HID_40aa5] = 233, + [BNXT_ULP_CLASS_HID_4172d] = 234, + [BNXT_ULP_CLASS_HID_410e1] = 235, + [BNXT_ULP_CLASS_HID_41d69] = 236, + [BNXT_ULP_CLASS_HID_440d1] = 237, + [BNXT_ULP_CLASS_HID_44d59] = 238, + [BNXT_ULP_CLASS_HID_4471d] = 239, + [BNXT_ULP_CLASS_HID_45385] = 240, + [BNXT_ULP_CLASS_HID_6400d] = 241, + [BNXT_ULP_CLASS_HID_64cb5] = 242, + [BNXT_ULP_CLASS_HID_64649] = 243, + [BNXT_ULP_CLASS_HID_652f1] = 244, + [BNXT_ULP_CLASS_HID_619ed] = 245, + [BNXT_ULP_CLASS_HID_62615] = 246, + [BNXT_ULP_CLASS_HID_62029] = 247, + [BNXT_ULP_CLASS_HID_62c51] = 248, + [BNXT_ULP_CLASS_HID_636a5] = 249, + [BNXT_ULP_CLASS_HID_6432d] = 250, + [BNXT_ULP_CLASS_HID_63ce1] = 251, + [BNXT_ULP_CLASS_HID_64969] = 252, + [BNXT_ULP_CLASS_HID_61005] = 253, + [BNXT_ULP_CLASS_HID_61c8d] = 254, + [BNXT_ULP_CLASS_HID_61641] = 255, + [BNXT_ULP_CLASS_HID_622c9] = 256, + [BNXT_ULP_CLASS_HID_52a0d] = 257, + [BNXT_ULP_CLASS_HID_536b5] = 258, + [BNXT_ULP_CLASS_HID_53049] = 259, + [BNXT_ULP_CLASS_HID_53cf1] = 260, + [BNXT_ULP_CLASS_HID_503ed] = 261, + [BNXT_ULP_CLASS_HID_51015] = 262, + [BNXT_ULP_CLASS_HID_50a29] = 263, + [BNXT_ULP_CLASS_HID_51651] = 264, + [BNXT_ULP_CLASS_HID_520a5] = 265, + [BNXT_ULP_CLASS_HID_52d2d] = 266, + [BNXT_ULP_CLASS_HID_526e1] = 267, + [BNXT_ULP_CLASS_HID_53369] = 268, + [BNXT_ULP_CLASS_HID_556d1] = 269, + [BNXT_ULP_CLASS_HID_5068d] = 270, + [BNXT_ULP_CLASS_HID_50041] = 271, + [BNXT_ULP_CLASS_HID_50cc9] = 272, + [BNXT_ULP_CLASS_HID_7560d] = 273, + [BNXT_ULP_CLASS_HID_705f9] = 274, + [BNXT_ULP_CLASS_HID_75c49] = 275, + [BNXT_ULP_CLASS_HID_70c25] = 276, + [BNXT_ULP_CLASS_HID_72fed] = 277, + [BNXT_ULP_CLASS_HID_73c15] = 278, + [BNXT_ULP_CLASS_HID_73629] = 279, + [BNXT_ULP_CLASS_HID_74251] = 280, + [BNXT_ULP_CLASS_HID_74ca5] = 281, + [BNXT_ULP_CLASS_HID_7592d] = 282, + [BNXT_ULP_CLASS_HID_752e1] = 283, + [BNXT_ULP_CLASS_HID_7025d] = 284, + [BNXT_ULP_CLASS_HID_72605] = 285, + [BNXT_ULP_CLASS_HID_7328d] = 286, + [BNXT_ULP_CLASS_HID_72c41] = 287, + [BNXT_ULP_CLASS_HID_738c9] = 288, + [BNXT_ULP_CLASS_HID_0591] = 289, + [BNXT_ULP_CLASS_HID_1269] = 290, + [BNXT_ULP_CLASS_HID_0bad] = 291, + [BNXT_ULP_CLASS_HID_1825] = 292, + [BNXT_ULP_CLASS_HID_2589] = 293, + [BNXT_ULP_CLASS_HID_3201] = 294, + [BNXT_ULP_CLASS_HID_2c45] = 295, + [BNXT_ULP_CLASS_HID_38dd] = 296, + [BNXT_ULP_CLASS_HID_3c7d] = 297, + [BNXT_ULP_CLASS_HID_48f5] = 298, + [BNXT_ULP_CLASS_HID_4239] = 299, + [BNXT_ULP_CLASS_HID_4eb1] = 300, + [BNXT_ULP_CLASS_HID_5c15] = 301, + [BNXT_ULP_CLASS_HID_0ba1] = 302, + [BNXT_ULP_CLASS_HID_05e5] = 303, + [BNXT_ULP_CLASS_HID_127d] = 304, + [BNXT_ULP_CLASS_HID_58a5] = 305, + [BNXT_ULP_CLASS_HID_08f1] = 306, + [BNXT_ULP_CLASS_HID_0235] = 307, + [BNXT_ULP_CLASS_HID_0e8d] = 308, + [BNXT_ULP_CLASS_HID_1c11] = 309, + [BNXT_ULP_CLASS_HID_28e9] = 310, + [BNXT_ULP_CLASS_HID_222d] = 311, + [BNXT_ULP_CLASS_HID_2ea5] = 312, + [BNXT_ULP_CLASS_HID_32c5] = 313, + [BNXT_ULP_CLASS_HID_3f5d] = 314, + [BNXT_ULP_CLASS_HID_3881] = 315, + [BNXT_ULP_CLASS_HID_4519] = 316, + [BNXT_ULP_CLASS_HID_52fd] = 317, + [BNXT_ULP_CLASS_HID_0209] = 318, + [BNXT_ULP_CLASS_HID_58b9] = 319, + [BNXT_ULP_CLASS_HID_08c5] = 320, + [BNXT_ULP_CLASS_HID_400a5] = 321, + [BNXT_ULP_CLASS_HID_40d3d] = 322, + [BNXT_ULP_CLASS_HID_40761] = 323, + [BNXT_ULP_CLASS_HID_413f9] = 324, + [BNXT_ULP_CLASS_HID_4215d] = 325, + [BNXT_ULP_CLASS_HID_42dd5] = 326, + [BNXT_ULP_CLASS_HID_42719] = 327, + [BNXT_ULP_CLASS_HID_43391] = 328, + [BNXT_ULP_CLASS_HID_43731] = 329, + [BNXT_ULP_CLASS_HID_44389] = 330, + [BNXT_ULP_CLASS_HID_43dcd] = 331, + [BNXT_ULP_CLASS_HID_44a45] = 332, + [BNXT_ULP_CLASS_HID_45729] = 333, + [BNXT_ULP_CLASS_HID_40775] = 334, + [BNXT_ULP_CLASS_HID_400b9] = 335, + [BNXT_ULP_CLASS_HID_40d31] = 336, + [BNXT_ULP_CLASS_HID_45479] = 337, + [BNXT_ULP_CLASS_HID_40385] = 338, + [BNXT_ULP_CLASS_HID_45a35] = 339, + [BNXT_ULP_CLASS_HID_40a41] = 340, + [BNXT_ULP_CLASS_HID_41725] = 341, + [BNXT_ULP_CLASS_HID_423bd] = 342, + [BNXT_ULP_CLASS_HID_41de1] = 343, + [BNXT_ULP_CLASS_HID_42a79] = 344, + [BNXT_ULP_CLASS_HID_42d99] = 345, + [BNXT_ULP_CLASS_HID_43a11] = 346, + [BNXT_ULP_CLASS_HID_43455] = 347, + [BNXT_ULP_CLASS_HID_4402d] = 348, + [BNXT_ULP_CLASS_HID_44db1] = 349, + [BNXT_ULP_CLASS_HID_45a09] = 350, + [BNXT_ULP_CLASS_HID_4544d] = 351, + [BNXT_ULP_CLASS_HID_40399] = 352, + [BNXT_ULP_CLASS_HID_4146d] = 353, + [BNXT_ULP_CLASS_HID_420d5] = 354, + [BNXT_ULP_CLASS_HID_41a29] = 355, + [BNXT_ULP_CLASS_HID_42691] = 356, + [BNXT_ULP_CLASS_HID_44ad9] = 357, + [BNXT_ULP_CLASS_HID_45741] = 358, + [BNXT_ULP_CLASS_HID_45085] = 359, + [BNXT_ULP_CLASS_HID_40031] = 360, + [BNXT_ULP_CLASS_HID_40ac5] = 361, + [BNXT_ULP_CLASS_HID_4174d] = 362, + [BNXT_ULP_CLASS_HID_41081] = 363, + [BNXT_ULP_CLASS_HID_41d09] = 364, + [BNXT_ULP_CLASS_HID_440b1] = 365, + [BNXT_ULP_CLASS_HID_44d39] = 366, + [BNXT_ULP_CLASS_HID_4477d] = 367, + [BNXT_ULP_CLASS_HID_453e5] = 368, + [BNXT_ULP_CLASS_HID_6406d] = 369, + [BNXT_ULP_CLASS_HID_64cd5] = 370, + [BNXT_ULP_CLASS_HID_64629] = 371, + [BNXT_ULP_CLASS_HID_65291] = 372, + [BNXT_ULP_CLASS_HID_6198d] = 373, + [BNXT_ULP_CLASS_HID_62675] = 374, + [BNXT_ULP_CLASS_HID_62049] = 375, + [BNXT_ULP_CLASS_HID_62c31] = 376, + [BNXT_ULP_CLASS_HID_636c5] = 377, + [BNXT_ULP_CLASS_HID_6434d] = 378, + [BNXT_ULP_CLASS_HID_63c81] = 379, + [BNXT_ULP_CLASS_HID_64909] = 380, + [BNXT_ULP_CLASS_HID_61065] = 381, + [BNXT_ULP_CLASS_HID_61ced] = 382, + [BNXT_ULP_CLASS_HID_61621] = 383, + [BNXT_ULP_CLASS_HID_622a9] = 384, + [BNXT_ULP_CLASS_HID_52a6d] = 385, + [BNXT_ULP_CLASS_HID_536d5] = 386, + [BNXT_ULP_CLASS_HID_53029] = 387, + [BNXT_ULP_CLASS_HID_53c91] = 388, + [BNXT_ULP_CLASS_HID_5038d] = 389, + [BNXT_ULP_CLASS_HID_51075] = 390, + [BNXT_ULP_CLASS_HID_50a49] = 391, + [BNXT_ULP_CLASS_HID_51631] = 392, + [BNXT_ULP_CLASS_HID_520c5] = 393, + [BNXT_ULP_CLASS_HID_52d4d] = 394, + [BNXT_ULP_CLASS_HID_52681] = 395, + [BNXT_ULP_CLASS_HID_53309] = 396, + [BNXT_ULP_CLASS_HID_556b1] = 397, + [BNXT_ULP_CLASS_HID_506ed] = 398, + [BNXT_ULP_CLASS_HID_50021] = 399, + [BNXT_ULP_CLASS_HID_50ca9] = 400, + [BNXT_ULP_CLASS_HID_7566d] = 401, + [BNXT_ULP_CLASS_HID_70599] = 402, + [BNXT_ULP_CLASS_HID_75c29] = 403, + [BNXT_ULP_CLASS_HID_70c45] = 404, + [BNXT_ULP_CLASS_HID_72f8d] = 405, + [BNXT_ULP_CLASS_HID_73c75] = 406, + [BNXT_ULP_CLASS_HID_73649] = 407, + [BNXT_ULP_CLASS_HID_74231] = 408, + [BNXT_ULP_CLASS_HID_74cc5] = 409, + [BNXT_ULP_CLASS_HID_7594d] = 410, + [BNXT_ULP_CLASS_HID_75281] = 411, + [BNXT_ULP_CLASS_HID_7023d] = 412, + [BNXT_ULP_CLASS_HID_72665] = 413, + [BNXT_ULP_CLASS_HID_732ed] = 414, + [BNXT_ULP_CLASS_HID_72c21] = 415, + [BNXT_ULP_CLASS_HID_738a9] = 416, + [BNXT_ULP_CLASS_HID_244c3] = 417, + [BNXT_ULP_CLASS_HID_2515b] = 418, + [BNXT_ULP_CLASS_HID_24b1f] = 419, + [BNXT_ULP_CLASS_HID_25797] = 420, + [BNXT_ULP_CLASS_HID_22f7f] = 421, + [BNXT_ULP_CLASS_HID_23bf7] = 422, + [BNXT_ULP_CLASS_HID_235bb] = 423, + [BNXT_ULP_CLASS_HID_24233] = 424, + [BNXT_ULP_CLASS_HID_20b8b] = 425, + [BNXT_ULP_CLASS_HID_21803] = 426, + [BNXT_ULP_CLASS_HID_211c7] = 427, + [BNXT_ULP_CLASS_HID_21e5f] = 428, + [BNXT_ULP_CLASS_HID_252d3] = 429, + [BNXT_ULP_CLASS_HID_202bf] = 430, + [BNXT_ULP_CLASS_HID_2592f] = 431, + [BNXT_ULP_CLASS_HID_208fb] = 432, + [BNXT_ULP_CLASS_HID_231f3] = 433, + [BNXT_ULP_CLASS_HID_23e0b] = 434, + [BNXT_ULP_CLASS_HID_237cf] = 435, + [BNXT_ULP_CLASS_HID_24447] = 436, + [BNXT_ULP_CLASS_HID_21c2f] = 437, + [BNXT_ULP_CLASS_HID_228a7] = 438, + [BNXT_ULP_CLASS_HID_2226b] = 439, + [BNXT_ULP_CLASS_HID_22ee3] = 440, + [BNXT_ULP_CLASS_HID_25567] = 441, + [BNXT_ULP_CLASS_HID_20533] = 442, + [BNXT_ULP_CLASS_HID_25ba3] = 443, + [BNXT_ULP_CLASS_HID_20b0f] = 444, + [BNXT_ULP_CLASS_HID_23f83] = 445, + [BNXT_ULP_CLASS_HID_24c1b] = 446, + [BNXT_ULP_CLASS_HID_245df] = 447, + [BNXT_ULP_CLASS_HID_25257] = 448, + [BNXT_ULP_CLASS_HID_64017] = 449, + [BNXT_ULP_CLASS_HID_64caf] = 450, + [BNXT_ULP_CLASS_HID_64653] = 451, + [BNXT_ULP_CLASS_HID_652eb] = 452, + [BNXT_ULP_CLASS_HID_62ab3] = 453, + [BNXT_ULP_CLASS_HID_636cb] = 454, + [BNXT_ULP_CLASS_HID_6308f] = 455, + [BNXT_ULP_CLASS_HID_63d07] = 456, + [BNXT_ULP_CLASS_HID_606df] = 457, + [BNXT_ULP_CLASS_HID_61357] = 458, + [BNXT_ULP_CLASS_HID_60d1b] = 459, + [BNXT_ULP_CLASS_HID_61993] = 460, + [BNXT_ULP_CLASS_HID_64e27] = 461, + [BNXT_ULP_CLASS_HID_65abf] = 462, + [BNXT_ULP_CLASS_HID_65463] = 463, + [BNXT_ULP_CLASS_HID_603cf] = 464, + [BNXT_ULP_CLASS_HID_62cc7] = 465, + [BNXT_ULP_CLASS_HID_6395f] = 466, + [BNXT_ULP_CLASS_HID_63303] = 467, + [BNXT_ULP_CLASS_HID_63f9b] = 468, + [BNXT_ULP_CLASS_HID_61763] = 469, + [BNXT_ULP_CLASS_HID_623fb] = 470, + [BNXT_ULP_CLASS_HID_61dbf] = 471, + [BNXT_ULP_CLASS_HID_62a37] = 472, + [BNXT_ULP_CLASS_HID_650bb] = 473, + [BNXT_ULP_CLASS_HID_60007] = 474, + [BNXT_ULP_CLASS_HID_656f7] = 475, + [BNXT_ULP_CLASS_HID_60643] = 476, + [BNXT_ULP_CLASS_HID_63ad7] = 477, + [BNXT_ULP_CLASS_HID_6476f] = 478, + [BNXT_ULP_CLASS_HID_64113] = 479, + [BNXT_ULP_CLASS_HID_64dab] = 480, + [BNXT_ULP_CLASS_HID_35ac3] = 481, + [BNXT_ULP_CLASS_HID_30aaf] = 482, + [BNXT_ULP_CLASS_HID_30453] = 483, + [BNXT_ULP_CLASS_HID_310eb] = 484, + [BNXT_ULP_CLASS_HID_3457f] = 485, + [BNXT_ULP_CLASS_HID_351f7] = 486, + [BNXT_ULP_CLASS_HID_34bbb] = 487, + [BNXT_ULP_CLASS_HID_35833] = 488, + [BNXT_ULP_CLASS_HID_3218b] = 489, + [BNXT_ULP_CLASS_HID_32e03] = 490, + [BNXT_ULP_CLASS_HID_327c7] = 491, + [BNXT_ULP_CLASS_HID_3345f] = 492, + [BNXT_ULP_CLASS_HID_30c27] = 493, + [BNXT_ULP_CLASS_HID_318bf] = 494, + [BNXT_ULP_CLASS_HID_31263] = 495, + [BNXT_ULP_CLASS_HID_31efb] = 496, + [BNXT_ULP_CLASS_HID_347f3] = 497, + [BNXT_ULP_CLASS_HID_3540b] = 498, + [BNXT_ULP_CLASS_HID_34dcf] = 499, + [BNXT_ULP_CLASS_HID_35a47] = 500, + [BNXT_ULP_CLASS_HID_3322f] = 501, + [BNXT_ULP_CLASS_HID_33ea7] = 502, + [BNXT_ULP_CLASS_HID_3386b] = 503, + [BNXT_ULP_CLASS_HID_344e3] = 504, + [BNXT_ULP_CLASS_HID_30ebb] = 505, + [BNXT_ULP_CLASS_HID_31b33] = 506, + [BNXT_ULP_CLASS_HID_314f7] = 507, + [BNXT_ULP_CLASS_HID_3210f] = 508, + [BNXT_ULP_CLASS_HID_35583] = 509, + [BNXT_ULP_CLASS_HID_3056f] = 510, + [BNXT_ULP_CLASS_HID_35bdf] = 511, + [BNXT_ULP_CLASS_HID_30bab] = 512, + [BNXT_ULP_CLASS_HID_75617] = 513, + [BNXT_ULP_CLASS_HID_705e3] = 514, + [BNXT_ULP_CLASS_HID_75c53] = 515, + [BNXT_ULP_CLASS_HID_70c3f] = 516, + [BNXT_ULP_CLASS_HID_740b3] = 517, + [BNXT_ULP_CLASS_HID_74ccb] = 518, + [BNXT_ULP_CLASS_HID_7468f] = 519, + [BNXT_ULP_CLASS_HID_75307] = 520, + [BNXT_ULP_CLASS_HID_71cdf] = 521, + [BNXT_ULP_CLASS_HID_72957] = 522, + [BNXT_ULP_CLASS_HID_7231b] = 523, + [BNXT_ULP_CLASS_HID_72f93] = 524, + [BNXT_ULP_CLASS_HID_7077b] = 525, + [BNXT_ULP_CLASS_HID_713f3] = 526, + [BNXT_ULP_CLASS_HID_70db7] = 527, + [BNXT_ULP_CLASS_HID_719cf] = 528, + [BNXT_ULP_CLASS_HID_742c7] = 529, + [BNXT_ULP_CLASS_HID_74f5f] = 530, + [BNXT_ULP_CLASS_HID_74903] = 531, + [BNXT_ULP_CLASS_HID_7559b] = 532, + [BNXT_ULP_CLASS_HID_72d63] = 533, + [BNXT_ULP_CLASS_HID_739fb] = 534, + [BNXT_ULP_CLASS_HID_733bf] = 535, + [BNXT_ULP_CLASS_HID_74037] = 536, + [BNXT_ULP_CLASS_HID_7098f] = 537, + [BNXT_ULP_CLASS_HID_71607] = 538, + [BNXT_ULP_CLASS_HID_70fcb] = 539, + [BNXT_ULP_CLASS_HID_71c43] = 540, + [BNXT_ULP_CLASS_HID_750d7] = 541, + [BNXT_ULP_CLASS_HID_700a3] = 542, + [BNXT_ULP_CLASS_HID_75713] = 543, + [BNXT_ULP_CLASS_HID_706ff] = 544, + [BNXT_ULP_CLASS_HID_2cfc3] = 545, + [BNXT_ULP_CLASS_HID_2dc5b] = 546, + [BNXT_ULP_CLASS_HID_2d61f] = 547, + [BNXT_ULP_CLASS_HID_285eb] = 548, + [BNXT_ULP_CLASS_HID_2ba7f] = 549, + [BNXT_ULP_CLASS_HID_2c6f7] = 550, + [BNXT_ULP_CLASS_HID_2c0bb] = 551, + [BNXT_ULP_CLASS_HID_2cd33] = 552, + [BNXT_ULP_CLASS_HID_2968b] = 553, + [BNXT_ULP_CLASS_HID_2a303] = 554, + [BNXT_ULP_CLASS_HID_29cc7] = 555, + [BNXT_ULP_CLASS_HID_2a95f] = 556, + [BNXT_ULP_CLASS_HID_28127] = 557, + [BNXT_ULP_CLASS_HID_28dbf] = 558, + [BNXT_ULP_CLASS_HID_28763] = 559, + [BNXT_ULP_CLASS_HID_293fb] = 560, + [BNXT_ULP_CLASS_HID_2bcf3] = 561, + [BNXT_ULP_CLASS_HID_2c90b] = 562, + [BNXT_ULP_CLASS_HID_2c2cf] = 563, + [BNXT_ULP_CLASS_HID_2cf47] = 564, + [BNXT_ULP_CLASS_HID_2a72f] = 565, + [BNXT_ULP_CLASS_HID_2b3a7] = 566, + [BNXT_ULP_CLASS_HID_2ad6b] = 567, + [BNXT_ULP_CLASS_HID_2b9e3] = 568, + [BNXT_ULP_CLASS_HID_283bb] = 569, + [BNXT_ULP_CLASS_HID_29033] = 570, + [BNXT_ULP_CLASS_HID_289f7] = 571, + [BNXT_ULP_CLASS_HID_2960f] = 572, + [BNXT_ULP_CLASS_HID_2ca83] = 573, + [BNXT_ULP_CLASS_HID_2d71b] = 574, + [BNXT_ULP_CLASS_HID_2d0df] = 575, + [BNXT_ULP_CLASS_HID_280ab] = 576, + [BNXT_ULP_CLASS_HID_6cb17] = 577, + [BNXT_ULP_CLASS_HID_6d7af] = 578, + [BNXT_ULP_CLASS_HID_6d153] = 579, + [BNXT_ULP_CLASS_HID_6813f] = 580, + [BNXT_ULP_CLASS_HID_6b5b3] = 581, + [BNXT_ULP_CLASS_HID_6c1cb] = 582, + [BNXT_ULP_CLASS_HID_6bb8f] = 583, + [BNXT_ULP_CLASS_HID_6c807] = 584, + [BNXT_ULP_CLASS_HID_691df] = 585, + [BNXT_ULP_CLASS_HID_69e57] = 586, + [BNXT_ULP_CLASS_HID_6981b] = 587, + [BNXT_ULP_CLASS_HID_6a493] = 588, + [BNXT_ULP_CLASS_HID_6d927] = 589, + [BNXT_ULP_CLASS_HID_688f3] = 590, + [BNXT_ULP_CLASS_HID_682b7] = 591, + [BNXT_ULP_CLASS_HID_68ecf] = 592, + [BNXT_ULP_CLASS_HID_6b7c7] = 593, + [BNXT_ULP_CLASS_HID_6c45f] = 594, + [BNXT_ULP_CLASS_HID_6be03] = 595, + [BNXT_ULP_CLASS_HID_6ca9b] = 596, + [BNXT_ULP_CLASS_HID_6a263] = 597, + [BNXT_ULP_CLASS_HID_6aefb] = 598, + [BNXT_ULP_CLASS_HID_6a8bf] = 599, + [BNXT_ULP_CLASS_HID_6b537] = 600, + [BNXT_ULP_CLASS_HID_6dbbb] = 601, + [BNXT_ULP_CLASS_HID_68b07] = 602, + [BNXT_ULP_CLASS_HID_684cb] = 603, + [BNXT_ULP_CLASS_HID_69143] = 604, + [BNXT_ULP_CLASS_HID_6c5d7] = 605, + [BNXT_ULP_CLASS_HID_6d26f] = 606, + [BNXT_ULP_CLASS_HID_6cc13] = 607, + [BNXT_ULP_CLASS_HID_6d8ab] = 608, + [BNXT_ULP_CLASS_HID_38917] = 609, + [BNXT_ULP_CLASS_HID_395af] = 610, + [BNXT_ULP_CLASS_HID_38f53] = 611, + [BNXT_ULP_CLASS_HID_39beb] = 612, + [BNXT_ULP_CLASS_HID_3d07f] = 613, + [BNXT_ULP_CLASS_HID_3dcf7] = 614, + [BNXT_ULP_CLASS_HID_3d6bb] = 615, + [BNXT_ULP_CLASS_HID_38607] = 616, + [BNXT_ULP_CLASS_HID_3ac8b] = 617, + [BNXT_ULP_CLASS_HID_3b903] = 618, + [BNXT_ULP_CLASS_HID_3b2c7] = 619, + [BNXT_ULP_CLASS_HID_3bf5f] = 620, + [BNXT_ULP_CLASS_HID_39727] = 621, + [BNXT_ULP_CLASS_HID_3a3bf] = 622, + [BNXT_ULP_CLASS_HID_39d63] = 623, + [BNXT_ULP_CLASS_HID_3a9fb] = 624, + [BNXT_ULP_CLASS_HID_3d2f3] = 625, + [BNXT_ULP_CLASS_HID_3825f] = 626, + [BNXT_ULP_CLASS_HID_3d8cf] = 627, + [BNXT_ULP_CLASS_HID_3889b] = 628, + [BNXT_ULP_CLASS_HID_3bd2f] = 629, + [BNXT_ULP_CLASS_HID_3c9a7] = 630, + [BNXT_ULP_CLASS_HID_3c36b] = 631, + [BNXT_ULP_CLASS_HID_3cfe3] = 632, + [BNXT_ULP_CLASS_HID_399bb] = 633, + [BNXT_ULP_CLASS_HID_3a633] = 634, + [BNXT_ULP_CLASS_HID_39ff7] = 635, + [BNXT_ULP_CLASS_HID_3ac0f] = 636, + [BNXT_ULP_CLASS_HID_383d7] = 637, + [BNXT_ULP_CLASS_HID_3906f] = 638, + [BNXT_ULP_CLASS_HID_38a13] = 639, + [BNXT_ULP_CLASS_HID_396ab] = 640, + [BNXT_ULP_CLASS_HID_7846b] = 641, + [BNXT_ULP_CLASS_HID_790e3] = 642, + [BNXT_ULP_CLASS_HID_78aa7] = 643, + [BNXT_ULP_CLASS_HID_7973f] = 644, + [BNXT_ULP_CLASS_HID_7cbb3] = 645, + [BNXT_ULP_CLASS_HID_7d7cb] = 646, + [BNXT_ULP_CLASS_HID_7d18f] = 647, + [BNXT_ULP_CLASS_HID_7815b] = 648, + [BNXT_ULP_CLASS_HID_7a7df] = 649, + [BNXT_ULP_CLASS_HID_7b457] = 650, + [BNXT_ULP_CLASS_HID_7ae1b] = 651, + [BNXT_ULP_CLASS_HID_7ba93] = 652, + [BNXT_ULP_CLASS_HID_7927b] = 653, + [BNXT_ULP_CLASS_HID_79ef3] = 654, + [BNXT_ULP_CLASS_HID_798b7] = 655, + [BNXT_ULP_CLASS_HID_7a4cf] = 656, + [BNXT_ULP_CLASS_HID_7cdc7] = 657, + [BNXT_ULP_CLASS_HID_7da5f] = 658, + [BNXT_ULP_CLASS_HID_7d403] = 659, + [BNXT_ULP_CLASS_HID_783ef] = 660, + [BNXT_ULP_CLASS_HID_7b863] = 661, + [BNXT_ULP_CLASS_HID_7c4fb] = 662, + [BNXT_ULP_CLASS_HID_7bebf] = 663, + [BNXT_ULP_CLASS_HID_7cb37] = 664, + [BNXT_ULP_CLASS_HID_7948f] = 665, + [BNXT_ULP_CLASS_HID_7a107] = 666, + [BNXT_ULP_CLASS_HID_79acb] = 667, + [BNXT_ULP_CLASS_HID_7a743] = 668, + [BNXT_ULP_CLASS_HID_7dbd7] = 669, + [BNXT_ULP_CLASS_HID_78ba3] = 670, + [BNXT_ULP_CLASS_HID_78567] = 671, + [BNXT_ULP_CLASS_HID_791ff] = 672, + [BNXT_ULP_CLASS_HID_a3db] = 673, + [BNXT_ULP_CLASS_HID_b043] = 674, + [BNXT_ULP_CLASS_HID_aa07] = 675, + [BNXT_ULP_CLASS_HID_b68f] = 676, + [BNXT_ULP_CLASS_HID_8e67] = 677, + [BNXT_ULP_CLASS_HID_9aef] = 678, + [BNXT_ULP_CLASS_HID_94a3] = 679, + [BNXT_ULP_CLASS_HID_a12b] = 680, + [BNXT_ULP_CLASS_HID_c7af] = 681, + [BNXT_ULP_CLASS_HID_d3d7] = 682, + [BNXT_ULP_CLASS_HID_cdeb] = 683, + [BNXT_ULP_CLASS_HID_da13] = 684, + [BNXT_ULP_CLASS_HID_b1cb] = 685, + [BNXT_ULP_CLASS_HID_be73] = 686, + [BNXT_ULP_CLASS_HID_b837] = 687, + [BNXT_ULP_CLASS_HID_c4bf] = 688, + [BNXT_ULP_CLASS_HID_49f0f] = 689, + [BNXT_ULP_CLASS_HID_4abb7] = 690, + [BNXT_ULP_CLASS_HID_4a54b] = 691, + [BNXT_ULP_CLASS_HID_4b1f3] = 692, + [BNXT_ULP_CLASS_HID_489ab] = 693, + [BNXT_ULP_CLASS_HID_495d3] = 694, + [BNXT_ULP_CLASS_HID_48f97] = 695, + [BNXT_ULP_CLASS_HID_49c1f] = 696, + [BNXT_ULP_CLASS_HID_4c293] = 697, + [BNXT_ULP_CLASS_HID_4cf1b] = 698, + [BNXT_ULP_CLASS_HID_4c8df] = 699, + [BNXT_ULP_CLASS_HID_4d547] = 700, + [BNXT_ULP_CLASS_HID_4ad3f] = 701, + [BNXT_ULP_CLASS_HID_4b9a7] = 702, + [BNXT_ULP_CLASS_HID_4b37b] = 703, + [BNXT_ULP_CLASS_HID_4bfe3] = 704, + [BNXT_ULP_CLASS_HID_1b9db] = 705, + [BNXT_ULP_CLASS_HID_1c643] = 706, + [BNXT_ULP_CLASS_HID_1c007] = 707, + [BNXT_ULP_CLASS_HID_1cc8f] = 708, + [BNXT_ULP_CLASS_HID_1a467] = 709, + [BNXT_ULP_CLASS_HID_1b0ef] = 710, + [BNXT_ULP_CLASS_HID_1aaa3] = 711, + [BNXT_ULP_CLASS_HID_1b72b] = 712, + [BNXT_ULP_CLASS_HID_18093] = 713, + [BNXT_ULP_CLASS_HID_18d1b] = 714, + [BNXT_ULP_CLASS_HID_186df] = 715, + [BNXT_ULP_CLASS_HID_19347] = 716, + [BNXT_ULP_CLASS_HID_1c7cb] = 717, + [BNXT_ULP_CLASS_HID_1d473] = 718, + [BNXT_ULP_CLASS_HID_1ce37] = 719, + [BNXT_ULP_CLASS_HID_1dabf] = 720, + [BNXT_ULP_CLASS_HID_5b50f] = 721, + [BNXT_ULP_CLASS_HID_5c1b7] = 722, + [BNXT_ULP_CLASS_HID_5bb4b] = 723, + [BNXT_ULP_CLASS_HID_5c7f3] = 724, + [BNXT_ULP_CLASS_HID_59fab] = 725, + [BNXT_ULP_CLASS_HID_5abd3] = 726, + [BNXT_ULP_CLASS_HID_5a597] = 727, + [BNXT_ULP_CLASS_HID_5b21f] = 728, + [BNXT_ULP_CLASS_HID_5d893] = 729, + [BNXT_ULP_CLASS_HID_5884f] = 730, + [BNXT_ULP_CLASS_HID_58203] = 731, + [BNXT_ULP_CLASS_HID_58e8b] = 732, + [BNXT_ULP_CLASS_HID_5c33f] = 733, + [BNXT_ULP_CLASS_HID_5cfa7] = 734, + [BNXT_ULP_CLASS_HID_5c97b] = 735, + [BNXT_ULP_CLASS_HID_5d5e3] = 736, + [BNXT_ULP_CLASS_HID_e95b] = 737, + [BNXT_ULP_CLASS_HID_f5c3] = 738, + [BNXT_ULP_CLASS_HID_ef87] = 739, + [BNXT_ULP_CLASS_HID_fc0f] = 740, + [BNXT_ULP_CLASS_HID_d3e7] = 741, + [BNXT_ULP_CLASS_HID_e06f] = 742, + [BNXT_ULP_CLASS_HID_da23] = 743, + [BNXT_ULP_CLASS_HID_e6ab] = 744, + [BNXT_ULP_CLASS_HID_cd2f] = 745, + [BNXT_ULP_CLASS_HID_d957] = 746, + [BNXT_ULP_CLASS_HID_d36b] = 747, + [BNXT_ULP_CLASS_HID_c2c7] = 748, + [BNXT_ULP_CLASS_HID_f74b] = 749, + [BNXT_ULP_CLASS_HID_c3f3] = 750, + [BNXT_ULP_CLASS_HID_fdb7] = 751, + [BNXT_ULP_CLASS_HID_ca3f] = 752, + [BNXT_ULP_CLASS_HID_4e48f] = 753, + [BNXT_ULP_CLASS_HID_4f137] = 754, + [BNXT_ULP_CLASS_HID_4eacb] = 755, + [BNXT_ULP_CLASS_HID_4f773] = 756, + [BNXT_ULP_CLASS_HID_4cf2b] = 757, + [BNXT_ULP_CLASS_HID_4db53] = 758, + [BNXT_ULP_CLASS_HID_4d517] = 759, + [BNXT_ULP_CLASS_HID_4e19f] = 760, + [BNXT_ULP_CLASS_HID_4c813] = 761, + [BNXT_ULP_CLASS_HID_4d49b] = 762, + [BNXT_ULP_CLASS_HID_4ce5f] = 763, + [BNXT_ULP_CLASS_HID_4dac7] = 764, + [BNXT_ULP_CLASS_HID_4f2bf] = 765, + [BNXT_ULP_CLASS_HID_4ff27] = 766, + [BNXT_ULP_CLASS_HID_4f8fb] = 767, + [BNXT_ULP_CLASS_HID_4c563] = 768, + [BNXT_ULP_CLASS_HID_1ff5b] = 769, + [BNXT_ULP_CLASS_HID_1cbc3] = 770, + [BNXT_ULP_CLASS_HID_1c587] = 771, + [BNXT_ULP_CLASS_HID_1d20f] = 772, + [BNXT_ULP_CLASS_HID_1e9e7] = 773, + [BNXT_ULP_CLASS_HID_1f66f] = 774, + [BNXT_ULP_CLASS_HID_1f023] = 775, + [BNXT_ULP_CLASS_HID_1fcab] = 776, + [BNXT_ULP_CLASS_HID_1c613] = 777, + [BNXT_ULP_CLASS_HID_1d29b] = 778, + [BNXT_ULP_CLASS_HID_1cc5f] = 779, + [BNXT_ULP_CLASS_HID_1d8c7] = 780, + [BNXT_ULP_CLASS_HID_1cd4b] = 781, + [BNXT_ULP_CLASS_HID_1d9f3] = 782, + [BNXT_ULP_CLASS_HID_1d3b7] = 783, + [BNXT_ULP_CLASS_HID_1c363] = 784, + [BNXT_ULP_CLASS_HID_5fa8f] = 785, + [BNXT_ULP_CLASS_HID_5c737] = 786, + [BNXT_ULP_CLASS_HID_5c0cb] = 787, + [BNXT_ULP_CLASS_HID_5cd73] = 788, + [BNXT_ULP_CLASS_HID_5e52b] = 789, + [BNXT_ULP_CLASS_HID_5f153] = 790, + [BNXT_ULP_CLASS_HID_5eb17] = 791, + [BNXT_ULP_CLASS_HID_5f79f] = 792, + [BNXT_ULP_CLASS_HID_5c147] = 793, + [BNXT_ULP_CLASS_HID_5cdcf] = 794, + [BNXT_ULP_CLASS_HID_5c783] = 795, + [BNXT_ULP_CLASS_HID_5d40b] = 796, + [BNXT_ULP_CLASS_HID_5c8bf] = 797, + [BNXT_ULP_CLASS_HID_5d527] = 798, + [BNXT_ULP_CLASS_HID_5cefb] = 799, + [BNXT_ULP_CLASS_HID_5db63] = 800, + [BNXT_ULP_CLASS_HID_a69b] = 801, + [BNXT_ULP_CLASS_HID_b303] = 802, + [BNXT_ULP_CLASS_HID_acc7] = 803, + [BNXT_ULP_CLASS_HID_b94f] = 804, + [BNXT_ULP_CLASS_HID_b127] = 805, + [BNXT_ULP_CLASS_HID_bdaf] = 806, + [BNXT_ULP_CLASS_HID_b763] = 807, + [BNXT_ULP_CLASS_HID_a3eb] = 808, + [BNXT_ULP_CLASS_HID_ea6f] = 809, + [BNXT_ULP_CLASS_HID_f697] = 810, + [BNXT_ULP_CLASS_HID_f0ab] = 811, + [BNXT_ULP_CLASS_HID_a007] = 812, + [BNXT_ULP_CLASS_HID_b48b] = 813, + [BNXT_ULP_CLASS_HID_e133] = 814, + [BNXT_ULP_CLASS_HID_baf7] = 815, + [BNXT_ULP_CLASS_HID_e77f] = 816, + [BNXT_ULP_CLASS_HID_4a1cf] = 817, + [BNXT_ULP_CLASS_HID_4ae77] = 818, + [BNXT_ULP_CLASS_HID_4a80b] = 819, + [BNXT_ULP_CLASS_HID_4b4b3] = 820, + [BNXT_ULP_CLASS_HID_4ac6b] = 821, + [BNXT_ULP_CLASS_HID_4b893] = 822, + [BNXT_ULP_CLASS_HID_4b257] = 823, + [BNXT_ULP_CLASS_HID_4bedf] = 824, + [BNXT_ULP_CLASS_HID_4e553] = 825, + [BNXT_ULP_CLASS_HID_4f1db] = 826, + [BNXT_ULP_CLASS_HID_4eb9f] = 827, + [BNXT_ULP_CLASS_HID_4f807] = 828, + [BNXT_ULP_CLASS_HID_4afff] = 829, + [BNXT_ULP_CLASS_HID_4bc67] = 830, + [BNXT_ULP_CLASS_HID_4b63b] = 831, + [BNXT_ULP_CLASS_HID_4e2a3] = 832, + [BNXT_ULP_CLASS_HID_1bc9b] = 833, + [BNXT_ULP_CLASS_HID_1e903] = 834, + [BNXT_ULP_CLASS_HID_1e2c7] = 835, + [BNXT_ULP_CLASS_HID_1ef4f] = 836, + [BNXT_ULP_CLASS_HID_1a727] = 837, + [BNXT_ULP_CLASS_HID_1b3af] = 838, + [BNXT_ULP_CLASS_HID_1ad63] = 839, + [BNXT_ULP_CLASS_HID_1b9eb] = 840, + [BNXT_ULP_CLASS_HID_1a353] = 841, + [BNXT_ULP_CLASS_HID_1afdb] = 842, + [BNXT_ULP_CLASS_HID_1a99f] = 843, + [BNXT_ULP_CLASS_HID_1b607] = 844, + [BNXT_ULP_CLASS_HID_1ea8b] = 845, + [BNXT_ULP_CLASS_HID_1f733] = 846, + [BNXT_ULP_CLASS_HID_1f0f7] = 847, + [BNXT_ULP_CLASS_HID_1a0a3] = 848, + [BNXT_ULP_CLASS_HID_5b7cf] = 849, + [BNXT_ULP_CLASS_HID_5e477] = 850, + [BNXT_ULP_CLASS_HID_5be0b] = 851, + [BNXT_ULP_CLASS_HID_5eab3] = 852, + [BNXT_ULP_CLASS_HID_5a26b] = 853, + [BNXT_ULP_CLASS_HID_5ae93] = 854, + [BNXT_ULP_CLASS_HID_5a857] = 855, + [BNXT_ULP_CLASS_HID_5b4df] = 856, + [BNXT_ULP_CLASS_HID_5fb53] = 857, + [BNXT_ULP_CLASS_HID_5ab0f] = 858, + [BNXT_ULP_CLASS_HID_5a4c3] = 859, + [BNXT_ULP_CLASS_HID_5b14b] = 860, + [BNXT_ULP_CLASS_HID_5e5ff] = 861, + [BNXT_ULP_CLASS_HID_5f267] = 862, + [BNXT_ULP_CLASS_HID_5ec3b] = 863, + [BNXT_ULP_CLASS_HID_5f8a3] = 864, + [BNXT_ULP_CLASS_HID_ec1b] = 865, + [BNXT_ULP_CLASS_HID_f883] = 866, + [BNXT_ULP_CLASS_HID_f247] = 867, + [BNXT_ULP_CLASS_HID_fecf] = 868, + [BNXT_ULP_CLASS_HID_f6a7] = 869, + [BNXT_ULP_CLASS_HID_e32f] = 870, + [BNXT_ULP_CLASS_HID_fce3] = 871, + [BNXT_ULP_CLASS_HID_e96b] = 872, + [BNXT_ULP_CLASS_HID_efef] = 873, + [BNXT_ULP_CLASS_HID_fc17] = 874, + [BNXT_ULP_CLASS_HID_f62b] = 875, + [BNXT_ULP_CLASS_HID_e587] = 876, + [BNXT_ULP_CLASS_HID_fa0b] = 877, + [BNXT_ULP_CLASS_HID_e6b3] = 878, + [BNXT_ULP_CLASS_HID_e077] = 879, + [BNXT_ULP_CLASS_HID_ecff] = 880, + [BNXT_ULP_CLASS_HID_4e74f] = 881, + [BNXT_ULP_CLASS_HID_4f3f7] = 882, + [BNXT_ULP_CLASS_HID_4ed8b] = 883, + [BNXT_ULP_CLASS_HID_4fa33] = 884, + [BNXT_ULP_CLASS_HID_4f1eb] = 885, + [BNXT_ULP_CLASS_HID_4fe13] = 886, + [BNXT_ULP_CLASS_HID_4f7d7] = 887, + [BNXT_ULP_CLASS_HID_4e45f] = 888, + [BNXT_ULP_CLASS_HID_4ead3] = 889, + [BNXT_ULP_CLASS_HID_4f75b] = 890, + [BNXT_ULP_CLASS_HID_4f11f] = 891, + [BNXT_ULP_CLASS_HID_4e0cb] = 892, + [BNXT_ULP_CLASS_HID_4f57f] = 893, + [BNXT_ULP_CLASS_HID_4e1e7] = 894, + [BNXT_ULP_CLASS_HID_4fbbb] = 895, + [BNXT_ULP_CLASS_HID_4e823] = 896, + [BNXT_ULP_CLASS_HID_1e21b] = 897, + [BNXT_ULP_CLASS_HID_1ee83] = 898, + [BNXT_ULP_CLASS_HID_1e847] = 899, + [BNXT_ULP_CLASS_HID_1f4cf] = 900, + [BNXT_ULP_CLASS_HID_1eca7] = 901, + [BNXT_ULP_CLASS_HID_1f92f] = 902, + [BNXT_ULP_CLASS_HID_1f2e3] = 903, + [BNXT_ULP_CLASS_HID_1ff6b] = 904, + [BNXT_ULP_CLASS_HID_1e8d3] = 905, + [BNXT_ULP_CLASS_HID_1f55b] = 906, + [BNXT_ULP_CLASS_HID_1ef1f] = 907, + [BNXT_ULP_CLASS_HID_1fb87] = 908, + [BNXT_ULP_CLASS_HID_1f00b] = 909, + [BNXT_ULP_CLASS_HID_1fcb3] = 910, + [BNXT_ULP_CLASS_HID_1f677] = 911, + [BNXT_ULP_CLASS_HID_1e623] = 912, + [BNXT_ULP_CLASS_HID_5fd4f] = 913, + [BNXT_ULP_CLASS_HID_5e9f7] = 914, + [BNXT_ULP_CLASS_HID_5e38b] = 915, + [BNXT_ULP_CLASS_HID_5f033] = 916, + [BNXT_ULP_CLASS_HID_5e7eb] = 917, + [BNXT_ULP_CLASS_HID_5f413] = 918, + [BNXT_ULP_CLASS_HID_5edd7] = 919, + [BNXT_ULP_CLASS_HID_5fa5f] = 920, + [BNXT_ULP_CLASS_HID_5e407] = 921, + [BNXT_ULP_CLASS_HID_5f08f] = 922, + [BNXT_ULP_CLASS_HID_5ea43] = 923, + [BNXT_ULP_CLASS_HID_5f6cb] = 924, + [BNXT_ULP_CLASS_HID_5eb7f] = 925, + [BNXT_ULP_CLASS_HID_5f7e7] = 926, + [BNXT_ULP_CLASS_HID_5f1bb] = 927, + [BNXT_ULP_CLASS_HID_5e117] = 928, + [BNXT_ULP_CLASS_HID_244a3] = 929, + [BNXT_ULP_CLASS_HID_2513b] = 930, + [BNXT_ULP_CLASS_HID_24b7f] = 931, + [BNXT_ULP_CLASS_HID_257f7] = 932, + [BNXT_ULP_CLASS_HID_22f1f] = 933, + [BNXT_ULP_CLASS_HID_23b97] = 934, + [BNXT_ULP_CLASS_HID_235db] = 935, + [BNXT_ULP_CLASS_HID_24253] = 936, + [BNXT_ULP_CLASS_HID_20beb] = 937, + [BNXT_ULP_CLASS_HID_21863] = 938, + [BNXT_ULP_CLASS_HID_211a7] = 939, + [BNXT_ULP_CLASS_HID_21e3f] = 940, + [BNXT_ULP_CLASS_HID_252b3] = 941, + [BNXT_ULP_CLASS_HID_202df] = 942, + [BNXT_ULP_CLASS_HID_2594f] = 943, + [BNXT_ULP_CLASS_HID_2089b] = 944, + [BNXT_ULP_CLASS_HID_23193] = 945, + [BNXT_ULP_CLASS_HID_23e6b] = 946, + [BNXT_ULP_CLASS_HID_237af] = 947, + [BNXT_ULP_CLASS_HID_24427] = 948, + [BNXT_ULP_CLASS_HID_21c4f] = 949, + [BNXT_ULP_CLASS_HID_228c7] = 950, + [BNXT_ULP_CLASS_HID_2220b] = 951, + [BNXT_ULP_CLASS_HID_22e83] = 952, + [BNXT_ULP_CLASS_HID_25507] = 953, + [BNXT_ULP_CLASS_HID_20553] = 954, + [BNXT_ULP_CLASS_HID_25bc3] = 955, + [BNXT_ULP_CLASS_HID_20b6f] = 956, + [BNXT_ULP_CLASS_HID_23fe3] = 957, + [BNXT_ULP_CLASS_HID_24c7b] = 958, + [BNXT_ULP_CLASS_HID_245bf] = 959, + [BNXT_ULP_CLASS_HID_25237] = 960, + [BNXT_ULP_CLASS_HID_64077] = 961, + [BNXT_ULP_CLASS_HID_64ccf] = 962, + [BNXT_ULP_CLASS_HID_64633] = 963, + [BNXT_ULP_CLASS_HID_6528b] = 964, + [BNXT_ULP_CLASS_HID_62ad3] = 965, + [BNXT_ULP_CLASS_HID_636ab] = 966, + [BNXT_ULP_CLASS_HID_630ef] = 967, + [BNXT_ULP_CLASS_HID_63d67] = 968, + [BNXT_ULP_CLASS_HID_606bf] = 969, + [BNXT_ULP_CLASS_HID_61337] = 970, + [BNXT_ULP_CLASS_HID_60d7b] = 971, + [BNXT_ULP_CLASS_HID_619f3] = 972, + [BNXT_ULP_CLASS_HID_64e47] = 973, + [BNXT_ULP_CLASS_HID_65adf] = 974, + [BNXT_ULP_CLASS_HID_65403] = 975, + [BNXT_ULP_CLASS_HID_603af] = 976, + [BNXT_ULP_CLASS_HID_62ca7] = 977, + [BNXT_ULP_CLASS_HID_6393f] = 978, + [BNXT_ULP_CLASS_HID_63363] = 979, + [BNXT_ULP_CLASS_HID_63ffb] = 980, + [BNXT_ULP_CLASS_HID_61703] = 981, + [BNXT_ULP_CLASS_HID_6239b] = 982, + [BNXT_ULP_CLASS_HID_61ddf] = 983, + [BNXT_ULP_CLASS_HID_62a57] = 984, + [BNXT_ULP_CLASS_HID_650db] = 985, + [BNXT_ULP_CLASS_HID_60067] = 986, + [BNXT_ULP_CLASS_HID_65697] = 987, + [BNXT_ULP_CLASS_HID_60623] = 988, + [BNXT_ULP_CLASS_HID_63ab7] = 989, + [BNXT_ULP_CLASS_HID_6470f] = 990, + [BNXT_ULP_CLASS_HID_64173] = 991, + [BNXT_ULP_CLASS_HID_64dcb] = 992, + [BNXT_ULP_CLASS_HID_35aa3] = 993, + [BNXT_ULP_CLASS_HID_30acf] = 994, + [BNXT_ULP_CLASS_HID_30433] = 995, + [BNXT_ULP_CLASS_HID_3108b] = 996, + [BNXT_ULP_CLASS_HID_3451f] = 997, + [BNXT_ULP_CLASS_HID_35197] = 998, + [BNXT_ULP_CLASS_HID_34bdb] = 999, + [BNXT_ULP_CLASS_HID_35853] = 1000, + [BNXT_ULP_CLASS_HID_321eb] = 1001, + [BNXT_ULP_CLASS_HID_32e63] = 1002, + [BNXT_ULP_CLASS_HID_327a7] = 1003, + [BNXT_ULP_CLASS_HID_3343f] = 1004, + [BNXT_ULP_CLASS_HID_30c47] = 1005, + [BNXT_ULP_CLASS_HID_318df] = 1006, + [BNXT_ULP_CLASS_HID_31203] = 1007, + [BNXT_ULP_CLASS_HID_31e9b] = 1008, + [BNXT_ULP_CLASS_HID_34793] = 1009, + [BNXT_ULP_CLASS_HID_3546b] = 1010, + [BNXT_ULP_CLASS_HID_34daf] = 1011, + [BNXT_ULP_CLASS_HID_35a27] = 1012, + [BNXT_ULP_CLASS_HID_3324f] = 1013, + [BNXT_ULP_CLASS_HID_33ec7] = 1014, + [BNXT_ULP_CLASS_HID_3380b] = 1015, + [BNXT_ULP_CLASS_HID_34483] = 1016, + [BNXT_ULP_CLASS_HID_30edb] = 1017, + [BNXT_ULP_CLASS_HID_31b53] = 1018, + [BNXT_ULP_CLASS_HID_31497] = 1019, + [BNXT_ULP_CLASS_HID_3216f] = 1020, + [BNXT_ULP_CLASS_HID_355e3] = 1021, + [BNXT_ULP_CLASS_HID_3050f] = 1022, + [BNXT_ULP_CLASS_HID_35bbf] = 1023, + [BNXT_ULP_CLASS_HID_30bcb] = 1024, + [BNXT_ULP_CLASS_HID_75677] = 1025, + [BNXT_ULP_CLASS_HID_70583] = 1026, + [BNXT_ULP_CLASS_HID_75c33] = 1027, + [BNXT_ULP_CLASS_HID_70c5f] = 1028, + [BNXT_ULP_CLASS_HID_740d3] = 1029, + [BNXT_ULP_CLASS_HID_74cab] = 1030, + [BNXT_ULP_CLASS_HID_746ef] = 1031, + [BNXT_ULP_CLASS_HID_75367] = 1032, + [BNXT_ULP_CLASS_HID_71cbf] = 1033, + [BNXT_ULP_CLASS_HID_72937] = 1034, + [BNXT_ULP_CLASS_HID_7237b] = 1035, + [BNXT_ULP_CLASS_HID_72ff3] = 1036, + [BNXT_ULP_CLASS_HID_7071b] = 1037, + [BNXT_ULP_CLASS_HID_71393] = 1038, + [BNXT_ULP_CLASS_HID_70dd7] = 1039, + [BNXT_ULP_CLASS_HID_719af] = 1040, + [BNXT_ULP_CLASS_HID_742a7] = 1041, + [BNXT_ULP_CLASS_HID_74f3f] = 1042, + [BNXT_ULP_CLASS_HID_74963] = 1043, + [BNXT_ULP_CLASS_HID_755fb] = 1044, + [BNXT_ULP_CLASS_HID_72d03] = 1045, + [BNXT_ULP_CLASS_HID_7399b] = 1046, + [BNXT_ULP_CLASS_HID_733df] = 1047, + [BNXT_ULP_CLASS_HID_74057] = 1048, + [BNXT_ULP_CLASS_HID_709ef] = 1049, + [BNXT_ULP_CLASS_HID_71667] = 1050, + [BNXT_ULP_CLASS_HID_70fab] = 1051, + [BNXT_ULP_CLASS_HID_71c23] = 1052, + [BNXT_ULP_CLASS_HID_750b7] = 1053, + [BNXT_ULP_CLASS_HID_700c3] = 1054, + [BNXT_ULP_CLASS_HID_75773] = 1055, + [BNXT_ULP_CLASS_HID_7069f] = 1056, + [BNXT_ULP_CLASS_HID_2cfa3] = 1057, + [BNXT_ULP_CLASS_HID_2dc3b] = 1058, + [BNXT_ULP_CLASS_HID_2d67f] = 1059, + [BNXT_ULP_CLASS_HID_2858b] = 1060, + [BNXT_ULP_CLASS_HID_2ba1f] = 1061, + [BNXT_ULP_CLASS_HID_2c697] = 1062, + [BNXT_ULP_CLASS_HID_2c0db] = 1063, + [BNXT_ULP_CLASS_HID_2cd53] = 1064, + [BNXT_ULP_CLASS_HID_296eb] = 1065, + [BNXT_ULP_CLASS_HID_2a363] = 1066, + [BNXT_ULP_CLASS_HID_29ca7] = 1067, + [BNXT_ULP_CLASS_HID_2a93f] = 1068, + [BNXT_ULP_CLASS_HID_28147] = 1069, + [BNXT_ULP_CLASS_HID_28ddf] = 1070, + [BNXT_ULP_CLASS_HID_28703] = 1071, + [BNXT_ULP_CLASS_HID_2939b] = 1072, + [BNXT_ULP_CLASS_HID_2bc93] = 1073, + [BNXT_ULP_CLASS_HID_2c96b] = 1074, + [BNXT_ULP_CLASS_HID_2c2af] = 1075, + [BNXT_ULP_CLASS_HID_2cf27] = 1076, + [BNXT_ULP_CLASS_HID_2a74f] = 1077, + [BNXT_ULP_CLASS_HID_2b3c7] = 1078, + [BNXT_ULP_CLASS_HID_2ad0b] = 1079, + [BNXT_ULP_CLASS_HID_2b983] = 1080, + [BNXT_ULP_CLASS_HID_283db] = 1081, + [BNXT_ULP_CLASS_HID_29053] = 1082, + [BNXT_ULP_CLASS_HID_28997] = 1083, + [BNXT_ULP_CLASS_HID_2966f] = 1084, + [BNXT_ULP_CLASS_HID_2cae3] = 1085, + [BNXT_ULP_CLASS_HID_2d77b] = 1086, + [BNXT_ULP_CLASS_HID_2d0bf] = 1087, + [BNXT_ULP_CLASS_HID_280cb] = 1088, + [BNXT_ULP_CLASS_HID_6cb77] = 1089, + [BNXT_ULP_CLASS_HID_6d7cf] = 1090, + [BNXT_ULP_CLASS_HID_6d133] = 1091, + [BNXT_ULP_CLASS_HID_6815f] = 1092, + [BNXT_ULP_CLASS_HID_6b5d3] = 1093, + [BNXT_ULP_CLASS_HID_6c1ab] = 1094, + [BNXT_ULP_CLASS_HID_6bbef] = 1095, + [BNXT_ULP_CLASS_HID_6c867] = 1096, + [BNXT_ULP_CLASS_HID_691bf] = 1097, + [BNXT_ULP_CLASS_HID_69e37] = 1098, + [BNXT_ULP_CLASS_HID_6987b] = 1099, + [BNXT_ULP_CLASS_HID_6a4f3] = 1100, + [BNXT_ULP_CLASS_HID_6d947] = 1101, + [BNXT_ULP_CLASS_HID_68893] = 1102, + [BNXT_ULP_CLASS_HID_682d7] = 1103, + [BNXT_ULP_CLASS_HID_68eaf] = 1104, + [BNXT_ULP_CLASS_HID_6b7a7] = 1105, + [BNXT_ULP_CLASS_HID_6c43f] = 1106, + [BNXT_ULP_CLASS_HID_6be63] = 1107, + [BNXT_ULP_CLASS_HID_6cafb] = 1108, + [BNXT_ULP_CLASS_HID_6a203] = 1109, + [BNXT_ULP_CLASS_HID_6ae9b] = 1110, + [BNXT_ULP_CLASS_HID_6a8df] = 1111, + [BNXT_ULP_CLASS_HID_6b557] = 1112, + [BNXT_ULP_CLASS_HID_6dbdb] = 1113, + [BNXT_ULP_CLASS_HID_68b67] = 1114, + [BNXT_ULP_CLASS_HID_684ab] = 1115, + [BNXT_ULP_CLASS_HID_69123] = 1116, + [BNXT_ULP_CLASS_HID_6c5b7] = 1117, + [BNXT_ULP_CLASS_HID_6d20f] = 1118, + [BNXT_ULP_CLASS_HID_6cc73] = 1119, + [BNXT_ULP_CLASS_HID_6d8cb] = 1120, + [BNXT_ULP_CLASS_HID_38977] = 1121, + [BNXT_ULP_CLASS_HID_395cf] = 1122, + [BNXT_ULP_CLASS_HID_38f33] = 1123, + [BNXT_ULP_CLASS_HID_39b8b] = 1124, + [BNXT_ULP_CLASS_HID_3d01f] = 1125, + [BNXT_ULP_CLASS_HID_3dc97] = 1126, + [BNXT_ULP_CLASS_HID_3d6db] = 1127, + [BNXT_ULP_CLASS_HID_38667] = 1128, + [BNXT_ULP_CLASS_HID_3aceb] = 1129, + [BNXT_ULP_CLASS_HID_3b963] = 1130, + [BNXT_ULP_CLASS_HID_3b2a7] = 1131, + [BNXT_ULP_CLASS_HID_3bf3f] = 1132, + [BNXT_ULP_CLASS_HID_39747] = 1133, + [BNXT_ULP_CLASS_HID_3a3df] = 1134, + [BNXT_ULP_CLASS_HID_39d03] = 1135, + [BNXT_ULP_CLASS_HID_3a99b] = 1136, + [BNXT_ULP_CLASS_HID_3d293] = 1137, + [BNXT_ULP_CLASS_HID_3823f] = 1138, + [BNXT_ULP_CLASS_HID_3d8af] = 1139, + [BNXT_ULP_CLASS_HID_388fb] = 1140, + [BNXT_ULP_CLASS_HID_3bd4f] = 1141, + [BNXT_ULP_CLASS_HID_3c9c7] = 1142, + [BNXT_ULP_CLASS_HID_3c30b] = 1143, + [BNXT_ULP_CLASS_HID_3cf83] = 1144, + [BNXT_ULP_CLASS_HID_399db] = 1145, + [BNXT_ULP_CLASS_HID_3a653] = 1146, + [BNXT_ULP_CLASS_HID_39f97] = 1147, + [BNXT_ULP_CLASS_HID_3ac6f] = 1148, + [BNXT_ULP_CLASS_HID_383b7] = 1149, + [BNXT_ULP_CLASS_HID_3900f] = 1150, + [BNXT_ULP_CLASS_HID_38a73] = 1151, + [BNXT_ULP_CLASS_HID_396cb] = 1152, + [BNXT_ULP_CLASS_HID_7840b] = 1153, + [BNXT_ULP_CLASS_HID_79083] = 1154, + [BNXT_ULP_CLASS_HID_78ac7] = 1155, + [BNXT_ULP_CLASS_HID_7975f] = 1156, + [BNXT_ULP_CLASS_HID_7cbd3] = 1157, + [BNXT_ULP_CLASS_HID_7d7ab] = 1158, + [BNXT_ULP_CLASS_HID_7d1ef] = 1159, + [BNXT_ULP_CLASS_HID_7813b] = 1160, + [BNXT_ULP_CLASS_HID_7a7bf] = 1161, + [BNXT_ULP_CLASS_HID_7b437] = 1162, + [BNXT_ULP_CLASS_HID_7ae7b] = 1163, + [BNXT_ULP_CLASS_HID_7baf3] = 1164, + [BNXT_ULP_CLASS_HID_7921b] = 1165, + [BNXT_ULP_CLASS_HID_79e93] = 1166, + [BNXT_ULP_CLASS_HID_798d7] = 1167, + [BNXT_ULP_CLASS_HID_7a4af] = 1168, + [BNXT_ULP_CLASS_HID_7cda7] = 1169, + [BNXT_ULP_CLASS_HID_7da3f] = 1170, + [BNXT_ULP_CLASS_HID_7d463] = 1171, + [BNXT_ULP_CLASS_HID_7838f] = 1172, + [BNXT_ULP_CLASS_HID_7b803] = 1173, + [BNXT_ULP_CLASS_HID_7c49b] = 1174, + [BNXT_ULP_CLASS_HID_7bedf] = 1175, + [BNXT_ULP_CLASS_HID_7cb57] = 1176, + [BNXT_ULP_CLASS_HID_794ef] = 1177, + [BNXT_ULP_CLASS_HID_7a167] = 1178, + [BNXT_ULP_CLASS_HID_79aab] = 1179, + [BNXT_ULP_CLASS_HID_7a723] = 1180, + [BNXT_ULP_CLASS_HID_7dbb7] = 1181, + [BNXT_ULP_CLASS_HID_78bc3] = 1182, + [BNXT_ULP_CLASS_HID_78507] = 1183, + [BNXT_ULP_CLASS_HID_7919f] = 1184, + [BNXT_ULP_CLASS_HID_a3bb] = 1185, + [BNXT_ULP_CLASS_HID_b023] = 1186, + [BNXT_ULP_CLASS_HID_aa67] = 1187, + [BNXT_ULP_CLASS_HID_b6ef] = 1188, + [BNXT_ULP_CLASS_HID_8e07] = 1189, + [BNXT_ULP_CLASS_HID_9a8f] = 1190, + [BNXT_ULP_CLASS_HID_94c3] = 1191, + [BNXT_ULP_CLASS_HID_a14b] = 1192, + [BNXT_ULP_CLASS_HID_c7cf] = 1193, + [BNXT_ULP_CLASS_HID_d3b7] = 1194, + [BNXT_ULP_CLASS_HID_cd8b] = 1195, + [BNXT_ULP_CLASS_HID_da73] = 1196, + [BNXT_ULP_CLASS_HID_b1ab] = 1197, + [BNXT_ULP_CLASS_HID_be13] = 1198, + [BNXT_ULP_CLASS_HID_b857] = 1199, + [BNXT_ULP_CLASS_HID_c4df] = 1200, + [BNXT_ULP_CLASS_HID_49f6f] = 1201, + [BNXT_ULP_CLASS_HID_4abd7] = 1202, + [BNXT_ULP_CLASS_HID_4a52b] = 1203, + [BNXT_ULP_CLASS_HID_4b193] = 1204, + [BNXT_ULP_CLASS_HID_489cb] = 1205, + [BNXT_ULP_CLASS_HID_495b3] = 1206, + [BNXT_ULP_CLASS_HID_48ff7] = 1207, + [BNXT_ULP_CLASS_HID_49c7f] = 1208, + [BNXT_ULP_CLASS_HID_4c2f3] = 1209, + [BNXT_ULP_CLASS_HID_4cf7b] = 1210, + [BNXT_ULP_CLASS_HID_4c8bf] = 1211, + [BNXT_ULP_CLASS_HID_4d527] = 1212, + [BNXT_ULP_CLASS_HID_4ad5f] = 1213, + [BNXT_ULP_CLASS_HID_4b9c7] = 1214, + [BNXT_ULP_CLASS_HID_4b31b] = 1215, + [BNXT_ULP_CLASS_HID_4bf83] = 1216, + [BNXT_ULP_CLASS_HID_1b9bb] = 1217, + [BNXT_ULP_CLASS_HID_1c623] = 1218, + [BNXT_ULP_CLASS_HID_1c067] = 1219, + [BNXT_ULP_CLASS_HID_1ccef] = 1220, + [BNXT_ULP_CLASS_HID_1a407] = 1221, + [BNXT_ULP_CLASS_HID_1b08f] = 1222, + [BNXT_ULP_CLASS_HID_1aac3] = 1223, + [BNXT_ULP_CLASS_HID_1b74b] = 1224, + [BNXT_ULP_CLASS_HID_180f3] = 1225, + [BNXT_ULP_CLASS_HID_18d7b] = 1226, + [BNXT_ULP_CLASS_HID_186bf] = 1227, + [BNXT_ULP_CLASS_HID_19327] = 1228, + [BNXT_ULP_CLASS_HID_1c7ab] = 1229, + [BNXT_ULP_CLASS_HID_1d413] = 1230, + [BNXT_ULP_CLASS_HID_1ce57] = 1231, + [BNXT_ULP_CLASS_HID_1dadf] = 1232, + [BNXT_ULP_CLASS_HID_5b56f] = 1233, + [BNXT_ULP_CLASS_HID_5c1d7] = 1234, + [BNXT_ULP_CLASS_HID_5bb2b] = 1235, + [BNXT_ULP_CLASS_HID_5c793] = 1236, + [BNXT_ULP_CLASS_HID_59fcb] = 1237, + [BNXT_ULP_CLASS_HID_5abb3] = 1238, + [BNXT_ULP_CLASS_HID_5a5f7] = 1239, + [BNXT_ULP_CLASS_HID_5b27f] = 1240, + [BNXT_ULP_CLASS_HID_5d8f3] = 1241, + [BNXT_ULP_CLASS_HID_5882f] = 1242, + [BNXT_ULP_CLASS_HID_58263] = 1243, + [BNXT_ULP_CLASS_HID_58eeb] = 1244, + [BNXT_ULP_CLASS_HID_5c35f] = 1245, + [BNXT_ULP_CLASS_HID_5cfc7] = 1246, + [BNXT_ULP_CLASS_HID_5c91b] = 1247, + [BNXT_ULP_CLASS_HID_5d583] = 1248, + [BNXT_ULP_CLASS_HID_e93b] = 1249, + [BNXT_ULP_CLASS_HID_f5a3] = 1250, + [BNXT_ULP_CLASS_HID_efe7] = 1251, + [BNXT_ULP_CLASS_HID_fc6f] = 1252, + [BNXT_ULP_CLASS_HID_d387] = 1253, + [BNXT_ULP_CLASS_HID_e00f] = 1254, + [BNXT_ULP_CLASS_HID_da43] = 1255, + [BNXT_ULP_CLASS_HID_e6cb] = 1256, + [BNXT_ULP_CLASS_HID_cd4f] = 1257, + [BNXT_ULP_CLASS_HID_d937] = 1258, + [BNXT_ULP_CLASS_HID_d30b] = 1259, + [BNXT_ULP_CLASS_HID_c2a7] = 1260, + [BNXT_ULP_CLASS_HID_f72b] = 1261, + [BNXT_ULP_CLASS_HID_c393] = 1262, + [BNXT_ULP_CLASS_HID_fdd7] = 1263, + [BNXT_ULP_CLASS_HID_ca5f] = 1264, + [BNXT_ULP_CLASS_HID_4e4ef] = 1265, + [BNXT_ULP_CLASS_HID_4f157] = 1266, + [BNXT_ULP_CLASS_HID_4eaab] = 1267, + [BNXT_ULP_CLASS_HID_4f713] = 1268, + [BNXT_ULP_CLASS_HID_4cf4b] = 1269, + [BNXT_ULP_CLASS_HID_4db33] = 1270, + [BNXT_ULP_CLASS_HID_4d577] = 1271, + [BNXT_ULP_CLASS_HID_4e1ff] = 1272, + [BNXT_ULP_CLASS_HID_4c873] = 1273, + [BNXT_ULP_CLASS_HID_4d4fb] = 1274, + [BNXT_ULP_CLASS_HID_4ce3f] = 1275, + [BNXT_ULP_CLASS_HID_4daa7] = 1276, + [BNXT_ULP_CLASS_HID_4f2df] = 1277, + [BNXT_ULP_CLASS_HID_4ff47] = 1278, + [BNXT_ULP_CLASS_HID_4f89b] = 1279, + [BNXT_ULP_CLASS_HID_4c503] = 1280, + [BNXT_ULP_CLASS_HID_1ff3b] = 1281, + [BNXT_ULP_CLASS_HID_1cba3] = 1282, + [BNXT_ULP_CLASS_HID_1c5e7] = 1283, + [BNXT_ULP_CLASS_HID_1d26f] = 1284, + [BNXT_ULP_CLASS_HID_1e987] = 1285, + [BNXT_ULP_CLASS_HID_1f60f] = 1286, + [BNXT_ULP_CLASS_HID_1f043] = 1287, + [BNXT_ULP_CLASS_HID_1fccb] = 1288, + [BNXT_ULP_CLASS_HID_1c673] = 1289, + [BNXT_ULP_CLASS_HID_1d2fb] = 1290, + [BNXT_ULP_CLASS_HID_1cc3f] = 1291, + [BNXT_ULP_CLASS_HID_1d8a7] = 1292, + [BNXT_ULP_CLASS_HID_1cd2b] = 1293, + [BNXT_ULP_CLASS_HID_1d993] = 1294, + [BNXT_ULP_CLASS_HID_1d3d7] = 1295, + [BNXT_ULP_CLASS_HID_1c303] = 1296, + [BNXT_ULP_CLASS_HID_5faef] = 1297, + [BNXT_ULP_CLASS_HID_5c757] = 1298, + [BNXT_ULP_CLASS_HID_5c0ab] = 1299, + [BNXT_ULP_CLASS_HID_5cd13] = 1300, + [BNXT_ULP_CLASS_HID_5e54b] = 1301, + [BNXT_ULP_CLASS_HID_5f133] = 1302, + [BNXT_ULP_CLASS_HID_5eb77] = 1303, + [BNXT_ULP_CLASS_HID_5f7ff] = 1304, + [BNXT_ULP_CLASS_HID_5c127] = 1305, + [BNXT_ULP_CLASS_HID_5cdaf] = 1306, + [BNXT_ULP_CLASS_HID_5c7e3] = 1307, + [BNXT_ULP_CLASS_HID_5d46b] = 1308, + [BNXT_ULP_CLASS_HID_5c8df] = 1309, + [BNXT_ULP_CLASS_HID_5d547] = 1310, + [BNXT_ULP_CLASS_HID_5ce9b] = 1311, + [BNXT_ULP_CLASS_HID_5db03] = 1312, + [BNXT_ULP_CLASS_HID_a6fb] = 1313, + [BNXT_ULP_CLASS_HID_b363] = 1314, + [BNXT_ULP_CLASS_HID_aca7] = 1315, + [BNXT_ULP_CLASS_HID_b92f] = 1316, + [BNXT_ULP_CLASS_HID_b147] = 1317, + [BNXT_ULP_CLASS_HID_bdcf] = 1318, + [BNXT_ULP_CLASS_HID_b703] = 1319, + [BNXT_ULP_CLASS_HID_a38b] = 1320, + [BNXT_ULP_CLASS_HID_ea0f] = 1321, + [BNXT_ULP_CLASS_HID_f6f7] = 1322, + [BNXT_ULP_CLASS_HID_f0cb] = 1323, + [BNXT_ULP_CLASS_HID_a067] = 1324, + [BNXT_ULP_CLASS_HID_b4eb] = 1325, + [BNXT_ULP_CLASS_HID_e153] = 1326, + [BNXT_ULP_CLASS_HID_ba97] = 1327, + [BNXT_ULP_CLASS_HID_e71f] = 1328, + [BNXT_ULP_CLASS_HID_4a1af] = 1329, + [BNXT_ULP_CLASS_HID_4ae17] = 1330, + [BNXT_ULP_CLASS_HID_4a86b] = 1331, + [BNXT_ULP_CLASS_HID_4b4d3] = 1332, + [BNXT_ULP_CLASS_HID_4ac0b] = 1333, + [BNXT_ULP_CLASS_HID_4b8f3] = 1334, + [BNXT_ULP_CLASS_HID_4b237] = 1335, + [BNXT_ULP_CLASS_HID_4bebf] = 1336, + [BNXT_ULP_CLASS_HID_4e533] = 1337, + [BNXT_ULP_CLASS_HID_4f1bb] = 1338, + [BNXT_ULP_CLASS_HID_4ebff] = 1339, + [BNXT_ULP_CLASS_HID_4f867] = 1340, + [BNXT_ULP_CLASS_HID_4af9f] = 1341, + [BNXT_ULP_CLASS_HID_4bc07] = 1342, + [BNXT_ULP_CLASS_HID_4b65b] = 1343, + [BNXT_ULP_CLASS_HID_4e2c3] = 1344, + [BNXT_ULP_CLASS_HID_1bcfb] = 1345, + [BNXT_ULP_CLASS_HID_1e963] = 1346, + [BNXT_ULP_CLASS_HID_1e2a7] = 1347, + [BNXT_ULP_CLASS_HID_1ef2f] = 1348, + [BNXT_ULP_CLASS_HID_1a747] = 1349, + [BNXT_ULP_CLASS_HID_1b3cf] = 1350, + [BNXT_ULP_CLASS_HID_1ad03] = 1351, + [BNXT_ULP_CLASS_HID_1b98b] = 1352, + [BNXT_ULP_CLASS_HID_1a333] = 1353, + [BNXT_ULP_CLASS_HID_1afbb] = 1354, + [BNXT_ULP_CLASS_HID_1a9ff] = 1355, + [BNXT_ULP_CLASS_HID_1b667] = 1356, + [BNXT_ULP_CLASS_HID_1eaeb] = 1357, + [BNXT_ULP_CLASS_HID_1f753] = 1358, + [BNXT_ULP_CLASS_HID_1f097] = 1359, + [BNXT_ULP_CLASS_HID_1a0c3] = 1360, + [BNXT_ULP_CLASS_HID_5b7af] = 1361, + [BNXT_ULP_CLASS_HID_5e417] = 1362, + [BNXT_ULP_CLASS_HID_5be6b] = 1363, + [BNXT_ULP_CLASS_HID_5ead3] = 1364, + [BNXT_ULP_CLASS_HID_5a20b] = 1365, + [BNXT_ULP_CLASS_HID_5aef3] = 1366, + [BNXT_ULP_CLASS_HID_5a837] = 1367, + [BNXT_ULP_CLASS_HID_5b4bf] = 1368, + [BNXT_ULP_CLASS_HID_5fb33] = 1369, + [BNXT_ULP_CLASS_HID_5ab6f] = 1370, + [BNXT_ULP_CLASS_HID_5a4a3] = 1371, + [BNXT_ULP_CLASS_HID_5b12b] = 1372, + [BNXT_ULP_CLASS_HID_5e59f] = 1373, + [BNXT_ULP_CLASS_HID_5f207] = 1374, + [BNXT_ULP_CLASS_HID_5ec5b] = 1375, + [BNXT_ULP_CLASS_HID_5f8c3] = 1376, + [BNXT_ULP_CLASS_HID_ec7b] = 1377, + [BNXT_ULP_CLASS_HID_f8e3] = 1378, + [BNXT_ULP_CLASS_HID_f227] = 1379, + [BNXT_ULP_CLASS_HID_feaf] = 1380, + [BNXT_ULP_CLASS_HID_f6c7] = 1381, + [BNXT_ULP_CLASS_HID_e34f] = 1382, + [BNXT_ULP_CLASS_HID_fc83] = 1383, + [BNXT_ULP_CLASS_HID_e90b] = 1384, + [BNXT_ULP_CLASS_HID_ef8f] = 1385, + [BNXT_ULP_CLASS_HID_fc77] = 1386, + [BNXT_ULP_CLASS_HID_f64b] = 1387, + [BNXT_ULP_CLASS_HID_e5e7] = 1388, + [BNXT_ULP_CLASS_HID_fa6b] = 1389, + [BNXT_ULP_CLASS_HID_e6d3] = 1390, + [BNXT_ULP_CLASS_HID_e017] = 1391, + [BNXT_ULP_CLASS_HID_ec9f] = 1392, + [BNXT_ULP_CLASS_HID_4e72f] = 1393, + [BNXT_ULP_CLASS_HID_4f397] = 1394, + [BNXT_ULP_CLASS_HID_4edeb] = 1395, + [BNXT_ULP_CLASS_HID_4fa53] = 1396, + [BNXT_ULP_CLASS_HID_4f18b] = 1397, + [BNXT_ULP_CLASS_HID_4fe73] = 1398, + [BNXT_ULP_CLASS_HID_4f7b7] = 1399, + [BNXT_ULP_CLASS_HID_4e43f] = 1400, + [BNXT_ULP_CLASS_HID_4eab3] = 1401, + [BNXT_ULP_CLASS_HID_4f73b] = 1402, + [BNXT_ULP_CLASS_HID_4f17f] = 1403, + [BNXT_ULP_CLASS_HID_4e0ab] = 1404, + [BNXT_ULP_CLASS_HID_4f51f] = 1405, + [BNXT_ULP_CLASS_HID_4e187] = 1406, + [BNXT_ULP_CLASS_HID_4fbdb] = 1407, + [BNXT_ULP_CLASS_HID_4e843] = 1408, + [BNXT_ULP_CLASS_HID_1e27b] = 1409, + [BNXT_ULP_CLASS_HID_1eee3] = 1410, + [BNXT_ULP_CLASS_HID_1e827] = 1411, + [BNXT_ULP_CLASS_HID_1f4af] = 1412, + [BNXT_ULP_CLASS_HID_1ecc7] = 1413, + [BNXT_ULP_CLASS_HID_1f94f] = 1414, + [BNXT_ULP_CLASS_HID_1f283] = 1415, + [BNXT_ULP_CLASS_HID_1ff0b] = 1416, + [BNXT_ULP_CLASS_HID_1e8b3] = 1417, + [BNXT_ULP_CLASS_HID_1f53b] = 1418, + [BNXT_ULP_CLASS_HID_1ef7f] = 1419, + [BNXT_ULP_CLASS_HID_1fbe7] = 1420, + [BNXT_ULP_CLASS_HID_1f06b] = 1421, + [BNXT_ULP_CLASS_HID_1fcd3] = 1422, + [BNXT_ULP_CLASS_HID_1f617] = 1423, + [BNXT_ULP_CLASS_HID_1e643] = 1424, + [BNXT_ULP_CLASS_HID_5fd2f] = 1425, + [BNXT_ULP_CLASS_HID_5e997] = 1426, + [BNXT_ULP_CLASS_HID_5e3eb] = 1427, + [BNXT_ULP_CLASS_HID_5f053] = 1428, + [BNXT_ULP_CLASS_HID_5e78b] = 1429, + [BNXT_ULP_CLASS_HID_5f473] = 1430, + [BNXT_ULP_CLASS_HID_5edb7] = 1431, + [BNXT_ULP_CLASS_HID_5fa3f] = 1432, + [BNXT_ULP_CLASS_HID_5e467] = 1433, + [BNXT_ULP_CLASS_HID_5f0ef] = 1434, + [BNXT_ULP_CLASS_HID_5ea23] = 1435, + [BNXT_ULP_CLASS_HID_5f6ab] = 1436, + [BNXT_ULP_CLASS_HID_5eb1f] = 1437, + [BNXT_ULP_CLASS_HID_5f787] = 1438, + [BNXT_ULP_CLASS_HID_5f1db] = 1439, + [BNXT_ULP_CLASS_HID_5e177] = 1440, + [BNXT_ULP_CLASS_HID_498d] = 1441, + [BNXT_ULP_CLASS_HID_4fc9] = 1442, + [BNXT_ULP_CLASS_HID_0cf9] = 1443, + [BNXT_ULP_CLASS_HID_1335] = 1444, + [BNXT_ULP_CLASS_HID_232d] = 1445, + [BNXT_ULP_CLASS_HID_2969] = 1446, + [BNXT_ULP_CLASS_HID_4345] = 1447, + [BNXT_ULP_CLASS_HID_4981] = 1448, + [BNXT_ULP_CLASS_HID_45809] = 1449, + [BNXT_ULP_CLASS_HID_40179] = 1450, + [BNXT_ULP_CLASS_HID_431a9] = 1451, + [BNXT_ULP_CLASS_HID_437d5] = 1452, + [BNXT_ULP_CLASS_HID_44e61] = 1453, + [BNXT_ULP_CLASS_HID_454ad] = 1454, + [BNXT_ULP_CLASS_HID_42801] = 1455, + [BNXT_ULP_CLASS_HID_42e4d] = 1456, + [BNXT_ULP_CLASS_HID_22c13] = 1457, + [BNXT_ULP_CLASS_HID_2322f] = 1458, + [BNXT_ULP_CLASS_HID_2164f] = 1459, + [BNXT_ULP_CLASS_HID_21c8b] = 1460, + [BNXT_ULP_CLASS_HID_24f87] = 1461, + [BNXT_ULP_CLASS_HID_255c3] = 1462, + [BNXT_ULP_CLASS_HID_239e3] = 1463, + [BNXT_ULP_CLASS_HID_2403f] = 1464, + [BNXT_ULP_CLASS_HID_218c3] = 1465, + [BNXT_ULP_CLASS_HID_21f1f] = 1466, + [BNXT_ULP_CLASS_HID_2033f] = 1467, + [BNXT_ULP_CLASS_HID_2097b] = 1468, + [BNXT_ULP_CLASS_HID_23c77] = 1469, + [BNXT_ULP_CLASS_HID_242b3] = 1470, + [BNXT_ULP_CLASS_HID_226d3] = 1471, + [BNXT_ULP_CLASS_HID_22cef] = 1472, + [BNXT_ULP_CLASS_HID_62727] = 1473, + [BNXT_ULP_CLASS_HID_62d63] = 1474, + [BNXT_ULP_CLASS_HID_61183] = 1475, + [BNXT_ULP_CLASS_HID_617df] = 1476, + [BNXT_ULP_CLASS_HID_64adb] = 1477, + [BNXT_ULP_CLASS_HID_65117] = 1478, + [BNXT_ULP_CLASS_HID_63537] = 1479, + [BNXT_ULP_CLASS_HID_63b73] = 1480, + [BNXT_ULP_CLASS_HID_61417] = 1481, + [BNXT_ULP_CLASS_HID_61a53] = 1482, + [BNXT_ULP_CLASS_HID_65b3f] = 1483, + [BNXT_ULP_CLASS_HID_6048f] = 1484, + [BNXT_ULP_CLASS_HID_6378b] = 1485, + [BNXT_ULP_CLASS_HID_63dc7] = 1486, + [BNXT_ULP_CLASS_HID_621e7] = 1487, + [BNXT_ULP_CLASS_HID_62823] = 1488, + [BNXT_ULP_CLASS_HID_8b0b] = 1489, + [BNXT_ULP_CLASS_HID_9137] = 1490, + [BNXT_ULP_CLASS_HID_d223] = 1491, + [BNXT_ULP_CLASS_HID_d86f] = 1492, + [BNXT_ULP_CLASS_HID_ae9f] = 1493, + [BNXT_ULP_CLASS_HID_b4db] = 1494, + [BNXT_ULP_CLASS_HID_98fb] = 1495, + [BNXT_ULP_CLASS_HID_9f27] = 1496, + [BNXT_ULP_CLASS_HID_4863f] = 1497, + [BNXT_ULP_CLASS_HID_48c7b] = 1498, + [BNXT_ULP_CLASS_HID_4cd57] = 1499, + [BNXT_ULP_CLASS_HID_4d393] = 1500, + [BNXT_ULP_CLASS_HID_4a9c3] = 1501, + [BNXT_ULP_CLASS_HID_4b00f] = 1502, + [BNXT_ULP_CLASS_HID_4942f] = 1503, + [BNXT_ULP_CLASS_HID_49a6b] = 1504, + [BNXT_ULP_CLASS_HID_1a10b] = 1505, + [BNXT_ULP_CLASS_HID_1a737] = 1506, + [BNXT_ULP_CLASS_HID_18b57] = 1507, + [BNXT_ULP_CLASS_HID_19193] = 1508, + [BNXT_ULP_CLASS_HID_1c49f] = 1509, + [BNXT_ULP_CLASS_HID_1cadb] = 1510, + [BNXT_ULP_CLASS_HID_1aefb] = 1511, + [BNXT_ULP_CLASS_HID_1b527] = 1512, + [BNXT_ULP_CLASS_HID_59c3f] = 1513, + [BNXT_ULP_CLASS_HID_5a27b] = 1514, + [BNXT_ULP_CLASS_HID_5869b] = 1515, + [BNXT_ULP_CLASS_HID_58cc7] = 1516, + [BNXT_ULP_CLASS_HID_5bfc3] = 1517, + [BNXT_ULP_CLASS_HID_5c60f] = 1518, + [BNXT_ULP_CLASS_HID_5aa2f] = 1519, + [BNXT_ULP_CLASS_HID_5b06b] = 1520, + [BNXT_ULP_CLASS_HID_49ad] = 1521, + [BNXT_ULP_CLASS_HID_4fe9] = 1522, + [BNXT_ULP_CLASS_HID_0cd9] = 1523, + [BNXT_ULP_CLASS_HID_1315] = 1524, + [BNXT_ULP_CLASS_HID_230d] = 1525, + [BNXT_ULP_CLASS_HID_2949] = 1526, + [BNXT_ULP_CLASS_HID_4365] = 1527, + [BNXT_ULP_CLASS_HID_49a1] = 1528, + [BNXT_ULP_CLASS_HID_4035] = 1529, + [BNXT_ULP_CLASS_HID_4671] = 1530, + [BNXT_ULP_CLASS_HID_0361] = 1531, + [BNXT_ULP_CLASS_HID_09bd] = 1532, + [BNXT_ULP_CLASS_HID_1995] = 1533, + [BNXT_ULP_CLASS_HID_1fd1] = 1534, + [BNXT_ULP_CLASS_HID_398d] = 1535, + [BNXT_ULP_CLASS_HID_3fc9] = 1536, + [BNXT_ULP_CLASS_HID_444e1] = 1537, + [BNXT_ULP_CLASS_HID_44b3d] = 1538, + [BNXT_ULP_CLASS_HID_4082d] = 1539, + [BNXT_ULP_CLASS_HID_40e69] = 1540, + [BNXT_ULP_CLASS_HID_41e41] = 1541, + [BNXT_ULP_CLASS_HID_4249d] = 1542, + [BNXT_ULP_CLASS_HID_43eb9] = 1543, + [BNXT_ULP_CLASS_HID_444f5] = 1544, + [BNXT_ULP_CLASS_HID_43b09] = 1545, + [BNXT_ULP_CLASS_HID_44145] = 1546, + [BNXT_ULP_CLASS_HID_45b61] = 1547, + [BNXT_ULP_CLASS_HID_404f1] = 1548, + [BNXT_ULP_CLASS_HID_414e9] = 1549, + [BNXT_ULP_CLASS_HID_41b25] = 1550, + [BNXT_ULP_CLASS_HID_434c1] = 1551, + [BNXT_ULP_CLASS_HID_43b1d] = 1552, + [BNXT_ULP_CLASS_HID_45829] = 1553, + [BNXT_ULP_CLASS_HID_40159] = 1554, + [BNXT_ULP_CLASS_HID_43189] = 1555, + [BNXT_ULP_CLASS_HID_437f5] = 1556, + [BNXT_ULP_CLASS_HID_44e41] = 1557, + [BNXT_ULP_CLASS_HID_4548d] = 1558, + [BNXT_ULP_CLASS_HID_42821] = 1559, + [BNXT_ULP_CLASS_HID_42e6d] = 1560, + [BNXT_ULP_CLASS_HID_6271d] = 1561, + [BNXT_ULP_CLASS_HID_62d59] = 1562, + [BNXT_ULP_CLASS_HID_600fd] = 1563, + [BNXT_ULP_CLASS_HID_60739] = 1564, + [BNXT_ULP_CLASS_HID_61db5] = 1565, + [BNXT_ULP_CLASS_HID_623f1] = 1566, + [BNXT_ULP_CLASS_HID_65421] = 1567, + [BNXT_ULP_CLASS_HID_65a6d] = 1568, + [BNXT_ULP_CLASS_HID_5111d] = 1569, + [BNXT_ULP_CLASS_HID_51759] = 1570, + [BNXT_ULP_CLASS_HID_54789] = 1571, + [BNXT_ULP_CLASS_HID_54df5] = 1572, + [BNXT_ULP_CLASS_HID_507b5] = 1573, + [BNXT_ULP_CLASS_HID_50df1] = 1574, + [BNXT_ULP_CLASS_HID_53e21] = 1575, + [BNXT_ULP_CLASS_HID_5446d] = 1576, + [BNXT_ULP_CLASS_HID_73d1d] = 1577, + [BNXT_ULP_CLASS_HID_74359] = 1578, + [BNXT_ULP_CLASS_HID_716fd] = 1579, + [BNXT_ULP_CLASS_HID_71d39] = 1580, + [BNXT_ULP_CLASS_HID_733b5] = 1581, + [BNXT_ULP_CLASS_HID_739f1] = 1582, + [BNXT_ULP_CLASS_HID_70d15] = 1583, + [BNXT_ULP_CLASS_HID_71351] = 1584, + [BNXT_ULP_CLASS_HID_49cd] = 1585, + [BNXT_ULP_CLASS_HID_4f89] = 1586, + [BNXT_ULP_CLASS_HID_0cb9] = 1587, + [BNXT_ULP_CLASS_HID_1375] = 1588, + [BNXT_ULP_CLASS_HID_236d] = 1589, + [BNXT_ULP_CLASS_HID_2929] = 1590, + [BNXT_ULP_CLASS_HID_4305] = 1591, + [BNXT_ULP_CLASS_HID_49c1] = 1592, + [BNXT_ULP_CLASS_HID_4055] = 1593, + [BNXT_ULP_CLASS_HID_4611] = 1594, + [BNXT_ULP_CLASS_HID_0301] = 1595, + [BNXT_ULP_CLASS_HID_09dd] = 1596, + [BNXT_ULP_CLASS_HID_19f5] = 1597, + [BNXT_ULP_CLASS_HID_1fb1] = 1598, + [BNXT_ULP_CLASS_HID_39ed] = 1599, + [BNXT_ULP_CLASS_HID_3fa9] = 1600, + [BNXT_ULP_CLASS_HID_44481] = 1601, + [BNXT_ULP_CLASS_HID_44b5d] = 1602, + [BNXT_ULP_CLASS_HID_4084d] = 1603, + [BNXT_ULP_CLASS_HID_40e09] = 1604, + [BNXT_ULP_CLASS_HID_41e21] = 1605, + [BNXT_ULP_CLASS_HID_424fd] = 1606, + [BNXT_ULP_CLASS_HID_43ed9] = 1607, + [BNXT_ULP_CLASS_HID_44495] = 1608, + [BNXT_ULP_CLASS_HID_43b69] = 1609, + [BNXT_ULP_CLASS_HID_44125] = 1610, + [BNXT_ULP_CLASS_HID_45b01] = 1611, + [BNXT_ULP_CLASS_HID_40491] = 1612, + [BNXT_ULP_CLASS_HID_41489] = 1613, + [BNXT_ULP_CLASS_HID_41b45] = 1614, + [BNXT_ULP_CLASS_HID_434a1] = 1615, + [BNXT_ULP_CLASS_HID_43b7d] = 1616, + [BNXT_ULP_CLASS_HID_45849] = 1617, + [BNXT_ULP_CLASS_HID_40139] = 1618, + [BNXT_ULP_CLASS_HID_431e9] = 1619, + [BNXT_ULP_CLASS_HID_43795] = 1620, + [BNXT_ULP_CLASS_HID_44e21] = 1621, + [BNXT_ULP_CLASS_HID_454ed] = 1622, + [BNXT_ULP_CLASS_HID_42841] = 1623, + [BNXT_ULP_CLASS_HID_42e0d] = 1624, + [BNXT_ULP_CLASS_HID_6277d] = 1625, + [BNXT_ULP_CLASS_HID_62d39] = 1626, + [BNXT_ULP_CLASS_HID_6009d] = 1627, + [BNXT_ULP_CLASS_HID_60759] = 1628, + [BNXT_ULP_CLASS_HID_61dd5] = 1629, + [BNXT_ULP_CLASS_HID_62391] = 1630, + [BNXT_ULP_CLASS_HID_65441] = 1631, + [BNXT_ULP_CLASS_HID_65a0d] = 1632, + [BNXT_ULP_CLASS_HID_5117d] = 1633, + [BNXT_ULP_CLASS_HID_51739] = 1634, + [BNXT_ULP_CLASS_HID_547e9] = 1635, + [BNXT_ULP_CLASS_HID_54d95] = 1636, + [BNXT_ULP_CLASS_HID_507d5] = 1637, + [BNXT_ULP_CLASS_HID_50d91] = 1638, + [BNXT_ULP_CLASS_HID_53e41] = 1639, + [BNXT_ULP_CLASS_HID_5440d] = 1640, + [BNXT_ULP_CLASS_HID_73d7d] = 1641, + [BNXT_ULP_CLASS_HID_74339] = 1642, + [BNXT_ULP_CLASS_HID_7169d] = 1643, + [BNXT_ULP_CLASS_HID_71d59] = 1644, + [BNXT_ULP_CLASS_HID_733d5] = 1645, + [BNXT_ULP_CLASS_HID_73991] = 1646, + [BNXT_ULP_CLASS_HID_70d75] = 1647, + [BNXT_ULP_CLASS_HID_71331] = 1648, + [BNXT_ULP_CLASS_HID_22c33] = 1649, + [BNXT_ULP_CLASS_HID_2320f] = 1650, + [BNXT_ULP_CLASS_HID_2166f] = 1651, + [BNXT_ULP_CLASS_HID_21cab] = 1652, + [BNXT_ULP_CLASS_HID_24fa7] = 1653, + [BNXT_ULP_CLASS_HID_255e3] = 1654, + [BNXT_ULP_CLASS_HID_239c3] = 1655, + [BNXT_ULP_CLASS_HID_2401f] = 1656, + [BNXT_ULP_CLASS_HID_218e3] = 1657, + [BNXT_ULP_CLASS_HID_21f3f] = 1658, + [BNXT_ULP_CLASS_HID_2031f] = 1659, + [BNXT_ULP_CLASS_HID_2095b] = 1660, + [BNXT_ULP_CLASS_HID_23c57] = 1661, + [BNXT_ULP_CLASS_HID_24293] = 1662, + [BNXT_ULP_CLASS_HID_226f3] = 1663, + [BNXT_ULP_CLASS_HID_22ccf] = 1664, + [BNXT_ULP_CLASS_HID_62707] = 1665, + [BNXT_ULP_CLASS_HID_62d43] = 1666, + [BNXT_ULP_CLASS_HID_611a3] = 1667, + [BNXT_ULP_CLASS_HID_617ff] = 1668, + [BNXT_ULP_CLASS_HID_64afb] = 1669, + [BNXT_ULP_CLASS_HID_65137] = 1670, + [BNXT_ULP_CLASS_HID_63517] = 1671, + [BNXT_ULP_CLASS_HID_63b53] = 1672, + [BNXT_ULP_CLASS_HID_61437] = 1673, + [BNXT_ULP_CLASS_HID_61a73] = 1674, + [BNXT_ULP_CLASS_HID_65b1f] = 1675, + [BNXT_ULP_CLASS_HID_604af] = 1676, + [BNXT_ULP_CLASS_HID_637ab] = 1677, + [BNXT_ULP_CLASS_HID_63de7] = 1678, + [BNXT_ULP_CLASS_HID_621c7] = 1679, + [BNXT_ULP_CLASS_HID_62803] = 1680, + [BNXT_ULP_CLASS_HID_34233] = 1681, + [BNXT_ULP_CLASS_HID_3480f] = 1682, + [BNXT_ULP_CLASS_HID_32c6f] = 1683, + [BNXT_ULP_CLASS_HID_332ab] = 1684, + [BNXT_ULP_CLASS_HID_308fb] = 1685, + [BNXT_ULP_CLASS_HID_30f37] = 1686, + [BNXT_ULP_CLASS_HID_34fc3] = 1687, + [BNXT_ULP_CLASS_HID_3561f] = 1688, + [BNXT_ULP_CLASS_HID_32ee3] = 1689, + [BNXT_ULP_CLASS_HID_3353f] = 1690, + [BNXT_ULP_CLASS_HID_3191f] = 1691, + [BNXT_ULP_CLASS_HID_31f5b] = 1692, + [BNXT_ULP_CLASS_HID_35257] = 1693, + [BNXT_ULP_CLASS_HID_35893] = 1694, + [BNXT_ULP_CLASS_HID_33cf3] = 1695, + [BNXT_ULP_CLASS_HID_342cf] = 1696, + [BNXT_ULP_CLASS_HID_73d07] = 1697, + [BNXT_ULP_CLASS_HID_74343] = 1698, + [BNXT_ULP_CLASS_HID_727a3] = 1699, + [BNXT_ULP_CLASS_HID_72dff] = 1700, + [BNXT_ULP_CLASS_HID_703cf] = 1701, + [BNXT_ULP_CLASS_HID_70a0b] = 1702, + [BNXT_ULP_CLASS_HID_74b17] = 1703, + [BNXT_ULP_CLASS_HID_75153] = 1704, + [BNXT_ULP_CLASS_HID_72a37] = 1705, + [BNXT_ULP_CLASS_HID_73073] = 1706, + [BNXT_ULP_CLASS_HID_71453] = 1707, + [BNXT_ULP_CLASS_HID_71aaf] = 1708, + [BNXT_ULP_CLASS_HID_74dab] = 1709, + [BNXT_ULP_CLASS_HID_753e7] = 1710, + [BNXT_ULP_CLASS_HID_737c7] = 1711, + [BNXT_ULP_CLASS_HID_73e03] = 1712, + [BNXT_ULP_CLASS_HID_2b733] = 1713, + [BNXT_ULP_CLASS_HID_2bd0f] = 1714, + [BNXT_ULP_CLASS_HID_2a16f] = 1715, + [BNXT_ULP_CLASS_HID_2a7ab] = 1716, + [BNXT_ULP_CLASS_HID_2daa7] = 1717, + [BNXT_ULP_CLASS_HID_28437] = 1718, + [BNXT_ULP_CLASS_HID_2c4c3] = 1719, + [BNXT_ULP_CLASS_HID_2cb1f] = 1720, + [BNXT_ULP_CLASS_HID_2a3e3] = 1721, + [BNXT_ULP_CLASS_HID_2aa3f] = 1722, + [BNXT_ULP_CLASS_HID_28e1f] = 1723, + [BNXT_ULP_CLASS_HID_2945b] = 1724, + [BNXT_ULP_CLASS_HID_2c757] = 1725, + [BNXT_ULP_CLASS_HID_2cd93] = 1726, + [BNXT_ULP_CLASS_HID_2b1f3] = 1727, + [BNXT_ULP_CLASS_HID_2b7cf] = 1728, + [BNXT_ULP_CLASS_HID_6b207] = 1729, + [BNXT_ULP_CLASS_HID_6b843] = 1730, + [BNXT_ULP_CLASS_HID_69ca3] = 1731, + [BNXT_ULP_CLASS_HID_6a2ff] = 1732, + [BNXT_ULP_CLASS_HID_6d5fb] = 1733, + [BNXT_ULP_CLASS_HID_6dc37] = 1734, + [BNXT_ULP_CLASS_HID_6c017] = 1735, + [BNXT_ULP_CLASS_HID_6c653] = 1736, + [BNXT_ULP_CLASS_HID_69f37] = 1737, + [BNXT_ULP_CLASS_HID_6a573] = 1738, + [BNXT_ULP_CLASS_HID_68953] = 1739, + [BNXT_ULP_CLASS_HID_68faf] = 1740, + [BNXT_ULP_CLASS_HID_6c2ab] = 1741, + [BNXT_ULP_CLASS_HID_6c8e7] = 1742, + [BNXT_ULP_CLASS_HID_6acc7] = 1743, + [BNXT_ULP_CLASS_HID_6b303] = 1744, + [BNXT_ULP_CLASS_HID_3cd33] = 1745, + [BNXT_ULP_CLASS_HID_3d30f] = 1746, + [BNXT_ULP_CLASS_HID_3b76f] = 1747, + [BNXT_ULP_CLASS_HID_3bdab] = 1748, + [BNXT_ULP_CLASS_HID_393fb] = 1749, + [BNXT_ULP_CLASS_HID_39a37] = 1750, + [BNXT_ULP_CLASS_HID_3dac3] = 1751, + [BNXT_ULP_CLASS_HID_38453] = 1752, + [BNXT_ULP_CLASS_HID_3b9e3] = 1753, + [BNXT_ULP_CLASS_HID_3c03f] = 1754, + [BNXT_ULP_CLASS_HID_3a41f] = 1755, + [BNXT_ULP_CLASS_HID_3aa5b] = 1756, + [BNXT_ULP_CLASS_HID_380ab] = 1757, + [BNXT_ULP_CLASS_HID_386e7] = 1758, + [BNXT_ULP_CLASS_HID_3c7f3] = 1759, + [BNXT_ULP_CLASS_HID_3cdcf] = 1760, + [BNXT_ULP_CLASS_HID_7c807] = 1761, + [BNXT_ULP_CLASS_HID_7ce43] = 1762, + [BNXT_ULP_CLASS_HID_7b2a3] = 1763, + [BNXT_ULP_CLASS_HID_7b8ff] = 1764, + [BNXT_ULP_CLASS_HID_78ecf] = 1765, + [BNXT_ULP_CLASS_HID_7950b] = 1766, + [BNXT_ULP_CLASS_HID_7d617] = 1767, + [BNXT_ULP_CLASS_HID_7dc53] = 1768, + [BNXT_ULP_CLASS_HID_7b537] = 1769, + [BNXT_ULP_CLASS_HID_7bb73] = 1770, + [BNXT_ULP_CLASS_HID_79f53] = 1771, + [BNXT_ULP_CLASS_HID_7a5af] = 1772, + [BNXT_ULP_CLASS_HID_7d8ab] = 1773, + [BNXT_ULP_CLASS_HID_7823b] = 1774, + [BNXT_ULP_CLASS_HID_7c2c7] = 1775, + [BNXT_ULP_CLASS_HID_7c903] = 1776, + [BNXT_ULP_CLASS_HID_8b2b] = 1777, + [BNXT_ULP_CLASS_HID_9117] = 1778, + [BNXT_ULP_CLASS_HID_d203] = 1779, + [BNXT_ULP_CLASS_HID_d84f] = 1780, + [BNXT_ULP_CLASS_HID_aebf] = 1781, + [BNXT_ULP_CLASS_HID_b4fb] = 1782, + [BNXT_ULP_CLASS_HID_98db] = 1783, + [BNXT_ULP_CLASS_HID_9f07] = 1784, + [BNXT_ULP_CLASS_HID_4861f] = 1785, + [BNXT_ULP_CLASS_HID_48c5b] = 1786, + [BNXT_ULP_CLASS_HID_4cd77] = 1787, + [BNXT_ULP_CLASS_HID_4d3b3] = 1788, + [BNXT_ULP_CLASS_HID_4a9e3] = 1789, + [BNXT_ULP_CLASS_HID_4b02f] = 1790, + [BNXT_ULP_CLASS_HID_4940f] = 1791, + [BNXT_ULP_CLASS_HID_49a4b] = 1792, + [BNXT_ULP_CLASS_HID_1a12b] = 1793, + [BNXT_ULP_CLASS_HID_1a717] = 1794, + [BNXT_ULP_CLASS_HID_18b77] = 1795, + [BNXT_ULP_CLASS_HID_191b3] = 1796, + [BNXT_ULP_CLASS_HID_1c4bf] = 1797, + [BNXT_ULP_CLASS_HID_1cafb] = 1798, + [BNXT_ULP_CLASS_HID_1aedb] = 1799, + [BNXT_ULP_CLASS_HID_1b507] = 1800, + [BNXT_ULP_CLASS_HID_59c1f] = 1801, + [BNXT_ULP_CLASS_HID_5a25b] = 1802, + [BNXT_ULP_CLASS_HID_586bb] = 1803, + [BNXT_ULP_CLASS_HID_58ce7] = 1804, + [BNXT_ULP_CLASS_HID_5bfe3] = 1805, + [BNXT_ULP_CLASS_HID_5c62f] = 1806, + [BNXT_ULP_CLASS_HID_5aa0f] = 1807, + [BNXT_ULP_CLASS_HID_5b04b] = 1808, + [BNXT_ULP_CLASS_HID_d0ab] = 1809, + [BNXT_ULP_CLASS_HID_d697] = 1810, + [BNXT_ULP_CLASS_HID_d783] = 1811, + [BNXT_ULP_CLASS_HID_c133] = 1812, + [BNXT_ULP_CLASS_HID_f43f] = 1813, + [BNXT_ULP_CLASS_HID_fa7b] = 1814, + [BNXT_ULP_CLASS_HID_de5b] = 1815, + [BNXT_ULP_CLASS_HID_e487] = 1816, + [BNXT_ULP_CLASS_HID_4cb9f] = 1817, + [BNXT_ULP_CLASS_HID_4d1db] = 1818, + [BNXT_ULP_CLASS_HID_4d2f7] = 1819, + [BNXT_ULP_CLASS_HID_4d933] = 1820, + [BNXT_ULP_CLASS_HID_4ef63] = 1821, + [BNXT_ULP_CLASS_HID_4f5af] = 1822, + [BNXT_ULP_CLASS_HID_4d98f] = 1823, + [BNXT_ULP_CLASS_HID_4dfcb] = 1824, + [BNXT_ULP_CLASS_HID_1e6ab] = 1825, + [BNXT_ULP_CLASS_HID_1ec97] = 1826, + [BNXT_ULP_CLASS_HID_1d0f7] = 1827, + [BNXT_ULP_CLASS_HID_1d733] = 1828, + [BNXT_ULP_CLASS_HID_1ca3f] = 1829, + [BNXT_ULP_CLASS_HID_1d07b] = 1830, + [BNXT_ULP_CLASS_HID_1f45b] = 1831, + [BNXT_ULP_CLASS_HID_1fa87] = 1832, + [BNXT_ULP_CLASS_HID_5e19f] = 1833, + [BNXT_ULP_CLASS_HID_5e7db] = 1834, + [BNXT_ULP_CLASS_HID_5cc3b] = 1835, + [BNXT_ULP_CLASS_HID_5d267] = 1836, + [BNXT_ULP_CLASS_HID_5c563] = 1837, + [BNXT_ULP_CLASS_HID_5cbaf] = 1838, + [BNXT_ULP_CLASS_HID_5ef8f] = 1839, + [BNXT_ULP_CLASS_HID_5f5cb] = 1840, + [BNXT_ULP_CLASS_HID_adeb] = 1841, + [BNXT_ULP_CLASS_HID_b3d7] = 1842, + [BNXT_ULP_CLASS_HID_f4c3] = 1843, + [BNXT_ULP_CLASS_HID_fb0f] = 1844, + [BNXT_ULP_CLASS_HID_b17f] = 1845, + [BNXT_ULP_CLASS_HID_b7bb] = 1846, + [BNXT_ULP_CLASS_HID_bb9b] = 1847, + [BNXT_ULP_CLASS_HID_a1c7] = 1848, + [BNXT_ULP_CLASS_HID_4a8df] = 1849, + [BNXT_ULP_CLASS_HID_4af1b] = 1850, + [BNXT_ULP_CLASS_HID_4f037] = 1851, + [BNXT_ULP_CLASS_HID_4f673] = 1852, + [BNXT_ULP_CLASS_HID_4aca3] = 1853, + [BNXT_ULP_CLASS_HID_4b2ef] = 1854, + [BNXT_ULP_CLASS_HID_4b6cf] = 1855, + [BNXT_ULP_CLASS_HID_4bd0b] = 1856, + [BNXT_ULP_CLASS_HID_1a3eb] = 1857, + [BNXT_ULP_CLASS_HID_1a9d7] = 1858, + [BNXT_ULP_CLASS_HID_1ae37] = 1859, + [BNXT_ULP_CLASS_HID_1b473] = 1860, + [BNXT_ULP_CLASS_HID_1e77f] = 1861, + [BNXT_ULP_CLASS_HID_1edbb] = 1862, + [BNXT_ULP_CLASS_HID_1b19b] = 1863, + [BNXT_ULP_CLASS_HID_1b7c7] = 1864, + [BNXT_ULP_CLASS_HID_5bedf] = 1865, + [BNXT_ULP_CLASS_HID_5a51b] = 1866, + [BNXT_ULP_CLASS_HID_5a97b] = 1867, + [BNXT_ULP_CLASS_HID_5afa7] = 1868, + [BNXT_ULP_CLASS_HID_5e2a3] = 1869, + [BNXT_ULP_CLASS_HID_5e8ef] = 1870, + [BNXT_ULP_CLASS_HID_5accf] = 1871, + [BNXT_ULP_CLASS_HID_5b30b] = 1872, + [BNXT_ULP_CLASS_HID_f36b] = 1873, + [BNXT_ULP_CLASS_HID_f957] = 1874, + [BNXT_ULP_CLASS_HID_fa43] = 1875, + [BNXT_ULP_CLASS_HID_e3f3] = 1876, + [BNXT_ULP_CLASS_HID_f6ff] = 1877, + [BNXT_ULP_CLASS_HID_fd3b] = 1878, + [BNXT_ULP_CLASS_HID_e11b] = 1879, + [BNXT_ULP_CLASS_HID_e747] = 1880, + [BNXT_ULP_CLASS_HID_4ee5f] = 1881, + [BNXT_ULP_CLASS_HID_4f49b] = 1882, + [BNXT_ULP_CLASS_HID_4f5b7] = 1883, + [BNXT_ULP_CLASS_HID_4fbf3] = 1884, + [BNXT_ULP_CLASS_HID_4f223] = 1885, + [BNXT_ULP_CLASS_HID_4f86f] = 1886, + [BNXT_ULP_CLASS_HID_4fc4f] = 1887, + [BNXT_ULP_CLASS_HID_4e28b] = 1888, + [BNXT_ULP_CLASS_HID_1e96b] = 1889, + [BNXT_ULP_CLASS_HID_1ef57] = 1890, + [BNXT_ULP_CLASS_HID_1f3b7] = 1891, + [BNXT_ULP_CLASS_HID_1f9f3] = 1892, + [BNXT_ULP_CLASS_HID_1ecff] = 1893, + [BNXT_ULP_CLASS_HID_1f33b] = 1894, + [BNXT_ULP_CLASS_HID_1f71b] = 1895, + [BNXT_ULP_CLASS_HID_1fd47] = 1896, + [BNXT_ULP_CLASS_HID_5e45f] = 1897, + [BNXT_ULP_CLASS_HID_5ea9b] = 1898, + [BNXT_ULP_CLASS_HID_5eefb] = 1899, + [BNXT_ULP_CLASS_HID_5f527] = 1900, + [BNXT_ULP_CLASS_HID_5e823] = 1901, + [BNXT_ULP_CLASS_HID_5ee6f] = 1902, + [BNXT_ULP_CLASS_HID_5f24f] = 1903, + [BNXT_ULP_CLASS_HID_5f88b] = 1904, + [BNXT_ULP_CLASS_HID_22c53] = 1905, + [BNXT_ULP_CLASS_HID_2326f] = 1906, + [BNXT_ULP_CLASS_HID_2160f] = 1907, + [BNXT_ULP_CLASS_HID_21ccb] = 1908, + [BNXT_ULP_CLASS_HID_24fc7] = 1909, + [BNXT_ULP_CLASS_HID_25583] = 1910, + [BNXT_ULP_CLASS_HID_239a3] = 1911, + [BNXT_ULP_CLASS_HID_2407f] = 1912, + [BNXT_ULP_CLASS_HID_21883] = 1913, + [BNXT_ULP_CLASS_HID_21f5f] = 1914, + [BNXT_ULP_CLASS_HID_2037f] = 1915, + [BNXT_ULP_CLASS_HID_2093b] = 1916, + [BNXT_ULP_CLASS_HID_23c37] = 1917, + [BNXT_ULP_CLASS_HID_242f3] = 1918, + [BNXT_ULP_CLASS_HID_22693] = 1919, + [BNXT_ULP_CLASS_HID_22caf] = 1920, + [BNXT_ULP_CLASS_HID_62767] = 1921, + [BNXT_ULP_CLASS_HID_62d23] = 1922, + [BNXT_ULP_CLASS_HID_611c3] = 1923, + [BNXT_ULP_CLASS_HID_6179f] = 1924, + [BNXT_ULP_CLASS_HID_64a9b] = 1925, + [BNXT_ULP_CLASS_HID_65157] = 1926, + [BNXT_ULP_CLASS_HID_63577] = 1927, + [BNXT_ULP_CLASS_HID_63b33] = 1928, + [BNXT_ULP_CLASS_HID_61457] = 1929, + [BNXT_ULP_CLASS_HID_61a13] = 1930, + [BNXT_ULP_CLASS_HID_65b7f] = 1931, + [BNXT_ULP_CLASS_HID_604cf] = 1932, + [BNXT_ULP_CLASS_HID_637cb] = 1933, + [BNXT_ULP_CLASS_HID_63d87] = 1934, + [BNXT_ULP_CLASS_HID_621a7] = 1935, + [BNXT_ULP_CLASS_HID_62863] = 1936, + [BNXT_ULP_CLASS_HID_34253] = 1937, + [BNXT_ULP_CLASS_HID_3486f] = 1938, + [BNXT_ULP_CLASS_HID_32c0f] = 1939, + [BNXT_ULP_CLASS_HID_332cb] = 1940, + [BNXT_ULP_CLASS_HID_3089b] = 1941, + [BNXT_ULP_CLASS_HID_30f57] = 1942, + [BNXT_ULP_CLASS_HID_34fa3] = 1943, + [BNXT_ULP_CLASS_HID_3567f] = 1944, + [BNXT_ULP_CLASS_HID_32e83] = 1945, + [BNXT_ULP_CLASS_HID_3355f] = 1946, + [BNXT_ULP_CLASS_HID_3197f] = 1947, + [BNXT_ULP_CLASS_HID_31f3b] = 1948, + [BNXT_ULP_CLASS_HID_35237] = 1949, + [BNXT_ULP_CLASS_HID_358f3] = 1950, + [BNXT_ULP_CLASS_HID_33c93] = 1951, + [BNXT_ULP_CLASS_HID_342af] = 1952, + [BNXT_ULP_CLASS_HID_73d67] = 1953, + [BNXT_ULP_CLASS_HID_74323] = 1954, + [BNXT_ULP_CLASS_HID_727c3] = 1955, + [BNXT_ULP_CLASS_HID_72d9f] = 1956, + [BNXT_ULP_CLASS_HID_703af] = 1957, + [BNXT_ULP_CLASS_HID_70a6b] = 1958, + [BNXT_ULP_CLASS_HID_74b77] = 1959, + [BNXT_ULP_CLASS_HID_75133] = 1960, + [BNXT_ULP_CLASS_HID_72a57] = 1961, + [BNXT_ULP_CLASS_HID_73013] = 1962, + [BNXT_ULP_CLASS_HID_71433] = 1963, + [BNXT_ULP_CLASS_HID_71acf] = 1964, + [BNXT_ULP_CLASS_HID_74dcb] = 1965, + [BNXT_ULP_CLASS_HID_75387] = 1966, + [BNXT_ULP_CLASS_HID_737a7] = 1967, + [BNXT_ULP_CLASS_HID_73e63] = 1968, + [BNXT_ULP_CLASS_HID_2b753] = 1969, + [BNXT_ULP_CLASS_HID_2bd6f] = 1970, + [BNXT_ULP_CLASS_HID_2a10f] = 1971, + [BNXT_ULP_CLASS_HID_2a7cb] = 1972, + [BNXT_ULP_CLASS_HID_2dac7] = 1973, + [BNXT_ULP_CLASS_HID_28457] = 1974, + [BNXT_ULP_CLASS_HID_2c4a3] = 1975, + [BNXT_ULP_CLASS_HID_2cb7f] = 1976, + [BNXT_ULP_CLASS_HID_2a383] = 1977, + [BNXT_ULP_CLASS_HID_2aa5f] = 1978, + [BNXT_ULP_CLASS_HID_28e7f] = 1979, + [BNXT_ULP_CLASS_HID_2943b] = 1980, + [BNXT_ULP_CLASS_HID_2c737] = 1981, + [BNXT_ULP_CLASS_HID_2cdf3] = 1982, + [BNXT_ULP_CLASS_HID_2b193] = 1983, + [BNXT_ULP_CLASS_HID_2b7af] = 1984, + [BNXT_ULP_CLASS_HID_6b267] = 1985, + [BNXT_ULP_CLASS_HID_6b823] = 1986, + [BNXT_ULP_CLASS_HID_69cc3] = 1987, + [BNXT_ULP_CLASS_HID_6a29f] = 1988, + [BNXT_ULP_CLASS_HID_6d59b] = 1989, + [BNXT_ULP_CLASS_HID_6dc57] = 1990, + [BNXT_ULP_CLASS_HID_6c077] = 1991, + [BNXT_ULP_CLASS_HID_6c633] = 1992, + [BNXT_ULP_CLASS_HID_69f57] = 1993, + [BNXT_ULP_CLASS_HID_6a513] = 1994, + [BNXT_ULP_CLASS_HID_68933] = 1995, + [BNXT_ULP_CLASS_HID_68fcf] = 1996, + [BNXT_ULP_CLASS_HID_6c2cb] = 1997, + [BNXT_ULP_CLASS_HID_6c887] = 1998, + [BNXT_ULP_CLASS_HID_6aca7] = 1999, + [BNXT_ULP_CLASS_HID_6b363] = 2000, + [BNXT_ULP_CLASS_HID_3cd53] = 2001, + [BNXT_ULP_CLASS_HID_3d36f] = 2002, + [BNXT_ULP_CLASS_HID_3b70f] = 2003, + [BNXT_ULP_CLASS_HID_3bdcb] = 2004, + [BNXT_ULP_CLASS_HID_3939b] = 2005, + [BNXT_ULP_CLASS_HID_39a57] = 2006, + [BNXT_ULP_CLASS_HID_3daa3] = 2007, + [BNXT_ULP_CLASS_HID_38433] = 2008, + [BNXT_ULP_CLASS_HID_3b983] = 2009, + [BNXT_ULP_CLASS_HID_3c05f] = 2010, + [BNXT_ULP_CLASS_HID_3a47f] = 2011, + [BNXT_ULP_CLASS_HID_3aa3b] = 2012, + [BNXT_ULP_CLASS_HID_380cb] = 2013, + [BNXT_ULP_CLASS_HID_38687] = 2014, + [BNXT_ULP_CLASS_HID_3c793] = 2015, + [BNXT_ULP_CLASS_HID_3cdaf] = 2016, + [BNXT_ULP_CLASS_HID_7c867] = 2017, + [BNXT_ULP_CLASS_HID_7ce23] = 2018, + [BNXT_ULP_CLASS_HID_7b2c3] = 2019, + [BNXT_ULP_CLASS_HID_7b89f] = 2020, + [BNXT_ULP_CLASS_HID_78eaf] = 2021, + [BNXT_ULP_CLASS_HID_7956b] = 2022, + [BNXT_ULP_CLASS_HID_7d677] = 2023, + [BNXT_ULP_CLASS_HID_7dc33] = 2024, + [BNXT_ULP_CLASS_HID_7b557] = 2025, + [BNXT_ULP_CLASS_HID_7bb13] = 2026, + [BNXT_ULP_CLASS_HID_79f33] = 2027, + [BNXT_ULP_CLASS_HID_7a5cf] = 2028, + [BNXT_ULP_CLASS_HID_7d8cb] = 2029, + [BNXT_ULP_CLASS_HID_7825b] = 2030, + [BNXT_ULP_CLASS_HID_7c2a7] = 2031, + [BNXT_ULP_CLASS_HID_7c963] = 2032, + [BNXT_ULP_CLASS_HID_8b4b] = 2033, + [BNXT_ULP_CLASS_HID_9177] = 2034, + [BNXT_ULP_CLASS_HID_d263] = 2035, + [BNXT_ULP_CLASS_HID_d82f] = 2036, + [BNXT_ULP_CLASS_HID_aedf] = 2037, + [BNXT_ULP_CLASS_HID_b49b] = 2038, + [BNXT_ULP_CLASS_HID_98bb] = 2039, + [BNXT_ULP_CLASS_HID_9f67] = 2040, + [BNXT_ULP_CLASS_HID_4867f] = 2041, + [BNXT_ULP_CLASS_HID_48c3b] = 2042, + [BNXT_ULP_CLASS_HID_4cd17] = 2043, + [BNXT_ULP_CLASS_HID_4d3d3] = 2044, + [BNXT_ULP_CLASS_HID_4a983] = 2045, + [BNXT_ULP_CLASS_HID_4b04f] = 2046, + [BNXT_ULP_CLASS_HID_4946f] = 2047, + [BNXT_ULP_CLASS_HID_49a2b] = 2048, + [BNXT_ULP_CLASS_HID_1a14b] = 2049, + [BNXT_ULP_CLASS_HID_1a777] = 2050, + [BNXT_ULP_CLASS_HID_18b17] = 2051, + [BNXT_ULP_CLASS_HID_191d3] = 2052, + [BNXT_ULP_CLASS_HID_1c4df] = 2053, + [BNXT_ULP_CLASS_HID_1ca9b] = 2054, + [BNXT_ULP_CLASS_HID_1aebb] = 2055, + [BNXT_ULP_CLASS_HID_1b567] = 2056, + [BNXT_ULP_CLASS_HID_59c7f] = 2057, + [BNXT_ULP_CLASS_HID_5a23b] = 2058, + [BNXT_ULP_CLASS_HID_586db] = 2059, + [BNXT_ULP_CLASS_HID_58c87] = 2060, + [BNXT_ULP_CLASS_HID_5bf83] = 2061, + [BNXT_ULP_CLASS_HID_5c64f] = 2062, + [BNXT_ULP_CLASS_HID_5aa6f] = 2063, + [BNXT_ULP_CLASS_HID_5b02b] = 2064, + [BNXT_ULP_CLASS_HID_d0cb] = 2065, + [BNXT_ULP_CLASS_HID_d6f7] = 2066, + [BNXT_ULP_CLASS_HID_d7e3] = 2067, + [BNXT_ULP_CLASS_HID_c153] = 2068, + [BNXT_ULP_CLASS_HID_f45f] = 2069, + [BNXT_ULP_CLASS_HID_fa1b] = 2070, + [BNXT_ULP_CLASS_HID_de3b] = 2071, + [BNXT_ULP_CLASS_HID_e4e7] = 2072, + [BNXT_ULP_CLASS_HID_4cbff] = 2073, + [BNXT_ULP_CLASS_HID_4d1bb] = 2074, + [BNXT_ULP_CLASS_HID_4d297] = 2075, + [BNXT_ULP_CLASS_HID_4d953] = 2076, + [BNXT_ULP_CLASS_HID_4ef03] = 2077, + [BNXT_ULP_CLASS_HID_4f5cf] = 2078, + [BNXT_ULP_CLASS_HID_4d9ef] = 2079, + [BNXT_ULP_CLASS_HID_4dfab] = 2080, + [BNXT_ULP_CLASS_HID_1e6cb] = 2081, + [BNXT_ULP_CLASS_HID_1ecf7] = 2082, + [BNXT_ULP_CLASS_HID_1d097] = 2083, + [BNXT_ULP_CLASS_HID_1d753] = 2084, + [BNXT_ULP_CLASS_HID_1ca5f] = 2085, + [BNXT_ULP_CLASS_HID_1d01b] = 2086, + [BNXT_ULP_CLASS_HID_1f43b] = 2087, + [BNXT_ULP_CLASS_HID_1fae7] = 2088, + [BNXT_ULP_CLASS_HID_5e1ff] = 2089, + [BNXT_ULP_CLASS_HID_5e7bb] = 2090, + [BNXT_ULP_CLASS_HID_5cc5b] = 2091, + [BNXT_ULP_CLASS_HID_5d207] = 2092, + [BNXT_ULP_CLASS_HID_5c503] = 2093, + [BNXT_ULP_CLASS_HID_5cbcf] = 2094, + [BNXT_ULP_CLASS_HID_5efef] = 2095, + [BNXT_ULP_CLASS_HID_5f5ab] = 2096, + [BNXT_ULP_CLASS_HID_ad8b] = 2097, + [BNXT_ULP_CLASS_HID_b3b7] = 2098, + [BNXT_ULP_CLASS_HID_f4a3] = 2099, + [BNXT_ULP_CLASS_HID_fb6f] = 2100, + [BNXT_ULP_CLASS_HID_b11f] = 2101, + [BNXT_ULP_CLASS_HID_b7db] = 2102, + [BNXT_ULP_CLASS_HID_bbfb] = 2103, + [BNXT_ULP_CLASS_HID_a1a7] = 2104, + [BNXT_ULP_CLASS_HID_4a8bf] = 2105, + [BNXT_ULP_CLASS_HID_4af7b] = 2106, + [BNXT_ULP_CLASS_HID_4f057] = 2107, + [BNXT_ULP_CLASS_HID_4f613] = 2108, + [BNXT_ULP_CLASS_HID_4acc3] = 2109, + [BNXT_ULP_CLASS_HID_4b28f] = 2110, + [BNXT_ULP_CLASS_HID_4b6af] = 2111, + [BNXT_ULP_CLASS_HID_4bd6b] = 2112, + [BNXT_ULP_CLASS_HID_1a38b] = 2113, + [BNXT_ULP_CLASS_HID_1a9b7] = 2114, + [BNXT_ULP_CLASS_HID_1ae57] = 2115, + [BNXT_ULP_CLASS_HID_1b413] = 2116, + [BNXT_ULP_CLASS_HID_1e71f] = 2117, + [BNXT_ULP_CLASS_HID_1eddb] = 2118, + [BNXT_ULP_CLASS_HID_1b1fb] = 2119, + [BNXT_ULP_CLASS_HID_1b7a7] = 2120, + [BNXT_ULP_CLASS_HID_5bebf] = 2121, + [BNXT_ULP_CLASS_HID_5a57b] = 2122, + [BNXT_ULP_CLASS_HID_5a91b] = 2123, + [BNXT_ULP_CLASS_HID_5afc7] = 2124, + [BNXT_ULP_CLASS_HID_5e2c3] = 2125, + [BNXT_ULP_CLASS_HID_5e88f] = 2126, + [BNXT_ULP_CLASS_HID_5acaf] = 2127, + [BNXT_ULP_CLASS_HID_5b36b] = 2128, + [BNXT_ULP_CLASS_HID_f30b] = 2129, + [BNXT_ULP_CLASS_HID_f937] = 2130, + [BNXT_ULP_CLASS_HID_fa23] = 2131, + [BNXT_ULP_CLASS_HID_e393] = 2132, + [BNXT_ULP_CLASS_HID_f69f] = 2133, + [BNXT_ULP_CLASS_HID_fd5b] = 2134, + [BNXT_ULP_CLASS_HID_e17b] = 2135, + [BNXT_ULP_CLASS_HID_e727] = 2136, + [BNXT_ULP_CLASS_HID_4ee3f] = 2137, + [BNXT_ULP_CLASS_HID_4f4fb] = 2138, + [BNXT_ULP_CLASS_HID_4f5d7] = 2139, + [BNXT_ULP_CLASS_HID_4fb93] = 2140, + [BNXT_ULP_CLASS_HID_4f243] = 2141, + [BNXT_ULP_CLASS_HID_4f80f] = 2142, + [BNXT_ULP_CLASS_HID_4fc2f] = 2143, + [BNXT_ULP_CLASS_HID_4e2eb] = 2144, + [BNXT_ULP_CLASS_HID_1e90b] = 2145, + [BNXT_ULP_CLASS_HID_1ef37] = 2146, + [BNXT_ULP_CLASS_HID_1f3d7] = 2147, + [BNXT_ULP_CLASS_HID_1f993] = 2148, + [BNXT_ULP_CLASS_HID_1ec9f] = 2149, + [BNXT_ULP_CLASS_HID_1f35b] = 2150, + [BNXT_ULP_CLASS_HID_1f77b] = 2151, + [BNXT_ULP_CLASS_HID_1fd27] = 2152, + [BNXT_ULP_CLASS_HID_5e43f] = 2153, + [BNXT_ULP_CLASS_HID_5eafb] = 2154, + [BNXT_ULP_CLASS_HID_5ee9b] = 2155, + [BNXT_ULP_CLASS_HID_5f547] = 2156, + [BNXT_ULP_CLASS_HID_5e843] = 2157, + [BNXT_ULP_CLASS_HID_5ee0f] = 2158, + [BNXT_ULP_CLASS_HID_5f22f] = 2159, + [BNXT_ULP_CLASS_HID_5f8eb] = 2160, + [BNXT_ULP_CLASS_HID_2579] = 2161, + [BNXT_ULP_CLASS_HID_2bb5] = 2162, + [BNXT_ULP_CLASS_HID_4591] = 2163, + [BNXT_ULP_CLASS_HID_4bad] = 2164, + [BNXT_ULP_CLASS_HID_2561] = 2165, + [BNXT_ULP_CLASS_HID_2bad] = 2166, + [BNXT_ULP_CLASS_HID_5bdd] = 2167, + [BNXT_ULP_CLASS_HID_054d] = 2168, + [BNXT_ULP_CLASS_HID_257b] = 2169, + [BNXT_ULP_CLASS_HID_2bb7] = 2170, + [BNXT_ULP_CLASS_HID_0fd7] = 2171, + [BNXT_ULP_CLASS_HID_1613] = 2172, + [BNXT_ULP_CLASS_HID_48ef] = 2173, + [BNXT_ULP_CLASS_HID_4f2b] = 2174, + [BNXT_ULP_CLASS_HID_334b] = 2175, + [BNXT_ULP_CLASS_HID_3987] = 2176, + [BNXT_ULP_CLASS_HID_122b] = 2177, + [BNXT_ULP_CLASS_HID_1867] = 2178, + [BNXT_ULP_CLASS_HID_5973] = 2179, + [BNXT_ULP_CLASS_HID_02c3] = 2180, + [BNXT_ULP_CLASS_HID_35df] = 2181, + [BNXT_ULP_CLASS_HID_3c1b] = 2182, + [BNXT_ULP_CLASS_HID_203b] = 2183, + [BNXT_ULP_CLASS_HID_2677] = 2184, + [BNXT_ULP_CLASS_HID_2563] = 2185, + [BNXT_ULP_CLASS_HID_2baf] = 2186, + [BNXT_ULP_CLASS_HID_0fcf] = 2187, + [BNXT_ULP_CLASS_HID_160b] = 2188, + [BNXT_ULP_CLASS_HID_48f7] = 2189, + [BNXT_ULP_CLASS_HID_4f33] = 2190, + [BNXT_ULP_CLASS_HID_3353] = 2191, + [BNXT_ULP_CLASS_HID_399f] = 2192, + [BNXT_ULP_CLASS_HID_42097] = 2193, + [BNXT_ULP_CLASS_HID_426d3] = 2194, + [BNXT_ULP_CLASS_HID_40af3] = 2195, + [BNXT_ULP_CLASS_HID_4113f] = 2196, + [BNXT_ULP_CLASS_HID_4443b] = 2197, + [BNXT_ULP_CLASS_HID_44a67] = 2198, + [BNXT_ULP_CLASS_HID_42e87] = 2199, + [BNXT_ULP_CLASS_HID_434c3] = 2200, + [BNXT_ULP_CLASS_HID_2559] = 2201, + [BNXT_ULP_CLASS_HID_2b95] = 2202, + [BNXT_ULP_CLASS_HID_45b1] = 2203, + [BNXT_ULP_CLASS_HID_4b8d] = 2204, + [BNXT_ULP_CLASS_HID_2541] = 2205, + [BNXT_ULP_CLASS_HID_2b8d] = 2206, + [BNXT_ULP_CLASS_HID_5bfd] = 2207, + [BNXT_ULP_CLASS_HID_056d] = 2208, + [BNXT_ULP_CLASS_HID_2539] = 2209, + [BNXT_ULP_CLASS_HID_2bf5] = 2210, + [BNXT_ULP_CLASS_HID_45d1] = 2211, + [BNXT_ULP_CLASS_HID_4bed] = 2212, + [BNXT_ULP_CLASS_HID_2521] = 2213, + [BNXT_ULP_CLASS_HID_2bed] = 2214, + [BNXT_ULP_CLASS_HID_5b9d] = 2215, + [BNXT_ULP_CLASS_HID_050d] = 2216, + [BNXT_ULP_CLASS_HID_255b] = 2217, + [BNXT_ULP_CLASS_HID_2b97] = 2218, + [BNXT_ULP_CLASS_HID_0ff7] = 2219, + [BNXT_ULP_CLASS_HID_1633] = 2220, + [BNXT_ULP_CLASS_HID_48cf] = 2221, + [BNXT_ULP_CLASS_HID_4f0b] = 2222, + [BNXT_ULP_CLASS_HID_336b] = 2223, + [BNXT_ULP_CLASS_HID_39a7] = 2224, + [BNXT_ULP_CLASS_HID_120b] = 2225, + [BNXT_ULP_CLASS_HID_1847] = 2226, + [BNXT_ULP_CLASS_HID_5953] = 2227, + [BNXT_ULP_CLASS_HID_02e3] = 2228, + [BNXT_ULP_CLASS_HID_35ff] = 2229, + [BNXT_ULP_CLASS_HID_3c3b] = 2230, + [BNXT_ULP_CLASS_HID_201b] = 2231, + [BNXT_ULP_CLASS_HID_2657] = 2232, + [BNXT_ULP_CLASS_HID_2543] = 2233, + [BNXT_ULP_CLASS_HID_2b8f] = 2234, + [BNXT_ULP_CLASS_HID_0fef] = 2235, + [BNXT_ULP_CLASS_HID_162b] = 2236, + [BNXT_ULP_CLASS_HID_48d7] = 2237, + [BNXT_ULP_CLASS_HID_4f13] = 2238, + [BNXT_ULP_CLASS_HID_3373] = 2239, + [BNXT_ULP_CLASS_HID_39bf] = 2240, + [BNXT_ULP_CLASS_HID_420b7] = 2241, + [BNXT_ULP_CLASS_HID_426f3] = 2242, + [BNXT_ULP_CLASS_HID_40ad3] = 2243, + [BNXT_ULP_CLASS_HID_4111f] = 2244, + [BNXT_ULP_CLASS_HID_4441b] = 2245, + [BNXT_ULP_CLASS_HID_44a47] = 2246, + [BNXT_ULP_CLASS_HID_42ea7] = 2247, + [BNXT_ULP_CLASS_HID_434e3] = 2248, + [BNXT_ULP_CLASS_HID_253b] = 2249, + [BNXT_ULP_CLASS_HID_2bf7] = 2250, + [BNXT_ULP_CLASS_HID_0f97] = 2251, + [BNXT_ULP_CLASS_HID_1653] = 2252, + [BNXT_ULP_CLASS_HID_48af] = 2253, + [BNXT_ULP_CLASS_HID_4f6b] = 2254, + [BNXT_ULP_CLASS_HID_330b] = 2255, + [BNXT_ULP_CLASS_HID_39c7] = 2256, + [BNXT_ULP_CLASS_HID_126b] = 2257, + [BNXT_ULP_CLASS_HID_1827] = 2258, + [BNXT_ULP_CLASS_HID_5933] = 2259, + [BNXT_ULP_CLASS_HID_0283] = 2260, + [BNXT_ULP_CLASS_HID_359f] = 2261, + [BNXT_ULP_CLASS_HID_3c5b] = 2262, + [BNXT_ULP_CLASS_HID_207b] = 2263, + [BNXT_ULP_CLASS_HID_2637] = 2264, + [BNXT_ULP_CLASS_HID_2523] = 2265, + [BNXT_ULP_CLASS_HID_2bef] = 2266, + [BNXT_ULP_CLASS_HID_0f8f] = 2267, + [BNXT_ULP_CLASS_HID_164b] = 2268, + [BNXT_ULP_CLASS_HID_48b7] = 2269, + [BNXT_ULP_CLASS_HID_4f73] = 2270, + [BNXT_ULP_CLASS_HID_3313] = 2271, + [BNXT_ULP_CLASS_HID_39df] = 2272, + [BNXT_ULP_CLASS_HID_420d7] = 2273, + [BNXT_ULP_CLASS_HID_42693] = 2274, + [BNXT_ULP_CLASS_HID_40ab3] = 2275, + [BNXT_ULP_CLASS_HID_4117f] = 2276, + [BNXT_ULP_CLASS_HID_4447b] = 2277, + [BNXT_ULP_CLASS_HID_44a27] = 2278, + [BNXT_ULP_CLASS_HID_42ec7] = 2279, + [BNXT_ULP_CLASS_HID_43483] = 2280, + [BNXT_ULP_CLASS_HID_4156d] = 2281, + [BNXT_ULP_CLASS_HID_41b29] = 2282, + [BNXT_ULP_CLASS_HID_52b6d] = 2283, + [BNXT_ULP_CLASS_HID_53129] = 2284, + [BNXT_ULP_CLASS_HID_478a] = 2285, + [BNXT_ULP_CLASS_HID_03a6] = 2286, + [BNXT_ULP_CLASS_HID_4dce] = 2287, + [BNXT_ULP_CLASS_HID_09ea] = 2288, + [BNXT_ULP_CLASS_HID_08fe] = 2289, + [BNXT_ULP_CLASS_HID_23ce] = 2290, + [BNXT_ULP_CLASS_HID_0e02] = 2291, + [BNXT_ULP_CLASS_HID_2912] = 2292, + [BNXT_ULP_CLASS_HID_3e2a] = 2293, + [BNXT_ULP_CLASS_HID_593a] = 2294, + [BNXT_ULP_CLASS_HID_246e] = 2295, + [BNXT_ULP_CLASS_HID_5f7e] = 2296, + [BNXT_ULP_CLASS_HID_5e52] = 2297, + [BNXT_ULP_CLASS_HID_1a6e] = 2298, + [BNXT_ULP_CLASS_HID_4796] = 2299, + [BNXT_ULP_CLASS_HID_03b2] = 2300, + [BNXT_ULP_CLASS_HID_4163a] = 2301, + [BNXT_ULP_CLASS_HID_4310a] = 2302, + [BNXT_ULP_CLASS_HID_41c7e] = 2303, + [BNXT_ULP_CLASS_HID_4374e] = 2304, + [BNXT_ULP_CLASS_HID_42f8e] = 2305, + [BNXT_ULP_CLASS_HID_4469e] = 2306, + [BNXT_ULP_CLASS_HID_455c2] = 2307, + [BNXT_ULP_CLASS_HID_411ee] = 2308, + [BNXT_ULP_CLASS_HID_44b76] = 2309, + [BNXT_ULP_CLASS_HID_40692] = 2310, + [BNXT_ULP_CLASS_HID_415c6] = 2311, + [BNXT_ULP_CLASS_HID_40cd6] = 2312, + [BNXT_ULP_CLASS_HID_42516] = 2313, + [BNXT_ULP_CLASS_HID_45ce6] = 2314, + [BNXT_ULP_CLASS_HID_42b2a] = 2315, + [BNXT_ULP_CLASS_HID_4423a] = 2316, + [BNXT_ULP_CLASS_HID_229d8] = 2317, + [BNXT_ULP_CLASS_HID_240c8] = 2318, + [BNXT_ULP_CLASS_HID_22f14] = 2319, + [BNXT_ULP_CLASS_HID_24604] = 2320, + [BNXT_ULP_CLASS_HID_23374] = 2321, + [BNXT_ULP_CLASS_HID_22a64] = 2322, + [BNXT_ULP_CLASS_HID_238b0] = 2323, + [BNXT_ULP_CLASS_HID_253a0] = 2324, + [BNXT_ULP_CLASS_HID_24dac] = 2325, + [BNXT_ULP_CLASS_HID_20990] = 2326, + [BNXT_ULP_CLASS_HID_214dc] = 2327, + [BNXT_ULP_CLASS_HID_20fcc] = 2328, + [BNXT_ULP_CLASS_HID_257c8] = 2329, + [BNXT_ULP_CLASS_HID_2132c] = 2330, + [BNXT_ULP_CLASS_HID_25d04] = 2331, + [BNXT_ULP_CLASS_HID_21968] = 2332, + [BNXT_ULP_CLASS_HID_234e8] = 2333, + [BNXT_ULP_CLASS_HID_22f98] = 2334, + [BNXT_ULP_CLASS_HID_23a24] = 2335, + [BNXT_ULP_CLASS_HID_255d4] = 2336, + [BNXT_ULP_CLASS_HID_21e04] = 2337, + [BNXT_ULP_CLASS_HID_23934] = 2338, + [BNXT_ULP_CLASS_HID_20440] = 2339, + [BNXT_ULP_CLASS_HID_23f70] = 2340, + [BNXT_ULP_CLASS_HID_2597c] = 2341, + [BNXT_ULP_CLASS_HID_214a0] = 2342, + [BNXT_ULP_CLASS_HID_25eb8] = 2343, + [BNXT_ULP_CLASS_HID_21a9c] = 2344, + [BNXT_ULP_CLASS_HID_22298] = 2345, + [BNXT_ULP_CLASS_HID_25d88] = 2346, + [BNXT_ULP_CLASS_HID_228d4] = 2347, + [BNXT_ULP_CLASS_HID_243c4] = 2348, + [BNXT_ULP_CLASS_HID_6220c] = 2349, + [BNXT_ULP_CLASS_HID_65d3c] = 2350, + [BNXT_ULP_CLASS_HID_62848] = 2351, + [BNXT_ULP_CLASS_HID_64378] = 2352, + [BNXT_ULP_CLASS_HID_60fa8] = 2353, + [BNXT_ULP_CLASS_HID_62758] = 2354, + [BNXT_ULP_CLASS_HID_635e4] = 2355, + [BNXT_ULP_CLASS_HID_62c94] = 2356, + [BNXT_ULP_CLASS_HID_646e0] = 2357, + [BNXT_ULP_CLASS_HID_602c4] = 2358, + [BNXT_ULP_CLASS_HID_61110] = 2359, + [BNXT_ULP_CLASS_HID_60800] = 2360, + [BNXT_ULP_CLASS_HID_6503c] = 2361, + [BNXT_ULP_CLASS_HID_64b2c] = 2362, + [BNXT_ULP_CLASS_HID_65678] = 2363, + [BNXT_ULP_CLASS_HID_6125c] = 2364, + [BNXT_ULP_CLASS_HID_631dc] = 2365, + [BNXT_ULP_CLASS_HID_628cc] = 2366, + [BNXT_ULP_CLASS_HID_63718] = 2367, + [BNXT_ULP_CLASS_HID_62e08] = 2368, + [BNXT_ULP_CLASS_HID_61b78] = 2369, + [BNXT_ULP_CLASS_HID_63268] = 2370, + [BNXT_ULP_CLASS_HID_600b4] = 2371, + [BNXT_ULP_CLASS_HID_63ba4] = 2372, + [BNXT_ULP_CLASS_HID_655b0] = 2373, + [BNXT_ULP_CLASS_HID_61194] = 2374, + [BNXT_ULP_CLASS_HID_65bec] = 2375, + [BNXT_ULP_CLASS_HID_617d0] = 2376, + [BNXT_ULP_CLASS_HID_63fcc] = 2377, + [BNXT_ULP_CLASS_HID_656fc] = 2378, + [BNXT_ULP_CLASS_HID_62508] = 2379, + [BNXT_ULP_CLASS_HID_65c38] = 2380, + [BNXT_ULP_CLASS_HID_86e0] = 2381, + [BNXT_ULP_CLASS_HID_a1f0] = 2382, + [BNXT_ULP_CLASS_HID_8c2c] = 2383, + [BNXT_ULP_CLASS_HID_a73c] = 2384, + [BNXT_ULP_CLASS_HID_904c] = 2385, + [BNXT_ULP_CLASS_HID_8b5c] = 2386, + [BNXT_ULP_CLASS_HID_9988] = 2387, + [BNXT_ULP_CLASS_HID_b098] = 2388, + [BNXT_ULP_CLASS_HID_aa94] = 2389, + [BNXT_ULP_CLASS_HID_c264] = 2390, + [BNXT_ULP_CLASS_HID_d0d0] = 2391, + [BNXT_ULP_CLASS_HID_cba0] = 2392, + [BNXT_ULP_CLASS_HID_b4f0] = 2393, + [BNXT_ULP_CLASS_HID_afc0] = 2394, + [BNXT_ULP_CLASS_HID_ba3c] = 2395, + [BNXT_ULP_CLASS_HID_d50c] = 2396, + [BNXT_ULP_CLASS_HID_48334] = 2397, + [BNXT_ULP_CLASS_HID_4ba04] = 2398, + [BNXT_ULP_CLASS_HID_48970] = 2399, + [BNXT_ULP_CLASS_HID_4a040] = 2400, + [BNXT_ULP_CLASS_HID_4c84c] = 2401, + [BNXT_ULP_CLASS_HID_48460] = 2402, + [BNXT_ULP_CLASS_HID_492dc] = 2403, + [BNXT_ULP_CLASS_HID_48dac] = 2404, + [BNXT_ULP_CLASS_HID_4a7d8] = 2405, + [BNXT_ULP_CLASS_HID_4dea8] = 2406, + [BNXT_ULP_CLASS_HID_4ade4] = 2407, + [BNXT_ULP_CLASS_HID_4c4f4] = 2408, + [BNXT_ULP_CLASS_HID_4b104] = 2409, + [BNXT_ULP_CLASS_HID_4a814] = 2410, + [BNXT_ULP_CLASS_HID_4b740] = 2411, + [BNXT_ULP_CLASS_HID_4ae50] = 2412, + [BNXT_ULP_CLASS_HID_1bce0] = 2413, + [BNXT_ULP_CLASS_HID_1d7f0] = 2414, + [BNXT_ULP_CLASS_HID_1a22c] = 2415, + [BNXT_ULP_CLASS_HID_1dd3c] = 2416, + [BNXT_ULP_CLASS_HID_1864c] = 2417, + [BNXT_ULP_CLASS_HID_1a15c] = 2418, + [BNXT_ULP_CLASS_HID_18f88] = 2419, + [BNXT_ULP_CLASS_HID_1a698] = 2420, + [BNXT_ULP_CLASS_HID_1c094] = 2421, + [BNXT_ULP_CLASS_HID_19ca8] = 2422, + [BNXT_ULP_CLASS_HID_1c6d0] = 2423, + [BNXT_ULP_CLASS_HID_182f4] = 2424, + [BNXT_ULP_CLASS_HID_1aaf0] = 2425, + [BNXT_ULP_CLASS_HID_1c5c0] = 2426, + [BNXT_ULP_CLASS_HID_1d03c] = 2427, + [BNXT_ULP_CLASS_HID_1cb0c] = 2428, + [BNXT_ULP_CLASS_HID_5b934] = 2429, + [BNXT_ULP_CLASS_HID_5d004] = 2430, + [BNXT_ULP_CLASS_HID_5bf70] = 2431, + [BNXT_ULP_CLASS_HID_5d640] = 2432, + [BNXT_ULP_CLASS_HID_58290] = 2433, + [BNXT_ULP_CLASS_HID_5ba60] = 2434, + [BNXT_ULP_CLASS_HID_588dc] = 2435, + [BNXT_ULP_CLASS_HID_5a3ac] = 2436, + [BNXT_ULP_CLASS_HID_5ddd8] = 2437, + [BNXT_ULP_CLASS_HID_599fc] = 2438, + [BNXT_ULP_CLASS_HID_5c3e4] = 2439, + [BNXT_ULP_CLASS_HID_59f38] = 2440, + [BNXT_ULP_CLASS_HID_5a704] = 2441, + [BNXT_ULP_CLASS_HID_5de14] = 2442, + [BNXT_ULP_CLASS_HID_5ad40] = 2443, + [BNXT_ULP_CLASS_HID_5c450] = 2444, + [BNXT_ULP_CLASS_HID_47aa] = 2445, + [BNXT_ULP_CLASS_HID_0386] = 2446, + [BNXT_ULP_CLASS_HID_4dee] = 2447, + [BNXT_ULP_CLASS_HID_09ca] = 2448, + [BNXT_ULP_CLASS_HID_08de] = 2449, + [BNXT_ULP_CLASS_HID_23ee] = 2450, + [BNXT_ULP_CLASS_HID_0e22] = 2451, + [BNXT_ULP_CLASS_HID_2932] = 2452, + [BNXT_ULP_CLASS_HID_3e0a] = 2453, + [BNXT_ULP_CLASS_HID_591a] = 2454, + [BNXT_ULP_CLASS_HID_244e] = 2455, + [BNXT_ULP_CLASS_HID_5f5e] = 2456, + [BNXT_ULP_CLASS_HID_5e72] = 2457, + [BNXT_ULP_CLASS_HID_1a4e] = 2458, + [BNXT_ULP_CLASS_HID_47b6] = 2459, + [BNXT_ULP_CLASS_HID_0392] = 2460, + [BNXT_ULP_CLASS_HID_5dc2] = 2461, + [BNXT_ULP_CLASS_HID_191e] = 2462, + [BNXT_ULP_CLASS_HID_4306] = 2463, + [BNXT_ULP_CLASS_HID_1f62] = 2464, + [BNXT_ULP_CLASS_HID_1e76] = 2465, + [BNXT_ULP_CLASS_HID_3906] = 2466, + [BNXT_ULP_CLASS_HID_07ba] = 2467, + [BNXT_ULP_CLASS_HID_3f4a] = 2468, + [BNXT_ULP_CLASS_HID_37a2] = 2469, + [BNXT_ULP_CLASS_HID_2eb2] = 2470, + [BNXT_ULP_CLASS_HID_3de6] = 2471, + [BNXT_ULP_CLASS_HID_54f6] = 2472, + [BNXT_ULP_CLASS_HID_578a] = 2473, + [BNXT_ULP_CLASS_HID_13e6] = 2474, + [BNXT_ULP_CLASS_HID_5dce] = 2475, + [BNXT_ULP_CLASS_HID_192a] = 2476, + [BNXT_ULP_CLASS_HID_440f6] = 2477, + [BNXT_ULP_CLASS_HID_41cd2] = 2478, + [BNXT_ULP_CLASS_HID_4463a] = 2479, + [BNXT_ULP_CLASS_HID_40216] = 2480, + [BNXT_ULP_CLASS_HID_4052a] = 2481, + [BNXT_ULP_CLASS_HID_43c3a] = 2482, + [BNXT_ULP_CLASS_HID_40b6e] = 2483, + [BNXT_ULP_CLASS_HID_4227e] = 2484, + [BNXT_ULP_CLASS_HID_43b56] = 2485, + [BNXT_ULP_CLASS_HID_45266] = 2486, + [BNXT_ULP_CLASS_HID_4209a] = 2487, + [BNXT_ULP_CLASS_HID_45baa] = 2488, + [BNXT_ULP_CLASS_HID_45abe] = 2489, + [BNXT_ULP_CLASS_HID_4169a] = 2490, + [BNXT_ULP_CLASS_HID_44082] = 2491, + [BNXT_ULP_CLASS_HID_41cde] = 2492, + [BNXT_ULP_CLASS_HID_4560e] = 2493, + [BNXT_ULP_CLASS_HID_4126a] = 2494, + [BNXT_ULP_CLASS_HID_45c52] = 2495, + [BNXT_ULP_CLASS_HID_41bae] = 2496, + [BNXT_ULP_CLASS_HID_41b42] = 2497, + [BNXT_ULP_CLASS_HID_43252] = 2498, + [BNXT_ULP_CLASS_HID_40086] = 2499, + [BNXT_ULP_CLASS_HID_43b96] = 2500, + [BNXT_ULP_CLASS_HID_430ee] = 2501, + [BNXT_ULP_CLASS_HID_42bfe] = 2502, + [BNXT_ULP_CLASS_HID_43632] = 2503, + [BNXT_ULP_CLASS_HID_451c2] = 2504, + [BNXT_ULP_CLASS_HID_450d6] = 2505, + [BNXT_ULP_CLASS_HID_44be6] = 2506, + [BNXT_ULP_CLASS_HID_4561a] = 2507, + [BNXT_ULP_CLASS_HID_41276] = 2508, + [BNXT_ULP_CLASS_HID_4161a] = 2509, + [BNXT_ULP_CLASS_HID_4312a] = 2510, + [BNXT_ULP_CLASS_HID_41c5e] = 2511, + [BNXT_ULP_CLASS_HID_4376e] = 2512, + [BNXT_ULP_CLASS_HID_42fae] = 2513, + [BNXT_ULP_CLASS_HID_446be] = 2514, + [BNXT_ULP_CLASS_HID_455e2] = 2515, + [BNXT_ULP_CLASS_HID_411ce] = 2516, + [BNXT_ULP_CLASS_HID_44b56] = 2517, + [BNXT_ULP_CLASS_HID_406b2] = 2518, + [BNXT_ULP_CLASS_HID_415e6] = 2519, + [BNXT_ULP_CLASS_HID_40cf6] = 2520, + [BNXT_ULP_CLASS_HID_42536] = 2521, + [BNXT_ULP_CLASS_HID_45cc6] = 2522, + [BNXT_ULP_CLASS_HID_42b0a] = 2523, + [BNXT_ULP_CLASS_HID_4421a] = 2524, + [BNXT_ULP_CLASS_HID_6221a] = 2525, + [BNXT_ULP_CLASS_HID_65d2a] = 2526, + [BNXT_ULP_CLASS_HID_6285e] = 2527, + [BNXT_ULP_CLASS_HID_6436e] = 2528, + [BNXT_ULP_CLASS_HID_61cfa] = 2529, + [BNXT_ULP_CLASS_HID_6378a] = 2530, + [BNXT_ULP_CLASS_HID_6023e] = 2531, + [BNXT_ULP_CLASS_HID_63dce] = 2532, + [BNXT_ULP_CLASS_HID_63ba2] = 2533, + [BNXT_ULP_CLASS_HID_652b2] = 2534, + [BNXT_ULP_CLASS_HID_621e6] = 2535, + [BNXT_ULP_CLASS_HID_658f6] = 2536, + [BNXT_ULP_CLASS_HID_61202] = 2537, + [BNXT_ULP_CLASS_HID_60d12] = 2538, + [BNXT_ULP_CLASS_HID_61846] = 2539, + [BNXT_ULP_CLASS_HID_63356] = 2540, + [BNXT_ULP_CLASS_HID_50c1a] = 2541, + [BNXT_ULP_CLASS_HID_5272a] = 2542, + [BNXT_ULP_CLASS_HID_5325e] = 2543, + [BNXT_ULP_CLASS_HID_52d6e] = 2544, + [BNXT_ULP_CLASS_HID_545ae] = 2545, + [BNXT_ULP_CLASS_HID_5018a] = 2546, + [BNXT_ULP_CLASS_HID_54be2] = 2547, + [BNXT_ULP_CLASS_HID_507ce] = 2548, + [BNXT_ULP_CLASS_HID_505a2] = 2549, + [BNXT_ULP_CLASS_HID_53cb2] = 2550, + [BNXT_ULP_CLASS_HID_50be6] = 2551, + [BNXT_ULP_CLASS_HID_522f6] = 2552, + [BNXT_ULP_CLASS_HID_55b36] = 2553, + [BNXT_ULP_CLASS_HID_51712] = 2554, + [BNXT_ULP_CLASS_HID_5410a] = 2555, + [BNXT_ULP_CLASS_HID_51d56] = 2556, + [BNXT_ULP_CLASS_HID_7581a] = 2557, + [BNXT_ULP_CLASS_HID_71466] = 2558, + [BNXT_ULP_CLASS_HID_75e5e] = 2559, + [BNXT_ULP_CLASS_HID_71dba] = 2560, + [BNXT_ULP_CLASS_HID_732fa] = 2561, + [BNXT_ULP_CLASS_HID_72d8a] = 2562, + [BNXT_ULP_CLASS_HID_7383e] = 2563, + [BNXT_ULP_CLASS_HID_753ce] = 2564, + [BNXT_ULP_CLASS_HID_751a2] = 2565, + [BNXT_ULP_CLASS_HID_748b2] = 2566, + [BNXT_ULP_CLASS_HID_757e6] = 2567, + [BNXT_ULP_CLASS_HID_713c2] = 2568, + [BNXT_ULP_CLASS_HID_70802] = 2569, + [BNXT_ULP_CLASS_HID_72312] = 2570, + [BNXT_ULP_CLASS_HID_70e46] = 2571, + [BNXT_ULP_CLASS_HID_72956] = 2572, + [BNXT_ULP_CLASS_HID_47ca] = 2573, + [BNXT_ULP_CLASS_HID_03e6] = 2574, + [BNXT_ULP_CLASS_HID_4d8e] = 2575, + [BNXT_ULP_CLASS_HID_09aa] = 2576, + [BNXT_ULP_CLASS_HID_08be] = 2577, + [BNXT_ULP_CLASS_HID_238e] = 2578, + [BNXT_ULP_CLASS_HID_0e42] = 2579, + [BNXT_ULP_CLASS_HID_2952] = 2580, + [BNXT_ULP_CLASS_HID_3e6a] = 2581, + [BNXT_ULP_CLASS_HID_597a] = 2582, + [BNXT_ULP_CLASS_HID_242e] = 2583, + [BNXT_ULP_CLASS_HID_5f3e] = 2584, + [BNXT_ULP_CLASS_HID_5e12] = 2585, + [BNXT_ULP_CLASS_HID_1a2e] = 2586, + [BNXT_ULP_CLASS_HID_47d6] = 2587, + [BNXT_ULP_CLASS_HID_03f2] = 2588, + [BNXT_ULP_CLASS_HID_5da2] = 2589, + [BNXT_ULP_CLASS_HID_197e] = 2590, + [BNXT_ULP_CLASS_HID_4366] = 2591, + [BNXT_ULP_CLASS_HID_1f02] = 2592, + [BNXT_ULP_CLASS_HID_1e16] = 2593, + [BNXT_ULP_CLASS_HID_3966] = 2594, + [BNXT_ULP_CLASS_HID_07da] = 2595, + [BNXT_ULP_CLASS_HID_3f2a] = 2596, + [BNXT_ULP_CLASS_HID_37c2] = 2597, + [BNXT_ULP_CLASS_HID_2ed2] = 2598, + [BNXT_ULP_CLASS_HID_3d86] = 2599, + [BNXT_ULP_CLASS_HID_5496] = 2600, + [BNXT_ULP_CLASS_HID_57ea] = 2601, + [BNXT_ULP_CLASS_HID_1386] = 2602, + [BNXT_ULP_CLASS_HID_5dae] = 2603, + [BNXT_ULP_CLASS_HID_194a] = 2604, + [BNXT_ULP_CLASS_HID_44096] = 2605, + [BNXT_ULP_CLASS_HID_41cb2] = 2606, + [BNXT_ULP_CLASS_HID_4465a] = 2607, + [BNXT_ULP_CLASS_HID_40276] = 2608, + [BNXT_ULP_CLASS_HID_4054a] = 2609, + [BNXT_ULP_CLASS_HID_43c5a] = 2610, + [BNXT_ULP_CLASS_HID_40b0e] = 2611, + [BNXT_ULP_CLASS_HID_4221e] = 2612, + [BNXT_ULP_CLASS_HID_43b36] = 2613, + [BNXT_ULP_CLASS_HID_45206] = 2614, + [BNXT_ULP_CLASS_HID_420fa] = 2615, + [BNXT_ULP_CLASS_HID_45bca] = 2616, + [BNXT_ULP_CLASS_HID_45ade] = 2617, + [BNXT_ULP_CLASS_HID_416fa] = 2618, + [BNXT_ULP_CLASS_HID_440e2] = 2619, + [BNXT_ULP_CLASS_HID_41cbe] = 2620, + [BNXT_ULP_CLASS_HID_4566e] = 2621, + [BNXT_ULP_CLASS_HID_4120a] = 2622, + [BNXT_ULP_CLASS_HID_45c32] = 2623, + [BNXT_ULP_CLASS_HID_41bce] = 2624, + [BNXT_ULP_CLASS_HID_41b22] = 2625, + [BNXT_ULP_CLASS_HID_43232] = 2626, + [BNXT_ULP_CLASS_HID_400e6] = 2627, + [BNXT_ULP_CLASS_HID_43bf6] = 2628, + [BNXT_ULP_CLASS_HID_4308e] = 2629, + [BNXT_ULP_CLASS_HID_42b9e] = 2630, + [BNXT_ULP_CLASS_HID_43652] = 2631, + [BNXT_ULP_CLASS_HID_451a2] = 2632, + [BNXT_ULP_CLASS_HID_450b6] = 2633, + [BNXT_ULP_CLASS_HID_44b86] = 2634, + [BNXT_ULP_CLASS_HID_4567a] = 2635, + [BNXT_ULP_CLASS_HID_41216] = 2636, + [BNXT_ULP_CLASS_HID_4167a] = 2637, + [BNXT_ULP_CLASS_HID_4314a] = 2638, + [BNXT_ULP_CLASS_HID_41c3e] = 2639, + [BNXT_ULP_CLASS_HID_4370e] = 2640, + [BNXT_ULP_CLASS_HID_42fce] = 2641, + [BNXT_ULP_CLASS_HID_446de] = 2642, + [BNXT_ULP_CLASS_HID_45582] = 2643, + [BNXT_ULP_CLASS_HID_411ae] = 2644, + [BNXT_ULP_CLASS_HID_44b36] = 2645, + [BNXT_ULP_CLASS_HID_406d2] = 2646, + [BNXT_ULP_CLASS_HID_41586] = 2647, + [BNXT_ULP_CLASS_HID_40c96] = 2648, + [BNXT_ULP_CLASS_HID_42556] = 2649, + [BNXT_ULP_CLASS_HID_45ca6] = 2650, + [BNXT_ULP_CLASS_HID_42b6a] = 2651, + [BNXT_ULP_CLASS_HID_4427a] = 2652, + [BNXT_ULP_CLASS_HID_6227a] = 2653, + [BNXT_ULP_CLASS_HID_65d4a] = 2654, + [BNXT_ULP_CLASS_HID_6283e] = 2655, + [BNXT_ULP_CLASS_HID_6430e] = 2656, + [BNXT_ULP_CLASS_HID_61c9a] = 2657, + [BNXT_ULP_CLASS_HID_637ea] = 2658, + [BNXT_ULP_CLASS_HID_6025e] = 2659, + [BNXT_ULP_CLASS_HID_63dae] = 2660, + [BNXT_ULP_CLASS_HID_63bc2] = 2661, + [BNXT_ULP_CLASS_HID_652d2] = 2662, + [BNXT_ULP_CLASS_HID_62186] = 2663, + [BNXT_ULP_CLASS_HID_65896] = 2664, + [BNXT_ULP_CLASS_HID_61262] = 2665, + [BNXT_ULP_CLASS_HID_60d72] = 2666, + [BNXT_ULP_CLASS_HID_61826] = 2667, + [BNXT_ULP_CLASS_HID_63336] = 2668, + [BNXT_ULP_CLASS_HID_50c7a] = 2669, + [BNXT_ULP_CLASS_HID_5274a] = 2670, + [BNXT_ULP_CLASS_HID_5323e] = 2671, + [BNXT_ULP_CLASS_HID_52d0e] = 2672, + [BNXT_ULP_CLASS_HID_545ce] = 2673, + [BNXT_ULP_CLASS_HID_501ea] = 2674, + [BNXT_ULP_CLASS_HID_54b82] = 2675, + [BNXT_ULP_CLASS_HID_507ae] = 2676, + [BNXT_ULP_CLASS_HID_505c2] = 2677, + [BNXT_ULP_CLASS_HID_53cd2] = 2678, + [BNXT_ULP_CLASS_HID_50b86] = 2679, + [BNXT_ULP_CLASS_HID_52296] = 2680, + [BNXT_ULP_CLASS_HID_55b56] = 2681, + [BNXT_ULP_CLASS_HID_51772] = 2682, + [BNXT_ULP_CLASS_HID_5416a] = 2683, + [BNXT_ULP_CLASS_HID_51d36] = 2684, + [BNXT_ULP_CLASS_HID_7587a] = 2685, + [BNXT_ULP_CLASS_HID_71406] = 2686, + [BNXT_ULP_CLASS_HID_75e3e] = 2687, + [BNXT_ULP_CLASS_HID_71dda] = 2688, + [BNXT_ULP_CLASS_HID_7329a] = 2689, + [BNXT_ULP_CLASS_HID_72dea] = 2690, + [BNXT_ULP_CLASS_HID_7385e] = 2691, + [BNXT_ULP_CLASS_HID_753ae] = 2692, + [BNXT_ULP_CLASS_HID_751c2] = 2693, + [BNXT_ULP_CLASS_HID_748d2] = 2694, + [BNXT_ULP_CLASS_HID_75786] = 2695, + [BNXT_ULP_CLASS_HID_713a2] = 2696, + [BNXT_ULP_CLASS_HID_70862] = 2697, + [BNXT_ULP_CLASS_HID_72372] = 2698, + [BNXT_ULP_CLASS_HID_70e26] = 2699, + [BNXT_ULP_CLASS_HID_72936] = 2700, + [BNXT_ULP_CLASS_HID_229b8] = 2701, + [BNXT_ULP_CLASS_HID_240a8] = 2702, + [BNXT_ULP_CLASS_HID_22f74] = 2703, + [BNXT_ULP_CLASS_HID_24664] = 2704, + [BNXT_ULP_CLASS_HID_23314] = 2705, + [BNXT_ULP_CLASS_HID_22a04] = 2706, + [BNXT_ULP_CLASS_HID_238d0] = 2707, + [BNXT_ULP_CLASS_HID_253c0] = 2708, + [BNXT_ULP_CLASS_HID_24dcc] = 2709, + [BNXT_ULP_CLASS_HID_209f0] = 2710, + [BNXT_ULP_CLASS_HID_214bc] = 2711, + [BNXT_ULP_CLASS_HID_20fac] = 2712, + [BNXT_ULP_CLASS_HID_257a8] = 2713, + [BNXT_ULP_CLASS_HID_2134c] = 2714, + [BNXT_ULP_CLASS_HID_25d64] = 2715, + [BNXT_ULP_CLASS_HID_21908] = 2716, + [BNXT_ULP_CLASS_HID_23488] = 2717, + [BNXT_ULP_CLASS_HID_22ff8] = 2718, + [BNXT_ULP_CLASS_HID_23a44] = 2719, + [BNXT_ULP_CLASS_HID_255b4] = 2720, + [BNXT_ULP_CLASS_HID_21e64] = 2721, + [BNXT_ULP_CLASS_HID_23954] = 2722, + [BNXT_ULP_CLASS_HID_20420] = 2723, + [BNXT_ULP_CLASS_HID_23f10] = 2724, + [BNXT_ULP_CLASS_HID_2591c] = 2725, + [BNXT_ULP_CLASS_HID_214c0] = 2726, + [BNXT_ULP_CLASS_HID_25ed8] = 2727, + [BNXT_ULP_CLASS_HID_21afc] = 2728, + [BNXT_ULP_CLASS_HID_222f8] = 2729, + [BNXT_ULP_CLASS_HID_25de8] = 2730, + [BNXT_ULP_CLASS_HID_228b4] = 2731, + [BNXT_ULP_CLASS_HID_243a4] = 2732, + [BNXT_ULP_CLASS_HID_6226c] = 2733, + [BNXT_ULP_CLASS_HID_65d5c] = 2734, + [BNXT_ULP_CLASS_HID_62828] = 2735, + [BNXT_ULP_CLASS_HID_64318] = 2736, + [BNXT_ULP_CLASS_HID_60fc8] = 2737, + [BNXT_ULP_CLASS_HID_62738] = 2738, + [BNXT_ULP_CLASS_HID_63584] = 2739, + [BNXT_ULP_CLASS_HID_62cf4] = 2740, + [BNXT_ULP_CLASS_HID_64680] = 2741, + [BNXT_ULP_CLASS_HID_602a4] = 2742, + [BNXT_ULP_CLASS_HID_61170] = 2743, + [BNXT_ULP_CLASS_HID_60860] = 2744, + [BNXT_ULP_CLASS_HID_6505c] = 2745, + [BNXT_ULP_CLASS_HID_64b4c] = 2746, + [BNXT_ULP_CLASS_HID_65618] = 2747, + [BNXT_ULP_CLASS_HID_6123c] = 2748, + [BNXT_ULP_CLASS_HID_631bc] = 2749, + [BNXT_ULP_CLASS_HID_628ac] = 2750, + [BNXT_ULP_CLASS_HID_63778] = 2751, + [BNXT_ULP_CLASS_HID_62e68] = 2752, + [BNXT_ULP_CLASS_HID_61b18] = 2753, + [BNXT_ULP_CLASS_HID_63208] = 2754, + [BNXT_ULP_CLASS_HID_600d4] = 2755, + [BNXT_ULP_CLASS_HID_63bc4] = 2756, + [BNXT_ULP_CLASS_HID_655d0] = 2757, + [BNXT_ULP_CLASS_HID_611f4] = 2758, + [BNXT_ULP_CLASS_HID_65b8c] = 2759, + [BNXT_ULP_CLASS_HID_617b0] = 2760, + [BNXT_ULP_CLASS_HID_63fac] = 2761, + [BNXT_ULP_CLASS_HID_6569c] = 2762, + [BNXT_ULP_CLASS_HID_62568] = 2763, + [BNXT_ULP_CLASS_HID_65c58] = 2764, + [BNXT_ULP_CLASS_HID_35fb8] = 2765, + [BNXT_ULP_CLASS_HID_31b5c] = 2766, + [BNXT_ULP_CLASS_HID_34574] = 2767, + [BNXT_ULP_CLASS_HID_30118] = 2768, + [BNXT_ULP_CLASS_HID_32914] = 2769, + [BNXT_ULP_CLASS_HID_34004] = 2770, + [BNXT_ULP_CLASS_HID_32ed0] = 2771, + [BNXT_ULP_CLASS_HID_349c0] = 2772, + [BNXT_ULP_CLASS_HID_30480] = 2773, + [BNXT_ULP_CLASS_HID_33ff0] = 2774, + [BNXT_ULP_CLASS_HID_30abc] = 2775, + [BNXT_ULP_CLASS_HID_325ac] = 2776, + [BNXT_ULP_CLASS_HID_34da8] = 2777, + [BNXT_ULP_CLASS_HID_3094c] = 2778, + [BNXT_ULP_CLASS_HID_31418] = 2779, + [BNXT_ULP_CLASS_HID_30f08] = 2780, + [BNXT_ULP_CLASS_HID_32a88] = 2781, + [BNXT_ULP_CLASS_HID_345f8] = 2782, + [BNXT_ULP_CLASS_HID_35044] = 2783, + [BNXT_ULP_CLASS_HID_34bb4] = 2784, + [BNXT_ULP_CLASS_HID_33464] = 2785, + [BNXT_ULP_CLASS_HID_32f54] = 2786, + [BNXT_ULP_CLASS_HID_33a20] = 2787, + [BNXT_ULP_CLASS_HID_35510] = 2788, + [BNXT_ULP_CLASS_HID_313d0] = 2789, + [BNXT_ULP_CLASS_HID_30ac0] = 2790, + [BNXT_ULP_CLASS_HID_3198c] = 2791, + [BNXT_ULP_CLASS_HID_330fc] = 2792, + [BNXT_ULP_CLASS_HID_358f8] = 2793, + [BNXT_ULP_CLASS_HID_3149c] = 2794, + [BNXT_ULP_CLASS_HID_35eb4] = 2795, + [BNXT_ULP_CLASS_HID_31a58] = 2796, + [BNXT_ULP_CLASS_HID_7586c] = 2797, + [BNXT_ULP_CLASS_HID_71410] = 2798, + [BNXT_ULP_CLASS_HID_75e28] = 2799, + [BNXT_ULP_CLASS_HID_71dcc] = 2800, + [BNXT_ULP_CLASS_HID_725c8] = 2801, + [BNXT_ULP_CLASS_HID_75d38] = 2802, + [BNXT_ULP_CLASS_HID_72b84] = 2803, + [BNXT_ULP_CLASS_HID_742f4] = 2804, + [BNXT_ULP_CLASS_HID_701b4] = 2805, + [BNXT_ULP_CLASS_HID_738a4] = 2806, + [BNXT_ULP_CLASS_HID_70770] = 2807, + [BNXT_ULP_CLASS_HID_73e60] = 2808, + [BNXT_ULP_CLASS_HID_7465c] = 2809, + [BNXT_ULP_CLASS_HID_70200] = 2810, + [BNXT_ULP_CLASS_HID_710cc] = 2811, + [BNXT_ULP_CLASS_HID_7083c] = 2812, + [BNXT_ULP_CLASS_HID_727bc] = 2813, + [BNXT_ULP_CLASS_HID_75eac] = 2814, + [BNXT_ULP_CLASS_HID_72d78] = 2815, + [BNXT_ULP_CLASS_HID_74468] = 2816, + [BNXT_ULP_CLASS_HID_73118] = 2817, + [BNXT_ULP_CLASS_HID_72808] = 2818, + [BNXT_ULP_CLASS_HID_736d4] = 2819, + [BNXT_ULP_CLASS_HID_751c4] = 2820, + [BNXT_ULP_CLASS_HID_74bd0] = 2821, + [BNXT_ULP_CLASS_HID_707f4] = 2822, + [BNXT_ULP_CLASS_HID_71240] = 2823, + [BNXT_ULP_CLASS_HID_70db0] = 2824, + [BNXT_ULP_CLASS_HID_755ac] = 2825, + [BNXT_ULP_CLASS_HID_71150] = 2826, + [BNXT_ULP_CLASS_HID_75b68] = 2827, + [BNXT_ULP_CLASS_HID_7170c] = 2828, + [BNXT_ULP_CLASS_HID_2d2b8] = 2829, + [BNXT_ULP_CLASS_HID_2cda8] = 2830, + [BNXT_ULP_CLASS_HID_2d874] = 2831, + [BNXT_ULP_CLASS_HID_29418] = 2832, + [BNXT_ULP_CLASS_HID_2bc14] = 2833, + [BNXT_ULP_CLASS_HID_2d704] = 2834, + [BNXT_ULP_CLASS_HID_2a5d0] = 2835, + [BNXT_ULP_CLASS_HID_2dcc0] = 2836, + [BNXT_ULP_CLASS_HID_29b80] = 2837, + [BNXT_ULP_CLASS_HID_2b2f0] = 2838, + [BNXT_ULP_CLASS_HID_281bc] = 2839, + [BNXT_ULP_CLASS_HID_2b8ac] = 2840, + [BNXT_ULP_CLASS_HID_2c0a8] = 2841, + [BNXT_ULP_CLASS_HID_29c4c] = 2842, + [BNXT_ULP_CLASS_HID_2c664] = 2843, + [BNXT_ULP_CLASS_HID_28208] = 2844, + [BNXT_ULP_CLASS_HID_2a188] = 2845, + [BNXT_ULP_CLASS_HID_2d8f8] = 2846, + [BNXT_ULP_CLASS_HID_2a744] = 2847, + [BNXT_ULP_CLASS_HID_2deb4] = 2848, + [BNXT_ULP_CLASS_HID_28b64] = 2849, + [BNXT_ULP_CLASS_HID_2a254] = 2850, + [BNXT_ULP_CLASS_HID_2b120] = 2851, + [BNXT_ULP_CLASS_HID_2a810] = 2852, + [BNXT_ULP_CLASS_HID_2c21c] = 2853, + [BNXT_ULP_CLASS_HID_281c0] = 2854, + [BNXT_ULP_CLASS_HID_2cbd8] = 2855, + [BNXT_ULP_CLASS_HID_287fc] = 2856, + [BNXT_ULP_CLASS_HID_2aff8] = 2857, + [BNXT_ULP_CLASS_HID_2c6e8] = 2858, + [BNXT_ULP_CLASS_HID_2d5b4] = 2859, + [BNXT_ULP_CLASS_HID_29158] = 2860, + [BNXT_ULP_CLASS_HID_6af6c] = 2861, + [BNXT_ULP_CLASS_HID_6c65c] = 2862, + [BNXT_ULP_CLASS_HID_6d528] = 2863, + [BNXT_ULP_CLASS_HID_690cc] = 2864, + [BNXT_ULP_CLASS_HID_6b8c8] = 2865, + [BNXT_ULP_CLASS_HID_6d038] = 2866, + [BNXT_ULP_CLASS_HID_6be84] = 2867, + [BNXT_ULP_CLASS_HID_6d9f4] = 2868, + [BNXT_ULP_CLASS_HID_694b4] = 2869, + [BNXT_ULP_CLASS_HID_68fa4] = 2870, + [BNXT_ULP_CLASS_HID_69a70] = 2871, + [BNXT_ULP_CLASS_HID_6b560] = 2872, + [BNXT_ULP_CLASS_HID_6dd5c] = 2873, + [BNXT_ULP_CLASS_HID_69900] = 2874, + [BNXT_ULP_CLASS_HID_6c318] = 2875, + [BNXT_ULP_CLASS_HID_69f3c] = 2876, + [BNXT_ULP_CLASS_HID_6babc] = 2877, + [BNXT_ULP_CLASS_HID_6d5ac] = 2878, + [BNXT_ULP_CLASS_HID_6a078] = 2879, + [BNXT_ULP_CLASS_HID_6db68] = 2880, + [BNXT_ULP_CLASS_HID_68418] = 2881, + [BNXT_ULP_CLASS_HID_6bf08] = 2882, + [BNXT_ULP_CLASS_HID_68dd4] = 2883, + [BNXT_ULP_CLASS_HID_6a4c4] = 2884, + [BNXT_ULP_CLASS_HID_6ded0] = 2885, + [BNXT_ULP_CLASS_HID_69af4] = 2886, + [BNXT_ULP_CLASS_HID_6c48c] = 2887, + [BNXT_ULP_CLASS_HID_680b0] = 2888, + [BNXT_ULP_CLASS_HID_6a8ac] = 2889, + [BNXT_ULP_CLASS_HID_6c39c] = 2890, + [BNXT_ULP_CLASS_HID_6ae68] = 2891, + [BNXT_ULP_CLASS_HID_6c958] = 2892, + [BNXT_ULP_CLASS_HID_3c8b8] = 2893, + [BNXT_ULP_CLASS_HID_3845c] = 2894, + [BNXT_ULP_CLASS_HID_39328] = 2895, + [BNXT_ULP_CLASS_HID_38a18] = 2896, + [BNXT_ULP_CLASS_HID_3d214] = 2897, + [BNXT_ULP_CLASS_HID_3cd04] = 2898, + [BNXT_ULP_CLASS_HID_3dbd0] = 2899, + [BNXT_ULP_CLASS_HID_397f4] = 2900, + [BNXT_ULP_CLASS_HID_3b180] = 2901, + [BNXT_ULP_CLASS_HID_3a8f0] = 2902, + [BNXT_ULP_CLASS_HID_3b7bc] = 2903, + [BNXT_ULP_CLASS_HID_3aeac] = 2904, + [BNXT_ULP_CLASS_HID_39b5c] = 2905, + [BNXT_ULP_CLASS_HID_3b24c] = 2906, + [BNXT_ULP_CLASS_HID_38118] = 2907, + [BNXT_ULP_CLASS_HID_3b808] = 2908, + [BNXT_ULP_CLASS_HID_3d788] = 2909, + [BNXT_ULP_CLASS_HID_393ac] = 2910, + [BNXT_ULP_CLASS_HID_3dd44] = 2911, + [BNXT_ULP_CLASS_HID_39968] = 2912, + [BNXT_ULP_CLASS_HID_3a164] = 2913, + [BNXT_ULP_CLASS_HID_3d854] = 2914, + [BNXT_ULP_CLASS_HID_3a720] = 2915, + [BNXT_ULP_CLASS_HID_3de10] = 2916, + [BNXT_ULP_CLASS_HID_39cd0] = 2917, + [BNXT_ULP_CLASS_HID_3b7c0] = 2918, + [BNXT_ULP_CLASS_HID_3828c] = 2919, + [BNXT_ULP_CLASS_HID_3bdfc] = 2920, + [BNXT_ULP_CLASS_HID_3c5f8] = 2921, + [BNXT_ULP_CLASS_HID_3819c] = 2922, + [BNXT_ULP_CLASS_HID_3cbb4] = 2923, + [BNXT_ULP_CLASS_HID_38758] = 2924, + [BNXT_ULP_CLASS_HID_7c56c] = 2925, + [BNXT_ULP_CLASS_HID_78110] = 2926, + [BNXT_ULP_CLASS_HID_7cb28] = 2927, + [BNXT_ULP_CLASS_HID_786cc] = 2928, + [BNXT_ULP_CLASS_HID_7aec8] = 2929, + [BNXT_ULP_CLASS_HID_7c638] = 2930, + [BNXT_ULP_CLASS_HID_7d484] = 2931, + [BNXT_ULP_CLASS_HID_790a8] = 2932, + [BNXT_ULP_CLASS_HID_78ab4] = 2933, + [BNXT_ULP_CLASS_HID_7a5a4] = 2934, + [BNXT_ULP_CLASS_HID_7b070] = 2935, + [BNXT_ULP_CLASS_HID_7ab60] = 2936, + [BNXT_ULP_CLASS_HID_79410] = 2937, + [BNXT_ULP_CLASS_HID_78f00] = 2938, + [BNXT_ULP_CLASS_HID_79dcc] = 2939, + [BNXT_ULP_CLASS_HID_7b53c] = 2940, + [BNXT_ULP_CLASS_HID_7d0bc] = 2941, + [BNXT_ULP_CLASS_HID_7cbac] = 2942, + [BNXT_ULP_CLASS_HID_7d678] = 2943, + [BNXT_ULP_CLASS_HID_7921c] = 2944, + [BNXT_ULP_CLASS_HID_7ba18] = 2945, + [BNXT_ULP_CLASS_HID_7d508] = 2946, + [BNXT_ULP_CLASS_HID_7a3d4] = 2947, + [BNXT_ULP_CLASS_HID_7dac4] = 2948, + [BNXT_ULP_CLASS_HID_79984] = 2949, + [BNXT_ULP_CLASS_HID_7b0f4] = 2950, + [BNXT_ULP_CLASS_HID_79f40] = 2951, + [BNXT_ULP_CLASS_HID_7b6b0] = 2952, + [BNXT_ULP_CLASS_HID_7deac] = 2953, + [BNXT_ULP_CLASS_HID_79a50] = 2954, + [BNXT_ULP_CLASS_HID_7c468] = 2955, + [BNXT_ULP_CLASS_HID_7800c] = 2956, + [BNXT_ULP_CLASS_HID_86c0] = 2957, + [BNXT_ULP_CLASS_HID_a1d0] = 2958, + [BNXT_ULP_CLASS_HID_8c0c] = 2959, + [BNXT_ULP_CLASS_HID_a71c] = 2960, + [BNXT_ULP_CLASS_HID_906c] = 2961, + [BNXT_ULP_CLASS_HID_8b7c] = 2962, + [BNXT_ULP_CLASS_HID_99a8] = 2963, + [BNXT_ULP_CLASS_HID_b0b8] = 2964, + [BNXT_ULP_CLASS_HID_aab4] = 2965, + [BNXT_ULP_CLASS_HID_c244] = 2966, + [BNXT_ULP_CLASS_HID_d0f0] = 2967, + [BNXT_ULP_CLASS_HID_cb80] = 2968, + [BNXT_ULP_CLASS_HID_b4d0] = 2969, + [BNXT_ULP_CLASS_HID_afe0] = 2970, + [BNXT_ULP_CLASS_HID_ba1c] = 2971, + [BNXT_ULP_CLASS_HID_d52c] = 2972, + [BNXT_ULP_CLASS_HID_48314] = 2973, + [BNXT_ULP_CLASS_HID_4ba24] = 2974, + [BNXT_ULP_CLASS_HID_48950] = 2975, + [BNXT_ULP_CLASS_HID_4a060] = 2976, + [BNXT_ULP_CLASS_HID_4c86c] = 2977, + [BNXT_ULP_CLASS_HID_48440] = 2978, + [BNXT_ULP_CLASS_HID_492fc] = 2979, + [BNXT_ULP_CLASS_HID_48d8c] = 2980, + [BNXT_ULP_CLASS_HID_4a7f8] = 2981, + [BNXT_ULP_CLASS_HID_4de88] = 2982, + [BNXT_ULP_CLASS_HID_4adc4] = 2983, + [BNXT_ULP_CLASS_HID_4c4d4] = 2984, + [BNXT_ULP_CLASS_HID_4b124] = 2985, + [BNXT_ULP_CLASS_HID_4a834] = 2986, + [BNXT_ULP_CLASS_HID_4b760] = 2987, + [BNXT_ULP_CLASS_HID_4ae70] = 2988, + [BNXT_ULP_CLASS_HID_1bcc0] = 2989, + [BNXT_ULP_CLASS_HID_1d7d0] = 2990, + [BNXT_ULP_CLASS_HID_1a20c] = 2991, + [BNXT_ULP_CLASS_HID_1dd1c] = 2992, + [BNXT_ULP_CLASS_HID_1866c] = 2993, + [BNXT_ULP_CLASS_HID_1a17c] = 2994, + [BNXT_ULP_CLASS_HID_18fa8] = 2995, + [BNXT_ULP_CLASS_HID_1a6b8] = 2996, + [BNXT_ULP_CLASS_HID_1c0b4] = 2997, + [BNXT_ULP_CLASS_HID_19c88] = 2998, + [BNXT_ULP_CLASS_HID_1c6f0] = 2999, + [BNXT_ULP_CLASS_HID_182d4] = 3000, + [BNXT_ULP_CLASS_HID_1aad0] = 3001, + [BNXT_ULP_CLASS_HID_1c5e0] = 3002, + [BNXT_ULP_CLASS_HID_1d01c] = 3003, + [BNXT_ULP_CLASS_HID_1cb2c] = 3004, + [BNXT_ULP_CLASS_HID_5b914] = 3005, + [BNXT_ULP_CLASS_HID_5d024] = 3006, + [BNXT_ULP_CLASS_HID_5bf50] = 3007, + [BNXT_ULP_CLASS_HID_5d660] = 3008, + [BNXT_ULP_CLASS_HID_582b0] = 3009, + [BNXT_ULP_CLASS_HID_5ba40] = 3010, + [BNXT_ULP_CLASS_HID_588fc] = 3011, + [BNXT_ULP_CLASS_HID_5a38c] = 3012, + [BNXT_ULP_CLASS_HID_5ddf8] = 3013, + [BNXT_ULP_CLASS_HID_599dc] = 3014, + [BNXT_ULP_CLASS_HID_5c3c4] = 3015, + [BNXT_ULP_CLASS_HID_59f18] = 3016, + [BNXT_ULP_CLASS_HID_5a724] = 3017, + [BNXT_ULP_CLASS_HID_5de34] = 3018, + [BNXT_ULP_CLASS_HID_5ad60] = 3019, + [BNXT_ULP_CLASS_HID_5c470] = 3020, + [BNXT_ULP_CLASS_HID_cd40] = 3021, + [BNXT_ULP_CLASS_HID_e450] = 3022, + [BNXT_ULP_CLASS_HID_f28c] = 3023, + [BNXT_ULP_CLASS_HID_ed9c] = 3024, + [BNXT_ULP_CLASS_HID_d6ec] = 3025, + [BNXT_ULP_CLASS_HID_f1fc] = 3026, + [BNXT_ULP_CLASS_HID_dc28] = 3027, + [BNXT_ULP_CLASS_HID_f738] = 3028, + [BNXT_ULP_CLASS_HID_d134] = 3029, + [BNXT_ULP_CLASS_HID_c8c4] = 3030, + [BNXT_ULP_CLASS_HID_d770] = 3031, + [BNXT_ULP_CLASS_HID_d354] = 3032, + [BNXT_ULP_CLASS_HID_fb50] = 3033, + [BNXT_ULP_CLASS_HID_d260] = 3034, + [BNXT_ULP_CLASS_HID_e09c] = 3035, + [BNXT_ULP_CLASS_HID_dbac] = 3036, + [BNXT_ULP_CLASS_HID_4c994] = 3037, + [BNXT_ULP_CLASS_HID_4e0a4] = 3038, + [BNXT_ULP_CLASS_HID_4cfd0] = 3039, + [BNXT_ULP_CLASS_HID_4e6e0] = 3040, + [BNXT_ULP_CLASS_HID_4d330] = 3041, + [BNXT_ULP_CLASS_HID_4cac0] = 3042, + [BNXT_ULP_CLASS_HID_4d97c] = 3043, + [BNXT_ULP_CLASS_HID_4f00c] = 3044, + [BNXT_ULP_CLASS_HID_4ea78] = 3045, + [BNXT_ULP_CLASS_HID_4c508] = 3046, + [BNXT_ULP_CLASS_HID_4d044] = 3047, + [BNXT_ULP_CLASS_HID_4cb54] = 3048, + [BNXT_ULP_CLASS_HID_4f7a4] = 3049, + [BNXT_ULP_CLASS_HID_4eeb4] = 3050, + [BNXT_ULP_CLASS_HID_4fde0] = 3051, + [BNXT_ULP_CLASS_HID_4d4f0] = 3052, + [BNXT_ULP_CLASS_HID_1e340] = 3053, + [BNXT_ULP_CLASS_HID_1da50] = 3054, + [BNXT_ULP_CLASS_HID_1e88c] = 3055, + [BNXT_ULP_CLASS_HID_1c39c] = 3056, + [BNXT_ULP_CLASS_HID_1ccec] = 3057, + [BNXT_ULP_CLASS_HID_1e7fc] = 3058, + [BNXT_ULP_CLASS_HID_1f228] = 3059, + [BNXT_ULP_CLASS_HID_1ed38] = 3060, + [BNXT_ULP_CLASS_HID_1c734] = 3061, + [BNXT_ULP_CLASS_HID_1c308] = 3062, + [BNXT_ULP_CLASS_HID_1cd70] = 3063, + [BNXT_ULP_CLASS_HID_1c954] = 3064, + [BNXT_ULP_CLASS_HID_1d150] = 3065, + [BNXT_ULP_CLASS_HID_1c860] = 3066, + [BNXT_ULP_CLASS_HID_1d69c] = 3067, + [BNXT_ULP_CLASS_HID_1d2f0] = 3068, + [BNXT_ULP_CLASS_HID_5ff94] = 3069, + [BNXT_ULP_CLASS_HID_5d6a4] = 3070, + [BNXT_ULP_CLASS_HID_5e5d0] = 3071, + [BNXT_ULP_CLASS_HID_5dce0] = 3072, + [BNXT_ULP_CLASS_HID_5c930] = 3073, + [BNXT_ULP_CLASS_HID_5e0c0] = 3074, + [BNXT_ULP_CLASS_HID_5cf7c] = 3075, + [BNXT_ULP_CLASS_HID_5e60c] = 3076, + [BNXT_ULP_CLASS_HID_5c078] = 3077, + [BNXT_ULP_CLASS_HID_5dc5c] = 3078, + [BNXT_ULP_CLASS_HID_5c644] = 3079, + [BNXT_ULP_CLASS_HID_5c598] = 3080, + [BNXT_ULP_CLASS_HID_5eda4] = 3081, + [BNXT_ULP_CLASS_HID_5c4b4] = 3082, + [BNXT_ULP_CLASS_HID_5d3e0] = 3083, + [BNXT_ULP_CLASS_HID_5caf0] = 3084, + [BNXT_ULP_CLASS_HID_ab80] = 3085, + [BNXT_ULP_CLASS_HID_a290] = 3086, + [BNXT_ULP_CLASS_HID_b1cc] = 3087, + [BNXT_ULP_CLASS_HID_a8dc] = 3088, + [BNXT_ULP_CLASS_HID_b52c] = 3089, + [BNXT_ULP_CLASS_HID_ac3c] = 3090, + [BNXT_ULP_CLASS_HID_bb68] = 3091, + [BNXT_ULP_CLASS_HID_b278] = 3092, + [BNXT_ULP_CLASS_HID_ac74] = 3093, + [BNXT_ULP_CLASS_HID_e704] = 3094, + [BNXT_ULP_CLASS_HID_f5b0] = 3095, + [BNXT_ULP_CLASS_HID_b194] = 3096, + [BNXT_ULP_CLASS_HID_b990] = 3097, + [BNXT_ULP_CLASS_HID_f0a0] = 3098, + [BNXT_ULP_CLASS_HID_bfdc] = 3099, + [BNXT_ULP_CLASS_HID_f6ec] = 3100, + [BNXT_ULP_CLASS_HID_4a4d4] = 3101, + [BNXT_ULP_CLASS_HID_4bfe4] = 3102, + [BNXT_ULP_CLASS_HID_4aa10] = 3103, + [BNXT_ULP_CLASS_HID_4a520] = 3104, + [BNXT_ULP_CLASS_HID_4ed2c] = 3105, + [BNXT_ULP_CLASS_HID_4a900] = 3106, + [BNXT_ULP_CLASS_HID_4b7bc] = 3107, + [BNXT_ULP_CLASS_HID_4af4c] = 3108, + [BNXT_ULP_CLASS_HID_4a8b8] = 3109, + [BNXT_ULP_CLASS_HID_4e048] = 3110, + [BNXT_ULP_CLASS_HID_4ae84] = 3111, + [BNXT_ULP_CLASS_HID_4e994] = 3112, + [BNXT_ULP_CLASS_HID_4b2e4] = 3113, + [BNXT_ULP_CLASS_HID_4adf4] = 3114, + [BNXT_ULP_CLASS_HID_4b820] = 3115, + [BNXT_ULP_CLASS_HID_4f330] = 3116, + [BNXT_ULP_CLASS_HID_1a180] = 3117, + [BNXT_ULP_CLASS_HID_1f890] = 3118, + [BNXT_ULP_CLASS_HID_1a7cc] = 3119, + [BNXT_ULP_CLASS_HID_1fedc] = 3120, + [BNXT_ULP_CLASS_HID_1ab2c] = 3121, + [BNXT_ULP_CLASS_HID_1a23c] = 3122, + [BNXT_ULP_CLASS_HID_1b168] = 3123, + [BNXT_ULP_CLASS_HID_1a878] = 3124, + [BNXT_ULP_CLASS_HID_1e274] = 3125, + [BNXT_ULP_CLASS_HID_1be48] = 3126, + [BNXT_ULP_CLASS_HID_1ebb0] = 3127, + [BNXT_ULP_CLASS_HID_1a794] = 3128, + [BNXT_ULP_CLASS_HID_1af90] = 3129, + [BNXT_ULP_CLASS_HID_1e6a0] = 3130, + [BNXT_ULP_CLASS_HID_1f5dc] = 3131, + [BNXT_ULP_CLASS_HID_1b130] = 3132, + [BNXT_ULP_CLASS_HID_5bad4] = 3133, + [BNXT_ULP_CLASS_HID_5f5e4] = 3134, + [BNXT_ULP_CLASS_HID_5a010] = 3135, + [BNXT_ULP_CLASS_HID_5fb20] = 3136, + [BNXT_ULP_CLASS_HID_5a470] = 3137, + [BNXT_ULP_CLASS_HID_5bf00] = 3138, + [BNXT_ULP_CLASS_HID_5adbc] = 3139, + [BNXT_ULP_CLASS_HID_5a54c] = 3140, + [BNXT_ULP_CLASS_HID_5feb8] = 3141, + [BNXT_ULP_CLASS_HID_5ba9c] = 3142, + [BNXT_ULP_CLASS_HID_5e484] = 3143, + [BNXT_ULP_CLASS_HID_5a0d8] = 3144, + [BNXT_ULP_CLASS_HID_5a8e4] = 3145, + [BNXT_ULP_CLASS_HID_5e3f4] = 3146, + [BNXT_ULP_CLASS_HID_5ae20] = 3147, + [BNXT_ULP_CLASS_HID_5e930] = 3148, + [BNXT_ULP_CLASS_HID_ee00] = 3149, + [BNXT_ULP_CLASS_HID_e910] = 3150, + [BNXT_ULP_CLASS_HID_f44c] = 3151, + [BNXT_ULP_CLASS_HID_ef5c] = 3152, + [BNXT_ULP_CLASS_HID_fbac] = 3153, + [BNXT_ULP_CLASS_HID_f2bc] = 3154, + [BNXT_ULP_CLASS_HID_e1e8] = 3155, + [BNXT_ULP_CLASS_HID_f8f8] = 3156, + [BNXT_ULP_CLASS_HID_f2f4] = 3157, + [BNXT_ULP_CLASS_HID_ed84] = 3158, + [BNXT_ULP_CLASS_HID_f830] = 3159, + [BNXT_ULP_CLASS_HID_f414] = 3160, + [BNXT_ULP_CLASS_HID_fc10] = 3161, + [BNXT_ULP_CLASS_HID_f720] = 3162, + [BNXT_ULP_CLASS_HID_e25c] = 3163, + [BNXT_ULP_CLASS_HID_fd6c] = 3164, + [BNXT_ULP_CLASS_HID_4eb54] = 3165, + [BNXT_ULP_CLASS_HID_4e264] = 3166, + [BNXT_ULP_CLASS_HID_4f090] = 3167, + [BNXT_ULP_CLASS_HID_4eba0] = 3168, + [BNXT_ULP_CLASS_HID_4f4f0] = 3169, + [BNXT_ULP_CLASS_HID_4ef80] = 3170, + [BNXT_ULP_CLASS_HID_4fa3c] = 3171, + [BNXT_ULP_CLASS_HID_4f5cc] = 3172, + [BNXT_ULP_CLASS_HID_4ef38] = 3173, + [BNXT_ULP_CLASS_HID_4e6c8] = 3174, + [BNXT_ULP_CLASS_HID_4f504] = 3175, + [BNXT_ULP_CLASS_HID_4f158] = 3176, + [BNXT_ULP_CLASS_HID_4f964] = 3177, + [BNXT_ULP_CLASS_HID_4f074] = 3178, + [BNXT_ULP_CLASS_HID_4fea0] = 3179, + [BNXT_ULP_CLASS_HID_4f9b0] = 3180, + [BNXT_ULP_CLASS_HID_1e400] = 3181, + [BNXT_ULP_CLASS_HID_1ff10] = 3182, + [BNXT_ULP_CLASS_HID_1ea4c] = 3183, + [BNXT_ULP_CLASS_HID_1e55c] = 3184, + [BNXT_ULP_CLASS_HID_1f1ac] = 3185, + [BNXT_ULP_CLASS_HID_1e8bc] = 3186, + [BNXT_ULP_CLASS_HID_1f7e8] = 3187, + [BNXT_ULP_CLASS_HID_1eef8] = 3188, + [BNXT_ULP_CLASS_HID_1e8f4] = 3189, + [BNXT_ULP_CLASS_HID_1e4c8] = 3190, + [BNXT_ULP_CLASS_HID_1f304] = 3191, + [BNXT_ULP_CLASS_HID_1ea14] = 3192, + [BNXT_ULP_CLASS_HID_1f210] = 3193, + [BNXT_ULP_CLASS_HID_1ed20] = 3194, + [BNXT_ULP_CLASS_HID_1f85c] = 3195, + [BNXT_ULP_CLASS_HID_1f7b0] = 3196, + [BNXT_ULP_CLASS_HID_5e154] = 3197, + [BNXT_ULP_CLASS_HID_5f864] = 3198, + [BNXT_ULP_CLASS_HID_5e690] = 3199, + [BNXT_ULP_CLASS_HID_5e1a0] = 3200, + [BNXT_ULP_CLASS_HID_5eaf0] = 3201, + [BNXT_ULP_CLASS_HID_5e580] = 3202, + [BNXT_ULP_CLASS_HID_5f03c] = 3203, + [BNXT_ULP_CLASS_HID_5ebcc] = 3204, + [BNXT_ULP_CLASS_HID_5e538] = 3205, + [BNXT_ULP_CLASS_HID_5e11c] = 3206, + [BNXT_ULP_CLASS_HID_5eb04] = 3207, + [BNXT_ULP_CLASS_HID_5e758] = 3208, + [BNXT_ULP_CLASS_HID_5ef64] = 3209, + [BNXT_ULP_CLASS_HID_5e674] = 3210, + [BNXT_ULP_CLASS_HID_5f4a0] = 3211, + [BNXT_ULP_CLASS_HID_5f084] = 3212, + [BNXT_ULP_CLASS_HID_22998] = 3213, + [BNXT_ULP_CLASS_HID_24088] = 3214, + [BNXT_ULP_CLASS_HID_22f54] = 3215, + [BNXT_ULP_CLASS_HID_24644] = 3216, + [BNXT_ULP_CLASS_HID_23334] = 3217, + [BNXT_ULP_CLASS_HID_22a24] = 3218, + [BNXT_ULP_CLASS_HID_238f0] = 3219, + [BNXT_ULP_CLASS_HID_253e0] = 3220, + [BNXT_ULP_CLASS_HID_24dec] = 3221, + [BNXT_ULP_CLASS_HID_209d0] = 3222, + [BNXT_ULP_CLASS_HID_2149c] = 3223, + [BNXT_ULP_CLASS_HID_20f8c] = 3224, + [BNXT_ULP_CLASS_HID_25788] = 3225, + [BNXT_ULP_CLASS_HID_2136c] = 3226, + [BNXT_ULP_CLASS_HID_25d44] = 3227, + [BNXT_ULP_CLASS_HID_21928] = 3228, + [BNXT_ULP_CLASS_HID_234a8] = 3229, + [BNXT_ULP_CLASS_HID_22fd8] = 3230, + [BNXT_ULP_CLASS_HID_23a64] = 3231, + [BNXT_ULP_CLASS_HID_25594] = 3232, + [BNXT_ULP_CLASS_HID_21e44] = 3233, + [BNXT_ULP_CLASS_HID_23974] = 3234, + [BNXT_ULP_CLASS_HID_20400] = 3235, + [BNXT_ULP_CLASS_HID_23f30] = 3236, + [BNXT_ULP_CLASS_HID_2593c] = 3237, + [BNXT_ULP_CLASS_HID_214e0] = 3238, + [BNXT_ULP_CLASS_HID_25ef8] = 3239, + [BNXT_ULP_CLASS_HID_21adc] = 3240, + [BNXT_ULP_CLASS_HID_222d8] = 3241, + [BNXT_ULP_CLASS_HID_25dc8] = 3242, + [BNXT_ULP_CLASS_HID_22894] = 3243, + [BNXT_ULP_CLASS_HID_24384] = 3244, + [BNXT_ULP_CLASS_HID_6224c] = 3245, + [BNXT_ULP_CLASS_HID_65d7c] = 3246, + [BNXT_ULP_CLASS_HID_62808] = 3247, + [BNXT_ULP_CLASS_HID_64338] = 3248, + [BNXT_ULP_CLASS_HID_60fe8] = 3249, + [BNXT_ULP_CLASS_HID_62718] = 3250, + [BNXT_ULP_CLASS_HID_635a4] = 3251, + [BNXT_ULP_CLASS_HID_62cd4] = 3252, + [BNXT_ULP_CLASS_HID_646a0] = 3253, + [BNXT_ULP_CLASS_HID_60284] = 3254, + [BNXT_ULP_CLASS_HID_61150] = 3255, + [BNXT_ULP_CLASS_HID_60840] = 3256, + [BNXT_ULP_CLASS_HID_6507c] = 3257, + [BNXT_ULP_CLASS_HID_64b6c] = 3258, + [BNXT_ULP_CLASS_HID_65638] = 3259, + [BNXT_ULP_CLASS_HID_6121c] = 3260, + [BNXT_ULP_CLASS_HID_6319c] = 3261, + [BNXT_ULP_CLASS_HID_6288c] = 3262, + [BNXT_ULP_CLASS_HID_63758] = 3263, + [BNXT_ULP_CLASS_HID_62e48] = 3264, + [BNXT_ULP_CLASS_HID_61b38] = 3265, + [BNXT_ULP_CLASS_HID_63228] = 3266, + [BNXT_ULP_CLASS_HID_600f4] = 3267, + [BNXT_ULP_CLASS_HID_63be4] = 3268, + [BNXT_ULP_CLASS_HID_655f0] = 3269, + [BNXT_ULP_CLASS_HID_611d4] = 3270, + [BNXT_ULP_CLASS_HID_65bac] = 3271, + [BNXT_ULP_CLASS_HID_61790] = 3272, + [BNXT_ULP_CLASS_HID_63f8c] = 3273, + [BNXT_ULP_CLASS_HID_656bc] = 3274, + [BNXT_ULP_CLASS_HID_62548] = 3275, + [BNXT_ULP_CLASS_HID_65c78] = 3276, + [BNXT_ULP_CLASS_HID_35f98] = 3277, + [BNXT_ULP_CLASS_HID_31b7c] = 3278, + [BNXT_ULP_CLASS_HID_34554] = 3279, + [BNXT_ULP_CLASS_HID_30138] = 3280, + [BNXT_ULP_CLASS_HID_32934] = 3281, + [BNXT_ULP_CLASS_HID_34024] = 3282, + [BNXT_ULP_CLASS_HID_32ef0] = 3283, + [BNXT_ULP_CLASS_HID_349e0] = 3284, + [BNXT_ULP_CLASS_HID_304a0] = 3285, + [BNXT_ULP_CLASS_HID_33fd0] = 3286, + [BNXT_ULP_CLASS_HID_30a9c] = 3287, + [BNXT_ULP_CLASS_HID_3258c] = 3288, + [BNXT_ULP_CLASS_HID_34d88] = 3289, + [BNXT_ULP_CLASS_HID_3096c] = 3290, + [BNXT_ULP_CLASS_HID_31438] = 3291, + [BNXT_ULP_CLASS_HID_30f28] = 3292, + [BNXT_ULP_CLASS_HID_32aa8] = 3293, + [BNXT_ULP_CLASS_HID_345d8] = 3294, + [BNXT_ULP_CLASS_HID_35064] = 3295, + [BNXT_ULP_CLASS_HID_34b94] = 3296, + [BNXT_ULP_CLASS_HID_33444] = 3297, + [BNXT_ULP_CLASS_HID_32f74] = 3298, + [BNXT_ULP_CLASS_HID_33a00] = 3299, + [BNXT_ULP_CLASS_HID_35530] = 3300, + [BNXT_ULP_CLASS_HID_313f0] = 3301, + [BNXT_ULP_CLASS_HID_30ae0] = 3302, + [BNXT_ULP_CLASS_HID_319ac] = 3303, + [BNXT_ULP_CLASS_HID_330dc] = 3304, + [BNXT_ULP_CLASS_HID_358d8] = 3305, + [BNXT_ULP_CLASS_HID_314bc] = 3306, + [BNXT_ULP_CLASS_HID_35e94] = 3307, + [BNXT_ULP_CLASS_HID_31a78] = 3308, + [BNXT_ULP_CLASS_HID_7584c] = 3309, + [BNXT_ULP_CLASS_HID_71430] = 3310, + [BNXT_ULP_CLASS_HID_75e08] = 3311, + [BNXT_ULP_CLASS_HID_71dec] = 3312, + [BNXT_ULP_CLASS_HID_725e8] = 3313, + [BNXT_ULP_CLASS_HID_75d18] = 3314, + [BNXT_ULP_CLASS_HID_72ba4] = 3315, + [BNXT_ULP_CLASS_HID_742d4] = 3316, + [BNXT_ULP_CLASS_HID_70194] = 3317, + [BNXT_ULP_CLASS_HID_73884] = 3318, + [BNXT_ULP_CLASS_HID_70750] = 3319, + [BNXT_ULP_CLASS_HID_73e40] = 3320, + [BNXT_ULP_CLASS_HID_7467c] = 3321, + [BNXT_ULP_CLASS_HID_70220] = 3322, + [BNXT_ULP_CLASS_HID_710ec] = 3323, + [BNXT_ULP_CLASS_HID_7081c] = 3324, + [BNXT_ULP_CLASS_HID_7279c] = 3325, + [BNXT_ULP_CLASS_HID_75e8c] = 3326, + [BNXT_ULP_CLASS_HID_72d58] = 3327, + [BNXT_ULP_CLASS_HID_74448] = 3328, + [BNXT_ULP_CLASS_HID_73138] = 3329, + [BNXT_ULP_CLASS_HID_72828] = 3330, + [BNXT_ULP_CLASS_HID_736f4] = 3331, + [BNXT_ULP_CLASS_HID_751e4] = 3332, + [BNXT_ULP_CLASS_HID_74bf0] = 3333, + [BNXT_ULP_CLASS_HID_707d4] = 3334, + [BNXT_ULP_CLASS_HID_71260] = 3335, + [BNXT_ULP_CLASS_HID_70d90] = 3336, + [BNXT_ULP_CLASS_HID_7558c] = 3337, + [BNXT_ULP_CLASS_HID_71170] = 3338, + [BNXT_ULP_CLASS_HID_75b48] = 3339, + [BNXT_ULP_CLASS_HID_7172c] = 3340, + [BNXT_ULP_CLASS_HID_2d298] = 3341, + [BNXT_ULP_CLASS_HID_2cd88] = 3342, + [BNXT_ULP_CLASS_HID_2d854] = 3343, + [BNXT_ULP_CLASS_HID_29438] = 3344, + [BNXT_ULP_CLASS_HID_2bc34] = 3345, + [BNXT_ULP_CLASS_HID_2d724] = 3346, + [BNXT_ULP_CLASS_HID_2a5f0] = 3347, + [BNXT_ULP_CLASS_HID_2dce0] = 3348, + [BNXT_ULP_CLASS_HID_29ba0] = 3349, + [BNXT_ULP_CLASS_HID_2b2d0] = 3350, + [BNXT_ULP_CLASS_HID_2819c] = 3351, + [BNXT_ULP_CLASS_HID_2b88c] = 3352, + [BNXT_ULP_CLASS_HID_2c088] = 3353, + [BNXT_ULP_CLASS_HID_29c6c] = 3354, + [BNXT_ULP_CLASS_HID_2c644] = 3355, + [BNXT_ULP_CLASS_HID_28228] = 3356, + [BNXT_ULP_CLASS_HID_2a1a8] = 3357, + [BNXT_ULP_CLASS_HID_2d8d8] = 3358, + [BNXT_ULP_CLASS_HID_2a764] = 3359, + [BNXT_ULP_CLASS_HID_2de94] = 3360, + [BNXT_ULP_CLASS_HID_28b44] = 3361, + [BNXT_ULP_CLASS_HID_2a274] = 3362, + [BNXT_ULP_CLASS_HID_2b100] = 3363, + [BNXT_ULP_CLASS_HID_2a830] = 3364, + [BNXT_ULP_CLASS_HID_2c23c] = 3365, + [BNXT_ULP_CLASS_HID_281e0] = 3366, + [BNXT_ULP_CLASS_HID_2cbf8] = 3367, + [BNXT_ULP_CLASS_HID_287dc] = 3368, + [BNXT_ULP_CLASS_HID_2afd8] = 3369, + [BNXT_ULP_CLASS_HID_2c6c8] = 3370, + [BNXT_ULP_CLASS_HID_2d594] = 3371, + [BNXT_ULP_CLASS_HID_29178] = 3372, + [BNXT_ULP_CLASS_HID_6af4c] = 3373, + [BNXT_ULP_CLASS_HID_6c67c] = 3374, + [BNXT_ULP_CLASS_HID_6d508] = 3375, + [BNXT_ULP_CLASS_HID_690ec] = 3376, + [BNXT_ULP_CLASS_HID_6b8e8] = 3377, + [BNXT_ULP_CLASS_HID_6d018] = 3378, + [BNXT_ULP_CLASS_HID_6bea4] = 3379, + [BNXT_ULP_CLASS_HID_6d9d4] = 3380, + [BNXT_ULP_CLASS_HID_69494] = 3381, + [BNXT_ULP_CLASS_HID_68f84] = 3382, + [BNXT_ULP_CLASS_HID_69a50] = 3383, + [BNXT_ULP_CLASS_HID_6b540] = 3384, + [BNXT_ULP_CLASS_HID_6dd7c] = 3385, + [BNXT_ULP_CLASS_HID_69920] = 3386, + [BNXT_ULP_CLASS_HID_6c338] = 3387, + [BNXT_ULP_CLASS_HID_69f1c] = 3388, + [BNXT_ULP_CLASS_HID_6ba9c] = 3389, + [BNXT_ULP_CLASS_HID_6d58c] = 3390, + [BNXT_ULP_CLASS_HID_6a058] = 3391, + [BNXT_ULP_CLASS_HID_6db48] = 3392, + [BNXT_ULP_CLASS_HID_68438] = 3393, + [BNXT_ULP_CLASS_HID_6bf28] = 3394, + [BNXT_ULP_CLASS_HID_68df4] = 3395, + [BNXT_ULP_CLASS_HID_6a4e4] = 3396, + [BNXT_ULP_CLASS_HID_6def0] = 3397, + [BNXT_ULP_CLASS_HID_69ad4] = 3398, + [BNXT_ULP_CLASS_HID_6c4ac] = 3399, + [BNXT_ULP_CLASS_HID_68090] = 3400, + [BNXT_ULP_CLASS_HID_6a88c] = 3401, + [BNXT_ULP_CLASS_HID_6c3bc] = 3402, + [BNXT_ULP_CLASS_HID_6ae48] = 3403, + [BNXT_ULP_CLASS_HID_6c978] = 3404, + [BNXT_ULP_CLASS_HID_3c898] = 3405, + [BNXT_ULP_CLASS_HID_3847c] = 3406, + [BNXT_ULP_CLASS_HID_39308] = 3407, + [BNXT_ULP_CLASS_HID_38a38] = 3408, + [BNXT_ULP_CLASS_HID_3d234] = 3409, + [BNXT_ULP_CLASS_HID_3cd24] = 3410, + [BNXT_ULP_CLASS_HID_3dbf0] = 3411, + [BNXT_ULP_CLASS_HID_397d4] = 3412, + [BNXT_ULP_CLASS_HID_3b1a0] = 3413, + [BNXT_ULP_CLASS_HID_3a8d0] = 3414, + [BNXT_ULP_CLASS_HID_3b79c] = 3415, + [BNXT_ULP_CLASS_HID_3ae8c] = 3416, + [BNXT_ULP_CLASS_HID_39b7c] = 3417, + [BNXT_ULP_CLASS_HID_3b26c] = 3418, + [BNXT_ULP_CLASS_HID_38138] = 3419, + [BNXT_ULP_CLASS_HID_3b828] = 3420, + [BNXT_ULP_CLASS_HID_3d7a8] = 3421, + [BNXT_ULP_CLASS_HID_3938c] = 3422, + [BNXT_ULP_CLASS_HID_3dd64] = 3423, + [BNXT_ULP_CLASS_HID_39948] = 3424, + [BNXT_ULP_CLASS_HID_3a144] = 3425, + [BNXT_ULP_CLASS_HID_3d874] = 3426, + [BNXT_ULP_CLASS_HID_3a700] = 3427, + [BNXT_ULP_CLASS_HID_3de30] = 3428, + [BNXT_ULP_CLASS_HID_39cf0] = 3429, + [BNXT_ULP_CLASS_HID_3b7e0] = 3430, + [BNXT_ULP_CLASS_HID_382ac] = 3431, + [BNXT_ULP_CLASS_HID_3bddc] = 3432, + [BNXT_ULP_CLASS_HID_3c5d8] = 3433, + [BNXT_ULP_CLASS_HID_381bc] = 3434, + [BNXT_ULP_CLASS_HID_3cb94] = 3435, + [BNXT_ULP_CLASS_HID_38778] = 3436, + [BNXT_ULP_CLASS_HID_7c54c] = 3437, + [BNXT_ULP_CLASS_HID_78130] = 3438, + [BNXT_ULP_CLASS_HID_7cb08] = 3439, + [BNXT_ULP_CLASS_HID_786ec] = 3440, + [BNXT_ULP_CLASS_HID_7aee8] = 3441, + [BNXT_ULP_CLASS_HID_7c618] = 3442, + [BNXT_ULP_CLASS_HID_7d4a4] = 3443, + [BNXT_ULP_CLASS_HID_79088] = 3444, + [BNXT_ULP_CLASS_HID_78a94] = 3445, + [BNXT_ULP_CLASS_HID_7a584] = 3446, + [BNXT_ULP_CLASS_HID_7b050] = 3447, + [BNXT_ULP_CLASS_HID_7ab40] = 3448, + [BNXT_ULP_CLASS_HID_79430] = 3449, + [BNXT_ULP_CLASS_HID_78f20] = 3450, + [BNXT_ULP_CLASS_HID_79dec] = 3451, + [BNXT_ULP_CLASS_HID_7b51c] = 3452, + [BNXT_ULP_CLASS_HID_7d09c] = 3453, + [BNXT_ULP_CLASS_HID_7cb8c] = 3454, + [BNXT_ULP_CLASS_HID_7d658] = 3455, + [BNXT_ULP_CLASS_HID_7923c] = 3456, + [BNXT_ULP_CLASS_HID_7ba38] = 3457, + [BNXT_ULP_CLASS_HID_7d528] = 3458, + [BNXT_ULP_CLASS_HID_7a3f4] = 3459, + [BNXT_ULP_CLASS_HID_7dae4] = 3460, + [BNXT_ULP_CLASS_HID_799a4] = 3461, + [BNXT_ULP_CLASS_HID_7b0d4] = 3462, + [BNXT_ULP_CLASS_HID_79f60] = 3463, + [BNXT_ULP_CLASS_HID_7b690] = 3464, + [BNXT_ULP_CLASS_HID_7de8c] = 3465, + [BNXT_ULP_CLASS_HID_79a70] = 3466, + [BNXT_ULP_CLASS_HID_7c448] = 3467, + [BNXT_ULP_CLASS_HID_7802c] = 3468, + [BNXT_ULP_CLASS_HID_86a0] = 3469, + [BNXT_ULP_CLASS_HID_a1b0] = 3470, + [BNXT_ULP_CLASS_HID_8c6c] = 3471, + [BNXT_ULP_CLASS_HID_a77c] = 3472, + [BNXT_ULP_CLASS_HID_900c] = 3473, + [BNXT_ULP_CLASS_HID_8b1c] = 3474, + [BNXT_ULP_CLASS_HID_99c8] = 3475, + [BNXT_ULP_CLASS_HID_b0d8] = 3476, + [BNXT_ULP_CLASS_HID_aad4] = 3477, + [BNXT_ULP_CLASS_HID_c224] = 3478, + [BNXT_ULP_CLASS_HID_d090] = 3479, + [BNXT_ULP_CLASS_HID_cbe0] = 3480, + [BNXT_ULP_CLASS_HID_b4b0] = 3481, + [BNXT_ULP_CLASS_HID_af80] = 3482, + [BNXT_ULP_CLASS_HID_ba7c] = 3483, + [BNXT_ULP_CLASS_HID_d54c] = 3484, + [BNXT_ULP_CLASS_HID_48374] = 3485, + [BNXT_ULP_CLASS_HID_4ba44] = 3486, + [BNXT_ULP_CLASS_HID_48930] = 3487, + [BNXT_ULP_CLASS_HID_4a000] = 3488, + [BNXT_ULP_CLASS_HID_4c80c] = 3489, + [BNXT_ULP_CLASS_HID_48420] = 3490, + [BNXT_ULP_CLASS_HID_4929c] = 3491, + [BNXT_ULP_CLASS_HID_48dec] = 3492, + [BNXT_ULP_CLASS_HID_4a798] = 3493, + [BNXT_ULP_CLASS_HID_4dee8] = 3494, + [BNXT_ULP_CLASS_HID_4ada4] = 3495, + [BNXT_ULP_CLASS_HID_4c4b4] = 3496, + [BNXT_ULP_CLASS_HID_4b144] = 3497, + [BNXT_ULP_CLASS_HID_4a854] = 3498, + [BNXT_ULP_CLASS_HID_4b700] = 3499, + [BNXT_ULP_CLASS_HID_4ae10] = 3500, + [BNXT_ULP_CLASS_HID_1bca0] = 3501, + [BNXT_ULP_CLASS_HID_1d7b0] = 3502, + [BNXT_ULP_CLASS_HID_1a26c] = 3503, + [BNXT_ULP_CLASS_HID_1dd7c] = 3504, + [BNXT_ULP_CLASS_HID_1860c] = 3505, + [BNXT_ULP_CLASS_HID_1a11c] = 3506, + [BNXT_ULP_CLASS_HID_18fc8] = 3507, + [BNXT_ULP_CLASS_HID_1a6d8] = 3508, + [BNXT_ULP_CLASS_HID_1c0d4] = 3509, + [BNXT_ULP_CLASS_HID_19ce8] = 3510, + [BNXT_ULP_CLASS_HID_1c690] = 3511, + [BNXT_ULP_CLASS_HID_182b4] = 3512, + [BNXT_ULP_CLASS_HID_1aab0] = 3513, + [BNXT_ULP_CLASS_HID_1c580] = 3514, + [BNXT_ULP_CLASS_HID_1d07c] = 3515, + [BNXT_ULP_CLASS_HID_1cb4c] = 3516, + [BNXT_ULP_CLASS_HID_5b974] = 3517, + [BNXT_ULP_CLASS_HID_5d044] = 3518, + [BNXT_ULP_CLASS_HID_5bf30] = 3519, + [BNXT_ULP_CLASS_HID_5d600] = 3520, + [BNXT_ULP_CLASS_HID_582d0] = 3521, + [BNXT_ULP_CLASS_HID_5ba20] = 3522, + [BNXT_ULP_CLASS_HID_5889c] = 3523, + [BNXT_ULP_CLASS_HID_5a3ec] = 3524, + [BNXT_ULP_CLASS_HID_5dd98] = 3525, + [BNXT_ULP_CLASS_HID_599bc] = 3526, + [BNXT_ULP_CLASS_HID_5c3a4] = 3527, + [BNXT_ULP_CLASS_HID_59f78] = 3528, + [BNXT_ULP_CLASS_HID_5a744] = 3529, + [BNXT_ULP_CLASS_HID_5de54] = 3530, + [BNXT_ULP_CLASS_HID_5ad00] = 3531, + [BNXT_ULP_CLASS_HID_5c410] = 3532, + [BNXT_ULP_CLASS_HID_cd20] = 3533, + [BNXT_ULP_CLASS_HID_e430] = 3534, + [BNXT_ULP_CLASS_HID_f2ec] = 3535, + [BNXT_ULP_CLASS_HID_edfc] = 3536, + [BNXT_ULP_CLASS_HID_d68c] = 3537, + [BNXT_ULP_CLASS_HID_f19c] = 3538, + [BNXT_ULP_CLASS_HID_dc48] = 3539, + [BNXT_ULP_CLASS_HID_f758] = 3540, + [BNXT_ULP_CLASS_HID_d154] = 3541, + [BNXT_ULP_CLASS_HID_c8a4] = 3542, + [BNXT_ULP_CLASS_HID_d710] = 3543, + [BNXT_ULP_CLASS_HID_d334] = 3544, + [BNXT_ULP_CLASS_HID_fb30] = 3545, + [BNXT_ULP_CLASS_HID_d200] = 3546, + [BNXT_ULP_CLASS_HID_e0fc] = 3547, + [BNXT_ULP_CLASS_HID_dbcc] = 3548, + [BNXT_ULP_CLASS_HID_4c9f4] = 3549, + [BNXT_ULP_CLASS_HID_4e0c4] = 3550, + [BNXT_ULP_CLASS_HID_4cfb0] = 3551, + [BNXT_ULP_CLASS_HID_4e680] = 3552, + [BNXT_ULP_CLASS_HID_4d350] = 3553, + [BNXT_ULP_CLASS_HID_4caa0] = 3554, + [BNXT_ULP_CLASS_HID_4d91c] = 3555, + [BNXT_ULP_CLASS_HID_4f06c] = 3556, + [BNXT_ULP_CLASS_HID_4ea18] = 3557, + [BNXT_ULP_CLASS_HID_4c568] = 3558, + [BNXT_ULP_CLASS_HID_4d024] = 3559, + [BNXT_ULP_CLASS_HID_4cb34] = 3560, + [BNXT_ULP_CLASS_HID_4f7c4] = 3561, + [BNXT_ULP_CLASS_HID_4eed4] = 3562, + [BNXT_ULP_CLASS_HID_4fd80] = 3563, + [BNXT_ULP_CLASS_HID_4d490] = 3564, + [BNXT_ULP_CLASS_HID_1e320] = 3565, + [BNXT_ULP_CLASS_HID_1da30] = 3566, + [BNXT_ULP_CLASS_HID_1e8ec] = 3567, + [BNXT_ULP_CLASS_HID_1c3fc] = 3568, + [BNXT_ULP_CLASS_HID_1cc8c] = 3569, + [BNXT_ULP_CLASS_HID_1e79c] = 3570, + [BNXT_ULP_CLASS_HID_1f248] = 3571, + [BNXT_ULP_CLASS_HID_1ed58] = 3572, + [BNXT_ULP_CLASS_HID_1c754] = 3573, + [BNXT_ULP_CLASS_HID_1c368] = 3574, + [BNXT_ULP_CLASS_HID_1cd10] = 3575, + [BNXT_ULP_CLASS_HID_1c934] = 3576, + [BNXT_ULP_CLASS_HID_1d130] = 3577, + [BNXT_ULP_CLASS_HID_1c800] = 3578, + [BNXT_ULP_CLASS_HID_1d6fc] = 3579, + [BNXT_ULP_CLASS_HID_1d290] = 3580, + [BNXT_ULP_CLASS_HID_5fff4] = 3581, + [BNXT_ULP_CLASS_HID_5d6c4] = 3582, + [BNXT_ULP_CLASS_HID_5e5b0] = 3583, + [BNXT_ULP_CLASS_HID_5dc80] = 3584, + [BNXT_ULP_CLASS_HID_5c950] = 3585, + [BNXT_ULP_CLASS_HID_5e0a0] = 3586, + [BNXT_ULP_CLASS_HID_5cf1c] = 3587, + [BNXT_ULP_CLASS_HID_5e66c] = 3588, + [BNXT_ULP_CLASS_HID_5c018] = 3589, + [BNXT_ULP_CLASS_HID_5dc3c] = 3590, + [BNXT_ULP_CLASS_HID_5c624] = 3591, + [BNXT_ULP_CLASS_HID_5c5f8] = 3592, + [BNXT_ULP_CLASS_HID_5edc4] = 3593, + [BNXT_ULP_CLASS_HID_5c4d4] = 3594, + [BNXT_ULP_CLASS_HID_5d380] = 3595, + [BNXT_ULP_CLASS_HID_5ca90] = 3596, + [BNXT_ULP_CLASS_HID_abe0] = 3597, + [BNXT_ULP_CLASS_HID_a2f0] = 3598, + [BNXT_ULP_CLASS_HID_b1ac] = 3599, + [BNXT_ULP_CLASS_HID_a8bc] = 3600, + [BNXT_ULP_CLASS_HID_b54c] = 3601, + [BNXT_ULP_CLASS_HID_ac5c] = 3602, + [BNXT_ULP_CLASS_HID_bb08] = 3603, + [BNXT_ULP_CLASS_HID_b218] = 3604, + [BNXT_ULP_CLASS_HID_ac14] = 3605, + [BNXT_ULP_CLASS_HID_e764] = 3606, + [BNXT_ULP_CLASS_HID_f5d0] = 3607, + [BNXT_ULP_CLASS_HID_b1f4] = 3608, + [BNXT_ULP_CLASS_HID_b9f0] = 3609, + [BNXT_ULP_CLASS_HID_f0c0] = 3610, + [BNXT_ULP_CLASS_HID_bfbc] = 3611, + [BNXT_ULP_CLASS_HID_f68c] = 3612, + [BNXT_ULP_CLASS_HID_4a4b4] = 3613, + [BNXT_ULP_CLASS_HID_4bf84] = 3614, + [BNXT_ULP_CLASS_HID_4aa70] = 3615, + [BNXT_ULP_CLASS_HID_4a540] = 3616, + [BNXT_ULP_CLASS_HID_4ed4c] = 3617, + [BNXT_ULP_CLASS_HID_4a960] = 3618, + [BNXT_ULP_CLASS_HID_4b7dc] = 3619, + [BNXT_ULP_CLASS_HID_4af2c] = 3620, + [BNXT_ULP_CLASS_HID_4a8d8] = 3621, + [BNXT_ULP_CLASS_HID_4e028] = 3622, + [BNXT_ULP_CLASS_HID_4aee4] = 3623, + [BNXT_ULP_CLASS_HID_4e9f4] = 3624, + [BNXT_ULP_CLASS_HID_4b284] = 3625, + [BNXT_ULP_CLASS_HID_4ad94] = 3626, + [BNXT_ULP_CLASS_HID_4b840] = 3627, + [BNXT_ULP_CLASS_HID_4f350] = 3628, + [BNXT_ULP_CLASS_HID_1a1e0] = 3629, + [BNXT_ULP_CLASS_HID_1f8f0] = 3630, + [BNXT_ULP_CLASS_HID_1a7ac] = 3631, + [BNXT_ULP_CLASS_HID_1febc] = 3632, + [BNXT_ULP_CLASS_HID_1ab4c] = 3633, + [BNXT_ULP_CLASS_HID_1a25c] = 3634, + [BNXT_ULP_CLASS_HID_1b108] = 3635, + [BNXT_ULP_CLASS_HID_1a818] = 3636, + [BNXT_ULP_CLASS_HID_1e214] = 3637, + [BNXT_ULP_CLASS_HID_1be28] = 3638, + [BNXT_ULP_CLASS_HID_1ebd0] = 3639, + [BNXT_ULP_CLASS_HID_1a7f4] = 3640, + [BNXT_ULP_CLASS_HID_1aff0] = 3641, + [BNXT_ULP_CLASS_HID_1e6c0] = 3642, + [BNXT_ULP_CLASS_HID_1f5bc] = 3643, + [BNXT_ULP_CLASS_HID_1b150] = 3644, + [BNXT_ULP_CLASS_HID_5bab4] = 3645, + [BNXT_ULP_CLASS_HID_5f584] = 3646, + [BNXT_ULP_CLASS_HID_5a070] = 3647, + [BNXT_ULP_CLASS_HID_5fb40] = 3648, + [BNXT_ULP_CLASS_HID_5a410] = 3649, + [BNXT_ULP_CLASS_HID_5bf60] = 3650, + [BNXT_ULP_CLASS_HID_5addc] = 3651, + [BNXT_ULP_CLASS_HID_5a52c] = 3652, + [BNXT_ULP_CLASS_HID_5fed8] = 3653, + [BNXT_ULP_CLASS_HID_5bafc] = 3654, + [BNXT_ULP_CLASS_HID_5e4e4] = 3655, + [BNXT_ULP_CLASS_HID_5a0b8] = 3656, + [BNXT_ULP_CLASS_HID_5a884] = 3657, + [BNXT_ULP_CLASS_HID_5e394] = 3658, + [BNXT_ULP_CLASS_HID_5ae40] = 3659, + [BNXT_ULP_CLASS_HID_5e950] = 3660, + [BNXT_ULP_CLASS_HID_ee60] = 3661, + [BNXT_ULP_CLASS_HID_e970] = 3662, + [BNXT_ULP_CLASS_HID_f42c] = 3663, + [BNXT_ULP_CLASS_HID_ef3c] = 3664, + [BNXT_ULP_CLASS_HID_fbcc] = 3665, + [BNXT_ULP_CLASS_HID_f2dc] = 3666, + [BNXT_ULP_CLASS_HID_e188] = 3667, + [BNXT_ULP_CLASS_HID_f898] = 3668, + [BNXT_ULP_CLASS_HID_f294] = 3669, + [BNXT_ULP_CLASS_HID_ede4] = 3670, + [BNXT_ULP_CLASS_HID_f850] = 3671, + [BNXT_ULP_CLASS_HID_f474] = 3672, + [BNXT_ULP_CLASS_HID_fc70] = 3673, + [BNXT_ULP_CLASS_HID_f740] = 3674, + [BNXT_ULP_CLASS_HID_e23c] = 3675, + [BNXT_ULP_CLASS_HID_fd0c] = 3676, + [BNXT_ULP_CLASS_HID_4eb34] = 3677, + [BNXT_ULP_CLASS_HID_4e204] = 3678, + [BNXT_ULP_CLASS_HID_4f0f0] = 3679, + [BNXT_ULP_CLASS_HID_4ebc0] = 3680, + [BNXT_ULP_CLASS_HID_4f490] = 3681, + [BNXT_ULP_CLASS_HID_4efe0] = 3682, + [BNXT_ULP_CLASS_HID_4fa5c] = 3683, + [BNXT_ULP_CLASS_HID_4f5ac] = 3684, + [BNXT_ULP_CLASS_HID_4ef58] = 3685, + [BNXT_ULP_CLASS_HID_4e6a8] = 3686, + [BNXT_ULP_CLASS_HID_4f564] = 3687, + [BNXT_ULP_CLASS_HID_4f138] = 3688, + [BNXT_ULP_CLASS_HID_4f904] = 3689, + [BNXT_ULP_CLASS_HID_4f014] = 3690, + [BNXT_ULP_CLASS_HID_4fec0] = 3691, + [BNXT_ULP_CLASS_HID_4f9d0] = 3692, + [BNXT_ULP_CLASS_HID_1e460] = 3693, + [BNXT_ULP_CLASS_HID_1ff70] = 3694, + [BNXT_ULP_CLASS_HID_1ea2c] = 3695, + [BNXT_ULP_CLASS_HID_1e53c] = 3696, + [BNXT_ULP_CLASS_HID_1f1cc] = 3697, + [BNXT_ULP_CLASS_HID_1e8dc] = 3698, + [BNXT_ULP_CLASS_HID_1f788] = 3699, + [BNXT_ULP_CLASS_HID_1ee98] = 3700, + [BNXT_ULP_CLASS_HID_1e894] = 3701, + [BNXT_ULP_CLASS_HID_1e4a8] = 3702, + [BNXT_ULP_CLASS_HID_1f364] = 3703, + [BNXT_ULP_CLASS_HID_1ea74] = 3704, + [BNXT_ULP_CLASS_HID_1f270] = 3705, + [BNXT_ULP_CLASS_HID_1ed40] = 3706, + [BNXT_ULP_CLASS_HID_1f83c] = 3707, + [BNXT_ULP_CLASS_HID_1f7d0] = 3708, + [BNXT_ULP_CLASS_HID_5e134] = 3709, + [BNXT_ULP_CLASS_HID_5f804] = 3710, + [BNXT_ULP_CLASS_HID_5e6f0] = 3711, + [BNXT_ULP_CLASS_HID_5e1c0] = 3712, + [BNXT_ULP_CLASS_HID_5ea90] = 3713, + [BNXT_ULP_CLASS_HID_5e5e0] = 3714, + [BNXT_ULP_CLASS_HID_5f05c] = 3715, + [BNXT_ULP_CLASS_HID_5ebac] = 3716, + [BNXT_ULP_CLASS_HID_5e558] = 3717, + [BNXT_ULP_CLASS_HID_5e17c] = 3718, + [BNXT_ULP_CLASS_HID_5eb64] = 3719, + [BNXT_ULP_CLASS_HID_5e738] = 3720, + [BNXT_ULP_CLASS_HID_5ef04] = 3721, + [BNXT_ULP_CLASS_HID_5e614] = 3722, + [BNXT_ULP_CLASS_HID_5f4c0] = 3723, + [BNXT_ULP_CLASS_HID_5f0e4] = 3724, + [BNXT_ULP_CLASS_HID_5802] = 3725, + [BNXT_ULP_CLASS_HID_5e46] = 3726, + [BNXT_ULP_CLASS_HID_1d76] = 3727, + [BNXT_ULP_CLASS_HID_02ba] = 3728, + [BNXT_ULP_CLASS_HID_32a2] = 3729, + [BNXT_ULP_CLASS_HID_38e6] = 3730, + [BNXT_ULP_CLASS_HID_52ca] = 3731, + [BNXT_ULP_CLASS_HID_580e] = 3732, + [BNXT_ULP_CLASS_HID_44996] = 3733, + [BNXT_ULP_CLASS_HID_410e6] = 3734, + [BNXT_ULP_CLASS_HID_42036] = 3735, + [BNXT_ULP_CLASS_HID_4264a] = 3736, + [BNXT_ULP_CLASS_HID_45ffe] = 3737, + [BNXT_ULP_CLASS_HID_44532] = 3738, + [BNXT_ULP_CLASS_HID_4399e] = 3739, + [BNXT_ULP_CLASS_HID_43fd2] = 3740, + [BNXT_ULP_CLASS_HID_23da0] = 3741, + [BNXT_ULP_CLASS_HID_2239c] = 3742, + [BNXT_ULP_CLASS_HID_207fc] = 3743, + [BNXT_ULP_CLASS_HID_20d38] = 3744, + [BNXT_ULP_CLASS_HID_25e34] = 3745, + [BNXT_ULP_CLASS_HID_24470] = 3746, + [BNXT_ULP_CLASS_HID_22850] = 3747, + [BNXT_ULP_CLASS_HID_2518c] = 3748, + [BNXT_ULP_CLASS_HID_20970] = 3749, + [BNXT_ULP_CLASS_HID_20eac] = 3750, + [BNXT_ULP_CLASS_HID_2128c] = 3751, + [BNXT_ULP_CLASS_HID_218c8] = 3752, + [BNXT_ULP_CLASS_HID_22dc4] = 3753, + [BNXT_ULP_CLASS_HID_25300] = 3754, + [BNXT_ULP_CLASS_HID_23760] = 3755, + [BNXT_ULP_CLASS_HID_23d5c] = 3756, + [BNXT_ULP_CLASS_HID_63694] = 3757, + [BNXT_ULP_CLASS_HID_63cd0] = 3758, + [BNXT_ULP_CLASS_HID_60030] = 3759, + [BNXT_ULP_CLASS_HID_6066c] = 3760, + [BNXT_ULP_CLASS_HID_65b68] = 3761, + [BNXT_ULP_CLASS_HID_640a4] = 3762, + [BNXT_ULP_CLASS_HID_62484] = 3763, + [BNXT_ULP_CLASS_HID_62ac0] = 3764, + [BNXT_ULP_CLASS_HID_605a4] = 3765, + [BNXT_ULP_CLASS_HID_60be0] = 3766, + [BNXT_ULP_CLASS_HID_64a8c] = 3767, + [BNXT_ULP_CLASS_HID_6153c] = 3768, + [BNXT_ULP_CLASS_HID_62638] = 3769, + [BNXT_ULP_CLASS_HID_62c74] = 3770, + [BNXT_ULP_CLASS_HID_63054] = 3771, + [BNXT_ULP_CLASS_HID_63990] = 3772, + [BNXT_ULP_CLASS_HID_9a98] = 3773, + [BNXT_ULP_CLASS_HID_80a4] = 3774, + [BNXT_ULP_CLASS_HID_c3b0] = 3775, + [BNXT_ULP_CLASS_HID_c9fc] = 3776, + [BNXT_ULP_CLASS_HID_bf0c] = 3777, + [BNXT_ULP_CLASS_HID_a548] = 3778, + [BNXT_ULP_CLASS_HID_8968] = 3779, + [BNXT_ULP_CLASS_HID_8eb4] = 3780, + [BNXT_ULP_CLASS_HID_497ac] = 3781, + [BNXT_ULP_CLASS_HID_49de8] = 3782, + [BNXT_ULP_CLASS_HID_4dcc4] = 3783, + [BNXT_ULP_CLASS_HID_4c200] = 3784, + [BNXT_ULP_CLASS_HID_4b850] = 3785, + [BNXT_ULP_CLASS_HID_4a19c] = 3786, + [BNXT_ULP_CLASS_HID_485bc] = 3787, + [BNXT_ULP_CLASS_HID_48bf8] = 3788, + [BNXT_ULP_CLASS_HID_1b098] = 3789, + [BNXT_ULP_CLASS_HID_1b6a4] = 3790, + [BNXT_ULP_CLASS_HID_19ac4] = 3791, + [BNXT_ULP_CLASS_HID_18000] = 3792, + [BNXT_ULP_CLASS_HID_1d50c] = 3793, + [BNXT_ULP_CLASS_HID_1db48] = 3794, + [BNXT_ULP_CLASS_HID_1bf68] = 3795, + [BNXT_ULP_CLASS_HID_1a4b4] = 3796, + [BNXT_ULP_CLASS_HID_58dac] = 3797, + [BNXT_ULP_CLASS_HID_5b3e8] = 3798, + [BNXT_ULP_CLASS_HID_59708] = 3799, + [BNXT_ULP_CLASS_HID_59d54] = 3800, + [BNXT_ULP_CLASS_HID_5ae50] = 3801, + [BNXT_ULP_CLASS_HID_5d79c] = 3802, + [BNXT_ULP_CLASS_HID_5bbbc] = 3803, + [BNXT_ULP_CLASS_HID_5a1f8] = 3804, + [BNXT_ULP_CLASS_HID_5822] = 3805, + [BNXT_ULP_CLASS_HID_5e66] = 3806, + [BNXT_ULP_CLASS_HID_1d56] = 3807, + [BNXT_ULP_CLASS_HID_029a] = 3808, + [BNXT_ULP_CLASS_HID_3282] = 3809, + [BNXT_ULP_CLASS_HID_38c6] = 3810, + [BNXT_ULP_CLASS_HID_52ea] = 3811, + [BNXT_ULP_CLASS_HID_582e] = 3812, + [BNXT_ULP_CLASS_HID_51ba] = 3813, + [BNXT_ULP_CLASS_HID_57fe] = 3814, + [BNXT_ULP_CLASS_HID_12ee] = 3815, + [BNXT_ULP_CLASS_HID_1832] = 3816, + [BNXT_ULP_CLASS_HID_081a] = 3817, + [BNXT_ULP_CLASS_HID_0e5e] = 3818, + [BNXT_ULP_CLASS_HID_2802] = 3819, + [BNXT_ULP_CLASS_HID_2e46] = 3820, + [BNXT_ULP_CLASS_HID_4556e] = 3821, + [BNXT_ULP_CLASS_HID_45ab2] = 3822, + [BNXT_ULP_CLASS_HID_419a2] = 3823, + [BNXT_ULP_CLASS_HID_41fe6] = 3824, + [BNXT_ULP_CLASS_HID_40fce] = 3825, + [BNXT_ULP_CLASS_HID_43512] = 3826, + [BNXT_ULP_CLASS_HID_42f36] = 3827, + [BNXT_ULP_CLASS_HID_4557a] = 3828, + [BNXT_ULP_CLASS_HID_42a86] = 3829, + [BNXT_ULP_CLASS_HID_450ca] = 3830, + [BNXT_ULP_CLASS_HID_44aee] = 3831, + [BNXT_ULP_CLASS_HID_4157e] = 3832, + [BNXT_ULP_CLASS_HID_40566] = 3833, + [BNXT_ULP_CLASS_HID_40aaa] = 3834, + [BNXT_ULP_CLASS_HID_4254e] = 3835, + [BNXT_ULP_CLASS_HID_42a92] = 3836, + [BNXT_ULP_CLASS_HID_449b6] = 3837, + [BNXT_ULP_CLASS_HID_410c6] = 3838, + [BNXT_ULP_CLASS_HID_42016] = 3839, + [BNXT_ULP_CLASS_HID_4266a] = 3840, + [BNXT_ULP_CLASS_HID_45fde] = 3841, + [BNXT_ULP_CLASS_HID_44512] = 3842, + [BNXT_ULP_CLASS_HID_439be] = 3843, + [BNXT_ULP_CLASS_HID_43ff2] = 3844, + [BNXT_ULP_CLASS_HID_63682] = 3845, + [BNXT_ULP_CLASS_HID_63cc6] = 3846, + [BNXT_ULP_CLASS_HID_61162] = 3847, + [BNXT_ULP_CLASS_HID_616a6] = 3848, + [BNXT_ULP_CLASS_HID_60c2a] = 3849, + [BNXT_ULP_CLASS_HID_6326e] = 3850, + [BNXT_ULP_CLASS_HID_645be] = 3851, + [BNXT_ULP_CLASS_HID_64bf2] = 3852, + [BNXT_ULP_CLASS_HID_50082] = 3853, + [BNXT_ULP_CLASS_HID_506c6] = 3854, + [BNXT_ULP_CLASS_HID_55616] = 3855, + [BNXT_ULP_CLASS_HID_55c6a] = 3856, + [BNXT_ULP_CLASS_HID_5162a] = 3857, + [BNXT_ULP_CLASS_HID_51c6e] = 3858, + [BNXT_ULP_CLASS_HID_52fbe] = 3859, + [BNXT_ULP_CLASS_HID_555f2] = 3860, + [BNXT_ULP_CLASS_HID_72c82] = 3861, + [BNXT_ULP_CLASS_HID_752c6] = 3862, + [BNXT_ULP_CLASS_HID_70762] = 3863, + [BNXT_ULP_CLASS_HID_70ca6] = 3864, + [BNXT_ULP_CLASS_HID_7222a] = 3865, + [BNXT_ULP_CLASS_HID_7286e] = 3866, + [BNXT_ULP_CLASS_HID_71c8a] = 3867, + [BNXT_ULP_CLASS_HID_702ce] = 3868, + [BNXT_ULP_CLASS_HID_5842] = 3869, + [BNXT_ULP_CLASS_HID_5e06] = 3870, + [BNXT_ULP_CLASS_HID_1d36] = 3871, + [BNXT_ULP_CLASS_HID_02fa] = 3872, + [BNXT_ULP_CLASS_HID_32e2] = 3873, + [BNXT_ULP_CLASS_HID_38a6] = 3874, + [BNXT_ULP_CLASS_HID_528a] = 3875, + [BNXT_ULP_CLASS_HID_584e] = 3876, + [BNXT_ULP_CLASS_HID_51da] = 3877, + [BNXT_ULP_CLASS_HID_579e] = 3878, + [BNXT_ULP_CLASS_HID_128e] = 3879, + [BNXT_ULP_CLASS_HID_1852] = 3880, + [BNXT_ULP_CLASS_HID_087a] = 3881, + [BNXT_ULP_CLASS_HID_0e3e] = 3882, + [BNXT_ULP_CLASS_HID_2862] = 3883, + [BNXT_ULP_CLASS_HID_2e26] = 3884, + [BNXT_ULP_CLASS_HID_4550e] = 3885, + [BNXT_ULP_CLASS_HID_45ad2] = 3886, + [BNXT_ULP_CLASS_HID_419c2] = 3887, + [BNXT_ULP_CLASS_HID_41f86] = 3888, + [BNXT_ULP_CLASS_HID_40fae] = 3889, + [BNXT_ULP_CLASS_HID_43572] = 3890, + [BNXT_ULP_CLASS_HID_42f56] = 3891, + [BNXT_ULP_CLASS_HID_4551a] = 3892, + [BNXT_ULP_CLASS_HID_42ae6] = 3893, + [BNXT_ULP_CLASS_HID_450aa] = 3894, + [BNXT_ULP_CLASS_HID_44a8e] = 3895, + [BNXT_ULP_CLASS_HID_4151e] = 3896, + [BNXT_ULP_CLASS_HID_40506] = 3897, + [BNXT_ULP_CLASS_HID_40aca] = 3898, + [BNXT_ULP_CLASS_HID_4252e] = 3899, + [BNXT_ULP_CLASS_HID_42af2] = 3900, + [BNXT_ULP_CLASS_HID_449d6] = 3901, + [BNXT_ULP_CLASS_HID_410a6] = 3902, + [BNXT_ULP_CLASS_HID_42076] = 3903, + [BNXT_ULP_CLASS_HID_4260a] = 3904, + [BNXT_ULP_CLASS_HID_45fbe] = 3905, + [BNXT_ULP_CLASS_HID_44572] = 3906, + [BNXT_ULP_CLASS_HID_439de] = 3907, + [BNXT_ULP_CLASS_HID_43f92] = 3908, + [BNXT_ULP_CLASS_HID_636e2] = 3909, + [BNXT_ULP_CLASS_HID_63ca6] = 3910, + [BNXT_ULP_CLASS_HID_61102] = 3911, + [BNXT_ULP_CLASS_HID_616c6] = 3912, + [BNXT_ULP_CLASS_HID_60c4a] = 3913, + [BNXT_ULP_CLASS_HID_6320e] = 3914, + [BNXT_ULP_CLASS_HID_645de] = 3915, + [BNXT_ULP_CLASS_HID_64b92] = 3916, + [BNXT_ULP_CLASS_HID_500e2] = 3917, + [BNXT_ULP_CLASS_HID_506a6] = 3918, + [BNXT_ULP_CLASS_HID_55676] = 3919, + [BNXT_ULP_CLASS_HID_55c0a] = 3920, + [BNXT_ULP_CLASS_HID_5164a] = 3921, + [BNXT_ULP_CLASS_HID_51c0e] = 3922, + [BNXT_ULP_CLASS_HID_52fde] = 3923, + [BNXT_ULP_CLASS_HID_55592] = 3924, + [BNXT_ULP_CLASS_HID_72ce2] = 3925, + [BNXT_ULP_CLASS_HID_752a6] = 3926, + [BNXT_ULP_CLASS_HID_70702] = 3927, + [BNXT_ULP_CLASS_HID_70cc6] = 3928, + [BNXT_ULP_CLASS_HID_7224a] = 3929, + [BNXT_ULP_CLASS_HID_7280e] = 3930, + [BNXT_ULP_CLASS_HID_71cea] = 3931, + [BNXT_ULP_CLASS_HID_702ae] = 3932, + [BNXT_ULP_CLASS_HID_23dc0] = 3933, + [BNXT_ULP_CLASS_HID_223fc] = 3934, + [BNXT_ULP_CLASS_HID_2079c] = 3935, + [BNXT_ULP_CLASS_HID_20d58] = 3936, + [BNXT_ULP_CLASS_HID_25e54] = 3937, + [BNXT_ULP_CLASS_HID_24410] = 3938, + [BNXT_ULP_CLASS_HID_22830] = 3939, + [BNXT_ULP_CLASS_HID_251ec] = 3940, + [BNXT_ULP_CLASS_HID_20910] = 3941, + [BNXT_ULP_CLASS_HID_20ecc] = 3942, + [BNXT_ULP_CLASS_HID_212ec] = 3943, + [BNXT_ULP_CLASS_HID_218a8] = 3944, + [BNXT_ULP_CLASS_HID_22da4] = 3945, + [BNXT_ULP_CLASS_HID_25360] = 3946, + [BNXT_ULP_CLASS_HID_23700] = 3947, + [BNXT_ULP_CLASS_HID_23d3c] = 3948, + [BNXT_ULP_CLASS_HID_636f4] = 3949, + [BNXT_ULP_CLASS_HID_63cb0] = 3950, + [BNXT_ULP_CLASS_HID_60050] = 3951, + [BNXT_ULP_CLASS_HID_6060c] = 3952, + [BNXT_ULP_CLASS_HID_65b08] = 3953, + [BNXT_ULP_CLASS_HID_640c4] = 3954, + [BNXT_ULP_CLASS_HID_624e4] = 3955, + [BNXT_ULP_CLASS_HID_62aa0] = 3956, + [BNXT_ULP_CLASS_HID_605c4] = 3957, + [BNXT_ULP_CLASS_HID_60b80] = 3958, + [BNXT_ULP_CLASS_HID_64aec] = 3959, + [BNXT_ULP_CLASS_HID_6155c] = 3960, + [BNXT_ULP_CLASS_HID_62658] = 3961, + [BNXT_ULP_CLASS_HID_62c14] = 3962, + [BNXT_ULP_CLASS_HID_63034] = 3963, + [BNXT_ULP_CLASS_HID_639f0] = 3964, + [BNXT_ULP_CLASS_HID_353c0] = 3965, + [BNXT_ULP_CLASS_HID_359fc] = 3966, + [BNXT_ULP_CLASS_HID_33d9c] = 3967, + [BNXT_ULP_CLASS_HID_32358] = 3968, + [BNXT_ULP_CLASS_HID_31908] = 3969, + [BNXT_ULP_CLASS_HID_31ec4] = 3970, + [BNXT_ULP_CLASS_HID_35e30] = 3971, + [BNXT_ULP_CLASS_HID_347ec] = 3972, + [BNXT_ULP_CLASS_HID_33f10] = 3973, + [BNXT_ULP_CLASS_HID_324cc] = 3974, + [BNXT_ULP_CLASS_HID_308ec] = 3975, + [BNXT_ULP_CLASS_HID_30ea8] = 3976, + [BNXT_ULP_CLASS_HID_343a4] = 3977, + [BNXT_ULP_CLASS_HID_34960] = 3978, + [BNXT_ULP_CLASS_HID_32d00] = 3979, + [BNXT_ULP_CLASS_HID_3533c] = 3980, + [BNXT_ULP_CLASS_HID_72cf4] = 3981, + [BNXT_ULP_CLASS_HID_752b0] = 3982, + [BNXT_ULP_CLASS_HID_73650] = 3983, + [BNXT_ULP_CLASS_HID_73c0c] = 3984, + [BNXT_ULP_CLASS_HID_7123c] = 3985, + [BNXT_ULP_CLASS_HID_71bf8] = 3986, + [BNXT_ULP_CLASS_HID_75ae4] = 3987, + [BNXT_ULP_CLASS_HID_740a0] = 3988, + [BNXT_ULP_CLASS_HID_73bc4] = 3989, + [BNXT_ULP_CLASS_HID_72180] = 3990, + [BNXT_ULP_CLASS_HID_705a0] = 3991, + [BNXT_ULP_CLASS_HID_70b5c] = 3992, + [BNXT_ULP_CLASS_HID_75c58] = 3993, + [BNXT_ULP_CLASS_HID_74214] = 3994, + [BNXT_ULP_CLASS_HID_72634] = 3995, + [BNXT_ULP_CLASS_HID_72ff0] = 3996, + [BNXT_ULP_CLASS_HID_2a6c0] = 3997, + [BNXT_ULP_CLASS_HID_2acfc] = 3998, + [BNXT_ULP_CLASS_HID_2b09c] = 3999, + [BNXT_ULP_CLASS_HID_2b658] = 4000, + [BNXT_ULP_CLASS_HID_2cb54] = 4001, + [BNXT_ULP_CLASS_HID_295c4] = 4002, + [BNXT_ULP_CLASS_HID_2d530] = 4003, + [BNXT_ULP_CLASS_HID_2daec] = 4004, + [BNXT_ULP_CLASS_HID_2b210] = 4005, + [BNXT_ULP_CLASS_HID_2bbcc] = 4006, + [BNXT_ULP_CLASS_HID_29fec] = 4007, + [BNXT_ULP_CLASS_HID_285a8] = 4008, + [BNXT_ULP_CLASS_HID_2d6a4] = 4009, + [BNXT_ULP_CLASS_HID_2dc60] = 4010, + [BNXT_ULP_CLASS_HID_2a000] = 4011, + [BNXT_ULP_CLASS_HID_2a63c] = 4012, + [BNXT_ULP_CLASS_HID_6a3f4] = 4013, + [BNXT_ULP_CLASS_HID_6a9b0] = 4014, + [BNXT_ULP_CLASS_HID_68d50] = 4015, + [BNXT_ULP_CLASS_HID_6b30c] = 4016, + [BNXT_ULP_CLASS_HID_6c408] = 4017, + [BNXT_ULP_CLASS_HID_6cdc4] = 4018, + [BNXT_ULP_CLASS_HID_6d1e4] = 4019, + [BNXT_ULP_CLASS_HID_6d7a0] = 4020, + [BNXT_ULP_CLASS_HID_68ec4] = 4021, + [BNXT_ULP_CLASS_HID_6b480] = 4022, + [BNXT_ULP_CLASS_HID_698a0] = 4023, + [BNXT_ULP_CLASS_HID_69e5c] = 4024, + [BNXT_ULP_CLASS_HID_6d358] = 4025, + [BNXT_ULP_CLASS_HID_6d914] = 4026, + [BNXT_ULP_CLASS_HID_6bd34] = 4027, + [BNXT_ULP_CLASS_HID_6a2f0] = 4028, + [BNXT_ULP_CLASS_HID_3dcc0] = 4029, + [BNXT_ULP_CLASS_HID_3c2fc] = 4030, + [BNXT_ULP_CLASS_HID_3a69c] = 4031, + [BNXT_ULP_CLASS_HID_3ac58] = 4032, + [BNXT_ULP_CLASS_HID_38208] = 4033, + [BNXT_ULP_CLASS_HID_38bc4] = 4034, + [BNXT_ULP_CLASS_HID_3cb30] = 4035, + [BNXT_ULP_CLASS_HID_395a0] = 4036, + [BNXT_ULP_CLASS_HID_3a810] = 4037, + [BNXT_ULP_CLASS_HID_3d1cc] = 4038, + [BNXT_ULP_CLASS_HID_3b5ec] = 4039, + [BNXT_ULP_CLASS_HID_3bba8] = 4040, + [BNXT_ULP_CLASS_HID_39158] = 4041, + [BNXT_ULP_CLASS_HID_39714] = 4042, + [BNXT_ULP_CLASS_HID_3d600] = 4043, + [BNXT_ULP_CLASS_HID_3dc3c] = 4044, + [BNXT_ULP_CLASS_HID_7d9f4] = 4045, + [BNXT_ULP_CLASS_HID_7dfb0] = 4046, + [BNXT_ULP_CLASS_HID_7a350] = 4047, + [BNXT_ULP_CLASS_HID_7a90c] = 4048, + [BNXT_ULP_CLASS_HID_79f3c] = 4049, + [BNXT_ULP_CLASS_HID_784f8] = 4050, + [BNXT_ULP_CLASS_HID_7c7e4] = 4051, + [BNXT_ULP_CLASS_HID_7cda0] = 4052, + [BNXT_ULP_CLASS_HID_7a4c4] = 4053, + [BNXT_ULP_CLASS_HID_7aa80] = 4054, + [BNXT_ULP_CLASS_HID_78ea0] = 4055, + [BNXT_ULP_CLASS_HID_7b45c] = 4056, + [BNXT_ULP_CLASS_HID_7c958] = 4057, + [BNXT_ULP_CLASS_HID_793c8] = 4058, + [BNXT_ULP_CLASS_HID_7d334] = 4059, + [BNXT_ULP_CLASS_HID_7d8f0] = 4060, + [BNXT_ULP_CLASS_HID_9ab8] = 4061, + [BNXT_ULP_CLASS_HID_8084] = 4062, + [BNXT_ULP_CLASS_HID_c390] = 4063, + [BNXT_ULP_CLASS_HID_c9dc] = 4064, + [BNXT_ULP_CLASS_HID_bf2c] = 4065, + [BNXT_ULP_CLASS_HID_a568] = 4066, + [BNXT_ULP_CLASS_HID_8948] = 4067, + [BNXT_ULP_CLASS_HID_8e94] = 4068, + [BNXT_ULP_CLASS_HID_4978c] = 4069, + [BNXT_ULP_CLASS_HID_49dc8] = 4070, + [BNXT_ULP_CLASS_HID_4dce4] = 4071, + [BNXT_ULP_CLASS_HID_4c220] = 4072, + [BNXT_ULP_CLASS_HID_4b870] = 4073, + [BNXT_ULP_CLASS_HID_4a1bc] = 4074, + [BNXT_ULP_CLASS_HID_4859c] = 4075, + [BNXT_ULP_CLASS_HID_48bd8] = 4076, + [BNXT_ULP_CLASS_HID_1b0b8] = 4077, + [BNXT_ULP_CLASS_HID_1b684] = 4078, + [BNXT_ULP_CLASS_HID_19ae4] = 4079, + [BNXT_ULP_CLASS_HID_18020] = 4080, + [BNXT_ULP_CLASS_HID_1d52c] = 4081, + [BNXT_ULP_CLASS_HID_1db68] = 4082, + [BNXT_ULP_CLASS_HID_1bf48] = 4083, + [BNXT_ULP_CLASS_HID_1a494] = 4084, + [BNXT_ULP_CLASS_HID_58d8c] = 4085, + [BNXT_ULP_CLASS_HID_5b3c8] = 4086, + [BNXT_ULP_CLASS_HID_59728] = 4087, + [BNXT_ULP_CLASS_HID_59d74] = 4088, + [BNXT_ULP_CLASS_HID_5ae70] = 4089, + [BNXT_ULP_CLASS_HID_5d7bc] = 4090, + [BNXT_ULP_CLASS_HID_5bb9c] = 4091, + [BNXT_ULP_CLASS_HID_5a1d8] = 4092, + [BNXT_ULP_CLASS_HID_c138] = 4093, + [BNXT_ULP_CLASS_HID_c704] = 4094, + [BNXT_ULP_CLASS_HID_c610] = 4095, + [BNXT_ULP_CLASS_HID_d0a0] = 4096, + [BNXT_ULP_CLASS_HID_e5ac] = 4097, + [BNXT_ULP_CLASS_HID_ebe8] = 4098, + [BNXT_ULP_CLASS_HID_cfc8] = 4099, + [BNXT_ULP_CLASS_HID_f514] = 4100, + [BNXT_ULP_CLASS_HID_4da0c] = 4101, + [BNXT_ULP_CLASS_HID_4c048] = 4102, + [BNXT_ULP_CLASS_HID_4c364] = 4103, + [BNXT_ULP_CLASS_HID_4c8a0] = 4104, + [BNXT_ULP_CLASS_HID_4fef0] = 4105, + [BNXT_ULP_CLASS_HID_4e43c] = 4106, + [BNXT_ULP_CLASS_HID_4c81c] = 4107, + [BNXT_ULP_CLASS_HID_4ce58] = 4108, + [BNXT_ULP_CLASS_HID_1f738] = 4109, + [BNXT_ULP_CLASS_HID_1fd04] = 4110, + [BNXT_ULP_CLASS_HID_1c164] = 4111, + [BNXT_ULP_CLASS_HID_1c6a0] = 4112, + [BNXT_ULP_CLASS_HID_1dbac] = 4113, + [BNXT_ULP_CLASS_HID_1c1e8] = 4114, + [BNXT_ULP_CLASS_HID_1e5c8] = 4115, + [BNXT_ULP_CLASS_HID_1eb14] = 4116, + [BNXT_ULP_CLASS_HID_5f00c] = 4117, + [BNXT_ULP_CLASS_HID_5f648] = 4118, + [BNXT_ULP_CLASS_HID_5dda8] = 4119, + [BNXT_ULP_CLASS_HID_5c3f4] = 4120, + [BNXT_ULP_CLASS_HID_5d4f0] = 4121, + [BNXT_ULP_CLASS_HID_5da3c] = 4122, + [BNXT_ULP_CLASS_HID_5fe1c] = 4123, + [BNXT_ULP_CLASS_HID_5e458] = 4124, + [BNXT_ULP_CLASS_HID_bc78] = 4125, + [BNXT_ULP_CLASS_HID_a244] = 4126, + [BNXT_ULP_CLASS_HID_e550] = 4127, + [BNXT_ULP_CLASS_HID_ea9c] = 4128, + [BNXT_ULP_CLASS_HID_a0ec] = 4129, + [BNXT_ULP_CLASS_HID_a628] = 4130, + [BNXT_ULP_CLASS_HID_aa08] = 4131, + [BNXT_ULP_CLASS_HID_b054] = 4132, + [BNXT_ULP_CLASS_HID_4b94c] = 4133, + [BNXT_ULP_CLASS_HID_4be88] = 4134, + [BNXT_ULP_CLASS_HID_4e1a4] = 4135, + [BNXT_ULP_CLASS_HID_4e7e0] = 4136, + [BNXT_ULP_CLASS_HID_4bd30] = 4137, + [BNXT_ULP_CLASS_HID_4a37c] = 4138, + [BNXT_ULP_CLASS_HID_4a75c] = 4139, + [BNXT_ULP_CLASS_HID_4ac98] = 4140, + [BNXT_ULP_CLASS_HID_1b278] = 4141, + [BNXT_ULP_CLASS_HID_1b844] = 4142, + [BNXT_ULP_CLASS_HID_1bfa4] = 4143, + [BNXT_ULP_CLASS_HID_1a5e0] = 4144, + [BNXT_ULP_CLASS_HID_1f6ec] = 4145, + [BNXT_ULP_CLASS_HID_1fc28] = 4146, + [BNXT_ULP_CLASS_HID_1a008] = 4147, + [BNXT_ULP_CLASS_HID_1a654] = 4148, + [BNXT_ULP_CLASS_HID_5af4c] = 4149, + [BNXT_ULP_CLASS_HID_5b488] = 4150, + [BNXT_ULP_CLASS_HID_5b8e8] = 4151, + [BNXT_ULP_CLASS_HID_5be34] = 4152, + [BNXT_ULP_CLASS_HID_5f330] = 4153, + [BNXT_ULP_CLASS_HID_5f97c] = 4154, + [BNXT_ULP_CLASS_HID_5bd5c] = 4155, + [BNXT_ULP_CLASS_HID_5a298] = 4156, + [BNXT_ULP_CLASS_HID_e2f8] = 4157, + [BNXT_ULP_CLASS_HID_e8c4] = 4158, + [BNXT_ULP_CLASS_HID_ebd0] = 4159, + [BNXT_ULP_CLASS_HID_f260] = 4160, + [BNXT_ULP_CLASS_HID_e76c] = 4161, + [BNXT_ULP_CLASS_HID_eca8] = 4162, + [BNXT_ULP_CLASS_HID_f088] = 4163, + [BNXT_ULP_CLASS_HID_f6d4] = 4164, + [BNXT_ULP_CLASS_HID_4ffcc] = 4165, + [BNXT_ULP_CLASS_HID_4e508] = 4166, + [BNXT_ULP_CLASS_HID_4e424] = 4167, + [BNXT_ULP_CLASS_HID_4ea60] = 4168, + [BNXT_ULP_CLASS_HID_4e3b0] = 4169, + [BNXT_ULP_CLASS_HID_4e9fc] = 4170, + [BNXT_ULP_CLASS_HID_4eddc] = 4171, + [BNXT_ULP_CLASS_HID_4f318] = 4172, + [BNXT_ULP_CLASS_HID_1f8f8] = 4173, + [BNXT_ULP_CLASS_HID_1fec4] = 4174, + [BNXT_ULP_CLASS_HID_1e224] = 4175, + [BNXT_ULP_CLASS_HID_1e860] = 4176, + [BNXT_ULP_CLASS_HID_1fd6c] = 4177, + [BNXT_ULP_CLASS_HID_1e2a8] = 4178, + [BNXT_ULP_CLASS_HID_1e688] = 4179, + [BNXT_ULP_CLASS_HID_1ecd4] = 4180, + [BNXT_ULP_CLASS_HID_5f5cc] = 4181, + [BNXT_ULP_CLASS_HID_5fb08] = 4182, + [BNXT_ULP_CLASS_HID_5ff68] = 4183, + [BNXT_ULP_CLASS_HID_5e4b4] = 4184, + [BNXT_ULP_CLASS_HID_5f9b0] = 4185, + [BNXT_ULP_CLASS_HID_5fffc] = 4186, + [BNXT_ULP_CLASS_HID_5e3dc] = 4187, + [BNXT_ULP_CLASS_HID_5e918] = 4188, + [BNXT_ULP_CLASS_HID_23de0] = 4189, + [BNXT_ULP_CLASS_HID_223dc] = 4190, + [BNXT_ULP_CLASS_HID_207bc] = 4191, + [BNXT_ULP_CLASS_HID_20d78] = 4192, + [BNXT_ULP_CLASS_HID_25e74] = 4193, + [BNXT_ULP_CLASS_HID_24430] = 4194, + [BNXT_ULP_CLASS_HID_22810] = 4195, + [BNXT_ULP_CLASS_HID_251cc] = 4196, + [BNXT_ULP_CLASS_HID_20930] = 4197, + [BNXT_ULP_CLASS_HID_20eec] = 4198, + [BNXT_ULP_CLASS_HID_212cc] = 4199, + [BNXT_ULP_CLASS_HID_21888] = 4200, + [BNXT_ULP_CLASS_HID_22d84] = 4201, + [BNXT_ULP_CLASS_HID_25340] = 4202, + [BNXT_ULP_CLASS_HID_23720] = 4203, + [BNXT_ULP_CLASS_HID_23d1c] = 4204, + [BNXT_ULP_CLASS_HID_636d4] = 4205, + [BNXT_ULP_CLASS_HID_63c90] = 4206, + [BNXT_ULP_CLASS_HID_60070] = 4207, + [BNXT_ULP_CLASS_HID_6062c] = 4208, + [BNXT_ULP_CLASS_HID_65b28] = 4209, + [BNXT_ULP_CLASS_HID_640e4] = 4210, + [BNXT_ULP_CLASS_HID_624c4] = 4211, + [BNXT_ULP_CLASS_HID_62a80] = 4212, + [BNXT_ULP_CLASS_HID_605e4] = 4213, + [BNXT_ULP_CLASS_HID_60ba0] = 4214, + [BNXT_ULP_CLASS_HID_64acc] = 4215, + [BNXT_ULP_CLASS_HID_6157c] = 4216, + [BNXT_ULP_CLASS_HID_62678] = 4217, + [BNXT_ULP_CLASS_HID_62c34] = 4218, + [BNXT_ULP_CLASS_HID_63014] = 4219, + [BNXT_ULP_CLASS_HID_639d0] = 4220, + [BNXT_ULP_CLASS_HID_353e0] = 4221, + [BNXT_ULP_CLASS_HID_359dc] = 4222, + [BNXT_ULP_CLASS_HID_33dbc] = 4223, + [BNXT_ULP_CLASS_HID_32378] = 4224, + [BNXT_ULP_CLASS_HID_31928] = 4225, + [BNXT_ULP_CLASS_HID_31ee4] = 4226, + [BNXT_ULP_CLASS_HID_35e10] = 4227, + [BNXT_ULP_CLASS_HID_347cc] = 4228, + [BNXT_ULP_CLASS_HID_33f30] = 4229, + [BNXT_ULP_CLASS_HID_324ec] = 4230, + [BNXT_ULP_CLASS_HID_308cc] = 4231, + [BNXT_ULP_CLASS_HID_30e88] = 4232, + [BNXT_ULP_CLASS_HID_34384] = 4233, + [BNXT_ULP_CLASS_HID_34940] = 4234, + [BNXT_ULP_CLASS_HID_32d20] = 4235, + [BNXT_ULP_CLASS_HID_3531c] = 4236, + [BNXT_ULP_CLASS_HID_72cd4] = 4237, + [BNXT_ULP_CLASS_HID_75290] = 4238, + [BNXT_ULP_CLASS_HID_73670] = 4239, + [BNXT_ULP_CLASS_HID_73c2c] = 4240, + [BNXT_ULP_CLASS_HID_7121c] = 4241, + [BNXT_ULP_CLASS_HID_71bd8] = 4242, + [BNXT_ULP_CLASS_HID_75ac4] = 4243, + [BNXT_ULP_CLASS_HID_74080] = 4244, + [BNXT_ULP_CLASS_HID_73be4] = 4245, + [BNXT_ULP_CLASS_HID_721a0] = 4246, + [BNXT_ULP_CLASS_HID_70580] = 4247, + [BNXT_ULP_CLASS_HID_70b7c] = 4248, + [BNXT_ULP_CLASS_HID_75c78] = 4249, + [BNXT_ULP_CLASS_HID_74234] = 4250, + [BNXT_ULP_CLASS_HID_72614] = 4251, + [BNXT_ULP_CLASS_HID_72fd0] = 4252, + [BNXT_ULP_CLASS_HID_2a6e0] = 4253, + [BNXT_ULP_CLASS_HID_2acdc] = 4254, + [BNXT_ULP_CLASS_HID_2b0bc] = 4255, + [BNXT_ULP_CLASS_HID_2b678] = 4256, + [BNXT_ULP_CLASS_HID_2cb74] = 4257, + [BNXT_ULP_CLASS_HID_295e4] = 4258, + [BNXT_ULP_CLASS_HID_2d510] = 4259, + [BNXT_ULP_CLASS_HID_2dacc] = 4260, + [BNXT_ULP_CLASS_HID_2b230] = 4261, + [BNXT_ULP_CLASS_HID_2bbec] = 4262, + [BNXT_ULP_CLASS_HID_29fcc] = 4263, + [BNXT_ULP_CLASS_HID_28588] = 4264, + [BNXT_ULP_CLASS_HID_2d684] = 4265, + [BNXT_ULP_CLASS_HID_2dc40] = 4266, + [BNXT_ULP_CLASS_HID_2a020] = 4267, + [BNXT_ULP_CLASS_HID_2a61c] = 4268, + [BNXT_ULP_CLASS_HID_6a3d4] = 4269, + [BNXT_ULP_CLASS_HID_6a990] = 4270, + [BNXT_ULP_CLASS_HID_68d70] = 4271, + [BNXT_ULP_CLASS_HID_6b32c] = 4272, + [BNXT_ULP_CLASS_HID_6c428] = 4273, + [BNXT_ULP_CLASS_HID_6cde4] = 4274, + [BNXT_ULP_CLASS_HID_6d1c4] = 4275, + [BNXT_ULP_CLASS_HID_6d780] = 4276, + [BNXT_ULP_CLASS_HID_68ee4] = 4277, + [BNXT_ULP_CLASS_HID_6b4a0] = 4278, + [BNXT_ULP_CLASS_HID_69880] = 4279, + [BNXT_ULP_CLASS_HID_69e7c] = 4280, + [BNXT_ULP_CLASS_HID_6d378] = 4281, + [BNXT_ULP_CLASS_HID_6d934] = 4282, + [BNXT_ULP_CLASS_HID_6bd14] = 4283, + [BNXT_ULP_CLASS_HID_6a2d0] = 4284, + [BNXT_ULP_CLASS_HID_3dce0] = 4285, + [BNXT_ULP_CLASS_HID_3c2dc] = 4286, + [BNXT_ULP_CLASS_HID_3a6bc] = 4287, + [BNXT_ULP_CLASS_HID_3ac78] = 4288, + [BNXT_ULP_CLASS_HID_38228] = 4289, + [BNXT_ULP_CLASS_HID_38be4] = 4290, + [BNXT_ULP_CLASS_HID_3cb10] = 4291, + [BNXT_ULP_CLASS_HID_39580] = 4292, + [BNXT_ULP_CLASS_HID_3a830] = 4293, + [BNXT_ULP_CLASS_HID_3d1ec] = 4294, + [BNXT_ULP_CLASS_HID_3b5cc] = 4295, + [BNXT_ULP_CLASS_HID_3bb88] = 4296, + [BNXT_ULP_CLASS_HID_39178] = 4297, + [BNXT_ULP_CLASS_HID_39734] = 4298, + [BNXT_ULP_CLASS_HID_3d620] = 4299, + [BNXT_ULP_CLASS_HID_3dc1c] = 4300, + [BNXT_ULP_CLASS_HID_7d9d4] = 4301, + [BNXT_ULP_CLASS_HID_7df90] = 4302, + [BNXT_ULP_CLASS_HID_7a370] = 4303, + [BNXT_ULP_CLASS_HID_7a92c] = 4304, + [BNXT_ULP_CLASS_HID_79f1c] = 4305, + [BNXT_ULP_CLASS_HID_784d8] = 4306, + [BNXT_ULP_CLASS_HID_7c7c4] = 4307, + [BNXT_ULP_CLASS_HID_7cd80] = 4308, + [BNXT_ULP_CLASS_HID_7a4e4] = 4309, + [BNXT_ULP_CLASS_HID_7aaa0] = 4310, + [BNXT_ULP_CLASS_HID_78e80] = 4311, + [BNXT_ULP_CLASS_HID_7b47c] = 4312, + [BNXT_ULP_CLASS_HID_7c978] = 4313, + [BNXT_ULP_CLASS_HID_793e8] = 4314, + [BNXT_ULP_CLASS_HID_7d314] = 4315, + [BNXT_ULP_CLASS_HID_7d8d0] = 4316, + [BNXT_ULP_CLASS_HID_9ad8] = 4317, + [BNXT_ULP_CLASS_HID_80e4] = 4318, + [BNXT_ULP_CLASS_HID_c3f0] = 4319, + [BNXT_ULP_CLASS_HID_c9bc] = 4320, + [BNXT_ULP_CLASS_HID_bf4c] = 4321, + [BNXT_ULP_CLASS_HID_a508] = 4322, + [BNXT_ULP_CLASS_HID_8928] = 4323, + [BNXT_ULP_CLASS_HID_8ef4] = 4324, + [BNXT_ULP_CLASS_HID_497ec] = 4325, + [BNXT_ULP_CLASS_HID_49da8] = 4326, + [BNXT_ULP_CLASS_HID_4dc84] = 4327, + [BNXT_ULP_CLASS_HID_4c240] = 4328, + [BNXT_ULP_CLASS_HID_4b810] = 4329, + [BNXT_ULP_CLASS_HID_4a1dc] = 4330, + [BNXT_ULP_CLASS_HID_485fc] = 4331, + [BNXT_ULP_CLASS_HID_48bb8] = 4332, + [BNXT_ULP_CLASS_HID_1b0d8] = 4333, + [BNXT_ULP_CLASS_HID_1b6e4] = 4334, + [BNXT_ULP_CLASS_HID_19a84] = 4335, + [BNXT_ULP_CLASS_HID_18040] = 4336, + [BNXT_ULP_CLASS_HID_1d54c] = 4337, + [BNXT_ULP_CLASS_HID_1db08] = 4338, + [BNXT_ULP_CLASS_HID_1bf28] = 4339, + [BNXT_ULP_CLASS_HID_1a4f4] = 4340, + [BNXT_ULP_CLASS_HID_58dec] = 4341, + [BNXT_ULP_CLASS_HID_5b3a8] = 4342, + [BNXT_ULP_CLASS_HID_59748] = 4343, + [BNXT_ULP_CLASS_HID_59d14] = 4344, + [BNXT_ULP_CLASS_HID_5ae10] = 4345, + [BNXT_ULP_CLASS_HID_5d7dc] = 4346, + [BNXT_ULP_CLASS_HID_5bbfc] = 4347, + [BNXT_ULP_CLASS_HID_5a1b8] = 4348, + [BNXT_ULP_CLASS_HID_c158] = 4349, + [BNXT_ULP_CLASS_HID_c764] = 4350, + [BNXT_ULP_CLASS_HID_c670] = 4351, + [BNXT_ULP_CLASS_HID_d0c0] = 4352, + [BNXT_ULP_CLASS_HID_e5cc] = 4353, + [BNXT_ULP_CLASS_HID_eb88] = 4354, + [BNXT_ULP_CLASS_HID_cfa8] = 4355, + [BNXT_ULP_CLASS_HID_f574] = 4356, + [BNXT_ULP_CLASS_HID_4da6c] = 4357, + [BNXT_ULP_CLASS_HID_4c028] = 4358, + [BNXT_ULP_CLASS_HID_4c304] = 4359, + [BNXT_ULP_CLASS_HID_4c8c0] = 4360, + [BNXT_ULP_CLASS_HID_4fe90] = 4361, + [BNXT_ULP_CLASS_HID_4e45c] = 4362, + [BNXT_ULP_CLASS_HID_4c87c] = 4363, + [BNXT_ULP_CLASS_HID_4ce38] = 4364, + [BNXT_ULP_CLASS_HID_1f758] = 4365, + [BNXT_ULP_CLASS_HID_1fd64] = 4366, + [BNXT_ULP_CLASS_HID_1c104] = 4367, + [BNXT_ULP_CLASS_HID_1c6c0] = 4368, + [BNXT_ULP_CLASS_HID_1dbcc] = 4369, + [BNXT_ULP_CLASS_HID_1c188] = 4370, + [BNXT_ULP_CLASS_HID_1e5a8] = 4371, + [BNXT_ULP_CLASS_HID_1eb74] = 4372, + [BNXT_ULP_CLASS_HID_5f06c] = 4373, + [BNXT_ULP_CLASS_HID_5f628] = 4374, + [BNXT_ULP_CLASS_HID_5ddc8] = 4375, + [BNXT_ULP_CLASS_HID_5c394] = 4376, + [BNXT_ULP_CLASS_HID_5d490] = 4377, + [BNXT_ULP_CLASS_HID_5da5c] = 4378, + [BNXT_ULP_CLASS_HID_5fe7c] = 4379, + [BNXT_ULP_CLASS_HID_5e438] = 4380, + [BNXT_ULP_CLASS_HID_bc18] = 4381, + [BNXT_ULP_CLASS_HID_a224] = 4382, + [BNXT_ULP_CLASS_HID_e530] = 4383, + [BNXT_ULP_CLASS_HID_eafc] = 4384, + [BNXT_ULP_CLASS_HID_a08c] = 4385, + [BNXT_ULP_CLASS_HID_a648] = 4386, + [BNXT_ULP_CLASS_HID_aa68] = 4387, + [BNXT_ULP_CLASS_HID_b034] = 4388, + [BNXT_ULP_CLASS_HID_4b92c] = 4389, + [BNXT_ULP_CLASS_HID_4bee8] = 4390, + [BNXT_ULP_CLASS_HID_4e1c4] = 4391, + [BNXT_ULP_CLASS_HID_4e780] = 4392, + [BNXT_ULP_CLASS_HID_4bd50] = 4393, + [BNXT_ULP_CLASS_HID_4a31c] = 4394, + [BNXT_ULP_CLASS_HID_4a73c] = 4395, + [BNXT_ULP_CLASS_HID_4acf8] = 4396, + [BNXT_ULP_CLASS_HID_1b218] = 4397, + [BNXT_ULP_CLASS_HID_1b824] = 4398, + [BNXT_ULP_CLASS_HID_1bfc4] = 4399, + [BNXT_ULP_CLASS_HID_1a580] = 4400, + [BNXT_ULP_CLASS_HID_1f68c] = 4401, + [BNXT_ULP_CLASS_HID_1fc48] = 4402, + [BNXT_ULP_CLASS_HID_1a068] = 4403, + [BNXT_ULP_CLASS_HID_1a634] = 4404, + [BNXT_ULP_CLASS_HID_5af2c] = 4405, + [BNXT_ULP_CLASS_HID_5b4e8] = 4406, + [BNXT_ULP_CLASS_HID_5b888] = 4407, + [BNXT_ULP_CLASS_HID_5be54] = 4408, + [BNXT_ULP_CLASS_HID_5f350] = 4409, + [BNXT_ULP_CLASS_HID_5f91c] = 4410, + [BNXT_ULP_CLASS_HID_5bd3c] = 4411, + [BNXT_ULP_CLASS_HID_5a2f8] = 4412, + [BNXT_ULP_CLASS_HID_e298] = 4413, + [BNXT_ULP_CLASS_HID_e8a4] = 4414, + [BNXT_ULP_CLASS_HID_ebb0] = 4415, + [BNXT_ULP_CLASS_HID_f200] = 4416, + [BNXT_ULP_CLASS_HID_e70c] = 4417, + [BNXT_ULP_CLASS_HID_ecc8] = 4418, + [BNXT_ULP_CLASS_HID_f0e8] = 4419, + [BNXT_ULP_CLASS_HID_f6b4] = 4420, + [BNXT_ULP_CLASS_HID_4ffac] = 4421, + [BNXT_ULP_CLASS_HID_4e568] = 4422, + [BNXT_ULP_CLASS_HID_4e444] = 4423, + [BNXT_ULP_CLASS_HID_4ea00] = 4424, + [BNXT_ULP_CLASS_HID_4e3d0] = 4425, + [BNXT_ULP_CLASS_HID_4e99c] = 4426, + [BNXT_ULP_CLASS_HID_4edbc] = 4427, + [BNXT_ULP_CLASS_HID_4f378] = 4428, + [BNXT_ULP_CLASS_HID_1f898] = 4429, + [BNXT_ULP_CLASS_HID_1fea4] = 4430, + [BNXT_ULP_CLASS_HID_1e244] = 4431, + [BNXT_ULP_CLASS_HID_1e800] = 4432, + [BNXT_ULP_CLASS_HID_1fd0c] = 4433, + [BNXT_ULP_CLASS_HID_1e2c8] = 4434, + [BNXT_ULP_CLASS_HID_1e6e8] = 4435, + [BNXT_ULP_CLASS_HID_1ecb4] = 4436, + [BNXT_ULP_CLASS_HID_5f5ac] = 4437, + [BNXT_ULP_CLASS_HID_5fb68] = 4438, + [BNXT_ULP_CLASS_HID_5ff08] = 4439, + [BNXT_ULP_CLASS_HID_5e4d4] = 4440, + [BNXT_ULP_CLASS_HID_5f9d0] = 4441, + [BNXT_ULP_CLASS_HID_5ff9c] = 4442, + [BNXT_ULP_CLASS_HID_5e3bc] = 4443, + [BNXT_ULP_CLASS_HID_5e978] = 4444, + [BNXT_ULP_CLASS_HID_34f6] = 4445, + [BNXT_ULP_CLASS_HID_3a3a] = 4446, + [BNXT_ULP_CLASS_HID_541e] = 4447, + [BNXT_ULP_CLASS_HID_5a22] = 4448, + [BNXT_ULP_CLASS_HID_34fe] = 4449, + [BNXT_ULP_CLASS_HID_3a32] = 4450, + [BNXT_ULP_CLASS_HID_4a42] = 4451, + [BNXT_ULP_CLASS_HID_14d2] = 4452, + [BNXT_ULP_CLASS_HID_34c8] = 4453, + [BNXT_ULP_CLASS_HID_3a04] = 4454, + [BNXT_ULP_CLASS_HID_1e64] = 4455, + [BNXT_ULP_CLASS_HID_07a0] = 4456, + [BNXT_ULP_CLASS_HID_595c] = 4457, + [BNXT_ULP_CLASS_HID_5e98] = 4458, + [BNXT_ULP_CLASS_HID_22f8] = 4459, + [BNXT_ULP_CLASS_HID_2834] = 4460, + [BNXT_ULP_CLASS_HID_0398] = 4461, + [BNXT_ULP_CLASS_HID_09d4] = 4462, + [BNXT_ULP_CLASS_HID_48c0] = 4463, + [BNXT_ULP_CLASS_HID_1370] = 4464, + [BNXT_ULP_CLASS_HID_246c] = 4465, + [BNXT_ULP_CLASS_HID_2da8] = 4466, + [BNXT_ULP_CLASS_HID_3188] = 4467, + [BNXT_ULP_CLASS_HID_37c4] = 4468, + [BNXT_ULP_CLASS_HID_34f0] = 4469, + [BNXT_ULP_CLASS_HID_3a3c] = 4470, + [BNXT_ULP_CLASS_HID_1e5c] = 4471, + [BNXT_ULP_CLASS_HID_0798] = 4472, + [BNXT_ULP_CLASS_HID_5964] = 4473, + [BNXT_ULP_CLASS_HID_5ea0] = 4474, + [BNXT_ULP_CLASS_HID_22c0] = 4475, + [BNXT_ULP_CLASS_HID_280c] = 4476, + [BNXT_ULP_CLASS_HID_43104] = 4477, + [BNXT_ULP_CLASS_HID_43740] = 4478, + [BNXT_ULP_CLASS_HID_41b60] = 4479, + [BNXT_ULP_CLASS_HID_400ac] = 4480, + [BNXT_ULP_CLASS_HID_455a8] = 4481, + [BNXT_ULP_CLASS_HID_45bf4] = 4482, + [BNXT_ULP_CLASS_HID_43f14] = 4483, + [BNXT_ULP_CLASS_HID_42550] = 4484, + [BNXT_ULP_CLASS_HID_34d6] = 4485, + [BNXT_ULP_CLASS_HID_3a1a] = 4486, + [BNXT_ULP_CLASS_HID_543e] = 4487, + [BNXT_ULP_CLASS_HID_5a02] = 4488, + [BNXT_ULP_CLASS_HID_34de] = 4489, + [BNXT_ULP_CLASS_HID_3a12] = 4490, + [BNXT_ULP_CLASS_HID_4a62] = 4491, + [BNXT_ULP_CLASS_HID_14f2] = 4492, + [BNXT_ULP_CLASS_HID_34b6] = 4493, + [BNXT_ULP_CLASS_HID_3a7a] = 4494, + [BNXT_ULP_CLASS_HID_545e] = 4495, + [BNXT_ULP_CLASS_HID_5a62] = 4496, + [BNXT_ULP_CLASS_HID_34be] = 4497, + [BNXT_ULP_CLASS_HID_3a72] = 4498, + [BNXT_ULP_CLASS_HID_4a02] = 4499, + [BNXT_ULP_CLASS_HID_1492] = 4500, + [BNXT_ULP_CLASS_HID_34a8] = 4501, + [BNXT_ULP_CLASS_HID_3a64] = 4502, + [BNXT_ULP_CLASS_HID_1e04] = 4503, + [BNXT_ULP_CLASS_HID_07c0] = 4504, + [BNXT_ULP_CLASS_HID_593c] = 4505, + [BNXT_ULP_CLASS_HID_5ef8] = 4506, + [BNXT_ULP_CLASS_HID_2298] = 4507, + [BNXT_ULP_CLASS_HID_2854] = 4508, + [BNXT_ULP_CLASS_HID_03f8] = 4509, + [BNXT_ULP_CLASS_HID_09b4] = 4510, + [BNXT_ULP_CLASS_HID_48a0] = 4511, + [BNXT_ULP_CLASS_HID_1310] = 4512, + [BNXT_ULP_CLASS_HID_240c] = 4513, + [BNXT_ULP_CLASS_HID_2dc8] = 4514, + [BNXT_ULP_CLASS_HID_31e8] = 4515, + [BNXT_ULP_CLASS_HID_37a4] = 4516, + [BNXT_ULP_CLASS_HID_34d0] = 4517, + [BNXT_ULP_CLASS_HID_3a1c] = 4518, + [BNXT_ULP_CLASS_HID_1e7c] = 4519, + [BNXT_ULP_CLASS_HID_07b8] = 4520, + [BNXT_ULP_CLASS_HID_5944] = 4521, + [BNXT_ULP_CLASS_HID_5e80] = 4522, + [BNXT_ULP_CLASS_HID_22e0] = 4523, + [BNXT_ULP_CLASS_HID_282c] = 4524, + [BNXT_ULP_CLASS_HID_43124] = 4525, + [BNXT_ULP_CLASS_HID_43760] = 4526, + [BNXT_ULP_CLASS_HID_41b40] = 4527, + [BNXT_ULP_CLASS_HID_4008c] = 4528, + [BNXT_ULP_CLASS_HID_45588] = 4529, + [BNXT_ULP_CLASS_HID_45bd4] = 4530, + [BNXT_ULP_CLASS_HID_43f34] = 4531, + [BNXT_ULP_CLASS_HID_42570] = 4532, + [BNXT_ULP_CLASS_HID_3488] = 4533, + [BNXT_ULP_CLASS_HID_3a44] = 4534, + [BNXT_ULP_CLASS_HID_1e24] = 4535, + [BNXT_ULP_CLASS_HID_07e0] = 4536, + [BNXT_ULP_CLASS_HID_591c] = 4537, + [BNXT_ULP_CLASS_HID_5ed8] = 4538, + [BNXT_ULP_CLASS_HID_22b8] = 4539, + [BNXT_ULP_CLASS_HID_2874] = 4540, + [BNXT_ULP_CLASS_HID_03d8] = 4541, + [BNXT_ULP_CLASS_HID_0994] = 4542, + [BNXT_ULP_CLASS_HID_4880] = 4543, + [BNXT_ULP_CLASS_HID_1330] = 4544, + [BNXT_ULP_CLASS_HID_242c] = 4545, + [BNXT_ULP_CLASS_HID_2de8] = 4546, + [BNXT_ULP_CLASS_HID_31c8] = 4547, + [BNXT_ULP_CLASS_HID_3784] = 4548, + [BNXT_ULP_CLASS_HID_34b0] = 4549, + [BNXT_ULP_CLASS_HID_3a7c] = 4550, + [BNXT_ULP_CLASS_HID_1e1c] = 4551, + [BNXT_ULP_CLASS_HID_07d8] = 4552, + [BNXT_ULP_CLASS_HID_5924] = 4553, + [BNXT_ULP_CLASS_HID_5ee0] = 4554, + [BNXT_ULP_CLASS_HID_2280] = 4555, + [BNXT_ULP_CLASS_HID_284c] = 4556, + [BNXT_ULP_CLASS_HID_43144] = 4557, + [BNXT_ULP_CLASS_HID_43700] = 4558, + [BNXT_ULP_CLASS_HID_41b20] = 4559, + [BNXT_ULP_CLASS_HID_400ec] = 4560, + [BNXT_ULP_CLASS_HID_455e8] = 4561, + [BNXT_ULP_CLASS_HID_45bb4] = 4562, + [BNXT_ULP_CLASS_HID_43f54] = 4563, + [BNXT_ULP_CLASS_HID_42510] = 4564 }; /* Array for the proto matcher list */ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { [1] = { - .class_hid = BNXT_ULP_CLASS_HID_26d1, + .class_hid = BNXT_ULP_CLASS_HID_05d1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 0, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2] = { - .class_hid = BNXT_ULP_CLASS_HID_0071, + .class_hid = BNXT_ULP_CLASS_HID_1229, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 1, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [3] = { - .class_hid = BNXT_ULP_CLASS_HID_53a5, + .class_hid = BNXT_ULP_CLASS_HID_0bed, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 1, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [4] = { - .class_hid = BNXT_ULP_CLASS_HID_1d49, + .class_hid = BNXT_ULP_CLASS_HID_1865, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 2, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [5] = { - .class_hid = BNXT_ULP_CLASS_HID_2095, + .class_hid = BNXT_ULP_CLASS_HID_25c9, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 2, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [6] = { - .class_hid = BNXT_ULP_CLASS_HID_5701, + .class_hid = BNXT_ULP_CLASS_HID_3241, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 2, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [7] = { - .class_hid = BNXT_ULP_CLASS_HID_4d79, + .class_hid = BNXT_ULP_CLASS_HID_2c05, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 2, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [8] = { - .class_hid = BNXT_ULP_CLASS_HID_170d, + .class_hid = BNXT_ULP_CLASS_HID_389d, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 2, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [9] = { - .class_hid = BNXT_ULP_CLASS_HID_1a69, + .class_hid = BNXT_ULP_CLASS_HID_3c3d, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 2, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [10] = { - .class_hid = BNXT_ULP_CLASS_HID_50c5, + .class_hid = BNXT_ULP_CLASS_HID_48b5, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 3, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [11] = { - .class_hid = BNXT_ULP_CLASS_HID_473d, + .class_hid = BNXT_ULP_CLASS_HID_4279, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 3, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [12] = { - .class_hid = BNXT_ULP_CLASS_HID_10c1, + .class_hid = BNXT_ULP_CLASS_HID_4ef1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [13] = { - .class_hid = BNXT_ULP_CLASS_HID_142d, + .class_hid = BNXT_ULP_CLASS_HID_5c55, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [14] = { - .class_hid = BNXT_ULP_CLASS_HID_4a99, + .class_hid = BNXT_ULP_CLASS_HID_0be1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [15] = { - .class_hid = BNXT_ULP_CLASS_HID_40f1, + .class_hid = BNXT_ULP_CLASS_HID_05a5, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [16] = { - .class_hid = BNXT_ULP_CLASS_HID_0a85, + .class_hid = BNXT_ULP_CLASS_HID_123d, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [17] = { - .class_hid = BNXT_ULP_CLASS_HID_0179, + .class_hid = BNXT_ULP_CLASS_HID_4142d, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4, - .flow_pattern_id = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [18] = { - .class_hid = BNXT_ULP_CLASS_HID_37d5, + .class_hid = BNXT_ULP_CLASS_HID_42095, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 5, - .flow_pattern_id = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16392, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [19] = { - .class_hid = BNXT_ULP_CLASS_HID_2e4d, + .class_hid = BNXT_ULP_CLASS_HID_41a69, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 5, - .flow_pattern_id = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [20] = { - .class_hid = BNXT_ULP_CLASS_HID_54ad, + .class_hid = BNXT_ULP_CLASS_HID_426d1, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6, - .flow_pattern_id = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16392, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [21] = { - .class_hid = BNXT_ULP_CLASS_HID_5809, + .class_hid = BNXT_ULP_CLASS_HID_44a99, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6, - .flow_pattern_id = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [22] = { - .class_hid = BNXT_ULP_CLASS_HID_31a9, + .class_hid = BNXT_ULP_CLASS_HID_45701, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6, - .flow_pattern_id = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16392, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [23] = { - .class_hid = BNXT_ULP_CLASS_HID_2801, + .class_hid = BNXT_ULP_CLASS_HID_450c5, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6, - .flow_pattern_id = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [24] = { - .class_hid = BNXT_ULP_CLASS_HID_4e61, + .class_hid = BNXT_ULP_CLASS_HID_40071, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6, - .flow_pattern_id = 1, + .hdr_sig_id = 1, + .flow_sig_id = 16392, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [25] = { - .class_hid = BNXT_ULP_CLASS_HID_2561, + .class_hid = BNXT_ULP_CLASS_HID_40a85, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6, - .flow_pattern_id = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [26] = { - .class_hid = BNXT_ULP_CLASS_HID_2bad, + .class_hid = BNXT_ULP_CLASS_HID_4170d, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 7, - .flow_pattern_id = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24584, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [27] = { - .class_hid = BNXT_ULP_CLASS_HID_054d, + .class_hid = BNXT_ULP_CLASS_HID_410c1, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 7, - .flow_pattern_id = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [28] = { - .class_hid = BNXT_ULP_CLASS_HID_5bdd, + .class_hid = BNXT_ULP_CLASS_HID_41d49, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 7, - .flow_pattern_id = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24584, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [29] = { - .class_hid = BNXT_ULP_CLASS_HID_26f1, + .class_hid = BNXT_ULP_CLASS_HID_440f1, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [30] = { - .class_hid = BNXT_ULP_CLASS_HID_13cf1, + .class_hid = BNXT_ULP_CLASS_HID_44d79, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 7, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [31] = { - .class_hid = BNXT_ULP_CLASS_HID_252f1, + .class_hid = BNXT_ULP_CLASS_HID_4473d, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 8, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [32] = { - .class_hid = BNXT_ULP_CLASS_HID_30c25, + .class_hid = BNXT_ULP_CLASS_HID_453a5, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 9, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [33] = { - .class_hid = BNXT_ULP_CLASS_HID_0051, + .class_hid = BNXT_ULP_CLASS_HID_244e3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 10, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [34] = { - .class_hid = BNXT_ULP_CLASS_HID_11651, + .class_hid = BNXT_ULP_CLASS_HID_2517b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 10, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [35] = { - .class_hid = BNXT_ULP_CLASS_HID_22c51, + .class_hid = BNXT_ULP_CLASS_HID_24b3f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 10, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [36] = { - .class_hid = BNXT_ULP_CLASS_HID_34251, + .class_hid = BNXT_ULP_CLASS_HID_257b7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 10, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [37] = { - .class_hid = BNXT_ULP_CLASS_HID_5385, + .class_hid = BNXT_ULP_CLASS_HID_22f5f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 10, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [38] = { - .class_hid = BNXT_ULP_CLASS_HID_10cc9, + .class_hid = BNXT_ULP_CLASS_HID_23bd7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 10, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [39] = { - .class_hid = BNXT_ULP_CLASS_HID_222c9, + .class_hid = BNXT_ULP_CLASS_HID_2359b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 11, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [40] = { - .class_hid = BNXT_ULP_CLASS_HID_338c9, + .class_hid = BNXT_ULP_CLASS_HID_24213, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 12, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [41] = { - .class_hid = BNXT_ULP_CLASS_HID_1d69, + .class_hid = BNXT_ULP_CLASS_HID_20bab, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [42] = { - .class_hid = BNXT_ULP_CLASS_HID_13369, + .class_hid = BNXT_ULP_CLASS_HID_21823, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [43] = { - .class_hid = BNXT_ULP_CLASS_HID_24969, + .class_hid = BNXT_ULP_CLASS_HID_211e7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [44] = { - .class_hid = BNXT_ULP_CLASS_HID_3025d, + .class_hid = BNXT_ULP_CLASS_HID_21e7f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [45] = { - .class_hid = BNXT_ULP_CLASS_HID_20b5, + .class_hid = BNXT_ULP_CLASS_HID_252f3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [46] = { - .class_hid = BNXT_ULP_CLASS_HID_136b5, + .class_hid = BNXT_ULP_CLASS_HID_2029f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [47] = { - .class_hid = BNXT_ULP_CLASS_HID_24cb5, + .class_hid = BNXT_ULP_CLASS_HID_2590f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [48] = { - .class_hid = BNXT_ULP_CLASS_HID_305f9, + .class_hid = BNXT_ULP_CLASS_HID_208db, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [49] = { - .class_hid = BNXT_ULP_CLASS_HID_5721, + .class_hid = BNXT_ULP_CLASS_HID_231d3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [50] = { - .class_hid = BNXT_ULP_CLASS_HID_11015, + .class_hid = BNXT_ULP_CLASS_HID_23e2b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [51] = { - .class_hid = BNXT_ULP_CLASS_HID_22615, + .class_hid = BNXT_ULP_CLASS_HID_237ef, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [52] = { - .class_hid = BNXT_ULP_CLASS_HID_33c15, + .class_hid = BNXT_ULP_CLASS_HID_24467, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [53] = { - .class_hid = BNXT_ULP_CLASS_HID_4d59, + .class_hid = BNXT_ULP_CLASS_HID_21c0f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [54] = { - .class_hid = BNXT_ULP_CLASS_HID_1068d, + .class_hid = BNXT_ULP_CLASS_HID_22887, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [55] = { - .class_hid = BNXT_ULP_CLASS_HID_21c8d, + .class_hid = BNXT_ULP_CLASS_HID_2224b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [56] = { - .class_hid = BNXT_ULP_CLASS_HID_3328d, + .class_hid = BNXT_ULP_CLASS_HID_22ec3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [57] = { - .class_hid = BNXT_ULP_CLASS_HID_172d, + .class_hid = BNXT_ULP_CLASS_HID_25547, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [58] = { - .class_hid = BNXT_ULP_CLASS_HID_12d2d, + .class_hid = BNXT_ULP_CLASS_HID_20513, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [59] = { - .class_hid = BNXT_ULP_CLASS_HID_2432d, + .class_hid = BNXT_ULP_CLASS_HID_25b83, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [60] = { - .class_hid = BNXT_ULP_CLASS_HID_3592d, + .class_hid = BNXT_ULP_CLASS_HID_20b2f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [61] = { - .class_hid = BNXT_ULP_CLASS_HID_1a49, + .class_hid = BNXT_ULP_CLASS_HID_23fa3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [62] = { - .class_hid = BNXT_ULP_CLASS_HID_13049, + .class_hid = BNXT_ULP_CLASS_HID_24c3b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 13, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [63] = { - .class_hid = BNXT_ULP_CLASS_HID_24649, + .class_hid = BNXT_ULP_CLASS_HID_245ff, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 14, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [64] = { - .class_hid = BNXT_ULP_CLASS_HID_35c49, + .class_hid = BNXT_ULP_CLASS_HID_25277, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 15, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [65] = { - .class_hid = BNXT_ULP_CLASS_HID_50e5, + .class_hid = BNXT_ULP_CLASS_HID_64037, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [66] = { - .class_hid = BNXT_ULP_CLASS_HID_10a29, + .class_hid = BNXT_ULP_CLASS_HID_64c8f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [67] = { - .class_hid = BNXT_ULP_CLASS_HID_22029, + .class_hid = BNXT_ULP_CLASS_HID_64673, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [68] = { - .class_hid = BNXT_ULP_CLASS_HID_33629, + .class_hid = BNXT_ULP_CLASS_HID_652cb, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [69] = { - .class_hid = BNXT_ULP_CLASS_HID_471d, + .class_hid = BNXT_ULP_CLASS_HID_62a93, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [70] = { - .class_hid = BNXT_ULP_CLASS_HID_10041, + .class_hid = BNXT_ULP_CLASS_HID_636eb, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16, + .hdr_sig_id = 2, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [71] = { - .class_hid = BNXT_ULP_CLASS_HID_21641, + .class_hid = BNXT_ULP_CLASS_HID_630af, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 17, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [72] = { - .class_hid = BNXT_ULP_CLASS_HID_32c41, + .class_hid = BNXT_ULP_CLASS_HID_63d27, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 18, + .hdr_sig_id = 2, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [73] = { - .class_hid = BNXT_ULP_CLASS_HID_10e1, + .class_hid = BNXT_ULP_CLASS_HID_606ff, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [74] = { - .class_hid = BNXT_ULP_CLASS_HID_126e1, + .class_hid = BNXT_ULP_CLASS_HID_61377, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [75] = { - .class_hid = BNXT_ULP_CLASS_HID_23ce1, + .class_hid = BNXT_ULP_CLASS_HID_60d3b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [76] = { - .class_hid = BNXT_ULP_CLASS_HID_352e1, + .class_hid = BNXT_ULP_CLASS_HID_619b3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [77] = { - .class_hid = BNXT_ULP_CLASS_HID_140d, + .class_hid = BNXT_ULP_CLASS_HID_64e07, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [78] = { - .class_hid = BNXT_ULP_CLASS_HID_12a0d, + .class_hid = BNXT_ULP_CLASS_HID_65a9f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [79] = { - .class_hid = BNXT_ULP_CLASS_HID_2400d, + .class_hid = BNXT_ULP_CLASS_HID_65443, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [80] = { - .class_hid = BNXT_ULP_CLASS_HID_3560d, + .class_hid = BNXT_ULP_CLASS_HID_603ef, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [81] = { - .class_hid = BNXT_ULP_CLASS_HID_4ab9, + .class_hid = BNXT_ULP_CLASS_HID_62ce7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [82] = { - .class_hid = BNXT_ULP_CLASS_HID_103ed, + .class_hid = BNXT_ULP_CLASS_HID_6397f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [83] = { - .class_hid = BNXT_ULP_CLASS_HID_219ed, + .class_hid = BNXT_ULP_CLASS_HID_63323, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [84] = { - .class_hid = BNXT_ULP_CLASS_HID_32fed, + .class_hid = BNXT_ULP_CLASS_HID_63fbb, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [85] = { - .class_hid = BNXT_ULP_CLASS_HID_40d1, + .class_hid = BNXT_ULP_CLASS_HID_61743, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [86] = { - .class_hid = BNXT_ULP_CLASS_HID_156d1, + .class_hid = BNXT_ULP_CLASS_HID_623db, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [87] = { - .class_hid = BNXT_ULP_CLASS_HID_21005, + .class_hid = BNXT_ULP_CLASS_HID_61d9f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [88] = { - .class_hid = BNXT_ULP_CLASS_HID_32605, + .class_hid = BNXT_ULP_CLASS_HID_62a17, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [89] = { - .class_hid = BNXT_ULP_CLASS_HID_0aa5, + .class_hid = BNXT_ULP_CLASS_HID_6509b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [90] = { - .class_hid = BNXT_ULP_CLASS_HID_120a5, + .class_hid = BNXT_ULP_CLASS_HID_60027, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [91] = { - .class_hid = BNXT_ULP_CLASS_HID_236a5, + .class_hid = BNXT_ULP_CLASS_HID_656d7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [92] = { - .class_hid = BNXT_ULP_CLASS_HID_34ca5, + .class_hid = BNXT_ULP_CLASS_HID_60663, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [93] = { - .class_hid = BNXT_ULP_CLASS_HID_0159, + .class_hid = BNXT_ULP_CLASS_HID_63af7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, - .flow_pattern_id = 1, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [94] = { - .class_hid = BNXT_ULP_CLASS_HID_11759, + .class_hid = BNXT_ULP_CLASS_HID_6474f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 19, - .flow_pattern_id = 1, + .hdr_sig_id = 2, + .flow_sig_id = 49224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [95] = { - .class_hid = BNXT_ULP_CLASS_HID_22d59, + .class_hid = BNXT_ULP_CLASS_HID_64133, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 20, - .flow_pattern_id = 1, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [96] = { - .class_hid = BNXT_ULP_CLASS_HID_34359, + .class_hid = BNXT_ULP_CLASS_HID_64d8b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 21, - .flow_pattern_id = 1, + .hdr_sig_id = 2, + .flow_sig_id = 49224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [97] = { - .class_hid = BNXT_ULP_CLASS_HID_37f5, + .class_hid = BNXT_ULP_CLASS_HID_a3fb, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 22, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [98] = { - .class_hid = BNXT_ULP_CLASS_HID_14df5, + .class_hid = BNXT_ULP_CLASS_HID_b063, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 22, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [99] = { - .class_hid = BNXT_ULP_CLASS_HID_20739, + .class_hid = BNXT_ULP_CLASS_HID_aa27, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 22, - .flow_pattern_id = 1, - .hdr_sig = { .bits = + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [100] = { - .class_hid = BNXT_ULP_CLASS_HID_31d39, + .class_hid = BNXT_ULP_CLASS_HID_b6af, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 22, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [101] = { - .class_hid = BNXT_ULP_CLASS_HID_2e6d, + .class_hid = BNXT_ULP_CLASS_HID_8e47, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 22, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [102] = { - .class_hid = BNXT_ULP_CLASS_HID_1446d, + .class_hid = BNXT_ULP_CLASS_HID_9acf, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 22, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [103] = { - .class_hid = BNXT_ULP_CLASS_HID_25a6d, + .class_hid = BNXT_ULP_CLASS_HID_9483, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 23, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [104] = { - .class_hid = BNXT_ULP_CLASS_HID_31351, + .class_hid = BNXT_ULP_CLASS_HID_a10b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [105] = { - .class_hid = BNXT_ULP_CLASS_HID_548d, + .class_hid = BNXT_ULP_CLASS_HID_c78f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [106] = { - .class_hid = BNXT_ULP_CLASS_HID_10df1, + .class_hid = BNXT_ULP_CLASS_HID_d3f7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [107] = { - .class_hid = BNXT_ULP_CLASS_HID_223f1, + .class_hid = BNXT_ULP_CLASS_HID_cdcb, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [108] = { - .class_hid = BNXT_ULP_CLASS_HID_339f1, + .class_hid = BNXT_ULP_CLASS_HID_da33, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [109] = { - .class_hid = BNXT_ULP_CLASS_HID_5829, + .class_hid = BNXT_ULP_CLASS_HID_b1eb, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [110] = { - .class_hid = BNXT_ULP_CLASS_HID_1111d, + .class_hid = BNXT_ULP_CLASS_HID_be53, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [111] = { - .class_hid = BNXT_ULP_CLASS_HID_2271d, + .class_hid = BNXT_ULP_CLASS_HID_b817, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [112] = { - .class_hid = BNXT_ULP_CLASS_HID_33d1d, + .class_hid = BNXT_ULP_CLASS_HID_c49f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [113] = { - .class_hid = BNXT_ULP_CLASS_HID_3189, + .class_hid = BNXT_ULP_CLASS_HID_49f2f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [114] = { - .class_hid = BNXT_ULP_CLASS_HID_14789, + .class_hid = BNXT_ULP_CLASS_HID_4ab97, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [115] = { - .class_hid = BNXT_ULP_CLASS_HID_200fd, + .class_hid = BNXT_ULP_CLASS_HID_4a56b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [116] = { - .class_hid = BNXT_ULP_CLASS_HID_316fd, + .class_hid = BNXT_ULP_CLASS_HID_4b1d3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [117] = { - .class_hid = BNXT_ULP_CLASS_HID_2821, + .class_hid = BNXT_ULP_CLASS_HID_4898b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [118] = { - .class_hid = BNXT_ULP_CLASS_HID_13e21, + .class_hid = BNXT_ULP_CLASS_HID_495f3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [119] = { - .class_hid = BNXT_ULP_CLASS_HID_25421, + .class_hid = BNXT_ULP_CLASS_HID_48fb7, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [120] = { - .class_hid = BNXT_ULP_CLASS_HID_30d15, + .class_hid = BNXT_ULP_CLASS_HID_49c3f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [121] = { - .class_hid = BNXT_ULP_CLASS_HID_4e41, + .class_hid = BNXT_ULP_CLASS_HID_4c2b3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [122] = { - .class_hid = BNXT_ULP_CLASS_HID_107b5, + .class_hid = BNXT_ULP_CLASS_HID_4cf3b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [123] = { - .class_hid = BNXT_ULP_CLASS_HID_21db5, + .class_hid = BNXT_ULP_CLASS_HID_4c8ff, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [124] = { - .class_hid = BNXT_ULP_CLASS_HID_333b5, + .class_hid = BNXT_ULP_CLASS_HID_4d567, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [125] = { - .class_hid = BNXT_ULP_CLASS_HID_2541, + .class_hid = BNXT_ULP_CLASS_HID_4ad1f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [126] = { - .class_hid = BNXT_ULP_CLASS_HID_2b8d, + .class_hid = BNXT_ULP_CLASS_HID_4b987, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [127] = { - .class_hid = BNXT_ULP_CLASS_HID_056d, + .class_hid = BNXT_ULP_CLASS_HID_4b35b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [128] = { - .class_hid = BNXT_ULP_CLASS_HID_5bfd, + .class_hid = BNXT_ULP_CLASS_HID_4bfc3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 25, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [129] = { - .class_hid = BNXT_ULP_CLASS_HID_2691, + .class_hid = BNXT_ULP_CLASS_HID_1b9fb, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 25, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [130] = { - .class_hid = BNXT_ULP_CLASS_HID_13c91, + .class_hid = BNXT_ULP_CLASS_HID_1c663, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 25, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [131] = { - .class_hid = BNXT_ULP_CLASS_HID_25291, + .class_hid = BNXT_ULP_CLASS_HID_1c027, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 26, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [132] = { - .class_hid = BNXT_ULP_CLASS_HID_30c45, + .class_hid = BNXT_ULP_CLASS_HID_1ccaf, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 27, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [133] = { - .class_hid = BNXT_ULP_CLASS_HID_0031, + .class_hid = BNXT_ULP_CLASS_HID_1a447, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 28, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [134] = { - .class_hid = BNXT_ULP_CLASS_HID_11631, + .class_hid = BNXT_ULP_CLASS_HID_1b0cf, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 28, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [135] = { - .class_hid = BNXT_ULP_CLASS_HID_22c31, + .class_hid = BNXT_ULP_CLASS_HID_1aa83, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 28, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [136] = { - .class_hid = BNXT_ULP_CLASS_HID_34231, + .class_hid = BNXT_ULP_CLASS_HID_1b70b, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 28, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [137] = { - .class_hid = BNXT_ULP_CLASS_HID_53e5, + .class_hid = BNXT_ULP_CLASS_HID_180b3, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 28, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [138] = { - .class_hid = BNXT_ULP_CLASS_HID_10ca9, + .class_hid = BNXT_ULP_CLASS_HID_18d3b, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 28, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [139] = { - .class_hid = BNXT_ULP_CLASS_HID_222a9, + .class_hid = BNXT_ULP_CLASS_HID_186ff, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 29, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [140] = { - .class_hid = BNXT_ULP_CLASS_HID_338a9, + .class_hid = BNXT_ULP_CLASS_HID_19367, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 30, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [141] = { - .class_hid = BNXT_ULP_CLASS_HID_1d09, + .class_hid = BNXT_ULP_CLASS_HID_1c7eb, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [142] = { - .class_hid = BNXT_ULP_CLASS_HID_13309, + .class_hid = BNXT_ULP_CLASS_HID_1d453, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [143] = { - .class_hid = BNXT_ULP_CLASS_HID_24909, + .class_hid = BNXT_ULP_CLASS_HID_1ce17, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [144] = { - .class_hid = BNXT_ULP_CLASS_HID_3023d, + .class_hid = BNXT_ULP_CLASS_HID_1da9f, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [145] = { - .class_hid = BNXT_ULP_CLASS_HID_20d5, + .class_hid = BNXT_ULP_CLASS_HID_5b52f, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [146] = { - .class_hid = BNXT_ULP_CLASS_HID_136d5, + .class_hid = BNXT_ULP_CLASS_HID_5c197, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [147] = { - .class_hid = BNXT_ULP_CLASS_HID_24cd5, + .class_hid = BNXT_ULP_CLASS_HID_5bb6b, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [148] = { - .class_hid = BNXT_ULP_CLASS_HID_30599, + .class_hid = BNXT_ULP_CLASS_HID_5c7d3, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [149] = { - .class_hid = BNXT_ULP_CLASS_HID_5741, + .class_hid = BNXT_ULP_CLASS_HID_59f8b, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [150] = { - .class_hid = BNXT_ULP_CLASS_HID_11075, + .class_hid = BNXT_ULP_CLASS_HID_5abf3, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [151] = { - .class_hid = BNXT_ULP_CLASS_HID_22675, + .class_hid = BNXT_ULP_CLASS_HID_5a5b7, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [152] = { - .class_hid = BNXT_ULP_CLASS_HID_33c75, + .class_hid = BNXT_ULP_CLASS_HID_5b23f, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [153] = { - .class_hid = BNXT_ULP_CLASS_HID_4d39, + .class_hid = BNXT_ULP_CLASS_HID_5d8b3, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [154] = { - .class_hid = BNXT_ULP_CLASS_HID_106ed, + .class_hid = BNXT_ULP_CLASS_HID_5886f, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [155] = { - .class_hid = BNXT_ULP_CLASS_HID_21ced, + .class_hid = BNXT_ULP_CLASS_HID_58223, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [156] = { - .class_hid = BNXT_ULP_CLASS_HID_332ed, + .class_hid = BNXT_ULP_CLASS_HID_58eab, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [157] = { - .class_hid = BNXT_ULP_CLASS_HID_174d, + .class_hid = BNXT_ULP_CLASS_HID_5c31f, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [158] = { - .class_hid = BNXT_ULP_CLASS_HID_12d4d, + .class_hid = BNXT_ULP_CLASS_HID_5cf87, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [159] = { - .class_hid = BNXT_ULP_CLASS_HID_2434d, + .class_hid = BNXT_ULP_CLASS_HID_5c95b, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [160] = { - .class_hid = BNXT_ULP_CLASS_HID_3594d, + .class_hid = BNXT_ULP_CLASS_HID_5d5c3, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [161] = { - .class_hid = BNXT_ULP_CLASS_HID_1a29, + .class_hid = BNXT_ULP_CLASS_HID_05f1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 4, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [162] = { - .class_hid = BNXT_ULP_CLASS_HID_13029, + .class_hid = BNXT_ULP_CLASS_HID_1209, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 31, + .hdr_sig_id = 4, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [163] = { - .class_hid = BNXT_ULP_CLASS_HID_24629, + .class_hid = BNXT_ULP_CLASS_HID_0bcd, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32, + .hdr_sig_id = 4, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [164] = { - .class_hid = BNXT_ULP_CLASS_HID_35c29, + .class_hid = BNXT_ULP_CLASS_HID_1845, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 33, + .hdr_sig_id = 4, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [165] = { - .class_hid = BNXT_ULP_CLASS_HID_5085, + .class_hid = BNXT_ULP_CLASS_HID_25e9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 34, + .hdr_sig_id = 4, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [166] = { - .class_hid = BNXT_ULP_CLASS_HID_10a49, + .class_hid = BNXT_ULP_CLASS_HID_3261, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 34, + .hdr_sig_id = 4, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [167] = { - .class_hid = BNXT_ULP_CLASS_HID_22049, + .class_hid = BNXT_ULP_CLASS_HID_2c25, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 34, + .hdr_sig_id = 4, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [168] = { - .class_hid = BNXT_ULP_CLASS_HID_33649, + .class_hid = BNXT_ULP_CLASS_HID_38bd, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 34, + .hdr_sig_id = 4, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [169] = { - .class_hid = BNXT_ULP_CLASS_HID_477d, + .class_hid = BNXT_ULP_CLASS_HID_3c1d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 34, + .hdr_sig_id = 4, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [170] = { - .class_hid = BNXT_ULP_CLASS_HID_10021, + .class_hid = BNXT_ULP_CLASS_HID_4895, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 34, + .hdr_sig_id = 4, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [171] = { - .class_hid = BNXT_ULP_CLASS_HID_21621, + .class_hid = BNXT_ULP_CLASS_HID_4259, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 35, + .hdr_sig_id = 4, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [172] = { - .class_hid = BNXT_ULP_CLASS_HID_32c21, + .class_hid = BNXT_ULP_CLASS_HID_4ed1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 36, + .hdr_sig_id = 4, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [173] = { - .class_hid = BNXT_ULP_CLASS_HID_1081, + .class_hid = BNXT_ULP_CLASS_HID_5c75, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [174] = { - .class_hid = BNXT_ULP_CLASS_HID_12681, + .class_hid = BNXT_ULP_CLASS_HID_0bc1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [175] = { - .class_hid = BNXT_ULP_CLASS_HID_23c81, + .class_hid = BNXT_ULP_CLASS_HID_0585, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [176] = { - .class_hid = BNXT_ULP_CLASS_HID_35281, + .class_hid = BNXT_ULP_CLASS_HID_121d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [177] = { - .class_hid = BNXT_ULP_CLASS_HID_146d, + .class_hid = BNXT_ULP_CLASS_HID_58c5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [178] = { - .class_hid = BNXT_ULP_CLASS_HID_12a6d, + .class_hid = BNXT_ULP_CLASS_HID_0891, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [179] = { - .class_hid = BNXT_ULP_CLASS_HID_2406d, + .class_hid = BNXT_ULP_CLASS_HID_0255, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [180] = { - .class_hid = BNXT_ULP_CLASS_HID_3566d, + .class_hid = BNXT_ULP_CLASS_HID_0eed, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [181] = { - .class_hid = BNXT_ULP_CLASS_HID_4ad9, + .class_hid = BNXT_ULP_CLASS_HID_1c71, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [182] = { - .class_hid = BNXT_ULP_CLASS_HID_1038d, + .class_hid = BNXT_ULP_CLASS_HID_2889, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [183] = { - .class_hid = BNXT_ULP_CLASS_HID_2198d, + .class_hid = BNXT_ULP_CLASS_HID_224d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [184] = { - .class_hid = BNXT_ULP_CLASS_HID_32f8d, + .class_hid = BNXT_ULP_CLASS_HID_2ec5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [185] = { - .class_hid = BNXT_ULP_CLASS_HID_40b1, + .class_hid = BNXT_ULP_CLASS_HID_32a5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [186] = { - .class_hid = BNXT_ULP_CLASS_HID_156b1, + .class_hid = BNXT_ULP_CLASS_HID_3f3d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [187] = { - .class_hid = BNXT_ULP_CLASS_HID_21065, + .class_hid = BNXT_ULP_CLASS_HID_38e1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [188] = { - .class_hid = BNXT_ULP_CLASS_HID_32665, + .class_hid = BNXT_ULP_CLASS_HID_4579, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [189] = { - .class_hid = BNXT_ULP_CLASS_HID_0ac5, + .class_hid = BNXT_ULP_CLASS_HID_529d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [190] = { - .class_hid = BNXT_ULP_CLASS_HID_120c5, + .class_hid = BNXT_ULP_CLASS_HID_0269, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [191] = { - .class_hid = BNXT_ULP_CLASS_HID_236c5, + .class_hid = BNXT_ULP_CLASS_HID_58d9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [192] = { - .class_hid = BNXT_ULP_CLASS_HID_34cc5, + .class_hid = BNXT_ULP_CLASS_HID_08a5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, + .hdr_sig_id = 4, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [193] = { - .class_hid = BNXT_ULP_CLASS_HID_0139, + .class_hid = BNXT_ULP_CLASS_HID_400c5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [194] = { - .class_hid = BNXT_ULP_CLASS_HID_11739, + .class_hid = BNXT_ULP_CLASS_HID_40d5d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 37, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20488, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [195] = { - .class_hid = BNXT_ULP_CLASS_HID_22d39, + .class_hid = BNXT_ULP_CLASS_HID_40701, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 38, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [196] = { - .class_hid = BNXT_ULP_CLASS_HID_34339, + .class_hid = BNXT_ULP_CLASS_HID_41399, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 39, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20488, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [197] = { - .class_hid = BNXT_ULP_CLASS_HID_3795, + .class_hid = BNXT_ULP_CLASS_HID_4213d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 40, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [198] = { - .class_hid = BNXT_ULP_CLASS_HID_14d95, + .class_hid = BNXT_ULP_CLASS_HID_42db5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 40, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20488, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [199] = { - .class_hid = BNXT_ULP_CLASS_HID_20759, + .class_hid = BNXT_ULP_CLASS_HID_42779, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 40, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [200] = { - .class_hid = BNXT_ULP_CLASS_HID_31d59, + .class_hid = BNXT_ULP_CLASS_HID_433f1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 40, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20488, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [201] = { - .class_hid = BNXT_ULP_CLASS_HID_2e0d, + .class_hid = BNXT_ULP_CLASS_HID_43751, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 40, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [202] = { - .class_hid = BNXT_ULP_CLASS_HID_1440d, + .class_hid = BNXT_ULP_CLASS_HID_443e9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 40, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22536, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [203] = { - .class_hid = BNXT_ULP_CLASS_HID_25a0d, + .class_hid = BNXT_ULP_CLASS_HID_43dad, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 41, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [204] = { - .class_hid = BNXT_ULP_CLASS_HID_31331, + .class_hid = BNXT_ULP_CLASS_HID_44a25, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 42, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22536, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [205] = { - .class_hid = BNXT_ULP_CLASS_HID_54ed, + .class_hid = BNXT_ULP_CLASS_HID_45749, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [206] = { - .class_hid = BNXT_ULP_CLASS_HID_10d91, + .class_hid = BNXT_ULP_CLASS_HID_40715, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22536, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [207] = { - .class_hid = BNXT_ULP_CLASS_HID_22391, + .class_hid = BNXT_ULP_CLASS_HID_400d9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [208] = { - .class_hid = BNXT_ULP_CLASS_HID_33991, + .class_hid = BNXT_ULP_CLASS_HID_40d51, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22536, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [209] = { - .class_hid = BNXT_ULP_CLASS_HID_5849, + .class_hid = BNXT_ULP_CLASS_HID_45419, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [210] = { - .class_hid = BNXT_ULP_CLASS_HID_1117d, + .class_hid = BNXT_ULP_CLASS_HID_403e5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [211] = { - .class_hid = BNXT_ULP_CLASS_HID_2277d, + .class_hid = BNXT_ULP_CLASS_HID_45a55, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [212] = { - .class_hid = BNXT_ULP_CLASS_HID_33d7d, + .class_hid = BNXT_ULP_CLASS_HID_40a21, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [213] = { - .class_hid = BNXT_ULP_CLASS_HID_31e9, + .class_hid = BNXT_ULP_CLASS_HID_41745, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [214] = { - .class_hid = BNXT_ULP_CLASS_HID_147e9, + .class_hid = BNXT_ULP_CLASS_HID_423dd, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [215] = { - .class_hid = BNXT_ULP_CLASS_HID_2009d, + .class_hid = BNXT_ULP_CLASS_HID_41d81, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [216] = { - .class_hid = BNXT_ULP_CLASS_HID_3169d, + .class_hid = BNXT_ULP_CLASS_HID_42a19, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [217] = { - .class_hid = BNXT_ULP_CLASS_HID_2841, + .class_hid = BNXT_ULP_CLASS_HID_42df9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [218] = { - .class_hid = BNXT_ULP_CLASS_HID_13e41, + .class_hid = BNXT_ULP_CLASS_HID_43a71, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30728, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [219] = { - .class_hid = BNXT_ULP_CLASS_HID_25441, + .class_hid = BNXT_ULP_CLASS_HID_43435, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [220] = { - .class_hid = BNXT_ULP_CLASS_HID_30d75, + .class_hid = BNXT_ULP_CLASS_HID_4404d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30728, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [221] = { - .class_hid = BNXT_ULP_CLASS_HID_4e21, + .class_hid = BNXT_ULP_CLASS_HID_44dd1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [222] = { - .class_hid = BNXT_ULP_CLASS_HID_107d5, + .class_hid = BNXT_ULP_CLASS_HID_45a69, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30728, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [223] = { - .class_hid = BNXT_ULP_CLASS_HID_21dd5, + .class_hid = BNXT_ULP_CLASS_HID_4542d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [224] = { - .class_hid = BNXT_ULP_CLASS_HID_333d5, + .class_hid = BNXT_ULP_CLASS_HID_403f9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30728, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [225] = { - .class_hid = BNXT_ULP_CLASS_HID_2521, + .class_hid = BNXT_ULP_CLASS_HID_4140d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [226] = { - .class_hid = BNXT_ULP_CLASS_HID_2bed, + .class_hid = BNXT_ULP_CLASS_HID_420b5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16392, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [227] = { - .class_hid = BNXT_ULP_CLASS_HID_050d, + .class_hid = BNXT_ULP_CLASS_HID_41a49, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [228] = { - .class_hid = BNXT_ULP_CLASS_HID_5b9d, + .class_hid = BNXT_ULP_CLASS_HID_426f1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 43, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16392, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [229] = { - .class_hid = BNXT_ULP_CLASS_HID_1865, + .class_hid = BNXT_ULP_CLASS_HID_44ab9, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 43, + .hdr_sig_id = 5, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [230] = { - .class_hid = BNXT_ULP_CLASS_HID_389d, + .class_hid = BNXT_ULP_CLASS_HID_45721, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 44, + .hdr_sig_id = 5, + .flow_sig_id = 16392, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [231] = { - .class_hid = BNXT_ULP_CLASS_HID_123d, + .class_hid = BNXT_ULP_CLASS_HID_450e5, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 44, + .hdr_sig_id = 5, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [232] = { - .class_hid = BNXT_ULP_CLASS_HID_4ef1, + .class_hid = BNXT_ULP_CLASS_HID_40051, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 45, + .hdr_sig_id = 5, + .flow_sig_id = 16392, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [233] = { - .class_hid = BNXT_ULP_CLASS_HID_1229, + .class_hid = BNXT_ULP_CLASS_HID_40aa5, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 45, + .hdr_sig_id = 5, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [234] = { - .class_hid = BNXT_ULP_CLASS_HID_3241, + .class_hid = BNXT_ULP_CLASS_HID_4172d, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 45, + .hdr_sig_id = 5, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [235] = { - .class_hid = BNXT_ULP_CLASS_HID_0be1, + .class_hid = BNXT_ULP_CLASS_HID_410e1, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 45, + .hdr_sig_id = 5, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [236] = { - .class_hid = BNXT_ULP_CLASS_HID_48b5, + .class_hid = BNXT_ULP_CLASS_HID_41d69, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 45, + .hdr_sig_id = 5, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [237] = { - .class_hid = BNXT_ULP_CLASS_HID_0bed, + .class_hid = BNXT_ULP_CLASS_HID_440d1, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 45, + .hdr_sig_id = 5, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [238] = { - .class_hid = BNXT_ULP_CLASS_HID_2c05, + .class_hid = BNXT_ULP_CLASS_HID_44d59, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 46, + .hdr_sig_id = 5, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [239] = { - .class_hid = BNXT_ULP_CLASS_HID_05a5, + .class_hid = BNXT_ULP_CLASS_HID_4471d, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 46, + .hdr_sig_id = 5, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [240] = { - .class_hid = BNXT_ULP_CLASS_HID_4279, + .class_hid = BNXT_ULP_CLASS_HID_45385, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 47, + .hdr_sig_id = 5, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [241] = { - .class_hid = BNXT_ULP_CLASS_HID_05d1, + .class_hid = BNXT_ULP_CLASS_HID_6400d, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 47, + .hdr_sig_id = 5, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [242] = { - .class_hid = BNXT_ULP_CLASS_HID_25c9, + .class_hid = BNXT_ULP_CLASS_HID_64cb5, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 47, + .hdr_sig_id = 5, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [243] = { - .class_hid = BNXT_ULP_CLASS_HID_5c55, + .class_hid = BNXT_ULP_CLASS_HID_64649, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 47, + .hdr_sig_id = 5, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [244] = { - .class_hid = BNXT_ULP_CLASS_HID_3c3d, + .class_hid = BNXT_ULP_CLASS_HID_652f1, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 47, + .hdr_sig_id = 5, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [245] = { - .class_hid = BNXT_ULP_CLASS_HID_4fc9, + .class_hid = BNXT_ULP_CLASS_HID_619ed, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 47, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [246] = { - .class_hid = BNXT_ULP_CLASS_HID_1335, + .class_hid = BNXT_ULP_CLASS_HID_62615, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 48, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 49160, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [247] = { - .class_hid = BNXT_ULP_CLASS_HID_4981, + .class_hid = BNXT_ULP_CLASS_HID_62029, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 48, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [248] = { - .class_hid = BNXT_ULP_CLASS_HID_2969, + .class_hid = BNXT_ULP_CLASS_HID_62c51, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 49160, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [249] = { - .class_hid = BNXT_ULP_CLASS_HID_498d, + .class_hid = BNXT_ULP_CLASS_HID_636a5, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [250] = { - .class_hid = BNXT_ULP_CLASS_HID_0cf9, + .class_hid = BNXT_ULP_CLASS_HID_6432d, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 57352, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [251] = { - .class_hid = BNXT_ULP_CLASS_HID_4345, + .class_hid = BNXT_ULP_CLASS_HID_63ce1, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [252] = { - .class_hid = BNXT_ULP_CLASS_HID_232d, + .class_hid = BNXT_ULP_CLASS_HID_64969, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 57352, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [253] = { - .class_hid = BNXT_ULP_CLASS_HID_2579, + .class_hid = BNXT_ULP_CLASS_HID_61005, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [254] = { - .class_hid = BNXT_ULP_CLASS_HID_2bb5, + .class_hid = BNXT_ULP_CLASS_HID_61c8d, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57352, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [255] = { - .class_hid = BNXT_ULP_CLASS_HID_4bad, + .class_hid = BNXT_ULP_CLASS_HID_61641, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [256] = { - .class_hid = BNXT_ULP_CLASS_HID_4591, + .class_hid = BNXT_ULP_CLASS_HID_622c9, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 49, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57352, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [257] = { - .class_hid = BNXT_ULP_CLASS_HID_1845, + .class_hid = BNXT_ULP_CLASS_HID_52a0d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 49, + .hdr_sig_id = 5, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [258] = { - .class_hid = BNXT_ULP_CLASS_HID_1399, + .class_hid = BNXT_ULP_CLASS_HID_536b5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 49, + .hdr_sig_id = 5, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [259] = { - .class_hid = BNXT_ULP_CLASS_HID_0eed, + .class_hid = BNXT_ULP_CLASS_HID_53049, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 50, + .hdr_sig_id = 5, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [260] = { - .class_hid = BNXT_ULP_CLASS_HID_0a21, + .class_hid = BNXT_ULP_CLASS_HID_53cf1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 51, + .hdr_sig_id = 5, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [261] = { - .class_hid = BNXT_ULP_CLASS_HID_38bd, + .class_hid = BNXT_ULP_CLASS_HID_503ed, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 52, + .hdr_sig_id = 5, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [262] = { - .class_hid = BNXT_ULP_CLASS_HID_33f1, + .class_hid = BNXT_ULP_CLASS_HID_51015, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 52, + .hdr_sig_id = 5, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [263] = { - .class_hid = BNXT_ULP_CLASS_HID_2ec5, + .class_hid = BNXT_ULP_CLASS_HID_50a29, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 52, + .hdr_sig_id = 5, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [264] = { - .class_hid = BNXT_ULP_CLASS_HID_2a19, + .class_hid = BNXT_ULP_CLASS_HID_51651, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 52, + .hdr_sig_id = 5, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [265] = { - .class_hid = BNXT_ULP_CLASS_HID_121d, + .class_hid = BNXT_ULP_CLASS_HID_520a5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 52, + .hdr_sig_id = 5, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [266] = { - .class_hid = BNXT_ULP_CLASS_HID_0d51, + .class_hid = BNXT_ULP_CLASS_HID_52d2d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 52, + .hdr_sig_id = 5, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [267] = { - .class_hid = BNXT_ULP_CLASS_HID_08a5, + .class_hid = BNXT_ULP_CLASS_HID_526e1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 53, + .hdr_sig_id = 5, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [268] = { - .class_hid = BNXT_ULP_CLASS_HID_03f9, + .class_hid = BNXT_ULP_CLASS_HID_53369, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 54, + .hdr_sig_id = 5, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [269] = { - .class_hid = BNXT_ULP_CLASS_HID_4ed1, + .class_hid = BNXT_ULP_CLASS_HID_556d1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [270] = { - .class_hid = BNXT_ULP_CLASS_HID_4a25, + .class_hid = BNXT_ULP_CLASS_HID_5068d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [271] = { - .class_hid = BNXT_ULP_CLASS_HID_4579, + .class_hid = BNXT_ULP_CLASS_HID_50041, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [272] = { - .class_hid = BNXT_ULP_CLASS_HID_404d, + .class_hid = BNXT_ULP_CLASS_HID_50cc9, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [273] = { - .class_hid = BNXT_ULP_CLASS_HID_1209, + .class_hid = BNXT_ULP_CLASS_HID_7560d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [274] = { - .class_hid = BNXT_ULP_CLASS_HID_0d5d, + .class_hid = BNXT_ULP_CLASS_HID_705f9, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [275] = { - .class_hid = BNXT_ULP_CLASS_HID_0891, + .class_hid = BNXT_ULP_CLASS_HID_75c49, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [276] = { - .class_hid = BNXT_ULP_CLASS_HID_03e5, + .class_hid = BNXT_ULP_CLASS_HID_70c25, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [277] = { - .class_hid = BNXT_ULP_CLASS_HID_3261, + .class_hid = BNXT_ULP_CLASS_HID_72fed, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [278] = { - .class_hid = BNXT_ULP_CLASS_HID_2db5, + .class_hid = BNXT_ULP_CLASS_HID_73c15, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [279] = { - .class_hid = BNXT_ULP_CLASS_HID_2889, + .class_hid = BNXT_ULP_CLASS_HID_73629, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [280] = { - .class_hid = BNXT_ULP_CLASS_HID_23dd, + .class_hid = BNXT_ULP_CLASS_HID_74251, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [281] = { - .class_hid = BNXT_ULP_CLASS_HID_0bc1, + .class_hid = BNXT_ULP_CLASS_HID_74ca5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [282] = { - .class_hid = BNXT_ULP_CLASS_HID_0715, + .class_hid = BNXT_ULP_CLASS_HID_7592d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [283] = { - .class_hid = BNXT_ULP_CLASS_HID_0269, + .class_hid = BNXT_ULP_CLASS_HID_752e1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [284] = { - .class_hid = BNXT_ULP_CLASS_HID_5a69, + .class_hid = BNXT_ULP_CLASS_HID_7025d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [285] = { - .class_hid = BNXT_ULP_CLASS_HID_4895, + .class_hid = BNXT_ULP_CLASS_HID_72605, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [286] = { - .class_hid = BNXT_ULP_CLASS_HID_43e9, + .class_hid = BNXT_ULP_CLASS_HID_7328d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [287] = { - .class_hid = BNXT_ULP_CLASS_HID_3f3d, + .class_hid = BNXT_ULP_CLASS_HID_72c41, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [288] = { - .class_hid = BNXT_ULP_CLASS_HID_3a71, + .class_hid = BNXT_ULP_CLASS_HID_738c9, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 5, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [289] = { - .class_hid = BNXT_ULP_CLASS_HID_0bcd, + .class_hid = BNXT_ULP_CLASS_HID_0591, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [290] = { - .class_hid = BNXT_ULP_CLASS_HID_0701, + .class_hid = BNXT_ULP_CLASS_HID_1269, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 55, + .hdr_sig_id = 6, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [291] = { - .class_hid = BNXT_ULP_CLASS_HID_0255, + .class_hid = BNXT_ULP_CLASS_HID_0bad, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 56, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [292] = { - .class_hid = BNXT_ULP_CLASS_HID_5a55, + .class_hid = BNXT_ULP_CLASS_HID_1825, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 57, + .hdr_sig_id = 6, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [293] = { - .class_hid = BNXT_ULP_CLASS_HID_2c25, + .class_hid = BNXT_ULP_CLASS_HID_2589, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 58, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [294] = { - .class_hid = BNXT_ULP_CLASS_HID_2779, + .class_hid = BNXT_ULP_CLASS_HID_3201, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 58, + .hdr_sig_id = 6, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [295] = { - .class_hid = BNXT_ULP_CLASS_HID_224d, + .class_hid = BNXT_ULP_CLASS_HID_2c45, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 58, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [296] = { - .class_hid = BNXT_ULP_CLASS_HID_1d81, + .class_hid = BNXT_ULP_CLASS_HID_38dd, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 58, + .hdr_sig_id = 6, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [297] = { - .class_hid = BNXT_ULP_CLASS_HID_0585, + .class_hid = BNXT_ULP_CLASS_HID_3c7d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 58, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [298] = { - .class_hid = BNXT_ULP_CLASS_HID_00d9, + .class_hid = BNXT_ULP_CLASS_HID_48f5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 58, + .hdr_sig_id = 6, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [299] = { - .class_hid = BNXT_ULP_CLASS_HID_58d9, + .class_hid = BNXT_ULP_CLASS_HID_4239, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 59, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [300] = { - .class_hid = BNXT_ULP_CLASS_HID_542d, + .class_hid = BNXT_ULP_CLASS_HID_4eb1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 60, + .hdr_sig_id = 6, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [301] = { - .class_hid = BNXT_ULP_CLASS_HID_4259, + .class_hid = BNXT_ULP_CLASS_HID_5c15, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [302] = { - .class_hid = BNXT_ULP_CLASS_HID_3dad, + .class_hid = BNXT_ULP_CLASS_HID_0ba1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [303] = { - .class_hid = BNXT_ULP_CLASS_HID_38e1, + .class_hid = BNXT_ULP_CLASS_HID_05e5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [304] = { - .class_hid = BNXT_ULP_CLASS_HID_3435, + .class_hid = BNXT_ULP_CLASS_HID_127d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [305] = { - .class_hid = BNXT_ULP_CLASS_HID_05f1, + .class_hid = BNXT_ULP_CLASS_HID_58a5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [306] = { - .class_hid = BNXT_ULP_CLASS_HID_00c5, + .class_hid = BNXT_ULP_CLASS_HID_08f1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [307] = { - .class_hid = BNXT_ULP_CLASS_HID_58c5, + .class_hid = BNXT_ULP_CLASS_HID_0235, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [308] = { - .class_hid = BNXT_ULP_CLASS_HID_5419, + .class_hid = BNXT_ULP_CLASS_HID_0e8d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [309] = { - .class_hid = BNXT_ULP_CLASS_HID_25e9, + .class_hid = BNXT_ULP_CLASS_HID_1c11, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [310] = { - .class_hid = BNXT_ULP_CLASS_HID_213d, + .class_hid = BNXT_ULP_CLASS_HID_28e9, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [311] = { - .class_hid = BNXT_ULP_CLASS_HID_1c71, + .class_hid = BNXT_ULP_CLASS_HID_222d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [312] = { - .class_hid = BNXT_ULP_CLASS_HID_1745, + .class_hid = BNXT_ULP_CLASS_HID_2ea5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [313] = { - .class_hid = BNXT_ULP_CLASS_HID_5c75, + .class_hid = BNXT_ULP_CLASS_HID_32c5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [314] = { - .class_hid = BNXT_ULP_CLASS_HID_5749, + .class_hid = BNXT_ULP_CLASS_HID_3f5d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [315] = { - .class_hid = BNXT_ULP_CLASS_HID_529d, + .class_hid = BNXT_ULP_CLASS_HID_3881, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [316] = { - .class_hid = BNXT_ULP_CLASS_HID_4dd1, + .class_hid = BNXT_ULP_CLASS_HID_4519, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [317] = { - .class_hid = BNXT_ULP_CLASS_HID_3c1d, + .class_hid = BNXT_ULP_CLASS_HID_52fd, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [318] = { - .class_hid = BNXT_ULP_CLASS_HID_3751, + .class_hid = BNXT_ULP_CLASS_HID_0209, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [319] = { - .class_hid = BNXT_ULP_CLASS_HID_32a5, + .class_hid = BNXT_ULP_CLASS_HID_58b9, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [320] = { - .class_hid = BNXT_ULP_CLASS_HID_2df9, + .class_hid = BNXT_ULP_CLASS_HID_08c5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, + .hdr_sig_id = 6, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [321] = { - .class_hid = BNXT_ULP_CLASS_HID_4fe9, + .class_hid = BNXT_ULP_CLASS_HID_400a5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [322] = { - .class_hid = BNXT_ULP_CLASS_HID_4b3d, + .class_hid = BNXT_ULP_CLASS_HID_40d3d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 61, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20488, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [323] = { - .class_hid = BNXT_ULP_CLASS_HID_4671, + .class_hid = BNXT_ULP_CLASS_HID_40761, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 62, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [324] = { - .class_hid = BNXT_ULP_CLASS_HID_4145, + .class_hid = BNXT_ULP_CLASS_HID_413f9, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 63, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20488, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [325] = { - .class_hid = BNXT_ULP_CLASS_HID_1315, + .class_hid = BNXT_ULP_CLASS_HID_4215d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 64, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [326] = { - .class_hid = BNXT_ULP_CLASS_HID_0e69, + .class_hid = BNXT_ULP_CLASS_HID_42dd5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 64, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20488, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [327] = { - .class_hid = BNXT_ULP_CLASS_HID_09bd, + .class_hid = BNXT_ULP_CLASS_HID_42719, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 64, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [328] = { - .class_hid = BNXT_ULP_CLASS_HID_04f1, + .class_hid = BNXT_ULP_CLASS_HID_43391, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 64, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20488, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [329] = { - .class_hid = BNXT_ULP_CLASS_HID_49a1, + .class_hid = BNXT_ULP_CLASS_HID_43731, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 64, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [330] = { - .class_hid = BNXT_ULP_CLASS_HID_44f5, + .class_hid = BNXT_ULP_CLASS_HID_44389, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 64, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22536, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [331] = { - .class_hid = BNXT_ULP_CLASS_HID_3fc9, + .class_hid = BNXT_ULP_CLASS_HID_43dcd, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 65, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [332] = { - .class_hid = BNXT_ULP_CLASS_HID_3b1d, + .class_hid = BNXT_ULP_CLASS_HID_44a45, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 66, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22536, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [333] = { - .class_hid = BNXT_ULP_CLASS_HID_2949, + .class_hid = BNXT_ULP_CLASS_HID_45729, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [334] = { - .class_hid = BNXT_ULP_CLASS_HID_249d, + .class_hid = BNXT_ULP_CLASS_HID_40775, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22536, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [335] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd1, + .class_hid = BNXT_ULP_CLASS_HID_400b9, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [336] = { - .class_hid = BNXT_ULP_CLASS_HID_1b25, + .class_hid = BNXT_ULP_CLASS_HID_40d31, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22536, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [337] = { - .class_hid = BNXT_ULP_CLASS_HID_49ad, + .class_hid = BNXT_ULP_CLASS_HID_45479, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [338] = { - .class_hid = BNXT_ULP_CLASS_HID_44e1, + .class_hid = BNXT_ULP_CLASS_HID_40385, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [339] = { - .class_hid = BNXT_ULP_CLASS_HID_4035, + .class_hid = BNXT_ULP_CLASS_HID_45a35, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [340] = { - .class_hid = BNXT_ULP_CLASS_HID_3b09, + .class_hid = BNXT_ULP_CLASS_HID_40a41, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [341] = { - .class_hid = BNXT_ULP_CLASS_HID_0cd9, + .class_hid = BNXT_ULP_CLASS_HID_41725, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [342] = { - .class_hid = BNXT_ULP_CLASS_HID_082d, + .class_hid = BNXT_ULP_CLASS_HID_423bd, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [343] = { - .class_hid = BNXT_ULP_CLASS_HID_0361, + .class_hid = BNXT_ULP_CLASS_HID_41de1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [344] = { - .class_hid = BNXT_ULP_CLASS_HID_5b61, + .class_hid = BNXT_ULP_CLASS_HID_42a79, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [345] = { - .class_hid = BNXT_ULP_CLASS_HID_4365, + .class_hid = BNXT_ULP_CLASS_HID_42d99, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [346] = { - .class_hid = BNXT_ULP_CLASS_HID_3eb9, + .class_hid = BNXT_ULP_CLASS_HID_43a11, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30728, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [347] = { - .class_hid = BNXT_ULP_CLASS_HID_398d, + .class_hid = BNXT_ULP_CLASS_HID_43455, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [348] = { - .class_hid = BNXT_ULP_CLASS_HID_34c1, + .class_hid = BNXT_ULP_CLASS_HID_4402d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30728, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [349] = { - .class_hid = BNXT_ULP_CLASS_HID_230d, + .class_hid = BNXT_ULP_CLASS_HID_44db1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [350] = { - .class_hid = BNXT_ULP_CLASS_HID_1e41, + .class_hid = BNXT_ULP_CLASS_HID_45a09, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30728, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [351] = { - .class_hid = BNXT_ULP_CLASS_HID_1995, + .class_hid = BNXT_ULP_CLASS_HID_4544d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [352] = { - .class_hid = BNXT_ULP_CLASS_HID_14e9, + .class_hid = BNXT_ULP_CLASS_HID_40399, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30728, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [353] = { - .class_hid = BNXT_ULP_CLASS_HID_2559, + .class_hid = BNXT_ULP_CLASS_HID_4146d, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [354] = { - .class_hid = BNXT_ULP_CLASS_HID_2b95, + .class_hid = BNXT_ULP_CLASS_HID_420d5, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 16392, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [355] = { - .class_hid = BNXT_ULP_CLASS_HID_4b8d, + .class_hid = BNXT_ULP_CLASS_HID_41a29, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [356] = { - .class_hid = BNXT_ULP_CLASS_HID_45b1, + .class_hid = BNXT_ULP_CLASS_HID_42691, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 67, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 16392, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [357] = { - .class_hid = BNXT_ULP_CLASS_HID_1825, + .class_hid = BNXT_ULP_CLASS_HID_44ad9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 67, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [358] = { - .class_hid = BNXT_ULP_CLASS_HID_13f9, + .class_hid = BNXT_ULP_CLASS_HID_45741, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 67, + .hdr_sig_id = 7, + .flow_sig_id = 16392, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [359] = { - .class_hid = BNXT_ULP_CLASS_HID_0e8d, + .class_hid = BNXT_ULP_CLASS_HID_45085, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 68, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, [360] = { - .class_hid = BNXT_ULP_CLASS_HID_0a41, + .class_hid = BNXT_ULP_CLASS_HID_40031, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 69, + .hdr_sig_id = 7, + .flow_sig_id = 16392, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [361] = { - .class_hid = BNXT_ULP_CLASS_HID_38dd, + .class_hid = BNXT_ULP_CLASS_HID_40ac5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 70, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [362] = { - .class_hid = BNXT_ULP_CLASS_HID_3391, + .class_hid = BNXT_ULP_CLASS_HID_4174d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 70, + .hdr_sig_id = 7, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [363] = { - .class_hid = BNXT_ULP_CLASS_HID_2ea5, + .class_hid = BNXT_ULP_CLASS_HID_41081, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 70, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [364] = { - .class_hid = BNXT_ULP_CLASS_HID_2a79, + .class_hid = BNXT_ULP_CLASS_HID_41d09, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 70, + .hdr_sig_id = 7, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [365] = { - .class_hid = BNXT_ULP_CLASS_HID_127d, + .class_hid = BNXT_ULP_CLASS_HID_440b1, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 70, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [366] = { - .class_hid = BNXT_ULP_CLASS_HID_0d31, + .class_hid = BNXT_ULP_CLASS_HID_44d39, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 70, + .hdr_sig_id = 7, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [367] = { - .class_hid = BNXT_ULP_CLASS_HID_08c5, + .class_hid = BNXT_ULP_CLASS_HID_4477d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 71, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [368] = { - .class_hid = BNXT_ULP_CLASS_HID_0399, + .class_hid = BNXT_ULP_CLASS_HID_453e5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 72, + .hdr_sig_id = 7, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [369] = { - .class_hid = BNXT_ULP_CLASS_HID_4eb1, + .class_hid = BNXT_ULP_CLASS_HID_6406d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [370] = { - .class_hid = BNXT_ULP_CLASS_HID_4a45, + .class_hid = BNXT_ULP_CLASS_HID_64cd5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [371] = { - .class_hid = BNXT_ULP_CLASS_HID_4519, + .class_hid = BNXT_ULP_CLASS_HID_64629, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [372] = { - .class_hid = BNXT_ULP_CLASS_HID_402d, + .class_hid = BNXT_ULP_CLASS_HID_65291, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [373] = { - .class_hid = BNXT_ULP_CLASS_HID_1269, + .class_hid = BNXT_ULP_CLASS_HID_6198d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [374] = { - .class_hid = BNXT_ULP_CLASS_HID_0d3d, + .class_hid = BNXT_ULP_CLASS_HID_62675, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [375] = { - .class_hid = BNXT_ULP_CLASS_HID_08f1, + .class_hid = BNXT_ULP_CLASS_HID_62049, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [376] = { - .class_hid = BNXT_ULP_CLASS_HID_0385, + .class_hid = BNXT_ULP_CLASS_HID_62c31, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [377] = { - .class_hid = BNXT_ULP_CLASS_HID_3201, + .class_hid = BNXT_ULP_CLASS_HID_636c5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [378] = { - .class_hid = BNXT_ULP_CLASS_HID_2dd5, + .class_hid = BNXT_ULP_CLASS_HID_6434d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 57352, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [379] = { - .class_hid = BNXT_ULP_CLASS_HID_28e9, + .class_hid = BNXT_ULP_CLASS_HID_63c81, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [380] = { - .class_hid = BNXT_ULP_CLASS_HID_23bd, + .class_hid = BNXT_ULP_CLASS_HID_64909, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 57352, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [381] = { - .class_hid = BNXT_ULP_CLASS_HID_0ba1, + .class_hid = BNXT_ULP_CLASS_HID_61065, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [382] = { - .class_hid = BNXT_ULP_CLASS_HID_0775, + .class_hid = BNXT_ULP_CLASS_HID_61ced, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 57352, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [383] = { - .class_hid = BNXT_ULP_CLASS_HID_0209, + .class_hid = BNXT_ULP_CLASS_HID_61621, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [384] = { - .class_hid = BNXT_ULP_CLASS_HID_5a09, + .class_hid = BNXT_ULP_CLASS_HID_622a9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 57352, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [385] = { - .class_hid = BNXT_ULP_CLASS_HID_48f5, + .class_hid = BNXT_ULP_CLASS_HID_52a6d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [386] = { - .class_hid = BNXT_ULP_CLASS_HID_4389, + .class_hid = BNXT_ULP_CLASS_HID_536d5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [387] = { - .class_hid = BNXT_ULP_CLASS_HID_3f5d, + .class_hid = BNXT_ULP_CLASS_HID_53029, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [388] = { - .class_hid = BNXT_ULP_CLASS_HID_3a11, + .class_hid = BNXT_ULP_CLASS_HID_53c91, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [389] = { - .class_hid = BNXT_ULP_CLASS_HID_0bad, + .class_hid = BNXT_ULP_CLASS_HID_5038d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [390] = { - .class_hid = BNXT_ULP_CLASS_HID_0761, + .class_hid = BNXT_ULP_CLASS_HID_51075, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 73, + .hdr_sig_id = 7, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [391] = { - .class_hid = BNXT_ULP_CLASS_HID_0235, + .class_hid = BNXT_ULP_CLASS_HID_50a49, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 74, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [392] = { - .class_hid = BNXT_ULP_CLASS_HID_5a35, + .class_hid = BNXT_ULP_CLASS_HID_51631, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 75, + .hdr_sig_id = 7, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [393] = { - .class_hid = BNXT_ULP_CLASS_HID_2c45, + .class_hid = BNXT_ULP_CLASS_HID_520c5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 76, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [394] = { - .class_hid = BNXT_ULP_CLASS_HID_2719, + .class_hid = BNXT_ULP_CLASS_HID_52d4d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 76, + .hdr_sig_id = 7, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [395] = { - .class_hid = BNXT_ULP_CLASS_HID_222d, + .class_hid = BNXT_ULP_CLASS_HID_52681, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 76, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [396] = { - .class_hid = BNXT_ULP_CLASS_HID_1de1, + .class_hid = BNXT_ULP_CLASS_HID_53309, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 76, + .hdr_sig_id = 7, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [397] = { - .class_hid = BNXT_ULP_CLASS_HID_05e5, + .class_hid = BNXT_ULP_CLASS_HID_556b1, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 76, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [398] = { - .class_hid = BNXT_ULP_CLASS_HID_00b9, + .class_hid = BNXT_ULP_CLASS_HID_506ed, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 76, + .hdr_sig_id = 7, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [399] = { - .class_hid = BNXT_ULP_CLASS_HID_58b9, + .class_hid = BNXT_ULP_CLASS_HID_50021, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 77, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [400] = { - .class_hid = BNXT_ULP_CLASS_HID_544d, + .class_hid = BNXT_ULP_CLASS_HID_50ca9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 78, + .hdr_sig_id = 7, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [401] = { - .class_hid = BNXT_ULP_CLASS_HID_4239, + .class_hid = BNXT_ULP_CLASS_HID_7566d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [402] = { - .class_hid = BNXT_ULP_CLASS_HID_3dcd, + .class_hid = BNXT_ULP_CLASS_HID_70599, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [403] = { - .class_hid = BNXT_ULP_CLASS_HID_3881, + .class_hid = BNXT_ULP_CLASS_HID_75c29, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [404] = { - .class_hid = BNXT_ULP_CLASS_HID_3455, + .class_hid = BNXT_ULP_CLASS_HID_70c45, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [405] = { - .class_hid = BNXT_ULP_CLASS_HID_0591, + .class_hid = BNXT_ULP_CLASS_HID_72f8d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [406] = { - .class_hid = BNXT_ULP_CLASS_HID_00a5, + .class_hid = BNXT_ULP_CLASS_HID_73c75, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [407] = { - .class_hid = BNXT_ULP_CLASS_HID_58a5, + .class_hid = BNXT_ULP_CLASS_HID_73649, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [408] = { - .class_hid = BNXT_ULP_CLASS_HID_5479, + .class_hid = BNXT_ULP_CLASS_HID_74231, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [409] = { - .class_hid = BNXT_ULP_CLASS_HID_2589, + .class_hid = BNXT_ULP_CLASS_HID_74cc5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [410] = { - .class_hid = BNXT_ULP_CLASS_HID_215d, + .class_hid = BNXT_ULP_CLASS_HID_7594d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [411] = { - .class_hid = BNXT_ULP_CLASS_HID_1c11, + .class_hid = BNXT_ULP_CLASS_HID_75281, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [412] = { - .class_hid = BNXT_ULP_CLASS_HID_1725, + .class_hid = BNXT_ULP_CLASS_HID_7023d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [413] = { - .class_hid = BNXT_ULP_CLASS_HID_5c15, + .class_hid = BNXT_ULP_CLASS_HID_72665, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [414] = { - .class_hid = BNXT_ULP_CLASS_HID_5729, + .class_hid = BNXT_ULP_CLASS_HID_732ed, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [415] = { - .class_hid = BNXT_ULP_CLASS_HID_52fd, + .class_hid = BNXT_ULP_CLASS_HID_72c21, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [416] = { - .class_hid = BNXT_ULP_CLASS_HID_4db1, + .class_hid = BNXT_ULP_CLASS_HID_738a9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 7, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [417] = { - .class_hid = BNXT_ULP_CLASS_HID_3c7d, + .class_hid = BNXT_ULP_CLASS_HID_244c3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [418] = { - .class_hid = BNXT_ULP_CLASS_HID_3731, + .class_hid = BNXT_ULP_CLASS_HID_2515b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 8, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [419] = { - .class_hid = BNXT_ULP_CLASS_HID_32c5, + .class_hid = BNXT_ULP_CLASS_HID_24b1f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [420] = { - .class_hid = BNXT_ULP_CLASS_HID_2d99, + .class_hid = BNXT_ULP_CLASS_HID_25797, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, + .hdr_sig_id = 8, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [421] = { - .class_hid = BNXT_ULP_CLASS_HID_4f89, + .class_hid = BNXT_ULP_CLASS_HID_22f7f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [422] = { - .class_hid = BNXT_ULP_CLASS_HID_4b5d, + .class_hid = BNXT_ULP_CLASS_HID_23bf7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 79, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [423] = { - .class_hid = BNXT_ULP_CLASS_HID_4611, + .class_hid = BNXT_ULP_CLASS_HID_235bb, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 80, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [424] = { - .class_hid = BNXT_ULP_CLASS_HID_4125, + .class_hid = BNXT_ULP_CLASS_HID_24233, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [425] = { - .class_hid = BNXT_ULP_CLASS_HID_1375, + .class_hid = BNXT_ULP_CLASS_HID_20b8b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 82, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [426] = { - .class_hid = BNXT_ULP_CLASS_HID_0e09, + .class_hid = BNXT_ULP_CLASS_HID_21803, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 82, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32776, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [427] = { - .class_hid = BNXT_ULP_CLASS_HID_09dd, + .class_hid = BNXT_ULP_CLASS_HID_211c7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 82, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [428] = { - .class_hid = BNXT_ULP_CLASS_HID_0491, + .class_hid = BNXT_ULP_CLASS_HID_21e5f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 82, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32776, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [429] = { - .class_hid = BNXT_ULP_CLASS_HID_49c1, + .class_hid = BNXT_ULP_CLASS_HID_252d3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 82, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [430] = { - .class_hid = BNXT_ULP_CLASS_HID_4495, + .class_hid = BNXT_ULP_CLASS_HID_202bf, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 82, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [431] = { - .class_hid = BNXT_ULP_CLASS_HID_3fa9, + .class_hid = BNXT_ULP_CLASS_HID_2592f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 83, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [432] = { - .class_hid = BNXT_ULP_CLASS_HID_3b7d, + .class_hid = BNXT_ULP_CLASS_HID_208fb, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 84, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [433] = { - .class_hid = BNXT_ULP_CLASS_HID_2929, + .class_hid = BNXT_ULP_CLASS_HID_231f3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [434] = { - .class_hid = BNXT_ULP_CLASS_HID_24fd, + .class_hid = BNXT_ULP_CLASS_HID_23e0b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32776, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [435] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb1, + .class_hid = BNXT_ULP_CLASS_HID_237cf, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [436] = { - .class_hid = BNXT_ULP_CLASS_HID_1b45, + .class_hid = BNXT_ULP_CLASS_HID_24447, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32776, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [437] = { - .class_hid = BNXT_ULP_CLASS_HID_49cd, + .class_hid = BNXT_ULP_CLASS_HID_21c2f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [438] = { - .class_hid = BNXT_ULP_CLASS_HID_4481, + .class_hid = BNXT_ULP_CLASS_HID_228a7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [439] = { - .class_hid = BNXT_ULP_CLASS_HID_4055, + .class_hid = BNXT_ULP_CLASS_HID_2226b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [440] = { - .class_hid = BNXT_ULP_CLASS_HID_3b69, + .class_hid = BNXT_ULP_CLASS_HID_22ee3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [441] = { - .class_hid = BNXT_ULP_CLASS_HID_0cb9, + .class_hid = BNXT_ULP_CLASS_HID_25567, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [442] = { - .class_hid = BNXT_ULP_CLASS_HID_084d, + .class_hid = BNXT_ULP_CLASS_HID_20533, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32776, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [443] = { - .class_hid = BNXT_ULP_CLASS_HID_0301, + .class_hid = BNXT_ULP_CLASS_HID_25ba3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [444] = { - .class_hid = BNXT_ULP_CLASS_HID_5b01, + .class_hid = BNXT_ULP_CLASS_HID_20b0f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32776, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [445] = { - .class_hid = BNXT_ULP_CLASS_HID_4305, + .class_hid = BNXT_ULP_CLASS_HID_23f83, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [446] = { - .class_hid = BNXT_ULP_CLASS_HID_3ed9, + .class_hid = BNXT_ULP_CLASS_HID_24c1b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [447] = { - .class_hid = BNXT_ULP_CLASS_HID_39ed, + .class_hid = BNXT_ULP_CLASS_HID_245df, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [448] = { - .class_hid = BNXT_ULP_CLASS_HID_34a1, + .class_hid = BNXT_ULP_CLASS_HID_25257, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [449] = { - .class_hid = BNXT_ULP_CLASS_HID_236d, + .class_hid = BNXT_ULP_CLASS_HID_64017, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [450] = { - .class_hid = BNXT_ULP_CLASS_HID_1e21, + .class_hid = BNXT_ULP_CLASS_HID_64caf, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 49160, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [451] = { - .class_hid = BNXT_ULP_CLASS_HID_19f5, + .class_hid = BNXT_ULP_CLASS_HID_64653, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [452] = { - .class_hid = BNXT_ULP_CLASS_HID_1489, + .class_hid = BNXT_ULP_CLASS_HID_652eb, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 49160, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [453] = { - .class_hid = BNXT_ULP_CLASS_HID_2539, + .class_hid = BNXT_ULP_CLASS_HID_62ab3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [454] = { - .class_hid = BNXT_ULP_CLASS_HID_2bf5, + .class_hid = BNXT_ULP_CLASS_HID_636cb, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 49224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [455] = { - .class_hid = BNXT_ULP_CLASS_HID_4bed, + .class_hid = BNXT_ULP_CLASS_HID_6308f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [456] = { - .class_hid = BNXT_ULP_CLASS_HID_45d1, + .class_hid = BNXT_ULP_CLASS_HID_63d07, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 85, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 49224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [457] = { - .class_hid = BNXT_ULP_CLASS_HID_b6af, + .class_hid = BNXT_ULP_CLASS_HID_606df, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [458] = { - .class_hid = BNXT_ULP_CLASS_HID_b1d3, + .class_hid = BNXT_ULP_CLASS_HID_61357, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [459] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7d3, + .class_hid = BNXT_ULP_CLASS_HID_60d1b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [460] = { - .class_hid = BNXT_ULP_CLASS_HID_1ccaf, + .class_hid = BNXT_ULP_CLASS_HID_61993, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [461] = { - .class_hid = BNXT_ULP_CLASS_HID_da33, + .class_hid = BNXT_ULP_CLASS_HID_64e27, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [462] = { - .class_hid = BNXT_ULP_CLASS_HID_d567, + .class_hid = BNXT_ULP_CLASS_HID_65abf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [463] = { - .class_hid = BNXT_ULP_CLASS_HID_18eab, + .class_hid = BNXT_ULP_CLASS_HID_65463, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [464] = { - .class_hid = BNXT_ULP_CLASS_HID_19367, + .class_hid = BNXT_ULP_CLASS_HID_603cf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [465] = { - .class_hid = BNXT_ULP_CLASS_HID_a10b, + .class_hid = BNXT_ULP_CLASS_HID_62cc7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 85, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [466] = { - .class_hid = BNXT_ULP_CLASS_HID_9c3f, + .class_hid = BNXT_ULP_CLASS_HID_6395f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 86, + .hdr_sig_id = 8, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [467] = { - .class_hid = BNXT_ULP_CLASS_HID_1b23f, + .class_hid = BNXT_ULP_CLASS_HID_63303, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 86, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [468] = { - .class_hid = BNXT_ULP_CLASS_HID_1b70b, + .class_hid = BNXT_ULP_CLASS_HID_63f9b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [469] = { - .class_hid = BNXT_ULP_CLASS_HID_c49f, + .class_hid = BNXT_ULP_CLASS_HID_61763, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [470] = { - .class_hid = BNXT_ULP_CLASS_HID_bfc3, + .class_hid = BNXT_ULP_CLASS_HID_623fb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [471] = { - .class_hid = BNXT_ULP_CLASS_HID_1d5c3, + .class_hid = BNXT_ULP_CLASS_HID_61dbf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [472] = { - .class_hid = BNXT_ULP_CLASS_HID_1da9f, + .class_hid = BNXT_ULP_CLASS_HID_62a37, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [473] = { - .class_hid = BNXT_ULP_CLASS_HID_b063, + .class_hid = BNXT_ULP_CLASS_HID_650bb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [474] = { - .class_hid = BNXT_ULP_CLASS_HID_ab97, + .class_hid = BNXT_ULP_CLASS_HID_60007, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [475] = { - .class_hid = BNXT_ULP_CLASS_HID_1c197, + .class_hid = BNXT_ULP_CLASS_HID_656f7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [476] = { - .class_hid = BNXT_ULP_CLASS_HID_1c663, + .class_hid = BNXT_ULP_CLASS_HID_60643, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [477] = { - .class_hid = BNXT_ULP_CLASS_HID_d3f7, + .class_hid = BNXT_ULP_CLASS_HID_63ad7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [478] = { - .class_hid = BNXT_ULP_CLASS_HID_cf3b, + .class_hid = BNXT_ULP_CLASS_HID_6476f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [479] = { - .class_hid = BNXT_ULP_CLASS_HID_1886f, + .class_hid = BNXT_ULP_CLASS_HID_64113, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [480] = { - .class_hid = BNXT_ULP_CLASS_HID_18d3b, + .class_hid = BNXT_ULP_CLASS_HID_64dab, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [481] = { - .class_hid = BNXT_ULP_CLASS_HID_9acf, + .class_hid = BNXT_ULP_CLASS_HID_35ac3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [482] = { - .class_hid = BNXT_ULP_CLASS_HID_95f3, + .class_hid = BNXT_ULP_CLASS_HID_30aaf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [483] = { - .class_hid = BNXT_ULP_CLASS_HID_1abf3, + .class_hid = BNXT_ULP_CLASS_HID_30453, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [484] = { - .class_hid = BNXT_ULP_CLASS_HID_1b0cf, + .class_hid = BNXT_ULP_CLASS_HID_310eb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [485] = { - .class_hid = BNXT_ULP_CLASS_HID_be53, + .class_hid = BNXT_ULP_CLASS_HID_3457f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [486] = { - .class_hid = BNXT_ULP_CLASS_HID_b987, + .class_hid = BNXT_ULP_CLASS_HID_351f7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [487] = { - .class_hid = BNXT_ULP_CLASS_HID_1cf87, + .class_hid = BNXT_ULP_CLASS_HID_34bbb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [488] = { - .class_hid = BNXT_ULP_CLASS_HID_1d453, + .class_hid = BNXT_ULP_CLASS_HID_35833, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [489] = { - .class_hid = BNXT_ULP_CLASS_HID_aa27, + .class_hid = BNXT_ULP_CLASS_HID_3218b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [490] = { - .class_hid = BNXT_ULP_CLASS_HID_a56b, + .class_hid = BNXT_ULP_CLASS_HID_32e03, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [491] = { - .class_hid = BNXT_ULP_CLASS_HID_1bb6b, + .class_hid = BNXT_ULP_CLASS_HID_327c7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [492] = { - .class_hid = BNXT_ULP_CLASS_HID_1c027, + .class_hid = BNXT_ULP_CLASS_HID_3345f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [493] = { - .class_hid = BNXT_ULP_CLASS_HID_cdcb, + .class_hid = BNXT_ULP_CLASS_HID_30c27, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [494] = { - .class_hid = BNXT_ULP_CLASS_HID_c8ff, + .class_hid = BNXT_ULP_CLASS_HID_318bf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [495] = { - .class_hid = BNXT_ULP_CLASS_HID_18223, + .class_hid = BNXT_ULP_CLASS_HID_31263, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [496] = { - .class_hid = BNXT_ULP_CLASS_HID_186ff, + .class_hid = BNXT_ULP_CLASS_HID_31efb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, [497] = { - .class_hid = BNXT_ULP_CLASS_HID_9483, + .class_hid = BNXT_ULP_CLASS_HID_347f3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 87, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [498] = { - .class_hid = BNXT_ULP_CLASS_HID_8fb7, + .class_hid = BNXT_ULP_CLASS_HID_3540b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 88, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [499] = { - .class_hid = BNXT_ULP_CLASS_HID_1a5b7, + .class_hid = BNXT_ULP_CLASS_HID_34dcf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 88, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [500] = { - .class_hid = BNXT_ULP_CLASS_HID_1aa83, + .class_hid = BNXT_ULP_CLASS_HID_35a47, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [501] = { - .class_hid = BNXT_ULP_CLASS_HID_b817, + .class_hid = BNXT_ULP_CLASS_HID_3322f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [502] = { - .class_hid = BNXT_ULP_CLASS_HID_b35b, + .class_hid = BNXT_ULP_CLASS_HID_33ea7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [503] = { - .class_hid = BNXT_ULP_CLASS_HID_1c95b, + .class_hid = BNXT_ULP_CLASS_HID_3386b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [504] = { - .class_hid = BNXT_ULP_CLASS_HID_1ce17, + .class_hid = BNXT_ULP_CLASS_HID_344e3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [505] = { - .class_hid = BNXT_ULP_CLASS_HID_a3fb, + .class_hid = BNXT_ULP_CLASS_HID_30ebb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [506] = { - .class_hid = BNXT_ULP_CLASS_HID_9f2f, + .class_hid = BNXT_ULP_CLASS_HID_31b33, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [507] = { - .class_hid = BNXT_ULP_CLASS_HID_1b52f, + .class_hid = BNXT_ULP_CLASS_HID_314f7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [508] = { - .class_hid = BNXT_ULP_CLASS_HID_1b9fb, + .class_hid = BNXT_ULP_CLASS_HID_3210f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [509] = { - .class_hid = BNXT_ULP_CLASS_HID_c78f, + .class_hid = BNXT_ULP_CLASS_HID_35583, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [510] = { - .class_hid = BNXT_ULP_CLASS_HID_c2b3, + .class_hid = BNXT_ULP_CLASS_HID_3056f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [511] = { - .class_hid = BNXT_ULP_CLASS_HID_1d8b3, + .class_hid = BNXT_ULP_CLASS_HID_35bdf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [512] = { - .class_hid = BNXT_ULP_CLASS_HID_180b3, + .class_hid = BNXT_ULP_CLASS_HID_30bab, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [513] = { - .class_hid = BNXT_ULP_CLASS_HID_8e47, + .class_hid = BNXT_ULP_CLASS_HID_75617, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [514] = { - .class_hid = BNXT_ULP_CLASS_HID_898b, + .class_hid = BNXT_ULP_CLASS_HID_705e3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [515] = { - .class_hid = BNXT_ULP_CLASS_HID_19f8b, + .class_hid = BNXT_ULP_CLASS_HID_75c53, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [516] = { - .class_hid = BNXT_ULP_CLASS_HID_1a447, + .class_hid = BNXT_ULP_CLASS_HID_70c3f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [517] = { - .class_hid = BNXT_ULP_CLASS_HID_b1eb, + .class_hid = BNXT_ULP_CLASS_HID_740b3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [518] = { - .class_hid = BNXT_ULP_CLASS_HID_ad1f, + .class_hid = BNXT_ULP_CLASS_HID_74ccb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [519] = { - .class_hid = BNXT_ULP_CLASS_HID_1c31f, + .class_hid = BNXT_ULP_CLASS_HID_7468f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [520] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7eb, + .class_hid = BNXT_ULP_CLASS_HID_75307, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, + .hdr_sig_id = 8, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [521] = { - .class_hid = BNXT_ULP_CLASS_HID_9137, + .class_hid = BNXT_ULP_CLASS_HID_71cdf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [522] = { - .class_hid = BNXT_ULP_CLASS_HID_8c7b, + .class_hid = BNXT_ULP_CLASS_HID_72957, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114696, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [523] = { - .class_hid = BNXT_ULP_CLASS_HID_1a27b, + .class_hid = BNXT_ULP_CLASS_HID_7231b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [524] = { - .class_hid = BNXT_ULP_CLASS_HID_1a737, + .class_hid = BNXT_ULP_CLASS_HID_72f93, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114696, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [525] = { - .class_hid = BNXT_ULP_CLASS_HID_b4db, + .class_hid = BNXT_ULP_CLASS_HID_7077b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [526] = { - .class_hid = BNXT_ULP_CLASS_HID_b00f, + .class_hid = BNXT_ULP_CLASS_HID_713f3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [527] = { - .class_hid = BNXT_ULP_CLASS_HID_1c60f, + .class_hid = BNXT_ULP_CLASS_HID_70db7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [528] = { - .class_hid = BNXT_ULP_CLASS_HID_1cadb, + .class_hid = BNXT_ULP_CLASS_HID_719cf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [529] = { - .class_hid = BNXT_ULP_CLASS_HID_8b0b, + .class_hid = BNXT_ULP_CLASS_HID_742c7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [530] = { - .class_hid = BNXT_ULP_CLASS_HID_863f, + .class_hid = BNXT_ULP_CLASS_HID_74f5f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114696, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [531] = { - .class_hid = BNXT_ULP_CLASS_HID_19c3f, + .class_hid = BNXT_ULP_CLASS_HID_74903, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [532] = { - .class_hid = BNXT_ULP_CLASS_HID_1a10b, + .class_hid = BNXT_ULP_CLASS_HID_7559b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114696, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [533] = { - .class_hid = BNXT_ULP_CLASS_HID_ae9f, + .class_hid = BNXT_ULP_CLASS_HID_72d63, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [534] = { - .class_hid = BNXT_ULP_CLASS_HID_a9c3, + .class_hid = BNXT_ULP_CLASS_HID_739fb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [535] = { - .class_hid = BNXT_ULP_CLASS_HID_1bfc3, + .class_hid = BNXT_ULP_CLASS_HID_733bf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [536] = { - .class_hid = BNXT_ULP_CLASS_HID_1c49f, + .class_hid = BNXT_ULP_CLASS_HID_74037, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [537] = { - .class_hid = BNXT_ULP_CLASS_HID_2563, + .class_hid = BNXT_ULP_CLASS_HID_7098f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [538] = { - .class_hid = BNXT_ULP_CLASS_HID_2baf, + .class_hid = BNXT_ULP_CLASS_HID_71607, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114696, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [539] = { - .class_hid = BNXT_ULP_CLASS_HID_26d3, + .class_hid = BNXT_ULP_CLASS_HID_70fcb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [540] = { - .class_hid = BNXT_ULP_CLASS_HID_4f33, + .class_hid = BNXT_ULP_CLASS_HID_71c43, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114696, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [541] = { - .class_hid = BNXT_ULP_CLASS_HID_4a67, + .class_hid = BNXT_ULP_CLASS_HID_750d7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [542] = { - .class_hid = BNXT_ULP_CLASS_HID_160b, + .class_hid = BNXT_ULP_CLASS_HID_700a3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 89, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [543] = { - .class_hid = BNXT_ULP_CLASS_HID_113f, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [543] = { + .class_hid = BNXT_ULP_CLASS_HID_75713, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [544] = { - .class_hid = BNXT_ULP_CLASS_HID_399f, + .class_hid = BNXT_ULP_CLASS_HID_706ff, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [545] = { - .class_hid = BNXT_ULP_CLASS_HID_34c3, + .class_hid = BNXT_ULP_CLASS_HID_2cfc3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [546] = { - .class_hid = BNXT_ULP_CLASS_HID_2097, + .class_hid = BNXT_ULP_CLASS_HID_2dc5b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 163848, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [547] = { - .class_hid = BNXT_ULP_CLASS_HID_48f7, + .class_hid = BNXT_ULP_CLASS_HID_2d61f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [548] = { - .class_hid = BNXT_ULP_CLASS_HID_443b, + .class_hid = BNXT_ULP_CLASS_HID_285eb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 163848, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [549] = { - .class_hid = BNXT_ULP_CLASS_HID_0fcf, + .class_hid = BNXT_ULP_CLASS_HID_2ba7f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [550] = { - .class_hid = BNXT_ULP_CLASS_HID_0af3, + .class_hid = BNXT_ULP_CLASS_HID_2c6f7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 163912, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [551] = { - .class_hid = BNXT_ULP_CLASS_HID_3353, + .class_hid = BNXT_ULP_CLASS_HID_2c0bb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [552] = { - .class_hid = BNXT_ULP_CLASS_HID_2e87, + .class_hid = BNXT_ULP_CLASS_HID_2cd33, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 90, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 163912, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [553] = { - .class_hid = BNXT_ULP_CLASS_HID_b68f, + .class_hid = BNXT_ULP_CLASS_HID_2968b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [554] = { - .class_hid = BNXT_ULP_CLASS_HID_b94f, + .class_hid = BNXT_ULP_CLASS_HID_2a303, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [555] = { - .class_hid = BNXT_ULP_CLASS_HID_fc0f, + .class_hid = BNXT_ULP_CLASS_HID_29cc7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [556] = { - .class_hid = BNXT_ULP_CLASS_HID_fecf, + .class_hid = BNXT_ULP_CLASS_HID_2a95f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [557] = { - .class_hid = BNXT_ULP_CLASS_HID_b1f3, + .class_hid = BNXT_ULP_CLASS_HID_28127, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [558] = { - .class_hid = BNXT_ULP_CLASS_HID_b4b3, + .class_hid = BNXT_ULP_CLASS_HID_28dbf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [559] = { - .class_hid = BNXT_ULP_CLASS_HID_f773, + .class_hid = BNXT_ULP_CLASS_HID_28763, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [560] = { - .class_hid = BNXT_ULP_CLASS_HID_fa33, + .class_hid = BNXT_ULP_CLASS_HID_293fb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [561] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7f3, + .class_hid = BNXT_ULP_CLASS_HID_2bcf3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [562] = { - .class_hid = BNXT_ULP_CLASS_HID_1eab3, + .class_hid = BNXT_ULP_CLASS_HID_2c90b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [563] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd73, + .class_hid = BNXT_ULP_CLASS_HID_2c2cf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [564] = { - .class_hid = BNXT_ULP_CLASS_HID_1f033, + .class_hid = BNXT_ULP_CLASS_HID_2cf47, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [565] = { - .class_hid = BNXT_ULP_CLASS_HID_1cc8f, + .class_hid = BNXT_ULP_CLASS_HID_2a72f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [566] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef4f, + .class_hid = BNXT_ULP_CLASS_HID_2b3a7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [567] = { - .class_hid = BNXT_ULP_CLASS_HID_1d20f, + .class_hid = BNXT_ULP_CLASS_HID_2ad6b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [568] = { - .class_hid = BNXT_ULP_CLASS_HID_1f4cf, + .class_hid = BNXT_ULP_CLASS_HID_2b9e3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [569] = { - .class_hid = BNXT_ULP_CLASS_HID_da13, + .class_hid = BNXT_ULP_CLASS_HID_283bb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [570] = { - .class_hid = BNXT_ULP_CLASS_HID_a007, + .class_hid = BNXT_ULP_CLASS_HID_29033, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [571] = { - .class_hid = BNXT_ULP_CLASS_HID_c2c7, + .class_hid = BNXT_ULP_CLASS_HID_289f7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [572] = { - .class_hid = BNXT_ULP_CLASS_HID_e587, + .class_hid = BNXT_ULP_CLASS_HID_2960f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [573] = { - .class_hid = BNXT_ULP_CLASS_HID_d547, + .class_hid = BNXT_ULP_CLASS_HID_2ca83, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [574] = { - .class_hid = BNXT_ULP_CLASS_HID_f807, + .class_hid = BNXT_ULP_CLASS_HID_2d71b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [575] = { - .class_hid = BNXT_ULP_CLASS_HID_dac7, + .class_hid = BNXT_ULP_CLASS_HID_2d0df, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [576] = { - .class_hid = BNXT_ULP_CLASS_HID_e0cb, + .class_hid = BNXT_ULP_CLASS_HID_280ab, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [577] = { - .class_hid = BNXT_ULP_CLASS_HID_18e8b, + .class_hid = BNXT_ULP_CLASS_HID_6cb17, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [578] = { - .class_hid = BNXT_ULP_CLASS_HID_1b14b, + .class_hid = BNXT_ULP_CLASS_HID_6d7af, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [579] = { - .class_hid = BNXT_ULP_CLASS_HID_1d40b, + .class_hid = BNXT_ULP_CLASS_HID_6d153, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [580] = { - .class_hid = BNXT_ULP_CLASS_HID_1f6cb, + .class_hid = BNXT_ULP_CLASS_HID_6813f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, [581] = { - .class_hid = BNXT_ULP_CLASS_HID_19347, + .class_hid = BNXT_ULP_CLASS_HID_6b5b3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [582] = { - .class_hid = BNXT_ULP_CLASS_HID_1b607, + .class_hid = BNXT_ULP_CLASS_HID_6c1cb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [583] = { - .class_hid = BNXT_ULP_CLASS_HID_1d8c7, + .class_hid = BNXT_ULP_CLASS_HID_6bb8f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [584] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb87, + .class_hid = BNXT_ULP_CLASS_HID_6c807, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [585] = { - .class_hid = BNXT_ULP_CLASS_HID_a12b, + .class_hid = BNXT_ULP_CLASS_HID_691df, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [586] = { - .class_hid = BNXT_ULP_CLASS_HID_a3eb, + .class_hid = BNXT_ULP_CLASS_HID_69e57, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [587] = { - .class_hid = BNXT_ULP_CLASS_HID_e6ab, + .class_hid = BNXT_ULP_CLASS_HID_6981b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 91, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [588] = { - .class_hid = BNXT_ULP_CLASS_HID_e96b, + .class_hid = BNXT_ULP_CLASS_HID_6a493, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 92, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [589] = { - .class_hid = BNXT_ULP_CLASS_HID_9c1f, + .class_hid = BNXT_ULP_CLASS_HID_6d927, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 93, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [590] = { - .class_hid = BNXT_ULP_CLASS_HID_bedf, + .class_hid = BNXT_ULP_CLASS_HID_688f3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 93, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [591] = { - .class_hid = BNXT_ULP_CLASS_HID_e19f, + .class_hid = BNXT_ULP_CLASS_HID_682b7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 93, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [592] = { - .class_hid = BNXT_ULP_CLASS_HID_e45f, + .class_hid = BNXT_ULP_CLASS_HID_68ecf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 93, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [593] = { - .class_hid = BNXT_ULP_CLASS_HID_1b21f, + .class_hid = BNXT_ULP_CLASS_HID_6b7c7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 93, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [594] = { - .class_hid = BNXT_ULP_CLASS_HID_1b4df, + .class_hid = BNXT_ULP_CLASS_HID_6c45f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 93, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [595] = { - .class_hid = BNXT_ULP_CLASS_HID_1f79f, + .class_hid = BNXT_ULP_CLASS_HID_6be03, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 94, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [596] = { - .class_hid = BNXT_ULP_CLASS_HID_1fa5f, + .class_hid = BNXT_ULP_CLASS_HID_6ca9b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 95, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [597] = { - .class_hid = BNXT_ULP_CLASS_HID_1b72b, + .class_hid = BNXT_ULP_CLASS_HID_6a263, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [598] = { - .class_hid = BNXT_ULP_CLASS_HID_1b9eb, + .class_hid = BNXT_ULP_CLASS_HID_6aefb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [599] = { - .class_hid = BNXT_ULP_CLASS_HID_1fcab, + .class_hid = BNXT_ULP_CLASS_HID_6a8bf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [600] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff6b, + .class_hid = BNXT_ULP_CLASS_HID_6b537, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [601] = { - .class_hid = BNXT_ULP_CLASS_HID_c4bf, + .class_hid = BNXT_ULP_CLASS_HID_6dbbb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [602] = { - .class_hid = BNXT_ULP_CLASS_HID_e77f, + .class_hid = BNXT_ULP_CLASS_HID_68b07, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [603] = { - .class_hid = BNXT_ULP_CLASS_HID_ca3f, + .class_hid = BNXT_ULP_CLASS_HID_684cb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [604] = { - .class_hid = BNXT_ULP_CLASS_HID_ecff, + .class_hid = BNXT_ULP_CLASS_HID_69143, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [605] = { - .class_hid = BNXT_ULP_CLASS_HID_bfe3, + .class_hid = BNXT_ULP_CLASS_HID_6c5d7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [606] = { - .class_hid = BNXT_ULP_CLASS_HID_e2a3, + .class_hid = BNXT_ULP_CLASS_HID_6d26f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [607] = { - .class_hid = BNXT_ULP_CLASS_HID_c563, + .class_hid = BNXT_ULP_CLASS_HID_6cc13, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [608] = { - .class_hid = BNXT_ULP_CLASS_HID_e823, + .class_hid = BNXT_ULP_CLASS_HID_6d8ab, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [609] = { - .class_hid = BNXT_ULP_CLASS_HID_1d5e3, + .class_hid = BNXT_ULP_CLASS_HID_38917, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [610] = { - .class_hid = BNXT_ULP_CLASS_HID_1f8a3, + .class_hid = BNXT_ULP_CLASS_HID_395af, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [611] = { - .class_hid = BNXT_ULP_CLASS_HID_1db63, + .class_hid = BNXT_ULP_CLASS_HID_38f53, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [612] = { - .class_hid = BNXT_ULP_CLASS_HID_1e117, + .class_hid = BNXT_ULP_CLASS_HID_39beb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [613] = { - .class_hid = BNXT_ULP_CLASS_HID_1dabf, + .class_hid = BNXT_ULP_CLASS_HID_3d07f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [614] = { - .class_hid = BNXT_ULP_CLASS_HID_1a0a3, + .class_hid = BNXT_ULP_CLASS_HID_3dcf7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [615] = { - .class_hid = BNXT_ULP_CLASS_HID_1c363, + .class_hid = BNXT_ULP_CLASS_HID_3d6bb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [616] = { - .class_hid = BNXT_ULP_CLASS_HID_1e623, + .class_hid = BNXT_ULP_CLASS_HID_38607, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [617] = { - .class_hid = BNXT_ULP_CLASS_HID_b043, + .class_hid = BNXT_ULP_CLASS_HID_3ac8b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [618] = { - .class_hid = BNXT_ULP_CLASS_HID_b303, + .class_hid = BNXT_ULP_CLASS_HID_3b903, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [619] = { - .class_hid = BNXT_ULP_CLASS_HID_f5c3, + .class_hid = BNXT_ULP_CLASS_HID_3b2c7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [620] = { - .class_hid = BNXT_ULP_CLASS_HID_f883, + .class_hid = BNXT_ULP_CLASS_HID_3bf5f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [621] = { - .class_hid = BNXT_ULP_CLASS_HID_abb7, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [621] = { + .class_hid = BNXT_ULP_CLASS_HID_39727, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [622] = { - .class_hid = BNXT_ULP_CLASS_HID_ae77, + .class_hid = BNXT_ULP_CLASS_HID_3a3bf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [623] = { - .class_hid = BNXT_ULP_CLASS_HID_f137, + .class_hid = BNXT_ULP_CLASS_HID_39d63, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [624] = { - .class_hid = BNXT_ULP_CLASS_HID_f3f7, + .class_hid = BNXT_ULP_CLASS_HID_3a9fb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [625] = { - .class_hid = BNXT_ULP_CLASS_HID_1c1b7, + .class_hid = BNXT_ULP_CLASS_HID_3d2f3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [626] = { - .class_hid = BNXT_ULP_CLASS_HID_1e477, + .class_hid = BNXT_ULP_CLASS_HID_3825f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [627] = { - .class_hid = BNXT_ULP_CLASS_HID_1c737, + .class_hid = BNXT_ULP_CLASS_HID_3d8cf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [628] = { - .class_hid = BNXT_ULP_CLASS_HID_1e9f7, + .class_hid = BNXT_ULP_CLASS_HID_3889b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [629] = { - .class_hid = BNXT_ULP_CLASS_HID_1c643, + .class_hid = BNXT_ULP_CLASS_HID_3bd2f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [630] = { - .class_hid = BNXT_ULP_CLASS_HID_1e903, + .class_hid = BNXT_ULP_CLASS_HID_3c9a7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [631] = { - .class_hid = BNXT_ULP_CLASS_HID_1cbc3, + .class_hid = BNXT_ULP_CLASS_HID_3c36b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [632] = { - .class_hid = BNXT_ULP_CLASS_HID_1ee83, + .class_hid = BNXT_ULP_CLASS_HID_3cfe3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [633] = { - .class_hid = BNXT_ULP_CLASS_HID_d3d7, + .class_hid = BNXT_ULP_CLASS_HID_399bb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [634] = { - .class_hid = BNXT_ULP_CLASS_HID_f697, + .class_hid = BNXT_ULP_CLASS_HID_3a633, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [635] = { - .class_hid = BNXT_ULP_CLASS_HID_d957, + .class_hid = BNXT_ULP_CLASS_HID_39ff7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [636] = { - .class_hid = BNXT_ULP_CLASS_HID_fc17, + .class_hid = BNXT_ULP_CLASS_HID_3ac0f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [637] = { - .class_hid = BNXT_ULP_CLASS_HID_cf1b, + .class_hid = BNXT_ULP_CLASS_HID_383d7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [638] = { - .class_hid = BNXT_ULP_CLASS_HID_f1db, + .class_hid = BNXT_ULP_CLASS_HID_3906f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [639] = { - .class_hid = BNXT_ULP_CLASS_HID_d49b, + .class_hid = BNXT_ULP_CLASS_HID_38a13, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [640] = { - .class_hid = BNXT_ULP_CLASS_HID_f75b, + .class_hid = BNXT_ULP_CLASS_HID_396ab, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [641] = { - .class_hid = BNXT_ULP_CLASS_HID_1884f, + .class_hid = BNXT_ULP_CLASS_HID_7846b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [642] = { - .class_hid = BNXT_ULP_CLASS_HID_1ab0f, + .class_hid = BNXT_ULP_CLASS_HID_790e3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [643] = { - .class_hid = BNXT_ULP_CLASS_HID_1cdcf, + .class_hid = BNXT_ULP_CLASS_HID_78aa7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [644] = { - .class_hid = BNXT_ULP_CLASS_HID_1f08f, + .class_hid = BNXT_ULP_CLASS_HID_7973f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [645] = { - .class_hid = BNXT_ULP_CLASS_HID_18d1b, + .class_hid = BNXT_ULP_CLASS_HID_7cbb3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [646] = { - .class_hid = BNXT_ULP_CLASS_HID_1afdb, + .class_hid = BNXT_ULP_CLASS_HID_7d7cb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [647] = { - .class_hid = BNXT_ULP_CLASS_HID_1d29b, + .class_hid = BNXT_ULP_CLASS_HID_7d18f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [648] = { - .class_hid = BNXT_ULP_CLASS_HID_1f55b, + .class_hid = BNXT_ULP_CLASS_HID_7815b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [649] = { - .class_hid = BNXT_ULP_CLASS_HID_9aef, + .class_hid = BNXT_ULP_CLASS_HID_7a7df, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [650] = { - .class_hid = BNXT_ULP_CLASS_HID_bdaf, + .class_hid = BNXT_ULP_CLASS_HID_7b457, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [651] = { - .class_hid = BNXT_ULP_CLASS_HID_e06f, + .class_hid = BNXT_ULP_CLASS_HID_7ae1b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [652] = { - .class_hid = BNXT_ULP_CLASS_HID_e32f, + .class_hid = BNXT_ULP_CLASS_HID_7ba93, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [653] = { - .class_hid = BNXT_ULP_CLASS_HID_95d3, + .class_hid = BNXT_ULP_CLASS_HID_7927b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [654] = { - .class_hid = BNXT_ULP_CLASS_HID_b893, + .class_hid = BNXT_ULP_CLASS_HID_79ef3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [655] = { - .class_hid = BNXT_ULP_CLASS_HID_db53, + .class_hid = BNXT_ULP_CLASS_HID_798b7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [656] = { - .class_hid = BNXT_ULP_CLASS_HID_fe13, + .class_hid = BNXT_ULP_CLASS_HID_7a4cf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [657] = { - .class_hid = BNXT_ULP_CLASS_HID_1abd3, + .class_hid = BNXT_ULP_CLASS_HID_7cdc7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [658] = { - .class_hid = BNXT_ULP_CLASS_HID_1ae93, + .class_hid = BNXT_ULP_CLASS_HID_7da5f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [659] = { - .class_hid = BNXT_ULP_CLASS_HID_1f153, + .class_hid = BNXT_ULP_CLASS_HID_7d403, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [660] = { - .class_hid = BNXT_ULP_CLASS_HID_1f413, + .class_hid = BNXT_ULP_CLASS_HID_783ef, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [661] = { - .class_hid = BNXT_ULP_CLASS_HID_1b0ef, + .class_hid = BNXT_ULP_CLASS_HID_7b863, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [662] = { - .class_hid = BNXT_ULP_CLASS_HID_1b3af, + .class_hid = BNXT_ULP_CLASS_HID_7c4fb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [663] = { - .class_hid = BNXT_ULP_CLASS_HID_1f66f, + .class_hid = BNXT_ULP_CLASS_HID_7bebf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [664] = { - .class_hid = BNXT_ULP_CLASS_HID_1f92f, + .class_hid = BNXT_ULP_CLASS_HID_7cb37, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [665] = { - .class_hid = BNXT_ULP_CLASS_HID_be73, + .class_hid = BNXT_ULP_CLASS_HID_7948f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [666] = { - .class_hid = BNXT_ULP_CLASS_HID_e133, + .class_hid = BNXT_ULP_CLASS_HID_7a107, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [667] = { - .class_hid = BNXT_ULP_CLASS_HID_c3f3, + .class_hid = BNXT_ULP_CLASS_HID_79acb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [668] = { - .class_hid = BNXT_ULP_CLASS_HID_e6b3, + .class_hid = BNXT_ULP_CLASS_HID_7a743, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [669] = { - .class_hid = BNXT_ULP_CLASS_HID_b9a7, + .class_hid = BNXT_ULP_CLASS_HID_7dbd7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [670] = { - .class_hid = BNXT_ULP_CLASS_HID_bc67, + .class_hid = BNXT_ULP_CLASS_HID_78ba3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [671] = { - .class_hid = BNXT_ULP_CLASS_HID_ff27, + .class_hid = BNXT_ULP_CLASS_HID_78567, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [672] = { - .class_hid = BNXT_ULP_CLASS_HID_e1e7, + .class_hid = BNXT_ULP_CLASS_HID_791ff, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [673] = { - .class_hid = BNXT_ULP_CLASS_HID_1cfa7, + .class_hid = BNXT_ULP_CLASS_HID_a3db, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16661,20 +17813,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [674] = { - .class_hid = BNXT_ULP_CLASS_HID_1f267, + .class_hid = BNXT_ULP_CLASS_HID_b043, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16683,21 +17830,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [675] = { - .class_hid = BNXT_ULP_CLASS_HID_1d527, + .class_hid = BNXT_ULP_CLASS_HID_aa07, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16706,21 +17848,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [676] = { - .class_hid = BNXT_ULP_CLASS_HID_1f7e7, + .class_hid = BNXT_ULP_CLASS_HID_b68f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16729,22 +17866,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [677] = { - .class_hid = BNXT_ULP_CLASS_HID_1d473, + .class_hid = BNXT_ULP_CLASS_HID_8e67, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16753,19 +17885,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [678] = { - .class_hid = BNXT_ULP_CLASS_HID_1f733, + .class_hid = BNXT_ULP_CLASS_HID_9aef, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16774,20 +17903,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [679] = { - .class_hid = BNXT_ULP_CLASS_HID_1d9f3, + .class_hid = BNXT_ULP_CLASS_HID_94a3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16796,20 +17922,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [680] = { - .class_hid = BNXT_ULP_CLASS_HID_1fcb3, + .class_hid = BNXT_ULP_CLASS_HID_a12b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16818,21 +17941,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [681] = { - .class_hid = BNXT_ULP_CLASS_HID_aa07, + .class_hid = BNXT_ULP_CLASS_HID_c7af, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16841,16 +17961,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [682] = { - .class_hid = BNXT_ULP_CLASS_HID_acc7, + .class_hid = BNXT_ULP_CLASS_HID_d3d7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16859,17 +17979,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [683] = { - .class_hid = BNXT_ULP_CLASS_HID_ef87, + .class_hid = BNXT_ULP_CLASS_HID_cdeb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16878,17 +17998,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [684] = { - .class_hid = BNXT_ULP_CLASS_HID_f247, + .class_hid = BNXT_ULP_CLASS_HID_da13, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16897,18 +18017,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [685] = { - .class_hid = BNXT_ULP_CLASS_HID_a54b, + .class_hid = BNXT_ULP_CLASS_HID_b1cb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16917,17 +18037,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [686] = { - .class_hid = BNXT_ULP_CLASS_HID_a80b, + .class_hid = BNXT_ULP_CLASS_HID_be73, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16936,18 +18056,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [687] = { - .class_hid = BNXT_ULP_CLASS_HID_eacb, + .class_hid = BNXT_ULP_CLASS_HID_b837, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16956,18 +18076,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [688] = { - .class_hid = BNXT_ULP_CLASS_HID_ed8b, + .class_hid = BNXT_ULP_CLASS_HID_c4bf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16976,19 +18096,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [689] = { - .class_hid = BNXT_ULP_CLASS_HID_1bb4b, + .class_hid = BNXT_ULP_CLASS_HID_49f0f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -16997,18 +18117,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [690] = { - .class_hid = BNXT_ULP_CLASS_HID_1be0b, + .class_hid = BNXT_ULP_CLASS_HID_4abb7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17017,19 +18135,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [691] = { - .class_hid = BNXT_ULP_CLASS_HID_1c0cb, + .class_hid = BNXT_ULP_CLASS_HID_4a54b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17038,19 +18154,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [692] = { - .class_hid = BNXT_ULP_CLASS_HID_1e38b, + .class_hid = BNXT_ULP_CLASS_HID_4b1f3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17059,20 +18173,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [693] = { - .class_hid = BNXT_ULP_CLASS_HID_1c007, + .class_hid = BNXT_ULP_CLASS_HID_489ab, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17081,17 +18193,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [694] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2c7, + .class_hid = BNXT_ULP_CLASS_HID_495d3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17100,18 +18212,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [695] = { - .class_hid = BNXT_ULP_CLASS_HID_1c587, + .class_hid = BNXT_ULP_CLASS_HID_48f97, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17120,18 +18232,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [696] = { - .class_hid = BNXT_ULP_CLASS_HID_1e847, + .class_hid = BNXT_ULP_CLASS_HID_49c1f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17140,19 +18252,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [697] = { - .class_hid = BNXT_ULP_CLASS_HID_cdeb, + .class_hid = BNXT_ULP_CLASS_HID_4c293, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17161,17 +18273,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [698] = { - .class_hid = BNXT_ULP_CLASS_HID_f0ab, + .class_hid = BNXT_ULP_CLASS_HID_4cf1b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17180,18 +18292,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [699] = { - .class_hid = BNXT_ULP_CLASS_HID_d36b, + .class_hid = BNXT_ULP_CLASS_HID_4c8df, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17200,18 +18312,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [700] = { - .class_hid = BNXT_ULP_CLASS_HID_f62b, + .class_hid = BNXT_ULP_CLASS_HID_4d547, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17220,19 +18332,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [701] = { - .class_hid = BNXT_ULP_CLASS_HID_c8df, + .class_hid = BNXT_ULP_CLASS_HID_4ad3f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17241,18 +18353,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [702] = { - .class_hid = BNXT_ULP_CLASS_HID_eb9f, + .class_hid = BNXT_ULP_CLASS_HID_4b9a7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17261,19 +18373,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [703] = { - .class_hid = BNXT_ULP_CLASS_HID_ce5f, + .class_hid = BNXT_ULP_CLASS_HID_4b37b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17282,19 +18394,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [704] = { - .class_hid = BNXT_ULP_CLASS_HID_f11f, + .class_hid = BNXT_ULP_CLASS_HID_4bfe3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17303,20 +18415,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [705] = { - .class_hid = BNXT_ULP_CLASS_HID_18203, + .class_hid = BNXT_ULP_CLASS_HID_1b9db, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17325,19 +18437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [706] = { - .class_hid = BNXT_ULP_CLASS_HID_1a4c3, + .class_hid = BNXT_ULP_CLASS_HID_1c643, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17346,20 +18455,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [707] = { - .class_hid = BNXT_ULP_CLASS_HID_1c783, + .class_hid = BNXT_ULP_CLASS_HID_1c007, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17368,20 +18474,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [708] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea43, + .class_hid = BNXT_ULP_CLASS_HID_1cc8f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17390,21 +18493,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [709] = { - .class_hid = BNXT_ULP_CLASS_HID_186df, + .class_hid = BNXT_ULP_CLASS_HID_1a467, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17413,18 +18513,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [710] = { - .class_hid = BNXT_ULP_CLASS_HID_1a99f, + .class_hid = BNXT_ULP_CLASS_HID_1b0ef, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17433,19 +18532,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [711] = { - .class_hid = BNXT_ULP_CLASS_HID_1cc5f, + .class_hid = BNXT_ULP_CLASS_HID_1aaa3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17454,19 +18552,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [712] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef1f, + .class_hid = BNXT_ULP_CLASS_HID_1b72b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17475,20 +18572,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [713] = { - .class_hid = BNXT_ULP_CLASS_HID_94a3, + .class_hid = BNXT_ULP_CLASS_HID_18093, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17497,17 +18593,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [714] = { - .class_hid = BNXT_ULP_CLASS_HID_b763, + .class_hid = BNXT_ULP_CLASS_HID_18d1b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 96, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17516,18 +18612,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [715] = { - .class_hid = BNXT_ULP_CLASS_HID_da23, + .class_hid = BNXT_ULP_CLASS_HID_186df, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 97, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17536,18 +18632,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [716] = { - .class_hid = BNXT_ULP_CLASS_HID_fce3, + .class_hid = BNXT_ULP_CLASS_HID_19347, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 98, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17556,19 +18652,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [717] = { - .class_hid = BNXT_ULP_CLASS_HID_8f97, + .class_hid = BNXT_ULP_CLASS_HID_1c7cb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 99, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17577,18 +18673,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [718] = { - .class_hid = BNXT_ULP_CLASS_HID_b257, + .class_hid = BNXT_ULP_CLASS_HID_1d473, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 99, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17597,19 +18693,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [719] = { - .class_hid = BNXT_ULP_CLASS_HID_d517, + .class_hid = BNXT_ULP_CLASS_HID_1ce37, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 99, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17618,19 +18714,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [720] = { - .class_hid = BNXT_ULP_CLASS_HID_f7d7, + .class_hid = BNXT_ULP_CLASS_HID_1dabf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 99, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17639,20 +18735,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [721] = { - .class_hid = BNXT_ULP_CLASS_HID_1a597, + .class_hid = BNXT_ULP_CLASS_HID_5b50f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 99, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17661,19 +18757,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [722] = { - .class_hid = BNXT_ULP_CLASS_HID_1a857, + .class_hid = BNXT_ULP_CLASS_HID_5c1b7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 99, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17682,20 +18776,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [723] = { - .class_hid = BNXT_ULP_CLASS_HID_1eb17, + .class_hid = BNXT_ULP_CLASS_HID_5bb4b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 100, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17704,20 +18796,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [724] = { - .class_hid = BNXT_ULP_CLASS_HID_1edd7, + .class_hid = BNXT_ULP_CLASS_HID_5c7f3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 101, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17726,21 +18816,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [725] = { - .class_hid = BNXT_ULP_CLASS_HID_1aaa3, + .class_hid = BNXT_ULP_CLASS_HID_59fab, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17749,18 +18837,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [726] = { - .class_hid = BNXT_ULP_CLASS_HID_1ad63, + .class_hid = BNXT_ULP_CLASS_HID_5abd3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17769,19 +18857,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [727] = { - .class_hid = BNXT_ULP_CLASS_HID_1f023, + .class_hid = BNXT_ULP_CLASS_HID_5a597, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17790,19 +18878,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [728] = { - .class_hid = BNXT_ULP_CLASS_HID_1f2e3, + .class_hid = BNXT_ULP_CLASS_HID_5b21f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17811,20 +18899,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [729] = { - .class_hid = BNXT_ULP_CLASS_HID_b837, + .class_hid = BNXT_ULP_CLASS_HID_5d893, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17833,18 +18921,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [730] = { - .class_hid = BNXT_ULP_CLASS_HID_baf7, + .class_hid = BNXT_ULP_CLASS_HID_5884f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17853,19 +18941,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [731] = { - .class_hid = BNXT_ULP_CLASS_HID_fdb7, + .class_hid = BNXT_ULP_CLASS_HID_58203, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17874,19 +18962,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [732] = { - .class_hid = BNXT_ULP_CLASS_HID_e077, + .class_hid = BNXT_ULP_CLASS_HID_58e8b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17895,20 +18983,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [733] = { - .class_hid = BNXT_ULP_CLASS_HID_b37b, + .class_hid = BNXT_ULP_CLASS_HID_5c33f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17917,19 +19005,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [734] = { - .class_hid = BNXT_ULP_CLASS_HID_b63b, + .class_hid = BNXT_ULP_CLASS_HID_5cfa7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17938,20 +19026,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [735] = { - .class_hid = BNXT_ULP_CLASS_HID_f8fb, + .class_hid = BNXT_ULP_CLASS_HID_5c97b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17960,20 +19048,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [736] = { - .class_hid = BNXT_ULP_CLASS_HID_fbbb, + .class_hid = BNXT_ULP_CLASS_HID_5d5e3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -17982,21 +19070,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [737] = { - .class_hid = BNXT_ULP_CLASS_HID_1c97b, + .class_hid = BNXT_ULP_CLASS_HID_e95b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18005,20 +19093,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [738] = { - .class_hid = BNXT_ULP_CLASS_HID_1ec3b, + .class_hid = BNXT_ULP_CLASS_HID_f5c3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18027,21 +19111,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [739] = { - .class_hid = BNXT_ULP_CLASS_HID_1cefb, + .class_hid = BNXT_ULP_CLASS_HID_ef87, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18050,21 +19130,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [740] = { - .class_hid = BNXT_ULP_CLASS_HID_1f1bb, + .class_hid = BNXT_ULP_CLASS_HID_fc0f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18073,22 +19149,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [741] = { - .class_hid = BNXT_ULP_CLASS_HID_1ce37, + .class_hid = BNXT_ULP_CLASS_HID_d3e7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18097,19 +19169,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [742] = { - .class_hid = BNXT_ULP_CLASS_HID_1f0f7, + .class_hid = BNXT_ULP_CLASS_HID_e06f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18118,20 +19188,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [743] = { - .class_hid = BNXT_ULP_CLASS_HID_1d3b7, + .class_hid = BNXT_ULP_CLASS_HID_da23, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18140,20 +19208,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [744] = { - .class_hid = BNXT_ULP_CLASS_HID_1f677, + .class_hid = BNXT_ULP_CLASS_HID_e6ab, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18162,21 +19228,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [745] = { - .class_hid = BNXT_ULP_CLASS_HID_a3db, + .class_hid = BNXT_ULP_CLASS_HID_cd2f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18185,15 +19249,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [746] = { - .class_hid = BNXT_ULP_CLASS_HID_a69b, + .class_hid = BNXT_ULP_CLASS_HID_d957, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18202,16 +19268,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [747] = { - .class_hid = BNXT_ULP_CLASS_HID_e95b, + .class_hid = BNXT_ULP_CLASS_HID_d36b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18220,16 +19288,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [748] = { - .class_hid = BNXT_ULP_CLASS_HID_ec1b, + .class_hid = BNXT_ULP_CLASS_HID_c2c7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18238,17 +19308,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [749] = { - .class_hid = BNXT_ULP_CLASS_HID_9f0f, + .class_hid = BNXT_ULP_CLASS_HID_f74b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18257,16 +19329,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [750] = { - .class_hid = BNXT_ULP_CLASS_HID_a1cf, + .class_hid = BNXT_ULP_CLASS_HID_c3f3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18275,17 +19349,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [751] = { - .class_hid = BNXT_ULP_CLASS_HID_e48f, + .class_hid = BNXT_ULP_CLASS_HID_fdb7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18294,17 +19370,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [752] = { - .class_hid = BNXT_ULP_CLASS_HID_e74f, + .class_hid = BNXT_ULP_CLASS_HID_ca3f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18313,18 +19391,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [753] = { - .class_hid = BNXT_ULP_CLASS_HID_1b50f, + .class_hid = BNXT_ULP_CLASS_HID_4e48f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18333,17 +19413,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [754] = { - .class_hid = BNXT_ULP_CLASS_HID_1b7cf, + .class_hid = BNXT_ULP_CLASS_HID_4f137, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18352,18 +19432,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [755] = { - .class_hid = BNXT_ULP_CLASS_HID_1fa8f, + .class_hid = BNXT_ULP_CLASS_HID_4eacb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18372,18 +19452,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [756] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd4f, + .class_hid = BNXT_ULP_CLASS_HID_4f773, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18392,19 +19472,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [757] = { - .class_hid = BNXT_ULP_CLASS_HID_1b9db, + .class_hid = BNXT_ULP_CLASS_HID_4cf2b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18413,16 +19493,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [758] = { - .class_hid = BNXT_ULP_CLASS_HID_1bc9b, + .class_hid = BNXT_ULP_CLASS_HID_4db53, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18431,17 +19513,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [759] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff5b, + .class_hid = BNXT_ULP_CLASS_HID_4d517, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18450,17 +19534,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [760] = { - .class_hid = BNXT_ULP_CLASS_HID_1e21b, + .class_hid = BNXT_ULP_CLASS_HID_4e19f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18469,18 +19555,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [761] = { - .class_hid = BNXT_ULP_CLASS_HID_c7af, + .class_hid = BNXT_ULP_CLASS_HID_4c813, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18489,16 +19577,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [762] = { - .class_hid = BNXT_ULP_CLASS_HID_ea6f, + .class_hid = BNXT_ULP_CLASS_HID_4d49b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18507,17 +19597,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [763] = { - .class_hid = BNXT_ULP_CLASS_HID_cd2f, + .class_hid = BNXT_ULP_CLASS_HID_4ce5f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18526,17 +19618,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [764] = { - .class_hid = BNXT_ULP_CLASS_HID_efef, + .class_hid = BNXT_ULP_CLASS_HID_4dac7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18545,18 +19639,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [765] = { - .class_hid = BNXT_ULP_CLASS_HID_c293, + .class_hid = BNXT_ULP_CLASS_HID_4f2bf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18565,17 +19661,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [766] = { - .class_hid = BNXT_ULP_CLASS_HID_e553, + .class_hid = BNXT_ULP_CLASS_HID_4ff27, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18584,18 +19682,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [767] = { - .class_hid = BNXT_ULP_CLASS_HID_c813, + .class_hid = BNXT_ULP_CLASS_HID_4f8fb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18604,18 +19704,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [768] = { - .class_hid = BNXT_ULP_CLASS_HID_ead3, + .class_hid = BNXT_ULP_CLASS_HID_4c563, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18624,19 +19726,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [769] = { - .class_hid = BNXT_ULP_CLASS_HID_1d893, + .class_hid = BNXT_ULP_CLASS_HID_1ff5b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18645,18 +19749,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [770] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb53, + .class_hid = BNXT_ULP_CLASS_HID_1cbc3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18665,19 +19768,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [771] = { - .class_hid = BNXT_ULP_CLASS_HID_1c147, + .class_hid = BNXT_ULP_CLASS_HID_1c587, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18686,19 +19788,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [772] = { - .class_hid = BNXT_ULP_CLASS_HID_1e407, + .class_hid = BNXT_ULP_CLASS_HID_1d20f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18707,20 +19808,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [773] = { - .class_hid = BNXT_ULP_CLASS_HID_18093, + .class_hid = BNXT_ULP_CLASS_HID_1e9e7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18729,17 +19829,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [774] = { - .class_hid = BNXT_ULP_CLASS_HID_1a353, + .class_hid = BNXT_ULP_CLASS_HID_1f66f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18748,18 +19849,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [775] = { - .class_hid = BNXT_ULP_CLASS_HID_1c613, + .class_hid = BNXT_ULP_CLASS_HID_1f023, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18768,18 +19870,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [776] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8d3, + .class_hid = BNXT_ULP_CLASS_HID_1fcab, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18788,19 +19891,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [777] = { - .class_hid = BNXT_ULP_CLASS_HID_8e67, + .class_hid = BNXT_ULP_CLASS_HID_1c613, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18809,16 +19913,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [778] = { - .class_hid = BNXT_ULP_CLASS_HID_b127, + .class_hid = BNXT_ULP_CLASS_HID_1d29b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18827,17 +19933,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [779] = { - .class_hid = BNXT_ULP_CLASS_HID_d3e7, + .class_hid = BNXT_ULP_CLASS_HID_1cc5f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18846,17 +19954,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [780] = { - .class_hid = BNXT_ULP_CLASS_HID_f6a7, + .class_hid = BNXT_ULP_CLASS_HID_1d8c7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18865,18 +19975,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [781] = { - .class_hid = BNXT_ULP_CLASS_HID_89ab, + .class_hid = BNXT_ULP_CLASS_HID_1cd4b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18885,17 +19997,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [782] = { - .class_hid = BNXT_ULP_CLASS_HID_ac6b, + .class_hid = BNXT_ULP_CLASS_HID_1d9f3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18904,18 +20018,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [783] = { - .class_hid = BNXT_ULP_CLASS_HID_cf2b, + .class_hid = BNXT_ULP_CLASS_HID_1d3b7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18924,18 +20040,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [784] = { - .class_hid = BNXT_ULP_CLASS_HID_f1eb, + .class_hid = BNXT_ULP_CLASS_HID_1c363, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18944,19 +20062,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [785] = { - .class_hid = BNXT_ULP_CLASS_HID_19fab, + .class_hid = BNXT_ULP_CLASS_HID_5fa8f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18965,18 +20085,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [786] = { - .class_hid = BNXT_ULP_CLASS_HID_1a26b, + .class_hid = BNXT_ULP_CLASS_HID_5c737, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -18985,19 +20105,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [787] = { - .class_hid = BNXT_ULP_CLASS_HID_1e52b, + .class_hid = BNXT_ULP_CLASS_HID_5c0cb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19006,19 +20126,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [788] = { - .class_hid = BNXT_ULP_CLASS_HID_1e7eb, + .class_hid = BNXT_ULP_CLASS_HID_5cd73, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19027,20 +20147,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [789] = { - .class_hid = BNXT_ULP_CLASS_HID_1a467, + .class_hid = BNXT_ULP_CLASS_HID_5e52b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19049,17 +20169,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [790] = { - .class_hid = BNXT_ULP_CLASS_HID_1a727, + .class_hid = BNXT_ULP_CLASS_HID_5f153, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19068,18 +20190,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [791] = { - .class_hid = BNXT_ULP_CLASS_HID_1e9e7, + .class_hid = BNXT_ULP_CLASS_HID_5eb17, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19088,18 +20212,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [792] = { - .class_hid = BNXT_ULP_CLASS_HID_1eca7, + .class_hid = BNXT_ULP_CLASS_HID_5f79f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19108,19 +20234,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [793] = { - .class_hid = BNXT_ULP_CLASS_HID_b1cb, + .class_hid = BNXT_ULP_CLASS_HID_5c147, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19129,17 +20257,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [794] = { - .class_hid = BNXT_ULP_CLASS_HID_b48b, + .class_hid = BNXT_ULP_CLASS_HID_5cdcf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19148,18 +20278,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [795] = { - .class_hid = BNXT_ULP_CLASS_HID_f74b, + .class_hid = BNXT_ULP_CLASS_HID_5c783, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19168,18 +20300,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [796] = { - .class_hid = BNXT_ULP_CLASS_HID_fa0b, + .class_hid = BNXT_ULP_CLASS_HID_5d40b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19188,19 +20322,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [797] = { - .class_hid = BNXT_ULP_CLASS_HID_ad3f, + .class_hid = BNXT_ULP_CLASS_HID_5c8bf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19209,18 +20345,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [798] = { - .class_hid = BNXT_ULP_CLASS_HID_afff, + .class_hid = BNXT_ULP_CLASS_HID_5d527, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19229,19 +20367,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [799] = { - .class_hid = BNXT_ULP_CLASS_HID_f2bf, + .class_hid = BNXT_ULP_CLASS_HID_5cefb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19250,19 +20390,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [800] = { - .class_hid = BNXT_ULP_CLASS_HID_f57f, + .class_hid = BNXT_ULP_CLASS_HID_5db63, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19271,20 +20413,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [801] = { - .class_hid = BNXT_ULP_CLASS_HID_1c33f, + .class_hid = BNXT_ULP_CLASS_HID_a69b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19293,19 +20437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [802] = { - .class_hid = BNXT_ULP_CLASS_HID_1e5ff, + .class_hid = BNXT_ULP_CLASS_HID_b303, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19314,20 +20455,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [803] = { - .class_hid = BNXT_ULP_CLASS_HID_1c8bf, + .class_hid = BNXT_ULP_CLASS_HID_acc7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19336,20 +20474,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [804] = { - .class_hid = BNXT_ULP_CLASS_HID_1eb7f, + .class_hid = BNXT_ULP_CLASS_HID_b94f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19358,21 +20493,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [805] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7cb, + .class_hid = BNXT_ULP_CLASS_HID_b127, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19381,18 +20513,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [806] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea8b, + .class_hid = BNXT_ULP_CLASS_HID_bdaf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19401,19 +20532,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [807] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd4b, + .class_hid = BNXT_ULP_CLASS_HID_b763, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19422,19 +20552,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [808] = { - .class_hid = BNXT_ULP_CLASS_HID_1f00b, + .class_hid = BNXT_ULP_CLASS_HID_a3eb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -19443,21 +20572,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [809] = { - .class_hid = BNXT_ULP_CLASS_HID_9117, + .class_hid = BNXT_ULP_CLASS_HID_ea6f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19465,16 +20593,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [810] = { - .class_hid = BNXT_ULP_CLASS_HID_b3d7, + .class_hid = BNXT_ULP_CLASS_HID_f697, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19482,17 +20612,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [811] = { - .class_hid = BNXT_ULP_CLASS_HID_d697, + .class_hid = BNXT_ULP_CLASS_HID_f0ab, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19500,17 +20632,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [812] = { - .class_hid = BNXT_ULP_CLASS_HID_f957, + .class_hid = BNXT_ULP_CLASS_HID_a007, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19518,18 +20652,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [813] = { - .class_hid = BNXT_ULP_CLASS_HID_8c5b, + .class_hid = BNXT_ULP_CLASS_HID_b48b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19537,17 +20673,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [814] = { - .class_hid = BNXT_ULP_CLASS_HID_af1b, + .class_hid = BNXT_ULP_CLASS_HID_e133, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655432, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19555,18 +20693,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [815] = { - .class_hid = BNXT_ULP_CLASS_HID_d1db, + .class_hid = BNXT_ULP_CLASS_HID_baf7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19574,18 +20714,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [816] = { - .class_hid = BNXT_ULP_CLASS_HID_f49b, + .class_hid = BNXT_ULP_CLASS_HID_e77f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655432, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19593,19 +20735,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [817] = { - .class_hid = BNXT_ULP_CLASS_HID_1a25b, + .class_hid = BNXT_ULP_CLASS_HID_4a1cf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19613,18 +20757,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [818] = { - .class_hid = BNXT_ULP_CLASS_HID_1a51b, + .class_hid = BNXT_ULP_CLASS_HID_4ae77, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19632,19 +20776,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [819] = { - .class_hid = BNXT_ULP_CLASS_HID_1e7db, + .class_hid = BNXT_ULP_CLASS_HID_4a80b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19652,19 +20796,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [820] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea9b, + .class_hid = BNXT_ULP_CLASS_HID_4b4b3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19672,20 +20816,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [821] = { - .class_hid = BNXT_ULP_CLASS_HID_1a717, + .class_hid = BNXT_ULP_CLASS_HID_4ac6b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19693,17 +20837,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [822] = { - .class_hid = BNXT_ULP_CLASS_HID_1a9d7, + .class_hid = BNXT_ULP_CLASS_HID_4b893, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655432, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19711,18 +20857,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [823] = { - .class_hid = BNXT_ULP_CLASS_HID_1ec97, + .class_hid = BNXT_ULP_CLASS_HID_4b257, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19730,18 +20878,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [824] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef57, + .class_hid = BNXT_ULP_CLASS_HID_4bedf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655432, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19749,19 +20899,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [825] = { - .class_hid = BNXT_ULP_CLASS_HID_b4fb, + .class_hid = BNXT_ULP_CLASS_HID_4e553, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19769,17 +20921,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [826] = { - .class_hid = BNXT_ULP_CLASS_HID_b7bb, + .class_hid = BNXT_ULP_CLASS_HID_4f1db, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19787,18 +20941,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [827] = { - .class_hid = BNXT_ULP_CLASS_HID_fa7b, + .class_hid = BNXT_ULP_CLASS_HID_4eb9f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19806,18 +20962,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [828] = { - .class_hid = BNXT_ULP_CLASS_HID_fd3b, + .class_hid = BNXT_ULP_CLASS_HID_4f807, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19825,19 +20983,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [829] = { - .class_hid = BNXT_ULP_CLASS_HID_b02f, + .class_hid = BNXT_ULP_CLASS_HID_4afff, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19845,18 +21005,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [830] = { - .class_hid = BNXT_ULP_CLASS_HID_b2ef, + .class_hid = BNXT_ULP_CLASS_HID_4bc67, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655432, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19864,19 +21026,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [831] = { - .class_hid = BNXT_ULP_CLASS_HID_f5af, + .class_hid = BNXT_ULP_CLASS_HID_4b63b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19884,19 +21048,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [832] = { - .class_hid = BNXT_ULP_CLASS_HID_f86f, + .class_hid = BNXT_ULP_CLASS_HID_4e2a3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655432, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19904,20 +21070,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [833] = { - .class_hid = BNXT_ULP_CLASS_HID_1c62f, + .class_hid = BNXT_ULP_CLASS_HID_1bc9b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19925,19 +21093,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [834] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8ef, + .class_hid = BNXT_ULP_CLASS_HID_1e903, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19945,20 +21112,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [835] = { - .class_hid = BNXT_ULP_CLASS_HID_1cbaf, + .class_hid = BNXT_ULP_CLASS_HID_1e2c7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19966,20 +21132,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [836] = { - .class_hid = BNXT_ULP_CLASS_HID_1ee6f, + .class_hid = BNXT_ULP_CLASS_HID_1ef4f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -19987,21 +21152,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [837] = { - .class_hid = BNXT_ULP_CLASS_HID_1cafb, + .class_hid = BNXT_ULP_CLASS_HID_1a727, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20009,18 +21173,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [838] = { - .class_hid = BNXT_ULP_CLASS_HID_1edbb, + .class_hid = BNXT_ULP_CLASS_HID_1b3af, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720968, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20028,19 +21193,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [839] = { - .class_hid = BNXT_ULP_CLASS_HID_1d07b, + .class_hid = BNXT_ULP_CLASS_HID_1ad63, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20048,19 +21214,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [840] = { - .class_hid = BNXT_ULP_CLASS_HID_1f33b, + .class_hid = BNXT_ULP_CLASS_HID_1b9eb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720968, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20068,20 +21235,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [841] = { - .class_hid = BNXT_ULP_CLASS_HID_8b2b, + .class_hid = BNXT_ULP_CLASS_HID_1a353, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20089,15 +21257,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [842] = { - .class_hid = BNXT_ULP_CLASS_HID_adeb, + .class_hid = BNXT_ULP_CLASS_HID_1afdb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20105,16 +21277,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [843] = { - .class_hid = BNXT_ULP_CLASS_HID_d0ab, + .class_hid = BNXT_ULP_CLASS_HID_1a99f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20122,16 +21298,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [844] = { - .class_hid = BNXT_ULP_CLASS_HID_f36b, + .class_hid = BNXT_ULP_CLASS_HID_1b607, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20139,17 +21319,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [845] = { - .class_hid = BNXT_ULP_CLASS_HID_861f, + .class_hid = BNXT_ULP_CLASS_HID_1ea8b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20157,16 +21341,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [846] = { - .class_hid = BNXT_ULP_CLASS_HID_a8df, + .class_hid = BNXT_ULP_CLASS_HID_1f733, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720968, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20174,17 +21362,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [847] = { - .class_hid = BNXT_ULP_CLASS_HID_cb9f, + .class_hid = BNXT_ULP_CLASS_HID_1f0f7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20192,17 +21384,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [848] = { - .class_hid = BNXT_ULP_CLASS_HID_ee5f, + .class_hid = BNXT_ULP_CLASS_HID_1a0a3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720968, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20210,18 +21406,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [849] = { - .class_hid = BNXT_ULP_CLASS_HID_19c1f, + .class_hid = BNXT_ULP_CLASS_HID_5b7cf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20229,17 +21429,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [850] = { - .class_hid = BNXT_ULP_CLASS_HID_1bedf, + .class_hid = BNXT_ULP_CLASS_HID_5e477, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20247,18 +21449,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [851] = { - .class_hid = BNXT_ULP_CLASS_HID_1e19f, + .class_hid = BNXT_ULP_CLASS_HID_5be0b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20266,18 +21470,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [852] = { - .class_hid = BNXT_ULP_CLASS_HID_1e45f, + .class_hid = BNXT_ULP_CLASS_HID_5eab3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20285,19 +21491,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [853] = { - .class_hid = BNXT_ULP_CLASS_HID_1a12b, + .class_hid = BNXT_ULP_CLASS_HID_5a26b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20305,16 +21513,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [854] = { - .class_hid = BNXT_ULP_CLASS_HID_1a3eb, + .class_hid = BNXT_ULP_CLASS_HID_5ae93, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720968, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20322,17 +21534,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [855] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6ab, + .class_hid = BNXT_ULP_CLASS_HID_5a857, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20340,17 +21556,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [856] = { - .class_hid = BNXT_ULP_CLASS_HID_1e96b, + .class_hid = BNXT_ULP_CLASS_HID_5b4df, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720968, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20358,18 +21578,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [857] = { - .class_hid = BNXT_ULP_CLASS_HID_aebf, + .class_hid = BNXT_ULP_CLASS_HID_5fb53, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20377,16 +21601,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [858] = { - .class_hid = BNXT_ULP_CLASS_HID_b17f, + .class_hid = BNXT_ULP_CLASS_HID_5ab0f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20394,17 +21622,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [859] = { - .class_hid = BNXT_ULP_CLASS_HID_f43f, + .class_hid = BNXT_ULP_CLASS_HID_5a4c3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20412,17 +21644,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [860] = { - .class_hid = BNXT_ULP_CLASS_HID_f6ff, + .class_hid = BNXT_ULP_CLASS_HID_5b14b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20430,18 +21666,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [861] = { - .class_hid = BNXT_ULP_CLASS_HID_a9e3, + .class_hid = BNXT_ULP_CLASS_HID_5e5ff, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20449,17 +21689,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [862] = { - .class_hid = BNXT_ULP_CLASS_HID_aca3, + .class_hid = BNXT_ULP_CLASS_HID_5f267, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720968, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20467,18 +21711,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [863] = { - .class_hid = BNXT_ULP_CLASS_HID_ef63, + .class_hid = BNXT_ULP_CLASS_HID_5ec3b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20486,18 +21734,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [864] = { - .class_hid = BNXT_ULP_CLASS_HID_f223, + .class_hid = BNXT_ULP_CLASS_HID_5f8a3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720968, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20505,19 +21757,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [865] = { - .class_hid = BNXT_ULP_CLASS_HID_1bfe3, + .class_hid = BNXT_ULP_CLASS_HID_ec1b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20525,18 +21781,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [866] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2a3, + .class_hid = BNXT_ULP_CLASS_HID_f883, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917512, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20544,19 +21800,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [867] = { - .class_hid = BNXT_ULP_CLASS_HID_1c563, + .class_hid = BNXT_ULP_CLASS_HID_f247, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20564,19 +21820,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [868] = { - .class_hid = BNXT_ULP_CLASS_HID_1e823, + .class_hid = BNXT_ULP_CLASS_HID_fecf, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917512, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20584,38 +21840,40 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [869] = { - .class_hid = BNXT_ULP_CLASS_HID_1c4bf, + .class_hid = BNXT_ULP_CLASS_HID_f6a7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, - .hdr_sig = { .bits = + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 0, + .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [870] = { - .class_hid = BNXT_ULP_CLASS_HID_1e77f, + .class_hid = BNXT_ULP_CLASS_HID_e32f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20623,18 +21881,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [871] = { - .class_hid = BNXT_ULP_CLASS_HID_1ca3f, + .class_hid = BNXT_ULP_CLASS_HID_fce3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20642,18 +21902,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [872] = { - .class_hid = BNXT_ULP_CLASS_HID_1ecff, + .class_hid = BNXT_ULP_CLASS_HID_e96b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20661,19 +21923,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [873] = { - .class_hid = BNXT_ULP_CLASS_HID_2543, + .class_hid = BNXT_ULP_CLASS_HID_efef, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20681,16 +21945,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [874] = { - .class_hid = BNXT_ULP_CLASS_HID_2b8f, + .class_hid = BNXT_ULP_CLASS_HID_fc17, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917512, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20698,17 +21965,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [875] = { - .class_hid = BNXT_ULP_CLASS_HID_26f3, + .class_hid = BNXT_ULP_CLASS_HID_f62b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20716,18 +21986,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [876] = { - .class_hid = BNXT_ULP_CLASS_HID_4f13, + .class_hid = BNXT_ULP_CLASS_HID_e587, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917512, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20735,18 +22007,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [877] = { - .class_hid = BNXT_ULP_CLASS_HID_4a47, + .class_hid = BNXT_ULP_CLASS_HID_fa0b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20754,19 +22029,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [878] = { - .class_hid = BNXT_ULP_CLASS_HID_162b, + .class_hid = BNXT_ULP_CLASS_HID_e6b3, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20774,18 +22050,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [879] = { - .class_hid = BNXT_ULP_CLASS_HID_111f, + .class_hid = BNXT_ULP_CLASS_HID_e077, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20793,19 +22072,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [880] = { - .class_hid = BNXT_ULP_CLASS_HID_39bf, + .class_hid = BNXT_ULP_CLASS_HID_ecff, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20813,19 +22094,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [881] = { - .class_hid = BNXT_ULP_CLASS_HID_34e3, + .class_hid = BNXT_ULP_CLASS_HID_4e74f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20833,20 +22117,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [882] = { - .class_hid = BNXT_ULP_CLASS_HID_20b7, + .class_hid = BNXT_ULP_CLASS_HID_4f3f7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917512, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20854,17 +22137,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [883] = { - .class_hid = BNXT_ULP_CLASS_HID_48d7, + .class_hid = BNXT_ULP_CLASS_HID_4ed8b, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20872,17 +22158,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [884] = { - .class_hid = BNXT_ULP_CLASS_HID_441b, + .class_hid = BNXT_ULP_CLASS_HID_4fa33, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917512, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20890,18 +22179,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [885] = { - .class_hid = BNXT_ULP_CLASS_HID_0fef, + .class_hid = BNXT_ULP_CLASS_HID_4f1eb, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20909,17 +22201,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [886] = { - .class_hid = BNXT_ULP_CLASS_HID_0ad3, + .class_hid = BNXT_ULP_CLASS_HID_4fe13, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20927,18 +22222,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [887] = { - .class_hid = BNXT_ULP_CLASS_HID_3373, + .class_hid = BNXT_ULP_CLASS_HID_4f7d7, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20946,18 +22244,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [888] = { - .class_hid = BNXT_ULP_CLASS_HID_2ea7, + .class_hid = BNXT_ULP_CLASS_HID_4e45f, .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 102, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 917576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -20965,6159 +22266,6298 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [889] = { - .class_hid = BNXT_ULP_CLASS_HID_b6ef, + .class_hid = BNXT_ULP_CLASS_HID_4ead3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [890] = { - .class_hid = BNXT_ULP_CLASS_HID_b92f, + .class_hid = BNXT_ULP_CLASS_HID_4f75b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [891] = { - .class_hid = BNXT_ULP_CLASS_HID_fc6f, + .class_hid = BNXT_ULP_CLASS_HID_4f11f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [892] = { - .class_hid = BNXT_ULP_CLASS_HID_feaf, + .class_hid = BNXT_ULP_CLASS_HID_4e0cb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [893] = { - .class_hid = BNXT_ULP_CLASS_HID_b193, + .class_hid = BNXT_ULP_CLASS_HID_4f57f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [894] = { - .class_hid = BNXT_ULP_CLASS_HID_b4d3, + .class_hid = BNXT_ULP_CLASS_HID_4e1e7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [895] = { - .class_hid = BNXT_ULP_CLASS_HID_f713, + .class_hid = BNXT_ULP_CLASS_HID_4fbbb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [896] = { - .class_hid = BNXT_ULP_CLASS_HID_fa53, + .class_hid = BNXT_ULP_CLASS_HID_4e823, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [897] = { - .class_hid = BNXT_ULP_CLASS_HID_1c793, + .class_hid = BNXT_ULP_CLASS_HID_1e21b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [898] = { - .class_hid = BNXT_ULP_CLASS_HID_1ead3, + .class_hid = BNXT_ULP_CLASS_HID_1ee83, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [899] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd13, + .class_hid = BNXT_ULP_CLASS_HID_1e847, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [900] = { - .class_hid = BNXT_ULP_CLASS_HID_1f053, + .class_hid = BNXT_ULP_CLASS_HID_1f4cf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [901] = { - .class_hid = BNXT_ULP_CLASS_HID_1ccef, + .class_hid = BNXT_ULP_CLASS_HID_1eca7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [902] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef2f, + .class_hid = BNXT_ULP_CLASS_HID_1f92f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [903] = { - .class_hid = BNXT_ULP_CLASS_HID_1d26f, + .class_hid = BNXT_ULP_CLASS_HID_1f2e3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [904] = { - .class_hid = BNXT_ULP_CLASS_HID_1f4af, + .class_hid = BNXT_ULP_CLASS_HID_1ff6b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [905] = { - .class_hid = BNXT_ULP_CLASS_HID_da73, + .class_hid = BNXT_ULP_CLASS_HID_1e8d3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [906] = { - .class_hid = BNXT_ULP_CLASS_HID_a067, + .class_hid = BNXT_ULP_CLASS_HID_1f55b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [907] = { - .class_hid = BNXT_ULP_CLASS_HID_c2a7, + .class_hid = BNXT_ULP_CLASS_HID_1ef1f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [908] = { - .class_hid = BNXT_ULP_CLASS_HID_e5e7, + .class_hid = BNXT_ULP_CLASS_HID_1fb87, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [909] = { - .class_hid = BNXT_ULP_CLASS_HID_d527, + .class_hid = BNXT_ULP_CLASS_HID_1f00b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [910] = { - .class_hid = BNXT_ULP_CLASS_HID_f867, + .class_hid = BNXT_ULP_CLASS_HID_1fcb3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [911] = { - .class_hid = BNXT_ULP_CLASS_HID_daa7, + .class_hid = BNXT_ULP_CLASS_HID_1f677, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [912] = { - .class_hid = BNXT_ULP_CLASS_HID_e0ab, + .class_hid = BNXT_ULP_CLASS_HID_1e623, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [913] = { - .class_hid = BNXT_ULP_CLASS_HID_18eeb, + .class_hid = BNXT_ULP_CLASS_HID_5fd4f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [914] = { - .class_hid = BNXT_ULP_CLASS_HID_1b12b, + .class_hid = BNXT_ULP_CLASS_HID_5e9f7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [915] = { - .class_hid = BNXT_ULP_CLASS_HID_1d46b, + .class_hid = BNXT_ULP_CLASS_HID_5e38b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [916] = { - .class_hid = BNXT_ULP_CLASS_HID_1f6ab, + .class_hid = BNXT_ULP_CLASS_HID_5f033, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [917] = { - .class_hid = BNXT_ULP_CLASS_HID_19327, + .class_hid = BNXT_ULP_CLASS_HID_5e7eb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [918] = { - .class_hid = BNXT_ULP_CLASS_HID_1b667, + .class_hid = BNXT_ULP_CLASS_HID_5f413, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [919] = { - .class_hid = BNXT_ULP_CLASS_HID_1d8a7, + .class_hid = BNXT_ULP_CLASS_HID_5edd7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [920] = { - .class_hid = BNXT_ULP_CLASS_HID_1fbe7, + .class_hid = BNXT_ULP_CLASS_HID_5fa5f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [921] = { - .class_hid = BNXT_ULP_CLASS_HID_a14b, + .class_hid = BNXT_ULP_CLASS_HID_5e407, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [922] = { - .class_hid = BNXT_ULP_CLASS_HID_a38b, + .class_hid = BNXT_ULP_CLASS_HID_5f08f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 102, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [923] = { - .class_hid = BNXT_ULP_CLASS_HID_e6cb, + .class_hid = BNXT_ULP_CLASS_HID_5ea43, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 103, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [924] = { - .class_hid = BNXT_ULP_CLASS_HID_e90b, + .class_hid = BNXT_ULP_CLASS_HID_5f6cb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 104, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [925] = { - .class_hid = BNXT_ULP_CLASS_HID_9c7f, + .class_hid = BNXT_ULP_CLASS_HID_5eb7f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 105, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [926] = { - .class_hid = BNXT_ULP_CLASS_HID_bebf, + .class_hid = BNXT_ULP_CLASS_HID_5f7e7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 105, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [927] = { - .class_hid = BNXT_ULP_CLASS_HID_e1ff, + .class_hid = BNXT_ULP_CLASS_HID_5f1bb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 105, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [928] = { - .class_hid = BNXT_ULP_CLASS_HID_e43f, + .class_hid = BNXT_ULP_CLASS_HID_5e117, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 105, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [929] = { - .class_hid = BNXT_ULP_CLASS_HID_1b27f, + .class_hid = BNXT_ULP_CLASS_HID_244a3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 105, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [930] = { - .class_hid = BNXT_ULP_CLASS_HID_1b4bf, + .class_hid = BNXT_ULP_CLASS_HID_2513b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 105, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [931] = { - .class_hid = BNXT_ULP_CLASS_HID_1f7ff, + .class_hid = BNXT_ULP_CLASS_HID_24b7f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 106, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [932] = { - .class_hid = BNXT_ULP_CLASS_HID_1fa3f, + .class_hid = BNXT_ULP_CLASS_HID_257f7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 107, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [933] = { - .class_hid = BNXT_ULP_CLASS_HID_1b74b, + .class_hid = BNXT_ULP_CLASS_HID_22f1f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [934] = { - .class_hid = BNXT_ULP_CLASS_HID_1b98b, + .class_hid = BNXT_ULP_CLASS_HID_23b97, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [935] = { - .class_hid = BNXT_ULP_CLASS_HID_1fccb, + .class_hid = BNXT_ULP_CLASS_HID_235db, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [936] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff0b, + .class_hid = BNXT_ULP_CLASS_HID_24253, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [937] = { - .class_hid = BNXT_ULP_CLASS_HID_c4df, + .class_hid = BNXT_ULP_CLASS_HID_20beb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [938] = { - .class_hid = BNXT_ULP_CLASS_HID_e71f, + .class_hid = BNXT_ULP_CLASS_HID_21863, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [939] = { - .class_hid = BNXT_ULP_CLASS_HID_ca5f, + .class_hid = BNXT_ULP_CLASS_HID_211a7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [940] = { - .class_hid = BNXT_ULP_CLASS_HID_ec9f, + .class_hid = BNXT_ULP_CLASS_HID_21e3f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [941] = { - .class_hid = BNXT_ULP_CLASS_HID_bf83, + .class_hid = BNXT_ULP_CLASS_HID_252b3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [942] = { - .class_hid = BNXT_ULP_CLASS_HID_e2c3, + .class_hid = BNXT_ULP_CLASS_HID_202df, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [943] = { - .class_hid = BNXT_ULP_CLASS_HID_c503, + .class_hid = BNXT_ULP_CLASS_HID_2594f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [944] = { - .class_hid = BNXT_ULP_CLASS_HID_e843, + .class_hid = BNXT_ULP_CLASS_HID_2089b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [945] = { - .class_hid = BNXT_ULP_CLASS_HID_1d583, + .class_hid = BNXT_ULP_CLASS_HID_23193, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [946] = { - .class_hid = BNXT_ULP_CLASS_HID_1f8c3, + .class_hid = BNXT_ULP_CLASS_HID_23e6b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [947] = { - .class_hid = BNXT_ULP_CLASS_HID_1db03, + .class_hid = BNXT_ULP_CLASS_HID_237af, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [948] = { - .class_hid = BNXT_ULP_CLASS_HID_1e177, + .class_hid = BNXT_ULP_CLASS_HID_24427, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [949] = { - .class_hid = BNXT_ULP_CLASS_HID_1dadf, + .class_hid = BNXT_ULP_CLASS_HID_21c4f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [950] = { - .class_hid = BNXT_ULP_CLASS_HID_1a0c3, + .class_hid = BNXT_ULP_CLASS_HID_228c7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [951] = { - .class_hid = BNXT_ULP_CLASS_HID_1c303, + .class_hid = BNXT_ULP_CLASS_HID_2220b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [952] = { - .class_hid = BNXT_ULP_CLASS_HID_1e643, + .class_hid = BNXT_ULP_CLASS_HID_22e83, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [953] = { - .class_hid = BNXT_ULP_CLASS_HID_b023, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [953] = { + .class_hid = BNXT_ULP_CLASS_HID_25507, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [954] = { - .class_hid = BNXT_ULP_CLASS_HID_b363, + .class_hid = BNXT_ULP_CLASS_HID_20553, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [955] = { - .class_hid = BNXT_ULP_CLASS_HID_f5a3, + .class_hid = BNXT_ULP_CLASS_HID_25bc3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [956] = { - .class_hid = BNXT_ULP_CLASS_HID_f8e3, + .class_hid = BNXT_ULP_CLASS_HID_20b6f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [957] = { - .class_hid = BNXT_ULP_CLASS_HID_abd7, + .class_hid = BNXT_ULP_CLASS_HID_23fe3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [958] = { - .class_hid = BNXT_ULP_CLASS_HID_ae17, + .class_hid = BNXT_ULP_CLASS_HID_24c7b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [959] = { - .class_hid = BNXT_ULP_CLASS_HID_f157, + .class_hid = BNXT_ULP_CLASS_HID_245bf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [960] = { - .class_hid = BNXT_ULP_CLASS_HID_f397, + .class_hid = BNXT_ULP_CLASS_HID_25237, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [961] = { - .class_hid = BNXT_ULP_CLASS_HID_1c1d7, + .class_hid = BNXT_ULP_CLASS_HID_64077, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [962] = { - .class_hid = BNXT_ULP_CLASS_HID_1e417, + .class_hid = BNXT_ULP_CLASS_HID_64ccf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [963] = { - .class_hid = BNXT_ULP_CLASS_HID_1c757, + .class_hid = BNXT_ULP_CLASS_HID_64633, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [964] = { - .class_hid = BNXT_ULP_CLASS_HID_1e997, + .class_hid = BNXT_ULP_CLASS_HID_6528b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [965] = { - .class_hid = BNXT_ULP_CLASS_HID_1c623, + .class_hid = BNXT_ULP_CLASS_HID_62ad3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [966] = { - .class_hid = BNXT_ULP_CLASS_HID_1e963, + .class_hid = BNXT_ULP_CLASS_HID_636ab, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [967] = { - .class_hid = BNXT_ULP_CLASS_HID_1cba3, + .class_hid = BNXT_ULP_CLASS_HID_630ef, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [968] = { - .class_hid = BNXT_ULP_CLASS_HID_1eee3, + .class_hid = BNXT_ULP_CLASS_HID_63d67, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [969] = { - .class_hid = BNXT_ULP_CLASS_HID_d3b7, + .class_hid = BNXT_ULP_CLASS_HID_606bf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [970] = { - .class_hid = BNXT_ULP_CLASS_HID_f6f7, + .class_hid = BNXT_ULP_CLASS_HID_61337, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [971] = { - .class_hid = BNXT_ULP_CLASS_HID_d937, + .class_hid = BNXT_ULP_CLASS_HID_60d7b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [972] = { - .class_hid = BNXT_ULP_CLASS_HID_fc77, + .class_hid = BNXT_ULP_CLASS_HID_619f3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [973] = { - .class_hid = BNXT_ULP_CLASS_HID_cf7b, + .class_hid = BNXT_ULP_CLASS_HID_64e47, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [974] = { - .class_hid = BNXT_ULP_CLASS_HID_f1bb, + .class_hid = BNXT_ULP_CLASS_HID_65adf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [975] = { - .class_hid = BNXT_ULP_CLASS_HID_d4fb, + .class_hid = BNXT_ULP_CLASS_HID_65403, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [976] = { - .class_hid = BNXT_ULP_CLASS_HID_f73b, + .class_hid = BNXT_ULP_CLASS_HID_603af, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [977] = { - .class_hid = BNXT_ULP_CLASS_HID_1882f, + .class_hid = BNXT_ULP_CLASS_HID_62ca7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [978] = { - .class_hid = BNXT_ULP_CLASS_HID_1ab6f, + .class_hid = BNXT_ULP_CLASS_HID_6393f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [979] = { - .class_hid = BNXT_ULP_CLASS_HID_1cdaf, + .class_hid = BNXT_ULP_CLASS_HID_63363, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [980] = { - .class_hid = BNXT_ULP_CLASS_HID_1f0ef, + .class_hid = BNXT_ULP_CLASS_HID_63ffb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [981] = { - .class_hid = BNXT_ULP_CLASS_HID_18d7b, + .class_hid = BNXT_ULP_CLASS_HID_61703, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [982] = { - .class_hid = BNXT_ULP_CLASS_HID_1afbb, + .class_hid = BNXT_ULP_CLASS_HID_6239b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [983] = { - .class_hid = BNXT_ULP_CLASS_HID_1d2fb, + .class_hid = BNXT_ULP_CLASS_HID_61ddf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [984] = { - .class_hid = BNXT_ULP_CLASS_HID_1f53b, + .class_hid = BNXT_ULP_CLASS_HID_62a57, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [985] = { - .class_hid = BNXT_ULP_CLASS_HID_9a8f, + .class_hid = BNXT_ULP_CLASS_HID_650db, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [986] = { - .class_hid = BNXT_ULP_CLASS_HID_bdcf, + .class_hid = BNXT_ULP_CLASS_HID_60067, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [987] = { - .class_hid = BNXT_ULP_CLASS_HID_e00f, + .class_hid = BNXT_ULP_CLASS_HID_65697, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [988] = { - .class_hid = BNXT_ULP_CLASS_HID_e34f, + .class_hid = BNXT_ULP_CLASS_HID_60623, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [989] = { - .class_hid = BNXT_ULP_CLASS_HID_95b3, + .class_hid = BNXT_ULP_CLASS_HID_63ab7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [990] = { - .class_hid = BNXT_ULP_CLASS_HID_b8f3, + .class_hid = BNXT_ULP_CLASS_HID_6470f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [991] = { - .class_hid = BNXT_ULP_CLASS_HID_db33, + .class_hid = BNXT_ULP_CLASS_HID_64173, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [992] = { - .class_hid = BNXT_ULP_CLASS_HID_fe73, + .class_hid = BNXT_ULP_CLASS_HID_64dcb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [993] = { - .class_hid = BNXT_ULP_CLASS_HID_1abb3, + .class_hid = BNXT_ULP_CLASS_HID_35aa3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [994] = { - .class_hid = BNXT_ULP_CLASS_HID_1aef3, + .class_hid = BNXT_ULP_CLASS_HID_30acf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [995] = { - .class_hid = BNXT_ULP_CLASS_HID_1f133, + .class_hid = BNXT_ULP_CLASS_HID_30433, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [996] = { - .class_hid = BNXT_ULP_CLASS_HID_1f473, + .class_hid = BNXT_ULP_CLASS_HID_3108b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [997] = { - .class_hid = BNXT_ULP_CLASS_HID_1b08f, + .class_hid = BNXT_ULP_CLASS_HID_3451f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [998] = { - .class_hid = BNXT_ULP_CLASS_HID_1b3cf, + .class_hid = BNXT_ULP_CLASS_HID_35197, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [999] = { - .class_hid = BNXT_ULP_CLASS_HID_1f60f, + .class_hid = BNXT_ULP_CLASS_HID_34bdb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1000] = { - .class_hid = BNXT_ULP_CLASS_HID_1f94f, + .class_hid = BNXT_ULP_CLASS_HID_35853, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1001] = { - .class_hid = BNXT_ULP_CLASS_HID_be13, + .class_hid = BNXT_ULP_CLASS_HID_321eb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1002] = { - .class_hid = BNXT_ULP_CLASS_HID_e153, + .class_hid = BNXT_ULP_CLASS_HID_32e63, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1003] = { - .class_hid = BNXT_ULP_CLASS_HID_c393, + .class_hid = BNXT_ULP_CLASS_HID_327a7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1004] = { - .class_hid = BNXT_ULP_CLASS_HID_e6d3, + .class_hid = BNXT_ULP_CLASS_HID_3343f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1005] = { - .class_hid = BNXT_ULP_CLASS_HID_b9c7, + .class_hid = BNXT_ULP_CLASS_HID_30c47, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1006] = { - .class_hid = BNXT_ULP_CLASS_HID_bc07, + .class_hid = BNXT_ULP_CLASS_HID_318df, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1007] = { - .class_hid = BNXT_ULP_CLASS_HID_ff47, + .class_hid = BNXT_ULP_CLASS_HID_31203, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1008] = { - .class_hid = BNXT_ULP_CLASS_HID_e187, + .class_hid = BNXT_ULP_CLASS_HID_31e9b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1009] = { - .class_hid = BNXT_ULP_CLASS_HID_1cfc7, + .class_hid = BNXT_ULP_CLASS_HID_34793, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1010] = { - .class_hid = BNXT_ULP_CLASS_HID_1f207, + .class_hid = BNXT_ULP_CLASS_HID_3546b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1011] = { - .class_hid = BNXT_ULP_CLASS_HID_1d547, + .class_hid = BNXT_ULP_CLASS_HID_34daf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1012] = { - .class_hid = BNXT_ULP_CLASS_HID_1f787, + .class_hid = BNXT_ULP_CLASS_HID_35a27, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1013] = { - .class_hid = BNXT_ULP_CLASS_HID_1d413, + .class_hid = BNXT_ULP_CLASS_HID_3324f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1014] = { - .class_hid = BNXT_ULP_CLASS_HID_1f753, + .class_hid = BNXT_ULP_CLASS_HID_33ec7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1015] = { - .class_hid = BNXT_ULP_CLASS_HID_1d993, + .class_hid = BNXT_ULP_CLASS_HID_3380b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1016] = { - .class_hid = BNXT_ULP_CLASS_HID_1fcd3, + .class_hid = BNXT_ULP_CLASS_HID_34483, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1017] = { - .class_hid = BNXT_ULP_CLASS_HID_aa67, + .class_hid = BNXT_ULP_CLASS_HID_30edb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1018] = { - .class_hid = BNXT_ULP_CLASS_HID_aca7, + .class_hid = BNXT_ULP_CLASS_HID_31b53, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1019] = { - .class_hid = BNXT_ULP_CLASS_HID_efe7, + .class_hid = BNXT_ULP_CLASS_HID_31497, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1020] = { - .class_hid = BNXT_ULP_CLASS_HID_f227, + .class_hid = BNXT_ULP_CLASS_HID_3216f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1021] = { - .class_hid = BNXT_ULP_CLASS_HID_a52b, + .class_hid = BNXT_ULP_CLASS_HID_355e3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1022] = { - .class_hid = BNXT_ULP_CLASS_HID_a86b, + .class_hid = BNXT_ULP_CLASS_HID_3050f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1023] = { - .class_hid = BNXT_ULP_CLASS_HID_eaab, + .class_hid = BNXT_ULP_CLASS_HID_35bbf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1024] = { - .class_hid = BNXT_ULP_CLASS_HID_edeb, + .class_hid = BNXT_ULP_CLASS_HID_30bcb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1025] = { - .class_hid = BNXT_ULP_CLASS_HID_1bb2b, + .class_hid = BNXT_ULP_CLASS_HID_75677, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1026] = { - .class_hid = BNXT_ULP_CLASS_HID_1be6b, + .class_hid = BNXT_ULP_CLASS_HID_70583, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1027] = { - .class_hid = BNXT_ULP_CLASS_HID_1c0ab, + .class_hid = BNXT_ULP_CLASS_HID_75c33, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1028] = { - .class_hid = BNXT_ULP_CLASS_HID_1e3eb, + .class_hid = BNXT_ULP_CLASS_HID_70c5f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1029] = { - .class_hid = BNXT_ULP_CLASS_HID_1c067, + .class_hid = BNXT_ULP_CLASS_HID_740d3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1030] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2a7, + .class_hid = BNXT_ULP_CLASS_HID_74cab, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1031] = { - .class_hid = BNXT_ULP_CLASS_HID_1c5e7, + .class_hid = BNXT_ULP_CLASS_HID_746ef, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1032] = { - .class_hid = BNXT_ULP_CLASS_HID_1e827, + .class_hid = BNXT_ULP_CLASS_HID_75367, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1033] = { - .class_hid = BNXT_ULP_CLASS_HID_cd8b, + .class_hid = BNXT_ULP_CLASS_HID_71cbf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1034] = { - .class_hid = BNXT_ULP_CLASS_HID_f0cb, + .class_hid = BNXT_ULP_CLASS_HID_72937, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1035] = { - .class_hid = BNXT_ULP_CLASS_HID_d30b, + .class_hid = BNXT_ULP_CLASS_HID_7237b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1036] = { - .class_hid = BNXT_ULP_CLASS_HID_f64b, + .class_hid = BNXT_ULP_CLASS_HID_72ff3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1037] = { - .class_hid = BNXT_ULP_CLASS_HID_c8bf, + .class_hid = BNXT_ULP_CLASS_HID_7071b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1038] = { - .class_hid = BNXT_ULP_CLASS_HID_ebff, + .class_hid = BNXT_ULP_CLASS_HID_71393, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1039] = { - .class_hid = BNXT_ULP_CLASS_HID_ce3f, + .class_hid = BNXT_ULP_CLASS_HID_70dd7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1040] = { - .class_hid = BNXT_ULP_CLASS_HID_f17f, + .class_hid = BNXT_ULP_CLASS_HID_719af, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1041] = { - .class_hid = BNXT_ULP_CLASS_HID_18263, + .class_hid = BNXT_ULP_CLASS_HID_742a7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1042] = { - .class_hid = BNXT_ULP_CLASS_HID_1a4a3, + .class_hid = BNXT_ULP_CLASS_HID_74f3f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1043] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7e3, + .class_hid = BNXT_ULP_CLASS_HID_74963, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1044] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea23, + .class_hid = BNXT_ULP_CLASS_HID_755fb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1045] = { - .class_hid = BNXT_ULP_CLASS_HID_186bf, + .class_hid = BNXT_ULP_CLASS_HID_72d03, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1046] = { - .class_hid = BNXT_ULP_CLASS_HID_1a9ff, + .class_hid = BNXT_ULP_CLASS_HID_7399b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1047] = { - .class_hid = BNXT_ULP_CLASS_HID_1cc3f, + .class_hid = BNXT_ULP_CLASS_HID_733df, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1048] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef7f, + .class_hid = BNXT_ULP_CLASS_HID_74057, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1049] = { - .class_hid = BNXT_ULP_CLASS_HID_94c3, + .class_hid = BNXT_ULP_CLASS_HID_709ef, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1050] = { - .class_hid = BNXT_ULP_CLASS_HID_b703, + .class_hid = BNXT_ULP_CLASS_HID_71667, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 108, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1051] = { - .class_hid = BNXT_ULP_CLASS_HID_da43, + .class_hid = BNXT_ULP_CLASS_HID_70fab, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 109, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1052] = { - .class_hid = BNXT_ULP_CLASS_HID_fc83, + .class_hid = BNXT_ULP_CLASS_HID_71c23, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 110, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1053] = { - .class_hid = BNXT_ULP_CLASS_HID_8ff7, + .class_hid = BNXT_ULP_CLASS_HID_750b7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 111, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1054] = { - .class_hid = BNXT_ULP_CLASS_HID_b237, + .class_hid = BNXT_ULP_CLASS_HID_700c3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 111, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1055] = { - .class_hid = BNXT_ULP_CLASS_HID_d577, + .class_hid = BNXT_ULP_CLASS_HID_75773, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 111, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1056] = { - .class_hid = BNXT_ULP_CLASS_HID_f7b7, + .class_hid = BNXT_ULP_CLASS_HID_7069f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 111, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1057] = { - .class_hid = BNXT_ULP_CLASS_HID_1a5f7, + .class_hid = BNXT_ULP_CLASS_HID_2cfa3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 111, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1058] = { - .class_hid = BNXT_ULP_CLASS_HID_1a837, + .class_hid = BNXT_ULP_CLASS_HID_2dc3b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 111, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1059] = { - .class_hid = BNXT_ULP_CLASS_HID_1eb77, + .class_hid = BNXT_ULP_CLASS_HID_2d67f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 112, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1060] = { - .class_hid = BNXT_ULP_CLASS_HID_1edb7, + .class_hid = BNXT_ULP_CLASS_HID_2858b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 113, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1061] = { - .class_hid = BNXT_ULP_CLASS_HID_1aac3, + .class_hid = BNXT_ULP_CLASS_HID_2ba1f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1062] = { - .class_hid = BNXT_ULP_CLASS_HID_1ad03, + .class_hid = BNXT_ULP_CLASS_HID_2c697, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1063] = { - .class_hid = BNXT_ULP_CLASS_HID_1f043, + .class_hid = BNXT_ULP_CLASS_HID_2c0db, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1064] = { - .class_hid = BNXT_ULP_CLASS_HID_1f283, + .class_hid = BNXT_ULP_CLASS_HID_2cd53, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1065] = { - .class_hid = BNXT_ULP_CLASS_HID_b857, + .class_hid = BNXT_ULP_CLASS_HID_296eb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1066] = { - .class_hid = BNXT_ULP_CLASS_HID_ba97, + .class_hid = BNXT_ULP_CLASS_HID_2a363, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1067] = { - .class_hid = BNXT_ULP_CLASS_HID_fdd7, + .class_hid = BNXT_ULP_CLASS_HID_29ca7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1068] = { - .class_hid = BNXT_ULP_CLASS_HID_e017, + .class_hid = BNXT_ULP_CLASS_HID_2a93f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1069] = { - .class_hid = BNXT_ULP_CLASS_HID_b31b, + .class_hid = BNXT_ULP_CLASS_HID_28147, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1070] = { - .class_hid = BNXT_ULP_CLASS_HID_b65b, + .class_hid = BNXT_ULP_CLASS_HID_28ddf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1071] = { - .class_hid = BNXT_ULP_CLASS_HID_f89b, + .class_hid = BNXT_ULP_CLASS_HID_28703, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1072] = { - .class_hid = BNXT_ULP_CLASS_HID_fbdb, + .class_hid = BNXT_ULP_CLASS_HID_2939b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1073] = { - .class_hid = BNXT_ULP_CLASS_HID_1c91b, + .class_hid = BNXT_ULP_CLASS_HID_2bc93, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1074] = { - .class_hid = BNXT_ULP_CLASS_HID_1ec5b, + .class_hid = BNXT_ULP_CLASS_HID_2c96b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1075] = { - .class_hid = BNXT_ULP_CLASS_HID_1ce9b, + .class_hid = BNXT_ULP_CLASS_HID_2c2af, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1076] = { - .class_hid = BNXT_ULP_CLASS_HID_1f1db, + .class_hid = BNXT_ULP_CLASS_HID_2cf27, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1077] = { - .class_hid = BNXT_ULP_CLASS_HID_1ce57, + .class_hid = BNXT_ULP_CLASS_HID_2a74f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1078] = { - .class_hid = BNXT_ULP_CLASS_HID_1f097, + .class_hid = BNXT_ULP_CLASS_HID_2b3c7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1079] = { - .class_hid = BNXT_ULP_CLASS_HID_1d3d7, + .class_hid = BNXT_ULP_CLASS_HID_2ad0b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1080] = { - .class_hid = BNXT_ULP_CLASS_HID_1f617, + .class_hid = BNXT_ULP_CLASS_HID_2b983, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1081] = { - .class_hid = BNXT_ULP_CLASS_HID_a3bb, + .class_hid = BNXT_ULP_CLASS_HID_283db, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1082] = { - .class_hid = BNXT_ULP_CLASS_HID_a6fb, + .class_hid = BNXT_ULP_CLASS_HID_29053, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1083] = { - .class_hid = BNXT_ULP_CLASS_HID_e93b, + .class_hid = BNXT_ULP_CLASS_HID_28997, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1084] = { - .class_hid = BNXT_ULP_CLASS_HID_ec7b, + .class_hid = BNXT_ULP_CLASS_HID_2966f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1085] = { - .class_hid = BNXT_ULP_CLASS_HID_9f6f, + .class_hid = BNXT_ULP_CLASS_HID_2cae3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1086] = { - .class_hid = BNXT_ULP_CLASS_HID_a1af, + .class_hid = BNXT_ULP_CLASS_HID_2d77b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1087] = { - .class_hid = BNXT_ULP_CLASS_HID_e4ef, + .class_hid = BNXT_ULP_CLASS_HID_2d0bf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1088] = { - .class_hid = BNXT_ULP_CLASS_HID_e72f, + .class_hid = BNXT_ULP_CLASS_HID_280cb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1089] = { - .class_hid = BNXT_ULP_CLASS_HID_1b56f, + .class_hid = BNXT_ULP_CLASS_HID_6cb77, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1090] = { - .class_hid = BNXT_ULP_CLASS_HID_1b7af, + .class_hid = BNXT_ULP_CLASS_HID_6d7cf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1091] = { - .class_hid = BNXT_ULP_CLASS_HID_1faef, + .class_hid = BNXT_ULP_CLASS_HID_6d133, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1092] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd2f, + .class_hid = BNXT_ULP_CLASS_HID_6815f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1093] = { - .class_hid = BNXT_ULP_CLASS_HID_1b9bb, + .class_hid = BNXT_ULP_CLASS_HID_6b5d3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1094] = { - .class_hid = BNXT_ULP_CLASS_HID_1bcfb, + .class_hid = BNXT_ULP_CLASS_HID_6c1ab, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1095] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff3b, + .class_hid = BNXT_ULP_CLASS_HID_6bbef, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1096] = { - .class_hid = BNXT_ULP_CLASS_HID_1e27b, + .class_hid = BNXT_ULP_CLASS_HID_6c867, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1097] = { - .class_hid = BNXT_ULP_CLASS_HID_c7cf, + .class_hid = BNXT_ULP_CLASS_HID_691bf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1098] = { - .class_hid = BNXT_ULP_CLASS_HID_ea0f, + .class_hid = BNXT_ULP_CLASS_HID_69e37, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1099] = { - .class_hid = BNXT_ULP_CLASS_HID_cd4f, + .class_hid = BNXT_ULP_CLASS_HID_6987b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1100] = { - .class_hid = BNXT_ULP_CLASS_HID_ef8f, + .class_hid = BNXT_ULP_CLASS_HID_6a4f3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1101] = { - .class_hid = BNXT_ULP_CLASS_HID_c2f3, + .class_hid = BNXT_ULP_CLASS_HID_6d947, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1102] = { - .class_hid = BNXT_ULP_CLASS_HID_e533, + .class_hid = BNXT_ULP_CLASS_HID_68893, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1103] = { - .class_hid = BNXT_ULP_CLASS_HID_c873, + .class_hid = BNXT_ULP_CLASS_HID_682d7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1104] = { - .class_hid = BNXT_ULP_CLASS_HID_eab3, + .class_hid = BNXT_ULP_CLASS_HID_68eaf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1105] = { - .class_hid = BNXT_ULP_CLASS_HID_1d8f3, + .class_hid = BNXT_ULP_CLASS_HID_6b7a7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1106] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb33, + .class_hid = BNXT_ULP_CLASS_HID_6c43f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1107] = { - .class_hid = BNXT_ULP_CLASS_HID_1c127, + .class_hid = BNXT_ULP_CLASS_HID_6be63, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1108] = { - .class_hid = BNXT_ULP_CLASS_HID_1e467, + .class_hid = BNXT_ULP_CLASS_HID_6cafb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1109] = { - .class_hid = BNXT_ULP_CLASS_HID_180f3, + .class_hid = BNXT_ULP_CLASS_HID_6a203, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1110] = { - .class_hid = BNXT_ULP_CLASS_HID_1a333, + .class_hid = BNXT_ULP_CLASS_HID_6ae9b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1111] = { - .class_hid = BNXT_ULP_CLASS_HID_1c673, + .class_hid = BNXT_ULP_CLASS_HID_6a8df, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1112] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8b3, + .class_hid = BNXT_ULP_CLASS_HID_6b557, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1113] = { - .class_hid = BNXT_ULP_CLASS_HID_8e07, + .class_hid = BNXT_ULP_CLASS_HID_6dbdb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1114] = { - .class_hid = BNXT_ULP_CLASS_HID_b147, + .class_hid = BNXT_ULP_CLASS_HID_68b67, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1115] = { - .class_hid = BNXT_ULP_CLASS_HID_d387, + .class_hid = BNXT_ULP_CLASS_HID_684ab, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1116] = { - .class_hid = BNXT_ULP_CLASS_HID_f6c7, + .class_hid = BNXT_ULP_CLASS_HID_69123, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1117] = { - .class_hid = BNXT_ULP_CLASS_HID_89cb, + .class_hid = BNXT_ULP_CLASS_HID_6c5b7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1118] = { - .class_hid = BNXT_ULP_CLASS_HID_ac0b, + .class_hid = BNXT_ULP_CLASS_HID_6d20f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1119] = { - .class_hid = BNXT_ULP_CLASS_HID_cf4b, + .class_hid = BNXT_ULP_CLASS_HID_6cc73, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1120] = { - .class_hid = BNXT_ULP_CLASS_HID_f18b, + .class_hid = BNXT_ULP_CLASS_HID_6d8cb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1121] = { - .class_hid = BNXT_ULP_CLASS_HID_19fcb, + .class_hid = BNXT_ULP_CLASS_HID_38977, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1122] = { - .class_hid = BNXT_ULP_CLASS_HID_1a20b, + .class_hid = BNXT_ULP_CLASS_HID_395cf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1123] = { - .class_hid = BNXT_ULP_CLASS_HID_1e54b, + .class_hid = BNXT_ULP_CLASS_HID_38f33, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1124] = { - .class_hid = BNXT_ULP_CLASS_HID_1e78b, + .class_hid = BNXT_ULP_CLASS_HID_39b8b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1125] = { - .class_hid = BNXT_ULP_CLASS_HID_1a407, + .class_hid = BNXT_ULP_CLASS_HID_3d01f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1126] = { - .class_hid = BNXT_ULP_CLASS_HID_1a747, + .class_hid = BNXT_ULP_CLASS_HID_3dc97, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1127] = { - .class_hid = BNXT_ULP_CLASS_HID_1e987, + .class_hid = BNXT_ULP_CLASS_HID_3d6db, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1128] = { - .class_hid = BNXT_ULP_CLASS_HID_1ecc7, + .class_hid = BNXT_ULP_CLASS_HID_38667, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1129] = { - .class_hid = BNXT_ULP_CLASS_HID_b1ab, + .class_hid = BNXT_ULP_CLASS_HID_3aceb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1130] = { - .class_hid = BNXT_ULP_CLASS_HID_b4eb, + .class_hid = BNXT_ULP_CLASS_HID_3b963, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1131] = { - .class_hid = BNXT_ULP_CLASS_HID_f72b, + .class_hid = BNXT_ULP_CLASS_HID_3b2a7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1132] = { - .class_hid = BNXT_ULP_CLASS_HID_fa6b, + .class_hid = BNXT_ULP_CLASS_HID_3bf3f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1133] = { - .class_hid = BNXT_ULP_CLASS_HID_ad5f, + .class_hid = BNXT_ULP_CLASS_HID_39747, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1134] = { - .class_hid = BNXT_ULP_CLASS_HID_af9f, + .class_hid = BNXT_ULP_CLASS_HID_3a3df, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1135] = { - .class_hid = BNXT_ULP_CLASS_HID_f2df, + .class_hid = BNXT_ULP_CLASS_HID_39d03, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1136] = { - .class_hid = BNXT_ULP_CLASS_HID_f51f, + .class_hid = BNXT_ULP_CLASS_HID_3a99b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1137] = { - .class_hid = BNXT_ULP_CLASS_HID_1c35f, + .class_hid = BNXT_ULP_CLASS_HID_3d293, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1138] = { - .class_hid = BNXT_ULP_CLASS_HID_1e59f, + .class_hid = BNXT_ULP_CLASS_HID_3823f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1139] = { - .class_hid = BNXT_ULP_CLASS_HID_1c8df, + .class_hid = BNXT_ULP_CLASS_HID_3d8af, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1140] = { - .class_hid = BNXT_ULP_CLASS_HID_1eb1f, + .class_hid = BNXT_ULP_CLASS_HID_388fb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1141] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7ab, + .class_hid = BNXT_ULP_CLASS_HID_3bd4f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1142] = { - .class_hid = BNXT_ULP_CLASS_HID_1eaeb, + .class_hid = BNXT_ULP_CLASS_HID_3c9c7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1143] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd2b, + .class_hid = BNXT_ULP_CLASS_HID_3c30b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1144] = { - .class_hid = BNXT_ULP_CLASS_HID_1f06b, + .class_hid = BNXT_ULP_CLASS_HID_3cf83, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, + .hdr_sig_id = 10, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1145] = { - .class_hid = BNXT_ULP_CLASS_HID_9177, + .class_hid = BNXT_ULP_CLASS_HID_399db, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1146] = { - .class_hid = BNXT_ULP_CLASS_HID_b3b7, + .class_hid = BNXT_ULP_CLASS_HID_3a653, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1147] = { - .class_hid = BNXT_ULP_CLASS_HID_d6f7, + .class_hid = BNXT_ULP_CLASS_HID_39f97, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1148] = { - .class_hid = BNXT_ULP_CLASS_HID_f937, + .class_hid = BNXT_ULP_CLASS_HID_3ac6f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1149] = { - .class_hid = BNXT_ULP_CLASS_HID_8c3b, + .class_hid = BNXT_ULP_CLASS_HID_383b7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1150] = { - .class_hid = BNXT_ULP_CLASS_HID_af7b, + .class_hid = BNXT_ULP_CLASS_HID_3900f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229448, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1151] = { - .class_hid = BNXT_ULP_CLASS_HID_d1bb, + .class_hid = BNXT_ULP_CLASS_HID_38a73, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1152] = { - .class_hid = BNXT_ULP_CLASS_HID_f4fb, + .class_hid = BNXT_ULP_CLASS_HID_396cb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229448, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1153] = { - .class_hid = BNXT_ULP_CLASS_HID_1a23b, + .class_hid = BNXT_ULP_CLASS_HID_7840b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1154] = { - .class_hid = BNXT_ULP_CLASS_HID_1a57b, + .class_hid = BNXT_ULP_CLASS_HID_79083, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1155] = { - .class_hid = BNXT_ULP_CLASS_HID_1e7bb, + .class_hid = BNXT_ULP_CLASS_HID_78ac7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1156] = { - .class_hid = BNXT_ULP_CLASS_HID_1eafb, + .class_hid = BNXT_ULP_CLASS_HID_7975f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1157] = { - .class_hid = BNXT_ULP_CLASS_HID_1a777, + .class_hid = BNXT_ULP_CLASS_HID_7cbd3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1158] = { - .class_hid = BNXT_ULP_CLASS_HID_1a9b7, + .class_hid = BNXT_ULP_CLASS_HID_7d7ab, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1159] = { - .class_hid = BNXT_ULP_CLASS_HID_1ecf7, + .class_hid = BNXT_ULP_CLASS_HID_7d1ef, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1160] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef37, + .class_hid = BNXT_ULP_CLASS_HID_7813b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1161] = { - .class_hid = BNXT_ULP_CLASS_HID_b49b, + .class_hid = BNXT_ULP_CLASS_HID_7a7bf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1162] = { - .class_hid = BNXT_ULP_CLASS_HID_b7db, + .class_hid = BNXT_ULP_CLASS_HID_7b437, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1163] = { - .class_hid = BNXT_ULP_CLASS_HID_fa1b, + .class_hid = BNXT_ULP_CLASS_HID_7ae7b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1164] = { - .class_hid = BNXT_ULP_CLASS_HID_fd5b, + .class_hid = BNXT_ULP_CLASS_HID_7baf3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1165] = { - .class_hid = BNXT_ULP_CLASS_HID_b04f, + .class_hid = BNXT_ULP_CLASS_HID_7921b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1166] = { - .class_hid = BNXT_ULP_CLASS_HID_b28f, + .class_hid = BNXT_ULP_CLASS_HID_79e93, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1167] = { - .class_hid = BNXT_ULP_CLASS_HID_f5cf, + .class_hid = BNXT_ULP_CLASS_HID_798d7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1168] = { - .class_hid = BNXT_ULP_CLASS_HID_f80f, + .class_hid = BNXT_ULP_CLASS_HID_7a4af, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1169] = { - .class_hid = BNXT_ULP_CLASS_HID_1c64f, + .class_hid = BNXT_ULP_CLASS_HID_7cda7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1170] = { - .class_hid = BNXT_ULP_CLASS_HID_1e88f, + .class_hid = BNXT_ULP_CLASS_HID_7da3f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1171] = { - .class_hid = BNXT_ULP_CLASS_HID_1cbcf, + .class_hid = BNXT_ULP_CLASS_HID_7d463, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1172] = { - .class_hid = BNXT_ULP_CLASS_HID_1ee0f, + .class_hid = BNXT_ULP_CLASS_HID_7838f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1173] = { - .class_hid = BNXT_ULP_CLASS_HID_1ca9b, + .class_hid = BNXT_ULP_CLASS_HID_7b803, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1174] = { - .class_hid = BNXT_ULP_CLASS_HID_1eddb, + .class_hid = BNXT_ULP_CLASS_HID_7c49b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1175] = { - .class_hid = BNXT_ULP_CLASS_HID_1d01b, + .class_hid = BNXT_ULP_CLASS_HID_7bedf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1176] = { - .class_hid = BNXT_ULP_CLASS_HID_1f35b, + .class_hid = BNXT_ULP_CLASS_HID_7cb57, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1177] = { - .class_hid = BNXT_ULP_CLASS_HID_8b4b, + .class_hid = BNXT_ULP_CLASS_HID_794ef, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1178] = { - .class_hid = BNXT_ULP_CLASS_HID_ad8b, + .class_hid = BNXT_ULP_CLASS_HID_7a167, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1179] = { - .class_hid = BNXT_ULP_CLASS_HID_d0cb, + .class_hid = BNXT_ULP_CLASS_HID_79aab, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1180] = { - .class_hid = BNXT_ULP_CLASS_HID_f30b, + .class_hid = BNXT_ULP_CLASS_HID_7a723, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1181] = { - .class_hid = BNXT_ULP_CLASS_HID_867f, + .class_hid = BNXT_ULP_CLASS_HID_7dbb7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1182] = { - .class_hid = BNXT_ULP_CLASS_HID_a8bf, + .class_hid = BNXT_ULP_CLASS_HID_78bc3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1183] = { - .class_hid = BNXT_ULP_CLASS_HID_cbff, + .class_hid = BNXT_ULP_CLASS_HID_78507, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1184] = { - .class_hid = BNXT_ULP_CLASS_HID_ee3f, + .class_hid = BNXT_ULP_CLASS_HID_7919f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1185] = { - .class_hid = BNXT_ULP_CLASS_HID_19c7f, + .class_hid = BNXT_ULP_CLASS_HID_a3bb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27125,17 +28565,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1186] = { - .class_hid = BNXT_ULP_CLASS_HID_1bebf, + .class_hid = BNXT_ULP_CLASS_HID_b023, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27143,18 +28582,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1187] = { - .class_hid = BNXT_ULP_CLASS_HID_1e1ff, + .class_hid = BNXT_ULP_CLASS_HID_aa67, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27162,18 +28600,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1188] = { - .class_hid = BNXT_ULP_CLASS_HID_1e43f, + .class_hid = BNXT_ULP_CLASS_HID_b6ef, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27181,19 +28618,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1189] = { - .class_hid = BNXT_ULP_CLASS_HID_1a14b, + .class_hid = BNXT_ULP_CLASS_HID_8e07, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27201,16 +28637,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1190] = { - .class_hid = BNXT_ULP_CLASS_HID_1a38b, + .class_hid = BNXT_ULP_CLASS_HID_9a8f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27218,17 +28655,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1191] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6cb, + .class_hid = BNXT_ULP_CLASS_HID_94c3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27236,17 +28674,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1192] = { - .class_hid = BNXT_ULP_CLASS_HID_1e90b, + .class_hid = BNXT_ULP_CLASS_HID_a14b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27254,18 +28693,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1193] = { - .class_hid = BNXT_ULP_CLASS_HID_aedf, + .class_hid = BNXT_ULP_CLASS_HID_c7cf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27273,16 +28713,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1194] = { - .class_hid = BNXT_ULP_CLASS_HID_b11f, + .class_hid = BNXT_ULP_CLASS_HID_d3b7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27290,17 +28731,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1195] = { - .class_hid = BNXT_ULP_CLASS_HID_f45f, + .class_hid = BNXT_ULP_CLASS_HID_cd8b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27308,17 +28750,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1196] = { - .class_hid = BNXT_ULP_CLASS_HID_f69f, + .class_hid = BNXT_ULP_CLASS_HID_da73, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27326,18 +28769,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1197] = { - .class_hid = BNXT_ULP_CLASS_HID_a983, + .class_hid = BNXT_ULP_CLASS_HID_b1ab, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27345,17 +28789,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1198] = { - .class_hid = BNXT_ULP_CLASS_HID_acc3, + .class_hid = BNXT_ULP_CLASS_HID_be13, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27363,18 +28808,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1199] = { - .class_hid = BNXT_ULP_CLASS_HID_ef03, + .class_hid = BNXT_ULP_CLASS_HID_b857, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27382,18 +28828,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1200] = { - .class_hid = BNXT_ULP_CLASS_HID_f243, + .class_hid = BNXT_ULP_CLASS_HID_c4df, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27401,19 +28848,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1201] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf83, + .class_hid = BNXT_ULP_CLASS_HID_49f6f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27421,18 +28869,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1202] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2c3, + .class_hid = BNXT_ULP_CLASS_HID_4abd7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27440,19 +28887,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1203] = { - .class_hid = BNXT_ULP_CLASS_HID_1c503, + .class_hid = BNXT_ULP_CLASS_HID_4a52b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27460,19 +28906,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1204] = { - .class_hid = BNXT_ULP_CLASS_HID_1e843, + .class_hid = BNXT_ULP_CLASS_HID_4b193, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27480,20 +28925,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1205] = { - .class_hid = BNXT_ULP_CLASS_HID_1c4df, + .class_hid = BNXT_ULP_CLASS_HID_489cb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27501,17 +28945,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1206] = { - .class_hid = BNXT_ULP_CLASS_HID_1e71f, + .class_hid = BNXT_ULP_CLASS_HID_495b3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27519,18 +28964,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1207] = { - .class_hid = BNXT_ULP_CLASS_HID_1ca5f, + .class_hid = BNXT_ULP_CLASS_HID_48ff7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27538,18 +28984,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1208] = { - .class_hid = BNXT_ULP_CLASS_HID_1ec9f, + .class_hid = BNXT_ULP_CLASS_HID_49c7f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27557,19 +29004,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1209] = { - .class_hid = BNXT_ULP_CLASS_HID_2523, + .class_hid = BNXT_ULP_CLASS_HID_4c2f3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27577,16 +29025,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1210] = { - .class_hid = BNXT_ULP_CLASS_HID_2bef, + .class_hid = BNXT_ULP_CLASS_HID_4cf7b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27594,17 +29044,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1211] = { - .class_hid = BNXT_ULP_CLASS_HID_2693, + .class_hid = BNXT_ULP_CLASS_HID_4c8bf, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27612,18 +29064,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1212] = { - .class_hid = BNXT_ULP_CLASS_HID_4f73, + .class_hid = BNXT_ULP_CLASS_HID_4d527, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131080, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27631,18 +29084,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1213] = { - .class_hid = BNXT_ULP_CLASS_HID_4a27, + .class_hid = BNXT_ULP_CLASS_HID_4ad5f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27650,19 +29105,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1214] = { - .class_hid = BNXT_ULP_CLASS_HID_164b, + .class_hid = BNXT_ULP_CLASS_HID_4b9c7, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27670,18 +29125,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1215] = { - .class_hid = BNXT_ULP_CLASS_HID_117f, + .class_hid = BNXT_ULP_CLASS_HID_4b31b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27689,19 +29146,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1216] = { - .class_hid = BNXT_ULP_CLASS_HID_39df, + .class_hid = BNXT_ULP_CLASS_HID_4bf83, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27709,19 +29167,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1217] = { - .class_hid = BNXT_ULP_CLASS_HID_3483, + .class_hid = BNXT_ULP_CLASS_HID_1b9bb, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27729,20 +29189,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1218] = { - .class_hid = BNXT_ULP_CLASS_HID_20d7, + .class_hid = BNXT_ULP_CLASS_HID_1c623, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196616, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27750,17 +29207,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1219] = { - .class_hid = BNXT_ULP_CLASS_HID_48b7, + .class_hid = BNXT_ULP_CLASS_HID_1c067, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27768,17 +29226,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1220] = { - .class_hid = BNXT_ULP_CLASS_HID_447b, + .class_hid = BNXT_ULP_CLASS_HID_1ccef, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196616, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27786,18 +29245,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1221] = { - .class_hid = BNXT_ULP_CLASS_HID_0f8f, + .class_hid = BNXT_ULP_CLASS_HID_1a407, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27805,17 +29265,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1222] = { - .class_hid = BNXT_ULP_CLASS_HID_0ab3, + .class_hid = BNXT_ULP_CLASS_HID_1b08f, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27823,18 +29284,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1223] = { - .class_hid = BNXT_ULP_CLASS_HID_3313, + .class_hid = BNXT_ULP_CLASS_HID_1aac3, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27842,18 +29304,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1224] = { - .class_hid = BNXT_ULP_CLASS_HID_2ec7, + .class_hid = BNXT_ULP_CLASS_HID_1b74b, .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196680, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -27861,8539 +29324,8224 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1225] = { - .class_hid = BNXT_ULP_CLASS_HID_257b7, + .class_hid = BNXT_ULP_CLASS_HID_180f3, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1226] = { - .class_hid = BNXT_ULP_CLASS_HID_24467, + .class_hid = BNXT_ULP_CLASS_HID_18d7b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1227] = { - .class_hid = BNXT_ULP_CLASS_HID_23fbb, + .class_hid = BNXT_ULP_CLASS_HID_186bf, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1228] = { - .class_hid = BNXT_ULP_CLASS_HID_252cb, + .class_hid = BNXT_ULP_CLASS_HID_19327, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1229] = { - .class_hid = BNXT_ULP_CLASS_HID_21e7f, + .class_hid = BNXT_ULP_CLASS_HID_1c7ab, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1230] = { - .class_hid = BNXT_ULP_CLASS_HID_20b2f, + .class_hid = BNXT_ULP_CLASS_HID_1d413, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1231] = { - .class_hid = BNXT_ULP_CLASS_HID_20663, + .class_hid = BNXT_ULP_CLASS_HID_1ce57, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1232] = { - .class_hid = BNXT_ULP_CLASS_HID_219b3, + .class_hid = BNXT_ULP_CLASS_HID_1dadf, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1233] = { - .class_hid = BNXT_ULP_CLASS_HID_24213, + .class_hid = BNXT_ULP_CLASS_HID_5b56f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 114, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1234] = { - .class_hid = BNXT_ULP_CLASS_HID_22ec3, + .class_hid = BNXT_ULP_CLASS_HID_5c1d7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 115, + .hdr_sig_id = 11, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1235] = { - .class_hid = BNXT_ULP_CLASS_HID_22a17, + .class_hid = BNXT_ULP_CLASS_HID_5bb2b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 115, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1236] = { - .class_hid = BNXT_ULP_CLASS_HID_23d27, + .class_hid = BNXT_ULP_CLASS_HID_5c793, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1237] = { - .class_hid = BNXT_ULP_CLASS_HID_208db, + .class_hid = BNXT_ULP_CLASS_HID_59fcb, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1238] = { - .class_hid = BNXT_ULP_CLASS_HID_25277, + .class_hid = BNXT_ULP_CLASS_HID_5abb3, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1239] = { - .class_hid = BNXT_ULP_CLASS_HID_24d8b, + .class_hid = BNXT_ULP_CLASS_HID_5a5f7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1240] = { - .class_hid = BNXT_ULP_CLASS_HID_203ef, + .class_hid = BNXT_ULP_CLASS_HID_5b27f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1241] = { - .class_hid = BNXT_ULP_CLASS_HID_2517b, + .class_hid = BNXT_ULP_CLASS_HID_5d8f3, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1242] = { - .class_hid = BNXT_ULP_CLASS_HID_23e2b, + .class_hid = BNXT_ULP_CLASS_HID_5882f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1243] = { - .class_hid = BNXT_ULP_CLASS_HID_2397f, + .class_hid = BNXT_ULP_CLASS_HID_58263, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1244] = { - .class_hid = BNXT_ULP_CLASS_HID_24c8f, + .class_hid = BNXT_ULP_CLASS_HID_58eeb, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1245] = { - .class_hid = BNXT_ULP_CLASS_HID_21823, + .class_hid = BNXT_ULP_CLASS_HID_5c35f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1246] = { - .class_hid = BNXT_ULP_CLASS_HID_20513, + .class_hid = BNXT_ULP_CLASS_HID_5cfc7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1247] = { - .class_hid = BNXT_ULP_CLASS_HID_20027, + .class_hid = BNXT_ULP_CLASS_HID_5c91b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1248] = { - .class_hid = BNXT_ULP_CLASS_HID_21377, + .class_hid = BNXT_ULP_CLASS_HID_5d583, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1249] = { - .class_hid = BNXT_ULP_CLASS_HID_23bd7, + .class_hid = BNXT_ULP_CLASS_HID_e93b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1250] = { - .class_hid = BNXT_ULP_CLASS_HID_22887, + .class_hid = BNXT_ULP_CLASS_HID_f5a3, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1251] = { - .class_hid = BNXT_ULP_CLASS_HID_223db, + .class_hid = BNXT_ULP_CLASS_HID_efe7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1252] = { - .class_hid = BNXT_ULP_CLASS_HID_236eb, + .class_hid = BNXT_ULP_CLASS_HID_fc6f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1253] = { - .class_hid = BNXT_ULP_CLASS_HID_2029f, + .class_hid = BNXT_ULP_CLASS_HID_d387, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1254] = { - .class_hid = BNXT_ULP_CLASS_HID_24c3b, + .class_hid = BNXT_ULP_CLASS_HID_e00f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1255] = { - .class_hid = BNXT_ULP_CLASS_HID_2474f, + .class_hid = BNXT_ULP_CLASS_HID_da43, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1256] = { - .class_hid = BNXT_ULP_CLASS_HID_25a9f, + .class_hid = BNXT_ULP_CLASS_HID_e6cb, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1257] = { - .class_hid = BNXT_ULP_CLASS_HID_24b3f, + .class_hid = BNXT_ULP_CLASS_HID_cd4f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1258] = { - .class_hid = BNXT_ULP_CLASS_HID_237ef, + .class_hid = BNXT_ULP_CLASS_HID_d937, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1259] = { - .class_hid = BNXT_ULP_CLASS_HID_23323, + .class_hid = BNXT_ULP_CLASS_HID_d30b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1260] = { - .class_hid = BNXT_ULP_CLASS_HID_24673, + .class_hid = BNXT_ULP_CLASS_HID_c2a7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1261] = { - .class_hid = BNXT_ULP_CLASS_HID_211e7, + .class_hid = BNXT_ULP_CLASS_HID_f72b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1262] = { - .class_hid = BNXT_ULP_CLASS_HID_25b83, + .class_hid = BNXT_ULP_CLASS_HID_c393, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1263] = { - .class_hid = BNXT_ULP_CLASS_HID_256d7, + .class_hid = BNXT_ULP_CLASS_HID_fdd7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1264] = { - .class_hid = BNXT_ULP_CLASS_HID_20d3b, + .class_hid = BNXT_ULP_CLASS_HID_ca5f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1265] = { - .class_hid = BNXT_ULP_CLASS_HID_2359b, + .class_hid = BNXT_ULP_CLASS_HID_4e4ef, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 116, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1266] = { - .class_hid = BNXT_ULP_CLASS_HID_2224b, + .class_hid = BNXT_ULP_CLASS_HID_4f157, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 117, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1267] = { - .class_hid = BNXT_ULP_CLASS_HID_21d9f, + .class_hid = BNXT_ULP_CLASS_HID_4eaab, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 117, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1268] = { - .class_hid = BNXT_ULP_CLASS_HID_230af, + .class_hid = BNXT_ULP_CLASS_HID_4f713, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1269] = { - .class_hid = BNXT_ULP_CLASS_HID_2590f, + .class_hid = BNXT_ULP_CLASS_HID_4cf4b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1270] = { - .class_hid = BNXT_ULP_CLASS_HID_245ff, + .class_hid = BNXT_ULP_CLASS_HID_4db33, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1271] = { - .class_hid = BNXT_ULP_CLASS_HID_24133, + .class_hid = BNXT_ULP_CLASS_HID_4d577, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1272] = { - .class_hid = BNXT_ULP_CLASS_HID_25443, + .class_hid = BNXT_ULP_CLASS_HID_4e1ff, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1273] = { - .class_hid = BNXT_ULP_CLASS_HID_244e3, + .class_hid = BNXT_ULP_CLASS_HID_4c873, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1274] = { - .class_hid = BNXT_ULP_CLASS_HID_231d3, + .class_hid = BNXT_ULP_CLASS_HID_4d4fb, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1275] = { - .class_hid = BNXT_ULP_CLASS_HID_22ce7, + .class_hid = BNXT_ULP_CLASS_HID_4ce3f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1276] = { - .class_hid = BNXT_ULP_CLASS_HID_24037, + .class_hid = BNXT_ULP_CLASS_HID_4daa7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1277] = { - .class_hid = BNXT_ULP_CLASS_HID_20bab, + .class_hid = BNXT_ULP_CLASS_HID_4f2df, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1278] = { - .class_hid = BNXT_ULP_CLASS_HID_25547, + .class_hid = BNXT_ULP_CLASS_HID_4ff47, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1279] = { - .class_hid = BNXT_ULP_CLASS_HID_2509b, + .class_hid = BNXT_ULP_CLASS_HID_4f89b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1280] = { - .class_hid = BNXT_ULP_CLASS_HID_206ff, + .class_hid = BNXT_ULP_CLASS_HID_4c503, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1281] = { - .class_hid = BNXT_ULP_CLASS_HID_22f5f, + .class_hid = BNXT_ULP_CLASS_HID_1ff3b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1282] = { - .class_hid = BNXT_ULP_CLASS_HID_21c0f, + .class_hid = BNXT_ULP_CLASS_HID_1cba3, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1283] = { - .class_hid = BNXT_ULP_CLASS_HID_21743, + .class_hid = BNXT_ULP_CLASS_HID_1c5e7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1284] = { - .class_hid = BNXT_ULP_CLASS_HID_22a93, + .class_hid = BNXT_ULP_CLASS_HID_1d26f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1285] = { - .class_hid = BNXT_ULP_CLASS_HID_252f3, + .class_hid = BNXT_ULP_CLASS_HID_1e987, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1286] = { - .class_hid = BNXT_ULP_CLASS_HID_23fa3, + .class_hid = BNXT_ULP_CLASS_HID_1f60f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1287] = { - .class_hid = BNXT_ULP_CLASS_HID_23af7, + .class_hid = BNXT_ULP_CLASS_HID_1f043, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1288] = { - .class_hid = BNXT_ULP_CLASS_HID_24e07, + .class_hid = BNXT_ULP_CLASS_HID_1fccb, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1289] = { - .class_hid = BNXT_ULP_CLASS_HID_2322f, + .class_hid = BNXT_ULP_CLASS_HID_1c673, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1290] = { - .class_hid = BNXT_ULP_CLASS_HID_21f1f, + .class_hid = BNXT_ULP_CLASS_HID_1d2fb, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1291] = { - .class_hid = BNXT_ULP_CLASS_HID_21a53, + .class_hid = BNXT_ULP_CLASS_HID_1cc3f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1292] = { - .class_hid = BNXT_ULP_CLASS_HID_22d63, + .class_hid = BNXT_ULP_CLASS_HID_1d8a7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1293] = { - .class_hid = BNXT_ULP_CLASS_HID_255c3, + .class_hid = BNXT_ULP_CLASS_HID_1cd2b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1294] = { - .class_hid = BNXT_ULP_CLASS_HID_242b3, + .class_hid = BNXT_ULP_CLASS_HID_1d993, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1295] = { - .class_hid = BNXT_ULP_CLASS_HID_23dc7, + .class_hid = BNXT_ULP_CLASS_HID_1d3d7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1296] = { - .class_hid = BNXT_ULP_CLASS_HID_25117, + .class_hid = BNXT_ULP_CLASS_HID_1c303, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1297] = { - .class_hid = BNXT_ULP_CLASS_HID_22c13, + .class_hid = BNXT_ULP_CLASS_HID_5faef, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1298] = { - .class_hid = BNXT_ULP_CLASS_HID_218c3, + .class_hid = BNXT_ULP_CLASS_HID_5c757, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1299] = { - .class_hid = BNXT_ULP_CLASS_HID_21417, + .class_hid = BNXT_ULP_CLASS_HID_5c0ab, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1300] = { - .class_hid = BNXT_ULP_CLASS_HID_22727, + .class_hid = BNXT_ULP_CLASS_HID_5cd13, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1301] = { - .class_hid = BNXT_ULP_CLASS_HID_24f87, + .class_hid = BNXT_ULP_CLASS_HID_5e54b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1302] = { - .class_hid = BNXT_ULP_CLASS_HID_23c77, + .class_hid = BNXT_ULP_CLASS_HID_5f133, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1303] = { - .class_hid = BNXT_ULP_CLASS_HID_2378b, + .class_hid = BNXT_ULP_CLASS_HID_5eb77, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1304] = { - .class_hid = BNXT_ULP_CLASS_HID_24adb, + .class_hid = BNXT_ULP_CLASS_HID_5f7ff, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1305] = { - .class_hid = BNXT_ULP_CLASS_HID_257b, + .class_hid = BNXT_ULP_CLASS_HID_5c127, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1306] = { - .class_hid = BNXT_ULP_CLASS_HID_2bb7, + .class_hid = BNXT_ULP_CLASS_HID_5cdaf, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1307] = { - .class_hid = BNXT_ULP_CLASS_HID_1867, + .class_hid = BNXT_ULP_CLASS_HID_5c7e3, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1308] = { - .class_hid = BNXT_ULP_CLASS_HID_4f2b, + .class_hid = BNXT_ULP_CLASS_HID_5d46b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1309] = { - .class_hid = BNXT_ULP_CLASS_HID_3c1b, + .class_hid = BNXT_ULP_CLASS_HID_5c8df, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1310] = { - .class_hid = BNXT_ULP_CLASS_HID_1613, + .class_hid = BNXT_ULP_CLASS_HID_5d547, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1311] = { - .class_hid = BNXT_ULP_CLASS_HID_02c3, + .class_hid = BNXT_ULP_CLASS_HID_5ce9b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1312] = { - .class_hid = BNXT_ULP_CLASS_HID_3987, + .class_hid = BNXT_ULP_CLASS_HID_5db03, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1313] = { - .class_hid = BNXT_ULP_CLASS_HID_2677, + .class_hid = BNXT_ULP_CLASS_HID_a6fb, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1314] = { - .class_hid = BNXT_ULP_CLASS_HID_122b, + .class_hid = BNXT_ULP_CLASS_HID_b363, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1315] = { - .class_hid = BNXT_ULP_CLASS_HID_48ef, + .class_hid = BNXT_ULP_CLASS_HID_aca7, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1316] = { - .class_hid = BNXT_ULP_CLASS_HID_35df, + .class_hid = BNXT_ULP_CLASS_HID_b92f, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1317] = { - .class_hid = BNXT_ULP_CLASS_HID_0fd7, + .class_hid = BNXT_ULP_CLASS_HID_b147, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1318] = { - .class_hid = BNXT_ULP_CLASS_HID_5973, + .class_hid = BNXT_ULP_CLASS_HID_bdcf, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655432, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1319] = { - .class_hid = BNXT_ULP_CLASS_HID_334b, + .class_hid = BNXT_ULP_CLASS_HID_b703, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1320] = { - .class_hid = BNXT_ULP_CLASS_HID_203b, + .class_hid = BNXT_ULP_CLASS_HID_a38b, .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 118, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655432, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1321] = { - .class_hid = BNXT_ULP_CLASS_HID_25797, + .class_hid = BNXT_ULP_CLASS_HID_ea0f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1322] = { - .class_hid = BNXT_ULP_CLASS_HID_285eb, + .class_hid = BNXT_ULP_CLASS_HID_f6f7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1323] = { - .class_hid = BNXT_ULP_CLASS_HID_310eb, + .class_hid = BNXT_ULP_CLASS_HID_f0cb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1324] = { - .class_hid = BNXT_ULP_CLASS_HID_39beb, + .class_hid = BNXT_ULP_CLASS_HID_a067, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1325] = { - .class_hid = BNXT_ULP_CLASS_HID_24447, + .class_hid = BNXT_ULP_CLASS_HID_b4eb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1326] = { - .class_hid = BNXT_ULP_CLASS_HID_2cf47, + .class_hid = BNXT_ULP_CLASS_HID_e153, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1327] = { - .class_hid = BNXT_ULP_CLASS_HID_35a47, + .class_hid = BNXT_ULP_CLASS_HID_ba97, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1328] = { - .class_hid = BNXT_ULP_CLASS_HID_3889b, + .class_hid = BNXT_ULP_CLASS_HID_e71f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1329] = { - .class_hid = BNXT_ULP_CLASS_HID_23f9b, + .class_hid = BNXT_ULP_CLASS_HID_4a1af, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1330] = { - .class_hid = BNXT_ULP_CLASS_HID_2ca9b, + .class_hid = BNXT_ULP_CLASS_HID_4ae17, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1331] = { - .class_hid = BNXT_ULP_CLASS_HID_3559b, + .class_hid = BNXT_ULP_CLASS_HID_4a86b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1332] = { - .class_hid = BNXT_ULP_CLASS_HID_383ef, + .class_hid = BNXT_ULP_CLASS_HID_4b4d3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1333] = { - .class_hid = BNXT_ULP_CLASS_HID_252eb, + .class_hid = BNXT_ULP_CLASS_HID_4ac0b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1334] = { - .class_hid = BNXT_ULP_CLASS_HID_2813f, + .class_hid = BNXT_ULP_CLASS_HID_4b8f3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1335] = { - .class_hid = BNXT_ULP_CLASS_HID_30c3f, + .class_hid = BNXT_ULP_CLASS_HID_4b237, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1336] = { - .class_hid = BNXT_ULP_CLASS_HID_3973f, + .class_hid = BNXT_ULP_CLASS_HID_4bebf, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1337] = { - .class_hid = BNXT_ULP_CLASS_HID_21e5f, + .class_hid = BNXT_ULP_CLASS_HID_4e533, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1338] = { - .class_hid = BNXT_ULP_CLASS_HID_2a95f, + .class_hid = BNXT_ULP_CLASS_HID_4f1bb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1339] = { - .class_hid = BNXT_ULP_CLASS_HID_3345f, + .class_hid = BNXT_ULP_CLASS_HID_4ebff, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1340] = { - .class_hid = BNXT_ULP_CLASS_HID_3bf5f, + .class_hid = BNXT_ULP_CLASS_HID_4f867, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1341] = { - .class_hid = BNXT_ULP_CLASS_HID_20b0f, + .class_hid = BNXT_ULP_CLASS_HID_4af9f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1342] = { - .class_hid = BNXT_ULP_CLASS_HID_2960f, + .class_hid = BNXT_ULP_CLASS_HID_4bc07, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1343] = { - .class_hid = BNXT_ULP_CLASS_HID_3210f, + .class_hid = BNXT_ULP_CLASS_HID_4b65b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1344] = { - .class_hid = BNXT_ULP_CLASS_HID_3ac0f, + .class_hid = BNXT_ULP_CLASS_HID_4e2c3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1345] = { - .class_hid = BNXT_ULP_CLASS_HID_20643, + .class_hid = BNXT_ULP_CLASS_HID_1bcfb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1346] = { - .class_hid = BNXT_ULP_CLASS_HID_29143, + .class_hid = BNXT_ULP_CLASS_HID_1e963, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1347] = { - .class_hid = BNXT_ULP_CLASS_HID_31c43, + .class_hid = BNXT_ULP_CLASS_HID_1e2a7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1348] = { - .class_hid = BNXT_ULP_CLASS_HID_3a743, + .class_hid = BNXT_ULP_CLASS_HID_1ef2f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1349] = { - .class_hid = BNXT_ULP_CLASS_HID_21993, + .class_hid = BNXT_ULP_CLASS_HID_1a747, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1350] = { - .class_hid = BNXT_ULP_CLASS_HID_2a493, + .class_hid = BNXT_ULP_CLASS_HID_1b3cf, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1351] = { - .class_hid = BNXT_ULP_CLASS_HID_32f93, + .class_hid = BNXT_ULP_CLASS_HID_1ad03, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1352] = { - .class_hid = BNXT_ULP_CLASS_HID_3ba93, + .class_hid = BNXT_ULP_CLASS_HID_1b98b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1353] = { - .class_hid = BNXT_ULP_CLASS_HID_24233, + .class_hid = BNXT_ULP_CLASS_HID_1a333, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1354] = { - .class_hid = BNXT_ULP_CLASS_HID_2cd33, + .class_hid = BNXT_ULP_CLASS_HID_1afbb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 118, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1355] = { - .class_hid = BNXT_ULP_CLASS_HID_35833, + .class_hid = BNXT_ULP_CLASS_HID_1a9ff, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 119, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1356] = { - .class_hid = BNXT_ULP_CLASS_HID_38607, + .class_hid = BNXT_ULP_CLASS_HID_1b667, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 120, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1357] = { - .class_hid = BNXT_ULP_CLASS_HID_22ee3, + .class_hid = BNXT_ULP_CLASS_HID_1eaeb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 121, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1358] = { - .class_hid = BNXT_ULP_CLASS_HID_2b9e3, + .class_hid = BNXT_ULP_CLASS_HID_1f753, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 121, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1359] = { - .class_hid = BNXT_ULP_CLASS_HID_344e3, + .class_hid = BNXT_ULP_CLASS_HID_1f097, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 121, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1360] = { - .class_hid = BNXT_ULP_CLASS_HID_3cfe3, + .class_hid = BNXT_ULP_CLASS_HID_1a0c3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 121, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1361] = { - .class_hid = BNXT_ULP_CLASS_HID_22a37, + .class_hid = BNXT_ULP_CLASS_HID_5b7af, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 121, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1362] = { - .class_hid = BNXT_ULP_CLASS_HID_2b537, + .class_hid = BNXT_ULP_CLASS_HID_5e417, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 121, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1363] = { - .class_hid = BNXT_ULP_CLASS_HID_34037, + .class_hid = BNXT_ULP_CLASS_HID_5be6b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 122, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1364] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb37, + .class_hid = BNXT_ULP_CLASS_HID_5ead3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 123, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1365] = { - .class_hid = BNXT_ULP_CLASS_HID_23d07, + .class_hid = BNXT_ULP_CLASS_HID_5a20b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1366] = { - .class_hid = BNXT_ULP_CLASS_HID_2c807, + .class_hid = BNXT_ULP_CLASS_HID_5aef3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1367] = { - .class_hid = BNXT_ULP_CLASS_HID_35307, + .class_hid = BNXT_ULP_CLASS_HID_5a837, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1368] = { - .class_hid = BNXT_ULP_CLASS_HID_3815b, + .class_hid = BNXT_ULP_CLASS_HID_5b4bf, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1369] = { - .class_hid = BNXT_ULP_CLASS_HID_208fb, + .class_hid = BNXT_ULP_CLASS_HID_5fb33, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1370] = { - .class_hid = BNXT_ULP_CLASS_HID_293fb, + .class_hid = BNXT_ULP_CLASS_HID_5ab6f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1371] = { - .class_hid = BNXT_ULP_CLASS_HID_31efb, + .class_hid = BNXT_ULP_CLASS_HID_5a4a3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1372] = { - .class_hid = BNXT_ULP_CLASS_HID_3a9fb, + .class_hid = BNXT_ULP_CLASS_HID_5b12b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1373] = { - .class_hid = BNXT_ULP_CLASS_HID_25257, + .class_hid = BNXT_ULP_CLASS_HID_5e59f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1374] = { - .class_hid = BNXT_ULP_CLASS_HID_280ab, + .class_hid = BNXT_ULP_CLASS_HID_5f207, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1375] = { - .class_hid = BNXT_ULP_CLASS_HID_30bab, + .class_hid = BNXT_ULP_CLASS_HID_5ec5b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1376] = { - .class_hid = BNXT_ULP_CLASS_HID_396ab, + .class_hid = BNXT_ULP_CLASS_HID_5f8c3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1377] = { - .class_hid = BNXT_ULP_CLASS_HID_24dab, + .class_hid = BNXT_ULP_CLASS_HID_ec7b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1378] = { - .class_hid = BNXT_ULP_CLASS_HID_2d8ab, + .class_hid = BNXT_ULP_CLASS_HID_f8e3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1379] = { - .class_hid = BNXT_ULP_CLASS_HID_306ff, + .class_hid = BNXT_ULP_CLASS_HID_f227, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1380] = { - .class_hid = BNXT_ULP_CLASS_HID_391ff, + .class_hid = BNXT_ULP_CLASS_HID_feaf, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1381] = { - .class_hid = BNXT_ULP_CLASS_HID_203cf, + .class_hid = BNXT_ULP_CLASS_HID_f6c7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1382] = { - .class_hid = BNXT_ULP_CLASS_HID_28ecf, + .class_hid = BNXT_ULP_CLASS_HID_e34f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1383] = { - .class_hid = BNXT_ULP_CLASS_HID_319cf, + .class_hid = BNXT_ULP_CLASS_HID_fc83, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1384] = { - .class_hid = BNXT_ULP_CLASS_HID_3a4cf, + .class_hid = BNXT_ULP_CLASS_HID_e90b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1385] = { - .class_hid = BNXT_ULP_CLASS_HID_2515b, + .class_hid = BNXT_ULP_CLASS_HID_ef8f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1386] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc5b, + .class_hid = BNXT_ULP_CLASS_HID_fc77, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1387] = { - .class_hid = BNXT_ULP_CLASS_HID_30aaf, + .class_hid = BNXT_ULP_CLASS_HID_f64b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1388] = { - .class_hid = BNXT_ULP_CLASS_HID_395af, + .class_hid = BNXT_ULP_CLASS_HID_e5e7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1389] = { - .class_hid = BNXT_ULP_CLASS_HID_23e0b, + .class_hid = BNXT_ULP_CLASS_HID_fa6b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1390] = { - .class_hid = BNXT_ULP_CLASS_HID_2c90b, + .class_hid = BNXT_ULP_CLASS_HID_e6d3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1391] = { - .class_hid = BNXT_ULP_CLASS_HID_3540b, + .class_hid = BNXT_ULP_CLASS_HID_e017, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1392] = { - .class_hid = BNXT_ULP_CLASS_HID_3825f, + .class_hid = BNXT_ULP_CLASS_HID_ec9f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1393] = { - .class_hid = BNXT_ULP_CLASS_HID_2395f, + .class_hid = BNXT_ULP_CLASS_HID_4e72f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1394] = { - .class_hid = BNXT_ULP_CLASS_HID_2c45f, + .class_hid = BNXT_ULP_CLASS_HID_4f397, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1395] = { - .class_hid = BNXT_ULP_CLASS_HID_34f5f, + .class_hid = BNXT_ULP_CLASS_HID_4edeb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1396] = { - .class_hid = BNXT_ULP_CLASS_HID_3da5f, + .class_hid = BNXT_ULP_CLASS_HID_4fa53, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1397] = { - .class_hid = BNXT_ULP_CLASS_HID_24caf, + .class_hid = BNXT_ULP_CLASS_HID_4f18b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1398] = { - .class_hid = BNXT_ULP_CLASS_HID_2d7af, + .class_hid = BNXT_ULP_CLASS_HID_4fe73, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1399] = { - .class_hid = BNXT_ULP_CLASS_HID_305e3, + .class_hid = BNXT_ULP_CLASS_HID_4f7b7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1400] = { - .class_hid = BNXT_ULP_CLASS_HID_390e3, + .class_hid = BNXT_ULP_CLASS_HID_4e43f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1401] = { - .class_hid = BNXT_ULP_CLASS_HID_21803, + .class_hid = BNXT_ULP_CLASS_HID_4eab3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1402] = { - .class_hid = BNXT_ULP_CLASS_HID_2a303, + .class_hid = BNXT_ULP_CLASS_HID_4f73b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1403] = { - .class_hid = BNXT_ULP_CLASS_HID_32e03, + .class_hid = BNXT_ULP_CLASS_HID_4f17f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1404] = { - .class_hid = BNXT_ULP_CLASS_HID_3b903, + .class_hid = BNXT_ULP_CLASS_HID_4e0ab, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1405] = { - .class_hid = BNXT_ULP_CLASS_HID_20533, + .class_hid = BNXT_ULP_CLASS_HID_4f51f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1406] = { - .class_hid = BNXT_ULP_CLASS_HID_29033, + .class_hid = BNXT_ULP_CLASS_HID_4e187, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1407] = { - .class_hid = BNXT_ULP_CLASS_HID_31b33, + .class_hid = BNXT_ULP_CLASS_HID_4fbdb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1408] = { - .class_hid = BNXT_ULP_CLASS_HID_3a633, + .class_hid = BNXT_ULP_CLASS_HID_4e843, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1409] = { - .class_hid = BNXT_ULP_CLASS_HID_20007, + .class_hid = BNXT_ULP_CLASS_HID_1e27b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, [1410] = { - .class_hid = BNXT_ULP_CLASS_HID_28b07, + .class_hid = BNXT_ULP_CLASS_HID_1eee3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1411] = { - .class_hid = BNXT_ULP_CLASS_HID_31607, + .class_hid = BNXT_ULP_CLASS_HID_1e827, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1412] = { - .class_hid = BNXT_ULP_CLASS_HID_3a107, + .class_hid = BNXT_ULP_CLASS_HID_1f4af, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1413] = { - .class_hid = BNXT_ULP_CLASS_HID_21357, + .class_hid = BNXT_ULP_CLASS_HID_1ecc7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1414] = { - .class_hid = BNXT_ULP_CLASS_HID_29e57, + .class_hid = BNXT_ULP_CLASS_HID_1f94f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1415] = { - .class_hid = BNXT_ULP_CLASS_HID_32957, + .class_hid = BNXT_ULP_CLASS_HID_1f283, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1416] = { - .class_hid = BNXT_ULP_CLASS_HID_3b457, + .class_hid = BNXT_ULP_CLASS_HID_1ff0b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1417] = { - .class_hid = BNXT_ULP_CLASS_HID_23bf7, + .class_hid = BNXT_ULP_CLASS_HID_1e8b3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1418] = { - .class_hid = BNXT_ULP_CLASS_HID_2c6f7, + .class_hid = BNXT_ULP_CLASS_HID_1f53b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1419] = { - .class_hid = BNXT_ULP_CLASS_HID_351f7, + .class_hid = BNXT_ULP_CLASS_HID_1ef7f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1420] = { - .class_hid = BNXT_ULP_CLASS_HID_3dcf7, + .class_hid = BNXT_ULP_CLASS_HID_1fbe7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1421] = { - .class_hid = BNXT_ULP_CLASS_HID_228a7, + .class_hid = BNXT_ULP_CLASS_HID_1f06b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1422] = { - .class_hid = BNXT_ULP_CLASS_HID_2b3a7, + .class_hid = BNXT_ULP_CLASS_HID_1fcd3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1423] = { - .class_hid = BNXT_ULP_CLASS_HID_33ea7, + .class_hid = BNXT_ULP_CLASS_HID_1f617, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1424] = { - .class_hid = BNXT_ULP_CLASS_HID_3c9a7, + .class_hid = BNXT_ULP_CLASS_HID_1e643, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1425] = { - .class_hid = BNXT_ULP_CLASS_HID_223fb, + .class_hid = BNXT_ULP_CLASS_HID_5fd2f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1426] = { - .class_hid = BNXT_ULP_CLASS_HID_2aefb, + .class_hid = BNXT_ULP_CLASS_HID_5e997, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1427] = { - .class_hid = BNXT_ULP_CLASS_HID_339fb, + .class_hid = BNXT_ULP_CLASS_HID_5e3eb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1428] = { - .class_hid = BNXT_ULP_CLASS_HID_3c4fb, + .class_hid = BNXT_ULP_CLASS_HID_5f053, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1429] = { - .class_hid = BNXT_ULP_CLASS_HID_236cb, + .class_hid = BNXT_ULP_CLASS_HID_5e78b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1430] = { - .class_hid = BNXT_ULP_CLASS_HID_2c1cb, + .class_hid = BNXT_ULP_CLASS_HID_5f473, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1431] = { - .class_hid = BNXT_ULP_CLASS_HID_34ccb, + .class_hid = BNXT_ULP_CLASS_HID_5edb7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1432] = { - .class_hid = BNXT_ULP_CLASS_HID_3d7cb, + .class_hid = BNXT_ULP_CLASS_HID_5fa3f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1433] = { - .class_hid = BNXT_ULP_CLASS_HID_202bf, + .class_hid = BNXT_ULP_CLASS_HID_5e467, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1434] = { - .class_hid = BNXT_ULP_CLASS_HID_28dbf, + .class_hid = BNXT_ULP_CLASS_HID_5f0ef, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1435] = { - .class_hid = BNXT_ULP_CLASS_HID_318bf, + .class_hid = BNXT_ULP_CLASS_HID_5ea23, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1436] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3bf, + .class_hid = BNXT_ULP_CLASS_HID_5f6ab, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1437] = { - .class_hid = BNXT_ULP_CLASS_HID_24c1b, + .class_hid = BNXT_ULP_CLASS_HID_5eb1f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1438] = { - .class_hid = BNXT_ULP_CLASS_HID_2d71b, + .class_hid = BNXT_ULP_CLASS_HID_5f787, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1439] = { - .class_hid = BNXT_ULP_CLASS_HID_3056f, + .class_hid = BNXT_ULP_CLASS_HID_5f1db, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1440] = { - .class_hid = BNXT_ULP_CLASS_HID_3906f, + .class_hid = BNXT_ULP_CLASS_HID_5e177, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1441] = { - .class_hid = BNXT_ULP_CLASS_HID_2476f, + .class_hid = BNXT_ULP_CLASS_HID_498d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1442] = { - .class_hid = BNXT_ULP_CLASS_HID_2d26f, + .class_hid = BNXT_ULP_CLASS_HID_4fc9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1443] = { - .class_hid = BNXT_ULP_CLASS_HID_300a3, + .class_hid = BNXT_ULP_CLASS_HID_0cf9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1444] = { - .class_hid = BNXT_ULP_CLASS_HID_38ba3, + .class_hid = BNXT_ULP_CLASS_HID_1335, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1445] = { - .class_hid = BNXT_ULP_CLASS_HID_25abf, + .class_hid = BNXT_ULP_CLASS_HID_232d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1446] = { - .class_hid = BNXT_ULP_CLASS_HID_288f3, + .class_hid = BNXT_ULP_CLASS_HID_2969, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1447] = { - .class_hid = BNXT_ULP_CLASS_HID_313f3, + .class_hid = BNXT_ULP_CLASS_HID_4345, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1448] = { - .class_hid = BNXT_ULP_CLASS_HID_39ef3, + .class_hid = BNXT_ULP_CLASS_HID_4981, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1449] = { - .class_hid = BNXT_ULP_CLASS_HID_24b1f, + .class_hid = BNXT_ULP_CLASS_HID_45809, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1450] = { - .class_hid = BNXT_ULP_CLASS_HID_2d61f, + .class_hid = BNXT_ULP_CLASS_HID_40179, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1451] = { - .class_hid = BNXT_ULP_CLASS_HID_30453, + .class_hid = BNXT_ULP_CLASS_HID_431a9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1452] = { - .class_hid = BNXT_ULP_CLASS_HID_38f53, + .class_hid = BNXT_ULP_CLASS_HID_437d5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1453] = { - .class_hid = BNXT_ULP_CLASS_HID_237cf, + .class_hid = BNXT_ULP_CLASS_HID_44e61, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1454] = { - .class_hid = BNXT_ULP_CLASS_HID_2c2cf, + .class_hid = BNXT_ULP_CLASS_HID_454ad, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1455] = { - .class_hid = BNXT_ULP_CLASS_HID_34dcf, + .class_hid = BNXT_ULP_CLASS_HID_42801, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1456] = { - .class_hid = BNXT_ULP_CLASS_HID_3d8cf, + .class_hid = BNXT_ULP_CLASS_HID_42e4d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1457] = { - .class_hid = BNXT_ULP_CLASS_HID_23303, + .class_hid = BNXT_ULP_CLASS_HID_22c13, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1458] = { - .class_hid = BNXT_ULP_CLASS_HID_2be03, + .class_hid = BNXT_ULP_CLASS_HID_2322f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1459] = { - .class_hid = BNXT_ULP_CLASS_HID_34903, + .class_hid = BNXT_ULP_CLASS_HID_2164f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1460] = { - .class_hid = BNXT_ULP_CLASS_HID_3d403, + .class_hid = BNXT_ULP_CLASS_HID_21c8b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1461] = { - .class_hid = BNXT_ULP_CLASS_HID_24653, + .class_hid = BNXT_ULP_CLASS_HID_24f87, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1462] = { - .class_hid = BNXT_ULP_CLASS_HID_2d153, + .class_hid = BNXT_ULP_CLASS_HID_255c3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1463] = { - .class_hid = BNXT_ULP_CLASS_HID_35c53, + .class_hid = BNXT_ULP_CLASS_HID_239e3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1464] = { - .class_hid = BNXT_ULP_CLASS_HID_38aa7, + .class_hid = BNXT_ULP_CLASS_HID_2403f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1465] = { - .class_hid = BNXT_ULP_CLASS_HID_211c7, + .class_hid = BNXT_ULP_CLASS_HID_218c3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1466] = { - .class_hid = BNXT_ULP_CLASS_HID_29cc7, + .class_hid = BNXT_ULP_CLASS_HID_21f1f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1467] = { - .class_hid = BNXT_ULP_CLASS_HID_327c7, + .class_hid = BNXT_ULP_CLASS_HID_2033f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1468] = { - .class_hid = BNXT_ULP_CLASS_HID_3b2c7, + .class_hid = BNXT_ULP_CLASS_HID_2097b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1469] = { - .class_hid = BNXT_ULP_CLASS_HID_25ba3, + .class_hid = BNXT_ULP_CLASS_HID_23c77, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1470] = { - .class_hid = BNXT_ULP_CLASS_HID_289f7, + .class_hid = BNXT_ULP_CLASS_HID_242b3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1471] = { - .class_hid = BNXT_ULP_CLASS_HID_314f7, + .class_hid = BNXT_ULP_CLASS_HID_226d3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1472] = { - .class_hid = BNXT_ULP_CLASS_HID_39ff7, + .class_hid = BNXT_ULP_CLASS_HID_22cef, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1473] = { - .class_hid = BNXT_ULP_CLASS_HID_256f7, + .class_hid = BNXT_ULP_CLASS_HID_62727, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1474] = { - .class_hid = BNXT_ULP_CLASS_HID_284cb, + .class_hid = BNXT_ULP_CLASS_HID_62d63, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1475] = { - .class_hid = BNXT_ULP_CLASS_HID_30fcb, + .class_hid = BNXT_ULP_CLASS_HID_61183, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1476] = { - .class_hid = BNXT_ULP_CLASS_HID_39acb, + .class_hid = BNXT_ULP_CLASS_HID_617df, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1477] = { - .class_hid = BNXT_ULP_CLASS_HID_20d1b, + .class_hid = BNXT_ULP_CLASS_HID_64adb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1478] = { - .class_hid = BNXT_ULP_CLASS_HID_2981b, + .class_hid = BNXT_ULP_CLASS_HID_65117, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1479] = { - .class_hid = BNXT_ULP_CLASS_HID_3231b, + .class_hid = BNXT_ULP_CLASS_HID_63537, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1480] = { - .class_hid = BNXT_ULP_CLASS_HID_3ae1b, + .class_hid = BNXT_ULP_CLASS_HID_63b73, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1481] = { - .class_hid = BNXT_ULP_CLASS_HID_235bb, + .class_hid = BNXT_ULP_CLASS_HID_61417, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1482] = { - .class_hid = BNXT_ULP_CLASS_HID_2c0bb, + .class_hid = BNXT_ULP_CLASS_HID_61a53, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 124, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1483] = { - .class_hid = BNXT_ULP_CLASS_HID_34bbb, + .class_hid = BNXT_ULP_CLASS_HID_65b3f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 125, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1484] = { - .class_hid = BNXT_ULP_CLASS_HID_3d6bb, + .class_hid = BNXT_ULP_CLASS_HID_6048f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 126, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1485] = { - .class_hid = BNXT_ULP_CLASS_HID_2226b, + .class_hid = BNXT_ULP_CLASS_HID_6378b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 127, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1486] = { - .class_hid = BNXT_ULP_CLASS_HID_2ad6b, + .class_hid = BNXT_ULP_CLASS_HID_63dc7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 127, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1487] = { - .class_hid = BNXT_ULP_CLASS_HID_3386b, + .class_hid = BNXT_ULP_CLASS_HID_621e7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 127, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1488] = { - .class_hid = BNXT_ULP_CLASS_HID_3c36b, + .class_hid = BNXT_ULP_CLASS_HID_62823, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 127, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1489] = { - .class_hid = BNXT_ULP_CLASS_HID_21dbf, + .class_hid = BNXT_ULP_CLASS_HID_8b0b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 127, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1490] = { - .class_hid = BNXT_ULP_CLASS_HID_2a8bf, + .class_hid = BNXT_ULP_CLASS_HID_9137, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 127, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1491] = { - .class_hid = BNXT_ULP_CLASS_HID_333bf, + .class_hid = BNXT_ULP_CLASS_HID_d223, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 128, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1492] = { - .class_hid = BNXT_ULP_CLASS_HID_3bebf, + .class_hid = BNXT_ULP_CLASS_HID_d86f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 129, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1493] = { - .class_hid = BNXT_ULP_CLASS_HID_2308f, + .class_hid = BNXT_ULP_CLASS_HID_ae9f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1494] = { - .class_hid = BNXT_ULP_CLASS_HID_2bb8f, + .class_hid = BNXT_ULP_CLASS_HID_b4db, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1495] = { - .class_hid = BNXT_ULP_CLASS_HID_3468f, + .class_hid = BNXT_ULP_CLASS_HID_98fb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1496] = { - .class_hid = BNXT_ULP_CLASS_HID_3d18f, + .class_hid = BNXT_ULP_CLASS_HID_9f27, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1497] = { - .class_hid = BNXT_ULP_CLASS_HID_2592f, + .class_hid = BNXT_ULP_CLASS_HID_4863f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1498] = { - .class_hid = BNXT_ULP_CLASS_HID_28763, + .class_hid = BNXT_ULP_CLASS_HID_48c7b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1499] = { - .class_hid = BNXT_ULP_CLASS_HID_31263, + .class_hid = BNXT_ULP_CLASS_HID_4cd57, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1500] = { - .class_hid = BNXT_ULP_CLASS_HID_39d63, + .class_hid = BNXT_ULP_CLASS_HID_4d393, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1501] = { - .class_hid = BNXT_ULP_CLASS_HID_245df, + .class_hid = BNXT_ULP_CLASS_HID_4a9c3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1502] = { - .class_hid = BNXT_ULP_CLASS_HID_2d0df, + .class_hid = BNXT_ULP_CLASS_HID_4b00f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1503] = { - .class_hid = BNXT_ULP_CLASS_HID_35bdf, + .class_hid = BNXT_ULP_CLASS_HID_4942f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1504] = { - .class_hid = BNXT_ULP_CLASS_HID_38a13, + .class_hid = BNXT_ULP_CLASS_HID_49a6b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1505] = { - .class_hid = BNXT_ULP_CLASS_HID_24113, + .class_hid = BNXT_ULP_CLASS_HID_1a10b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1506] = { - .class_hid = BNXT_ULP_CLASS_HID_2cc13, + .class_hid = BNXT_ULP_CLASS_HID_1a737, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1507] = { - .class_hid = BNXT_ULP_CLASS_HID_35713, + .class_hid = BNXT_ULP_CLASS_HID_18b57, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1508] = { - .class_hid = BNXT_ULP_CLASS_HID_38567, + .class_hid = BNXT_ULP_CLASS_HID_19193, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1509] = { - .class_hid = BNXT_ULP_CLASS_HID_25463, + .class_hid = BNXT_ULP_CLASS_HID_1c49f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1510] = { - .class_hid = BNXT_ULP_CLASS_HID_282b7, + .class_hid = BNXT_ULP_CLASS_HID_1cadb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1511] = { - .class_hid = BNXT_ULP_CLASS_HID_30db7, + .class_hid = BNXT_ULP_CLASS_HID_1aefb, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1512] = { - .class_hid = BNXT_ULP_CLASS_HID_398b7, + .class_hid = BNXT_ULP_CLASS_HID_1b527, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1513] = { - .class_hid = BNXT_ULP_CLASS_HID_244c3, + .class_hid = BNXT_ULP_CLASS_HID_59c3f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1514] = { - .class_hid = BNXT_ULP_CLASS_HID_2cfc3, + .class_hid = BNXT_ULP_CLASS_HID_5a27b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1515] = { - .class_hid = BNXT_ULP_CLASS_HID_35ac3, + .class_hid = BNXT_ULP_CLASS_HID_5869b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1516] = { - .class_hid = BNXT_ULP_CLASS_HID_38917, + .class_hid = BNXT_ULP_CLASS_HID_58cc7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1517] = { - .class_hid = BNXT_ULP_CLASS_HID_231f3, + .class_hid = BNXT_ULP_CLASS_HID_5bfc3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1518] = { - .class_hid = BNXT_ULP_CLASS_HID_2bcf3, + .class_hid = BNXT_ULP_CLASS_HID_5c60f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1519] = { - .class_hid = BNXT_ULP_CLASS_HID_347f3, + .class_hid = BNXT_ULP_CLASS_HID_5aa2f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1520] = { - .class_hid = BNXT_ULP_CLASS_HID_3d2f3, + .class_hid = BNXT_ULP_CLASS_HID_5b06b, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1521] = { - .class_hid = BNXT_ULP_CLASS_HID_22cc7, + .class_hid = BNXT_ULP_CLASS_HID_49ad, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1522] = { - .class_hid = BNXT_ULP_CLASS_HID_2b7c7, + .class_hid = BNXT_ULP_CLASS_HID_4fe9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1523] = { - .class_hid = BNXT_ULP_CLASS_HID_342c7, + .class_hid = BNXT_ULP_CLASS_HID_0cd9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1524] = { - .class_hid = BNXT_ULP_CLASS_HID_3cdc7, + .class_hid = BNXT_ULP_CLASS_HID_1315, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1525] = { - .class_hid = BNXT_ULP_CLASS_HID_24017, + .class_hid = BNXT_ULP_CLASS_HID_230d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1526] = { - .class_hid = BNXT_ULP_CLASS_HID_2cb17, + .class_hid = BNXT_ULP_CLASS_HID_2949, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1527] = { - .class_hid = BNXT_ULP_CLASS_HID_35617, + .class_hid = BNXT_ULP_CLASS_HID_4365, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1528] = { - .class_hid = BNXT_ULP_CLASS_HID_3846b, + .class_hid = BNXT_ULP_CLASS_HID_49a1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1529] = { - .class_hid = BNXT_ULP_CLASS_HID_20b8b, + .class_hid = BNXT_ULP_CLASS_HID_4035, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1530] = { - .class_hid = BNXT_ULP_CLASS_HID_2968b, + .class_hid = BNXT_ULP_CLASS_HID_4671, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1531] = { - .class_hid = BNXT_ULP_CLASS_HID_3218b, + .class_hid = BNXT_ULP_CLASS_HID_0361, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1532] = { - .class_hid = BNXT_ULP_CLASS_HID_3ac8b, + .class_hid = BNXT_ULP_CLASS_HID_09bd, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1533] = { - .class_hid = BNXT_ULP_CLASS_HID_25567, + .class_hid = BNXT_ULP_CLASS_HID_1995, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1534] = { - .class_hid = BNXT_ULP_CLASS_HID_283bb, + .class_hid = BNXT_ULP_CLASS_HID_1fd1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1535] = { - .class_hid = BNXT_ULP_CLASS_HID_30ebb, + .class_hid = BNXT_ULP_CLASS_HID_398d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1536] = { - .class_hid = BNXT_ULP_CLASS_HID_399bb, + .class_hid = BNXT_ULP_CLASS_HID_3fc9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1537] = { - .class_hid = BNXT_ULP_CLASS_HID_250bb, + .class_hid = BNXT_ULP_CLASS_HID_444e1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1538] = { - .class_hid = BNXT_ULP_CLASS_HID_2dbbb, + .class_hid = BNXT_ULP_CLASS_HID_44b3d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1539] = { - .class_hid = BNXT_ULP_CLASS_HID_3098f, + .class_hid = BNXT_ULP_CLASS_HID_4082d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1540] = { - .class_hid = BNXT_ULP_CLASS_HID_3948f, + .class_hid = BNXT_ULP_CLASS_HID_40e69, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1541] = { - .class_hid = BNXT_ULP_CLASS_HID_206df, + .class_hid = BNXT_ULP_CLASS_HID_41e41, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1542] = { - .class_hid = BNXT_ULP_CLASS_HID_291df, + .class_hid = BNXT_ULP_CLASS_HID_4249d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1543] = { - .class_hid = BNXT_ULP_CLASS_HID_31cdf, + .class_hid = BNXT_ULP_CLASS_HID_43eb9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1544] = { - .class_hid = BNXT_ULP_CLASS_HID_3a7df, + .class_hid = BNXT_ULP_CLASS_HID_444f5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1545] = { - .class_hid = BNXT_ULP_CLASS_HID_22f7f, + .class_hid = BNXT_ULP_CLASS_HID_43b09, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1546] = { - .class_hid = BNXT_ULP_CLASS_HID_2ba7f, + .class_hid = BNXT_ULP_CLASS_HID_44145, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1547] = { - .class_hid = BNXT_ULP_CLASS_HID_3457f, + .class_hid = BNXT_ULP_CLASS_HID_45b61, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1548] = { - .class_hid = BNXT_ULP_CLASS_HID_3d07f, + .class_hid = BNXT_ULP_CLASS_HID_404f1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1549] = { - .class_hid = BNXT_ULP_CLASS_HID_21c2f, + .class_hid = BNXT_ULP_CLASS_HID_414e9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1550] = { - .class_hid = BNXT_ULP_CLASS_HID_2a72f, + .class_hid = BNXT_ULP_CLASS_HID_41b25, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1551] = { - .class_hid = BNXT_ULP_CLASS_HID_3322f, + .class_hid = BNXT_ULP_CLASS_HID_434c1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1552] = { - .class_hid = BNXT_ULP_CLASS_HID_3bd2f, + .class_hid = BNXT_ULP_CLASS_HID_43b1d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1553] = { - .class_hid = BNXT_ULP_CLASS_HID_21763, + .class_hid = BNXT_ULP_CLASS_HID_45829, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1554] = { - .class_hid = BNXT_ULP_CLASS_HID_2a263, + .class_hid = BNXT_ULP_CLASS_HID_40159, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1555] = { - .class_hid = BNXT_ULP_CLASS_HID_32d63, + .class_hid = BNXT_ULP_CLASS_HID_43189, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1556] = { - .class_hid = BNXT_ULP_CLASS_HID_3b863, + .class_hid = BNXT_ULP_CLASS_HID_437f5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1557] = { - .class_hid = BNXT_ULP_CLASS_HID_22ab3, + .class_hid = BNXT_ULP_CLASS_HID_44e41, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1558] = { - .class_hid = BNXT_ULP_CLASS_HID_2b5b3, + .class_hid = BNXT_ULP_CLASS_HID_4548d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1559] = { - .class_hid = BNXT_ULP_CLASS_HID_340b3, + .class_hid = BNXT_ULP_CLASS_HID_42821, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1560] = { - .class_hid = BNXT_ULP_CLASS_HID_3cbb3, + .class_hid = BNXT_ULP_CLASS_HID_42e6d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1561] = { - .class_hid = BNXT_ULP_CLASS_HID_252d3, + .class_hid = BNXT_ULP_CLASS_HID_6271d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1562] = { - .class_hid = BNXT_ULP_CLASS_HID_28127, + .class_hid = BNXT_ULP_CLASS_HID_62d59, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1563] = { - .class_hid = BNXT_ULP_CLASS_HID_30c27, + .class_hid = BNXT_ULP_CLASS_HID_600fd, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1564] = { - .class_hid = BNXT_ULP_CLASS_HID_39727, + .class_hid = BNXT_ULP_CLASS_HID_60739, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1565] = { - .class_hid = BNXT_ULP_CLASS_HID_23f83, + .class_hid = BNXT_ULP_CLASS_HID_61db5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1566] = { - .class_hid = BNXT_ULP_CLASS_HID_2ca83, + .class_hid = BNXT_ULP_CLASS_HID_623f1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1567] = { - .class_hid = BNXT_ULP_CLASS_HID_35583, + .class_hid = BNXT_ULP_CLASS_HID_65421, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1568] = { - .class_hid = BNXT_ULP_CLASS_HID_383d7, + .class_hid = BNXT_ULP_CLASS_HID_65a6d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1569] = { - .class_hid = BNXT_ULP_CLASS_HID_23ad7, + .class_hid = BNXT_ULP_CLASS_HID_5111d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1570] = { - .class_hid = BNXT_ULP_CLASS_HID_2c5d7, + .class_hid = BNXT_ULP_CLASS_HID_51759, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1571] = { - .class_hid = BNXT_ULP_CLASS_HID_350d7, + .class_hid = BNXT_ULP_CLASS_HID_54789, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1572] = { - .class_hid = BNXT_ULP_CLASS_HID_3dbd7, + .class_hid = BNXT_ULP_CLASS_HID_54df5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1573] = { - .class_hid = BNXT_ULP_CLASS_HID_24e27, + .class_hid = BNXT_ULP_CLASS_HID_507b5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1574] = { - .class_hid = BNXT_ULP_CLASS_HID_2d927, + .class_hid = BNXT_ULP_CLASS_HID_50df1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1575] = { - .class_hid = BNXT_ULP_CLASS_HID_3077b, + .class_hid = BNXT_ULP_CLASS_HID_53e21, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1576] = { - .class_hid = BNXT_ULP_CLASS_HID_3927b, + .class_hid = BNXT_ULP_CLASS_HID_5446d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1577] = { - .class_hid = BNXT_ULP_CLASS_HID_2320f, + .class_hid = BNXT_ULP_CLASS_HID_73d1d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1578] = { - .class_hid = BNXT_ULP_CLASS_HID_2bd0f, + .class_hid = BNXT_ULP_CLASS_HID_74359, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1579] = { - .class_hid = BNXT_ULP_CLASS_HID_3480f, + .class_hid = BNXT_ULP_CLASS_HID_716fd, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1580] = { - .class_hid = BNXT_ULP_CLASS_HID_3d30f, + .class_hid = BNXT_ULP_CLASS_HID_71d39, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1581] = { - .class_hid = BNXT_ULP_CLASS_HID_21f3f, + .class_hid = BNXT_ULP_CLASS_HID_733b5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1582] = { - .class_hid = BNXT_ULP_CLASS_HID_2aa3f, + .class_hid = BNXT_ULP_CLASS_HID_739f1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1583] = { - .class_hid = BNXT_ULP_CLASS_HID_3353f, + .class_hid = BNXT_ULP_CLASS_HID_70d15, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1584] = { - .class_hid = BNXT_ULP_CLASS_HID_3c03f, + .class_hid = BNXT_ULP_CLASS_HID_71351, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1585] = { - .class_hid = BNXT_ULP_CLASS_HID_21a73, + .class_hid = BNXT_ULP_CLASS_HID_49cd, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1586] = { - .class_hid = BNXT_ULP_CLASS_HID_2a573, + .class_hid = BNXT_ULP_CLASS_HID_4f89, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1587] = { - .class_hid = BNXT_ULP_CLASS_HID_33073, + .class_hid = BNXT_ULP_CLASS_HID_0cb9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1588] = { - .class_hid = BNXT_ULP_CLASS_HID_3bb73, + .class_hid = BNXT_ULP_CLASS_HID_1375, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1589] = { - .class_hid = BNXT_ULP_CLASS_HID_22d43, + .class_hid = BNXT_ULP_CLASS_HID_236d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1590] = { - .class_hid = BNXT_ULP_CLASS_HID_2b843, + .class_hid = BNXT_ULP_CLASS_HID_2929, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1591] = { - .class_hid = BNXT_ULP_CLASS_HID_34343, + .class_hid = BNXT_ULP_CLASS_HID_4305, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1592] = { - .class_hid = BNXT_ULP_CLASS_HID_3ce43, + .class_hid = BNXT_ULP_CLASS_HID_49c1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1593] = { - .class_hid = BNXT_ULP_CLASS_HID_255e3, + .class_hid = BNXT_ULP_CLASS_HID_4055, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1594] = { - .class_hid = BNXT_ULP_CLASS_HID_28437, + .class_hid = BNXT_ULP_CLASS_HID_4611, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1595] = { - .class_hid = BNXT_ULP_CLASS_HID_30f37, + .class_hid = BNXT_ULP_CLASS_HID_0301, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1596] = { - .class_hid = BNXT_ULP_CLASS_HID_39a37, + .class_hid = BNXT_ULP_CLASS_HID_09dd, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1597] = { - .class_hid = BNXT_ULP_CLASS_HID_24293, + .class_hid = BNXT_ULP_CLASS_HID_19f5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1598] = { - .class_hid = BNXT_ULP_CLASS_HID_2cd93, + .class_hid = BNXT_ULP_CLASS_HID_1fb1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1599] = { - .class_hid = BNXT_ULP_CLASS_HID_35893, + .class_hid = BNXT_ULP_CLASS_HID_39ed, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1600] = { - .class_hid = BNXT_ULP_CLASS_HID_386e7, + .class_hid = BNXT_ULP_CLASS_HID_3fa9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1601] = { - .class_hid = BNXT_ULP_CLASS_HID_23de7, + .class_hid = BNXT_ULP_CLASS_HID_44481, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1602] = { - .class_hid = BNXT_ULP_CLASS_HID_2c8e7, + .class_hid = BNXT_ULP_CLASS_HID_44b5d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1603] = { - .class_hid = BNXT_ULP_CLASS_HID_353e7, + .class_hid = BNXT_ULP_CLASS_HID_4084d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1604] = { - .class_hid = BNXT_ULP_CLASS_HID_3823b, + .class_hid = BNXT_ULP_CLASS_HID_40e09, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1605] = { - .class_hid = BNXT_ULP_CLASS_HID_25137, + .class_hid = BNXT_ULP_CLASS_HID_41e21, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1606] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc37, + .class_hid = BNXT_ULP_CLASS_HID_424fd, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1607] = { - .class_hid = BNXT_ULP_CLASS_HID_30a0b, + .class_hid = BNXT_ULP_CLASS_HID_43ed9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1608] = { - .class_hid = BNXT_ULP_CLASS_HID_3950b, + .class_hid = BNXT_ULP_CLASS_HID_44495, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1609] = { - .class_hid = BNXT_ULP_CLASS_HID_22c33, + .class_hid = BNXT_ULP_CLASS_HID_43b69, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1610] = { - .class_hid = BNXT_ULP_CLASS_HID_2b733, + .class_hid = BNXT_ULP_CLASS_HID_44125, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1611] = { - .class_hid = BNXT_ULP_CLASS_HID_34233, + .class_hid = BNXT_ULP_CLASS_HID_45b01, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1612] = { - .class_hid = BNXT_ULP_CLASS_HID_3cd33, + .class_hid = BNXT_ULP_CLASS_HID_40491, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1613] = { - .class_hid = BNXT_ULP_CLASS_HID_218e3, + .class_hid = BNXT_ULP_CLASS_HID_41489, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1614] = { - .class_hid = BNXT_ULP_CLASS_HID_2a3e3, + .class_hid = BNXT_ULP_CLASS_HID_41b45, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1615] = { - .class_hid = BNXT_ULP_CLASS_HID_32ee3, + .class_hid = BNXT_ULP_CLASS_HID_434a1, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1616] = { - .class_hid = BNXT_ULP_CLASS_HID_3b9e3, + .class_hid = BNXT_ULP_CLASS_HID_43b7d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1617] = { - .class_hid = BNXT_ULP_CLASS_HID_21437, + .class_hid = BNXT_ULP_CLASS_HID_45849, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1618] = { - .class_hid = BNXT_ULP_CLASS_HID_29f37, + .class_hid = BNXT_ULP_CLASS_HID_40139, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1619] = { - .class_hid = BNXT_ULP_CLASS_HID_32a37, + .class_hid = BNXT_ULP_CLASS_HID_431e9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1620] = { - .class_hid = BNXT_ULP_CLASS_HID_3b537, + .class_hid = BNXT_ULP_CLASS_HID_43795, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1621] = { - .class_hid = BNXT_ULP_CLASS_HID_22707, + .class_hid = BNXT_ULP_CLASS_HID_44e21, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1622] = { - .class_hid = BNXT_ULP_CLASS_HID_2b207, + .class_hid = BNXT_ULP_CLASS_HID_454ed, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1623] = { - .class_hid = BNXT_ULP_CLASS_HID_33d07, + .class_hid = BNXT_ULP_CLASS_HID_42841, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1624] = { - .class_hid = BNXT_ULP_CLASS_HID_3c807, + .class_hid = BNXT_ULP_CLASS_HID_42e0d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1625] = { - .class_hid = BNXT_ULP_CLASS_HID_24fa7, + .class_hid = BNXT_ULP_CLASS_HID_6277d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1626] = { - .class_hid = BNXT_ULP_CLASS_HID_2daa7, + .class_hid = BNXT_ULP_CLASS_HID_62d39, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1627] = { - .class_hid = BNXT_ULP_CLASS_HID_308fb, + .class_hid = BNXT_ULP_CLASS_HID_6009d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1628] = { - .class_hid = BNXT_ULP_CLASS_HID_393fb, + .class_hid = BNXT_ULP_CLASS_HID_60759, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1629] = { - .class_hid = BNXT_ULP_CLASS_HID_23c57, + .class_hid = BNXT_ULP_CLASS_HID_61dd5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1630] = { - .class_hid = BNXT_ULP_CLASS_HID_2c757, + .class_hid = BNXT_ULP_CLASS_HID_62391, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1631] = { - .class_hid = BNXT_ULP_CLASS_HID_35257, + .class_hid = BNXT_ULP_CLASS_HID_65441, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1632] = { - .class_hid = BNXT_ULP_CLASS_HID_380ab, + .class_hid = BNXT_ULP_CLASS_HID_65a0d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1633] = { - .class_hid = BNXT_ULP_CLASS_HID_237ab, + .class_hid = BNXT_ULP_CLASS_HID_5117d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1634] = { - .class_hid = BNXT_ULP_CLASS_HID_2c2ab, + .class_hid = BNXT_ULP_CLASS_HID_51739, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1635] = { - .class_hid = BNXT_ULP_CLASS_HID_34dab, + .class_hid = BNXT_ULP_CLASS_HID_547e9, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1636] = { - .class_hid = BNXT_ULP_CLASS_HID_3d8ab, + .class_hid = BNXT_ULP_CLASS_HID_54d95, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1637] = { - .class_hid = BNXT_ULP_CLASS_HID_24afb, + .class_hid = BNXT_ULP_CLASS_HID_507d5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1638] = { - .class_hid = BNXT_ULP_CLASS_HID_2d5fb, + .class_hid = BNXT_ULP_CLASS_HID_50d91, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1639] = { - .class_hid = BNXT_ULP_CLASS_HID_303cf, + .class_hid = BNXT_ULP_CLASS_HID_53e41, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1640] = { - .class_hid = BNXT_ULP_CLASS_HID_38ecf, + .class_hid = BNXT_ULP_CLASS_HID_5440d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1641] = { - .class_hid = BNXT_ULP_CLASS_HID_255b, + .class_hid = BNXT_ULP_CLASS_HID_73d7d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1642] = { - .class_hid = BNXT_ULP_CLASS_HID_2b97, + .class_hid = BNXT_ULP_CLASS_HID_74339, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1643] = { - .class_hid = BNXT_ULP_CLASS_HID_1847, + .class_hid = BNXT_ULP_CLASS_HID_7169d, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1644] = { - .class_hid = BNXT_ULP_CLASS_HID_4f0b, + .class_hid = BNXT_ULP_CLASS_HID_71d59, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1645] = { - .class_hid = BNXT_ULP_CLASS_HID_3c3b, + .class_hid = BNXT_ULP_CLASS_HID_733d5, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1646] = { - .class_hid = BNXT_ULP_CLASS_HID_1633, + .class_hid = BNXT_ULP_CLASS_HID_73991, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1647] = { - .class_hid = BNXT_ULP_CLASS_HID_02e3, + .class_hid = BNXT_ULP_CLASS_HID_70d75, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1648] = { - .class_hid = BNXT_ULP_CLASS_HID_39a7, + .class_hid = BNXT_ULP_CLASS_HID_71331, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1649] = { - .class_hid = BNXT_ULP_CLASS_HID_2657, + .class_hid = BNXT_ULP_CLASS_HID_22c33, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -36401,20 +37549,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1650] = { - .class_hid = BNXT_ULP_CLASS_HID_120b, + .class_hid = BNXT_ULP_CLASS_HID_2320f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -36422,17 +37565,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1651] = { - .class_hid = BNXT_ULP_CLASS_HID_48cf, + .class_hid = BNXT_ULP_CLASS_HID_2166f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -36440,17 +37582,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1652] = { - .class_hid = BNXT_ULP_CLASS_HID_35ff, + .class_hid = BNXT_ULP_CLASS_HID_21cab, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -36458,18 +37599,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1653] = { - .class_hid = BNXT_ULP_CLASS_HID_0ff7, + .class_hid = BNXT_ULP_CLASS_HID_24fa7, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -36477,17 +37617,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1654] = { - .class_hid = BNXT_ULP_CLASS_HID_5953, + .class_hid = BNXT_ULP_CLASS_HID_255e3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -36495,18 +37634,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1655] = { - .class_hid = BNXT_ULP_CLASS_HID_336b, + .class_hid = BNXT_ULP_CLASS_HID_239c3, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -36514,18 +37652,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1656] = { - .class_hid = BNXT_ULP_CLASS_HID_201b, + .class_hid = BNXT_ULP_CLASS_HID_2401f, .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 130, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -36533,5223 +37670,4870 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1657] = { - .class_hid = BNXT_ULP_CLASS_HID_257f7, + .class_hid = BNXT_ULP_CLASS_HID_218e3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1658] = { - .class_hid = BNXT_ULP_CLASS_HID_2858b, + .class_hid = BNXT_ULP_CLASS_HID_21f3f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1659] = { - .class_hid = BNXT_ULP_CLASS_HID_3108b, + .class_hid = BNXT_ULP_CLASS_HID_2031f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1660] = { - .class_hid = BNXT_ULP_CLASS_HID_39b8b, + .class_hid = BNXT_ULP_CLASS_HID_2095b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1661] = { - .class_hid = BNXT_ULP_CLASS_HID_24427, + .class_hid = BNXT_ULP_CLASS_HID_23c57, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1662] = { - .class_hid = BNXT_ULP_CLASS_HID_2cf27, + .class_hid = BNXT_ULP_CLASS_HID_24293, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1663] = { - .class_hid = BNXT_ULP_CLASS_HID_35a27, + .class_hid = BNXT_ULP_CLASS_HID_226f3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1664] = { - .class_hid = BNXT_ULP_CLASS_HID_388fb, + .class_hid = BNXT_ULP_CLASS_HID_22ccf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1665] = { - .class_hid = BNXT_ULP_CLASS_HID_23ffb, + .class_hid = BNXT_ULP_CLASS_HID_62707, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1666] = { - .class_hid = BNXT_ULP_CLASS_HID_2cafb, + .class_hid = BNXT_ULP_CLASS_HID_62d43, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1667] = { - .class_hid = BNXT_ULP_CLASS_HID_355fb, + .class_hid = BNXT_ULP_CLASS_HID_611a3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1668] = { - .class_hid = BNXT_ULP_CLASS_HID_3838f, + .class_hid = BNXT_ULP_CLASS_HID_617ff, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1669] = { - .class_hid = BNXT_ULP_CLASS_HID_2528b, + .class_hid = BNXT_ULP_CLASS_HID_64afb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1670] = { - .class_hid = BNXT_ULP_CLASS_HID_2815f, + .class_hid = BNXT_ULP_CLASS_HID_65137, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1671] = { - .class_hid = BNXT_ULP_CLASS_HID_30c5f, + .class_hid = BNXT_ULP_CLASS_HID_63517, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1672] = { - .class_hid = BNXT_ULP_CLASS_HID_3975f, + .class_hid = BNXT_ULP_CLASS_HID_63b53, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1673] = { - .class_hid = BNXT_ULP_CLASS_HID_21e3f, + .class_hid = BNXT_ULP_CLASS_HID_61437, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1674] = { - .class_hid = BNXT_ULP_CLASS_HID_2a93f, + .class_hid = BNXT_ULP_CLASS_HID_61a73, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1675] = { - .class_hid = BNXT_ULP_CLASS_HID_3343f, + .class_hid = BNXT_ULP_CLASS_HID_65b1f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1676] = { - .class_hid = BNXT_ULP_CLASS_HID_3bf3f, + .class_hid = BNXT_ULP_CLASS_HID_604af, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1677] = { - .class_hid = BNXT_ULP_CLASS_HID_20b6f, + .class_hid = BNXT_ULP_CLASS_HID_637ab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1678] = { - .class_hid = BNXT_ULP_CLASS_HID_2966f, + .class_hid = BNXT_ULP_CLASS_HID_63de7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1679] = { - .class_hid = BNXT_ULP_CLASS_HID_3216f, + .class_hid = BNXT_ULP_CLASS_HID_621c7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1680] = { - .class_hid = BNXT_ULP_CLASS_HID_3ac6f, + .class_hid = BNXT_ULP_CLASS_HID_62803, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1681] = { - .class_hid = BNXT_ULP_CLASS_HID_20623, + .class_hid = BNXT_ULP_CLASS_HID_34233, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1682] = { - .class_hid = BNXT_ULP_CLASS_HID_29123, + .class_hid = BNXT_ULP_CLASS_HID_3480f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1683] = { - .class_hid = BNXT_ULP_CLASS_HID_31c23, + .class_hid = BNXT_ULP_CLASS_HID_32c6f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1684] = { - .class_hid = BNXT_ULP_CLASS_HID_3a723, + .class_hid = BNXT_ULP_CLASS_HID_332ab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1685] = { - .class_hid = BNXT_ULP_CLASS_HID_219f3, + .class_hid = BNXT_ULP_CLASS_HID_308fb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1686] = { - .class_hid = BNXT_ULP_CLASS_HID_2a4f3, + .class_hid = BNXT_ULP_CLASS_HID_30f37, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1687] = { - .class_hid = BNXT_ULP_CLASS_HID_32ff3, + .class_hid = BNXT_ULP_CLASS_HID_34fc3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1688] = { - .class_hid = BNXT_ULP_CLASS_HID_3baf3, + .class_hid = BNXT_ULP_CLASS_HID_3561f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1689] = { - .class_hid = BNXT_ULP_CLASS_HID_24253, + .class_hid = BNXT_ULP_CLASS_HID_32ee3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1690] = { - .class_hid = BNXT_ULP_CLASS_HID_2cd53, + .class_hid = BNXT_ULP_CLASS_HID_3353f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 130, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1691] = { - .class_hid = BNXT_ULP_CLASS_HID_35853, + .class_hid = BNXT_ULP_CLASS_HID_3191f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1692] = { - .class_hid = BNXT_ULP_CLASS_HID_38667, + .class_hid = BNXT_ULP_CLASS_HID_31f5b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 132, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1693] = { - .class_hid = BNXT_ULP_CLASS_HID_22e83, + .class_hid = BNXT_ULP_CLASS_HID_35257, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 133, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1694] = { - .class_hid = BNXT_ULP_CLASS_HID_2b983, + .class_hid = BNXT_ULP_CLASS_HID_35893, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 133, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1695] = { - .class_hid = BNXT_ULP_CLASS_HID_34483, + .class_hid = BNXT_ULP_CLASS_HID_33cf3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 133, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1696] = { - .class_hid = BNXT_ULP_CLASS_HID_3cf83, + .class_hid = BNXT_ULP_CLASS_HID_342cf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 133, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1697] = { - .class_hid = BNXT_ULP_CLASS_HID_22a57, + .class_hid = BNXT_ULP_CLASS_HID_73d07, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 133, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1698] = { - .class_hid = BNXT_ULP_CLASS_HID_2b557, + .class_hid = BNXT_ULP_CLASS_HID_74343, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 133, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1699] = { - .class_hid = BNXT_ULP_CLASS_HID_34057, + .class_hid = BNXT_ULP_CLASS_HID_727a3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 134, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1700] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb57, + .class_hid = BNXT_ULP_CLASS_HID_72dff, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 135, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1701] = { - .class_hid = BNXT_ULP_CLASS_HID_23d67, + .class_hid = BNXT_ULP_CLASS_HID_703cf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1702] = { - .class_hid = BNXT_ULP_CLASS_HID_2c867, + .class_hid = BNXT_ULP_CLASS_HID_70a0b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1703] = { - .class_hid = BNXT_ULP_CLASS_HID_35367, + .class_hid = BNXT_ULP_CLASS_HID_74b17, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1704] = { - .class_hid = BNXT_ULP_CLASS_HID_3813b, + .class_hid = BNXT_ULP_CLASS_HID_75153, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1705] = { - .class_hid = BNXT_ULP_CLASS_HID_2089b, + .class_hid = BNXT_ULP_CLASS_HID_72a37, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1706] = { - .class_hid = BNXT_ULP_CLASS_HID_2939b, + .class_hid = BNXT_ULP_CLASS_HID_73073, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1707] = { - .class_hid = BNXT_ULP_CLASS_HID_31e9b, + .class_hid = BNXT_ULP_CLASS_HID_71453, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1708] = { - .class_hid = BNXT_ULP_CLASS_HID_3a99b, + .class_hid = BNXT_ULP_CLASS_HID_71aaf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1709] = { - .class_hid = BNXT_ULP_CLASS_HID_25237, + .class_hid = BNXT_ULP_CLASS_HID_74dab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1710] = { - .class_hid = BNXT_ULP_CLASS_HID_280cb, + .class_hid = BNXT_ULP_CLASS_HID_753e7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1711] = { - .class_hid = BNXT_ULP_CLASS_HID_30bcb, + .class_hid = BNXT_ULP_CLASS_HID_737c7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1712] = { - .class_hid = BNXT_ULP_CLASS_HID_396cb, + .class_hid = BNXT_ULP_CLASS_HID_73e03, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1713] = { - .class_hid = BNXT_ULP_CLASS_HID_24dcb, + .class_hid = BNXT_ULP_CLASS_HID_2b733, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1714] = { - .class_hid = BNXT_ULP_CLASS_HID_2d8cb, + .class_hid = BNXT_ULP_CLASS_HID_2bd0f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1715] = { - .class_hid = BNXT_ULP_CLASS_HID_3069f, + .class_hid = BNXT_ULP_CLASS_HID_2a16f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1716] = { - .class_hid = BNXT_ULP_CLASS_HID_3919f, + .class_hid = BNXT_ULP_CLASS_HID_2a7ab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1717] = { - .class_hid = BNXT_ULP_CLASS_HID_203af, + .class_hid = BNXT_ULP_CLASS_HID_2daa7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1718] = { - .class_hid = BNXT_ULP_CLASS_HID_28eaf, + .class_hid = BNXT_ULP_CLASS_HID_28437, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1719] = { - .class_hid = BNXT_ULP_CLASS_HID_319af, + .class_hid = BNXT_ULP_CLASS_HID_2c4c3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1720] = { - .class_hid = BNXT_ULP_CLASS_HID_3a4af, + .class_hid = BNXT_ULP_CLASS_HID_2cb1f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1721] = { - .class_hid = BNXT_ULP_CLASS_HID_2513b, + .class_hid = BNXT_ULP_CLASS_HID_2a3e3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1722] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc3b, + .class_hid = BNXT_ULP_CLASS_HID_2aa3f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1723] = { - .class_hid = BNXT_ULP_CLASS_HID_30acf, + .class_hid = BNXT_ULP_CLASS_HID_28e1f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1724] = { - .class_hid = BNXT_ULP_CLASS_HID_395cf, + .class_hid = BNXT_ULP_CLASS_HID_2945b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1725] = { - .class_hid = BNXT_ULP_CLASS_HID_23e6b, + .class_hid = BNXT_ULP_CLASS_HID_2c757, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1726] = { - .class_hid = BNXT_ULP_CLASS_HID_2c96b, + .class_hid = BNXT_ULP_CLASS_HID_2cd93, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1727] = { - .class_hid = BNXT_ULP_CLASS_HID_3546b, + .class_hid = BNXT_ULP_CLASS_HID_2b1f3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1728] = { - .class_hid = BNXT_ULP_CLASS_HID_3823f, + .class_hid = BNXT_ULP_CLASS_HID_2b7cf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1729] = { - .class_hid = BNXT_ULP_CLASS_HID_2393f, + .class_hid = BNXT_ULP_CLASS_HID_6b207, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1730] = { - .class_hid = BNXT_ULP_CLASS_HID_2c43f, + .class_hid = BNXT_ULP_CLASS_HID_6b843, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1731] = { - .class_hid = BNXT_ULP_CLASS_HID_34f3f, + .class_hid = BNXT_ULP_CLASS_HID_69ca3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1732] = { - .class_hid = BNXT_ULP_CLASS_HID_3da3f, + .class_hid = BNXT_ULP_CLASS_HID_6a2ff, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1733] = { - .class_hid = BNXT_ULP_CLASS_HID_24ccf, + .class_hid = BNXT_ULP_CLASS_HID_6d5fb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1734] = { - .class_hid = BNXT_ULP_CLASS_HID_2d7cf, + .class_hid = BNXT_ULP_CLASS_HID_6dc37, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1735] = { - .class_hid = BNXT_ULP_CLASS_HID_30583, + .class_hid = BNXT_ULP_CLASS_HID_6c017, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1736] = { - .class_hid = BNXT_ULP_CLASS_HID_39083, + .class_hid = BNXT_ULP_CLASS_HID_6c653, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1737] = { - .class_hid = BNXT_ULP_CLASS_HID_21863, + .class_hid = BNXT_ULP_CLASS_HID_69f37, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1738] = { - .class_hid = BNXT_ULP_CLASS_HID_2a363, + .class_hid = BNXT_ULP_CLASS_HID_6a573, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1739] = { - .class_hid = BNXT_ULP_CLASS_HID_32e63, + .class_hid = BNXT_ULP_CLASS_HID_68953, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1740] = { - .class_hid = BNXT_ULP_CLASS_HID_3b963, + .class_hid = BNXT_ULP_CLASS_HID_68faf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1741] = { - .class_hid = BNXT_ULP_CLASS_HID_20553, + .class_hid = BNXT_ULP_CLASS_HID_6c2ab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1742] = { - .class_hid = BNXT_ULP_CLASS_HID_29053, + .class_hid = BNXT_ULP_CLASS_HID_6c8e7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1743] = { - .class_hid = BNXT_ULP_CLASS_HID_31b53, + .class_hid = BNXT_ULP_CLASS_HID_6acc7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1744] = { - .class_hid = BNXT_ULP_CLASS_HID_3a653, + .class_hid = BNXT_ULP_CLASS_HID_6b303, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1745] = { - .class_hid = BNXT_ULP_CLASS_HID_20067, + .class_hid = BNXT_ULP_CLASS_HID_3cd33, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1746] = { - .class_hid = BNXT_ULP_CLASS_HID_28b67, + .class_hid = BNXT_ULP_CLASS_HID_3d30f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1747] = { - .class_hid = BNXT_ULP_CLASS_HID_31667, + .class_hid = BNXT_ULP_CLASS_HID_3b76f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1748] = { - .class_hid = BNXT_ULP_CLASS_HID_3a167, + .class_hid = BNXT_ULP_CLASS_HID_3bdab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1749] = { - .class_hid = BNXT_ULP_CLASS_HID_21337, + .class_hid = BNXT_ULP_CLASS_HID_393fb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1750] = { - .class_hid = BNXT_ULP_CLASS_HID_29e37, + .class_hid = BNXT_ULP_CLASS_HID_39a37, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1751] = { - .class_hid = BNXT_ULP_CLASS_HID_32937, + .class_hid = BNXT_ULP_CLASS_HID_3dac3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1752] = { - .class_hid = BNXT_ULP_CLASS_HID_3b437, + .class_hid = BNXT_ULP_CLASS_HID_38453, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1753] = { - .class_hid = BNXT_ULP_CLASS_HID_23b97, + .class_hid = BNXT_ULP_CLASS_HID_3b9e3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1754] = { - .class_hid = BNXT_ULP_CLASS_HID_2c697, + .class_hid = BNXT_ULP_CLASS_HID_3c03f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1755] = { - .class_hid = BNXT_ULP_CLASS_HID_35197, + .class_hid = BNXT_ULP_CLASS_HID_3a41f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1756] = { - .class_hid = BNXT_ULP_CLASS_HID_3dc97, + .class_hid = BNXT_ULP_CLASS_HID_3aa5b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1757] = { - .class_hid = BNXT_ULP_CLASS_HID_228c7, + .class_hid = BNXT_ULP_CLASS_HID_380ab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1758] = { - .class_hid = BNXT_ULP_CLASS_HID_2b3c7, + .class_hid = BNXT_ULP_CLASS_HID_386e7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1759] = { - .class_hid = BNXT_ULP_CLASS_HID_33ec7, + .class_hid = BNXT_ULP_CLASS_HID_3c7f3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1760] = { - .class_hid = BNXT_ULP_CLASS_HID_3c9c7, + .class_hid = BNXT_ULP_CLASS_HID_3cdcf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1761] = { - .class_hid = BNXT_ULP_CLASS_HID_2239b, + .class_hid = BNXT_ULP_CLASS_HID_7c807, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1762] = { - .class_hid = BNXT_ULP_CLASS_HID_2ae9b, + .class_hid = BNXT_ULP_CLASS_HID_7ce43, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1763] = { - .class_hid = BNXT_ULP_CLASS_HID_3399b, + .class_hid = BNXT_ULP_CLASS_HID_7b2a3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1764] = { - .class_hid = BNXT_ULP_CLASS_HID_3c49b, + .class_hid = BNXT_ULP_CLASS_HID_7b8ff, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1765] = { - .class_hid = BNXT_ULP_CLASS_HID_236ab, + .class_hid = BNXT_ULP_CLASS_HID_78ecf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1766] = { - .class_hid = BNXT_ULP_CLASS_HID_2c1ab, + .class_hid = BNXT_ULP_CLASS_HID_7950b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1767] = { - .class_hid = BNXT_ULP_CLASS_HID_34cab, + .class_hid = BNXT_ULP_CLASS_HID_7d617, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1768] = { - .class_hid = BNXT_ULP_CLASS_HID_3d7ab, + .class_hid = BNXT_ULP_CLASS_HID_7dc53, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1769] = { - .class_hid = BNXT_ULP_CLASS_HID_202df, + .class_hid = BNXT_ULP_CLASS_HID_7b537, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1770] = { - .class_hid = BNXT_ULP_CLASS_HID_28ddf, + .class_hid = BNXT_ULP_CLASS_HID_7bb73, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1771] = { - .class_hid = BNXT_ULP_CLASS_HID_318df, + .class_hid = BNXT_ULP_CLASS_HID_79f53, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1772] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3df, + .class_hid = BNXT_ULP_CLASS_HID_7a5af, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1773] = { - .class_hid = BNXT_ULP_CLASS_HID_24c7b, + .class_hid = BNXT_ULP_CLASS_HID_7d8ab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1774] = { - .class_hid = BNXT_ULP_CLASS_HID_2d77b, + .class_hid = BNXT_ULP_CLASS_HID_7823b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1775] = { - .class_hid = BNXT_ULP_CLASS_HID_3050f, + .class_hid = BNXT_ULP_CLASS_HID_7c2c7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1776] = { - .class_hid = BNXT_ULP_CLASS_HID_3900f, + .class_hid = BNXT_ULP_CLASS_HID_7c903, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1777] = { - .class_hid = BNXT_ULP_CLASS_HID_2470f, + .class_hid = BNXT_ULP_CLASS_HID_8b2b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1778] = { - .class_hid = BNXT_ULP_CLASS_HID_2d20f, + .class_hid = BNXT_ULP_CLASS_HID_9117, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1779] = { - .class_hid = BNXT_ULP_CLASS_HID_300c3, + .class_hid = BNXT_ULP_CLASS_HID_d203, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1780] = { - .class_hid = BNXT_ULP_CLASS_HID_38bc3, + .class_hid = BNXT_ULP_CLASS_HID_d84f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1781] = { - .class_hid = BNXT_ULP_CLASS_HID_25adf, + .class_hid = BNXT_ULP_CLASS_HID_aebf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1782] = { - .class_hid = BNXT_ULP_CLASS_HID_28893, + .class_hid = BNXT_ULP_CLASS_HID_b4fb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1783] = { - .class_hid = BNXT_ULP_CLASS_HID_31393, + .class_hid = BNXT_ULP_CLASS_HID_98db, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1784] = { - .class_hid = BNXT_ULP_CLASS_HID_39e93, + .class_hid = BNXT_ULP_CLASS_HID_9f07, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1785] = { - .class_hid = BNXT_ULP_CLASS_HID_24b7f, + .class_hid = BNXT_ULP_CLASS_HID_4861f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1786] = { - .class_hid = BNXT_ULP_CLASS_HID_2d67f, + .class_hid = BNXT_ULP_CLASS_HID_48c5b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1787] = { - .class_hid = BNXT_ULP_CLASS_HID_30433, + .class_hid = BNXT_ULP_CLASS_HID_4cd77, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1788] = { - .class_hid = BNXT_ULP_CLASS_HID_38f33, + .class_hid = BNXT_ULP_CLASS_HID_4d3b3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1789] = { - .class_hid = BNXT_ULP_CLASS_HID_237af, + .class_hid = BNXT_ULP_CLASS_HID_4a9e3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1790] = { - .class_hid = BNXT_ULP_CLASS_HID_2c2af, + .class_hid = BNXT_ULP_CLASS_HID_4b02f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1791] = { - .class_hid = BNXT_ULP_CLASS_HID_34daf, + .class_hid = BNXT_ULP_CLASS_HID_4940f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1792] = { - .class_hid = BNXT_ULP_CLASS_HID_3d8af, + .class_hid = BNXT_ULP_CLASS_HID_49a4b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1793] = { - .class_hid = BNXT_ULP_CLASS_HID_23363, + .class_hid = BNXT_ULP_CLASS_HID_1a12b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1794] = { - .class_hid = BNXT_ULP_CLASS_HID_2be63, + .class_hid = BNXT_ULP_CLASS_HID_1a717, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1795] = { - .class_hid = BNXT_ULP_CLASS_HID_34963, + .class_hid = BNXT_ULP_CLASS_HID_18b77, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1796] = { - .class_hid = BNXT_ULP_CLASS_HID_3d463, + .class_hid = BNXT_ULP_CLASS_HID_191b3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1797] = { - .class_hid = BNXT_ULP_CLASS_HID_24633, + .class_hid = BNXT_ULP_CLASS_HID_1c4bf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1798] = { - .class_hid = BNXT_ULP_CLASS_HID_2d133, + .class_hid = BNXT_ULP_CLASS_HID_1cafb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1799] = { - .class_hid = BNXT_ULP_CLASS_HID_35c33, + .class_hid = BNXT_ULP_CLASS_HID_1aedb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1800] = { - .class_hid = BNXT_ULP_CLASS_HID_38ac7, + .class_hid = BNXT_ULP_CLASS_HID_1b507, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1801] = { - .class_hid = BNXT_ULP_CLASS_HID_211a7, + .class_hid = BNXT_ULP_CLASS_HID_59c1f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1802] = { - .class_hid = BNXT_ULP_CLASS_HID_29ca7, + .class_hid = BNXT_ULP_CLASS_HID_5a25b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1803] = { - .class_hid = BNXT_ULP_CLASS_HID_327a7, + .class_hid = BNXT_ULP_CLASS_HID_586bb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1804] = { - .class_hid = BNXT_ULP_CLASS_HID_3b2a7, + .class_hid = BNXT_ULP_CLASS_HID_58ce7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1805] = { - .class_hid = BNXT_ULP_CLASS_HID_25bc3, + .class_hid = BNXT_ULP_CLASS_HID_5bfe3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1806] = { - .class_hid = BNXT_ULP_CLASS_HID_28997, + .class_hid = BNXT_ULP_CLASS_HID_5c62f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1807] = { - .class_hid = BNXT_ULP_CLASS_HID_31497, + .class_hid = BNXT_ULP_CLASS_HID_5aa0f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1808] = { - .class_hid = BNXT_ULP_CLASS_HID_39f97, + .class_hid = BNXT_ULP_CLASS_HID_5b04b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1809] = { - .class_hid = BNXT_ULP_CLASS_HID_25697, + .class_hid = BNXT_ULP_CLASS_HID_d0ab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1810] = { - .class_hid = BNXT_ULP_CLASS_HID_284ab, + .class_hid = BNXT_ULP_CLASS_HID_d697, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1811] = { - .class_hid = BNXT_ULP_CLASS_HID_30fab, + .class_hid = BNXT_ULP_CLASS_HID_d783, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1812] = { - .class_hid = BNXT_ULP_CLASS_HID_39aab, + .class_hid = BNXT_ULP_CLASS_HID_c133, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1813] = { - .class_hid = BNXT_ULP_CLASS_HID_20d7b, + .class_hid = BNXT_ULP_CLASS_HID_f43f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1814] = { - .class_hid = BNXT_ULP_CLASS_HID_2987b, + .class_hid = BNXT_ULP_CLASS_HID_fa7b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1815] = { - .class_hid = BNXT_ULP_CLASS_HID_3237b, + .class_hid = BNXT_ULP_CLASS_HID_de5b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1816] = { - .class_hid = BNXT_ULP_CLASS_HID_3ae7b, + .class_hid = BNXT_ULP_CLASS_HID_e487, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1817] = { - .class_hid = BNXT_ULP_CLASS_HID_235db, + .class_hid = BNXT_ULP_CLASS_HID_4cb9f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1818] = { - .class_hid = BNXT_ULP_CLASS_HID_2c0db, + .class_hid = BNXT_ULP_CLASS_HID_4d1db, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 136, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1819] = { - .class_hid = BNXT_ULP_CLASS_HID_34bdb, + .class_hid = BNXT_ULP_CLASS_HID_4d2f7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 137, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1820] = { - .class_hid = BNXT_ULP_CLASS_HID_3d6db, + .class_hid = BNXT_ULP_CLASS_HID_4d933, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 138, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1821] = { - .class_hid = BNXT_ULP_CLASS_HID_2220b, + .class_hid = BNXT_ULP_CLASS_HID_4ef63, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 139, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1822] = { - .class_hid = BNXT_ULP_CLASS_HID_2ad0b, + .class_hid = BNXT_ULP_CLASS_HID_4f5af, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 139, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1823] = { - .class_hid = BNXT_ULP_CLASS_HID_3380b, + .class_hid = BNXT_ULP_CLASS_HID_4d98f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 139, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1824] = { - .class_hid = BNXT_ULP_CLASS_HID_3c30b, + .class_hid = BNXT_ULP_CLASS_HID_4dfcb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 139, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1825] = { - .class_hid = BNXT_ULP_CLASS_HID_21ddf, + .class_hid = BNXT_ULP_CLASS_HID_1e6ab, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 139, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1826] = { - .class_hid = BNXT_ULP_CLASS_HID_2a8df, + .class_hid = BNXT_ULP_CLASS_HID_1ec97, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 139, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1827] = { - .class_hid = BNXT_ULP_CLASS_HID_333df, + .class_hid = BNXT_ULP_CLASS_HID_1d0f7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 140, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1828] = { - .class_hid = BNXT_ULP_CLASS_HID_3bedf, + .class_hid = BNXT_ULP_CLASS_HID_1d733, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 141, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1829] = { - .class_hid = BNXT_ULP_CLASS_HID_230ef, + .class_hid = BNXT_ULP_CLASS_HID_1ca3f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1830] = { - .class_hid = BNXT_ULP_CLASS_HID_2bbef, + .class_hid = BNXT_ULP_CLASS_HID_1d07b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1831] = { - .class_hid = BNXT_ULP_CLASS_HID_346ef, + .class_hid = BNXT_ULP_CLASS_HID_1f45b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1832] = { - .class_hid = BNXT_ULP_CLASS_HID_3d1ef, + .class_hid = BNXT_ULP_CLASS_HID_1fa87, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1833] = { - .class_hid = BNXT_ULP_CLASS_HID_2594f, + .class_hid = BNXT_ULP_CLASS_HID_5e19f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1834] = { - .class_hid = BNXT_ULP_CLASS_HID_28703, + .class_hid = BNXT_ULP_CLASS_HID_5e7db, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1835] = { - .class_hid = BNXT_ULP_CLASS_HID_31203, + .class_hid = BNXT_ULP_CLASS_HID_5cc3b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1836] = { - .class_hid = BNXT_ULP_CLASS_HID_39d03, + .class_hid = BNXT_ULP_CLASS_HID_5d267, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1837] = { - .class_hid = BNXT_ULP_CLASS_HID_245bf, + .class_hid = BNXT_ULP_CLASS_HID_5c563, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1838] = { - .class_hid = BNXT_ULP_CLASS_HID_2d0bf, + .class_hid = BNXT_ULP_CLASS_HID_5cbaf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1839] = { - .class_hid = BNXT_ULP_CLASS_HID_35bbf, + .class_hid = BNXT_ULP_CLASS_HID_5ef8f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1840] = { - .class_hid = BNXT_ULP_CLASS_HID_38a73, + .class_hid = BNXT_ULP_CLASS_HID_5f5cb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1841] = { - .class_hid = BNXT_ULP_CLASS_HID_24173, + .class_hid = BNXT_ULP_CLASS_HID_adeb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1842] = { - .class_hid = BNXT_ULP_CLASS_HID_2cc73, + .class_hid = BNXT_ULP_CLASS_HID_b3d7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1843] = { - .class_hid = BNXT_ULP_CLASS_HID_35773, + .class_hid = BNXT_ULP_CLASS_HID_f4c3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1844] = { - .class_hid = BNXT_ULP_CLASS_HID_38507, + .class_hid = BNXT_ULP_CLASS_HID_fb0f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1845] = { - .class_hid = BNXT_ULP_CLASS_HID_25403, + .class_hid = BNXT_ULP_CLASS_HID_b17f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1846] = { - .class_hid = BNXT_ULP_CLASS_HID_282d7, + .class_hid = BNXT_ULP_CLASS_HID_b7bb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1847] = { - .class_hid = BNXT_ULP_CLASS_HID_30dd7, + .class_hid = BNXT_ULP_CLASS_HID_bb9b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1848] = { - .class_hid = BNXT_ULP_CLASS_HID_398d7, + .class_hid = BNXT_ULP_CLASS_HID_a1c7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1849] = { - .class_hid = BNXT_ULP_CLASS_HID_244a3, + .class_hid = BNXT_ULP_CLASS_HID_4a8df, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1850] = { - .class_hid = BNXT_ULP_CLASS_HID_2cfa3, + .class_hid = BNXT_ULP_CLASS_HID_4af1b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1851] = { - .class_hid = BNXT_ULP_CLASS_HID_35aa3, + .class_hid = BNXT_ULP_CLASS_HID_4f037, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1852] = { - .class_hid = BNXT_ULP_CLASS_HID_38977, + .class_hid = BNXT_ULP_CLASS_HID_4f673, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1853] = { - .class_hid = BNXT_ULP_CLASS_HID_23193, + .class_hid = BNXT_ULP_CLASS_HID_4aca3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1854] = { - .class_hid = BNXT_ULP_CLASS_HID_2bc93, + .class_hid = BNXT_ULP_CLASS_HID_4b2ef, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1855] = { - .class_hid = BNXT_ULP_CLASS_HID_34793, + .class_hid = BNXT_ULP_CLASS_HID_4b6cf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1856] = { - .class_hid = BNXT_ULP_CLASS_HID_3d293, + .class_hid = BNXT_ULP_CLASS_HID_4bd0b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1857] = { - .class_hid = BNXT_ULP_CLASS_HID_22ca7, + .class_hid = BNXT_ULP_CLASS_HID_1a3eb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1858] = { - .class_hid = BNXT_ULP_CLASS_HID_2b7a7, + .class_hid = BNXT_ULP_CLASS_HID_1a9d7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1859] = { - .class_hid = BNXT_ULP_CLASS_HID_342a7, + .class_hid = BNXT_ULP_CLASS_HID_1ae37, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1860] = { - .class_hid = BNXT_ULP_CLASS_HID_3cda7, + .class_hid = BNXT_ULP_CLASS_HID_1b473, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1861] = { - .class_hid = BNXT_ULP_CLASS_HID_24077, + .class_hid = BNXT_ULP_CLASS_HID_1e77f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1862] = { - .class_hid = BNXT_ULP_CLASS_HID_2cb77, + .class_hid = BNXT_ULP_CLASS_HID_1edbb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1863] = { - .class_hid = BNXT_ULP_CLASS_HID_35677, + .class_hid = BNXT_ULP_CLASS_HID_1b19b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1864] = { - .class_hid = BNXT_ULP_CLASS_HID_3840b, + .class_hid = BNXT_ULP_CLASS_HID_1b7c7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1865] = { - .class_hid = BNXT_ULP_CLASS_HID_20beb, + .class_hid = BNXT_ULP_CLASS_HID_5bedf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1866] = { - .class_hid = BNXT_ULP_CLASS_HID_296eb, + .class_hid = BNXT_ULP_CLASS_HID_5a51b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1867] = { - .class_hid = BNXT_ULP_CLASS_HID_321eb, + .class_hid = BNXT_ULP_CLASS_HID_5a97b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1868] = { - .class_hid = BNXT_ULP_CLASS_HID_3aceb, + .class_hid = BNXT_ULP_CLASS_HID_5afa7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1869] = { - .class_hid = BNXT_ULP_CLASS_HID_25507, + .class_hid = BNXT_ULP_CLASS_HID_5e2a3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1870] = { - .class_hid = BNXT_ULP_CLASS_HID_283db, + .class_hid = BNXT_ULP_CLASS_HID_5e8ef, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1871] = { - .class_hid = BNXT_ULP_CLASS_HID_30edb, + .class_hid = BNXT_ULP_CLASS_HID_5accf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1872] = { - .class_hid = BNXT_ULP_CLASS_HID_399db, + .class_hid = BNXT_ULP_CLASS_HID_5b30b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1873] = { - .class_hid = BNXT_ULP_CLASS_HID_250db, + .class_hid = BNXT_ULP_CLASS_HID_f36b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1874] = { - .class_hid = BNXT_ULP_CLASS_HID_2dbdb, + .class_hid = BNXT_ULP_CLASS_HID_f957, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1875] = { - .class_hid = BNXT_ULP_CLASS_HID_309ef, + .class_hid = BNXT_ULP_CLASS_HID_fa43, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1876] = { - .class_hid = BNXT_ULP_CLASS_HID_394ef, + .class_hid = BNXT_ULP_CLASS_HID_e3f3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1877] = { - .class_hid = BNXT_ULP_CLASS_HID_206bf, + .class_hid = BNXT_ULP_CLASS_HID_f6ff, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1878] = { - .class_hid = BNXT_ULP_CLASS_HID_291bf, + .class_hid = BNXT_ULP_CLASS_HID_fd3b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1879] = { - .class_hid = BNXT_ULP_CLASS_HID_31cbf, + .class_hid = BNXT_ULP_CLASS_HID_e11b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1880] = { - .class_hid = BNXT_ULP_CLASS_HID_3a7bf, + .class_hid = BNXT_ULP_CLASS_HID_e747, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1881] = { - .class_hid = BNXT_ULP_CLASS_HID_22f1f, + .class_hid = BNXT_ULP_CLASS_HID_4ee5f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1882] = { - .class_hid = BNXT_ULP_CLASS_HID_2ba1f, + .class_hid = BNXT_ULP_CLASS_HID_4f49b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1883] = { - .class_hid = BNXT_ULP_CLASS_HID_3451f, + .class_hid = BNXT_ULP_CLASS_HID_4f5b7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1884] = { - .class_hid = BNXT_ULP_CLASS_HID_3d01f, + .class_hid = BNXT_ULP_CLASS_HID_4fbf3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1885] = { - .class_hid = BNXT_ULP_CLASS_HID_21c4f, + .class_hid = BNXT_ULP_CLASS_HID_4f223, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1886] = { - .class_hid = BNXT_ULP_CLASS_HID_2a74f, + .class_hid = BNXT_ULP_CLASS_HID_4f86f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1887] = { - .class_hid = BNXT_ULP_CLASS_HID_3324f, + .class_hid = BNXT_ULP_CLASS_HID_4fc4f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1888] = { - .class_hid = BNXT_ULP_CLASS_HID_3bd4f, + .class_hid = BNXT_ULP_CLASS_HID_4e28b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1889] = { - .class_hid = BNXT_ULP_CLASS_HID_21703, + .class_hid = BNXT_ULP_CLASS_HID_1e96b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1890] = { - .class_hid = BNXT_ULP_CLASS_HID_2a203, + .class_hid = BNXT_ULP_CLASS_HID_1ef57, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1891] = { - .class_hid = BNXT_ULP_CLASS_HID_32d03, + .class_hid = BNXT_ULP_CLASS_HID_1f3b7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1892] = { - .class_hid = BNXT_ULP_CLASS_HID_3b803, + .class_hid = BNXT_ULP_CLASS_HID_1f9f3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1893] = { - .class_hid = BNXT_ULP_CLASS_HID_22ad3, + .class_hid = BNXT_ULP_CLASS_HID_1ecff, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1894] = { - .class_hid = BNXT_ULP_CLASS_HID_2b5d3, + .class_hid = BNXT_ULP_CLASS_HID_1f33b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1895] = { - .class_hid = BNXT_ULP_CLASS_HID_340d3, + .class_hid = BNXT_ULP_CLASS_HID_1f71b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1896] = { - .class_hid = BNXT_ULP_CLASS_HID_3cbd3, + .class_hid = BNXT_ULP_CLASS_HID_1fd47, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1897] = { - .class_hid = BNXT_ULP_CLASS_HID_252b3, + .class_hid = BNXT_ULP_CLASS_HID_5e45f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1898] = { - .class_hid = BNXT_ULP_CLASS_HID_28147, + .class_hid = BNXT_ULP_CLASS_HID_5ea9b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1899] = { - .class_hid = BNXT_ULP_CLASS_HID_30c47, + .class_hid = BNXT_ULP_CLASS_HID_5eefb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1900] = { - .class_hid = BNXT_ULP_CLASS_HID_39747, + .class_hid = BNXT_ULP_CLASS_HID_5f527, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1901] = { - .class_hid = BNXT_ULP_CLASS_HID_23fe3, + .class_hid = BNXT_ULP_CLASS_HID_5e823, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1902] = { - .class_hid = BNXT_ULP_CLASS_HID_2cae3, + .class_hid = BNXT_ULP_CLASS_HID_5ee6f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1903] = { - .class_hid = BNXT_ULP_CLASS_HID_355e3, + .class_hid = BNXT_ULP_CLASS_HID_5f24f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1904] = { - .class_hid = BNXT_ULP_CLASS_HID_383b7, + .class_hid = BNXT_ULP_CLASS_HID_5f88b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1905] = { - .class_hid = BNXT_ULP_CLASS_HID_23ab7, + .class_hid = BNXT_ULP_CLASS_HID_22c53, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -41757,20 +42541,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1906] = { - .class_hid = BNXT_ULP_CLASS_HID_2c5b7, + .class_hid = BNXT_ULP_CLASS_HID_2326f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -41778,21 +42557,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1907] = { - .class_hid = BNXT_ULP_CLASS_HID_350b7, + .class_hid = BNXT_ULP_CLASS_HID_2160f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -41800,21 +42574,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1908] = { - .class_hid = BNXT_ULP_CLASS_HID_3dbb7, + .class_hid = BNXT_ULP_CLASS_HID_21ccb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -41822,22 +42591,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1909] = { - .class_hid = BNXT_ULP_CLASS_HID_24e47, + .class_hid = BNXT_ULP_CLASS_HID_24fc7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -41845,19 +42609,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1910] = { - .class_hid = BNXT_ULP_CLASS_HID_2d947, + .class_hid = BNXT_ULP_CLASS_HID_25583, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -41865,20 +42626,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1911] = { - .class_hid = BNXT_ULP_CLASS_HID_3071b, + .class_hid = BNXT_ULP_CLASS_HID_239a3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -41886,20 +42644,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1912] = { - .class_hid = BNXT_ULP_CLASS_HID_3921b, + .class_hid = BNXT_ULP_CLASS_HID_2407f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -41907,20 +42662,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1913] = { - .class_hid = BNXT_ULP_CLASS_HID_2326f, + .class_hid = BNXT_ULP_CLASS_HID_21883, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -41929,15 +42681,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1914] = { - .class_hid = BNXT_ULP_CLASS_HID_2bd6f, + .class_hid = BNXT_ULP_CLASS_HID_21f5f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -41946,16 +42698,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1915] = { - .class_hid = BNXT_ULP_CLASS_HID_3486f, + .class_hid = BNXT_ULP_CLASS_HID_2037f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -41964,16 +42716,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1916] = { - .class_hid = BNXT_ULP_CLASS_HID_3d36f, + .class_hid = BNXT_ULP_CLASS_HID_2093b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -41982,17 +42734,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1917] = { - .class_hid = BNXT_ULP_CLASS_HID_21f5f, + .class_hid = BNXT_ULP_CLASS_HID_23c37, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42001,16 +42753,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1918] = { - .class_hid = BNXT_ULP_CLASS_HID_2aa5f, + .class_hid = BNXT_ULP_CLASS_HID_242f3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42019,17 +42771,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1919] = { - .class_hid = BNXT_ULP_CLASS_HID_3355f, + .class_hid = BNXT_ULP_CLASS_HID_22693, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42038,17 +42790,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1920] = { - .class_hid = BNXT_ULP_CLASS_HID_3c05f, + .class_hid = BNXT_ULP_CLASS_HID_22caf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42057,18 +42809,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1921] = { - .class_hid = BNXT_ULP_CLASS_HID_21a13, + .class_hid = BNXT_ULP_CLASS_HID_62767, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42077,17 +42829,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1922] = { - .class_hid = BNXT_ULP_CLASS_HID_2a513, + .class_hid = BNXT_ULP_CLASS_HID_62d23, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42096,18 +42846,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1923] = { - .class_hid = BNXT_ULP_CLASS_HID_33013, + .class_hid = BNXT_ULP_CLASS_HID_611c3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42116,18 +42864,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1924] = { - .class_hid = BNXT_ULP_CLASS_HID_3bb13, + .class_hid = BNXT_ULP_CLASS_HID_6179f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42136,19 +42882,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1925] = { - .class_hid = BNXT_ULP_CLASS_HID_22d23, + .class_hid = BNXT_ULP_CLASS_HID_64a9b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42157,16 +42901,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1926] = { - .class_hid = BNXT_ULP_CLASS_HID_2b823, + .class_hid = BNXT_ULP_CLASS_HID_65157, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42175,17 +42919,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1927] = { - .class_hid = BNXT_ULP_CLASS_HID_34323, + .class_hid = BNXT_ULP_CLASS_HID_63577, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42194,17 +42938,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1928] = { - .class_hid = BNXT_ULP_CLASS_HID_3ce23, + .class_hid = BNXT_ULP_CLASS_HID_63b33, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42213,18 +42957,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1929] = { - .class_hid = BNXT_ULP_CLASS_HID_25583, + .class_hid = BNXT_ULP_CLASS_HID_61457, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42233,16 +42977,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1930] = { - .class_hid = BNXT_ULP_CLASS_HID_28457, + .class_hid = BNXT_ULP_CLASS_HID_61a13, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42251,17 +42995,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1931] = { - .class_hid = BNXT_ULP_CLASS_HID_30f57, + .class_hid = BNXT_ULP_CLASS_HID_65b7f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42270,17 +43014,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1932] = { - .class_hid = BNXT_ULP_CLASS_HID_39a57, + .class_hid = BNXT_ULP_CLASS_HID_604cf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42289,18 +43033,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1933] = { - .class_hid = BNXT_ULP_CLASS_HID_242f3, + .class_hid = BNXT_ULP_CLASS_HID_637cb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42309,17 +43053,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1934] = { - .class_hid = BNXT_ULP_CLASS_HID_2cdf3, + .class_hid = BNXT_ULP_CLASS_HID_63d87, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42328,18 +43072,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1935] = { - .class_hid = BNXT_ULP_CLASS_HID_358f3, + .class_hid = BNXT_ULP_CLASS_HID_621a7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42348,18 +43092,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1936] = { - .class_hid = BNXT_ULP_CLASS_HID_38687, + .class_hid = BNXT_ULP_CLASS_HID_62863, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42368,19 +43112,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1937] = { - .class_hid = BNXT_ULP_CLASS_HID_23d87, + .class_hid = BNXT_ULP_CLASS_HID_34253, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42389,18 +43133,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1938] = { - .class_hid = BNXT_ULP_CLASS_HID_2c887, + .class_hid = BNXT_ULP_CLASS_HID_3486f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42409,19 +43150,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1939] = { - .class_hid = BNXT_ULP_CLASS_HID_35387, + .class_hid = BNXT_ULP_CLASS_HID_32c0f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42430,19 +43168,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1940] = { - .class_hid = BNXT_ULP_CLASS_HID_3825b, + .class_hid = BNXT_ULP_CLASS_HID_332cb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42451,20 +43186,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1941] = { - .class_hid = BNXT_ULP_CLASS_HID_25157, + .class_hid = BNXT_ULP_CLASS_HID_3089b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42473,17 +43205,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1942] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc57, + .class_hid = BNXT_ULP_CLASS_HID_30f57, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42492,18 +43223,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1943] = { - .class_hid = BNXT_ULP_CLASS_HID_30a6b, + .class_hid = BNXT_ULP_CLASS_HID_34fa3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42512,18 +43242,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1944] = { - .class_hid = BNXT_ULP_CLASS_HID_3956b, + .class_hid = BNXT_ULP_CLASS_HID_3567f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42532,19 +43261,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1945] = { - .class_hid = BNXT_ULP_CLASS_HID_22c53, + .class_hid = BNXT_ULP_CLASS_HID_32e83, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42553,14 +43281,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1946] = { - .class_hid = BNXT_ULP_CLASS_HID_2b753, + .class_hid = BNXT_ULP_CLASS_HID_3355f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42569,15 +43299,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1947] = { - .class_hid = BNXT_ULP_CLASS_HID_34253, + .class_hid = BNXT_ULP_CLASS_HID_3197f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42586,15 +43318,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1948] = { - .class_hid = BNXT_ULP_CLASS_HID_3cd53, + .class_hid = BNXT_ULP_CLASS_HID_31f3b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42603,16 +43337,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1949] = { - .class_hid = BNXT_ULP_CLASS_HID_21883, + .class_hid = BNXT_ULP_CLASS_HID_35237, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42621,15 +43357,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1950] = { - .class_hid = BNXT_ULP_CLASS_HID_2a383, + .class_hid = BNXT_ULP_CLASS_HID_358f3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42638,16 +43376,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1951] = { - .class_hid = BNXT_ULP_CLASS_HID_32e83, + .class_hid = BNXT_ULP_CLASS_HID_33c93, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42656,16 +43396,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1952] = { - .class_hid = BNXT_ULP_CLASS_HID_3b983, + .class_hid = BNXT_ULP_CLASS_HID_342af, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42674,17 +43416,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1953] = { - .class_hid = BNXT_ULP_CLASS_HID_21457, + .class_hid = BNXT_ULP_CLASS_HID_73d67, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42693,16 +43437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1954] = { - .class_hid = BNXT_ULP_CLASS_HID_29f57, + .class_hid = BNXT_ULP_CLASS_HID_74323, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42711,17 +43455,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1955] = { - .class_hid = BNXT_ULP_CLASS_HID_32a57, + .class_hid = BNXT_ULP_CLASS_HID_727c3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42730,17 +43474,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1956] = { - .class_hid = BNXT_ULP_CLASS_HID_3b557, + .class_hid = BNXT_ULP_CLASS_HID_72d9f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42749,18 +43493,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1957] = { - .class_hid = BNXT_ULP_CLASS_HID_22767, + .class_hid = BNXT_ULP_CLASS_HID_703af, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42769,15 +43513,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1958] = { - .class_hid = BNXT_ULP_CLASS_HID_2b267, + .class_hid = BNXT_ULP_CLASS_HID_70a6b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42786,16 +43532,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1959] = { - .class_hid = BNXT_ULP_CLASS_HID_33d67, + .class_hid = BNXT_ULP_CLASS_HID_74b77, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42804,16 +43552,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1960] = { - .class_hid = BNXT_ULP_CLASS_HID_3c867, + .class_hid = BNXT_ULP_CLASS_HID_75133, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42822,17 +43572,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1961] = { - .class_hid = BNXT_ULP_CLASS_HID_24fc7, + .class_hid = BNXT_ULP_CLASS_HID_72a57, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42841,15 +43593,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1962] = { - .class_hid = BNXT_ULP_CLASS_HID_2dac7, + .class_hid = BNXT_ULP_CLASS_HID_73013, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42858,16 +43612,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1963] = { - .class_hid = BNXT_ULP_CLASS_HID_3089b, + .class_hid = BNXT_ULP_CLASS_HID_71433, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42876,16 +43632,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1964] = { - .class_hid = BNXT_ULP_CLASS_HID_3939b, + .class_hid = BNXT_ULP_CLASS_HID_71acf, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42894,17 +43652,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1965] = { - .class_hid = BNXT_ULP_CLASS_HID_23c37, + .class_hid = BNXT_ULP_CLASS_HID_74dcb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42913,16 +43673,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1966] = { - .class_hid = BNXT_ULP_CLASS_HID_2c737, + .class_hid = BNXT_ULP_CLASS_HID_75387, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42931,17 +43693,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1967] = { - .class_hid = BNXT_ULP_CLASS_HID_35237, + .class_hid = BNXT_ULP_CLASS_HID_737a7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42950,17 +43714,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1968] = { - .class_hid = BNXT_ULP_CLASS_HID_380cb, + .class_hid = BNXT_ULP_CLASS_HID_73e63, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42969,18 +43735,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1969] = { - .class_hid = BNXT_ULP_CLASS_HID_237cb, + .class_hid = BNXT_ULP_CLASS_HID_2b753, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -42989,17 +43757,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1970] = { - .class_hid = BNXT_ULP_CLASS_HID_2c2cb, + .class_hid = BNXT_ULP_CLASS_HID_2bd6f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -43008,18 +43774,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1971] = { - .class_hid = BNXT_ULP_CLASS_HID_34dcb, + .class_hid = BNXT_ULP_CLASS_HID_2a10f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -43028,18 +43792,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1972] = { - .class_hid = BNXT_ULP_CLASS_HID_3d8cb, + .class_hid = BNXT_ULP_CLASS_HID_2a7cb, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -43048,19 +43810,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1973] = { - .class_hid = BNXT_ULP_CLASS_HID_24a9b, + .class_hid = BNXT_ULP_CLASS_HID_2dac7, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -43069,16 +43829,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1974] = { - .class_hid = BNXT_ULP_CLASS_HID_2d59b, + .class_hid = BNXT_ULP_CLASS_HID_28457, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -43087,17 +43847,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1975] = { - .class_hid = BNXT_ULP_CLASS_HID_303af, + .class_hid = BNXT_ULP_CLASS_HID_2c4a3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -43106,17 +43866,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1976] = { - .class_hid = BNXT_ULP_CLASS_HID_38eaf, + .class_hid = BNXT_ULP_CLASS_HID_2cb7f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -43125,19 +43885,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1977] = { - .class_hid = BNXT_ULP_CLASS_HID_253b, + .class_hid = BNXT_ULP_CLASS_HID_2a383, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43145,16 +43905,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1978] = { - .class_hid = BNXT_ULP_CLASS_HID_2bf7, + .class_hid = BNXT_ULP_CLASS_HID_2aa5f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43162,17 +43923,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1979] = { - .class_hid = BNXT_ULP_CLASS_HID_1827, + .class_hid = BNXT_ULP_CLASS_HID_28e7f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43180,18 +43942,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1980] = { - .class_hid = BNXT_ULP_CLASS_HID_4f6b, + .class_hid = BNXT_ULP_CLASS_HID_2943b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43199,18 +43961,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1981] = { - .class_hid = BNXT_ULP_CLASS_HID_3c5b, + .class_hid = BNXT_ULP_CLASS_HID_2c737, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43218,19 +43981,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1982] = { - .class_hid = BNXT_ULP_CLASS_HID_1653, + .class_hid = BNXT_ULP_CLASS_HID_2cdf3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43238,18 +44000,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, [1983] = { - .class_hid = BNXT_ULP_CLASS_HID_0283, + .class_hid = BNXT_ULP_CLASS_HID_2b193, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43257,19 +44020,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1984] = { - .class_hid = BNXT_ULP_CLASS_HID_39c7, + .class_hid = BNXT_ULP_CLASS_HID_2b7af, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43277,19 +44040,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1985] = { - .class_hid = BNXT_ULP_CLASS_HID_2637, + .class_hid = BNXT_ULP_CLASS_HID_6b267, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43297,20 +44061,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1986] = { - .class_hid = BNXT_ULP_CLASS_HID_126b, + .class_hid = BNXT_ULP_CLASS_HID_6b823, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43318,17 +44079,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1987] = { - .class_hid = BNXT_ULP_CLASS_HID_48af, + .class_hid = BNXT_ULP_CLASS_HID_69cc3, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43336,17 +44098,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1988] = { - .class_hid = BNXT_ULP_CLASS_HID_359f, + .class_hid = BNXT_ULP_CLASS_HID_6a29f, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43354,18 +44117,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1989] = { - .class_hid = BNXT_ULP_CLASS_HID_0f97, + .class_hid = BNXT_ULP_CLASS_HID_6d59b, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43373,17 +44137,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1990] = { - .class_hid = BNXT_ULP_CLASS_HID_5933, + .class_hid = BNXT_ULP_CLASS_HID_6dc57, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43391,18 +44156,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1991] = { - .class_hid = BNXT_ULP_CLASS_HID_330b, + .class_hid = BNXT_ULP_CLASS_HID_6c077, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43410,18 +44176,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1992] = { - .class_hid = BNXT_ULP_CLASS_HID_207b, + .class_hid = BNXT_ULP_CLASS_HID_6c633, .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 142, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -43429,10090 +44196,22259 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1993] = { - .class_hid = BNXT_ULP_CLASS_HID_374e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 142, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_69f57, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1994] = { - .class_hid = BNXT_ULP_CLASS_HID_11ee, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 143, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_6a513, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1995] = { - .class_hid = BNXT_ULP_CLASS_HID_423a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 143, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_68933, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1996] = { - .class_hid = BNXT_ULP_CLASS_HID_0cd6, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 144, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_68fcf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1997] = { - .class_hid = BNXT_ULP_CLASS_HID_310a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 144, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_6c2cb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1998] = { - .class_hid = BNXT_ULP_CLASS_HID_469e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 144, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_6c887, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [1999] = { - .class_hid = BNXT_ULP_CLASS_HID_5ce6, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 144, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_6aca7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2000] = { - .class_hid = BNXT_ULP_CLASS_HID_0692, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 144, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_6b363, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2001] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 144, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_3cd53, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2002] = { - .class_hid = BNXT_ULP_CLASS_HID_55c2, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 145, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_3d36f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2003] = { - .class_hid = BNXT_ULP_CLASS_HID_2b2a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 145, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_3b70f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2004] = { - .class_hid = BNXT_ULP_CLASS_HID_15c6, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 146, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_3bdcb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2005] = { - .class_hid = BNXT_ULP_CLASS_HID_163a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 146, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_3939b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2006] = { - .class_hid = BNXT_ULP_CLASS_HID_2f8e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 146, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_39a57, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2007] = { - .class_hid = BNXT_ULP_CLASS_HID_2516, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 146, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_3daa3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2008] = { - .class_hid = BNXT_ULP_CLASS_HID_4b76, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 146, - .flow_pattern_id = 0, + .class_hid = BNXT_ULP_CLASS_HID_38433, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2009] = { - .class_hid = BNXT_ULP_CLASS_HID_10e6, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 146, + .class_hid = BNXT_ULP_CLASS_HID_3b983, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2010] = { - .class_hid = BNXT_ULP_CLASS_HID_264a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 147, + .class_hid = BNXT_ULP_CLASS_HID_3c05f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2011] = { - .class_hid = BNXT_ULP_CLASS_HID_3fd2, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 147, + .class_hid = BNXT_ULP_CLASS_HID_3a47f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2012] = { - .class_hid = BNXT_ULP_CLASS_HID_4532, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 148, + .class_hid = BNXT_ULP_CLASS_HID_3aa3b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2013] = { - .class_hid = BNXT_ULP_CLASS_HID_4996, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 148, + .class_hid = BNXT_ULP_CLASS_HID_380cb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2014] = { - .class_hid = BNXT_ULP_CLASS_HID_2036, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 148, + .class_hid = BNXT_ULP_CLASS_HID_38687, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, [2015] = { - .class_hid = BNXT_ULP_CLASS_HID_399e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 148, + .class_hid = BNXT_ULP_CLASS_HID_3c793, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, [2016] = { - .class_hid = BNXT_ULP_CLASS_HID_5ffe, + .class_hid = BNXT_ULP_CLASS_HID_3cdaf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2017] = { + .class_hid = BNXT_ULP_CLASS_HID_7c867, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2018] = { + .class_hid = BNXT_ULP_CLASS_HID_7ce23, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2019] = { + .class_hid = BNXT_ULP_CLASS_HID_7b2c3, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2020] = { + .class_hid = BNXT_ULP_CLASS_HID_7b89f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2021] = { + .class_hid = BNXT_ULP_CLASS_HID_78eaf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2022] = { + .class_hid = BNXT_ULP_CLASS_HID_7956b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2023] = { + .class_hid = BNXT_ULP_CLASS_HID_7d677, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2024] = { + .class_hid = BNXT_ULP_CLASS_HID_7dc33, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2025] = { + .class_hid = BNXT_ULP_CLASS_HID_7b557, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2026] = { + .class_hid = BNXT_ULP_CLASS_HID_7bb13, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2027] = { + .class_hid = BNXT_ULP_CLASS_HID_79f33, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2028] = { + .class_hid = BNXT_ULP_CLASS_HID_7a5cf, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2029] = { + .class_hid = BNXT_ULP_CLASS_HID_7d8cb, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2030] = { + .class_hid = BNXT_ULP_CLASS_HID_7825b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2031] = { + .class_hid = BNXT_ULP_CLASS_HID_7c2a7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2032] = { + .class_hid = BNXT_ULP_CLASS_HID_7c963, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2033] = { + .class_hid = BNXT_ULP_CLASS_HID_8b4b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2034] = { + .class_hid = BNXT_ULP_CLASS_HID_9177, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2035] = { + .class_hid = BNXT_ULP_CLASS_HID_d263, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2036] = { + .class_hid = BNXT_ULP_CLASS_HID_d82f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2037] = { + .class_hid = BNXT_ULP_CLASS_HID_aedf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2038] = { + .class_hid = BNXT_ULP_CLASS_HID_b49b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2039] = { + .class_hid = BNXT_ULP_CLASS_HID_98bb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2040] = { + .class_hid = BNXT_ULP_CLASS_HID_9f67, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2041] = { + .class_hid = BNXT_ULP_CLASS_HID_4867f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2042] = { + .class_hid = BNXT_ULP_CLASS_HID_48c3b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2043] = { + .class_hid = BNXT_ULP_CLASS_HID_4cd17, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2044] = { + .class_hid = BNXT_ULP_CLASS_HID_4d3d3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2045] = { + .class_hid = BNXT_ULP_CLASS_HID_4a983, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2046] = { + .class_hid = BNXT_ULP_CLASS_HID_4b04f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2047] = { + .class_hid = BNXT_ULP_CLASS_HID_4946f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2048] = { + .class_hid = BNXT_ULP_CLASS_HID_49a2b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2049] = { + .class_hid = BNXT_ULP_CLASS_HID_1a14b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2050] = { + .class_hid = BNXT_ULP_CLASS_HID_1a777, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2051] = { + .class_hid = BNXT_ULP_CLASS_HID_18b17, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2052] = { + .class_hid = BNXT_ULP_CLASS_HID_191d3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2053] = { + .class_hid = BNXT_ULP_CLASS_HID_1c4df, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2054] = { + .class_hid = BNXT_ULP_CLASS_HID_1ca9b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2055] = { + .class_hid = BNXT_ULP_CLASS_HID_1aebb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2056] = { + .class_hid = BNXT_ULP_CLASS_HID_1b567, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2057] = { + .class_hid = BNXT_ULP_CLASS_HID_59c7f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2058] = { + .class_hid = BNXT_ULP_CLASS_HID_5a23b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2059] = { + .class_hid = BNXT_ULP_CLASS_HID_586db, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2060] = { + .class_hid = BNXT_ULP_CLASS_HID_58c87, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2061] = { + .class_hid = BNXT_ULP_CLASS_HID_5bf83, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2062] = { + .class_hid = BNXT_ULP_CLASS_HID_5c64f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2063] = { + .class_hid = BNXT_ULP_CLASS_HID_5aa6f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2064] = { + .class_hid = BNXT_ULP_CLASS_HID_5b02b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2065] = { + .class_hid = BNXT_ULP_CLASS_HID_d0cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2066] = { + .class_hid = BNXT_ULP_CLASS_HID_d6f7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2067] = { + .class_hid = BNXT_ULP_CLASS_HID_d7e3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2068] = { + .class_hid = BNXT_ULP_CLASS_HID_c153, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2069] = { + .class_hid = BNXT_ULP_CLASS_HID_f45f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2070] = { + .class_hid = BNXT_ULP_CLASS_HID_fa1b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2071] = { + .class_hid = BNXT_ULP_CLASS_HID_de3b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2072] = { + .class_hid = BNXT_ULP_CLASS_HID_e4e7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2073] = { + .class_hid = BNXT_ULP_CLASS_HID_4cbff, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2074] = { + .class_hid = BNXT_ULP_CLASS_HID_4d1bb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2075] = { + .class_hid = BNXT_ULP_CLASS_HID_4d297, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2076] = { + .class_hid = BNXT_ULP_CLASS_HID_4d953, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2077] = { + .class_hid = BNXT_ULP_CLASS_HID_4ef03, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2078] = { + .class_hid = BNXT_ULP_CLASS_HID_4f5cf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2079] = { + .class_hid = BNXT_ULP_CLASS_HID_4d9ef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2080] = { + .class_hid = BNXT_ULP_CLASS_HID_4dfab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2081] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6cb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2082] = { + .class_hid = BNXT_ULP_CLASS_HID_1ecf7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2083] = { + .class_hid = BNXT_ULP_CLASS_HID_1d097, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2084] = { + .class_hid = BNXT_ULP_CLASS_HID_1d753, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2085] = { + .class_hid = BNXT_ULP_CLASS_HID_1ca5f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2086] = { + .class_hid = BNXT_ULP_CLASS_HID_1d01b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2087] = { + .class_hid = BNXT_ULP_CLASS_HID_1f43b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2088] = { + .class_hid = BNXT_ULP_CLASS_HID_1fae7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2089] = { + .class_hid = BNXT_ULP_CLASS_HID_5e1ff, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2090] = { + .class_hid = BNXT_ULP_CLASS_HID_5e7bb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2091] = { + .class_hid = BNXT_ULP_CLASS_HID_5cc5b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2092] = { + .class_hid = BNXT_ULP_CLASS_HID_5d207, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2093] = { + .class_hid = BNXT_ULP_CLASS_HID_5c503, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2094] = { + .class_hid = BNXT_ULP_CLASS_HID_5cbcf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2095] = { + .class_hid = BNXT_ULP_CLASS_HID_5efef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2096] = { + .class_hid = BNXT_ULP_CLASS_HID_5f5ab, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2097] = { + .class_hid = BNXT_ULP_CLASS_HID_ad8b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2098] = { + .class_hid = BNXT_ULP_CLASS_HID_b3b7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2099] = { + .class_hid = BNXT_ULP_CLASS_HID_f4a3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2100] = { + .class_hid = BNXT_ULP_CLASS_HID_fb6f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2101] = { + .class_hid = BNXT_ULP_CLASS_HID_b11f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2102] = { + .class_hid = BNXT_ULP_CLASS_HID_b7db, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2103] = { + .class_hid = BNXT_ULP_CLASS_HID_bbfb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2104] = { + .class_hid = BNXT_ULP_CLASS_HID_a1a7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2105] = { + .class_hid = BNXT_ULP_CLASS_HID_4a8bf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2106] = { + .class_hid = BNXT_ULP_CLASS_HID_4af7b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2107] = { + .class_hid = BNXT_ULP_CLASS_HID_4f057, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2108] = { + .class_hid = BNXT_ULP_CLASS_HID_4f613, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2109] = { + .class_hid = BNXT_ULP_CLASS_HID_4acc3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2110] = { + .class_hid = BNXT_ULP_CLASS_HID_4b28f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2111] = { + .class_hid = BNXT_ULP_CLASS_HID_4b6af, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2112] = { + .class_hid = BNXT_ULP_CLASS_HID_4bd6b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2113] = { + .class_hid = BNXT_ULP_CLASS_HID_1a38b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2114] = { + .class_hid = BNXT_ULP_CLASS_HID_1a9b7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2115] = { + .class_hid = BNXT_ULP_CLASS_HID_1ae57, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2116] = { + .class_hid = BNXT_ULP_CLASS_HID_1b413, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2117] = { + .class_hid = BNXT_ULP_CLASS_HID_1e71f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2118] = { + .class_hid = BNXT_ULP_CLASS_HID_1eddb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2119] = { + .class_hid = BNXT_ULP_CLASS_HID_1b1fb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2120] = { + .class_hid = BNXT_ULP_CLASS_HID_1b7a7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2121] = { + .class_hid = BNXT_ULP_CLASS_HID_5bebf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2122] = { + .class_hid = BNXT_ULP_CLASS_HID_5a57b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2123] = { + .class_hid = BNXT_ULP_CLASS_HID_5a91b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2124] = { + .class_hid = BNXT_ULP_CLASS_HID_5afc7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2125] = { + .class_hid = BNXT_ULP_CLASS_HID_5e2c3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2126] = { + .class_hid = BNXT_ULP_CLASS_HID_5e88f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2127] = { + .class_hid = BNXT_ULP_CLASS_HID_5acaf, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2128] = { + .class_hid = BNXT_ULP_CLASS_HID_5b36b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2129] = { + .class_hid = BNXT_ULP_CLASS_HID_f30b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2130] = { + .class_hid = BNXT_ULP_CLASS_HID_f937, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2131] = { + .class_hid = BNXT_ULP_CLASS_HID_fa23, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2132] = { + .class_hid = BNXT_ULP_CLASS_HID_e393, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2133] = { + .class_hid = BNXT_ULP_CLASS_HID_f69f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2134] = { + .class_hid = BNXT_ULP_CLASS_HID_fd5b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2135] = { + .class_hid = BNXT_ULP_CLASS_HID_e17b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2136] = { + .class_hid = BNXT_ULP_CLASS_HID_e727, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2137] = { + .class_hid = BNXT_ULP_CLASS_HID_4ee3f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2138] = { + .class_hid = BNXT_ULP_CLASS_HID_4f4fb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2139] = { + .class_hid = BNXT_ULP_CLASS_HID_4f5d7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2140] = { + .class_hid = BNXT_ULP_CLASS_HID_4fb93, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2141] = { + .class_hid = BNXT_ULP_CLASS_HID_4f243, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2142] = { + .class_hid = BNXT_ULP_CLASS_HID_4f80f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2143] = { + .class_hid = BNXT_ULP_CLASS_HID_4fc2f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2144] = { + .class_hid = BNXT_ULP_CLASS_HID_4e2eb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2145] = { + .class_hid = BNXT_ULP_CLASS_HID_1e90b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2146] = { + .class_hid = BNXT_ULP_CLASS_HID_1ef37, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2147] = { + .class_hid = BNXT_ULP_CLASS_HID_1f3d7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2148] = { + .class_hid = BNXT_ULP_CLASS_HID_1f993, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2149] = { + .class_hid = BNXT_ULP_CLASS_HID_1ec9f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2150] = { + .class_hid = BNXT_ULP_CLASS_HID_1f35b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2151] = { + .class_hid = BNXT_ULP_CLASS_HID_1f77b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2152] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd27, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2153] = { + .class_hid = BNXT_ULP_CLASS_HID_5e43f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2154] = { + .class_hid = BNXT_ULP_CLASS_HID_5eafb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2155] = { + .class_hid = BNXT_ULP_CLASS_HID_5ee9b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2156] = { + .class_hid = BNXT_ULP_CLASS_HID_5f547, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2157] = { + .class_hid = BNXT_ULP_CLASS_HID_5e843, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2158] = { + .class_hid = BNXT_ULP_CLASS_HID_5ee0f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2159] = { + .class_hid = BNXT_ULP_CLASS_HID_5f22f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2160] = { + .class_hid = BNXT_ULP_CLASS_HID_5f8eb, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2161] = { + .class_hid = BNXT_ULP_CLASS_HID_2579, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2162] = { + .class_hid = BNXT_ULP_CLASS_HID_2bb5, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2163] = { + .class_hid = BNXT_ULP_CLASS_HID_4591, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2164] = { + .class_hid = BNXT_ULP_CLASS_HID_4bad, + .class_tid = 1, + .hdr_sig_id = 0, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2165] = { + .class_hid = BNXT_ULP_CLASS_HID_2561, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2166] = { + .class_hid = BNXT_ULP_CLASS_HID_2bad, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2167] = { + .class_hid = BNXT_ULP_CLASS_HID_5bdd, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2168] = { + .class_hid = BNXT_ULP_CLASS_HID_054d, + .class_tid = 1, + .hdr_sig_id = 1, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2169] = { + .class_hid = BNXT_ULP_CLASS_HID_257b, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2170] = { + .class_hid = BNXT_ULP_CLASS_HID_2bb7, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2171] = { + .class_hid = BNXT_ULP_CLASS_HID_0fd7, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2172] = { + .class_hid = BNXT_ULP_CLASS_HID_1613, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2173] = { + .class_hid = BNXT_ULP_CLASS_HID_48ef, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2174] = { + .class_hid = BNXT_ULP_CLASS_HID_4f2b, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2175] = { + .class_hid = BNXT_ULP_CLASS_HID_334b, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2176] = { + .class_hid = BNXT_ULP_CLASS_HID_3987, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2177] = { + .class_hid = BNXT_ULP_CLASS_HID_122b, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2178] = { + .class_hid = BNXT_ULP_CLASS_HID_1867, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2179] = { + .class_hid = BNXT_ULP_CLASS_HID_5973, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2180] = { + .class_hid = BNXT_ULP_CLASS_HID_02c3, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2181] = { + .class_hid = BNXT_ULP_CLASS_HID_35df, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2182] = { + .class_hid = BNXT_ULP_CLASS_HID_3c1b, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2183] = { + .class_hid = BNXT_ULP_CLASS_HID_203b, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2184] = { + .class_hid = BNXT_ULP_CLASS_HID_2677, + .class_tid = 1, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2185] = { + .class_hid = BNXT_ULP_CLASS_HID_2563, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2186] = { + .class_hid = BNXT_ULP_CLASS_HID_2baf, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2187] = { + .class_hid = BNXT_ULP_CLASS_HID_0fcf, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2188] = { + .class_hid = BNXT_ULP_CLASS_HID_160b, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2189] = { + .class_hid = BNXT_ULP_CLASS_HID_48f7, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2190] = { + .class_hid = BNXT_ULP_CLASS_HID_4f33, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2191] = { + .class_hid = BNXT_ULP_CLASS_HID_3353, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2192] = { + .class_hid = BNXT_ULP_CLASS_HID_399f, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2193] = { + .class_hid = BNXT_ULP_CLASS_HID_42097, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2194] = { + .class_hid = BNXT_ULP_CLASS_HID_426d3, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2195] = { + .class_hid = BNXT_ULP_CLASS_HID_40af3, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2196] = { + .class_hid = BNXT_ULP_CLASS_HID_4113f, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2197] = { + .class_hid = BNXT_ULP_CLASS_HID_4443b, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2198] = { + .class_hid = BNXT_ULP_CLASS_HID_44a67, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2199] = { + .class_hid = BNXT_ULP_CLASS_HID_42e87, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2200] = { + .class_hid = BNXT_ULP_CLASS_HID_434c3, + .class_tid = 1, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2201] = { + .class_hid = BNXT_ULP_CLASS_HID_2559, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2202] = { + .class_hid = BNXT_ULP_CLASS_HID_2b95, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2203] = { + .class_hid = BNXT_ULP_CLASS_HID_45b1, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2204] = { + .class_hid = BNXT_ULP_CLASS_HID_4b8d, + .class_tid = 1, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2205] = { + .class_hid = BNXT_ULP_CLASS_HID_2541, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2206] = { + .class_hid = BNXT_ULP_CLASS_HID_2b8d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2207] = { + .class_hid = BNXT_ULP_CLASS_HID_5bfd, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2208] = { + .class_hid = BNXT_ULP_CLASS_HID_056d, + .class_tid = 1, + .hdr_sig_id = 5, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2209] = { + .class_hid = BNXT_ULP_CLASS_HID_2539, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2210] = { + .class_hid = BNXT_ULP_CLASS_HID_2bf5, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2211] = { + .class_hid = BNXT_ULP_CLASS_HID_45d1, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2212] = { + .class_hid = BNXT_ULP_CLASS_HID_4bed, + .class_tid = 1, + .hdr_sig_id = 6, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2213] = { + .class_hid = BNXT_ULP_CLASS_HID_2521, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2214] = { + .class_hid = BNXT_ULP_CLASS_HID_2bed, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2215] = { + .class_hid = BNXT_ULP_CLASS_HID_5b9d, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2216] = { + .class_hid = BNXT_ULP_CLASS_HID_050d, + .class_tid = 1, + .hdr_sig_id = 7, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2217] = { + .class_hid = BNXT_ULP_CLASS_HID_255b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2218] = { + .class_hid = BNXT_ULP_CLASS_HID_2b97, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2219] = { + .class_hid = BNXT_ULP_CLASS_HID_0ff7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2220] = { + .class_hid = BNXT_ULP_CLASS_HID_1633, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2221] = { + .class_hid = BNXT_ULP_CLASS_HID_48cf, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2222] = { + .class_hid = BNXT_ULP_CLASS_HID_4f0b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2223] = { + .class_hid = BNXT_ULP_CLASS_HID_336b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2224] = { + .class_hid = BNXT_ULP_CLASS_HID_39a7, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2225] = { + .class_hid = BNXT_ULP_CLASS_HID_120b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2226] = { + .class_hid = BNXT_ULP_CLASS_HID_1847, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2227] = { + .class_hid = BNXT_ULP_CLASS_HID_5953, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2228] = { + .class_hid = BNXT_ULP_CLASS_HID_02e3, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2229] = { + .class_hid = BNXT_ULP_CLASS_HID_35ff, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2230] = { + .class_hid = BNXT_ULP_CLASS_HID_3c3b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2231] = { + .class_hid = BNXT_ULP_CLASS_HID_201b, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2232] = { + .class_hid = BNXT_ULP_CLASS_HID_2657, + .class_tid = 1, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2233] = { + .class_hid = BNXT_ULP_CLASS_HID_2543, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2234] = { + .class_hid = BNXT_ULP_CLASS_HID_2b8f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2235] = { + .class_hid = BNXT_ULP_CLASS_HID_0fef, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2236] = { + .class_hid = BNXT_ULP_CLASS_HID_162b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2237] = { + .class_hid = BNXT_ULP_CLASS_HID_48d7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2238] = { + .class_hid = BNXT_ULP_CLASS_HID_4f13, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2239] = { + .class_hid = BNXT_ULP_CLASS_HID_3373, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2240] = { + .class_hid = BNXT_ULP_CLASS_HID_39bf, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2241] = { + .class_hid = BNXT_ULP_CLASS_HID_420b7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2242] = { + .class_hid = BNXT_ULP_CLASS_HID_426f3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2243] = { + .class_hid = BNXT_ULP_CLASS_HID_40ad3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2244] = { + .class_hid = BNXT_ULP_CLASS_HID_4111f, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2245] = { + .class_hid = BNXT_ULP_CLASS_HID_4441b, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2246] = { + .class_hid = BNXT_ULP_CLASS_HID_44a47, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2247] = { + .class_hid = BNXT_ULP_CLASS_HID_42ea7, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2248] = { + .class_hid = BNXT_ULP_CLASS_HID_434e3, + .class_tid = 1, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2249] = { + .class_hid = BNXT_ULP_CLASS_HID_253b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2250] = { + .class_hid = BNXT_ULP_CLASS_HID_2bf7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2251] = { + .class_hid = BNXT_ULP_CLASS_HID_0f97, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2252] = { + .class_hid = BNXT_ULP_CLASS_HID_1653, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2253] = { + .class_hid = BNXT_ULP_CLASS_HID_48af, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2254] = { + .class_hid = BNXT_ULP_CLASS_HID_4f6b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2255] = { + .class_hid = BNXT_ULP_CLASS_HID_330b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2256] = { + .class_hid = BNXT_ULP_CLASS_HID_39c7, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2257] = { + .class_hid = BNXT_ULP_CLASS_HID_126b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2258] = { + .class_hid = BNXT_ULP_CLASS_HID_1827, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2259] = { + .class_hid = BNXT_ULP_CLASS_HID_5933, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2260] = { + .class_hid = BNXT_ULP_CLASS_HID_0283, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2261] = { + .class_hid = BNXT_ULP_CLASS_HID_359f, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2262] = { + .class_hid = BNXT_ULP_CLASS_HID_3c5b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2263] = { + .class_hid = BNXT_ULP_CLASS_HID_207b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2264] = { + .class_hid = BNXT_ULP_CLASS_HID_2637, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2265] = { + .class_hid = BNXT_ULP_CLASS_HID_2523, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2266] = { + .class_hid = BNXT_ULP_CLASS_HID_2bef, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2267] = { + .class_hid = BNXT_ULP_CLASS_HID_0f8f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2268] = { + .class_hid = BNXT_ULP_CLASS_HID_164b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2269] = { + .class_hid = BNXT_ULP_CLASS_HID_48b7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2270] = { + .class_hid = BNXT_ULP_CLASS_HID_4f73, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2271] = { + .class_hid = BNXT_ULP_CLASS_HID_3313, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2272] = { + .class_hid = BNXT_ULP_CLASS_HID_39df, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2273] = { + .class_hid = BNXT_ULP_CLASS_HID_420d7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2274] = { + .class_hid = BNXT_ULP_CLASS_HID_42693, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2275] = { + .class_hid = BNXT_ULP_CLASS_HID_40ab3, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2276] = { + .class_hid = BNXT_ULP_CLASS_HID_4117f, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2277] = { + .class_hid = BNXT_ULP_CLASS_HID_4447b, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2278] = { + .class_hid = BNXT_ULP_CLASS_HID_44a27, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2279] = { + .class_hid = BNXT_ULP_CLASS_HID_42ec7, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2280] = { + .class_hid = BNXT_ULP_CLASS_HID_43483, + .class_tid = 1, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2281] = { + .class_hid = BNXT_ULP_CLASS_HID_4156d, + .class_tid = 1, + .hdr_sig_id = 12, + .flow_sig_id = 16384, + .flow_pattern_id = 3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2282] = { + .class_hid = BNXT_ULP_CLASS_HID_41b29, + .class_tid = 1, + .hdr_sig_id = 12, + .flow_sig_id = 16384, + .flow_pattern_id = 3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_12_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2283] = { + .class_hid = BNXT_ULP_CLASS_HID_52b6d, + .class_tid = 1, + .hdr_sig_id = 12, + .flow_sig_id = 81920, + .flow_pattern_id = 3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2284] = { + .class_hid = BNXT_ULP_CLASS_HID_53129, + .class_tid = 1, + .hdr_sig_id = 12, + .flow_sig_id = 81920, + .flow_pattern_id = 3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_12_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2285] = { + .class_hid = BNXT_ULP_CLASS_HID_478a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2286] = { + .class_hid = BNXT_ULP_CLASS_HID_03a6, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2287] = { + .class_hid = BNXT_ULP_CLASS_HID_4dce, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2288] = { + .class_hid = BNXT_ULP_CLASS_HID_09ea, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2289] = { + .class_hid = BNXT_ULP_CLASS_HID_08fe, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2290] = { + .class_hid = BNXT_ULP_CLASS_HID_23ce, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2291] = { + .class_hid = BNXT_ULP_CLASS_HID_0e02, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2292] = { + .class_hid = BNXT_ULP_CLASS_HID_2912, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2293] = { + .class_hid = BNXT_ULP_CLASS_HID_3e2a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2294] = { + .class_hid = BNXT_ULP_CLASS_HID_593a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2295] = { + .class_hid = BNXT_ULP_CLASS_HID_246e, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2296] = { + .class_hid = BNXT_ULP_CLASS_HID_5f7e, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2297] = { + .class_hid = BNXT_ULP_CLASS_HID_5e52, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2298] = { + .class_hid = BNXT_ULP_CLASS_HID_1a6e, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2299] = { + .class_hid = BNXT_ULP_CLASS_HID_4796, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2300] = { + .class_hid = BNXT_ULP_CLASS_HID_03b2, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2301] = { + .class_hid = BNXT_ULP_CLASS_HID_4163a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2302] = { + .class_hid = BNXT_ULP_CLASS_HID_4310a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16388, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2303] = { + .class_hid = BNXT_ULP_CLASS_HID_41c7e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2304] = { + .class_hid = BNXT_ULP_CLASS_HID_4374e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16388, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2305] = { + .class_hid = BNXT_ULP_CLASS_HID_42f8e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2306] = { + .class_hid = BNXT_ULP_CLASS_HID_4469e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16388, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2307] = { + .class_hid = BNXT_ULP_CLASS_HID_455c2, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2308] = { + .class_hid = BNXT_ULP_CLASS_HID_411ee, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16388, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2309] = { + .class_hid = BNXT_ULP_CLASS_HID_44b76, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2310] = { + .class_hid = BNXT_ULP_CLASS_HID_40692, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24580, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2311] = { + .class_hid = BNXT_ULP_CLASS_HID_415c6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2312] = { + .class_hid = BNXT_ULP_CLASS_HID_40cd6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24580, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2313] = { + .class_hid = BNXT_ULP_CLASS_HID_42516, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2314] = { + .class_hid = BNXT_ULP_CLASS_HID_45ce6, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24580, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2315] = { + .class_hid = BNXT_ULP_CLASS_HID_42b2a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2316] = { + .class_hid = BNXT_ULP_CLASS_HID_4423a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24580, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2317] = { + .class_hid = BNXT_ULP_CLASS_HID_229d8, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2318] = { + .class_hid = BNXT_ULP_CLASS_HID_240c8, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2319] = { + .class_hid = BNXT_ULP_CLASS_HID_22f14, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2320] = { + .class_hid = BNXT_ULP_CLASS_HID_24604, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2321] = { + .class_hid = BNXT_ULP_CLASS_HID_23374, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2322] = { + .class_hid = BNXT_ULP_CLASS_HID_22a64, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2323] = { + .class_hid = BNXT_ULP_CLASS_HID_238b0, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2324] = { + .class_hid = BNXT_ULP_CLASS_HID_253a0, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2325] = { + .class_hid = BNXT_ULP_CLASS_HID_24dac, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2326] = { + .class_hid = BNXT_ULP_CLASS_HID_20990, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2327] = { + .class_hid = BNXT_ULP_CLASS_HID_214dc, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2328] = { + .class_hid = BNXT_ULP_CLASS_HID_20fcc, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2329] = { + .class_hid = BNXT_ULP_CLASS_HID_257c8, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2330] = { + .class_hid = BNXT_ULP_CLASS_HID_2132c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2331] = { + .class_hid = BNXT_ULP_CLASS_HID_25d04, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2332] = { + .class_hid = BNXT_ULP_CLASS_HID_21968, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2333] = { + .class_hid = BNXT_ULP_CLASS_HID_234e8, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2334] = { + .class_hid = BNXT_ULP_CLASS_HID_22f98, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2335] = { + .class_hid = BNXT_ULP_CLASS_HID_23a24, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2336] = { + .class_hid = BNXT_ULP_CLASS_HID_255d4, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2337] = { + .class_hid = BNXT_ULP_CLASS_HID_21e04, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2338] = { + .class_hid = BNXT_ULP_CLASS_HID_23934, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2339] = { + .class_hid = BNXT_ULP_CLASS_HID_20440, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2340] = { + .class_hid = BNXT_ULP_CLASS_HID_23f70, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2341] = { + .class_hid = BNXT_ULP_CLASS_HID_2597c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2342] = { + .class_hid = BNXT_ULP_CLASS_HID_214a0, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2343] = { + .class_hid = BNXT_ULP_CLASS_HID_25eb8, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2344] = { + .class_hid = BNXT_ULP_CLASS_HID_21a9c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2345] = { + .class_hid = BNXT_ULP_CLASS_HID_22298, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2346] = { + .class_hid = BNXT_ULP_CLASS_HID_25d88, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2347] = { + .class_hid = BNXT_ULP_CLASS_HID_228d4, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2348] = { + .class_hid = BNXT_ULP_CLASS_HID_243c4, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2349] = { + .class_hid = BNXT_ULP_CLASS_HID_6220c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2350] = { + .class_hid = BNXT_ULP_CLASS_HID_65d3c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2351] = { + .class_hid = BNXT_ULP_CLASS_HID_62848, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2352] = { + .class_hid = BNXT_ULP_CLASS_HID_64378, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2353] = { + .class_hid = BNXT_ULP_CLASS_HID_60fa8, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2354] = { + .class_hid = BNXT_ULP_CLASS_HID_62758, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2355] = { + .class_hid = BNXT_ULP_CLASS_HID_635e4, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2356] = { + .class_hid = BNXT_ULP_CLASS_HID_62c94, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2357] = { + .class_hid = BNXT_ULP_CLASS_HID_646e0, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2358] = { + .class_hid = BNXT_ULP_CLASS_HID_602c4, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2359] = { + .class_hid = BNXT_ULP_CLASS_HID_61110, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2360] = { + .class_hid = BNXT_ULP_CLASS_HID_60800, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2361] = { + .class_hid = BNXT_ULP_CLASS_HID_6503c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2362] = { + .class_hid = BNXT_ULP_CLASS_HID_64b2c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2363] = { + .class_hid = BNXT_ULP_CLASS_HID_65678, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2364] = { + .class_hid = BNXT_ULP_CLASS_HID_6125c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2365] = { + .class_hid = BNXT_ULP_CLASS_HID_631dc, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2366] = { + .class_hid = BNXT_ULP_CLASS_HID_628cc, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2367] = { + .class_hid = BNXT_ULP_CLASS_HID_63718, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2368] = { + .class_hid = BNXT_ULP_CLASS_HID_62e08, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2369] = { + .class_hid = BNXT_ULP_CLASS_HID_61b78, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2370] = { + .class_hid = BNXT_ULP_CLASS_HID_63268, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2371] = { + .class_hid = BNXT_ULP_CLASS_HID_600b4, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2372] = { + .class_hid = BNXT_ULP_CLASS_HID_63ba4, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2373] = { + .class_hid = BNXT_ULP_CLASS_HID_655b0, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2374] = { + .class_hid = BNXT_ULP_CLASS_HID_61194, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2375] = { + .class_hid = BNXT_ULP_CLASS_HID_65bec, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2376] = { + .class_hid = BNXT_ULP_CLASS_HID_617d0, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2377] = { + .class_hid = BNXT_ULP_CLASS_HID_63fcc, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2378] = { + .class_hid = BNXT_ULP_CLASS_HID_656fc, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2379] = { + .class_hid = BNXT_ULP_CLASS_HID_62508, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2380] = { + .class_hid = BNXT_ULP_CLASS_HID_65c38, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2381] = { + .class_hid = BNXT_ULP_CLASS_HID_86e0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2382] = { + .class_hid = BNXT_ULP_CLASS_HID_a1f0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2383] = { + .class_hid = BNXT_ULP_CLASS_HID_8c2c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2384] = { + .class_hid = BNXT_ULP_CLASS_HID_a73c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2385] = { + .class_hid = BNXT_ULP_CLASS_HID_904c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2386] = { + .class_hid = BNXT_ULP_CLASS_HID_8b5c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2387] = { + .class_hid = BNXT_ULP_CLASS_HID_9988, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2388] = { + .class_hid = BNXT_ULP_CLASS_HID_b098, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2389] = { + .class_hid = BNXT_ULP_CLASS_HID_aa94, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2390] = { + .class_hid = BNXT_ULP_CLASS_HID_c264, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2391] = { + .class_hid = BNXT_ULP_CLASS_HID_d0d0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2392] = { + .class_hid = BNXT_ULP_CLASS_HID_cba0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2393] = { + .class_hid = BNXT_ULP_CLASS_HID_b4f0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2394] = { + .class_hid = BNXT_ULP_CLASS_HID_afc0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2395] = { + .class_hid = BNXT_ULP_CLASS_HID_ba3c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2396] = { + .class_hid = BNXT_ULP_CLASS_HID_d50c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2397] = { + .class_hid = BNXT_ULP_CLASS_HID_48334, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2398] = { + .class_hid = BNXT_ULP_CLASS_HID_4ba04, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2399] = { + .class_hid = BNXT_ULP_CLASS_HID_48970, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2400] = { + .class_hid = BNXT_ULP_CLASS_HID_4a040, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2401] = { + .class_hid = BNXT_ULP_CLASS_HID_4c84c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2402] = { + .class_hid = BNXT_ULP_CLASS_HID_48460, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2403] = { + .class_hid = BNXT_ULP_CLASS_HID_492dc, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2404] = { + .class_hid = BNXT_ULP_CLASS_HID_48dac, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2405] = { + .class_hid = BNXT_ULP_CLASS_HID_4a7d8, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2406] = { + .class_hid = BNXT_ULP_CLASS_HID_4dea8, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2407] = { + .class_hid = BNXT_ULP_CLASS_HID_4ade4, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2408] = { + .class_hid = BNXT_ULP_CLASS_HID_4c4f4, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2409] = { + .class_hid = BNXT_ULP_CLASS_HID_4b104, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2410] = { + .class_hid = BNXT_ULP_CLASS_HID_4a814, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2411] = { + .class_hid = BNXT_ULP_CLASS_HID_4b740, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2412] = { + .class_hid = BNXT_ULP_CLASS_HID_4ae50, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2413] = { + .class_hid = BNXT_ULP_CLASS_HID_1bce0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2414] = { + .class_hid = BNXT_ULP_CLASS_HID_1d7f0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2415] = { + .class_hid = BNXT_ULP_CLASS_HID_1a22c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2416] = { + .class_hid = BNXT_ULP_CLASS_HID_1dd3c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2417] = { + .class_hid = BNXT_ULP_CLASS_HID_1864c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2418] = { + .class_hid = BNXT_ULP_CLASS_HID_1a15c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2419] = { + .class_hid = BNXT_ULP_CLASS_HID_18f88, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2420] = { + .class_hid = BNXT_ULP_CLASS_HID_1a698, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2421] = { + .class_hid = BNXT_ULP_CLASS_HID_1c094, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2422] = { + .class_hid = BNXT_ULP_CLASS_HID_19ca8, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2423] = { + .class_hid = BNXT_ULP_CLASS_HID_1c6d0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2424] = { + .class_hid = BNXT_ULP_CLASS_HID_182f4, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2425] = { + .class_hid = BNXT_ULP_CLASS_HID_1aaf0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2426] = { + .class_hid = BNXT_ULP_CLASS_HID_1c5c0, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2427] = { + .class_hid = BNXT_ULP_CLASS_HID_1d03c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2428] = { + .class_hid = BNXT_ULP_CLASS_HID_1cb0c, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2429] = { + .class_hid = BNXT_ULP_CLASS_HID_5b934, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2430] = { + .class_hid = BNXT_ULP_CLASS_HID_5d004, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2431] = { + .class_hid = BNXT_ULP_CLASS_HID_5bf70, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2432] = { + .class_hid = BNXT_ULP_CLASS_HID_5d640, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2433] = { + .class_hid = BNXT_ULP_CLASS_HID_58290, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2434] = { + .class_hid = BNXT_ULP_CLASS_HID_5ba60, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2435] = { + .class_hid = BNXT_ULP_CLASS_HID_588dc, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2436] = { + .class_hid = BNXT_ULP_CLASS_HID_5a3ac, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2437] = { + .class_hid = BNXT_ULP_CLASS_HID_5ddd8, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2438] = { + .class_hid = BNXT_ULP_CLASS_HID_599fc, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2439] = { + .class_hid = BNXT_ULP_CLASS_HID_5c3e4, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2440] = { + .class_hid = BNXT_ULP_CLASS_HID_59f38, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2441] = { + .class_hid = BNXT_ULP_CLASS_HID_5a704, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2442] = { + .class_hid = BNXT_ULP_CLASS_HID_5de14, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2443] = { + .class_hid = BNXT_ULP_CLASS_HID_5ad40, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2444] = { + .class_hid = BNXT_ULP_CLASS_HID_5c450, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2445] = { + .class_hid = BNXT_ULP_CLASS_HID_47aa, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2446] = { + .class_hid = BNXT_ULP_CLASS_HID_0386, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2447] = { + .class_hid = BNXT_ULP_CLASS_HID_4dee, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2448] = { + .class_hid = BNXT_ULP_CLASS_HID_09ca, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2449] = { + .class_hid = BNXT_ULP_CLASS_HID_08de, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2450] = { + .class_hid = BNXT_ULP_CLASS_HID_23ee, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2451] = { + .class_hid = BNXT_ULP_CLASS_HID_0e22, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2452] = { + .class_hid = BNXT_ULP_CLASS_HID_2932, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2453] = { + .class_hid = BNXT_ULP_CLASS_HID_3e0a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2454] = { + .class_hid = BNXT_ULP_CLASS_HID_591a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2455] = { + .class_hid = BNXT_ULP_CLASS_HID_244e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2456] = { + .class_hid = BNXT_ULP_CLASS_HID_5f5e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2457] = { + .class_hid = BNXT_ULP_CLASS_HID_5e72, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2458] = { + .class_hid = BNXT_ULP_CLASS_HID_1a4e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2459] = { + .class_hid = BNXT_ULP_CLASS_HID_47b6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2460] = { + .class_hid = BNXT_ULP_CLASS_HID_0392, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2461] = { + .class_hid = BNXT_ULP_CLASS_HID_5dc2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2462] = { + .class_hid = BNXT_ULP_CLASS_HID_191e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12292, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2463] = { + .class_hid = BNXT_ULP_CLASS_HID_4306, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2464] = { + .class_hid = BNXT_ULP_CLASS_HID_1f62, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12292, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2465] = { + .class_hid = BNXT_ULP_CLASS_HID_1e76, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2466] = { + .class_hid = BNXT_ULP_CLASS_HID_3906, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12292, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2467] = { + .class_hid = BNXT_ULP_CLASS_HID_07ba, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2468] = { + .class_hid = BNXT_ULP_CLASS_HID_3f4a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12292, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2469] = { + .class_hid = BNXT_ULP_CLASS_HID_37a2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2470] = { + .class_hid = BNXT_ULP_CLASS_HID_2eb2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14340, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2471] = { + .class_hid = BNXT_ULP_CLASS_HID_3de6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2472] = { + .class_hid = BNXT_ULP_CLASS_HID_54f6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14340, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2473] = { + .class_hid = BNXT_ULP_CLASS_HID_578a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2474] = { + .class_hid = BNXT_ULP_CLASS_HID_13e6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14340, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2475] = { + .class_hid = BNXT_ULP_CLASS_HID_5dce, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2476] = { + .class_hid = BNXT_ULP_CLASS_HID_192a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14340, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2477] = { + .class_hid = BNXT_ULP_CLASS_HID_440f6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2478] = { + .class_hid = BNXT_ULP_CLASS_HID_41cd2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20484, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2479] = { + .class_hid = BNXT_ULP_CLASS_HID_4463a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2480] = { + .class_hid = BNXT_ULP_CLASS_HID_40216, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20484, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2481] = { + .class_hid = BNXT_ULP_CLASS_HID_4052a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2482] = { + .class_hid = BNXT_ULP_CLASS_HID_43c3a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20484, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2483] = { + .class_hid = BNXT_ULP_CLASS_HID_40b6e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2484] = { + .class_hid = BNXT_ULP_CLASS_HID_4227e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20484, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2485] = { + .class_hid = BNXT_ULP_CLASS_HID_43b56, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2486] = { + .class_hid = BNXT_ULP_CLASS_HID_45266, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22532, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2487] = { + .class_hid = BNXT_ULP_CLASS_HID_4209a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2488] = { + .class_hid = BNXT_ULP_CLASS_HID_45baa, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22532, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2489] = { + .class_hid = BNXT_ULP_CLASS_HID_45abe, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2490] = { + .class_hid = BNXT_ULP_CLASS_HID_4169a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22532, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2491] = { + .class_hid = BNXT_ULP_CLASS_HID_44082, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2492] = { + .class_hid = BNXT_ULP_CLASS_HID_41cde, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22532, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2493] = { + .class_hid = BNXT_ULP_CLASS_HID_4560e, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2494] = { + .class_hid = BNXT_ULP_CLASS_HID_4126a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2495] = { + .class_hid = BNXT_ULP_CLASS_HID_45c52, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2496] = { + .class_hid = BNXT_ULP_CLASS_HID_41bae, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2497] = { + .class_hid = BNXT_ULP_CLASS_HID_41b42, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2498] = { + .class_hid = BNXT_ULP_CLASS_HID_43252, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2499] = { + .class_hid = BNXT_ULP_CLASS_HID_40086, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2500] = { + .class_hid = BNXT_ULP_CLASS_HID_43b96, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28676, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2501] = { + .class_hid = BNXT_ULP_CLASS_HID_430ee, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2502] = { + .class_hid = BNXT_ULP_CLASS_HID_42bfe, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30724, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2503] = { + .class_hid = BNXT_ULP_CLASS_HID_43632, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2504] = { + .class_hid = BNXT_ULP_CLASS_HID_451c2, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30724, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2505] = { + .class_hid = BNXT_ULP_CLASS_HID_450d6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2506] = { + .class_hid = BNXT_ULP_CLASS_HID_44be6, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30724, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2507] = { + .class_hid = BNXT_ULP_CLASS_HID_4561a, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2508] = { + .class_hid = BNXT_ULP_CLASS_HID_41276, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30724, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2509] = { + .class_hid = BNXT_ULP_CLASS_HID_4161a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2510] = { + .class_hid = BNXT_ULP_CLASS_HID_4312a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16388, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2511] = { + .class_hid = BNXT_ULP_CLASS_HID_41c5e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2512] = { + .class_hid = BNXT_ULP_CLASS_HID_4376e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16388, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2513] = { + .class_hid = BNXT_ULP_CLASS_HID_42fae, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2514] = { + .class_hid = BNXT_ULP_CLASS_HID_446be, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16388, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2515] = { + .class_hid = BNXT_ULP_CLASS_HID_455e2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2516] = { + .class_hid = BNXT_ULP_CLASS_HID_411ce, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16388, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2517] = { + .class_hid = BNXT_ULP_CLASS_HID_44b56, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2518] = { + .class_hid = BNXT_ULP_CLASS_HID_406b2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24580, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2519] = { + .class_hid = BNXT_ULP_CLASS_HID_415e6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2520] = { + .class_hid = BNXT_ULP_CLASS_HID_40cf6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24580, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2521] = { + .class_hid = BNXT_ULP_CLASS_HID_42536, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2522] = { + .class_hid = BNXT_ULP_CLASS_HID_45cc6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24580, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2523] = { + .class_hid = BNXT_ULP_CLASS_HID_42b0a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2524] = { + .class_hid = BNXT_ULP_CLASS_HID_4421a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24580, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2525] = { + .class_hid = BNXT_ULP_CLASS_HID_6221a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2526] = { + .class_hid = BNXT_ULP_CLASS_HID_65d2a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2527] = { + .class_hid = BNXT_ULP_CLASS_HID_6285e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2528] = { + .class_hid = BNXT_ULP_CLASS_HID_6436e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2529] = { + .class_hid = BNXT_ULP_CLASS_HID_61cfa, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2530] = { + .class_hid = BNXT_ULP_CLASS_HID_6378a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2531] = { + .class_hid = BNXT_ULP_CLASS_HID_6023e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2532] = { + .class_hid = BNXT_ULP_CLASS_HID_63dce, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49156, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2533] = { + .class_hid = BNXT_ULP_CLASS_HID_63ba2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2534] = { + .class_hid = BNXT_ULP_CLASS_HID_652b2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57348, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2535] = { + .class_hid = BNXT_ULP_CLASS_HID_621e6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2536] = { + .class_hid = BNXT_ULP_CLASS_HID_658f6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57348, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2537] = { + .class_hid = BNXT_ULP_CLASS_HID_61202, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2538] = { + .class_hid = BNXT_ULP_CLASS_HID_60d12, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57348, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2539] = { + .class_hid = BNXT_ULP_CLASS_HID_61846, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2540] = { + .class_hid = BNXT_ULP_CLASS_HID_63356, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57348, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2541] = { + .class_hid = BNXT_ULP_CLASS_HID_50c1a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2542] = { + .class_hid = BNXT_ULP_CLASS_HID_5272a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81924, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2543] = { + .class_hid = BNXT_ULP_CLASS_HID_5325e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2544] = { + .class_hid = BNXT_ULP_CLASS_HID_52d6e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81924, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2545] = { + .class_hid = BNXT_ULP_CLASS_HID_545ae, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2546] = { + .class_hid = BNXT_ULP_CLASS_HID_5018a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81924, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2547] = { + .class_hid = BNXT_ULP_CLASS_HID_54be2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2548] = { + .class_hid = BNXT_ULP_CLASS_HID_507ce, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81924, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2549] = { + .class_hid = BNXT_ULP_CLASS_HID_505a2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2550] = { + .class_hid = BNXT_ULP_CLASS_HID_53cb2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2551] = { + .class_hid = BNXT_ULP_CLASS_HID_50be6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2552] = { + .class_hid = BNXT_ULP_CLASS_HID_522f6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2553] = { + .class_hid = BNXT_ULP_CLASS_HID_55b36, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2554] = { + .class_hid = BNXT_ULP_CLASS_HID_51712, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2555] = { + .class_hid = BNXT_ULP_CLASS_HID_5410a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2556] = { + .class_hid = BNXT_ULP_CLASS_HID_51d56, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90116, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2557] = { + .class_hid = BNXT_ULP_CLASS_HID_7581a, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 114688, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2558] = { + .class_hid = BNXT_ULP_CLASS_HID_71466, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 114692, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2559] = { + .class_hid = BNXT_ULP_CLASS_HID_75e5e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 114688, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2560] = { + .class_hid = BNXT_ULP_CLASS_HID_71dba, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 114692, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2561] = { + .class_hid = BNXT_ULP_CLASS_HID_732fa, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 114688, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2562] = { + .class_hid = BNXT_ULP_CLASS_HID_72d8a, .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 148, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2017] = { - .class_hid = BNXT_ULP_CLASS_HID_34fe, + [2563] = { + .class_hid = BNXT_ULP_CLASS_HID_7383e, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 114688, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2564] = { + .class_hid = BNXT_ULP_CLASS_HID_753ce, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 114692, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2565] = { + .class_hid = BNXT_ULP_CLASS_HID_751a2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122880, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2566] = { + .class_hid = BNXT_ULP_CLASS_HID_748b2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122884, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2567] = { + .class_hid = BNXT_ULP_CLASS_HID_757e6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122880, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2568] = { + .class_hid = BNXT_ULP_CLASS_HID_713c2, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122884, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2569] = { + .class_hid = BNXT_ULP_CLASS_HID_70802, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122880, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2570] = { + .class_hid = BNXT_ULP_CLASS_HID_72312, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122884, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2571] = { + .class_hid = BNXT_ULP_CLASS_HID_70e46, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122880, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2572] = { + .class_hid = BNXT_ULP_CLASS_HID_72956, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122884, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2573] = { + .class_hid = BNXT_ULP_CLASS_HID_47ca, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2574] = { + .class_hid = BNXT_ULP_CLASS_HID_03e6, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2575] = { + .class_hid = BNXT_ULP_CLASS_HID_4d8e, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2576] = { + .class_hid = BNXT_ULP_CLASS_HID_09aa, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2577] = { + .class_hid = BNXT_ULP_CLASS_HID_08be, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2578] = { + .class_hid = BNXT_ULP_CLASS_HID_238e, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2579] = { + .class_hid = BNXT_ULP_CLASS_HID_0e42, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4096, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2580] = { + .class_hid = BNXT_ULP_CLASS_HID_2952, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4100, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2581] = { + .class_hid = BNXT_ULP_CLASS_HID_3e6a, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2582] = { + .class_hid = BNXT_ULP_CLASS_HID_597a, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2583] = { + .class_hid = BNXT_ULP_CLASS_HID_242e, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2584] = { + .class_hid = BNXT_ULP_CLASS_HID_5f3e, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2585] = { + .class_hid = BNXT_ULP_CLASS_HID_5e12, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2586] = { + .class_hid = BNXT_ULP_CLASS_HID_1a2e, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2587] = { + .class_hid = BNXT_ULP_CLASS_HID_47d6, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6144, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2588] = { + .class_hid = BNXT_ULP_CLASS_HID_03f2, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6148, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2589] = { + .class_hid = BNXT_ULP_CLASS_HID_5da2, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2590] = { + .class_hid = BNXT_ULP_CLASS_HID_197e, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12292, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2591] = { + .class_hid = BNXT_ULP_CLASS_HID_4366, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2592] = { + .class_hid = BNXT_ULP_CLASS_HID_1f02, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12292, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2593] = { + .class_hid = BNXT_ULP_CLASS_HID_1e16, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2594] = { + .class_hid = BNXT_ULP_CLASS_HID_3966, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12292, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2595] = { + .class_hid = BNXT_ULP_CLASS_HID_07da, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2596] = { + .class_hid = BNXT_ULP_CLASS_HID_3f2a, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12292, + .flow_pattern_id = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + }, + [2597] = { + .class_hid = BNXT_ULP_CLASS_HID_37c2, .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 148, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2018] = { - .class_hid = BNXT_ULP_CLASS_HID_3a32, + [2598] = { + .class_hid = BNXT_ULP_CLASS_HID_2ed2, .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 149, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14340, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2019] = { - .class_hid = BNXT_ULP_CLASS_HID_14d2, + [2599] = { + .class_hid = BNXT_ULP_CLASS_HID_3d86, .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 149, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2020] = { - .class_hid = BNXT_ULP_CLASS_HID_4a42, + [2600] = { + .class_hid = BNXT_ULP_CLASS_HID_5496, .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 149, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14340, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2021] = { - .class_hid = BNXT_ULP_CLASS_HID_376e, + [2601] = { + .class_hid = BNXT_ULP_CLASS_HID_57ea, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 149, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2022] = { - .class_hid = BNXT_ULP_CLASS_HID_12d6e, + [2602] = { + .class_hid = BNXT_ULP_CLASS_HID_1386, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 149, + .hdr_sig_id = 6, + .flow_sig_id = 14340, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2023] = { - .class_hid = BNXT_ULP_CLASS_HID_2436e, + [2603] = { + .class_hid = BNXT_ULP_CLASS_HID_5dae, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 150, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2024] = { - .class_hid = BNXT_ULP_CLASS_HID_31dba, + [2604] = { + .class_hid = BNXT_ULP_CLASS_HID_194a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 151, + .hdr_sig_id = 6, + .flow_sig_id = 14340, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2025] = { - .class_hid = BNXT_ULP_CLASS_HID_11ce, + [2605] = { + .class_hid = BNXT_ULP_CLASS_HID_44096, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 152, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2026] = { - .class_hid = BNXT_ULP_CLASS_HID_107ce, + [2606] = { + .class_hid = BNXT_ULP_CLASS_HID_41cb2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 152, + .hdr_sig_id = 6, + .flow_sig_id = 20484, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2027] = { - .class_hid = BNXT_ULP_CLASS_HID_23dce, + [2607] = { + .class_hid = BNXT_ULP_CLASS_HID_4465a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 152, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2028] = { - .class_hid = BNXT_ULP_CLASS_HID_353ce, + [2608] = { + .class_hid = BNXT_ULP_CLASS_HID_40276, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 152, + .hdr_sig_id = 6, + .flow_sig_id = 20484, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2029] = { - .class_hid = BNXT_ULP_CLASS_HID_421a, + [2609] = { + .class_hid = BNXT_ULP_CLASS_HID_4054a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 152, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2030] = { - .class_hid = BNXT_ULP_CLASS_HID_11d56, + [2610] = { + .class_hid = BNXT_ULP_CLASS_HID_43c5a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 152, + .hdr_sig_id = 6, + .flow_sig_id = 20484, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2031] = { - .class_hid = BNXT_ULP_CLASS_HID_23356, + [2611] = { + .class_hid = BNXT_ULP_CLASS_HID_40b0e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 153, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2032] = { - .class_hid = BNXT_ULP_CLASS_HID_32956, + [2612] = { + .class_hid = BNXT_ULP_CLASS_HID_4221e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 154, + .hdr_sig_id = 6, + .flow_sig_id = 20484, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2033] = { - .class_hid = BNXT_ULP_CLASS_HID_0cf6, + [2613] = { + .class_hid = BNXT_ULP_CLASS_HID_43b36, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2034] = { - .class_hid = BNXT_ULP_CLASS_HID_122f6, + [2614] = { + .class_hid = BNXT_ULP_CLASS_HID_45206, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 22532, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2035] = { - .class_hid = BNXT_ULP_CLASS_HID_258f6, + [2615] = { + .class_hid = BNXT_ULP_CLASS_HID_420fa, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2036] = { - .class_hid = BNXT_ULP_CLASS_HID_313c2, + [2616] = { + .class_hid = BNXT_ULP_CLASS_HID_45bca, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 22532, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2037] = { - .class_hid = BNXT_ULP_CLASS_HID_312a, + [2617] = { + .class_hid = BNXT_ULP_CLASS_HID_45ade, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2038] = { - .class_hid = BNXT_ULP_CLASS_HID_1272a, + [2618] = { + .class_hid = BNXT_ULP_CLASS_HID_416fa, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 22532, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2039] = { - .class_hid = BNXT_ULP_CLASS_HID_25d2a, + [2619] = { + .class_hid = BNXT_ULP_CLASS_HID_440e2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2040] = { - .class_hid = BNXT_ULP_CLASS_HID_31466, + [2620] = { + .class_hid = BNXT_ULP_CLASS_HID_41cbe, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 22532, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2041] = { - .class_hid = BNXT_ULP_CLASS_HID_46be, + [2621] = { + .class_hid = BNXT_ULP_CLASS_HID_4566e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2042] = { - .class_hid = BNXT_ULP_CLASS_HID_1018a, + [2622] = { + .class_hid = BNXT_ULP_CLASS_HID_4120a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 28676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2043] = { - .class_hid = BNXT_ULP_CLASS_HID_2378a, + [2623] = { + .class_hid = BNXT_ULP_CLASS_HID_45c32, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2044] = { - .class_hid = BNXT_ULP_CLASS_HID_32d8a, + [2624] = { + .class_hid = BNXT_ULP_CLASS_HID_41bce, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 28676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2045] = { - .class_hid = BNXT_ULP_CLASS_HID_5cc6, + [2625] = { + .class_hid = BNXT_ULP_CLASS_HID_41b22, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2046] = { - .class_hid = BNXT_ULP_CLASS_HID_11712, + [2626] = { + .class_hid = BNXT_ULP_CLASS_HID_43232, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 28676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2047] = { - .class_hid = BNXT_ULP_CLASS_HID_20d12, + [2627] = { + .class_hid = BNXT_ULP_CLASS_HID_400e6, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2048] = { - .class_hid = BNXT_ULP_CLASS_HID_32312, + [2628] = { + .class_hid = BNXT_ULP_CLASS_HID_43bf6, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 28676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2049] = { - .class_hid = BNXT_ULP_CLASS_HID_06b2, + [2629] = { + .class_hid = BNXT_ULP_CLASS_HID_4308e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2050] = { - .class_hid = BNXT_ULP_CLASS_HID_13cb2, + [2630] = { + .class_hid = BNXT_ULP_CLASS_HID_42b9e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 30724, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2051] = { - .class_hid = BNXT_ULP_CLASS_HID_252b2, + [2631] = { + .class_hid = BNXT_ULP_CLASS_HID_43652, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2052] = { - .class_hid = BNXT_ULP_CLASS_HID_348b2, + [2632] = { + .class_hid = BNXT_ULP_CLASS_HID_451a2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 30724, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2053] = { - .class_hid = BNXT_ULP_CLASS_HID_1c5e, + [2633] = { + .class_hid = BNXT_ULP_CLASS_HID_450b6, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2054] = { - .class_hid = BNXT_ULP_CLASS_HID_1325e, + [2634] = { + .class_hid = BNXT_ULP_CLASS_HID_44b86, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 155, + .hdr_sig_id = 6, + .flow_sig_id = 30724, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2055] = { - .class_hid = BNXT_ULP_CLASS_HID_2285e, + [2635] = { + .class_hid = BNXT_ULP_CLASS_HID_4567a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 156, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2056] = { - .class_hid = BNXT_ULP_CLASS_HID_35e5e, + [2636] = { + .class_hid = BNXT_ULP_CLASS_HID_41216, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 157, + .hdr_sig_id = 6, + .flow_sig_id = 30724, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2057] = { - .class_hid = BNXT_ULP_CLASS_HID_55e2, + [2637] = { + .class_hid = BNXT_ULP_CLASS_HID_4167a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 158, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2058] = { - .class_hid = BNXT_ULP_CLASS_HID_14be2, + [2638] = { + .class_hid = BNXT_ULP_CLASS_HID_4314a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 158, + .hdr_sig_id = 7, + .flow_sig_id = 16388, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2059] = { - .class_hid = BNXT_ULP_CLASS_HID_2023e, + [2639] = { + .class_hid = BNXT_ULP_CLASS_HID_41c3e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 158, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2060] = { - .class_hid = BNXT_ULP_CLASS_HID_3383e, + [2640] = { + .class_hid = BNXT_ULP_CLASS_HID_4370e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 158, + .hdr_sig_id = 7, + .flow_sig_id = 16388, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2061] = { - .class_hid = BNXT_ULP_CLASS_HID_2b0a, + [2641] = { + .class_hid = BNXT_ULP_CLASS_HID_42fce, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 158, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2062] = { - .class_hid = BNXT_ULP_CLASS_HID_1410a, + [2642] = { + .class_hid = BNXT_ULP_CLASS_HID_446de, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 158, + .hdr_sig_id = 7, + .flow_sig_id = 16388, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2063] = { - .class_hid = BNXT_ULP_CLASS_HID_21846, + [2643] = { + .class_hid = BNXT_ULP_CLASS_HID_45582, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 159, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2064] = { - .class_hid = BNXT_ULP_CLASS_HID_30e46, + [2644] = { + .class_hid = BNXT_ULP_CLASS_HID_411ae, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 160, + .hdr_sig_id = 7, + .flow_sig_id = 16388, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2065] = { - .class_hid = BNXT_ULP_CLASS_HID_15e6, + [2645] = { + .class_hid = BNXT_ULP_CLASS_HID_44b36, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2066] = { - .class_hid = BNXT_ULP_CLASS_HID_10be6, + [2646] = { + .class_hid = BNXT_ULP_CLASS_HID_406d2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 24580, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2067] = { - .class_hid = BNXT_ULP_CLASS_HID_221e6, + [2647] = { + .class_hid = BNXT_ULP_CLASS_HID_41586, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2068] = { - .class_hid = BNXT_ULP_CLASS_HID_357e6, + [2648] = { + .class_hid = BNXT_ULP_CLASS_HID_40c96, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 24580, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2069] = { - .class_hid = BNXT_ULP_CLASS_HID_161a, + [2649] = { + .class_hid = BNXT_ULP_CLASS_HID_42556, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2070] = { - .class_hid = BNXT_ULP_CLASS_HID_10c1a, + [2650] = { + .class_hid = BNXT_ULP_CLASS_HID_45ca6, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 24580, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2071] = { - .class_hid = BNXT_ULP_CLASS_HID_2221a, + [2651] = { + .class_hid = BNXT_ULP_CLASS_HID_42b6a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2072] = { - .class_hid = BNXT_ULP_CLASS_HID_3581a, + [2652] = { + .class_hid = BNXT_ULP_CLASS_HID_4427a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 24580, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2073] = { - .class_hid = BNXT_ULP_CLASS_HID_2fae, + [2653] = { + .class_hid = BNXT_ULP_CLASS_HID_6227a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2074] = { - .class_hid = BNXT_ULP_CLASS_HID_145ae, + [2654] = { + .class_hid = BNXT_ULP_CLASS_HID_65d4a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2075] = { - .class_hid = BNXT_ULP_CLASS_HID_21cfa, + [2655] = { + .class_hid = BNXT_ULP_CLASS_HID_6283e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2076] = { - .class_hid = BNXT_ULP_CLASS_HID_332fa, + [2656] = { + .class_hid = BNXT_ULP_CLASS_HID_6430e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2077] = { - .class_hid = BNXT_ULP_CLASS_HID_2536, + [2657] = { + .class_hid = BNXT_ULP_CLASS_HID_61c9a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2078] = { - .class_hid = BNXT_ULP_CLASS_HID_15b36, + [2658] = { + .class_hid = BNXT_ULP_CLASS_HID_637ea, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2079] = { - .class_hid = BNXT_ULP_CLASS_HID_21202, + [2659] = { + .class_hid = BNXT_ULP_CLASS_HID_6025e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2080] = { - .class_hid = BNXT_ULP_CLASS_HID_30802, + [2660] = { + .class_hid = BNXT_ULP_CLASS_HID_63dae, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2081] = { - .class_hid = BNXT_ULP_CLASS_HID_4b56, + [2661] = { + .class_hid = BNXT_ULP_CLASS_HID_63bc2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2082] = { - .class_hid = BNXT_ULP_CLASS_HID_105a2, + [2662] = { + .class_hid = BNXT_ULP_CLASS_HID_652d2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 57348, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2083] = { - .class_hid = BNXT_ULP_CLASS_HID_23ba2, + [2663] = { + .class_hid = BNXT_ULP_CLASS_HID_62186, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2084] = { - .class_hid = BNXT_ULP_CLASS_HID_351a2, + [2664] = { + .class_hid = BNXT_ULP_CLASS_HID_65896, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, + .hdr_sig_id = 7, + .flow_sig_id = 57348, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2085] = { - .class_hid = BNXT_ULP_CLASS_HID_10c6, + [2665] = { + .class_hid = BNXT_ULP_CLASS_HID_61262, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2086] = { - .class_hid = BNXT_ULP_CLASS_HID_106c6, + [2666] = { + .class_hid = BNXT_ULP_CLASS_HID_60d72, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 161, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 57348, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2087] = { - .class_hid = BNXT_ULP_CLASS_HID_23cc6, + [2667] = { + .class_hid = BNXT_ULP_CLASS_HID_61826, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 162, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2088] = { - .class_hid = BNXT_ULP_CLASS_HID_352c6, + [2668] = { + .class_hid = BNXT_ULP_CLASS_HID_63336, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 163, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 57348, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2089] = { - .class_hid = BNXT_ULP_CLASS_HID_266a, + [2669] = { + .class_hid = BNXT_ULP_CLASS_HID_50c7a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 164, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2090] = { - .class_hid = BNXT_ULP_CLASS_HID_15c6a, + [2670] = { + .class_hid = BNXT_ULP_CLASS_HID_5274a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 164, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81924, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2091] = { - .class_hid = BNXT_ULP_CLASS_HID_216a6, + [2671] = { + .class_hid = BNXT_ULP_CLASS_HID_5323e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 164, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2092] = { - .class_hid = BNXT_ULP_CLASS_HID_30ca6, + [2672] = { + .class_hid = BNXT_ULP_CLASS_HID_52d0e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 164, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81924, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2093] = { - .class_hid = BNXT_ULP_CLASS_HID_3ff2, + [2673] = { + .class_hid = BNXT_ULP_CLASS_HID_545ce, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 164, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2094] = { - .class_hid = BNXT_ULP_CLASS_HID_155f2, + [2674] = { + .class_hid = BNXT_ULP_CLASS_HID_501ea, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 164, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81924, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2095] = { - .class_hid = BNXT_ULP_CLASS_HID_24bf2, + [2675] = { + .class_hid = BNXT_ULP_CLASS_HID_54b82, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 165, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2096] = { - .class_hid = BNXT_ULP_CLASS_HID_302ce, + [2676] = { + .class_hid = BNXT_ULP_CLASS_HID_507ae, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 166, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81924, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2097] = { - .class_hid = BNXT_ULP_CLASS_HID_4512, + [2677] = { + .class_hid = BNXT_ULP_CLASS_HID_505c2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2098] = { - .class_hid = BNXT_ULP_CLASS_HID_11c6e, + [2678] = { + .class_hid = BNXT_ULP_CLASS_HID_53cd2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90116, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2099] = { - .class_hid = BNXT_ULP_CLASS_HID_2326e, + [2679] = { + .class_hid = BNXT_ULP_CLASS_HID_50b86, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2100] = { - .class_hid = BNXT_ULP_CLASS_HID_3286e, + [2680] = { + .class_hid = BNXT_ULP_CLASS_HID_52296, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90116, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2101] = { - .class_hid = BNXT_ULP_CLASS_HID_49b6, + [2681] = { + .class_hid = BNXT_ULP_CLASS_HID_55b56, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2102] = { - .class_hid = BNXT_ULP_CLASS_HID_10082, + [2682] = { + .class_hid = BNXT_ULP_CLASS_HID_51772, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90116, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2103] = { - .class_hid = BNXT_ULP_CLASS_HID_23682, + [2683] = { + .class_hid = BNXT_ULP_CLASS_HID_5416a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2104] = { - .class_hid = BNXT_ULP_CLASS_HID_32c82, + [2684] = { + .class_hid = BNXT_ULP_CLASS_HID_51d36, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90116, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2105] = { - .class_hid = BNXT_ULP_CLASS_HID_2016, + [2685] = { + .class_hid = BNXT_ULP_CLASS_HID_7587a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2106] = { - .class_hid = BNXT_ULP_CLASS_HID_15616, + [2686] = { + .class_hid = BNXT_ULP_CLASS_HID_71406, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2107] = { - .class_hid = BNXT_ULP_CLASS_HID_21162, + [2687] = { + .class_hid = BNXT_ULP_CLASS_HID_75e3e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2108] = { - .class_hid = BNXT_ULP_CLASS_HID_30762, + [2688] = { + .class_hid = BNXT_ULP_CLASS_HID_71dda, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2109] = { - .class_hid = BNXT_ULP_CLASS_HID_39be, + [2689] = { + .class_hid = BNXT_ULP_CLASS_HID_7329a, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2110] = { - .class_hid = BNXT_ULP_CLASS_HID_12fbe, + [2690] = { + .class_hid = BNXT_ULP_CLASS_HID_72dea, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2111] = { - .class_hid = BNXT_ULP_CLASS_HID_245be, + [2691] = { + .class_hid = BNXT_ULP_CLASS_HID_7385e, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2112] = { - .class_hid = BNXT_ULP_CLASS_HID_31c8a, + [2692] = { + .class_hid = BNXT_ULP_CLASS_HID_753ae, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2113] = { - .class_hid = BNXT_ULP_CLASS_HID_5fde, + [2693] = { + .class_hid = BNXT_ULP_CLASS_HID_751c2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2114] = { - .class_hid = BNXT_ULP_CLASS_HID_1162a, + [2694] = { + .class_hid = BNXT_ULP_CLASS_HID_748d2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 122884, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2115] = { - .class_hid = BNXT_ULP_CLASS_HID_20c2a, + [2695] = { + .class_hid = BNXT_ULP_CLASS_HID_75786, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2116] = { - .class_hid = BNXT_ULP_CLASS_HID_3222a, + [2696] = { + .class_hid = BNXT_ULP_CLASS_HID_713a2, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 122884, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2117] = { - .class_hid = BNXT_ULP_CLASS_HID_34de, + [2697] = { + .class_hid = BNXT_ULP_CLASS_HID_70862, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2118] = { - .class_hid = BNXT_ULP_CLASS_HID_3a12, + [2698] = { + .class_hid = BNXT_ULP_CLASS_HID_72372, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 122884, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2119] = { - .class_hid = BNXT_ULP_CLASS_HID_14f2, + [2699] = { + .class_hid = BNXT_ULP_CLASS_HID_70e26, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2120] = { - .class_hid = BNXT_ULP_CLASS_HID_4a62, + [2700] = { + .class_hid = BNXT_ULP_CLASS_HID_72936, .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 167, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 122884, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2121] = { - .class_hid = BNXT_ULP_CLASS_HID_370e, + [2701] = { + .class_hid = BNXT_ULP_CLASS_HID_229b8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 167, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2122] = { - .class_hid = BNXT_ULP_CLASS_HID_12d0e, + [2702] = { + .class_hid = BNXT_ULP_CLASS_HID_240a8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 167, + .hdr_sig_id = 8, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2123] = { - .class_hid = BNXT_ULP_CLASS_HID_2430e, + [2703] = { + .class_hid = BNXT_ULP_CLASS_HID_22f74, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 168, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2124] = { - .class_hid = BNXT_ULP_CLASS_HID_31dda, + [2704] = { + .class_hid = BNXT_ULP_CLASS_HID_24664, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 169, + .hdr_sig_id = 8, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2125] = { - .class_hid = BNXT_ULP_CLASS_HID_11ae, + [2705] = { + .class_hid = BNXT_ULP_CLASS_HID_23314, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 170, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2126] = { - .class_hid = BNXT_ULP_CLASS_HID_107ae, + [2706] = { + .class_hid = BNXT_ULP_CLASS_HID_22a04, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 170, + .hdr_sig_id = 8, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2127] = { - .class_hid = BNXT_ULP_CLASS_HID_23dae, + [2707] = { + .class_hid = BNXT_ULP_CLASS_HID_238d0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 170, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2128] = { - .class_hid = BNXT_ULP_CLASS_HID_353ae, + [2708] = { + .class_hid = BNXT_ULP_CLASS_HID_253c0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 170, + .hdr_sig_id = 8, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2129] = { - .class_hid = BNXT_ULP_CLASS_HID_427a, + [2709] = { + .class_hid = BNXT_ULP_CLASS_HID_24dcc, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 170, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2130] = { - .class_hid = BNXT_ULP_CLASS_HID_11d36, + [2710] = { + .class_hid = BNXT_ULP_CLASS_HID_209f0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 170, + .hdr_sig_id = 8, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2131] = { - .class_hid = BNXT_ULP_CLASS_HID_23336, + [2711] = { + .class_hid = BNXT_ULP_CLASS_HID_214bc, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 171, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2132] = { - .class_hid = BNXT_ULP_CLASS_HID_32936, + [2712] = { + .class_hid = BNXT_ULP_CLASS_HID_20fac, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 172, + .hdr_sig_id = 8, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2133] = { - .class_hid = BNXT_ULP_CLASS_HID_0c96, + [2713] = { + .class_hid = BNXT_ULP_CLASS_HID_257a8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2134] = { - .class_hid = BNXT_ULP_CLASS_HID_12296, + [2714] = { + .class_hid = BNXT_ULP_CLASS_HID_2134c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2135] = { - .class_hid = BNXT_ULP_CLASS_HID_25896, + [2715] = { + .class_hid = BNXT_ULP_CLASS_HID_25d64, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2136] = { - .class_hid = BNXT_ULP_CLASS_HID_313a2, + [2716] = { + .class_hid = BNXT_ULP_CLASS_HID_21908, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2137] = { - .class_hid = BNXT_ULP_CLASS_HID_314a, + [2717] = { + .class_hid = BNXT_ULP_CLASS_HID_23488, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2138] = { - .class_hid = BNXT_ULP_CLASS_HID_1274a, + [2718] = { + .class_hid = BNXT_ULP_CLASS_HID_22ff8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2139] = { - .class_hid = BNXT_ULP_CLASS_HID_25d4a, + [2719] = { + .class_hid = BNXT_ULP_CLASS_HID_23a44, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2140] = { - .class_hid = BNXT_ULP_CLASS_HID_31406, + [2720] = { + .class_hid = BNXT_ULP_CLASS_HID_255b4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2141] = { - .class_hid = BNXT_ULP_CLASS_HID_46de, + [2721] = { + .class_hid = BNXT_ULP_CLASS_HID_21e64, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2142] = { - .class_hid = BNXT_ULP_CLASS_HID_101ea, + [2722] = { + .class_hid = BNXT_ULP_CLASS_HID_23954, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2143] = { - .class_hid = BNXT_ULP_CLASS_HID_237ea, + [2723] = { + .class_hid = BNXT_ULP_CLASS_HID_20420, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2144] = { - .class_hid = BNXT_ULP_CLASS_HID_32dea, + [2724] = { + .class_hid = BNXT_ULP_CLASS_HID_23f10, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2145] = { - .class_hid = BNXT_ULP_CLASS_HID_5ca6, + [2725] = { + .class_hid = BNXT_ULP_CLASS_HID_2591c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2146] = { - .class_hid = BNXT_ULP_CLASS_HID_11772, + [2726] = { + .class_hid = BNXT_ULP_CLASS_HID_214c0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2147] = { - .class_hid = BNXT_ULP_CLASS_HID_20d72, + [2727] = { + .class_hid = BNXT_ULP_CLASS_HID_25ed8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2148] = { - .class_hid = BNXT_ULP_CLASS_HID_32372, + [2728] = { + .class_hid = BNXT_ULP_CLASS_HID_21afc, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2149] = { - .class_hid = BNXT_ULP_CLASS_HID_06d2, + [2729] = { + .class_hid = BNXT_ULP_CLASS_HID_222f8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2150] = { - .class_hid = BNXT_ULP_CLASS_HID_13cd2, + [2730] = { + .class_hid = BNXT_ULP_CLASS_HID_25de8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2151] = { - .class_hid = BNXT_ULP_CLASS_HID_252d2, + [2731] = { + .class_hid = BNXT_ULP_CLASS_HID_228b4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2152] = { - .class_hid = BNXT_ULP_CLASS_HID_348d2, + [2732] = { + .class_hid = BNXT_ULP_CLASS_HID_243a4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2153] = { - .class_hid = BNXT_ULP_CLASS_HID_1c3e, + [2733] = { + .class_hid = BNXT_ULP_CLASS_HID_6226c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2154] = { - .class_hid = BNXT_ULP_CLASS_HID_1323e, + [2734] = { + .class_hid = BNXT_ULP_CLASS_HID_65d5c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 173, + .hdr_sig_id = 8, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2155] = { - .class_hid = BNXT_ULP_CLASS_HID_2283e, + [2735] = { + .class_hid = BNXT_ULP_CLASS_HID_62828, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 174, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2156] = { - .class_hid = BNXT_ULP_CLASS_HID_35e3e, + [2736] = { + .class_hid = BNXT_ULP_CLASS_HID_64318, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 175, + .hdr_sig_id = 8, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2157] = { - .class_hid = BNXT_ULP_CLASS_HID_5582, + [2737] = { + .class_hid = BNXT_ULP_CLASS_HID_60fc8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 176, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2158] = { - .class_hid = BNXT_ULP_CLASS_HID_14b82, + [2738] = { + .class_hid = BNXT_ULP_CLASS_HID_62738, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 176, + .hdr_sig_id = 8, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2159] = { - .class_hid = BNXT_ULP_CLASS_HID_2025e, + [2739] = { + .class_hid = BNXT_ULP_CLASS_HID_63584, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 176, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2160] = { - .class_hid = BNXT_ULP_CLASS_HID_3385e, + [2740] = { + .class_hid = BNXT_ULP_CLASS_HID_62cf4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 176, + .hdr_sig_id = 8, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2161] = { - .class_hid = BNXT_ULP_CLASS_HID_2b6a, + [2741] = { + .class_hid = BNXT_ULP_CLASS_HID_64680, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 176, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2162] = { - .class_hid = BNXT_ULP_CLASS_HID_1416a, + [2742] = { + .class_hid = BNXT_ULP_CLASS_HID_602a4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 176, + .hdr_sig_id = 8, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2163] = { - .class_hid = BNXT_ULP_CLASS_HID_21826, + [2743] = { + .class_hid = BNXT_ULP_CLASS_HID_61170, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 177, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2164] = { - .class_hid = BNXT_ULP_CLASS_HID_30e26, + [2744] = { + .class_hid = BNXT_ULP_CLASS_HID_60860, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 178, + .hdr_sig_id = 8, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2165] = { - .class_hid = BNXT_ULP_CLASS_HID_1586, + [2745] = { + .class_hid = BNXT_ULP_CLASS_HID_6505c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2166] = { - .class_hid = BNXT_ULP_CLASS_HID_10b86, + [2746] = { + .class_hid = BNXT_ULP_CLASS_HID_64b4c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2167] = { - .class_hid = BNXT_ULP_CLASS_HID_22186, + [2747] = { + .class_hid = BNXT_ULP_CLASS_HID_65618, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2168] = { - .class_hid = BNXT_ULP_CLASS_HID_35786, + [2748] = { + .class_hid = BNXT_ULP_CLASS_HID_6123c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2169] = { - .class_hid = BNXT_ULP_CLASS_HID_167a, + [2749] = { + .class_hid = BNXT_ULP_CLASS_HID_631bc, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2170] = { - .class_hid = BNXT_ULP_CLASS_HID_10c7a, + [2750] = { + .class_hid = BNXT_ULP_CLASS_HID_628ac, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2171] = { - .class_hid = BNXT_ULP_CLASS_HID_2227a, + [2751] = { + .class_hid = BNXT_ULP_CLASS_HID_63778, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2172] = { - .class_hid = BNXT_ULP_CLASS_HID_3587a, + [2752] = { + .class_hid = BNXT_ULP_CLASS_HID_62e68, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2173] = { - .class_hid = BNXT_ULP_CLASS_HID_2fce, + [2753] = { + .class_hid = BNXT_ULP_CLASS_HID_61b18, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2174] = { - .class_hid = BNXT_ULP_CLASS_HID_145ce, + [2754] = { + .class_hid = BNXT_ULP_CLASS_HID_63208, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2175] = { - .class_hid = BNXT_ULP_CLASS_HID_21c9a, + [2755] = { + .class_hid = BNXT_ULP_CLASS_HID_600d4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2176] = { - .class_hid = BNXT_ULP_CLASS_HID_3329a, + [2756] = { + .class_hid = BNXT_ULP_CLASS_HID_63bc4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2177] = { - .class_hid = BNXT_ULP_CLASS_HID_2556, + [2757] = { + .class_hid = BNXT_ULP_CLASS_HID_655d0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2178] = { - .class_hid = BNXT_ULP_CLASS_HID_15b56, + [2758] = { + .class_hid = BNXT_ULP_CLASS_HID_611f4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2179] = { - .class_hid = BNXT_ULP_CLASS_HID_21262, + [2759] = { + .class_hid = BNXT_ULP_CLASS_HID_65b8c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2180] = { - .class_hid = BNXT_ULP_CLASS_HID_30862, + [2760] = { + .class_hid = BNXT_ULP_CLASS_HID_617b0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2181] = { - .class_hid = BNXT_ULP_CLASS_HID_4b36, + [2761] = { + .class_hid = BNXT_ULP_CLASS_HID_63fac, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2182] = { - .class_hid = BNXT_ULP_CLASS_HID_105c2, + [2762] = { + .class_hid = BNXT_ULP_CLASS_HID_6569c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2183] = { - .class_hid = BNXT_ULP_CLASS_HID_23bc2, + [2763] = { + .class_hid = BNXT_ULP_CLASS_HID_62568, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2184] = { - .class_hid = BNXT_ULP_CLASS_HID_351c2, + [2764] = { + .class_hid = BNXT_ULP_CLASS_HID_65c58, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, + .hdr_sig_id = 8, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2185] = { - .class_hid = BNXT_ULP_CLASS_HID_10a6, + [2765] = { + .class_hid = BNXT_ULP_CLASS_HID_35fb8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2186] = { - .class_hid = BNXT_ULP_CLASS_HID_106a6, + [2766] = { + .class_hid = BNXT_ULP_CLASS_HID_31b5c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 179, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2187] = { - .class_hid = BNXT_ULP_CLASS_HID_23ca6, + [2767] = { + .class_hid = BNXT_ULP_CLASS_HID_34574, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 180, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2188] = { - .class_hid = BNXT_ULP_CLASS_HID_352a6, + [2768] = { + .class_hid = BNXT_ULP_CLASS_HID_30118, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 181, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2189] = { - .class_hid = BNXT_ULP_CLASS_HID_260a, + [2769] = { + .class_hid = BNXT_ULP_CLASS_HID_32914, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 182, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2190] = { - .class_hid = BNXT_ULP_CLASS_HID_15c0a, + [2770] = { + .class_hid = BNXT_ULP_CLASS_HID_34004, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 182, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2191] = { - .class_hid = BNXT_ULP_CLASS_HID_216c6, + [2771] = { + .class_hid = BNXT_ULP_CLASS_HID_32ed0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 182, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2192] = { - .class_hid = BNXT_ULP_CLASS_HID_30cc6, + [2772] = { + .class_hid = BNXT_ULP_CLASS_HID_349c0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 182, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2193] = { - .class_hid = BNXT_ULP_CLASS_HID_3f92, + [2773] = { + .class_hid = BNXT_ULP_CLASS_HID_30480, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 182, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2194] = { - .class_hid = BNXT_ULP_CLASS_HID_15592, + [2774] = { + .class_hid = BNXT_ULP_CLASS_HID_33ff0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 182, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2195] = { - .class_hid = BNXT_ULP_CLASS_HID_24b92, + [2775] = { + .class_hid = BNXT_ULP_CLASS_HID_30abc, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 183, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2196] = { - .class_hid = BNXT_ULP_CLASS_HID_302ae, + [2776] = { + .class_hid = BNXT_ULP_CLASS_HID_325ac, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 184, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2197] = { - .class_hid = BNXT_ULP_CLASS_HID_4572, + [2777] = { + .class_hid = BNXT_ULP_CLASS_HID_34da8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2198] = { - .class_hid = BNXT_ULP_CLASS_HID_11c0e, + [2778] = { + .class_hid = BNXT_ULP_CLASS_HID_3094c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2199] = { - .class_hid = BNXT_ULP_CLASS_HID_2320e, + [2779] = { + .class_hid = BNXT_ULP_CLASS_HID_31418, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2200] = { - .class_hid = BNXT_ULP_CLASS_HID_3280e, + [2780] = { + .class_hid = BNXT_ULP_CLASS_HID_30f08, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2201] = { - .class_hid = BNXT_ULP_CLASS_HID_49d6, + [2781] = { + .class_hid = BNXT_ULP_CLASS_HID_32a88, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2202] = { - .class_hid = BNXT_ULP_CLASS_HID_100e2, + [2782] = { + .class_hid = BNXT_ULP_CLASS_HID_345f8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2203] = { - .class_hid = BNXT_ULP_CLASS_HID_236e2, + [2783] = { + .class_hid = BNXT_ULP_CLASS_HID_35044, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2204] = { - .class_hid = BNXT_ULP_CLASS_HID_32ce2, + [2784] = { + .class_hid = BNXT_ULP_CLASS_HID_34bb4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2205] = { - .class_hid = BNXT_ULP_CLASS_HID_2076, + [2785] = { + .class_hid = BNXT_ULP_CLASS_HID_33464, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2206] = { - .class_hid = BNXT_ULP_CLASS_HID_15676, + [2786] = { + .class_hid = BNXT_ULP_CLASS_HID_32f54, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2207] = { - .class_hid = BNXT_ULP_CLASS_HID_21102, + [2787] = { + .class_hid = BNXT_ULP_CLASS_HID_33a20, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2208] = { - .class_hid = BNXT_ULP_CLASS_HID_30702, + [2788] = { + .class_hid = BNXT_ULP_CLASS_HID_35510, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2209] = { - .class_hid = BNXT_ULP_CLASS_HID_39de, + [2789] = { + .class_hid = BNXT_ULP_CLASS_HID_313d0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2210] = { - .class_hid = BNXT_ULP_CLASS_HID_12fde, + [2790] = { + .class_hid = BNXT_ULP_CLASS_HID_30ac0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2211] = { - .class_hid = BNXT_ULP_CLASS_HID_245de, + [2791] = { + .class_hid = BNXT_ULP_CLASS_HID_3198c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2212] = { - .class_hid = BNXT_ULP_CLASS_HID_31cea, + [2792] = { + .class_hid = BNXT_ULP_CLASS_HID_330fc, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2213] = { - .class_hid = BNXT_ULP_CLASS_HID_5fbe, + [2793] = { + .class_hid = BNXT_ULP_CLASS_HID_358f8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2214] = { - .class_hid = BNXT_ULP_CLASS_HID_1164a, + [2794] = { + .class_hid = BNXT_ULP_CLASS_HID_3149c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2215] = { - .class_hid = BNXT_ULP_CLASS_HID_20c4a, + [2795] = { + .class_hid = BNXT_ULP_CLASS_HID_35eb4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2216] = { - .class_hid = BNXT_ULP_CLASS_HID_3224a, + [2796] = { + .class_hid = BNXT_ULP_CLASS_HID_31a58, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2217] = { - .class_hid = BNXT_ULP_CLASS_HID_34be, + [2797] = { + .class_hid = BNXT_ULP_CLASS_HID_7586c, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2218] = { - .class_hid = BNXT_ULP_CLASS_HID_3a72, + [2798] = { + .class_hid = BNXT_ULP_CLASS_HID_71410, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2219] = { - .class_hid = BNXT_ULP_CLASS_HID_1492, + [2799] = { + .class_hid = BNXT_ULP_CLASS_HID_75e28, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2220] = { - .class_hid = BNXT_ULP_CLASS_HID_4a02, + [2800] = { + .class_hid = BNXT_ULP_CLASS_HID_71dcc, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 185, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2221] = { - .class_hid = BNXT_ULP_CLASS_HID_09ea, + [2801] = { + .class_hid = BNXT_ULP_CLASS_HID_725c8, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 185, + .hdr_sig_id = 8, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2222] = { - .class_hid = BNXT_ULP_CLASS_HID_2912, + [2802] = { + .class_hid = BNXT_ULP_CLASS_HID_75d38, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 186, + .hdr_sig_id = 8, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2223] = { - .class_hid = BNXT_ULP_CLASS_HID_03b2, + [2803] = { + .class_hid = BNXT_ULP_CLASS_HID_72b84, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 186, + .hdr_sig_id = 8, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2224] = { - .class_hid = BNXT_ULP_CLASS_HID_5f7e, + [2804] = { + .class_hid = BNXT_ULP_CLASS_HID_742f4, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 187, + .hdr_sig_id = 8, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2225] = { - .class_hid = BNXT_ULP_CLASS_HID_03a6, + [2805] = { + .class_hid = BNXT_ULP_CLASS_HID_701b4, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 187, + .hdr_sig_id = 8, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2226] = { - .class_hid = BNXT_ULP_CLASS_HID_23ce, + [2806] = { + .class_hid = BNXT_ULP_CLASS_HID_738a4, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 187, + .hdr_sig_id = 8, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2227] = { - .class_hid = BNXT_ULP_CLASS_HID_1a6e, + [2807] = { + .class_hid = BNXT_ULP_CLASS_HID_70770, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 187, + .hdr_sig_id = 8, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2228] = { - .class_hid = BNXT_ULP_CLASS_HID_593a, + [2808] = { + .class_hid = BNXT_ULP_CLASS_HID_73e60, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 187, + .hdr_sig_id = 8, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2229] = { - .class_hid = BNXT_ULP_CLASS_HID_4dce, + [2809] = { + .class_hid = BNXT_ULP_CLASS_HID_7465c, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 187, + .hdr_sig_id = 8, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2230] = { - .class_hid = BNXT_ULP_CLASS_HID_0e02, + [2810] = { + .class_hid = BNXT_ULP_CLASS_HID_70200, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 188, + .hdr_sig_id = 8, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2231] = { - .class_hid = BNXT_ULP_CLASS_HID_4796, + [2811] = { + .class_hid = BNXT_ULP_CLASS_HID_710cc, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 188, + .hdr_sig_id = 8, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2232] = { - .class_hid = BNXT_ULP_CLASS_HID_246e, + [2812] = { + .class_hid = BNXT_ULP_CLASS_HID_7083c, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 189, + .hdr_sig_id = 8, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2233] = { - .class_hid = BNXT_ULP_CLASS_HID_478a, + [2813] = { + .class_hid = BNXT_ULP_CLASS_HID_727bc, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 189, + .hdr_sig_id = 8, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2234] = { - .class_hid = BNXT_ULP_CLASS_HID_08fe, + [2814] = { + .class_hid = BNXT_ULP_CLASS_HID_75eac, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 189, + .hdr_sig_id = 8, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2235] = { - .class_hid = BNXT_ULP_CLASS_HID_5e52, + [2815] = { + .class_hid = BNXT_ULP_CLASS_HID_72d78, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 189, + .hdr_sig_id = 8, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2236] = { - .class_hid = BNXT_ULP_CLASS_HID_3e2a, + [2816] = { + .class_hid = BNXT_ULP_CLASS_HID_74468, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 189, + .hdr_sig_id = 8, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2237] = { - .class_hid = BNXT_ULP_CLASS_HID_5e46, + [2817] = { + .class_hid = BNXT_ULP_CLASS_HID_73118, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 189, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2238] = { - .class_hid = BNXT_ULP_CLASS_HID_02ba, + [2818] = { + .class_hid = BNXT_ULP_CLASS_HID_72808, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 190, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114756, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2239] = { - .class_hid = BNXT_ULP_CLASS_HID_580e, + [2819] = { + .class_hid = BNXT_ULP_CLASS_HID_736d4, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 190, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2240] = { - .class_hid = BNXT_ULP_CLASS_HID_38e6, + [2820] = { + .class_hid = BNXT_ULP_CLASS_HID_751c4, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114756, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2241] = { - .class_hid = BNXT_ULP_CLASS_HID_5802, + [2821] = { + .class_hid = BNXT_ULP_CLASS_HID_74bd0, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2242] = { - .class_hid = BNXT_ULP_CLASS_HID_1d76, + [2822] = { + .class_hid = BNXT_ULP_CLASS_HID_707f4, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2243] = { - .class_hid = BNXT_ULP_CLASS_HID_52ca, + [2823] = { + .class_hid = BNXT_ULP_CLASS_HID_71240, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2244] = { - .class_hid = BNXT_ULP_CLASS_HID_32a2, + [2824] = { + .class_hid = BNXT_ULP_CLASS_HID_70db0, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2245] = { - .class_hid = BNXT_ULP_CLASS_HID_34f6, + [2825] = { + .class_hid = BNXT_ULP_CLASS_HID_755ac, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2246] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3a, + [2826] = { + .class_hid = BNXT_ULP_CLASS_HID_71150, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114756, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2247] = { - .class_hid = BNXT_ULP_CLASS_HID_5a22, + [2827] = { + .class_hid = BNXT_ULP_CLASS_HID_75b68, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2248] = { - .class_hid = BNXT_ULP_CLASS_HID_541e, + [2828] = { + .class_hid = BNXT_ULP_CLASS_HID_7170c, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 191, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 114756, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2249] = { - .class_hid = BNXT_ULP_CLASS_HID_09ca, + [2829] = { + .class_hid = BNXT_ULP_CLASS_HID_2d2b8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 191, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2250] = { - .class_hid = BNXT_ULP_CLASS_HID_0216, + [2830] = { + .class_hid = BNXT_ULP_CLASS_HID_2cda8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 191, + .hdr_sig_id = 8, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2251] = { - .class_hid = BNXT_ULP_CLASS_HID_1f62, + [2831] = { + .class_hid = BNXT_ULP_CLASS_HID_2d874, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 192, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2252] = { - .class_hid = BNXT_ULP_CLASS_HID_1bae, + [2832] = { + .class_hid = BNXT_ULP_CLASS_HID_29418, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 193, + .hdr_sig_id = 8, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2253] = { - .class_hid = BNXT_ULP_CLASS_HID_2932, + [2833] = { + .class_hid = BNXT_ULP_CLASS_HID_2bc14, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 194, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2254] = { - .class_hid = BNXT_ULP_CLASS_HID_227e, + [2834] = { + .class_hid = BNXT_ULP_CLASS_HID_2d704, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 194, + .hdr_sig_id = 8, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2255] = { - .class_hid = BNXT_ULP_CLASS_HID_3f4a, + [2835] = { + .class_hid = BNXT_ULP_CLASS_HID_2a5d0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 194, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2256] = { - .class_hid = BNXT_ULP_CLASS_HID_3b96, + [2836] = { + .class_hid = BNXT_ULP_CLASS_HID_2dcc0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 194, + .hdr_sig_id = 8, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2257] = { - .class_hid = BNXT_ULP_CLASS_HID_0392, + [2837] = { + .class_hid = BNXT_ULP_CLASS_HID_29b80, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 194, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2258] = { - .class_hid = BNXT_ULP_CLASS_HID_1cde, + [2838] = { + .class_hid = BNXT_ULP_CLASS_HID_2b2f0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 194, + .hdr_sig_id = 8, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2259] = { - .class_hid = BNXT_ULP_CLASS_HID_192a, + [2839] = { + .class_hid = BNXT_ULP_CLASS_HID_281bc, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 195, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2260] = { - .class_hid = BNXT_ULP_CLASS_HID_1276, + [2840] = { + .class_hid = BNXT_ULP_CLASS_HID_2b8ac, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 196, + .hdr_sig_id = 8, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2261] = { - .class_hid = BNXT_ULP_CLASS_HID_5f5e, + [2841] = { + .class_hid = BNXT_ULP_CLASS_HID_2c0a8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2262] = { - .class_hid = BNXT_ULP_CLASS_HID_5baa, + [2842] = { + .class_hid = BNXT_ULP_CLASS_HID_29c4c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2263] = { - .class_hid = BNXT_ULP_CLASS_HID_54f6, + [2843] = { + .class_hid = BNXT_ULP_CLASS_HID_2c664, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2264] = { - .class_hid = BNXT_ULP_CLASS_HID_51c2, + [2844] = { + .class_hid = BNXT_ULP_CLASS_HID_28208, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2265] = { - .class_hid = BNXT_ULP_CLASS_HID_0386, + [2845] = { + .class_hid = BNXT_ULP_CLASS_HID_2a188, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2266] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd2, + [2846] = { + .class_hid = BNXT_ULP_CLASS_HID_2d8f8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2267] = { - .class_hid = BNXT_ULP_CLASS_HID_191e, + [2847] = { + .class_hid = BNXT_ULP_CLASS_HID_2a744, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2268] = { - .class_hid = BNXT_ULP_CLASS_HID_126a, + [2848] = { + .class_hid = BNXT_ULP_CLASS_HID_2deb4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2269] = { - .class_hid = BNXT_ULP_CLASS_HID_23ee, + [2849] = { + .class_hid = BNXT_ULP_CLASS_HID_28b64, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2270] = { - .class_hid = BNXT_ULP_CLASS_HID_3c3a, + [2850] = { + .class_hid = BNXT_ULP_CLASS_HID_2a254, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2271] = { - .class_hid = BNXT_ULP_CLASS_HID_3906, + [2851] = { + .class_hid = BNXT_ULP_CLASS_HID_2b120, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2272] = { - .class_hid = BNXT_ULP_CLASS_HID_3252, + [2852] = { + .class_hid = BNXT_ULP_CLASS_HID_2a810, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2273] = { - .class_hid = BNXT_ULP_CLASS_HID_1a4e, + [2853] = { + .class_hid = BNXT_ULP_CLASS_HID_2c21c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2274] = { - .class_hid = BNXT_ULP_CLASS_HID_169a, + [2854] = { + .class_hid = BNXT_ULP_CLASS_HID_281c0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2275] = { - .class_hid = BNXT_ULP_CLASS_HID_13e6, + [2855] = { + .class_hid = BNXT_ULP_CLASS_HID_2cbd8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2276] = { - .class_hid = BNXT_ULP_CLASS_HID_4be6, + [2856] = { + .class_hid = BNXT_ULP_CLASS_HID_287fc, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2277] = { - .class_hid = BNXT_ULP_CLASS_HID_591a, + [2857] = { + .class_hid = BNXT_ULP_CLASS_HID_2aff8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2278] = { - .class_hid = BNXT_ULP_CLASS_HID_5266, + [2858] = { + .class_hid = BNXT_ULP_CLASS_HID_2c6e8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2279] = { - .class_hid = BNXT_ULP_CLASS_HID_2eb2, + [2859] = { + .class_hid = BNXT_ULP_CLASS_HID_2d5b4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2280] = { - .class_hid = BNXT_ULP_CLASS_HID_2bfe, + [2860] = { + .class_hid = BNXT_ULP_CLASS_HID_29158, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2281] = { - .class_hid = BNXT_ULP_CLASS_HID_4dee, + [2861] = { + .class_hid = BNXT_ULP_CLASS_HID_6af6c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2282] = { - .class_hid = BNXT_ULP_CLASS_HID_463a, + [2862] = { + .class_hid = BNXT_ULP_CLASS_HID_6c65c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 197, + .hdr_sig_id = 8, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2283] = { - .class_hid = BNXT_ULP_CLASS_HID_4306, + [2863] = { + .class_hid = BNXT_ULP_CLASS_HID_6d528, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 198, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2284] = { - .class_hid = BNXT_ULP_CLASS_HID_5c52, + [2864] = { + .class_hid = BNXT_ULP_CLASS_HID_690cc, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 199, + .hdr_sig_id = 8, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2285] = { - .class_hid = BNXT_ULP_CLASS_HID_0e22, + [2865] = { + .class_hid = BNXT_ULP_CLASS_HID_6b8c8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 200, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2286] = { - .class_hid = BNXT_ULP_CLASS_HID_0b6e, + [2866] = { + .class_hid = BNXT_ULP_CLASS_HID_6d038, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 200, + .hdr_sig_id = 8, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2287] = { - .class_hid = BNXT_ULP_CLASS_HID_07ba, + [2867] = { + .class_hid = BNXT_ULP_CLASS_HID_6be84, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 200, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2288] = { - .class_hid = BNXT_ULP_CLASS_HID_0086, + [2868] = { + .class_hid = BNXT_ULP_CLASS_HID_6d9f4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 200, + .hdr_sig_id = 8, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2289] = { - .class_hid = BNXT_ULP_CLASS_HID_47b6, + [2869] = { + .class_hid = BNXT_ULP_CLASS_HID_694b4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 200, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2290] = { - .class_hid = BNXT_ULP_CLASS_HID_4082, + [2870] = { + .class_hid = BNXT_ULP_CLASS_HID_68fa4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 200, + .hdr_sig_id = 8, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2291] = { - .class_hid = BNXT_ULP_CLASS_HID_5dce, + [2871] = { + .class_hid = BNXT_ULP_CLASS_HID_69a70, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 201, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2292] = { - .class_hid = BNXT_ULP_CLASS_HID_561a, + [2872] = { + .class_hid = BNXT_ULP_CLASS_HID_6b560, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 202, + .hdr_sig_id = 8, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2293] = { - .class_hid = BNXT_ULP_CLASS_HID_244e, + [2873] = { + .class_hid = BNXT_ULP_CLASS_HID_6dd5c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2294] = { - .class_hid = BNXT_ULP_CLASS_HID_209a, + [2874] = { + .class_hid = BNXT_ULP_CLASS_HID_69900, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2295] = { - .class_hid = BNXT_ULP_CLASS_HID_3de6, + [2875] = { + .class_hid = BNXT_ULP_CLASS_HID_6c318, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2296] = { - .class_hid = BNXT_ULP_CLASS_HID_3632, + [2876] = { + .class_hid = BNXT_ULP_CLASS_HID_69f3c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2297] = { - .class_hid = BNXT_ULP_CLASS_HID_47aa, + [2877] = { + .class_hid = BNXT_ULP_CLASS_HID_6babc, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2298] = { - .class_hid = BNXT_ULP_CLASS_HID_40f6, + [2878] = { + .class_hid = BNXT_ULP_CLASS_HID_6d5ac, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2299] = { - .class_hid = BNXT_ULP_CLASS_HID_5dc2, + [2879] = { + .class_hid = BNXT_ULP_CLASS_HID_6a078, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2300] = { - .class_hid = BNXT_ULP_CLASS_HID_560e, + [2880] = { + .class_hid = BNXT_ULP_CLASS_HID_6db68, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2301] = { - .class_hid = BNXT_ULP_CLASS_HID_08de, + [2881] = { + .class_hid = BNXT_ULP_CLASS_HID_68418, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2302] = { - .class_hid = BNXT_ULP_CLASS_HID_052a, + [2882] = { + .class_hid = BNXT_ULP_CLASS_HID_6bf08, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2303] = { - .class_hid = BNXT_ULP_CLASS_HID_1e76, + [2883] = { + .class_hid = BNXT_ULP_CLASS_HID_68dd4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2304] = { - .class_hid = BNXT_ULP_CLASS_HID_1b42, + [2884] = { + .class_hid = BNXT_ULP_CLASS_HID_6a4c4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2305] = { - .class_hid = BNXT_ULP_CLASS_HID_5e72, + [2885] = { + .class_hid = BNXT_ULP_CLASS_HID_6ded0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2306] = { - .class_hid = BNXT_ULP_CLASS_HID_5abe, + [2886] = { + .class_hid = BNXT_ULP_CLASS_HID_69af4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2307] = { - .class_hid = BNXT_ULP_CLASS_HID_578a, + [2887] = { + .class_hid = BNXT_ULP_CLASS_HID_6c48c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2308] = { - .class_hid = BNXT_ULP_CLASS_HID_50d6, + [2888] = { + .class_hid = BNXT_ULP_CLASS_HID_680b0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2309] = { - .class_hid = BNXT_ULP_CLASS_HID_3e0a, + [2889] = { + .class_hid = BNXT_ULP_CLASS_HID_6a8ac, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2310] = { - .class_hid = BNXT_ULP_CLASS_HID_3b56, + [2890] = { + .class_hid = BNXT_ULP_CLASS_HID_6c39c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2311] = { - .class_hid = BNXT_ULP_CLASS_HID_37a2, + [2891] = { + .class_hid = BNXT_ULP_CLASS_HID_6ae68, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2312] = { - .class_hid = BNXT_ULP_CLASS_HID_30ee, + [2892] = { + .class_hid = BNXT_ULP_CLASS_HID_6c958, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, + .hdr_sig_id = 8, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2313] = { - .class_hid = BNXT_ULP_CLASS_HID_5e66, + [2893] = { + .class_hid = BNXT_ULP_CLASS_HID_3c8b8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2314] = { - .class_hid = BNXT_ULP_CLASS_HID_5ab2, + [2894] = { + .class_hid = BNXT_ULP_CLASS_HID_3845c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 203, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2315] = { - .class_hid = BNXT_ULP_CLASS_HID_57fe, + [2895] = { + .class_hid = BNXT_ULP_CLASS_HID_39328, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 204, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2316] = { - .class_hid = BNXT_ULP_CLASS_HID_50ca, + [2896] = { + .class_hid = BNXT_ULP_CLASS_HID_38a18, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 205, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2317] = { - .class_hid = BNXT_ULP_CLASS_HID_029a, + [2897] = { + .class_hid = BNXT_ULP_CLASS_HID_3d214, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 206, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2318] = { - .class_hid = BNXT_ULP_CLASS_HID_1fe6, + [2898] = { + .class_hid = BNXT_ULP_CLASS_HID_3cd04, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 206, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2319] = { - .class_hid = BNXT_ULP_CLASS_HID_1832, + [2899] = { + .class_hid = BNXT_ULP_CLASS_HID_3dbd0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 206, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2320] = { - .class_hid = BNXT_ULP_CLASS_HID_157e, + [2900] = { + .class_hid = BNXT_ULP_CLASS_HID_397f4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 206, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2321] = { - .class_hid = BNXT_ULP_CLASS_HID_582e, + [2901] = { + .class_hid = BNXT_ULP_CLASS_HID_3b180, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 206, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2322] = { - .class_hid = BNXT_ULP_CLASS_HID_557a, + [2902] = { + .class_hid = BNXT_ULP_CLASS_HID_3a8f0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 206, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2323] = { - .class_hid = BNXT_ULP_CLASS_HID_2e46, + [2903] = { + .class_hid = BNXT_ULP_CLASS_HID_3b7bc, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 207, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2324] = { - .class_hid = BNXT_ULP_CLASS_HID_2a92, + [2904] = { + .class_hid = BNXT_ULP_CLASS_HID_3aeac, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 208, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2325] = { - .class_hid = BNXT_ULP_CLASS_HID_38c6, + [2905] = { + .class_hid = BNXT_ULP_CLASS_HID_39b5c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2326] = { - .class_hid = BNXT_ULP_CLASS_HID_3512, + [2906] = { + .class_hid = BNXT_ULP_CLASS_HID_3b24c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2327] = { - .class_hid = BNXT_ULP_CLASS_HID_0e5e, + [2907] = { + .class_hid = BNXT_ULP_CLASS_HID_38118, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2328] = { - .class_hid = BNXT_ULP_CLASS_HID_0aaa, + [2908] = { + .class_hid = BNXT_ULP_CLASS_HID_3b808, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2329] = { - .class_hid = BNXT_ULP_CLASS_HID_5822, + [2909] = { + .class_hid = BNXT_ULP_CLASS_HID_3d788, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2330] = { - .class_hid = BNXT_ULP_CLASS_HID_556e, + [2910] = { + .class_hid = BNXT_ULP_CLASS_HID_393ac, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2331] = { - .class_hid = BNXT_ULP_CLASS_HID_51ba, + [2911] = { + .class_hid = BNXT_ULP_CLASS_HID_3dd44, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2332] = { - .class_hid = BNXT_ULP_CLASS_HID_2a86, + [2912] = { + .class_hid = BNXT_ULP_CLASS_HID_39968, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2333] = { - .class_hid = BNXT_ULP_CLASS_HID_1d56, + [2913] = { + .class_hid = BNXT_ULP_CLASS_HID_3a164, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2334] = { - .class_hid = BNXT_ULP_CLASS_HID_19a2, + [2914] = { + .class_hid = BNXT_ULP_CLASS_HID_3d854, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2335] = { - .class_hid = BNXT_ULP_CLASS_HID_12ee, + [2915] = { + .class_hid = BNXT_ULP_CLASS_HID_3a720, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2336] = { - .class_hid = BNXT_ULP_CLASS_HID_4aee, + [2916] = { + .class_hid = BNXT_ULP_CLASS_HID_3de10, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2337] = { - .class_hid = BNXT_ULP_CLASS_HID_52ea, + [2917] = { + .class_hid = BNXT_ULP_CLASS_HID_39cd0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2338] = { - .class_hid = BNXT_ULP_CLASS_HID_2f36, + [2918] = { + .class_hid = BNXT_ULP_CLASS_HID_3b7c0, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2339] = { - .class_hid = BNXT_ULP_CLASS_HID_2802, + [2919] = { + .class_hid = BNXT_ULP_CLASS_HID_3828c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2340] = { - .class_hid = BNXT_ULP_CLASS_HID_254e, + [2920] = { + .class_hid = BNXT_ULP_CLASS_HID_3bdfc, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2341] = { - .class_hid = BNXT_ULP_CLASS_HID_3282, + [2921] = { + .class_hid = BNXT_ULP_CLASS_HID_3c5f8, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2342] = { - .class_hid = BNXT_ULP_CLASS_HID_0fce, + [2922] = { + .class_hid = BNXT_ULP_CLASS_HID_3819c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2343] = { - .class_hid = BNXT_ULP_CLASS_HID_081a, + [2923] = { + .class_hid = BNXT_ULP_CLASS_HID_3cbb4, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2344] = { - .class_hid = BNXT_ULP_CLASS_HID_0566, + [2924] = { + .class_hid = BNXT_ULP_CLASS_HID_38758, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2345] = { - .class_hid = BNXT_ULP_CLASS_HID_34d6, + [2925] = { + .class_hid = BNXT_ULP_CLASS_HID_7c56c, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2346] = { - .class_hid = BNXT_ULP_CLASS_HID_3a1a, + [2926] = { + .class_hid = BNXT_ULP_CLASS_HID_78110, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2347] = { - .class_hid = BNXT_ULP_CLASS_HID_5a02, + [2927] = { + .class_hid = BNXT_ULP_CLASS_HID_7cb28, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2348] = { - .class_hid = BNXT_ULP_CLASS_HID_543e, + [2928] = { + .class_hid = BNXT_ULP_CLASS_HID_786cc, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 209, - .flow_pattern_id = 2, + .hdr_sig_id = 8, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2349] = { - .class_hid = BNXT_ULP_CLASS_HID_09aa, + [2929] = { + .class_hid = BNXT_ULP_CLASS_HID_7aec8, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 209, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2350] = { - .class_hid = BNXT_ULP_CLASS_HID_0276, + [2930] = { + .class_hid = BNXT_ULP_CLASS_HID_7c638, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 209, + .hdr_sig_id = 8, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2351] = { - .class_hid = BNXT_ULP_CLASS_HID_1f02, + [2931] = { + .class_hid = BNXT_ULP_CLASS_HID_7d484, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 210, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2352] = { - .class_hid = BNXT_ULP_CLASS_HID_1bce, + [2932] = { + .class_hid = BNXT_ULP_CLASS_HID_790a8, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 211, + .hdr_sig_id = 8, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2353] = { - .class_hid = BNXT_ULP_CLASS_HID_2952, + [2933] = { + .class_hid = BNXT_ULP_CLASS_HID_78ab4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 212, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2354] = { - .class_hid = BNXT_ULP_CLASS_HID_221e, + [2934] = { + .class_hid = BNXT_ULP_CLASS_HID_7a5a4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 212, + .hdr_sig_id = 8, + .flow_sig_id = 245764, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2355] = { - .class_hid = BNXT_ULP_CLASS_HID_3f2a, + [2935] = { + .class_hid = BNXT_ULP_CLASS_HID_7b070, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 212, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2356] = { - .class_hid = BNXT_ULP_CLASS_HID_3bf6, + [2936] = { + .class_hid = BNXT_ULP_CLASS_HID_7ab60, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 212, + .hdr_sig_id = 8, + .flow_sig_id = 245764, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2357] = { - .class_hid = BNXT_ULP_CLASS_HID_03f2, + [2937] = { + .class_hid = BNXT_ULP_CLASS_HID_79410, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 212, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2358] = { - .class_hid = BNXT_ULP_CLASS_HID_1cbe, + [2938] = { + .class_hid = BNXT_ULP_CLASS_HID_78f00, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 212, + .hdr_sig_id = 8, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2359] = { - .class_hid = BNXT_ULP_CLASS_HID_194a, + [2939] = { + .class_hid = BNXT_ULP_CLASS_HID_79dcc, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 213, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2360] = { - .class_hid = BNXT_ULP_CLASS_HID_1216, + [2940] = { + .class_hid = BNXT_ULP_CLASS_HID_7b53c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 214, + .hdr_sig_id = 8, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2361] = { - .class_hid = BNXT_ULP_CLASS_HID_5f3e, + [2941] = { + .class_hid = BNXT_ULP_CLASS_HID_7d0bc, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2362] = { - .class_hid = BNXT_ULP_CLASS_HID_5bca, + [2942] = { + .class_hid = BNXT_ULP_CLASS_HID_7cbac, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245764, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2363] = { - .class_hid = BNXT_ULP_CLASS_HID_5496, + [2943] = { + .class_hid = BNXT_ULP_CLASS_HID_7d678, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2364] = { - .class_hid = BNXT_ULP_CLASS_HID_51a2, + [2944] = { + .class_hid = BNXT_ULP_CLASS_HID_7921c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245764, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2365] = { - .class_hid = BNXT_ULP_CLASS_HID_03e6, + [2945] = { + .class_hid = BNXT_ULP_CLASS_HID_7ba18, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2366] = { - .class_hid = BNXT_ULP_CLASS_HID_1cb2, + [2946] = { + .class_hid = BNXT_ULP_CLASS_HID_7d508, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2367] = { - .class_hid = BNXT_ULP_CLASS_HID_197e, + [2947] = { + .class_hid = BNXT_ULP_CLASS_HID_7a3d4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2368] = { - .class_hid = BNXT_ULP_CLASS_HID_120a, + [2948] = { + .class_hid = BNXT_ULP_CLASS_HID_7dac4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2369] = { - .class_hid = BNXT_ULP_CLASS_HID_238e, + [2949] = { + .class_hid = BNXT_ULP_CLASS_HID_79984, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2370] = { - .class_hid = BNXT_ULP_CLASS_HID_3c5a, + [2950] = { + .class_hid = BNXT_ULP_CLASS_HID_7b0f4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245764, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2371] = { - .class_hid = BNXT_ULP_CLASS_HID_3966, + [2951] = { + .class_hid = BNXT_ULP_CLASS_HID_79f40, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2372] = { - .class_hid = BNXT_ULP_CLASS_HID_3232, + [2952] = { + .class_hid = BNXT_ULP_CLASS_HID_7b6b0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245764, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2373] = { - .class_hid = BNXT_ULP_CLASS_HID_1a2e, + [2953] = { + .class_hid = BNXT_ULP_CLASS_HID_7deac, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2374] = { - .class_hid = BNXT_ULP_CLASS_HID_16fa, + [2954] = { + .class_hid = BNXT_ULP_CLASS_HID_79a50, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2375] = { - .class_hid = BNXT_ULP_CLASS_HID_1386, + [2955] = { + .class_hid = BNXT_ULP_CLASS_HID_7c468, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2376] = { - .class_hid = BNXT_ULP_CLASS_HID_4b86, + [2956] = { + .class_hid = BNXT_ULP_CLASS_HID_7800c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 8, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2377] = { - .class_hid = BNXT_ULP_CLASS_HID_597a, + [2957] = { + .class_hid = BNXT_ULP_CLASS_HID_86c0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2378] = { - .class_hid = BNXT_ULP_CLASS_HID_5206, + [2958] = { + .class_hid = BNXT_ULP_CLASS_HID_a1d0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 9, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2379] = { - .class_hid = BNXT_ULP_CLASS_HID_2ed2, + [2959] = { + .class_hid = BNXT_ULP_CLASS_HID_8c0c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2380] = { - .class_hid = BNXT_ULP_CLASS_HID_2b9e, + [2960] = { + .class_hid = BNXT_ULP_CLASS_HID_a71c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 9, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2381] = { - .class_hid = BNXT_ULP_CLASS_HID_4d8e, + [2961] = { + .class_hid = BNXT_ULP_CLASS_HID_906c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2382] = { - .class_hid = BNXT_ULP_CLASS_HID_465a, + [2962] = { + .class_hid = BNXT_ULP_CLASS_HID_8b7c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 215, + .hdr_sig_id = 9, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2383] = { - .class_hid = BNXT_ULP_CLASS_HID_4366, + [2963] = { + .class_hid = BNXT_ULP_CLASS_HID_99a8, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 216, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2384] = { - .class_hid = BNXT_ULP_CLASS_HID_5c32, + [2964] = { + .class_hid = BNXT_ULP_CLASS_HID_b0b8, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 217, + .hdr_sig_id = 9, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2385] = { - .class_hid = BNXT_ULP_CLASS_HID_0e42, + [2965] = { + .class_hid = BNXT_ULP_CLASS_HID_aab4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 218, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2386] = { - .class_hid = BNXT_ULP_CLASS_HID_0b0e, + [2966] = { + .class_hid = BNXT_ULP_CLASS_HID_c244, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 218, + .hdr_sig_id = 9, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2387] = { - .class_hid = BNXT_ULP_CLASS_HID_07da, + [2967] = { + .class_hid = BNXT_ULP_CLASS_HID_d0f0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 218, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2388] = { - .class_hid = BNXT_ULP_CLASS_HID_00e6, + [2968] = { + .class_hid = BNXT_ULP_CLASS_HID_cb80, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 218, + .hdr_sig_id = 9, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2389] = { - .class_hid = BNXT_ULP_CLASS_HID_47d6, + [2969] = { + .class_hid = BNXT_ULP_CLASS_HID_b4d0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 218, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2390] = { - .class_hid = BNXT_ULP_CLASS_HID_40e2, + [2970] = { + .class_hid = BNXT_ULP_CLASS_HID_afe0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 218, + .hdr_sig_id = 9, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2391] = { - .class_hid = BNXT_ULP_CLASS_HID_5dae, + [2971] = { + .class_hid = BNXT_ULP_CLASS_HID_ba1c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 219, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2392] = { - .class_hid = BNXT_ULP_CLASS_HID_567a, + [2972] = { + .class_hid = BNXT_ULP_CLASS_HID_d52c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 220, + .hdr_sig_id = 9, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2393] = { - .class_hid = BNXT_ULP_CLASS_HID_242e, + [2973] = { + .class_hid = BNXT_ULP_CLASS_HID_48314, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2394] = { - .class_hid = BNXT_ULP_CLASS_HID_20fa, + [2974] = { + .class_hid = BNXT_ULP_CLASS_HID_4ba24, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2395] = { - .class_hid = BNXT_ULP_CLASS_HID_3d86, + [2975] = { + .class_hid = BNXT_ULP_CLASS_HID_48950, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2396] = { - .class_hid = BNXT_ULP_CLASS_HID_3652, + [2976] = { + .class_hid = BNXT_ULP_CLASS_HID_4a060, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2397] = { - .class_hid = BNXT_ULP_CLASS_HID_47ca, + [2977] = { + .class_hid = BNXT_ULP_CLASS_HID_4c86c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2398] = { - .class_hid = BNXT_ULP_CLASS_HID_4096, + [2978] = { + .class_hid = BNXT_ULP_CLASS_HID_48440, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2399] = { - .class_hid = BNXT_ULP_CLASS_HID_5da2, + [2979] = { + .class_hid = BNXT_ULP_CLASS_HID_492fc, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2400] = { - .class_hid = BNXT_ULP_CLASS_HID_566e, + [2980] = { + .class_hid = BNXT_ULP_CLASS_HID_48d8c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2401] = { - .class_hid = BNXT_ULP_CLASS_HID_08be, + [2981] = { + .class_hid = BNXT_ULP_CLASS_HID_4a7f8, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2402] = { - .class_hid = BNXT_ULP_CLASS_HID_054a, + [2982] = { + .class_hid = BNXT_ULP_CLASS_HID_4de88, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2403] = { - .class_hid = BNXT_ULP_CLASS_HID_1e16, + [2983] = { + .class_hid = BNXT_ULP_CLASS_HID_4adc4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2404] = { - .class_hid = BNXT_ULP_CLASS_HID_1b22, + [2984] = { + .class_hid = BNXT_ULP_CLASS_HID_4c4d4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2405] = { - .class_hid = BNXT_ULP_CLASS_HID_5e12, + [2985] = { + .class_hid = BNXT_ULP_CLASS_HID_4b124, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2406] = { - .class_hid = BNXT_ULP_CLASS_HID_5ade, + [2986] = { + .class_hid = BNXT_ULP_CLASS_HID_4a834, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2407] = { - .class_hid = BNXT_ULP_CLASS_HID_57ea, + [2987] = { + .class_hid = BNXT_ULP_CLASS_HID_4b760, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2408] = { - .class_hid = BNXT_ULP_CLASS_HID_50b6, + [2988] = { + .class_hid = BNXT_ULP_CLASS_HID_4ae70, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2409] = { - .class_hid = BNXT_ULP_CLASS_HID_3e6a, + [2989] = { + .class_hid = BNXT_ULP_CLASS_HID_1bcc0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2410] = { - .class_hid = BNXT_ULP_CLASS_HID_3b36, + [2990] = { + .class_hid = BNXT_ULP_CLASS_HID_1d7d0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2411] = { - .class_hid = BNXT_ULP_CLASS_HID_37c2, + [2991] = { + .class_hid = BNXT_ULP_CLASS_HID_1a20c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2412] = { - .class_hid = BNXT_ULP_CLASS_HID_308e, + [2992] = { + .class_hid = BNXT_ULP_CLASS_HID_1dd1c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, + .hdr_sig_id = 9, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2413] = { - .class_hid = BNXT_ULP_CLASS_HID_5e06, + [2993] = { + .class_hid = BNXT_ULP_CLASS_HID_1866c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2414] = { - .class_hid = BNXT_ULP_CLASS_HID_5ad2, + [2994] = { + .class_hid = BNXT_ULP_CLASS_HID_1a17c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 221, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2415] = { - .class_hid = BNXT_ULP_CLASS_HID_579e, + [2995] = { + .class_hid = BNXT_ULP_CLASS_HID_18fa8, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 222, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2416] = { - .class_hid = BNXT_ULP_CLASS_HID_50aa, + [2996] = { + .class_hid = BNXT_ULP_CLASS_HID_1a6b8, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 223, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2417] = { - .class_hid = BNXT_ULP_CLASS_HID_02fa, + [2997] = { + .class_hid = BNXT_ULP_CLASS_HID_1c0b4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 224, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2418] = { - .class_hid = BNXT_ULP_CLASS_HID_1f86, + [2998] = { + .class_hid = BNXT_ULP_CLASS_HID_19c88, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 224, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2419] = { - .class_hid = BNXT_ULP_CLASS_HID_1852, + [2999] = { + .class_hid = BNXT_ULP_CLASS_HID_1c6f0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 224, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2420] = { - .class_hid = BNXT_ULP_CLASS_HID_151e, + [3000] = { + .class_hid = BNXT_ULP_CLASS_HID_182d4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 224, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2421] = { - .class_hid = BNXT_ULP_CLASS_HID_584e, + [3001] = { + .class_hid = BNXT_ULP_CLASS_HID_1aad0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 224, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2422] = { - .class_hid = BNXT_ULP_CLASS_HID_551a, + [3002] = { + .class_hid = BNXT_ULP_CLASS_HID_1c5e0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 224, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2423] = { - .class_hid = BNXT_ULP_CLASS_HID_2e26, + [3003] = { + .class_hid = BNXT_ULP_CLASS_HID_1d01c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 225, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2424] = { - .class_hid = BNXT_ULP_CLASS_HID_2af2, + [3004] = { + .class_hid = BNXT_ULP_CLASS_HID_1cb2c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 226, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2425] = { - .class_hid = BNXT_ULP_CLASS_HID_38a6, + [3005] = { + .class_hid = BNXT_ULP_CLASS_HID_5b914, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2426] = { - .class_hid = BNXT_ULP_CLASS_HID_3572, + [3006] = { + .class_hid = BNXT_ULP_CLASS_HID_5d024, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2427] = { - .class_hid = BNXT_ULP_CLASS_HID_0e3e, + [3007] = { + .class_hid = BNXT_ULP_CLASS_HID_5bf50, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2428] = { - .class_hid = BNXT_ULP_CLASS_HID_0aca, + [3008] = { + .class_hid = BNXT_ULP_CLASS_HID_5d660, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2429] = { - .class_hid = BNXT_ULP_CLASS_HID_5842, + [3009] = { + .class_hid = BNXT_ULP_CLASS_HID_582b0, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2430] = { - .class_hid = BNXT_ULP_CLASS_HID_550e, + [3010] = { + .class_hid = BNXT_ULP_CLASS_HID_5ba40, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2431] = { - .class_hid = BNXT_ULP_CLASS_HID_51da, + [3011] = { + .class_hid = BNXT_ULP_CLASS_HID_588fc, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2432] = { - .class_hid = BNXT_ULP_CLASS_HID_2ae6, + [3012] = { + .class_hid = BNXT_ULP_CLASS_HID_5a38c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2433] = { - .class_hid = BNXT_ULP_CLASS_HID_1d36, + [3013] = { + .class_hid = BNXT_ULP_CLASS_HID_5ddf8, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2434] = { - .class_hid = BNXT_ULP_CLASS_HID_19c2, + [3014] = { + .class_hid = BNXT_ULP_CLASS_HID_599dc, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2435] = { - .class_hid = BNXT_ULP_CLASS_HID_128e, + [3015] = { + .class_hid = BNXT_ULP_CLASS_HID_5c3c4, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2436] = { - .class_hid = BNXT_ULP_CLASS_HID_4a8e, + [3016] = { + .class_hid = BNXT_ULP_CLASS_HID_59f18, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2437] = { - .class_hid = BNXT_ULP_CLASS_HID_528a, + [3017] = { + .class_hid = BNXT_ULP_CLASS_HID_5a724, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2438] = { - .class_hid = BNXT_ULP_CLASS_HID_2f56, + [3018] = { + .class_hid = BNXT_ULP_CLASS_HID_5de34, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2439] = { - .class_hid = BNXT_ULP_CLASS_HID_2862, + [3019] = { + .class_hid = BNXT_ULP_CLASS_HID_5ad60, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2440] = { - .class_hid = BNXT_ULP_CLASS_HID_252e, + [3020] = { + .class_hid = BNXT_ULP_CLASS_HID_5c470, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2441] = { - .class_hid = BNXT_ULP_CLASS_HID_32e2, + [3021] = { + .class_hid = BNXT_ULP_CLASS_HID_cd40, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2442] = { - .class_hid = BNXT_ULP_CLASS_HID_0fae, + [3022] = { + .class_hid = BNXT_ULP_CLASS_HID_e450, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 393220, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2443] = { - .class_hid = BNXT_ULP_CLASS_HID_087a, + [3023] = { + .class_hid = BNXT_ULP_CLASS_HID_f28c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2444] = { - .class_hid = BNXT_ULP_CLASS_HID_0506, + [3024] = { + .class_hid = BNXT_ULP_CLASS_HID_ed9c, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 393220, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2445] = { - .class_hid = BNXT_ULP_CLASS_HID_34b6, + [3025] = { + .class_hid = BNXT_ULP_CLASS_HID_d6ec, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2446] = { - .class_hid = BNXT_ULP_CLASS_HID_3a7a, + [3026] = { + .class_hid = BNXT_ULP_CLASS_HID_f1fc, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 393284, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2447] = { - .class_hid = BNXT_ULP_CLASS_HID_5a62, + [3027] = { + .class_hid = BNXT_ULP_CLASS_HID_dc28, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2448] = { - .class_hid = BNXT_ULP_CLASS_HID_545e, + [3028] = { + .class_hid = BNXT_ULP_CLASS_HID_f738, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 227, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 393284, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2449] = { - .class_hid = BNXT_ULP_CLASS_HID_a73c, + [3029] = { + .class_hid = BNXT_ULP_CLASS_HID_d134, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2450] = { - .class_hid = BNXT_ULP_CLASS_HID_a040, + [3030] = { + .class_hid = BNXT_ULP_CLASS_HID_c8c4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2451] = { - .class_hid = BNXT_ULP_CLASS_HID_1d640, + [3031] = { + .class_hid = BNXT_ULP_CLASS_HID_d770, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2452] = { - .class_hid = BNXT_ULP_CLASS_HID_1dd3c, + [3032] = { + .class_hid = BNXT_ULP_CLASS_HID_d354, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2453] = { - .class_hid = BNXT_ULP_CLASS_HID_cba0, + [3033] = { + .class_hid = BNXT_ULP_CLASS_HID_fb50, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2454] = { - .class_hid = BNXT_ULP_CLASS_HID_c4f4, + [3034] = { + .class_hid = BNXT_ULP_CLASS_HID_d260, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2455] = { - .class_hid = BNXT_ULP_CLASS_HID_19f38, + [3035] = { + .class_hid = BNXT_ULP_CLASS_HID_e09c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2456] = { - .class_hid = BNXT_ULP_CLASS_HID_182f4, + [3036] = { + .class_hid = BNXT_ULP_CLASS_HID_dbac, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2457] = { - .class_hid = BNXT_ULP_CLASS_HID_b098, + [3037] = { + .class_hid = BNXT_ULP_CLASS_HID_4c994, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 227, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2458] = { - .class_hid = BNXT_ULP_CLASS_HID_8dac, + [3038] = { + .class_hid = BNXT_ULP_CLASS_HID_4e0a4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 228, + .hdr_sig_id = 9, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2459] = { - .class_hid = BNXT_ULP_CLASS_HID_1a3ac, + [3039] = { + .class_hid = BNXT_ULP_CLASS_HID_4cfd0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 228, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2460] = { - .class_hid = BNXT_ULP_CLASS_HID_1a698, + [3040] = { + .class_hid = BNXT_ULP_CLASS_HID_4e6e0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2461] = { - .class_hid = BNXT_ULP_CLASS_HID_d50c, + [3041] = { + .class_hid = BNXT_ULP_CLASS_HID_4d330, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2462] = { - .class_hid = BNXT_ULP_CLASS_HID_ae50, + [3042] = { + .class_hid = BNXT_ULP_CLASS_HID_4cac0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2463] = { - .class_hid = BNXT_ULP_CLASS_HID_1c450, + [3043] = { + .class_hid = BNXT_ULP_CLASS_HID_4d97c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2464] = { - .class_hid = BNXT_ULP_CLASS_HID_1cb0c, + [3044] = { + .class_hid = BNXT_ULP_CLASS_HID_4f00c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2465] = { - .class_hid = BNXT_ULP_CLASS_HID_a1f0, + [3045] = { + .class_hid = BNXT_ULP_CLASS_HID_4ea78, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2466] = { - .class_hid = BNXT_ULP_CLASS_HID_ba04, + [3046] = { + .class_hid = BNXT_ULP_CLASS_HID_4c508, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2467] = { - .class_hid = BNXT_ULP_CLASS_HID_1d004, + [3047] = { + .class_hid = BNXT_ULP_CLASS_HID_4d044, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2468] = { - .class_hid = BNXT_ULP_CLASS_HID_1d7f0, + [3048] = { + .class_hid = BNXT_ULP_CLASS_HID_4cb54, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2469] = { - .class_hid = BNXT_ULP_CLASS_HID_c264, + [3049] = { + .class_hid = BNXT_ULP_CLASS_HID_4f7a4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2470] = { - .class_hid = BNXT_ULP_CLASS_HID_dea8, + [3050] = { + .class_hid = BNXT_ULP_CLASS_HID_4eeb4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2471] = { - .class_hid = BNXT_ULP_CLASS_HID_199fc, + [3051] = { + .class_hid = BNXT_ULP_CLASS_HID_4fde0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2472] = { - .class_hid = BNXT_ULP_CLASS_HID_19ca8, + [3052] = { + .class_hid = BNXT_ULP_CLASS_HID_4d4f0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2473] = { - .class_hid = BNXT_ULP_CLASS_HID_8b5c, + [3053] = { + .class_hid = BNXT_ULP_CLASS_HID_1e340, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2474] = { - .class_hid = BNXT_ULP_CLASS_HID_8460, + [3054] = { + .class_hid = BNXT_ULP_CLASS_HID_1da50, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2475] = { - .class_hid = BNXT_ULP_CLASS_HID_1ba60, + [3055] = { + .class_hid = BNXT_ULP_CLASS_HID_1e88c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2476] = { - .class_hid = BNXT_ULP_CLASS_HID_1a15c, + [3056] = { + .class_hid = BNXT_ULP_CLASS_HID_1c39c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2477] = { - .class_hid = BNXT_ULP_CLASS_HID_afc0, + [3057] = { + .class_hid = BNXT_ULP_CLASS_HID_1ccec, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2478] = { - .class_hid = BNXT_ULP_CLASS_HID_a814, + [3058] = { + .class_hid = BNXT_ULP_CLASS_HID_1e7fc, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2479] = { - .class_hid = BNXT_ULP_CLASS_HID_1de14, + [3059] = { + .class_hid = BNXT_ULP_CLASS_HID_1f228, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2480] = { - .class_hid = BNXT_ULP_CLASS_HID_1c5c0, + [3060] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed38, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2481] = { - .class_hid = BNXT_ULP_CLASS_HID_8c2c, + [3061] = { + .class_hid = BNXT_ULP_CLASS_HID_1c734, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2482] = { - .class_hid = BNXT_ULP_CLASS_HID_8970, + [3062] = { + .class_hid = BNXT_ULP_CLASS_HID_1c308, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2483] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf70, + [3063] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd70, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2484] = { - .class_hid = BNXT_ULP_CLASS_HID_1a22c, + [3064] = { + .class_hid = BNXT_ULP_CLASS_HID_1c954, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2485] = { - .class_hid = BNXT_ULP_CLASS_HID_d0d0, + [3065] = { + .class_hid = BNXT_ULP_CLASS_HID_1d150, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2486] = { - .class_hid = BNXT_ULP_CLASS_HID_ade4, + [3066] = { + .class_hid = BNXT_ULP_CLASS_HID_1c860, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2487] = { - .class_hid = BNXT_ULP_CLASS_HID_1c3e4, + [3067] = { + .class_hid = BNXT_ULP_CLASS_HID_1d69c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2488] = { - .class_hid = BNXT_ULP_CLASS_HID_1c6d0, + [3068] = { + .class_hid = BNXT_ULP_CLASS_HID_1d2f0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2489] = { - .class_hid = BNXT_ULP_CLASS_HID_9988, + [3069] = { + .class_hid = BNXT_ULP_CLASS_HID_5ff94, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 229, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2490] = { - .class_hid = BNXT_ULP_CLASS_HID_92dc, + [3070] = { + .class_hid = BNXT_ULP_CLASS_HID_5d6a4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 230, + .hdr_sig_id = 9, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2491] = { - .class_hid = BNXT_ULP_CLASS_HID_188dc, + [3071] = { + .class_hid = BNXT_ULP_CLASS_HID_5e5d0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 230, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2492] = { - .class_hid = BNXT_ULP_CLASS_HID_18f88, + [3072] = { + .class_hid = BNXT_ULP_CLASS_HID_5dce0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2493] = { - .class_hid = BNXT_ULP_CLASS_HID_ba3c, + [3073] = { + .class_hid = BNXT_ULP_CLASS_HID_5c930, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2494] = { - .class_hid = BNXT_ULP_CLASS_HID_b740, + [3074] = { + .class_hid = BNXT_ULP_CLASS_HID_5e0c0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2495] = { - .class_hid = BNXT_ULP_CLASS_HID_1ad40, + [3075] = { + .class_hid = BNXT_ULP_CLASS_HID_5cf7c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2496] = { - .class_hid = BNXT_ULP_CLASS_HID_1d03c, + [3076] = { + .class_hid = BNXT_ULP_CLASS_HID_5e60c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2497] = { - .class_hid = BNXT_ULP_CLASS_HID_86e0, + [3077] = { + .class_hid = BNXT_ULP_CLASS_HID_5c078, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2498] = { - .class_hid = BNXT_ULP_CLASS_HID_8334, + [3078] = { + .class_hid = BNXT_ULP_CLASS_HID_5dc5c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2499] = { - .class_hid = BNXT_ULP_CLASS_HID_1b934, + [3079] = { + .class_hid = BNXT_ULP_CLASS_HID_5c644, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2500] = { - .class_hid = BNXT_ULP_CLASS_HID_1bce0, + [3080] = { + .class_hid = BNXT_ULP_CLASS_HID_5c598, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2501] = { - .class_hid = BNXT_ULP_CLASS_HID_aa94, + [3081] = { + .class_hid = BNXT_ULP_CLASS_HID_5eda4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2502] = { - .class_hid = BNXT_ULP_CLASS_HID_a7d8, + [3082] = { + .class_hid = BNXT_ULP_CLASS_HID_5c4b4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2503] = { - .class_hid = BNXT_ULP_CLASS_HID_1ddd8, + [3083] = { + .class_hid = BNXT_ULP_CLASS_HID_5d3e0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2504] = { - .class_hid = BNXT_ULP_CLASS_HID_1c094, + [3084] = { + .class_hid = BNXT_ULP_CLASS_HID_5caf0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2505] = { - .class_hid = BNXT_ULP_CLASS_HID_904c, + [3085] = { + .class_hid = BNXT_ULP_CLASS_HID_ab80, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2506] = { - .class_hid = BNXT_ULP_CLASS_HID_c84c, + [3086] = { + .class_hid = BNXT_ULP_CLASS_HID_a290, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2507] = { - .class_hid = BNXT_ULP_CLASS_HID_18290, + [3087] = { + .class_hid = BNXT_ULP_CLASS_HID_b1cc, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2508] = { - .class_hid = BNXT_ULP_CLASS_HID_1864c, + [3088] = { + .class_hid = BNXT_ULP_CLASS_HID_a8dc, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2509] = { - .class_hid = BNXT_ULP_CLASS_HID_b4f0, + [3089] = { + .class_hid = BNXT_ULP_CLASS_HID_b52c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2510] = { - .class_hid = BNXT_ULP_CLASS_HID_b104, + [3090] = { + .class_hid = BNXT_ULP_CLASS_HID_ac3c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2511] = { - .class_hid = BNXT_ULP_CLASS_HID_1a704, + [3091] = { + .class_hid = BNXT_ULP_CLASS_HID_bb68, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2512] = { - .class_hid = BNXT_ULP_CLASS_HID_1aaf0, + [3092] = { + .class_hid = BNXT_ULP_CLASS_HID_b278, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, + .hdr_sig_id = 9, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2513] = { - .class_hid = BNXT_ULP_CLASS_HID_80a4, + [3093] = { + .class_hid = BNXT_ULP_CLASS_HID_ac74, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2514] = { - .class_hid = BNXT_ULP_CLASS_HID_9de8, + [3094] = { + .class_hid = BNXT_ULP_CLASS_HID_e704, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655364, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2515] = { - .class_hid = BNXT_ULP_CLASS_HID_1b3e8, + [3095] = { + .class_hid = BNXT_ULP_CLASS_HID_f5b0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2516] = { - .class_hid = BNXT_ULP_CLASS_HID_1b6a4, + [3096] = { + .class_hid = BNXT_ULP_CLASS_HID_b194, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655364, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2517] = { - .class_hid = BNXT_ULP_CLASS_HID_a548, + [3097] = { + .class_hid = BNXT_ULP_CLASS_HID_b990, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2518] = { - .class_hid = BNXT_ULP_CLASS_HID_a19c, + [3098] = { + .class_hid = BNXT_ULP_CLASS_HID_f0a0, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655428, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2519] = { - .class_hid = BNXT_ULP_CLASS_HID_1d79c, + [3099] = { + .class_hid = BNXT_ULP_CLASS_HID_bfdc, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2520] = { - .class_hid = BNXT_ULP_CLASS_HID_1db48, + [3100] = { + .class_hid = BNXT_ULP_CLASS_HID_f6ec, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655428, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2521] = { - .class_hid = BNXT_ULP_CLASS_HID_9a98, + [3101] = { + .class_hid = BNXT_ULP_CLASS_HID_4a4d4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2522] = { - .class_hid = BNXT_ULP_CLASS_HID_97ac, + [3102] = { + .class_hid = BNXT_ULP_CLASS_HID_4bfe4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655364, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2523] = { - .class_hid = BNXT_ULP_CLASS_HID_18dac, + [3103] = { + .class_hid = BNXT_ULP_CLASS_HID_4aa10, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2524] = { - .class_hid = BNXT_ULP_CLASS_HID_1b098, + [3104] = { + .class_hid = BNXT_ULP_CLASS_HID_4a520, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655364, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2525] = { - .class_hid = BNXT_ULP_CLASS_HID_bf0c, + [3105] = { + .class_hid = BNXT_ULP_CLASS_HID_4ed2c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2526] = { - .class_hid = BNXT_ULP_CLASS_HID_b850, + [3106] = { + .class_hid = BNXT_ULP_CLASS_HID_4a900, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655428, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2527] = { - .class_hid = BNXT_ULP_CLASS_HID_1ae50, + [3107] = { + .class_hid = BNXT_ULP_CLASS_HID_4b7bc, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2528] = { - .class_hid = BNXT_ULP_CLASS_HID_1d50c, + [3108] = { + .class_hid = BNXT_ULP_CLASS_HID_4af4c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655428, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2529] = { - .class_hid = BNXT_ULP_CLASS_HID_34f0, + [3109] = { + .class_hid = BNXT_ULP_CLASS_HID_4a8b8, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2530] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3c, + [3110] = { + .class_hid = BNXT_ULP_CLASS_HID_4e048, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655364, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2531] = { - .class_hid = BNXT_ULP_CLASS_HID_3740, + [3111] = { + .class_hid = BNXT_ULP_CLASS_HID_4ae84, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2532] = { - .class_hid = BNXT_ULP_CLASS_HID_5ea0, + [3112] = { + .class_hid = BNXT_ULP_CLASS_HID_4e994, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655364, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2533] = { - .class_hid = BNXT_ULP_CLASS_HID_5bf4, + [3113] = { + .class_hid = BNXT_ULP_CLASS_HID_4b2e4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2534] = { - .class_hid = BNXT_ULP_CLASS_HID_0798, + [3114] = { + .class_hid = BNXT_ULP_CLASS_HID_4adf4, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 231, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655428, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2535] = { - .class_hid = BNXT_ULP_CLASS_HID_00ac, + [3115] = { + .class_hid = BNXT_ULP_CLASS_HID_4b820, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2536] = { - .class_hid = BNXT_ULP_CLASS_HID_280c, + [3116] = { + .class_hid = BNXT_ULP_CLASS_HID_4f330, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655428, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2537] = { - .class_hid = BNXT_ULP_CLASS_HID_2550, + [3117] = { + .class_hid = BNXT_ULP_CLASS_HID_1a180, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2538] = { - .class_hid = BNXT_ULP_CLASS_HID_3104, + [3118] = { + .class_hid = BNXT_ULP_CLASS_HID_1f890, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720900, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2539] = { - .class_hid = BNXT_ULP_CLASS_HID_5964, + [3119] = { + .class_hid = BNXT_ULP_CLASS_HID_1a7cc, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2540] = { - .class_hid = BNXT_ULP_CLASS_HID_55a8, + [3120] = { + .class_hid = BNXT_ULP_CLASS_HID_1fedc, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720900, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2541] = { - .class_hid = BNXT_ULP_CLASS_HID_1e5c, + [3121] = { + .class_hid = BNXT_ULP_CLASS_HID_1ab2c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2542] = { - .class_hid = BNXT_ULP_CLASS_HID_1b60, + [3122] = { + .class_hid = BNXT_ULP_CLASS_HID_1a23c, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720964, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2543] = { - .class_hid = BNXT_ULP_CLASS_HID_22c0, + [3123] = { + .class_hid = BNXT_ULP_CLASS_HID_1b168, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2544] = { - .class_hid = BNXT_ULP_CLASS_HID_3f14, + [3124] = { + .class_hid = BNXT_ULP_CLASS_HID_1a878, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 232, - .flow_pattern_id = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720964, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2545] = { - .class_hid = BNXT_ULP_CLASS_HID_a71c, + [3125] = { + .class_hid = BNXT_ULP_CLASS_HID_1e274, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53521,17 +66457,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2546] = { - .class_hid = BNXT_ULP_CLASS_HID_a8dc, + [3126] = { + .class_hid = BNXT_ULP_CLASS_HID_1be48, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53540,18 +66477,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2547] = { - .class_hid = BNXT_ULP_CLASS_HID_ed9c, + [3127] = { + .class_hid = BNXT_ULP_CLASS_HID_1ebb0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53560,18 +66498,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2548] = { - .class_hid = BNXT_ULP_CLASS_HID_ef5c, + [3128] = { + .class_hid = BNXT_ULP_CLASS_HID_1a794, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53580,19 +66519,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2549] = { - .class_hid = BNXT_ULP_CLASS_HID_a060, + [3129] = { + .class_hid = BNXT_ULP_CLASS_HID_1af90, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53601,18 +66541,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2550] = { - .class_hid = BNXT_ULP_CLASS_HID_a520, + [3130] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6a0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53621,19 +66562,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2551] = { - .class_hid = BNXT_ULP_CLASS_HID_e6e0, + [3131] = { + .class_hid = BNXT_ULP_CLASS_HID_1f5dc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53642,19 +66584,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2552] = { - .class_hid = BNXT_ULP_CLASS_HID_eba0, + [3132] = { + .class_hid = BNXT_ULP_CLASS_HID_1b130, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53663,20 +66606,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2553] = { - .class_hid = BNXT_ULP_CLASS_HID_1d660, + [3133] = { + .class_hid = BNXT_ULP_CLASS_HID_5bad4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53685,19 +66629,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2554] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb20, + [3134] = { + .class_hid = BNXT_ULP_CLASS_HID_5f5e4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53706,20 +66649,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2555] = { - .class_hid = BNXT_ULP_CLASS_HID_1dce0, + [3135] = { + .class_hid = BNXT_ULP_CLASS_HID_5a010, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53728,20 +66670,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2556] = { - .class_hid = BNXT_ULP_CLASS_HID_1e1a0, + [3136] = { + .class_hid = BNXT_ULP_CLASS_HID_5fb20, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53750,21 +66691,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2557] = { - .class_hid = BNXT_ULP_CLASS_HID_1dd1c, + [3137] = { + .class_hid = BNXT_ULP_CLASS_HID_5a470, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53773,18 +66713,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2558] = { - .class_hid = BNXT_ULP_CLASS_HID_1fedc, + [3138] = { + .class_hid = BNXT_ULP_CLASS_HID_5bf00, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53793,19 +66734,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2559] = { - .class_hid = BNXT_ULP_CLASS_HID_1c39c, + [3139] = { + .class_hid = BNXT_ULP_CLASS_HID_5adbc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53814,19 +66756,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2560] = { - .class_hid = BNXT_ULP_CLASS_HID_1e55c, + [3140] = { + .class_hid = BNXT_ULP_CLASS_HID_5a54c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53835,20 +66778,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2561] = { - .class_hid = BNXT_ULP_CLASS_HID_cb80, + [3141] = { + .class_hid = BNXT_ULP_CLASS_HID_5feb8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53857,18 +66801,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2562] = { - .class_hid = BNXT_ULP_CLASS_HID_b194, + [3142] = { + .class_hid = BNXT_ULP_CLASS_HID_5ba9c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53877,19 +66822,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2563] = { - .class_hid = BNXT_ULP_CLASS_HID_d354, + [3143] = { + .class_hid = BNXT_ULP_CLASS_HID_5e484, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53898,19 +66844,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2564] = { - .class_hid = BNXT_ULP_CLASS_HID_f414, + [3144] = { + .class_hid = BNXT_ULP_CLASS_HID_5a0d8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53919,20 +66866,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2565] = { - .class_hid = BNXT_ULP_CLASS_HID_c4d4, + [3145] = { + .class_hid = BNXT_ULP_CLASS_HID_5a8e4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53941,19 +66889,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2566] = { - .class_hid = BNXT_ULP_CLASS_HID_e994, + [3146] = { + .class_hid = BNXT_ULP_CLASS_HID_5e3f4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53962,20 +66911,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2567] = { - .class_hid = BNXT_ULP_CLASS_HID_cb54, + [3147] = { + .class_hid = BNXT_ULP_CLASS_HID_5ae20, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -53984,20 +66934,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2568] = { - .class_hid = BNXT_ULP_CLASS_HID_f158, + [3148] = { + .class_hid = BNXT_ULP_CLASS_HID_5e930, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54006,21 +66957,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2569] = { - .class_hid = BNXT_ULP_CLASS_HID_19f18, + [3149] = { + .class_hid = BNXT_ULP_CLASS_HID_ee00, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54029,20 +66981,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2570] = { - .class_hid = BNXT_ULP_CLASS_HID_1a0d8, + [3150] = { + .class_hid = BNXT_ULP_CLASS_HID_e910, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54051,44 +67000,38 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2571] = { - .class_hid = BNXT_ULP_CLASS_HID_1c598, + [3151] = { + .class_hid = BNXT_ULP_CLASS_HID_f44c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2572] = { - .class_hid = BNXT_ULP_CLASS_HID_1e758, + [3152] = { + .class_hid = BNXT_ULP_CLASS_HID_ef5c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54097,22 +67040,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2573] = { - .class_hid = BNXT_ULP_CLASS_HID_182d4, + [3153] = { + .class_hid = BNXT_ULP_CLASS_HID_fbac, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54121,19 +67061,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2574] = { - .class_hid = BNXT_ULP_CLASS_HID_1a794, + [3154] = { + .class_hid = BNXT_ULP_CLASS_HID_f2bc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54142,20 +67081,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2575] = { - .class_hid = BNXT_ULP_CLASS_HID_1c954, + [3155] = { + .class_hid = BNXT_ULP_CLASS_HID_e1e8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54164,20 +67102,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2576] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea14, + [3156] = { + .class_hid = BNXT_ULP_CLASS_HID_f8f8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54186,21 +67123,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2577] = { - .class_hid = BNXT_ULP_CLASS_HID_b0b8, + [3157] = { + .class_hid = BNXT_ULP_CLASS_HID_f2f4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54209,18 +67145,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2578] = { - .class_hid = BNXT_ULP_CLASS_HID_b278, + [3158] = { + .class_hid = BNXT_ULP_CLASS_HID_ed84, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 232, + .hdr_sig_id = 9, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54229,19 +67165,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2579] = { - .class_hid = BNXT_ULP_CLASS_HID_f738, + [3159] = { + .class_hid = BNXT_ULP_CLASS_HID_f830, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 233, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54250,19 +67186,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2580] = { - .class_hid = BNXT_ULP_CLASS_HID_f8f8, + [3160] = { + .class_hid = BNXT_ULP_CLASS_HID_f414, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 234, + .hdr_sig_id = 9, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54271,20 +67207,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2581] = { - .class_hid = BNXT_ULP_CLASS_HID_8d8c, + [3161] = { + .class_hid = BNXT_ULP_CLASS_HID_fc10, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 235, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54293,19 +67229,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2582] = { - .class_hid = BNXT_ULP_CLASS_HID_af4c, + [3162] = { + .class_hid = BNXT_ULP_CLASS_HID_f720, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 235, + .hdr_sig_id = 9, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54314,20 +67250,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2583] = { - .class_hid = BNXT_ULP_CLASS_HID_f00c, + [3163] = { + .class_hid = BNXT_ULP_CLASS_HID_e25c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 235, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54336,20 +67272,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2584] = { - .class_hid = BNXT_ULP_CLASS_HID_f5cc, + [3164] = { + .class_hid = BNXT_ULP_CLASS_HID_fd6c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 235, + .hdr_sig_id = 9, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54358,21 +67294,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2585] = { - .class_hid = BNXT_ULP_CLASS_HID_1a38c, + [3165] = { + .class_hid = BNXT_ULP_CLASS_HID_4eb54, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 235, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54381,20 +67317,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2586] = { - .class_hid = BNXT_ULP_CLASS_HID_1a54c, + [3166] = { + .class_hid = BNXT_ULP_CLASS_HID_4e264, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 235, + .hdr_sig_id = 9, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54403,21 +67337,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2587] = { - .class_hid = BNXT_ULP_CLASS_HID_1e60c, + [3167] = { + .class_hid = BNXT_ULP_CLASS_HID_4f090, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 236, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54426,21 +67358,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2588] = { - .class_hid = BNXT_ULP_CLASS_HID_1ebcc, + [3168] = { + .class_hid = BNXT_ULP_CLASS_HID_4eba0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 237, + .hdr_sig_id = 9, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54449,22 +67379,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2589] = { - .class_hid = BNXT_ULP_CLASS_HID_1a6b8, + [3169] = { + .class_hid = BNXT_ULP_CLASS_HID_4f4f0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54473,19 +67401,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2590] = { - .class_hid = BNXT_ULP_CLASS_HID_1a878, + [3170] = { + .class_hid = BNXT_ULP_CLASS_HID_4ef80, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54494,20 +67422,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2591] = { - .class_hid = BNXT_ULP_CLASS_HID_1ed38, + [3171] = { + .class_hid = BNXT_ULP_CLASS_HID_4fa3c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54516,20 +67444,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2592] = { - .class_hid = BNXT_ULP_CLASS_HID_1eef8, + [3172] = { + .class_hid = BNXT_ULP_CLASS_HID_4f5cc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54538,21 +67466,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2593] = { - .class_hid = BNXT_ULP_CLASS_HID_d52c, + [3173] = { + .class_hid = BNXT_ULP_CLASS_HID_4ef38, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54561,19 +67489,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2594] = { - .class_hid = BNXT_ULP_CLASS_HID_f6ec, + [3174] = { + .class_hid = BNXT_ULP_CLASS_HID_4e6c8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54582,20 +67510,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2595] = { - .class_hid = BNXT_ULP_CLASS_HID_dbac, + [3175] = { + .class_hid = BNXT_ULP_CLASS_HID_4f504, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54604,20 +67532,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2596] = { - .class_hid = BNXT_ULP_CLASS_HID_fd6c, + [3176] = { + .class_hid = BNXT_ULP_CLASS_HID_4f158, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54626,21 +67554,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2597] = { - .class_hid = BNXT_ULP_CLASS_HID_ae70, + [3177] = { + .class_hid = BNXT_ULP_CLASS_HID_4f964, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54649,20 +67577,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2598] = { - .class_hid = BNXT_ULP_CLASS_HID_f330, + [3178] = { + .class_hid = BNXT_ULP_CLASS_HID_4f074, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54671,21 +67599,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2599] = { - .class_hid = BNXT_ULP_CLASS_HID_d4f0, + [3179] = { + .class_hid = BNXT_ULP_CLASS_HID_4fea0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54694,21 +67622,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2600] = { - .class_hid = BNXT_ULP_CLASS_HID_f9b0, + [3180] = { + .class_hid = BNXT_ULP_CLASS_HID_4f9b0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54717,22 +67645,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2601] = { - .class_hid = BNXT_ULP_CLASS_HID_1c470, + [3181] = { + .class_hid = BNXT_ULP_CLASS_HID_1e400, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54741,21 +67669,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2602] = { - .class_hid = BNXT_ULP_CLASS_HID_1e930, + [3182] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff10, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54764,22 +67689,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2603] = { - .class_hid = BNXT_ULP_CLASS_HID_1caf0, + [3183] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea4c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54788,22 +67710,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2604] = { - .class_hid = BNXT_ULP_CLASS_HID_1f084, + [3184] = { + .class_hid = BNXT_ULP_CLASS_HID_1e55c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54812,23 +67731,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2605] = { - .class_hid = BNXT_ULP_CLASS_HID_1cb2c, + [3185] = { + .class_hid = BNXT_ULP_CLASS_HID_1f1ac, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54837,20 +67753,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2606] = { - .class_hid = BNXT_ULP_CLASS_HID_1b130, + [3186] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8bc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54859,21 +67774,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2607] = { - .class_hid = BNXT_ULP_CLASS_HID_1d2f0, + [3187] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7e8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54882,21 +67796,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2608] = { - .class_hid = BNXT_ULP_CLASS_HID_1f7b0, + [3188] = { + .class_hid = BNXT_ULP_CLASS_HID_1eef8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54905,22 +67818,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2609] = { - .class_hid = BNXT_ULP_CLASS_HID_a1d0, + [3189] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8f4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54929,35 +67841,41 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2610] = { - .class_hid = BNXT_ULP_CLASS_HID_a290, + [3190] = { + .class_hid = BNXT_ULP_CLASS_HID_1e4c8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2611] = { - .class_hid = BNXT_ULP_CLASS_HID_e450, + [3191] = { + .class_hid = BNXT_ULP_CLASS_HID_1f304, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54966,17 +67884,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2612] = { - .class_hid = BNXT_ULP_CLASS_HID_e910, + [3192] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea14, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -54985,18 +67906,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2613] = { - .class_hid = BNXT_ULP_CLASS_HID_ba24, + [3193] = { + .class_hid = BNXT_ULP_CLASS_HID_1f210, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55005,17 +67929,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2614] = { - .class_hid = BNXT_ULP_CLASS_HID_bfe4, + [3194] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed20, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55024,18 +67951,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2615] = { - .class_hid = BNXT_ULP_CLASS_HID_e0a4, + [3195] = { + .class_hid = BNXT_ULP_CLASS_HID_1f85c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55044,18 +67974,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2616] = { - .class_hid = BNXT_ULP_CLASS_HID_e264, + [3196] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7b0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55064,19 +67997,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2617] = { - .class_hid = BNXT_ULP_CLASS_HID_1d024, + [3197] = { + .class_hid = BNXT_ULP_CLASS_HID_5e154, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55085,18 +68021,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2618] = { - .class_hid = BNXT_ULP_CLASS_HID_1f5e4, + [3198] = { + .class_hid = BNXT_ULP_CLASS_HID_5f864, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55105,19 +68042,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2619] = { - .class_hid = BNXT_ULP_CLASS_HID_1d6a4, + [3199] = { + .class_hid = BNXT_ULP_CLASS_HID_5e690, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55126,19 +68064,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2620] = { - .class_hid = BNXT_ULP_CLASS_HID_1f864, + [3200] = { + .class_hid = BNXT_ULP_CLASS_HID_5e1a0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55147,20 +68086,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2621] = { - .class_hid = BNXT_ULP_CLASS_HID_1d7d0, + [3201] = { + .class_hid = BNXT_ULP_CLASS_HID_5eaf0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55169,17 +68109,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2622] = { - .class_hid = BNXT_ULP_CLASS_HID_1f890, + [3202] = { + .class_hid = BNXT_ULP_CLASS_HID_5e580, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55188,18 +68131,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2623] = { - .class_hid = BNXT_ULP_CLASS_HID_1da50, + [3203] = { + .class_hid = BNXT_ULP_CLASS_HID_5f03c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55208,18 +68154,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2624] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff10, + [3204] = { + .class_hid = BNXT_ULP_CLASS_HID_5ebcc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55228,19 +68177,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2625] = { - .class_hid = BNXT_ULP_CLASS_HID_c244, + [3205] = { + .class_hid = BNXT_ULP_CLASS_HID_5e538, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55249,17 +68201,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2626] = { - .class_hid = BNXT_ULP_CLASS_HID_e704, + [3206] = { + .class_hid = BNXT_ULP_CLASS_HID_5e11c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55268,18 +68223,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2627] = { - .class_hid = BNXT_ULP_CLASS_HID_c8c4, + [3207] = { + .class_hid = BNXT_ULP_CLASS_HID_5eb04, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55288,18 +68246,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2628] = { - .class_hid = BNXT_ULP_CLASS_HID_ed84, + [3208] = { + .class_hid = BNXT_ULP_CLASS_HID_5e758, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55308,19 +68269,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2629] = { - .class_hid = BNXT_ULP_CLASS_HID_de88, + [3209] = { + .class_hid = BNXT_ULP_CLASS_HID_5ef64, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55329,18 +68293,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2630] = { - .class_hid = BNXT_ULP_CLASS_HID_e048, + [3210] = { + .class_hid = BNXT_ULP_CLASS_HID_5e674, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55349,19 +68316,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2631] = { - .class_hid = BNXT_ULP_CLASS_HID_c508, + [3211] = { + .class_hid = BNXT_ULP_CLASS_HID_5f4a0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55370,19 +68340,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2632] = { - .class_hid = BNXT_ULP_CLASS_HID_e6c8, + [3212] = { + .class_hid = BNXT_ULP_CLASS_HID_5f084, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 9, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -55391,5188 +68364,5399 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2633] = { - .class_hid = BNXT_ULP_CLASS_HID_199dc, + [3213] = { + .class_hid = BNXT_ULP_CLASS_HID_22998, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2634] = { - .class_hid = BNXT_ULP_CLASS_HID_1ba9c, + [3214] = { + .class_hid = BNXT_ULP_CLASS_HID_24088, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2635] = { - .class_hid = BNXT_ULP_CLASS_HID_1dc5c, + [3215] = { + .class_hid = BNXT_ULP_CLASS_HID_22f54, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2636] = { - .class_hid = BNXT_ULP_CLASS_HID_1e11c, + [3216] = { + .class_hid = BNXT_ULP_CLASS_HID_24644, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2637] = { - .class_hid = BNXT_ULP_CLASS_HID_19c88, + [3217] = { + .class_hid = BNXT_ULP_CLASS_HID_23334, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2638] = { - .class_hid = BNXT_ULP_CLASS_HID_1be48, + [3218] = { + .class_hid = BNXT_ULP_CLASS_HID_22a24, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2639] = { - .class_hid = BNXT_ULP_CLASS_HID_1c308, + [3219] = { + .class_hid = BNXT_ULP_CLASS_HID_238f0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2640] = { - .class_hid = BNXT_ULP_CLASS_HID_1e4c8, + [3220] = { + .class_hid = BNXT_ULP_CLASS_HID_253e0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2641] = { - .class_hid = BNXT_ULP_CLASS_HID_8b7c, + [3221] = { + .class_hid = BNXT_ULP_CLASS_HID_24dec, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2642] = { - .class_hid = BNXT_ULP_CLASS_HID_ac3c, + [3222] = { + .class_hid = BNXT_ULP_CLASS_HID_209d0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2643] = { - .class_hid = BNXT_ULP_CLASS_HID_f1fc, + [3223] = { + .class_hid = BNXT_ULP_CLASS_HID_2149c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2644] = { - .class_hid = BNXT_ULP_CLASS_HID_f2bc, + [3224] = { + .class_hid = BNXT_ULP_CLASS_HID_20f8c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2645] = { - .class_hid = BNXT_ULP_CLASS_HID_8440, + [3225] = { + .class_hid = BNXT_ULP_CLASS_HID_25788, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2646] = { - .class_hid = BNXT_ULP_CLASS_HID_a900, + [3226] = { + .class_hid = BNXT_ULP_CLASS_HID_2136c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2647] = { - .class_hid = BNXT_ULP_CLASS_HID_cac0, + [3227] = { + .class_hid = BNXT_ULP_CLASS_HID_25d44, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2648] = { - .class_hid = BNXT_ULP_CLASS_HID_ef80, + [3228] = { + .class_hid = BNXT_ULP_CLASS_HID_21928, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2649] = { - .class_hid = BNXT_ULP_CLASS_HID_1ba40, + [3229] = { + .class_hid = BNXT_ULP_CLASS_HID_234a8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2650] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf00, + [3230] = { + .class_hid = BNXT_ULP_CLASS_HID_22fd8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2651] = { - .class_hid = BNXT_ULP_CLASS_HID_1e0c0, + [3231] = { + .class_hid = BNXT_ULP_CLASS_HID_23a64, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2652] = { - .class_hid = BNXT_ULP_CLASS_HID_1e580, + [3232] = { + .class_hid = BNXT_ULP_CLASS_HID_25594, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2653] = { - .class_hid = BNXT_ULP_CLASS_HID_1a17c, + [3233] = { + .class_hid = BNXT_ULP_CLASS_HID_21e44, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2654] = { - .class_hid = BNXT_ULP_CLASS_HID_1a23c, + [3234] = { + .class_hid = BNXT_ULP_CLASS_HID_23974, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2655] = { - .class_hid = BNXT_ULP_CLASS_HID_1e7fc, + [3235] = { + .class_hid = BNXT_ULP_CLASS_HID_20400, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2656] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8bc, + [3236] = { + .class_hid = BNXT_ULP_CLASS_HID_23f30, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2657] = { - .class_hid = BNXT_ULP_CLASS_HID_afe0, + [3237] = { + .class_hid = BNXT_ULP_CLASS_HID_2593c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2658] = { - .class_hid = BNXT_ULP_CLASS_HID_f0a0, + [3238] = { + .class_hid = BNXT_ULP_CLASS_HID_214e0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2659] = { - .class_hid = BNXT_ULP_CLASS_HID_d260, + [3239] = { + .class_hid = BNXT_ULP_CLASS_HID_25ef8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2660] = { - .class_hid = BNXT_ULP_CLASS_HID_f720, + [3240] = { + .class_hid = BNXT_ULP_CLASS_HID_21adc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2661] = { - .class_hid = BNXT_ULP_CLASS_HID_a834, + [3241] = { + .class_hid = BNXT_ULP_CLASS_HID_222d8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2662] = { - .class_hid = BNXT_ULP_CLASS_HID_adf4, + [3242] = { + .class_hid = BNXT_ULP_CLASS_HID_25dc8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2663] = { - .class_hid = BNXT_ULP_CLASS_HID_eeb4, + [3243] = { + .class_hid = BNXT_ULP_CLASS_HID_22894, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2664] = { - .class_hid = BNXT_ULP_CLASS_HID_f074, + [3244] = { + .class_hid = BNXT_ULP_CLASS_HID_24384, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2665] = { - .class_hid = BNXT_ULP_CLASS_HID_1de34, + [3245] = { + .class_hid = BNXT_ULP_CLASS_HID_6224c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2666] = { - .class_hid = BNXT_ULP_CLASS_HID_1e3f4, + [3246] = { + .class_hid = BNXT_ULP_CLASS_HID_65d7c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2667] = { - .class_hid = BNXT_ULP_CLASS_HID_1c4b4, + [3247] = { + .class_hid = BNXT_ULP_CLASS_HID_62808, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2668] = { - .class_hid = BNXT_ULP_CLASS_HID_1e674, + [3248] = { + .class_hid = BNXT_ULP_CLASS_HID_64338, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2669] = { - .class_hid = BNXT_ULP_CLASS_HID_1c5e0, + [3249] = { + .class_hid = BNXT_ULP_CLASS_HID_60fe8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2670] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6a0, + [3250] = { + .class_hid = BNXT_ULP_CLASS_HID_62718, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2671] = { - .class_hid = BNXT_ULP_CLASS_HID_1c860, + [3251] = { + .class_hid = BNXT_ULP_CLASS_HID_635a4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2672] = { - .class_hid = BNXT_ULP_CLASS_HID_1ed20, + [3252] = { + .class_hid = BNXT_ULP_CLASS_HID_62cd4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2673] = { - .class_hid = BNXT_ULP_CLASS_HID_8c0c, + [3253] = { + .class_hid = BNXT_ULP_CLASS_HID_646a0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2674] = { - .class_hid = BNXT_ULP_CLASS_HID_b1cc, + [3254] = { + .class_hid = BNXT_ULP_CLASS_HID_60284, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2675] = { - .class_hid = BNXT_ULP_CLASS_HID_f28c, + [3255] = { + .class_hid = BNXT_ULP_CLASS_HID_61150, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2676] = { - .class_hid = BNXT_ULP_CLASS_HID_f44c, + [3256] = { + .class_hid = BNXT_ULP_CLASS_HID_60840, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2677] = { - .class_hid = BNXT_ULP_CLASS_HID_8950, + [3257] = { + .class_hid = BNXT_ULP_CLASS_HID_6507c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2678] = { - .class_hid = BNXT_ULP_CLASS_HID_aa10, + [3258] = { + .class_hid = BNXT_ULP_CLASS_HID_64b6c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2679] = { - .class_hid = BNXT_ULP_CLASS_HID_cfd0, + [3259] = { + .class_hid = BNXT_ULP_CLASS_HID_65638, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2680] = { - .class_hid = BNXT_ULP_CLASS_HID_f090, + [3260] = { + .class_hid = BNXT_ULP_CLASS_HID_6121c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2681] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf50, + [3261] = { + .class_hid = BNXT_ULP_CLASS_HID_6319c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2682] = { - .class_hid = BNXT_ULP_CLASS_HID_1a010, + [3262] = { + .class_hid = BNXT_ULP_CLASS_HID_6288c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2683] = { - .class_hid = BNXT_ULP_CLASS_HID_1e5d0, + [3263] = { + .class_hid = BNXT_ULP_CLASS_HID_63758, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2684] = { - .class_hid = BNXT_ULP_CLASS_HID_1e690, + [3264] = { + .class_hid = BNXT_ULP_CLASS_HID_62e48, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2685] = { - .class_hid = BNXT_ULP_CLASS_HID_1a20c, + [3265] = { + .class_hid = BNXT_ULP_CLASS_HID_61b38, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2686] = { - .class_hid = BNXT_ULP_CLASS_HID_1a7cc, + [3266] = { + .class_hid = BNXT_ULP_CLASS_HID_63228, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2687] = { - .class_hid = BNXT_ULP_CLASS_HID_1e88c, + [3267] = { + .class_hid = BNXT_ULP_CLASS_HID_600f4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2688] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea4c, + [3268] = { + .class_hid = BNXT_ULP_CLASS_HID_63be4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2689] = { - .class_hid = BNXT_ULP_CLASS_HID_d0f0, + [3269] = { + .class_hid = BNXT_ULP_CLASS_HID_655f0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2690] = { - .class_hid = BNXT_ULP_CLASS_HID_f5b0, + [3270] = { + .class_hid = BNXT_ULP_CLASS_HID_611d4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2691] = { - .class_hid = BNXT_ULP_CLASS_HID_d770, + [3271] = { + .class_hid = BNXT_ULP_CLASS_HID_65bac, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2692] = { - .class_hid = BNXT_ULP_CLASS_HID_f830, + [3272] = { + .class_hid = BNXT_ULP_CLASS_HID_61790, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49156, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2693] = { - .class_hid = BNXT_ULP_CLASS_HID_adc4, + [3273] = { + .class_hid = BNXT_ULP_CLASS_HID_63f8c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2694] = { - .class_hid = BNXT_ULP_CLASS_HID_ae84, + [3274] = { + .class_hid = BNXT_ULP_CLASS_HID_656bc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2695] = { - .class_hid = BNXT_ULP_CLASS_HID_d044, + [3275] = { + .class_hid = BNXT_ULP_CLASS_HID_62548, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2696] = { - .class_hid = BNXT_ULP_CLASS_HID_f504, + [3276] = { + .class_hid = BNXT_ULP_CLASS_HID_65c78, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 49220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2697] = { - .class_hid = BNXT_ULP_CLASS_HID_1c3c4, + [3277] = { + .class_hid = BNXT_ULP_CLASS_HID_35f98, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2698] = { - .class_hid = BNXT_ULP_CLASS_HID_1e484, + [3278] = { + .class_hid = BNXT_ULP_CLASS_HID_31b7c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98308, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2699] = { - .class_hid = BNXT_ULP_CLASS_HID_1c644, + [3279] = { + .class_hid = BNXT_ULP_CLASS_HID_34554, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2700] = { - .class_hid = BNXT_ULP_CLASS_HID_1eb04, + [3280] = { + .class_hid = BNXT_ULP_CLASS_HID_30138, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98308, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2701] = { - .class_hid = BNXT_ULP_CLASS_HID_1c6f0, + [3281] = { + .class_hid = BNXT_ULP_CLASS_HID_32934, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2702] = { - .class_hid = BNXT_ULP_CLASS_HID_1ebb0, + [3282] = { + .class_hid = BNXT_ULP_CLASS_HID_34024, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98372, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2703] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd70, + [3283] = { + .class_hid = BNXT_ULP_CLASS_HID_32ef0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2704] = { - .class_hid = BNXT_ULP_CLASS_HID_1f304, + [3284] = { + .class_hid = BNXT_ULP_CLASS_HID_349e0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98372, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2705] = { - .class_hid = BNXT_ULP_CLASS_HID_99a8, + [3285] = { + .class_hid = BNXT_ULP_CLASS_HID_304a0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2706] = { - .class_hid = BNXT_ULP_CLASS_HID_bb68, + [3286] = { + .class_hid = BNXT_ULP_CLASS_HID_33fd0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 238, + .hdr_sig_id = 10, + .flow_sig_id = 98308, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2707] = { - .class_hid = BNXT_ULP_CLASS_HID_dc28, + [3287] = { + .class_hid = BNXT_ULP_CLASS_HID_30a9c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 239, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2708] = { - .class_hid = BNXT_ULP_CLASS_HID_e1e8, + [3288] = { + .class_hid = BNXT_ULP_CLASS_HID_3258c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 240, + .hdr_sig_id = 10, + .flow_sig_id = 98308, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2709] = { - .class_hid = BNXT_ULP_CLASS_HID_92fc, + [3289] = { + .class_hid = BNXT_ULP_CLASS_HID_34d88, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 241, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2710] = { - .class_hid = BNXT_ULP_CLASS_HID_b7bc, + [3290] = { + .class_hid = BNXT_ULP_CLASS_HID_3096c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 241, + .hdr_sig_id = 10, + .flow_sig_id = 98372, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2711] = { - .class_hid = BNXT_ULP_CLASS_HID_d97c, + [3291] = { + .class_hid = BNXT_ULP_CLASS_HID_31438, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 241, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2712] = { - .class_hid = BNXT_ULP_CLASS_HID_fa3c, + [3292] = { + .class_hid = BNXT_ULP_CLASS_HID_30f28, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 241, + .hdr_sig_id = 10, + .flow_sig_id = 98372, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2713] = { - .class_hid = BNXT_ULP_CLASS_HID_188fc, + [3293] = { + .class_hid = BNXT_ULP_CLASS_HID_32aa8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 241, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2714] = { - .class_hid = BNXT_ULP_CLASS_HID_1adbc, + [3294] = { + .class_hid = BNXT_ULP_CLASS_HID_345d8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 241, + .hdr_sig_id = 10, + .flow_sig_id = 98308, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2715] = { - .class_hid = BNXT_ULP_CLASS_HID_1cf7c, + [3295] = { + .class_hid = BNXT_ULP_CLASS_HID_35064, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 242, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2716] = { - .class_hid = BNXT_ULP_CLASS_HID_1f03c, + [3296] = { + .class_hid = BNXT_ULP_CLASS_HID_34b94, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 243, + .hdr_sig_id = 10, + .flow_sig_id = 98308, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2717] = { - .class_hid = BNXT_ULP_CLASS_HID_18fa8, + [3297] = { + .class_hid = BNXT_ULP_CLASS_HID_33444, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2718] = { - .class_hid = BNXT_ULP_CLASS_HID_1b168, + [3298] = { + .class_hid = BNXT_ULP_CLASS_HID_32f74, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98372, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2719] = { - .class_hid = BNXT_ULP_CLASS_HID_1f228, + [3299] = { + .class_hid = BNXT_ULP_CLASS_HID_33a00, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2720] = { - .class_hid = BNXT_ULP_CLASS_HID_1f7e8, + [3300] = { + .class_hid = BNXT_ULP_CLASS_HID_35530, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98372, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2721] = { - .class_hid = BNXT_ULP_CLASS_HID_ba1c, + [3301] = { + .class_hid = BNXT_ULP_CLASS_HID_313f0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2722] = { - .class_hid = BNXT_ULP_CLASS_HID_bfdc, + [3302] = { + .class_hid = BNXT_ULP_CLASS_HID_30ae0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98308, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2723] = { - .class_hid = BNXT_ULP_CLASS_HID_e09c, + [3303] = { + .class_hid = BNXT_ULP_CLASS_HID_319ac, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2724] = { - .class_hid = BNXT_ULP_CLASS_HID_e25c, + [3304] = { + .class_hid = BNXT_ULP_CLASS_HID_330dc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98308, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2725] = { - .class_hid = BNXT_ULP_CLASS_HID_b760, + [3305] = { + .class_hid = BNXT_ULP_CLASS_HID_358d8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2726] = { - .class_hid = BNXT_ULP_CLASS_HID_b820, + [3306] = { + .class_hid = BNXT_ULP_CLASS_HID_314bc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98372, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2727] = { - .class_hid = BNXT_ULP_CLASS_HID_fde0, + [3307] = { + .class_hid = BNXT_ULP_CLASS_HID_35e94, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2728] = { - .class_hid = BNXT_ULP_CLASS_HID_fea0, + [3308] = { + .class_hid = BNXT_ULP_CLASS_HID_31a78, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 98372, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2729] = { - .class_hid = BNXT_ULP_CLASS_HID_1ad60, + [3309] = { + .class_hid = BNXT_ULP_CLASS_HID_7584c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2730] = { - .class_hid = BNXT_ULP_CLASS_HID_1ae20, + [3310] = { + .class_hid = BNXT_ULP_CLASS_HID_71430, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2731] = { - .class_hid = BNXT_ULP_CLASS_HID_1d3e0, + [3311] = { + .class_hid = BNXT_ULP_CLASS_HID_75e08, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2732] = { - .class_hid = BNXT_ULP_CLASS_HID_1f4a0, + [3312] = { + .class_hid = BNXT_ULP_CLASS_HID_71dec, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2733] = { - .class_hid = BNXT_ULP_CLASS_HID_1d01c, + [3313] = { + .class_hid = BNXT_ULP_CLASS_HID_725e8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2734] = { - .class_hid = BNXT_ULP_CLASS_HID_1f5dc, + [3314] = { + .class_hid = BNXT_ULP_CLASS_HID_75d18, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2735] = { - .class_hid = BNXT_ULP_CLASS_HID_1d69c, + [3315] = { + .class_hid = BNXT_ULP_CLASS_HID_72ba4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2736] = { - .class_hid = BNXT_ULP_CLASS_HID_1f85c, + [3316] = { + .class_hid = BNXT_ULP_CLASS_HID_742d4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2737] = { - .class_hid = BNXT_ULP_CLASS_HID_86c0, + [3317] = { + .class_hid = BNXT_ULP_CLASS_HID_70194, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2738] = { - .class_hid = BNXT_ULP_CLASS_HID_ab80, + [3318] = { + .class_hid = BNXT_ULP_CLASS_HID_73884, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2739] = { - .class_hid = BNXT_ULP_CLASS_HID_cd40, + [3319] = { + .class_hid = BNXT_ULP_CLASS_HID_70750, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2740] = { - .class_hid = BNXT_ULP_CLASS_HID_ee00, + [3320] = { + .class_hid = BNXT_ULP_CLASS_HID_73e40, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2741] = { - .class_hid = BNXT_ULP_CLASS_HID_8314, + [3321] = { + .class_hid = BNXT_ULP_CLASS_HID_7467c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2742] = { - .class_hid = BNXT_ULP_CLASS_HID_a4d4, + [3322] = { + .class_hid = BNXT_ULP_CLASS_HID_70220, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2743] = { - .class_hid = BNXT_ULP_CLASS_HID_c994, + [3323] = { + .class_hid = BNXT_ULP_CLASS_HID_710ec, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2744] = { - .class_hid = BNXT_ULP_CLASS_HID_eb54, + [3324] = { + .class_hid = BNXT_ULP_CLASS_HID_7081c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2745] = { - .class_hid = BNXT_ULP_CLASS_HID_1b914, + [3325] = { + .class_hid = BNXT_ULP_CLASS_HID_7279c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2746] = { - .class_hid = BNXT_ULP_CLASS_HID_1bad4, + [3326] = { + .class_hid = BNXT_ULP_CLASS_HID_75e8c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2747] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff94, + [3327] = { + .class_hid = BNXT_ULP_CLASS_HID_72d58, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2748] = { - .class_hid = BNXT_ULP_CLASS_HID_1e154, + [3328] = { + .class_hid = BNXT_ULP_CLASS_HID_74448, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2749] = { - .class_hid = BNXT_ULP_CLASS_HID_1bcc0, + [3329] = { + .class_hid = BNXT_ULP_CLASS_HID_73138, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2750] = { - .class_hid = BNXT_ULP_CLASS_HID_1a180, + [3330] = { + .class_hid = BNXT_ULP_CLASS_HID_72828, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2751] = { - .class_hid = BNXT_ULP_CLASS_HID_1e340, + [3331] = { + .class_hid = BNXT_ULP_CLASS_HID_736f4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2752] = { - .class_hid = BNXT_ULP_CLASS_HID_1e400, + [3332] = { + .class_hid = BNXT_ULP_CLASS_HID_751e4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2753] = { - .class_hid = BNXT_ULP_CLASS_HID_aab4, + [3333] = { + .class_hid = BNXT_ULP_CLASS_HID_74bf0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2754] = { - .class_hid = BNXT_ULP_CLASS_HID_ac74, + [3334] = { + .class_hid = BNXT_ULP_CLASS_HID_707d4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2755] = { - .class_hid = BNXT_ULP_CLASS_HID_d134, + [3335] = { + .class_hid = BNXT_ULP_CLASS_HID_71260, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2756] = { - .class_hid = BNXT_ULP_CLASS_HID_f2f4, + [3336] = { + .class_hid = BNXT_ULP_CLASS_HID_70d90, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114692, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2757] = { - .class_hid = BNXT_ULP_CLASS_HID_a7f8, + [3337] = { + .class_hid = BNXT_ULP_CLASS_HID_7558c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2758] = { - .class_hid = BNXT_ULP_CLASS_HID_a8b8, + [3338] = { + .class_hid = BNXT_ULP_CLASS_HID_71170, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2759] = { - .class_hid = BNXT_ULP_CLASS_HID_ea78, + [3339] = { + .class_hid = BNXT_ULP_CLASS_HID_75b48, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2760] = { - .class_hid = BNXT_ULP_CLASS_HID_ef38, + [3340] = { + .class_hid = BNXT_ULP_CLASS_HID_7172c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 114756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2761] = { - .class_hid = BNXT_ULP_CLASS_HID_1ddf8, + [3341] = { + .class_hid = BNXT_ULP_CLASS_HID_2d298, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2762] = { - .class_hid = BNXT_ULP_CLASS_HID_1feb8, + [3342] = { + .class_hid = BNXT_ULP_CLASS_HID_2cd88, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2763] = { - .class_hid = BNXT_ULP_CLASS_HID_1c078, + [3343] = { + .class_hid = BNXT_ULP_CLASS_HID_2d854, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2764] = { - .class_hid = BNXT_ULP_CLASS_HID_1e538, + [3344] = { + .class_hid = BNXT_ULP_CLASS_HID_29438, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2765] = { - .class_hid = BNXT_ULP_CLASS_HID_1c0b4, + [3345] = { + .class_hid = BNXT_ULP_CLASS_HID_2bc34, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2766] = { - .class_hid = BNXT_ULP_CLASS_HID_1e274, + [3346] = { + .class_hid = BNXT_ULP_CLASS_HID_2d724, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2767] = { - .class_hid = BNXT_ULP_CLASS_HID_1c734, + [3347] = { + .class_hid = BNXT_ULP_CLASS_HID_2a5f0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2768] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8f4, + [3348] = { + .class_hid = BNXT_ULP_CLASS_HID_2dce0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2769] = { - .class_hid = BNXT_ULP_CLASS_HID_906c, + [3349] = { + .class_hid = BNXT_ULP_CLASS_HID_29ba0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2770] = { - .class_hid = BNXT_ULP_CLASS_HID_b52c, + [3350] = { + .class_hid = BNXT_ULP_CLASS_HID_2b2d0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2771] = { - .class_hid = BNXT_ULP_CLASS_HID_d6ec, + [3351] = { + .class_hid = BNXT_ULP_CLASS_HID_2819c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2772] = { - .class_hid = BNXT_ULP_CLASS_HID_fbac, + [3352] = { + .class_hid = BNXT_ULP_CLASS_HID_2b88c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2773] = { - .class_hid = BNXT_ULP_CLASS_HID_c86c, + [3353] = { + .class_hid = BNXT_ULP_CLASS_HID_2c088, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2774] = { - .class_hid = BNXT_ULP_CLASS_HID_ed2c, + [3354] = { + .class_hid = BNXT_ULP_CLASS_HID_29c6c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2775] = { - .class_hid = BNXT_ULP_CLASS_HID_d330, + [3355] = { + .class_hid = BNXT_ULP_CLASS_HID_2c644, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2776] = { - .class_hid = BNXT_ULP_CLASS_HID_f4f0, + [3356] = { + .class_hid = BNXT_ULP_CLASS_HID_28228, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2777] = { - .class_hid = BNXT_ULP_CLASS_HID_182b0, + [3357] = { + .class_hid = BNXT_ULP_CLASS_HID_2a1a8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2778] = { - .class_hid = BNXT_ULP_CLASS_HID_1a470, + [3358] = { + .class_hid = BNXT_ULP_CLASS_HID_2d8d8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2779] = { - .class_hid = BNXT_ULP_CLASS_HID_1c930, + [3359] = { + .class_hid = BNXT_ULP_CLASS_HID_2a764, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2780] = { - .class_hid = BNXT_ULP_CLASS_HID_1eaf0, + [3360] = { + .class_hid = BNXT_ULP_CLASS_HID_2de94, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2781] = { - .class_hid = BNXT_ULP_CLASS_HID_1866c, + [3361] = { + .class_hid = BNXT_ULP_CLASS_HID_28b44, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2782] = { - .class_hid = BNXT_ULP_CLASS_HID_1ab2c, + [3362] = { + .class_hid = BNXT_ULP_CLASS_HID_2a274, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2783] = { - .class_hid = BNXT_ULP_CLASS_HID_1ccec, + [3363] = { + .class_hid = BNXT_ULP_CLASS_HID_2b100, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2784] = { - .class_hid = BNXT_ULP_CLASS_HID_1f1ac, + [3364] = { + .class_hid = BNXT_ULP_CLASS_HID_2a830, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2785] = { - .class_hid = BNXT_ULP_CLASS_HID_b4d0, + [3365] = { + .class_hid = BNXT_ULP_CLASS_HID_2c23c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2786] = { - .class_hid = BNXT_ULP_CLASS_HID_b990, + [3366] = { + .class_hid = BNXT_ULP_CLASS_HID_281e0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2787] = { - .class_hid = BNXT_ULP_CLASS_HID_fb50, + [3367] = { + .class_hid = BNXT_ULP_CLASS_HID_2cbf8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2788] = { - .class_hid = BNXT_ULP_CLASS_HID_fc10, + [3368] = { + .class_hid = BNXT_ULP_CLASS_HID_287dc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163844, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2789] = { - .class_hid = BNXT_ULP_CLASS_HID_b124, + [3369] = { + .class_hid = BNXT_ULP_CLASS_HID_2afd8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2790] = { - .class_hid = BNXT_ULP_CLASS_HID_b2e4, + [3370] = { + .class_hid = BNXT_ULP_CLASS_HID_2c6c8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2791] = { - .class_hid = BNXT_ULP_CLASS_HID_f7a4, + [3371] = { + .class_hid = BNXT_ULP_CLASS_HID_2d594, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2792] = { - .class_hid = BNXT_ULP_CLASS_HID_f964, + [3372] = { + .class_hid = BNXT_ULP_CLASS_HID_29178, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 163908, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2793] = { - .class_hid = BNXT_ULP_CLASS_HID_1a724, + [3373] = { + .class_hid = BNXT_ULP_CLASS_HID_6af4c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2794] = { - .class_hid = BNXT_ULP_CLASS_HID_1a8e4, + [3374] = { + .class_hid = BNXT_ULP_CLASS_HID_6c67c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2795] = { - .class_hid = BNXT_ULP_CLASS_HID_1eda4, + [3375] = { + .class_hid = BNXT_ULP_CLASS_HID_6d508, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2796] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef64, + [3376] = { + .class_hid = BNXT_ULP_CLASS_HID_690ec, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 180228, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2797] = { - .class_hid = BNXT_ULP_CLASS_HID_1aad0, + [3377] = { + .class_hid = BNXT_ULP_CLASS_HID_6b8e8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2798] = { - .class_hid = BNXT_ULP_CLASS_HID_1af90, + [3378] = { + .class_hid = BNXT_ULP_CLASS_HID_6d018, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2799] = { - .class_hid = BNXT_ULP_CLASS_HID_1d150, + [3379] = { + .class_hid = BNXT_ULP_CLASS_HID_6bea4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2800] = { - .class_hid = BNXT_ULP_CLASS_HID_1f210, + [3380] = { + .class_hid = BNXT_ULP_CLASS_HID_6d9d4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 180292, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2801] = { - .class_hid = BNXT_ULP_CLASS_HID_8084, + [3381] = { + .class_hid = BNXT_ULP_CLASS_HID_69494, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2802] = { - .class_hid = BNXT_ULP_CLASS_HID_a244, + [3382] = { + .class_hid = BNXT_ULP_CLASS_HID_68f84, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180228, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2803] = { - .class_hid = BNXT_ULP_CLASS_HID_c704, + [3383] = { + .class_hid = BNXT_ULP_CLASS_HID_69a50, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2804] = { - .class_hid = BNXT_ULP_CLASS_HID_e8c4, + [3384] = { + .class_hid = BNXT_ULP_CLASS_HID_6b540, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180228, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2805] = { - .class_hid = BNXT_ULP_CLASS_HID_9dc8, + [3385] = { + .class_hid = BNXT_ULP_CLASS_HID_6dd7c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2806] = { - .class_hid = BNXT_ULP_CLASS_HID_be88, + [3386] = { + .class_hid = BNXT_ULP_CLASS_HID_69920, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2807] = { - .class_hid = BNXT_ULP_CLASS_HID_c048, + [3387] = { + .class_hid = BNXT_ULP_CLASS_HID_6c338, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2808] = { - .class_hid = BNXT_ULP_CLASS_HID_e508, + [3388] = { + .class_hid = BNXT_ULP_CLASS_HID_69f1c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2809] = { - .class_hid = BNXT_ULP_CLASS_HID_1b3c8, + [3389] = { + .class_hid = BNXT_ULP_CLASS_HID_6ba9c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2810] = { - .class_hid = BNXT_ULP_CLASS_HID_1b488, + [3390] = { + .class_hid = BNXT_ULP_CLASS_HID_6d58c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180228, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2811] = { - .class_hid = BNXT_ULP_CLASS_HID_1f648, + [3391] = { + .class_hid = BNXT_ULP_CLASS_HID_6a058, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2812] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb08, + [3392] = { + .class_hid = BNXT_ULP_CLASS_HID_6db48, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180228, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2813] = { - .class_hid = BNXT_ULP_CLASS_HID_1b684, + [3393] = { + .class_hid = BNXT_ULP_CLASS_HID_68438, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2814] = { - .class_hid = BNXT_ULP_CLASS_HID_1b844, + [3394] = { + .class_hid = BNXT_ULP_CLASS_HID_6bf28, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2815] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd04, + [3395] = { + .class_hid = BNXT_ULP_CLASS_HID_68df4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2816] = { - .class_hid = BNXT_ULP_CLASS_HID_1fec4, + [3396] = { + .class_hid = BNXT_ULP_CLASS_HID_6a4e4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2817] = { - .class_hid = BNXT_ULP_CLASS_HID_a568, + [3397] = { + .class_hid = BNXT_ULP_CLASS_HID_6def0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2818] = { - .class_hid = BNXT_ULP_CLASS_HID_a628, + [3398] = { + .class_hid = BNXT_ULP_CLASS_HID_69ad4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180228, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2819] = { - .class_hid = BNXT_ULP_CLASS_HID_ebe8, + [3399] = { + .class_hid = BNXT_ULP_CLASS_HID_6c4ac, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2820] = { - .class_hid = BNXT_ULP_CLASS_HID_eca8, + [3400] = { + .class_hid = BNXT_ULP_CLASS_HID_68090, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180228, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2821] = { - .class_hid = BNXT_ULP_CLASS_HID_a1bc, + [3401] = { + .class_hid = BNXT_ULP_CLASS_HID_6a88c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2822] = { - .class_hid = BNXT_ULP_CLASS_HID_a37c, + [3402] = { + .class_hid = BNXT_ULP_CLASS_HID_6c3bc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2823] = { - .class_hid = BNXT_ULP_CLASS_HID_e43c, + [3403] = { + .class_hid = BNXT_ULP_CLASS_HID_6ae48, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2824] = { - .class_hid = BNXT_ULP_CLASS_HID_e9fc, + [3404] = { + .class_hid = BNXT_ULP_CLASS_HID_6c978, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2825] = { - .class_hid = BNXT_ULP_CLASS_HID_1d7bc, + [3405] = { + .class_hid = BNXT_ULP_CLASS_HID_3c898, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2826] = { - .class_hid = BNXT_ULP_CLASS_HID_1f97c, + [3406] = { + .class_hid = BNXT_ULP_CLASS_HID_3847c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2827] = { - .class_hid = BNXT_ULP_CLASS_HID_1da3c, + [3407] = { + .class_hid = BNXT_ULP_CLASS_HID_39308, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2828] = { - .class_hid = BNXT_ULP_CLASS_HID_1fffc, + [3408] = { + .class_hid = BNXT_ULP_CLASS_HID_38a38, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2829] = { - .class_hid = BNXT_ULP_CLASS_HID_1db68, + [3409] = { + .class_hid = BNXT_ULP_CLASS_HID_3d234, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2830] = { - .class_hid = BNXT_ULP_CLASS_HID_1fc28, + [3410] = { + .class_hid = BNXT_ULP_CLASS_HID_3cd24, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2831] = { - .class_hid = BNXT_ULP_CLASS_HID_1c1e8, + [3411] = { + .class_hid = BNXT_ULP_CLASS_HID_3dbf0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2832] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2a8, + [3412] = { + .class_hid = BNXT_ULP_CLASS_HID_397d4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2833] = { - .class_hid = BNXT_ULP_CLASS_HID_9ab8, + [3413] = { + .class_hid = BNXT_ULP_CLASS_HID_3b1a0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2834] = { - .class_hid = BNXT_ULP_CLASS_HID_bc78, + [3414] = { + .class_hid = BNXT_ULP_CLASS_HID_3a8d0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2835] = { - .class_hid = BNXT_ULP_CLASS_HID_c138, + [3415] = { + .class_hid = BNXT_ULP_CLASS_HID_3b79c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2836] = { - .class_hid = BNXT_ULP_CLASS_HID_e2f8, + [3416] = { + .class_hid = BNXT_ULP_CLASS_HID_3ae8c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2837] = { - .class_hid = BNXT_ULP_CLASS_HID_978c, + [3417] = { + .class_hid = BNXT_ULP_CLASS_HID_39b7c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2838] = { - .class_hid = BNXT_ULP_CLASS_HID_b94c, + [3418] = { + .class_hid = BNXT_ULP_CLASS_HID_3b26c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2839] = { - .class_hid = BNXT_ULP_CLASS_HID_da0c, + [3419] = { + .class_hid = BNXT_ULP_CLASS_HID_38138, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2840] = { - .class_hid = BNXT_ULP_CLASS_HID_ffcc, + [3420] = { + .class_hid = BNXT_ULP_CLASS_HID_3b828, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2841] = { - .class_hid = BNXT_ULP_CLASS_HID_18d8c, + [3421] = { + .class_hid = BNXT_ULP_CLASS_HID_3d7a8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2842] = { - .class_hid = BNXT_ULP_CLASS_HID_1af4c, + [3422] = { + .class_hid = BNXT_ULP_CLASS_HID_3938c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2843] = { - .class_hid = BNXT_ULP_CLASS_HID_1f00c, + [3423] = { + .class_hid = BNXT_ULP_CLASS_HID_3dd64, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2844] = { - .class_hid = BNXT_ULP_CLASS_HID_1f5cc, + [3424] = { + .class_hid = BNXT_ULP_CLASS_HID_39948, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2845] = { - .class_hid = BNXT_ULP_CLASS_HID_1b0b8, + [3425] = { + .class_hid = BNXT_ULP_CLASS_HID_3a144, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2846] = { - .class_hid = BNXT_ULP_CLASS_HID_1b278, + [3426] = { + .class_hid = BNXT_ULP_CLASS_HID_3d874, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2847] = { - .class_hid = BNXT_ULP_CLASS_HID_1f738, + [3427] = { + .class_hid = BNXT_ULP_CLASS_HID_3a700, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2848] = { - .class_hid = BNXT_ULP_CLASS_HID_1f8f8, + [3428] = { + .class_hid = BNXT_ULP_CLASS_HID_3de30, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2849] = { - .class_hid = BNXT_ULP_CLASS_HID_bf2c, + [3429] = { + .class_hid = BNXT_ULP_CLASS_HID_39cf0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2850] = { - .class_hid = BNXT_ULP_CLASS_HID_a0ec, + [3430] = { + .class_hid = BNXT_ULP_CLASS_HID_3b7e0, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2851] = { - .class_hid = BNXT_ULP_CLASS_HID_e5ac, + [3431] = { + .class_hid = BNXT_ULP_CLASS_HID_382ac, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2852] = { - .class_hid = BNXT_ULP_CLASS_HID_e76c, + [3432] = { + .class_hid = BNXT_ULP_CLASS_HID_3bddc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2853] = { - .class_hid = BNXT_ULP_CLASS_HID_b870, + [3433] = { + .class_hid = BNXT_ULP_CLASS_HID_3c5d8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2854] = { - .class_hid = BNXT_ULP_CLASS_HID_bd30, + [3434] = { + .class_hid = BNXT_ULP_CLASS_HID_381bc, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2855] = { - .class_hid = BNXT_ULP_CLASS_HID_fef0, + [3435] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb94, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2856] = { - .class_hid = BNXT_ULP_CLASS_HID_e3b0, + [3436] = { + .class_hid = BNXT_ULP_CLASS_HID_38778, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2857] = { - .class_hid = BNXT_ULP_CLASS_HID_1ae70, + [3437] = { + .class_hid = BNXT_ULP_CLASS_HID_7c54c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2858] = { - .class_hid = BNXT_ULP_CLASS_HID_1f330, + [3438] = { + .class_hid = BNXT_ULP_CLASS_HID_78130, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2859] = { - .class_hid = BNXT_ULP_CLASS_HID_1d4f0, + [3439] = { + .class_hid = BNXT_ULP_CLASS_HID_7cb08, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2860] = { - .class_hid = BNXT_ULP_CLASS_HID_1f9b0, + [3440] = { + .class_hid = BNXT_ULP_CLASS_HID_786ec, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2861] = { - .class_hid = BNXT_ULP_CLASS_HID_1d52c, + [3441] = { + .class_hid = BNXT_ULP_CLASS_HID_7aee8, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2862] = { - .class_hid = BNXT_ULP_CLASS_HID_1f6ec, + [3442] = { + .class_hid = BNXT_ULP_CLASS_HID_7c618, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245828, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2863] = { - .class_hid = BNXT_ULP_CLASS_HID_1dbac, + [3443] = { + .class_hid = BNXT_ULP_CLASS_HID_7d4a4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2864] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd6c, + [3444] = { + .class_hid = BNXT_ULP_CLASS_HID_79088, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245828, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2865] = { - .class_hid = BNXT_ULP_CLASS_HID_34d0, + [3445] = { + .class_hid = BNXT_ULP_CLASS_HID_78a94, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2866] = { - .class_hid = BNXT_ULP_CLASS_HID_3a1c, + [3446] = { + .class_hid = BNXT_ULP_CLASS_HID_7a584, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2867] = { - .class_hid = BNXT_ULP_CLASS_HID_3760, + [3447] = { + .class_hid = BNXT_ULP_CLASS_HID_7b050, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2868] = { - .class_hid = BNXT_ULP_CLASS_HID_5e80, + [3448] = { + .class_hid = BNXT_ULP_CLASS_HID_7ab40, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2869] = { - .class_hid = BNXT_ULP_CLASS_HID_5bd4, + [3449] = { + .class_hid = BNXT_ULP_CLASS_HID_79430, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2870] = { - .class_hid = BNXT_ULP_CLASS_HID_07b8, + [3450] = { + .class_hid = BNXT_ULP_CLASS_HID_78f20, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245828, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2871] = { - .class_hid = BNXT_ULP_CLASS_HID_008c, + [3451] = { + .class_hid = BNXT_ULP_CLASS_HID_79dec, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2872] = { - .class_hid = BNXT_ULP_CLASS_HID_282c, + [3452] = { + .class_hid = BNXT_ULP_CLASS_HID_7b51c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245828, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2873] = { - .class_hid = BNXT_ULP_CLASS_HID_2570, + [3453] = { + .class_hid = BNXT_ULP_CLASS_HID_7d09c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2874] = { - .class_hid = BNXT_ULP_CLASS_HID_3124, + [3454] = { + .class_hid = BNXT_ULP_CLASS_HID_7cb8c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2875] = { - .class_hid = BNXT_ULP_CLASS_HID_5944, + [3455] = { + .class_hid = BNXT_ULP_CLASS_HID_7d658, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2876] = { - .class_hid = BNXT_ULP_CLASS_HID_5588, + [3456] = { + .class_hid = BNXT_ULP_CLASS_HID_7923c, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2877] = { - .class_hid = BNXT_ULP_CLASS_HID_1e7c, + [3457] = { + .class_hid = BNXT_ULP_CLASS_HID_7ba38, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2878] = { - .class_hid = BNXT_ULP_CLASS_HID_1b40, + [3458] = { + .class_hid = BNXT_ULP_CLASS_HID_7d528, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245828, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2879] = { - .class_hid = BNXT_ULP_CLASS_HID_22e0, + [3459] = { + .class_hid = BNXT_ULP_CLASS_HID_7a3f4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2880] = { - .class_hid = BNXT_ULP_CLASS_HID_3f34, + [3460] = { + .class_hid = BNXT_ULP_CLASS_HID_7dae4, .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 244, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 245828, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2881] = { - .class_hid = BNXT_ULP_CLASS_HID_a77c, + [3461] = { + .class_hid = BNXT_ULP_CLASS_HID_799a4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2882] = { - .class_hid = BNXT_ULP_CLASS_HID_a8bc, + [3462] = { + .class_hid = BNXT_ULP_CLASS_HID_7b0d4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 245764, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2883] = { - .class_hid = BNXT_ULP_CLASS_HID_edfc, + [3463] = { + .class_hid = BNXT_ULP_CLASS_HID_79f60, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2884] = { - .class_hid = BNXT_ULP_CLASS_HID_ef3c, + [3464] = { + .class_hid = BNXT_ULP_CLASS_HID_7b690, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 245764, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2885] = { - .class_hid = BNXT_ULP_CLASS_HID_a000, + [3465] = { + .class_hid = BNXT_ULP_CLASS_HID_7de8c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2886] = { - .class_hid = BNXT_ULP_CLASS_HID_a540, + [3466] = { + .class_hid = BNXT_ULP_CLASS_HID_79a70, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2887] = { - .class_hid = BNXT_ULP_CLASS_HID_e680, + [3467] = { + .class_hid = BNXT_ULP_CLASS_HID_7c448, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2888] = { - .class_hid = BNXT_ULP_CLASS_HID_ebc0, + [3468] = { + .class_hid = BNXT_ULP_CLASS_HID_7802c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 10, + .flow_sig_id = 245828, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2889] = { - .class_hid = BNXT_ULP_CLASS_HID_1d600, + [3469] = { + .class_hid = BNXT_ULP_CLASS_HID_86a0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60581,19 +73765,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2890] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb40, + [3470] = { + .class_hid = BNXT_ULP_CLASS_HID_a1b0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60602,20 +73782,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2891] = { - .class_hid = BNXT_ULP_CLASS_HID_1dc80, + [3471] = { + .class_hid = BNXT_ULP_CLASS_HID_8c6c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60624,20 +73800,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2892] = { - .class_hid = BNXT_ULP_CLASS_HID_1e1c0, + [3472] = { + .class_hid = BNXT_ULP_CLASS_HID_a77c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60646,21 +73818,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2893] = { - .class_hid = BNXT_ULP_CLASS_HID_1dd7c, + [3473] = { + .class_hid = BNXT_ULP_CLASS_HID_900c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60669,18 +73837,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2894] = { - .class_hid = BNXT_ULP_CLASS_HID_1febc, + [3474] = { + .class_hid = BNXT_ULP_CLASS_HID_8b1c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60689,19 +73855,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2895] = { - .class_hid = BNXT_ULP_CLASS_HID_1c3fc, + [3475] = { + .class_hid = BNXT_ULP_CLASS_HID_99c8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60710,19 +73874,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2896] = { - .class_hid = BNXT_ULP_CLASS_HID_1e53c, + [3476] = { + .class_hid = BNXT_ULP_CLASS_HID_b0d8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60731,20 +73893,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2897] = { - .class_hid = BNXT_ULP_CLASS_HID_cbe0, + [3477] = { + .class_hid = BNXT_ULP_CLASS_HID_aad4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60753,18 +73913,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2898] = { - .class_hid = BNXT_ULP_CLASS_HID_b1f4, + [3478] = { + .class_hid = BNXT_ULP_CLASS_HID_c224, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60773,19 +73931,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2899] = { - .class_hid = BNXT_ULP_CLASS_HID_d334, + [3479] = { + .class_hid = BNXT_ULP_CLASS_HID_d090, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60794,19 +73950,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2900] = { - .class_hid = BNXT_ULP_CLASS_HID_f474, + [3480] = { + .class_hid = BNXT_ULP_CLASS_HID_cbe0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60815,20 +73969,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2901] = { - .class_hid = BNXT_ULP_CLASS_HID_c4b4, + [3481] = { + .class_hid = BNXT_ULP_CLASS_HID_b4b0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60837,19 +73989,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2902] = { - .class_hid = BNXT_ULP_CLASS_HID_e9f4, + [3482] = { + .class_hid = BNXT_ULP_CLASS_HID_af80, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60858,20 +74008,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2903] = { - .class_hid = BNXT_ULP_CLASS_HID_cb34, + [3483] = { + .class_hid = BNXT_ULP_CLASS_HID_ba7c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60880,20 +74028,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2904] = { - .class_hid = BNXT_ULP_CLASS_HID_f138, + [3484] = { + .class_hid = BNXT_ULP_CLASS_HID_d54c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60902,21 +74048,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2905] = { - .class_hid = BNXT_ULP_CLASS_HID_19f78, + [3485] = { + .class_hid = BNXT_ULP_CLASS_HID_48374, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60925,20 +74069,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2906] = { - .class_hid = BNXT_ULP_CLASS_HID_1a0b8, + [3486] = { + .class_hid = BNXT_ULP_CLASS_HID_4ba44, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60947,21 +74087,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2907] = { - .class_hid = BNXT_ULP_CLASS_HID_1c5f8, + [3487] = { + .class_hid = BNXT_ULP_CLASS_HID_48930, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60970,21 +74106,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2908] = { - .class_hid = BNXT_ULP_CLASS_HID_1e738, + [3488] = { + .class_hid = BNXT_ULP_CLASS_HID_4a000, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -60993,22 +74125,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2909] = { - .class_hid = BNXT_ULP_CLASS_HID_182b4, + [3489] = { + .class_hid = BNXT_ULP_CLASS_HID_4c80c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61017,19 +74145,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2910] = { - .class_hid = BNXT_ULP_CLASS_HID_1a7f4, + [3490] = { + .class_hid = BNXT_ULP_CLASS_HID_48420, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61038,20 +74164,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2911] = { - .class_hid = BNXT_ULP_CLASS_HID_1c934, + [3491] = { + .class_hid = BNXT_ULP_CLASS_HID_4929c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61060,43 +74184,39 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2912] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea74, + [3492] = { + .class_hid = BNXT_ULP_CLASS_HID_48dec, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2913] = { - .class_hid = BNXT_ULP_CLASS_HID_b0d8, + [3493] = { + .class_hid = BNXT_ULP_CLASS_HID_4a798, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61105,18 +74225,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2914] = { - .class_hid = BNXT_ULP_CLASS_HID_b218, + [3494] = { + .class_hid = BNXT_ULP_CLASS_HID_4dee8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 244, + .hdr_sig_id = 11, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61125,19 +74244,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2915] = { - .class_hid = BNXT_ULP_CLASS_HID_f758, + [3495] = { + .class_hid = BNXT_ULP_CLASS_HID_4ada4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61146,19 +74264,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2916] = { - .class_hid = BNXT_ULP_CLASS_HID_f898, + [3496] = { + .class_hid = BNXT_ULP_CLASS_HID_4c4b4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 246, + .hdr_sig_id = 11, + .flow_sig_id = 131076, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61167,20 +74284,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2917] = { - .class_hid = BNXT_ULP_CLASS_HID_8dec, + [3497] = { + .class_hid = BNXT_ULP_CLASS_HID_4b144, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 247, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61189,19 +74305,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2918] = { - .class_hid = BNXT_ULP_CLASS_HID_af2c, + [3498] = { + .class_hid = BNXT_ULP_CLASS_HID_4a854, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 247, + .hdr_sig_id = 11, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61210,20 +74325,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2919] = { - .class_hid = BNXT_ULP_CLASS_HID_f06c, + [3499] = { + .class_hid = BNXT_ULP_CLASS_HID_4b700, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 247, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61232,20 +74346,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2920] = { - .class_hid = BNXT_ULP_CLASS_HID_f5ac, + [3500] = { + .class_hid = BNXT_ULP_CLASS_HID_4ae10, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 247, + .hdr_sig_id = 11, + .flow_sig_id = 131140, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61254,21 +74367,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2921] = { - .class_hid = BNXT_ULP_CLASS_HID_1a3ec, + [3501] = { + .class_hid = BNXT_ULP_CLASS_HID_1bca0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 247, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61277,20 +74389,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2922] = { - .class_hid = BNXT_ULP_CLASS_HID_1a52c, + [3502] = { + .class_hid = BNXT_ULP_CLASS_HID_1d7b0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 247, + .hdr_sig_id = 11, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61299,21 +74407,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2923] = { - .class_hid = BNXT_ULP_CLASS_HID_1e66c, + [3503] = { + .class_hid = BNXT_ULP_CLASS_HID_1a26c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 248, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61322,21 +74426,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2924] = { - .class_hid = BNXT_ULP_CLASS_HID_1ebac, + [3504] = { + .class_hid = BNXT_ULP_CLASS_HID_1dd7c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 249, + .hdr_sig_id = 11, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61345,22 +74445,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2925] = { - .class_hid = BNXT_ULP_CLASS_HID_1a6d8, + [3505] = { + .class_hid = BNXT_ULP_CLASS_HID_1860c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61369,19 +74465,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2926] = { - .class_hid = BNXT_ULP_CLASS_HID_1a818, + [3506] = { + .class_hid = BNXT_ULP_CLASS_HID_1a11c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61390,20 +74484,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2927] = { - .class_hid = BNXT_ULP_CLASS_HID_1ed58, + [3507] = { + .class_hid = BNXT_ULP_CLASS_HID_18fc8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61412,20 +74504,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2928] = { - .class_hid = BNXT_ULP_CLASS_HID_1ee98, + [3508] = { + .class_hid = BNXT_ULP_CLASS_HID_1a6d8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61434,21 +74524,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2929] = { - .class_hid = BNXT_ULP_CLASS_HID_d54c, + [3509] = { + .class_hid = BNXT_ULP_CLASS_HID_1c0d4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61457,19 +74545,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2930] = { - .class_hid = BNXT_ULP_CLASS_HID_f68c, + [3510] = { + .class_hid = BNXT_ULP_CLASS_HID_19ce8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61478,20 +74564,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2931] = { - .class_hid = BNXT_ULP_CLASS_HID_dbcc, + [3511] = { + .class_hid = BNXT_ULP_CLASS_HID_1c690, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61500,20 +74584,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2932] = { - .class_hid = BNXT_ULP_CLASS_HID_fd0c, + [3512] = { + .class_hid = BNXT_ULP_CLASS_HID_182b4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61522,21 +74604,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2933] = { - .class_hid = BNXT_ULP_CLASS_HID_ae10, + [3513] = { + .class_hid = BNXT_ULP_CLASS_HID_1aab0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61545,20 +74625,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2934] = { - .class_hid = BNXT_ULP_CLASS_HID_f350, + [3514] = { + .class_hid = BNXT_ULP_CLASS_HID_1c580, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61567,21 +74645,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2935] = { - .class_hid = BNXT_ULP_CLASS_HID_d490, + [3515] = { + .class_hid = BNXT_ULP_CLASS_HID_1d07c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61590,21 +74666,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2936] = { - .class_hid = BNXT_ULP_CLASS_HID_f9d0, + [3516] = { + .class_hid = BNXT_ULP_CLASS_HID_1cb4c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61613,22 +74687,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2937] = { - .class_hid = BNXT_ULP_CLASS_HID_1c410, + [3517] = { + .class_hid = BNXT_ULP_CLASS_HID_5b974, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61637,21 +74709,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2938] = { - .class_hid = BNXT_ULP_CLASS_HID_1e950, + [3518] = { + .class_hid = BNXT_ULP_CLASS_HID_5d044, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61660,22 +74728,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2939] = { - .class_hid = BNXT_ULP_CLASS_HID_1ca90, + [3519] = { + .class_hid = BNXT_ULP_CLASS_HID_5bf30, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61684,22 +74748,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2940] = { - .class_hid = BNXT_ULP_CLASS_HID_1f0e4, + [3520] = { + .class_hid = BNXT_ULP_CLASS_HID_5d600, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61708,23 +74768,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2941] = { - .class_hid = BNXT_ULP_CLASS_HID_1cb4c, + [3521] = { + .class_hid = BNXT_ULP_CLASS_HID_582d0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61733,20 +74789,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2942] = { - .class_hid = BNXT_ULP_CLASS_HID_1b150, + [3522] = { + .class_hid = BNXT_ULP_CLASS_HID_5ba20, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61755,21 +74809,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2943] = { - .class_hid = BNXT_ULP_CLASS_HID_1d290, + [3523] = { + .class_hid = BNXT_ULP_CLASS_HID_5889c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61778,21 +74830,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2944] = { - .class_hid = BNXT_ULP_CLASS_HID_1f7d0, + [3524] = { + .class_hid = BNXT_ULP_CLASS_HID_5a3ec, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61801,22 +74851,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2945] = { - .class_hid = BNXT_ULP_CLASS_HID_a1b0, + [3525] = { + .class_hid = BNXT_ULP_CLASS_HID_5dd98, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61825,16 +74873,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2946] = { - .class_hid = BNXT_ULP_CLASS_HID_a2f0, + [3526] = { + .class_hid = BNXT_ULP_CLASS_HID_599bc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61843,17 +74893,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2947] = { - .class_hid = BNXT_ULP_CLASS_HID_e430, + [3527] = { + .class_hid = BNXT_ULP_CLASS_HID_5c3a4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61862,17 +74914,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2948] = { - .class_hid = BNXT_ULP_CLASS_HID_e970, + [3528] = { + .class_hid = BNXT_ULP_CLASS_HID_59f78, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196612, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61881,18 +74935,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2949] = { - .class_hid = BNXT_ULP_CLASS_HID_ba44, + [3529] = { + .class_hid = BNXT_ULP_CLASS_HID_5a744, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61901,17 +74957,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2950] = { - .class_hid = BNXT_ULP_CLASS_HID_bf84, + [3530] = { + .class_hid = BNXT_ULP_CLASS_HID_5de54, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61920,18 +74978,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2951] = { - .class_hid = BNXT_ULP_CLASS_HID_e0c4, + [3531] = { + .class_hid = BNXT_ULP_CLASS_HID_5ad00, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61940,18 +75000,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2952] = { - .class_hid = BNXT_ULP_CLASS_HID_e204, + [3532] = { + .class_hid = BNXT_ULP_CLASS_HID_5c410, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 196676, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61960,19 +75022,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2953] = { - .class_hid = BNXT_ULP_CLASS_HID_1d044, + [3533] = { + .class_hid = BNXT_ULP_CLASS_HID_cd20, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -61981,18 +75045,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2954] = { - .class_hid = BNXT_ULP_CLASS_HID_1f584, + [3534] = { + .class_hid = BNXT_ULP_CLASS_HID_e430, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62001,19 +75063,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2955] = { - .class_hid = BNXT_ULP_CLASS_HID_1d6c4, + [3535] = { + .class_hid = BNXT_ULP_CLASS_HID_f2ec, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62022,19 +75082,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2956] = { - .class_hid = BNXT_ULP_CLASS_HID_1f804, + [3536] = { + .class_hid = BNXT_ULP_CLASS_HID_edfc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62043,20 +75101,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2957] = { - .class_hid = BNXT_ULP_CLASS_HID_1d7b0, + [3537] = { + .class_hid = BNXT_ULP_CLASS_HID_d68c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62065,17 +75121,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2958] = { - .class_hid = BNXT_ULP_CLASS_HID_1f8f0, + [3538] = { + .class_hid = BNXT_ULP_CLASS_HID_f19c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62084,18 +75140,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2959] = { - .class_hid = BNXT_ULP_CLASS_HID_1da30, + [3539] = { + .class_hid = BNXT_ULP_CLASS_HID_dc48, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62104,18 +75160,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2960] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff70, + [3540] = { + .class_hid = BNXT_ULP_CLASS_HID_f758, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62124,19 +75180,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2961] = { - .class_hid = BNXT_ULP_CLASS_HID_c224, + [3541] = { + .class_hid = BNXT_ULP_CLASS_HID_d154, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62145,17 +75201,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2962] = { - .class_hid = BNXT_ULP_CLASS_HID_e764, + [3542] = { + .class_hid = BNXT_ULP_CLASS_HID_c8a4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62164,18 +75220,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2963] = { - .class_hid = BNXT_ULP_CLASS_HID_c8a4, + [3543] = { + .class_hid = BNXT_ULP_CLASS_HID_d710, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62184,18 +75240,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2964] = { - .class_hid = BNXT_ULP_CLASS_HID_ede4, + [3544] = { + .class_hid = BNXT_ULP_CLASS_HID_d334, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62204,19 +75260,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2965] = { - .class_hid = BNXT_ULP_CLASS_HID_dee8, + [3545] = { + .class_hid = BNXT_ULP_CLASS_HID_fb30, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62225,18 +75281,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2966] = { - .class_hid = BNXT_ULP_CLASS_HID_e028, + [3546] = { + .class_hid = BNXT_ULP_CLASS_HID_d200, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62245,19 +75301,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2967] = { - .class_hid = BNXT_ULP_CLASS_HID_c568, + [3547] = { + .class_hid = BNXT_ULP_CLASS_HID_e0fc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62266,19 +75322,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2968] = { - .class_hid = BNXT_ULP_CLASS_HID_e6a8, + [3548] = { + .class_hid = BNXT_ULP_CLASS_HID_dbcc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62287,20 +75343,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2969] = { - .class_hid = BNXT_ULP_CLASS_HID_199bc, + [3549] = { + .class_hid = BNXT_ULP_CLASS_HID_4c9f4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62309,19 +75365,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2970] = { - .class_hid = BNXT_ULP_CLASS_HID_1bafc, + [3550] = { + .class_hid = BNXT_ULP_CLASS_HID_4e0c4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62330,20 +75384,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2971] = { - .class_hid = BNXT_ULP_CLASS_HID_1dc3c, + [3551] = { + .class_hid = BNXT_ULP_CLASS_HID_4cfb0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62352,20 +75404,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2972] = { - .class_hid = BNXT_ULP_CLASS_HID_1e17c, + [3552] = { + .class_hid = BNXT_ULP_CLASS_HID_4e680, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62374,21 +75424,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2973] = { - .class_hid = BNXT_ULP_CLASS_HID_19ce8, + [3553] = { + .class_hid = BNXT_ULP_CLASS_HID_4d350, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62397,18 +75445,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2974] = { - .class_hid = BNXT_ULP_CLASS_HID_1be28, + [3554] = { + .class_hid = BNXT_ULP_CLASS_HID_4caa0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62417,19 +75465,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2975] = { - .class_hid = BNXT_ULP_CLASS_HID_1c368, + [3555] = { + .class_hid = BNXT_ULP_CLASS_HID_4d91c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62438,19 +75486,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2976] = { - .class_hid = BNXT_ULP_CLASS_HID_1e4a8, + [3556] = { + .class_hid = BNXT_ULP_CLASS_HID_4f06c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62459,20 +75507,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2977] = { - .class_hid = BNXT_ULP_CLASS_HID_8b1c, + [3557] = { + .class_hid = BNXT_ULP_CLASS_HID_4ea18, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62481,17 +75529,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2978] = { - .class_hid = BNXT_ULP_CLASS_HID_ac5c, + [3558] = { + .class_hid = BNXT_ULP_CLASS_HID_4c568, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62500,18 +75549,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2979] = { - .class_hid = BNXT_ULP_CLASS_HID_f19c, + [3559] = { + .class_hid = BNXT_ULP_CLASS_HID_4d024, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62520,18 +75570,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2980] = { - .class_hid = BNXT_ULP_CLASS_HID_f2dc, + [3560] = { + .class_hid = BNXT_ULP_CLASS_HID_4cb34, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393220, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62540,19 +75591,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2981] = { - .class_hid = BNXT_ULP_CLASS_HID_8420, + [3561] = { + .class_hid = BNXT_ULP_CLASS_HID_4f7c4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62561,18 +75613,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2982] = { - .class_hid = BNXT_ULP_CLASS_HID_a960, + [3562] = { + .class_hid = BNXT_ULP_CLASS_HID_4eed4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62581,19 +75634,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2983] = { - .class_hid = BNXT_ULP_CLASS_HID_caa0, + [3563] = { + .class_hid = BNXT_ULP_CLASS_HID_4fd80, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62602,19 +75656,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2984] = { - .class_hid = BNXT_ULP_CLASS_HID_efe0, + [3564] = { + .class_hid = BNXT_ULP_CLASS_HID_4d490, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 393284, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62623,20 +75678,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2985] = { - .class_hid = BNXT_ULP_CLASS_HID_1ba20, + [3565] = { + .class_hid = BNXT_ULP_CLASS_HID_1e320, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62645,19 +75701,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2986] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf60, + [3566] = { + .class_hid = BNXT_ULP_CLASS_HID_1da30, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62666,20 +75720,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2987] = { - .class_hid = BNXT_ULP_CLASS_HID_1e0a0, + [3567] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8ec, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62688,20 +75740,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2988] = { - .class_hid = BNXT_ULP_CLASS_HID_1e5e0, + [3568] = { + .class_hid = BNXT_ULP_CLASS_HID_1c3fc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62710,21 +75760,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2989] = { - .class_hid = BNXT_ULP_CLASS_HID_1a11c, + [3569] = { + .class_hid = BNXT_ULP_CLASS_HID_1cc8c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62733,18 +75781,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2990] = { - .class_hid = BNXT_ULP_CLASS_HID_1a25c, + [3570] = { + .class_hid = BNXT_ULP_CLASS_HID_1e79c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62753,19 +75801,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2991] = { - .class_hid = BNXT_ULP_CLASS_HID_1e79c, + [3571] = { + .class_hid = BNXT_ULP_CLASS_HID_1f248, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62774,19 +75822,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2992] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8dc, + [3572] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed58, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62795,20 +75843,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2993] = { - .class_hid = BNXT_ULP_CLASS_HID_af80, + [3573] = { + .class_hid = BNXT_ULP_CLASS_HID_1c754, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62817,18 +75865,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2994] = { - .class_hid = BNXT_ULP_CLASS_HID_f0c0, + [3574] = { + .class_hid = BNXT_ULP_CLASS_HID_1c368, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62837,19 +75885,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2995] = { - .class_hid = BNXT_ULP_CLASS_HID_d200, + [3575] = { + .class_hid = BNXT_ULP_CLASS_HID_1cd10, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62858,19 +75906,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2996] = { - .class_hid = BNXT_ULP_CLASS_HID_f740, + [3576] = { + .class_hid = BNXT_ULP_CLASS_HID_1c934, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62879,20 +75927,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2997] = { - .class_hid = BNXT_ULP_CLASS_HID_a854, + [3577] = { + .class_hid = BNXT_ULP_CLASS_HID_1d130, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62901,19 +75949,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2998] = { - .class_hid = BNXT_ULP_CLASS_HID_ad94, + [3578] = { + .class_hid = BNXT_ULP_CLASS_HID_1c800, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62922,20 +75970,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [2999] = { - .class_hid = BNXT_ULP_CLASS_HID_eed4, + [3579] = { + .class_hid = BNXT_ULP_CLASS_HID_1d6fc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62944,20 +75992,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3000] = { - .class_hid = BNXT_ULP_CLASS_HID_f014, + [3580] = { + .class_hid = BNXT_ULP_CLASS_HID_1d290, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62966,21 +76014,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3001] = { - .class_hid = BNXT_ULP_CLASS_HID_1de54, + [3581] = { + .class_hid = BNXT_ULP_CLASS_HID_5fff4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -62989,20 +76037,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3002] = { - .class_hid = BNXT_ULP_CLASS_HID_1e394, + [3582] = { + .class_hid = BNXT_ULP_CLASS_HID_5d6c4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63011,21 +76057,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3003] = { - .class_hid = BNXT_ULP_CLASS_HID_1c4d4, + [3583] = { + .class_hid = BNXT_ULP_CLASS_HID_5e5b0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63034,21 +76078,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3004] = { - .class_hid = BNXT_ULP_CLASS_HID_1e614, + [3584] = { + .class_hid = BNXT_ULP_CLASS_HID_5dc80, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63057,22 +76099,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3005] = { - .class_hid = BNXT_ULP_CLASS_HID_1c580, + [3585] = { + .class_hid = BNXT_ULP_CLASS_HID_5c950, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63081,19 +76121,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3006] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6c0, + [3586] = { + .class_hid = BNXT_ULP_CLASS_HID_5e0a0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63102,20 +76142,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3007] = { - .class_hid = BNXT_ULP_CLASS_HID_1c800, + [3587] = { + .class_hid = BNXT_ULP_CLASS_HID_5cf1c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63124,20 +76164,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3008] = { - .class_hid = BNXT_ULP_CLASS_HID_1ed40, + [3588] = { + .class_hid = BNXT_ULP_CLASS_HID_5e66c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63146,21 +76186,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3009] = { - .class_hid = BNXT_ULP_CLASS_HID_8c6c, + [3589] = { + .class_hid = BNXT_ULP_CLASS_HID_5c018, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63169,16 +76209,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3010] = { - .class_hid = BNXT_ULP_CLASS_HID_b1ac, + [3590] = { + .class_hid = BNXT_ULP_CLASS_HID_5dc3c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63187,17 +76230,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3011] = { - .class_hid = BNXT_ULP_CLASS_HID_f2ec, + [3591] = { + .class_hid = BNXT_ULP_CLASS_HID_5c624, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63206,17 +76252,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3012] = { - .class_hid = BNXT_ULP_CLASS_HID_f42c, + [3592] = { + .class_hid = BNXT_ULP_CLASS_HID_5c5f8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458756, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63225,18 +76274,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3013] = { - .class_hid = BNXT_ULP_CLASS_HID_8930, + [3593] = { + .class_hid = BNXT_ULP_CLASS_HID_5edc4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63245,17 +76297,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3014] = { - .class_hid = BNXT_ULP_CLASS_HID_aa70, + [3594] = { + .class_hid = BNXT_ULP_CLASS_HID_5c4d4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63264,18 +76319,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3015] = { - .class_hid = BNXT_ULP_CLASS_HID_cfb0, + [3595] = { + .class_hid = BNXT_ULP_CLASS_HID_5d380, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63284,18 +76342,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3016] = { - .class_hid = BNXT_ULP_CLASS_HID_f0f0, + [3596] = { + .class_hid = BNXT_ULP_CLASS_HID_5ca90, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 458820, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63304,19 +76365,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3017] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf30, + [3597] = { + .class_hid = BNXT_ULP_CLASS_HID_abe0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63325,18 +76389,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3018] = { - .class_hid = BNXT_ULP_CLASS_HID_1a070, + [3598] = { + .class_hid = BNXT_ULP_CLASS_HID_a2f0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63345,19 +76407,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3019] = { - .class_hid = BNXT_ULP_CLASS_HID_1e5b0, + [3599] = { + .class_hid = BNXT_ULP_CLASS_HID_b1ac, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63366,19 +76426,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3020] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6f0, + [3600] = { + .class_hid = BNXT_ULP_CLASS_HID_a8bc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63387,20 +76445,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3021] = { - .class_hid = BNXT_ULP_CLASS_HID_1a26c, + [3601] = { + .class_hid = BNXT_ULP_CLASS_HID_b54c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63409,17 +76465,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3022] = { - .class_hid = BNXT_ULP_CLASS_HID_1a7ac, + [3602] = { + .class_hid = BNXT_ULP_CLASS_HID_ac5c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63428,18 +76484,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3023] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8ec, + [3603] = { + .class_hid = BNXT_ULP_CLASS_HID_bb08, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63448,18 +76504,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3024] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea2c, + [3604] = { + .class_hid = BNXT_ULP_CLASS_HID_b218, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63468,19 +76524,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3025] = { - .class_hid = BNXT_ULP_CLASS_HID_d090, + [3605] = { + .class_hid = BNXT_ULP_CLASS_HID_ac14, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63489,17 +76545,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3026] = { - .class_hid = BNXT_ULP_CLASS_HID_f5d0, + [3606] = { + .class_hid = BNXT_ULP_CLASS_HID_e764, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63508,18 +76564,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3027] = { - .class_hid = BNXT_ULP_CLASS_HID_d710, + [3607] = { + .class_hid = BNXT_ULP_CLASS_HID_f5d0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63528,18 +76584,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3028] = { - .class_hid = BNXT_ULP_CLASS_HID_f850, + [3608] = { + .class_hid = BNXT_ULP_CLASS_HID_b1f4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63548,19 +76604,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3029] = { - .class_hid = BNXT_ULP_CLASS_HID_ada4, + [3609] = { + .class_hid = BNXT_ULP_CLASS_HID_b9f0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63569,18 +76625,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3030] = { - .class_hid = BNXT_ULP_CLASS_HID_aee4, + [3610] = { + .class_hid = BNXT_ULP_CLASS_HID_f0c0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63589,19 +76645,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3031] = { - .class_hid = BNXT_ULP_CLASS_HID_d024, + [3611] = { + .class_hid = BNXT_ULP_CLASS_HID_bfbc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63610,19 +76666,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3032] = { - .class_hid = BNXT_ULP_CLASS_HID_f564, + [3612] = { + .class_hid = BNXT_ULP_CLASS_HID_f68c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63631,20 +76687,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3033] = { - .class_hid = BNXT_ULP_CLASS_HID_1c3a4, + [3613] = { + .class_hid = BNXT_ULP_CLASS_HID_4a4b4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63653,19 +76709,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3034] = { - .class_hid = BNXT_ULP_CLASS_HID_1e4e4, + [3614] = { + .class_hid = BNXT_ULP_CLASS_HID_4bf84, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63674,20 +76728,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3035] = { - .class_hid = BNXT_ULP_CLASS_HID_1c624, + [3615] = { + .class_hid = BNXT_ULP_CLASS_HID_4aa70, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63696,20 +76748,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3036] = { - .class_hid = BNXT_ULP_CLASS_HID_1eb64, + [3616] = { + .class_hid = BNXT_ULP_CLASS_HID_4a540, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63718,21 +76768,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3037] = { - .class_hid = BNXT_ULP_CLASS_HID_1c690, + [3617] = { + .class_hid = BNXT_ULP_CLASS_HID_4ed4c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63741,18 +76789,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3038] = { - .class_hid = BNXT_ULP_CLASS_HID_1ebd0, + [3618] = { + .class_hid = BNXT_ULP_CLASS_HID_4a960, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63761,19 +76809,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3039] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd10, + [3619] = { + .class_hid = BNXT_ULP_CLASS_HID_4b7dc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63782,19 +76830,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3040] = { - .class_hid = BNXT_ULP_CLASS_HID_1f364, + [3620] = { + .class_hid = BNXT_ULP_CLASS_HID_4af2c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63803,20 +76851,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3041] = { - .class_hid = BNXT_ULP_CLASS_HID_99c8, + [3621] = { + .class_hid = BNXT_ULP_CLASS_HID_4a8d8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63825,17 +76873,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3042] = { - .class_hid = BNXT_ULP_CLASS_HID_bb08, + [3622] = { + .class_hid = BNXT_ULP_CLASS_HID_4e028, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 250, + .hdr_sig_id = 11, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63844,18 +76893,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3043] = { - .class_hid = BNXT_ULP_CLASS_HID_dc48, + [3623] = { + .class_hid = BNXT_ULP_CLASS_HID_4aee4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 251, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63864,18 +76914,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3044] = { - .class_hid = BNXT_ULP_CLASS_HID_e188, + [3624] = { + .class_hid = BNXT_ULP_CLASS_HID_4e9f4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 252, + .hdr_sig_id = 11, + .flow_sig_id = 655364, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63884,19 +76935,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3045] = { - .class_hid = BNXT_ULP_CLASS_HID_929c, + [3625] = { + .class_hid = BNXT_ULP_CLASS_HID_4b284, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 253, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63905,18 +76957,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3046] = { - .class_hid = BNXT_ULP_CLASS_HID_b7dc, + [3626] = { + .class_hid = BNXT_ULP_CLASS_HID_4ad94, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 253, + .hdr_sig_id = 11, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63925,19 +76978,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3047] = { - .class_hid = BNXT_ULP_CLASS_HID_d91c, + [3627] = { + .class_hid = BNXT_ULP_CLASS_HID_4b840, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 253, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63946,19 +77000,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3048] = { - .class_hid = BNXT_ULP_CLASS_HID_fa5c, + [3628] = { + .class_hid = BNXT_ULP_CLASS_HID_4f350, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 253, + .hdr_sig_id = 11, + .flow_sig_id = 655428, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63967,20 +77022,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3049] = { - .class_hid = BNXT_ULP_CLASS_HID_1889c, + [3629] = { + .class_hid = BNXT_ULP_CLASS_HID_1a1e0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 253, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -63989,19 +77045,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3050] = { - .class_hid = BNXT_ULP_CLASS_HID_1addc, + [3630] = { + .class_hid = BNXT_ULP_CLASS_HID_1f8f0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 253, + .hdr_sig_id = 11, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64010,20 +77064,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3051] = { - .class_hid = BNXT_ULP_CLASS_HID_1cf1c, + [3631] = { + .class_hid = BNXT_ULP_CLASS_HID_1a7ac, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 254, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64032,20 +77084,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3052] = { - .class_hid = BNXT_ULP_CLASS_HID_1f05c, + [3632] = { + .class_hid = BNXT_ULP_CLASS_HID_1febc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 255, + .hdr_sig_id = 11, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64054,21 +77104,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3053] = { - .class_hid = BNXT_ULP_CLASS_HID_18fc8, + [3633] = { + .class_hid = BNXT_ULP_CLASS_HID_1ab4c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64077,18 +77125,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3054] = { - .class_hid = BNXT_ULP_CLASS_HID_1b108, + [3634] = { + .class_hid = BNXT_ULP_CLASS_HID_1a25c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64097,19 +77145,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3055] = { - .class_hid = BNXT_ULP_CLASS_HID_1f248, + [3635] = { + .class_hid = BNXT_ULP_CLASS_HID_1b108, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64118,19 +77166,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3056] = { - .class_hid = BNXT_ULP_CLASS_HID_1f788, + [3636] = { + .class_hid = BNXT_ULP_CLASS_HID_1a818, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64139,20 +77187,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3057] = { - .class_hid = BNXT_ULP_CLASS_HID_ba7c, + [3637] = { + .class_hid = BNXT_ULP_CLASS_HID_1e214, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64161,18 +77209,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3058] = { - .class_hid = BNXT_ULP_CLASS_HID_bfbc, + [3638] = { + .class_hid = BNXT_ULP_CLASS_HID_1be28, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64181,19 +77229,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3059] = { - .class_hid = BNXT_ULP_CLASS_HID_e0fc, + [3639] = { + .class_hid = BNXT_ULP_CLASS_HID_1ebd0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64202,19 +77250,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3060] = { - .class_hid = BNXT_ULP_CLASS_HID_e23c, + [3640] = { + .class_hid = BNXT_ULP_CLASS_HID_1a7f4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64223,20 +77271,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3061] = { - .class_hid = BNXT_ULP_CLASS_HID_b700, + [3641] = { + .class_hid = BNXT_ULP_CLASS_HID_1aff0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64245,19 +77293,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3062] = { - .class_hid = BNXT_ULP_CLASS_HID_b840, + [3642] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6c0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64266,20 +77314,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3063] = { - .class_hid = BNXT_ULP_CLASS_HID_fd80, + [3643] = { + .class_hid = BNXT_ULP_CLASS_HID_1f5bc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64288,20 +77336,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3064] = { - .class_hid = BNXT_ULP_CLASS_HID_fec0, + [3644] = { + .class_hid = BNXT_ULP_CLASS_HID_1b150, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64310,21 +77358,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3065] = { - .class_hid = BNXT_ULP_CLASS_HID_1ad00, + [3645] = { + .class_hid = BNXT_ULP_CLASS_HID_5bab4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64333,20 +77381,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3066] = { - .class_hid = BNXT_ULP_CLASS_HID_1ae40, + [3646] = { + .class_hid = BNXT_ULP_CLASS_HID_5f584, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64355,21 +77401,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3067] = { - .class_hid = BNXT_ULP_CLASS_HID_1d380, + [3647] = { + .class_hid = BNXT_ULP_CLASS_HID_5a070, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64378,21 +77422,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3068] = { - .class_hid = BNXT_ULP_CLASS_HID_1f4c0, + [3648] = { + .class_hid = BNXT_ULP_CLASS_HID_5fb40, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64401,22 +77443,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3069] = { - .class_hid = BNXT_ULP_CLASS_HID_1d07c, + [3649] = { + .class_hid = BNXT_ULP_CLASS_HID_5a410, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64425,19 +77465,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3070] = { - .class_hid = BNXT_ULP_CLASS_HID_1f5bc, + [3650] = { + .class_hid = BNXT_ULP_CLASS_HID_5bf60, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64446,20 +77486,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3071] = { - .class_hid = BNXT_ULP_CLASS_HID_1d6fc, + [3651] = { + .class_hid = BNXT_ULP_CLASS_HID_5addc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64468,20 +77508,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3072] = { - .class_hid = BNXT_ULP_CLASS_HID_1f83c, + [3652] = { + .class_hid = BNXT_ULP_CLASS_HID_5a52c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64490,21 +77530,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3073] = { - .class_hid = BNXT_ULP_CLASS_HID_86a0, + [3653] = { + .class_hid = BNXT_ULP_CLASS_HID_5fed8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64513,15 +77553,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3074] = { - .class_hid = BNXT_ULP_CLASS_HID_abe0, + [3654] = { + .class_hid = BNXT_ULP_CLASS_HID_5bafc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64530,16 +77574,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3075] = { - .class_hid = BNXT_ULP_CLASS_HID_cd20, + [3655] = { + .class_hid = BNXT_ULP_CLASS_HID_5e4e4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64548,16 +77596,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3076] = { - .class_hid = BNXT_ULP_CLASS_HID_ee60, + [3656] = { + .class_hid = BNXT_ULP_CLASS_HID_5a0b8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720900, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64566,17 +77618,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3077] = { - .class_hid = BNXT_ULP_CLASS_HID_8374, + [3657] = { + .class_hid = BNXT_ULP_CLASS_HID_5a884, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64585,16 +77641,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3078] = { - .class_hid = BNXT_ULP_CLASS_HID_a4b4, + [3658] = { + .class_hid = BNXT_ULP_CLASS_HID_5e394, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64603,17 +77663,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3079] = { - .class_hid = BNXT_ULP_CLASS_HID_c9f4, + [3659] = { + .class_hid = BNXT_ULP_CLASS_HID_5ae40, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64622,17 +77686,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3080] = { - .class_hid = BNXT_ULP_CLASS_HID_eb34, + [3660] = { + .class_hid = BNXT_ULP_CLASS_HID_5e950, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 720964, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64641,18 +77709,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3081] = { - .class_hid = BNXT_ULP_CLASS_HID_1b974, + [3661] = { + .class_hid = BNXT_ULP_CLASS_HID_ee60, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64661,17 +77733,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3082] = { - .class_hid = BNXT_ULP_CLASS_HID_1bab4, + [3662] = { + .class_hid = BNXT_ULP_CLASS_HID_e970, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64680,18 +77752,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3083] = { - .class_hid = BNXT_ULP_CLASS_HID_1fff4, + [3663] = { + .class_hid = BNXT_ULP_CLASS_HID_f42c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64700,18 +77772,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3084] = { - .class_hid = BNXT_ULP_CLASS_HID_1e134, + [3664] = { + .class_hid = BNXT_ULP_CLASS_HID_ef3c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64720,19 +77792,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3085] = { - .class_hid = BNXT_ULP_CLASS_HID_1bca0, + [3665] = { + .class_hid = BNXT_ULP_CLASS_HID_fbcc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64741,16 +77813,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3086] = { - .class_hid = BNXT_ULP_CLASS_HID_1a1e0, + [3666] = { + .class_hid = BNXT_ULP_CLASS_HID_f2dc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64759,17 +77833,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3087] = { - .class_hid = BNXT_ULP_CLASS_HID_1e320, + [3667] = { + .class_hid = BNXT_ULP_CLASS_HID_e188, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64778,17 +77854,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3088] = { - .class_hid = BNXT_ULP_CLASS_HID_1e460, + [3668] = { + .class_hid = BNXT_ULP_CLASS_HID_f898, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64797,18 +77875,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3089] = { - .class_hid = BNXT_ULP_CLASS_HID_aad4, + [3669] = { + .class_hid = BNXT_ULP_CLASS_HID_f294, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64817,16 +77897,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3090] = { - .class_hid = BNXT_ULP_CLASS_HID_ac14, + [3670] = { + .class_hid = BNXT_ULP_CLASS_HID_ede4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64835,17 +77917,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3091] = { - .class_hid = BNXT_ULP_CLASS_HID_d154, + [3671] = { + .class_hid = BNXT_ULP_CLASS_HID_f850, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64854,17 +77938,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3092] = { - .class_hid = BNXT_ULP_CLASS_HID_f294, + [3672] = { + .class_hid = BNXT_ULP_CLASS_HID_f474, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64873,18 +77959,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3093] = { - .class_hid = BNXT_ULP_CLASS_HID_a798, + [3673] = { + .class_hid = BNXT_ULP_CLASS_HID_fc70, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64893,17 +77981,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3094] = { - .class_hid = BNXT_ULP_CLASS_HID_a8d8, + [3674] = { + .class_hid = BNXT_ULP_CLASS_HID_f740, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64912,18 +78002,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3095] = { - .class_hid = BNXT_ULP_CLASS_HID_ea18, + [3675] = { + .class_hid = BNXT_ULP_CLASS_HID_e23c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64932,18 +78024,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3096] = { - .class_hid = BNXT_ULP_CLASS_HID_ef58, + [3676] = { + .class_hid = BNXT_ULP_CLASS_HID_fd0c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64952,19 +78046,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3097] = { - .class_hid = BNXT_ULP_CLASS_HID_1dd98, + [3677] = { + .class_hid = BNXT_ULP_CLASS_HID_4eb34, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64973,18 +78069,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3098] = { - .class_hid = BNXT_ULP_CLASS_HID_1fed8, + [3678] = { + .class_hid = BNXT_ULP_CLASS_HID_4e204, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -64993,19 +78089,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3099] = { - .class_hid = BNXT_ULP_CLASS_HID_1c018, + [3679] = { + .class_hid = BNXT_ULP_CLASS_HID_4f0f0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65014,19 +78110,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3100] = { - .class_hid = BNXT_ULP_CLASS_HID_1e558, + [3680] = { + .class_hid = BNXT_ULP_CLASS_HID_4ebc0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65035,20 +78131,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3101] = { - .class_hid = BNXT_ULP_CLASS_HID_1c0d4, + [3681] = { + .class_hid = BNXT_ULP_CLASS_HID_4f490, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65057,17 +78153,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3102] = { - .class_hid = BNXT_ULP_CLASS_HID_1e214, + [3682] = { + .class_hid = BNXT_ULP_CLASS_HID_4efe0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65076,18 +78174,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3103] = { - .class_hid = BNXT_ULP_CLASS_HID_1c754, + [3683] = { + .class_hid = BNXT_ULP_CLASS_HID_4fa5c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65096,18 +78196,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3104] = { - .class_hid = BNXT_ULP_CLASS_HID_1e894, + [3684] = { + .class_hid = BNXT_ULP_CLASS_HID_4f5ac, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65116,19 +78218,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3105] = { - .class_hid = BNXT_ULP_CLASS_HID_900c, + [3685] = { + .class_hid = BNXT_ULP_CLASS_HID_4ef58, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65137,16 +78241,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3106] = { - .class_hid = BNXT_ULP_CLASS_HID_b54c, + [3686] = { + .class_hid = BNXT_ULP_CLASS_HID_4e6a8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65155,17 +78262,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3107] = { - .class_hid = BNXT_ULP_CLASS_HID_d68c, + [3687] = { + .class_hid = BNXT_ULP_CLASS_HID_4f564, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65174,17 +78284,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3108] = { - .class_hid = BNXT_ULP_CLASS_HID_fbcc, + [3688] = { + .class_hid = BNXT_ULP_CLASS_HID_4f138, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917508, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65193,18 +78306,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3109] = { - .class_hid = BNXT_ULP_CLASS_HID_c80c, + [3689] = { + .class_hid = BNXT_ULP_CLASS_HID_4f904, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65213,17 +78329,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3110] = { - .class_hid = BNXT_ULP_CLASS_HID_ed4c, + [3690] = { + .class_hid = BNXT_ULP_CLASS_HID_4f014, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65232,18 +78351,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3111] = { - .class_hid = BNXT_ULP_CLASS_HID_d350, + [3691] = { + .class_hid = BNXT_ULP_CLASS_HID_4fec0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65252,18 +78374,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3112] = { - .class_hid = BNXT_ULP_CLASS_HID_f490, + [3692] = { + .class_hid = BNXT_ULP_CLASS_HID_4f9d0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 917572, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65272,19 +78397,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3113] = { - .class_hid = BNXT_ULP_CLASS_HID_182d0, + [3693] = { + .class_hid = BNXT_ULP_CLASS_HID_1e460, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65293,18 +78421,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3114] = { - .class_hid = BNXT_ULP_CLASS_HID_1a410, + [3694] = { + .class_hid = BNXT_ULP_CLASS_HID_1ff70, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65313,19 +78441,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3115] = { - .class_hid = BNXT_ULP_CLASS_HID_1c950, + [3695] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea2c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65334,19 +78462,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3116] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea90, + [3696] = { + .class_hid = BNXT_ULP_CLASS_HID_1e53c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65355,20 +78483,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3117] = { - .class_hid = BNXT_ULP_CLASS_HID_1860c, + [3697] = { + .class_hid = BNXT_ULP_CLASS_HID_1f1cc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65377,17 +78505,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3118] = { - .class_hid = BNXT_ULP_CLASS_HID_1ab4c, + [3698] = { + .class_hid = BNXT_ULP_CLASS_HID_1e8dc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65396,18 +78526,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3119] = { - .class_hid = BNXT_ULP_CLASS_HID_1cc8c, + [3699] = { + .class_hid = BNXT_ULP_CLASS_HID_1f788, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65416,18 +78548,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3120] = { - .class_hid = BNXT_ULP_CLASS_HID_1f1cc, + [3700] = { + .class_hid = BNXT_ULP_CLASS_HID_1ee98, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65436,19 +78570,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3121] = { - .class_hid = BNXT_ULP_CLASS_HID_b4b0, + [3701] = { + .class_hid = BNXT_ULP_CLASS_HID_1e894, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65457,17 +78593,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3122] = { - .class_hid = BNXT_ULP_CLASS_HID_b9f0, + [3702] = { + .class_hid = BNXT_ULP_CLASS_HID_1e4a8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65476,18 +78614,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3123] = { - .class_hid = BNXT_ULP_CLASS_HID_fb30, + [3703] = { + .class_hid = BNXT_ULP_CLASS_HID_1f364, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65496,18 +78636,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3124] = { - .class_hid = BNXT_ULP_CLASS_HID_fc70, + [3704] = { + .class_hid = BNXT_ULP_CLASS_HID_1ea74, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65516,19 +78658,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3125] = { - .class_hid = BNXT_ULP_CLASS_HID_b144, + [3705] = { + .class_hid = BNXT_ULP_CLASS_HID_1f270, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65537,18 +78681,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3126] = { - .class_hid = BNXT_ULP_CLASS_HID_b284, + [3706] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed40, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65557,19 +78703,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3127] = { - .class_hid = BNXT_ULP_CLASS_HID_f7c4, + [3707] = { + .class_hid = BNXT_ULP_CLASS_HID_1f83c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65578,19 +78726,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3128] = { - .class_hid = BNXT_ULP_CLASS_HID_f904, + [3708] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7d0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65599,20 +78749,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3129] = { - .class_hid = BNXT_ULP_CLASS_HID_1a744, + [3709] = { + .class_hid = BNXT_ULP_CLASS_HID_5e134, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65621,19 +78773,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3130] = { - .class_hid = BNXT_ULP_CLASS_HID_1a884, + [3710] = { + .class_hid = BNXT_ULP_CLASS_HID_5f804, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65642,20 +78794,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3131] = { - .class_hid = BNXT_ULP_CLASS_HID_1edc4, + [3711] = { + .class_hid = BNXT_ULP_CLASS_HID_5e6f0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65664,20 +78816,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3132] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef04, + [3712] = { + .class_hid = BNXT_ULP_CLASS_HID_5e1c0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983044, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65686,21 +78838,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3133] = { - .class_hid = BNXT_ULP_CLASS_HID_1aab0, + [3713] = { + .class_hid = BNXT_ULP_CLASS_HID_5ea90, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65709,18 +78861,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3134] = { - .class_hid = BNXT_ULP_CLASS_HID_1aff0, + [3714] = { + .class_hid = BNXT_ULP_CLASS_HID_5e5e0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65729,19 +78883,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3135] = { - .class_hid = BNXT_ULP_CLASS_HID_1d130, + [3715] = { + .class_hid = BNXT_ULP_CLASS_HID_5f05c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65750,19 +78906,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3136] = { - .class_hid = BNXT_ULP_CLASS_HID_1f270, + [3716] = { + .class_hid = BNXT_ULP_CLASS_HID_5ebac, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 11, + .flow_sig_id = 983108, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -65771,21 +78929,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3137] = { - .class_hid = BNXT_ULP_CLASS_HID_80e4, + [3717] = { + .class_hid = BNXT_ULP_CLASS_HID_5e558, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -65793,16 +78953,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3138] = { - .class_hid = BNXT_ULP_CLASS_HID_a224, + [3718] = { + .class_hid = BNXT_ULP_CLASS_HID_5e17c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983044, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -65810,17 +78975,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3139] = { - .class_hid = BNXT_ULP_CLASS_HID_c764, + [3719] = { + .class_hid = BNXT_ULP_CLASS_HID_5eb64, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -65828,17 +78998,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3140] = { - .class_hid = BNXT_ULP_CLASS_HID_e8a4, + [3720] = { + .class_hid = BNXT_ULP_CLASS_HID_5e738, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983044, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -65846,18 +79021,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3141] = { - .class_hid = BNXT_ULP_CLASS_HID_9da8, + [3721] = { + .class_hid = BNXT_ULP_CLASS_HID_5ef04, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -65865,17 +79045,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3142] = { - .class_hid = BNXT_ULP_CLASS_HID_bee8, + [3722] = { + .class_hid = BNXT_ULP_CLASS_HID_5e614, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983108, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -65883,18 +79068,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3143] = { - .class_hid = BNXT_ULP_CLASS_HID_c028, + [3723] = { + .class_hid = BNXT_ULP_CLASS_HID_5f4c0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -65902,18 +79092,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3144] = { - .class_hid = BNXT_ULP_CLASS_HID_e568, + [3724] = { + .class_hid = BNXT_ULP_CLASS_HID_5f0e4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 1, + .hdr_sig_id = 11, + .flow_sig_id = 983108, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -65921,4027 +79116,3632 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3145] = { - .class_hid = BNXT_ULP_CLASS_HID_1b3a8, + [3725] = { + .class_hid = BNXT_ULP_CLASS_HID_5802, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 0, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3146] = { - .class_hid = BNXT_ULP_CLASS_HID_1b4e8, + [3726] = { + .class_hid = BNXT_ULP_CLASS_HID_5e46, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 0, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3147] = { - .class_hid = BNXT_ULP_CLASS_HID_1f628, + [3727] = { + .class_hid = BNXT_ULP_CLASS_HID_1d76, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 0, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3148] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb68, + [3728] = { + .class_hid = BNXT_ULP_CLASS_HID_02ba, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 0, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3149] = { - .class_hid = BNXT_ULP_CLASS_HID_1b6e4, + [3729] = { + .class_hid = BNXT_ULP_CLASS_HID_32a2, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 0, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3150] = { - .class_hid = BNXT_ULP_CLASS_HID_1b824, + [3730] = { + .class_hid = BNXT_ULP_CLASS_HID_38e6, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 0, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3151] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd64, + [3731] = { + .class_hid = BNXT_ULP_CLASS_HID_52ca, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 0, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3152] = { - .class_hid = BNXT_ULP_CLASS_HID_1fea4, + [3732] = { + .class_hid = BNXT_ULP_CLASS_HID_580e, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 0, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3153] = { - .class_hid = BNXT_ULP_CLASS_HID_a508, + [3733] = { + .class_hid = BNXT_ULP_CLASS_HID_44996, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 1, + .flow_sig_id = 16384, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3154] = { - .class_hid = BNXT_ULP_CLASS_HID_a648, + [3734] = { + .class_hid = BNXT_ULP_CLASS_HID_410e6, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 1, + .flow_sig_id = 16384, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3155] = { - .class_hid = BNXT_ULP_CLASS_HID_eb88, + [3735] = { + .class_hid = BNXT_ULP_CLASS_HID_42036, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 1, + .flow_sig_id = 16384, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3156] = { - .class_hid = BNXT_ULP_CLASS_HID_ecc8, + [3736] = { + .class_hid = BNXT_ULP_CLASS_HID_4264a, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 1, + .flow_sig_id = 16384, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3157] = { - .class_hid = BNXT_ULP_CLASS_HID_a1dc, + [3737] = { + .class_hid = BNXT_ULP_CLASS_HID_45ffe, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 1, + .flow_sig_id = 24576, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3158] = { - .class_hid = BNXT_ULP_CLASS_HID_a31c, + [3738] = { + .class_hid = BNXT_ULP_CLASS_HID_44532, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 1, + .flow_sig_id = 24576, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3159] = { - .class_hid = BNXT_ULP_CLASS_HID_e45c, + [3739] = { + .class_hid = BNXT_ULP_CLASS_HID_4399e, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 1, + .flow_sig_id = 24576, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3160] = { - .class_hid = BNXT_ULP_CLASS_HID_e99c, + [3740] = { + .class_hid = BNXT_ULP_CLASS_HID_43fd2, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 1, + .flow_sig_id = 24576, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3161] = { - .class_hid = BNXT_ULP_CLASS_HID_1d7dc, + [3741] = { + .class_hid = BNXT_ULP_CLASS_HID_23da0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3162] = { - .class_hid = BNXT_ULP_CLASS_HID_1f91c, + [3742] = { + .class_hid = BNXT_ULP_CLASS_HID_2239c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3163] = { - .class_hid = BNXT_ULP_CLASS_HID_1da5c, + [3743] = { + .class_hid = BNXT_ULP_CLASS_HID_207fc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3164] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff9c, + [3744] = { + .class_hid = BNXT_ULP_CLASS_HID_20d38, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3165] = { - .class_hid = BNXT_ULP_CLASS_HID_1db08, + [3745] = { + .class_hid = BNXT_ULP_CLASS_HID_25e34, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3166] = { - .class_hid = BNXT_ULP_CLASS_HID_1fc48, + [3746] = { + .class_hid = BNXT_ULP_CLASS_HID_24470, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3167] = { - .class_hid = BNXT_ULP_CLASS_HID_1c188, + [3747] = { + .class_hid = BNXT_ULP_CLASS_HID_22850, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3168] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2c8, + [3748] = { + .class_hid = BNXT_ULP_CLASS_HID_2518c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3169] = { - .class_hid = BNXT_ULP_CLASS_HID_9ad8, + [3749] = { + .class_hid = BNXT_ULP_CLASS_HID_20970, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3170] = { - .class_hid = BNXT_ULP_CLASS_HID_bc18, + [3750] = { + .class_hid = BNXT_ULP_CLASS_HID_20eac, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3171] = { - .class_hid = BNXT_ULP_CLASS_HID_c158, + [3751] = { + .class_hid = BNXT_ULP_CLASS_HID_2128c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3172] = { - .class_hid = BNXT_ULP_CLASS_HID_e298, + [3752] = { + .class_hid = BNXT_ULP_CLASS_HID_218c8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3173] = { - .class_hid = BNXT_ULP_CLASS_HID_97ec, + [3753] = { + .class_hid = BNXT_ULP_CLASS_HID_22dc4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3174] = { - .class_hid = BNXT_ULP_CLASS_HID_b92c, + [3754] = { + .class_hid = BNXT_ULP_CLASS_HID_25300, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3175] = { - .class_hid = BNXT_ULP_CLASS_HID_da6c, + [3755] = { + .class_hid = BNXT_ULP_CLASS_HID_23760, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3176] = { - .class_hid = BNXT_ULP_CLASS_HID_ffac, + [3756] = { + .class_hid = BNXT_ULP_CLASS_HID_23d5c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3177] = { - .class_hid = BNXT_ULP_CLASS_HID_18dec, + [3757] = { + .class_hid = BNXT_ULP_CLASS_HID_63694, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3178] = { - .class_hid = BNXT_ULP_CLASS_HID_1af2c, + [3758] = { + .class_hid = BNXT_ULP_CLASS_HID_63cd0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3179] = { - .class_hid = BNXT_ULP_CLASS_HID_1f06c, + [3759] = { + .class_hid = BNXT_ULP_CLASS_HID_60030, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3180] = { - .class_hid = BNXT_ULP_CLASS_HID_1f5ac, + [3760] = { + .class_hid = BNXT_ULP_CLASS_HID_6066c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3181] = { - .class_hid = BNXT_ULP_CLASS_HID_1b0d8, + [3761] = { + .class_hid = BNXT_ULP_CLASS_HID_65b68, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3182] = { - .class_hid = BNXT_ULP_CLASS_HID_1b218, + [3762] = { + .class_hid = BNXT_ULP_CLASS_HID_640a4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3183] = { - .class_hid = BNXT_ULP_CLASS_HID_1f758, + [3763] = { + .class_hid = BNXT_ULP_CLASS_HID_62484, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3184] = { - .class_hid = BNXT_ULP_CLASS_HID_1f898, + [3764] = { + .class_hid = BNXT_ULP_CLASS_HID_62ac0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3185] = { - .class_hid = BNXT_ULP_CLASS_HID_bf4c, + [3765] = { + .class_hid = BNXT_ULP_CLASS_HID_605a4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3186] = { - .class_hid = BNXT_ULP_CLASS_HID_a08c, + [3766] = { + .class_hid = BNXT_ULP_CLASS_HID_60be0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3187] = { - .class_hid = BNXT_ULP_CLASS_HID_e5cc, + [3767] = { + .class_hid = BNXT_ULP_CLASS_HID_64a8c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3188] = { - .class_hid = BNXT_ULP_CLASS_HID_e70c, + [3768] = { + .class_hid = BNXT_ULP_CLASS_HID_6153c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3189] = { - .class_hid = BNXT_ULP_CLASS_HID_b810, + [3769] = { + .class_hid = BNXT_ULP_CLASS_HID_62638, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3190] = { - .class_hid = BNXT_ULP_CLASS_HID_bd50, + [3770] = { + .class_hid = BNXT_ULP_CLASS_HID_62c74, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3191] = { - .class_hid = BNXT_ULP_CLASS_HID_fe90, + [3771] = { + .class_hid = BNXT_ULP_CLASS_HID_63054, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3192] = { - .class_hid = BNXT_ULP_CLASS_HID_e3d0, + [3772] = { + .class_hid = BNXT_ULP_CLASS_HID_63990, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3193] = { - .class_hid = BNXT_ULP_CLASS_HID_1ae10, + [3773] = { + .class_hid = BNXT_ULP_CLASS_HID_9a98, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 3, + .flow_sig_id = 131072, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3194] = { - .class_hid = BNXT_ULP_CLASS_HID_1f350, + [3774] = { + .class_hid = BNXT_ULP_CLASS_HID_80a4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 3, + .flow_sig_id = 131072, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3195] = { - .class_hid = BNXT_ULP_CLASS_HID_1d490, + [3775] = { + .class_hid = BNXT_ULP_CLASS_HID_c3b0, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 3, + .flow_sig_id = 131136, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3196] = { - .class_hid = BNXT_ULP_CLASS_HID_1f9d0, + [3776] = { + .class_hid = BNXT_ULP_CLASS_HID_c9fc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 3, + .flow_sig_id = 131136, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3197] = { - .class_hid = BNXT_ULP_CLASS_HID_1d54c, + [3777] = { + .class_hid = BNXT_ULP_CLASS_HID_bf0c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 3, + .flow_sig_id = 131072, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3198] = { - .class_hid = BNXT_ULP_CLASS_HID_1f68c, + [3778] = { + .class_hid = BNXT_ULP_CLASS_HID_a548, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 3, + .flow_sig_id = 131072, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3199] = { - .class_hid = BNXT_ULP_CLASS_HID_1dbcc, + [3779] = { + .class_hid = BNXT_ULP_CLASS_HID_8968, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 3, + .flow_sig_id = 131136, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3200] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd0c, + [3780] = { + .class_hid = BNXT_ULP_CLASS_HID_8eb4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, + .hdr_sig_id = 3, + .flow_sig_id = 131136, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3201] = { - .class_hid = BNXT_ULP_CLASS_HID_34b0, + [3781] = { + .class_hid = BNXT_ULP_CLASS_HID_497ac, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3202] = { - .class_hid = BNXT_ULP_CLASS_HID_3a7c, + [3782] = { + .class_hid = BNXT_ULP_CLASS_HID_49de8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3203] = { - .class_hid = BNXT_ULP_CLASS_HID_3700, + [3783] = { + .class_hid = BNXT_ULP_CLASS_HID_4dcc4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3204] = { - .class_hid = BNXT_ULP_CLASS_HID_5ee0, + [3784] = { + .class_hid = BNXT_ULP_CLASS_HID_4c200, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3205] = { - .class_hid = BNXT_ULP_CLASS_HID_5bb4, + [3785] = { + .class_hid = BNXT_ULP_CLASS_HID_4b850, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3206] = { - .class_hid = BNXT_ULP_CLASS_HID_07d8, + [3786] = { + .class_hid = BNXT_ULP_CLASS_HID_4a19c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3207] = { - .class_hid = BNXT_ULP_CLASS_HID_00ec, + [3787] = { + .class_hid = BNXT_ULP_CLASS_HID_485bc, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3208] = { - .class_hid = BNXT_ULP_CLASS_HID_284c, + [3788] = { + .class_hid = BNXT_ULP_CLASS_HID_48bf8, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3209] = { - .class_hid = BNXT_ULP_CLASS_HID_2510, + [3789] = { + .class_hid = BNXT_ULP_CLASS_HID_1b098, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3210] = { - .class_hid = BNXT_ULP_CLASS_HID_3144, + [3790] = { + .class_hid = BNXT_ULP_CLASS_HID_1b6a4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3211] = { - .class_hid = BNXT_ULP_CLASS_HID_5924, + [3791] = { + .class_hid = BNXT_ULP_CLASS_HID_19ac4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3212] = { - .class_hid = BNXT_ULP_CLASS_HID_55e8, + [3792] = { + .class_hid = BNXT_ULP_CLASS_HID_18000, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3213] = { - .class_hid = BNXT_ULP_CLASS_HID_1e1c, + [3793] = { + .class_hid = BNXT_ULP_CLASS_HID_1d50c, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3214] = { - .class_hid = BNXT_ULP_CLASS_HID_1b20, + [3794] = { + .class_hid = BNXT_ULP_CLASS_HID_1db48, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3215] = { - .class_hid = BNXT_ULP_CLASS_HID_2280, + [3795] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf68, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3216] = { - .class_hid = BNXT_ULP_CLASS_HID_3f54, + [3796] = { + .class_hid = BNXT_ULP_CLASS_HID_1a4b4, .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 256, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3217] = { - .class_hid = BNXT_ULP_CLASS_HID_24604, + [3797] = { + .class_hid = BNXT_ULP_CLASS_HID_58dac, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3218] = { - .class_hid = BNXT_ULP_CLASS_HID_255d4, + [3798] = { + .class_hid = BNXT_ULP_CLASS_HID_5b3e8, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3219] = { - .class_hid = BNXT_ULP_CLASS_HID_22e08, + [3799] = { + .class_hid = BNXT_ULP_CLASS_HID_59708, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3220] = { - .class_hid = BNXT_ULP_CLASS_HID_24378, + [3800] = { + .class_hid = BNXT_ULP_CLASS_HID_59d54, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3221] = { - .class_hid = BNXT_ULP_CLASS_HID_20fcc, + [3801] = { + .class_hid = BNXT_ULP_CLASS_HID_5ae50, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3222] = { - .class_hid = BNXT_ULP_CLASS_HID_21a9c, + [3802] = { + .class_hid = BNXT_ULP_CLASS_HID_5d79c, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3223] = { - .class_hid = BNXT_ULP_CLASS_HID_217d0, + [3803] = { + .class_hid = BNXT_ULP_CLASS_HID_5bbbc, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3224] = { - .class_hid = BNXT_ULP_CLASS_HID_20800, + [3804] = { + .class_hid = BNXT_ULP_CLASS_HID_5a1f8, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3225] = { - .class_hid = BNXT_ULP_CLASS_HID_253a0, + [3805] = { + .class_hid = BNXT_ULP_CLASS_HID_5822, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 256, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3226] = { - .class_hid = BNXT_ULP_CLASS_HID_23f70, + [3806] = { + .class_hid = BNXT_ULP_CLASS_HID_5e66, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 257, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3227] = { - .class_hid = BNXT_ULP_CLASS_HID_23ba4, + [3807] = { + .class_hid = BNXT_ULP_CLASS_HID_1d56, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 257, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3228] = { - .class_hid = BNXT_ULP_CLASS_HID_22c94, + [3808] = { + .class_hid = BNXT_ULP_CLASS_HID_029a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3229] = { - .class_hid = BNXT_ULP_CLASS_HID_21968, + [3809] = { + .class_hid = BNXT_ULP_CLASS_HID_3282, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3230] = { - .class_hid = BNXT_ULP_CLASS_HID_243c4, + [3810] = { + .class_hid = BNXT_ULP_CLASS_HID_38c6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3231] = { - .class_hid = BNXT_ULP_CLASS_HID_25c38, + [3811] = { + .class_hid = BNXT_ULP_CLASS_HID_52ea, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3232] = { - .class_hid = BNXT_ULP_CLASS_HID_2125c, + [3812] = { + .class_hid = BNXT_ULP_CLASS_HID_582e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3233] = { - .class_hid = BNXT_ULP_CLASS_HID_240c8, + [3813] = { + .class_hid = BNXT_ULP_CLASS_HID_51ba, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3234] = { - .class_hid = BNXT_ULP_CLASS_HID_22f98, + [3814] = { + .class_hid = BNXT_ULP_CLASS_HID_57fe, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3235] = { - .class_hid = BNXT_ULP_CLASS_HID_228cc, + [3815] = { + .class_hid = BNXT_ULP_CLASS_HID_12ee, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3236] = { - .class_hid = BNXT_ULP_CLASS_HID_25d3c, + [3816] = { + .class_hid = BNXT_ULP_CLASS_HID_1832, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3237] = { - .class_hid = BNXT_ULP_CLASS_HID_20990, + [3817] = { + .class_hid = BNXT_ULP_CLASS_HID_081a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3238] = { - .class_hid = BNXT_ULP_CLASS_HID_214a0, + [3818] = { + .class_hid = BNXT_ULP_CLASS_HID_0e5e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3239] = { - .class_hid = BNXT_ULP_CLASS_HID_21194, + [3819] = { + .class_hid = BNXT_ULP_CLASS_HID_2802, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3240] = { - .class_hid = BNXT_ULP_CLASS_HID_202c4, + [3820] = { + .class_hid = BNXT_ULP_CLASS_HID_2e46, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3241] = { - .class_hid = BNXT_ULP_CLASS_HID_22a64, + [3821] = { + .class_hid = BNXT_ULP_CLASS_HID_4556e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3242] = { - .class_hid = BNXT_ULP_CLASS_HID_23934, + [3822] = { + .class_hid = BNXT_ULP_CLASS_HID_45ab2, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3243] = { - .class_hid = BNXT_ULP_CLASS_HID_23268, + [3823] = { + .class_hid = BNXT_ULP_CLASS_HID_419a2, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3244] = { - .class_hid = BNXT_ULP_CLASS_HID_22758, + [3824] = { + .class_hid = BNXT_ULP_CLASS_HID_41fe6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3245] = { - .class_hid = BNXT_ULP_CLASS_HID_2132c, + [3825] = { + .class_hid = BNXT_ULP_CLASS_HID_40fce, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3246] = { - .class_hid = BNXT_ULP_CLASS_HID_25d88, + [3826] = { + .class_hid = BNXT_ULP_CLASS_HID_43512, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3247] = { - .class_hid = BNXT_ULP_CLASS_HID_256fc, + [3827] = { + .class_hid = BNXT_ULP_CLASS_HID_42f36, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3248] = { - .class_hid = BNXT_ULP_CLASS_HID_24b2c, + [3828] = { + .class_hid = BNXT_ULP_CLASS_HID_4557a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3249] = { - .class_hid = BNXT_ULP_CLASS_HID_22f14, + [3829] = { + .class_hid = BNXT_ULP_CLASS_HID_42a86, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3250] = { - .class_hid = BNXT_ULP_CLASS_HID_23a24, + [3830] = { + .class_hid = BNXT_ULP_CLASS_HID_450ca, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3251] = { - .class_hid = BNXT_ULP_CLASS_HID_23718, + [3831] = { + .class_hid = BNXT_ULP_CLASS_HID_44aee, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3252] = { - .class_hid = BNXT_ULP_CLASS_HID_22848, + [3832] = { + .class_hid = BNXT_ULP_CLASS_HID_4157e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3253] = { - .class_hid = BNXT_ULP_CLASS_HID_214dc, + [3833] = { + .class_hid = BNXT_ULP_CLASS_HID_40566, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3254] = { - .class_hid = BNXT_ULP_CLASS_HID_25eb8, + [3834] = { + .class_hid = BNXT_ULP_CLASS_HID_40aaa, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3255] = { - .class_hid = BNXT_ULP_CLASS_HID_25bec, + [3835] = { + .class_hid = BNXT_ULP_CLASS_HID_4254e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3256] = { - .class_hid = BNXT_ULP_CLASS_HID_21110, + [3836] = { + .class_hid = BNXT_ULP_CLASS_HID_42a92, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3257] = { - .class_hid = BNXT_ULP_CLASS_HID_238b0, + [3837] = { + .class_hid = BNXT_ULP_CLASS_HID_449b6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 258, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3258] = { - .class_hid = BNXT_ULP_CLASS_HID_20440, + [3838] = { + .class_hid = BNXT_ULP_CLASS_HID_410c6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 259, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3259] = { - .class_hid = BNXT_ULP_CLASS_HID_200b4, + [3839] = { + .class_hid = BNXT_ULP_CLASS_HID_42016, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 259, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3260] = { - .class_hid = BNXT_ULP_CLASS_HID_235e4, + [3840] = { + .class_hid = BNXT_ULP_CLASS_HID_4266a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3261] = { - .class_hid = BNXT_ULP_CLASS_HID_25d04, + [3841] = { + .class_hid = BNXT_ULP_CLASS_HID_45fde, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3262] = { - .class_hid = BNXT_ULP_CLASS_HID_228d4, + [3842] = { + .class_hid = BNXT_ULP_CLASS_HID_44512, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3263] = { - .class_hid = BNXT_ULP_CLASS_HID_22508, + [3843] = { + .class_hid = BNXT_ULP_CLASS_HID_439be, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3264] = { - .class_hid = BNXT_ULP_CLASS_HID_25678, + [3844] = { + .class_hid = BNXT_ULP_CLASS_HID_43ff2, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3265] = { - .class_hid = BNXT_ULP_CLASS_HID_229d8, + [3845] = { + .class_hid = BNXT_ULP_CLASS_HID_63682, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3266] = { - .class_hid = BNXT_ULP_CLASS_HID_234e8, + [3846] = { + .class_hid = BNXT_ULP_CLASS_HID_63cc6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3267] = { - .class_hid = BNXT_ULP_CLASS_HID_231dc, + [3847] = { + .class_hid = BNXT_ULP_CLASS_HID_61162, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3268] = { - .class_hid = BNXT_ULP_CLASS_HID_2220c, + [3848] = { + .class_hid = BNXT_ULP_CLASS_HID_616a6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3269] = { - .class_hid = BNXT_ULP_CLASS_HID_24dac, + [3849] = { + .class_hid = BNXT_ULP_CLASS_HID_60c2a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3270] = { - .class_hid = BNXT_ULP_CLASS_HID_2597c, + [3850] = { + .class_hid = BNXT_ULP_CLASS_HID_6326e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3271] = { - .class_hid = BNXT_ULP_CLASS_HID_255b0, + [3851] = { + .class_hid = BNXT_ULP_CLASS_HID_645be, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3272] = { - .class_hid = BNXT_ULP_CLASS_HID_246e0, + [3852] = { + .class_hid = BNXT_ULP_CLASS_HID_64bf2, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3273] = { - .class_hid = BNXT_ULP_CLASS_HID_23374, + [3853] = { + .class_hid = BNXT_ULP_CLASS_HID_50082, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3274] = { - .class_hid = BNXT_ULP_CLASS_HID_21e04, + [3854] = { + .class_hid = BNXT_ULP_CLASS_HID_506c6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3275] = { - .class_hid = BNXT_ULP_CLASS_HID_21b78, + [3855] = { + .class_hid = BNXT_ULP_CLASS_HID_55616, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3276] = { - .class_hid = BNXT_ULP_CLASS_HID_20fa8, + [3856] = { + .class_hid = BNXT_ULP_CLASS_HID_55c6a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3277] = { - .class_hid = BNXT_ULP_CLASS_HID_257c8, + [3857] = { + .class_hid = BNXT_ULP_CLASS_HID_5162a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3278] = { - .class_hid = BNXT_ULP_CLASS_HID_22298, + [3858] = { + .class_hid = BNXT_ULP_CLASS_HID_51c6e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3279] = { - .class_hid = BNXT_ULP_CLASS_HID_23fcc, + [3859] = { + .class_hid = BNXT_ULP_CLASS_HID_52fbe, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3280] = { - .class_hid = BNXT_ULP_CLASS_HID_2503c, + [3860] = { + .class_hid = BNXT_ULP_CLASS_HID_555f2, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3281] = { - .class_hid = BNXT_ULP_CLASS_HID_2239c, + [3861] = { + .class_hid = BNXT_ULP_CLASS_HID_72c82, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3282] = { - .class_hid = BNXT_ULP_CLASS_HID_20eac, + [3862] = { + .class_hid = BNXT_ULP_CLASS_HID_752c6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3283] = { - .class_hid = BNXT_ULP_CLASS_HID_20be0, + [3863] = { + .class_hid = BNXT_ULP_CLASS_HID_70762, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3284] = { - .class_hid = BNXT_ULP_CLASS_HID_23cd0, + [3864] = { + .class_hid = BNXT_ULP_CLASS_HID_70ca6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3285] = { - .class_hid = BNXT_ULP_CLASS_HID_24470, + [3865] = { + .class_hid = BNXT_ULP_CLASS_HID_7222a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3286] = { - .class_hid = BNXT_ULP_CLASS_HID_25300, + [3866] = { + .class_hid = BNXT_ULP_CLASS_HID_7286e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3287] = { - .class_hid = BNXT_ULP_CLASS_HID_22c74, + [3867] = { + .class_hid = BNXT_ULP_CLASS_HID_71c8a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3288] = { - .class_hid = BNXT_ULP_CLASS_HID_240a4, + [3868] = { + .class_hid = BNXT_ULP_CLASS_HID_702ce, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3289] = { - .class_hid = BNXT_ULP_CLASS_HID_23da0, + [3869] = { + .class_hid = BNXT_ULP_CLASS_HID_5842, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3290] = { - .class_hid = BNXT_ULP_CLASS_HID_20970, + [3870] = { + .class_hid = BNXT_ULP_CLASS_HID_5e06, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3291] = { - .class_hid = BNXT_ULP_CLASS_HID_205a4, + [3871] = { + .class_hid = BNXT_ULP_CLASS_HID_1d36, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3292] = { - .class_hid = BNXT_ULP_CLASS_HID_23694, + [3872] = { + .class_hid = BNXT_ULP_CLASS_HID_02fa, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3293] = { - .class_hid = BNXT_ULP_CLASS_HID_25e34, + [3873] = { + .class_hid = BNXT_ULP_CLASS_HID_32e2, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3294] = { - .class_hid = BNXT_ULP_CLASS_HID_22dc4, + [3874] = { + .class_hid = BNXT_ULP_CLASS_HID_38a6, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3295] = { - .class_hid = BNXT_ULP_CLASS_HID_22638, + [3875] = { + .class_hid = BNXT_ULP_CLASS_HID_528a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3296] = { - .class_hid = BNXT_ULP_CLASS_HID_25b68, + [3876] = { + .class_hid = BNXT_ULP_CLASS_HID_584e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3297] = { - .class_hid = BNXT_ULP_CLASS_HID_34c8, + [3877] = { + .class_hid = BNXT_ULP_CLASS_HID_51da, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3298] = { - .class_hid = BNXT_ULP_CLASS_HID_3a04, + [3878] = { + .class_hid = BNXT_ULP_CLASS_HID_579e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3299] = { - .class_hid = BNXT_ULP_CLASS_HID_09d4, + [3879] = { + .class_hid = BNXT_ULP_CLASS_HID_128e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3300] = { - .class_hid = BNXT_ULP_CLASS_HID_5e98, + [3880] = { + .class_hid = BNXT_ULP_CLASS_HID_1852, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3301] = { - .class_hid = BNXT_ULP_CLASS_HID_2da8, + [3881] = { + .class_hid = BNXT_ULP_CLASS_HID_087a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3302] = { - .class_hid = BNXT_ULP_CLASS_HID_07a0, + [3882] = { + .class_hid = BNXT_ULP_CLASS_HID_0e3e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3303] = { - .class_hid = BNXT_ULP_CLASS_HID_1370, + [3883] = { + .class_hid = BNXT_ULP_CLASS_HID_2862, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3304] = { - .class_hid = BNXT_ULP_CLASS_HID_2834, + [3884] = { + .class_hid = BNXT_ULP_CLASS_HID_2e26, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3305] = { - .class_hid = BNXT_ULP_CLASS_HID_37c4, + [3885] = { + .class_hid = BNXT_ULP_CLASS_HID_4550e, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3306] = { - .class_hid = BNXT_ULP_CLASS_HID_0398, + [3886] = { + .class_hid = BNXT_ULP_CLASS_HID_45ad2, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3307] = { - .class_hid = BNXT_ULP_CLASS_HID_595c, + [3887] = { + .class_hid = BNXT_ULP_CLASS_HID_419c2, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3308] = { - .class_hid = BNXT_ULP_CLASS_HID_246c, + [3888] = { + .class_hid = BNXT_ULP_CLASS_HID_41f86, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3309] = { - .class_hid = BNXT_ULP_CLASS_HID_1e64, + [3889] = { + .class_hid = BNXT_ULP_CLASS_HID_40fae, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3310] = { - .class_hid = BNXT_ULP_CLASS_HID_48c0, + [3890] = { + .class_hid = BNXT_ULP_CLASS_HID_43572, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3311] = { - .class_hid = BNXT_ULP_CLASS_HID_22f8, + [3891] = { + .class_hid = BNXT_ULP_CLASS_HID_42f56, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3312] = { - .class_hid = BNXT_ULP_CLASS_HID_3188, + [3892] = { + .class_hid = BNXT_ULP_CLASS_HID_4551a, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 260, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3313] = { - .class_hid = BNXT_ULP_CLASS_HID_24664, + [3893] = { + .class_hid = BNXT_ULP_CLASS_HID_42ae6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3314] = { - .class_hid = BNXT_ULP_CLASS_HID_29418, + [3894] = { + .class_hid = BNXT_ULP_CLASS_HID_450aa, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3315] = { - .class_hid = BNXT_ULP_CLASS_HID_30118, + [3895] = { + .class_hid = BNXT_ULP_CLASS_HID_44a8e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3316] = { - .class_hid = BNXT_ULP_CLASS_HID_38a18, + [3896] = { + .class_hid = BNXT_ULP_CLASS_HID_4151e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3317] = { - .class_hid = BNXT_ULP_CLASS_HID_255b4, + [3897] = { + .class_hid = BNXT_ULP_CLASS_HID_40506, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3318] = { - .class_hid = BNXT_ULP_CLASS_HID_2deb4, + [3898] = { + .class_hid = BNXT_ULP_CLASS_HID_40aca, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3319] = { - .class_hid = BNXT_ULP_CLASS_HID_34bb4, + [3899] = { + .class_hid = BNXT_ULP_CLASS_HID_4252e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3320] = { - .class_hid = BNXT_ULP_CLASS_HID_39968, + [3900] = { + .class_hid = BNXT_ULP_CLASS_HID_42af2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3321] = { - .class_hid = BNXT_ULP_CLASS_HID_22e68, + [3901] = { + .class_hid = BNXT_ULP_CLASS_HID_449d6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3322] = { - .class_hid = BNXT_ULP_CLASS_HID_2db68, + [3902] = { + .class_hid = BNXT_ULP_CLASS_HID_410a6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3323] = { - .class_hid = BNXT_ULP_CLASS_HID_34468, + [3903] = { + .class_hid = BNXT_ULP_CLASS_HID_42076, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3324] = { - .class_hid = BNXT_ULP_CLASS_HID_3921c, + [3904] = { + .class_hid = BNXT_ULP_CLASS_HID_4260a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3325] = { - .class_hid = BNXT_ULP_CLASS_HID_24318, + [3905] = { + .class_hid = BNXT_ULP_CLASS_HID_45fbe, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3326] = { - .class_hid = BNXT_ULP_CLASS_HID_290cc, + [3906] = { + .class_hid = BNXT_ULP_CLASS_HID_44572, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3327] = { - .class_hid = BNXT_ULP_CLASS_HID_31dcc, + [3907] = { + .class_hid = BNXT_ULP_CLASS_HID_439de, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3328] = { - .class_hid = BNXT_ULP_CLASS_HID_386cc, + [3908] = { + .class_hid = BNXT_ULP_CLASS_HID_43f92, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3329] = { - .class_hid = BNXT_ULP_CLASS_HID_20fac, + [3909] = { + .class_hid = BNXT_ULP_CLASS_HID_636e2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3330] = { - .class_hid = BNXT_ULP_CLASS_HID_2b8ac, + [3910] = { + .class_hid = BNXT_ULP_CLASS_HID_63ca6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3331] = { - .class_hid = BNXT_ULP_CLASS_HID_325ac, + [3911] = { + .class_hid = BNXT_ULP_CLASS_HID_61102, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3332] = { - .class_hid = BNXT_ULP_CLASS_HID_3aeac, + [3912] = { + .class_hid = BNXT_ULP_CLASS_HID_616c6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3333] = { - .class_hid = BNXT_ULP_CLASS_HID_21afc, + [3913] = { + .class_hid = BNXT_ULP_CLASS_HID_60c4a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3334] = { - .class_hid = BNXT_ULP_CLASS_HID_287fc, + [3914] = { + .class_hid = BNXT_ULP_CLASS_HID_6320e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3335] = { - .class_hid = BNXT_ULP_CLASS_HID_330fc, + [3915] = { + .class_hid = BNXT_ULP_CLASS_HID_645de, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3336] = { - .class_hid = BNXT_ULP_CLASS_HID_3bdfc, + [3916] = { + .class_hid = BNXT_ULP_CLASS_HID_64b92, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3337] = { - .class_hid = BNXT_ULP_CLASS_HID_217b0, + [3917] = { + .class_hid = BNXT_ULP_CLASS_HID_500e2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3338] = { - .class_hid = BNXT_ULP_CLASS_HID_280b0, + [3918] = { + .class_hid = BNXT_ULP_CLASS_HID_506a6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3339] = { - .class_hid = BNXT_ULP_CLASS_HID_30db0, + [3919] = { + .class_hid = BNXT_ULP_CLASS_HID_55676, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3340] = { - .class_hid = BNXT_ULP_CLASS_HID_3b6b0, + [3920] = { + .class_hid = BNXT_ULP_CLASS_HID_55c0a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3341] = { - .class_hid = BNXT_ULP_CLASS_HID_20860, + [3921] = { + .class_hid = BNXT_ULP_CLASS_HID_5164a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3342] = { - .class_hid = BNXT_ULP_CLASS_HID_2b560, + [3922] = { + .class_hid = BNXT_ULP_CLASS_HID_51c0e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3343] = { - .class_hid = BNXT_ULP_CLASS_HID_33e60, + [3923] = { + .class_hid = BNXT_ULP_CLASS_HID_52fde, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3344] = { - .class_hid = BNXT_ULP_CLASS_HID_3ab60, + [3924] = { + .class_hid = BNXT_ULP_CLASS_HID_55592, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3345] = { - .class_hid = BNXT_ULP_CLASS_HID_253c0, + [3925] = { + .class_hid = BNXT_ULP_CLASS_HID_72ce2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3346] = { - .class_hid = BNXT_ULP_CLASS_HID_2dcc0, + [3926] = { + .class_hid = BNXT_ULP_CLASS_HID_752a6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 260, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3347] = { - .class_hid = BNXT_ULP_CLASS_HID_349c0, + [3927] = { + .class_hid = BNXT_ULP_CLASS_HID_70702, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 261, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3348] = { - .class_hid = BNXT_ULP_CLASS_HID_397f4, + [3928] = { + .class_hid = BNXT_ULP_CLASS_HID_70cc6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 262, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3349] = { - .class_hid = BNXT_ULP_CLASS_HID_23f10, + [3929] = { + .class_hid = BNXT_ULP_CLASS_HID_7224a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 263, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3350] = { - .class_hid = BNXT_ULP_CLASS_HID_2a810, + [3930] = { + .class_hid = BNXT_ULP_CLASS_HID_7280e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 263, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3351] = { - .class_hid = BNXT_ULP_CLASS_HID_35510, + [3931] = { + .class_hid = BNXT_ULP_CLASS_HID_71cea, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 263, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3352] = { - .class_hid = BNXT_ULP_CLASS_HID_3de10, + [3932] = { + .class_hid = BNXT_ULP_CLASS_HID_702ae, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 263, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3353] = { - .class_hid = BNXT_ULP_CLASS_HID_23bc4, + [3933] = { + .class_hid = BNXT_ULP_CLASS_HID_23dc0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 263, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -69949,21 +82749,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3354] = { - .class_hid = BNXT_ULP_CLASS_HID_2a4c4, + [3934] = { + .class_hid = BNXT_ULP_CLASS_HID_223fc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 263, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -69971,22 +82765,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3355] = { - .class_hid = BNXT_ULP_CLASS_HID_351c4, + [3935] = { + .class_hid = BNXT_ULP_CLASS_HID_2079c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 264, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -69994,22 +82782,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3356] = { - .class_hid = BNXT_ULP_CLASS_HID_3dac4, + [3936] = { + .class_hid = BNXT_ULP_CLASS_HID_20d58, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 265, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70017,44 +82799,34 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3357] = { - .class_hid = BNXT_ULP_CLASS_HID_22cf4, + [3937] = { + .class_hid = BNXT_ULP_CLASS_HID_25e54, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3358] = { - .class_hid = BNXT_ULP_CLASS_HID_2d9f4, + [3938] = { + .class_hid = BNXT_ULP_CLASS_HID_24410, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70062,21 +82834,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3359] = { - .class_hid = BNXT_ULP_CLASS_HID_342f4, + [3939] = { + .class_hid = BNXT_ULP_CLASS_HID_22830, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70084,21 +82852,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3360] = { - .class_hid = BNXT_ULP_CLASS_HID_390a8, + [3940] = { + .class_hid = BNXT_ULP_CLASS_HID_251ec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70106,22 +82870,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3361] = { - .class_hid = BNXT_ULP_CLASS_HID_21908, + [3941] = { + .class_hid = BNXT_ULP_CLASS_HID_20910, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70129,20 +82889,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3362] = { - .class_hid = BNXT_ULP_CLASS_HID_28208, + [3942] = { + .class_hid = BNXT_ULP_CLASS_HID_20ecc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70150,21 +82906,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3363] = { - .class_hid = BNXT_ULP_CLASS_HID_30f08, + [3943] = { + .class_hid = BNXT_ULP_CLASS_HID_212ec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70172,21 +82924,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3364] = { - .class_hid = BNXT_ULP_CLASS_HID_3b808, + [3944] = { + .class_hid = BNXT_ULP_CLASS_HID_218a8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70194,22 +82942,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3365] = { - .class_hid = BNXT_ULP_CLASS_HID_243a4, + [3945] = { + .class_hid = BNXT_ULP_CLASS_HID_22da4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70217,21 +82961,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3366] = { - .class_hid = BNXT_ULP_CLASS_HID_29158, + [3946] = { + .class_hid = BNXT_ULP_CLASS_HID_25360, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70239,22 +82979,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3367] = { - .class_hid = BNXT_ULP_CLASS_HID_31a58, + [3947] = { + .class_hid = BNXT_ULP_CLASS_HID_23700, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70262,22 +82998,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3368] = { - .class_hid = BNXT_ULP_CLASS_HID_38758, + [3948] = { + .class_hid = BNXT_ULP_CLASS_HID_23d3c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70285,23 +83017,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3369] = { - .class_hid = BNXT_ULP_CLASS_HID_25c58, + [3949] = { + .class_hid = BNXT_ULP_CLASS_HID_636f4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70309,22 +83037,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3370] = { - .class_hid = BNXT_ULP_CLASS_HID_2c958, + [3950] = { + .class_hid = BNXT_ULP_CLASS_HID_63cb0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70332,23 +83054,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3371] = { - .class_hid = BNXT_ULP_CLASS_HID_3170c, + [3951] = { + .class_hid = BNXT_ULP_CLASS_HID_60050, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70356,23 +83072,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3372] = { - .class_hid = BNXT_ULP_CLASS_HID_3800c, + [3952] = { + .class_hid = BNXT_ULP_CLASS_HID_6060c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70380,24 +83090,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3373] = { - .class_hid = BNXT_ULP_CLASS_HID_2123c, + [3953] = { + .class_hid = BNXT_ULP_CLASS_HID_65b08, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70405,21 +83109,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3374] = { - .class_hid = BNXT_ULP_CLASS_HID_29f3c, + [3954] = { + .class_hid = BNXT_ULP_CLASS_HID_640c4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70427,22 +83127,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3375] = { - .class_hid = BNXT_ULP_CLASS_HID_3083c, + [3955] = { + .class_hid = BNXT_ULP_CLASS_HID_624e4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70450,22 +83146,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3376] = { - .class_hid = BNXT_ULP_CLASS_HID_3b53c, + [3956] = { + .class_hid = BNXT_ULP_CLASS_HID_62aa0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70473,23 +83165,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3377] = { - .class_hid = BNXT_ULP_CLASS_HID_240a8, + [3957] = { + .class_hid = BNXT_ULP_CLASS_HID_605c4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70497,17 +83185,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3378] = { - .class_hid = BNXT_ULP_CLASS_HID_2cda8, + [3958] = { + .class_hid = BNXT_ULP_CLASS_HID_60b80, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70515,18 +83203,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3379] = { - .class_hid = BNXT_ULP_CLASS_HID_31b5c, + [3959] = { + .class_hid = BNXT_ULP_CLASS_HID_64aec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70534,18 +83222,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3380] = { - .class_hid = BNXT_ULP_CLASS_HID_3845c, + [3960] = { + .class_hid = BNXT_ULP_CLASS_HID_6155c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70553,19 +83241,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3381] = { - .class_hid = BNXT_ULP_CLASS_HID_22ff8, + [3961] = { + .class_hid = BNXT_ULP_CLASS_HID_62658, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70573,18 +83261,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3382] = { - .class_hid = BNXT_ULP_CLASS_HID_2d8f8, + [3962] = { + .class_hid = BNXT_ULP_CLASS_HID_62c14, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70592,19 +83280,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3383] = { - .class_hid = BNXT_ULP_CLASS_HID_345f8, + [3963] = { + .class_hid = BNXT_ULP_CLASS_HID_63034, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70612,19 +83300,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3384] = { - .class_hid = BNXT_ULP_CLASS_HID_393ac, + [3964] = { + .class_hid = BNXT_ULP_CLASS_HID_639f0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70632,20 +83320,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3385] = { - .class_hid = BNXT_ULP_CLASS_HID_228ac, + [3965] = { + .class_hid = BNXT_ULP_CLASS_HID_353c0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70653,19 +83341,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3386] = { - .class_hid = BNXT_ULP_CLASS_HID_2d5ac, + [3966] = { + .class_hid = BNXT_ULP_CLASS_HID_359fc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70673,20 +83358,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3387] = { - .class_hid = BNXT_ULP_CLASS_HID_35eac, + [3967] = { + .class_hid = BNXT_ULP_CLASS_HID_33d9c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70694,20 +83376,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3388] = { - .class_hid = BNXT_ULP_CLASS_HID_3cbac, + [3968] = { + .class_hid = BNXT_ULP_CLASS_HID_32358, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70715,21 +83394,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3389] = { - .class_hid = BNXT_ULP_CLASS_HID_25d5c, + [3969] = { + .class_hid = BNXT_ULP_CLASS_HID_31908, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70737,18 +83413,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3390] = { - .class_hid = BNXT_ULP_CLASS_HID_2c65c, + [3970] = { + .class_hid = BNXT_ULP_CLASS_HID_31ec4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70756,19 +83431,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3391] = { - .class_hid = BNXT_ULP_CLASS_HID_31410, + [3971] = { + .class_hid = BNXT_ULP_CLASS_HID_35e30, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70776,19 +83450,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3392] = { - .class_hid = BNXT_ULP_CLASS_HID_38110, + [3972] = { + .class_hid = BNXT_ULP_CLASS_HID_347ec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70796,20 +83469,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3393] = { - .class_hid = BNXT_ULP_CLASS_HID_209f0, + [3973] = { + .class_hid = BNXT_ULP_CLASS_HID_33f10, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70817,18 +83489,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3394] = { - .class_hid = BNXT_ULP_CLASS_HID_2b2f0, + [3974] = { + .class_hid = BNXT_ULP_CLASS_HID_324cc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70836,19 +83507,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3395] = { - .class_hid = BNXT_ULP_CLASS_HID_33ff0, + [3975] = { + .class_hid = BNXT_ULP_CLASS_HID_308ec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70856,19 +83526,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3396] = { - .class_hid = BNXT_ULP_CLASS_HID_3a8f0, + [3976] = { + .class_hid = BNXT_ULP_CLASS_HID_30ea8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70876,20 +83545,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3397] = { - .class_hid = BNXT_ULP_CLASS_HID_214c0, + [3977] = { + .class_hid = BNXT_ULP_CLASS_HID_343a4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70897,19 +83565,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3398] = { - .class_hid = BNXT_ULP_CLASS_HID_281c0, + [3978] = { + .class_hid = BNXT_ULP_CLASS_HID_34960, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70917,20 +83584,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3399] = { - .class_hid = BNXT_ULP_CLASS_HID_30ac0, + [3979] = { + .class_hid = BNXT_ULP_CLASS_HID_32d00, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70938,20 +83604,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3400] = { - .class_hid = BNXT_ULP_CLASS_HID_3b7c0, + [3980] = { + .class_hid = BNXT_ULP_CLASS_HID_3533c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70959,21 +83624,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3401] = { - .class_hid = BNXT_ULP_CLASS_HID_211f4, + [3981] = { + .class_hid = BNXT_ULP_CLASS_HID_72cf4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -70981,20 +83645,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3402] = { - .class_hid = BNXT_ULP_CLASS_HID_29af4, + [3982] = { + .class_hid = BNXT_ULP_CLASS_HID_752b0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71002,21 +83663,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3403] = { - .class_hid = BNXT_ULP_CLASS_HID_307f4, + [3983] = { + .class_hid = BNXT_ULP_CLASS_HID_73650, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71024,21 +83682,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3404] = { - .class_hid = BNXT_ULP_CLASS_HID_3b0f4, + [3984] = { + .class_hid = BNXT_ULP_CLASS_HID_73c0c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71046,22 +83701,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3405] = { - .class_hid = BNXT_ULP_CLASS_HID_202a4, + [3985] = { + .class_hid = BNXT_ULP_CLASS_HID_7123c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71069,19 +83721,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3406] = { - .class_hid = BNXT_ULP_CLASS_HID_28fa4, + [3986] = { + .class_hid = BNXT_ULP_CLASS_HID_71bf8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71089,20 +83740,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3407] = { - .class_hid = BNXT_ULP_CLASS_HID_338a4, + [3987] = { + .class_hid = BNXT_ULP_CLASS_HID_75ae4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71110,20 +83760,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3408] = { - .class_hid = BNXT_ULP_CLASS_HID_3a5a4, + [3988] = { + .class_hid = BNXT_ULP_CLASS_HID_740a0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71131,21 +83780,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3409] = { - .class_hid = BNXT_ULP_CLASS_HID_22a04, + [3989] = { + .class_hid = BNXT_ULP_CLASS_HID_73bc4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71153,18 +83801,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3410] = { - .class_hid = BNXT_ULP_CLASS_HID_2d704, + [3990] = { + .class_hid = BNXT_ULP_CLASS_HID_72180, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71172,19 +83820,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3411] = { - .class_hid = BNXT_ULP_CLASS_HID_34004, + [3991] = { + .class_hid = BNXT_ULP_CLASS_HID_705a0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71192,19 +83840,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3412] = { - .class_hid = BNXT_ULP_CLASS_HID_3cd04, + [3992] = { + .class_hid = BNXT_ULP_CLASS_HID_70b5c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71212,20 +83860,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3413] = { - .class_hid = BNXT_ULP_CLASS_HID_23954, + [3993] = { + .class_hid = BNXT_ULP_CLASS_HID_75c58, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71233,19 +83881,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3414] = { - .class_hid = BNXT_ULP_CLASS_HID_2a254, + [3994] = { + .class_hid = BNXT_ULP_CLASS_HID_74214, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71253,20 +83901,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3415] = { - .class_hid = BNXT_ULP_CLASS_HID_32f54, + [3995] = { + .class_hid = BNXT_ULP_CLASS_HID_72634, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71274,20 +83922,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3416] = { - .class_hid = BNXT_ULP_CLASS_HID_3d854, + [3996] = { + .class_hid = BNXT_ULP_CLASS_HID_72ff0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71295,21 +83943,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3417] = { - .class_hid = BNXT_ULP_CLASS_HID_23208, + [3997] = { + .class_hid = BNXT_ULP_CLASS_HID_2a6c0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71317,20 +83965,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3418] = { - .class_hid = BNXT_ULP_CLASS_HID_2bf08, + [3998] = { + .class_hid = BNXT_ULP_CLASS_HID_2acfc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71338,21 +83982,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3419] = { - .class_hid = BNXT_ULP_CLASS_HID_32808, + [3999] = { + .class_hid = BNXT_ULP_CLASS_HID_2b09c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71360,21 +84000,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3420] = { - .class_hid = BNXT_ULP_CLASS_HID_3d508, + [4000] = { + .class_hid = BNXT_ULP_CLASS_HID_2b658, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71382,22 +84018,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3421] = { - .class_hid = BNXT_ULP_CLASS_HID_22738, + [4001] = { + .class_hid = BNXT_ULP_CLASS_HID_2cb54, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71405,19 +84037,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3422] = { - .class_hid = BNXT_ULP_CLASS_HID_2d038, + [4002] = { + .class_hid = BNXT_ULP_CLASS_HID_295c4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71425,20 +84055,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3423] = { - .class_hid = BNXT_ULP_CLASS_HID_35d38, + [4003] = { + .class_hid = BNXT_ULP_CLASS_HID_2d530, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71446,20 +84074,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3424] = { - .class_hid = BNXT_ULP_CLASS_HID_3c638, + [4004] = { + .class_hid = BNXT_ULP_CLASS_HID_2daec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71467,21 +84093,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3425] = { - .class_hid = BNXT_ULP_CLASS_HID_2134c, + [4005] = { + .class_hid = BNXT_ULP_CLASS_HID_2b210, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71489,19 +84113,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3426] = { - .class_hid = BNXT_ULP_CLASS_HID_29c4c, + [4006] = { + .class_hid = BNXT_ULP_CLASS_HID_2bbcc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71509,20 +84131,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3427] = { - .class_hid = BNXT_ULP_CLASS_HID_3094c, + [4007] = { + .class_hid = BNXT_ULP_CLASS_HID_29fec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71530,20 +84150,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3428] = { - .class_hid = BNXT_ULP_CLASS_HID_3b24c, + [4008] = { + .class_hid = BNXT_ULP_CLASS_HID_285a8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71551,21 +84169,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3429] = { - .class_hid = BNXT_ULP_CLASS_HID_25de8, + [4009] = { + .class_hid = BNXT_ULP_CLASS_HID_2d6a4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71573,20 +84189,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3430] = { - .class_hid = BNXT_ULP_CLASS_HID_2c6e8, + [4010] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc60, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71594,21 +84208,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3431] = { - .class_hid = BNXT_ULP_CLASS_HID_3149c, + [4011] = { + .class_hid = BNXT_ULP_CLASS_HID_2a000, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71616,21 +84228,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3432] = { - .class_hid = BNXT_ULP_CLASS_HID_3819c, + [4012] = { + .class_hid = BNXT_ULP_CLASS_HID_2a63c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71638,22 +84248,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3433] = { - .class_hid = BNXT_ULP_CLASS_HID_2569c, + [4013] = { + .class_hid = BNXT_ULP_CLASS_HID_6a3f4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71661,21 +84269,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3434] = { - .class_hid = BNXT_ULP_CLASS_HID_2c39c, + [4014] = { + .class_hid = BNXT_ULP_CLASS_HID_6a9b0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71683,22 +84287,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3435] = { - .class_hid = BNXT_ULP_CLASS_HID_31150, + [4015] = { + .class_hid = BNXT_ULP_CLASS_HID_68d50, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71706,22 +84306,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3436] = { - .class_hid = BNXT_ULP_CLASS_HID_39a50, + [4016] = { + .class_hid = BNXT_ULP_CLASS_HID_6b30c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71729,23 +84325,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3437] = { - .class_hid = BNXT_ULP_CLASS_HID_24b4c, + [4017] = { + .class_hid = BNXT_ULP_CLASS_HID_6c408, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71753,20 +84345,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3438] = { - .class_hid = BNXT_ULP_CLASS_HID_29900, + [4018] = { + .class_hid = BNXT_ULP_CLASS_HID_6cdc4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71774,21 +84364,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3439] = { - .class_hid = BNXT_ULP_CLASS_HID_30200, + [4019] = { + .class_hid = BNXT_ULP_CLASS_HID_6d1e4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71796,21 +84384,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3440] = { - .class_hid = BNXT_ULP_CLASS_HID_38f00, + [4020] = { + .class_hid = BNXT_ULP_CLASS_HID_6d7a0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71818,22 +84404,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3441] = { - .class_hid = BNXT_ULP_CLASS_HID_22f74, + [4021] = { + .class_hid = BNXT_ULP_CLASS_HID_68ec4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71841,17 +84425,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3442] = { - .class_hid = BNXT_ULP_CLASS_HID_2d874, + [4022] = { + .class_hid = BNXT_ULP_CLASS_HID_6b480, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71859,18 +84444,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3443] = { - .class_hid = BNXT_ULP_CLASS_HID_34574, + [4023] = { + .class_hid = BNXT_ULP_CLASS_HID_698a0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71878,18 +84464,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3444] = { - .class_hid = BNXT_ULP_CLASS_HID_39328, + [4024] = { + .class_hid = BNXT_ULP_CLASS_HID_69e5c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71897,19 +84484,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3445] = { - .class_hid = BNXT_ULP_CLASS_HID_23a44, + [4025] = { + .class_hid = BNXT_ULP_CLASS_HID_6d358, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71917,18 +84505,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3446] = { - .class_hid = BNXT_ULP_CLASS_HID_2a744, + [4026] = { + .class_hid = BNXT_ULP_CLASS_HID_6d914, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71936,19 +84525,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3447] = { - .class_hid = BNXT_ULP_CLASS_HID_35044, + [4027] = { + .class_hid = BNXT_ULP_CLASS_HID_6bd34, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71956,19 +84546,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3448] = { - .class_hid = BNXT_ULP_CLASS_HID_3dd44, + [4028] = { + .class_hid = BNXT_ULP_CLASS_HID_6a2f0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71976,20 +84567,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3449] = { - .class_hid = BNXT_ULP_CLASS_HID_23778, + [4029] = { + .class_hid = BNXT_ULP_CLASS_HID_3dcc0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -71997,19 +84589,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3450] = { - .class_hid = BNXT_ULP_CLASS_HID_2a078, + [4030] = { + .class_hid = BNXT_ULP_CLASS_HID_3c2fc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72017,20 +84607,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3451] = { - .class_hid = BNXT_ULP_CLASS_HID_32d78, + [4031] = { + .class_hid = BNXT_ULP_CLASS_HID_3a69c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72038,20 +84626,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3452] = { - .class_hid = BNXT_ULP_CLASS_HID_3d678, + [4032] = { + .class_hid = BNXT_ULP_CLASS_HID_3ac58, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72059,21 +84645,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3453] = { - .class_hid = BNXT_ULP_CLASS_HID_22828, + [4033] = { + .class_hid = BNXT_ULP_CLASS_HID_38208, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72081,18 +84665,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3454] = { - .class_hid = BNXT_ULP_CLASS_HID_2d528, + [4034] = { + .class_hid = BNXT_ULP_CLASS_HID_38bc4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72100,19 +84684,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3455] = { - .class_hid = BNXT_ULP_CLASS_HID_35e28, + [4035] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb30, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72120,19 +84704,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3456] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb28, + [4036] = { + .class_hid = BNXT_ULP_CLASS_HID_395a0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72140,20 +84724,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3457] = { - .class_hid = BNXT_ULP_CLASS_HID_214bc, + [4037] = { + .class_hid = BNXT_ULP_CLASS_HID_3a810, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72161,18 +84745,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3458] = { - .class_hid = BNXT_ULP_CLASS_HID_281bc, + [4038] = { + .class_hid = BNXT_ULP_CLASS_HID_3d1cc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72180,19 +84764,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3459] = { - .class_hid = BNXT_ULP_CLASS_HID_30abc, + [4039] = { + .class_hid = BNXT_ULP_CLASS_HID_3b5ec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72200,19 +84784,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3460] = { - .class_hid = BNXT_ULP_CLASS_HID_3b7bc, + [4040] = { + .class_hid = BNXT_ULP_CLASS_HID_3bba8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72220,20 +84804,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3461] = { - .class_hid = BNXT_ULP_CLASS_HID_25ed8, + [4041] = { + .class_hid = BNXT_ULP_CLASS_HID_39158, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72241,19 +84825,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3462] = { - .class_hid = BNXT_ULP_CLASS_HID_2cbd8, + [4042] = { + .class_hid = BNXT_ULP_CLASS_HID_39714, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72261,20 +84845,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3463] = { - .class_hid = BNXT_ULP_CLASS_HID_3198c, + [4043] = { + .class_hid = BNXT_ULP_CLASS_HID_3d600, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72282,20 +84866,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3464] = { - .class_hid = BNXT_ULP_CLASS_HID_3828c, + [4044] = { + .class_hid = BNXT_ULP_CLASS_HID_3dc3c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72303,21 +84887,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3465] = { - .class_hid = BNXT_ULP_CLASS_HID_25b8c, + [4045] = { + .class_hid = BNXT_ULP_CLASS_HID_7d9f4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72325,20 +84909,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3466] = { - .class_hid = BNXT_ULP_CLASS_HID_2c48c, + [4046] = { + .class_hid = BNXT_ULP_CLASS_HID_7dfb0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72346,21 +84928,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3467] = { - .class_hid = BNXT_ULP_CLASS_HID_31240, + [4047] = { + .class_hid = BNXT_ULP_CLASS_HID_7a350, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72368,21 +84948,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3468] = { - .class_hid = BNXT_ULP_CLASS_HID_39f40, + [4048] = { + .class_hid = BNXT_ULP_CLASS_HID_7a90c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72390,22 +84968,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3469] = { - .class_hid = BNXT_ULP_CLASS_HID_21170, + [4049] = { + .class_hid = BNXT_ULP_CLASS_HID_79f3c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72413,19 +84989,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3470] = { - .class_hid = BNXT_ULP_CLASS_HID_29a70, + [4050] = { + .class_hid = BNXT_ULP_CLASS_HID_784f8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72433,20 +85009,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3471] = { - .class_hid = BNXT_ULP_CLASS_HID_30770, + [4051] = { + .class_hid = BNXT_ULP_CLASS_HID_7c7e4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72454,20 +85030,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3472] = { - .class_hid = BNXT_ULP_CLASS_HID_3b070, + [4052] = { + .class_hid = BNXT_ULP_CLASS_HID_7cda0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72475,21 +85051,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3473] = { - .class_hid = BNXT_ULP_CLASS_HID_238d0, + [4053] = { + .class_hid = BNXT_ULP_CLASS_HID_7a4c4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72497,18 +85073,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3474] = { - .class_hid = BNXT_ULP_CLASS_HID_2a5d0, + [4054] = { + .class_hid = BNXT_ULP_CLASS_HID_7aa80, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 266, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72516,19 +85093,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3475] = { - .class_hid = BNXT_ULP_CLASS_HID_32ed0, + [4055] = { + .class_hid = BNXT_ULP_CLASS_HID_78ea0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 267, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72536,19 +85114,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3476] = { - .class_hid = BNXT_ULP_CLASS_HID_3dbd0, + [4056] = { + .class_hid = BNXT_ULP_CLASS_HID_7b45c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 268, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72556,20 +85135,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3477] = { - .class_hid = BNXT_ULP_CLASS_HID_20420, + [4057] = { + .class_hid = BNXT_ULP_CLASS_HID_7c958, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 269, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72577,19 +85157,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3478] = { - .class_hid = BNXT_ULP_CLASS_HID_2b120, + [4058] = { + .class_hid = BNXT_ULP_CLASS_HID_793c8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 269, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72597,20 +85178,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3479] = { - .class_hid = BNXT_ULP_CLASS_HID_33a20, + [4059] = { + .class_hid = BNXT_ULP_CLASS_HID_7d334, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 269, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72618,20 +85200,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3480] = { - .class_hid = BNXT_ULP_CLASS_HID_3a720, + [4060] = { + .class_hid = BNXT_ULP_CLASS_HID_7d8f0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 269, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -72639,2814 +85222,2735 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3481] = { - .class_hid = BNXT_ULP_CLASS_HID_200d4, + [4061] = { + .class_hid = BNXT_ULP_CLASS_HID_9ab8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 269, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3482] = { - .class_hid = BNXT_ULP_CLASS_HID_28dd4, + [4062] = { + .class_hid = BNXT_ULP_CLASS_HID_8084, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 269, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3483] = { - .class_hid = BNXT_ULP_CLASS_HID_336d4, + [4063] = { + .class_hid = BNXT_ULP_CLASS_HID_c390, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 270, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3484] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3d4, + [4064] = { + .class_hid = BNXT_ULP_CLASS_HID_c9dc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 271, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3485] = { - .class_hid = BNXT_ULP_CLASS_HID_23584, + [4065] = { + .class_hid = BNXT_ULP_CLASS_HID_bf2c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3486] = { - .class_hid = BNXT_ULP_CLASS_HID_2be84, + [4066] = { + .class_hid = BNXT_ULP_CLASS_HID_a568, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3487] = { - .class_hid = BNXT_ULP_CLASS_HID_32b84, + [4067] = { + .class_hid = BNXT_ULP_CLASS_HID_8948, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3488] = { - .class_hid = BNXT_ULP_CLASS_HID_3d484, + [4068] = { + .class_hid = BNXT_ULP_CLASS_HID_8e94, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3489] = { - .class_hid = BNXT_ULP_CLASS_HID_25d64, + [4069] = { + .class_hid = BNXT_ULP_CLASS_HID_4978c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3490] = { - .class_hid = BNXT_ULP_CLASS_HID_2c664, + [4070] = { + .class_hid = BNXT_ULP_CLASS_HID_49dc8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3491] = { - .class_hid = BNXT_ULP_CLASS_HID_31418, + [4071] = { + .class_hid = BNXT_ULP_CLASS_HID_4dce4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3492] = { - .class_hid = BNXT_ULP_CLASS_HID_38118, + [4072] = { + .class_hid = BNXT_ULP_CLASS_HID_4c220, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3493] = { - .class_hid = BNXT_ULP_CLASS_HID_228b4, + [4073] = { + .class_hid = BNXT_ULP_CLASS_HID_4b870, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3494] = { - .class_hid = BNXT_ULP_CLASS_HID_2d5b4, + [4074] = { + .class_hid = BNXT_ULP_CLASS_HID_4a1bc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3495] = { - .class_hid = BNXT_ULP_CLASS_HID_35eb4, + [4075] = { + .class_hid = BNXT_ULP_CLASS_HID_4859c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3496] = { - .class_hid = BNXT_ULP_CLASS_HID_3cbb4, + [4076] = { + .class_hid = BNXT_ULP_CLASS_HID_48bd8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3497] = { - .class_hid = BNXT_ULP_CLASS_HID_22568, + [4077] = { + .class_hid = BNXT_ULP_CLASS_HID_1b0b8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3498] = { - .class_hid = BNXT_ULP_CLASS_HID_2ae68, + [4078] = { + .class_hid = BNXT_ULP_CLASS_HID_1b684, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3499] = { - .class_hid = BNXT_ULP_CLASS_HID_35b68, + [4079] = { + .class_hid = BNXT_ULP_CLASS_HID_19ae4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3500] = { - .class_hid = BNXT_ULP_CLASS_HID_3c468, + [4080] = { + .class_hid = BNXT_ULP_CLASS_HID_18020, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3501] = { - .class_hid = BNXT_ULP_CLASS_HID_25618, + [4081] = { + .class_hid = BNXT_ULP_CLASS_HID_1d52c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3502] = { - .class_hid = BNXT_ULP_CLASS_HID_2c318, + [4082] = { + .class_hid = BNXT_ULP_CLASS_HID_1db68, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3503] = { - .class_hid = BNXT_ULP_CLASS_HID_310cc, + [4083] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf48, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3504] = { - .class_hid = BNXT_ULP_CLASS_HID_39dcc, + [4084] = { + .class_hid = BNXT_ULP_CLASS_HID_1a494, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3505] = { - .class_hid = BNXT_ULP_CLASS_HID_229b8, + [4085] = { + .class_hid = BNXT_ULP_CLASS_HID_58d8c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3506] = { - .class_hid = BNXT_ULP_CLASS_HID_2d2b8, + [4086] = { + .class_hid = BNXT_ULP_CLASS_HID_5b3c8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3507] = { - .class_hid = BNXT_ULP_CLASS_HID_35fb8, + [4087] = { + .class_hid = BNXT_ULP_CLASS_HID_59728, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3508] = { - .class_hid = BNXT_ULP_CLASS_HID_3c8b8, + [4088] = { + .class_hid = BNXT_ULP_CLASS_HID_59d74, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3509] = { - .class_hid = BNXT_ULP_CLASS_HID_23488, + [4089] = { + .class_hid = BNXT_ULP_CLASS_HID_5ae70, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3510] = { - .class_hid = BNXT_ULP_CLASS_HID_2a188, + [4090] = { + .class_hid = BNXT_ULP_CLASS_HID_5d7bc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3511] = { - .class_hid = BNXT_ULP_CLASS_HID_32a88, + [4091] = { + .class_hid = BNXT_ULP_CLASS_HID_5bb9c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3512] = { - .class_hid = BNXT_ULP_CLASS_HID_3d788, + [4092] = { + .class_hid = BNXT_ULP_CLASS_HID_5a1d8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3513] = { - .class_hid = BNXT_ULP_CLASS_HID_231bc, + [4093] = { + .class_hid = BNXT_ULP_CLASS_HID_c138, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3514] = { - .class_hid = BNXT_ULP_CLASS_HID_2babc, + [4094] = { + .class_hid = BNXT_ULP_CLASS_HID_c704, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3515] = { - .class_hid = BNXT_ULP_CLASS_HID_327bc, + [4095] = { + .class_hid = BNXT_ULP_CLASS_HID_c610, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3516] = { - .class_hid = BNXT_ULP_CLASS_HID_3d0bc, + [4096] = { + .class_hid = BNXT_ULP_CLASS_HID_d0a0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3517] = { - .class_hid = BNXT_ULP_CLASS_HID_2226c, + [4097] = { + .class_hid = BNXT_ULP_CLASS_HID_e5ac, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3518] = { - .class_hid = BNXT_ULP_CLASS_HID_2af6c, + [4098] = { + .class_hid = BNXT_ULP_CLASS_HID_ebe8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3519] = { - .class_hid = BNXT_ULP_CLASS_HID_3586c, + [4099] = { + .class_hid = BNXT_ULP_CLASS_HID_cfc8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3520] = { - .class_hid = BNXT_ULP_CLASS_HID_3c56c, + [4100] = { + .class_hid = BNXT_ULP_CLASS_HID_f514, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3521] = { - .class_hid = BNXT_ULP_CLASS_HID_24dcc, + [4101] = { + .class_hid = BNXT_ULP_CLASS_HID_4da0c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3522] = { - .class_hid = BNXT_ULP_CLASS_HID_29b80, + [4102] = { + .class_hid = BNXT_ULP_CLASS_HID_4c048, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3523] = { - .class_hid = BNXT_ULP_CLASS_HID_30480, + [4103] = { + .class_hid = BNXT_ULP_CLASS_HID_4c364, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3524] = { - .class_hid = BNXT_ULP_CLASS_HID_3b180, + [4104] = { + .class_hid = BNXT_ULP_CLASS_HID_4c8a0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3525] = { - .class_hid = BNXT_ULP_CLASS_HID_2591c, + [4105] = { + .class_hid = BNXT_ULP_CLASS_HID_4fef0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3526] = { - .class_hid = BNXT_ULP_CLASS_HID_2c21c, + [4106] = { + .class_hid = BNXT_ULP_CLASS_HID_4e43c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3527] = { - .class_hid = BNXT_ULP_CLASS_HID_313d0, + [4107] = { + .class_hid = BNXT_ULP_CLASS_HID_4c81c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3528] = { - .class_hid = BNXT_ULP_CLASS_HID_39cd0, + [4108] = { + .class_hid = BNXT_ULP_CLASS_HID_4ce58, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3529] = { - .class_hid = BNXT_ULP_CLASS_HID_255d0, + [4109] = { + .class_hid = BNXT_ULP_CLASS_HID_1f738, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3530] = { - .class_hid = BNXT_ULP_CLASS_HID_2ded0, + [4110] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd04, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3531] = { - .class_hid = BNXT_ULP_CLASS_HID_34bd0, + [4111] = { + .class_hid = BNXT_ULP_CLASS_HID_1c164, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3532] = { - .class_hid = BNXT_ULP_CLASS_HID_39984, + [4112] = { + .class_hid = BNXT_ULP_CLASS_HID_1c6a0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3533] = { - .class_hid = BNXT_ULP_CLASS_HID_24680, + [4113] = { + .class_hid = BNXT_ULP_CLASS_HID_1dbac, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3534] = { - .class_hid = BNXT_ULP_CLASS_HID_294b4, + [4114] = { + .class_hid = BNXT_ULP_CLASS_HID_1c1e8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3535] = { - .class_hid = BNXT_ULP_CLASS_HID_301b4, + [4115] = { + .class_hid = BNXT_ULP_CLASS_HID_1e5c8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3536] = { - .class_hid = BNXT_ULP_CLASS_HID_38ab4, + [4116] = { + .class_hid = BNXT_ULP_CLASS_HID_1eb14, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3537] = { - .class_hid = BNXT_ULP_CLASS_HID_23314, + [4117] = { + .class_hid = BNXT_ULP_CLASS_HID_5f00c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3538] = { - .class_hid = BNXT_ULP_CLASS_HID_2bc14, + [4118] = { + .class_hid = BNXT_ULP_CLASS_HID_5f648, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3539] = { - .class_hid = BNXT_ULP_CLASS_HID_32914, + [4119] = { + .class_hid = BNXT_ULP_CLASS_HID_5dda8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3540] = { - .class_hid = BNXT_ULP_CLASS_HID_3d214, + [4120] = { + .class_hid = BNXT_ULP_CLASS_HID_5c3f4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3541] = { - .class_hid = BNXT_ULP_CLASS_HID_21e64, + [4121] = { + .class_hid = BNXT_ULP_CLASS_HID_5d4f0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3542] = { - .class_hid = BNXT_ULP_CLASS_HID_28b64, + [4122] = { + .class_hid = BNXT_ULP_CLASS_HID_5da3c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3543] = { - .class_hid = BNXT_ULP_CLASS_HID_33464, + [4123] = { + .class_hid = BNXT_ULP_CLASS_HID_5fe1c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3544] = { - .class_hid = BNXT_ULP_CLASS_HID_3a164, + [4124] = { + .class_hid = BNXT_ULP_CLASS_HID_5e458, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3545] = { - .class_hid = BNXT_ULP_CLASS_HID_21b18, + [4125] = { + .class_hid = BNXT_ULP_CLASS_HID_bc78, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3546] = { - .class_hid = BNXT_ULP_CLASS_HID_28418, + [4126] = { + .class_hid = BNXT_ULP_CLASS_HID_a244, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3547] = { - .class_hid = BNXT_ULP_CLASS_HID_33118, + [4127] = { + .class_hid = BNXT_ULP_CLASS_HID_e550, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3548] = { - .class_hid = BNXT_ULP_CLASS_HID_3ba18, + [4128] = { + .class_hid = BNXT_ULP_CLASS_HID_ea9c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3549] = { - .class_hid = BNXT_ULP_CLASS_HID_20fc8, + [4129] = { + .class_hid = BNXT_ULP_CLASS_HID_a0ec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3550] = { - .class_hid = BNXT_ULP_CLASS_HID_2b8c8, + [4130] = { + .class_hid = BNXT_ULP_CLASS_HID_a628, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3551] = { - .class_hid = BNXT_ULP_CLASS_HID_325c8, + [4131] = { + .class_hid = BNXT_ULP_CLASS_HID_aa08, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3552] = { - .class_hid = BNXT_ULP_CLASS_HID_3aec8, + [4132] = { + .class_hid = BNXT_ULP_CLASS_HID_b054, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3553] = { - .class_hid = BNXT_ULP_CLASS_HID_257a8, + [4133] = { + .class_hid = BNXT_ULP_CLASS_HID_4b94c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3554] = { - .class_hid = BNXT_ULP_CLASS_HID_2c0a8, + [4134] = { + .class_hid = BNXT_ULP_CLASS_HID_4be88, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3555] = { - .class_hid = BNXT_ULP_CLASS_HID_34da8, + [4135] = { + .class_hid = BNXT_ULP_CLASS_HID_4e1a4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3556] = { - .class_hid = BNXT_ULP_CLASS_HID_39b5c, + [4136] = { + .class_hid = BNXT_ULP_CLASS_HID_4e7e0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3557] = { - .class_hid = BNXT_ULP_CLASS_HID_222f8, + [4137] = { + .class_hid = BNXT_ULP_CLASS_HID_4bd30, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3558] = { - .class_hid = BNXT_ULP_CLASS_HID_2aff8, + [4138] = { + .class_hid = BNXT_ULP_CLASS_HID_4a37c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3559] = { - .class_hid = BNXT_ULP_CLASS_HID_358f8, + [4139] = { + .class_hid = BNXT_ULP_CLASS_HID_4a75c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3560] = { - .class_hid = BNXT_ULP_CLASS_HID_3c5f8, + [4140] = { + .class_hid = BNXT_ULP_CLASS_HID_4ac98, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3561] = { - .class_hid = BNXT_ULP_CLASS_HID_23fac, + [4141] = { + .class_hid = BNXT_ULP_CLASS_HID_1b278, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3562] = { - .class_hid = BNXT_ULP_CLASS_HID_2a8ac, + [4142] = { + .class_hid = BNXT_ULP_CLASS_HID_1b844, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3563] = { - .class_hid = BNXT_ULP_CLASS_HID_355ac, + [4143] = { + .class_hid = BNXT_ULP_CLASS_HID_1bfa4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3564] = { - .class_hid = BNXT_ULP_CLASS_HID_3deac, + [4144] = { + .class_hid = BNXT_ULP_CLASS_HID_1a5e0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3565] = { - .class_hid = BNXT_ULP_CLASS_HID_2505c, + [4145] = { + .class_hid = BNXT_ULP_CLASS_HID_1f6ec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3566] = { - .class_hid = BNXT_ULP_CLASS_HID_2dd5c, + [4146] = { + .class_hid = BNXT_ULP_CLASS_HID_1fc28, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3567] = { - .class_hid = BNXT_ULP_CLASS_HID_3465c, + [4147] = { + .class_hid = BNXT_ULP_CLASS_HID_1a008, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3568] = { - .class_hid = BNXT_ULP_CLASS_HID_39410, + [4148] = { + .class_hid = BNXT_ULP_CLASS_HID_1a654, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3569] = { - .class_hid = BNXT_ULP_CLASS_HID_223fc, + [4149] = { + .class_hid = BNXT_ULP_CLASS_HID_5af4c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3570] = { - .class_hid = BNXT_ULP_CLASS_HID_2acfc, + [4150] = { + .class_hid = BNXT_ULP_CLASS_HID_5b488, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3571] = { - .class_hid = BNXT_ULP_CLASS_HID_359fc, + [4151] = { + .class_hid = BNXT_ULP_CLASS_HID_5b8e8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3572] = { - .class_hid = BNXT_ULP_CLASS_HID_3c2fc, + [4152] = { + .class_hid = BNXT_ULP_CLASS_HID_5be34, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3573] = { - .class_hid = BNXT_ULP_CLASS_HID_20ecc, + [4153] = { + .class_hid = BNXT_ULP_CLASS_HID_5f330, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3574] = { - .class_hid = BNXT_ULP_CLASS_HID_2bbcc, + [4154] = { + .class_hid = BNXT_ULP_CLASS_HID_5f97c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3575] = { - .class_hid = BNXT_ULP_CLASS_HID_324cc, + [4155] = { + .class_hid = BNXT_ULP_CLASS_HID_5bd5c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3576] = { - .class_hid = BNXT_ULP_CLASS_HID_3d1cc, + [4156] = { + .class_hid = BNXT_ULP_CLASS_HID_5a298, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3577] = { - .class_hid = BNXT_ULP_CLASS_HID_20b80, + [4157] = { + .class_hid = BNXT_ULP_CLASS_HID_e2f8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3578] = { - .class_hid = BNXT_ULP_CLASS_HID_2b480, + [4158] = { + .class_hid = BNXT_ULP_CLASS_HID_e8c4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3579] = { - .class_hid = BNXT_ULP_CLASS_HID_32180, + [4159] = { + .class_hid = BNXT_ULP_CLASS_HID_ebd0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3580] = { - .class_hid = BNXT_ULP_CLASS_HID_3aa80, + [4160] = { + .class_hid = BNXT_ULP_CLASS_HID_f260, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3581] = { - .class_hid = BNXT_ULP_CLASS_HID_23cb0, + [4161] = { + .class_hid = BNXT_ULP_CLASS_HID_e76c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3582] = { - .class_hid = BNXT_ULP_CLASS_HID_2a9b0, + [4162] = { + .class_hid = BNXT_ULP_CLASS_HID_eca8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3583] = { - .class_hid = BNXT_ULP_CLASS_HID_352b0, + [4163] = { + .class_hid = BNXT_ULP_CLASS_HID_f088, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3584] = { - .class_hid = BNXT_ULP_CLASS_HID_3dfb0, + [4164] = { + .class_hid = BNXT_ULP_CLASS_HID_f6d4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3585] = { - .class_hid = BNXT_ULP_CLASS_HID_24410, + [4165] = { + .class_hid = BNXT_ULP_CLASS_HID_4ffcc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3586] = { - .class_hid = BNXT_ULP_CLASS_HID_295c4, + [4166] = { + .class_hid = BNXT_ULP_CLASS_HID_4e508, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3587] = { - .class_hid = BNXT_ULP_CLASS_HID_31ec4, + [4167] = { + .class_hid = BNXT_ULP_CLASS_HID_4e424, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3588] = { - .class_hid = BNXT_ULP_CLASS_HID_38bc4, + [4168] = { + .class_hid = BNXT_ULP_CLASS_HID_4ea60, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3589] = { - .class_hid = BNXT_ULP_CLASS_HID_25360, + [4169] = { + .class_hid = BNXT_ULP_CLASS_HID_4e3b0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3590] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc60, + [4170] = { + .class_hid = BNXT_ULP_CLASS_HID_4e9fc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3591] = { - .class_hid = BNXT_ULP_CLASS_HID_34960, + [4171] = { + .class_hid = BNXT_ULP_CLASS_HID_4eddc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3592] = { - .class_hid = BNXT_ULP_CLASS_HID_39714, + [4172] = { + .class_hid = BNXT_ULP_CLASS_HID_4f318, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3593] = { - .class_hid = BNXT_ULP_CLASS_HID_22c14, + [4173] = { + .class_hid = BNXT_ULP_CLASS_HID_1f8f8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3594] = { - .class_hid = BNXT_ULP_CLASS_HID_2d914, + [4174] = { + .class_hid = BNXT_ULP_CLASS_HID_1fec4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3595] = { - .class_hid = BNXT_ULP_CLASS_HID_34214, + [4175] = { + .class_hid = BNXT_ULP_CLASS_HID_1e224, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3596] = { - .class_hid = BNXT_ULP_CLASS_HID_393c8, + [4176] = { + .class_hid = BNXT_ULP_CLASS_HID_1e860, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3597] = { - .class_hid = BNXT_ULP_CLASS_HID_240c4, + [4177] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd6c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3598] = { - .class_hid = BNXT_ULP_CLASS_HID_2cdc4, + [4178] = { + .class_hid = BNXT_ULP_CLASS_HID_1e2a8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3599] = { - .class_hid = BNXT_ULP_CLASS_HID_31bf8, + [4179] = { + .class_hid = BNXT_ULP_CLASS_HID_1e688, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3600] = { - .class_hid = BNXT_ULP_CLASS_HID_384f8, + [4180] = { + .class_hid = BNXT_ULP_CLASS_HID_1ecd4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3601] = { - .class_hid = BNXT_ULP_CLASS_HID_23dc0, + [4181] = { + .class_hid = BNXT_ULP_CLASS_HID_5f5cc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3602] = { - .class_hid = BNXT_ULP_CLASS_HID_2a6c0, + [4182] = { + .class_hid = BNXT_ULP_CLASS_HID_5fb08, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3603] = { - .class_hid = BNXT_ULP_CLASS_HID_353c0, + [4183] = { + .class_hid = BNXT_ULP_CLASS_HID_5ff68, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3604] = { - .class_hid = BNXT_ULP_CLASS_HID_3dcc0, + [4184] = { + .class_hid = BNXT_ULP_CLASS_HID_5e4b4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3605] = { - .class_hid = BNXT_ULP_CLASS_HID_20910, + [4185] = { + .class_hid = BNXT_ULP_CLASS_HID_5f9b0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3606] = { - .class_hid = BNXT_ULP_CLASS_HID_2b210, + [4186] = { + .class_hid = BNXT_ULP_CLASS_HID_5fffc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3607] = { - .class_hid = BNXT_ULP_CLASS_HID_33f10, + [4187] = { + .class_hid = BNXT_ULP_CLASS_HID_5e3dc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3608] = { - .class_hid = BNXT_ULP_CLASS_HID_3a810, + [4188] = { + .class_hid = BNXT_ULP_CLASS_HID_5e918, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 272, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3609] = { - .class_hid = BNXT_ULP_CLASS_HID_205c4, + [4189] = { + .class_hid = BNXT_ULP_CLASS_HID_23de0, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3610] = { - .class_hid = BNXT_ULP_CLASS_HID_28ec4, + [4190] = { + .class_hid = BNXT_ULP_CLASS_HID_223dc, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3611] = { - .class_hid = BNXT_ULP_CLASS_HID_33bc4, + [4191] = { + .class_hid = BNXT_ULP_CLASS_HID_207bc, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3612] = { - .class_hid = BNXT_ULP_CLASS_HID_3a4c4, + [4192] = { + .class_hid = BNXT_ULP_CLASS_HID_20d78, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3613] = { - .class_hid = BNXT_ULP_CLASS_HID_236f4, + [4193] = { + .class_hid = BNXT_ULP_CLASS_HID_25e74, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3614] = { - .class_hid = BNXT_ULP_CLASS_HID_2a3f4, + [4194] = { + .class_hid = BNXT_ULP_CLASS_HID_24430, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3615] = { - .class_hid = BNXT_ULP_CLASS_HID_32cf4, + [4195] = { + .class_hid = BNXT_ULP_CLASS_HID_22810, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3616] = { - .class_hid = BNXT_ULP_CLASS_HID_3d9f4, + [4196] = { + .class_hid = BNXT_ULP_CLASS_HID_251cc, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3617] = { - .class_hid = BNXT_ULP_CLASS_HID_25e54, + [4197] = { + .class_hid = BNXT_ULP_CLASS_HID_20930, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3618] = { - .class_hid = BNXT_ULP_CLASS_HID_2cb54, + [4198] = { + .class_hid = BNXT_ULP_CLASS_HID_20eec, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3619] = { - .class_hid = BNXT_ULP_CLASS_HID_31908, + [4199] = { + .class_hid = BNXT_ULP_CLASS_HID_212cc, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3620] = { - .class_hid = BNXT_ULP_CLASS_HID_38208, + [4200] = { + .class_hid = BNXT_ULP_CLASS_HID_21888, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3621] = { - .class_hid = BNXT_ULP_CLASS_HID_22da4, + [4201] = { + .class_hid = BNXT_ULP_CLASS_HID_22d84, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | @@ -75454,155 +87958,147 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3622] = { - .class_hid = BNXT_ULP_CLASS_HID_2d6a4, + [4202] = { + .class_hid = BNXT_ULP_CLASS_HID_25340, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32768, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3623] = { - .class_hid = BNXT_ULP_CLASS_HID_343a4, + [4203] = { + .class_hid = BNXT_ULP_CLASS_HID_23720, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3624] = { - .class_hid = BNXT_ULP_CLASS_HID_39158, + [4204] = { + .class_hid = BNXT_ULP_CLASS_HID_23d1c, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 32832, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3625] = { - .class_hid = BNXT_ULP_CLASS_HID_22658, + [4205] = { + .class_hid = BNXT_ULP_CLASS_HID_636d4, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3626] = { - .class_hid = BNXT_ULP_CLASS_HID_2d358, + [4206] = { + .class_hid = BNXT_ULP_CLASS_HID_63c90, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3627] = { - .class_hid = BNXT_ULP_CLASS_HID_35c58, + [4207] = { + .class_hid = BNXT_ULP_CLASS_HID_60070, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3628] = { - .class_hid = BNXT_ULP_CLASS_HID_3c958, + [4208] = { + .class_hid = BNXT_ULP_CLASS_HID_6062c, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3629] = { - .class_hid = BNXT_ULP_CLASS_HID_25b08, + [4209] = { + .class_hid = BNXT_ULP_CLASS_HID_65b28, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | @@ -75610,374 +88106,374 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3630] = { - .class_hid = BNXT_ULP_CLASS_HID_2c408, + [4210] = { + .class_hid = BNXT_ULP_CLASS_HID_640e4, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 49152, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3631] = { - .class_hid = BNXT_ULP_CLASS_HID_3123c, + [4211] = { + .class_hid = BNXT_ULP_CLASS_HID_624c4, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3632] = { - .class_hid = BNXT_ULP_CLASS_HID_39f3c, + [4212] = { + .class_hid = BNXT_ULP_CLASS_HID_62a80, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, + .flow_sig_id = 49216, .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3633] = { - .class_hid = BNXT_ULP_CLASS_HID_34a8, + [4213] = { + .class_hid = BNXT_ULP_CLASS_HID_605e4, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3634] = { - .class_hid = BNXT_ULP_CLASS_HID_3a64, + [4214] = { + .class_hid = BNXT_ULP_CLASS_HID_60ba0, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3635] = { - .class_hid = BNXT_ULP_CLASS_HID_09b4, + [4215] = { + .class_hid = BNXT_ULP_CLASS_HID_64acc, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3636] = { - .class_hid = BNXT_ULP_CLASS_HID_5ef8, + [4216] = { + .class_hid = BNXT_ULP_CLASS_HID_6157c, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3637] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc8, + [4217] = { + .class_hid = BNXT_ULP_CLASS_HID_62678, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3638] = { - .class_hid = BNXT_ULP_CLASS_HID_07c0, + [4218] = { + .class_hid = BNXT_ULP_CLASS_HID_62c34, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3639] = { - .class_hid = BNXT_ULP_CLASS_HID_1310, + [4219] = { + .class_hid = BNXT_ULP_CLASS_HID_63014, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3640] = { - .class_hid = BNXT_ULP_CLASS_HID_2854, + [4220] = { + .class_hid = BNXT_ULP_CLASS_HID_639d0, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3641] = { - .class_hid = BNXT_ULP_CLASS_HID_37a4, + [4221] = { + .class_hid = BNXT_ULP_CLASS_HID_353e0, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3642] = { - .class_hid = BNXT_ULP_CLASS_HID_03f8, + [4222] = { + .class_hid = BNXT_ULP_CLASS_HID_359dc, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3643] = { - .class_hid = BNXT_ULP_CLASS_HID_593c, + [4223] = { + .class_hid = BNXT_ULP_CLASS_HID_33dbc, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3644] = { - .class_hid = BNXT_ULP_CLASS_HID_240c, + [4224] = { + .class_hid = BNXT_ULP_CLASS_HID_32378, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3645] = { - .class_hid = BNXT_ULP_CLASS_HID_1e04, + [4225] = { + .class_hid = BNXT_ULP_CLASS_HID_31928, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3646] = { - .class_hid = BNXT_ULP_CLASS_HID_48a0, + [4226] = { + .class_hid = BNXT_ULP_CLASS_HID_31ee4, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3647] = { - .class_hid = BNXT_ULP_CLASS_HID_2298, + [4227] = { + .class_hid = BNXT_ULP_CLASS_HID_35e10, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3648] = { - .class_hid = BNXT_ULP_CLASS_HID_31e8, + [4228] = { + .class_hid = BNXT_ULP_CLASS_HID_347cc, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 272, - .flow_pattern_id = 2, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3649] = { - .class_hid = BNXT_ULP_CLASS_HID_24644, + [4229] = { + .class_hid = BNXT_ULP_CLASS_HID_33f30, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -75985,18 +88481,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3650] = { - .class_hid = BNXT_ULP_CLASS_HID_29438, + [4230] = { + .class_hid = BNXT_ULP_CLASS_HID_324ec, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76004,19 +88499,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3651] = { - .class_hid = BNXT_ULP_CLASS_HID_30138, + [4231] = { + .class_hid = BNXT_ULP_CLASS_HID_308cc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76024,19 +88518,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3652] = { - .class_hid = BNXT_ULP_CLASS_HID_38a38, + [4232] = { + .class_hid = BNXT_ULP_CLASS_HID_30e88, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76044,20 +88537,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3653] = { - .class_hid = BNXT_ULP_CLASS_HID_25594, + [4233] = { + .class_hid = BNXT_ULP_CLASS_HID_34384, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76065,19 +88557,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3654] = { - .class_hid = BNXT_ULP_CLASS_HID_2de94, + [4234] = { + .class_hid = BNXT_ULP_CLASS_HID_34940, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76085,20 +88576,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3655] = { - .class_hid = BNXT_ULP_CLASS_HID_34b94, + [4235] = { + .class_hid = BNXT_ULP_CLASS_HID_32d20, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76106,20 +88596,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3656] = { - .class_hid = BNXT_ULP_CLASS_HID_39948, + [4236] = { + .class_hid = BNXT_ULP_CLASS_HID_3531c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76127,21 +88616,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3657] = { - .class_hid = BNXT_ULP_CLASS_HID_22e48, + [4237] = { + .class_hid = BNXT_ULP_CLASS_HID_72cd4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76149,20 +88637,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3658] = { - .class_hid = BNXT_ULP_CLASS_HID_2db48, + [4238] = { + .class_hid = BNXT_ULP_CLASS_HID_75290, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76170,21 +88655,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3659] = { - .class_hid = BNXT_ULP_CLASS_HID_34448, + [4239] = { + .class_hid = BNXT_ULP_CLASS_HID_73670, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76192,21 +88674,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3660] = { - .class_hid = BNXT_ULP_CLASS_HID_3923c, + [4240] = { + .class_hid = BNXT_ULP_CLASS_HID_73c2c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76214,22 +88693,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3661] = { - .class_hid = BNXT_ULP_CLASS_HID_24338, + [4241] = { + .class_hid = BNXT_ULP_CLASS_HID_7121c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76237,19 +88713,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3662] = { - .class_hid = BNXT_ULP_CLASS_HID_290ec, + [4242] = { + .class_hid = BNXT_ULP_CLASS_HID_71bd8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76257,20 +88732,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3663] = { - .class_hid = BNXT_ULP_CLASS_HID_31dec, + [4243] = { + .class_hid = BNXT_ULP_CLASS_HID_75ac4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76278,20 +88752,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3664] = { - .class_hid = BNXT_ULP_CLASS_HID_386ec, + [4244] = { + .class_hid = BNXT_ULP_CLASS_HID_74080, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76299,21 +88772,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3665] = { - .class_hid = BNXT_ULP_CLASS_HID_20f8c, + [4245] = { + .class_hid = BNXT_ULP_CLASS_HID_73be4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76321,19 +88793,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3666] = { - .class_hid = BNXT_ULP_CLASS_HID_2b88c, + [4246] = { + .class_hid = BNXT_ULP_CLASS_HID_721a0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76341,20 +88812,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3667] = { - .class_hid = BNXT_ULP_CLASS_HID_3258c, + [4247] = { + .class_hid = BNXT_ULP_CLASS_HID_70580, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76362,20 +88832,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3668] = { - .class_hid = BNXT_ULP_CLASS_HID_3ae8c, + [4248] = { + .class_hid = BNXT_ULP_CLASS_HID_70b7c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76383,21 +88852,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3669] = { - .class_hid = BNXT_ULP_CLASS_HID_21adc, + [4249] = { + .class_hid = BNXT_ULP_CLASS_HID_75c78, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76405,20 +88873,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3670] = { - .class_hid = BNXT_ULP_CLASS_HID_287dc, + [4250] = { + .class_hid = BNXT_ULP_CLASS_HID_74234, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76426,21 +88893,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3671] = { - .class_hid = BNXT_ULP_CLASS_HID_330dc, + [4251] = { + .class_hid = BNXT_ULP_CLASS_HID_72614, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76448,21 +88914,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3672] = { - .class_hid = BNXT_ULP_CLASS_HID_3bddc, + [4252] = { + .class_hid = BNXT_ULP_CLASS_HID_72fd0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76470,22 +88935,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3673] = { - .class_hid = BNXT_ULP_CLASS_HID_21790, + [4253] = { + .class_hid = BNXT_ULP_CLASS_HID_2a6e0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76493,21 +88957,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3674] = { - .class_hid = BNXT_ULP_CLASS_HID_28090, + [4254] = { + .class_hid = BNXT_ULP_CLASS_HID_2acdc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76515,22 +88974,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3675] = { - .class_hid = BNXT_ULP_CLASS_HID_30d90, + [4255] = { + .class_hid = BNXT_ULP_CLASS_HID_2b0bc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76538,22 +88992,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3676] = { - .class_hid = BNXT_ULP_CLASS_HID_3b690, + [4256] = { + .class_hid = BNXT_ULP_CLASS_HID_2b678, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76561,23 +89010,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3677] = { - .class_hid = BNXT_ULP_CLASS_HID_20840, + [4257] = { + .class_hid = BNXT_ULP_CLASS_HID_2cb74, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76585,20 +89029,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3678] = { - .class_hid = BNXT_ULP_CLASS_HID_2b540, + [4258] = { + .class_hid = BNXT_ULP_CLASS_HID_295e4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76606,21 +89047,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3679] = { - .class_hid = BNXT_ULP_CLASS_HID_33e40, + [4259] = { + .class_hid = BNXT_ULP_CLASS_HID_2d510, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76628,21 +89066,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3680] = { - .class_hid = BNXT_ULP_CLASS_HID_3ab40, + [4260] = { + .class_hid = BNXT_ULP_CLASS_HID_2dacc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76650,22 +89085,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3681] = { - .class_hid = BNXT_ULP_CLASS_HID_253e0, + [4261] = { + .class_hid = BNXT_ULP_CLASS_HID_2b230, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76673,19 +89105,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3682] = { - .class_hid = BNXT_ULP_CLASS_HID_2dce0, + [4262] = { + .class_hid = BNXT_ULP_CLASS_HID_2bbec, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 272, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76693,20 +89123,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3683] = { - .class_hid = BNXT_ULP_CLASS_HID_349e0, + [4263] = { + .class_hid = BNXT_ULP_CLASS_HID_29fcc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 273, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76714,20 +89142,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3684] = { - .class_hid = BNXT_ULP_CLASS_HID_397d4, + [4264] = { + .class_hid = BNXT_ULP_CLASS_HID_28588, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 274, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76735,21 +89161,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3685] = { - .class_hid = BNXT_ULP_CLASS_HID_23f30, + [4265] = { + .class_hid = BNXT_ULP_CLASS_HID_2d684, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 275, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76757,20 +89181,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3686] = { - .class_hid = BNXT_ULP_CLASS_HID_2a830, + [4266] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc40, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 275, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76778,21 +89200,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3687] = { - .class_hid = BNXT_ULP_CLASS_HID_35530, + [4267] = { + .class_hid = BNXT_ULP_CLASS_HID_2a020, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 275, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76800,21 +89220,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3688] = { - .class_hid = BNXT_ULP_CLASS_HID_3de30, + [4268] = { + .class_hid = BNXT_ULP_CLASS_HID_2a61c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 275, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76822,22 +89240,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3689] = { - .class_hid = BNXT_ULP_CLASS_HID_23be4, + [4269] = { + .class_hid = BNXT_ULP_CLASS_HID_6a3d4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 275, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76845,21 +89261,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3690] = { - .class_hid = BNXT_ULP_CLASS_HID_2a4e4, + [4270] = { + .class_hid = BNXT_ULP_CLASS_HID_6a990, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 275, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76867,22 +89279,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3691] = { - .class_hid = BNXT_ULP_CLASS_HID_351e4, + [4271] = { + .class_hid = BNXT_ULP_CLASS_HID_68d70, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 276, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76890,22 +89298,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3692] = { - .class_hid = BNXT_ULP_CLASS_HID_3dae4, + [4272] = { + .class_hid = BNXT_ULP_CLASS_HID_6b32c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 277, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76913,23 +89317,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3693] = { - .class_hid = BNXT_ULP_CLASS_HID_22cd4, + [4273] = { + .class_hid = BNXT_ULP_CLASS_HID_6c428, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76937,20 +89337,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3694] = { - .class_hid = BNXT_ULP_CLASS_HID_2d9d4, + [4274] = { + .class_hid = BNXT_ULP_CLASS_HID_6cde4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76958,21 +89356,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3695] = { - .class_hid = BNXT_ULP_CLASS_HID_342d4, + [4275] = { + .class_hid = BNXT_ULP_CLASS_HID_6d1c4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -76980,21 +89376,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3696] = { - .class_hid = BNXT_ULP_CLASS_HID_39088, + [4276] = { + .class_hid = BNXT_ULP_CLASS_HID_6d780, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77002,22 +89396,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3697] = { - .class_hid = BNXT_ULP_CLASS_HID_21928, + [4277] = { + .class_hid = BNXT_ULP_CLASS_HID_68ee4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77025,20 +89417,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3698] = { - .class_hid = BNXT_ULP_CLASS_HID_28228, + [4278] = { + .class_hid = BNXT_ULP_CLASS_HID_6b4a0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77046,21 +89436,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3699] = { - .class_hid = BNXT_ULP_CLASS_HID_30f28, + [4279] = { + .class_hid = BNXT_ULP_CLASS_HID_69880, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77068,21 +89456,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3700] = { - .class_hid = BNXT_ULP_CLASS_HID_3b828, + [4280] = { + .class_hid = BNXT_ULP_CLASS_HID_69e7c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77090,22 +89476,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3701] = { - .class_hid = BNXT_ULP_CLASS_HID_24384, + [4281] = { + .class_hid = BNXT_ULP_CLASS_HID_6d378, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77113,21 +89497,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3702] = { - .class_hid = BNXT_ULP_CLASS_HID_29178, + [4282] = { + .class_hid = BNXT_ULP_CLASS_HID_6d934, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77135,22 +89517,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3703] = { - .class_hid = BNXT_ULP_CLASS_HID_31a78, + [4283] = { + .class_hid = BNXT_ULP_CLASS_HID_6bd14, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77158,22 +89538,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3704] = { - .class_hid = BNXT_ULP_CLASS_HID_38778, + [4284] = { + .class_hid = BNXT_ULP_CLASS_HID_6a2d0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77181,23 +89559,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3705] = { - .class_hid = BNXT_ULP_CLASS_HID_25c78, + [4285] = { + .class_hid = BNXT_ULP_CLASS_HID_3dce0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77205,22 +89581,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3706] = { - .class_hid = BNXT_ULP_CLASS_HID_2c978, + [4286] = { + .class_hid = BNXT_ULP_CLASS_HID_3c2dc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77228,23 +89599,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3707] = { - .class_hid = BNXT_ULP_CLASS_HID_3172c, + [4287] = { + .class_hid = BNXT_ULP_CLASS_HID_3a6bc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77252,23 +89618,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3708] = { - .class_hid = BNXT_ULP_CLASS_HID_3802c, + [4288] = { + .class_hid = BNXT_ULP_CLASS_HID_3ac78, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77276,24 +89637,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3709] = { - .class_hid = BNXT_ULP_CLASS_HID_2121c, + [4289] = { + .class_hid = BNXT_ULP_CLASS_HID_38228, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77301,21 +89657,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3710] = { - .class_hid = BNXT_ULP_CLASS_HID_29f1c, + [4290] = { + .class_hid = BNXT_ULP_CLASS_HID_38be4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77323,22 +89676,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3711] = { - .class_hid = BNXT_ULP_CLASS_HID_3081c, + [4291] = { + .class_hid = BNXT_ULP_CLASS_HID_3cb10, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77346,22 +89696,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3712] = { - .class_hid = BNXT_ULP_CLASS_HID_3b51c, + [4292] = { + .class_hid = BNXT_ULP_CLASS_HID_39580, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77369,23 +89716,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3713] = { - .class_hid = BNXT_ULP_CLASS_HID_24088, + [4293] = { + .class_hid = BNXT_ULP_CLASS_HID_3a830, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77393,17 +89737,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3714] = { - .class_hid = BNXT_ULP_CLASS_HID_2cd88, + [4294] = { + .class_hid = BNXT_ULP_CLASS_HID_3d1ec, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77411,18 +89756,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3715] = { - .class_hid = BNXT_ULP_CLASS_HID_31b7c, + [4295] = { + .class_hid = BNXT_ULP_CLASS_HID_3b5cc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77430,18 +89776,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3716] = { - .class_hid = BNXT_ULP_CLASS_HID_3847c, + [4296] = { + .class_hid = BNXT_ULP_CLASS_HID_3bb88, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77449,19 +89796,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3717] = { - .class_hid = BNXT_ULP_CLASS_HID_22fd8, + [4297] = { + .class_hid = BNXT_ULP_CLASS_HID_39178, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77469,18 +89817,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3718] = { - .class_hid = BNXT_ULP_CLASS_HID_2d8d8, + [4298] = { + .class_hid = BNXT_ULP_CLASS_HID_39734, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77488,19 +89837,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3719] = { - .class_hid = BNXT_ULP_CLASS_HID_345d8, + [4299] = { + .class_hid = BNXT_ULP_CLASS_HID_3d620, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77508,19 +89858,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3720] = { - .class_hid = BNXT_ULP_CLASS_HID_3938c, + [4300] = { + .class_hid = BNXT_ULP_CLASS_HID_3dc1c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77528,20 +89879,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3721] = { - .class_hid = BNXT_ULP_CLASS_HID_2288c, + [4301] = { + .class_hid = BNXT_ULP_CLASS_HID_7d9d4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77549,19 +89901,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3722] = { - .class_hid = BNXT_ULP_CLASS_HID_2d58c, + [4302] = { + .class_hid = BNXT_ULP_CLASS_HID_7df90, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77569,20 +89920,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3723] = { - .class_hid = BNXT_ULP_CLASS_HID_35e8c, + [4303] = { + .class_hid = BNXT_ULP_CLASS_HID_7a370, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77590,20 +89940,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3724] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb8c, + [4304] = { + .class_hid = BNXT_ULP_CLASS_HID_7a92c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77611,40 +89960,40 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3725] = { - .class_hid = BNXT_ULP_CLASS_HID_25d7c, + [4305] = { + .class_hid = BNXT_ULP_CLASS_HID_79f1c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3726] = { - .class_hid = BNXT_ULP_CLASS_HID_2c67c, + [4306] = { + .class_hid = BNXT_ULP_CLASS_HID_784d8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77652,19 +90001,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3727] = { - .class_hid = BNXT_ULP_CLASS_HID_31430, + [4307] = { + .class_hid = BNXT_ULP_CLASS_HID_7c7c4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77672,19 +90022,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3728] = { - .class_hid = BNXT_ULP_CLASS_HID_38130, + [4308] = { + .class_hid = BNXT_ULP_CLASS_HID_7cd80, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77692,20 +90043,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3729] = { - .class_hid = BNXT_ULP_CLASS_HID_209d0, + [4309] = { + .class_hid = BNXT_ULP_CLASS_HID_7a4e4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77713,18 +90065,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3730] = { - .class_hid = BNXT_ULP_CLASS_HID_2b2d0, + [4310] = { + .class_hid = BNXT_ULP_CLASS_HID_7aaa0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77732,19 +90085,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3731] = { - .class_hid = BNXT_ULP_CLASS_HID_33fd0, + [4311] = { + .class_hid = BNXT_ULP_CLASS_HID_78e80, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77752,19 +90106,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3732] = { - .class_hid = BNXT_ULP_CLASS_HID_3a8d0, + [4312] = { + .class_hid = BNXT_ULP_CLASS_HID_7b47c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77772,20 +90127,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3733] = { - .class_hid = BNXT_ULP_CLASS_HID_214e0, + [4313] = { + .class_hid = BNXT_ULP_CLASS_HID_7c978, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77793,19 +90149,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3734] = { - .class_hid = BNXT_ULP_CLASS_HID_281e0, + [4314] = { + .class_hid = BNXT_ULP_CLASS_HID_793e8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77813,20 +90170,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3735] = { - .class_hid = BNXT_ULP_CLASS_HID_30ae0, + [4315] = { + .class_hid = BNXT_ULP_CLASS_HID_7d314, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77834,20 +90192,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3736] = { - .class_hid = BNXT_ULP_CLASS_HID_3b7e0, + [4316] = { + .class_hid = BNXT_ULP_CLASS_HID_7d8d0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -77855,4417 +90214,4102 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3737] = { - .class_hid = BNXT_ULP_CLASS_HID_211d4, + [4317] = { + .class_hid = BNXT_ULP_CLASS_HID_9ad8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3738] = { - .class_hid = BNXT_ULP_CLASS_HID_29ad4, + [4318] = { + .class_hid = BNXT_ULP_CLASS_HID_80e4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3739] = { - .class_hid = BNXT_ULP_CLASS_HID_307d4, + [4319] = { + .class_hid = BNXT_ULP_CLASS_HID_c3f0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3740] = { - .class_hid = BNXT_ULP_CLASS_HID_3b0d4, + [4320] = { + .class_hid = BNXT_ULP_CLASS_HID_c9bc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3741] = { - .class_hid = BNXT_ULP_CLASS_HID_20284, + [4321] = { + .class_hid = BNXT_ULP_CLASS_HID_bf4c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3742] = { - .class_hid = BNXT_ULP_CLASS_HID_28f84, + [4322] = { + .class_hid = BNXT_ULP_CLASS_HID_a508, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3743] = { - .class_hid = BNXT_ULP_CLASS_HID_33884, + [4323] = { + .class_hid = BNXT_ULP_CLASS_HID_8928, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3744] = { - .class_hid = BNXT_ULP_CLASS_HID_3a584, + [4324] = { + .class_hid = BNXT_ULP_CLASS_HID_8ef4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3745] = { - .class_hid = BNXT_ULP_CLASS_HID_22a24, + [4325] = { + .class_hid = BNXT_ULP_CLASS_HID_497ec, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3746] = { - .class_hid = BNXT_ULP_CLASS_HID_2d724, + [4326] = { + .class_hid = BNXT_ULP_CLASS_HID_49da8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3747] = { - .class_hid = BNXT_ULP_CLASS_HID_34024, + [4327] = { + .class_hid = BNXT_ULP_CLASS_HID_4dc84, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3748] = { - .class_hid = BNXT_ULP_CLASS_HID_3cd24, + [4328] = { + .class_hid = BNXT_ULP_CLASS_HID_4c240, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3749] = { - .class_hid = BNXT_ULP_CLASS_HID_23974, + [4329] = { + .class_hid = BNXT_ULP_CLASS_HID_4b810, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3750] = { - .class_hid = BNXT_ULP_CLASS_HID_2a274, + [4330] = { + .class_hid = BNXT_ULP_CLASS_HID_4a1dc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3751] = { - .class_hid = BNXT_ULP_CLASS_HID_32f74, + [4331] = { + .class_hid = BNXT_ULP_CLASS_HID_485fc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3752] = { - .class_hid = BNXT_ULP_CLASS_HID_3d874, + [4332] = { + .class_hid = BNXT_ULP_CLASS_HID_48bb8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3753] = { - .class_hid = BNXT_ULP_CLASS_HID_23228, + [4333] = { + .class_hid = BNXT_ULP_CLASS_HID_1b0d8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3754] = { - .class_hid = BNXT_ULP_CLASS_HID_2bf28, + [4334] = { + .class_hid = BNXT_ULP_CLASS_HID_1b6e4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3755] = { - .class_hid = BNXT_ULP_CLASS_HID_32828, + [4335] = { + .class_hid = BNXT_ULP_CLASS_HID_19a84, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3756] = { - .class_hid = BNXT_ULP_CLASS_HID_3d528, + [4336] = { + .class_hid = BNXT_ULP_CLASS_HID_18040, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3757] = { - .class_hid = BNXT_ULP_CLASS_HID_22718, + [4337] = { + .class_hid = BNXT_ULP_CLASS_HID_1d54c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3758] = { - .class_hid = BNXT_ULP_CLASS_HID_2d018, + [4338] = { + .class_hid = BNXT_ULP_CLASS_HID_1db08, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3759] = { - .class_hid = BNXT_ULP_CLASS_HID_35d18, + [4339] = { + .class_hid = BNXT_ULP_CLASS_HID_1bf28, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3760] = { - .class_hid = BNXT_ULP_CLASS_HID_3c618, + [4340] = { + .class_hid = BNXT_ULP_CLASS_HID_1a4f4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3761] = { - .class_hid = BNXT_ULP_CLASS_HID_2136c, + [4341] = { + .class_hid = BNXT_ULP_CLASS_HID_58dec, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3762] = { - .class_hid = BNXT_ULP_CLASS_HID_29c6c, + [4342] = { + .class_hid = BNXT_ULP_CLASS_HID_5b3a8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3763] = { - .class_hid = BNXT_ULP_CLASS_HID_3096c, + [4343] = { + .class_hid = BNXT_ULP_CLASS_HID_59748, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3764] = { - .class_hid = BNXT_ULP_CLASS_HID_3b26c, + [4344] = { + .class_hid = BNXT_ULP_CLASS_HID_59d14, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3765] = { - .class_hid = BNXT_ULP_CLASS_HID_25dc8, + [4345] = { + .class_hid = BNXT_ULP_CLASS_HID_5ae10, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3766] = { - .class_hid = BNXT_ULP_CLASS_HID_2c6c8, + [4346] = { + .class_hid = BNXT_ULP_CLASS_HID_5d7dc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3767] = { - .class_hid = BNXT_ULP_CLASS_HID_314bc, + [4347] = { + .class_hid = BNXT_ULP_CLASS_HID_5bbfc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3768] = { - .class_hid = BNXT_ULP_CLASS_HID_381bc, + [4348] = { + .class_hid = BNXT_ULP_CLASS_HID_5a1b8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3769] = { - .class_hid = BNXT_ULP_CLASS_HID_256bc, + [4349] = { + .class_hid = BNXT_ULP_CLASS_HID_c158, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3770] = { - .class_hid = BNXT_ULP_CLASS_HID_2c3bc, + [4350] = { + .class_hid = BNXT_ULP_CLASS_HID_c764, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3771] = { - .class_hid = BNXT_ULP_CLASS_HID_31170, + [4351] = { + .class_hid = BNXT_ULP_CLASS_HID_c670, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3772] = { - .class_hid = BNXT_ULP_CLASS_HID_39a70, + [4352] = { + .class_hid = BNXT_ULP_CLASS_HID_d0c0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3773] = { - .class_hid = BNXT_ULP_CLASS_HID_24b6c, + [4353] = { + .class_hid = BNXT_ULP_CLASS_HID_e5cc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3774] = { - .class_hid = BNXT_ULP_CLASS_HID_29920, + [4354] = { + .class_hid = BNXT_ULP_CLASS_HID_eb88, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3775] = { - .class_hid = BNXT_ULP_CLASS_HID_30220, + [4355] = { + .class_hid = BNXT_ULP_CLASS_HID_cfa8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3776] = { - .class_hid = BNXT_ULP_CLASS_HID_38f20, + [4356] = { + .class_hid = BNXT_ULP_CLASS_HID_f574, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3777] = { - .class_hid = BNXT_ULP_CLASS_HID_22f54, + [4357] = { + .class_hid = BNXT_ULP_CLASS_HID_4da6c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3778] = { - .class_hid = BNXT_ULP_CLASS_HID_2d854, + [4358] = { + .class_hid = BNXT_ULP_CLASS_HID_4c028, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3779] = { - .class_hid = BNXT_ULP_CLASS_HID_34554, + [4359] = { + .class_hid = BNXT_ULP_CLASS_HID_4c304, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3780] = { - .class_hid = BNXT_ULP_CLASS_HID_39308, + [4360] = { + .class_hid = BNXT_ULP_CLASS_HID_4c8c0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3781] = { - .class_hid = BNXT_ULP_CLASS_HID_23a64, + [4361] = { + .class_hid = BNXT_ULP_CLASS_HID_4fe90, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3782] = { - .class_hid = BNXT_ULP_CLASS_HID_2a764, + [4362] = { + .class_hid = BNXT_ULP_CLASS_HID_4e45c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3783] = { - .class_hid = BNXT_ULP_CLASS_HID_35064, + [4363] = { + .class_hid = BNXT_ULP_CLASS_HID_4c87c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3784] = { - .class_hid = BNXT_ULP_CLASS_HID_3dd64, + [4364] = { + .class_hid = BNXT_ULP_CLASS_HID_4ce38, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3785] = { - .class_hid = BNXT_ULP_CLASS_HID_23758, + [4365] = { + .class_hid = BNXT_ULP_CLASS_HID_1f758, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3786] = { - .class_hid = BNXT_ULP_CLASS_HID_2a058, + [4366] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd64, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3787] = { - .class_hid = BNXT_ULP_CLASS_HID_32d58, + [4367] = { + .class_hid = BNXT_ULP_CLASS_HID_1c104, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3788] = { - .class_hid = BNXT_ULP_CLASS_HID_3d658, + [4368] = { + .class_hid = BNXT_ULP_CLASS_HID_1c6c0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3789] = { - .class_hid = BNXT_ULP_CLASS_HID_22808, + [4369] = { + .class_hid = BNXT_ULP_CLASS_HID_1dbcc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3790] = { - .class_hid = BNXT_ULP_CLASS_HID_2d508, + [4370] = { + .class_hid = BNXT_ULP_CLASS_HID_1c188, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3791] = { - .class_hid = BNXT_ULP_CLASS_HID_35e08, + [4371] = { + .class_hid = BNXT_ULP_CLASS_HID_1e5a8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3792] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb08, + [4372] = { + .class_hid = BNXT_ULP_CLASS_HID_1eb74, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3793] = { - .class_hid = BNXT_ULP_CLASS_HID_2149c, + [4373] = { + .class_hid = BNXT_ULP_CLASS_HID_5f06c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3794] = { - .class_hid = BNXT_ULP_CLASS_HID_2819c, + [4374] = { + .class_hid = BNXT_ULP_CLASS_HID_5f628, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3795] = { - .class_hid = BNXT_ULP_CLASS_HID_30a9c, + [4375] = { + .class_hid = BNXT_ULP_CLASS_HID_5ddc8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3796] = { - .class_hid = BNXT_ULP_CLASS_HID_3b79c, + [4376] = { + .class_hid = BNXT_ULP_CLASS_HID_5c394, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3797] = { - .class_hid = BNXT_ULP_CLASS_HID_25ef8, + [4377] = { + .class_hid = BNXT_ULP_CLASS_HID_5d490, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3798] = { - .class_hid = BNXT_ULP_CLASS_HID_2cbf8, + [4378] = { + .class_hid = BNXT_ULP_CLASS_HID_5da5c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3799] = { - .class_hid = BNXT_ULP_CLASS_HID_319ac, + [4379] = { + .class_hid = BNXT_ULP_CLASS_HID_5fe7c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3800] = { - .class_hid = BNXT_ULP_CLASS_HID_382ac, + [4380] = { + .class_hid = BNXT_ULP_CLASS_HID_5e438, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3801] = { - .class_hid = BNXT_ULP_CLASS_HID_25bac, + [4381] = { + .class_hid = BNXT_ULP_CLASS_HID_bc18, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3802] = { - .class_hid = BNXT_ULP_CLASS_HID_2c4ac, + [4382] = { + .class_hid = BNXT_ULP_CLASS_HID_a224, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3803] = { - .class_hid = BNXT_ULP_CLASS_HID_31260, + [4383] = { + .class_hid = BNXT_ULP_CLASS_HID_e530, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3804] = { - .class_hid = BNXT_ULP_CLASS_HID_39f60, + [4384] = { + .class_hid = BNXT_ULP_CLASS_HID_eafc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3805] = { - .class_hid = BNXT_ULP_CLASS_HID_21150, + [4385] = { + .class_hid = BNXT_ULP_CLASS_HID_a08c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3806] = { - .class_hid = BNXT_ULP_CLASS_HID_29a50, + [4386] = { + .class_hid = BNXT_ULP_CLASS_HID_a648, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3807] = { - .class_hid = BNXT_ULP_CLASS_HID_30750, + [4387] = { + .class_hid = BNXT_ULP_CLASS_HID_aa68, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3808] = { - .class_hid = BNXT_ULP_CLASS_HID_3b050, + [4388] = { + .class_hid = BNXT_ULP_CLASS_HID_b034, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3809] = { - .class_hid = BNXT_ULP_CLASS_HID_238f0, + [4389] = { + .class_hid = BNXT_ULP_CLASS_HID_4b92c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3810] = { - .class_hid = BNXT_ULP_CLASS_HID_2a5f0, + [4390] = { + .class_hid = BNXT_ULP_CLASS_HID_4bee8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 278, - .flow_pattern_id = 0, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3811] = { - .class_hid = BNXT_ULP_CLASS_HID_32ef0, + [4391] = { + .class_hid = BNXT_ULP_CLASS_HID_4e1c4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 279, - .flow_pattern_id = 0, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3812] = { - .class_hid = BNXT_ULP_CLASS_HID_3dbf0, + [4392] = { + .class_hid = BNXT_ULP_CLASS_HID_4e780, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 280, - .flow_pattern_id = 0, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3813] = { - .class_hid = BNXT_ULP_CLASS_HID_20400, + [4393] = { + .class_hid = BNXT_ULP_CLASS_HID_4bd50, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 281, - .flow_pattern_id = 0, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3814] = { - .class_hid = BNXT_ULP_CLASS_HID_2b100, + [4394] = { + .class_hid = BNXT_ULP_CLASS_HID_4a31c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 281, - .flow_pattern_id = 0, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3815] = { - .class_hid = BNXT_ULP_CLASS_HID_33a00, + [4395] = { + .class_hid = BNXT_ULP_CLASS_HID_4a73c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 281, - .flow_pattern_id = 0, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3816] = { - .class_hid = BNXT_ULP_CLASS_HID_3a700, + [4396] = { + .class_hid = BNXT_ULP_CLASS_HID_4acf8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 281, - .flow_pattern_id = 0, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3817] = { - .class_hid = BNXT_ULP_CLASS_HID_200f4, + [4397] = { + .class_hid = BNXT_ULP_CLASS_HID_1b218, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 281, - .flow_pattern_id = 0, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3818] = { - .class_hid = BNXT_ULP_CLASS_HID_28df4, + [4398] = { + .class_hid = BNXT_ULP_CLASS_HID_1b824, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 281, - .flow_pattern_id = 0, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3819] = { - .class_hid = BNXT_ULP_CLASS_HID_336f4, + [4399] = { + .class_hid = BNXT_ULP_CLASS_HID_1bfc4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 282, - .flow_pattern_id = 0, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3820] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3f4, + [4400] = { + .class_hid = BNXT_ULP_CLASS_HID_1a580, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 283, - .flow_pattern_id = 0, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3821] = { - .class_hid = BNXT_ULP_CLASS_HID_235a4, + [4401] = { + .class_hid = BNXT_ULP_CLASS_HID_1f68c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3822] = { - .class_hid = BNXT_ULP_CLASS_HID_2bea4, + [4402] = { + .class_hid = BNXT_ULP_CLASS_HID_1fc48, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3823] = { - .class_hid = BNXT_ULP_CLASS_HID_32ba4, + [4403] = { + .class_hid = BNXT_ULP_CLASS_HID_1a068, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3824] = { - .class_hid = BNXT_ULP_CLASS_HID_3d4a4, + [4404] = { + .class_hid = BNXT_ULP_CLASS_HID_1a634, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3825] = { - .class_hid = BNXT_ULP_CLASS_HID_25d44, + [4405] = { + .class_hid = BNXT_ULP_CLASS_HID_5af2c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3826] = { - .class_hid = BNXT_ULP_CLASS_HID_2c644, + [4406] = { + .class_hid = BNXT_ULP_CLASS_HID_5b4e8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3827] = { - .class_hid = BNXT_ULP_CLASS_HID_31438, + [4407] = { + .class_hid = BNXT_ULP_CLASS_HID_5b888, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3828] = { - .class_hid = BNXT_ULP_CLASS_HID_38138, + [4408] = { + .class_hid = BNXT_ULP_CLASS_HID_5be54, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3829] = { - .class_hid = BNXT_ULP_CLASS_HID_22894, + [4409] = { + .class_hid = BNXT_ULP_CLASS_HID_5f350, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3830] = { - .class_hid = BNXT_ULP_CLASS_HID_2d594, + [4410] = { + .class_hid = BNXT_ULP_CLASS_HID_5f91c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3831] = { - .class_hid = BNXT_ULP_CLASS_HID_35e94, + [4411] = { + .class_hid = BNXT_ULP_CLASS_HID_5bd3c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3832] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb94, + [4412] = { + .class_hid = BNXT_ULP_CLASS_HID_5a2f8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3833] = { - .class_hid = BNXT_ULP_CLASS_HID_22548, + [4413] = { + .class_hid = BNXT_ULP_CLASS_HID_e298, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3834] = { - .class_hid = BNXT_ULP_CLASS_HID_2ae48, + [4414] = { + .class_hid = BNXT_ULP_CLASS_HID_e8a4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3835] = { - .class_hid = BNXT_ULP_CLASS_HID_35b48, + [4415] = { + .class_hid = BNXT_ULP_CLASS_HID_ebb0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3836] = { - .class_hid = BNXT_ULP_CLASS_HID_3c448, + [4416] = { + .class_hid = BNXT_ULP_CLASS_HID_f200, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3837] = { - .class_hid = BNXT_ULP_CLASS_HID_25638, + [4417] = { + .class_hid = BNXT_ULP_CLASS_HID_e70c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3838] = { - .class_hid = BNXT_ULP_CLASS_HID_2c338, + [4418] = { + .class_hid = BNXT_ULP_CLASS_HID_ecc8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3839] = { - .class_hid = BNXT_ULP_CLASS_HID_310ec, + [4419] = { + .class_hid = BNXT_ULP_CLASS_HID_f0e8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3840] = { - .class_hid = BNXT_ULP_CLASS_HID_39dec, + [4420] = { + .class_hid = BNXT_ULP_CLASS_HID_f6b4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3841] = { - .class_hid = BNXT_ULP_CLASS_HID_22998, + [4421] = { + .class_hid = BNXT_ULP_CLASS_HID_4ffac, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3842] = { - .class_hid = BNXT_ULP_CLASS_HID_2d298, + [4422] = { + .class_hid = BNXT_ULP_CLASS_HID_4e568, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3843] = { - .class_hid = BNXT_ULP_CLASS_HID_35f98, + [4423] = { + .class_hid = BNXT_ULP_CLASS_HID_4e444, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3844] = { - .class_hid = BNXT_ULP_CLASS_HID_3c898, + [4424] = { + .class_hid = BNXT_ULP_CLASS_HID_4ea00, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3845] = { - .class_hid = BNXT_ULP_CLASS_HID_234a8, + [4425] = { + .class_hid = BNXT_ULP_CLASS_HID_4e3d0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3846] = { - .class_hid = BNXT_ULP_CLASS_HID_2a1a8, + [4426] = { + .class_hid = BNXT_ULP_CLASS_HID_4e99c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3847] = { - .class_hid = BNXT_ULP_CLASS_HID_32aa8, + [4427] = { + .class_hid = BNXT_ULP_CLASS_HID_4edbc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3848] = { - .class_hid = BNXT_ULP_CLASS_HID_3d7a8, + [4428] = { + .class_hid = BNXT_ULP_CLASS_HID_4f378, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3849] = { - .class_hid = BNXT_ULP_CLASS_HID_2319c, + [4429] = { + .class_hid = BNXT_ULP_CLASS_HID_1f898, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3850] = { - .class_hid = BNXT_ULP_CLASS_HID_2ba9c, + [4430] = { + .class_hid = BNXT_ULP_CLASS_HID_1fea4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3851] = { - .class_hid = BNXT_ULP_CLASS_HID_3279c, + [4431] = { + .class_hid = BNXT_ULP_CLASS_HID_1e244, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3852] = { - .class_hid = BNXT_ULP_CLASS_HID_3d09c, + [4432] = { + .class_hid = BNXT_ULP_CLASS_HID_1e800, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3853] = { - .class_hid = BNXT_ULP_CLASS_HID_2224c, + [4433] = { + .class_hid = BNXT_ULP_CLASS_HID_1fd0c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3854] = { - .class_hid = BNXT_ULP_CLASS_HID_2af4c, + [4434] = { + .class_hid = BNXT_ULP_CLASS_HID_1e2c8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3855] = { - .class_hid = BNXT_ULP_CLASS_HID_3584c, + [4435] = { + .class_hid = BNXT_ULP_CLASS_HID_1e6e8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3856] = { - .class_hid = BNXT_ULP_CLASS_HID_3c54c, + [4436] = { + .class_hid = BNXT_ULP_CLASS_HID_1ecb4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3857] = { - .class_hid = BNXT_ULP_CLASS_HID_24dec, + [4437] = { + .class_hid = BNXT_ULP_CLASS_HID_5f5ac, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3858] = { - .class_hid = BNXT_ULP_CLASS_HID_29ba0, + [4438] = { + .class_hid = BNXT_ULP_CLASS_HID_5fb68, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3859] = { - .class_hid = BNXT_ULP_CLASS_HID_304a0, + [4439] = { + .class_hid = BNXT_ULP_CLASS_HID_5ff08, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3860] = { - .class_hid = BNXT_ULP_CLASS_HID_3b1a0, + [4440] = { + .class_hid = BNXT_ULP_CLASS_HID_5e4d4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3861] = { - .class_hid = BNXT_ULP_CLASS_HID_2593c, + [4441] = { + .class_hid = BNXT_ULP_CLASS_HID_5f9d0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3862] = { - .class_hid = BNXT_ULP_CLASS_HID_2c23c, + [4442] = { + .class_hid = BNXT_ULP_CLASS_HID_5ff9c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3863] = { - .class_hid = BNXT_ULP_CLASS_HID_313f0, + [4443] = { + .class_hid = BNXT_ULP_CLASS_HID_5e3bc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3864] = { - .class_hid = BNXT_ULP_CLASS_HID_39cf0, + [4444] = { + .class_hid = BNXT_ULP_CLASS_HID_5e978, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3865] = { - .class_hid = BNXT_ULP_CLASS_HID_255f0, + [4445] = { + .class_hid = BNXT_ULP_CLASS_HID_34f6, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3866] = { - .class_hid = BNXT_ULP_CLASS_HID_2def0, + [4446] = { + .class_hid = BNXT_ULP_CLASS_HID_3a3a, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3867] = { - .class_hid = BNXT_ULP_CLASS_HID_34bf0, + [4447] = { + .class_hid = BNXT_ULP_CLASS_HID_541e, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3868] = { - .class_hid = BNXT_ULP_CLASS_HID_399a4, + [4448] = { + .class_hid = BNXT_ULP_CLASS_HID_5a22, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3869] = { - .class_hid = BNXT_ULP_CLASS_HID_246a0, + [4449] = { + .class_hid = BNXT_ULP_CLASS_HID_34fe, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3870] = { - .class_hid = BNXT_ULP_CLASS_HID_29494, + [4450] = { + .class_hid = BNXT_ULP_CLASS_HID_3a32, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3871] = { - .class_hid = BNXT_ULP_CLASS_HID_30194, + [4451] = { + .class_hid = BNXT_ULP_CLASS_HID_4a42, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3872] = { - .class_hid = BNXT_ULP_CLASS_HID_38a94, + [4452] = { + .class_hid = BNXT_ULP_CLASS_HID_14d2, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3873] = { - .class_hid = BNXT_ULP_CLASS_HID_23334, + [4453] = { + .class_hid = BNXT_ULP_CLASS_HID_34c8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3874] = { - .class_hid = BNXT_ULP_CLASS_HID_2bc34, + [4454] = { + .class_hid = BNXT_ULP_CLASS_HID_3a04, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3875] = { - .class_hid = BNXT_ULP_CLASS_HID_32934, + [4455] = { + .class_hid = BNXT_ULP_CLASS_HID_1e64, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3876] = { - .class_hid = BNXT_ULP_CLASS_HID_3d234, + [4456] = { + .class_hid = BNXT_ULP_CLASS_HID_07a0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3877] = { - .class_hid = BNXT_ULP_CLASS_HID_21e44, + [4457] = { + .class_hid = BNXT_ULP_CLASS_HID_595c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3878] = { - .class_hid = BNXT_ULP_CLASS_HID_28b44, + [4458] = { + .class_hid = BNXT_ULP_CLASS_HID_5e98, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3879] = { - .class_hid = BNXT_ULP_CLASS_HID_33444, + [4459] = { + .class_hid = BNXT_ULP_CLASS_HID_22f8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3880] = { - .class_hid = BNXT_ULP_CLASS_HID_3a144, + [4460] = { + .class_hid = BNXT_ULP_CLASS_HID_2834, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3881] = { - .class_hid = BNXT_ULP_CLASS_HID_21b38, + [4461] = { + .class_hid = BNXT_ULP_CLASS_HID_0398, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3882] = { - .class_hid = BNXT_ULP_CLASS_HID_28438, + [4462] = { + .class_hid = BNXT_ULP_CLASS_HID_09d4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3883] = { - .class_hid = BNXT_ULP_CLASS_HID_33138, + [4463] = { + .class_hid = BNXT_ULP_CLASS_HID_48c0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3884] = { - .class_hid = BNXT_ULP_CLASS_HID_3ba38, + [4464] = { + .class_hid = BNXT_ULP_CLASS_HID_1370, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3885] = { - .class_hid = BNXT_ULP_CLASS_HID_20fe8, + [4465] = { + .class_hid = BNXT_ULP_CLASS_HID_246c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3886] = { - .class_hid = BNXT_ULP_CLASS_HID_2b8e8, + [4466] = { + .class_hid = BNXT_ULP_CLASS_HID_2da8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3887] = { - .class_hid = BNXT_ULP_CLASS_HID_325e8, + [4467] = { + .class_hid = BNXT_ULP_CLASS_HID_3188, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3888] = { - .class_hid = BNXT_ULP_CLASS_HID_3aee8, + [4468] = { + .class_hid = BNXT_ULP_CLASS_HID_37c4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3889] = { - .class_hid = BNXT_ULP_CLASS_HID_25788, + [4469] = { + .class_hid = BNXT_ULP_CLASS_HID_34f0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3890] = { - .class_hid = BNXT_ULP_CLASS_HID_2c088, + [4470] = { + .class_hid = BNXT_ULP_CLASS_HID_3a3c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3891] = { - .class_hid = BNXT_ULP_CLASS_HID_34d88, + [4471] = { + .class_hid = BNXT_ULP_CLASS_HID_1e5c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3892] = { - .class_hid = BNXT_ULP_CLASS_HID_39b7c, + [4472] = { + .class_hid = BNXT_ULP_CLASS_HID_0798, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3893] = { - .class_hid = BNXT_ULP_CLASS_HID_222d8, + [4473] = { + .class_hid = BNXT_ULP_CLASS_HID_5964, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3894] = { - .class_hid = BNXT_ULP_CLASS_HID_2afd8, + [4474] = { + .class_hid = BNXT_ULP_CLASS_HID_5ea0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3895] = { - .class_hid = BNXT_ULP_CLASS_HID_358d8, + [4475] = { + .class_hid = BNXT_ULP_CLASS_HID_22c0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3896] = { - .class_hid = BNXT_ULP_CLASS_HID_3c5d8, + [4476] = { + .class_hid = BNXT_ULP_CLASS_HID_280c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3897] = { - .class_hid = BNXT_ULP_CLASS_HID_23f8c, + [4477] = { + .class_hid = BNXT_ULP_CLASS_HID_43104, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3898] = { - .class_hid = BNXT_ULP_CLASS_HID_2a88c, + [4478] = { + .class_hid = BNXT_ULP_CLASS_HID_43740, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3899] = { - .class_hid = BNXT_ULP_CLASS_HID_3558c, + [4479] = { + .class_hid = BNXT_ULP_CLASS_HID_41b60, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3900] = { - .class_hid = BNXT_ULP_CLASS_HID_3de8c, + [4480] = { + .class_hid = BNXT_ULP_CLASS_HID_400ac, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3901] = { - .class_hid = BNXT_ULP_CLASS_HID_2507c, + [4481] = { + .class_hid = BNXT_ULP_CLASS_HID_455a8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3902] = { - .class_hid = BNXT_ULP_CLASS_HID_2dd7c, + [4482] = { + .class_hid = BNXT_ULP_CLASS_HID_45bf4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3903] = { - .class_hid = BNXT_ULP_CLASS_HID_3467c, + [4483] = { + .class_hid = BNXT_ULP_CLASS_HID_43f14, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3904] = { - .class_hid = BNXT_ULP_CLASS_HID_39430, + [4484] = { + .class_hid = BNXT_ULP_CLASS_HID_42550, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3905] = { - .class_hid = BNXT_ULP_CLASS_HID_223dc, + [4485] = { + .class_hid = BNXT_ULP_CLASS_HID_34d6, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3906] = { - .class_hid = BNXT_ULP_CLASS_HID_2acdc, + [4486] = { + .class_hid = BNXT_ULP_CLASS_HID_3a1a, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3907] = { - .class_hid = BNXT_ULP_CLASS_HID_359dc, + [4487] = { + .class_hid = BNXT_ULP_CLASS_HID_543e, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3908] = { - .class_hid = BNXT_ULP_CLASS_HID_3c2dc, + [4488] = { + .class_hid = BNXT_ULP_CLASS_HID_5a02, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3909] = { - .class_hid = BNXT_ULP_CLASS_HID_20eec, + [4489] = { + .class_hid = BNXT_ULP_CLASS_HID_34de, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3910] = { - .class_hid = BNXT_ULP_CLASS_HID_2bbec, + [4490] = { + .class_hid = BNXT_ULP_CLASS_HID_3a12, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3911] = { - .class_hid = BNXT_ULP_CLASS_HID_324ec, + [4491] = { + .class_hid = BNXT_ULP_CLASS_HID_4a62, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3912] = { - .class_hid = BNXT_ULP_CLASS_HID_3d1ec, + [4492] = { + .class_hid = BNXT_ULP_CLASS_HID_14f2, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3913] = { - .class_hid = BNXT_ULP_CLASS_HID_20ba0, + [4493] = { + .class_hid = BNXT_ULP_CLASS_HID_34b6, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3914] = { - .class_hid = BNXT_ULP_CLASS_HID_2b4a0, + [4494] = { + .class_hid = BNXT_ULP_CLASS_HID_3a7a, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3915] = { - .class_hid = BNXT_ULP_CLASS_HID_321a0, + [4495] = { + .class_hid = BNXT_ULP_CLASS_HID_545e, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3916] = { - .class_hid = BNXT_ULP_CLASS_HID_3aaa0, + [4496] = { + .class_hid = BNXT_ULP_CLASS_HID_5a62, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3917] = { - .class_hid = BNXT_ULP_CLASS_HID_23c90, + [4497] = { + .class_hid = BNXT_ULP_CLASS_HID_34be, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3918] = { - .class_hid = BNXT_ULP_CLASS_HID_2a990, + [4498] = { + .class_hid = BNXT_ULP_CLASS_HID_3a72, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3919] = { - .class_hid = BNXT_ULP_CLASS_HID_35290, + [4499] = { + .class_hid = BNXT_ULP_CLASS_HID_4a02, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3920] = { - .class_hid = BNXT_ULP_CLASS_HID_3df90, + [4500] = { + .class_hid = BNXT_ULP_CLASS_HID_1492, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3921] = { - .class_hid = BNXT_ULP_CLASS_HID_24430, + [4501] = { + .class_hid = BNXT_ULP_CLASS_HID_34a8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3922] = { - .class_hid = BNXT_ULP_CLASS_HID_295e4, + [4502] = { + .class_hid = BNXT_ULP_CLASS_HID_3a64, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3923] = { - .class_hid = BNXT_ULP_CLASS_HID_31ee4, + [4503] = { + .class_hid = BNXT_ULP_CLASS_HID_1e04, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3924] = { - .class_hid = BNXT_ULP_CLASS_HID_38be4, + [4504] = { + .class_hid = BNXT_ULP_CLASS_HID_07c0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3925] = { - .class_hid = BNXT_ULP_CLASS_HID_25340, + [4505] = { + .class_hid = BNXT_ULP_CLASS_HID_593c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3926] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc40, + [4506] = { + .class_hid = BNXT_ULP_CLASS_HID_5ef8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3927] = { - .class_hid = BNXT_ULP_CLASS_HID_34940, + [4507] = { + .class_hid = BNXT_ULP_CLASS_HID_2298, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3928] = { - .class_hid = BNXT_ULP_CLASS_HID_39734, + [4508] = { + .class_hid = BNXT_ULP_CLASS_HID_2854, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3929] = { - .class_hid = BNXT_ULP_CLASS_HID_22c34, + [4509] = { + .class_hid = BNXT_ULP_CLASS_HID_03f8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3930] = { - .class_hid = BNXT_ULP_CLASS_HID_2d934, + [4510] = { + .class_hid = BNXT_ULP_CLASS_HID_09b4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3931] = { - .class_hid = BNXT_ULP_CLASS_HID_34234, + [4511] = { + .class_hid = BNXT_ULP_CLASS_HID_48a0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3932] = { - .class_hid = BNXT_ULP_CLASS_HID_393e8, + [4512] = { + .class_hid = BNXT_ULP_CLASS_HID_1310, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3933] = { - .class_hid = BNXT_ULP_CLASS_HID_240e4, + [4513] = { + .class_hid = BNXT_ULP_CLASS_HID_240c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3934] = { - .class_hid = BNXT_ULP_CLASS_HID_2cde4, + [4514] = { + .class_hid = BNXT_ULP_CLASS_HID_2dc8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3935] = { - .class_hid = BNXT_ULP_CLASS_HID_31bd8, + [4515] = { + .class_hid = BNXT_ULP_CLASS_HID_31e8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3936] = { - .class_hid = BNXT_ULP_CLASS_HID_384d8, + [4516] = { + .class_hid = BNXT_ULP_CLASS_HID_37a4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3937] = { - .class_hid = BNXT_ULP_CLASS_HID_23de0, + [4517] = { + .class_hid = BNXT_ULP_CLASS_HID_34d0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3938] = { - .class_hid = BNXT_ULP_CLASS_HID_2a6e0, + [4518] = { + .class_hid = BNXT_ULP_CLASS_HID_3a1c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3939] = { - .class_hid = BNXT_ULP_CLASS_HID_353e0, + [4519] = { + .class_hid = BNXT_ULP_CLASS_HID_1e7c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3940] = { - .class_hid = BNXT_ULP_CLASS_HID_3dce0, + [4520] = { + .class_hid = BNXT_ULP_CLASS_HID_07b8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3941] = { - .class_hid = BNXT_ULP_CLASS_HID_20930, + [4521] = { + .class_hid = BNXT_ULP_CLASS_HID_5944, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3942] = { - .class_hid = BNXT_ULP_CLASS_HID_2b230, + [4522] = { + .class_hid = BNXT_ULP_CLASS_HID_5e80, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3943] = { - .class_hid = BNXT_ULP_CLASS_HID_33f30, + [4523] = { + .class_hid = BNXT_ULP_CLASS_HID_22e0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3944] = { - .class_hid = BNXT_ULP_CLASS_HID_3a830, + [4524] = { + .class_hid = BNXT_ULP_CLASS_HID_282c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3945] = { - .class_hid = BNXT_ULP_CLASS_HID_205e4, + [4525] = { + .class_hid = BNXT_ULP_CLASS_HID_43124, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3946] = { - .class_hid = BNXT_ULP_CLASS_HID_28ee4, + [4526] = { + .class_hid = BNXT_ULP_CLASS_HID_43760, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3947] = { - .class_hid = BNXT_ULP_CLASS_HID_33be4, + [4527] = { + .class_hid = BNXT_ULP_CLASS_HID_41b40, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3948] = { - .class_hid = BNXT_ULP_CLASS_HID_3a4e4, + [4528] = { + .class_hid = BNXT_ULP_CLASS_HID_4008c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3949] = { - .class_hid = BNXT_ULP_CLASS_HID_236d4, + [4529] = { + .class_hid = BNXT_ULP_CLASS_HID_45588, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3950] = { - .class_hid = BNXT_ULP_CLASS_HID_2a3d4, + [4530] = { + .class_hid = BNXT_ULP_CLASS_HID_45bd4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3951] = { - .class_hid = BNXT_ULP_CLASS_HID_32cd4, + [4531] = { + .class_hid = BNXT_ULP_CLASS_HID_43f34, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3952] = { - .class_hid = BNXT_ULP_CLASS_HID_3d9d4, + [4532] = { + .class_hid = BNXT_ULP_CLASS_HID_42570, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3953] = { - .class_hid = BNXT_ULP_CLASS_HID_25e74, + [4533] = { + .class_hid = BNXT_ULP_CLASS_HID_3488, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82273,16 +94317,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3954] = { - .class_hid = BNXT_ULP_CLASS_HID_2cb74, + [4534] = { + .class_hid = BNXT_ULP_CLASS_HID_3a44, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82290,17 +94334,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3955] = { - .class_hid = BNXT_ULP_CLASS_HID_31928, + [4535] = { + .class_hid = BNXT_ULP_CLASS_HID_1e24, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82308,17 +94352,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3956] = { - .class_hid = BNXT_ULP_CLASS_HID_38228, + [4536] = { + .class_hid = BNXT_ULP_CLASS_HID_07e0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82326,18 +94370,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3957] = { - .class_hid = BNXT_ULP_CLASS_HID_22d84, + [4537] = { + .class_hid = BNXT_ULP_CLASS_HID_591c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82345,17 +94389,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3958] = { - .class_hid = BNXT_ULP_CLASS_HID_2d684, + [4538] = { + .class_hid = BNXT_ULP_CLASS_HID_5ed8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82363,18 +94407,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3959] = { - .class_hid = BNXT_ULP_CLASS_HID_34384, + [4539] = { + .class_hid = BNXT_ULP_CLASS_HID_22b8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82382,18 +94426,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3960] = { - .class_hid = BNXT_ULP_CLASS_HID_39178, + [4540] = { + .class_hid = BNXT_ULP_CLASS_HID_2874, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82401,19 +94445,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3961] = { - .class_hid = BNXT_ULP_CLASS_HID_22678, + [4541] = { + .class_hid = BNXT_ULP_CLASS_HID_03d8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82421,18 +94465,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3962] = { - .class_hid = BNXT_ULP_CLASS_HID_2d378, + [4542] = { + .class_hid = BNXT_ULP_CLASS_HID_0994, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82440,19 +94483,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3963] = { - .class_hid = BNXT_ULP_CLASS_HID_35c78, + [4543] = { + .class_hid = BNXT_ULP_CLASS_HID_4880, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82460,19 +94502,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3964] = { - .class_hid = BNXT_ULP_CLASS_HID_3c978, + [4544] = { + .class_hid = BNXT_ULP_CLASS_HID_1330, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82480,20 +94521,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3965] = { - .class_hid = BNXT_ULP_CLASS_HID_25b28, + [4545] = { + .class_hid = BNXT_ULP_CLASS_HID_242c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82501,17 +94541,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3966] = { - .class_hid = BNXT_ULP_CLASS_HID_2c428, + [4546] = { + .class_hid = BNXT_ULP_CLASS_HID_2de8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82519,18 +94560,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3967] = { - .class_hid = BNXT_ULP_CLASS_HID_3121c, + [4547] = { + .class_hid = BNXT_ULP_CLASS_HID_31c8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82538,18 +94580,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3968] = { - .class_hid = BNXT_ULP_CLASS_HID_39f1c, + [4548] = { + .class_hid = BNXT_ULP_CLASS_HID_3784, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 284, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 68, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -82557,23 +94600,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3969] = { - .class_hid = BNXT_ULP_CLASS_HID_3488, + [4549] = { + .class_hid = BNXT_ULP_CLASS_HID_34b0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = @@ -82581,16 +94625,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3970] = { - .class_hid = BNXT_ULP_CLASS_HID_3a44, + [4550] = { + .class_hid = BNXT_ULP_CLASS_HID_3a7c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = @@ -82599,113 +94643,109 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3971] = { - .class_hid = BNXT_ULP_CLASS_HID_0994, + [4551] = { + .class_hid = BNXT_ULP_CLASS_HID_1e1c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3972] = { - .class_hid = BNXT_ULP_CLASS_HID_5ed8, + [4552] = { + .class_hid = BNXT_ULP_CLASS_HID_07d8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3973] = { - .class_hid = BNXT_ULP_CLASS_HID_2de8, + [4553] = { + .class_hid = BNXT_ULP_CLASS_HID_5924, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3974] = { - .class_hid = BNXT_ULP_CLASS_HID_07e0, + [4554] = { + .class_hid = BNXT_ULP_CLASS_HID_5ee0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3975] = { - .class_hid = BNXT_ULP_CLASS_HID_1330, + [4555] = { + .class_hid = BNXT_ULP_CLASS_HID_2280, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3976] = { - .class_hid = BNXT_ULP_CLASS_HID_2874, + [4556] = { + .class_hid = BNXT_ULP_CLASS_HID_284c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = @@ -82716,129 +94756,131 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3977] = { - .class_hid = BNXT_ULP_CLASS_HID_3784, + [4557] = { + .class_hid = BNXT_ULP_CLASS_HID_43144, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3978] = { - .class_hid = BNXT_ULP_CLASS_HID_03d8, + [4558] = { + .class_hid = BNXT_ULP_CLASS_HID_43700, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3979] = { - .class_hid = BNXT_ULP_CLASS_HID_591c, + [4559] = { + .class_hid = BNXT_ULP_CLASS_HID_41b20, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3980] = { - .class_hid = BNXT_ULP_CLASS_HID_242c, + [4560] = { + .class_hid = BNXT_ULP_CLASS_HID_400ec, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3981] = { - .class_hid = BNXT_ULP_CLASS_HID_1e24, + [4561] = { + .class_hid = BNXT_ULP_CLASS_HID_455e8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3982] = { - .class_hid = BNXT_ULP_CLASS_HID_4880, + [4562] = { + .class_hid = BNXT_ULP_CLASS_HID_45bb4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3983] = { - .class_hid = BNXT_ULP_CLASS_HID_22b8, + [4563] = { + .class_hid = BNXT_ULP_CLASS_HID_43f54, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = @@ -82846,26 +94888,28 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, }, - [3984] = { - .class_hid = BNXT_ULP_CLASS_HID_31c8, + [4564] = { + .class_hid = BNXT_ULP_CLASS_HID_42510, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 284, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index a6da4729b9..866fff74c4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -1,24 +1,24 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ -/* date: Fri Jan 29 09:44:41 2021 */ +/* date: Thu Mar 4 10:12:06 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 34 +#define BNXT_ULP_REGFILE_MAX_SZ 38 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 8 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 262144 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 3985 +#define BNXT_ULP_GEN_TBL_MAX_SZ 10 +#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 524288 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4565 #define BNXT_ULP_CLASS_HID_LOW_PRIME 5939 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7669 #define BNXT_ULP_CLASS_HID_SHFTR 31 #define BNXT_ULP_CLASS_HID_SHFTL 31 -#define BNXT_ULP_CLASS_HID_MASK 262143 +#define BNXT_ULP_CLASS_HID_MASK 524287 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 @@ -27,34 +27,33 @@ #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8 -#define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 #define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595 -#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 69 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 418 -#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 17 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 519 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 20 -#define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7 -#define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38 -#define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192 -#define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10 -#define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341 -#define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10 +#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 73 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 484 +#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 550 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 32 +#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5 +#define ULP_THOR_CLASS_TBL_LIST_SIZE 26 +#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 90 +#define ULP_THOR_CLASS_IDENT_LIST_SIZE 3 +#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 138 +#define ULP_THOR_CLASS_COND_LIST_SIZE 6 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512 #define ULP_WH_PLUS_ACT_COND_LIST_SIZE 26 -#define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2 -#define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4 -#define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0 -#define ULP_STINGRAY_ACT_IDENT_LIST_SIZE 0 -#define ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE 65 -#define ULP_STINGRAY_ACT_COND_LIST_SIZE 2 +#define ULP_THOR_ACT_TMPL_LIST_SIZE 7 +#define ULP_THOR_ACT_TBL_LIST_SIZE 0 +#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 0 +#define ULP_THOR_ACT_IDENT_LIST_SIZE 0 +#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 0 +#define ULP_THOR_ACT_COND_LIST_SIZE 0 enum bnxt_ulp_act_bit { BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001, @@ -95,17 +94,19 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000010, BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000020, BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000040, - BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000080, - BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000100, - BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000200, - BNXT_ULP_HDR_BIT_IO_VLAN = 0x0000000000000400, - BNXT_ULP_HDR_BIT_II_VLAN = 0x0000000000000800, - BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000001000, - BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000002000, - BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000004000, - BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000008000, - BNXT_ULP_HDR_BIT_F1 = 0x0000000000010000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000020000 + BNXT_ULP_HDR_BIT_O_ICMP = 0x0000000000000080, + BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000100, + BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000200, + BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000400, + BNXT_ULP_HDR_BIT_IO_VLAN = 0x0000000000000800, + BNXT_ULP_HDR_BIT_II_VLAN = 0x0000000000001000, + BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000002000, + BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000004000, + BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000008000, + BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000, + BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, + BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000 }; enum bnxt_ulp_accept_opc { @@ -145,44 +146,52 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_I_L3 = 14, BNXT_ULP_CF_IDX_O_L4 = 15, BNXT_ULP_CF_IDX_I_L4 = 16, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 17, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 18, - BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 19, - BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 20, - BNXT_ULP_CF_IDX_DEV_PORT_ID = 21, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 22, - BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 23, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 24, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 25, - BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 26, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 27, - BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 28, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 29, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 30, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 31, - BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 32, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 33, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 34, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 35, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 36, - BNXT_ULP_CF_IDX_ACT_DEC_TTL = 37, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 38, - BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 39, - BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 40, - BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 41, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 42, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 43, - BNXT_ULP_CF_IDX_VF_TO_VF = 44, - BNXT_ULP_CF_IDX_L3_HDR_CNT = 45, - BNXT_ULP_CF_IDX_L4_HDR_CNT = 46, - BNXT_ULP_CF_IDX_VFR_MODE = 47, - BNXT_ULP_CF_IDX_L3_TUN = 48, - BNXT_ULP_CF_IDX_L3_TUN_DECAP = 49, - BNXT_ULP_CF_IDX_FID = 50, - BNXT_ULP_CF_IDX_HDR_SIG_ID = 51, - BNXT_ULP_CF_IDX_FLOW_SIG_ID = 52, - BNXT_ULP_CF_IDX_WC_MATCH = 53, - BNXT_ULP_CF_IDX_LAST = 54 + BNXT_ULP_CF_IDX_O_L4_SRC_PORT = 17, + BNXT_ULP_CF_IDX_O_L4_DST_PORT = 18, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT = 19, + BNXT_ULP_CF_IDX_I_L4_DST_PORT = 20, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 21, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 22, + BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 23, + BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 24, + BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 25, + BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 26, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 27, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 28, + BNXT_ULP_CF_IDX_DEV_PORT_ID = 29, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 30, + BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 31, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 32, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 33, + BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 34, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 35, + BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 36, + BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 37, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 38, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 39, + BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 40, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 41, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 42, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 43, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 44, + BNXT_ULP_CF_IDX_ACT_DEC_TTL = 45, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 46, + BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 47, + BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 48, + BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 49, + BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 50, + BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 51, + BNXT_ULP_CF_IDX_VF_TO_VF = 52, + BNXT_ULP_CF_IDX_L3_HDR_CNT = 53, + BNXT_ULP_CF_IDX_L4_HDR_CNT = 54, + BNXT_ULP_CF_IDX_VFR_MODE = 55, + BNXT_ULP_CF_IDX_L3_TUN = 56, + BNXT_ULP_CF_IDX_L3_TUN_DECAP = 57, + BNXT_ULP_CF_IDX_FID = 58, + BNXT_ULP_CF_IDX_HDR_SIG_ID = 59, + BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60, + BNXT_ULP_CF_IDX_WC_MATCH = 61, + BNXT_ULP_CF_IDX_LAST = 62 }; enum bnxt_ulp_cond_list_opc { @@ -310,8 +319,7 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 3, BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4, BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5, - BNXT_ULP_GLB_RF_IDX_DEFAULT_ING_AREC_PTR = 6, - BNXT_ULP_GLB_RF_IDX_LAST = 7 + BNXT_ULP_GLB_RF_IDX_LAST = 6 }; enum bnxt_ulp_hdr_type { @@ -333,11 +341,11 @@ enum bnxt_ulp_if_tbl_opc { enum bnxt_ulp_index_tbl_opc { BNXT_ULP_INDEX_TBL_OPC_NOT_USED = 0, BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE = 1, - BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE = 2, - BNXT_ULP_INDEX_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 3, - BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE = 4, - BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE = 5, - BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE = 6, + BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE = 2, + BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE = 3, + BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE = 4, + BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE = 5, + BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE = 6, BNXT_ULP_INDEX_TBL_OPC_LAST = 7 }; @@ -424,7 +432,11 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_RID = 31, BNXT_ULP_RF_IDX_WC_KEY_ID_0 = 32, BNXT_ULP_RF_IDX_EM_KEY_ID_0 = 33, - BNXT_ULP_RF_IDX_LAST = 34 + BNXT_ULP_RF_IDX_DRV_FUNC_MAC = 34, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC = 35, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR = 36, + BNXT_ULP_RF_IDX_CC = 37, + BNXT_ULP_RF_IDX_LAST = 38 }; enum bnxt_ulp_tcam_tbl_opc { @@ -483,7 +495,8 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM = 0, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4 }; enum bnxt_ulp_act_prop_sz { @@ -801,4209 +814,4794 @@ enum ulp_wp_sym { ULP_WP_SYM_RECYCLE_DST = 0x800 }; -enum ulp_sr_sym { - ULP_SR_SYM_PKT_TYPE_IGNORE = 0, - ULP_SR_SYM_PKT_TYPE_L2 = 0, - ULP_SR_SYM_PKT_TYPE_0_IGNORE = 0, - ULP_SR_SYM_PKT_TYPE_0_L2 = 0, - ULP_SR_SYM_PKT_TYPE_1_IGNORE = 0, - ULP_SR_SYM_PKT_TYPE_1_L2 = 0, - ULP_SR_SYM_RECYCLE_CNT_IGNORE = 0, - ULP_SR_SYM_RECYCLE_CNT_ZERO = 0, - ULP_SR_SYM_RECYCLE_CNT_ONE = 1, - ULP_SR_SYM_RECYCLE_CNT_TWO = 2, - ULP_SR_SYM_RECYCLE_CNT_THREE = 3, - ULP_SR_SYM_AGG_ERROR_IGNORE = 0, - ULP_SR_SYM_AGG_ERROR_NO = 0, - ULP_SR_SYM_AGG_ERROR_YES = 1, - ULP_SR_SYM_RESERVED_IGNORE = 0, - ULP_SR_SYM_HREC_NEXT_IGNORE = 0, - ULP_SR_SYM_HREC_NEXT_NO = 0, - ULP_SR_SYM_HREC_NEXT_YES = 1, - ULP_SR_SYM_TL2_HDR_VALID_IGNORE = 0, - ULP_SR_SYM_TL2_HDR_VALID_NO = 0, - ULP_SR_SYM_TL2_HDR_VALID_YES = 1, - ULP_SR_SYM_TL2_HDR_TYPE_IGNORE = 0, - ULP_SR_SYM_TL2_HDR_TYPE_DIX = 0, - ULP_SR_SYM_TL2_UC_MC_BC_IGNORE = 0, - ULP_SR_SYM_TL2_UC_MC_BC_UC = 0, - ULP_SR_SYM_TL2_UC_MC_BC_MC = 2, - ULP_SR_SYM_TL2_UC_MC_BC_BC = 3, - ULP_SR_SYM_TL2_VTAG_PRESENT_IGNORE = 0, - ULP_SR_SYM_TL2_VTAG_PRESENT_NO = 0, - ULP_SR_SYM_TL2_VTAG_PRESENT_YES = 1, - ULP_SR_SYM_TL2_TWO_VTAGS_IGNORE = 0, - ULP_SR_SYM_TL2_TWO_VTAGS_NO = 0, - ULP_SR_SYM_TL2_TWO_VTAGS_YES = 1, - ULP_SR_SYM_TL3_HDR_VALID_IGNORE = 0, - ULP_SR_SYM_TL3_HDR_VALID_NO = 0, - ULP_SR_SYM_TL3_HDR_VALID_YES = 1, - ULP_SR_SYM_TL3_HDR_ERROR_IGNORE = 0, - ULP_SR_SYM_TL3_HDR_ERROR_NO = 0, - ULP_SR_SYM_TL3_HDR_ERROR_YES = 1, - ULP_SR_SYM_TL3_HDR_TYPE_IGNORE = 0, - ULP_SR_SYM_TL3_HDR_TYPE_IPV4 = 0, - ULP_SR_SYM_TL3_HDR_TYPE_IPV6 = 1, - ULP_SR_SYM_TL3_HDR_ISIP_IGNORE = 0, - ULP_SR_SYM_TL3_HDR_ISIP_NO = 0, - ULP_SR_SYM_TL3_HDR_ISIP_YES = 1, - ULP_SR_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, - ULP_SR_SYM_TL3_IPV6_CMP_SRC_NO = 0, - ULP_SR_SYM_TL3_IPV6_CMP_SRC_YES = 1, - ULP_SR_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, - ULP_SR_SYM_TL3_IPV6_CMP_DST_NO = 0, - ULP_SR_SYM_TL3_IPV6_CMP_DST_YES = 1, - ULP_SR_SYM_TL4_HDR_VALID_IGNORE = 0, - ULP_SR_SYM_TL4_HDR_VALID_NO = 0, - ULP_SR_SYM_TL4_HDR_VALID_YES = 1, - ULP_SR_SYM_TL4_HDR_ERROR_IGNORE = 0, - ULP_SR_SYM_TL4_HDR_ERROR_NO = 0, - ULP_SR_SYM_TL4_HDR_ERROR_YES = 1, - ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, - ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, - ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, - ULP_SR_SYM_TL4_HDR_TYPE_IGNORE = 0, - ULP_SR_SYM_TL4_HDR_TYPE_TCP = 0, - ULP_SR_SYM_TL4_HDR_TYPE_UDP = 1, - ULP_SR_SYM_TUN_HDR_VALID_IGNORE = 0, - ULP_SR_SYM_TUN_HDR_VALID_NO = 0, - ULP_SR_SYM_TUN_HDR_VALID_YES = 1, - ULP_SR_SYM_TUN_HDR_ERROR_IGNORE = 0, - ULP_SR_SYM_TUN_HDR_ERROR_NO = 0, - ULP_SR_SYM_TUN_HDR_ERROR_YES = 1, - ULP_SR_SYM_TUN_HDR_TYPE_IGNORE = 0, - ULP_SR_SYM_TUN_HDR_TYPE_VXLAN = 0, - ULP_SR_SYM_TUN_HDR_TYPE_GENEVE = 1, - ULP_SR_SYM_TUN_HDR_TYPE_NVGRE = 2, - ULP_SR_SYM_TUN_HDR_TYPE_GRE = 3, - ULP_SR_SYM_TUN_HDR_TYPE_IPV4 = 4, - ULP_SR_SYM_TUN_HDR_TYPE_IPV6 = 5, - ULP_SR_SYM_TUN_HDR_TYPE_PPPOE = 6, - ULP_SR_SYM_TUN_HDR_TYPE_MPLS = 7, - ULP_SR_SYM_TUN_HDR_TYPE_UPAR1 = 8, - ULP_SR_SYM_TUN_HDR_TYPE_UPAR2 = 9, - ULP_SR_SYM_TUN_HDR_TYPE_NONE = 15, - ULP_SR_SYM_TUN_HDR_FLAGS_IGNORE = 0, - ULP_SR_SYM_L2_HDR_VALID_IGNORE = 0, - ULP_SR_SYM_L2_HDR_VALID_NO = 0, - ULP_SR_SYM_L2_HDR_VALID_YES = 1, - ULP_SR_SYM_L2_HDR_ERROR_IGNORE = 0, - ULP_SR_SYM_L2_HDR_ERROR_NO = 0, - ULP_SR_SYM_L2_HDR_ERROR_YES = 1, - ULP_SR_SYM_L2_HDR_TYPE_IGNORE = 0, - ULP_SR_SYM_L2_HDR_TYPE_DIX = 0, - ULP_SR_SYM_L2_HDR_TYPE_LLC_SNAP = 1, - ULP_SR_SYM_L2_HDR_TYPE_LLC = 2, - ULP_SR_SYM_L2_UC_MC_BC_IGNORE = 0, - ULP_SR_SYM_L2_UC_MC_BC_UC = 0, - ULP_SR_SYM_L2_UC_MC_BC_MC = 2, - ULP_SR_SYM_L2_UC_MC_BC_BC = 3, - ULP_SR_SYM_L2_VTAG_PRESENT_IGNORE = 0, - ULP_SR_SYM_L2_VTAG_PRESENT_NO = 0, - ULP_SR_SYM_L2_VTAG_PRESENT_YES = 1, - ULP_SR_SYM_L2_TWO_VTAGS_IGNORE = 0, - ULP_SR_SYM_L2_TWO_VTAGS_NO = 0, - ULP_SR_SYM_L2_TWO_VTAGS_YES = 1, - ULP_SR_SYM_L3_HDR_VALID_IGNORE = 0, - ULP_SR_SYM_L3_HDR_VALID_NO = 0, - ULP_SR_SYM_L3_HDR_VALID_YES = 1, - ULP_SR_SYM_L3_HDR_ERROR_IGNORE = 0, - ULP_SR_SYM_L3_HDR_ERROR_NO = 0, - ULP_SR_SYM_L3_HDR_ERROR_YES = 1, - ULP_SR_SYM_L3_HDR_TYPE_IGNORE = 0, - ULP_SR_SYM_L3_HDR_TYPE_IPV4 = 0, - ULP_SR_SYM_L3_HDR_TYPE_IPV6 = 1, - ULP_SR_SYM_L3_HDR_TYPE_ARP = 2, - ULP_SR_SYM_L3_HDR_TYPE_PTP = 3, - ULP_SR_SYM_L3_HDR_TYPE_EAPOL = 4, - ULP_SR_SYM_L3_HDR_TYPE_ROCE = 5, - ULP_SR_SYM_L3_HDR_TYPE_FCOE = 6, - ULP_SR_SYM_L3_HDR_TYPE_UPAR1 = 7, - ULP_SR_SYM_L3_HDR_TYPE_UPAR2 = 8, - ULP_SR_SYM_L3_HDR_ISIP_IGNORE = 0, - ULP_SR_SYM_L3_HDR_ISIP_NO = 0, - ULP_SR_SYM_L3_HDR_ISIP_YES = 1, - ULP_SR_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, - ULP_SR_SYM_L3_IPV6_CMP_SRC_NO = 0, - ULP_SR_SYM_L3_IPV6_CMP_SRC_YES = 1, - ULP_SR_SYM_L3_IPV6_CMP_DST_IGNORE = 0, - ULP_SR_SYM_L3_IPV6_CMP_DST_NO = 0, - ULP_SR_SYM_L3_IPV6_CMP_DST_YES = 1, - ULP_SR_SYM_L4_HDR_VALID_IGNORE = 0, - ULP_SR_SYM_L4_HDR_VALID_NO = 0, - ULP_SR_SYM_L4_HDR_VALID_YES = 1, - ULP_SR_SYM_L4_HDR_ERROR_IGNORE = 0, - ULP_SR_SYM_L4_HDR_ERROR_NO = 0, - ULP_SR_SYM_L4_HDR_ERROR_YES = 1, - ULP_SR_SYM_L4_HDR_TYPE_IGNORE = 0, - ULP_SR_SYM_L4_HDR_TYPE_TCP = 0, - ULP_SR_SYM_L4_HDR_TYPE_UDP = 1, - ULP_SR_SYM_L4_HDR_TYPE_ICMP = 2, - ULP_SR_SYM_L4_HDR_TYPE_UPAR1 = 3, - ULP_SR_SYM_L4_HDR_TYPE_UPAR2 = 4, - ULP_SR_SYM_L4_HDR_TYPE_BTH_V1 = 5, - ULP_SR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, - ULP_SR_SYM_L4_HDR_IS_UDP_TCP_NO = 0, - ULP_SR_SYM_L4_HDR_IS_UDP_TCP_YES = 1, - ULP_SR_SYM_POP_VLAN_NO = 0, - ULP_SR_SYM_POP_VLAN_YES = 1, - ULP_SR_SYM_DECAP_FUNC_NONE = 0, - ULP_SR_SYM_DECAP_FUNC_THRU_TL2 = 3, - ULP_SR_SYM_DECAP_FUNC_THRU_TL3 = 8, - ULP_SR_SYM_DECAP_FUNC_THRU_TL4 = 9, - ULP_SR_SYM_DECAP_FUNC_THRU_TUN = 10, - ULP_SR_SYM_DECAP_FUNC_THRU_L2 = 11, - ULP_SR_SYM_DECAP_FUNC_THRU_L3 = 12, - ULP_SR_SYM_DECAP_FUNC_THRU_L4 = 13, - ULP_SR_SYM_ECV_VALID_NO = 0, - ULP_SR_SYM_ECV_VALID_YES = 1, - ULP_SR_SYM_ECV_CUSTOM_EN_NO = 0, - ULP_SR_SYM_ECV_CUSTOM_EN_YES = 1, - ULP_SR_SYM_ECV_L2_EN_NO = 0, - ULP_SR_SYM_ECV_L2_EN_YES = 1, - ULP_SR_SYM_ECV_VTAG_TYPE_NOP = 0, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, - ULP_SR_SYM_ECV_L3_TYPE_NONE = 0, - ULP_SR_SYM_ECV_L3_TYPE_IPV4 = 4, - ULP_SR_SYM_ECV_L3_TYPE_IPV6 = 5, - ULP_SR_SYM_ECV_L3_TYPE_MPLS_8847 = 6, - ULP_SR_SYM_ECV_L3_TYPE_MPLS_8848 = 7, - ULP_SR_SYM_ECV_L4_TYPE_NONE = 0, - ULP_SR_SYM_ECV_L4_TYPE_UDP = 4, - ULP_SR_SYM_ECV_L4_TYPE_UDP_CSUM = 5, - ULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, - ULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, - ULP_SR_SYM_ECV_TUN_TYPE_NONE = 0, - ULP_SR_SYM_ECV_TUN_TYPE_GENERIC = 1, - ULP_SR_SYM_ECV_TUN_TYPE_VXLAN = 2, - ULP_SR_SYM_ECV_TUN_TYPE_NGE = 3, - ULP_SR_SYM_ECV_TUN_TYPE_NVGRE = 4, - ULP_SR_SYM_ECV_TUN_TYPE_GRE = 5, - ULP_SR_SYM_EEM_ACT_REC_INT = 0, - ULP_SR_SYM_EEM_EXT_FLOW_CNTR = 1, - ULP_SR_SYM_UC_ACT_REC = 0, - ULP_SR_SYM_MC_ACT_REC = 1, - ULP_SR_SYM_ACT_REC_DROP_YES = 1, - ULP_SR_SYM_ACT_REC_DROP_NO = 0, - ULP_SR_SYM_ACT_REC_POP_VLAN_YES = 1, - ULP_SR_SYM_ACT_REC_POP_VLAN_NO = 0, - ULP_SR_SYM_ACT_REC_METER_EN_YES = 1, - ULP_SR_SYM_ACT_REC_METER_EN_NO = 0, - ULP_SR_SYM_LOOPBACK_PORT = 16, - ULP_SR_SYM_LOOPBACK_PARIF = 15, - ULP_SR_SYM_EXT_EM_MAX_KEY_SIZE = 448, - ULP_SR_SYM_MATCH_TYPE_EM = 0, - ULP_SR_SYM_MATCH_TYPE_WM = 1, - ULP_SR_SYM_IP_PROTO_ICMP = 1, - ULP_SR_SYM_IP_PROTO_IGMP = 2, - ULP_SR_SYM_IP_PROTO_IP_IN_IP = 4, - ULP_SR_SYM_IP_PROTO_TCP = 6, - ULP_SR_SYM_IP_PROTO_UDP = 17, - ULP_SR_SYM_VF_FUNC_PARIF = 15, - ULP_SR_SYM_NO = 0, - ULP_SR_SYM_YES = 1, - ULP_SR_SYM_RECYCLE_DST = 0x800 +enum ulp_thor_sym { + ULP_THOR_SYM_CTXT_OPCODE_BYPASS_CFA = 0, + ULP_THOR_SYM_CTXT_OPCODE_BYPASS_LKUP = 1, + ULP_THOR_SYM_CTXT_OPCODE_META_UPDATE = 2, + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW = 3, + ULP_THOR_SYM_CTXT_OPCODE_DROP = 4, + ULP_THOR_SYM_PKT_TYPE_IGNORE = 0, + ULP_THOR_SYM_PKT_TYPE_L2 = 0, + ULP_THOR_SYM_PKT_TYPE_0_IGNORE = 0, + ULP_THOR_SYM_PKT_TYPE_0_L2 = 0, + ULP_THOR_SYM_PKT_TYPE_1_IGNORE = 0, + ULP_THOR_SYM_PKT_TYPE_1_L2 = 0, + ULP_THOR_SYM_RECYCLE_CNT_IGNORE = 0, + ULP_THOR_SYM_RECYCLE_CNT_ZERO = 0, + ULP_THOR_SYM_RECYCLE_CNT_ONE = 1, + ULP_THOR_SYM_RECYCLE_CNT_TWO = 2, + ULP_THOR_SYM_RECYCLE_CNT_THREE = 3, + ULP_THOR_SYM_AGG_ERROR_IGNORE = 0, + ULP_THOR_SYM_AGG_ERROR_NO = 0, + ULP_THOR_SYM_AGG_ERROR_YES = 1, + ULP_THOR_SYM_RESERVED_IGNORE = 0, + ULP_THOR_SYM_HREC_NEXT_IGNORE = 0, + ULP_THOR_SYM_HREC_NEXT_NO = 0, + ULP_THOR_SYM_HREC_NEXT_YES = 1, + ULP_THOR_SYM_TL2_HDR_VALID_IGNORE = 0, + ULP_THOR_SYM_TL2_HDR_VALID_NO = 0, + ULP_THOR_SYM_TL2_HDR_VALID_YES = 1, + ULP_THOR_SYM_TL2_HDR_TYPE_IGNORE = 0, + ULP_THOR_SYM_TL2_HDR_TYPE_DIX = 0, + ULP_THOR_SYM_TL2_UC_MC_BC_IGNORE = 0, + ULP_THOR_SYM_TL2_UC_MC_BC_UC = 0, + ULP_THOR_SYM_TL2_UC_MC_BC_MC = 2, + ULP_THOR_SYM_TL2_UC_MC_BC_BC = 3, + ULP_THOR_SYM_TL2_VTAG_PRESENT_IGNORE = 0, + ULP_THOR_SYM_TL2_VTAG_PRESENT_NO = 0, + ULP_THOR_SYM_TL2_VTAG_PRESENT_YES = 1, + ULP_THOR_SYM_TL2_TWO_VTAGS_IGNORE = 0, + ULP_THOR_SYM_TL2_TWO_VTAGS_NO = 0, + ULP_THOR_SYM_TL2_TWO_VTAGS_YES = 1, + ULP_THOR_SYM_TL3_HDR_VALID_IGNORE = 0, + ULP_THOR_SYM_TL3_HDR_VALID_NO = 0, + ULP_THOR_SYM_TL3_HDR_VALID_YES = 1, + ULP_THOR_SYM_TL3_HDR_ERROR_IGNORE = 0, + ULP_THOR_SYM_TL3_HDR_ERROR_NO = 0, + ULP_THOR_SYM_TL3_HDR_ERROR_YES = 1, + ULP_THOR_SYM_TL3_HDR_TYPE_IGNORE = 0, + ULP_THOR_SYM_TL3_HDR_TYPE_IPV4 = 0, + ULP_THOR_SYM_TL3_HDR_TYPE_IPV6 = 1, + ULP_THOR_SYM_TL3_HDR_ISIP_IGNORE = 0, + ULP_THOR_SYM_TL3_HDR_ISIP_NO = 0, + ULP_THOR_SYM_TL3_HDR_ISIP_YES = 1, + ULP_THOR_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, + ULP_THOR_SYM_TL3_IPV6_CMP_SRC_NO = 0, + ULP_THOR_SYM_TL3_IPV6_CMP_SRC_YES = 1, + ULP_THOR_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, + ULP_THOR_SYM_TL3_IPV6_CMP_DST_NO = 0, + ULP_THOR_SYM_TL3_IPV6_CMP_DST_YES = 1, + ULP_THOR_SYM_TL4_HDR_VALID_IGNORE = 0, + ULP_THOR_SYM_TL4_HDR_VALID_NO = 0, + ULP_THOR_SYM_TL4_HDR_VALID_YES = 1, + ULP_THOR_SYM_TL4_HDR_ERROR_IGNORE = 0, + ULP_THOR_SYM_TL4_HDR_ERROR_NO = 0, + ULP_THOR_SYM_TL4_HDR_ERROR_YES = 1, + ULP_THOR_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, + ULP_THOR_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, + ULP_THOR_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, + ULP_THOR_SYM_TL4_HDR_TYPE_IGNORE = 0, + ULP_THOR_SYM_TL4_HDR_TYPE_TCP = 0, + ULP_THOR_SYM_TL4_HDR_TYPE_UDP = 1, + ULP_THOR_SYM_TUN_HDR_VALID_IGNORE = 0, + ULP_THOR_SYM_TUN_HDR_VALID_NO = 0, + ULP_THOR_SYM_TUN_HDR_VALID_YES = 1, + ULP_THOR_SYM_TUN_HDR_ERROR_IGNORE = 0, + ULP_THOR_SYM_TUN_HDR_ERROR_NO = 0, + ULP_THOR_SYM_TUN_HDR_ERROR_YES = 1, + ULP_THOR_SYM_TUN_HDR_TYPE_IGNORE = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_VXLAN = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_GENEVE = 1, + ULP_THOR_SYM_TUN_HDR_TYPE_NVGRE = 2, + ULP_THOR_SYM_TUN_HDR_TYPE_GRE = 3, + ULP_THOR_SYM_TUN_HDR_TYPE_IPV4 = 4, + ULP_THOR_SYM_TUN_HDR_TYPE_IPV6 = 5, + ULP_THOR_SYM_TUN_HDR_TYPE_PPPOE = 6, + ULP_THOR_SYM_TUN_HDR_TYPE_MPLS = 7, + ULP_THOR_SYM_TUN_HDR_TYPE_UPAR1 = 8, + ULP_THOR_SYM_TUN_HDR_TYPE_UPAR2 = 9, + ULP_THOR_SYM_TUN_HDR_TYPE_NONE = 15, + ULP_THOR_SYM_TUN_HDR_FLAGS_IGNORE = 0, + ULP_THOR_SYM_L2_HDR_VALID_IGNORE = 0, + ULP_THOR_SYM_L2_HDR_VALID_NO = 0, + ULP_THOR_SYM_L2_HDR_VALID_YES = 1, + ULP_THOR_SYM_L2_HDR_ERROR_IGNORE = 0, + ULP_THOR_SYM_L2_HDR_ERROR_NO = 0, + ULP_THOR_SYM_L2_HDR_ERROR_YES = 1, + ULP_THOR_SYM_L2_HDR_TYPE_IGNORE = 0, + ULP_THOR_SYM_L2_HDR_TYPE_DIX = 0, + ULP_THOR_SYM_L2_HDR_TYPE_LLC_SNAP = 1, + ULP_THOR_SYM_L2_HDR_TYPE_LLC = 2, + ULP_THOR_SYM_L2_UC_MC_BC_IGNORE = 0, + ULP_THOR_SYM_L2_UC_MC_BC_UC = 0, + ULP_THOR_SYM_L2_UC_MC_BC_MC = 2, + ULP_THOR_SYM_L2_UC_MC_BC_BC = 3, + ULP_THOR_SYM_L2_VTAG_PRESENT_IGNORE = 0, + ULP_THOR_SYM_L2_VTAG_PRESENT_NO = 0, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES = 1, + ULP_THOR_SYM_L2_TWO_VTAGS_IGNORE = 0, + ULP_THOR_SYM_L2_TWO_VTAGS_NO = 0, + ULP_THOR_SYM_L2_TWO_VTAGS_YES = 1, + ULP_THOR_SYM_L3_HDR_VALID_IGNORE = 0, + ULP_THOR_SYM_L3_HDR_VALID_NO = 0, + ULP_THOR_SYM_L3_HDR_VALID_YES = 1, + ULP_THOR_SYM_L3_HDR_ERROR_IGNORE = 0, + ULP_THOR_SYM_L3_HDR_ERROR_NO = 0, + ULP_THOR_SYM_L3_HDR_ERROR_YES = 1, + ULP_THOR_SYM_L3_HDR_TYPE_IGNORE = 0, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4 = 0, + ULP_THOR_SYM_L3_HDR_TYPE_IPV6 = 1, + ULP_THOR_SYM_L3_HDR_TYPE_ARP = 2, + ULP_THOR_SYM_L3_HDR_TYPE_PTP = 3, + ULP_THOR_SYM_L3_HDR_TYPE_EAPOL = 4, + ULP_THOR_SYM_L3_HDR_TYPE_ROCE = 5, + ULP_THOR_SYM_L3_HDR_TYPE_FCOE = 6, + ULP_THOR_SYM_L3_HDR_TYPE_UPAR1 = 7, + ULP_THOR_SYM_L3_HDR_TYPE_UPAR2 = 8, + ULP_THOR_SYM_L3_HDR_ISIP_IGNORE = 0, + ULP_THOR_SYM_L3_HDR_ISIP_NO = 0, + ULP_THOR_SYM_L3_HDR_ISIP_YES = 1, + ULP_THOR_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, + ULP_THOR_SYM_L3_IPV6_CMP_SRC_NO = 0, + ULP_THOR_SYM_L3_IPV6_CMP_SRC_YES = 1, + ULP_THOR_SYM_L3_IPV6_CMP_DST_IGNORE = 0, + ULP_THOR_SYM_L3_IPV6_CMP_DST_NO = 0, + ULP_THOR_SYM_L3_IPV6_CMP_DST_YES = 1, + ULP_THOR_SYM_L4_HDR_VALID_IGNORE = 0, + ULP_THOR_SYM_L4_HDR_VALID_NO = 0, + ULP_THOR_SYM_L4_HDR_VALID_YES = 1, + ULP_THOR_SYM_L4_HDR_ERROR_IGNORE = 0, + ULP_THOR_SYM_L4_HDR_ERROR_NO = 0, + ULP_THOR_SYM_L4_HDR_ERROR_YES = 1, + ULP_THOR_SYM_L4_HDR_TYPE_IGNORE = 0, + ULP_THOR_SYM_L4_HDR_TYPE_TCP = 0, + ULP_THOR_SYM_L4_HDR_TYPE_UDP = 1, + ULP_THOR_SYM_L4_HDR_TYPE_ICMP = 2, + ULP_THOR_SYM_L4_HDR_TYPE_UPAR1 = 3, + ULP_THOR_SYM_L4_HDR_TYPE_UPAR2 = 4, + ULP_THOR_SYM_L4_HDR_TYPE_BTH_V1 = 5, + ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, + ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_NO = 0, + ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_YES = 1, + ULP_THOR_SYM_POP_VLAN_NO = 0, + ULP_THOR_SYM_POP_VLAN_YES = 1, + ULP_THOR_SYM_DECAP_FUNC_NONE = 0, + ULP_THOR_SYM_DECAP_FUNC_THRU_TL2 = 3, + ULP_THOR_SYM_DECAP_FUNC_THRU_TL3 = 8, + ULP_THOR_SYM_DECAP_FUNC_THRU_TL4 = 9, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN = 10, + ULP_THOR_SYM_DECAP_FUNC_THRU_L2 = 11, + ULP_THOR_SYM_DECAP_FUNC_THRU_L3 = 12, + ULP_THOR_SYM_DECAP_FUNC_THRU_L4 = 13, + ULP_THOR_SYM_ECV_VALID_NO = 0, + ULP_THOR_SYM_ECV_VALID_YES = 1, + ULP_THOR_SYM_ECV_CUSTOM_EN_NO = 0, + ULP_THOR_SYM_ECV_CUSTOM_EN_YES = 1, + ULP_THOR_SYM_ECV_L2_EN_NO = 0, + ULP_THOR_SYM_ECV_L2_EN_YES = 1, + ULP_THOR_SYM_ECV_VTAG_TYPE_NOP = 0, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, + ULP_THOR_SYM_ECV_L3_TYPE_NONE = 0, + ULP_THOR_SYM_ECV_L3_TYPE_IPV4 = 4, + ULP_THOR_SYM_ECV_L3_TYPE_IPV6 = 5, + ULP_THOR_SYM_ECV_L3_TYPE_MPLS_8847 = 6, + ULP_THOR_SYM_ECV_L3_TYPE_MPLS_8848 = 7, + ULP_THOR_SYM_ECV_L4_TYPE_NONE = 0, + ULP_THOR_SYM_ECV_L4_TYPE_UDP = 4, + ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM = 5, + ULP_THOR_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, + ULP_THOR_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, + ULP_THOR_SYM_ECV_TUN_TYPE_NONE = 0, + ULP_THOR_SYM_ECV_TUN_TYPE_GENERIC = 1, + ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN = 2, + ULP_THOR_SYM_ECV_TUN_TYPE_NGE = 3, + ULP_THOR_SYM_ECV_TUN_TYPE_NVGRE = 4, + ULP_THOR_SYM_ECV_TUN_TYPE_GRE = 5, + ULP_THOR_SYM_EEM_ACT_REC_INT = 0, + ULP_THOR_SYM_EEM_EXT_FLOW_CNTR = 0, + ULP_THOR_SYM_UC_ACT_REC = 0, + ULP_THOR_SYM_MC_ACT_REC = 1, + ULP_THOR_SYM_ACT_REC_DROP_YES = 1, + ULP_THOR_SYM_ACT_REC_DROP_NO = 0, + ULP_THOR_SYM_ACT_REC_POP_VLAN_YES = 1, + ULP_THOR_SYM_ACT_REC_POP_VLAN_NO = 0, + ULP_THOR_SYM_ACT_REC_METER_EN_YES = 1, + ULP_THOR_SYM_ACT_REC_METER_EN_NO = 0, + ULP_THOR_SYM_LOOPBACK_PORT = 3, + ULP_THOR_SYM_LOOPBACK_PARIF = 15, + ULP_THOR_SYM_EXT_EM_MAX_KEY_SIZE = 0, + ULP_THOR_SYM_MATCH_TYPE_EM = 0, + ULP_THOR_SYM_MATCH_TYPE_WM = 1, + ULP_THOR_SYM_IP_PROTO_ICMP = 1, + ULP_THOR_SYM_IP_PROTO_IGMP = 2, + ULP_THOR_SYM_IP_PROTO_IP_IN_IP = 4, + ULP_THOR_SYM_IP_PROTO_TCP = 6, + ULP_THOR_SYM_IP_PROTO_UDP = 17, + ULP_THOR_SYM_VF_FUNC_PARIF = 15, + ULP_THOR_SYM_NO = 0, + ULP_THOR_SYM_YES = 1, + ULP_THOR_SYM_RECYCLE_DST = 0x800 }; enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_26d1 = 0x26d1, - BNXT_ULP_CLASS_HID_0071 = 0x0071, - BNXT_ULP_CLASS_HID_53a5 = 0x53a5, - BNXT_ULP_CLASS_HID_1d49 = 0x1d49, - BNXT_ULP_CLASS_HID_2095 = 0x2095, - BNXT_ULP_CLASS_HID_5701 = 0x5701, - BNXT_ULP_CLASS_HID_4d79 = 0x4d79, - BNXT_ULP_CLASS_HID_170d = 0x170d, - BNXT_ULP_CLASS_HID_1a69 = 0x1a69, - BNXT_ULP_CLASS_HID_50c5 = 0x50c5, - BNXT_ULP_CLASS_HID_473d = 0x473d, - BNXT_ULP_CLASS_HID_10c1 = 0x10c1, - BNXT_ULP_CLASS_HID_142d = 0x142d, - BNXT_ULP_CLASS_HID_4a99 = 0x4a99, - BNXT_ULP_CLASS_HID_40f1 = 0x40f1, - BNXT_ULP_CLASS_HID_0a85 = 0x0a85, - BNXT_ULP_CLASS_HID_0179 = 0x0179, - BNXT_ULP_CLASS_HID_37d5 = 0x37d5, - BNXT_ULP_CLASS_HID_2e4d = 0x2e4d, - BNXT_ULP_CLASS_HID_54ad = 0x54ad, - BNXT_ULP_CLASS_HID_5809 = 0x5809, - BNXT_ULP_CLASS_HID_31a9 = 0x31a9, - BNXT_ULP_CLASS_HID_2801 = 0x2801, - BNXT_ULP_CLASS_HID_4e61 = 0x4e61, - BNXT_ULP_CLASS_HID_2561 = 0x2561, - BNXT_ULP_CLASS_HID_2bad = 0x2bad, - BNXT_ULP_CLASS_HID_054d = 0x054d, - BNXT_ULP_CLASS_HID_5bdd = 0x5bdd, - BNXT_ULP_CLASS_HID_26f1 = 0x26f1, - BNXT_ULP_CLASS_HID_13cf1 = 0x13cf1, - BNXT_ULP_CLASS_HID_252f1 = 0x252f1, - BNXT_ULP_CLASS_HID_30c25 = 0x30c25, - BNXT_ULP_CLASS_HID_0051 = 0x0051, - BNXT_ULP_CLASS_HID_11651 = 0x11651, - BNXT_ULP_CLASS_HID_22c51 = 0x22c51, - BNXT_ULP_CLASS_HID_34251 = 0x34251, - BNXT_ULP_CLASS_HID_5385 = 0x5385, - BNXT_ULP_CLASS_HID_10cc9 = 0x10cc9, - BNXT_ULP_CLASS_HID_222c9 = 0x222c9, - BNXT_ULP_CLASS_HID_338c9 = 0x338c9, - BNXT_ULP_CLASS_HID_1d69 = 0x1d69, - BNXT_ULP_CLASS_HID_13369 = 0x13369, - BNXT_ULP_CLASS_HID_24969 = 0x24969, - BNXT_ULP_CLASS_HID_3025d = 0x3025d, - BNXT_ULP_CLASS_HID_20b5 = 0x20b5, - BNXT_ULP_CLASS_HID_136b5 = 0x136b5, - BNXT_ULP_CLASS_HID_24cb5 = 0x24cb5, - BNXT_ULP_CLASS_HID_305f9 = 0x305f9, - BNXT_ULP_CLASS_HID_5721 = 0x5721, - BNXT_ULP_CLASS_HID_11015 = 0x11015, - BNXT_ULP_CLASS_HID_22615 = 0x22615, - BNXT_ULP_CLASS_HID_33c15 = 0x33c15, - BNXT_ULP_CLASS_HID_4d59 = 0x4d59, - BNXT_ULP_CLASS_HID_1068d = 0x1068d, - BNXT_ULP_CLASS_HID_21c8d = 0x21c8d, - BNXT_ULP_CLASS_HID_3328d = 0x3328d, - BNXT_ULP_CLASS_HID_172d = 0x172d, - BNXT_ULP_CLASS_HID_12d2d = 0x12d2d, - BNXT_ULP_CLASS_HID_2432d = 0x2432d, - BNXT_ULP_CLASS_HID_3592d = 0x3592d, - BNXT_ULP_CLASS_HID_1a49 = 0x1a49, - BNXT_ULP_CLASS_HID_13049 = 0x13049, - BNXT_ULP_CLASS_HID_24649 = 0x24649, - BNXT_ULP_CLASS_HID_35c49 = 0x35c49, - BNXT_ULP_CLASS_HID_50e5 = 0x50e5, - BNXT_ULP_CLASS_HID_10a29 = 0x10a29, - BNXT_ULP_CLASS_HID_22029 = 0x22029, - BNXT_ULP_CLASS_HID_33629 = 0x33629, - BNXT_ULP_CLASS_HID_471d = 0x471d, - BNXT_ULP_CLASS_HID_10041 = 0x10041, - BNXT_ULP_CLASS_HID_21641 = 0x21641, - BNXT_ULP_CLASS_HID_32c41 = 0x32c41, - BNXT_ULP_CLASS_HID_10e1 = 0x10e1, - BNXT_ULP_CLASS_HID_126e1 = 0x126e1, - BNXT_ULP_CLASS_HID_23ce1 = 0x23ce1, - BNXT_ULP_CLASS_HID_352e1 = 0x352e1, - BNXT_ULP_CLASS_HID_140d = 0x140d, - BNXT_ULP_CLASS_HID_12a0d = 0x12a0d, - BNXT_ULP_CLASS_HID_2400d = 0x2400d, - BNXT_ULP_CLASS_HID_3560d = 0x3560d, - BNXT_ULP_CLASS_HID_4ab9 = 0x4ab9, - BNXT_ULP_CLASS_HID_103ed = 0x103ed, - BNXT_ULP_CLASS_HID_219ed = 0x219ed, - BNXT_ULP_CLASS_HID_32fed = 0x32fed, - BNXT_ULP_CLASS_HID_40d1 = 0x40d1, - BNXT_ULP_CLASS_HID_156d1 = 0x156d1, - BNXT_ULP_CLASS_HID_21005 = 0x21005, - BNXT_ULP_CLASS_HID_32605 = 0x32605, - BNXT_ULP_CLASS_HID_0aa5 = 0x0aa5, - BNXT_ULP_CLASS_HID_120a5 = 0x120a5, - BNXT_ULP_CLASS_HID_236a5 = 0x236a5, - BNXT_ULP_CLASS_HID_34ca5 = 0x34ca5, - BNXT_ULP_CLASS_HID_0159 = 0x0159, - BNXT_ULP_CLASS_HID_11759 = 0x11759, - BNXT_ULP_CLASS_HID_22d59 = 0x22d59, - BNXT_ULP_CLASS_HID_34359 = 0x34359, - BNXT_ULP_CLASS_HID_37f5 = 0x37f5, - BNXT_ULP_CLASS_HID_14df5 = 0x14df5, - BNXT_ULP_CLASS_HID_20739 = 0x20739, - BNXT_ULP_CLASS_HID_31d39 = 0x31d39, - BNXT_ULP_CLASS_HID_2e6d = 0x2e6d, - BNXT_ULP_CLASS_HID_1446d = 0x1446d, - BNXT_ULP_CLASS_HID_25a6d = 0x25a6d, - BNXT_ULP_CLASS_HID_31351 = 0x31351, - BNXT_ULP_CLASS_HID_548d = 0x548d, - BNXT_ULP_CLASS_HID_10df1 = 0x10df1, - BNXT_ULP_CLASS_HID_223f1 = 0x223f1, - BNXT_ULP_CLASS_HID_339f1 = 0x339f1, - BNXT_ULP_CLASS_HID_5829 = 0x5829, - BNXT_ULP_CLASS_HID_1111d = 0x1111d, - BNXT_ULP_CLASS_HID_2271d = 0x2271d, - BNXT_ULP_CLASS_HID_33d1d = 0x33d1d, - BNXT_ULP_CLASS_HID_3189 = 0x3189, - BNXT_ULP_CLASS_HID_14789 = 0x14789, - BNXT_ULP_CLASS_HID_200fd = 0x200fd, - BNXT_ULP_CLASS_HID_316fd = 0x316fd, - BNXT_ULP_CLASS_HID_2821 = 0x2821, - BNXT_ULP_CLASS_HID_13e21 = 0x13e21, - BNXT_ULP_CLASS_HID_25421 = 0x25421, - BNXT_ULP_CLASS_HID_30d15 = 0x30d15, - BNXT_ULP_CLASS_HID_4e41 = 0x4e41, - BNXT_ULP_CLASS_HID_107b5 = 0x107b5, - BNXT_ULP_CLASS_HID_21db5 = 0x21db5, - BNXT_ULP_CLASS_HID_333b5 = 0x333b5, - BNXT_ULP_CLASS_HID_2541 = 0x2541, - BNXT_ULP_CLASS_HID_2b8d = 0x2b8d, - BNXT_ULP_CLASS_HID_056d = 0x056d, - BNXT_ULP_CLASS_HID_5bfd = 0x5bfd, - BNXT_ULP_CLASS_HID_2691 = 0x2691, - BNXT_ULP_CLASS_HID_13c91 = 0x13c91, - BNXT_ULP_CLASS_HID_25291 = 0x25291, - BNXT_ULP_CLASS_HID_30c45 = 0x30c45, - BNXT_ULP_CLASS_HID_0031 = 0x0031, - BNXT_ULP_CLASS_HID_11631 = 0x11631, - BNXT_ULP_CLASS_HID_22c31 = 0x22c31, - BNXT_ULP_CLASS_HID_34231 = 0x34231, - BNXT_ULP_CLASS_HID_53e5 = 0x53e5, - BNXT_ULP_CLASS_HID_10ca9 = 0x10ca9, - BNXT_ULP_CLASS_HID_222a9 = 0x222a9, - BNXT_ULP_CLASS_HID_338a9 = 0x338a9, - BNXT_ULP_CLASS_HID_1d09 = 0x1d09, - BNXT_ULP_CLASS_HID_13309 = 0x13309, - BNXT_ULP_CLASS_HID_24909 = 0x24909, - BNXT_ULP_CLASS_HID_3023d = 0x3023d, - BNXT_ULP_CLASS_HID_20d5 = 0x20d5, - BNXT_ULP_CLASS_HID_136d5 = 0x136d5, - BNXT_ULP_CLASS_HID_24cd5 = 0x24cd5, - BNXT_ULP_CLASS_HID_30599 = 0x30599, - BNXT_ULP_CLASS_HID_5741 = 0x5741, - BNXT_ULP_CLASS_HID_11075 = 0x11075, - BNXT_ULP_CLASS_HID_22675 = 0x22675, - BNXT_ULP_CLASS_HID_33c75 = 0x33c75, - BNXT_ULP_CLASS_HID_4d39 = 0x4d39, - BNXT_ULP_CLASS_HID_106ed = 0x106ed, - BNXT_ULP_CLASS_HID_21ced = 0x21ced, - BNXT_ULP_CLASS_HID_332ed = 0x332ed, - BNXT_ULP_CLASS_HID_174d = 0x174d, - BNXT_ULP_CLASS_HID_12d4d = 0x12d4d, - BNXT_ULP_CLASS_HID_2434d = 0x2434d, - BNXT_ULP_CLASS_HID_3594d = 0x3594d, - BNXT_ULP_CLASS_HID_1a29 = 0x1a29, - BNXT_ULP_CLASS_HID_13029 = 0x13029, - BNXT_ULP_CLASS_HID_24629 = 0x24629, - BNXT_ULP_CLASS_HID_35c29 = 0x35c29, - BNXT_ULP_CLASS_HID_5085 = 0x5085, - BNXT_ULP_CLASS_HID_10a49 = 0x10a49, - BNXT_ULP_CLASS_HID_22049 = 0x22049, - BNXT_ULP_CLASS_HID_33649 = 0x33649, - BNXT_ULP_CLASS_HID_477d = 0x477d, - BNXT_ULP_CLASS_HID_10021 = 0x10021, - BNXT_ULP_CLASS_HID_21621 = 0x21621, - BNXT_ULP_CLASS_HID_32c21 = 0x32c21, - BNXT_ULP_CLASS_HID_1081 = 0x1081, - BNXT_ULP_CLASS_HID_12681 = 0x12681, - BNXT_ULP_CLASS_HID_23c81 = 0x23c81, - BNXT_ULP_CLASS_HID_35281 = 0x35281, - BNXT_ULP_CLASS_HID_146d = 0x146d, - BNXT_ULP_CLASS_HID_12a6d = 0x12a6d, - BNXT_ULP_CLASS_HID_2406d = 0x2406d, - BNXT_ULP_CLASS_HID_3566d = 0x3566d, - BNXT_ULP_CLASS_HID_4ad9 = 0x4ad9, - BNXT_ULP_CLASS_HID_1038d = 0x1038d, - BNXT_ULP_CLASS_HID_2198d = 0x2198d, - BNXT_ULP_CLASS_HID_32f8d = 0x32f8d, - BNXT_ULP_CLASS_HID_40b1 = 0x40b1, - BNXT_ULP_CLASS_HID_156b1 = 0x156b1, - BNXT_ULP_CLASS_HID_21065 = 0x21065, - BNXT_ULP_CLASS_HID_32665 = 0x32665, - BNXT_ULP_CLASS_HID_0ac5 = 0x0ac5, - BNXT_ULP_CLASS_HID_120c5 = 0x120c5, - BNXT_ULP_CLASS_HID_236c5 = 0x236c5, - BNXT_ULP_CLASS_HID_34cc5 = 0x34cc5, - BNXT_ULP_CLASS_HID_0139 = 0x0139, - BNXT_ULP_CLASS_HID_11739 = 0x11739, - BNXT_ULP_CLASS_HID_22d39 = 0x22d39, - BNXT_ULP_CLASS_HID_34339 = 0x34339, - BNXT_ULP_CLASS_HID_3795 = 0x3795, - BNXT_ULP_CLASS_HID_14d95 = 0x14d95, - BNXT_ULP_CLASS_HID_20759 = 0x20759, - BNXT_ULP_CLASS_HID_31d59 = 0x31d59, - BNXT_ULP_CLASS_HID_2e0d = 0x2e0d, - BNXT_ULP_CLASS_HID_1440d = 0x1440d, - BNXT_ULP_CLASS_HID_25a0d = 0x25a0d, - BNXT_ULP_CLASS_HID_31331 = 0x31331, - BNXT_ULP_CLASS_HID_54ed = 0x54ed, - BNXT_ULP_CLASS_HID_10d91 = 0x10d91, - BNXT_ULP_CLASS_HID_22391 = 0x22391, - BNXT_ULP_CLASS_HID_33991 = 0x33991, - BNXT_ULP_CLASS_HID_5849 = 0x5849, - BNXT_ULP_CLASS_HID_1117d = 0x1117d, - BNXT_ULP_CLASS_HID_2277d = 0x2277d, - BNXT_ULP_CLASS_HID_33d7d = 0x33d7d, - BNXT_ULP_CLASS_HID_31e9 = 0x31e9, - BNXT_ULP_CLASS_HID_147e9 = 0x147e9, - BNXT_ULP_CLASS_HID_2009d = 0x2009d, - BNXT_ULP_CLASS_HID_3169d = 0x3169d, - BNXT_ULP_CLASS_HID_2841 = 0x2841, - BNXT_ULP_CLASS_HID_13e41 = 0x13e41, - BNXT_ULP_CLASS_HID_25441 = 0x25441, - BNXT_ULP_CLASS_HID_30d75 = 0x30d75, - BNXT_ULP_CLASS_HID_4e21 = 0x4e21, - BNXT_ULP_CLASS_HID_107d5 = 0x107d5, - BNXT_ULP_CLASS_HID_21dd5 = 0x21dd5, - BNXT_ULP_CLASS_HID_333d5 = 0x333d5, - BNXT_ULP_CLASS_HID_2521 = 0x2521, - BNXT_ULP_CLASS_HID_2bed = 0x2bed, - BNXT_ULP_CLASS_HID_050d = 0x050d, - BNXT_ULP_CLASS_HID_5b9d = 0x5b9d, - BNXT_ULP_CLASS_HID_1865 = 0x1865, - BNXT_ULP_CLASS_HID_389d = 0x389d, - BNXT_ULP_CLASS_HID_123d = 0x123d, - BNXT_ULP_CLASS_HID_4ef1 = 0x4ef1, + BNXT_ULP_CLASS_HID_05d1 = 0x05d1, BNXT_ULP_CLASS_HID_1229 = 0x1229, - BNXT_ULP_CLASS_HID_3241 = 0x3241, - BNXT_ULP_CLASS_HID_0be1 = 0x0be1, - BNXT_ULP_CLASS_HID_48b5 = 0x48b5, BNXT_ULP_CLASS_HID_0bed = 0x0bed, + BNXT_ULP_CLASS_HID_1865 = 0x1865, + BNXT_ULP_CLASS_HID_25c9 = 0x25c9, + BNXT_ULP_CLASS_HID_3241 = 0x3241, BNXT_ULP_CLASS_HID_2c05 = 0x2c05, - BNXT_ULP_CLASS_HID_05a5 = 0x05a5, + BNXT_ULP_CLASS_HID_389d = 0x389d, + BNXT_ULP_CLASS_HID_3c3d = 0x3c3d, + BNXT_ULP_CLASS_HID_48b5 = 0x48b5, BNXT_ULP_CLASS_HID_4279 = 0x4279, - BNXT_ULP_CLASS_HID_05d1 = 0x05d1, - BNXT_ULP_CLASS_HID_25c9 = 0x25c9, + BNXT_ULP_CLASS_HID_4ef1 = 0x4ef1, BNXT_ULP_CLASS_HID_5c55 = 0x5c55, - BNXT_ULP_CLASS_HID_3c3d = 0x3c3d, - BNXT_ULP_CLASS_HID_4fc9 = 0x4fc9, - BNXT_ULP_CLASS_HID_1335 = 0x1335, - BNXT_ULP_CLASS_HID_4981 = 0x4981, - BNXT_ULP_CLASS_HID_2969 = 0x2969, - BNXT_ULP_CLASS_HID_498d = 0x498d, - BNXT_ULP_CLASS_HID_0cf9 = 0x0cf9, - BNXT_ULP_CLASS_HID_4345 = 0x4345, - BNXT_ULP_CLASS_HID_232d = 0x232d, - BNXT_ULP_CLASS_HID_2579 = 0x2579, - BNXT_ULP_CLASS_HID_2bb5 = 0x2bb5, - BNXT_ULP_CLASS_HID_4bad = 0x4bad, - BNXT_ULP_CLASS_HID_4591 = 0x4591, + BNXT_ULP_CLASS_HID_0be1 = 0x0be1, + BNXT_ULP_CLASS_HID_05a5 = 0x05a5, + BNXT_ULP_CLASS_HID_123d = 0x123d, + BNXT_ULP_CLASS_HID_4142d = 0x4142d, + BNXT_ULP_CLASS_HID_42095 = 0x42095, + BNXT_ULP_CLASS_HID_41a69 = 0x41a69, + BNXT_ULP_CLASS_HID_426d1 = 0x426d1, + BNXT_ULP_CLASS_HID_44a99 = 0x44a99, + BNXT_ULP_CLASS_HID_45701 = 0x45701, + BNXT_ULP_CLASS_HID_450c5 = 0x450c5, + BNXT_ULP_CLASS_HID_40071 = 0x40071, + BNXT_ULP_CLASS_HID_40a85 = 0x40a85, + BNXT_ULP_CLASS_HID_4170d = 0x4170d, + BNXT_ULP_CLASS_HID_410c1 = 0x410c1, + BNXT_ULP_CLASS_HID_41d49 = 0x41d49, + BNXT_ULP_CLASS_HID_440f1 = 0x440f1, + BNXT_ULP_CLASS_HID_44d79 = 0x44d79, + BNXT_ULP_CLASS_HID_4473d = 0x4473d, + BNXT_ULP_CLASS_HID_453a5 = 0x453a5, + BNXT_ULP_CLASS_HID_244e3 = 0x244e3, + BNXT_ULP_CLASS_HID_2517b = 0x2517b, + BNXT_ULP_CLASS_HID_24b3f = 0x24b3f, + BNXT_ULP_CLASS_HID_257b7 = 0x257b7, + BNXT_ULP_CLASS_HID_22f5f = 0x22f5f, + BNXT_ULP_CLASS_HID_23bd7 = 0x23bd7, + BNXT_ULP_CLASS_HID_2359b = 0x2359b, + BNXT_ULP_CLASS_HID_24213 = 0x24213, + BNXT_ULP_CLASS_HID_20bab = 0x20bab, + BNXT_ULP_CLASS_HID_21823 = 0x21823, + BNXT_ULP_CLASS_HID_211e7 = 0x211e7, + BNXT_ULP_CLASS_HID_21e7f = 0x21e7f, + BNXT_ULP_CLASS_HID_252f3 = 0x252f3, + BNXT_ULP_CLASS_HID_2029f = 0x2029f, + BNXT_ULP_CLASS_HID_2590f = 0x2590f, + BNXT_ULP_CLASS_HID_208db = 0x208db, + BNXT_ULP_CLASS_HID_231d3 = 0x231d3, + BNXT_ULP_CLASS_HID_23e2b = 0x23e2b, + BNXT_ULP_CLASS_HID_237ef = 0x237ef, + BNXT_ULP_CLASS_HID_24467 = 0x24467, + BNXT_ULP_CLASS_HID_21c0f = 0x21c0f, + BNXT_ULP_CLASS_HID_22887 = 0x22887, + BNXT_ULP_CLASS_HID_2224b = 0x2224b, + BNXT_ULP_CLASS_HID_22ec3 = 0x22ec3, + BNXT_ULP_CLASS_HID_25547 = 0x25547, + BNXT_ULP_CLASS_HID_20513 = 0x20513, + BNXT_ULP_CLASS_HID_25b83 = 0x25b83, + BNXT_ULP_CLASS_HID_20b2f = 0x20b2f, + BNXT_ULP_CLASS_HID_23fa3 = 0x23fa3, + BNXT_ULP_CLASS_HID_24c3b = 0x24c3b, + BNXT_ULP_CLASS_HID_245ff = 0x245ff, + BNXT_ULP_CLASS_HID_25277 = 0x25277, + BNXT_ULP_CLASS_HID_64037 = 0x64037, + BNXT_ULP_CLASS_HID_64c8f = 0x64c8f, + BNXT_ULP_CLASS_HID_64673 = 0x64673, + BNXT_ULP_CLASS_HID_652cb = 0x652cb, + BNXT_ULP_CLASS_HID_62a93 = 0x62a93, + BNXT_ULP_CLASS_HID_636eb = 0x636eb, + BNXT_ULP_CLASS_HID_630af = 0x630af, + BNXT_ULP_CLASS_HID_63d27 = 0x63d27, + BNXT_ULP_CLASS_HID_606ff = 0x606ff, + BNXT_ULP_CLASS_HID_61377 = 0x61377, + BNXT_ULP_CLASS_HID_60d3b = 0x60d3b, + BNXT_ULP_CLASS_HID_619b3 = 0x619b3, + BNXT_ULP_CLASS_HID_64e07 = 0x64e07, + BNXT_ULP_CLASS_HID_65a9f = 0x65a9f, + BNXT_ULP_CLASS_HID_65443 = 0x65443, + BNXT_ULP_CLASS_HID_603ef = 0x603ef, + BNXT_ULP_CLASS_HID_62ce7 = 0x62ce7, + BNXT_ULP_CLASS_HID_6397f = 0x6397f, + BNXT_ULP_CLASS_HID_63323 = 0x63323, + BNXT_ULP_CLASS_HID_63fbb = 0x63fbb, + BNXT_ULP_CLASS_HID_61743 = 0x61743, + BNXT_ULP_CLASS_HID_623db = 0x623db, + BNXT_ULP_CLASS_HID_61d9f = 0x61d9f, + BNXT_ULP_CLASS_HID_62a17 = 0x62a17, + BNXT_ULP_CLASS_HID_6509b = 0x6509b, + BNXT_ULP_CLASS_HID_60027 = 0x60027, + BNXT_ULP_CLASS_HID_656d7 = 0x656d7, + BNXT_ULP_CLASS_HID_60663 = 0x60663, + BNXT_ULP_CLASS_HID_63af7 = 0x63af7, + BNXT_ULP_CLASS_HID_6474f = 0x6474f, + BNXT_ULP_CLASS_HID_64133 = 0x64133, + BNXT_ULP_CLASS_HID_64d8b = 0x64d8b, + BNXT_ULP_CLASS_HID_a3fb = 0xa3fb, + BNXT_ULP_CLASS_HID_b063 = 0xb063, + BNXT_ULP_CLASS_HID_aa27 = 0xaa27, + BNXT_ULP_CLASS_HID_b6af = 0xb6af, + BNXT_ULP_CLASS_HID_8e47 = 0x8e47, + BNXT_ULP_CLASS_HID_9acf = 0x9acf, + BNXT_ULP_CLASS_HID_9483 = 0x9483, + BNXT_ULP_CLASS_HID_a10b = 0xa10b, + BNXT_ULP_CLASS_HID_c78f = 0xc78f, + BNXT_ULP_CLASS_HID_d3f7 = 0xd3f7, + BNXT_ULP_CLASS_HID_cdcb = 0xcdcb, + BNXT_ULP_CLASS_HID_da33 = 0xda33, + BNXT_ULP_CLASS_HID_b1eb = 0xb1eb, + BNXT_ULP_CLASS_HID_be53 = 0xbe53, + BNXT_ULP_CLASS_HID_b817 = 0xb817, + BNXT_ULP_CLASS_HID_c49f = 0xc49f, + BNXT_ULP_CLASS_HID_49f2f = 0x49f2f, + BNXT_ULP_CLASS_HID_4ab97 = 0x4ab97, + BNXT_ULP_CLASS_HID_4a56b = 0x4a56b, + BNXT_ULP_CLASS_HID_4b1d3 = 0x4b1d3, + BNXT_ULP_CLASS_HID_4898b = 0x4898b, + BNXT_ULP_CLASS_HID_495f3 = 0x495f3, + BNXT_ULP_CLASS_HID_48fb7 = 0x48fb7, + BNXT_ULP_CLASS_HID_49c3f = 0x49c3f, + BNXT_ULP_CLASS_HID_4c2b3 = 0x4c2b3, + BNXT_ULP_CLASS_HID_4cf3b = 0x4cf3b, + BNXT_ULP_CLASS_HID_4c8ff = 0x4c8ff, + BNXT_ULP_CLASS_HID_4d567 = 0x4d567, + BNXT_ULP_CLASS_HID_4ad1f = 0x4ad1f, + BNXT_ULP_CLASS_HID_4b987 = 0x4b987, + BNXT_ULP_CLASS_HID_4b35b = 0x4b35b, + BNXT_ULP_CLASS_HID_4bfc3 = 0x4bfc3, + BNXT_ULP_CLASS_HID_1b9fb = 0x1b9fb, + BNXT_ULP_CLASS_HID_1c663 = 0x1c663, + BNXT_ULP_CLASS_HID_1c027 = 0x1c027, + BNXT_ULP_CLASS_HID_1ccaf = 0x1ccaf, + BNXT_ULP_CLASS_HID_1a447 = 0x1a447, + BNXT_ULP_CLASS_HID_1b0cf = 0x1b0cf, + BNXT_ULP_CLASS_HID_1aa83 = 0x1aa83, + BNXT_ULP_CLASS_HID_1b70b = 0x1b70b, + BNXT_ULP_CLASS_HID_180b3 = 0x180b3, + BNXT_ULP_CLASS_HID_18d3b = 0x18d3b, + BNXT_ULP_CLASS_HID_186ff = 0x186ff, + BNXT_ULP_CLASS_HID_19367 = 0x19367, + BNXT_ULP_CLASS_HID_1c7eb = 0x1c7eb, + BNXT_ULP_CLASS_HID_1d453 = 0x1d453, + BNXT_ULP_CLASS_HID_1ce17 = 0x1ce17, + BNXT_ULP_CLASS_HID_1da9f = 0x1da9f, + BNXT_ULP_CLASS_HID_5b52f = 0x5b52f, + BNXT_ULP_CLASS_HID_5c197 = 0x5c197, + BNXT_ULP_CLASS_HID_5bb6b = 0x5bb6b, + BNXT_ULP_CLASS_HID_5c7d3 = 0x5c7d3, + BNXT_ULP_CLASS_HID_59f8b = 0x59f8b, + BNXT_ULP_CLASS_HID_5abf3 = 0x5abf3, + BNXT_ULP_CLASS_HID_5a5b7 = 0x5a5b7, + BNXT_ULP_CLASS_HID_5b23f = 0x5b23f, + BNXT_ULP_CLASS_HID_5d8b3 = 0x5d8b3, + BNXT_ULP_CLASS_HID_5886f = 0x5886f, + BNXT_ULP_CLASS_HID_58223 = 0x58223, + BNXT_ULP_CLASS_HID_58eab = 0x58eab, + BNXT_ULP_CLASS_HID_5c31f = 0x5c31f, + BNXT_ULP_CLASS_HID_5cf87 = 0x5cf87, + BNXT_ULP_CLASS_HID_5c95b = 0x5c95b, + BNXT_ULP_CLASS_HID_5d5c3 = 0x5d5c3, + BNXT_ULP_CLASS_HID_05f1 = 0x05f1, + BNXT_ULP_CLASS_HID_1209 = 0x1209, + BNXT_ULP_CLASS_HID_0bcd = 0x0bcd, BNXT_ULP_CLASS_HID_1845 = 0x1845, - BNXT_ULP_CLASS_HID_1399 = 0x1399, - BNXT_ULP_CLASS_HID_0eed = 0x0eed, - BNXT_ULP_CLASS_HID_0a21 = 0x0a21, + BNXT_ULP_CLASS_HID_25e9 = 0x25e9, + BNXT_ULP_CLASS_HID_3261 = 0x3261, + BNXT_ULP_CLASS_HID_2c25 = 0x2c25, BNXT_ULP_CLASS_HID_38bd = 0x38bd, - BNXT_ULP_CLASS_HID_33f1 = 0x33f1, - BNXT_ULP_CLASS_HID_2ec5 = 0x2ec5, - BNXT_ULP_CLASS_HID_2a19 = 0x2a19, - BNXT_ULP_CLASS_HID_121d = 0x121d, - BNXT_ULP_CLASS_HID_0d51 = 0x0d51, - BNXT_ULP_CLASS_HID_08a5 = 0x08a5, - BNXT_ULP_CLASS_HID_03f9 = 0x03f9, + BNXT_ULP_CLASS_HID_3c1d = 0x3c1d, + BNXT_ULP_CLASS_HID_4895 = 0x4895, + BNXT_ULP_CLASS_HID_4259 = 0x4259, BNXT_ULP_CLASS_HID_4ed1 = 0x4ed1, - BNXT_ULP_CLASS_HID_4a25 = 0x4a25, - BNXT_ULP_CLASS_HID_4579 = 0x4579, - BNXT_ULP_CLASS_HID_404d = 0x404d, - BNXT_ULP_CLASS_HID_1209 = 0x1209, - BNXT_ULP_CLASS_HID_0d5d = 0x0d5d, - BNXT_ULP_CLASS_HID_0891 = 0x0891, - BNXT_ULP_CLASS_HID_03e5 = 0x03e5, - BNXT_ULP_CLASS_HID_3261 = 0x3261, - BNXT_ULP_CLASS_HID_2db5 = 0x2db5, - BNXT_ULP_CLASS_HID_2889 = 0x2889, - BNXT_ULP_CLASS_HID_23dd = 0x23dd, + BNXT_ULP_CLASS_HID_5c75 = 0x5c75, BNXT_ULP_CLASS_HID_0bc1 = 0x0bc1, - BNXT_ULP_CLASS_HID_0715 = 0x0715, - BNXT_ULP_CLASS_HID_0269 = 0x0269, - BNXT_ULP_CLASS_HID_5a69 = 0x5a69, - BNXT_ULP_CLASS_HID_4895 = 0x4895, - BNXT_ULP_CLASS_HID_43e9 = 0x43e9, - BNXT_ULP_CLASS_HID_3f3d = 0x3f3d, - BNXT_ULP_CLASS_HID_3a71 = 0x3a71, - BNXT_ULP_CLASS_HID_0bcd = 0x0bcd, - BNXT_ULP_CLASS_HID_0701 = 0x0701, - BNXT_ULP_CLASS_HID_0255 = 0x0255, - BNXT_ULP_CLASS_HID_5a55 = 0x5a55, - BNXT_ULP_CLASS_HID_2c25 = 0x2c25, - BNXT_ULP_CLASS_HID_2779 = 0x2779, - BNXT_ULP_CLASS_HID_224d = 0x224d, - BNXT_ULP_CLASS_HID_1d81 = 0x1d81, BNXT_ULP_CLASS_HID_0585 = 0x0585, - BNXT_ULP_CLASS_HID_00d9 = 0x00d9, - BNXT_ULP_CLASS_HID_58d9 = 0x58d9, - BNXT_ULP_CLASS_HID_542d = 0x542d, - BNXT_ULP_CLASS_HID_4259 = 0x4259, - BNXT_ULP_CLASS_HID_3dad = 0x3dad, - BNXT_ULP_CLASS_HID_38e1 = 0x38e1, - BNXT_ULP_CLASS_HID_3435 = 0x3435, - BNXT_ULP_CLASS_HID_05f1 = 0x05f1, - BNXT_ULP_CLASS_HID_00c5 = 0x00c5, + BNXT_ULP_CLASS_HID_121d = 0x121d, BNXT_ULP_CLASS_HID_58c5 = 0x58c5, - BNXT_ULP_CLASS_HID_5419 = 0x5419, - BNXT_ULP_CLASS_HID_25e9 = 0x25e9, - BNXT_ULP_CLASS_HID_213d = 0x213d, + BNXT_ULP_CLASS_HID_0891 = 0x0891, + BNXT_ULP_CLASS_HID_0255 = 0x0255, + BNXT_ULP_CLASS_HID_0eed = 0x0eed, BNXT_ULP_CLASS_HID_1c71 = 0x1c71, - BNXT_ULP_CLASS_HID_1745 = 0x1745, - BNXT_ULP_CLASS_HID_5c75 = 0x5c75, - BNXT_ULP_CLASS_HID_5749 = 0x5749, - BNXT_ULP_CLASS_HID_529d = 0x529d, - BNXT_ULP_CLASS_HID_4dd1 = 0x4dd1, - BNXT_ULP_CLASS_HID_3c1d = 0x3c1d, - BNXT_ULP_CLASS_HID_3751 = 0x3751, + BNXT_ULP_CLASS_HID_2889 = 0x2889, + BNXT_ULP_CLASS_HID_224d = 0x224d, + BNXT_ULP_CLASS_HID_2ec5 = 0x2ec5, BNXT_ULP_CLASS_HID_32a5 = 0x32a5, - BNXT_ULP_CLASS_HID_2df9 = 0x2df9, - BNXT_ULP_CLASS_HID_4fe9 = 0x4fe9, - BNXT_ULP_CLASS_HID_4b3d = 0x4b3d, - BNXT_ULP_CLASS_HID_4671 = 0x4671, - BNXT_ULP_CLASS_HID_4145 = 0x4145, - BNXT_ULP_CLASS_HID_1315 = 0x1315, - BNXT_ULP_CLASS_HID_0e69 = 0x0e69, - BNXT_ULP_CLASS_HID_09bd = 0x09bd, - BNXT_ULP_CLASS_HID_04f1 = 0x04f1, - BNXT_ULP_CLASS_HID_49a1 = 0x49a1, - BNXT_ULP_CLASS_HID_44f5 = 0x44f5, - BNXT_ULP_CLASS_HID_3fc9 = 0x3fc9, - BNXT_ULP_CLASS_HID_3b1d = 0x3b1d, - BNXT_ULP_CLASS_HID_2949 = 0x2949, - BNXT_ULP_CLASS_HID_249d = 0x249d, - BNXT_ULP_CLASS_HID_1fd1 = 0x1fd1, - BNXT_ULP_CLASS_HID_1b25 = 0x1b25, - BNXT_ULP_CLASS_HID_49ad = 0x49ad, - BNXT_ULP_CLASS_HID_44e1 = 0x44e1, - BNXT_ULP_CLASS_HID_4035 = 0x4035, - BNXT_ULP_CLASS_HID_3b09 = 0x3b09, - BNXT_ULP_CLASS_HID_0cd9 = 0x0cd9, - BNXT_ULP_CLASS_HID_082d = 0x082d, - BNXT_ULP_CLASS_HID_0361 = 0x0361, - BNXT_ULP_CLASS_HID_5b61 = 0x5b61, - BNXT_ULP_CLASS_HID_4365 = 0x4365, - BNXT_ULP_CLASS_HID_3eb9 = 0x3eb9, - BNXT_ULP_CLASS_HID_398d = 0x398d, - BNXT_ULP_CLASS_HID_34c1 = 0x34c1, - BNXT_ULP_CLASS_HID_230d = 0x230d, - BNXT_ULP_CLASS_HID_1e41 = 0x1e41, - BNXT_ULP_CLASS_HID_1995 = 0x1995, - BNXT_ULP_CLASS_HID_14e9 = 0x14e9, - BNXT_ULP_CLASS_HID_2559 = 0x2559, - BNXT_ULP_CLASS_HID_2b95 = 0x2b95, - BNXT_ULP_CLASS_HID_4b8d = 0x4b8d, - BNXT_ULP_CLASS_HID_45b1 = 0x45b1, + BNXT_ULP_CLASS_HID_3f3d = 0x3f3d, + BNXT_ULP_CLASS_HID_38e1 = 0x38e1, + BNXT_ULP_CLASS_HID_4579 = 0x4579, + BNXT_ULP_CLASS_HID_529d = 0x529d, + BNXT_ULP_CLASS_HID_0269 = 0x0269, + BNXT_ULP_CLASS_HID_58d9 = 0x58d9, + BNXT_ULP_CLASS_HID_08a5 = 0x08a5, + BNXT_ULP_CLASS_HID_400c5 = 0x400c5, + BNXT_ULP_CLASS_HID_40d5d = 0x40d5d, + BNXT_ULP_CLASS_HID_40701 = 0x40701, + BNXT_ULP_CLASS_HID_41399 = 0x41399, + BNXT_ULP_CLASS_HID_4213d = 0x4213d, + BNXT_ULP_CLASS_HID_42db5 = 0x42db5, + BNXT_ULP_CLASS_HID_42779 = 0x42779, + BNXT_ULP_CLASS_HID_433f1 = 0x433f1, + BNXT_ULP_CLASS_HID_43751 = 0x43751, + BNXT_ULP_CLASS_HID_443e9 = 0x443e9, + BNXT_ULP_CLASS_HID_43dad = 0x43dad, + BNXT_ULP_CLASS_HID_44a25 = 0x44a25, + BNXT_ULP_CLASS_HID_45749 = 0x45749, + BNXT_ULP_CLASS_HID_40715 = 0x40715, + BNXT_ULP_CLASS_HID_400d9 = 0x400d9, + BNXT_ULP_CLASS_HID_40d51 = 0x40d51, + BNXT_ULP_CLASS_HID_45419 = 0x45419, + BNXT_ULP_CLASS_HID_403e5 = 0x403e5, + BNXT_ULP_CLASS_HID_45a55 = 0x45a55, + BNXT_ULP_CLASS_HID_40a21 = 0x40a21, + BNXT_ULP_CLASS_HID_41745 = 0x41745, + BNXT_ULP_CLASS_HID_423dd = 0x423dd, + BNXT_ULP_CLASS_HID_41d81 = 0x41d81, + BNXT_ULP_CLASS_HID_42a19 = 0x42a19, + BNXT_ULP_CLASS_HID_42df9 = 0x42df9, + BNXT_ULP_CLASS_HID_43a71 = 0x43a71, + BNXT_ULP_CLASS_HID_43435 = 0x43435, + BNXT_ULP_CLASS_HID_4404d = 0x4404d, + BNXT_ULP_CLASS_HID_44dd1 = 0x44dd1, + BNXT_ULP_CLASS_HID_45a69 = 0x45a69, + BNXT_ULP_CLASS_HID_4542d = 0x4542d, + BNXT_ULP_CLASS_HID_403f9 = 0x403f9, + BNXT_ULP_CLASS_HID_4140d = 0x4140d, + BNXT_ULP_CLASS_HID_420b5 = 0x420b5, + BNXT_ULP_CLASS_HID_41a49 = 0x41a49, + BNXT_ULP_CLASS_HID_426f1 = 0x426f1, + BNXT_ULP_CLASS_HID_44ab9 = 0x44ab9, + BNXT_ULP_CLASS_HID_45721 = 0x45721, + BNXT_ULP_CLASS_HID_450e5 = 0x450e5, + BNXT_ULP_CLASS_HID_40051 = 0x40051, + BNXT_ULP_CLASS_HID_40aa5 = 0x40aa5, + BNXT_ULP_CLASS_HID_4172d = 0x4172d, + BNXT_ULP_CLASS_HID_410e1 = 0x410e1, + BNXT_ULP_CLASS_HID_41d69 = 0x41d69, + BNXT_ULP_CLASS_HID_440d1 = 0x440d1, + BNXT_ULP_CLASS_HID_44d59 = 0x44d59, + BNXT_ULP_CLASS_HID_4471d = 0x4471d, + BNXT_ULP_CLASS_HID_45385 = 0x45385, + BNXT_ULP_CLASS_HID_6400d = 0x6400d, + BNXT_ULP_CLASS_HID_64cb5 = 0x64cb5, + BNXT_ULP_CLASS_HID_64649 = 0x64649, + BNXT_ULP_CLASS_HID_652f1 = 0x652f1, + BNXT_ULP_CLASS_HID_619ed = 0x619ed, + BNXT_ULP_CLASS_HID_62615 = 0x62615, + BNXT_ULP_CLASS_HID_62029 = 0x62029, + BNXT_ULP_CLASS_HID_62c51 = 0x62c51, + BNXT_ULP_CLASS_HID_636a5 = 0x636a5, + BNXT_ULP_CLASS_HID_6432d = 0x6432d, + BNXT_ULP_CLASS_HID_63ce1 = 0x63ce1, + BNXT_ULP_CLASS_HID_64969 = 0x64969, + BNXT_ULP_CLASS_HID_61005 = 0x61005, + BNXT_ULP_CLASS_HID_61c8d = 0x61c8d, + BNXT_ULP_CLASS_HID_61641 = 0x61641, + BNXT_ULP_CLASS_HID_622c9 = 0x622c9, + BNXT_ULP_CLASS_HID_52a0d = 0x52a0d, + BNXT_ULP_CLASS_HID_536b5 = 0x536b5, + BNXT_ULP_CLASS_HID_53049 = 0x53049, + BNXT_ULP_CLASS_HID_53cf1 = 0x53cf1, + BNXT_ULP_CLASS_HID_503ed = 0x503ed, + BNXT_ULP_CLASS_HID_51015 = 0x51015, + BNXT_ULP_CLASS_HID_50a29 = 0x50a29, + BNXT_ULP_CLASS_HID_51651 = 0x51651, + BNXT_ULP_CLASS_HID_520a5 = 0x520a5, + BNXT_ULP_CLASS_HID_52d2d = 0x52d2d, + BNXT_ULP_CLASS_HID_526e1 = 0x526e1, + BNXT_ULP_CLASS_HID_53369 = 0x53369, + BNXT_ULP_CLASS_HID_556d1 = 0x556d1, + BNXT_ULP_CLASS_HID_5068d = 0x5068d, + BNXT_ULP_CLASS_HID_50041 = 0x50041, + BNXT_ULP_CLASS_HID_50cc9 = 0x50cc9, + BNXT_ULP_CLASS_HID_7560d = 0x7560d, + BNXT_ULP_CLASS_HID_705f9 = 0x705f9, + BNXT_ULP_CLASS_HID_75c49 = 0x75c49, + BNXT_ULP_CLASS_HID_70c25 = 0x70c25, + BNXT_ULP_CLASS_HID_72fed = 0x72fed, + BNXT_ULP_CLASS_HID_73c15 = 0x73c15, + BNXT_ULP_CLASS_HID_73629 = 0x73629, + BNXT_ULP_CLASS_HID_74251 = 0x74251, + BNXT_ULP_CLASS_HID_74ca5 = 0x74ca5, + BNXT_ULP_CLASS_HID_7592d = 0x7592d, + BNXT_ULP_CLASS_HID_752e1 = 0x752e1, + BNXT_ULP_CLASS_HID_7025d = 0x7025d, + BNXT_ULP_CLASS_HID_72605 = 0x72605, + BNXT_ULP_CLASS_HID_7328d = 0x7328d, + BNXT_ULP_CLASS_HID_72c41 = 0x72c41, + BNXT_ULP_CLASS_HID_738c9 = 0x738c9, + BNXT_ULP_CLASS_HID_0591 = 0x0591, + BNXT_ULP_CLASS_HID_1269 = 0x1269, + BNXT_ULP_CLASS_HID_0bad = 0x0bad, BNXT_ULP_CLASS_HID_1825 = 0x1825, - BNXT_ULP_CLASS_HID_13f9 = 0x13f9, - BNXT_ULP_CLASS_HID_0e8d = 0x0e8d, - BNXT_ULP_CLASS_HID_0a41 = 0x0a41, + BNXT_ULP_CLASS_HID_2589 = 0x2589, + BNXT_ULP_CLASS_HID_3201 = 0x3201, + BNXT_ULP_CLASS_HID_2c45 = 0x2c45, BNXT_ULP_CLASS_HID_38dd = 0x38dd, - BNXT_ULP_CLASS_HID_3391 = 0x3391, - BNXT_ULP_CLASS_HID_2ea5 = 0x2ea5, - BNXT_ULP_CLASS_HID_2a79 = 0x2a79, - BNXT_ULP_CLASS_HID_127d = 0x127d, - BNXT_ULP_CLASS_HID_0d31 = 0x0d31, - BNXT_ULP_CLASS_HID_08c5 = 0x08c5, - BNXT_ULP_CLASS_HID_0399 = 0x0399, + BNXT_ULP_CLASS_HID_3c7d = 0x3c7d, + BNXT_ULP_CLASS_HID_48f5 = 0x48f5, + BNXT_ULP_CLASS_HID_4239 = 0x4239, BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1, - BNXT_ULP_CLASS_HID_4a45 = 0x4a45, - BNXT_ULP_CLASS_HID_4519 = 0x4519, - BNXT_ULP_CLASS_HID_402d = 0x402d, - BNXT_ULP_CLASS_HID_1269 = 0x1269, - BNXT_ULP_CLASS_HID_0d3d = 0x0d3d, - BNXT_ULP_CLASS_HID_08f1 = 0x08f1, - BNXT_ULP_CLASS_HID_0385 = 0x0385, - BNXT_ULP_CLASS_HID_3201 = 0x3201, - BNXT_ULP_CLASS_HID_2dd5 = 0x2dd5, - BNXT_ULP_CLASS_HID_28e9 = 0x28e9, - BNXT_ULP_CLASS_HID_23bd = 0x23bd, + BNXT_ULP_CLASS_HID_5c15 = 0x5c15, BNXT_ULP_CLASS_HID_0ba1 = 0x0ba1, - BNXT_ULP_CLASS_HID_0775 = 0x0775, - BNXT_ULP_CLASS_HID_0209 = 0x0209, - BNXT_ULP_CLASS_HID_5a09 = 0x5a09, - BNXT_ULP_CLASS_HID_48f5 = 0x48f5, - BNXT_ULP_CLASS_HID_4389 = 0x4389, - BNXT_ULP_CLASS_HID_3f5d = 0x3f5d, - BNXT_ULP_CLASS_HID_3a11 = 0x3a11, - BNXT_ULP_CLASS_HID_0bad = 0x0bad, - BNXT_ULP_CLASS_HID_0761 = 0x0761, - BNXT_ULP_CLASS_HID_0235 = 0x0235, - BNXT_ULP_CLASS_HID_5a35 = 0x5a35, - BNXT_ULP_CLASS_HID_2c45 = 0x2c45, - BNXT_ULP_CLASS_HID_2719 = 0x2719, - BNXT_ULP_CLASS_HID_222d = 0x222d, - BNXT_ULP_CLASS_HID_1de1 = 0x1de1, BNXT_ULP_CLASS_HID_05e5 = 0x05e5, - BNXT_ULP_CLASS_HID_00b9 = 0x00b9, - BNXT_ULP_CLASS_HID_58b9 = 0x58b9, - BNXT_ULP_CLASS_HID_544d = 0x544d, - BNXT_ULP_CLASS_HID_4239 = 0x4239, - BNXT_ULP_CLASS_HID_3dcd = 0x3dcd, - BNXT_ULP_CLASS_HID_3881 = 0x3881, - BNXT_ULP_CLASS_HID_3455 = 0x3455, - BNXT_ULP_CLASS_HID_0591 = 0x0591, - BNXT_ULP_CLASS_HID_00a5 = 0x00a5, + BNXT_ULP_CLASS_HID_127d = 0x127d, BNXT_ULP_CLASS_HID_58a5 = 0x58a5, - BNXT_ULP_CLASS_HID_5479 = 0x5479, - BNXT_ULP_CLASS_HID_2589 = 0x2589, - BNXT_ULP_CLASS_HID_215d = 0x215d, + BNXT_ULP_CLASS_HID_08f1 = 0x08f1, + BNXT_ULP_CLASS_HID_0235 = 0x0235, + BNXT_ULP_CLASS_HID_0e8d = 0x0e8d, BNXT_ULP_CLASS_HID_1c11 = 0x1c11, - BNXT_ULP_CLASS_HID_1725 = 0x1725, - BNXT_ULP_CLASS_HID_5c15 = 0x5c15, - BNXT_ULP_CLASS_HID_5729 = 0x5729, - BNXT_ULP_CLASS_HID_52fd = 0x52fd, - BNXT_ULP_CLASS_HID_4db1 = 0x4db1, - BNXT_ULP_CLASS_HID_3c7d = 0x3c7d, - BNXT_ULP_CLASS_HID_3731 = 0x3731, + BNXT_ULP_CLASS_HID_28e9 = 0x28e9, + BNXT_ULP_CLASS_HID_222d = 0x222d, + BNXT_ULP_CLASS_HID_2ea5 = 0x2ea5, BNXT_ULP_CLASS_HID_32c5 = 0x32c5, - BNXT_ULP_CLASS_HID_2d99 = 0x2d99, - BNXT_ULP_CLASS_HID_4f89 = 0x4f89, - BNXT_ULP_CLASS_HID_4b5d = 0x4b5d, - BNXT_ULP_CLASS_HID_4611 = 0x4611, - BNXT_ULP_CLASS_HID_4125 = 0x4125, - BNXT_ULP_CLASS_HID_1375 = 0x1375, - BNXT_ULP_CLASS_HID_0e09 = 0x0e09, - BNXT_ULP_CLASS_HID_09dd = 0x09dd, - BNXT_ULP_CLASS_HID_0491 = 0x0491, - BNXT_ULP_CLASS_HID_49c1 = 0x49c1, - BNXT_ULP_CLASS_HID_4495 = 0x4495, - BNXT_ULP_CLASS_HID_3fa9 = 0x3fa9, - BNXT_ULP_CLASS_HID_3b7d = 0x3b7d, - BNXT_ULP_CLASS_HID_2929 = 0x2929, - BNXT_ULP_CLASS_HID_24fd = 0x24fd, - BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1, - BNXT_ULP_CLASS_HID_1b45 = 0x1b45, - BNXT_ULP_CLASS_HID_49cd = 0x49cd, - BNXT_ULP_CLASS_HID_4481 = 0x4481, - BNXT_ULP_CLASS_HID_4055 = 0x4055, - BNXT_ULP_CLASS_HID_3b69 = 0x3b69, - BNXT_ULP_CLASS_HID_0cb9 = 0x0cb9, - BNXT_ULP_CLASS_HID_084d = 0x084d, - BNXT_ULP_CLASS_HID_0301 = 0x0301, - BNXT_ULP_CLASS_HID_5b01 = 0x5b01, - BNXT_ULP_CLASS_HID_4305 = 0x4305, - BNXT_ULP_CLASS_HID_3ed9 = 0x3ed9, - BNXT_ULP_CLASS_HID_39ed = 0x39ed, - BNXT_ULP_CLASS_HID_34a1 = 0x34a1, - BNXT_ULP_CLASS_HID_236d = 0x236d, - BNXT_ULP_CLASS_HID_1e21 = 0x1e21, - BNXT_ULP_CLASS_HID_19f5 = 0x19f5, - BNXT_ULP_CLASS_HID_1489 = 0x1489, - BNXT_ULP_CLASS_HID_2539 = 0x2539, - BNXT_ULP_CLASS_HID_2bf5 = 0x2bf5, - BNXT_ULP_CLASS_HID_4bed = 0x4bed, - BNXT_ULP_CLASS_HID_45d1 = 0x45d1, - BNXT_ULP_CLASS_HID_b6af = 0xb6af, - BNXT_ULP_CLASS_HID_b1d3 = 0xb1d3, - BNXT_ULP_CLASS_HID_1c7d3 = 0x1c7d3, - BNXT_ULP_CLASS_HID_1ccaf = 0x1ccaf, - BNXT_ULP_CLASS_HID_da33 = 0xda33, - BNXT_ULP_CLASS_HID_d567 = 0xd567, - BNXT_ULP_CLASS_HID_18eab = 0x18eab, - BNXT_ULP_CLASS_HID_19367 = 0x19367, - BNXT_ULP_CLASS_HID_a10b = 0xa10b, - BNXT_ULP_CLASS_HID_9c3f = 0x9c3f, - BNXT_ULP_CLASS_HID_1b23f = 0x1b23f, - BNXT_ULP_CLASS_HID_1b70b = 0x1b70b, - BNXT_ULP_CLASS_HID_c49f = 0xc49f, - BNXT_ULP_CLASS_HID_bfc3 = 0xbfc3, - BNXT_ULP_CLASS_HID_1d5c3 = 0x1d5c3, - BNXT_ULP_CLASS_HID_1da9f = 0x1da9f, - BNXT_ULP_CLASS_HID_b063 = 0xb063, - BNXT_ULP_CLASS_HID_ab97 = 0xab97, - BNXT_ULP_CLASS_HID_1c197 = 0x1c197, - BNXT_ULP_CLASS_HID_1c663 = 0x1c663, - BNXT_ULP_CLASS_HID_d3f7 = 0xd3f7, - BNXT_ULP_CLASS_HID_cf3b = 0xcf3b, - BNXT_ULP_CLASS_HID_1886f = 0x1886f, - BNXT_ULP_CLASS_HID_18d3b = 0x18d3b, - BNXT_ULP_CLASS_HID_9acf = 0x9acf, - BNXT_ULP_CLASS_HID_95f3 = 0x95f3, - BNXT_ULP_CLASS_HID_1abf3 = 0x1abf3, - BNXT_ULP_CLASS_HID_1b0cf = 0x1b0cf, - BNXT_ULP_CLASS_HID_be53 = 0xbe53, - BNXT_ULP_CLASS_HID_b987 = 0xb987, - BNXT_ULP_CLASS_HID_1cf87 = 0x1cf87, - BNXT_ULP_CLASS_HID_1d453 = 0x1d453, - BNXT_ULP_CLASS_HID_aa27 = 0xaa27, - BNXT_ULP_CLASS_HID_a56b = 0xa56b, - BNXT_ULP_CLASS_HID_1bb6b = 0x1bb6b, - BNXT_ULP_CLASS_HID_1c027 = 0x1c027, - BNXT_ULP_CLASS_HID_cdcb = 0xcdcb, - BNXT_ULP_CLASS_HID_c8ff = 0xc8ff, - BNXT_ULP_CLASS_HID_18223 = 0x18223, - BNXT_ULP_CLASS_HID_186ff = 0x186ff, - BNXT_ULP_CLASS_HID_9483 = 0x9483, - BNXT_ULP_CLASS_HID_8fb7 = 0x8fb7, - BNXT_ULP_CLASS_HID_1a5b7 = 0x1a5b7, - BNXT_ULP_CLASS_HID_1aa83 = 0x1aa83, - BNXT_ULP_CLASS_HID_b817 = 0xb817, - BNXT_ULP_CLASS_HID_b35b = 0xb35b, - BNXT_ULP_CLASS_HID_1c95b = 0x1c95b, - BNXT_ULP_CLASS_HID_1ce17 = 0x1ce17, - BNXT_ULP_CLASS_HID_a3fb = 0xa3fb, - BNXT_ULP_CLASS_HID_9f2f = 0x9f2f, - BNXT_ULP_CLASS_HID_1b52f = 0x1b52f, - BNXT_ULP_CLASS_HID_1b9fb = 0x1b9fb, - BNXT_ULP_CLASS_HID_c78f = 0xc78f, - BNXT_ULP_CLASS_HID_c2b3 = 0xc2b3, - BNXT_ULP_CLASS_HID_1d8b3 = 0x1d8b3, - BNXT_ULP_CLASS_HID_180b3 = 0x180b3, - BNXT_ULP_CLASS_HID_8e47 = 0x8e47, - BNXT_ULP_CLASS_HID_898b = 0x898b, - BNXT_ULP_CLASS_HID_19f8b = 0x19f8b, - BNXT_ULP_CLASS_HID_1a447 = 0x1a447, - BNXT_ULP_CLASS_HID_b1eb = 0xb1eb, - BNXT_ULP_CLASS_HID_ad1f = 0xad1f, - BNXT_ULP_CLASS_HID_1c31f = 0x1c31f, - BNXT_ULP_CLASS_HID_1c7eb = 0x1c7eb, - BNXT_ULP_CLASS_HID_9137 = 0x9137, - BNXT_ULP_CLASS_HID_8c7b = 0x8c7b, - BNXT_ULP_CLASS_HID_1a27b = 0x1a27b, - BNXT_ULP_CLASS_HID_1a737 = 0x1a737, - BNXT_ULP_CLASS_HID_b4db = 0xb4db, - BNXT_ULP_CLASS_HID_b00f = 0xb00f, - BNXT_ULP_CLASS_HID_1c60f = 0x1c60f, - BNXT_ULP_CLASS_HID_1cadb = 0x1cadb, - BNXT_ULP_CLASS_HID_8b0b = 0x8b0b, - BNXT_ULP_CLASS_HID_863f = 0x863f, - BNXT_ULP_CLASS_HID_19c3f = 0x19c3f, - BNXT_ULP_CLASS_HID_1a10b = 0x1a10b, - BNXT_ULP_CLASS_HID_ae9f = 0xae9f, - BNXT_ULP_CLASS_HID_a9c3 = 0xa9c3, - BNXT_ULP_CLASS_HID_1bfc3 = 0x1bfc3, - BNXT_ULP_CLASS_HID_1c49f = 0x1c49f, - BNXT_ULP_CLASS_HID_2563 = 0x2563, - BNXT_ULP_CLASS_HID_2baf = 0x2baf, - BNXT_ULP_CLASS_HID_26d3 = 0x26d3, - BNXT_ULP_CLASS_HID_4f33 = 0x4f33, - BNXT_ULP_CLASS_HID_4a67 = 0x4a67, - BNXT_ULP_CLASS_HID_160b = 0x160b, - BNXT_ULP_CLASS_HID_113f = 0x113f, - BNXT_ULP_CLASS_HID_399f = 0x399f, - BNXT_ULP_CLASS_HID_34c3 = 0x34c3, - BNXT_ULP_CLASS_HID_2097 = 0x2097, - BNXT_ULP_CLASS_HID_48f7 = 0x48f7, - BNXT_ULP_CLASS_HID_443b = 0x443b, - BNXT_ULP_CLASS_HID_0fcf = 0x0fcf, - BNXT_ULP_CLASS_HID_0af3 = 0x0af3, - BNXT_ULP_CLASS_HID_3353 = 0x3353, - BNXT_ULP_CLASS_HID_2e87 = 0x2e87, + BNXT_ULP_CLASS_HID_3f5d = 0x3f5d, + BNXT_ULP_CLASS_HID_3881 = 0x3881, + BNXT_ULP_CLASS_HID_4519 = 0x4519, + BNXT_ULP_CLASS_HID_52fd = 0x52fd, + BNXT_ULP_CLASS_HID_0209 = 0x0209, + BNXT_ULP_CLASS_HID_58b9 = 0x58b9, + BNXT_ULP_CLASS_HID_08c5 = 0x08c5, + BNXT_ULP_CLASS_HID_400a5 = 0x400a5, + BNXT_ULP_CLASS_HID_40d3d = 0x40d3d, + BNXT_ULP_CLASS_HID_40761 = 0x40761, + BNXT_ULP_CLASS_HID_413f9 = 0x413f9, + BNXT_ULP_CLASS_HID_4215d = 0x4215d, + BNXT_ULP_CLASS_HID_42dd5 = 0x42dd5, + BNXT_ULP_CLASS_HID_42719 = 0x42719, + BNXT_ULP_CLASS_HID_43391 = 0x43391, + BNXT_ULP_CLASS_HID_43731 = 0x43731, + BNXT_ULP_CLASS_HID_44389 = 0x44389, + BNXT_ULP_CLASS_HID_43dcd = 0x43dcd, + BNXT_ULP_CLASS_HID_44a45 = 0x44a45, + BNXT_ULP_CLASS_HID_45729 = 0x45729, + BNXT_ULP_CLASS_HID_40775 = 0x40775, + BNXT_ULP_CLASS_HID_400b9 = 0x400b9, + BNXT_ULP_CLASS_HID_40d31 = 0x40d31, + BNXT_ULP_CLASS_HID_45479 = 0x45479, + BNXT_ULP_CLASS_HID_40385 = 0x40385, + BNXT_ULP_CLASS_HID_45a35 = 0x45a35, + BNXT_ULP_CLASS_HID_40a41 = 0x40a41, + BNXT_ULP_CLASS_HID_41725 = 0x41725, + BNXT_ULP_CLASS_HID_423bd = 0x423bd, + BNXT_ULP_CLASS_HID_41de1 = 0x41de1, + BNXT_ULP_CLASS_HID_42a79 = 0x42a79, + BNXT_ULP_CLASS_HID_42d99 = 0x42d99, + BNXT_ULP_CLASS_HID_43a11 = 0x43a11, + BNXT_ULP_CLASS_HID_43455 = 0x43455, + BNXT_ULP_CLASS_HID_4402d = 0x4402d, + BNXT_ULP_CLASS_HID_44db1 = 0x44db1, + BNXT_ULP_CLASS_HID_45a09 = 0x45a09, + BNXT_ULP_CLASS_HID_4544d = 0x4544d, + BNXT_ULP_CLASS_HID_40399 = 0x40399, + BNXT_ULP_CLASS_HID_4146d = 0x4146d, + BNXT_ULP_CLASS_HID_420d5 = 0x420d5, + BNXT_ULP_CLASS_HID_41a29 = 0x41a29, + BNXT_ULP_CLASS_HID_42691 = 0x42691, + BNXT_ULP_CLASS_HID_44ad9 = 0x44ad9, + BNXT_ULP_CLASS_HID_45741 = 0x45741, + BNXT_ULP_CLASS_HID_45085 = 0x45085, + BNXT_ULP_CLASS_HID_40031 = 0x40031, + BNXT_ULP_CLASS_HID_40ac5 = 0x40ac5, + BNXT_ULP_CLASS_HID_4174d = 0x4174d, + BNXT_ULP_CLASS_HID_41081 = 0x41081, + BNXT_ULP_CLASS_HID_41d09 = 0x41d09, + BNXT_ULP_CLASS_HID_440b1 = 0x440b1, + BNXT_ULP_CLASS_HID_44d39 = 0x44d39, + BNXT_ULP_CLASS_HID_4477d = 0x4477d, + BNXT_ULP_CLASS_HID_453e5 = 0x453e5, + BNXT_ULP_CLASS_HID_6406d = 0x6406d, + BNXT_ULP_CLASS_HID_64cd5 = 0x64cd5, + BNXT_ULP_CLASS_HID_64629 = 0x64629, + BNXT_ULP_CLASS_HID_65291 = 0x65291, + BNXT_ULP_CLASS_HID_6198d = 0x6198d, + BNXT_ULP_CLASS_HID_62675 = 0x62675, + BNXT_ULP_CLASS_HID_62049 = 0x62049, + BNXT_ULP_CLASS_HID_62c31 = 0x62c31, + BNXT_ULP_CLASS_HID_636c5 = 0x636c5, + BNXT_ULP_CLASS_HID_6434d = 0x6434d, + BNXT_ULP_CLASS_HID_63c81 = 0x63c81, + BNXT_ULP_CLASS_HID_64909 = 0x64909, + BNXT_ULP_CLASS_HID_61065 = 0x61065, + BNXT_ULP_CLASS_HID_61ced = 0x61ced, + BNXT_ULP_CLASS_HID_61621 = 0x61621, + BNXT_ULP_CLASS_HID_622a9 = 0x622a9, + BNXT_ULP_CLASS_HID_52a6d = 0x52a6d, + BNXT_ULP_CLASS_HID_536d5 = 0x536d5, + BNXT_ULP_CLASS_HID_53029 = 0x53029, + BNXT_ULP_CLASS_HID_53c91 = 0x53c91, + BNXT_ULP_CLASS_HID_5038d = 0x5038d, + BNXT_ULP_CLASS_HID_51075 = 0x51075, + BNXT_ULP_CLASS_HID_50a49 = 0x50a49, + BNXT_ULP_CLASS_HID_51631 = 0x51631, + BNXT_ULP_CLASS_HID_520c5 = 0x520c5, + BNXT_ULP_CLASS_HID_52d4d = 0x52d4d, + BNXT_ULP_CLASS_HID_52681 = 0x52681, + BNXT_ULP_CLASS_HID_53309 = 0x53309, + BNXT_ULP_CLASS_HID_556b1 = 0x556b1, + BNXT_ULP_CLASS_HID_506ed = 0x506ed, + BNXT_ULP_CLASS_HID_50021 = 0x50021, + BNXT_ULP_CLASS_HID_50ca9 = 0x50ca9, + BNXT_ULP_CLASS_HID_7566d = 0x7566d, + BNXT_ULP_CLASS_HID_70599 = 0x70599, + BNXT_ULP_CLASS_HID_75c29 = 0x75c29, + BNXT_ULP_CLASS_HID_70c45 = 0x70c45, + BNXT_ULP_CLASS_HID_72f8d = 0x72f8d, + BNXT_ULP_CLASS_HID_73c75 = 0x73c75, + BNXT_ULP_CLASS_HID_73649 = 0x73649, + BNXT_ULP_CLASS_HID_74231 = 0x74231, + BNXT_ULP_CLASS_HID_74cc5 = 0x74cc5, + BNXT_ULP_CLASS_HID_7594d = 0x7594d, + BNXT_ULP_CLASS_HID_75281 = 0x75281, + BNXT_ULP_CLASS_HID_7023d = 0x7023d, + BNXT_ULP_CLASS_HID_72665 = 0x72665, + BNXT_ULP_CLASS_HID_732ed = 0x732ed, + BNXT_ULP_CLASS_HID_72c21 = 0x72c21, + BNXT_ULP_CLASS_HID_738a9 = 0x738a9, + BNXT_ULP_CLASS_HID_244c3 = 0x244c3, + BNXT_ULP_CLASS_HID_2515b = 0x2515b, + BNXT_ULP_CLASS_HID_24b1f = 0x24b1f, + BNXT_ULP_CLASS_HID_25797 = 0x25797, + BNXT_ULP_CLASS_HID_22f7f = 0x22f7f, + BNXT_ULP_CLASS_HID_23bf7 = 0x23bf7, + BNXT_ULP_CLASS_HID_235bb = 0x235bb, + BNXT_ULP_CLASS_HID_24233 = 0x24233, + BNXT_ULP_CLASS_HID_20b8b = 0x20b8b, + BNXT_ULP_CLASS_HID_21803 = 0x21803, + BNXT_ULP_CLASS_HID_211c7 = 0x211c7, + BNXT_ULP_CLASS_HID_21e5f = 0x21e5f, + BNXT_ULP_CLASS_HID_252d3 = 0x252d3, + BNXT_ULP_CLASS_HID_202bf = 0x202bf, + BNXT_ULP_CLASS_HID_2592f = 0x2592f, + BNXT_ULP_CLASS_HID_208fb = 0x208fb, + BNXT_ULP_CLASS_HID_231f3 = 0x231f3, + BNXT_ULP_CLASS_HID_23e0b = 0x23e0b, + BNXT_ULP_CLASS_HID_237cf = 0x237cf, + BNXT_ULP_CLASS_HID_24447 = 0x24447, + BNXT_ULP_CLASS_HID_21c2f = 0x21c2f, + BNXT_ULP_CLASS_HID_228a7 = 0x228a7, + BNXT_ULP_CLASS_HID_2226b = 0x2226b, + BNXT_ULP_CLASS_HID_22ee3 = 0x22ee3, + BNXT_ULP_CLASS_HID_25567 = 0x25567, + BNXT_ULP_CLASS_HID_20533 = 0x20533, + BNXT_ULP_CLASS_HID_25ba3 = 0x25ba3, + BNXT_ULP_CLASS_HID_20b0f = 0x20b0f, + BNXT_ULP_CLASS_HID_23f83 = 0x23f83, + BNXT_ULP_CLASS_HID_24c1b = 0x24c1b, + BNXT_ULP_CLASS_HID_245df = 0x245df, + BNXT_ULP_CLASS_HID_25257 = 0x25257, + BNXT_ULP_CLASS_HID_64017 = 0x64017, + BNXT_ULP_CLASS_HID_64caf = 0x64caf, + BNXT_ULP_CLASS_HID_64653 = 0x64653, + BNXT_ULP_CLASS_HID_652eb = 0x652eb, + BNXT_ULP_CLASS_HID_62ab3 = 0x62ab3, + BNXT_ULP_CLASS_HID_636cb = 0x636cb, + BNXT_ULP_CLASS_HID_6308f = 0x6308f, + BNXT_ULP_CLASS_HID_63d07 = 0x63d07, + BNXT_ULP_CLASS_HID_606df = 0x606df, + BNXT_ULP_CLASS_HID_61357 = 0x61357, + BNXT_ULP_CLASS_HID_60d1b = 0x60d1b, + BNXT_ULP_CLASS_HID_61993 = 0x61993, + BNXT_ULP_CLASS_HID_64e27 = 0x64e27, + BNXT_ULP_CLASS_HID_65abf = 0x65abf, + BNXT_ULP_CLASS_HID_65463 = 0x65463, + BNXT_ULP_CLASS_HID_603cf = 0x603cf, + BNXT_ULP_CLASS_HID_62cc7 = 0x62cc7, + BNXT_ULP_CLASS_HID_6395f = 0x6395f, + BNXT_ULP_CLASS_HID_63303 = 0x63303, + BNXT_ULP_CLASS_HID_63f9b = 0x63f9b, + BNXT_ULP_CLASS_HID_61763 = 0x61763, + BNXT_ULP_CLASS_HID_623fb = 0x623fb, + BNXT_ULP_CLASS_HID_61dbf = 0x61dbf, + BNXT_ULP_CLASS_HID_62a37 = 0x62a37, + BNXT_ULP_CLASS_HID_650bb = 0x650bb, + BNXT_ULP_CLASS_HID_60007 = 0x60007, + BNXT_ULP_CLASS_HID_656f7 = 0x656f7, + BNXT_ULP_CLASS_HID_60643 = 0x60643, + BNXT_ULP_CLASS_HID_63ad7 = 0x63ad7, + BNXT_ULP_CLASS_HID_6476f = 0x6476f, + BNXT_ULP_CLASS_HID_64113 = 0x64113, + BNXT_ULP_CLASS_HID_64dab = 0x64dab, + BNXT_ULP_CLASS_HID_35ac3 = 0x35ac3, + BNXT_ULP_CLASS_HID_30aaf = 0x30aaf, + BNXT_ULP_CLASS_HID_30453 = 0x30453, + BNXT_ULP_CLASS_HID_310eb = 0x310eb, + BNXT_ULP_CLASS_HID_3457f = 0x3457f, + BNXT_ULP_CLASS_HID_351f7 = 0x351f7, + BNXT_ULP_CLASS_HID_34bbb = 0x34bbb, + BNXT_ULP_CLASS_HID_35833 = 0x35833, + BNXT_ULP_CLASS_HID_3218b = 0x3218b, + BNXT_ULP_CLASS_HID_32e03 = 0x32e03, + BNXT_ULP_CLASS_HID_327c7 = 0x327c7, + BNXT_ULP_CLASS_HID_3345f = 0x3345f, + BNXT_ULP_CLASS_HID_30c27 = 0x30c27, + BNXT_ULP_CLASS_HID_318bf = 0x318bf, + BNXT_ULP_CLASS_HID_31263 = 0x31263, + BNXT_ULP_CLASS_HID_31efb = 0x31efb, + BNXT_ULP_CLASS_HID_347f3 = 0x347f3, + BNXT_ULP_CLASS_HID_3540b = 0x3540b, + BNXT_ULP_CLASS_HID_34dcf = 0x34dcf, + BNXT_ULP_CLASS_HID_35a47 = 0x35a47, + BNXT_ULP_CLASS_HID_3322f = 0x3322f, + BNXT_ULP_CLASS_HID_33ea7 = 0x33ea7, + BNXT_ULP_CLASS_HID_3386b = 0x3386b, + BNXT_ULP_CLASS_HID_344e3 = 0x344e3, + BNXT_ULP_CLASS_HID_30ebb = 0x30ebb, + BNXT_ULP_CLASS_HID_31b33 = 0x31b33, + BNXT_ULP_CLASS_HID_314f7 = 0x314f7, + BNXT_ULP_CLASS_HID_3210f = 0x3210f, + BNXT_ULP_CLASS_HID_35583 = 0x35583, + BNXT_ULP_CLASS_HID_3056f = 0x3056f, + BNXT_ULP_CLASS_HID_35bdf = 0x35bdf, + BNXT_ULP_CLASS_HID_30bab = 0x30bab, + BNXT_ULP_CLASS_HID_75617 = 0x75617, + BNXT_ULP_CLASS_HID_705e3 = 0x705e3, + BNXT_ULP_CLASS_HID_75c53 = 0x75c53, + BNXT_ULP_CLASS_HID_70c3f = 0x70c3f, + BNXT_ULP_CLASS_HID_740b3 = 0x740b3, + BNXT_ULP_CLASS_HID_74ccb = 0x74ccb, + BNXT_ULP_CLASS_HID_7468f = 0x7468f, + BNXT_ULP_CLASS_HID_75307 = 0x75307, + BNXT_ULP_CLASS_HID_71cdf = 0x71cdf, + BNXT_ULP_CLASS_HID_72957 = 0x72957, + BNXT_ULP_CLASS_HID_7231b = 0x7231b, + BNXT_ULP_CLASS_HID_72f93 = 0x72f93, + BNXT_ULP_CLASS_HID_7077b = 0x7077b, + BNXT_ULP_CLASS_HID_713f3 = 0x713f3, + BNXT_ULP_CLASS_HID_70db7 = 0x70db7, + BNXT_ULP_CLASS_HID_719cf = 0x719cf, + BNXT_ULP_CLASS_HID_742c7 = 0x742c7, + BNXT_ULP_CLASS_HID_74f5f = 0x74f5f, + BNXT_ULP_CLASS_HID_74903 = 0x74903, + BNXT_ULP_CLASS_HID_7559b = 0x7559b, + BNXT_ULP_CLASS_HID_72d63 = 0x72d63, + BNXT_ULP_CLASS_HID_739fb = 0x739fb, + BNXT_ULP_CLASS_HID_733bf = 0x733bf, + BNXT_ULP_CLASS_HID_74037 = 0x74037, + BNXT_ULP_CLASS_HID_7098f = 0x7098f, + BNXT_ULP_CLASS_HID_71607 = 0x71607, + BNXT_ULP_CLASS_HID_70fcb = 0x70fcb, + BNXT_ULP_CLASS_HID_71c43 = 0x71c43, + BNXT_ULP_CLASS_HID_750d7 = 0x750d7, + BNXT_ULP_CLASS_HID_700a3 = 0x700a3, + BNXT_ULP_CLASS_HID_75713 = 0x75713, + BNXT_ULP_CLASS_HID_706ff = 0x706ff, + BNXT_ULP_CLASS_HID_2cfc3 = 0x2cfc3, + BNXT_ULP_CLASS_HID_2dc5b = 0x2dc5b, + BNXT_ULP_CLASS_HID_2d61f = 0x2d61f, + BNXT_ULP_CLASS_HID_285eb = 0x285eb, + BNXT_ULP_CLASS_HID_2ba7f = 0x2ba7f, + BNXT_ULP_CLASS_HID_2c6f7 = 0x2c6f7, + BNXT_ULP_CLASS_HID_2c0bb = 0x2c0bb, + BNXT_ULP_CLASS_HID_2cd33 = 0x2cd33, + BNXT_ULP_CLASS_HID_2968b = 0x2968b, + BNXT_ULP_CLASS_HID_2a303 = 0x2a303, + BNXT_ULP_CLASS_HID_29cc7 = 0x29cc7, + BNXT_ULP_CLASS_HID_2a95f = 0x2a95f, + BNXT_ULP_CLASS_HID_28127 = 0x28127, + BNXT_ULP_CLASS_HID_28dbf = 0x28dbf, + BNXT_ULP_CLASS_HID_28763 = 0x28763, + BNXT_ULP_CLASS_HID_293fb = 0x293fb, + BNXT_ULP_CLASS_HID_2bcf3 = 0x2bcf3, + BNXT_ULP_CLASS_HID_2c90b = 0x2c90b, + BNXT_ULP_CLASS_HID_2c2cf = 0x2c2cf, + BNXT_ULP_CLASS_HID_2cf47 = 0x2cf47, + BNXT_ULP_CLASS_HID_2a72f = 0x2a72f, + BNXT_ULP_CLASS_HID_2b3a7 = 0x2b3a7, + BNXT_ULP_CLASS_HID_2ad6b = 0x2ad6b, + BNXT_ULP_CLASS_HID_2b9e3 = 0x2b9e3, + BNXT_ULP_CLASS_HID_283bb = 0x283bb, + BNXT_ULP_CLASS_HID_29033 = 0x29033, + BNXT_ULP_CLASS_HID_289f7 = 0x289f7, + BNXT_ULP_CLASS_HID_2960f = 0x2960f, + BNXT_ULP_CLASS_HID_2ca83 = 0x2ca83, + BNXT_ULP_CLASS_HID_2d71b = 0x2d71b, + BNXT_ULP_CLASS_HID_2d0df = 0x2d0df, + BNXT_ULP_CLASS_HID_280ab = 0x280ab, + BNXT_ULP_CLASS_HID_6cb17 = 0x6cb17, + BNXT_ULP_CLASS_HID_6d7af = 0x6d7af, + BNXT_ULP_CLASS_HID_6d153 = 0x6d153, + BNXT_ULP_CLASS_HID_6813f = 0x6813f, + BNXT_ULP_CLASS_HID_6b5b3 = 0x6b5b3, + BNXT_ULP_CLASS_HID_6c1cb = 0x6c1cb, + BNXT_ULP_CLASS_HID_6bb8f = 0x6bb8f, + BNXT_ULP_CLASS_HID_6c807 = 0x6c807, + BNXT_ULP_CLASS_HID_691df = 0x691df, + BNXT_ULP_CLASS_HID_69e57 = 0x69e57, + BNXT_ULP_CLASS_HID_6981b = 0x6981b, + BNXT_ULP_CLASS_HID_6a493 = 0x6a493, + BNXT_ULP_CLASS_HID_6d927 = 0x6d927, + BNXT_ULP_CLASS_HID_688f3 = 0x688f3, + BNXT_ULP_CLASS_HID_682b7 = 0x682b7, + BNXT_ULP_CLASS_HID_68ecf = 0x68ecf, + BNXT_ULP_CLASS_HID_6b7c7 = 0x6b7c7, + BNXT_ULP_CLASS_HID_6c45f = 0x6c45f, + BNXT_ULP_CLASS_HID_6be03 = 0x6be03, + BNXT_ULP_CLASS_HID_6ca9b = 0x6ca9b, + BNXT_ULP_CLASS_HID_6a263 = 0x6a263, + BNXT_ULP_CLASS_HID_6aefb = 0x6aefb, + BNXT_ULP_CLASS_HID_6a8bf = 0x6a8bf, + BNXT_ULP_CLASS_HID_6b537 = 0x6b537, + BNXT_ULP_CLASS_HID_6dbbb = 0x6dbbb, + BNXT_ULP_CLASS_HID_68b07 = 0x68b07, + BNXT_ULP_CLASS_HID_684cb = 0x684cb, + BNXT_ULP_CLASS_HID_69143 = 0x69143, + BNXT_ULP_CLASS_HID_6c5d7 = 0x6c5d7, + BNXT_ULP_CLASS_HID_6d26f = 0x6d26f, + BNXT_ULP_CLASS_HID_6cc13 = 0x6cc13, + BNXT_ULP_CLASS_HID_6d8ab = 0x6d8ab, + BNXT_ULP_CLASS_HID_38917 = 0x38917, + BNXT_ULP_CLASS_HID_395af = 0x395af, + BNXT_ULP_CLASS_HID_38f53 = 0x38f53, + BNXT_ULP_CLASS_HID_39beb = 0x39beb, + BNXT_ULP_CLASS_HID_3d07f = 0x3d07f, + BNXT_ULP_CLASS_HID_3dcf7 = 0x3dcf7, + BNXT_ULP_CLASS_HID_3d6bb = 0x3d6bb, + BNXT_ULP_CLASS_HID_38607 = 0x38607, + BNXT_ULP_CLASS_HID_3ac8b = 0x3ac8b, + BNXT_ULP_CLASS_HID_3b903 = 0x3b903, + BNXT_ULP_CLASS_HID_3b2c7 = 0x3b2c7, + BNXT_ULP_CLASS_HID_3bf5f = 0x3bf5f, + BNXT_ULP_CLASS_HID_39727 = 0x39727, + BNXT_ULP_CLASS_HID_3a3bf = 0x3a3bf, + BNXT_ULP_CLASS_HID_39d63 = 0x39d63, + BNXT_ULP_CLASS_HID_3a9fb = 0x3a9fb, + BNXT_ULP_CLASS_HID_3d2f3 = 0x3d2f3, + BNXT_ULP_CLASS_HID_3825f = 0x3825f, + BNXT_ULP_CLASS_HID_3d8cf = 0x3d8cf, + BNXT_ULP_CLASS_HID_3889b = 0x3889b, + BNXT_ULP_CLASS_HID_3bd2f = 0x3bd2f, + BNXT_ULP_CLASS_HID_3c9a7 = 0x3c9a7, + BNXT_ULP_CLASS_HID_3c36b = 0x3c36b, + BNXT_ULP_CLASS_HID_3cfe3 = 0x3cfe3, + BNXT_ULP_CLASS_HID_399bb = 0x399bb, + BNXT_ULP_CLASS_HID_3a633 = 0x3a633, + BNXT_ULP_CLASS_HID_39ff7 = 0x39ff7, + BNXT_ULP_CLASS_HID_3ac0f = 0x3ac0f, + BNXT_ULP_CLASS_HID_383d7 = 0x383d7, + BNXT_ULP_CLASS_HID_3906f = 0x3906f, + BNXT_ULP_CLASS_HID_38a13 = 0x38a13, + BNXT_ULP_CLASS_HID_396ab = 0x396ab, + BNXT_ULP_CLASS_HID_7846b = 0x7846b, + BNXT_ULP_CLASS_HID_790e3 = 0x790e3, + BNXT_ULP_CLASS_HID_78aa7 = 0x78aa7, + BNXT_ULP_CLASS_HID_7973f = 0x7973f, + BNXT_ULP_CLASS_HID_7cbb3 = 0x7cbb3, + BNXT_ULP_CLASS_HID_7d7cb = 0x7d7cb, + BNXT_ULP_CLASS_HID_7d18f = 0x7d18f, + BNXT_ULP_CLASS_HID_7815b = 0x7815b, + BNXT_ULP_CLASS_HID_7a7df = 0x7a7df, + BNXT_ULP_CLASS_HID_7b457 = 0x7b457, + BNXT_ULP_CLASS_HID_7ae1b = 0x7ae1b, + BNXT_ULP_CLASS_HID_7ba93 = 0x7ba93, + BNXT_ULP_CLASS_HID_7927b = 0x7927b, + BNXT_ULP_CLASS_HID_79ef3 = 0x79ef3, + BNXT_ULP_CLASS_HID_798b7 = 0x798b7, + BNXT_ULP_CLASS_HID_7a4cf = 0x7a4cf, + BNXT_ULP_CLASS_HID_7cdc7 = 0x7cdc7, + BNXT_ULP_CLASS_HID_7da5f = 0x7da5f, + BNXT_ULP_CLASS_HID_7d403 = 0x7d403, + BNXT_ULP_CLASS_HID_783ef = 0x783ef, + BNXT_ULP_CLASS_HID_7b863 = 0x7b863, + BNXT_ULP_CLASS_HID_7c4fb = 0x7c4fb, + BNXT_ULP_CLASS_HID_7bebf = 0x7bebf, + BNXT_ULP_CLASS_HID_7cb37 = 0x7cb37, + BNXT_ULP_CLASS_HID_7948f = 0x7948f, + BNXT_ULP_CLASS_HID_7a107 = 0x7a107, + BNXT_ULP_CLASS_HID_79acb = 0x79acb, + BNXT_ULP_CLASS_HID_7a743 = 0x7a743, + BNXT_ULP_CLASS_HID_7dbd7 = 0x7dbd7, + BNXT_ULP_CLASS_HID_78ba3 = 0x78ba3, + BNXT_ULP_CLASS_HID_78567 = 0x78567, + BNXT_ULP_CLASS_HID_791ff = 0x791ff, + BNXT_ULP_CLASS_HID_a3db = 0xa3db, + BNXT_ULP_CLASS_HID_b043 = 0xb043, + BNXT_ULP_CLASS_HID_aa07 = 0xaa07, BNXT_ULP_CLASS_HID_b68f = 0xb68f, - BNXT_ULP_CLASS_HID_b94f = 0xb94f, - BNXT_ULP_CLASS_HID_fc0f = 0xfc0f, - BNXT_ULP_CLASS_HID_fecf = 0xfecf, - BNXT_ULP_CLASS_HID_b1f3 = 0xb1f3, - BNXT_ULP_CLASS_HID_b4b3 = 0xb4b3, - BNXT_ULP_CLASS_HID_f773 = 0xf773, - BNXT_ULP_CLASS_HID_fa33 = 0xfa33, - BNXT_ULP_CLASS_HID_1c7f3 = 0x1c7f3, - BNXT_ULP_CLASS_HID_1eab3 = 0x1eab3, - BNXT_ULP_CLASS_HID_1cd73 = 0x1cd73, - BNXT_ULP_CLASS_HID_1f033 = 0x1f033, - BNXT_ULP_CLASS_HID_1cc8f = 0x1cc8f, - BNXT_ULP_CLASS_HID_1ef4f = 0x1ef4f, - BNXT_ULP_CLASS_HID_1d20f = 0x1d20f, - BNXT_ULP_CLASS_HID_1f4cf = 0x1f4cf, - BNXT_ULP_CLASS_HID_da13 = 0xda13, - BNXT_ULP_CLASS_HID_a007 = 0xa007, - BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7, - BNXT_ULP_CLASS_HID_e587 = 0xe587, - BNXT_ULP_CLASS_HID_d547 = 0xd547, - BNXT_ULP_CLASS_HID_f807 = 0xf807, - BNXT_ULP_CLASS_HID_dac7 = 0xdac7, - BNXT_ULP_CLASS_HID_e0cb = 0xe0cb, - BNXT_ULP_CLASS_HID_18e8b = 0x18e8b, - BNXT_ULP_CLASS_HID_1b14b = 0x1b14b, - BNXT_ULP_CLASS_HID_1d40b = 0x1d40b, - BNXT_ULP_CLASS_HID_1f6cb = 0x1f6cb, - BNXT_ULP_CLASS_HID_19347 = 0x19347, - BNXT_ULP_CLASS_HID_1b607 = 0x1b607, - BNXT_ULP_CLASS_HID_1d8c7 = 0x1d8c7, - BNXT_ULP_CLASS_HID_1fb87 = 0x1fb87, + BNXT_ULP_CLASS_HID_8e67 = 0x8e67, + BNXT_ULP_CLASS_HID_9aef = 0x9aef, + BNXT_ULP_CLASS_HID_94a3 = 0x94a3, BNXT_ULP_CLASS_HID_a12b = 0xa12b, - BNXT_ULP_CLASS_HID_a3eb = 0xa3eb, - BNXT_ULP_CLASS_HID_e6ab = 0xe6ab, - BNXT_ULP_CLASS_HID_e96b = 0xe96b, - BNXT_ULP_CLASS_HID_9c1f = 0x9c1f, - BNXT_ULP_CLASS_HID_bedf = 0xbedf, - BNXT_ULP_CLASS_HID_e19f = 0xe19f, - BNXT_ULP_CLASS_HID_e45f = 0xe45f, - BNXT_ULP_CLASS_HID_1b21f = 0x1b21f, - BNXT_ULP_CLASS_HID_1b4df = 0x1b4df, - BNXT_ULP_CLASS_HID_1f79f = 0x1f79f, - BNXT_ULP_CLASS_HID_1fa5f = 0x1fa5f, - BNXT_ULP_CLASS_HID_1b72b = 0x1b72b, - BNXT_ULP_CLASS_HID_1b9eb = 0x1b9eb, - BNXT_ULP_CLASS_HID_1fcab = 0x1fcab, - BNXT_ULP_CLASS_HID_1ff6b = 0x1ff6b, + BNXT_ULP_CLASS_HID_c7af = 0xc7af, + BNXT_ULP_CLASS_HID_d3d7 = 0xd3d7, + BNXT_ULP_CLASS_HID_cdeb = 0xcdeb, + BNXT_ULP_CLASS_HID_da13 = 0xda13, + BNXT_ULP_CLASS_HID_b1cb = 0xb1cb, + BNXT_ULP_CLASS_HID_be73 = 0xbe73, + BNXT_ULP_CLASS_HID_b837 = 0xb837, BNXT_ULP_CLASS_HID_c4bf = 0xc4bf, - BNXT_ULP_CLASS_HID_e77f = 0xe77f, - BNXT_ULP_CLASS_HID_ca3f = 0xca3f, - BNXT_ULP_CLASS_HID_ecff = 0xecff, - BNXT_ULP_CLASS_HID_bfe3 = 0xbfe3, - BNXT_ULP_CLASS_HID_e2a3 = 0xe2a3, - BNXT_ULP_CLASS_HID_c563 = 0xc563, - BNXT_ULP_CLASS_HID_e823 = 0xe823, - BNXT_ULP_CLASS_HID_1d5e3 = 0x1d5e3, - BNXT_ULP_CLASS_HID_1f8a3 = 0x1f8a3, - BNXT_ULP_CLASS_HID_1db63 = 0x1db63, - BNXT_ULP_CLASS_HID_1e117 = 0x1e117, - BNXT_ULP_CLASS_HID_1dabf = 0x1dabf, - BNXT_ULP_CLASS_HID_1a0a3 = 0x1a0a3, - BNXT_ULP_CLASS_HID_1c363 = 0x1c363, - BNXT_ULP_CLASS_HID_1e623 = 0x1e623, - BNXT_ULP_CLASS_HID_b043 = 0xb043, - BNXT_ULP_CLASS_HID_b303 = 0xb303, - BNXT_ULP_CLASS_HID_f5c3 = 0xf5c3, - BNXT_ULP_CLASS_HID_f883 = 0xf883, - BNXT_ULP_CLASS_HID_abb7 = 0xabb7, - BNXT_ULP_CLASS_HID_ae77 = 0xae77, - BNXT_ULP_CLASS_HID_f137 = 0xf137, - BNXT_ULP_CLASS_HID_f3f7 = 0xf3f7, - BNXT_ULP_CLASS_HID_1c1b7 = 0x1c1b7, - BNXT_ULP_CLASS_HID_1e477 = 0x1e477, - BNXT_ULP_CLASS_HID_1c737 = 0x1c737, - BNXT_ULP_CLASS_HID_1e9f7 = 0x1e9f7, + BNXT_ULP_CLASS_HID_49f0f = 0x49f0f, + BNXT_ULP_CLASS_HID_4abb7 = 0x4abb7, + BNXT_ULP_CLASS_HID_4a54b = 0x4a54b, + BNXT_ULP_CLASS_HID_4b1f3 = 0x4b1f3, + BNXT_ULP_CLASS_HID_489ab = 0x489ab, + BNXT_ULP_CLASS_HID_495d3 = 0x495d3, + BNXT_ULP_CLASS_HID_48f97 = 0x48f97, + BNXT_ULP_CLASS_HID_49c1f = 0x49c1f, + BNXT_ULP_CLASS_HID_4c293 = 0x4c293, + BNXT_ULP_CLASS_HID_4cf1b = 0x4cf1b, + BNXT_ULP_CLASS_HID_4c8df = 0x4c8df, + BNXT_ULP_CLASS_HID_4d547 = 0x4d547, + BNXT_ULP_CLASS_HID_4ad3f = 0x4ad3f, + BNXT_ULP_CLASS_HID_4b9a7 = 0x4b9a7, + BNXT_ULP_CLASS_HID_4b37b = 0x4b37b, + BNXT_ULP_CLASS_HID_4bfe3 = 0x4bfe3, + BNXT_ULP_CLASS_HID_1b9db = 0x1b9db, BNXT_ULP_CLASS_HID_1c643 = 0x1c643, - BNXT_ULP_CLASS_HID_1e903 = 0x1e903, - BNXT_ULP_CLASS_HID_1cbc3 = 0x1cbc3, - BNXT_ULP_CLASS_HID_1ee83 = 0x1ee83, - BNXT_ULP_CLASS_HID_d3d7 = 0xd3d7, - BNXT_ULP_CLASS_HID_f697 = 0xf697, - BNXT_ULP_CLASS_HID_d957 = 0xd957, - BNXT_ULP_CLASS_HID_fc17 = 0xfc17, - BNXT_ULP_CLASS_HID_cf1b = 0xcf1b, - BNXT_ULP_CLASS_HID_f1db = 0xf1db, - BNXT_ULP_CLASS_HID_d49b = 0xd49b, - BNXT_ULP_CLASS_HID_f75b = 0xf75b, - BNXT_ULP_CLASS_HID_1884f = 0x1884f, - BNXT_ULP_CLASS_HID_1ab0f = 0x1ab0f, - BNXT_ULP_CLASS_HID_1cdcf = 0x1cdcf, - BNXT_ULP_CLASS_HID_1f08f = 0x1f08f, - BNXT_ULP_CLASS_HID_18d1b = 0x18d1b, - BNXT_ULP_CLASS_HID_1afdb = 0x1afdb, - BNXT_ULP_CLASS_HID_1d29b = 0x1d29b, - BNXT_ULP_CLASS_HID_1f55b = 0x1f55b, - BNXT_ULP_CLASS_HID_9aef = 0x9aef, - BNXT_ULP_CLASS_HID_bdaf = 0xbdaf, - BNXT_ULP_CLASS_HID_e06f = 0xe06f, - BNXT_ULP_CLASS_HID_e32f = 0xe32f, - BNXT_ULP_CLASS_HID_95d3 = 0x95d3, - BNXT_ULP_CLASS_HID_b893 = 0xb893, - BNXT_ULP_CLASS_HID_db53 = 0xdb53, - BNXT_ULP_CLASS_HID_fe13 = 0xfe13, - BNXT_ULP_CLASS_HID_1abd3 = 0x1abd3, - BNXT_ULP_CLASS_HID_1ae93 = 0x1ae93, - BNXT_ULP_CLASS_HID_1f153 = 0x1f153, - BNXT_ULP_CLASS_HID_1f413 = 0x1f413, + BNXT_ULP_CLASS_HID_1c007 = 0x1c007, + BNXT_ULP_CLASS_HID_1cc8f = 0x1cc8f, + BNXT_ULP_CLASS_HID_1a467 = 0x1a467, BNXT_ULP_CLASS_HID_1b0ef = 0x1b0ef, - BNXT_ULP_CLASS_HID_1b3af = 0x1b3af, - BNXT_ULP_CLASS_HID_1f66f = 0x1f66f, - BNXT_ULP_CLASS_HID_1f92f = 0x1f92f, - BNXT_ULP_CLASS_HID_be73 = 0xbe73, - BNXT_ULP_CLASS_HID_e133 = 0xe133, - BNXT_ULP_CLASS_HID_c3f3 = 0xc3f3, - BNXT_ULP_CLASS_HID_e6b3 = 0xe6b3, - BNXT_ULP_CLASS_HID_b9a7 = 0xb9a7, - BNXT_ULP_CLASS_HID_bc67 = 0xbc67, - BNXT_ULP_CLASS_HID_ff27 = 0xff27, - BNXT_ULP_CLASS_HID_e1e7 = 0xe1e7, - BNXT_ULP_CLASS_HID_1cfa7 = 0x1cfa7, - BNXT_ULP_CLASS_HID_1f267 = 0x1f267, - BNXT_ULP_CLASS_HID_1d527 = 0x1d527, - BNXT_ULP_CLASS_HID_1f7e7 = 0x1f7e7, + BNXT_ULP_CLASS_HID_1aaa3 = 0x1aaa3, + BNXT_ULP_CLASS_HID_1b72b = 0x1b72b, + BNXT_ULP_CLASS_HID_18093 = 0x18093, + BNXT_ULP_CLASS_HID_18d1b = 0x18d1b, + BNXT_ULP_CLASS_HID_186df = 0x186df, + BNXT_ULP_CLASS_HID_19347 = 0x19347, + BNXT_ULP_CLASS_HID_1c7cb = 0x1c7cb, BNXT_ULP_CLASS_HID_1d473 = 0x1d473, - BNXT_ULP_CLASS_HID_1f733 = 0x1f733, - BNXT_ULP_CLASS_HID_1d9f3 = 0x1d9f3, - BNXT_ULP_CLASS_HID_1fcb3 = 0x1fcb3, - BNXT_ULP_CLASS_HID_aa07 = 0xaa07, - BNXT_ULP_CLASS_HID_acc7 = 0xacc7, + BNXT_ULP_CLASS_HID_1ce37 = 0x1ce37, + BNXT_ULP_CLASS_HID_1dabf = 0x1dabf, + BNXT_ULP_CLASS_HID_5b50f = 0x5b50f, + BNXT_ULP_CLASS_HID_5c1b7 = 0x5c1b7, + BNXT_ULP_CLASS_HID_5bb4b = 0x5bb4b, + BNXT_ULP_CLASS_HID_5c7f3 = 0x5c7f3, + BNXT_ULP_CLASS_HID_59fab = 0x59fab, + BNXT_ULP_CLASS_HID_5abd3 = 0x5abd3, + BNXT_ULP_CLASS_HID_5a597 = 0x5a597, + BNXT_ULP_CLASS_HID_5b21f = 0x5b21f, + BNXT_ULP_CLASS_HID_5d893 = 0x5d893, + BNXT_ULP_CLASS_HID_5884f = 0x5884f, + BNXT_ULP_CLASS_HID_58203 = 0x58203, + BNXT_ULP_CLASS_HID_58e8b = 0x58e8b, + BNXT_ULP_CLASS_HID_5c33f = 0x5c33f, + BNXT_ULP_CLASS_HID_5cfa7 = 0x5cfa7, + BNXT_ULP_CLASS_HID_5c97b = 0x5c97b, + BNXT_ULP_CLASS_HID_5d5e3 = 0x5d5e3, + BNXT_ULP_CLASS_HID_e95b = 0xe95b, + BNXT_ULP_CLASS_HID_f5c3 = 0xf5c3, BNXT_ULP_CLASS_HID_ef87 = 0xef87, - BNXT_ULP_CLASS_HID_f247 = 0xf247, - BNXT_ULP_CLASS_HID_a54b = 0xa54b, - BNXT_ULP_CLASS_HID_a80b = 0xa80b, - BNXT_ULP_CLASS_HID_eacb = 0xeacb, - BNXT_ULP_CLASS_HID_ed8b = 0xed8b, - BNXT_ULP_CLASS_HID_1bb4b = 0x1bb4b, - BNXT_ULP_CLASS_HID_1be0b = 0x1be0b, - BNXT_ULP_CLASS_HID_1c0cb = 0x1c0cb, - BNXT_ULP_CLASS_HID_1e38b = 0x1e38b, - BNXT_ULP_CLASS_HID_1c007 = 0x1c007, - BNXT_ULP_CLASS_HID_1e2c7 = 0x1e2c7, - BNXT_ULP_CLASS_HID_1c587 = 0x1c587, - BNXT_ULP_CLASS_HID_1e847 = 0x1e847, - BNXT_ULP_CLASS_HID_cdeb = 0xcdeb, - BNXT_ULP_CLASS_HID_f0ab = 0xf0ab, - BNXT_ULP_CLASS_HID_d36b = 0xd36b, - BNXT_ULP_CLASS_HID_f62b = 0xf62b, - BNXT_ULP_CLASS_HID_c8df = 0xc8df, - BNXT_ULP_CLASS_HID_eb9f = 0xeb9f, - BNXT_ULP_CLASS_HID_ce5f = 0xce5f, - BNXT_ULP_CLASS_HID_f11f = 0xf11f, - BNXT_ULP_CLASS_HID_18203 = 0x18203, - BNXT_ULP_CLASS_HID_1a4c3 = 0x1a4c3, - BNXT_ULP_CLASS_HID_1c783 = 0x1c783, - BNXT_ULP_CLASS_HID_1ea43 = 0x1ea43, - BNXT_ULP_CLASS_HID_186df = 0x186df, - BNXT_ULP_CLASS_HID_1a99f = 0x1a99f, - BNXT_ULP_CLASS_HID_1cc5f = 0x1cc5f, - BNXT_ULP_CLASS_HID_1ef1f = 0x1ef1f, - BNXT_ULP_CLASS_HID_94a3 = 0x94a3, - BNXT_ULP_CLASS_HID_b763 = 0xb763, + BNXT_ULP_CLASS_HID_fc0f = 0xfc0f, + BNXT_ULP_CLASS_HID_d3e7 = 0xd3e7, + BNXT_ULP_CLASS_HID_e06f = 0xe06f, BNXT_ULP_CLASS_HID_da23 = 0xda23, - BNXT_ULP_CLASS_HID_fce3 = 0xfce3, - BNXT_ULP_CLASS_HID_8f97 = 0x8f97, - BNXT_ULP_CLASS_HID_b257 = 0xb257, - BNXT_ULP_CLASS_HID_d517 = 0xd517, - BNXT_ULP_CLASS_HID_f7d7 = 0xf7d7, - BNXT_ULP_CLASS_HID_1a597 = 0x1a597, - BNXT_ULP_CLASS_HID_1a857 = 0x1a857, - BNXT_ULP_CLASS_HID_1eb17 = 0x1eb17, - BNXT_ULP_CLASS_HID_1edd7 = 0x1edd7, - BNXT_ULP_CLASS_HID_1aaa3 = 0x1aaa3, - BNXT_ULP_CLASS_HID_1ad63 = 0x1ad63, - BNXT_ULP_CLASS_HID_1f023 = 0x1f023, - BNXT_ULP_CLASS_HID_1f2e3 = 0x1f2e3, - BNXT_ULP_CLASS_HID_b837 = 0xb837, - BNXT_ULP_CLASS_HID_baf7 = 0xbaf7, + BNXT_ULP_CLASS_HID_e6ab = 0xe6ab, + BNXT_ULP_CLASS_HID_cd2f = 0xcd2f, + BNXT_ULP_CLASS_HID_d957 = 0xd957, + BNXT_ULP_CLASS_HID_d36b = 0xd36b, + BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7, + BNXT_ULP_CLASS_HID_f74b = 0xf74b, + BNXT_ULP_CLASS_HID_c3f3 = 0xc3f3, BNXT_ULP_CLASS_HID_fdb7 = 0xfdb7, - BNXT_ULP_CLASS_HID_e077 = 0xe077, - BNXT_ULP_CLASS_HID_b37b = 0xb37b, - BNXT_ULP_CLASS_HID_b63b = 0xb63b, - BNXT_ULP_CLASS_HID_f8fb = 0xf8fb, - BNXT_ULP_CLASS_HID_fbbb = 0xfbbb, - BNXT_ULP_CLASS_HID_1c97b = 0x1c97b, - BNXT_ULP_CLASS_HID_1ec3b = 0x1ec3b, - BNXT_ULP_CLASS_HID_1cefb = 0x1cefb, - BNXT_ULP_CLASS_HID_1f1bb = 0x1f1bb, - BNXT_ULP_CLASS_HID_1ce37 = 0x1ce37, - BNXT_ULP_CLASS_HID_1f0f7 = 0x1f0f7, + BNXT_ULP_CLASS_HID_ca3f = 0xca3f, + BNXT_ULP_CLASS_HID_4e48f = 0x4e48f, + BNXT_ULP_CLASS_HID_4f137 = 0x4f137, + BNXT_ULP_CLASS_HID_4eacb = 0x4eacb, + BNXT_ULP_CLASS_HID_4f773 = 0x4f773, + BNXT_ULP_CLASS_HID_4cf2b = 0x4cf2b, + BNXT_ULP_CLASS_HID_4db53 = 0x4db53, + BNXT_ULP_CLASS_HID_4d517 = 0x4d517, + BNXT_ULP_CLASS_HID_4e19f = 0x4e19f, + BNXT_ULP_CLASS_HID_4c813 = 0x4c813, + BNXT_ULP_CLASS_HID_4d49b = 0x4d49b, + BNXT_ULP_CLASS_HID_4ce5f = 0x4ce5f, + BNXT_ULP_CLASS_HID_4dac7 = 0x4dac7, + BNXT_ULP_CLASS_HID_4f2bf = 0x4f2bf, + BNXT_ULP_CLASS_HID_4ff27 = 0x4ff27, + BNXT_ULP_CLASS_HID_4f8fb = 0x4f8fb, + BNXT_ULP_CLASS_HID_4c563 = 0x4c563, + BNXT_ULP_CLASS_HID_1ff5b = 0x1ff5b, + BNXT_ULP_CLASS_HID_1cbc3 = 0x1cbc3, + BNXT_ULP_CLASS_HID_1c587 = 0x1c587, + BNXT_ULP_CLASS_HID_1d20f = 0x1d20f, + BNXT_ULP_CLASS_HID_1e9e7 = 0x1e9e7, + BNXT_ULP_CLASS_HID_1f66f = 0x1f66f, + BNXT_ULP_CLASS_HID_1f023 = 0x1f023, + BNXT_ULP_CLASS_HID_1fcab = 0x1fcab, + BNXT_ULP_CLASS_HID_1c613 = 0x1c613, + BNXT_ULP_CLASS_HID_1d29b = 0x1d29b, + BNXT_ULP_CLASS_HID_1cc5f = 0x1cc5f, + BNXT_ULP_CLASS_HID_1d8c7 = 0x1d8c7, + BNXT_ULP_CLASS_HID_1cd4b = 0x1cd4b, + BNXT_ULP_CLASS_HID_1d9f3 = 0x1d9f3, BNXT_ULP_CLASS_HID_1d3b7 = 0x1d3b7, - BNXT_ULP_CLASS_HID_1f677 = 0x1f677, - BNXT_ULP_CLASS_HID_a3db = 0xa3db, + BNXT_ULP_CLASS_HID_1c363 = 0x1c363, + BNXT_ULP_CLASS_HID_5fa8f = 0x5fa8f, + BNXT_ULP_CLASS_HID_5c737 = 0x5c737, + BNXT_ULP_CLASS_HID_5c0cb = 0x5c0cb, + BNXT_ULP_CLASS_HID_5cd73 = 0x5cd73, + BNXT_ULP_CLASS_HID_5e52b = 0x5e52b, + BNXT_ULP_CLASS_HID_5f153 = 0x5f153, + BNXT_ULP_CLASS_HID_5eb17 = 0x5eb17, + BNXT_ULP_CLASS_HID_5f79f = 0x5f79f, + BNXT_ULP_CLASS_HID_5c147 = 0x5c147, + BNXT_ULP_CLASS_HID_5cdcf = 0x5cdcf, + BNXT_ULP_CLASS_HID_5c783 = 0x5c783, + BNXT_ULP_CLASS_HID_5d40b = 0x5d40b, + BNXT_ULP_CLASS_HID_5c8bf = 0x5c8bf, + BNXT_ULP_CLASS_HID_5d527 = 0x5d527, + BNXT_ULP_CLASS_HID_5cefb = 0x5cefb, + BNXT_ULP_CLASS_HID_5db63 = 0x5db63, BNXT_ULP_CLASS_HID_a69b = 0xa69b, - BNXT_ULP_CLASS_HID_e95b = 0xe95b, - BNXT_ULP_CLASS_HID_ec1b = 0xec1b, - BNXT_ULP_CLASS_HID_9f0f = 0x9f0f, - BNXT_ULP_CLASS_HID_a1cf = 0xa1cf, - BNXT_ULP_CLASS_HID_e48f = 0xe48f, - BNXT_ULP_CLASS_HID_e74f = 0xe74f, - BNXT_ULP_CLASS_HID_1b50f = 0x1b50f, - BNXT_ULP_CLASS_HID_1b7cf = 0x1b7cf, - BNXT_ULP_CLASS_HID_1fa8f = 0x1fa8f, - BNXT_ULP_CLASS_HID_1fd4f = 0x1fd4f, - BNXT_ULP_CLASS_HID_1b9db = 0x1b9db, - BNXT_ULP_CLASS_HID_1bc9b = 0x1bc9b, - BNXT_ULP_CLASS_HID_1ff5b = 0x1ff5b, - BNXT_ULP_CLASS_HID_1e21b = 0x1e21b, - BNXT_ULP_CLASS_HID_c7af = 0xc7af, + BNXT_ULP_CLASS_HID_b303 = 0xb303, + BNXT_ULP_CLASS_HID_acc7 = 0xacc7, + BNXT_ULP_CLASS_HID_b94f = 0xb94f, + BNXT_ULP_CLASS_HID_b127 = 0xb127, + BNXT_ULP_CLASS_HID_bdaf = 0xbdaf, + BNXT_ULP_CLASS_HID_b763 = 0xb763, + BNXT_ULP_CLASS_HID_a3eb = 0xa3eb, BNXT_ULP_CLASS_HID_ea6f = 0xea6f, - BNXT_ULP_CLASS_HID_cd2f = 0xcd2f, - BNXT_ULP_CLASS_HID_efef = 0xefef, - BNXT_ULP_CLASS_HID_c293 = 0xc293, - BNXT_ULP_CLASS_HID_e553 = 0xe553, - BNXT_ULP_CLASS_HID_c813 = 0xc813, - BNXT_ULP_CLASS_HID_ead3 = 0xead3, - BNXT_ULP_CLASS_HID_1d893 = 0x1d893, - BNXT_ULP_CLASS_HID_1fb53 = 0x1fb53, - BNXT_ULP_CLASS_HID_1c147 = 0x1c147, - BNXT_ULP_CLASS_HID_1e407 = 0x1e407, - BNXT_ULP_CLASS_HID_18093 = 0x18093, + BNXT_ULP_CLASS_HID_f697 = 0xf697, + BNXT_ULP_CLASS_HID_f0ab = 0xf0ab, + BNXT_ULP_CLASS_HID_a007 = 0xa007, + BNXT_ULP_CLASS_HID_b48b = 0xb48b, + BNXT_ULP_CLASS_HID_e133 = 0xe133, + BNXT_ULP_CLASS_HID_baf7 = 0xbaf7, + BNXT_ULP_CLASS_HID_e77f = 0xe77f, + BNXT_ULP_CLASS_HID_4a1cf = 0x4a1cf, + BNXT_ULP_CLASS_HID_4ae77 = 0x4ae77, + BNXT_ULP_CLASS_HID_4a80b = 0x4a80b, + BNXT_ULP_CLASS_HID_4b4b3 = 0x4b4b3, + BNXT_ULP_CLASS_HID_4ac6b = 0x4ac6b, + BNXT_ULP_CLASS_HID_4b893 = 0x4b893, + BNXT_ULP_CLASS_HID_4b257 = 0x4b257, + BNXT_ULP_CLASS_HID_4bedf = 0x4bedf, + BNXT_ULP_CLASS_HID_4e553 = 0x4e553, + BNXT_ULP_CLASS_HID_4f1db = 0x4f1db, + BNXT_ULP_CLASS_HID_4eb9f = 0x4eb9f, + BNXT_ULP_CLASS_HID_4f807 = 0x4f807, + BNXT_ULP_CLASS_HID_4afff = 0x4afff, + BNXT_ULP_CLASS_HID_4bc67 = 0x4bc67, + BNXT_ULP_CLASS_HID_4b63b = 0x4b63b, + BNXT_ULP_CLASS_HID_4e2a3 = 0x4e2a3, + BNXT_ULP_CLASS_HID_1bc9b = 0x1bc9b, + BNXT_ULP_CLASS_HID_1e903 = 0x1e903, + BNXT_ULP_CLASS_HID_1e2c7 = 0x1e2c7, + BNXT_ULP_CLASS_HID_1ef4f = 0x1ef4f, + BNXT_ULP_CLASS_HID_1a727 = 0x1a727, + BNXT_ULP_CLASS_HID_1b3af = 0x1b3af, + BNXT_ULP_CLASS_HID_1ad63 = 0x1ad63, + BNXT_ULP_CLASS_HID_1b9eb = 0x1b9eb, BNXT_ULP_CLASS_HID_1a353 = 0x1a353, - BNXT_ULP_CLASS_HID_1c613 = 0x1c613, - BNXT_ULP_CLASS_HID_1e8d3 = 0x1e8d3, - BNXT_ULP_CLASS_HID_8e67 = 0x8e67, - BNXT_ULP_CLASS_HID_b127 = 0xb127, - BNXT_ULP_CLASS_HID_d3e7 = 0xd3e7, + BNXT_ULP_CLASS_HID_1afdb = 0x1afdb, + BNXT_ULP_CLASS_HID_1a99f = 0x1a99f, + BNXT_ULP_CLASS_HID_1b607 = 0x1b607, + BNXT_ULP_CLASS_HID_1ea8b = 0x1ea8b, + BNXT_ULP_CLASS_HID_1f733 = 0x1f733, + BNXT_ULP_CLASS_HID_1f0f7 = 0x1f0f7, + BNXT_ULP_CLASS_HID_1a0a3 = 0x1a0a3, + BNXT_ULP_CLASS_HID_5b7cf = 0x5b7cf, + BNXT_ULP_CLASS_HID_5e477 = 0x5e477, + BNXT_ULP_CLASS_HID_5be0b = 0x5be0b, + BNXT_ULP_CLASS_HID_5eab3 = 0x5eab3, + BNXT_ULP_CLASS_HID_5a26b = 0x5a26b, + BNXT_ULP_CLASS_HID_5ae93 = 0x5ae93, + BNXT_ULP_CLASS_HID_5a857 = 0x5a857, + BNXT_ULP_CLASS_HID_5b4df = 0x5b4df, + BNXT_ULP_CLASS_HID_5fb53 = 0x5fb53, + BNXT_ULP_CLASS_HID_5ab0f = 0x5ab0f, + BNXT_ULP_CLASS_HID_5a4c3 = 0x5a4c3, + BNXT_ULP_CLASS_HID_5b14b = 0x5b14b, + BNXT_ULP_CLASS_HID_5e5ff = 0x5e5ff, + BNXT_ULP_CLASS_HID_5f267 = 0x5f267, + BNXT_ULP_CLASS_HID_5ec3b = 0x5ec3b, + BNXT_ULP_CLASS_HID_5f8a3 = 0x5f8a3, + BNXT_ULP_CLASS_HID_ec1b = 0xec1b, + BNXT_ULP_CLASS_HID_f883 = 0xf883, + BNXT_ULP_CLASS_HID_f247 = 0xf247, + BNXT_ULP_CLASS_HID_fecf = 0xfecf, BNXT_ULP_CLASS_HID_f6a7 = 0xf6a7, - BNXT_ULP_CLASS_HID_89ab = 0x89ab, - BNXT_ULP_CLASS_HID_ac6b = 0xac6b, - BNXT_ULP_CLASS_HID_cf2b = 0xcf2b, - BNXT_ULP_CLASS_HID_f1eb = 0xf1eb, - BNXT_ULP_CLASS_HID_19fab = 0x19fab, - BNXT_ULP_CLASS_HID_1a26b = 0x1a26b, - BNXT_ULP_CLASS_HID_1e52b = 0x1e52b, - BNXT_ULP_CLASS_HID_1e7eb = 0x1e7eb, - BNXT_ULP_CLASS_HID_1a467 = 0x1a467, - BNXT_ULP_CLASS_HID_1a727 = 0x1a727, - BNXT_ULP_CLASS_HID_1e9e7 = 0x1e9e7, - BNXT_ULP_CLASS_HID_1eca7 = 0x1eca7, - BNXT_ULP_CLASS_HID_b1cb = 0xb1cb, - BNXT_ULP_CLASS_HID_b48b = 0xb48b, - BNXT_ULP_CLASS_HID_f74b = 0xf74b, + BNXT_ULP_CLASS_HID_e32f = 0xe32f, + BNXT_ULP_CLASS_HID_fce3 = 0xfce3, + BNXT_ULP_CLASS_HID_e96b = 0xe96b, + BNXT_ULP_CLASS_HID_efef = 0xefef, + BNXT_ULP_CLASS_HID_fc17 = 0xfc17, + BNXT_ULP_CLASS_HID_f62b = 0xf62b, + BNXT_ULP_CLASS_HID_e587 = 0xe587, BNXT_ULP_CLASS_HID_fa0b = 0xfa0b, - BNXT_ULP_CLASS_HID_ad3f = 0xad3f, - BNXT_ULP_CLASS_HID_afff = 0xafff, - BNXT_ULP_CLASS_HID_f2bf = 0xf2bf, - BNXT_ULP_CLASS_HID_f57f = 0xf57f, - BNXT_ULP_CLASS_HID_1c33f = 0x1c33f, - BNXT_ULP_CLASS_HID_1e5ff = 0x1e5ff, - BNXT_ULP_CLASS_HID_1c8bf = 0x1c8bf, - BNXT_ULP_CLASS_HID_1eb7f = 0x1eb7f, - BNXT_ULP_CLASS_HID_1c7cb = 0x1c7cb, - BNXT_ULP_CLASS_HID_1ea8b = 0x1ea8b, - BNXT_ULP_CLASS_HID_1cd4b = 0x1cd4b, + BNXT_ULP_CLASS_HID_e6b3 = 0xe6b3, + BNXT_ULP_CLASS_HID_e077 = 0xe077, + BNXT_ULP_CLASS_HID_ecff = 0xecff, + BNXT_ULP_CLASS_HID_4e74f = 0x4e74f, + BNXT_ULP_CLASS_HID_4f3f7 = 0x4f3f7, + BNXT_ULP_CLASS_HID_4ed8b = 0x4ed8b, + BNXT_ULP_CLASS_HID_4fa33 = 0x4fa33, + BNXT_ULP_CLASS_HID_4f1eb = 0x4f1eb, + BNXT_ULP_CLASS_HID_4fe13 = 0x4fe13, + BNXT_ULP_CLASS_HID_4f7d7 = 0x4f7d7, + BNXT_ULP_CLASS_HID_4e45f = 0x4e45f, + BNXT_ULP_CLASS_HID_4ead3 = 0x4ead3, + BNXT_ULP_CLASS_HID_4f75b = 0x4f75b, + BNXT_ULP_CLASS_HID_4f11f = 0x4f11f, + BNXT_ULP_CLASS_HID_4e0cb = 0x4e0cb, + BNXT_ULP_CLASS_HID_4f57f = 0x4f57f, + BNXT_ULP_CLASS_HID_4e1e7 = 0x4e1e7, + BNXT_ULP_CLASS_HID_4fbbb = 0x4fbbb, + BNXT_ULP_CLASS_HID_4e823 = 0x4e823, + BNXT_ULP_CLASS_HID_1e21b = 0x1e21b, + BNXT_ULP_CLASS_HID_1ee83 = 0x1ee83, + BNXT_ULP_CLASS_HID_1e847 = 0x1e847, + BNXT_ULP_CLASS_HID_1f4cf = 0x1f4cf, + BNXT_ULP_CLASS_HID_1eca7 = 0x1eca7, + BNXT_ULP_CLASS_HID_1f92f = 0x1f92f, + BNXT_ULP_CLASS_HID_1f2e3 = 0x1f2e3, + BNXT_ULP_CLASS_HID_1ff6b = 0x1ff6b, + BNXT_ULP_CLASS_HID_1e8d3 = 0x1e8d3, + BNXT_ULP_CLASS_HID_1f55b = 0x1f55b, + BNXT_ULP_CLASS_HID_1ef1f = 0x1ef1f, + BNXT_ULP_CLASS_HID_1fb87 = 0x1fb87, BNXT_ULP_CLASS_HID_1f00b = 0x1f00b, - BNXT_ULP_CLASS_HID_9117 = 0x9117, - BNXT_ULP_CLASS_HID_b3d7 = 0xb3d7, - BNXT_ULP_CLASS_HID_d697 = 0xd697, - BNXT_ULP_CLASS_HID_f957 = 0xf957, - BNXT_ULP_CLASS_HID_8c5b = 0x8c5b, - BNXT_ULP_CLASS_HID_af1b = 0xaf1b, - BNXT_ULP_CLASS_HID_d1db = 0xd1db, - BNXT_ULP_CLASS_HID_f49b = 0xf49b, - BNXT_ULP_CLASS_HID_1a25b = 0x1a25b, - BNXT_ULP_CLASS_HID_1a51b = 0x1a51b, - BNXT_ULP_CLASS_HID_1e7db = 0x1e7db, - BNXT_ULP_CLASS_HID_1ea9b = 0x1ea9b, - BNXT_ULP_CLASS_HID_1a717 = 0x1a717, - BNXT_ULP_CLASS_HID_1a9d7 = 0x1a9d7, - BNXT_ULP_CLASS_HID_1ec97 = 0x1ec97, - BNXT_ULP_CLASS_HID_1ef57 = 0x1ef57, - BNXT_ULP_CLASS_HID_b4fb = 0xb4fb, - BNXT_ULP_CLASS_HID_b7bb = 0xb7bb, - BNXT_ULP_CLASS_HID_fa7b = 0xfa7b, - BNXT_ULP_CLASS_HID_fd3b = 0xfd3b, - BNXT_ULP_CLASS_HID_b02f = 0xb02f, - BNXT_ULP_CLASS_HID_b2ef = 0xb2ef, - BNXT_ULP_CLASS_HID_f5af = 0xf5af, - BNXT_ULP_CLASS_HID_f86f = 0xf86f, - BNXT_ULP_CLASS_HID_1c62f = 0x1c62f, - BNXT_ULP_CLASS_HID_1e8ef = 0x1e8ef, - BNXT_ULP_CLASS_HID_1cbaf = 0x1cbaf, - BNXT_ULP_CLASS_HID_1ee6f = 0x1ee6f, - BNXT_ULP_CLASS_HID_1cafb = 0x1cafb, - BNXT_ULP_CLASS_HID_1edbb = 0x1edbb, - BNXT_ULP_CLASS_HID_1d07b = 0x1d07b, - BNXT_ULP_CLASS_HID_1f33b = 0x1f33b, - BNXT_ULP_CLASS_HID_8b2b = 0x8b2b, - BNXT_ULP_CLASS_HID_adeb = 0xadeb, - BNXT_ULP_CLASS_HID_d0ab = 0xd0ab, - BNXT_ULP_CLASS_HID_f36b = 0xf36b, - BNXT_ULP_CLASS_HID_861f = 0x861f, - BNXT_ULP_CLASS_HID_a8df = 0xa8df, - BNXT_ULP_CLASS_HID_cb9f = 0xcb9f, - BNXT_ULP_CLASS_HID_ee5f = 0xee5f, - BNXT_ULP_CLASS_HID_19c1f = 0x19c1f, - BNXT_ULP_CLASS_HID_1bedf = 0x1bedf, - BNXT_ULP_CLASS_HID_1e19f = 0x1e19f, - BNXT_ULP_CLASS_HID_1e45f = 0x1e45f, - BNXT_ULP_CLASS_HID_1a12b = 0x1a12b, - BNXT_ULP_CLASS_HID_1a3eb = 0x1a3eb, - BNXT_ULP_CLASS_HID_1e6ab = 0x1e6ab, - BNXT_ULP_CLASS_HID_1e96b = 0x1e96b, - BNXT_ULP_CLASS_HID_aebf = 0xaebf, - BNXT_ULP_CLASS_HID_b17f = 0xb17f, - BNXT_ULP_CLASS_HID_f43f = 0xf43f, - BNXT_ULP_CLASS_HID_f6ff = 0xf6ff, - BNXT_ULP_CLASS_HID_a9e3 = 0xa9e3, - BNXT_ULP_CLASS_HID_aca3 = 0xaca3, - BNXT_ULP_CLASS_HID_ef63 = 0xef63, - BNXT_ULP_CLASS_HID_f223 = 0xf223, - BNXT_ULP_CLASS_HID_1bfe3 = 0x1bfe3, - BNXT_ULP_CLASS_HID_1e2a3 = 0x1e2a3, - BNXT_ULP_CLASS_HID_1c563 = 0x1c563, - BNXT_ULP_CLASS_HID_1e823 = 0x1e823, - BNXT_ULP_CLASS_HID_1c4bf = 0x1c4bf, - BNXT_ULP_CLASS_HID_1e77f = 0x1e77f, - BNXT_ULP_CLASS_HID_1ca3f = 0x1ca3f, - BNXT_ULP_CLASS_HID_1ecff = 0x1ecff, - BNXT_ULP_CLASS_HID_2543 = 0x2543, - BNXT_ULP_CLASS_HID_2b8f = 0x2b8f, - BNXT_ULP_CLASS_HID_26f3 = 0x26f3, - BNXT_ULP_CLASS_HID_4f13 = 0x4f13, - BNXT_ULP_CLASS_HID_4a47 = 0x4a47, - BNXT_ULP_CLASS_HID_162b = 0x162b, - BNXT_ULP_CLASS_HID_111f = 0x111f, - BNXT_ULP_CLASS_HID_39bf = 0x39bf, - BNXT_ULP_CLASS_HID_34e3 = 0x34e3, - BNXT_ULP_CLASS_HID_20b7 = 0x20b7, - BNXT_ULP_CLASS_HID_48d7 = 0x48d7, - BNXT_ULP_CLASS_HID_441b = 0x441b, - BNXT_ULP_CLASS_HID_0fef = 0x0fef, - BNXT_ULP_CLASS_HID_0ad3 = 0x0ad3, - BNXT_ULP_CLASS_HID_3373 = 0x3373, - BNXT_ULP_CLASS_HID_2ea7 = 0x2ea7, - BNXT_ULP_CLASS_HID_b6ef = 0xb6ef, - BNXT_ULP_CLASS_HID_b92f = 0xb92f, - BNXT_ULP_CLASS_HID_fc6f = 0xfc6f, - BNXT_ULP_CLASS_HID_feaf = 0xfeaf, - BNXT_ULP_CLASS_HID_b193 = 0xb193, - BNXT_ULP_CLASS_HID_b4d3 = 0xb4d3, - BNXT_ULP_CLASS_HID_f713 = 0xf713, - BNXT_ULP_CLASS_HID_fa53 = 0xfa53, - BNXT_ULP_CLASS_HID_1c793 = 0x1c793, - BNXT_ULP_CLASS_HID_1ead3 = 0x1ead3, - BNXT_ULP_CLASS_HID_1cd13 = 0x1cd13, - BNXT_ULP_CLASS_HID_1f053 = 0x1f053, - BNXT_ULP_CLASS_HID_1ccef = 0x1ccef, - BNXT_ULP_CLASS_HID_1ef2f = 0x1ef2f, - BNXT_ULP_CLASS_HID_1d26f = 0x1d26f, - BNXT_ULP_CLASS_HID_1f4af = 0x1f4af, - BNXT_ULP_CLASS_HID_da73 = 0xda73, - BNXT_ULP_CLASS_HID_a067 = 0xa067, - BNXT_ULP_CLASS_HID_c2a7 = 0xc2a7, - BNXT_ULP_CLASS_HID_e5e7 = 0xe5e7, - BNXT_ULP_CLASS_HID_d527 = 0xd527, - BNXT_ULP_CLASS_HID_f867 = 0xf867, - BNXT_ULP_CLASS_HID_daa7 = 0xdaa7, - BNXT_ULP_CLASS_HID_e0ab = 0xe0ab, - BNXT_ULP_CLASS_HID_18eeb = 0x18eeb, - BNXT_ULP_CLASS_HID_1b12b = 0x1b12b, - BNXT_ULP_CLASS_HID_1d46b = 0x1d46b, - BNXT_ULP_CLASS_HID_1f6ab = 0x1f6ab, - BNXT_ULP_CLASS_HID_19327 = 0x19327, - BNXT_ULP_CLASS_HID_1b667 = 0x1b667, - BNXT_ULP_CLASS_HID_1d8a7 = 0x1d8a7, - BNXT_ULP_CLASS_HID_1fbe7 = 0x1fbe7, - BNXT_ULP_CLASS_HID_a14b = 0xa14b, - BNXT_ULP_CLASS_HID_a38b = 0xa38b, - BNXT_ULP_CLASS_HID_e6cb = 0xe6cb, - BNXT_ULP_CLASS_HID_e90b = 0xe90b, - BNXT_ULP_CLASS_HID_9c7f = 0x9c7f, - BNXT_ULP_CLASS_HID_bebf = 0xbebf, - BNXT_ULP_CLASS_HID_e1ff = 0xe1ff, - BNXT_ULP_CLASS_HID_e43f = 0xe43f, - BNXT_ULP_CLASS_HID_1b27f = 0x1b27f, - BNXT_ULP_CLASS_HID_1b4bf = 0x1b4bf, - BNXT_ULP_CLASS_HID_1f7ff = 0x1f7ff, - BNXT_ULP_CLASS_HID_1fa3f = 0x1fa3f, - BNXT_ULP_CLASS_HID_1b74b = 0x1b74b, - BNXT_ULP_CLASS_HID_1b98b = 0x1b98b, - BNXT_ULP_CLASS_HID_1fccb = 0x1fccb, - BNXT_ULP_CLASS_HID_1ff0b = 0x1ff0b, - BNXT_ULP_CLASS_HID_c4df = 0xc4df, - BNXT_ULP_CLASS_HID_e71f = 0xe71f, - BNXT_ULP_CLASS_HID_ca5f = 0xca5f, - BNXT_ULP_CLASS_HID_ec9f = 0xec9f, - BNXT_ULP_CLASS_HID_bf83 = 0xbf83, - BNXT_ULP_CLASS_HID_e2c3 = 0xe2c3, - BNXT_ULP_CLASS_HID_c503 = 0xc503, - BNXT_ULP_CLASS_HID_e843 = 0xe843, - BNXT_ULP_CLASS_HID_1d583 = 0x1d583, - BNXT_ULP_CLASS_HID_1f8c3 = 0x1f8c3, - BNXT_ULP_CLASS_HID_1db03 = 0x1db03, - BNXT_ULP_CLASS_HID_1e177 = 0x1e177, - BNXT_ULP_CLASS_HID_1dadf = 0x1dadf, - BNXT_ULP_CLASS_HID_1a0c3 = 0x1a0c3, - BNXT_ULP_CLASS_HID_1c303 = 0x1c303, - BNXT_ULP_CLASS_HID_1e643 = 0x1e643, - BNXT_ULP_CLASS_HID_b023 = 0xb023, - BNXT_ULP_CLASS_HID_b363 = 0xb363, - BNXT_ULP_CLASS_HID_f5a3 = 0xf5a3, - BNXT_ULP_CLASS_HID_f8e3 = 0xf8e3, - BNXT_ULP_CLASS_HID_abd7 = 0xabd7, - BNXT_ULP_CLASS_HID_ae17 = 0xae17, - BNXT_ULP_CLASS_HID_f157 = 0xf157, - BNXT_ULP_CLASS_HID_f397 = 0xf397, - BNXT_ULP_CLASS_HID_1c1d7 = 0x1c1d7, - BNXT_ULP_CLASS_HID_1e417 = 0x1e417, - BNXT_ULP_CLASS_HID_1c757 = 0x1c757, - BNXT_ULP_CLASS_HID_1e997 = 0x1e997, - BNXT_ULP_CLASS_HID_1c623 = 0x1c623, - BNXT_ULP_CLASS_HID_1e963 = 0x1e963, - BNXT_ULP_CLASS_HID_1cba3 = 0x1cba3, - BNXT_ULP_CLASS_HID_1eee3 = 0x1eee3, - BNXT_ULP_CLASS_HID_d3b7 = 0xd3b7, - BNXT_ULP_CLASS_HID_f6f7 = 0xf6f7, - BNXT_ULP_CLASS_HID_d937 = 0xd937, - BNXT_ULP_CLASS_HID_fc77 = 0xfc77, - BNXT_ULP_CLASS_HID_cf7b = 0xcf7b, - BNXT_ULP_CLASS_HID_f1bb = 0xf1bb, - BNXT_ULP_CLASS_HID_d4fb = 0xd4fb, - BNXT_ULP_CLASS_HID_f73b = 0xf73b, - BNXT_ULP_CLASS_HID_1882f = 0x1882f, - BNXT_ULP_CLASS_HID_1ab6f = 0x1ab6f, - BNXT_ULP_CLASS_HID_1cdaf = 0x1cdaf, - BNXT_ULP_CLASS_HID_1f0ef = 0x1f0ef, - BNXT_ULP_CLASS_HID_18d7b = 0x18d7b, - BNXT_ULP_CLASS_HID_1afbb = 0x1afbb, - BNXT_ULP_CLASS_HID_1d2fb = 0x1d2fb, - BNXT_ULP_CLASS_HID_1f53b = 0x1f53b, - BNXT_ULP_CLASS_HID_9a8f = 0x9a8f, - BNXT_ULP_CLASS_HID_bdcf = 0xbdcf, - BNXT_ULP_CLASS_HID_e00f = 0xe00f, - BNXT_ULP_CLASS_HID_e34f = 0xe34f, - BNXT_ULP_CLASS_HID_95b3 = 0x95b3, - BNXT_ULP_CLASS_HID_b8f3 = 0xb8f3, - BNXT_ULP_CLASS_HID_db33 = 0xdb33, - BNXT_ULP_CLASS_HID_fe73 = 0xfe73, - BNXT_ULP_CLASS_HID_1abb3 = 0x1abb3, - BNXT_ULP_CLASS_HID_1aef3 = 0x1aef3, - BNXT_ULP_CLASS_HID_1f133 = 0x1f133, - BNXT_ULP_CLASS_HID_1f473 = 0x1f473, - BNXT_ULP_CLASS_HID_1b08f = 0x1b08f, - BNXT_ULP_CLASS_HID_1b3cf = 0x1b3cf, - BNXT_ULP_CLASS_HID_1f60f = 0x1f60f, - BNXT_ULP_CLASS_HID_1f94f = 0x1f94f, - BNXT_ULP_CLASS_HID_be13 = 0xbe13, - BNXT_ULP_CLASS_HID_e153 = 0xe153, - BNXT_ULP_CLASS_HID_c393 = 0xc393, - BNXT_ULP_CLASS_HID_e6d3 = 0xe6d3, - BNXT_ULP_CLASS_HID_b9c7 = 0xb9c7, - BNXT_ULP_CLASS_HID_bc07 = 0xbc07, - BNXT_ULP_CLASS_HID_ff47 = 0xff47, - BNXT_ULP_CLASS_HID_e187 = 0xe187, - BNXT_ULP_CLASS_HID_1cfc7 = 0x1cfc7, - BNXT_ULP_CLASS_HID_1f207 = 0x1f207, - BNXT_ULP_CLASS_HID_1d547 = 0x1d547, - BNXT_ULP_CLASS_HID_1f787 = 0x1f787, - BNXT_ULP_CLASS_HID_1d413 = 0x1d413, - BNXT_ULP_CLASS_HID_1f753 = 0x1f753, - BNXT_ULP_CLASS_HID_1d993 = 0x1d993, - BNXT_ULP_CLASS_HID_1fcd3 = 0x1fcd3, - BNXT_ULP_CLASS_HID_aa67 = 0xaa67, - BNXT_ULP_CLASS_HID_aca7 = 0xaca7, - BNXT_ULP_CLASS_HID_efe7 = 0xefe7, - BNXT_ULP_CLASS_HID_f227 = 0xf227, - BNXT_ULP_CLASS_HID_a52b = 0xa52b, - BNXT_ULP_CLASS_HID_a86b = 0xa86b, - BNXT_ULP_CLASS_HID_eaab = 0xeaab, - BNXT_ULP_CLASS_HID_edeb = 0xedeb, - BNXT_ULP_CLASS_HID_1bb2b = 0x1bb2b, - BNXT_ULP_CLASS_HID_1be6b = 0x1be6b, - BNXT_ULP_CLASS_HID_1c0ab = 0x1c0ab, - BNXT_ULP_CLASS_HID_1e3eb = 0x1e3eb, - BNXT_ULP_CLASS_HID_1c067 = 0x1c067, - BNXT_ULP_CLASS_HID_1e2a7 = 0x1e2a7, - BNXT_ULP_CLASS_HID_1c5e7 = 0x1c5e7, - BNXT_ULP_CLASS_HID_1e827 = 0x1e827, - BNXT_ULP_CLASS_HID_cd8b = 0xcd8b, - BNXT_ULP_CLASS_HID_f0cb = 0xf0cb, - BNXT_ULP_CLASS_HID_d30b = 0xd30b, - BNXT_ULP_CLASS_HID_f64b = 0xf64b, - BNXT_ULP_CLASS_HID_c8bf = 0xc8bf, - BNXT_ULP_CLASS_HID_ebff = 0xebff, - BNXT_ULP_CLASS_HID_ce3f = 0xce3f, - BNXT_ULP_CLASS_HID_f17f = 0xf17f, - BNXT_ULP_CLASS_HID_18263 = 0x18263, - BNXT_ULP_CLASS_HID_1a4a3 = 0x1a4a3, - BNXT_ULP_CLASS_HID_1c7e3 = 0x1c7e3, - BNXT_ULP_CLASS_HID_1ea23 = 0x1ea23, - BNXT_ULP_CLASS_HID_186bf = 0x186bf, - BNXT_ULP_CLASS_HID_1a9ff = 0x1a9ff, - BNXT_ULP_CLASS_HID_1cc3f = 0x1cc3f, - BNXT_ULP_CLASS_HID_1ef7f = 0x1ef7f, - BNXT_ULP_CLASS_HID_94c3 = 0x94c3, - BNXT_ULP_CLASS_HID_b703 = 0xb703, - BNXT_ULP_CLASS_HID_da43 = 0xda43, - BNXT_ULP_CLASS_HID_fc83 = 0xfc83, - BNXT_ULP_CLASS_HID_8ff7 = 0x8ff7, - BNXT_ULP_CLASS_HID_b237 = 0xb237, - BNXT_ULP_CLASS_HID_d577 = 0xd577, - BNXT_ULP_CLASS_HID_f7b7 = 0xf7b7, - BNXT_ULP_CLASS_HID_1a5f7 = 0x1a5f7, - BNXT_ULP_CLASS_HID_1a837 = 0x1a837, - BNXT_ULP_CLASS_HID_1eb77 = 0x1eb77, - BNXT_ULP_CLASS_HID_1edb7 = 0x1edb7, - BNXT_ULP_CLASS_HID_1aac3 = 0x1aac3, - BNXT_ULP_CLASS_HID_1ad03 = 0x1ad03, - BNXT_ULP_CLASS_HID_1f043 = 0x1f043, - BNXT_ULP_CLASS_HID_1f283 = 0x1f283, + BNXT_ULP_CLASS_HID_1fcb3 = 0x1fcb3, + BNXT_ULP_CLASS_HID_1f677 = 0x1f677, + BNXT_ULP_CLASS_HID_1e623 = 0x1e623, + BNXT_ULP_CLASS_HID_5fd4f = 0x5fd4f, + BNXT_ULP_CLASS_HID_5e9f7 = 0x5e9f7, + BNXT_ULP_CLASS_HID_5e38b = 0x5e38b, + BNXT_ULP_CLASS_HID_5f033 = 0x5f033, + BNXT_ULP_CLASS_HID_5e7eb = 0x5e7eb, + BNXT_ULP_CLASS_HID_5f413 = 0x5f413, + BNXT_ULP_CLASS_HID_5edd7 = 0x5edd7, + BNXT_ULP_CLASS_HID_5fa5f = 0x5fa5f, + BNXT_ULP_CLASS_HID_5e407 = 0x5e407, + BNXT_ULP_CLASS_HID_5f08f = 0x5f08f, + BNXT_ULP_CLASS_HID_5ea43 = 0x5ea43, + BNXT_ULP_CLASS_HID_5f6cb = 0x5f6cb, + BNXT_ULP_CLASS_HID_5eb7f = 0x5eb7f, + BNXT_ULP_CLASS_HID_5f7e7 = 0x5f7e7, + BNXT_ULP_CLASS_HID_5f1bb = 0x5f1bb, + BNXT_ULP_CLASS_HID_5e117 = 0x5e117, + BNXT_ULP_CLASS_HID_244a3 = 0x244a3, + BNXT_ULP_CLASS_HID_2513b = 0x2513b, + BNXT_ULP_CLASS_HID_24b7f = 0x24b7f, + BNXT_ULP_CLASS_HID_257f7 = 0x257f7, + BNXT_ULP_CLASS_HID_22f1f = 0x22f1f, + BNXT_ULP_CLASS_HID_23b97 = 0x23b97, + BNXT_ULP_CLASS_HID_235db = 0x235db, + BNXT_ULP_CLASS_HID_24253 = 0x24253, + BNXT_ULP_CLASS_HID_20beb = 0x20beb, + BNXT_ULP_CLASS_HID_21863 = 0x21863, + BNXT_ULP_CLASS_HID_211a7 = 0x211a7, + BNXT_ULP_CLASS_HID_21e3f = 0x21e3f, + BNXT_ULP_CLASS_HID_252b3 = 0x252b3, + BNXT_ULP_CLASS_HID_202df = 0x202df, + BNXT_ULP_CLASS_HID_2594f = 0x2594f, + BNXT_ULP_CLASS_HID_2089b = 0x2089b, + BNXT_ULP_CLASS_HID_23193 = 0x23193, + BNXT_ULP_CLASS_HID_23e6b = 0x23e6b, + BNXT_ULP_CLASS_HID_237af = 0x237af, + BNXT_ULP_CLASS_HID_24427 = 0x24427, + BNXT_ULP_CLASS_HID_21c4f = 0x21c4f, + BNXT_ULP_CLASS_HID_228c7 = 0x228c7, + BNXT_ULP_CLASS_HID_2220b = 0x2220b, + BNXT_ULP_CLASS_HID_22e83 = 0x22e83, + BNXT_ULP_CLASS_HID_25507 = 0x25507, + BNXT_ULP_CLASS_HID_20553 = 0x20553, + BNXT_ULP_CLASS_HID_25bc3 = 0x25bc3, + BNXT_ULP_CLASS_HID_20b6f = 0x20b6f, + BNXT_ULP_CLASS_HID_23fe3 = 0x23fe3, + BNXT_ULP_CLASS_HID_24c7b = 0x24c7b, + BNXT_ULP_CLASS_HID_245bf = 0x245bf, + BNXT_ULP_CLASS_HID_25237 = 0x25237, + BNXT_ULP_CLASS_HID_64077 = 0x64077, + BNXT_ULP_CLASS_HID_64ccf = 0x64ccf, + BNXT_ULP_CLASS_HID_64633 = 0x64633, + BNXT_ULP_CLASS_HID_6528b = 0x6528b, + BNXT_ULP_CLASS_HID_62ad3 = 0x62ad3, + BNXT_ULP_CLASS_HID_636ab = 0x636ab, + BNXT_ULP_CLASS_HID_630ef = 0x630ef, + BNXT_ULP_CLASS_HID_63d67 = 0x63d67, + BNXT_ULP_CLASS_HID_606bf = 0x606bf, + BNXT_ULP_CLASS_HID_61337 = 0x61337, + BNXT_ULP_CLASS_HID_60d7b = 0x60d7b, + BNXT_ULP_CLASS_HID_619f3 = 0x619f3, + BNXT_ULP_CLASS_HID_64e47 = 0x64e47, + BNXT_ULP_CLASS_HID_65adf = 0x65adf, + BNXT_ULP_CLASS_HID_65403 = 0x65403, + BNXT_ULP_CLASS_HID_603af = 0x603af, + BNXT_ULP_CLASS_HID_62ca7 = 0x62ca7, + BNXT_ULP_CLASS_HID_6393f = 0x6393f, + BNXT_ULP_CLASS_HID_63363 = 0x63363, + BNXT_ULP_CLASS_HID_63ffb = 0x63ffb, + BNXT_ULP_CLASS_HID_61703 = 0x61703, + BNXT_ULP_CLASS_HID_6239b = 0x6239b, + BNXT_ULP_CLASS_HID_61ddf = 0x61ddf, + BNXT_ULP_CLASS_HID_62a57 = 0x62a57, + BNXT_ULP_CLASS_HID_650db = 0x650db, + BNXT_ULP_CLASS_HID_60067 = 0x60067, + BNXT_ULP_CLASS_HID_65697 = 0x65697, + BNXT_ULP_CLASS_HID_60623 = 0x60623, + BNXT_ULP_CLASS_HID_63ab7 = 0x63ab7, + BNXT_ULP_CLASS_HID_6470f = 0x6470f, + BNXT_ULP_CLASS_HID_64173 = 0x64173, + BNXT_ULP_CLASS_HID_64dcb = 0x64dcb, + BNXT_ULP_CLASS_HID_35aa3 = 0x35aa3, + BNXT_ULP_CLASS_HID_30acf = 0x30acf, + BNXT_ULP_CLASS_HID_30433 = 0x30433, + BNXT_ULP_CLASS_HID_3108b = 0x3108b, + BNXT_ULP_CLASS_HID_3451f = 0x3451f, + BNXT_ULP_CLASS_HID_35197 = 0x35197, + BNXT_ULP_CLASS_HID_34bdb = 0x34bdb, + BNXT_ULP_CLASS_HID_35853 = 0x35853, + BNXT_ULP_CLASS_HID_321eb = 0x321eb, + BNXT_ULP_CLASS_HID_32e63 = 0x32e63, + BNXT_ULP_CLASS_HID_327a7 = 0x327a7, + BNXT_ULP_CLASS_HID_3343f = 0x3343f, + BNXT_ULP_CLASS_HID_30c47 = 0x30c47, + BNXT_ULP_CLASS_HID_318df = 0x318df, + BNXT_ULP_CLASS_HID_31203 = 0x31203, + BNXT_ULP_CLASS_HID_31e9b = 0x31e9b, + BNXT_ULP_CLASS_HID_34793 = 0x34793, + BNXT_ULP_CLASS_HID_3546b = 0x3546b, + BNXT_ULP_CLASS_HID_34daf = 0x34daf, + BNXT_ULP_CLASS_HID_35a27 = 0x35a27, + BNXT_ULP_CLASS_HID_3324f = 0x3324f, + BNXT_ULP_CLASS_HID_33ec7 = 0x33ec7, + BNXT_ULP_CLASS_HID_3380b = 0x3380b, + BNXT_ULP_CLASS_HID_34483 = 0x34483, + BNXT_ULP_CLASS_HID_30edb = 0x30edb, + BNXT_ULP_CLASS_HID_31b53 = 0x31b53, + BNXT_ULP_CLASS_HID_31497 = 0x31497, + BNXT_ULP_CLASS_HID_3216f = 0x3216f, + BNXT_ULP_CLASS_HID_355e3 = 0x355e3, + BNXT_ULP_CLASS_HID_3050f = 0x3050f, + BNXT_ULP_CLASS_HID_35bbf = 0x35bbf, + BNXT_ULP_CLASS_HID_30bcb = 0x30bcb, + BNXT_ULP_CLASS_HID_75677 = 0x75677, + BNXT_ULP_CLASS_HID_70583 = 0x70583, + BNXT_ULP_CLASS_HID_75c33 = 0x75c33, + BNXT_ULP_CLASS_HID_70c5f = 0x70c5f, + BNXT_ULP_CLASS_HID_740d3 = 0x740d3, + BNXT_ULP_CLASS_HID_74cab = 0x74cab, + BNXT_ULP_CLASS_HID_746ef = 0x746ef, + BNXT_ULP_CLASS_HID_75367 = 0x75367, + BNXT_ULP_CLASS_HID_71cbf = 0x71cbf, + BNXT_ULP_CLASS_HID_72937 = 0x72937, + BNXT_ULP_CLASS_HID_7237b = 0x7237b, + BNXT_ULP_CLASS_HID_72ff3 = 0x72ff3, + BNXT_ULP_CLASS_HID_7071b = 0x7071b, + BNXT_ULP_CLASS_HID_71393 = 0x71393, + BNXT_ULP_CLASS_HID_70dd7 = 0x70dd7, + BNXT_ULP_CLASS_HID_719af = 0x719af, + BNXT_ULP_CLASS_HID_742a7 = 0x742a7, + BNXT_ULP_CLASS_HID_74f3f = 0x74f3f, + BNXT_ULP_CLASS_HID_74963 = 0x74963, + BNXT_ULP_CLASS_HID_755fb = 0x755fb, + BNXT_ULP_CLASS_HID_72d03 = 0x72d03, + BNXT_ULP_CLASS_HID_7399b = 0x7399b, + BNXT_ULP_CLASS_HID_733df = 0x733df, + BNXT_ULP_CLASS_HID_74057 = 0x74057, + BNXT_ULP_CLASS_HID_709ef = 0x709ef, + BNXT_ULP_CLASS_HID_71667 = 0x71667, + BNXT_ULP_CLASS_HID_70fab = 0x70fab, + BNXT_ULP_CLASS_HID_71c23 = 0x71c23, + BNXT_ULP_CLASS_HID_750b7 = 0x750b7, + BNXT_ULP_CLASS_HID_700c3 = 0x700c3, + BNXT_ULP_CLASS_HID_75773 = 0x75773, + BNXT_ULP_CLASS_HID_7069f = 0x7069f, + BNXT_ULP_CLASS_HID_2cfa3 = 0x2cfa3, + BNXT_ULP_CLASS_HID_2dc3b = 0x2dc3b, + BNXT_ULP_CLASS_HID_2d67f = 0x2d67f, + BNXT_ULP_CLASS_HID_2858b = 0x2858b, + BNXT_ULP_CLASS_HID_2ba1f = 0x2ba1f, + BNXT_ULP_CLASS_HID_2c697 = 0x2c697, + BNXT_ULP_CLASS_HID_2c0db = 0x2c0db, + BNXT_ULP_CLASS_HID_2cd53 = 0x2cd53, + BNXT_ULP_CLASS_HID_296eb = 0x296eb, + BNXT_ULP_CLASS_HID_2a363 = 0x2a363, + BNXT_ULP_CLASS_HID_29ca7 = 0x29ca7, + BNXT_ULP_CLASS_HID_2a93f = 0x2a93f, + BNXT_ULP_CLASS_HID_28147 = 0x28147, + BNXT_ULP_CLASS_HID_28ddf = 0x28ddf, + BNXT_ULP_CLASS_HID_28703 = 0x28703, + BNXT_ULP_CLASS_HID_2939b = 0x2939b, + BNXT_ULP_CLASS_HID_2bc93 = 0x2bc93, + BNXT_ULP_CLASS_HID_2c96b = 0x2c96b, + BNXT_ULP_CLASS_HID_2c2af = 0x2c2af, + BNXT_ULP_CLASS_HID_2cf27 = 0x2cf27, + BNXT_ULP_CLASS_HID_2a74f = 0x2a74f, + BNXT_ULP_CLASS_HID_2b3c7 = 0x2b3c7, + BNXT_ULP_CLASS_HID_2ad0b = 0x2ad0b, + BNXT_ULP_CLASS_HID_2b983 = 0x2b983, + BNXT_ULP_CLASS_HID_283db = 0x283db, + BNXT_ULP_CLASS_HID_29053 = 0x29053, + BNXT_ULP_CLASS_HID_28997 = 0x28997, + BNXT_ULP_CLASS_HID_2966f = 0x2966f, + BNXT_ULP_CLASS_HID_2cae3 = 0x2cae3, + BNXT_ULP_CLASS_HID_2d77b = 0x2d77b, + BNXT_ULP_CLASS_HID_2d0bf = 0x2d0bf, + BNXT_ULP_CLASS_HID_280cb = 0x280cb, + BNXT_ULP_CLASS_HID_6cb77 = 0x6cb77, + BNXT_ULP_CLASS_HID_6d7cf = 0x6d7cf, + BNXT_ULP_CLASS_HID_6d133 = 0x6d133, + BNXT_ULP_CLASS_HID_6815f = 0x6815f, + BNXT_ULP_CLASS_HID_6b5d3 = 0x6b5d3, + BNXT_ULP_CLASS_HID_6c1ab = 0x6c1ab, + BNXT_ULP_CLASS_HID_6bbef = 0x6bbef, + BNXT_ULP_CLASS_HID_6c867 = 0x6c867, + BNXT_ULP_CLASS_HID_691bf = 0x691bf, + BNXT_ULP_CLASS_HID_69e37 = 0x69e37, + BNXT_ULP_CLASS_HID_6987b = 0x6987b, + BNXT_ULP_CLASS_HID_6a4f3 = 0x6a4f3, + BNXT_ULP_CLASS_HID_6d947 = 0x6d947, + BNXT_ULP_CLASS_HID_68893 = 0x68893, + BNXT_ULP_CLASS_HID_682d7 = 0x682d7, + BNXT_ULP_CLASS_HID_68eaf = 0x68eaf, + BNXT_ULP_CLASS_HID_6b7a7 = 0x6b7a7, + BNXT_ULP_CLASS_HID_6c43f = 0x6c43f, + BNXT_ULP_CLASS_HID_6be63 = 0x6be63, + BNXT_ULP_CLASS_HID_6cafb = 0x6cafb, + BNXT_ULP_CLASS_HID_6a203 = 0x6a203, + BNXT_ULP_CLASS_HID_6ae9b = 0x6ae9b, + BNXT_ULP_CLASS_HID_6a8df = 0x6a8df, + BNXT_ULP_CLASS_HID_6b557 = 0x6b557, + BNXT_ULP_CLASS_HID_6dbdb = 0x6dbdb, + BNXT_ULP_CLASS_HID_68b67 = 0x68b67, + BNXT_ULP_CLASS_HID_684ab = 0x684ab, + BNXT_ULP_CLASS_HID_69123 = 0x69123, + BNXT_ULP_CLASS_HID_6c5b7 = 0x6c5b7, + BNXT_ULP_CLASS_HID_6d20f = 0x6d20f, + BNXT_ULP_CLASS_HID_6cc73 = 0x6cc73, + BNXT_ULP_CLASS_HID_6d8cb = 0x6d8cb, + BNXT_ULP_CLASS_HID_38977 = 0x38977, + BNXT_ULP_CLASS_HID_395cf = 0x395cf, + BNXT_ULP_CLASS_HID_38f33 = 0x38f33, + BNXT_ULP_CLASS_HID_39b8b = 0x39b8b, + BNXT_ULP_CLASS_HID_3d01f = 0x3d01f, + BNXT_ULP_CLASS_HID_3dc97 = 0x3dc97, + BNXT_ULP_CLASS_HID_3d6db = 0x3d6db, + BNXT_ULP_CLASS_HID_38667 = 0x38667, + BNXT_ULP_CLASS_HID_3aceb = 0x3aceb, + BNXT_ULP_CLASS_HID_3b963 = 0x3b963, + BNXT_ULP_CLASS_HID_3b2a7 = 0x3b2a7, + BNXT_ULP_CLASS_HID_3bf3f = 0x3bf3f, + BNXT_ULP_CLASS_HID_39747 = 0x39747, + BNXT_ULP_CLASS_HID_3a3df = 0x3a3df, + BNXT_ULP_CLASS_HID_39d03 = 0x39d03, + BNXT_ULP_CLASS_HID_3a99b = 0x3a99b, + BNXT_ULP_CLASS_HID_3d293 = 0x3d293, + BNXT_ULP_CLASS_HID_3823f = 0x3823f, + BNXT_ULP_CLASS_HID_3d8af = 0x3d8af, + BNXT_ULP_CLASS_HID_388fb = 0x388fb, + BNXT_ULP_CLASS_HID_3bd4f = 0x3bd4f, + BNXT_ULP_CLASS_HID_3c9c7 = 0x3c9c7, + BNXT_ULP_CLASS_HID_3c30b = 0x3c30b, + BNXT_ULP_CLASS_HID_3cf83 = 0x3cf83, + BNXT_ULP_CLASS_HID_399db = 0x399db, + BNXT_ULP_CLASS_HID_3a653 = 0x3a653, + BNXT_ULP_CLASS_HID_39f97 = 0x39f97, + BNXT_ULP_CLASS_HID_3ac6f = 0x3ac6f, + BNXT_ULP_CLASS_HID_383b7 = 0x383b7, + BNXT_ULP_CLASS_HID_3900f = 0x3900f, + BNXT_ULP_CLASS_HID_38a73 = 0x38a73, + BNXT_ULP_CLASS_HID_396cb = 0x396cb, + BNXT_ULP_CLASS_HID_7840b = 0x7840b, + BNXT_ULP_CLASS_HID_79083 = 0x79083, + BNXT_ULP_CLASS_HID_78ac7 = 0x78ac7, + BNXT_ULP_CLASS_HID_7975f = 0x7975f, + BNXT_ULP_CLASS_HID_7cbd3 = 0x7cbd3, + BNXT_ULP_CLASS_HID_7d7ab = 0x7d7ab, + BNXT_ULP_CLASS_HID_7d1ef = 0x7d1ef, + BNXT_ULP_CLASS_HID_7813b = 0x7813b, + BNXT_ULP_CLASS_HID_7a7bf = 0x7a7bf, + BNXT_ULP_CLASS_HID_7b437 = 0x7b437, + BNXT_ULP_CLASS_HID_7ae7b = 0x7ae7b, + BNXT_ULP_CLASS_HID_7baf3 = 0x7baf3, + BNXT_ULP_CLASS_HID_7921b = 0x7921b, + BNXT_ULP_CLASS_HID_79e93 = 0x79e93, + BNXT_ULP_CLASS_HID_798d7 = 0x798d7, + BNXT_ULP_CLASS_HID_7a4af = 0x7a4af, + BNXT_ULP_CLASS_HID_7cda7 = 0x7cda7, + BNXT_ULP_CLASS_HID_7da3f = 0x7da3f, + BNXT_ULP_CLASS_HID_7d463 = 0x7d463, + BNXT_ULP_CLASS_HID_7838f = 0x7838f, + BNXT_ULP_CLASS_HID_7b803 = 0x7b803, + BNXT_ULP_CLASS_HID_7c49b = 0x7c49b, + BNXT_ULP_CLASS_HID_7bedf = 0x7bedf, + BNXT_ULP_CLASS_HID_7cb57 = 0x7cb57, + BNXT_ULP_CLASS_HID_794ef = 0x794ef, + BNXT_ULP_CLASS_HID_7a167 = 0x7a167, + BNXT_ULP_CLASS_HID_79aab = 0x79aab, + BNXT_ULP_CLASS_HID_7a723 = 0x7a723, + BNXT_ULP_CLASS_HID_7dbb7 = 0x7dbb7, + BNXT_ULP_CLASS_HID_78bc3 = 0x78bc3, + BNXT_ULP_CLASS_HID_78507 = 0x78507, + BNXT_ULP_CLASS_HID_7919f = 0x7919f, + BNXT_ULP_CLASS_HID_a3bb = 0xa3bb, + BNXT_ULP_CLASS_HID_b023 = 0xb023, + BNXT_ULP_CLASS_HID_aa67 = 0xaa67, + BNXT_ULP_CLASS_HID_b6ef = 0xb6ef, + BNXT_ULP_CLASS_HID_8e07 = 0x8e07, + BNXT_ULP_CLASS_HID_9a8f = 0x9a8f, + BNXT_ULP_CLASS_HID_94c3 = 0x94c3, + BNXT_ULP_CLASS_HID_a14b = 0xa14b, + BNXT_ULP_CLASS_HID_c7cf = 0xc7cf, + BNXT_ULP_CLASS_HID_d3b7 = 0xd3b7, + BNXT_ULP_CLASS_HID_cd8b = 0xcd8b, + BNXT_ULP_CLASS_HID_da73 = 0xda73, + BNXT_ULP_CLASS_HID_b1ab = 0xb1ab, + BNXT_ULP_CLASS_HID_be13 = 0xbe13, BNXT_ULP_CLASS_HID_b857 = 0xb857, - BNXT_ULP_CLASS_HID_ba97 = 0xba97, - BNXT_ULP_CLASS_HID_fdd7 = 0xfdd7, - BNXT_ULP_CLASS_HID_e017 = 0xe017, - BNXT_ULP_CLASS_HID_b31b = 0xb31b, - BNXT_ULP_CLASS_HID_b65b = 0xb65b, - BNXT_ULP_CLASS_HID_f89b = 0xf89b, - BNXT_ULP_CLASS_HID_fbdb = 0xfbdb, - BNXT_ULP_CLASS_HID_1c91b = 0x1c91b, - BNXT_ULP_CLASS_HID_1ec5b = 0x1ec5b, - BNXT_ULP_CLASS_HID_1ce9b = 0x1ce9b, - BNXT_ULP_CLASS_HID_1f1db = 0x1f1db, + BNXT_ULP_CLASS_HID_c4df = 0xc4df, + BNXT_ULP_CLASS_HID_49f6f = 0x49f6f, + BNXT_ULP_CLASS_HID_4abd7 = 0x4abd7, + BNXT_ULP_CLASS_HID_4a52b = 0x4a52b, + BNXT_ULP_CLASS_HID_4b193 = 0x4b193, + BNXT_ULP_CLASS_HID_489cb = 0x489cb, + BNXT_ULP_CLASS_HID_495b3 = 0x495b3, + BNXT_ULP_CLASS_HID_48ff7 = 0x48ff7, + BNXT_ULP_CLASS_HID_49c7f = 0x49c7f, + BNXT_ULP_CLASS_HID_4c2f3 = 0x4c2f3, + BNXT_ULP_CLASS_HID_4cf7b = 0x4cf7b, + BNXT_ULP_CLASS_HID_4c8bf = 0x4c8bf, + BNXT_ULP_CLASS_HID_4d527 = 0x4d527, + BNXT_ULP_CLASS_HID_4ad5f = 0x4ad5f, + BNXT_ULP_CLASS_HID_4b9c7 = 0x4b9c7, + BNXT_ULP_CLASS_HID_4b31b = 0x4b31b, + BNXT_ULP_CLASS_HID_4bf83 = 0x4bf83, + BNXT_ULP_CLASS_HID_1b9bb = 0x1b9bb, + BNXT_ULP_CLASS_HID_1c623 = 0x1c623, + BNXT_ULP_CLASS_HID_1c067 = 0x1c067, + BNXT_ULP_CLASS_HID_1ccef = 0x1ccef, + BNXT_ULP_CLASS_HID_1a407 = 0x1a407, + BNXT_ULP_CLASS_HID_1b08f = 0x1b08f, + BNXT_ULP_CLASS_HID_1aac3 = 0x1aac3, + BNXT_ULP_CLASS_HID_1b74b = 0x1b74b, + BNXT_ULP_CLASS_HID_180f3 = 0x180f3, + BNXT_ULP_CLASS_HID_18d7b = 0x18d7b, + BNXT_ULP_CLASS_HID_186bf = 0x186bf, + BNXT_ULP_CLASS_HID_19327 = 0x19327, + BNXT_ULP_CLASS_HID_1c7ab = 0x1c7ab, + BNXT_ULP_CLASS_HID_1d413 = 0x1d413, BNXT_ULP_CLASS_HID_1ce57 = 0x1ce57, - BNXT_ULP_CLASS_HID_1f097 = 0x1f097, - BNXT_ULP_CLASS_HID_1d3d7 = 0x1d3d7, - BNXT_ULP_CLASS_HID_1f617 = 0x1f617, - BNXT_ULP_CLASS_HID_a3bb = 0xa3bb, - BNXT_ULP_CLASS_HID_a6fb = 0xa6fb, + BNXT_ULP_CLASS_HID_1dadf = 0x1dadf, + BNXT_ULP_CLASS_HID_5b56f = 0x5b56f, + BNXT_ULP_CLASS_HID_5c1d7 = 0x5c1d7, + BNXT_ULP_CLASS_HID_5bb2b = 0x5bb2b, + BNXT_ULP_CLASS_HID_5c793 = 0x5c793, + BNXT_ULP_CLASS_HID_59fcb = 0x59fcb, + BNXT_ULP_CLASS_HID_5abb3 = 0x5abb3, + BNXT_ULP_CLASS_HID_5a5f7 = 0x5a5f7, + BNXT_ULP_CLASS_HID_5b27f = 0x5b27f, + BNXT_ULP_CLASS_HID_5d8f3 = 0x5d8f3, + BNXT_ULP_CLASS_HID_5882f = 0x5882f, + BNXT_ULP_CLASS_HID_58263 = 0x58263, + BNXT_ULP_CLASS_HID_58eeb = 0x58eeb, + BNXT_ULP_CLASS_HID_5c35f = 0x5c35f, + BNXT_ULP_CLASS_HID_5cfc7 = 0x5cfc7, + BNXT_ULP_CLASS_HID_5c91b = 0x5c91b, + BNXT_ULP_CLASS_HID_5d583 = 0x5d583, BNXT_ULP_CLASS_HID_e93b = 0xe93b, - BNXT_ULP_CLASS_HID_ec7b = 0xec7b, - BNXT_ULP_CLASS_HID_9f6f = 0x9f6f, - BNXT_ULP_CLASS_HID_a1af = 0xa1af, - BNXT_ULP_CLASS_HID_e4ef = 0xe4ef, - BNXT_ULP_CLASS_HID_e72f = 0xe72f, - BNXT_ULP_CLASS_HID_1b56f = 0x1b56f, - BNXT_ULP_CLASS_HID_1b7af = 0x1b7af, - BNXT_ULP_CLASS_HID_1faef = 0x1faef, - BNXT_ULP_CLASS_HID_1fd2f = 0x1fd2f, - BNXT_ULP_CLASS_HID_1b9bb = 0x1b9bb, - BNXT_ULP_CLASS_HID_1bcfb = 0x1bcfb, - BNXT_ULP_CLASS_HID_1ff3b = 0x1ff3b, - BNXT_ULP_CLASS_HID_1e27b = 0x1e27b, - BNXT_ULP_CLASS_HID_c7cf = 0xc7cf, - BNXT_ULP_CLASS_HID_ea0f = 0xea0f, + BNXT_ULP_CLASS_HID_f5a3 = 0xf5a3, + BNXT_ULP_CLASS_HID_efe7 = 0xefe7, + BNXT_ULP_CLASS_HID_fc6f = 0xfc6f, + BNXT_ULP_CLASS_HID_d387 = 0xd387, + BNXT_ULP_CLASS_HID_e00f = 0xe00f, + BNXT_ULP_CLASS_HID_da43 = 0xda43, + BNXT_ULP_CLASS_HID_e6cb = 0xe6cb, BNXT_ULP_CLASS_HID_cd4f = 0xcd4f, - BNXT_ULP_CLASS_HID_ef8f = 0xef8f, - BNXT_ULP_CLASS_HID_c2f3 = 0xc2f3, - BNXT_ULP_CLASS_HID_e533 = 0xe533, - BNXT_ULP_CLASS_HID_c873 = 0xc873, - BNXT_ULP_CLASS_HID_eab3 = 0xeab3, - BNXT_ULP_CLASS_HID_1d8f3 = 0x1d8f3, - BNXT_ULP_CLASS_HID_1fb33 = 0x1fb33, - BNXT_ULP_CLASS_HID_1c127 = 0x1c127, - BNXT_ULP_CLASS_HID_1e467 = 0x1e467, - BNXT_ULP_CLASS_HID_180f3 = 0x180f3, - BNXT_ULP_CLASS_HID_1a333 = 0x1a333, + BNXT_ULP_CLASS_HID_d937 = 0xd937, + BNXT_ULP_CLASS_HID_d30b = 0xd30b, + BNXT_ULP_CLASS_HID_c2a7 = 0xc2a7, + BNXT_ULP_CLASS_HID_f72b = 0xf72b, + BNXT_ULP_CLASS_HID_c393 = 0xc393, + BNXT_ULP_CLASS_HID_fdd7 = 0xfdd7, + BNXT_ULP_CLASS_HID_ca5f = 0xca5f, + BNXT_ULP_CLASS_HID_4e4ef = 0x4e4ef, + BNXT_ULP_CLASS_HID_4f157 = 0x4f157, + BNXT_ULP_CLASS_HID_4eaab = 0x4eaab, + BNXT_ULP_CLASS_HID_4f713 = 0x4f713, + BNXT_ULP_CLASS_HID_4cf4b = 0x4cf4b, + BNXT_ULP_CLASS_HID_4db33 = 0x4db33, + BNXT_ULP_CLASS_HID_4d577 = 0x4d577, + BNXT_ULP_CLASS_HID_4e1ff = 0x4e1ff, + BNXT_ULP_CLASS_HID_4c873 = 0x4c873, + BNXT_ULP_CLASS_HID_4d4fb = 0x4d4fb, + BNXT_ULP_CLASS_HID_4ce3f = 0x4ce3f, + BNXT_ULP_CLASS_HID_4daa7 = 0x4daa7, + BNXT_ULP_CLASS_HID_4f2df = 0x4f2df, + BNXT_ULP_CLASS_HID_4ff47 = 0x4ff47, + BNXT_ULP_CLASS_HID_4f89b = 0x4f89b, + BNXT_ULP_CLASS_HID_4c503 = 0x4c503, + BNXT_ULP_CLASS_HID_1ff3b = 0x1ff3b, + BNXT_ULP_CLASS_HID_1cba3 = 0x1cba3, + BNXT_ULP_CLASS_HID_1c5e7 = 0x1c5e7, + BNXT_ULP_CLASS_HID_1d26f = 0x1d26f, + BNXT_ULP_CLASS_HID_1e987 = 0x1e987, + BNXT_ULP_CLASS_HID_1f60f = 0x1f60f, + BNXT_ULP_CLASS_HID_1f043 = 0x1f043, + BNXT_ULP_CLASS_HID_1fccb = 0x1fccb, BNXT_ULP_CLASS_HID_1c673 = 0x1c673, - BNXT_ULP_CLASS_HID_1e8b3 = 0x1e8b3, - BNXT_ULP_CLASS_HID_8e07 = 0x8e07, + BNXT_ULP_CLASS_HID_1d2fb = 0x1d2fb, + BNXT_ULP_CLASS_HID_1cc3f = 0x1cc3f, + BNXT_ULP_CLASS_HID_1d8a7 = 0x1d8a7, + BNXT_ULP_CLASS_HID_1cd2b = 0x1cd2b, + BNXT_ULP_CLASS_HID_1d993 = 0x1d993, + BNXT_ULP_CLASS_HID_1d3d7 = 0x1d3d7, + BNXT_ULP_CLASS_HID_1c303 = 0x1c303, + BNXT_ULP_CLASS_HID_5faef = 0x5faef, + BNXT_ULP_CLASS_HID_5c757 = 0x5c757, + BNXT_ULP_CLASS_HID_5c0ab = 0x5c0ab, + BNXT_ULP_CLASS_HID_5cd13 = 0x5cd13, + BNXT_ULP_CLASS_HID_5e54b = 0x5e54b, + BNXT_ULP_CLASS_HID_5f133 = 0x5f133, + BNXT_ULP_CLASS_HID_5eb77 = 0x5eb77, + BNXT_ULP_CLASS_HID_5f7ff = 0x5f7ff, + BNXT_ULP_CLASS_HID_5c127 = 0x5c127, + BNXT_ULP_CLASS_HID_5cdaf = 0x5cdaf, + BNXT_ULP_CLASS_HID_5c7e3 = 0x5c7e3, + BNXT_ULP_CLASS_HID_5d46b = 0x5d46b, + BNXT_ULP_CLASS_HID_5c8df = 0x5c8df, + BNXT_ULP_CLASS_HID_5d547 = 0x5d547, + BNXT_ULP_CLASS_HID_5ce9b = 0x5ce9b, + BNXT_ULP_CLASS_HID_5db03 = 0x5db03, + BNXT_ULP_CLASS_HID_a6fb = 0xa6fb, + BNXT_ULP_CLASS_HID_b363 = 0xb363, + BNXT_ULP_CLASS_HID_aca7 = 0xaca7, + BNXT_ULP_CLASS_HID_b92f = 0xb92f, BNXT_ULP_CLASS_HID_b147 = 0xb147, - BNXT_ULP_CLASS_HID_d387 = 0xd387, - BNXT_ULP_CLASS_HID_f6c7 = 0xf6c7, - BNXT_ULP_CLASS_HID_89cb = 0x89cb, - BNXT_ULP_CLASS_HID_ac0b = 0xac0b, - BNXT_ULP_CLASS_HID_cf4b = 0xcf4b, - BNXT_ULP_CLASS_HID_f18b = 0xf18b, - BNXT_ULP_CLASS_HID_19fcb = 0x19fcb, - BNXT_ULP_CLASS_HID_1a20b = 0x1a20b, - BNXT_ULP_CLASS_HID_1e54b = 0x1e54b, - BNXT_ULP_CLASS_HID_1e78b = 0x1e78b, - BNXT_ULP_CLASS_HID_1a407 = 0x1a407, - BNXT_ULP_CLASS_HID_1a747 = 0x1a747, - BNXT_ULP_CLASS_HID_1e987 = 0x1e987, - BNXT_ULP_CLASS_HID_1ecc7 = 0x1ecc7, - BNXT_ULP_CLASS_HID_b1ab = 0xb1ab, + BNXT_ULP_CLASS_HID_bdcf = 0xbdcf, + BNXT_ULP_CLASS_HID_b703 = 0xb703, + BNXT_ULP_CLASS_HID_a38b = 0xa38b, + BNXT_ULP_CLASS_HID_ea0f = 0xea0f, + BNXT_ULP_CLASS_HID_f6f7 = 0xf6f7, + BNXT_ULP_CLASS_HID_f0cb = 0xf0cb, + BNXT_ULP_CLASS_HID_a067 = 0xa067, BNXT_ULP_CLASS_HID_b4eb = 0xb4eb, - BNXT_ULP_CLASS_HID_f72b = 0xf72b, - BNXT_ULP_CLASS_HID_fa6b = 0xfa6b, - BNXT_ULP_CLASS_HID_ad5f = 0xad5f, - BNXT_ULP_CLASS_HID_af9f = 0xaf9f, - BNXT_ULP_CLASS_HID_f2df = 0xf2df, - BNXT_ULP_CLASS_HID_f51f = 0xf51f, - BNXT_ULP_CLASS_HID_1c35f = 0x1c35f, - BNXT_ULP_CLASS_HID_1e59f = 0x1e59f, - BNXT_ULP_CLASS_HID_1c8df = 0x1c8df, - BNXT_ULP_CLASS_HID_1eb1f = 0x1eb1f, - BNXT_ULP_CLASS_HID_1c7ab = 0x1c7ab, + BNXT_ULP_CLASS_HID_e153 = 0xe153, + BNXT_ULP_CLASS_HID_ba97 = 0xba97, + BNXT_ULP_CLASS_HID_e71f = 0xe71f, + BNXT_ULP_CLASS_HID_4a1af = 0x4a1af, + BNXT_ULP_CLASS_HID_4ae17 = 0x4ae17, + BNXT_ULP_CLASS_HID_4a86b = 0x4a86b, + BNXT_ULP_CLASS_HID_4b4d3 = 0x4b4d3, + BNXT_ULP_CLASS_HID_4ac0b = 0x4ac0b, + BNXT_ULP_CLASS_HID_4b8f3 = 0x4b8f3, + BNXT_ULP_CLASS_HID_4b237 = 0x4b237, + BNXT_ULP_CLASS_HID_4bebf = 0x4bebf, + BNXT_ULP_CLASS_HID_4e533 = 0x4e533, + BNXT_ULP_CLASS_HID_4f1bb = 0x4f1bb, + BNXT_ULP_CLASS_HID_4ebff = 0x4ebff, + BNXT_ULP_CLASS_HID_4f867 = 0x4f867, + BNXT_ULP_CLASS_HID_4af9f = 0x4af9f, + BNXT_ULP_CLASS_HID_4bc07 = 0x4bc07, + BNXT_ULP_CLASS_HID_4b65b = 0x4b65b, + BNXT_ULP_CLASS_HID_4e2c3 = 0x4e2c3, + BNXT_ULP_CLASS_HID_1bcfb = 0x1bcfb, + BNXT_ULP_CLASS_HID_1e963 = 0x1e963, + BNXT_ULP_CLASS_HID_1e2a7 = 0x1e2a7, + BNXT_ULP_CLASS_HID_1ef2f = 0x1ef2f, + BNXT_ULP_CLASS_HID_1a747 = 0x1a747, + BNXT_ULP_CLASS_HID_1b3cf = 0x1b3cf, + BNXT_ULP_CLASS_HID_1ad03 = 0x1ad03, + BNXT_ULP_CLASS_HID_1b98b = 0x1b98b, + BNXT_ULP_CLASS_HID_1a333 = 0x1a333, + BNXT_ULP_CLASS_HID_1afbb = 0x1afbb, + BNXT_ULP_CLASS_HID_1a9ff = 0x1a9ff, + BNXT_ULP_CLASS_HID_1b667 = 0x1b667, BNXT_ULP_CLASS_HID_1eaeb = 0x1eaeb, - BNXT_ULP_CLASS_HID_1cd2b = 0x1cd2b, - BNXT_ULP_CLASS_HID_1f06b = 0x1f06b, - BNXT_ULP_CLASS_HID_9177 = 0x9177, - BNXT_ULP_CLASS_HID_b3b7 = 0xb3b7, - BNXT_ULP_CLASS_HID_d6f7 = 0xd6f7, - BNXT_ULP_CLASS_HID_f937 = 0xf937, - BNXT_ULP_CLASS_HID_8c3b = 0x8c3b, - BNXT_ULP_CLASS_HID_af7b = 0xaf7b, - BNXT_ULP_CLASS_HID_d1bb = 0xd1bb, - BNXT_ULP_CLASS_HID_f4fb = 0xf4fb, - BNXT_ULP_CLASS_HID_1a23b = 0x1a23b, - BNXT_ULP_CLASS_HID_1a57b = 0x1a57b, - BNXT_ULP_CLASS_HID_1e7bb = 0x1e7bb, - BNXT_ULP_CLASS_HID_1eafb = 0x1eafb, - BNXT_ULP_CLASS_HID_1a777 = 0x1a777, - BNXT_ULP_CLASS_HID_1a9b7 = 0x1a9b7, - BNXT_ULP_CLASS_HID_1ecf7 = 0x1ecf7, - BNXT_ULP_CLASS_HID_1ef37 = 0x1ef37, + BNXT_ULP_CLASS_HID_1f753 = 0x1f753, + BNXT_ULP_CLASS_HID_1f097 = 0x1f097, + BNXT_ULP_CLASS_HID_1a0c3 = 0x1a0c3, + BNXT_ULP_CLASS_HID_5b7af = 0x5b7af, + BNXT_ULP_CLASS_HID_5e417 = 0x5e417, + BNXT_ULP_CLASS_HID_5be6b = 0x5be6b, + BNXT_ULP_CLASS_HID_5ead3 = 0x5ead3, + BNXT_ULP_CLASS_HID_5a20b = 0x5a20b, + BNXT_ULP_CLASS_HID_5aef3 = 0x5aef3, + BNXT_ULP_CLASS_HID_5a837 = 0x5a837, + BNXT_ULP_CLASS_HID_5b4bf = 0x5b4bf, + BNXT_ULP_CLASS_HID_5fb33 = 0x5fb33, + BNXT_ULP_CLASS_HID_5ab6f = 0x5ab6f, + BNXT_ULP_CLASS_HID_5a4a3 = 0x5a4a3, + BNXT_ULP_CLASS_HID_5b12b = 0x5b12b, + BNXT_ULP_CLASS_HID_5e59f = 0x5e59f, + BNXT_ULP_CLASS_HID_5f207 = 0x5f207, + BNXT_ULP_CLASS_HID_5ec5b = 0x5ec5b, + BNXT_ULP_CLASS_HID_5f8c3 = 0x5f8c3, + BNXT_ULP_CLASS_HID_ec7b = 0xec7b, + BNXT_ULP_CLASS_HID_f8e3 = 0xf8e3, + BNXT_ULP_CLASS_HID_f227 = 0xf227, + BNXT_ULP_CLASS_HID_feaf = 0xfeaf, + BNXT_ULP_CLASS_HID_f6c7 = 0xf6c7, + BNXT_ULP_CLASS_HID_e34f = 0xe34f, + BNXT_ULP_CLASS_HID_fc83 = 0xfc83, + BNXT_ULP_CLASS_HID_e90b = 0xe90b, + BNXT_ULP_CLASS_HID_ef8f = 0xef8f, + BNXT_ULP_CLASS_HID_fc77 = 0xfc77, + BNXT_ULP_CLASS_HID_f64b = 0xf64b, + BNXT_ULP_CLASS_HID_e5e7 = 0xe5e7, + BNXT_ULP_CLASS_HID_fa6b = 0xfa6b, + BNXT_ULP_CLASS_HID_e6d3 = 0xe6d3, + BNXT_ULP_CLASS_HID_e017 = 0xe017, + BNXT_ULP_CLASS_HID_ec9f = 0xec9f, + BNXT_ULP_CLASS_HID_4e72f = 0x4e72f, + BNXT_ULP_CLASS_HID_4f397 = 0x4f397, + BNXT_ULP_CLASS_HID_4edeb = 0x4edeb, + BNXT_ULP_CLASS_HID_4fa53 = 0x4fa53, + BNXT_ULP_CLASS_HID_4f18b = 0x4f18b, + BNXT_ULP_CLASS_HID_4fe73 = 0x4fe73, + BNXT_ULP_CLASS_HID_4f7b7 = 0x4f7b7, + BNXT_ULP_CLASS_HID_4e43f = 0x4e43f, + BNXT_ULP_CLASS_HID_4eab3 = 0x4eab3, + BNXT_ULP_CLASS_HID_4f73b = 0x4f73b, + BNXT_ULP_CLASS_HID_4f17f = 0x4f17f, + BNXT_ULP_CLASS_HID_4e0ab = 0x4e0ab, + BNXT_ULP_CLASS_HID_4f51f = 0x4f51f, + BNXT_ULP_CLASS_HID_4e187 = 0x4e187, + BNXT_ULP_CLASS_HID_4fbdb = 0x4fbdb, + BNXT_ULP_CLASS_HID_4e843 = 0x4e843, + BNXT_ULP_CLASS_HID_1e27b = 0x1e27b, + BNXT_ULP_CLASS_HID_1eee3 = 0x1eee3, + BNXT_ULP_CLASS_HID_1e827 = 0x1e827, + BNXT_ULP_CLASS_HID_1f4af = 0x1f4af, + BNXT_ULP_CLASS_HID_1ecc7 = 0x1ecc7, + BNXT_ULP_CLASS_HID_1f94f = 0x1f94f, + BNXT_ULP_CLASS_HID_1f283 = 0x1f283, + BNXT_ULP_CLASS_HID_1ff0b = 0x1ff0b, + BNXT_ULP_CLASS_HID_1e8b3 = 0x1e8b3, + BNXT_ULP_CLASS_HID_1f53b = 0x1f53b, + BNXT_ULP_CLASS_HID_1ef7f = 0x1ef7f, + BNXT_ULP_CLASS_HID_1fbe7 = 0x1fbe7, + BNXT_ULP_CLASS_HID_1f06b = 0x1f06b, + BNXT_ULP_CLASS_HID_1fcd3 = 0x1fcd3, + BNXT_ULP_CLASS_HID_1f617 = 0x1f617, + BNXT_ULP_CLASS_HID_1e643 = 0x1e643, + BNXT_ULP_CLASS_HID_5fd2f = 0x5fd2f, + BNXT_ULP_CLASS_HID_5e997 = 0x5e997, + BNXT_ULP_CLASS_HID_5e3eb = 0x5e3eb, + BNXT_ULP_CLASS_HID_5f053 = 0x5f053, + BNXT_ULP_CLASS_HID_5e78b = 0x5e78b, + BNXT_ULP_CLASS_HID_5f473 = 0x5f473, + BNXT_ULP_CLASS_HID_5edb7 = 0x5edb7, + BNXT_ULP_CLASS_HID_5fa3f = 0x5fa3f, + BNXT_ULP_CLASS_HID_5e467 = 0x5e467, + BNXT_ULP_CLASS_HID_5f0ef = 0x5f0ef, + BNXT_ULP_CLASS_HID_5ea23 = 0x5ea23, + BNXT_ULP_CLASS_HID_5f6ab = 0x5f6ab, + BNXT_ULP_CLASS_HID_5eb1f = 0x5eb1f, + BNXT_ULP_CLASS_HID_5f787 = 0x5f787, + BNXT_ULP_CLASS_HID_5f1db = 0x5f1db, + BNXT_ULP_CLASS_HID_5e177 = 0x5e177, + BNXT_ULP_CLASS_HID_498d = 0x498d, + BNXT_ULP_CLASS_HID_4fc9 = 0x4fc9, + BNXT_ULP_CLASS_HID_0cf9 = 0x0cf9, + BNXT_ULP_CLASS_HID_1335 = 0x1335, + BNXT_ULP_CLASS_HID_232d = 0x232d, + BNXT_ULP_CLASS_HID_2969 = 0x2969, + BNXT_ULP_CLASS_HID_4345 = 0x4345, + BNXT_ULP_CLASS_HID_4981 = 0x4981, + BNXT_ULP_CLASS_HID_45809 = 0x45809, + BNXT_ULP_CLASS_HID_40179 = 0x40179, + BNXT_ULP_CLASS_HID_431a9 = 0x431a9, + BNXT_ULP_CLASS_HID_437d5 = 0x437d5, + BNXT_ULP_CLASS_HID_44e61 = 0x44e61, + BNXT_ULP_CLASS_HID_454ad = 0x454ad, + BNXT_ULP_CLASS_HID_42801 = 0x42801, + BNXT_ULP_CLASS_HID_42e4d = 0x42e4d, + BNXT_ULP_CLASS_HID_22c13 = 0x22c13, + BNXT_ULP_CLASS_HID_2322f = 0x2322f, + BNXT_ULP_CLASS_HID_2164f = 0x2164f, + BNXT_ULP_CLASS_HID_21c8b = 0x21c8b, + BNXT_ULP_CLASS_HID_24f87 = 0x24f87, + BNXT_ULP_CLASS_HID_255c3 = 0x255c3, + BNXT_ULP_CLASS_HID_239e3 = 0x239e3, + BNXT_ULP_CLASS_HID_2403f = 0x2403f, + BNXT_ULP_CLASS_HID_218c3 = 0x218c3, + BNXT_ULP_CLASS_HID_21f1f = 0x21f1f, + BNXT_ULP_CLASS_HID_2033f = 0x2033f, + BNXT_ULP_CLASS_HID_2097b = 0x2097b, + BNXT_ULP_CLASS_HID_23c77 = 0x23c77, + BNXT_ULP_CLASS_HID_242b3 = 0x242b3, + BNXT_ULP_CLASS_HID_226d3 = 0x226d3, + BNXT_ULP_CLASS_HID_22cef = 0x22cef, + BNXT_ULP_CLASS_HID_62727 = 0x62727, + BNXT_ULP_CLASS_HID_62d63 = 0x62d63, + BNXT_ULP_CLASS_HID_61183 = 0x61183, + BNXT_ULP_CLASS_HID_617df = 0x617df, + BNXT_ULP_CLASS_HID_64adb = 0x64adb, + BNXT_ULP_CLASS_HID_65117 = 0x65117, + BNXT_ULP_CLASS_HID_63537 = 0x63537, + BNXT_ULP_CLASS_HID_63b73 = 0x63b73, + BNXT_ULP_CLASS_HID_61417 = 0x61417, + BNXT_ULP_CLASS_HID_61a53 = 0x61a53, + BNXT_ULP_CLASS_HID_65b3f = 0x65b3f, + BNXT_ULP_CLASS_HID_6048f = 0x6048f, + BNXT_ULP_CLASS_HID_6378b = 0x6378b, + BNXT_ULP_CLASS_HID_63dc7 = 0x63dc7, + BNXT_ULP_CLASS_HID_621e7 = 0x621e7, + BNXT_ULP_CLASS_HID_62823 = 0x62823, + BNXT_ULP_CLASS_HID_8b0b = 0x8b0b, + BNXT_ULP_CLASS_HID_9137 = 0x9137, + BNXT_ULP_CLASS_HID_d223 = 0xd223, + BNXT_ULP_CLASS_HID_d86f = 0xd86f, + BNXT_ULP_CLASS_HID_ae9f = 0xae9f, + BNXT_ULP_CLASS_HID_b4db = 0xb4db, + BNXT_ULP_CLASS_HID_98fb = 0x98fb, + BNXT_ULP_CLASS_HID_9f27 = 0x9f27, + BNXT_ULP_CLASS_HID_4863f = 0x4863f, + BNXT_ULP_CLASS_HID_48c7b = 0x48c7b, + BNXT_ULP_CLASS_HID_4cd57 = 0x4cd57, + BNXT_ULP_CLASS_HID_4d393 = 0x4d393, + BNXT_ULP_CLASS_HID_4a9c3 = 0x4a9c3, + BNXT_ULP_CLASS_HID_4b00f = 0x4b00f, + BNXT_ULP_CLASS_HID_4942f = 0x4942f, + BNXT_ULP_CLASS_HID_49a6b = 0x49a6b, + BNXT_ULP_CLASS_HID_1a10b = 0x1a10b, + BNXT_ULP_CLASS_HID_1a737 = 0x1a737, + BNXT_ULP_CLASS_HID_18b57 = 0x18b57, + BNXT_ULP_CLASS_HID_19193 = 0x19193, + BNXT_ULP_CLASS_HID_1c49f = 0x1c49f, + BNXT_ULP_CLASS_HID_1cadb = 0x1cadb, + BNXT_ULP_CLASS_HID_1aefb = 0x1aefb, + BNXT_ULP_CLASS_HID_1b527 = 0x1b527, + BNXT_ULP_CLASS_HID_59c3f = 0x59c3f, + BNXT_ULP_CLASS_HID_5a27b = 0x5a27b, + BNXT_ULP_CLASS_HID_5869b = 0x5869b, + BNXT_ULP_CLASS_HID_58cc7 = 0x58cc7, + BNXT_ULP_CLASS_HID_5bfc3 = 0x5bfc3, + BNXT_ULP_CLASS_HID_5c60f = 0x5c60f, + BNXT_ULP_CLASS_HID_5aa2f = 0x5aa2f, + BNXT_ULP_CLASS_HID_5b06b = 0x5b06b, + BNXT_ULP_CLASS_HID_49ad = 0x49ad, + BNXT_ULP_CLASS_HID_4fe9 = 0x4fe9, + BNXT_ULP_CLASS_HID_0cd9 = 0x0cd9, + BNXT_ULP_CLASS_HID_1315 = 0x1315, + BNXT_ULP_CLASS_HID_230d = 0x230d, + BNXT_ULP_CLASS_HID_2949 = 0x2949, + BNXT_ULP_CLASS_HID_4365 = 0x4365, + BNXT_ULP_CLASS_HID_49a1 = 0x49a1, + BNXT_ULP_CLASS_HID_4035 = 0x4035, + BNXT_ULP_CLASS_HID_4671 = 0x4671, + BNXT_ULP_CLASS_HID_0361 = 0x0361, + BNXT_ULP_CLASS_HID_09bd = 0x09bd, + BNXT_ULP_CLASS_HID_1995 = 0x1995, + BNXT_ULP_CLASS_HID_1fd1 = 0x1fd1, + BNXT_ULP_CLASS_HID_398d = 0x398d, + BNXT_ULP_CLASS_HID_3fc9 = 0x3fc9, + BNXT_ULP_CLASS_HID_444e1 = 0x444e1, + BNXT_ULP_CLASS_HID_44b3d = 0x44b3d, + BNXT_ULP_CLASS_HID_4082d = 0x4082d, + BNXT_ULP_CLASS_HID_40e69 = 0x40e69, + BNXT_ULP_CLASS_HID_41e41 = 0x41e41, + BNXT_ULP_CLASS_HID_4249d = 0x4249d, + BNXT_ULP_CLASS_HID_43eb9 = 0x43eb9, + BNXT_ULP_CLASS_HID_444f5 = 0x444f5, + BNXT_ULP_CLASS_HID_43b09 = 0x43b09, + BNXT_ULP_CLASS_HID_44145 = 0x44145, + BNXT_ULP_CLASS_HID_45b61 = 0x45b61, + BNXT_ULP_CLASS_HID_404f1 = 0x404f1, + BNXT_ULP_CLASS_HID_414e9 = 0x414e9, + BNXT_ULP_CLASS_HID_41b25 = 0x41b25, + BNXT_ULP_CLASS_HID_434c1 = 0x434c1, + BNXT_ULP_CLASS_HID_43b1d = 0x43b1d, + BNXT_ULP_CLASS_HID_45829 = 0x45829, + BNXT_ULP_CLASS_HID_40159 = 0x40159, + BNXT_ULP_CLASS_HID_43189 = 0x43189, + BNXT_ULP_CLASS_HID_437f5 = 0x437f5, + BNXT_ULP_CLASS_HID_44e41 = 0x44e41, + BNXT_ULP_CLASS_HID_4548d = 0x4548d, + BNXT_ULP_CLASS_HID_42821 = 0x42821, + BNXT_ULP_CLASS_HID_42e6d = 0x42e6d, + BNXT_ULP_CLASS_HID_6271d = 0x6271d, + BNXT_ULP_CLASS_HID_62d59 = 0x62d59, + BNXT_ULP_CLASS_HID_600fd = 0x600fd, + BNXT_ULP_CLASS_HID_60739 = 0x60739, + BNXT_ULP_CLASS_HID_61db5 = 0x61db5, + BNXT_ULP_CLASS_HID_623f1 = 0x623f1, + BNXT_ULP_CLASS_HID_65421 = 0x65421, + BNXT_ULP_CLASS_HID_65a6d = 0x65a6d, + BNXT_ULP_CLASS_HID_5111d = 0x5111d, + BNXT_ULP_CLASS_HID_51759 = 0x51759, + BNXT_ULP_CLASS_HID_54789 = 0x54789, + BNXT_ULP_CLASS_HID_54df5 = 0x54df5, + BNXT_ULP_CLASS_HID_507b5 = 0x507b5, + BNXT_ULP_CLASS_HID_50df1 = 0x50df1, + BNXT_ULP_CLASS_HID_53e21 = 0x53e21, + BNXT_ULP_CLASS_HID_5446d = 0x5446d, + BNXT_ULP_CLASS_HID_73d1d = 0x73d1d, + BNXT_ULP_CLASS_HID_74359 = 0x74359, + BNXT_ULP_CLASS_HID_716fd = 0x716fd, + BNXT_ULP_CLASS_HID_71d39 = 0x71d39, + BNXT_ULP_CLASS_HID_733b5 = 0x733b5, + BNXT_ULP_CLASS_HID_739f1 = 0x739f1, + BNXT_ULP_CLASS_HID_70d15 = 0x70d15, + BNXT_ULP_CLASS_HID_71351 = 0x71351, + BNXT_ULP_CLASS_HID_49cd = 0x49cd, + BNXT_ULP_CLASS_HID_4f89 = 0x4f89, + BNXT_ULP_CLASS_HID_0cb9 = 0x0cb9, + BNXT_ULP_CLASS_HID_1375 = 0x1375, + BNXT_ULP_CLASS_HID_236d = 0x236d, + BNXT_ULP_CLASS_HID_2929 = 0x2929, + BNXT_ULP_CLASS_HID_4305 = 0x4305, + BNXT_ULP_CLASS_HID_49c1 = 0x49c1, + BNXT_ULP_CLASS_HID_4055 = 0x4055, + BNXT_ULP_CLASS_HID_4611 = 0x4611, + BNXT_ULP_CLASS_HID_0301 = 0x0301, + BNXT_ULP_CLASS_HID_09dd = 0x09dd, + BNXT_ULP_CLASS_HID_19f5 = 0x19f5, + BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1, + BNXT_ULP_CLASS_HID_39ed = 0x39ed, + BNXT_ULP_CLASS_HID_3fa9 = 0x3fa9, + BNXT_ULP_CLASS_HID_44481 = 0x44481, + BNXT_ULP_CLASS_HID_44b5d = 0x44b5d, + BNXT_ULP_CLASS_HID_4084d = 0x4084d, + BNXT_ULP_CLASS_HID_40e09 = 0x40e09, + BNXT_ULP_CLASS_HID_41e21 = 0x41e21, + BNXT_ULP_CLASS_HID_424fd = 0x424fd, + BNXT_ULP_CLASS_HID_43ed9 = 0x43ed9, + BNXT_ULP_CLASS_HID_44495 = 0x44495, + BNXT_ULP_CLASS_HID_43b69 = 0x43b69, + BNXT_ULP_CLASS_HID_44125 = 0x44125, + BNXT_ULP_CLASS_HID_45b01 = 0x45b01, + BNXT_ULP_CLASS_HID_40491 = 0x40491, + BNXT_ULP_CLASS_HID_41489 = 0x41489, + BNXT_ULP_CLASS_HID_41b45 = 0x41b45, + BNXT_ULP_CLASS_HID_434a1 = 0x434a1, + BNXT_ULP_CLASS_HID_43b7d = 0x43b7d, + BNXT_ULP_CLASS_HID_45849 = 0x45849, + BNXT_ULP_CLASS_HID_40139 = 0x40139, + BNXT_ULP_CLASS_HID_431e9 = 0x431e9, + BNXT_ULP_CLASS_HID_43795 = 0x43795, + BNXT_ULP_CLASS_HID_44e21 = 0x44e21, + BNXT_ULP_CLASS_HID_454ed = 0x454ed, + BNXT_ULP_CLASS_HID_42841 = 0x42841, + BNXT_ULP_CLASS_HID_42e0d = 0x42e0d, + BNXT_ULP_CLASS_HID_6277d = 0x6277d, + BNXT_ULP_CLASS_HID_62d39 = 0x62d39, + BNXT_ULP_CLASS_HID_6009d = 0x6009d, + BNXT_ULP_CLASS_HID_60759 = 0x60759, + BNXT_ULP_CLASS_HID_61dd5 = 0x61dd5, + BNXT_ULP_CLASS_HID_62391 = 0x62391, + BNXT_ULP_CLASS_HID_65441 = 0x65441, + BNXT_ULP_CLASS_HID_65a0d = 0x65a0d, + BNXT_ULP_CLASS_HID_5117d = 0x5117d, + BNXT_ULP_CLASS_HID_51739 = 0x51739, + BNXT_ULP_CLASS_HID_547e9 = 0x547e9, + BNXT_ULP_CLASS_HID_54d95 = 0x54d95, + BNXT_ULP_CLASS_HID_507d5 = 0x507d5, + BNXT_ULP_CLASS_HID_50d91 = 0x50d91, + BNXT_ULP_CLASS_HID_53e41 = 0x53e41, + BNXT_ULP_CLASS_HID_5440d = 0x5440d, + BNXT_ULP_CLASS_HID_73d7d = 0x73d7d, + BNXT_ULP_CLASS_HID_74339 = 0x74339, + BNXT_ULP_CLASS_HID_7169d = 0x7169d, + BNXT_ULP_CLASS_HID_71d59 = 0x71d59, + BNXT_ULP_CLASS_HID_733d5 = 0x733d5, + BNXT_ULP_CLASS_HID_73991 = 0x73991, + BNXT_ULP_CLASS_HID_70d75 = 0x70d75, + BNXT_ULP_CLASS_HID_71331 = 0x71331, + BNXT_ULP_CLASS_HID_22c33 = 0x22c33, + BNXT_ULP_CLASS_HID_2320f = 0x2320f, + BNXT_ULP_CLASS_HID_2166f = 0x2166f, + BNXT_ULP_CLASS_HID_21cab = 0x21cab, + BNXT_ULP_CLASS_HID_24fa7 = 0x24fa7, + BNXT_ULP_CLASS_HID_255e3 = 0x255e3, + BNXT_ULP_CLASS_HID_239c3 = 0x239c3, + BNXT_ULP_CLASS_HID_2401f = 0x2401f, + BNXT_ULP_CLASS_HID_218e3 = 0x218e3, + BNXT_ULP_CLASS_HID_21f3f = 0x21f3f, + BNXT_ULP_CLASS_HID_2031f = 0x2031f, + BNXT_ULP_CLASS_HID_2095b = 0x2095b, + BNXT_ULP_CLASS_HID_23c57 = 0x23c57, + BNXT_ULP_CLASS_HID_24293 = 0x24293, + BNXT_ULP_CLASS_HID_226f3 = 0x226f3, + BNXT_ULP_CLASS_HID_22ccf = 0x22ccf, + BNXT_ULP_CLASS_HID_62707 = 0x62707, + BNXT_ULP_CLASS_HID_62d43 = 0x62d43, + BNXT_ULP_CLASS_HID_611a3 = 0x611a3, + BNXT_ULP_CLASS_HID_617ff = 0x617ff, + BNXT_ULP_CLASS_HID_64afb = 0x64afb, + BNXT_ULP_CLASS_HID_65137 = 0x65137, + BNXT_ULP_CLASS_HID_63517 = 0x63517, + BNXT_ULP_CLASS_HID_63b53 = 0x63b53, + BNXT_ULP_CLASS_HID_61437 = 0x61437, + BNXT_ULP_CLASS_HID_61a73 = 0x61a73, + BNXT_ULP_CLASS_HID_65b1f = 0x65b1f, + BNXT_ULP_CLASS_HID_604af = 0x604af, + BNXT_ULP_CLASS_HID_637ab = 0x637ab, + BNXT_ULP_CLASS_HID_63de7 = 0x63de7, + BNXT_ULP_CLASS_HID_621c7 = 0x621c7, + BNXT_ULP_CLASS_HID_62803 = 0x62803, + BNXT_ULP_CLASS_HID_34233 = 0x34233, + BNXT_ULP_CLASS_HID_3480f = 0x3480f, + BNXT_ULP_CLASS_HID_32c6f = 0x32c6f, + BNXT_ULP_CLASS_HID_332ab = 0x332ab, + BNXT_ULP_CLASS_HID_308fb = 0x308fb, + BNXT_ULP_CLASS_HID_30f37 = 0x30f37, + BNXT_ULP_CLASS_HID_34fc3 = 0x34fc3, + BNXT_ULP_CLASS_HID_3561f = 0x3561f, + BNXT_ULP_CLASS_HID_32ee3 = 0x32ee3, + BNXT_ULP_CLASS_HID_3353f = 0x3353f, + BNXT_ULP_CLASS_HID_3191f = 0x3191f, + BNXT_ULP_CLASS_HID_31f5b = 0x31f5b, + BNXT_ULP_CLASS_HID_35257 = 0x35257, + BNXT_ULP_CLASS_HID_35893 = 0x35893, + BNXT_ULP_CLASS_HID_33cf3 = 0x33cf3, + BNXT_ULP_CLASS_HID_342cf = 0x342cf, + BNXT_ULP_CLASS_HID_73d07 = 0x73d07, + BNXT_ULP_CLASS_HID_74343 = 0x74343, + BNXT_ULP_CLASS_HID_727a3 = 0x727a3, + BNXT_ULP_CLASS_HID_72dff = 0x72dff, + BNXT_ULP_CLASS_HID_703cf = 0x703cf, + BNXT_ULP_CLASS_HID_70a0b = 0x70a0b, + BNXT_ULP_CLASS_HID_74b17 = 0x74b17, + BNXT_ULP_CLASS_HID_75153 = 0x75153, + BNXT_ULP_CLASS_HID_72a37 = 0x72a37, + BNXT_ULP_CLASS_HID_73073 = 0x73073, + BNXT_ULP_CLASS_HID_71453 = 0x71453, + BNXT_ULP_CLASS_HID_71aaf = 0x71aaf, + BNXT_ULP_CLASS_HID_74dab = 0x74dab, + BNXT_ULP_CLASS_HID_753e7 = 0x753e7, + BNXT_ULP_CLASS_HID_737c7 = 0x737c7, + BNXT_ULP_CLASS_HID_73e03 = 0x73e03, + BNXT_ULP_CLASS_HID_2b733 = 0x2b733, + BNXT_ULP_CLASS_HID_2bd0f = 0x2bd0f, + BNXT_ULP_CLASS_HID_2a16f = 0x2a16f, + BNXT_ULP_CLASS_HID_2a7ab = 0x2a7ab, + BNXT_ULP_CLASS_HID_2daa7 = 0x2daa7, + BNXT_ULP_CLASS_HID_28437 = 0x28437, + BNXT_ULP_CLASS_HID_2c4c3 = 0x2c4c3, + BNXT_ULP_CLASS_HID_2cb1f = 0x2cb1f, + BNXT_ULP_CLASS_HID_2a3e3 = 0x2a3e3, + BNXT_ULP_CLASS_HID_2aa3f = 0x2aa3f, + BNXT_ULP_CLASS_HID_28e1f = 0x28e1f, + BNXT_ULP_CLASS_HID_2945b = 0x2945b, + BNXT_ULP_CLASS_HID_2c757 = 0x2c757, + BNXT_ULP_CLASS_HID_2cd93 = 0x2cd93, + BNXT_ULP_CLASS_HID_2b1f3 = 0x2b1f3, + BNXT_ULP_CLASS_HID_2b7cf = 0x2b7cf, + BNXT_ULP_CLASS_HID_6b207 = 0x6b207, + BNXT_ULP_CLASS_HID_6b843 = 0x6b843, + BNXT_ULP_CLASS_HID_69ca3 = 0x69ca3, + BNXT_ULP_CLASS_HID_6a2ff = 0x6a2ff, + BNXT_ULP_CLASS_HID_6d5fb = 0x6d5fb, + BNXT_ULP_CLASS_HID_6dc37 = 0x6dc37, + BNXT_ULP_CLASS_HID_6c017 = 0x6c017, + BNXT_ULP_CLASS_HID_6c653 = 0x6c653, + BNXT_ULP_CLASS_HID_69f37 = 0x69f37, + BNXT_ULP_CLASS_HID_6a573 = 0x6a573, + BNXT_ULP_CLASS_HID_68953 = 0x68953, + BNXT_ULP_CLASS_HID_68faf = 0x68faf, + BNXT_ULP_CLASS_HID_6c2ab = 0x6c2ab, + BNXT_ULP_CLASS_HID_6c8e7 = 0x6c8e7, + BNXT_ULP_CLASS_HID_6acc7 = 0x6acc7, + BNXT_ULP_CLASS_HID_6b303 = 0x6b303, + BNXT_ULP_CLASS_HID_3cd33 = 0x3cd33, + BNXT_ULP_CLASS_HID_3d30f = 0x3d30f, + BNXT_ULP_CLASS_HID_3b76f = 0x3b76f, + BNXT_ULP_CLASS_HID_3bdab = 0x3bdab, + BNXT_ULP_CLASS_HID_393fb = 0x393fb, + BNXT_ULP_CLASS_HID_39a37 = 0x39a37, + BNXT_ULP_CLASS_HID_3dac3 = 0x3dac3, + BNXT_ULP_CLASS_HID_38453 = 0x38453, + BNXT_ULP_CLASS_HID_3b9e3 = 0x3b9e3, + BNXT_ULP_CLASS_HID_3c03f = 0x3c03f, + BNXT_ULP_CLASS_HID_3a41f = 0x3a41f, + BNXT_ULP_CLASS_HID_3aa5b = 0x3aa5b, + BNXT_ULP_CLASS_HID_380ab = 0x380ab, + BNXT_ULP_CLASS_HID_386e7 = 0x386e7, + BNXT_ULP_CLASS_HID_3c7f3 = 0x3c7f3, + BNXT_ULP_CLASS_HID_3cdcf = 0x3cdcf, + BNXT_ULP_CLASS_HID_7c807 = 0x7c807, + BNXT_ULP_CLASS_HID_7ce43 = 0x7ce43, + BNXT_ULP_CLASS_HID_7b2a3 = 0x7b2a3, + BNXT_ULP_CLASS_HID_7b8ff = 0x7b8ff, + BNXT_ULP_CLASS_HID_78ecf = 0x78ecf, + BNXT_ULP_CLASS_HID_7950b = 0x7950b, + BNXT_ULP_CLASS_HID_7d617 = 0x7d617, + BNXT_ULP_CLASS_HID_7dc53 = 0x7dc53, + BNXT_ULP_CLASS_HID_7b537 = 0x7b537, + BNXT_ULP_CLASS_HID_7bb73 = 0x7bb73, + BNXT_ULP_CLASS_HID_79f53 = 0x79f53, + BNXT_ULP_CLASS_HID_7a5af = 0x7a5af, + BNXT_ULP_CLASS_HID_7d8ab = 0x7d8ab, + BNXT_ULP_CLASS_HID_7823b = 0x7823b, + BNXT_ULP_CLASS_HID_7c2c7 = 0x7c2c7, + BNXT_ULP_CLASS_HID_7c903 = 0x7c903, + BNXT_ULP_CLASS_HID_8b2b = 0x8b2b, + BNXT_ULP_CLASS_HID_9117 = 0x9117, + BNXT_ULP_CLASS_HID_d203 = 0xd203, + BNXT_ULP_CLASS_HID_d84f = 0xd84f, + BNXT_ULP_CLASS_HID_aebf = 0xaebf, + BNXT_ULP_CLASS_HID_b4fb = 0xb4fb, + BNXT_ULP_CLASS_HID_98db = 0x98db, + BNXT_ULP_CLASS_HID_9f07 = 0x9f07, + BNXT_ULP_CLASS_HID_4861f = 0x4861f, + BNXT_ULP_CLASS_HID_48c5b = 0x48c5b, + BNXT_ULP_CLASS_HID_4cd77 = 0x4cd77, + BNXT_ULP_CLASS_HID_4d3b3 = 0x4d3b3, + BNXT_ULP_CLASS_HID_4a9e3 = 0x4a9e3, + BNXT_ULP_CLASS_HID_4b02f = 0x4b02f, + BNXT_ULP_CLASS_HID_4940f = 0x4940f, + BNXT_ULP_CLASS_HID_49a4b = 0x49a4b, + BNXT_ULP_CLASS_HID_1a12b = 0x1a12b, + BNXT_ULP_CLASS_HID_1a717 = 0x1a717, + BNXT_ULP_CLASS_HID_18b77 = 0x18b77, + BNXT_ULP_CLASS_HID_191b3 = 0x191b3, + BNXT_ULP_CLASS_HID_1c4bf = 0x1c4bf, + BNXT_ULP_CLASS_HID_1cafb = 0x1cafb, + BNXT_ULP_CLASS_HID_1aedb = 0x1aedb, + BNXT_ULP_CLASS_HID_1b507 = 0x1b507, + BNXT_ULP_CLASS_HID_59c1f = 0x59c1f, + BNXT_ULP_CLASS_HID_5a25b = 0x5a25b, + BNXT_ULP_CLASS_HID_586bb = 0x586bb, + BNXT_ULP_CLASS_HID_58ce7 = 0x58ce7, + BNXT_ULP_CLASS_HID_5bfe3 = 0x5bfe3, + BNXT_ULP_CLASS_HID_5c62f = 0x5c62f, + BNXT_ULP_CLASS_HID_5aa0f = 0x5aa0f, + BNXT_ULP_CLASS_HID_5b04b = 0x5b04b, + BNXT_ULP_CLASS_HID_d0ab = 0xd0ab, + BNXT_ULP_CLASS_HID_d697 = 0xd697, + BNXT_ULP_CLASS_HID_d783 = 0xd783, + BNXT_ULP_CLASS_HID_c133 = 0xc133, + BNXT_ULP_CLASS_HID_f43f = 0xf43f, + BNXT_ULP_CLASS_HID_fa7b = 0xfa7b, + BNXT_ULP_CLASS_HID_de5b = 0xde5b, + BNXT_ULP_CLASS_HID_e487 = 0xe487, + BNXT_ULP_CLASS_HID_4cb9f = 0x4cb9f, + BNXT_ULP_CLASS_HID_4d1db = 0x4d1db, + BNXT_ULP_CLASS_HID_4d2f7 = 0x4d2f7, + BNXT_ULP_CLASS_HID_4d933 = 0x4d933, + BNXT_ULP_CLASS_HID_4ef63 = 0x4ef63, + BNXT_ULP_CLASS_HID_4f5af = 0x4f5af, + BNXT_ULP_CLASS_HID_4d98f = 0x4d98f, + BNXT_ULP_CLASS_HID_4dfcb = 0x4dfcb, + BNXT_ULP_CLASS_HID_1e6ab = 0x1e6ab, + BNXT_ULP_CLASS_HID_1ec97 = 0x1ec97, + BNXT_ULP_CLASS_HID_1d0f7 = 0x1d0f7, + BNXT_ULP_CLASS_HID_1d733 = 0x1d733, + BNXT_ULP_CLASS_HID_1ca3f = 0x1ca3f, + BNXT_ULP_CLASS_HID_1d07b = 0x1d07b, + BNXT_ULP_CLASS_HID_1f45b = 0x1f45b, + BNXT_ULP_CLASS_HID_1fa87 = 0x1fa87, + BNXT_ULP_CLASS_HID_5e19f = 0x5e19f, + BNXT_ULP_CLASS_HID_5e7db = 0x5e7db, + BNXT_ULP_CLASS_HID_5cc3b = 0x5cc3b, + BNXT_ULP_CLASS_HID_5d267 = 0x5d267, + BNXT_ULP_CLASS_HID_5c563 = 0x5c563, + BNXT_ULP_CLASS_HID_5cbaf = 0x5cbaf, + BNXT_ULP_CLASS_HID_5ef8f = 0x5ef8f, + BNXT_ULP_CLASS_HID_5f5cb = 0x5f5cb, + BNXT_ULP_CLASS_HID_adeb = 0xadeb, + BNXT_ULP_CLASS_HID_b3d7 = 0xb3d7, + BNXT_ULP_CLASS_HID_f4c3 = 0xf4c3, + BNXT_ULP_CLASS_HID_fb0f = 0xfb0f, + BNXT_ULP_CLASS_HID_b17f = 0xb17f, + BNXT_ULP_CLASS_HID_b7bb = 0xb7bb, + BNXT_ULP_CLASS_HID_bb9b = 0xbb9b, + BNXT_ULP_CLASS_HID_a1c7 = 0xa1c7, + BNXT_ULP_CLASS_HID_4a8df = 0x4a8df, + BNXT_ULP_CLASS_HID_4af1b = 0x4af1b, + BNXT_ULP_CLASS_HID_4f037 = 0x4f037, + BNXT_ULP_CLASS_HID_4f673 = 0x4f673, + BNXT_ULP_CLASS_HID_4aca3 = 0x4aca3, + BNXT_ULP_CLASS_HID_4b2ef = 0x4b2ef, + BNXT_ULP_CLASS_HID_4b6cf = 0x4b6cf, + BNXT_ULP_CLASS_HID_4bd0b = 0x4bd0b, + BNXT_ULP_CLASS_HID_1a3eb = 0x1a3eb, + BNXT_ULP_CLASS_HID_1a9d7 = 0x1a9d7, + BNXT_ULP_CLASS_HID_1ae37 = 0x1ae37, + BNXT_ULP_CLASS_HID_1b473 = 0x1b473, + BNXT_ULP_CLASS_HID_1e77f = 0x1e77f, + BNXT_ULP_CLASS_HID_1edbb = 0x1edbb, + BNXT_ULP_CLASS_HID_1b19b = 0x1b19b, + BNXT_ULP_CLASS_HID_1b7c7 = 0x1b7c7, + BNXT_ULP_CLASS_HID_5bedf = 0x5bedf, + BNXT_ULP_CLASS_HID_5a51b = 0x5a51b, + BNXT_ULP_CLASS_HID_5a97b = 0x5a97b, + BNXT_ULP_CLASS_HID_5afa7 = 0x5afa7, + BNXT_ULP_CLASS_HID_5e2a3 = 0x5e2a3, + BNXT_ULP_CLASS_HID_5e8ef = 0x5e8ef, + BNXT_ULP_CLASS_HID_5accf = 0x5accf, + BNXT_ULP_CLASS_HID_5b30b = 0x5b30b, + BNXT_ULP_CLASS_HID_f36b = 0xf36b, + BNXT_ULP_CLASS_HID_f957 = 0xf957, + BNXT_ULP_CLASS_HID_fa43 = 0xfa43, + BNXT_ULP_CLASS_HID_e3f3 = 0xe3f3, + BNXT_ULP_CLASS_HID_f6ff = 0xf6ff, + BNXT_ULP_CLASS_HID_fd3b = 0xfd3b, + BNXT_ULP_CLASS_HID_e11b = 0xe11b, + BNXT_ULP_CLASS_HID_e747 = 0xe747, + BNXT_ULP_CLASS_HID_4ee5f = 0x4ee5f, + BNXT_ULP_CLASS_HID_4f49b = 0x4f49b, + BNXT_ULP_CLASS_HID_4f5b7 = 0x4f5b7, + BNXT_ULP_CLASS_HID_4fbf3 = 0x4fbf3, + BNXT_ULP_CLASS_HID_4f223 = 0x4f223, + BNXT_ULP_CLASS_HID_4f86f = 0x4f86f, + BNXT_ULP_CLASS_HID_4fc4f = 0x4fc4f, + BNXT_ULP_CLASS_HID_4e28b = 0x4e28b, + BNXT_ULP_CLASS_HID_1e96b = 0x1e96b, + BNXT_ULP_CLASS_HID_1ef57 = 0x1ef57, + BNXT_ULP_CLASS_HID_1f3b7 = 0x1f3b7, + BNXT_ULP_CLASS_HID_1f9f3 = 0x1f9f3, + BNXT_ULP_CLASS_HID_1ecff = 0x1ecff, + BNXT_ULP_CLASS_HID_1f33b = 0x1f33b, + BNXT_ULP_CLASS_HID_1f71b = 0x1f71b, + BNXT_ULP_CLASS_HID_1fd47 = 0x1fd47, + BNXT_ULP_CLASS_HID_5e45f = 0x5e45f, + BNXT_ULP_CLASS_HID_5ea9b = 0x5ea9b, + BNXT_ULP_CLASS_HID_5eefb = 0x5eefb, + BNXT_ULP_CLASS_HID_5f527 = 0x5f527, + BNXT_ULP_CLASS_HID_5e823 = 0x5e823, + BNXT_ULP_CLASS_HID_5ee6f = 0x5ee6f, + BNXT_ULP_CLASS_HID_5f24f = 0x5f24f, + BNXT_ULP_CLASS_HID_5f88b = 0x5f88b, + BNXT_ULP_CLASS_HID_22c53 = 0x22c53, + BNXT_ULP_CLASS_HID_2326f = 0x2326f, + BNXT_ULP_CLASS_HID_2160f = 0x2160f, + BNXT_ULP_CLASS_HID_21ccb = 0x21ccb, + BNXT_ULP_CLASS_HID_24fc7 = 0x24fc7, + BNXT_ULP_CLASS_HID_25583 = 0x25583, + BNXT_ULP_CLASS_HID_239a3 = 0x239a3, + BNXT_ULP_CLASS_HID_2407f = 0x2407f, + BNXT_ULP_CLASS_HID_21883 = 0x21883, + BNXT_ULP_CLASS_HID_21f5f = 0x21f5f, + BNXT_ULP_CLASS_HID_2037f = 0x2037f, + BNXT_ULP_CLASS_HID_2093b = 0x2093b, + BNXT_ULP_CLASS_HID_23c37 = 0x23c37, + BNXT_ULP_CLASS_HID_242f3 = 0x242f3, + BNXT_ULP_CLASS_HID_22693 = 0x22693, + BNXT_ULP_CLASS_HID_22caf = 0x22caf, + BNXT_ULP_CLASS_HID_62767 = 0x62767, + BNXT_ULP_CLASS_HID_62d23 = 0x62d23, + BNXT_ULP_CLASS_HID_611c3 = 0x611c3, + BNXT_ULP_CLASS_HID_6179f = 0x6179f, + BNXT_ULP_CLASS_HID_64a9b = 0x64a9b, + BNXT_ULP_CLASS_HID_65157 = 0x65157, + BNXT_ULP_CLASS_HID_63577 = 0x63577, + BNXT_ULP_CLASS_HID_63b33 = 0x63b33, + BNXT_ULP_CLASS_HID_61457 = 0x61457, + BNXT_ULP_CLASS_HID_61a13 = 0x61a13, + BNXT_ULP_CLASS_HID_65b7f = 0x65b7f, + BNXT_ULP_CLASS_HID_604cf = 0x604cf, + BNXT_ULP_CLASS_HID_637cb = 0x637cb, + BNXT_ULP_CLASS_HID_63d87 = 0x63d87, + BNXT_ULP_CLASS_HID_621a7 = 0x621a7, + BNXT_ULP_CLASS_HID_62863 = 0x62863, + BNXT_ULP_CLASS_HID_34253 = 0x34253, + BNXT_ULP_CLASS_HID_3486f = 0x3486f, + BNXT_ULP_CLASS_HID_32c0f = 0x32c0f, + BNXT_ULP_CLASS_HID_332cb = 0x332cb, + BNXT_ULP_CLASS_HID_3089b = 0x3089b, + BNXT_ULP_CLASS_HID_30f57 = 0x30f57, + BNXT_ULP_CLASS_HID_34fa3 = 0x34fa3, + BNXT_ULP_CLASS_HID_3567f = 0x3567f, + BNXT_ULP_CLASS_HID_32e83 = 0x32e83, + BNXT_ULP_CLASS_HID_3355f = 0x3355f, + BNXT_ULP_CLASS_HID_3197f = 0x3197f, + BNXT_ULP_CLASS_HID_31f3b = 0x31f3b, + BNXT_ULP_CLASS_HID_35237 = 0x35237, + BNXT_ULP_CLASS_HID_358f3 = 0x358f3, + BNXT_ULP_CLASS_HID_33c93 = 0x33c93, + BNXT_ULP_CLASS_HID_342af = 0x342af, + BNXT_ULP_CLASS_HID_73d67 = 0x73d67, + BNXT_ULP_CLASS_HID_74323 = 0x74323, + BNXT_ULP_CLASS_HID_727c3 = 0x727c3, + BNXT_ULP_CLASS_HID_72d9f = 0x72d9f, + BNXT_ULP_CLASS_HID_703af = 0x703af, + BNXT_ULP_CLASS_HID_70a6b = 0x70a6b, + BNXT_ULP_CLASS_HID_74b77 = 0x74b77, + BNXT_ULP_CLASS_HID_75133 = 0x75133, + BNXT_ULP_CLASS_HID_72a57 = 0x72a57, + BNXT_ULP_CLASS_HID_73013 = 0x73013, + BNXT_ULP_CLASS_HID_71433 = 0x71433, + BNXT_ULP_CLASS_HID_71acf = 0x71acf, + BNXT_ULP_CLASS_HID_74dcb = 0x74dcb, + BNXT_ULP_CLASS_HID_75387 = 0x75387, + BNXT_ULP_CLASS_HID_737a7 = 0x737a7, + BNXT_ULP_CLASS_HID_73e63 = 0x73e63, + BNXT_ULP_CLASS_HID_2b753 = 0x2b753, + BNXT_ULP_CLASS_HID_2bd6f = 0x2bd6f, + BNXT_ULP_CLASS_HID_2a10f = 0x2a10f, + BNXT_ULP_CLASS_HID_2a7cb = 0x2a7cb, + BNXT_ULP_CLASS_HID_2dac7 = 0x2dac7, + BNXT_ULP_CLASS_HID_28457 = 0x28457, + BNXT_ULP_CLASS_HID_2c4a3 = 0x2c4a3, + BNXT_ULP_CLASS_HID_2cb7f = 0x2cb7f, + BNXT_ULP_CLASS_HID_2a383 = 0x2a383, + BNXT_ULP_CLASS_HID_2aa5f = 0x2aa5f, + BNXT_ULP_CLASS_HID_28e7f = 0x28e7f, + BNXT_ULP_CLASS_HID_2943b = 0x2943b, + BNXT_ULP_CLASS_HID_2c737 = 0x2c737, + BNXT_ULP_CLASS_HID_2cdf3 = 0x2cdf3, + BNXT_ULP_CLASS_HID_2b193 = 0x2b193, + BNXT_ULP_CLASS_HID_2b7af = 0x2b7af, + BNXT_ULP_CLASS_HID_6b267 = 0x6b267, + BNXT_ULP_CLASS_HID_6b823 = 0x6b823, + BNXT_ULP_CLASS_HID_69cc3 = 0x69cc3, + BNXT_ULP_CLASS_HID_6a29f = 0x6a29f, + BNXT_ULP_CLASS_HID_6d59b = 0x6d59b, + BNXT_ULP_CLASS_HID_6dc57 = 0x6dc57, + BNXT_ULP_CLASS_HID_6c077 = 0x6c077, + BNXT_ULP_CLASS_HID_6c633 = 0x6c633, + BNXT_ULP_CLASS_HID_69f57 = 0x69f57, + BNXT_ULP_CLASS_HID_6a513 = 0x6a513, + BNXT_ULP_CLASS_HID_68933 = 0x68933, + BNXT_ULP_CLASS_HID_68fcf = 0x68fcf, + BNXT_ULP_CLASS_HID_6c2cb = 0x6c2cb, + BNXT_ULP_CLASS_HID_6c887 = 0x6c887, + BNXT_ULP_CLASS_HID_6aca7 = 0x6aca7, + BNXT_ULP_CLASS_HID_6b363 = 0x6b363, + BNXT_ULP_CLASS_HID_3cd53 = 0x3cd53, + BNXT_ULP_CLASS_HID_3d36f = 0x3d36f, + BNXT_ULP_CLASS_HID_3b70f = 0x3b70f, + BNXT_ULP_CLASS_HID_3bdcb = 0x3bdcb, + BNXT_ULP_CLASS_HID_3939b = 0x3939b, + BNXT_ULP_CLASS_HID_39a57 = 0x39a57, + BNXT_ULP_CLASS_HID_3daa3 = 0x3daa3, + BNXT_ULP_CLASS_HID_38433 = 0x38433, + BNXT_ULP_CLASS_HID_3b983 = 0x3b983, + BNXT_ULP_CLASS_HID_3c05f = 0x3c05f, + BNXT_ULP_CLASS_HID_3a47f = 0x3a47f, + BNXT_ULP_CLASS_HID_3aa3b = 0x3aa3b, + BNXT_ULP_CLASS_HID_380cb = 0x380cb, + BNXT_ULP_CLASS_HID_38687 = 0x38687, + BNXT_ULP_CLASS_HID_3c793 = 0x3c793, + BNXT_ULP_CLASS_HID_3cdaf = 0x3cdaf, + BNXT_ULP_CLASS_HID_7c867 = 0x7c867, + BNXT_ULP_CLASS_HID_7ce23 = 0x7ce23, + BNXT_ULP_CLASS_HID_7b2c3 = 0x7b2c3, + BNXT_ULP_CLASS_HID_7b89f = 0x7b89f, + BNXT_ULP_CLASS_HID_78eaf = 0x78eaf, + BNXT_ULP_CLASS_HID_7956b = 0x7956b, + BNXT_ULP_CLASS_HID_7d677 = 0x7d677, + BNXT_ULP_CLASS_HID_7dc33 = 0x7dc33, + BNXT_ULP_CLASS_HID_7b557 = 0x7b557, + BNXT_ULP_CLASS_HID_7bb13 = 0x7bb13, + BNXT_ULP_CLASS_HID_79f33 = 0x79f33, + BNXT_ULP_CLASS_HID_7a5cf = 0x7a5cf, + BNXT_ULP_CLASS_HID_7d8cb = 0x7d8cb, + BNXT_ULP_CLASS_HID_7825b = 0x7825b, + BNXT_ULP_CLASS_HID_7c2a7 = 0x7c2a7, + BNXT_ULP_CLASS_HID_7c963 = 0x7c963, + BNXT_ULP_CLASS_HID_8b4b = 0x8b4b, + BNXT_ULP_CLASS_HID_9177 = 0x9177, + BNXT_ULP_CLASS_HID_d263 = 0xd263, + BNXT_ULP_CLASS_HID_d82f = 0xd82f, + BNXT_ULP_CLASS_HID_aedf = 0xaedf, BNXT_ULP_CLASS_HID_b49b = 0xb49b, - BNXT_ULP_CLASS_HID_b7db = 0xb7db, - BNXT_ULP_CLASS_HID_fa1b = 0xfa1b, - BNXT_ULP_CLASS_HID_fd5b = 0xfd5b, - BNXT_ULP_CLASS_HID_b04f = 0xb04f, - BNXT_ULP_CLASS_HID_b28f = 0xb28f, - BNXT_ULP_CLASS_HID_f5cf = 0xf5cf, - BNXT_ULP_CLASS_HID_f80f = 0xf80f, - BNXT_ULP_CLASS_HID_1c64f = 0x1c64f, - BNXT_ULP_CLASS_HID_1e88f = 0x1e88f, - BNXT_ULP_CLASS_HID_1cbcf = 0x1cbcf, - BNXT_ULP_CLASS_HID_1ee0f = 0x1ee0f, + BNXT_ULP_CLASS_HID_98bb = 0x98bb, + BNXT_ULP_CLASS_HID_9f67 = 0x9f67, + BNXT_ULP_CLASS_HID_4867f = 0x4867f, + BNXT_ULP_CLASS_HID_48c3b = 0x48c3b, + BNXT_ULP_CLASS_HID_4cd17 = 0x4cd17, + BNXT_ULP_CLASS_HID_4d3d3 = 0x4d3d3, + BNXT_ULP_CLASS_HID_4a983 = 0x4a983, + BNXT_ULP_CLASS_HID_4b04f = 0x4b04f, + BNXT_ULP_CLASS_HID_4946f = 0x4946f, + BNXT_ULP_CLASS_HID_49a2b = 0x49a2b, + BNXT_ULP_CLASS_HID_1a14b = 0x1a14b, + BNXT_ULP_CLASS_HID_1a777 = 0x1a777, + BNXT_ULP_CLASS_HID_18b17 = 0x18b17, + BNXT_ULP_CLASS_HID_191d3 = 0x191d3, + BNXT_ULP_CLASS_HID_1c4df = 0x1c4df, BNXT_ULP_CLASS_HID_1ca9b = 0x1ca9b, - BNXT_ULP_CLASS_HID_1eddb = 0x1eddb, - BNXT_ULP_CLASS_HID_1d01b = 0x1d01b, - BNXT_ULP_CLASS_HID_1f35b = 0x1f35b, - BNXT_ULP_CLASS_HID_8b4b = 0x8b4b, - BNXT_ULP_CLASS_HID_ad8b = 0xad8b, + BNXT_ULP_CLASS_HID_1aebb = 0x1aebb, + BNXT_ULP_CLASS_HID_1b567 = 0x1b567, + BNXT_ULP_CLASS_HID_59c7f = 0x59c7f, + BNXT_ULP_CLASS_HID_5a23b = 0x5a23b, + BNXT_ULP_CLASS_HID_586db = 0x586db, + BNXT_ULP_CLASS_HID_58c87 = 0x58c87, + BNXT_ULP_CLASS_HID_5bf83 = 0x5bf83, + BNXT_ULP_CLASS_HID_5c64f = 0x5c64f, + BNXT_ULP_CLASS_HID_5aa6f = 0x5aa6f, + BNXT_ULP_CLASS_HID_5b02b = 0x5b02b, BNXT_ULP_CLASS_HID_d0cb = 0xd0cb, - BNXT_ULP_CLASS_HID_f30b = 0xf30b, - BNXT_ULP_CLASS_HID_867f = 0x867f, - BNXT_ULP_CLASS_HID_a8bf = 0xa8bf, - BNXT_ULP_CLASS_HID_cbff = 0xcbff, - BNXT_ULP_CLASS_HID_ee3f = 0xee3f, - BNXT_ULP_CLASS_HID_19c7f = 0x19c7f, - BNXT_ULP_CLASS_HID_1bebf = 0x1bebf, - BNXT_ULP_CLASS_HID_1e1ff = 0x1e1ff, - BNXT_ULP_CLASS_HID_1e43f = 0x1e43f, - BNXT_ULP_CLASS_HID_1a14b = 0x1a14b, - BNXT_ULP_CLASS_HID_1a38b = 0x1a38b, + BNXT_ULP_CLASS_HID_d6f7 = 0xd6f7, + BNXT_ULP_CLASS_HID_d7e3 = 0xd7e3, + BNXT_ULP_CLASS_HID_c153 = 0xc153, + BNXT_ULP_CLASS_HID_f45f = 0xf45f, + BNXT_ULP_CLASS_HID_fa1b = 0xfa1b, + BNXT_ULP_CLASS_HID_de3b = 0xde3b, + BNXT_ULP_CLASS_HID_e4e7 = 0xe4e7, + BNXT_ULP_CLASS_HID_4cbff = 0x4cbff, + BNXT_ULP_CLASS_HID_4d1bb = 0x4d1bb, + BNXT_ULP_CLASS_HID_4d297 = 0x4d297, + BNXT_ULP_CLASS_HID_4d953 = 0x4d953, + BNXT_ULP_CLASS_HID_4ef03 = 0x4ef03, + BNXT_ULP_CLASS_HID_4f5cf = 0x4f5cf, + BNXT_ULP_CLASS_HID_4d9ef = 0x4d9ef, + BNXT_ULP_CLASS_HID_4dfab = 0x4dfab, BNXT_ULP_CLASS_HID_1e6cb = 0x1e6cb, - BNXT_ULP_CLASS_HID_1e90b = 0x1e90b, - BNXT_ULP_CLASS_HID_aedf = 0xaedf, + BNXT_ULP_CLASS_HID_1ecf7 = 0x1ecf7, + BNXT_ULP_CLASS_HID_1d097 = 0x1d097, + BNXT_ULP_CLASS_HID_1d753 = 0x1d753, + BNXT_ULP_CLASS_HID_1ca5f = 0x1ca5f, + BNXT_ULP_CLASS_HID_1d01b = 0x1d01b, + BNXT_ULP_CLASS_HID_1f43b = 0x1f43b, + BNXT_ULP_CLASS_HID_1fae7 = 0x1fae7, + BNXT_ULP_CLASS_HID_5e1ff = 0x5e1ff, + BNXT_ULP_CLASS_HID_5e7bb = 0x5e7bb, + BNXT_ULP_CLASS_HID_5cc5b = 0x5cc5b, + BNXT_ULP_CLASS_HID_5d207 = 0x5d207, + BNXT_ULP_CLASS_HID_5c503 = 0x5c503, + BNXT_ULP_CLASS_HID_5cbcf = 0x5cbcf, + BNXT_ULP_CLASS_HID_5efef = 0x5efef, + BNXT_ULP_CLASS_HID_5f5ab = 0x5f5ab, + BNXT_ULP_CLASS_HID_ad8b = 0xad8b, + BNXT_ULP_CLASS_HID_b3b7 = 0xb3b7, + BNXT_ULP_CLASS_HID_f4a3 = 0xf4a3, + BNXT_ULP_CLASS_HID_fb6f = 0xfb6f, BNXT_ULP_CLASS_HID_b11f = 0xb11f, - BNXT_ULP_CLASS_HID_f45f = 0xf45f, - BNXT_ULP_CLASS_HID_f69f = 0xf69f, - BNXT_ULP_CLASS_HID_a983 = 0xa983, - BNXT_ULP_CLASS_HID_acc3 = 0xacc3, - BNXT_ULP_CLASS_HID_ef03 = 0xef03, - BNXT_ULP_CLASS_HID_f243 = 0xf243, - BNXT_ULP_CLASS_HID_1bf83 = 0x1bf83, - BNXT_ULP_CLASS_HID_1e2c3 = 0x1e2c3, - BNXT_ULP_CLASS_HID_1c503 = 0x1c503, - BNXT_ULP_CLASS_HID_1e843 = 0x1e843, - BNXT_ULP_CLASS_HID_1c4df = 0x1c4df, + BNXT_ULP_CLASS_HID_b7db = 0xb7db, + BNXT_ULP_CLASS_HID_bbfb = 0xbbfb, + BNXT_ULP_CLASS_HID_a1a7 = 0xa1a7, + BNXT_ULP_CLASS_HID_4a8bf = 0x4a8bf, + BNXT_ULP_CLASS_HID_4af7b = 0x4af7b, + BNXT_ULP_CLASS_HID_4f057 = 0x4f057, + BNXT_ULP_CLASS_HID_4f613 = 0x4f613, + BNXT_ULP_CLASS_HID_4acc3 = 0x4acc3, + BNXT_ULP_CLASS_HID_4b28f = 0x4b28f, + BNXT_ULP_CLASS_HID_4b6af = 0x4b6af, + BNXT_ULP_CLASS_HID_4bd6b = 0x4bd6b, + BNXT_ULP_CLASS_HID_1a38b = 0x1a38b, + BNXT_ULP_CLASS_HID_1a9b7 = 0x1a9b7, + BNXT_ULP_CLASS_HID_1ae57 = 0x1ae57, + BNXT_ULP_CLASS_HID_1b413 = 0x1b413, BNXT_ULP_CLASS_HID_1e71f = 0x1e71f, - BNXT_ULP_CLASS_HID_1ca5f = 0x1ca5f, + BNXT_ULP_CLASS_HID_1eddb = 0x1eddb, + BNXT_ULP_CLASS_HID_1b1fb = 0x1b1fb, + BNXT_ULP_CLASS_HID_1b7a7 = 0x1b7a7, + BNXT_ULP_CLASS_HID_5bebf = 0x5bebf, + BNXT_ULP_CLASS_HID_5a57b = 0x5a57b, + BNXT_ULP_CLASS_HID_5a91b = 0x5a91b, + BNXT_ULP_CLASS_HID_5afc7 = 0x5afc7, + BNXT_ULP_CLASS_HID_5e2c3 = 0x5e2c3, + BNXT_ULP_CLASS_HID_5e88f = 0x5e88f, + BNXT_ULP_CLASS_HID_5acaf = 0x5acaf, + BNXT_ULP_CLASS_HID_5b36b = 0x5b36b, + BNXT_ULP_CLASS_HID_f30b = 0xf30b, + BNXT_ULP_CLASS_HID_f937 = 0xf937, + BNXT_ULP_CLASS_HID_fa23 = 0xfa23, + BNXT_ULP_CLASS_HID_e393 = 0xe393, + BNXT_ULP_CLASS_HID_f69f = 0xf69f, + BNXT_ULP_CLASS_HID_fd5b = 0xfd5b, + BNXT_ULP_CLASS_HID_e17b = 0xe17b, + BNXT_ULP_CLASS_HID_e727 = 0xe727, + BNXT_ULP_CLASS_HID_4ee3f = 0x4ee3f, + BNXT_ULP_CLASS_HID_4f4fb = 0x4f4fb, + BNXT_ULP_CLASS_HID_4f5d7 = 0x4f5d7, + BNXT_ULP_CLASS_HID_4fb93 = 0x4fb93, + BNXT_ULP_CLASS_HID_4f243 = 0x4f243, + BNXT_ULP_CLASS_HID_4f80f = 0x4f80f, + BNXT_ULP_CLASS_HID_4fc2f = 0x4fc2f, + BNXT_ULP_CLASS_HID_4e2eb = 0x4e2eb, + BNXT_ULP_CLASS_HID_1e90b = 0x1e90b, + BNXT_ULP_CLASS_HID_1ef37 = 0x1ef37, + BNXT_ULP_CLASS_HID_1f3d7 = 0x1f3d7, + BNXT_ULP_CLASS_HID_1f993 = 0x1f993, BNXT_ULP_CLASS_HID_1ec9f = 0x1ec9f, - BNXT_ULP_CLASS_HID_2523 = 0x2523, - BNXT_ULP_CLASS_HID_2bef = 0x2bef, - BNXT_ULP_CLASS_HID_2693 = 0x2693, - BNXT_ULP_CLASS_HID_4f73 = 0x4f73, - BNXT_ULP_CLASS_HID_4a27 = 0x4a27, - BNXT_ULP_CLASS_HID_164b = 0x164b, - BNXT_ULP_CLASS_HID_117f = 0x117f, - BNXT_ULP_CLASS_HID_39df = 0x39df, - BNXT_ULP_CLASS_HID_3483 = 0x3483, - BNXT_ULP_CLASS_HID_20d7 = 0x20d7, - BNXT_ULP_CLASS_HID_48b7 = 0x48b7, - BNXT_ULP_CLASS_HID_447b = 0x447b, - BNXT_ULP_CLASS_HID_0f8f = 0x0f8f, - BNXT_ULP_CLASS_HID_0ab3 = 0x0ab3, - BNXT_ULP_CLASS_HID_3313 = 0x3313, - BNXT_ULP_CLASS_HID_2ec7 = 0x2ec7, - BNXT_ULP_CLASS_HID_257b7 = 0x257b7, - BNXT_ULP_CLASS_HID_24467 = 0x24467, - BNXT_ULP_CLASS_HID_23fbb = 0x23fbb, - BNXT_ULP_CLASS_HID_252cb = 0x252cb, - BNXT_ULP_CLASS_HID_21e7f = 0x21e7f, - BNXT_ULP_CLASS_HID_20b2f = 0x20b2f, - BNXT_ULP_CLASS_HID_20663 = 0x20663, - BNXT_ULP_CLASS_HID_219b3 = 0x219b3, - BNXT_ULP_CLASS_HID_24213 = 0x24213, - BNXT_ULP_CLASS_HID_22ec3 = 0x22ec3, - BNXT_ULP_CLASS_HID_22a17 = 0x22a17, - BNXT_ULP_CLASS_HID_23d27 = 0x23d27, - BNXT_ULP_CLASS_HID_208db = 0x208db, - BNXT_ULP_CLASS_HID_25277 = 0x25277, - BNXT_ULP_CLASS_HID_24d8b = 0x24d8b, - BNXT_ULP_CLASS_HID_203ef = 0x203ef, - BNXT_ULP_CLASS_HID_2517b = 0x2517b, - BNXT_ULP_CLASS_HID_23e2b = 0x23e2b, - BNXT_ULP_CLASS_HID_2397f = 0x2397f, - BNXT_ULP_CLASS_HID_24c8f = 0x24c8f, - BNXT_ULP_CLASS_HID_21823 = 0x21823, - BNXT_ULP_CLASS_HID_20513 = 0x20513, - BNXT_ULP_CLASS_HID_20027 = 0x20027, - BNXT_ULP_CLASS_HID_21377 = 0x21377, - BNXT_ULP_CLASS_HID_23bd7 = 0x23bd7, - BNXT_ULP_CLASS_HID_22887 = 0x22887, - BNXT_ULP_CLASS_HID_223db = 0x223db, - BNXT_ULP_CLASS_HID_236eb = 0x236eb, - BNXT_ULP_CLASS_HID_2029f = 0x2029f, - BNXT_ULP_CLASS_HID_24c3b = 0x24c3b, - BNXT_ULP_CLASS_HID_2474f = 0x2474f, - BNXT_ULP_CLASS_HID_25a9f = 0x25a9f, - BNXT_ULP_CLASS_HID_24b3f = 0x24b3f, - BNXT_ULP_CLASS_HID_237ef = 0x237ef, - BNXT_ULP_CLASS_HID_23323 = 0x23323, - BNXT_ULP_CLASS_HID_24673 = 0x24673, - BNXT_ULP_CLASS_HID_211e7 = 0x211e7, - BNXT_ULP_CLASS_HID_25b83 = 0x25b83, - BNXT_ULP_CLASS_HID_256d7 = 0x256d7, - BNXT_ULP_CLASS_HID_20d3b = 0x20d3b, - BNXT_ULP_CLASS_HID_2359b = 0x2359b, - BNXT_ULP_CLASS_HID_2224b = 0x2224b, - BNXT_ULP_CLASS_HID_21d9f = 0x21d9f, - BNXT_ULP_CLASS_HID_230af = 0x230af, - BNXT_ULP_CLASS_HID_2590f = 0x2590f, - BNXT_ULP_CLASS_HID_245ff = 0x245ff, - BNXT_ULP_CLASS_HID_24133 = 0x24133, - BNXT_ULP_CLASS_HID_25443 = 0x25443, - BNXT_ULP_CLASS_HID_244e3 = 0x244e3, - BNXT_ULP_CLASS_HID_231d3 = 0x231d3, - BNXT_ULP_CLASS_HID_22ce7 = 0x22ce7, - BNXT_ULP_CLASS_HID_24037 = 0x24037, - BNXT_ULP_CLASS_HID_20bab = 0x20bab, - BNXT_ULP_CLASS_HID_25547 = 0x25547, - BNXT_ULP_CLASS_HID_2509b = 0x2509b, - BNXT_ULP_CLASS_HID_206ff = 0x206ff, - BNXT_ULP_CLASS_HID_22f5f = 0x22f5f, - BNXT_ULP_CLASS_HID_21c0f = 0x21c0f, - BNXT_ULP_CLASS_HID_21743 = 0x21743, - BNXT_ULP_CLASS_HID_22a93 = 0x22a93, - BNXT_ULP_CLASS_HID_252f3 = 0x252f3, - BNXT_ULP_CLASS_HID_23fa3 = 0x23fa3, - BNXT_ULP_CLASS_HID_23af7 = 0x23af7, - BNXT_ULP_CLASS_HID_24e07 = 0x24e07, - BNXT_ULP_CLASS_HID_2322f = 0x2322f, - BNXT_ULP_CLASS_HID_21f1f = 0x21f1f, - BNXT_ULP_CLASS_HID_21a53 = 0x21a53, - BNXT_ULP_CLASS_HID_22d63 = 0x22d63, - BNXT_ULP_CLASS_HID_255c3 = 0x255c3, - BNXT_ULP_CLASS_HID_242b3 = 0x242b3, - BNXT_ULP_CLASS_HID_23dc7 = 0x23dc7, - BNXT_ULP_CLASS_HID_25117 = 0x25117, - BNXT_ULP_CLASS_HID_22c13 = 0x22c13, - BNXT_ULP_CLASS_HID_218c3 = 0x218c3, - BNXT_ULP_CLASS_HID_21417 = 0x21417, - BNXT_ULP_CLASS_HID_22727 = 0x22727, - BNXT_ULP_CLASS_HID_24f87 = 0x24f87, - BNXT_ULP_CLASS_HID_23c77 = 0x23c77, - BNXT_ULP_CLASS_HID_2378b = 0x2378b, - BNXT_ULP_CLASS_HID_24adb = 0x24adb, + BNXT_ULP_CLASS_HID_1f35b = 0x1f35b, + BNXT_ULP_CLASS_HID_1f77b = 0x1f77b, + BNXT_ULP_CLASS_HID_1fd27 = 0x1fd27, + BNXT_ULP_CLASS_HID_5e43f = 0x5e43f, + BNXT_ULP_CLASS_HID_5eafb = 0x5eafb, + BNXT_ULP_CLASS_HID_5ee9b = 0x5ee9b, + BNXT_ULP_CLASS_HID_5f547 = 0x5f547, + BNXT_ULP_CLASS_HID_5e843 = 0x5e843, + BNXT_ULP_CLASS_HID_5ee0f = 0x5ee0f, + BNXT_ULP_CLASS_HID_5f22f = 0x5f22f, + BNXT_ULP_CLASS_HID_5f8eb = 0x5f8eb, + BNXT_ULP_CLASS_HID_2579 = 0x2579, + BNXT_ULP_CLASS_HID_2bb5 = 0x2bb5, + BNXT_ULP_CLASS_HID_4591 = 0x4591, + BNXT_ULP_CLASS_HID_4bad = 0x4bad, + BNXT_ULP_CLASS_HID_2561 = 0x2561, + BNXT_ULP_CLASS_HID_2bad = 0x2bad, + BNXT_ULP_CLASS_HID_5bdd = 0x5bdd, + BNXT_ULP_CLASS_HID_054d = 0x054d, BNXT_ULP_CLASS_HID_257b = 0x257b, BNXT_ULP_CLASS_HID_2bb7 = 0x2bb7, - BNXT_ULP_CLASS_HID_1867 = 0x1867, - BNXT_ULP_CLASS_HID_4f2b = 0x4f2b, - BNXT_ULP_CLASS_HID_3c1b = 0x3c1b, + BNXT_ULP_CLASS_HID_0fd7 = 0x0fd7, BNXT_ULP_CLASS_HID_1613 = 0x1613, - BNXT_ULP_CLASS_HID_02c3 = 0x02c3, + BNXT_ULP_CLASS_HID_48ef = 0x48ef, + BNXT_ULP_CLASS_HID_4f2b = 0x4f2b, + BNXT_ULP_CLASS_HID_334b = 0x334b, BNXT_ULP_CLASS_HID_3987 = 0x3987, - BNXT_ULP_CLASS_HID_2677 = 0x2677, BNXT_ULP_CLASS_HID_122b = 0x122b, - BNXT_ULP_CLASS_HID_48ef = 0x48ef, - BNXT_ULP_CLASS_HID_35df = 0x35df, - BNXT_ULP_CLASS_HID_0fd7 = 0x0fd7, + BNXT_ULP_CLASS_HID_1867 = 0x1867, BNXT_ULP_CLASS_HID_5973 = 0x5973, - BNXT_ULP_CLASS_HID_334b = 0x334b, + BNXT_ULP_CLASS_HID_02c3 = 0x02c3, + BNXT_ULP_CLASS_HID_35df = 0x35df, + BNXT_ULP_CLASS_HID_3c1b = 0x3c1b, BNXT_ULP_CLASS_HID_203b = 0x203b, - BNXT_ULP_CLASS_HID_25797 = 0x25797, - BNXT_ULP_CLASS_HID_285eb = 0x285eb, - BNXT_ULP_CLASS_HID_310eb = 0x310eb, - BNXT_ULP_CLASS_HID_39beb = 0x39beb, - BNXT_ULP_CLASS_HID_24447 = 0x24447, - BNXT_ULP_CLASS_HID_2cf47 = 0x2cf47, - BNXT_ULP_CLASS_HID_35a47 = 0x35a47, - BNXT_ULP_CLASS_HID_3889b = 0x3889b, - BNXT_ULP_CLASS_HID_23f9b = 0x23f9b, - BNXT_ULP_CLASS_HID_2ca9b = 0x2ca9b, - BNXT_ULP_CLASS_HID_3559b = 0x3559b, - BNXT_ULP_CLASS_HID_383ef = 0x383ef, - BNXT_ULP_CLASS_HID_252eb = 0x252eb, - BNXT_ULP_CLASS_HID_2813f = 0x2813f, - BNXT_ULP_CLASS_HID_30c3f = 0x30c3f, - BNXT_ULP_CLASS_HID_3973f = 0x3973f, - BNXT_ULP_CLASS_HID_21e5f = 0x21e5f, - BNXT_ULP_CLASS_HID_2a95f = 0x2a95f, - BNXT_ULP_CLASS_HID_3345f = 0x3345f, - BNXT_ULP_CLASS_HID_3bf5f = 0x3bf5f, - BNXT_ULP_CLASS_HID_20b0f = 0x20b0f, - BNXT_ULP_CLASS_HID_2960f = 0x2960f, - BNXT_ULP_CLASS_HID_3210f = 0x3210f, - BNXT_ULP_CLASS_HID_3ac0f = 0x3ac0f, - BNXT_ULP_CLASS_HID_20643 = 0x20643, - BNXT_ULP_CLASS_HID_29143 = 0x29143, - BNXT_ULP_CLASS_HID_31c43 = 0x31c43, - BNXT_ULP_CLASS_HID_3a743 = 0x3a743, - BNXT_ULP_CLASS_HID_21993 = 0x21993, - BNXT_ULP_CLASS_HID_2a493 = 0x2a493, - BNXT_ULP_CLASS_HID_32f93 = 0x32f93, - BNXT_ULP_CLASS_HID_3ba93 = 0x3ba93, - BNXT_ULP_CLASS_HID_24233 = 0x24233, - BNXT_ULP_CLASS_HID_2cd33 = 0x2cd33, - BNXT_ULP_CLASS_HID_35833 = 0x35833, - BNXT_ULP_CLASS_HID_38607 = 0x38607, - BNXT_ULP_CLASS_HID_22ee3 = 0x22ee3, - BNXT_ULP_CLASS_HID_2b9e3 = 0x2b9e3, - BNXT_ULP_CLASS_HID_344e3 = 0x344e3, - BNXT_ULP_CLASS_HID_3cfe3 = 0x3cfe3, - BNXT_ULP_CLASS_HID_22a37 = 0x22a37, - BNXT_ULP_CLASS_HID_2b537 = 0x2b537, - BNXT_ULP_CLASS_HID_34037 = 0x34037, - BNXT_ULP_CLASS_HID_3cb37 = 0x3cb37, - BNXT_ULP_CLASS_HID_23d07 = 0x23d07, - BNXT_ULP_CLASS_HID_2c807 = 0x2c807, - BNXT_ULP_CLASS_HID_35307 = 0x35307, - BNXT_ULP_CLASS_HID_3815b = 0x3815b, - BNXT_ULP_CLASS_HID_208fb = 0x208fb, - BNXT_ULP_CLASS_HID_293fb = 0x293fb, - BNXT_ULP_CLASS_HID_31efb = 0x31efb, - BNXT_ULP_CLASS_HID_3a9fb = 0x3a9fb, - BNXT_ULP_CLASS_HID_25257 = 0x25257, - BNXT_ULP_CLASS_HID_280ab = 0x280ab, - BNXT_ULP_CLASS_HID_30bab = 0x30bab, - BNXT_ULP_CLASS_HID_396ab = 0x396ab, - BNXT_ULP_CLASS_HID_24dab = 0x24dab, - BNXT_ULP_CLASS_HID_2d8ab = 0x2d8ab, - BNXT_ULP_CLASS_HID_306ff = 0x306ff, - BNXT_ULP_CLASS_HID_391ff = 0x391ff, - BNXT_ULP_CLASS_HID_203cf = 0x203cf, - BNXT_ULP_CLASS_HID_28ecf = 0x28ecf, - BNXT_ULP_CLASS_HID_319cf = 0x319cf, - BNXT_ULP_CLASS_HID_3a4cf = 0x3a4cf, - BNXT_ULP_CLASS_HID_2515b = 0x2515b, - BNXT_ULP_CLASS_HID_2dc5b = 0x2dc5b, - BNXT_ULP_CLASS_HID_30aaf = 0x30aaf, - BNXT_ULP_CLASS_HID_395af = 0x395af, - BNXT_ULP_CLASS_HID_23e0b = 0x23e0b, - BNXT_ULP_CLASS_HID_2c90b = 0x2c90b, - BNXT_ULP_CLASS_HID_3540b = 0x3540b, - BNXT_ULP_CLASS_HID_3825f = 0x3825f, - BNXT_ULP_CLASS_HID_2395f = 0x2395f, - BNXT_ULP_CLASS_HID_2c45f = 0x2c45f, - BNXT_ULP_CLASS_HID_34f5f = 0x34f5f, - BNXT_ULP_CLASS_HID_3da5f = 0x3da5f, - BNXT_ULP_CLASS_HID_24caf = 0x24caf, - BNXT_ULP_CLASS_HID_2d7af = 0x2d7af, - BNXT_ULP_CLASS_HID_305e3 = 0x305e3, - BNXT_ULP_CLASS_HID_390e3 = 0x390e3, - BNXT_ULP_CLASS_HID_21803 = 0x21803, - BNXT_ULP_CLASS_HID_2a303 = 0x2a303, - BNXT_ULP_CLASS_HID_32e03 = 0x32e03, - BNXT_ULP_CLASS_HID_3b903 = 0x3b903, - BNXT_ULP_CLASS_HID_20533 = 0x20533, - BNXT_ULP_CLASS_HID_29033 = 0x29033, - BNXT_ULP_CLASS_HID_31b33 = 0x31b33, - BNXT_ULP_CLASS_HID_3a633 = 0x3a633, - BNXT_ULP_CLASS_HID_20007 = 0x20007, - BNXT_ULP_CLASS_HID_28b07 = 0x28b07, - BNXT_ULP_CLASS_HID_31607 = 0x31607, - BNXT_ULP_CLASS_HID_3a107 = 0x3a107, - BNXT_ULP_CLASS_HID_21357 = 0x21357, - BNXT_ULP_CLASS_HID_29e57 = 0x29e57, - BNXT_ULP_CLASS_HID_32957 = 0x32957, - BNXT_ULP_CLASS_HID_3b457 = 0x3b457, - BNXT_ULP_CLASS_HID_23bf7 = 0x23bf7, - BNXT_ULP_CLASS_HID_2c6f7 = 0x2c6f7, - BNXT_ULP_CLASS_HID_351f7 = 0x351f7, - BNXT_ULP_CLASS_HID_3dcf7 = 0x3dcf7, - BNXT_ULP_CLASS_HID_228a7 = 0x228a7, - BNXT_ULP_CLASS_HID_2b3a7 = 0x2b3a7, - BNXT_ULP_CLASS_HID_33ea7 = 0x33ea7, - BNXT_ULP_CLASS_HID_3c9a7 = 0x3c9a7, - BNXT_ULP_CLASS_HID_223fb = 0x223fb, - BNXT_ULP_CLASS_HID_2aefb = 0x2aefb, - BNXT_ULP_CLASS_HID_339fb = 0x339fb, - BNXT_ULP_CLASS_HID_3c4fb = 0x3c4fb, - BNXT_ULP_CLASS_HID_236cb = 0x236cb, - BNXT_ULP_CLASS_HID_2c1cb = 0x2c1cb, - BNXT_ULP_CLASS_HID_34ccb = 0x34ccb, - BNXT_ULP_CLASS_HID_3d7cb = 0x3d7cb, - BNXT_ULP_CLASS_HID_202bf = 0x202bf, - BNXT_ULP_CLASS_HID_28dbf = 0x28dbf, - BNXT_ULP_CLASS_HID_318bf = 0x318bf, - BNXT_ULP_CLASS_HID_3a3bf = 0x3a3bf, - BNXT_ULP_CLASS_HID_24c1b = 0x24c1b, - BNXT_ULP_CLASS_HID_2d71b = 0x2d71b, - BNXT_ULP_CLASS_HID_3056f = 0x3056f, - BNXT_ULP_CLASS_HID_3906f = 0x3906f, - BNXT_ULP_CLASS_HID_2476f = 0x2476f, - BNXT_ULP_CLASS_HID_2d26f = 0x2d26f, - BNXT_ULP_CLASS_HID_300a3 = 0x300a3, - BNXT_ULP_CLASS_HID_38ba3 = 0x38ba3, - BNXT_ULP_CLASS_HID_25abf = 0x25abf, - BNXT_ULP_CLASS_HID_288f3 = 0x288f3, - BNXT_ULP_CLASS_HID_313f3 = 0x313f3, - BNXT_ULP_CLASS_HID_39ef3 = 0x39ef3, - BNXT_ULP_CLASS_HID_24b1f = 0x24b1f, - BNXT_ULP_CLASS_HID_2d61f = 0x2d61f, - BNXT_ULP_CLASS_HID_30453 = 0x30453, - BNXT_ULP_CLASS_HID_38f53 = 0x38f53, - BNXT_ULP_CLASS_HID_237cf = 0x237cf, - BNXT_ULP_CLASS_HID_2c2cf = 0x2c2cf, - BNXT_ULP_CLASS_HID_34dcf = 0x34dcf, - BNXT_ULP_CLASS_HID_3d8cf = 0x3d8cf, - BNXT_ULP_CLASS_HID_23303 = 0x23303, - BNXT_ULP_CLASS_HID_2be03 = 0x2be03, - BNXT_ULP_CLASS_HID_34903 = 0x34903, - BNXT_ULP_CLASS_HID_3d403 = 0x3d403, - BNXT_ULP_CLASS_HID_24653 = 0x24653, - BNXT_ULP_CLASS_HID_2d153 = 0x2d153, - BNXT_ULP_CLASS_HID_35c53 = 0x35c53, - BNXT_ULP_CLASS_HID_38aa7 = 0x38aa7, - BNXT_ULP_CLASS_HID_211c7 = 0x211c7, - BNXT_ULP_CLASS_HID_29cc7 = 0x29cc7, - BNXT_ULP_CLASS_HID_327c7 = 0x327c7, - BNXT_ULP_CLASS_HID_3b2c7 = 0x3b2c7, - BNXT_ULP_CLASS_HID_25ba3 = 0x25ba3, - BNXT_ULP_CLASS_HID_289f7 = 0x289f7, - BNXT_ULP_CLASS_HID_314f7 = 0x314f7, - BNXT_ULP_CLASS_HID_39ff7 = 0x39ff7, - BNXT_ULP_CLASS_HID_256f7 = 0x256f7, - BNXT_ULP_CLASS_HID_284cb = 0x284cb, - BNXT_ULP_CLASS_HID_30fcb = 0x30fcb, - BNXT_ULP_CLASS_HID_39acb = 0x39acb, - BNXT_ULP_CLASS_HID_20d1b = 0x20d1b, - BNXT_ULP_CLASS_HID_2981b = 0x2981b, - BNXT_ULP_CLASS_HID_3231b = 0x3231b, - BNXT_ULP_CLASS_HID_3ae1b = 0x3ae1b, - BNXT_ULP_CLASS_HID_235bb = 0x235bb, - BNXT_ULP_CLASS_HID_2c0bb = 0x2c0bb, - BNXT_ULP_CLASS_HID_34bbb = 0x34bbb, - BNXT_ULP_CLASS_HID_3d6bb = 0x3d6bb, - BNXT_ULP_CLASS_HID_2226b = 0x2226b, - BNXT_ULP_CLASS_HID_2ad6b = 0x2ad6b, - BNXT_ULP_CLASS_HID_3386b = 0x3386b, - BNXT_ULP_CLASS_HID_3c36b = 0x3c36b, - BNXT_ULP_CLASS_HID_21dbf = 0x21dbf, - BNXT_ULP_CLASS_HID_2a8bf = 0x2a8bf, - BNXT_ULP_CLASS_HID_333bf = 0x333bf, - BNXT_ULP_CLASS_HID_3bebf = 0x3bebf, - BNXT_ULP_CLASS_HID_2308f = 0x2308f, - BNXT_ULP_CLASS_HID_2bb8f = 0x2bb8f, - BNXT_ULP_CLASS_HID_3468f = 0x3468f, - BNXT_ULP_CLASS_HID_3d18f = 0x3d18f, - BNXT_ULP_CLASS_HID_2592f = 0x2592f, - BNXT_ULP_CLASS_HID_28763 = 0x28763, - BNXT_ULP_CLASS_HID_31263 = 0x31263, - BNXT_ULP_CLASS_HID_39d63 = 0x39d63, - BNXT_ULP_CLASS_HID_245df = 0x245df, - BNXT_ULP_CLASS_HID_2d0df = 0x2d0df, - BNXT_ULP_CLASS_HID_35bdf = 0x35bdf, - BNXT_ULP_CLASS_HID_38a13 = 0x38a13, - BNXT_ULP_CLASS_HID_24113 = 0x24113, - BNXT_ULP_CLASS_HID_2cc13 = 0x2cc13, - BNXT_ULP_CLASS_HID_35713 = 0x35713, - BNXT_ULP_CLASS_HID_38567 = 0x38567, - BNXT_ULP_CLASS_HID_25463 = 0x25463, - BNXT_ULP_CLASS_HID_282b7 = 0x282b7, - BNXT_ULP_CLASS_HID_30db7 = 0x30db7, - BNXT_ULP_CLASS_HID_398b7 = 0x398b7, - BNXT_ULP_CLASS_HID_244c3 = 0x244c3, - BNXT_ULP_CLASS_HID_2cfc3 = 0x2cfc3, - BNXT_ULP_CLASS_HID_35ac3 = 0x35ac3, - BNXT_ULP_CLASS_HID_38917 = 0x38917, - BNXT_ULP_CLASS_HID_231f3 = 0x231f3, - BNXT_ULP_CLASS_HID_2bcf3 = 0x2bcf3, - BNXT_ULP_CLASS_HID_347f3 = 0x347f3, - BNXT_ULP_CLASS_HID_3d2f3 = 0x3d2f3, - BNXT_ULP_CLASS_HID_22cc7 = 0x22cc7, - BNXT_ULP_CLASS_HID_2b7c7 = 0x2b7c7, - BNXT_ULP_CLASS_HID_342c7 = 0x342c7, - BNXT_ULP_CLASS_HID_3cdc7 = 0x3cdc7, - BNXT_ULP_CLASS_HID_24017 = 0x24017, - BNXT_ULP_CLASS_HID_2cb17 = 0x2cb17, - BNXT_ULP_CLASS_HID_35617 = 0x35617, - BNXT_ULP_CLASS_HID_3846b = 0x3846b, - BNXT_ULP_CLASS_HID_20b8b = 0x20b8b, - BNXT_ULP_CLASS_HID_2968b = 0x2968b, - BNXT_ULP_CLASS_HID_3218b = 0x3218b, - BNXT_ULP_CLASS_HID_3ac8b = 0x3ac8b, - BNXT_ULP_CLASS_HID_25567 = 0x25567, - BNXT_ULP_CLASS_HID_283bb = 0x283bb, - BNXT_ULP_CLASS_HID_30ebb = 0x30ebb, - BNXT_ULP_CLASS_HID_399bb = 0x399bb, - BNXT_ULP_CLASS_HID_250bb = 0x250bb, - BNXT_ULP_CLASS_HID_2dbbb = 0x2dbbb, - BNXT_ULP_CLASS_HID_3098f = 0x3098f, - BNXT_ULP_CLASS_HID_3948f = 0x3948f, - BNXT_ULP_CLASS_HID_206df = 0x206df, - BNXT_ULP_CLASS_HID_291df = 0x291df, - BNXT_ULP_CLASS_HID_31cdf = 0x31cdf, - BNXT_ULP_CLASS_HID_3a7df = 0x3a7df, - BNXT_ULP_CLASS_HID_22f7f = 0x22f7f, - BNXT_ULP_CLASS_HID_2ba7f = 0x2ba7f, - BNXT_ULP_CLASS_HID_3457f = 0x3457f, - BNXT_ULP_CLASS_HID_3d07f = 0x3d07f, - BNXT_ULP_CLASS_HID_21c2f = 0x21c2f, - BNXT_ULP_CLASS_HID_2a72f = 0x2a72f, - BNXT_ULP_CLASS_HID_3322f = 0x3322f, - BNXT_ULP_CLASS_HID_3bd2f = 0x3bd2f, - BNXT_ULP_CLASS_HID_21763 = 0x21763, - BNXT_ULP_CLASS_HID_2a263 = 0x2a263, - BNXT_ULP_CLASS_HID_32d63 = 0x32d63, - BNXT_ULP_CLASS_HID_3b863 = 0x3b863, - BNXT_ULP_CLASS_HID_22ab3 = 0x22ab3, - BNXT_ULP_CLASS_HID_2b5b3 = 0x2b5b3, - BNXT_ULP_CLASS_HID_340b3 = 0x340b3, - BNXT_ULP_CLASS_HID_3cbb3 = 0x3cbb3, - BNXT_ULP_CLASS_HID_252d3 = 0x252d3, - BNXT_ULP_CLASS_HID_28127 = 0x28127, - BNXT_ULP_CLASS_HID_30c27 = 0x30c27, - BNXT_ULP_CLASS_HID_39727 = 0x39727, - BNXT_ULP_CLASS_HID_23f83 = 0x23f83, - BNXT_ULP_CLASS_HID_2ca83 = 0x2ca83, - BNXT_ULP_CLASS_HID_35583 = 0x35583, - BNXT_ULP_CLASS_HID_383d7 = 0x383d7, - BNXT_ULP_CLASS_HID_23ad7 = 0x23ad7, - BNXT_ULP_CLASS_HID_2c5d7 = 0x2c5d7, - BNXT_ULP_CLASS_HID_350d7 = 0x350d7, - BNXT_ULP_CLASS_HID_3dbd7 = 0x3dbd7, - BNXT_ULP_CLASS_HID_24e27 = 0x24e27, - BNXT_ULP_CLASS_HID_2d927 = 0x2d927, - BNXT_ULP_CLASS_HID_3077b = 0x3077b, - BNXT_ULP_CLASS_HID_3927b = 0x3927b, - BNXT_ULP_CLASS_HID_2320f = 0x2320f, - BNXT_ULP_CLASS_HID_2bd0f = 0x2bd0f, - BNXT_ULP_CLASS_HID_3480f = 0x3480f, - BNXT_ULP_CLASS_HID_3d30f = 0x3d30f, - BNXT_ULP_CLASS_HID_21f3f = 0x21f3f, - BNXT_ULP_CLASS_HID_2aa3f = 0x2aa3f, - BNXT_ULP_CLASS_HID_3353f = 0x3353f, - BNXT_ULP_CLASS_HID_3c03f = 0x3c03f, - BNXT_ULP_CLASS_HID_21a73 = 0x21a73, - BNXT_ULP_CLASS_HID_2a573 = 0x2a573, - BNXT_ULP_CLASS_HID_33073 = 0x33073, - BNXT_ULP_CLASS_HID_3bb73 = 0x3bb73, - BNXT_ULP_CLASS_HID_22d43 = 0x22d43, - BNXT_ULP_CLASS_HID_2b843 = 0x2b843, - BNXT_ULP_CLASS_HID_34343 = 0x34343, - BNXT_ULP_CLASS_HID_3ce43 = 0x3ce43, - BNXT_ULP_CLASS_HID_255e3 = 0x255e3, - BNXT_ULP_CLASS_HID_28437 = 0x28437, - BNXT_ULP_CLASS_HID_30f37 = 0x30f37, - BNXT_ULP_CLASS_HID_39a37 = 0x39a37, - BNXT_ULP_CLASS_HID_24293 = 0x24293, - BNXT_ULP_CLASS_HID_2cd93 = 0x2cd93, - BNXT_ULP_CLASS_HID_35893 = 0x35893, - BNXT_ULP_CLASS_HID_386e7 = 0x386e7, - BNXT_ULP_CLASS_HID_23de7 = 0x23de7, - BNXT_ULP_CLASS_HID_2c8e7 = 0x2c8e7, - BNXT_ULP_CLASS_HID_353e7 = 0x353e7, - BNXT_ULP_CLASS_HID_3823b = 0x3823b, - BNXT_ULP_CLASS_HID_25137 = 0x25137, - BNXT_ULP_CLASS_HID_2dc37 = 0x2dc37, - BNXT_ULP_CLASS_HID_30a0b = 0x30a0b, - BNXT_ULP_CLASS_HID_3950b = 0x3950b, - BNXT_ULP_CLASS_HID_22c33 = 0x22c33, - BNXT_ULP_CLASS_HID_2b733 = 0x2b733, - BNXT_ULP_CLASS_HID_34233 = 0x34233, - BNXT_ULP_CLASS_HID_3cd33 = 0x3cd33, - BNXT_ULP_CLASS_HID_218e3 = 0x218e3, - BNXT_ULP_CLASS_HID_2a3e3 = 0x2a3e3, - BNXT_ULP_CLASS_HID_32ee3 = 0x32ee3, - BNXT_ULP_CLASS_HID_3b9e3 = 0x3b9e3, - BNXT_ULP_CLASS_HID_21437 = 0x21437, - BNXT_ULP_CLASS_HID_29f37 = 0x29f37, - BNXT_ULP_CLASS_HID_32a37 = 0x32a37, - BNXT_ULP_CLASS_HID_3b537 = 0x3b537, - BNXT_ULP_CLASS_HID_22707 = 0x22707, - BNXT_ULP_CLASS_HID_2b207 = 0x2b207, - BNXT_ULP_CLASS_HID_33d07 = 0x33d07, - BNXT_ULP_CLASS_HID_3c807 = 0x3c807, - BNXT_ULP_CLASS_HID_24fa7 = 0x24fa7, - BNXT_ULP_CLASS_HID_2daa7 = 0x2daa7, - BNXT_ULP_CLASS_HID_308fb = 0x308fb, - BNXT_ULP_CLASS_HID_393fb = 0x393fb, - BNXT_ULP_CLASS_HID_23c57 = 0x23c57, - BNXT_ULP_CLASS_HID_2c757 = 0x2c757, - BNXT_ULP_CLASS_HID_35257 = 0x35257, - BNXT_ULP_CLASS_HID_380ab = 0x380ab, - BNXT_ULP_CLASS_HID_237ab = 0x237ab, - BNXT_ULP_CLASS_HID_2c2ab = 0x2c2ab, - BNXT_ULP_CLASS_HID_34dab = 0x34dab, - BNXT_ULP_CLASS_HID_3d8ab = 0x3d8ab, - BNXT_ULP_CLASS_HID_24afb = 0x24afb, - BNXT_ULP_CLASS_HID_2d5fb = 0x2d5fb, - BNXT_ULP_CLASS_HID_303cf = 0x303cf, - BNXT_ULP_CLASS_HID_38ecf = 0x38ecf, + BNXT_ULP_CLASS_HID_2677 = 0x2677, + BNXT_ULP_CLASS_HID_2563 = 0x2563, + BNXT_ULP_CLASS_HID_2baf = 0x2baf, + BNXT_ULP_CLASS_HID_0fcf = 0x0fcf, + BNXT_ULP_CLASS_HID_160b = 0x160b, + BNXT_ULP_CLASS_HID_48f7 = 0x48f7, + BNXT_ULP_CLASS_HID_4f33 = 0x4f33, + BNXT_ULP_CLASS_HID_3353 = 0x3353, + BNXT_ULP_CLASS_HID_399f = 0x399f, + BNXT_ULP_CLASS_HID_42097 = 0x42097, + BNXT_ULP_CLASS_HID_426d3 = 0x426d3, + BNXT_ULP_CLASS_HID_40af3 = 0x40af3, + BNXT_ULP_CLASS_HID_4113f = 0x4113f, + BNXT_ULP_CLASS_HID_4443b = 0x4443b, + BNXT_ULP_CLASS_HID_44a67 = 0x44a67, + BNXT_ULP_CLASS_HID_42e87 = 0x42e87, + BNXT_ULP_CLASS_HID_434c3 = 0x434c3, + BNXT_ULP_CLASS_HID_2559 = 0x2559, + BNXT_ULP_CLASS_HID_2b95 = 0x2b95, + BNXT_ULP_CLASS_HID_45b1 = 0x45b1, + BNXT_ULP_CLASS_HID_4b8d = 0x4b8d, + BNXT_ULP_CLASS_HID_2541 = 0x2541, + BNXT_ULP_CLASS_HID_2b8d = 0x2b8d, + BNXT_ULP_CLASS_HID_5bfd = 0x5bfd, + BNXT_ULP_CLASS_HID_056d = 0x056d, + BNXT_ULP_CLASS_HID_2539 = 0x2539, + BNXT_ULP_CLASS_HID_2bf5 = 0x2bf5, + BNXT_ULP_CLASS_HID_45d1 = 0x45d1, + BNXT_ULP_CLASS_HID_4bed = 0x4bed, + BNXT_ULP_CLASS_HID_2521 = 0x2521, + BNXT_ULP_CLASS_HID_2bed = 0x2bed, + BNXT_ULP_CLASS_HID_5b9d = 0x5b9d, + BNXT_ULP_CLASS_HID_050d = 0x050d, BNXT_ULP_CLASS_HID_255b = 0x255b, BNXT_ULP_CLASS_HID_2b97 = 0x2b97, - BNXT_ULP_CLASS_HID_1847 = 0x1847, - BNXT_ULP_CLASS_HID_4f0b = 0x4f0b, - BNXT_ULP_CLASS_HID_3c3b = 0x3c3b, + BNXT_ULP_CLASS_HID_0ff7 = 0x0ff7, BNXT_ULP_CLASS_HID_1633 = 0x1633, - BNXT_ULP_CLASS_HID_02e3 = 0x02e3, - BNXT_ULP_CLASS_HID_39a7 = 0x39a7, - BNXT_ULP_CLASS_HID_2657 = 0x2657, - BNXT_ULP_CLASS_HID_120b = 0x120b, BNXT_ULP_CLASS_HID_48cf = 0x48cf, - BNXT_ULP_CLASS_HID_35ff = 0x35ff, - BNXT_ULP_CLASS_HID_0ff7 = 0x0ff7, - BNXT_ULP_CLASS_HID_5953 = 0x5953, - BNXT_ULP_CLASS_HID_336b = 0x336b, - BNXT_ULP_CLASS_HID_201b = 0x201b, - BNXT_ULP_CLASS_HID_257f7 = 0x257f7, - BNXT_ULP_CLASS_HID_2858b = 0x2858b, - BNXT_ULP_CLASS_HID_3108b = 0x3108b, - BNXT_ULP_CLASS_HID_39b8b = 0x39b8b, - BNXT_ULP_CLASS_HID_24427 = 0x24427, - BNXT_ULP_CLASS_HID_2cf27 = 0x2cf27, - BNXT_ULP_CLASS_HID_35a27 = 0x35a27, - BNXT_ULP_CLASS_HID_388fb = 0x388fb, - BNXT_ULP_CLASS_HID_23ffb = 0x23ffb, - BNXT_ULP_CLASS_HID_2cafb = 0x2cafb, - BNXT_ULP_CLASS_HID_355fb = 0x355fb, - BNXT_ULP_CLASS_HID_3838f = 0x3838f, - BNXT_ULP_CLASS_HID_2528b = 0x2528b, - BNXT_ULP_CLASS_HID_2815f = 0x2815f, - BNXT_ULP_CLASS_HID_30c5f = 0x30c5f, - BNXT_ULP_CLASS_HID_3975f = 0x3975f, - BNXT_ULP_CLASS_HID_21e3f = 0x21e3f, - BNXT_ULP_CLASS_HID_2a93f = 0x2a93f, - BNXT_ULP_CLASS_HID_3343f = 0x3343f, - BNXT_ULP_CLASS_HID_3bf3f = 0x3bf3f, - BNXT_ULP_CLASS_HID_20b6f = 0x20b6f, - BNXT_ULP_CLASS_HID_2966f = 0x2966f, - BNXT_ULP_CLASS_HID_3216f = 0x3216f, - BNXT_ULP_CLASS_HID_3ac6f = 0x3ac6f, - BNXT_ULP_CLASS_HID_20623 = 0x20623, - BNXT_ULP_CLASS_HID_29123 = 0x29123, - BNXT_ULP_CLASS_HID_31c23 = 0x31c23, - BNXT_ULP_CLASS_HID_3a723 = 0x3a723, - BNXT_ULP_CLASS_HID_219f3 = 0x219f3, - BNXT_ULP_CLASS_HID_2a4f3 = 0x2a4f3, - BNXT_ULP_CLASS_HID_32ff3 = 0x32ff3, - BNXT_ULP_CLASS_HID_3baf3 = 0x3baf3, - BNXT_ULP_CLASS_HID_24253 = 0x24253, - BNXT_ULP_CLASS_HID_2cd53 = 0x2cd53, - BNXT_ULP_CLASS_HID_35853 = 0x35853, - BNXT_ULP_CLASS_HID_38667 = 0x38667, - BNXT_ULP_CLASS_HID_22e83 = 0x22e83, - BNXT_ULP_CLASS_HID_2b983 = 0x2b983, - BNXT_ULP_CLASS_HID_34483 = 0x34483, - BNXT_ULP_CLASS_HID_3cf83 = 0x3cf83, - BNXT_ULP_CLASS_HID_22a57 = 0x22a57, - BNXT_ULP_CLASS_HID_2b557 = 0x2b557, - BNXT_ULP_CLASS_HID_34057 = 0x34057, - BNXT_ULP_CLASS_HID_3cb57 = 0x3cb57, - BNXT_ULP_CLASS_HID_23d67 = 0x23d67, - BNXT_ULP_CLASS_HID_2c867 = 0x2c867, - BNXT_ULP_CLASS_HID_35367 = 0x35367, - BNXT_ULP_CLASS_HID_3813b = 0x3813b, - BNXT_ULP_CLASS_HID_2089b = 0x2089b, - BNXT_ULP_CLASS_HID_2939b = 0x2939b, - BNXT_ULP_CLASS_HID_31e9b = 0x31e9b, - BNXT_ULP_CLASS_HID_3a99b = 0x3a99b, - BNXT_ULP_CLASS_HID_25237 = 0x25237, - BNXT_ULP_CLASS_HID_280cb = 0x280cb, - BNXT_ULP_CLASS_HID_30bcb = 0x30bcb, - BNXT_ULP_CLASS_HID_396cb = 0x396cb, - BNXT_ULP_CLASS_HID_24dcb = 0x24dcb, - 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BNXT_ULP_CLASS_HID_353ce = 0x353ce, - BNXT_ULP_CLASS_HID_421a = 0x421a, - BNXT_ULP_CLASS_HID_11d56 = 0x11d56, - BNXT_ULP_CLASS_HID_23356 = 0x23356, - BNXT_ULP_CLASS_HID_32956 = 0x32956, - BNXT_ULP_CLASS_HID_0cf6 = 0x0cf6, - BNXT_ULP_CLASS_HID_122f6 = 0x122f6, - BNXT_ULP_CLASS_HID_258f6 = 0x258f6, - BNXT_ULP_CLASS_HID_313c2 = 0x313c2, - BNXT_ULP_CLASS_HID_312a = 0x312a, - BNXT_ULP_CLASS_HID_1272a = 0x1272a, - BNXT_ULP_CLASS_HID_25d2a = 0x25d2a, - BNXT_ULP_CLASS_HID_31466 = 0x31466, - BNXT_ULP_CLASS_HID_46be = 0x46be, - BNXT_ULP_CLASS_HID_1018a = 0x1018a, - BNXT_ULP_CLASS_HID_2378a = 0x2378a, - BNXT_ULP_CLASS_HID_32d8a = 0x32d8a, - BNXT_ULP_CLASS_HID_5cc6 = 0x5cc6, - BNXT_ULP_CLASS_HID_11712 = 0x11712, - BNXT_ULP_CLASS_HID_20d12 = 0x20d12, - BNXT_ULP_CLASS_HID_32312 = 0x32312, - BNXT_ULP_CLASS_HID_06b2 = 0x06b2, - BNXT_ULP_CLASS_HID_13cb2 = 0x13cb2, - BNXT_ULP_CLASS_HID_252b2 = 0x252b2, - BNXT_ULP_CLASS_HID_348b2 = 0x348b2, - BNXT_ULP_CLASS_HID_1c5e = 0x1c5e, - BNXT_ULP_CLASS_HID_1325e = 0x1325e, - BNXT_ULP_CLASS_HID_2285e = 0x2285e, - BNXT_ULP_CLASS_HID_35e5e = 0x35e5e, - BNXT_ULP_CLASS_HID_55e2 = 0x55e2, - BNXT_ULP_CLASS_HID_14be2 = 0x14be2, - BNXT_ULP_CLASS_HID_2023e = 0x2023e, - BNXT_ULP_CLASS_HID_3383e = 0x3383e, - BNXT_ULP_CLASS_HID_2b0a = 0x2b0a, - BNXT_ULP_CLASS_HID_1410a = 0x1410a, - BNXT_ULP_CLASS_HID_21846 = 0x21846, - BNXT_ULP_CLASS_HID_30e46 = 0x30e46, - BNXT_ULP_CLASS_HID_15e6 = 0x15e6, - BNXT_ULP_CLASS_HID_10be6 = 0x10be6, - BNXT_ULP_CLASS_HID_221e6 = 0x221e6, - BNXT_ULP_CLASS_HID_357e6 = 0x357e6, - BNXT_ULP_CLASS_HID_161a = 0x161a, - BNXT_ULP_CLASS_HID_10c1a = 0x10c1a, - BNXT_ULP_CLASS_HID_2221a = 0x2221a, - BNXT_ULP_CLASS_HID_3581a = 0x3581a, - BNXT_ULP_CLASS_HID_2fae = 0x2fae, - BNXT_ULP_CLASS_HID_145ae = 0x145ae, - BNXT_ULP_CLASS_HID_21cfa = 0x21cfa, - BNXT_ULP_CLASS_HID_332fa = 0x332fa, - BNXT_ULP_CLASS_HID_2536 = 0x2536, - BNXT_ULP_CLASS_HID_15b36 = 0x15b36, - BNXT_ULP_CLASS_HID_21202 = 0x21202, - BNXT_ULP_CLASS_HID_30802 = 0x30802, - BNXT_ULP_CLASS_HID_4b56 = 0x4b56, - BNXT_ULP_CLASS_HID_105a2 = 0x105a2, - BNXT_ULP_CLASS_HID_23ba2 = 0x23ba2, - BNXT_ULP_CLASS_HID_351a2 = 0x351a2, - BNXT_ULP_CLASS_HID_10c6 = 0x10c6, - BNXT_ULP_CLASS_HID_106c6 = 0x106c6, - BNXT_ULP_CLASS_HID_23cc6 = 0x23cc6, - BNXT_ULP_CLASS_HID_352c6 = 0x352c6, - BNXT_ULP_CLASS_HID_266a = 0x266a, - BNXT_ULP_CLASS_HID_15c6a = 0x15c6a, - BNXT_ULP_CLASS_HID_216a6 = 0x216a6, - BNXT_ULP_CLASS_HID_30ca6 = 0x30ca6, - BNXT_ULP_CLASS_HID_3ff2 = 0x3ff2, - BNXT_ULP_CLASS_HID_155f2 = 0x155f2, - BNXT_ULP_CLASS_HID_24bf2 = 0x24bf2, - BNXT_ULP_CLASS_HID_302ce = 0x302ce, - BNXT_ULP_CLASS_HID_4512 = 0x4512, - BNXT_ULP_CLASS_HID_11c6e = 0x11c6e, - BNXT_ULP_CLASS_HID_2326e = 0x2326e, - BNXT_ULP_CLASS_HID_3286e = 0x3286e, - BNXT_ULP_CLASS_HID_49b6 = 0x49b6, - BNXT_ULP_CLASS_HID_10082 = 0x10082, - BNXT_ULP_CLASS_HID_23682 = 0x23682, - BNXT_ULP_CLASS_HID_32c82 = 0x32c82, - BNXT_ULP_CLASS_HID_2016 = 0x2016, - BNXT_ULP_CLASS_HID_15616 = 0x15616, - BNXT_ULP_CLASS_HID_21162 = 0x21162, - BNXT_ULP_CLASS_HID_30762 = 0x30762, - BNXT_ULP_CLASS_HID_39be = 0x39be, - BNXT_ULP_CLASS_HID_12fbe = 0x12fbe, - BNXT_ULP_CLASS_HID_245be = 0x245be, - BNXT_ULP_CLASS_HID_31c8a = 0x31c8a, - BNXT_ULP_CLASS_HID_5fde = 0x5fde, - BNXT_ULP_CLASS_HID_1162a = 0x1162a, - BNXT_ULP_CLASS_HID_20c2a = 0x20c2a, - BNXT_ULP_CLASS_HID_3222a = 0x3222a, - BNXT_ULP_CLASS_HID_34de = 0x34de, - BNXT_ULP_CLASS_HID_3a12 = 0x3a12, - BNXT_ULP_CLASS_HID_14f2 = 0x14f2, - BNXT_ULP_CLASS_HID_4a62 = 0x4a62, - BNXT_ULP_CLASS_HID_370e = 0x370e, - BNXT_ULP_CLASS_HID_12d0e = 0x12d0e, - BNXT_ULP_CLASS_HID_2430e = 0x2430e, - BNXT_ULP_CLASS_HID_31dda = 0x31dda, - BNXT_ULP_CLASS_HID_11ae = 0x11ae, - BNXT_ULP_CLASS_HID_107ae = 0x107ae, - BNXT_ULP_CLASS_HID_23dae = 0x23dae, - BNXT_ULP_CLASS_HID_353ae = 0x353ae, - BNXT_ULP_CLASS_HID_427a = 0x427a, - BNXT_ULP_CLASS_HID_11d36 = 0x11d36, - BNXT_ULP_CLASS_HID_23336 = 0x23336, - BNXT_ULP_CLASS_HID_32936 = 0x32936, - BNXT_ULP_CLASS_HID_0c96 = 0x0c96, - BNXT_ULP_CLASS_HID_12296 = 0x12296, - BNXT_ULP_CLASS_HID_25896 = 0x25896, - BNXT_ULP_CLASS_HID_313a2 = 0x313a2, - BNXT_ULP_CLASS_HID_314a = 0x314a, - BNXT_ULP_CLASS_HID_1274a = 0x1274a, - BNXT_ULP_CLASS_HID_25d4a = 0x25d4a, - BNXT_ULP_CLASS_HID_31406 = 0x31406, - BNXT_ULP_CLASS_HID_46de = 0x46de, - BNXT_ULP_CLASS_HID_101ea = 0x101ea, - BNXT_ULP_CLASS_HID_237ea = 0x237ea, - BNXT_ULP_CLASS_HID_32dea = 0x32dea, - BNXT_ULP_CLASS_HID_5ca6 = 0x5ca6, - BNXT_ULP_CLASS_HID_11772 = 0x11772, - BNXT_ULP_CLASS_HID_20d72 = 0x20d72, - BNXT_ULP_CLASS_HID_32372 = 0x32372, - BNXT_ULP_CLASS_HID_06d2 = 0x06d2, - BNXT_ULP_CLASS_HID_13cd2 = 0x13cd2, - BNXT_ULP_CLASS_HID_252d2 = 0x252d2, - BNXT_ULP_CLASS_HID_348d2 = 0x348d2, - BNXT_ULP_CLASS_HID_1c3e = 0x1c3e, - BNXT_ULP_CLASS_HID_1323e = 0x1323e, - BNXT_ULP_CLASS_HID_2283e = 0x2283e, - BNXT_ULP_CLASS_HID_35e3e = 0x35e3e, - BNXT_ULP_CLASS_HID_5582 = 0x5582, - BNXT_ULP_CLASS_HID_14b82 = 0x14b82, - BNXT_ULP_CLASS_HID_2025e = 0x2025e, - BNXT_ULP_CLASS_HID_3385e = 0x3385e, - BNXT_ULP_CLASS_HID_2b6a = 0x2b6a, - BNXT_ULP_CLASS_HID_1416a = 0x1416a, - BNXT_ULP_CLASS_HID_21826 = 0x21826, - BNXT_ULP_CLASS_HID_30e26 = 0x30e26, - BNXT_ULP_CLASS_HID_1586 = 0x1586, - BNXT_ULP_CLASS_HID_10b86 = 0x10b86, - BNXT_ULP_CLASS_HID_22186 = 0x22186, - BNXT_ULP_CLASS_HID_35786 = 0x35786, - BNXT_ULP_CLASS_HID_167a = 0x167a, - BNXT_ULP_CLASS_HID_10c7a = 0x10c7a, - BNXT_ULP_CLASS_HID_2227a = 0x2227a, - BNXT_ULP_CLASS_HID_3587a = 0x3587a, - BNXT_ULP_CLASS_HID_2fce = 0x2fce, - BNXT_ULP_CLASS_HID_145ce = 0x145ce, - BNXT_ULP_CLASS_HID_21c9a = 0x21c9a, - BNXT_ULP_CLASS_HID_3329a = 0x3329a, - BNXT_ULP_CLASS_HID_2556 = 0x2556, - BNXT_ULP_CLASS_HID_15b56 = 0x15b56, - BNXT_ULP_CLASS_HID_21262 = 0x21262, - BNXT_ULP_CLASS_HID_30862 = 0x30862, - BNXT_ULP_CLASS_HID_4b36 = 0x4b36, - BNXT_ULP_CLASS_HID_105c2 = 0x105c2, - BNXT_ULP_CLASS_HID_23bc2 = 0x23bc2, - BNXT_ULP_CLASS_HID_351c2 = 0x351c2, - BNXT_ULP_CLASS_HID_10a6 = 0x10a6, - BNXT_ULP_CLASS_HID_106a6 = 0x106a6, - BNXT_ULP_CLASS_HID_23ca6 = 0x23ca6, - BNXT_ULP_CLASS_HID_352a6 = 0x352a6, - BNXT_ULP_CLASS_HID_260a = 0x260a, - BNXT_ULP_CLASS_HID_15c0a = 0x15c0a, - BNXT_ULP_CLASS_HID_216c6 = 0x216c6, - BNXT_ULP_CLASS_HID_30cc6 = 0x30cc6, - BNXT_ULP_CLASS_HID_3f92 = 0x3f92, - BNXT_ULP_CLASS_HID_15592 = 0x15592, - BNXT_ULP_CLASS_HID_24b92 = 0x24b92, - BNXT_ULP_CLASS_HID_302ae = 0x302ae, - BNXT_ULP_CLASS_HID_4572 = 0x4572, - BNXT_ULP_CLASS_HID_11c0e = 0x11c0e, - BNXT_ULP_CLASS_HID_2320e = 0x2320e, - BNXT_ULP_CLASS_HID_3280e = 0x3280e, - BNXT_ULP_CLASS_HID_49d6 = 0x49d6, - BNXT_ULP_CLASS_HID_100e2 = 0x100e2, - BNXT_ULP_CLASS_HID_236e2 = 0x236e2, - BNXT_ULP_CLASS_HID_32ce2 = 0x32ce2, - BNXT_ULP_CLASS_HID_2076 = 0x2076, - BNXT_ULP_CLASS_HID_15676 = 0x15676, - BNXT_ULP_CLASS_HID_21102 = 0x21102, - BNXT_ULP_CLASS_HID_30702 = 0x30702, - BNXT_ULP_CLASS_HID_39de = 0x39de, - BNXT_ULP_CLASS_HID_12fde = 0x12fde, - BNXT_ULP_CLASS_HID_245de = 0x245de, - BNXT_ULP_CLASS_HID_31cea = 0x31cea, - BNXT_ULP_CLASS_HID_5fbe = 0x5fbe, - BNXT_ULP_CLASS_HID_1164a = 0x1164a, - BNXT_ULP_CLASS_HID_20c4a = 0x20c4a, - BNXT_ULP_CLASS_HID_3224a = 0x3224a, - BNXT_ULP_CLASS_HID_34be = 0x34be, - BNXT_ULP_CLASS_HID_3a72 = 0x3a72, - BNXT_ULP_CLASS_HID_1492 = 0x1492, - BNXT_ULP_CLASS_HID_4a02 = 0x4a02, - BNXT_ULP_CLASS_HID_09ea = 0x09ea, - BNXT_ULP_CLASS_HID_2912 = 0x2912, - BNXT_ULP_CLASS_HID_03b2 = 0x03b2, - BNXT_ULP_CLASS_HID_5f7e = 0x5f7e, - BNXT_ULP_CLASS_HID_03a6 = 0x03a6, - BNXT_ULP_CLASS_HID_23ce = 0x23ce, - BNXT_ULP_CLASS_HID_1a6e = 0x1a6e, - BNXT_ULP_CLASS_HID_593a = 0x593a, - BNXT_ULP_CLASS_HID_4dce = 0x4dce, - BNXT_ULP_CLASS_HID_0e02 = 0x0e02, - BNXT_ULP_CLASS_HID_4796 = 0x4796, - BNXT_ULP_CLASS_HID_246e = 0x246e, - BNXT_ULP_CLASS_HID_478a = 0x478a, - BNXT_ULP_CLASS_HID_08fe = 0x08fe, - BNXT_ULP_CLASS_HID_5e52 = 0x5e52, - BNXT_ULP_CLASS_HID_3e2a = 0x3e2a, - BNXT_ULP_CLASS_HID_5e46 = 0x5e46, - BNXT_ULP_CLASS_HID_02ba = 0x02ba, - BNXT_ULP_CLASS_HID_580e = 0x580e, - BNXT_ULP_CLASS_HID_38e6 = 0x38e6, - BNXT_ULP_CLASS_HID_5802 = 0x5802, - BNXT_ULP_CLASS_HID_1d76 = 0x1d76, - BNXT_ULP_CLASS_HID_52ca = 0x52ca, - BNXT_ULP_CLASS_HID_32a2 = 0x32a2, - BNXT_ULP_CLASS_HID_34f6 = 0x34f6, - BNXT_ULP_CLASS_HID_3a3a = 0x3a3a, - BNXT_ULP_CLASS_HID_5a22 = 0x5a22, - BNXT_ULP_CLASS_HID_541e = 0x541e, - BNXT_ULP_CLASS_HID_09ca = 0x09ca, - BNXT_ULP_CLASS_HID_0216 = 0x0216, - BNXT_ULP_CLASS_HID_1f62 = 0x1f62, - BNXT_ULP_CLASS_HID_1bae = 0x1bae, - BNXT_ULP_CLASS_HID_2932 = 0x2932, - BNXT_ULP_CLASS_HID_227e = 0x227e, - BNXT_ULP_CLASS_HID_3f4a = 0x3f4a, - BNXT_ULP_CLASS_HID_3b96 = 0x3b96, - BNXT_ULP_CLASS_HID_0392 = 0x0392, - BNXT_ULP_CLASS_HID_1cde = 0x1cde, - BNXT_ULP_CLASS_HID_192a = 0x192a, - BNXT_ULP_CLASS_HID_1276 = 0x1276, - BNXT_ULP_CLASS_HID_5f5e = 0x5f5e, - BNXT_ULP_CLASS_HID_5baa = 0x5baa, - BNXT_ULP_CLASS_HID_54f6 = 0x54f6, - BNXT_ULP_CLASS_HID_51c2 = 0x51c2, - BNXT_ULP_CLASS_HID_0386 = 0x0386, - BNXT_ULP_CLASS_HID_1cd2 = 0x1cd2, - BNXT_ULP_CLASS_HID_191e = 0x191e, - BNXT_ULP_CLASS_HID_126a = 0x126a, - BNXT_ULP_CLASS_HID_23ee = 0x23ee, - BNXT_ULP_CLASS_HID_3c3a = 0x3c3a, - BNXT_ULP_CLASS_HID_3906 = 0x3906, - BNXT_ULP_CLASS_HID_3252 = 0x3252, - BNXT_ULP_CLASS_HID_1a4e = 0x1a4e, - BNXT_ULP_CLASS_HID_169a = 0x169a, - BNXT_ULP_CLASS_HID_13e6 = 0x13e6, - BNXT_ULP_CLASS_HID_4be6 = 0x4be6, - BNXT_ULP_CLASS_HID_591a = 0x591a, - BNXT_ULP_CLASS_HID_5266 = 0x5266, - BNXT_ULP_CLASS_HID_2eb2 = 0x2eb2, - BNXT_ULP_CLASS_HID_2bfe = 0x2bfe, - BNXT_ULP_CLASS_HID_4dee = 0x4dee, - BNXT_ULP_CLASS_HID_463a = 0x463a, - BNXT_ULP_CLASS_HID_4306 = 0x4306, - BNXT_ULP_CLASS_HID_5c52 = 0x5c52, - BNXT_ULP_CLASS_HID_0e22 = 0x0e22, - BNXT_ULP_CLASS_HID_0b6e = 0x0b6e, - BNXT_ULP_CLASS_HID_07ba = 0x07ba, - BNXT_ULP_CLASS_HID_0086 = 0x0086, - BNXT_ULP_CLASS_HID_47b6 = 0x47b6, - BNXT_ULP_CLASS_HID_4082 = 0x4082, - BNXT_ULP_CLASS_HID_5dce = 0x5dce, - BNXT_ULP_CLASS_HID_561a = 0x561a, - BNXT_ULP_CLASS_HID_244e = 0x244e, - BNXT_ULP_CLASS_HID_209a = 0x209a, - BNXT_ULP_CLASS_HID_3de6 = 0x3de6, - BNXT_ULP_CLASS_HID_3632 = 0x3632, - BNXT_ULP_CLASS_HID_47aa = 0x47aa, - BNXT_ULP_CLASS_HID_40f6 = 0x40f6, - BNXT_ULP_CLASS_HID_5dc2 = 0x5dc2, - BNXT_ULP_CLASS_HID_560e = 0x560e, - BNXT_ULP_CLASS_HID_08de = 0x08de, - BNXT_ULP_CLASS_HID_052a = 0x052a, - BNXT_ULP_CLASS_HID_1e76 = 0x1e76, - BNXT_ULP_CLASS_HID_1b42 = 0x1b42, - BNXT_ULP_CLASS_HID_5e72 = 0x5e72, - BNXT_ULP_CLASS_HID_5abe = 0x5abe, - BNXT_ULP_CLASS_HID_578a = 0x578a, - BNXT_ULP_CLASS_HID_50d6 = 0x50d6, - BNXT_ULP_CLASS_HID_3e0a = 0x3e0a, - BNXT_ULP_CLASS_HID_3b56 = 0x3b56, - BNXT_ULP_CLASS_HID_37a2 = 0x37a2, - BNXT_ULP_CLASS_HID_30ee = 0x30ee, - BNXT_ULP_CLASS_HID_5e66 = 0x5e66, - BNXT_ULP_CLASS_HID_5ab2 = 0x5ab2, - BNXT_ULP_CLASS_HID_57fe = 0x57fe, - BNXT_ULP_CLASS_HID_50ca = 0x50ca, - BNXT_ULP_CLASS_HID_029a = 0x029a, - BNXT_ULP_CLASS_HID_1fe6 = 0x1fe6, - BNXT_ULP_CLASS_HID_1832 = 0x1832, - BNXT_ULP_CLASS_HID_157e = 0x157e, - BNXT_ULP_CLASS_HID_582e = 0x582e, - BNXT_ULP_CLASS_HID_557a = 0x557a, - BNXT_ULP_CLASS_HID_2e46 = 0x2e46, - BNXT_ULP_CLASS_HID_2a92 = 0x2a92, - BNXT_ULP_CLASS_HID_38c6 = 0x38c6, - BNXT_ULP_CLASS_HID_3512 = 0x3512, - BNXT_ULP_CLASS_HID_0e5e = 0x0e5e, - BNXT_ULP_CLASS_HID_0aaa = 0x0aaa, - BNXT_ULP_CLASS_HID_5822 = 0x5822, - BNXT_ULP_CLASS_HID_556e = 0x556e, - BNXT_ULP_CLASS_HID_51ba = 0x51ba, - BNXT_ULP_CLASS_HID_2a86 = 0x2a86, - BNXT_ULP_CLASS_HID_1d56 = 0x1d56, - BNXT_ULP_CLASS_HID_19a2 = 0x19a2, - BNXT_ULP_CLASS_HID_12ee = 0x12ee, - BNXT_ULP_CLASS_HID_4aee = 0x4aee, - BNXT_ULP_CLASS_HID_52ea = 0x52ea, - BNXT_ULP_CLASS_HID_2f36 = 0x2f36, - BNXT_ULP_CLASS_HID_2802 = 0x2802, - BNXT_ULP_CLASS_HID_254e = 0x254e, - BNXT_ULP_CLASS_HID_3282 = 0x3282, - BNXT_ULP_CLASS_HID_0fce = 0x0fce, - BNXT_ULP_CLASS_HID_081a = 0x081a, - BNXT_ULP_CLASS_HID_0566 = 0x0566, - BNXT_ULP_CLASS_HID_34d6 = 0x34d6, - BNXT_ULP_CLASS_HID_3a1a = 0x3a1a, - BNXT_ULP_CLASS_HID_5a02 = 0x5a02, - BNXT_ULP_CLASS_HID_543e = 0x543e, - BNXT_ULP_CLASS_HID_09aa = 0x09aa, - BNXT_ULP_CLASS_HID_0276 = 0x0276, - BNXT_ULP_CLASS_HID_1f02 = 0x1f02, - BNXT_ULP_CLASS_HID_1bce = 0x1bce, - BNXT_ULP_CLASS_HID_2952 = 0x2952, - BNXT_ULP_CLASS_HID_221e = 0x221e, - BNXT_ULP_CLASS_HID_3f2a = 0x3f2a, - BNXT_ULP_CLASS_HID_3bf6 = 0x3bf6, - BNXT_ULP_CLASS_HID_03f2 = 0x03f2, - BNXT_ULP_CLASS_HID_1cbe = 0x1cbe, - BNXT_ULP_CLASS_HID_194a = 0x194a, - BNXT_ULP_CLASS_HID_1216 = 0x1216, - BNXT_ULP_CLASS_HID_5f3e = 0x5f3e, - BNXT_ULP_CLASS_HID_5bca = 0x5bca, - BNXT_ULP_CLASS_HID_5496 = 0x5496, - BNXT_ULP_CLASS_HID_51a2 = 0x51a2, - BNXT_ULP_CLASS_HID_03e6 = 0x03e6, - BNXT_ULP_CLASS_HID_1cb2 = 0x1cb2, - BNXT_ULP_CLASS_HID_197e = 0x197e, - BNXT_ULP_CLASS_HID_120a = 0x120a, - BNXT_ULP_CLASS_HID_238e = 0x238e, - BNXT_ULP_CLASS_HID_3c5a = 0x3c5a, - BNXT_ULP_CLASS_HID_3966 = 0x3966, - BNXT_ULP_CLASS_HID_3232 = 0x3232, - BNXT_ULP_CLASS_HID_1a2e = 0x1a2e, - BNXT_ULP_CLASS_HID_16fa = 0x16fa, - BNXT_ULP_CLASS_HID_1386 = 0x1386, - BNXT_ULP_CLASS_HID_4b86 = 0x4b86, - BNXT_ULP_CLASS_HID_597a = 0x597a, - BNXT_ULP_CLASS_HID_5206 = 0x5206, - BNXT_ULP_CLASS_HID_2ed2 = 0x2ed2, - BNXT_ULP_CLASS_HID_2b9e = 0x2b9e, - BNXT_ULP_CLASS_HID_4d8e = 0x4d8e, - BNXT_ULP_CLASS_HID_465a = 0x465a, - BNXT_ULP_CLASS_HID_4366 = 0x4366, - BNXT_ULP_CLASS_HID_5c32 = 0x5c32, - BNXT_ULP_CLASS_HID_0e42 = 0x0e42, - BNXT_ULP_CLASS_HID_0b0e = 0x0b0e, - BNXT_ULP_CLASS_HID_07da = 0x07da, - BNXT_ULP_CLASS_HID_00e6 = 0x00e6, - BNXT_ULP_CLASS_HID_47d6 = 0x47d6, - BNXT_ULP_CLASS_HID_40e2 = 0x40e2, - BNXT_ULP_CLASS_HID_5dae = 0x5dae, - BNXT_ULP_CLASS_HID_567a = 0x567a, - BNXT_ULP_CLASS_HID_242e = 0x242e, - BNXT_ULP_CLASS_HID_20fa = 0x20fa, - BNXT_ULP_CLASS_HID_3d86 = 0x3d86, - BNXT_ULP_CLASS_HID_3652 = 0x3652, - BNXT_ULP_CLASS_HID_47ca = 0x47ca, - BNXT_ULP_CLASS_HID_4096 = 0x4096, - BNXT_ULP_CLASS_HID_5da2 = 0x5da2, - BNXT_ULP_CLASS_HID_566e = 0x566e, - BNXT_ULP_CLASS_HID_08be = 0x08be, - BNXT_ULP_CLASS_HID_054a = 0x054a, - BNXT_ULP_CLASS_HID_1e16 = 0x1e16, - BNXT_ULP_CLASS_HID_1b22 = 0x1b22, - BNXT_ULP_CLASS_HID_5e12 = 0x5e12, - BNXT_ULP_CLASS_HID_5ade = 0x5ade, - BNXT_ULP_CLASS_HID_57ea = 0x57ea, - BNXT_ULP_CLASS_HID_50b6 = 0x50b6, - BNXT_ULP_CLASS_HID_3e6a = 0x3e6a, - BNXT_ULP_CLASS_HID_3b36 = 0x3b36, - BNXT_ULP_CLASS_HID_37c2 = 0x37c2, - BNXT_ULP_CLASS_HID_308e = 0x308e, - BNXT_ULP_CLASS_HID_5e06 = 0x5e06, - BNXT_ULP_CLASS_HID_5ad2 = 0x5ad2, - BNXT_ULP_CLASS_HID_579e = 0x579e, - BNXT_ULP_CLASS_HID_50aa = 0x50aa, - BNXT_ULP_CLASS_HID_02fa = 0x02fa, - BNXT_ULP_CLASS_HID_1f86 = 0x1f86, - BNXT_ULP_CLASS_HID_1852 = 0x1852, - BNXT_ULP_CLASS_HID_151e = 0x151e, - BNXT_ULP_CLASS_HID_584e = 0x584e, - BNXT_ULP_CLASS_HID_551a = 0x551a, - BNXT_ULP_CLASS_HID_2e26 = 0x2e26, - BNXT_ULP_CLASS_HID_2af2 = 0x2af2, - BNXT_ULP_CLASS_HID_38a6 = 0x38a6, - BNXT_ULP_CLASS_HID_3572 = 0x3572, - BNXT_ULP_CLASS_HID_0e3e = 0x0e3e, - BNXT_ULP_CLASS_HID_0aca = 0x0aca, - BNXT_ULP_CLASS_HID_5842 = 0x5842, - BNXT_ULP_CLASS_HID_550e = 0x550e, - BNXT_ULP_CLASS_HID_51da = 0x51da, - BNXT_ULP_CLASS_HID_2ae6 = 0x2ae6, - BNXT_ULP_CLASS_HID_1d36 = 0x1d36, - BNXT_ULP_CLASS_HID_19c2 = 0x19c2, - BNXT_ULP_CLASS_HID_128e = 0x128e, - BNXT_ULP_CLASS_HID_4a8e = 0x4a8e, - BNXT_ULP_CLASS_HID_528a = 0x528a, - BNXT_ULP_CLASS_HID_2f56 = 0x2f56, - BNXT_ULP_CLASS_HID_2862 = 0x2862, - BNXT_ULP_CLASS_HID_252e = 0x252e, - BNXT_ULP_CLASS_HID_32e2 = 0x32e2, - BNXT_ULP_CLASS_HID_0fae = 0x0fae, - BNXT_ULP_CLASS_HID_087a = 0x087a, - BNXT_ULP_CLASS_HID_0506 = 0x0506, - BNXT_ULP_CLASS_HID_34b6 = 0x34b6, - BNXT_ULP_CLASS_HID_3a7a = 0x3a7a, - BNXT_ULP_CLASS_HID_5a62 = 0x5a62, - BNXT_ULP_CLASS_HID_545e = 0x545e, - BNXT_ULP_CLASS_HID_a73c = 0xa73c, - BNXT_ULP_CLASS_HID_a040 = 0xa040, - BNXT_ULP_CLASS_HID_1d640 = 0x1d640, - BNXT_ULP_CLASS_HID_1dd3c = 0x1dd3c, - BNXT_ULP_CLASS_HID_cba0 = 0xcba0, - BNXT_ULP_CLASS_HID_c4f4 = 0xc4f4, - BNXT_ULP_CLASS_HID_19f38 = 0x19f38, - BNXT_ULP_CLASS_HID_182f4 = 0x182f4, - BNXT_ULP_CLASS_HID_b098 = 0xb098, - BNXT_ULP_CLASS_HID_8dac = 0x8dac, - BNXT_ULP_CLASS_HID_1a3ac = 0x1a3ac, - BNXT_ULP_CLASS_HID_1a698 = 0x1a698, - BNXT_ULP_CLASS_HID_d50c = 0xd50c, - BNXT_ULP_CLASS_HID_ae50 = 0xae50, - BNXT_ULP_CLASS_HID_1c450 = 0x1c450, - BNXT_ULP_CLASS_HID_1cb0c = 0x1cb0c, - BNXT_ULP_CLASS_HID_a1f0 = 0xa1f0, - BNXT_ULP_CLASS_HID_ba04 = 0xba04, - BNXT_ULP_CLASS_HID_1d004 = 0x1d004, - BNXT_ULP_CLASS_HID_1d7f0 = 0x1d7f0, - BNXT_ULP_CLASS_HID_c264 = 0xc264, - BNXT_ULP_CLASS_HID_dea8 = 0xdea8, - BNXT_ULP_CLASS_HID_199fc = 0x199fc, - BNXT_ULP_CLASS_HID_19ca8 = 0x19ca8, - BNXT_ULP_CLASS_HID_8b5c = 0x8b5c, - BNXT_ULP_CLASS_HID_8460 = 0x8460, - BNXT_ULP_CLASS_HID_1ba60 = 0x1ba60, - BNXT_ULP_CLASS_HID_1a15c = 0x1a15c, - BNXT_ULP_CLASS_HID_afc0 = 0xafc0, - BNXT_ULP_CLASS_HID_a814 = 0xa814, - BNXT_ULP_CLASS_HID_1de14 = 0x1de14, - BNXT_ULP_CLASS_HID_1c5c0 = 0x1c5c0, - BNXT_ULP_CLASS_HID_8c2c = 0x8c2c, - BNXT_ULP_CLASS_HID_8970 = 0x8970, - BNXT_ULP_CLASS_HID_1bf70 = 0x1bf70, - BNXT_ULP_CLASS_HID_1a22c = 0x1a22c, - BNXT_ULP_CLASS_HID_d0d0 = 0xd0d0, - BNXT_ULP_CLASS_HID_ade4 = 0xade4, - BNXT_ULP_CLASS_HID_1c3e4 = 0x1c3e4, - BNXT_ULP_CLASS_HID_1c6d0 = 0x1c6d0, - BNXT_ULP_CLASS_HID_9988 = 0x9988, - BNXT_ULP_CLASS_HID_92dc = 0x92dc, - BNXT_ULP_CLASS_HID_188dc = 0x188dc, - BNXT_ULP_CLASS_HID_18f88 = 0x18f88, - BNXT_ULP_CLASS_HID_ba3c = 0xba3c, - BNXT_ULP_CLASS_HID_b740 = 0xb740, - BNXT_ULP_CLASS_HID_1ad40 = 0x1ad40, - BNXT_ULP_CLASS_HID_1d03c = 0x1d03c, - BNXT_ULP_CLASS_HID_86e0 = 0x86e0, - BNXT_ULP_CLASS_HID_8334 = 0x8334, - BNXT_ULP_CLASS_HID_1b934 = 0x1b934, - BNXT_ULP_CLASS_HID_1bce0 = 0x1bce0, - BNXT_ULP_CLASS_HID_aa94 = 0xaa94, - BNXT_ULP_CLASS_HID_a7d8 = 0xa7d8, - BNXT_ULP_CLASS_HID_1ddd8 = 0x1ddd8, - BNXT_ULP_CLASS_HID_1c094 = 0x1c094, - BNXT_ULP_CLASS_HID_904c = 0x904c, - BNXT_ULP_CLASS_HID_c84c = 0xc84c, - BNXT_ULP_CLASS_HID_18290 = 0x18290, - BNXT_ULP_CLASS_HID_1864c = 0x1864c, - BNXT_ULP_CLASS_HID_b4f0 = 0xb4f0, - BNXT_ULP_CLASS_HID_b104 = 0xb104, - BNXT_ULP_CLASS_HID_1a704 = 0x1a704, - BNXT_ULP_CLASS_HID_1aaf0 = 0x1aaf0, - BNXT_ULP_CLASS_HID_80a4 = 0x80a4, - BNXT_ULP_CLASS_HID_9de8 = 0x9de8, - BNXT_ULP_CLASS_HID_1b3e8 = 0x1b3e8, - BNXT_ULP_CLASS_HID_1b6a4 = 0x1b6a4, - BNXT_ULP_CLASS_HID_a548 = 0xa548, - BNXT_ULP_CLASS_HID_a19c = 0xa19c, - BNXT_ULP_CLASS_HID_1d79c = 0x1d79c, - BNXT_ULP_CLASS_HID_1db48 = 0x1db48, - BNXT_ULP_CLASS_HID_9a98 = 0x9a98, - BNXT_ULP_CLASS_HID_97ac = 0x97ac, - BNXT_ULP_CLASS_HID_18dac = 0x18dac, - BNXT_ULP_CLASS_HID_1b098 = 0x1b098, - BNXT_ULP_CLASS_HID_bf0c = 0xbf0c, - BNXT_ULP_CLASS_HID_b850 = 0xb850, - BNXT_ULP_CLASS_HID_1ae50 = 0x1ae50, - BNXT_ULP_CLASS_HID_1d50c = 0x1d50c, - BNXT_ULP_CLASS_HID_34f0 = 0x34f0, - BNXT_ULP_CLASS_HID_3a3c = 0x3a3c, - BNXT_ULP_CLASS_HID_3740 = 0x3740, - BNXT_ULP_CLASS_HID_5ea0 = 0x5ea0, - BNXT_ULP_CLASS_HID_5bf4 = 0x5bf4, - BNXT_ULP_CLASS_HID_0798 = 0x0798, - BNXT_ULP_CLASS_HID_00ac = 0x00ac, - BNXT_ULP_CLASS_HID_280c = 0x280c, - BNXT_ULP_CLASS_HID_2550 = 0x2550, - BNXT_ULP_CLASS_HID_3104 = 0x3104, - BNXT_ULP_CLASS_HID_5964 = 0x5964, - BNXT_ULP_CLASS_HID_55a8 = 0x55a8, - BNXT_ULP_CLASS_HID_1e5c = 0x1e5c, - BNXT_ULP_CLASS_HID_1b60 = 0x1b60, - BNXT_ULP_CLASS_HID_22c0 = 0x22c0, - BNXT_ULP_CLASS_HID_3f14 = 0x3f14, - BNXT_ULP_CLASS_HID_a71c = 0xa71c, - BNXT_ULP_CLASS_HID_a8dc = 0xa8dc, - BNXT_ULP_CLASS_HID_ed9c = 0xed9c, - BNXT_ULP_CLASS_HID_ef5c = 0xef5c, - BNXT_ULP_CLASS_HID_a060 = 0xa060, - BNXT_ULP_CLASS_HID_a520 = 0xa520, - BNXT_ULP_CLASS_HID_e6e0 = 0xe6e0, - BNXT_ULP_CLASS_HID_eba0 = 0xeba0, - BNXT_ULP_CLASS_HID_1d660 = 0x1d660, - BNXT_ULP_CLASS_HID_1fb20 = 0x1fb20, - BNXT_ULP_CLASS_HID_1dce0 = 0x1dce0, - BNXT_ULP_CLASS_HID_1e1a0 = 0x1e1a0, - BNXT_ULP_CLASS_HID_1dd1c = 0x1dd1c, - BNXT_ULP_CLASS_HID_1fedc = 0x1fedc, - BNXT_ULP_CLASS_HID_1c39c = 0x1c39c, - BNXT_ULP_CLASS_HID_1e55c = 0x1e55c, - BNXT_ULP_CLASS_HID_cb80 = 0xcb80, - BNXT_ULP_CLASS_HID_b194 = 0xb194, - BNXT_ULP_CLASS_HID_d354 = 0xd354, - BNXT_ULP_CLASS_HID_f414 = 0xf414, - BNXT_ULP_CLASS_HID_c4d4 = 0xc4d4, - BNXT_ULP_CLASS_HID_e994 = 0xe994, - BNXT_ULP_CLASS_HID_cb54 = 0xcb54, - BNXT_ULP_CLASS_HID_f158 = 0xf158, - BNXT_ULP_CLASS_HID_19f18 = 0x19f18, - BNXT_ULP_CLASS_HID_1a0d8 = 0x1a0d8, - BNXT_ULP_CLASS_HID_1c598 = 0x1c598, - BNXT_ULP_CLASS_HID_1e758 = 0x1e758, - BNXT_ULP_CLASS_HID_182d4 = 0x182d4, - BNXT_ULP_CLASS_HID_1a794 = 0x1a794, - BNXT_ULP_CLASS_HID_1c954 = 0x1c954, - BNXT_ULP_CLASS_HID_1ea14 = 0x1ea14, - BNXT_ULP_CLASS_HID_b0b8 = 0xb0b8, - BNXT_ULP_CLASS_HID_b278 = 0xb278, - BNXT_ULP_CLASS_HID_f738 = 0xf738, - BNXT_ULP_CLASS_HID_f8f8 = 0xf8f8, - BNXT_ULP_CLASS_HID_8d8c = 0x8d8c, - BNXT_ULP_CLASS_HID_af4c = 0xaf4c, - BNXT_ULP_CLASS_HID_f00c = 0xf00c, - BNXT_ULP_CLASS_HID_f5cc = 0xf5cc, - BNXT_ULP_CLASS_HID_1a38c = 0x1a38c, - BNXT_ULP_CLASS_HID_1a54c = 0x1a54c, - BNXT_ULP_CLASS_HID_1e60c = 0x1e60c, - BNXT_ULP_CLASS_HID_1ebcc = 0x1ebcc, - BNXT_ULP_CLASS_HID_1a6b8 = 0x1a6b8, - BNXT_ULP_CLASS_HID_1a878 = 0x1a878, - BNXT_ULP_CLASS_HID_1ed38 = 0x1ed38, - BNXT_ULP_CLASS_HID_1eef8 = 0x1eef8, - BNXT_ULP_CLASS_HID_d52c = 0xd52c, - BNXT_ULP_CLASS_HID_f6ec = 0xf6ec, - BNXT_ULP_CLASS_HID_dbac = 0xdbac, - BNXT_ULP_CLASS_HID_fd6c = 0xfd6c, - BNXT_ULP_CLASS_HID_ae70 = 0xae70, - BNXT_ULP_CLASS_HID_f330 = 0xf330, - BNXT_ULP_CLASS_HID_d4f0 = 0xd4f0, - BNXT_ULP_CLASS_HID_f9b0 = 0xf9b0, - BNXT_ULP_CLASS_HID_1c470 = 0x1c470, - BNXT_ULP_CLASS_HID_1e930 = 0x1e930, - BNXT_ULP_CLASS_HID_1caf0 = 0x1caf0, - BNXT_ULP_CLASS_HID_1f084 = 0x1f084, - BNXT_ULP_CLASS_HID_1cb2c = 0x1cb2c, - BNXT_ULP_CLASS_HID_1b130 = 0x1b130, - BNXT_ULP_CLASS_HID_1d2f0 = 0x1d2f0, - BNXT_ULP_CLASS_HID_1f7b0 = 0x1f7b0, - BNXT_ULP_CLASS_HID_a1d0 = 0xa1d0, - BNXT_ULP_CLASS_HID_a290 = 0xa290, - BNXT_ULP_CLASS_HID_e450 = 0xe450, - BNXT_ULP_CLASS_HID_e910 = 0xe910, - BNXT_ULP_CLASS_HID_ba24 = 0xba24, - BNXT_ULP_CLASS_HID_bfe4 = 0xbfe4, - BNXT_ULP_CLASS_HID_e0a4 = 0xe0a4, - BNXT_ULP_CLASS_HID_e264 = 0xe264, - BNXT_ULP_CLASS_HID_1d024 = 0x1d024, - BNXT_ULP_CLASS_HID_1f5e4 = 0x1f5e4, - BNXT_ULP_CLASS_HID_1d6a4 = 0x1d6a4, - BNXT_ULP_CLASS_HID_1f864 = 0x1f864, - BNXT_ULP_CLASS_HID_1d7d0 = 0x1d7d0, - BNXT_ULP_CLASS_HID_1f890 = 0x1f890, - BNXT_ULP_CLASS_HID_1da50 = 0x1da50, - BNXT_ULP_CLASS_HID_1ff10 = 0x1ff10, - BNXT_ULP_CLASS_HID_c244 = 0xc244, - BNXT_ULP_CLASS_HID_e704 = 0xe704, - BNXT_ULP_CLASS_HID_c8c4 = 0xc8c4, - BNXT_ULP_CLASS_HID_ed84 = 0xed84, - BNXT_ULP_CLASS_HID_de88 = 0xde88, - BNXT_ULP_CLASS_HID_e048 = 0xe048, - BNXT_ULP_CLASS_HID_c508 = 0xc508, - BNXT_ULP_CLASS_HID_e6c8 = 0xe6c8, - BNXT_ULP_CLASS_HID_199dc = 0x199dc, - BNXT_ULP_CLASS_HID_1ba9c = 0x1ba9c, - BNXT_ULP_CLASS_HID_1dc5c = 0x1dc5c, - BNXT_ULP_CLASS_HID_1e11c = 0x1e11c, - BNXT_ULP_CLASS_HID_19c88 = 0x19c88, - BNXT_ULP_CLASS_HID_1be48 = 0x1be48, - BNXT_ULP_CLASS_HID_1c308 = 0x1c308, - BNXT_ULP_CLASS_HID_1e4c8 = 0x1e4c8, - BNXT_ULP_CLASS_HID_8b7c = 0x8b7c, - BNXT_ULP_CLASS_HID_ac3c = 0xac3c, - BNXT_ULP_CLASS_HID_f1fc = 0xf1fc, - BNXT_ULP_CLASS_HID_f2bc = 0xf2bc, - BNXT_ULP_CLASS_HID_8440 = 0x8440, - BNXT_ULP_CLASS_HID_a900 = 0xa900, - BNXT_ULP_CLASS_HID_cac0 = 0xcac0, - BNXT_ULP_CLASS_HID_ef80 = 0xef80, - BNXT_ULP_CLASS_HID_1ba40 = 0x1ba40, - BNXT_ULP_CLASS_HID_1bf00 = 0x1bf00, - BNXT_ULP_CLASS_HID_1e0c0 = 0x1e0c0, - BNXT_ULP_CLASS_HID_1e580 = 0x1e580, - BNXT_ULP_CLASS_HID_1a17c = 0x1a17c, - BNXT_ULP_CLASS_HID_1a23c = 0x1a23c, - BNXT_ULP_CLASS_HID_1e7fc = 0x1e7fc, - BNXT_ULP_CLASS_HID_1e8bc = 0x1e8bc, - BNXT_ULP_CLASS_HID_afe0 = 0xafe0, - BNXT_ULP_CLASS_HID_f0a0 = 0xf0a0, - BNXT_ULP_CLASS_HID_d260 = 0xd260, - BNXT_ULP_CLASS_HID_f720 = 0xf720, - BNXT_ULP_CLASS_HID_a834 = 0xa834, - BNXT_ULP_CLASS_HID_adf4 = 0xadf4, - BNXT_ULP_CLASS_HID_eeb4 = 0xeeb4, - BNXT_ULP_CLASS_HID_f074 = 0xf074, - BNXT_ULP_CLASS_HID_1de34 = 0x1de34, - BNXT_ULP_CLASS_HID_1e3f4 = 0x1e3f4, - BNXT_ULP_CLASS_HID_1c4b4 = 0x1c4b4, - BNXT_ULP_CLASS_HID_1e674 = 0x1e674, - BNXT_ULP_CLASS_HID_1c5e0 = 0x1c5e0, - BNXT_ULP_CLASS_HID_1e6a0 = 0x1e6a0, - BNXT_ULP_CLASS_HID_1c860 = 0x1c860, - BNXT_ULP_CLASS_HID_1ed20 = 0x1ed20, - BNXT_ULP_CLASS_HID_8c0c = 0x8c0c, - BNXT_ULP_CLASS_HID_b1cc = 0xb1cc, - BNXT_ULP_CLASS_HID_f28c = 0xf28c, - BNXT_ULP_CLASS_HID_f44c = 0xf44c, - BNXT_ULP_CLASS_HID_8950 = 0x8950, - BNXT_ULP_CLASS_HID_aa10 = 0xaa10, - BNXT_ULP_CLASS_HID_cfd0 = 0xcfd0, - BNXT_ULP_CLASS_HID_f090 = 0xf090, - BNXT_ULP_CLASS_HID_1bf50 = 0x1bf50, - BNXT_ULP_CLASS_HID_1a010 = 0x1a010, - BNXT_ULP_CLASS_HID_1e5d0 = 0x1e5d0, - BNXT_ULP_CLASS_HID_1e690 = 0x1e690, - BNXT_ULP_CLASS_HID_1a20c = 0x1a20c, - BNXT_ULP_CLASS_HID_1a7cc = 0x1a7cc, - BNXT_ULP_CLASS_HID_1e88c = 0x1e88c, - BNXT_ULP_CLASS_HID_1ea4c = 0x1ea4c, - BNXT_ULP_CLASS_HID_d0f0 = 0xd0f0, - BNXT_ULP_CLASS_HID_f5b0 = 0xf5b0, - BNXT_ULP_CLASS_HID_d770 = 0xd770, - BNXT_ULP_CLASS_HID_f830 = 0xf830, - BNXT_ULP_CLASS_HID_adc4 = 0xadc4, - BNXT_ULP_CLASS_HID_ae84 = 0xae84, - BNXT_ULP_CLASS_HID_d044 = 0xd044, - BNXT_ULP_CLASS_HID_f504 = 0xf504, - BNXT_ULP_CLASS_HID_1c3c4 = 0x1c3c4, - BNXT_ULP_CLASS_HID_1e484 = 0x1e484, - BNXT_ULP_CLASS_HID_1c644 = 0x1c644, - BNXT_ULP_CLASS_HID_1eb04 = 0x1eb04, - BNXT_ULP_CLASS_HID_1c6f0 = 0x1c6f0, - BNXT_ULP_CLASS_HID_1ebb0 = 0x1ebb0, - BNXT_ULP_CLASS_HID_1cd70 = 0x1cd70, - BNXT_ULP_CLASS_HID_1f304 = 0x1f304, - BNXT_ULP_CLASS_HID_99a8 = 0x99a8, - BNXT_ULP_CLASS_HID_bb68 = 0xbb68, - BNXT_ULP_CLASS_HID_dc28 = 0xdc28, - BNXT_ULP_CLASS_HID_e1e8 = 0xe1e8, - BNXT_ULP_CLASS_HID_92fc = 0x92fc, - BNXT_ULP_CLASS_HID_b7bc = 0xb7bc, - BNXT_ULP_CLASS_HID_d97c = 0xd97c, - BNXT_ULP_CLASS_HID_fa3c = 0xfa3c, - BNXT_ULP_CLASS_HID_188fc = 0x188fc, - BNXT_ULP_CLASS_HID_1adbc = 0x1adbc, - BNXT_ULP_CLASS_HID_1cf7c = 0x1cf7c, - BNXT_ULP_CLASS_HID_1f03c = 0x1f03c, - BNXT_ULP_CLASS_HID_18fa8 = 0x18fa8, - BNXT_ULP_CLASS_HID_1b168 = 0x1b168, - BNXT_ULP_CLASS_HID_1f228 = 0x1f228, - BNXT_ULP_CLASS_HID_1f7e8 = 0x1f7e8, - BNXT_ULP_CLASS_HID_ba1c = 0xba1c, - BNXT_ULP_CLASS_HID_bfdc = 0xbfdc, - BNXT_ULP_CLASS_HID_e09c = 0xe09c, - BNXT_ULP_CLASS_HID_e25c = 0xe25c, - BNXT_ULP_CLASS_HID_b760 = 0xb760, - BNXT_ULP_CLASS_HID_b820 = 0xb820, - BNXT_ULP_CLASS_HID_fde0 = 0xfde0, - BNXT_ULP_CLASS_HID_fea0 = 0xfea0, - BNXT_ULP_CLASS_HID_1ad60 = 0x1ad60, - BNXT_ULP_CLASS_HID_1ae20 = 0x1ae20, - BNXT_ULP_CLASS_HID_1d3e0 = 0x1d3e0, - BNXT_ULP_CLASS_HID_1f4a0 = 0x1f4a0, - BNXT_ULP_CLASS_HID_1d01c = 0x1d01c, - BNXT_ULP_CLASS_HID_1f5dc = 0x1f5dc, - BNXT_ULP_CLASS_HID_1d69c = 0x1d69c, - BNXT_ULP_CLASS_HID_1f85c = 0x1f85c, - BNXT_ULP_CLASS_HID_86c0 = 0x86c0, - BNXT_ULP_CLASS_HID_ab80 = 0xab80, - BNXT_ULP_CLASS_HID_cd40 = 0xcd40, - BNXT_ULP_CLASS_HID_ee00 = 0xee00, - BNXT_ULP_CLASS_HID_8314 = 0x8314, - BNXT_ULP_CLASS_HID_a4d4 = 0xa4d4, - BNXT_ULP_CLASS_HID_c994 = 0xc994, - BNXT_ULP_CLASS_HID_eb54 = 0xeb54, - BNXT_ULP_CLASS_HID_1b914 = 0x1b914, - BNXT_ULP_CLASS_HID_1bad4 = 0x1bad4, - BNXT_ULP_CLASS_HID_1ff94 = 0x1ff94, - BNXT_ULP_CLASS_HID_1e154 = 0x1e154, - BNXT_ULP_CLASS_HID_1bcc0 = 0x1bcc0, - BNXT_ULP_CLASS_HID_1a180 = 0x1a180, - BNXT_ULP_CLASS_HID_1e340 = 0x1e340, - BNXT_ULP_CLASS_HID_1e400 = 0x1e400, - BNXT_ULP_CLASS_HID_aab4 = 0xaab4, - BNXT_ULP_CLASS_HID_ac74 = 0xac74, - BNXT_ULP_CLASS_HID_d134 = 0xd134, - BNXT_ULP_CLASS_HID_f2f4 = 0xf2f4, - BNXT_ULP_CLASS_HID_a7f8 = 0xa7f8, - BNXT_ULP_CLASS_HID_a8b8 = 0xa8b8, - BNXT_ULP_CLASS_HID_ea78 = 0xea78, - BNXT_ULP_CLASS_HID_ef38 = 0xef38, - BNXT_ULP_CLASS_HID_1ddf8 = 0x1ddf8, - BNXT_ULP_CLASS_HID_1feb8 = 0x1feb8, - BNXT_ULP_CLASS_HID_1c078 = 0x1c078, - BNXT_ULP_CLASS_HID_1e538 = 0x1e538, - BNXT_ULP_CLASS_HID_1c0b4 = 0x1c0b4, - BNXT_ULP_CLASS_HID_1e274 = 0x1e274, - BNXT_ULP_CLASS_HID_1c734 = 0x1c734, - BNXT_ULP_CLASS_HID_1e8f4 = 0x1e8f4, - BNXT_ULP_CLASS_HID_906c = 0x906c, - BNXT_ULP_CLASS_HID_b52c = 0xb52c, - BNXT_ULP_CLASS_HID_d6ec = 0xd6ec, - BNXT_ULP_CLASS_HID_fbac = 0xfbac, - BNXT_ULP_CLASS_HID_c86c = 0xc86c, - BNXT_ULP_CLASS_HID_ed2c = 0xed2c, - BNXT_ULP_CLASS_HID_d330 = 0xd330, - BNXT_ULP_CLASS_HID_f4f0 = 0xf4f0, - BNXT_ULP_CLASS_HID_182b0 = 0x182b0, - BNXT_ULP_CLASS_HID_1a470 = 0x1a470, - BNXT_ULP_CLASS_HID_1c930 = 0x1c930, - BNXT_ULP_CLASS_HID_1eaf0 = 0x1eaf0, - BNXT_ULP_CLASS_HID_1866c = 0x1866c, - BNXT_ULP_CLASS_HID_1ab2c = 0x1ab2c, - BNXT_ULP_CLASS_HID_1ccec = 0x1ccec, - BNXT_ULP_CLASS_HID_1f1ac = 0x1f1ac, - BNXT_ULP_CLASS_HID_b4d0 = 0xb4d0, - BNXT_ULP_CLASS_HID_b990 = 0xb990, - BNXT_ULP_CLASS_HID_fb50 = 0xfb50, - BNXT_ULP_CLASS_HID_fc10 = 0xfc10, - BNXT_ULP_CLASS_HID_b124 = 0xb124, - BNXT_ULP_CLASS_HID_b2e4 = 0xb2e4, - BNXT_ULP_CLASS_HID_f7a4 = 0xf7a4, - BNXT_ULP_CLASS_HID_f964 = 0xf964, - BNXT_ULP_CLASS_HID_1a724 = 0x1a724, - BNXT_ULP_CLASS_HID_1a8e4 = 0x1a8e4, - BNXT_ULP_CLASS_HID_1eda4 = 0x1eda4, - BNXT_ULP_CLASS_HID_1ef64 = 0x1ef64, - BNXT_ULP_CLASS_HID_1aad0 = 0x1aad0, - BNXT_ULP_CLASS_HID_1af90 = 0x1af90, - BNXT_ULP_CLASS_HID_1d150 = 0x1d150, - BNXT_ULP_CLASS_HID_1f210 = 0x1f210, - BNXT_ULP_CLASS_HID_8084 = 0x8084, - BNXT_ULP_CLASS_HID_a244 = 0xa244, - BNXT_ULP_CLASS_HID_c704 = 0xc704, - BNXT_ULP_CLASS_HID_e8c4 = 0xe8c4, - BNXT_ULP_CLASS_HID_9dc8 = 0x9dc8, - BNXT_ULP_CLASS_HID_be88 = 0xbe88, - BNXT_ULP_CLASS_HID_c048 = 0xc048, - BNXT_ULP_CLASS_HID_e508 = 0xe508, - BNXT_ULP_CLASS_HID_1b3c8 = 0x1b3c8, - BNXT_ULP_CLASS_HID_1b488 = 0x1b488, - BNXT_ULP_CLASS_HID_1f648 = 0x1f648, - BNXT_ULP_CLASS_HID_1fb08 = 0x1fb08, - BNXT_ULP_CLASS_HID_1b684 = 0x1b684, - BNXT_ULP_CLASS_HID_1b844 = 0x1b844, - BNXT_ULP_CLASS_HID_1fd04 = 0x1fd04, - BNXT_ULP_CLASS_HID_1fec4 = 0x1fec4, - BNXT_ULP_CLASS_HID_a568 = 0xa568, - BNXT_ULP_CLASS_HID_a628 = 0xa628, - BNXT_ULP_CLASS_HID_ebe8 = 0xebe8, - BNXT_ULP_CLASS_HID_eca8 = 0xeca8, - BNXT_ULP_CLASS_HID_a1bc = 0xa1bc, - BNXT_ULP_CLASS_HID_a37c = 0xa37c, - BNXT_ULP_CLASS_HID_e43c = 0xe43c, - BNXT_ULP_CLASS_HID_e9fc = 0xe9fc, - BNXT_ULP_CLASS_HID_1d7bc = 0x1d7bc, - BNXT_ULP_CLASS_HID_1f97c = 0x1f97c, - BNXT_ULP_CLASS_HID_1da3c = 0x1da3c, - BNXT_ULP_CLASS_HID_1fffc = 0x1fffc, - BNXT_ULP_CLASS_HID_1db68 = 0x1db68, - BNXT_ULP_CLASS_HID_1fc28 = 0x1fc28, - BNXT_ULP_CLASS_HID_1c1e8 = 0x1c1e8, - BNXT_ULP_CLASS_HID_1e2a8 = 0x1e2a8, - BNXT_ULP_CLASS_HID_9ab8 = 0x9ab8, - BNXT_ULP_CLASS_HID_bc78 = 0xbc78, - BNXT_ULP_CLASS_HID_c138 = 0xc138, - BNXT_ULP_CLASS_HID_e2f8 = 0xe2f8, - BNXT_ULP_CLASS_HID_978c = 0x978c, - BNXT_ULP_CLASS_HID_b94c = 0xb94c, - BNXT_ULP_CLASS_HID_da0c = 0xda0c, - BNXT_ULP_CLASS_HID_ffcc = 0xffcc, - BNXT_ULP_CLASS_HID_18d8c = 0x18d8c, - BNXT_ULP_CLASS_HID_1af4c = 0x1af4c, - BNXT_ULP_CLASS_HID_1f00c = 0x1f00c, - BNXT_ULP_CLASS_HID_1f5cc = 0x1f5cc, - BNXT_ULP_CLASS_HID_1b0b8 = 0x1b0b8, - BNXT_ULP_CLASS_HID_1b278 = 0x1b278, - BNXT_ULP_CLASS_HID_1f738 = 0x1f738, - BNXT_ULP_CLASS_HID_1f8f8 = 0x1f8f8, - BNXT_ULP_CLASS_HID_bf2c = 0xbf2c, - BNXT_ULP_CLASS_HID_a0ec = 0xa0ec, - BNXT_ULP_CLASS_HID_e5ac = 0xe5ac, - BNXT_ULP_CLASS_HID_e76c = 0xe76c, - BNXT_ULP_CLASS_HID_b870 = 0xb870, - BNXT_ULP_CLASS_HID_bd30 = 0xbd30, - BNXT_ULP_CLASS_HID_fef0 = 0xfef0, - BNXT_ULP_CLASS_HID_e3b0 = 0xe3b0, - BNXT_ULP_CLASS_HID_1ae70 = 0x1ae70, - BNXT_ULP_CLASS_HID_1f330 = 0x1f330, - BNXT_ULP_CLASS_HID_1d4f0 = 0x1d4f0, - BNXT_ULP_CLASS_HID_1f9b0 = 0x1f9b0, - BNXT_ULP_CLASS_HID_1d52c = 0x1d52c, - BNXT_ULP_CLASS_HID_1f6ec = 0x1f6ec, - BNXT_ULP_CLASS_HID_1dbac = 0x1dbac, - BNXT_ULP_CLASS_HID_1fd6c = 0x1fd6c, - BNXT_ULP_CLASS_HID_34d0 = 0x34d0, - BNXT_ULP_CLASS_HID_3a1c = 0x3a1c, - BNXT_ULP_CLASS_HID_3760 = 0x3760, - BNXT_ULP_CLASS_HID_5e80 = 0x5e80, - BNXT_ULP_CLASS_HID_5bd4 = 0x5bd4, - BNXT_ULP_CLASS_HID_07b8 = 0x07b8, - BNXT_ULP_CLASS_HID_008c = 0x008c, - BNXT_ULP_CLASS_HID_282c = 0x282c, - BNXT_ULP_CLASS_HID_2570 = 0x2570, - BNXT_ULP_CLASS_HID_3124 = 0x3124, - BNXT_ULP_CLASS_HID_5944 = 0x5944, - BNXT_ULP_CLASS_HID_5588 = 0x5588, - BNXT_ULP_CLASS_HID_1e7c = 0x1e7c, - BNXT_ULP_CLASS_HID_1b40 = 0x1b40, - BNXT_ULP_CLASS_HID_22e0 = 0x22e0, - BNXT_ULP_CLASS_HID_3f34 = 0x3f34, - BNXT_ULP_CLASS_HID_a77c = 0xa77c, - BNXT_ULP_CLASS_HID_a8bc = 0xa8bc, - BNXT_ULP_CLASS_HID_edfc = 0xedfc, - BNXT_ULP_CLASS_HID_ef3c = 0xef3c, - BNXT_ULP_CLASS_HID_a000 = 0xa000, - BNXT_ULP_CLASS_HID_a540 = 0xa540, - BNXT_ULP_CLASS_HID_e680 = 0xe680, - BNXT_ULP_CLASS_HID_ebc0 = 0xebc0, - BNXT_ULP_CLASS_HID_1d600 = 0x1d600, - BNXT_ULP_CLASS_HID_1fb40 = 0x1fb40, - BNXT_ULP_CLASS_HID_1dc80 = 0x1dc80, - BNXT_ULP_CLASS_HID_1e1c0 = 0x1e1c0, - BNXT_ULP_CLASS_HID_1dd7c = 0x1dd7c, - BNXT_ULP_CLASS_HID_1febc = 0x1febc, - BNXT_ULP_CLASS_HID_1c3fc = 0x1c3fc, - BNXT_ULP_CLASS_HID_1e53c = 0x1e53c, - BNXT_ULP_CLASS_HID_cbe0 = 0xcbe0, - BNXT_ULP_CLASS_HID_b1f4 = 0xb1f4, - BNXT_ULP_CLASS_HID_d334 = 0xd334, - BNXT_ULP_CLASS_HID_f474 = 0xf474, - BNXT_ULP_CLASS_HID_c4b4 = 0xc4b4, - BNXT_ULP_CLASS_HID_e9f4 = 0xe9f4, - BNXT_ULP_CLASS_HID_cb34 = 0xcb34, - BNXT_ULP_CLASS_HID_f138 = 0xf138, - BNXT_ULP_CLASS_HID_19f78 = 0x19f78, - BNXT_ULP_CLASS_HID_1a0b8 = 0x1a0b8, - BNXT_ULP_CLASS_HID_1c5f8 = 0x1c5f8, - BNXT_ULP_CLASS_HID_1e738 = 0x1e738, - BNXT_ULP_CLASS_HID_182b4 = 0x182b4, - BNXT_ULP_CLASS_HID_1a7f4 = 0x1a7f4, - BNXT_ULP_CLASS_HID_1c934 = 0x1c934, - BNXT_ULP_CLASS_HID_1ea74 = 0x1ea74, - BNXT_ULP_CLASS_HID_b0d8 = 0xb0d8, - BNXT_ULP_CLASS_HID_b218 = 0xb218, - BNXT_ULP_CLASS_HID_f758 = 0xf758, - BNXT_ULP_CLASS_HID_f898 = 0xf898, - BNXT_ULP_CLASS_HID_8dec = 0x8dec, - BNXT_ULP_CLASS_HID_af2c = 0xaf2c, - BNXT_ULP_CLASS_HID_f06c = 0xf06c, - BNXT_ULP_CLASS_HID_f5ac = 0xf5ac, - BNXT_ULP_CLASS_HID_1a3ec = 0x1a3ec, - BNXT_ULP_CLASS_HID_1a52c = 0x1a52c, - BNXT_ULP_CLASS_HID_1e66c = 0x1e66c, - BNXT_ULP_CLASS_HID_1ebac = 0x1ebac, - BNXT_ULP_CLASS_HID_1a6d8 = 0x1a6d8, - BNXT_ULP_CLASS_HID_1a818 = 0x1a818, - BNXT_ULP_CLASS_HID_1ed58 = 0x1ed58, - BNXT_ULP_CLASS_HID_1ee98 = 0x1ee98, - BNXT_ULP_CLASS_HID_d54c = 0xd54c, - BNXT_ULP_CLASS_HID_f68c = 0xf68c, - BNXT_ULP_CLASS_HID_dbcc = 0xdbcc, - BNXT_ULP_CLASS_HID_fd0c = 0xfd0c, - BNXT_ULP_CLASS_HID_ae10 = 0xae10, - BNXT_ULP_CLASS_HID_f350 = 0xf350, - BNXT_ULP_CLASS_HID_d490 = 0xd490, - BNXT_ULP_CLASS_HID_f9d0 = 0xf9d0, - BNXT_ULP_CLASS_HID_1c410 = 0x1c410, - BNXT_ULP_CLASS_HID_1e950 = 0x1e950, - BNXT_ULP_CLASS_HID_1ca90 = 0x1ca90, - BNXT_ULP_CLASS_HID_1f0e4 = 0x1f0e4, - BNXT_ULP_CLASS_HID_1cb4c = 0x1cb4c, - BNXT_ULP_CLASS_HID_1b150 = 0x1b150, - BNXT_ULP_CLASS_HID_1d290 = 0x1d290, - BNXT_ULP_CLASS_HID_1f7d0 = 0x1f7d0, - BNXT_ULP_CLASS_HID_a1b0 = 0xa1b0, - BNXT_ULP_CLASS_HID_a2f0 = 0xa2f0, - BNXT_ULP_CLASS_HID_e430 = 0xe430, - BNXT_ULP_CLASS_HID_e970 = 0xe970, - BNXT_ULP_CLASS_HID_ba44 = 0xba44, - BNXT_ULP_CLASS_HID_bf84 = 0xbf84, - BNXT_ULP_CLASS_HID_e0c4 = 0xe0c4, - BNXT_ULP_CLASS_HID_e204 = 0xe204, - BNXT_ULP_CLASS_HID_1d044 = 0x1d044, - BNXT_ULP_CLASS_HID_1f584 = 0x1f584, - BNXT_ULP_CLASS_HID_1d6c4 = 0x1d6c4, - BNXT_ULP_CLASS_HID_1f804 = 0x1f804, - BNXT_ULP_CLASS_HID_1d7b0 = 0x1d7b0, - BNXT_ULP_CLASS_HID_1f8f0 = 0x1f8f0, - BNXT_ULP_CLASS_HID_1da30 = 0x1da30, - BNXT_ULP_CLASS_HID_1ff70 = 0x1ff70, - BNXT_ULP_CLASS_HID_c224 = 0xc224, - BNXT_ULP_CLASS_HID_e764 = 0xe764, - BNXT_ULP_CLASS_HID_c8a4 = 0xc8a4, - BNXT_ULP_CLASS_HID_ede4 = 0xede4, - BNXT_ULP_CLASS_HID_dee8 = 0xdee8, - BNXT_ULP_CLASS_HID_e028 = 0xe028, - BNXT_ULP_CLASS_HID_c568 = 0xc568, - BNXT_ULP_CLASS_HID_e6a8 = 0xe6a8, - BNXT_ULP_CLASS_HID_199bc = 0x199bc, - BNXT_ULP_CLASS_HID_1bafc = 0x1bafc, - BNXT_ULP_CLASS_HID_1dc3c = 0x1dc3c, - BNXT_ULP_CLASS_HID_1e17c = 0x1e17c, - BNXT_ULP_CLASS_HID_19ce8 = 0x19ce8, - BNXT_ULP_CLASS_HID_1be28 = 0x1be28, - BNXT_ULP_CLASS_HID_1c368 = 0x1c368, - BNXT_ULP_CLASS_HID_1e4a8 = 0x1e4a8, - BNXT_ULP_CLASS_HID_8b1c = 0x8b1c, - BNXT_ULP_CLASS_HID_ac5c = 0xac5c, - BNXT_ULP_CLASS_HID_f19c = 0xf19c, - BNXT_ULP_CLASS_HID_f2dc = 0xf2dc, - BNXT_ULP_CLASS_HID_8420 = 0x8420, - BNXT_ULP_CLASS_HID_a960 = 0xa960, - BNXT_ULP_CLASS_HID_caa0 = 0xcaa0, - BNXT_ULP_CLASS_HID_efe0 = 0xefe0, - BNXT_ULP_CLASS_HID_1ba20 = 0x1ba20, - BNXT_ULP_CLASS_HID_1bf60 = 0x1bf60, - BNXT_ULP_CLASS_HID_1e0a0 = 0x1e0a0, - BNXT_ULP_CLASS_HID_1e5e0 = 0x1e5e0, - BNXT_ULP_CLASS_HID_1a11c = 0x1a11c, - BNXT_ULP_CLASS_HID_1a25c = 0x1a25c, - BNXT_ULP_CLASS_HID_1e79c = 0x1e79c, - BNXT_ULP_CLASS_HID_1e8dc = 0x1e8dc, - BNXT_ULP_CLASS_HID_af80 = 0xaf80, - BNXT_ULP_CLASS_HID_f0c0 = 0xf0c0, - BNXT_ULP_CLASS_HID_d200 = 0xd200, - BNXT_ULP_CLASS_HID_f740 = 0xf740, - BNXT_ULP_CLASS_HID_a854 = 0xa854, - BNXT_ULP_CLASS_HID_ad94 = 0xad94, - BNXT_ULP_CLASS_HID_eed4 = 0xeed4, - BNXT_ULP_CLASS_HID_f014 = 0xf014, - BNXT_ULP_CLASS_HID_1de54 = 0x1de54, - BNXT_ULP_CLASS_HID_1e394 = 0x1e394, - BNXT_ULP_CLASS_HID_1c4d4 = 0x1c4d4, - BNXT_ULP_CLASS_HID_1e614 = 0x1e614, - BNXT_ULP_CLASS_HID_1c580 = 0x1c580, - BNXT_ULP_CLASS_HID_1e6c0 = 0x1e6c0, - BNXT_ULP_CLASS_HID_1c800 = 0x1c800, - BNXT_ULP_CLASS_HID_1ed40 = 0x1ed40, - BNXT_ULP_CLASS_HID_8c6c = 0x8c6c, - BNXT_ULP_CLASS_HID_b1ac = 0xb1ac, - BNXT_ULP_CLASS_HID_f2ec = 0xf2ec, - BNXT_ULP_CLASS_HID_f42c = 0xf42c, - BNXT_ULP_CLASS_HID_8930 = 0x8930, - BNXT_ULP_CLASS_HID_aa70 = 0xaa70, - BNXT_ULP_CLASS_HID_cfb0 = 0xcfb0, - BNXT_ULP_CLASS_HID_f0f0 = 0xf0f0, - BNXT_ULP_CLASS_HID_1bf30 = 0x1bf30, - BNXT_ULP_CLASS_HID_1a070 = 0x1a070, - BNXT_ULP_CLASS_HID_1e5b0 = 0x1e5b0, - BNXT_ULP_CLASS_HID_1e6f0 = 0x1e6f0, - BNXT_ULP_CLASS_HID_1a26c = 0x1a26c, - BNXT_ULP_CLASS_HID_1a7ac = 0x1a7ac, - BNXT_ULP_CLASS_HID_1e8ec = 0x1e8ec, - BNXT_ULP_CLASS_HID_1ea2c = 0x1ea2c, - BNXT_ULP_CLASS_HID_d090 = 0xd090, - BNXT_ULP_CLASS_HID_f5d0 = 0xf5d0, - BNXT_ULP_CLASS_HID_d710 = 0xd710, - BNXT_ULP_CLASS_HID_f850 = 0xf850, - BNXT_ULP_CLASS_HID_ada4 = 0xada4, - BNXT_ULP_CLASS_HID_aee4 = 0xaee4, - BNXT_ULP_CLASS_HID_d024 = 0xd024, - BNXT_ULP_CLASS_HID_f564 = 0xf564, - BNXT_ULP_CLASS_HID_1c3a4 = 0x1c3a4, - BNXT_ULP_CLASS_HID_1e4e4 = 0x1e4e4, - BNXT_ULP_CLASS_HID_1c624 = 0x1c624, - BNXT_ULP_CLASS_HID_1eb64 = 0x1eb64, - BNXT_ULP_CLASS_HID_1c690 = 0x1c690, - BNXT_ULP_CLASS_HID_1ebd0 = 0x1ebd0, - BNXT_ULP_CLASS_HID_1cd10 = 0x1cd10, - BNXT_ULP_CLASS_HID_1f364 = 0x1f364, - BNXT_ULP_CLASS_HID_99c8 = 0x99c8, - BNXT_ULP_CLASS_HID_bb08 = 0xbb08, - BNXT_ULP_CLASS_HID_dc48 = 0xdc48, - BNXT_ULP_CLASS_HID_e188 = 0xe188, - BNXT_ULP_CLASS_HID_929c = 0x929c, - BNXT_ULP_CLASS_HID_b7dc = 0xb7dc, - BNXT_ULP_CLASS_HID_d91c = 0xd91c, - BNXT_ULP_CLASS_HID_fa5c = 0xfa5c, - BNXT_ULP_CLASS_HID_1889c = 0x1889c, - BNXT_ULP_CLASS_HID_1addc = 0x1addc, - BNXT_ULP_CLASS_HID_1cf1c = 0x1cf1c, - BNXT_ULP_CLASS_HID_1f05c = 0x1f05c, - BNXT_ULP_CLASS_HID_18fc8 = 0x18fc8, - BNXT_ULP_CLASS_HID_1b108 = 0x1b108, - BNXT_ULP_CLASS_HID_1f248 = 0x1f248, - BNXT_ULP_CLASS_HID_1f788 = 0x1f788, - BNXT_ULP_CLASS_HID_ba7c = 0xba7c, - BNXT_ULP_CLASS_HID_bfbc = 0xbfbc, - BNXT_ULP_CLASS_HID_e0fc = 0xe0fc, - BNXT_ULP_CLASS_HID_e23c = 0xe23c, - BNXT_ULP_CLASS_HID_b700 = 0xb700, - BNXT_ULP_CLASS_HID_b840 = 0xb840, - BNXT_ULP_CLASS_HID_fd80 = 0xfd80, - BNXT_ULP_CLASS_HID_fec0 = 0xfec0, - BNXT_ULP_CLASS_HID_1ad00 = 0x1ad00, - BNXT_ULP_CLASS_HID_1ae40 = 0x1ae40, - BNXT_ULP_CLASS_HID_1d380 = 0x1d380, - BNXT_ULP_CLASS_HID_1f4c0 = 0x1f4c0, - BNXT_ULP_CLASS_HID_1d07c = 0x1d07c, - BNXT_ULP_CLASS_HID_1f5bc = 0x1f5bc, - BNXT_ULP_CLASS_HID_1d6fc = 0x1d6fc, - BNXT_ULP_CLASS_HID_1f83c = 0x1f83c, - BNXT_ULP_CLASS_HID_86a0 = 0x86a0, - BNXT_ULP_CLASS_HID_abe0 = 0xabe0, - BNXT_ULP_CLASS_HID_cd20 = 0xcd20, - BNXT_ULP_CLASS_HID_ee60 = 0xee60, - BNXT_ULP_CLASS_HID_8374 = 0x8374, - BNXT_ULP_CLASS_HID_a4b4 = 0xa4b4, - BNXT_ULP_CLASS_HID_c9f4 = 0xc9f4, - BNXT_ULP_CLASS_HID_eb34 = 0xeb34, - BNXT_ULP_CLASS_HID_1b974 = 0x1b974, - BNXT_ULP_CLASS_HID_1bab4 = 0x1bab4, - BNXT_ULP_CLASS_HID_1fff4 = 0x1fff4, - BNXT_ULP_CLASS_HID_1e134 = 0x1e134, - BNXT_ULP_CLASS_HID_1bca0 = 0x1bca0, - BNXT_ULP_CLASS_HID_1a1e0 = 0x1a1e0, - BNXT_ULP_CLASS_HID_1e320 = 0x1e320, - BNXT_ULP_CLASS_HID_1e460 = 0x1e460, - BNXT_ULP_CLASS_HID_aad4 = 0xaad4, - BNXT_ULP_CLASS_HID_ac14 = 0xac14, - BNXT_ULP_CLASS_HID_d154 = 0xd154, - BNXT_ULP_CLASS_HID_f294 = 0xf294, - BNXT_ULP_CLASS_HID_a798 = 0xa798, - BNXT_ULP_CLASS_HID_a8d8 = 0xa8d8, - BNXT_ULP_CLASS_HID_ea18 = 0xea18, - BNXT_ULP_CLASS_HID_ef58 = 0xef58, - BNXT_ULP_CLASS_HID_1dd98 = 0x1dd98, - BNXT_ULP_CLASS_HID_1fed8 = 0x1fed8, - BNXT_ULP_CLASS_HID_1c018 = 0x1c018, - BNXT_ULP_CLASS_HID_1e558 = 0x1e558, - BNXT_ULP_CLASS_HID_1c0d4 = 0x1c0d4, - BNXT_ULP_CLASS_HID_1e214 = 0x1e214, - BNXT_ULP_CLASS_HID_1c754 = 0x1c754, - BNXT_ULP_CLASS_HID_1e894 = 0x1e894, - BNXT_ULP_CLASS_HID_900c = 0x900c, - BNXT_ULP_CLASS_HID_b54c = 0xb54c, - BNXT_ULP_CLASS_HID_d68c = 0xd68c, - BNXT_ULP_CLASS_HID_fbcc = 0xfbcc, - BNXT_ULP_CLASS_HID_c80c = 0xc80c, - BNXT_ULP_CLASS_HID_ed4c = 0xed4c, - BNXT_ULP_CLASS_HID_d350 = 0xd350, - BNXT_ULP_CLASS_HID_f490 = 0xf490, - BNXT_ULP_CLASS_HID_182d0 = 0x182d0, - BNXT_ULP_CLASS_HID_1a410 = 0x1a410, - BNXT_ULP_CLASS_HID_1c950 = 0x1c950, - BNXT_ULP_CLASS_HID_1ea90 = 0x1ea90, - BNXT_ULP_CLASS_HID_1860c = 0x1860c, - BNXT_ULP_CLASS_HID_1ab4c = 0x1ab4c, - BNXT_ULP_CLASS_HID_1cc8c = 0x1cc8c, - BNXT_ULP_CLASS_HID_1f1cc = 0x1f1cc, - BNXT_ULP_CLASS_HID_b4b0 = 0xb4b0, - BNXT_ULP_CLASS_HID_b9f0 = 0xb9f0, - BNXT_ULP_CLASS_HID_fb30 = 0xfb30, - BNXT_ULP_CLASS_HID_fc70 = 0xfc70, - BNXT_ULP_CLASS_HID_b144 = 0xb144, - BNXT_ULP_CLASS_HID_b284 = 0xb284, - BNXT_ULP_CLASS_HID_f7c4 = 0xf7c4, - BNXT_ULP_CLASS_HID_f904 = 0xf904, - BNXT_ULP_CLASS_HID_1a744 = 0x1a744, - BNXT_ULP_CLASS_HID_1a884 = 0x1a884, - BNXT_ULP_CLASS_HID_1edc4 = 0x1edc4, - BNXT_ULP_CLASS_HID_1ef04 = 0x1ef04, - BNXT_ULP_CLASS_HID_1aab0 = 0x1aab0, - BNXT_ULP_CLASS_HID_1aff0 = 0x1aff0, - BNXT_ULP_CLASS_HID_1d130 = 0x1d130, - BNXT_ULP_CLASS_HID_1f270 = 0x1f270, - BNXT_ULP_CLASS_HID_80e4 = 0x80e4, - BNXT_ULP_CLASS_HID_a224 = 0xa224, - BNXT_ULP_CLASS_HID_c764 = 0xc764, - BNXT_ULP_CLASS_HID_e8a4 = 0xe8a4, - BNXT_ULP_CLASS_HID_9da8 = 0x9da8, - BNXT_ULP_CLASS_HID_bee8 = 0xbee8, - BNXT_ULP_CLASS_HID_c028 = 0xc028, - BNXT_ULP_CLASS_HID_e568 = 0xe568, - BNXT_ULP_CLASS_HID_1b3a8 = 0x1b3a8, - BNXT_ULP_CLASS_HID_1b4e8 = 0x1b4e8, - BNXT_ULP_CLASS_HID_1f628 = 0x1f628, - BNXT_ULP_CLASS_HID_1fb68 = 0x1fb68, - BNXT_ULP_CLASS_HID_1b6e4 = 0x1b6e4, - BNXT_ULP_CLASS_HID_1b824 = 0x1b824, - BNXT_ULP_CLASS_HID_1fd64 = 0x1fd64, - BNXT_ULP_CLASS_HID_1fea4 = 0x1fea4, - BNXT_ULP_CLASS_HID_a508 = 0xa508, - BNXT_ULP_CLASS_HID_a648 = 0xa648, - BNXT_ULP_CLASS_HID_eb88 = 0xeb88, - BNXT_ULP_CLASS_HID_ecc8 = 0xecc8, - BNXT_ULP_CLASS_HID_a1dc = 0xa1dc, - BNXT_ULP_CLASS_HID_a31c = 0xa31c, - BNXT_ULP_CLASS_HID_e45c = 0xe45c, - BNXT_ULP_CLASS_HID_e99c = 0xe99c, - BNXT_ULP_CLASS_HID_1d7dc = 0x1d7dc, - BNXT_ULP_CLASS_HID_1f91c = 0x1f91c, - BNXT_ULP_CLASS_HID_1da5c = 0x1da5c, - BNXT_ULP_CLASS_HID_1ff9c = 0x1ff9c, - BNXT_ULP_CLASS_HID_1db08 = 0x1db08, - BNXT_ULP_CLASS_HID_1fc48 = 0x1fc48, - BNXT_ULP_CLASS_HID_1c188 = 0x1c188, - BNXT_ULP_CLASS_HID_1e2c8 = 0x1e2c8, - BNXT_ULP_CLASS_HID_9ad8 = 0x9ad8, - BNXT_ULP_CLASS_HID_bc18 = 0xbc18, - BNXT_ULP_CLASS_HID_c158 = 0xc158, - BNXT_ULP_CLASS_HID_e298 = 0xe298, - BNXT_ULP_CLASS_HID_97ec = 0x97ec, - BNXT_ULP_CLASS_HID_b92c = 0xb92c, - BNXT_ULP_CLASS_HID_da6c = 0xda6c, - BNXT_ULP_CLASS_HID_ffac = 0xffac, - BNXT_ULP_CLASS_HID_18dec = 0x18dec, - BNXT_ULP_CLASS_HID_1af2c = 0x1af2c, - BNXT_ULP_CLASS_HID_1f06c = 0x1f06c, - BNXT_ULP_CLASS_HID_1f5ac = 0x1f5ac, - BNXT_ULP_CLASS_HID_1b0d8 = 0x1b0d8, - BNXT_ULP_CLASS_HID_1b218 = 0x1b218, - BNXT_ULP_CLASS_HID_1f758 = 0x1f758, - BNXT_ULP_CLASS_HID_1f898 = 0x1f898, - BNXT_ULP_CLASS_HID_bf4c = 0xbf4c, - BNXT_ULP_CLASS_HID_a08c = 0xa08c, - BNXT_ULP_CLASS_HID_e5cc = 0xe5cc, - BNXT_ULP_CLASS_HID_e70c = 0xe70c, - BNXT_ULP_CLASS_HID_b810 = 0xb810, - BNXT_ULP_CLASS_HID_bd50 = 0xbd50, - BNXT_ULP_CLASS_HID_fe90 = 0xfe90, - BNXT_ULP_CLASS_HID_e3d0 = 0xe3d0, - BNXT_ULP_CLASS_HID_1ae10 = 0x1ae10, - BNXT_ULP_CLASS_HID_1f350 = 0x1f350, - BNXT_ULP_CLASS_HID_1d490 = 0x1d490, - BNXT_ULP_CLASS_HID_1f9d0 = 0x1f9d0, - BNXT_ULP_CLASS_HID_1d54c = 0x1d54c, - BNXT_ULP_CLASS_HID_1f68c = 0x1f68c, - BNXT_ULP_CLASS_HID_1dbcc = 0x1dbcc, - BNXT_ULP_CLASS_HID_1fd0c = 0x1fd0c, - BNXT_ULP_CLASS_HID_34b0 = 0x34b0, - BNXT_ULP_CLASS_HID_3a7c = 0x3a7c, - BNXT_ULP_CLASS_HID_3700 = 0x3700, - BNXT_ULP_CLASS_HID_5ee0 = 0x5ee0, - BNXT_ULP_CLASS_HID_5bb4 = 0x5bb4, - BNXT_ULP_CLASS_HID_07d8 = 0x07d8, - BNXT_ULP_CLASS_HID_00ec = 0x00ec, - BNXT_ULP_CLASS_HID_284c = 0x284c, - BNXT_ULP_CLASS_HID_2510 = 0x2510, - BNXT_ULP_CLASS_HID_3144 = 0x3144, - BNXT_ULP_CLASS_HID_5924 = 0x5924, - BNXT_ULP_CLASS_HID_55e8 = 0x55e8, - BNXT_ULP_CLASS_HID_1e1c = 0x1e1c, - BNXT_ULP_CLASS_HID_1b20 = 0x1b20, - BNXT_ULP_CLASS_HID_2280 = 0x2280, - BNXT_ULP_CLASS_HID_3f54 = 0x3f54, + BNXT_ULP_CLASS_HID_4f0b = 0x4f0b, + BNXT_ULP_CLASS_HID_336b = 0x336b, + BNXT_ULP_CLASS_HID_39a7 = 0x39a7, + BNXT_ULP_CLASS_HID_120b = 0x120b, + BNXT_ULP_CLASS_HID_1847 = 0x1847, + BNXT_ULP_CLASS_HID_5953 = 0x5953, + BNXT_ULP_CLASS_HID_02e3 = 0x02e3, + BNXT_ULP_CLASS_HID_35ff = 0x35ff, + BNXT_ULP_CLASS_HID_3c3b = 0x3c3b, + BNXT_ULP_CLASS_HID_201b = 0x201b, + BNXT_ULP_CLASS_HID_2657 = 0x2657, + BNXT_ULP_CLASS_HID_2543 = 0x2543, + BNXT_ULP_CLASS_HID_2b8f = 0x2b8f, + BNXT_ULP_CLASS_HID_0fef = 0x0fef, + BNXT_ULP_CLASS_HID_162b = 0x162b, + BNXT_ULP_CLASS_HID_48d7 = 0x48d7, + BNXT_ULP_CLASS_HID_4f13 = 0x4f13, + BNXT_ULP_CLASS_HID_3373 = 0x3373, + BNXT_ULP_CLASS_HID_39bf = 0x39bf, + BNXT_ULP_CLASS_HID_420b7 = 0x420b7, + BNXT_ULP_CLASS_HID_426f3 = 0x426f3, + BNXT_ULP_CLASS_HID_40ad3 = 0x40ad3, + BNXT_ULP_CLASS_HID_4111f = 0x4111f, + BNXT_ULP_CLASS_HID_4441b = 0x4441b, + BNXT_ULP_CLASS_HID_44a47 = 0x44a47, + BNXT_ULP_CLASS_HID_42ea7 = 0x42ea7, + BNXT_ULP_CLASS_HID_434e3 = 0x434e3, + BNXT_ULP_CLASS_HID_253b = 0x253b, + BNXT_ULP_CLASS_HID_2bf7 = 0x2bf7, + BNXT_ULP_CLASS_HID_0f97 = 0x0f97, + BNXT_ULP_CLASS_HID_1653 = 0x1653, + BNXT_ULP_CLASS_HID_48af = 0x48af, + BNXT_ULP_CLASS_HID_4f6b = 0x4f6b, + BNXT_ULP_CLASS_HID_330b = 0x330b, + BNXT_ULP_CLASS_HID_39c7 = 0x39c7, + BNXT_ULP_CLASS_HID_126b = 0x126b, + BNXT_ULP_CLASS_HID_1827 = 0x1827, + BNXT_ULP_CLASS_HID_5933 = 0x5933, + BNXT_ULP_CLASS_HID_0283 = 0x0283, + BNXT_ULP_CLASS_HID_359f = 0x359f, + BNXT_ULP_CLASS_HID_3c5b = 0x3c5b, + BNXT_ULP_CLASS_HID_207b = 0x207b, + BNXT_ULP_CLASS_HID_2637 = 0x2637, + BNXT_ULP_CLASS_HID_2523 = 0x2523, + BNXT_ULP_CLASS_HID_2bef = 0x2bef, + BNXT_ULP_CLASS_HID_0f8f = 0x0f8f, + BNXT_ULP_CLASS_HID_164b = 0x164b, + BNXT_ULP_CLASS_HID_48b7 = 0x48b7, + BNXT_ULP_CLASS_HID_4f73 = 0x4f73, + BNXT_ULP_CLASS_HID_3313 = 0x3313, + BNXT_ULP_CLASS_HID_39df = 0x39df, + BNXT_ULP_CLASS_HID_420d7 = 0x420d7, + BNXT_ULP_CLASS_HID_42693 = 0x42693, + BNXT_ULP_CLASS_HID_40ab3 = 0x40ab3, + BNXT_ULP_CLASS_HID_4117f = 0x4117f, + BNXT_ULP_CLASS_HID_4447b = 0x4447b, + BNXT_ULP_CLASS_HID_44a27 = 0x44a27, + BNXT_ULP_CLASS_HID_42ec7 = 0x42ec7, + BNXT_ULP_CLASS_HID_43483 = 0x43483, + BNXT_ULP_CLASS_HID_4156d = 0x4156d, + BNXT_ULP_CLASS_HID_41b29 = 0x41b29, + BNXT_ULP_CLASS_HID_52b6d = 0x52b6d, + BNXT_ULP_CLASS_HID_53129 = 0x53129, + BNXT_ULP_CLASS_HID_478a = 0x478a, + BNXT_ULP_CLASS_HID_03a6 = 0x03a6, + BNXT_ULP_CLASS_HID_4dce = 0x4dce, + BNXT_ULP_CLASS_HID_09ea = 0x09ea, + BNXT_ULP_CLASS_HID_08fe = 0x08fe, + BNXT_ULP_CLASS_HID_23ce = 0x23ce, + BNXT_ULP_CLASS_HID_0e02 = 0x0e02, + BNXT_ULP_CLASS_HID_2912 = 0x2912, + BNXT_ULP_CLASS_HID_3e2a = 0x3e2a, + BNXT_ULP_CLASS_HID_593a = 0x593a, + BNXT_ULP_CLASS_HID_246e = 0x246e, + BNXT_ULP_CLASS_HID_5f7e = 0x5f7e, + BNXT_ULP_CLASS_HID_5e52 = 0x5e52, + BNXT_ULP_CLASS_HID_1a6e = 0x1a6e, + BNXT_ULP_CLASS_HID_4796 = 0x4796, + BNXT_ULP_CLASS_HID_03b2 = 0x03b2, + BNXT_ULP_CLASS_HID_4163a = 0x4163a, + BNXT_ULP_CLASS_HID_4310a = 0x4310a, + BNXT_ULP_CLASS_HID_41c7e = 0x41c7e, + BNXT_ULP_CLASS_HID_4374e = 0x4374e, + BNXT_ULP_CLASS_HID_42f8e = 0x42f8e, + BNXT_ULP_CLASS_HID_4469e = 0x4469e, + BNXT_ULP_CLASS_HID_455c2 = 0x455c2, + BNXT_ULP_CLASS_HID_411ee = 0x411ee, + BNXT_ULP_CLASS_HID_44b76 = 0x44b76, + BNXT_ULP_CLASS_HID_40692 = 0x40692, + BNXT_ULP_CLASS_HID_415c6 = 0x415c6, + BNXT_ULP_CLASS_HID_40cd6 = 0x40cd6, + BNXT_ULP_CLASS_HID_42516 = 0x42516, + BNXT_ULP_CLASS_HID_45ce6 = 0x45ce6, + BNXT_ULP_CLASS_HID_42b2a = 0x42b2a, + BNXT_ULP_CLASS_HID_4423a = 0x4423a, + BNXT_ULP_CLASS_HID_229d8 = 0x229d8, + BNXT_ULP_CLASS_HID_240c8 = 0x240c8, + BNXT_ULP_CLASS_HID_22f14 = 0x22f14, BNXT_ULP_CLASS_HID_24604 = 0x24604, - BNXT_ULP_CLASS_HID_255d4 = 0x255d4, - BNXT_ULP_CLASS_HID_22e08 = 0x22e08, - BNXT_ULP_CLASS_HID_24378 = 0x24378, - BNXT_ULP_CLASS_HID_20fcc = 0x20fcc, - BNXT_ULP_CLASS_HID_21a9c = 0x21a9c, - BNXT_ULP_CLASS_HID_217d0 = 0x217d0, - BNXT_ULP_CLASS_HID_20800 = 0x20800, + BNXT_ULP_CLASS_HID_23374 = 0x23374, + BNXT_ULP_CLASS_HID_22a64 = 0x22a64, + BNXT_ULP_CLASS_HID_238b0 = 0x238b0, BNXT_ULP_CLASS_HID_253a0 = 0x253a0, - BNXT_ULP_CLASS_HID_23f70 = 0x23f70, - BNXT_ULP_CLASS_HID_23ba4 = 0x23ba4, - BNXT_ULP_CLASS_HID_22c94 = 0x22c94, - BNXT_ULP_CLASS_HID_21968 = 0x21968, - BNXT_ULP_CLASS_HID_243c4 = 0x243c4, - BNXT_ULP_CLASS_HID_25c38 = 0x25c38, - BNXT_ULP_CLASS_HID_2125c = 0x2125c, - BNXT_ULP_CLASS_HID_240c8 = 0x240c8, - BNXT_ULP_CLASS_HID_22f98 = 0x22f98, - BNXT_ULP_CLASS_HID_228cc = 0x228cc, - BNXT_ULP_CLASS_HID_25d3c = 0x25d3c, + BNXT_ULP_CLASS_HID_24dac = 0x24dac, BNXT_ULP_CLASS_HID_20990 = 0x20990, - BNXT_ULP_CLASS_HID_214a0 = 0x214a0, - BNXT_ULP_CLASS_HID_21194 = 0x21194, - BNXT_ULP_CLASS_HID_202c4 = 0x202c4, - BNXT_ULP_CLASS_HID_22a64 = 0x22a64, - BNXT_ULP_CLASS_HID_23934 = 0x23934, - BNXT_ULP_CLASS_HID_23268 = 0x23268, - BNXT_ULP_CLASS_HID_22758 = 0x22758, - BNXT_ULP_CLASS_HID_2132c = 0x2132c, - BNXT_ULP_CLASS_HID_25d88 = 0x25d88, - BNXT_ULP_CLASS_HID_256fc = 0x256fc, - BNXT_ULP_CLASS_HID_24b2c = 0x24b2c, - BNXT_ULP_CLASS_HID_22f14 = 0x22f14, - BNXT_ULP_CLASS_HID_23a24 = 0x23a24, - BNXT_ULP_CLASS_HID_23718 = 0x23718, - BNXT_ULP_CLASS_HID_22848 = 0x22848, BNXT_ULP_CLASS_HID_214dc = 0x214dc, - BNXT_ULP_CLASS_HID_25eb8 = 0x25eb8, - BNXT_ULP_CLASS_HID_25bec = 0x25bec, - BNXT_ULP_CLASS_HID_21110 = 0x21110, - BNXT_ULP_CLASS_HID_238b0 = 0x238b0, - BNXT_ULP_CLASS_HID_20440 = 0x20440, - BNXT_ULP_CLASS_HID_200b4 = 0x200b4, - BNXT_ULP_CLASS_HID_235e4 = 0x235e4, + BNXT_ULP_CLASS_HID_20fcc = 0x20fcc, + BNXT_ULP_CLASS_HID_257c8 = 0x257c8, + BNXT_ULP_CLASS_HID_2132c = 0x2132c, BNXT_ULP_CLASS_HID_25d04 = 0x25d04, - BNXT_ULP_CLASS_HID_228d4 = 0x228d4, - BNXT_ULP_CLASS_HID_22508 = 0x22508, - BNXT_ULP_CLASS_HID_25678 = 0x25678, - BNXT_ULP_CLASS_HID_229d8 = 0x229d8, + BNXT_ULP_CLASS_HID_21968 = 0x21968, BNXT_ULP_CLASS_HID_234e8 = 0x234e8, - BNXT_ULP_CLASS_HID_231dc = 0x231dc, - BNXT_ULP_CLASS_HID_2220c = 0x2220c, - BNXT_ULP_CLASS_HID_24dac = 0x24dac, - BNXT_ULP_CLASS_HID_2597c = 0x2597c, - BNXT_ULP_CLASS_HID_255b0 = 0x255b0, - BNXT_ULP_CLASS_HID_246e0 = 0x246e0, - BNXT_ULP_CLASS_HID_23374 = 0x23374, + BNXT_ULP_CLASS_HID_22f98 = 0x22f98, + BNXT_ULP_CLASS_HID_23a24 = 0x23a24, + BNXT_ULP_CLASS_HID_255d4 = 0x255d4, BNXT_ULP_CLASS_HID_21e04 = 0x21e04, - BNXT_ULP_CLASS_HID_21b78 = 0x21b78, - BNXT_ULP_CLASS_HID_20fa8 = 0x20fa8, - BNXT_ULP_CLASS_HID_257c8 = 0x257c8, + BNXT_ULP_CLASS_HID_23934 = 0x23934, + BNXT_ULP_CLASS_HID_20440 = 0x20440, + BNXT_ULP_CLASS_HID_23f70 = 0x23f70, + BNXT_ULP_CLASS_HID_2597c = 0x2597c, + BNXT_ULP_CLASS_HID_214a0 = 0x214a0, + BNXT_ULP_CLASS_HID_25eb8 = 0x25eb8, + BNXT_ULP_CLASS_HID_21a9c = 0x21a9c, BNXT_ULP_CLASS_HID_22298 = 0x22298, - BNXT_ULP_CLASS_HID_23fcc = 0x23fcc, - BNXT_ULP_CLASS_HID_2503c = 0x2503c, - BNXT_ULP_CLASS_HID_2239c = 0x2239c, - BNXT_ULP_CLASS_HID_20eac = 0x20eac, - BNXT_ULP_CLASS_HID_20be0 = 0x20be0, - BNXT_ULP_CLASS_HID_23cd0 = 0x23cd0, - BNXT_ULP_CLASS_HID_24470 = 0x24470, - BNXT_ULP_CLASS_HID_25300 = 0x25300, - BNXT_ULP_CLASS_HID_22c74 = 0x22c74, - BNXT_ULP_CLASS_HID_240a4 = 0x240a4, - BNXT_ULP_CLASS_HID_23da0 = 0x23da0, - BNXT_ULP_CLASS_HID_20970 = 0x20970, - BNXT_ULP_CLASS_HID_205a4 = 0x205a4, - BNXT_ULP_CLASS_HID_23694 = 0x23694, - BNXT_ULP_CLASS_HID_25e34 = 0x25e34, - BNXT_ULP_CLASS_HID_22dc4 = 0x22dc4, - BNXT_ULP_CLASS_HID_22638 = 0x22638, - BNXT_ULP_CLASS_HID_25b68 = 0x25b68, - BNXT_ULP_CLASS_HID_34c8 = 0x34c8, - BNXT_ULP_CLASS_HID_3a04 = 0x3a04, - BNXT_ULP_CLASS_HID_09d4 = 0x09d4, - BNXT_ULP_CLASS_HID_5e98 = 0x5e98, - BNXT_ULP_CLASS_HID_2da8 = 0x2da8, - BNXT_ULP_CLASS_HID_07a0 = 0x07a0, - BNXT_ULP_CLASS_HID_1370 = 0x1370, - BNXT_ULP_CLASS_HID_2834 = 0x2834, - BNXT_ULP_CLASS_HID_37c4 = 0x37c4, - BNXT_ULP_CLASS_HID_0398 = 0x0398, - BNXT_ULP_CLASS_HID_595c = 0x595c, - BNXT_ULP_CLASS_HID_246c = 0x246c, - BNXT_ULP_CLASS_HID_1e64 = 0x1e64, - BNXT_ULP_CLASS_HID_48c0 = 0x48c0, - BNXT_ULP_CLASS_HID_22f8 = 0x22f8, - BNXT_ULP_CLASS_HID_3188 = 0x3188, - BNXT_ULP_CLASS_HID_24664 = 0x24664, - BNXT_ULP_CLASS_HID_29418 = 0x29418, - BNXT_ULP_CLASS_HID_30118 = 0x30118, - BNXT_ULP_CLASS_HID_38a18 = 0x38a18, - BNXT_ULP_CLASS_HID_255b4 = 0x255b4, - BNXT_ULP_CLASS_HID_2deb4 = 0x2deb4, - BNXT_ULP_CLASS_HID_34bb4 = 0x34bb4, - BNXT_ULP_CLASS_HID_39968 = 0x39968, - BNXT_ULP_CLASS_HID_22e68 = 0x22e68, - BNXT_ULP_CLASS_HID_2db68 = 0x2db68, - BNXT_ULP_CLASS_HID_34468 = 0x34468, - BNXT_ULP_CLASS_HID_3921c = 0x3921c, - BNXT_ULP_CLASS_HID_24318 = 0x24318, - BNXT_ULP_CLASS_HID_290cc = 0x290cc, - BNXT_ULP_CLASS_HID_31dcc = 0x31dcc, - BNXT_ULP_CLASS_HID_386cc = 0x386cc, - BNXT_ULP_CLASS_HID_20fac = 0x20fac, - BNXT_ULP_CLASS_HID_2b8ac = 0x2b8ac, - BNXT_ULP_CLASS_HID_325ac = 0x325ac, - BNXT_ULP_CLASS_HID_3aeac = 0x3aeac, - BNXT_ULP_CLASS_HID_21afc = 0x21afc, - BNXT_ULP_CLASS_HID_287fc = 0x287fc, - BNXT_ULP_CLASS_HID_330fc = 0x330fc, - BNXT_ULP_CLASS_HID_3bdfc = 0x3bdfc, - BNXT_ULP_CLASS_HID_217b0 = 0x217b0, - BNXT_ULP_CLASS_HID_280b0 = 0x280b0, - BNXT_ULP_CLASS_HID_30db0 = 0x30db0, - BNXT_ULP_CLASS_HID_3b6b0 = 0x3b6b0, - BNXT_ULP_CLASS_HID_20860 = 0x20860, - BNXT_ULP_CLASS_HID_2b560 = 0x2b560, - BNXT_ULP_CLASS_HID_33e60 = 0x33e60, - BNXT_ULP_CLASS_HID_3ab60 = 0x3ab60, - BNXT_ULP_CLASS_HID_253c0 = 0x253c0, - BNXT_ULP_CLASS_HID_2dcc0 = 0x2dcc0, - BNXT_ULP_CLASS_HID_349c0 = 0x349c0, - BNXT_ULP_CLASS_HID_397f4 = 0x397f4, - BNXT_ULP_CLASS_HID_23f10 = 0x23f10, - BNXT_ULP_CLASS_HID_2a810 = 0x2a810, - BNXT_ULP_CLASS_HID_35510 = 0x35510, - BNXT_ULP_CLASS_HID_3de10 = 0x3de10, - BNXT_ULP_CLASS_HID_23bc4 = 0x23bc4, - BNXT_ULP_CLASS_HID_2a4c4 = 0x2a4c4, - BNXT_ULP_CLASS_HID_351c4 = 0x351c4, - BNXT_ULP_CLASS_HID_3dac4 = 0x3dac4, - BNXT_ULP_CLASS_HID_22cf4 = 0x22cf4, - BNXT_ULP_CLASS_HID_2d9f4 = 0x2d9f4, - BNXT_ULP_CLASS_HID_342f4 = 0x342f4, - BNXT_ULP_CLASS_HID_390a8 = 0x390a8, - BNXT_ULP_CLASS_HID_21908 = 0x21908, - BNXT_ULP_CLASS_HID_28208 = 0x28208, - BNXT_ULP_CLASS_HID_30f08 = 0x30f08, - BNXT_ULP_CLASS_HID_3b808 = 0x3b808, - BNXT_ULP_CLASS_HID_243a4 = 0x243a4, - BNXT_ULP_CLASS_HID_29158 = 0x29158, - BNXT_ULP_CLASS_HID_31a58 = 0x31a58, - BNXT_ULP_CLASS_HID_38758 = 0x38758, - BNXT_ULP_CLASS_HID_25c58 = 0x25c58, - BNXT_ULP_CLASS_HID_2c958 = 0x2c958, - BNXT_ULP_CLASS_HID_3170c = 0x3170c, - BNXT_ULP_CLASS_HID_3800c = 0x3800c, - BNXT_ULP_CLASS_HID_2123c = 0x2123c, - BNXT_ULP_CLASS_HID_29f3c = 0x29f3c, - BNXT_ULP_CLASS_HID_3083c = 0x3083c, - BNXT_ULP_CLASS_HID_3b53c = 0x3b53c, + BNXT_ULP_CLASS_HID_25d88 = 0x25d88, + BNXT_ULP_CLASS_HID_228d4 = 0x228d4, + BNXT_ULP_CLASS_HID_243c4 = 0x243c4, + BNXT_ULP_CLASS_HID_6220c = 0x6220c, + BNXT_ULP_CLASS_HID_65d3c = 0x65d3c, + BNXT_ULP_CLASS_HID_62848 = 0x62848, + BNXT_ULP_CLASS_HID_64378 = 0x64378, + BNXT_ULP_CLASS_HID_60fa8 = 0x60fa8, + BNXT_ULP_CLASS_HID_62758 = 0x62758, + BNXT_ULP_CLASS_HID_635e4 = 0x635e4, + BNXT_ULP_CLASS_HID_62c94 = 0x62c94, + BNXT_ULP_CLASS_HID_646e0 = 0x646e0, + BNXT_ULP_CLASS_HID_602c4 = 0x602c4, + BNXT_ULP_CLASS_HID_61110 = 0x61110, + BNXT_ULP_CLASS_HID_60800 = 0x60800, + BNXT_ULP_CLASS_HID_6503c = 0x6503c, + BNXT_ULP_CLASS_HID_64b2c = 0x64b2c, + BNXT_ULP_CLASS_HID_65678 = 0x65678, + BNXT_ULP_CLASS_HID_6125c = 0x6125c, + BNXT_ULP_CLASS_HID_631dc = 0x631dc, + BNXT_ULP_CLASS_HID_628cc = 0x628cc, + BNXT_ULP_CLASS_HID_63718 = 0x63718, + BNXT_ULP_CLASS_HID_62e08 = 0x62e08, + BNXT_ULP_CLASS_HID_61b78 = 0x61b78, + BNXT_ULP_CLASS_HID_63268 = 0x63268, + BNXT_ULP_CLASS_HID_600b4 = 0x600b4, + BNXT_ULP_CLASS_HID_63ba4 = 0x63ba4, + BNXT_ULP_CLASS_HID_655b0 = 0x655b0, + BNXT_ULP_CLASS_HID_61194 = 0x61194, + BNXT_ULP_CLASS_HID_65bec = 0x65bec, + BNXT_ULP_CLASS_HID_617d0 = 0x617d0, + BNXT_ULP_CLASS_HID_63fcc = 0x63fcc, + BNXT_ULP_CLASS_HID_656fc = 0x656fc, + BNXT_ULP_CLASS_HID_62508 = 0x62508, + BNXT_ULP_CLASS_HID_65c38 = 0x65c38, + BNXT_ULP_CLASS_HID_86e0 = 0x86e0, + BNXT_ULP_CLASS_HID_a1f0 = 0xa1f0, + BNXT_ULP_CLASS_HID_8c2c = 0x8c2c, + BNXT_ULP_CLASS_HID_a73c = 0xa73c, + BNXT_ULP_CLASS_HID_904c = 0x904c, + BNXT_ULP_CLASS_HID_8b5c = 0x8b5c, + BNXT_ULP_CLASS_HID_9988 = 0x9988, + BNXT_ULP_CLASS_HID_b098 = 0xb098, + BNXT_ULP_CLASS_HID_aa94 = 0xaa94, + BNXT_ULP_CLASS_HID_c264 = 0xc264, + BNXT_ULP_CLASS_HID_d0d0 = 0xd0d0, + BNXT_ULP_CLASS_HID_cba0 = 0xcba0, + BNXT_ULP_CLASS_HID_b4f0 = 0xb4f0, + BNXT_ULP_CLASS_HID_afc0 = 0xafc0, + BNXT_ULP_CLASS_HID_ba3c = 0xba3c, + BNXT_ULP_CLASS_HID_d50c = 0xd50c, + BNXT_ULP_CLASS_HID_48334 = 0x48334, + BNXT_ULP_CLASS_HID_4ba04 = 0x4ba04, + BNXT_ULP_CLASS_HID_48970 = 0x48970, + BNXT_ULP_CLASS_HID_4a040 = 0x4a040, + BNXT_ULP_CLASS_HID_4c84c = 0x4c84c, + BNXT_ULP_CLASS_HID_48460 = 0x48460, + BNXT_ULP_CLASS_HID_492dc = 0x492dc, + BNXT_ULP_CLASS_HID_48dac = 0x48dac, + BNXT_ULP_CLASS_HID_4a7d8 = 0x4a7d8, + BNXT_ULP_CLASS_HID_4dea8 = 0x4dea8, + BNXT_ULP_CLASS_HID_4ade4 = 0x4ade4, + BNXT_ULP_CLASS_HID_4c4f4 = 0x4c4f4, + BNXT_ULP_CLASS_HID_4b104 = 0x4b104, + BNXT_ULP_CLASS_HID_4a814 = 0x4a814, + BNXT_ULP_CLASS_HID_4b740 = 0x4b740, + BNXT_ULP_CLASS_HID_4ae50 = 0x4ae50, + BNXT_ULP_CLASS_HID_1bce0 = 0x1bce0, + BNXT_ULP_CLASS_HID_1d7f0 = 0x1d7f0, + BNXT_ULP_CLASS_HID_1a22c = 0x1a22c, + BNXT_ULP_CLASS_HID_1dd3c = 0x1dd3c, + BNXT_ULP_CLASS_HID_1864c = 0x1864c, + BNXT_ULP_CLASS_HID_1a15c = 0x1a15c, + BNXT_ULP_CLASS_HID_18f88 = 0x18f88, + BNXT_ULP_CLASS_HID_1a698 = 0x1a698, + BNXT_ULP_CLASS_HID_1c094 = 0x1c094, + BNXT_ULP_CLASS_HID_19ca8 = 0x19ca8, + BNXT_ULP_CLASS_HID_1c6d0 = 0x1c6d0, + BNXT_ULP_CLASS_HID_182f4 = 0x182f4, + BNXT_ULP_CLASS_HID_1aaf0 = 0x1aaf0, + BNXT_ULP_CLASS_HID_1c5c0 = 0x1c5c0, + BNXT_ULP_CLASS_HID_1d03c = 0x1d03c, + BNXT_ULP_CLASS_HID_1cb0c = 0x1cb0c, + BNXT_ULP_CLASS_HID_5b934 = 0x5b934, + BNXT_ULP_CLASS_HID_5d004 = 0x5d004, + BNXT_ULP_CLASS_HID_5bf70 = 0x5bf70, + BNXT_ULP_CLASS_HID_5d640 = 0x5d640, + BNXT_ULP_CLASS_HID_58290 = 0x58290, + BNXT_ULP_CLASS_HID_5ba60 = 0x5ba60, + BNXT_ULP_CLASS_HID_588dc = 0x588dc, + BNXT_ULP_CLASS_HID_5a3ac = 0x5a3ac, + BNXT_ULP_CLASS_HID_5ddd8 = 0x5ddd8, + BNXT_ULP_CLASS_HID_599fc = 0x599fc, + BNXT_ULP_CLASS_HID_5c3e4 = 0x5c3e4, + BNXT_ULP_CLASS_HID_59f38 = 0x59f38, + BNXT_ULP_CLASS_HID_5a704 = 0x5a704, + BNXT_ULP_CLASS_HID_5de14 = 0x5de14, + BNXT_ULP_CLASS_HID_5ad40 = 0x5ad40, + BNXT_ULP_CLASS_HID_5c450 = 0x5c450, + BNXT_ULP_CLASS_HID_47aa = 0x47aa, + BNXT_ULP_CLASS_HID_0386 = 0x0386, + BNXT_ULP_CLASS_HID_4dee = 0x4dee, + BNXT_ULP_CLASS_HID_09ca = 0x09ca, + BNXT_ULP_CLASS_HID_08de = 0x08de, + BNXT_ULP_CLASS_HID_23ee = 0x23ee, + BNXT_ULP_CLASS_HID_0e22 = 0x0e22, + BNXT_ULP_CLASS_HID_2932 = 0x2932, + BNXT_ULP_CLASS_HID_3e0a = 0x3e0a, + BNXT_ULP_CLASS_HID_591a = 0x591a, + BNXT_ULP_CLASS_HID_244e = 0x244e, + BNXT_ULP_CLASS_HID_5f5e = 0x5f5e, + BNXT_ULP_CLASS_HID_5e72 = 0x5e72, + BNXT_ULP_CLASS_HID_1a4e = 0x1a4e, + BNXT_ULP_CLASS_HID_47b6 = 0x47b6, + BNXT_ULP_CLASS_HID_0392 = 0x0392, + BNXT_ULP_CLASS_HID_5dc2 = 0x5dc2, + BNXT_ULP_CLASS_HID_191e = 0x191e, + BNXT_ULP_CLASS_HID_4306 = 0x4306, + BNXT_ULP_CLASS_HID_1f62 = 0x1f62, + BNXT_ULP_CLASS_HID_1e76 = 0x1e76, + BNXT_ULP_CLASS_HID_3906 = 0x3906, + BNXT_ULP_CLASS_HID_07ba = 0x07ba, + BNXT_ULP_CLASS_HID_3f4a = 0x3f4a, + BNXT_ULP_CLASS_HID_37a2 = 0x37a2, + BNXT_ULP_CLASS_HID_2eb2 = 0x2eb2, + BNXT_ULP_CLASS_HID_3de6 = 0x3de6, + BNXT_ULP_CLASS_HID_54f6 = 0x54f6, + BNXT_ULP_CLASS_HID_578a = 0x578a, + BNXT_ULP_CLASS_HID_13e6 = 0x13e6, + BNXT_ULP_CLASS_HID_5dce = 0x5dce, + BNXT_ULP_CLASS_HID_192a = 0x192a, + BNXT_ULP_CLASS_HID_440f6 = 0x440f6, + BNXT_ULP_CLASS_HID_41cd2 = 0x41cd2, + BNXT_ULP_CLASS_HID_4463a = 0x4463a, + BNXT_ULP_CLASS_HID_40216 = 0x40216, + BNXT_ULP_CLASS_HID_4052a = 0x4052a, + BNXT_ULP_CLASS_HID_43c3a = 0x43c3a, + BNXT_ULP_CLASS_HID_40b6e = 0x40b6e, + BNXT_ULP_CLASS_HID_4227e = 0x4227e, + BNXT_ULP_CLASS_HID_43b56 = 0x43b56, + BNXT_ULP_CLASS_HID_45266 = 0x45266, + BNXT_ULP_CLASS_HID_4209a = 0x4209a, + BNXT_ULP_CLASS_HID_45baa = 0x45baa, + BNXT_ULP_CLASS_HID_45abe = 0x45abe, + BNXT_ULP_CLASS_HID_4169a = 0x4169a, + BNXT_ULP_CLASS_HID_44082 = 0x44082, + BNXT_ULP_CLASS_HID_41cde = 0x41cde, + BNXT_ULP_CLASS_HID_4560e = 0x4560e, + BNXT_ULP_CLASS_HID_4126a = 0x4126a, + BNXT_ULP_CLASS_HID_45c52 = 0x45c52, + BNXT_ULP_CLASS_HID_41bae = 0x41bae, + BNXT_ULP_CLASS_HID_41b42 = 0x41b42, + BNXT_ULP_CLASS_HID_43252 = 0x43252, + BNXT_ULP_CLASS_HID_40086 = 0x40086, + BNXT_ULP_CLASS_HID_43b96 = 0x43b96, + BNXT_ULP_CLASS_HID_430ee = 0x430ee, + BNXT_ULP_CLASS_HID_42bfe = 0x42bfe, + BNXT_ULP_CLASS_HID_43632 = 0x43632, + BNXT_ULP_CLASS_HID_451c2 = 0x451c2, + BNXT_ULP_CLASS_HID_450d6 = 0x450d6, + BNXT_ULP_CLASS_HID_44be6 = 0x44be6, + BNXT_ULP_CLASS_HID_4561a = 0x4561a, + BNXT_ULP_CLASS_HID_41276 = 0x41276, + BNXT_ULP_CLASS_HID_4161a = 0x4161a, + BNXT_ULP_CLASS_HID_4312a = 0x4312a, + BNXT_ULP_CLASS_HID_41c5e = 0x41c5e, + BNXT_ULP_CLASS_HID_4376e = 0x4376e, + BNXT_ULP_CLASS_HID_42fae = 0x42fae, + BNXT_ULP_CLASS_HID_446be = 0x446be, + BNXT_ULP_CLASS_HID_455e2 = 0x455e2, + BNXT_ULP_CLASS_HID_411ce = 0x411ce, + BNXT_ULP_CLASS_HID_44b56 = 0x44b56, + BNXT_ULP_CLASS_HID_406b2 = 0x406b2, + BNXT_ULP_CLASS_HID_415e6 = 0x415e6, + BNXT_ULP_CLASS_HID_40cf6 = 0x40cf6, + BNXT_ULP_CLASS_HID_42536 = 0x42536, + BNXT_ULP_CLASS_HID_45cc6 = 0x45cc6, + BNXT_ULP_CLASS_HID_42b0a = 0x42b0a, + BNXT_ULP_CLASS_HID_4421a = 0x4421a, + BNXT_ULP_CLASS_HID_6221a = 0x6221a, + BNXT_ULP_CLASS_HID_65d2a = 0x65d2a, + BNXT_ULP_CLASS_HID_6285e = 0x6285e, + BNXT_ULP_CLASS_HID_6436e = 0x6436e, + BNXT_ULP_CLASS_HID_61cfa = 0x61cfa, + BNXT_ULP_CLASS_HID_6378a = 0x6378a, + BNXT_ULP_CLASS_HID_6023e = 0x6023e, + BNXT_ULP_CLASS_HID_63dce = 0x63dce, + BNXT_ULP_CLASS_HID_63ba2 = 0x63ba2, + BNXT_ULP_CLASS_HID_652b2 = 0x652b2, + BNXT_ULP_CLASS_HID_621e6 = 0x621e6, + BNXT_ULP_CLASS_HID_658f6 = 0x658f6, + BNXT_ULP_CLASS_HID_61202 = 0x61202, + BNXT_ULP_CLASS_HID_60d12 = 0x60d12, + BNXT_ULP_CLASS_HID_61846 = 0x61846, + BNXT_ULP_CLASS_HID_63356 = 0x63356, + BNXT_ULP_CLASS_HID_50c1a = 0x50c1a, + BNXT_ULP_CLASS_HID_5272a = 0x5272a, + BNXT_ULP_CLASS_HID_5325e = 0x5325e, + BNXT_ULP_CLASS_HID_52d6e = 0x52d6e, + BNXT_ULP_CLASS_HID_545ae = 0x545ae, + BNXT_ULP_CLASS_HID_5018a = 0x5018a, + BNXT_ULP_CLASS_HID_54be2 = 0x54be2, + BNXT_ULP_CLASS_HID_507ce = 0x507ce, + BNXT_ULP_CLASS_HID_505a2 = 0x505a2, + BNXT_ULP_CLASS_HID_53cb2 = 0x53cb2, + BNXT_ULP_CLASS_HID_50be6 = 0x50be6, + BNXT_ULP_CLASS_HID_522f6 = 0x522f6, + BNXT_ULP_CLASS_HID_55b36 = 0x55b36, + BNXT_ULP_CLASS_HID_51712 = 0x51712, + BNXT_ULP_CLASS_HID_5410a = 0x5410a, + BNXT_ULP_CLASS_HID_51d56 = 0x51d56, + BNXT_ULP_CLASS_HID_7581a = 0x7581a, + BNXT_ULP_CLASS_HID_71466 = 0x71466, + BNXT_ULP_CLASS_HID_75e5e = 0x75e5e, + BNXT_ULP_CLASS_HID_71dba = 0x71dba, + BNXT_ULP_CLASS_HID_732fa = 0x732fa, + BNXT_ULP_CLASS_HID_72d8a = 0x72d8a, + BNXT_ULP_CLASS_HID_7383e = 0x7383e, + BNXT_ULP_CLASS_HID_753ce = 0x753ce, + BNXT_ULP_CLASS_HID_751a2 = 0x751a2, + BNXT_ULP_CLASS_HID_748b2 = 0x748b2, + BNXT_ULP_CLASS_HID_757e6 = 0x757e6, + BNXT_ULP_CLASS_HID_713c2 = 0x713c2, + BNXT_ULP_CLASS_HID_70802 = 0x70802, + BNXT_ULP_CLASS_HID_72312 = 0x72312, + BNXT_ULP_CLASS_HID_70e46 = 0x70e46, + BNXT_ULP_CLASS_HID_72956 = 0x72956, + BNXT_ULP_CLASS_HID_47ca = 0x47ca, + BNXT_ULP_CLASS_HID_03e6 = 0x03e6, + BNXT_ULP_CLASS_HID_4d8e = 0x4d8e, + BNXT_ULP_CLASS_HID_09aa = 0x09aa, + BNXT_ULP_CLASS_HID_08be = 0x08be, + BNXT_ULP_CLASS_HID_238e = 0x238e, + BNXT_ULP_CLASS_HID_0e42 = 0x0e42, + BNXT_ULP_CLASS_HID_2952 = 0x2952, + BNXT_ULP_CLASS_HID_3e6a = 0x3e6a, + BNXT_ULP_CLASS_HID_597a = 0x597a, + BNXT_ULP_CLASS_HID_242e = 0x242e, + BNXT_ULP_CLASS_HID_5f3e = 0x5f3e, + BNXT_ULP_CLASS_HID_5e12 = 0x5e12, + BNXT_ULP_CLASS_HID_1a2e = 0x1a2e, + BNXT_ULP_CLASS_HID_47d6 = 0x47d6, + BNXT_ULP_CLASS_HID_03f2 = 0x03f2, + BNXT_ULP_CLASS_HID_5da2 = 0x5da2, + BNXT_ULP_CLASS_HID_197e = 0x197e, + BNXT_ULP_CLASS_HID_4366 = 0x4366, + BNXT_ULP_CLASS_HID_1f02 = 0x1f02, + BNXT_ULP_CLASS_HID_1e16 = 0x1e16, + BNXT_ULP_CLASS_HID_3966 = 0x3966, + BNXT_ULP_CLASS_HID_07da = 0x07da, + BNXT_ULP_CLASS_HID_3f2a = 0x3f2a, + BNXT_ULP_CLASS_HID_37c2 = 0x37c2, + BNXT_ULP_CLASS_HID_2ed2 = 0x2ed2, + BNXT_ULP_CLASS_HID_3d86 = 0x3d86, + BNXT_ULP_CLASS_HID_5496 = 0x5496, + BNXT_ULP_CLASS_HID_57ea = 0x57ea, + BNXT_ULP_CLASS_HID_1386 = 0x1386, + BNXT_ULP_CLASS_HID_5dae = 0x5dae, + BNXT_ULP_CLASS_HID_194a = 0x194a, + BNXT_ULP_CLASS_HID_44096 = 0x44096, + BNXT_ULP_CLASS_HID_41cb2 = 0x41cb2, + BNXT_ULP_CLASS_HID_4465a = 0x4465a, + BNXT_ULP_CLASS_HID_40276 = 0x40276, + BNXT_ULP_CLASS_HID_4054a = 0x4054a, + BNXT_ULP_CLASS_HID_43c5a = 0x43c5a, + BNXT_ULP_CLASS_HID_40b0e = 0x40b0e, + BNXT_ULP_CLASS_HID_4221e = 0x4221e, + BNXT_ULP_CLASS_HID_43b36 = 0x43b36, + BNXT_ULP_CLASS_HID_45206 = 0x45206, + BNXT_ULP_CLASS_HID_420fa = 0x420fa, + BNXT_ULP_CLASS_HID_45bca = 0x45bca, + BNXT_ULP_CLASS_HID_45ade = 0x45ade, + BNXT_ULP_CLASS_HID_416fa = 0x416fa, + BNXT_ULP_CLASS_HID_440e2 = 0x440e2, + BNXT_ULP_CLASS_HID_41cbe = 0x41cbe, + BNXT_ULP_CLASS_HID_4566e = 0x4566e, + BNXT_ULP_CLASS_HID_4120a = 0x4120a, + BNXT_ULP_CLASS_HID_45c32 = 0x45c32, + BNXT_ULP_CLASS_HID_41bce = 0x41bce, + BNXT_ULP_CLASS_HID_41b22 = 0x41b22, + BNXT_ULP_CLASS_HID_43232 = 0x43232, + BNXT_ULP_CLASS_HID_400e6 = 0x400e6, + BNXT_ULP_CLASS_HID_43bf6 = 0x43bf6, + BNXT_ULP_CLASS_HID_4308e = 0x4308e, + BNXT_ULP_CLASS_HID_42b9e = 0x42b9e, + BNXT_ULP_CLASS_HID_43652 = 0x43652, + BNXT_ULP_CLASS_HID_451a2 = 0x451a2, + BNXT_ULP_CLASS_HID_450b6 = 0x450b6, + BNXT_ULP_CLASS_HID_44b86 = 0x44b86, + BNXT_ULP_CLASS_HID_4567a = 0x4567a, + BNXT_ULP_CLASS_HID_41216 = 0x41216, + BNXT_ULP_CLASS_HID_4167a = 0x4167a, + BNXT_ULP_CLASS_HID_4314a = 0x4314a, + BNXT_ULP_CLASS_HID_41c3e = 0x41c3e, + BNXT_ULP_CLASS_HID_4370e = 0x4370e, + BNXT_ULP_CLASS_HID_42fce = 0x42fce, + BNXT_ULP_CLASS_HID_446de = 0x446de, + BNXT_ULP_CLASS_HID_45582 = 0x45582, + BNXT_ULP_CLASS_HID_411ae = 0x411ae, + BNXT_ULP_CLASS_HID_44b36 = 0x44b36, + BNXT_ULP_CLASS_HID_406d2 = 0x406d2, + BNXT_ULP_CLASS_HID_41586 = 0x41586, + BNXT_ULP_CLASS_HID_40c96 = 0x40c96, + BNXT_ULP_CLASS_HID_42556 = 0x42556, + BNXT_ULP_CLASS_HID_45ca6 = 0x45ca6, + BNXT_ULP_CLASS_HID_42b6a = 0x42b6a, + BNXT_ULP_CLASS_HID_4427a = 0x4427a, + BNXT_ULP_CLASS_HID_6227a = 0x6227a, + BNXT_ULP_CLASS_HID_65d4a = 0x65d4a, + BNXT_ULP_CLASS_HID_6283e = 0x6283e, + BNXT_ULP_CLASS_HID_6430e = 0x6430e, + BNXT_ULP_CLASS_HID_61c9a = 0x61c9a, + BNXT_ULP_CLASS_HID_637ea = 0x637ea, + BNXT_ULP_CLASS_HID_6025e = 0x6025e, + BNXT_ULP_CLASS_HID_63dae = 0x63dae, + BNXT_ULP_CLASS_HID_63bc2 = 0x63bc2, + BNXT_ULP_CLASS_HID_652d2 = 0x652d2, + BNXT_ULP_CLASS_HID_62186 = 0x62186, + BNXT_ULP_CLASS_HID_65896 = 0x65896, + BNXT_ULP_CLASS_HID_61262 = 0x61262, + BNXT_ULP_CLASS_HID_60d72 = 0x60d72, + BNXT_ULP_CLASS_HID_61826 = 0x61826, + BNXT_ULP_CLASS_HID_63336 = 0x63336, + BNXT_ULP_CLASS_HID_50c7a = 0x50c7a, + BNXT_ULP_CLASS_HID_5274a = 0x5274a, + BNXT_ULP_CLASS_HID_5323e = 0x5323e, + BNXT_ULP_CLASS_HID_52d0e = 0x52d0e, + BNXT_ULP_CLASS_HID_545ce = 0x545ce, + BNXT_ULP_CLASS_HID_501ea = 0x501ea, + BNXT_ULP_CLASS_HID_54b82 = 0x54b82, + BNXT_ULP_CLASS_HID_507ae = 0x507ae, + BNXT_ULP_CLASS_HID_505c2 = 0x505c2, + BNXT_ULP_CLASS_HID_53cd2 = 0x53cd2, + BNXT_ULP_CLASS_HID_50b86 = 0x50b86, + BNXT_ULP_CLASS_HID_52296 = 0x52296, + BNXT_ULP_CLASS_HID_55b56 = 0x55b56, + BNXT_ULP_CLASS_HID_51772 = 0x51772, + BNXT_ULP_CLASS_HID_5416a = 0x5416a, + BNXT_ULP_CLASS_HID_51d36 = 0x51d36, + BNXT_ULP_CLASS_HID_7587a = 0x7587a, + BNXT_ULP_CLASS_HID_71406 = 0x71406, + BNXT_ULP_CLASS_HID_75e3e = 0x75e3e, + BNXT_ULP_CLASS_HID_71dda = 0x71dda, + BNXT_ULP_CLASS_HID_7329a = 0x7329a, + BNXT_ULP_CLASS_HID_72dea = 0x72dea, + BNXT_ULP_CLASS_HID_7385e = 0x7385e, + BNXT_ULP_CLASS_HID_753ae = 0x753ae, + BNXT_ULP_CLASS_HID_751c2 = 0x751c2, + BNXT_ULP_CLASS_HID_748d2 = 0x748d2, + BNXT_ULP_CLASS_HID_75786 = 0x75786, + BNXT_ULP_CLASS_HID_713a2 = 0x713a2, + BNXT_ULP_CLASS_HID_70862 = 0x70862, + BNXT_ULP_CLASS_HID_72372 = 0x72372, + BNXT_ULP_CLASS_HID_70e26 = 0x70e26, + BNXT_ULP_CLASS_HID_72936 = 0x72936, + BNXT_ULP_CLASS_HID_229b8 = 0x229b8, BNXT_ULP_CLASS_HID_240a8 = 0x240a8, - BNXT_ULP_CLASS_HID_2cda8 = 0x2cda8, - BNXT_ULP_CLASS_HID_31b5c = 0x31b5c, - BNXT_ULP_CLASS_HID_3845c = 0x3845c, - BNXT_ULP_CLASS_HID_22ff8 = 0x22ff8, - BNXT_ULP_CLASS_HID_2d8f8 = 0x2d8f8, - BNXT_ULP_CLASS_HID_345f8 = 0x345f8, - BNXT_ULP_CLASS_HID_393ac = 0x393ac, - BNXT_ULP_CLASS_HID_228ac = 0x228ac, - BNXT_ULP_CLASS_HID_2d5ac = 0x2d5ac, - BNXT_ULP_CLASS_HID_35eac = 0x35eac, - BNXT_ULP_CLASS_HID_3cbac = 0x3cbac, - BNXT_ULP_CLASS_HID_25d5c = 0x25d5c, - BNXT_ULP_CLASS_HID_2c65c = 0x2c65c, - BNXT_ULP_CLASS_HID_31410 = 0x31410, - BNXT_ULP_CLASS_HID_38110 = 0x38110, - BNXT_ULP_CLASS_HID_209f0 = 0x209f0, - BNXT_ULP_CLASS_HID_2b2f0 = 0x2b2f0, - BNXT_ULP_CLASS_HID_33ff0 = 0x33ff0, - BNXT_ULP_CLASS_HID_3a8f0 = 0x3a8f0, - BNXT_ULP_CLASS_HID_214c0 = 0x214c0, - BNXT_ULP_CLASS_HID_281c0 = 0x281c0, - BNXT_ULP_CLASS_HID_30ac0 = 0x30ac0, - BNXT_ULP_CLASS_HID_3b7c0 = 0x3b7c0, - BNXT_ULP_CLASS_HID_211f4 = 0x211f4, - BNXT_ULP_CLASS_HID_29af4 = 0x29af4, - BNXT_ULP_CLASS_HID_307f4 = 0x307f4, - BNXT_ULP_CLASS_HID_3b0f4 = 0x3b0f4, - BNXT_ULP_CLASS_HID_202a4 = 0x202a4, - BNXT_ULP_CLASS_HID_28fa4 = 0x28fa4, - BNXT_ULP_CLASS_HID_338a4 = 0x338a4, - BNXT_ULP_CLASS_HID_3a5a4 = 0x3a5a4, + BNXT_ULP_CLASS_HID_22f74 = 0x22f74, + BNXT_ULP_CLASS_HID_24664 = 0x24664, + BNXT_ULP_CLASS_HID_23314 = 0x23314, BNXT_ULP_CLASS_HID_22a04 = 0x22a04, - BNXT_ULP_CLASS_HID_2d704 = 0x2d704, - BNXT_ULP_CLASS_HID_34004 = 0x34004, - BNXT_ULP_CLASS_HID_3cd04 = 0x3cd04, - BNXT_ULP_CLASS_HID_23954 = 0x23954, - BNXT_ULP_CLASS_HID_2a254 = 0x2a254, - BNXT_ULP_CLASS_HID_32f54 = 0x32f54, - BNXT_ULP_CLASS_HID_3d854 = 0x3d854, - BNXT_ULP_CLASS_HID_23208 = 0x23208, - BNXT_ULP_CLASS_HID_2bf08 = 0x2bf08, - BNXT_ULP_CLASS_HID_32808 = 0x32808, - BNXT_ULP_CLASS_HID_3d508 = 0x3d508, - BNXT_ULP_CLASS_HID_22738 = 0x22738, - BNXT_ULP_CLASS_HID_2d038 = 0x2d038, - BNXT_ULP_CLASS_HID_35d38 = 0x35d38, - BNXT_ULP_CLASS_HID_3c638 = 0x3c638, + BNXT_ULP_CLASS_HID_238d0 = 0x238d0, + BNXT_ULP_CLASS_HID_253c0 = 0x253c0, + BNXT_ULP_CLASS_HID_24dcc = 0x24dcc, + BNXT_ULP_CLASS_HID_209f0 = 0x209f0, + BNXT_ULP_CLASS_HID_214bc = 0x214bc, + BNXT_ULP_CLASS_HID_20fac = 0x20fac, + BNXT_ULP_CLASS_HID_257a8 = 0x257a8, BNXT_ULP_CLASS_HID_2134c = 0x2134c, - BNXT_ULP_CLASS_HID_29c4c = 0x29c4c, - BNXT_ULP_CLASS_HID_3094c = 0x3094c, - BNXT_ULP_CLASS_HID_3b24c = 0x3b24c, - BNXT_ULP_CLASS_HID_25de8 = 0x25de8, - BNXT_ULP_CLASS_HID_2c6e8 = 0x2c6e8, - BNXT_ULP_CLASS_HID_3149c = 0x3149c, - BNXT_ULP_CLASS_HID_3819c = 0x3819c, - BNXT_ULP_CLASS_HID_2569c = 0x2569c, - BNXT_ULP_CLASS_HID_2c39c = 0x2c39c, - BNXT_ULP_CLASS_HID_31150 = 0x31150, - BNXT_ULP_CLASS_HID_39a50 = 0x39a50, - BNXT_ULP_CLASS_HID_24b4c = 0x24b4c, - BNXT_ULP_CLASS_HID_29900 = 0x29900, - BNXT_ULP_CLASS_HID_30200 = 0x30200, - BNXT_ULP_CLASS_HID_38f00 = 0x38f00, - BNXT_ULP_CLASS_HID_22f74 = 0x22f74, - BNXT_ULP_CLASS_HID_2d874 = 0x2d874, - BNXT_ULP_CLASS_HID_34574 = 0x34574, - BNXT_ULP_CLASS_HID_39328 = 0x39328, + BNXT_ULP_CLASS_HID_25d64 = 0x25d64, + BNXT_ULP_CLASS_HID_21908 = 0x21908, + BNXT_ULP_CLASS_HID_23488 = 0x23488, + BNXT_ULP_CLASS_HID_22ff8 = 0x22ff8, BNXT_ULP_CLASS_HID_23a44 = 0x23a44, - BNXT_ULP_CLASS_HID_2a744 = 0x2a744, - BNXT_ULP_CLASS_HID_35044 = 0x35044, - BNXT_ULP_CLASS_HID_3dd44 = 0x3dd44, - BNXT_ULP_CLASS_HID_23778 = 0x23778, - BNXT_ULP_CLASS_HID_2a078 = 0x2a078, - BNXT_ULP_CLASS_HID_32d78 = 0x32d78, - BNXT_ULP_CLASS_HID_3d678 = 0x3d678, - BNXT_ULP_CLASS_HID_22828 = 0x22828, - BNXT_ULP_CLASS_HID_2d528 = 0x2d528, - BNXT_ULP_CLASS_HID_35e28 = 0x35e28, - BNXT_ULP_CLASS_HID_3cb28 = 0x3cb28, - BNXT_ULP_CLASS_HID_214bc = 0x214bc, - BNXT_ULP_CLASS_HID_281bc = 0x281bc, - BNXT_ULP_CLASS_HID_30abc = 0x30abc, - BNXT_ULP_CLASS_HID_3b7bc = 0x3b7bc, + BNXT_ULP_CLASS_HID_255b4 = 0x255b4, + BNXT_ULP_CLASS_HID_21e64 = 0x21e64, + BNXT_ULP_CLASS_HID_23954 = 0x23954, + BNXT_ULP_CLASS_HID_20420 = 0x20420, + BNXT_ULP_CLASS_HID_23f10 = 0x23f10, + BNXT_ULP_CLASS_HID_2591c = 0x2591c, + BNXT_ULP_CLASS_HID_214c0 = 0x214c0, BNXT_ULP_CLASS_HID_25ed8 = 0x25ed8, - BNXT_ULP_CLASS_HID_2cbd8 = 0x2cbd8, - BNXT_ULP_CLASS_HID_3198c = 0x3198c, - BNXT_ULP_CLASS_HID_3828c = 0x3828c, - BNXT_ULP_CLASS_HID_25b8c = 0x25b8c, - BNXT_ULP_CLASS_HID_2c48c = 0x2c48c, - BNXT_ULP_CLASS_HID_31240 = 0x31240, - BNXT_ULP_CLASS_HID_39f40 = 0x39f40, - BNXT_ULP_CLASS_HID_21170 = 0x21170, - BNXT_ULP_CLASS_HID_29a70 = 0x29a70, - BNXT_ULP_CLASS_HID_30770 = 0x30770, - BNXT_ULP_CLASS_HID_3b070 = 0x3b070, - BNXT_ULP_CLASS_HID_238d0 = 0x238d0, - BNXT_ULP_CLASS_HID_2a5d0 = 0x2a5d0, + BNXT_ULP_CLASS_HID_21afc = 0x21afc, + BNXT_ULP_CLASS_HID_222f8 = 0x222f8, + BNXT_ULP_CLASS_HID_25de8 = 0x25de8, + BNXT_ULP_CLASS_HID_228b4 = 0x228b4, + BNXT_ULP_CLASS_HID_243a4 = 0x243a4, + BNXT_ULP_CLASS_HID_6226c = 0x6226c, + BNXT_ULP_CLASS_HID_65d5c = 0x65d5c, + BNXT_ULP_CLASS_HID_62828 = 0x62828, + BNXT_ULP_CLASS_HID_64318 = 0x64318, + BNXT_ULP_CLASS_HID_60fc8 = 0x60fc8, + BNXT_ULP_CLASS_HID_62738 = 0x62738, + BNXT_ULP_CLASS_HID_63584 = 0x63584, + BNXT_ULP_CLASS_HID_62cf4 = 0x62cf4, + BNXT_ULP_CLASS_HID_64680 = 0x64680, + BNXT_ULP_CLASS_HID_602a4 = 0x602a4, + BNXT_ULP_CLASS_HID_61170 = 0x61170, + BNXT_ULP_CLASS_HID_60860 = 0x60860, + BNXT_ULP_CLASS_HID_6505c = 0x6505c, + BNXT_ULP_CLASS_HID_64b4c = 0x64b4c, + BNXT_ULP_CLASS_HID_65618 = 0x65618, + BNXT_ULP_CLASS_HID_6123c = 0x6123c, + BNXT_ULP_CLASS_HID_631bc = 0x631bc, + BNXT_ULP_CLASS_HID_628ac = 0x628ac, + BNXT_ULP_CLASS_HID_63778 = 0x63778, + BNXT_ULP_CLASS_HID_62e68 = 0x62e68, + BNXT_ULP_CLASS_HID_61b18 = 0x61b18, + BNXT_ULP_CLASS_HID_63208 = 0x63208, + BNXT_ULP_CLASS_HID_600d4 = 0x600d4, + BNXT_ULP_CLASS_HID_63bc4 = 0x63bc4, + BNXT_ULP_CLASS_HID_655d0 = 0x655d0, + BNXT_ULP_CLASS_HID_611f4 = 0x611f4, + BNXT_ULP_CLASS_HID_65b8c = 0x65b8c, + BNXT_ULP_CLASS_HID_617b0 = 0x617b0, + BNXT_ULP_CLASS_HID_63fac = 0x63fac, + BNXT_ULP_CLASS_HID_6569c = 0x6569c, + BNXT_ULP_CLASS_HID_62568 = 0x62568, + BNXT_ULP_CLASS_HID_65c58 = 0x65c58, + BNXT_ULP_CLASS_HID_35fb8 = 0x35fb8, + BNXT_ULP_CLASS_HID_31b5c = 0x31b5c, + BNXT_ULP_CLASS_HID_34574 = 0x34574, + BNXT_ULP_CLASS_HID_30118 = 0x30118, + BNXT_ULP_CLASS_HID_32914 = 0x32914, + BNXT_ULP_CLASS_HID_34004 = 0x34004, BNXT_ULP_CLASS_HID_32ed0 = 0x32ed0, - BNXT_ULP_CLASS_HID_3dbd0 = 0x3dbd0, - BNXT_ULP_CLASS_HID_20420 = 0x20420, - BNXT_ULP_CLASS_HID_2b120 = 0x2b120, - BNXT_ULP_CLASS_HID_33a20 = 0x33a20, - BNXT_ULP_CLASS_HID_3a720 = 0x3a720, - BNXT_ULP_CLASS_HID_200d4 = 0x200d4, - BNXT_ULP_CLASS_HID_28dd4 = 0x28dd4, - BNXT_ULP_CLASS_HID_336d4 = 0x336d4, - BNXT_ULP_CLASS_HID_3a3d4 = 0x3a3d4, - BNXT_ULP_CLASS_HID_23584 = 0x23584, - BNXT_ULP_CLASS_HID_2be84 = 0x2be84, - BNXT_ULP_CLASS_HID_32b84 = 0x32b84, - BNXT_ULP_CLASS_HID_3d484 = 0x3d484, - BNXT_ULP_CLASS_HID_25d64 = 0x25d64, - BNXT_ULP_CLASS_HID_2c664 = 0x2c664, + BNXT_ULP_CLASS_HID_349c0 = 0x349c0, + BNXT_ULP_CLASS_HID_30480 = 0x30480, + BNXT_ULP_CLASS_HID_33ff0 = 0x33ff0, + BNXT_ULP_CLASS_HID_30abc = 0x30abc, + BNXT_ULP_CLASS_HID_325ac = 0x325ac, + BNXT_ULP_CLASS_HID_34da8 = 0x34da8, + BNXT_ULP_CLASS_HID_3094c = 0x3094c, BNXT_ULP_CLASS_HID_31418 = 0x31418, - BNXT_ULP_CLASS_HID_38118 = 0x38118, - BNXT_ULP_CLASS_HID_228b4 = 0x228b4, - BNXT_ULP_CLASS_HID_2d5b4 = 0x2d5b4, + BNXT_ULP_CLASS_HID_30f08 = 0x30f08, + BNXT_ULP_CLASS_HID_32a88 = 0x32a88, + BNXT_ULP_CLASS_HID_345f8 = 0x345f8, + BNXT_ULP_CLASS_HID_35044 = 0x35044, + BNXT_ULP_CLASS_HID_34bb4 = 0x34bb4, + BNXT_ULP_CLASS_HID_33464 = 0x33464, + BNXT_ULP_CLASS_HID_32f54 = 0x32f54, + BNXT_ULP_CLASS_HID_33a20 = 0x33a20, + BNXT_ULP_CLASS_HID_35510 = 0x35510, + BNXT_ULP_CLASS_HID_313d0 = 0x313d0, + BNXT_ULP_CLASS_HID_30ac0 = 0x30ac0, + BNXT_ULP_CLASS_HID_3198c = 0x3198c, + BNXT_ULP_CLASS_HID_330fc = 0x330fc, + BNXT_ULP_CLASS_HID_358f8 = 0x358f8, + BNXT_ULP_CLASS_HID_3149c = 0x3149c, BNXT_ULP_CLASS_HID_35eb4 = 0x35eb4, - BNXT_ULP_CLASS_HID_3cbb4 = 0x3cbb4, - BNXT_ULP_CLASS_HID_22568 = 0x22568, - BNXT_ULP_CLASS_HID_2ae68 = 0x2ae68, - BNXT_ULP_CLASS_HID_35b68 = 0x35b68, - BNXT_ULP_CLASS_HID_3c468 = 0x3c468, - BNXT_ULP_CLASS_HID_25618 = 0x25618, - BNXT_ULP_CLASS_HID_2c318 = 0x2c318, - BNXT_ULP_CLASS_HID_310cc = 0x310cc, - BNXT_ULP_CLASS_HID_39dcc = 0x39dcc, - BNXT_ULP_CLASS_HID_229b8 = 0x229b8, + BNXT_ULP_CLASS_HID_31a58 = 0x31a58, + BNXT_ULP_CLASS_HID_7586c = 0x7586c, + BNXT_ULP_CLASS_HID_71410 = 0x71410, + BNXT_ULP_CLASS_HID_75e28 = 0x75e28, + BNXT_ULP_CLASS_HID_71dcc = 0x71dcc, + BNXT_ULP_CLASS_HID_725c8 = 0x725c8, + BNXT_ULP_CLASS_HID_75d38 = 0x75d38, + BNXT_ULP_CLASS_HID_72b84 = 0x72b84, + BNXT_ULP_CLASS_HID_742f4 = 0x742f4, + BNXT_ULP_CLASS_HID_701b4 = 0x701b4, + BNXT_ULP_CLASS_HID_738a4 = 0x738a4, + BNXT_ULP_CLASS_HID_70770 = 0x70770, + BNXT_ULP_CLASS_HID_73e60 = 0x73e60, + BNXT_ULP_CLASS_HID_7465c = 0x7465c, + BNXT_ULP_CLASS_HID_70200 = 0x70200, + BNXT_ULP_CLASS_HID_710cc = 0x710cc, + BNXT_ULP_CLASS_HID_7083c = 0x7083c, + BNXT_ULP_CLASS_HID_727bc = 0x727bc, + BNXT_ULP_CLASS_HID_75eac = 0x75eac, + BNXT_ULP_CLASS_HID_72d78 = 0x72d78, + BNXT_ULP_CLASS_HID_74468 = 0x74468, + BNXT_ULP_CLASS_HID_73118 = 0x73118, + BNXT_ULP_CLASS_HID_72808 = 0x72808, + BNXT_ULP_CLASS_HID_736d4 = 0x736d4, + BNXT_ULP_CLASS_HID_751c4 = 0x751c4, + BNXT_ULP_CLASS_HID_74bd0 = 0x74bd0, + BNXT_ULP_CLASS_HID_707f4 = 0x707f4, + BNXT_ULP_CLASS_HID_71240 = 0x71240, + BNXT_ULP_CLASS_HID_70db0 = 0x70db0, + BNXT_ULP_CLASS_HID_755ac = 0x755ac, + BNXT_ULP_CLASS_HID_71150 = 0x71150, + BNXT_ULP_CLASS_HID_75b68 = 0x75b68, + BNXT_ULP_CLASS_HID_7170c = 0x7170c, BNXT_ULP_CLASS_HID_2d2b8 = 0x2d2b8, - BNXT_ULP_CLASS_HID_35fb8 = 0x35fb8, - BNXT_ULP_CLASS_HID_3c8b8 = 0x3c8b8, - BNXT_ULP_CLASS_HID_23488 = 0x23488, - BNXT_ULP_CLASS_HID_2a188 = 0x2a188, - BNXT_ULP_CLASS_HID_32a88 = 0x32a88, - BNXT_ULP_CLASS_HID_3d788 = 0x3d788, - BNXT_ULP_CLASS_HID_231bc = 0x231bc, - BNXT_ULP_CLASS_HID_2babc = 0x2babc, - BNXT_ULP_CLASS_HID_327bc = 0x327bc, - BNXT_ULP_CLASS_HID_3d0bc = 0x3d0bc, - BNXT_ULP_CLASS_HID_2226c = 0x2226c, - BNXT_ULP_CLASS_HID_2af6c = 0x2af6c, - BNXT_ULP_CLASS_HID_3586c = 0x3586c, - BNXT_ULP_CLASS_HID_3c56c = 0x3c56c, - BNXT_ULP_CLASS_HID_24dcc = 0x24dcc, + BNXT_ULP_CLASS_HID_2cda8 = 0x2cda8, + BNXT_ULP_CLASS_HID_2d874 = 0x2d874, + BNXT_ULP_CLASS_HID_29418 = 0x29418, + BNXT_ULP_CLASS_HID_2bc14 = 0x2bc14, + BNXT_ULP_CLASS_HID_2d704 = 0x2d704, + BNXT_ULP_CLASS_HID_2a5d0 = 0x2a5d0, + BNXT_ULP_CLASS_HID_2dcc0 = 0x2dcc0, BNXT_ULP_CLASS_HID_29b80 = 0x29b80, - BNXT_ULP_CLASS_HID_30480 = 0x30480, - BNXT_ULP_CLASS_HID_3b180 = 0x3b180, - BNXT_ULP_CLASS_HID_2591c = 0x2591c, + BNXT_ULP_CLASS_HID_2b2f0 = 0x2b2f0, + BNXT_ULP_CLASS_HID_281bc = 0x281bc, + BNXT_ULP_CLASS_HID_2b8ac = 0x2b8ac, + BNXT_ULP_CLASS_HID_2c0a8 = 0x2c0a8, + BNXT_ULP_CLASS_HID_29c4c = 0x29c4c, + BNXT_ULP_CLASS_HID_2c664 = 0x2c664, + BNXT_ULP_CLASS_HID_28208 = 0x28208, + BNXT_ULP_CLASS_HID_2a188 = 0x2a188, + BNXT_ULP_CLASS_HID_2d8f8 = 0x2d8f8, + BNXT_ULP_CLASS_HID_2a744 = 0x2a744, + BNXT_ULP_CLASS_HID_2deb4 = 0x2deb4, + BNXT_ULP_CLASS_HID_28b64 = 0x28b64, + BNXT_ULP_CLASS_HID_2a254 = 0x2a254, + BNXT_ULP_CLASS_HID_2b120 = 0x2b120, + BNXT_ULP_CLASS_HID_2a810 = 0x2a810, BNXT_ULP_CLASS_HID_2c21c = 0x2c21c, - BNXT_ULP_CLASS_HID_313d0 = 0x313d0, - BNXT_ULP_CLASS_HID_39cd0 = 0x39cd0, - BNXT_ULP_CLASS_HID_255d0 = 0x255d0, - BNXT_ULP_CLASS_HID_2ded0 = 0x2ded0, - BNXT_ULP_CLASS_HID_34bd0 = 0x34bd0, - BNXT_ULP_CLASS_HID_39984 = 0x39984, - BNXT_ULP_CLASS_HID_24680 = 0x24680, - BNXT_ULP_CLASS_HID_294b4 = 0x294b4, - BNXT_ULP_CLASS_HID_301b4 = 0x301b4, - BNXT_ULP_CLASS_HID_38ab4 = 0x38ab4, - BNXT_ULP_CLASS_HID_23314 = 0x23314, - BNXT_ULP_CLASS_HID_2bc14 = 0x2bc14, - BNXT_ULP_CLASS_HID_32914 = 0x32914, + BNXT_ULP_CLASS_HID_281c0 = 0x281c0, + BNXT_ULP_CLASS_HID_2cbd8 = 0x2cbd8, + BNXT_ULP_CLASS_HID_287fc = 0x287fc, + BNXT_ULP_CLASS_HID_2aff8 = 0x2aff8, + BNXT_ULP_CLASS_HID_2c6e8 = 0x2c6e8, + BNXT_ULP_CLASS_HID_2d5b4 = 0x2d5b4, + BNXT_ULP_CLASS_HID_29158 = 0x29158, + BNXT_ULP_CLASS_HID_6af6c = 0x6af6c, + BNXT_ULP_CLASS_HID_6c65c = 0x6c65c, + BNXT_ULP_CLASS_HID_6d528 = 0x6d528, + BNXT_ULP_CLASS_HID_690cc = 0x690cc, + BNXT_ULP_CLASS_HID_6b8c8 = 0x6b8c8, + BNXT_ULP_CLASS_HID_6d038 = 0x6d038, + BNXT_ULP_CLASS_HID_6be84 = 0x6be84, + BNXT_ULP_CLASS_HID_6d9f4 = 0x6d9f4, + BNXT_ULP_CLASS_HID_694b4 = 0x694b4, + BNXT_ULP_CLASS_HID_68fa4 = 0x68fa4, + BNXT_ULP_CLASS_HID_69a70 = 0x69a70, + BNXT_ULP_CLASS_HID_6b560 = 0x6b560, + BNXT_ULP_CLASS_HID_6dd5c = 0x6dd5c, + BNXT_ULP_CLASS_HID_69900 = 0x69900, + BNXT_ULP_CLASS_HID_6c318 = 0x6c318, + BNXT_ULP_CLASS_HID_69f3c = 0x69f3c, + BNXT_ULP_CLASS_HID_6babc = 0x6babc, + BNXT_ULP_CLASS_HID_6d5ac = 0x6d5ac, + BNXT_ULP_CLASS_HID_6a078 = 0x6a078, + BNXT_ULP_CLASS_HID_6db68 = 0x6db68, + BNXT_ULP_CLASS_HID_68418 = 0x68418, + BNXT_ULP_CLASS_HID_6bf08 = 0x6bf08, + BNXT_ULP_CLASS_HID_68dd4 = 0x68dd4, + BNXT_ULP_CLASS_HID_6a4c4 = 0x6a4c4, + BNXT_ULP_CLASS_HID_6ded0 = 0x6ded0, + BNXT_ULP_CLASS_HID_69af4 = 0x69af4, + BNXT_ULP_CLASS_HID_6c48c = 0x6c48c, + BNXT_ULP_CLASS_HID_680b0 = 0x680b0, + BNXT_ULP_CLASS_HID_6a8ac = 0x6a8ac, + BNXT_ULP_CLASS_HID_6c39c = 0x6c39c, + BNXT_ULP_CLASS_HID_6ae68 = 0x6ae68, + BNXT_ULP_CLASS_HID_6c958 = 0x6c958, + BNXT_ULP_CLASS_HID_3c8b8 = 0x3c8b8, + BNXT_ULP_CLASS_HID_3845c = 0x3845c, + BNXT_ULP_CLASS_HID_39328 = 0x39328, + BNXT_ULP_CLASS_HID_38a18 = 0x38a18, BNXT_ULP_CLASS_HID_3d214 = 0x3d214, - BNXT_ULP_CLASS_HID_21e64 = 0x21e64, - BNXT_ULP_CLASS_HID_28b64 = 0x28b64, - BNXT_ULP_CLASS_HID_33464 = 0x33464, - BNXT_ULP_CLASS_HID_3a164 = 0x3a164, - BNXT_ULP_CLASS_HID_21b18 = 0x21b18, - BNXT_ULP_CLASS_HID_28418 = 0x28418, - BNXT_ULP_CLASS_HID_33118 = 0x33118, - BNXT_ULP_CLASS_HID_3ba18 = 0x3ba18, - BNXT_ULP_CLASS_HID_20fc8 = 0x20fc8, - BNXT_ULP_CLASS_HID_2b8c8 = 0x2b8c8, - BNXT_ULP_CLASS_HID_325c8 = 0x325c8, - BNXT_ULP_CLASS_HID_3aec8 = 0x3aec8, - BNXT_ULP_CLASS_HID_257a8 = 0x257a8, - BNXT_ULP_CLASS_HID_2c0a8 = 0x2c0a8, - BNXT_ULP_CLASS_HID_34da8 = 0x34da8, + BNXT_ULP_CLASS_HID_3cd04 = 0x3cd04, + BNXT_ULP_CLASS_HID_3dbd0 = 0x3dbd0, + BNXT_ULP_CLASS_HID_397f4 = 0x397f4, + BNXT_ULP_CLASS_HID_3b180 = 0x3b180, + BNXT_ULP_CLASS_HID_3a8f0 = 0x3a8f0, + BNXT_ULP_CLASS_HID_3b7bc = 0x3b7bc, + BNXT_ULP_CLASS_HID_3aeac = 0x3aeac, BNXT_ULP_CLASS_HID_39b5c = 0x39b5c, - BNXT_ULP_CLASS_HID_222f8 = 0x222f8, - BNXT_ULP_CLASS_HID_2aff8 = 0x2aff8, - BNXT_ULP_CLASS_HID_358f8 = 0x358f8, + BNXT_ULP_CLASS_HID_3b24c = 0x3b24c, + BNXT_ULP_CLASS_HID_38118 = 0x38118, + BNXT_ULP_CLASS_HID_3b808 = 0x3b808, + BNXT_ULP_CLASS_HID_3d788 = 0x3d788, + BNXT_ULP_CLASS_HID_393ac = 0x393ac, + BNXT_ULP_CLASS_HID_3dd44 = 0x3dd44, + BNXT_ULP_CLASS_HID_39968 = 0x39968, + BNXT_ULP_CLASS_HID_3a164 = 0x3a164, + BNXT_ULP_CLASS_HID_3d854 = 0x3d854, + BNXT_ULP_CLASS_HID_3a720 = 0x3a720, + BNXT_ULP_CLASS_HID_3de10 = 0x3de10, + BNXT_ULP_CLASS_HID_39cd0 = 0x39cd0, + BNXT_ULP_CLASS_HID_3b7c0 = 0x3b7c0, + BNXT_ULP_CLASS_HID_3828c = 0x3828c, + BNXT_ULP_CLASS_HID_3bdfc = 0x3bdfc, BNXT_ULP_CLASS_HID_3c5f8 = 0x3c5f8, - BNXT_ULP_CLASS_HID_23fac = 0x23fac, - BNXT_ULP_CLASS_HID_2a8ac = 0x2a8ac, - BNXT_ULP_CLASS_HID_355ac = 0x355ac, - BNXT_ULP_CLASS_HID_3deac = 0x3deac, - BNXT_ULP_CLASS_HID_2505c = 0x2505c, - BNXT_ULP_CLASS_HID_2dd5c = 0x2dd5c, - BNXT_ULP_CLASS_HID_3465c = 0x3465c, - BNXT_ULP_CLASS_HID_39410 = 0x39410, - BNXT_ULP_CLASS_HID_223fc = 0x223fc, - BNXT_ULP_CLASS_HID_2acfc = 0x2acfc, - BNXT_ULP_CLASS_HID_359fc = 0x359fc, - BNXT_ULP_CLASS_HID_3c2fc = 0x3c2fc, - BNXT_ULP_CLASS_HID_20ecc = 0x20ecc, - BNXT_ULP_CLASS_HID_2bbcc = 0x2bbcc, - BNXT_ULP_CLASS_HID_324cc = 0x324cc, - BNXT_ULP_CLASS_HID_3d1cc = 0x3d1cc, - BNXT_ULP_CLASS_HID_20b80 = 0x20b80, - BNXT_ULP_CLASS_HID_2b480 = 0x2b480, - BNXT_ULP_CLASS_HID_32180 = 0x32180, - BNXT_ULP_CLASS_HID_3aa80 = 0x3aa80, - BNXT_ULP_CLASS_HID_23cb0 = 0x23cb0, - BNXT_ULP_CLASS_HID_2a9b0 = 0x2a9b0, - BNXT_ULP_CLASS_HID_352b0 = 0x352b0, - BNXT_ULP_CLASS_HID_3dfb0 = 0x3dfb0, - BNXT_ULP_CLASS_HID_24410 = 0x24410, - BNXT_ULP_CLASS_HID_295c4 = 0x295c4, - BNXT_ULP_CLASS_HID_31ec4 = 0x31ec4, - BNXT_ULP_CLASS_HID_38bc4 = 0x38bc4, - BNXT_ULP_CLASS_HID_25360 = 0x25360, - BNXT_ULP_CLASS_HID_2dc60 = 0x2dc60, - BNXT_ULP_CLASS_HID_34960 = 0x34960, - BNXT_ULP_CLASS_HID_39714 = 0x39714, - BNXT_ULP_CLASS_HID_22c14 = 0x22c14, - BNXT_ULP_CLASS_HID_2d914 = 0x2d914, - BNXT_ULP_CLASS_HID_34214 = 0x34214, - BNXT_ULP_CLASS_HID_393c8 = 0x393c8, - BNXT_ULP_CLASS_HID_240c4 = 0x240c4, - BNXT_ULP_CLASS_HID_2cdc4 = 0x2cdc4, - BNXT_ULP_CLASS_HID_31bf8 = 0x31bf8, - BNXT_ULP_CLASS_HID_384f8 = 0x384f8, - BNXT_ULP_CLASS_HID_23dc0 = 0x23dc0, - BNXT_ULP_CLASS_HID_2a6c0 = 0x2a6c0, - BNXT_ULP_CLASS_HID_353c0 = 0x353c0, - BNXT_ULP_CLASS_HID_3dcc0 = 0x3dcc0, - BNXT_ULP_CLASS_HID_20910 = 0x20910, - BNXT_ULP_CLASS_HID_2b210 = 0x2b210, - BNXT_ULP_CLASS_HID_33f10 = 0x33f10, - BNXT_ULP_CLASS_HID_3a810 = 0x3a810, - BNXT_ULP_CLASS_HID_205c4 = 0x205c4, - BNXT_ULP_CLASS_HID_28ec4 = 0x28ec4, - BNXT_ULP_CLASS_HID_33bc4 = 0x33bc4, - BNXT_ULP_CLASS_HID_3a4c4 = 0x3a4c4, - BNXT_ULP_CLASS_HID_236f4 = 0x236f4, - BNXT_ULP_CLASS_HID_2a3f4 = 0x2a3f4, - BNXT_ULP_CLASS_HID_32cf4 = 0x32cf4, - BNXT_ULP_CLASS_HID_3d9f4 = 0x3d9f4, - BNXT_ULP_CLASS_HID_25e54 = 0x25e54, - BNXT_ULP_CLASS_HID_2cb54 = 0x2cb54, - BNXT_ULP_CLASS_HID_31908 = 0x31908, - BNXT_ULP_CLASS_HID_38208 = 0x38208, - BNXT_ULP_CLASS_HID_22da4 = 0x22da4, - BNXT_ULP_CLASS_HID_2d6a4 = 0x2d6a4, - BNXT_ULP_CLASS_HID_343a4 = 0x343a4, - BNXT_ULP_CLASS_HID_39158 = 0x39158, - BNXT_ULP_CLASS_HID_22658 = 0x22658, - BNXT_ULP_CLASS_HID_2d358 = 0x2d358, - BNXT_ULP_CLASS_HID_35c58 = 0x35c58, - BNXT_ULP_CLASS_HID_3c958 = 0x3c958, - BNXT_ULP_CLASS_HID_25b08 = 0x25b08, - BNXT_ULP_CLASS_HID_2c408 = 0x2c408, - BNXT_ULP_CLASS_HID_3123c = 0x3123c, - BNXT_ULP_CLASS_HID_39f3c = 0x39f3c, - BNXT_ULP_CLASS_HID_34a8 = 0x34a8, - BNXT_ULP_CLASS_HID_3a64 = 0x3a64, - BNXT_ULP_CLASS_HID_09b4 = 0x09b4, - BNXT_ULP_CLASS_HID_5ef8 = 0x5ef8, - BNXT_ULP_CLASS_HID_2dc8 = 0x2dc8, - BNXT_ULP_CLASS_HID_07c0 = 0x07c0, - BNXT_ULP_CLASS_HID_1310 = 0x1310, - BNXT_ULP_CLASS_HID_2854 = 0x2854, - BNXT_ULP_CLASS_HID_37a4 = 0x37a4, - BNXT_ULP_CLASS_HID_03f8 = 0x03f8, - BNXT_ULP_CLASS_HID_593c = 0x593c, - BNXT_ULP_CLASS_HID_240c = 0x240c, - BNXT_ULP_CLASS_HID_1e04 = 0x1e04, - BNXT_ULP_CLASS_HID_48a0 = 0x48a0, - BNXT_ULP_CLASS_HID_2298 = 0x2298, - BNXT_ULP_CLASS_HID_31e8 = 0x31e8, + BNXT_ULP_CLASS_HID_3819c = 0x3819c, + BNXT_ULP_CLASS_HID_3cbb4 = 0x3cbb4, + BNXT_ULP_CLASS_HID_38758 = 0x38758, + BNXT_ULP_CLASS_HID_7c56c = 0x7c56c, + BNXT_ULP_CLASS_HID_78110 = 0x78110, + BNXT_ULP_CLASS_HID_7cb28 = 0x7cb28, + BNXT_ULP_CLASS_HID_786cc = 0x786cc, + BNXT_ULP_CLASS_HID_7aec8 = 0x7aec8, + BNXT_ULP_CLASS_HID_7c638 = 0x7c638, + BNXT_ULP_CLASS_HID_7d484 = 0x7d484, + BNXT_ULP_CLASS_HID_790a8 = 0x790a8, + BNXT_ULP_CLASS_HID_78ab4 = 0x78ab4, + BNXT_ULP_CLASS_HID_7a5a4 = 0x7a5a4, + BNXT_ULP_CLASS_HID_7b070 = 0x7b070, + BNXT_ULP_CLASS_HID_7ab60 = 0x7ab60, + BNXT_ULP_CLASS_HID_79410 = 0x79410, + BNXT_ULP_CLASS_HID_78f00 = 0x78f00, + BNXT_ULP_CLASS_HID_79dcc = 0x79dcc, + BNXT_ULP_CLASS_HID_7b53c = 0x7b53c, + BNXT_ULP_CLASS_HID_7d0bc = 0x7d0bc, + BNXT_ULP_CLASS_HID_7cbac = 0x7cbac, + BNXT_ULP_CLASS_HID_7d678 = 0x7d678, + BNXT_ULP_CLASS_HID_7921c = 0x7921c, + BNXT_ULP_CLASS_HID_7ba18 = 0x7ba18, + BNXT_ULP_CLASS_HID_7d508 = 0x7d508, + BNXT_ULP_CLASS_HID_7a3d4 = 0x7a3d4, + BNXT_ULP_CLASS_HID_7dac4 = 0x7dac4, + BNXT_ULP_CLASS_HID_79984 = 0x79984, + BNXT_ULP_CLASS_HID_7b0f4 = 0x7b0f4, + BNXT_ULP_CLASS_HID_79f40 = 0x79f40, + BNXT_ULP_CLASS_HID_7b6b0 = 0x7b6b0, + BNXT_ULP_CLASS_HID_7deac = 0x7deac, + BNXT_ULP_CLASS_HID_79a50 = 0x79a50, + BNXT_ULP_CLASS_HID_7c468 = 0x7c468, + BNXT_ULP_CLASS_HID_7800c = 0x7800c, + BNXT_ULP_CLASS_HID_86c0 = 0x86c0, + BNXT_ULP_CLASS_HID_a1d0 = 0xa1d0, + BNXT_ULP_CLASS_HID_8c0c = 0x8c0c, + BNXT_ULP_CLASS_HID_a71c = 0xa71c, + BNXT_ULP_CLASS_HID_906c = 0x906c, + BNXT_ULP_CLASS_HID_8b7c = 0x8b7c, + BNXT_ULP_CLASS_HID_99a8 = 0x99a8, + BNXT_ULP_CLASS_HID_b0b8 = 0xb0b8, + BNXT_ULP_CLASS_HID_aab4 = 0xaab4, + BNXT_ULP_CLASS_HID_c244 = 0xc244, + BNXT_ULP_CLASS_HID_d0f0 = 0xd0f0, + BNXT_ULP_CLASS_HID_cb80 = 0xcb80, + BNXT_ULP_CLASS_HID_b4d0 = 0xb4d0, + BNXT_ULP_CLASS_HID_afe0 = 0xafe0, + BNXT_ULP_CLASS_HID_ba1c = 0xba1c, + BNXT_ULP_CLASS_HID_d52c = 0xd52c, + BNXT_ULP_CLASS_HID_48314 = 0x48314, + BNXT_ULP_CLASS_HID_4ba24 = 0x4ba24, + BNXT_ULP_CLASS_HID_48950 = 0x48950, + BNXT_ULP_CLASS_HID_4a060 = 0x4a060, + BNXT_ULP_CLASS_HID_4c86c = 0x4c86c, + BNXT_ULP_CLASS_HID_48440 = 0x48440, + BNXT_ULP_CLASS_HID_492fc = 0x492fc, + BNXT_ULP_CLASS_HID_48d8c = 0x48d8c, + BNXT_ULP_CLASS_HID_4a7f8 = 0x4a7f8, + BNXT_ULP_CLASS_HID_4de88 = 0x4de88, + BNXT_ULP_CLASS_HID_4adc4 = 0x4adc4, + BNXT_ULP_CLASS_HID_4c4d4 = 0x4c4d4, + BNXT_ULP_CLASS_HID_4b124 = 0x4b124, + BNXT_ULP_CLASS_HID_4a834 = 0x4a834, + BNXT_ULP_CLASS_HID_4b760 = 0x4b760, + BNXT_ULP_CLASS_HID_4ae70 = 0x4ae70, + BNXT_ULP_CLASS_HID_1bcc0 = 0x1bcc0, + BNXT_ULP_CLASS_HID_1d7d0 = 0x1d7d0, + BNXT_ULP_CLASS_HID_1a20c = 0x1a20c, + BNXT_ULP_CLASS_HID_1dd1c = 0x1dd1c, + BNXT_ULP_CLASS_HID_1866c = 0x1866c, + BNXT_ULP_CLASS_HID_1a17c = 0x1a17c, + BNXT_ULP_CLASS_HID_18fa8 = 0x18fa8, + BNXT_ULP_CLASS_HID_1a6b8 = 0x1a6b8, + BNXT_ULP_CLASS_HID_1c0b4 = 0x1c0b4, + BNXT_ULP_CLASS_HID_19c88 = 0x19c88, + BNXT_ULP_CLASS_HID_1c6f0 = 0x1c6f0, + BNXT_ULP_CLASS_HID_182d4 = 0x182d4, + BNXT_ULP_CLASS_HID_1aad0 = 0x1aad0, + BNXT_ULP_CLASS_HID_1c5e0 = 0x1c5e0, + BNXT_ULP_CLASS_HID_1d01c = 0x1d01c, + BNXT_ULP_CLASS_HID_1cb2c = 0x1cb2c, + BNXT_ULP_CLASS_HID_5b914 = 0x5b914, + BNXT_ULP_CLASS_HID_5d024 = 0x5d024, + BNXT_ULP_CLASS_HID_5bf50 = 0x5bf50, + BNXT_ULP_CLASS_HID_5d660 = 0x5d660, + BNXT_ULP_CLASS_HID_582b0 = 0x582b0, + BNXT_ULP_CLASS_HID_5ba40 = 0x5ba40, + BNXT_ULP_CLASS_HID_588fc = 0x588fc, + BNXT_ULP_CLASS_HID_5a38c = 0x5a38c, + BNXT_ULP_CLASS_HID_5ddf8 = 0x5ddf8, + BNXT_ULP_CLASS_HID_599dc = 0x599dc, + BNXT_ULP_CLASS_HID_5c3c4 = 0x5c3c4, + BNXT_ULP_CLASS_HID_59f18 = 0x59f18, + BNXT_ULP_CLASS_HID_5a724 = 0x5a724, + BNXT_ULP_CLASS_HID_5de34 = 0x5de34, + BNXT_ULP_CLASS_HID_5ad60 = 0x5ad60, + BNXT_ULP_CLASS_HID_5c470 = 0x5c470, + BNXT_ULP_CLASS_HID_cd40 = 0xcd40, + BNXT_ULP_CLASS_HID_e450 = 0xe450, + BNXT_ULP_CLASS_HID_f28c = 0xf28c, + BNXT_ULP_CLASS_HID_ed9c = 0xed9c, + BNXT_ULP_CLASS_HID_d6ec = 0xd6ec, + BNXT_ULP_CLASS_HID_f1fc = 0xf1fc, + BNXT_ULP_CLASS_HID_dc28 = 0xdc28, + BNXT_ULP_CLASS_HID_f738 = 0xf738, + BNXT_ULP_CLASS_HID_d134 = 0xd134, + BNXT_ULP_CLASS_HID_c8c4 = 0xc8c4, + BNXT_ULP_CLASS_HID_d770 = 0xd770, + BNXT_ULP_CLASS_HID_d354 = 0xd354, + BNXT_ULP_CLASS_HID_fb50 = 0xfb50, + BNXT_ULP_CLASS_HID_d260 = 0xd260, + BNXT_ULP_CLASS_HID_e09c = 0xe09c, + BNXT_ULP_CLASS_HID_dbac = 0xdbac, + BNXT_ULP_CLASS_HID_4c994 = 0x4c994, + BNXT_ULP_CLASS_HID_4e0a4 = 0x4e0a4, + BNXT_ULP_CLASS_HID_4cfd0 = 0x4cfd0, + BNXT_ULP_CLASS_HID_4e6e0 = 0x4e6e0, + BNXT_ULP_CLASS_HID_4d330 = 0x4d330, + BNXT_ULP_CLASS_HID_4cac0 = 0x4cac0, + BNXT_ULP_CLASS_HID_4d97c = 0x4d97c, + BNXT_ULP_CLASS_HID_4f00c = 0x4f00c, + BNXT_ULP_CLASS_HID_4ea78 = 0x4ea78, + BNXT_ULP_CLASS_HID_4c508 = 0x4c508, + BNXT_ULP_CLASS_HID_4d044 = 0x4d044, + BNXT_ULP_CLASS_HID_4cb54 = 0x4cb54, + BNXT_ULP_CLASS_HID_4f7a4 = 0x4f7a4, + BNXT_ULP_CLASS_HID_4eeb4 = 0x4eeb4, + BNXT_ULP_CLASS_HID_4fde0 = 0x4fde0, + BNXT_ULP_CLASS_HID_4d4f0 = 0x4d4f0, + BNXT_ULP_CLASS_HID_1e340 = 0x1e340, + BNXT_ULP_CLASS_HID_1da50 = 0x1da50, + BNXT_ULP_CLASS_HID_1e88c = 0x1e88c, + BNXT_ULP_CLASS_HID_1c39c = 0x1c39c, + BNXT_ULP_CLASS_HID_1ccec = 0x1ccec, + BNXT_ULP_CLASS_HID_1e7fc = 0x1e7fc, + BNXT_ULP_CLASS_HID_1f228 = 0x1f228, + BNXT_ULP_CLASS_HID_1ed38 = 0x1ed38, + BNXT_ULP_CLASS_HID_1c734 = 0x1c734, + BNXT_ULP_CLASS_HID_1c308 = 0x1c308, + BNXT_ULP_CLASS_HID_1cd70 = 0x1cd70, + BNXT_ULP_CLASS_HID_1c954 = 0x1c954, + BNXT_ULP_CLASS_HID_1d150 = 0x1d150, + BNXT_ULP_CLASS_HID_1c860 = 0x1c860, + BNXT_ULP_CLASS_HID_1d69c = 0x1d69c, + BNXT_ULP_CLASS_HID_1d2f0 = 0x1d2f0, + BNXT_ULP_CLASS_HID_5ff94 = 0x5ff94, + BNXT_ULP_CLASS_HID_5d6a4 = 0x5d6a4, + BNXT_ULP_CLASS_HID_5e5d0 = 0x5e5d0, + BNXT_ULP_CLASS_HID_5dce0 = 0x5dce0, + BNXT_ULP_CLASS_HID_5c930 = 0x5c930, + BNXT_ULP_CLASS_HID_5e0c0 = 0x5e0c0, + BNXT_ULP_CLASS_HID_5cf7c = 0x5cf7c, + BNXT_ULP_CLASS_HID_5e60c = 0x5e60c, + BNXT_ULP_CLASS_HID_5c078 = 0x5c078, + BNXT_ULP_CLASS_HID_5dc5c = 0x5dc5c, + BNXT_ULP_CLASS_HID_5c644 = 0x5c644, + BNXT_ULP_CLASS_HID_5c598 = 0x5c598, + BNXT_ULP_CLASS_HID_5eda4 = 0x5eda4, + BNXT_ULP_CLASS_HID_5c4b4 = 0x5c4b4, + BNXT_ULP_CLASS_HID_5d3e0 = 0x5d3e0, + BNXT_ULP_CLASS_HID_5caf0 = 0x5caf0, + BNXT_ULP_CLASS_HID_ab80 = 0xab80, + BNXT_ULP_CLASS_HID_a290 = 0xa290, + BNXT_ULP_CLASS_HID_b1cc = 0xb1cc, + BNXT_ULP_CLASS_HID_a8dc = 0xa8dc, + BNXT_ULP_CLASS_HID_b52c = 0xb52c, + BNXT_ULP_CLASS_HID_ac3c = 0xac3c, + BNXT_ULP_CLASS_HID_bb68 = 0xbb68, + BNXT_ULP_CLASS_HID_b278 = 0xb278, + BNXT_ULP_CLASS_HID_ac74 = 0xac74, + BNXT_ULP_CLASS_HID_e704 = 0xe704, + BNXT_ULP_CLASS_HID_f5b0 = 0xf5b0, + BNXT_ULP_CLASS_HID_b194 = 0xb194, + BNXT_ULP_CLASS_HID_b990 = 0xb990, + BNXT_ULP_CLASS_HID_f0a0 = 0xf0a0, + BNXT_ULP_CLASS_HID_bfdc = 0xbfdc, + BNXT_ULP_CLASS_HID_f6ec = 0xf6ec, + BNXT_ULP_CLASS_HID_4a4d4 = 0x4a4d4, + BNXT_ULP_CLASS_HID_4bfe4 = 0x4bfe4, + BNXT_ULP_CLASS_HID_4aa10 = 0x4aa10, + BNXT_ULP_CLASS_HID_4a520 = 0x4a520, + BNXT_ULP_CLASS_HID_4ed2c = 0x4ed2c, + BNXT_ULP_CLASS_HID_4a900 = 0x4a900, + BNXT_ULP_CLASS_HID_4b7bc = 0x4b7bc, + BNXT_ULP_CLASS_HID_4af4c = 0x4af4c, + BNXT_ULP_CLASS_HID_4a8b8 = 0x4a8b8, + BNXT_ULP_CLASS_HID_4e048 = 0x4e048, + BNXT_ULP_CLASS_HID_4ae84 = 0x4ae84, + BNXT_ULP_CLASS_HID_4e994 = 0x4e994, + BNXT_ULP_CLASS_HID_4b2e4 = 0x4b2e4, + BNXT_ULP_CLASS_HID_4adf4 = 0x4adf4, + BNXT_ULP_CLASS_HID_4b820 = 0x4b820, + BNXT_ULP_CLASS_HID_4f330 = 0x4f330, + BNXT_ULP_CLASS_HID_1a180 = 0x1a180, + BNXT_ULP_CLASS_HID_1f890 = 0x1f890, + BNXT_ULP_CLASS_HID_1a7cc = 0x1a7cc, + BNXT_ULP_CLASS_HID_1fedc = 0x1fedc, + BNXT_ULP_CLASS_HID_1ab2c = 0x1ab2c, + BNXT_ULP_CLASS_HID_1a23c = 0x1a23c, + BNXT_ULP_CLASS_HID_1b168 = 0x1b168, + BNXT_ULP_CLASS_HID_1a878 = 0x1a878, + BNXT_ULP_CLASS_HID_1e274 = 0x1e274, + BNXT_ULP_CLASS_HID_1be48 = 0x1be48, + BNXT_ULP_CLASS_HID_1ebb0 = 0x1ebb0, + BNXT_ULP_CLASS_HID_1a794 = 0x1a794, + BNXT_ULP_CLASS_HID_1af90 = 0x1af90, + BNXT_ULP_CLASS_HID_1e6a0 = 0x1e6a0, + BNXT_ULP_CLASS_HID_1f5dc = 0x1f5dc, + BNXT_ULP_CLASS_HID_1b130 = 0x1b130, + BNXT_ULP_CLASS_HID_5bad4 = 0x5bad4, + BNXT_ULP_CLASS_HID_5f5e4 = 0x5f5e4, + BNXT_ULP_CLASS_HID_5a010 = 0x5a010, + BNXT_ULP_CLASS_HID_5fb20 = 0x5fb20, + BNXT_ULP_CLASS_HID_5a470 = 0x5a470, + BNXT_ULP_CLASS_HID_5bf00 = 0x5bf00, + BNXT_ULP_CLASS_HID_5adbc = 0x5adbc, + BNXT_ULP_CLASS_HID_5a54c = 0x5a54c, + BNXT_ULP_CLASS_HID_5feb8 = 0x5feb8, + BNXT_ULP_CLASS_HID_5ba9c = 0x5ba9c, + BNXT_ULP_CLASS_HID_5e484 = 0x5e484, + BNXT_ULP_CLASS_HID_5a0d8 = 0x5a0d8, + BNXT_ULP_CLASS_HID_5a8e4 = 0x5a8e4, + BNXT_ULP_CLASS_HID_5e3f4 = 0x5e3f4, + BNXT_ULP_CLASS_HID_5ae20 = 0x5ae20, + BNXT_ULP_CLASS_HID_5e930 = 0x5e930, + BNXT_ULP_CLASS_HID_ee00 = 0xee00, + BNXT_ULP_CLASS_HID_e910 = 0xe910, + BNXT_ULP_CLASS_HID_f44c = 0xf44c, + BNXT_ULP_CLASS_HID_ef5c = 0xef5c, + BNXT_ULP_CLASS_HID_fbac = 0xfbac, + BNXT_ULP_CLASS_HID_f2bc = 0xf2bc, + BNXT_ULP_CLASS_HID_e1e8 = 0xe1e8, + BNXT_ULP_CLASS_HID_f8f8 = 0xf8f8, + BNXT_ULP_CLASS_HID_f2f4 = 0xf2f4, + BNXT_ULP_CLASS_HID_ed84 = 0xed84, + BNXT_ULP_CLASS_HID_f830 = 0xf830, + BNXT_ULP_CLASS_HID_f414 = 0xf414, + BNXT_ULP_CLASS_HID_fc10 = 0xfc10, + BNXT_ULP_CLASS_HID_f720 = 0xf720, + BNXT_ULP_CLASS_HID_e25c = 0xe25c, + BNXT_ULP_CLASS_HID_fd6c = 0xfd6c, + BNXT_ULP_CLASS_HID_4eb54 = 0x4eb54, + BNXT_ULP_CLASS_HID_4e264 = 0x4e264, + BNXT_ULP_CLASS_HID_4f090 = 0x4f090, + BNXT_ULP_CLASS_HID_4eba0 = 0x4eba0, + BNXT_ULP_CLASS_HID_4f4f0 = 0x4f4f0, + BNXT_ULP_CLASS_HID_4ef80 = 0x4ef80, + BNXT_ULP_CLASS_HID_4fa3c = 0x4fa3c, + BNXT_ULP_CLASS_HID_4f5cc = 0x4f5cc, + BNXT_ULP_CLASS_HID_4ef38 = 0x4ef38, + BNXT_ULP_CLASS_HID_4e6c8 = 0x4e6c8, + BNXT_ULP_CLASS_HID_4f504 = 0x4f504, + BNXT_ULP_CLASS_HID_4f158 = 0x4f158, + BNXT_ULP_CLASS_HID_4f964 = 0x4f964, + BNXT_ULP_CLASS_HID_4f074 = 0x4f074, + BNXT_ULP_CLASS_HID_4fea0 = 0x4fea0, + BNXT_ULP_CLASS_HID_4f9b0 = 0x4f9b0, + BNXT_ULP_CLASS_HID_1e400 = 0x1e400, + BNXT_ULP_CLASS_HID_1ff10 = 0x1ff10, + BNXT_ULP_CLASS_HID_1ea4c = 0x1ea4c, + BNXT_ULP_CLASS_HID_1e55c = 0x1e55c, + BNXT_ULP_CLASS_HID_1f1ac = 0x1f1ac, + BNXT_ULP_CLASS_HID_1e8bc = 0x1e8bc, + BNXT_ULP_CLASS_HID_1f7e8 = 0x1f7e8, + BNXT_ULP_CLASS_HID_1eef8 = 0x1eef8, + BNXT_ULP_CLASS_HID_1e8f4 = 0x1e8f4, + BNXT_ULP_CLASS_HID_1e4c8 = 0x1e4c8, + BNXT_ULP_CLASS_HID_1f304 = 0x1f304, + BNXT_ULP_CLASS_HID_1ea14 = 0x1ea14, + BNXT_ULP_CLASS_HID_1f210 = 0x1f210, + BNXT_ULP_CLASS_HID_1ed20 = 0x1ed20, + BNXT_ULP_CLASS_HID_1f85c = 0x1f85c, + BNXT_ULP_CLASS_HID_1f7b0 = 0x1f7b0, + BNXT_ULP_CLASS_HID_5e154 = 0x5e154, + BNXT_ULP_CLASS_HID_5f864 = 0x5f864, + BNXT_ULP_CLASS_HID_5e690 = 0x5e690, + BNXT_ULP_CLASS_HID_5e1a0 = 0x5e1a0, + BNXT_ULP_CLASS_HID_5eaf0 = 0x5eaf0, + BNXT_ULP_CLASS_HID_5e580 = 0x5e580, + BNXT_ULP_CLASS_HID_5f03c = 0x5f03c, + BNXT_ULP_CLASS_HID_5ebcc = 0x5ebcc, + BNXT_ULP_CLASS_HID_5e538 = 0x5e538, + BNXT_ULP_CLASS_HID_5e11c = 0x5e11c, + BNXT_ULP_CLASS_HID_5eb04 = 0x5eb04, + BNXT_ULP_CLASS_HID_5e758 = 0x5e758, + BNXT_ULP_CLASS_HID_5ef64 = 0x5ef64, + BNXT_ULP_CLASS_HID_5e674 = 0x5e674, + BNXT_ULP_CLASS_HID_5f4a0 = 0x5f4a0, + BNXT_ULP_CLASS_HID_5f084 = 0x5f084, + BNXT_ULP_CLASS_HID_22998 = 0x22998, + BNXT_ULP_CLASS_HID_24088 = 0x24088, + BNXT_ULP_CLASS_HID_22f54 = 0x22f54, BNXT_ULP_CLASS_HID_24644 = 0x24644, - BNXT_ULP_CLASS_HID_29438 = 0x29438, - BNXT_ULP_CLASS_HID_30138 = 0x30138, - BNXT_ULP_CLASS_HID_38a38 = 0x38a38, - BNXT_ULP_CLASS_HID_25594 = 0x25594, - BNXT_ULP_CLASS_HID_2de94 = 0x2de94, - BNXT_ULP_CLASS_HID_34b94 = 0x34b94, - BNXT_ULP_CLASS_HID_39948 = 0x39948, - BNXT_ULP_CLASS_HID_22e48 = 0x22e48, - BNXT_ULP_CLASS_HID_2db48 = 0x2db48, - BNXT_ULP_CLASS_HID_34448 = 0x34448, - BNXT_ULP_CLASS_HID_3923c = 0x3923c, - BNXT_ULP_CLASS_HID_24338 = 0x24338, - BNXT_ULP_CLASS_HID_290ec = 0x290ec, - BNXT_ULP_CLASS_HID_31dec = 0x31dec, - BNXT_ULP_CLASS_HID_386ec = 0x386ec, - BNXT_ULP_CLASS_HID_20f8c = 0x20f8c, - BNXT_ULP_CLASS_HID_2b88c = 0x2b88c, - BNXT_ULP_CLASS_HID_3258c = 0x3258c, - BNXT_ULP_CLASS_HID_3ae8c = 0x3ae8c, - BNXT_ULP_CLASS_HID_21adc = 0x21adc, - BNXT_ULP_CLASS_HID_287dc = 0x287dc, - BNXT_ULP_CLASS_HID_330dc = 0x330dc, - BNXT_ULP_CLASS_HID_3bddc = 0x3bddc, - BNXT_ULP_CLASS_HID_21790 = 0x21790, - BNXT_ULP_CLASS_HID_28090 = 0x28090, - BNXT_ULP_CLASS_HID_30d90 = 0x30d90, - BNXT_ULP_CLASS_HID_3b690 = 0x3b690, - BNXT_ULP_CLASS_HID_20840 = 0x20840, - BNXT_ULP_CLASS_HID_2b540 = 0x2b540, - BNXT_ULP_CLASS_HID_33e40 = 0x33e40, - BNXT_ULP_CLASS_HID_3ab40 = 0x3ab40, + BNXT_ULP_CLASS_HID_23334 = 0x23334, + BNXT_ULP_CLASS_HID_22a24 = 0x22a24, + BNXT_ULP_CLASS_HID_238f0 = 0x238f0, BNXT_ULP_CLASS_HID_253e0 = 0x253e0, - BNXT_ULP_CLASS_HID_2dce0 = 0x2dce0, - BNXT_ULP_CLASS_HID_349e0 = 0x349e0, - BNXT_ULP_CLASS_HID_397d4 = 0x397d4, - BNXT_ULP_CLASS_HID_23f30 = 0x23f30, - BNXT_ULP_CLASS_HID_2a830 = 0x2a830, - BNXT_ULP_CLASS_HID_35530 = 0x35530, - BNXT_ULP_CLASS_HID_3de30 = 0x3de30, - BNXT_ULP_CLASS_HID_23be4 = 0x23be4, - BNXT_ULP_CLASS_HID_2a4e4 = 0x2a4e4, - BNXT_ULP_CLASS_HID_351e4 = 0x351e4, - BNXT_ULP_CLASS_HID_3dae4 = 0x3dae4, - BNXT_ULP_CLASS_HID_22cd4 = 0x22cd4, - BNXT_ULP_CLASS_HID_2d9d4 = 0x2d9d4, - BNXT_ULP_CLASS_HID_342d4 = 0x342d4, - BNXT_ULP_CLASS_HID_39088 = 0x39088, + BNXT_ULP_CLASS_HID_24dec = 0x24dec, + BNXT_ULP_CLASS_HID_209d0 = 0x209d0, + BNXT_ULP_CLASS_HID_2149c = 0x2149c, + BNXT_ULP_CLASS_HID_20f8c = 0x20f8c, + BNXT_ULP_CLASS_HID_25788 = 0x25788, + BNXT_ULP_CLASS_HID_2136c = 0x2136c, + BNXT_ULP_CLASS_HID_25d44 = 0x25d44, BNXT_ULP_CLASS_HID_21928 = 0x21928, - BNXT_ULP_CLASS_HID_28228 = 0x28228, - BNXT_ULP_CLASS_HID_30f28 = 0x30f28, - BNXT_ULP_CLASS_HID_3b828 = 0x3b828, - BNXT_ULP_CLASS_HID_24384 = 0x24384, - BNXT_ULP_CLASS_HID_29178 = 0x29178, - BNXT_ULP_CLASS_HID_31a78 = 0x31a78, - BNXT_ULP_CLASS_HID_38778 = 0x38778, - BNXT_ULP_CLASS_HID_25c78 = 0x25c78, - BNXT_ULP_CLASS_HID_2c978 = 0x2c978, - BNXT_ULP_CLASS_HID_3172c = 0x3172c, - BNXT_ULP_CLASS_HID_3802c = 0x3802c, - BNXT_ULP_CLASS_HID_2121c = 0x2121c, - BNXT_ULP_CLASS_HID_29f1c = 0x29f1c, - BNXT_ULP_CLASS_HID_3081c = 0x3081c, - BNXT_ULP_CLASS_HID_3b51c = 0x3b51c, - BNXT_ULP_CLASS_HID_24088 = 0x24088, - BNXT_ULP_CLASS_HID_2cd88 = 0x2cd88, - BNXT_ULP_CLASS_HID_31b7c = 0x31b7c, - BNXT_ULP_CLASS_HID_3847c = 0x3847c, + BNXT_ULP_CLASS_HID_234a8 = 0x234a8, BNXT_ULP_CLASS_HID_22fd8 = 0x22fd8, - BNXT_ULP_CLASS_HID_2d8d8 = 0x2d8d8, - BNXT_ULP_CLASS_HID_345d8 = 0x345d8, - BNXT_ULP_CLASS_HID_3938c = 0x3938c, - BNXT_ULP_CLASS_HID_2288c = 0x2288c, - BNXT_ULP_CLASS_HID_2d58c = 0x2d58c, - BNXT_ULP_CLASS_HID_35e8c = 0x35e8c, - BNXT_ULP_CLASS_HID_3cb8c = 0x3cb8c, - BNXT_ULP_CLASS_HID_25d7c = 0x25d7c, - BNXT_ULP_CLASS_HID_2c67c = 0x2c67c, - BNXT_ULP_CLASS_HID_31430 = 0x31430, - BNXT_ULP_CLASS_HID_38130 = 0x38130, - BNXT_ULP_CLASS_HID_209d0 = 0x209d0, - BNXT_ULP_CLASS_HID_2b2d0 = 0x2b2d0, - BNXT_ULP_CLASS_HID_33fd0 = 0x33fd0, - BNXT_ULP_CLASS_HID_3a8d0 = 0x3a8d0, - BNXT_ULP_CLASS_HID_214e0 = 0x214e0, - BNXT_ULP_CLASS_HID_281e0 = 0x281e0, - BNXT_ULP_CLASS_HID_30ae0 = 0x30ae0, - BNXT_ULP_CLASS_HID_3b7e0 = 0x3b7e0, - BNXT_ULP_CLASS_HID_211d4 = 0x211d4, - BNXT_ULP_CLASS_HID_29ad4 = 0x29ad4, - BNXT_ULP_CLASS_HID_307d4 = 0x307d4, - BNXT_ULP_CLASS_HID_3b0d4 = 0x3b0d4, - BNXT_ULP_CLASS_HID_20284 = 0x20284, - BNXT_ULP_CLASS_HID_28f84 = 0x28f84, - BNXT_ULP_CLASS_HID_33884 = 0x33884, - BNXT_ULP_CLASS_HID_3a584 = 0x3a584, - BNXT_ULP_CLASS_HID_22a24 = 0x22a24, - BNXT_ULP_CLASS_HID_2d724 = 0x2d724, - BNXT_ULP_CLASS_HID_34024 = 0x34024, - BNXT_ULP_CLASS_HID_3cd24 = 0x3cd24, + BNXT_ULP_CLASS_HID_23a64 = 0x23a64, + BNXT_ULP_CLASS_HID_25594 = 0x25594, + BNXT_ULP_CLASS_HID_21e44 = 0x21e44, BNXT_ULP_CLASS_HID_23974 = 0x23974, - BNXT_ULP_CLASS_HID_2a274 = 0x2a274, - BNXT_ULP_CLASS_HID_32f74 = 0x32f74, - BNXT_ULP_CLASS_HID_3d874 = 0x3d874, - BNXT_ULP_CLASS_HID_23228 = 0x23228, - BNXT_ULP_CLASS_HID_2bf28 = 0x2bf28, - BNXT_ULP_CLASS_HID_32828 = 0x32828, - BNXT_ULP_CLASS_HID_3d528 = 0x3d528, - BNXT_ULP_CLASS_HID_22718 = 0x22718, - BNXT_ULP_CLASS_HID_2d018 = 0x2d018, - BNXT_ULP_CLASS_HID_35d18 = 0x35d18, - BNXT_ULP_CLASS_HID_3c618 = 0x3c618, - BNXT_ULP_CLASS_HID_2136c = 0x2136c, - BNXT_ULP_CLASS_HID_29c6c = 0x29c6c, - BNXT_ULP_CLASS_HID_3096c = 0x3096c, - BNXT_ULP_CLASS_HID_3b26c = 0x3b26c, + BNXT_ULP_CLASS_HID_20400 = 0x20400, + BNXT_ULP_CLASS_HID_23f30 = 0x23f30, + BNXT_ULP_CLASS_HID_2593c = 0x2593c, + BNXT_ULP_CLASS_HID_214e0 = 0x214e0, + BNXT_ULP_CLASS_HID_25ef8 = 0x25ef8, + BNXT_ULP_CLASS_HID_21adc = 0x21adc, + BNXT_ULP_CLASS_HID_222d8 = 0x222d8, BNXT_ULP_CLASS_HID_25dc8 = 0x25dc8, - BNXT_ULP_CLASS_HID_2c6c8 = 0x2c6c8, - BNXT_ULP_CLASS_HID_314bc = 0x314bc, - BNXT_ULP_CLASS_HID_381bc = 0x381bc, - BNXT_ULP_CLASS_HID_256bc = 0x256bc, - BNXT_ULP_CLASS_HID_2c3bc = 0x2c3bc, - BNXT_ULP_CLASS_HID_31170 = 0x31170, - BNXT_ULP_CLASS_HID_39a70 = 0x39a70, - BNXT_ULP_CLASS_HID_24b6c = 0x24b6c, - BNXT_ULP_CLASS_HID_29920 = 0x29920, - BNXT_ULP_CLASS_HID_30220 = 0x30220, - BNXT_ULP_CLASS_HID_38f20 = 0x38f20, - BNXT_ULP_CLASS_HID_22f54 = 0x22f54, - BNXT_ULP_CLASS_HID_2d854 = 0x2d854, + BNXT_ULP_CLASS_HID_22894 = 0x22894, + BNXT_ULP_CLASS_HID_24384 = 0x24384, + BNXT_ULP_CLASS_HID_6224c = 0x6224c, + BNXT_ULP_CLASS_HID_65d7c = 0x65d7c, + BNXT_ULP_CLASS_HID_62808 = 0x62808, + BNXT_ULP_CLASS_HID_64338 = 0x64338, + BNXT_ULP_CLASS_HID_60fe8 = 0x60fe8, + BNXT_ULP_CLASS_HID_62718 = 0x62718, + BNXT_ULP_CLASS_HID_635a4 = 0x635a4, + BNXT_ULP_CLASS_HID_62cd4 = 0x62cd4, + BNXT_ULP_CLASS_HID_646a0 = 0x646a0, + BNXT_ULP_CLASS_HID_60284 = 0x60284, + BNXT_ULP_CLASS_HID_61150 = 0x61150, + BNXT_ULP_CLASS_HID_60840 = 0x60840, + BNXT_ULP_CLASS_HID_6507c = 0x6507c, + BNXT_ULP_CLASS_HID_64b6c = 0x64b6c, + BNXT_ULP_CLASS_HID_65638 = 0x65638, + BNXT_ULP_CLASS_HID_6121c = 0x6121c, + BNXT_ULP_CLASS_HID_6319c = 0x6319c, + BNXT_ULP_CLASS_HID_6288c = 0x6288c, + BNXT_ULP_CLASS_HID_63758 = 0x63758, + BNXT_ULP_CLASS_HID_62e48 = 0x62e48, + BNXT_ULP_CLASS_HID_61b38 = 0x61b38, + BNXT_ULP_CLASS_HID_63228 = 0x63228, + BNXT_ULP_CLASS_HID_600f4 = 0x600f4, + BNXT_ULP_CLASS_HID_63be4 = 0x63be4, + BNXT_ULP_CLASS_HID_655f0 = 0x655f0, + BNXT_ULP_CLASS_HID_611d4 = 0x611d4, + BNXT_ULP_CLASS_HID_65bac = 0x65bac, + BNXT_ULP_CLASS_HID_61790 = 0x61790, + BNXT_ULP_CLASS_HID_63f8c = 0x63f8c, + BNXT_ULP_CLASS_HID_656bc = 0x656bc, + BNXT_ULP_CLASS_HID_62548 = 0x62548, + BNXT_ULP_CLASS_HID_65c78 = 0x65c78, + BNXT_ULP_CLASS_HID_35f98 = 0x35f98, + BNXT_ULP_CLASS_HID_31b7c = 0x31b7c, BNXT_ULP_CLASS_HID_34554 = 0x34554, - BNXT_ULP_CLASS_HID_39308 = 0x39308, - BNXT_ULP_CLASS_HID_23a64 = 0x23a64, - BNXT_ULP_CLASS_HID_2a764 = 0x2a764, - BNXT_ULP_CLASS_HID_35064 = 0x35064, - BNXT_ULP_CLASS_HID_3dd64 = 0x3dd64, - BNXT_ULP_CLASS_HID_23758 = 0x23758, - BNXT_ULP_CLASS_HID_2a058 = 0x2a058, - BNXT_ULP_CLASS_HID_32d58 = 0x32d58, - BNXT_ULP_CLASS_HID_3d658 = 0x3d658, - BNXT_ULP_CLASS_HID_22808 = 0x22808, - BNXT_ULP_CLASS_HID_2d508 = 0x2d508, - BNXT_ULP_CLASS_HID_35e08 = 0x35e08, - BNXT_ULP_CLASS_HID_3cb08 = 0x3cb08, - BNXT_ULP_CLASS_HID_2149c = 0x2149c, - BNXT_ULP_CLASS_HID_2819c = 0x2819c, - BNXT_ULP_CLASS_HID_30a9c = 0x30a9c, - BNXT_ULP_CLASS_HID_3b79c = 0x3b79c, - BNXT_ULP_CLASS_HID_25ef8 = 0x25ef8, - BNXT_ULP_CLASS_HID_2cbf8 = 0x2cbf8, - BNXT_ULP_CLASS_HID_319ac = 0x319ac, - BNXT_ULP_CLASS_HID_382ac = 0x382ac, - BNXT_ULP_CLASS_HID_25bac = 0x25bac, - BNXT_ULP_CLASS_HID_2c4ac = 0x2c4ac, - BNXT_ULP_CLASS_HID_31260 = 0x31260, - BNXT_ULP_CLASS_HID_39f60 = 0x39f60, - BNXT_ULP_CLASS_HID_21150 = 0x21150, - BNXT_ULP_CLASS_HID_29a50 = 0x29a50, - BNXT_ULP_CLASS_HID_30750 = 0x30750, - BNXT_ULP_CLASS_HID_3b050 = 0x3b050, - BNXT_ULP_CLASS_HID_238f0 = 0x238f0, - BNXT_ULP_CLASS_HID_2a5f0 = 0x2a5f0, + BNXT_ULP_CLASS_HID_30138 = 0x30138, + BNXT_ULP_CLASS_HID_32934 = 0x32934, + BNXT_ULP_CLASS_HID_34024 = 0x34024, BNXT_ULP_CLASS_HID_32ef0 = 0x32ef0, - BNXT_ULP_CLASS_HID_3dbf0 = 0x3dbf0, - BNXT_ULP_CLASS_HID_20400 = 0x20400, - BNXT_ULP_CLASS_HID_2b100 = 0x2b100, - BNXT_ULP_CLASS_HID_33a00 = 0x33a00, - BNXT_ULP_CLASS_HID_3a700 = 0x3a700, - BNXT_ULP_CLASS_HID_200f4 = 0x200f4, - BNXT_ULP_CLASS_HID_28df4 = 0x28df4, - BNXT_ULP_CLASS_HID_336f4 = 0x336f4, - BNXT_ULP_CLASS_HID_3a3f4 = 0x3a3f4, - BNXT_ULP_CLASS_HID_235a4 = 0x235a4, - BNXT_ULP_CLASS_HID_2bea4 = 0x2bea4, - BNXT_ULP_CLASS_HID_32ba4 = 0x32ba4, - BNXT_ULP_CLASS_HID_3d4a4 = 0x3d4a4, - BNXT_ULP_CLASS_HID_25d44 = 0x25d44, - BNXT_ULP_CLASS_HID_2c644 = 0x2c644, + BNXT_ULP_CLASS_HID_349e0 = 0x349e0, + BNXT_ULP_CLASS_HID_304a0 = 0x304a0, + BNXT_ULP_CLASS_HID_33fd0 = 0x33fd0, + BNXT_ULP_CLASS_HID_30a9c = 0x30a9c, + BNXT_ULP_CLASS_HID_3258c = 0x3258c, + BNXT_ULP_CLASS_HID_34d88 = 0x34d88, + BNXT_ULP_CLASS_HID_3096c = 0x3096c, BNXT_ULP_CLASS_HID_31438 = 0x31438, - BNXT_ULP_CLASS_HID_38138 = 0x38138, - BNXT_ULP_CLASS_HID_22894 = 0x22894, - BNXT_ULP_CLASS_HID_2d594 = 0x2d594, + BNXT_ULP_CLASS_HID_30f28 = 0x30f28, + BNXT_ULP_CLASS_HID_32aa8 = 0x32aa8, + BNXT_ULP_CLASS_HID_345d8 = 0x345d8, + BNXT_ULP_CLASS_HID_35064 = 0x35064, + BNXT_ULP_CLASS_HID_34b94 = 0x34b94, + BNXT_ULP_CLASS_HID_33444 = 0x33444, + BNXT_ULP_CLASS_HID_32f74 = 0x32f74, + BNXT_ULP_CLASS_HID_33a00 = 0x33a00, + BNXT_ULP_CLASS_HID_35530 = 0x35530, + BNXT_ULP_CLASS_HID_313f0 = 0x313f0, + BNXT_ULP_CLASS_HID_30ae0 = 0x30ae0, + BNXT_ULP_CLASS_HID_319ac = 0x319ac, + BNXT_ULP_CLASS_HID_330dc = 0x330dc, + BNXT_ULP_CLASS_HID_358d8 = 0x358d8, + BNXT_ULP_CLASS_HID_314bc = 0x314bc, BNXT_ULP_CLASS_HID_35e94 = 0x35e94, - BNXT_ULP_CLASS_HID_3cb94 = 0x3cb94, - BNXT_ULP_CLASS_HID_22548 = 0x22548, - BNXT_ULP_CLASS_HID_2ae48 = 0x2ae48, - BNXT_ULP_CLASS_HID_35b48 = 0x35b48, - BNXT_ULP_CLASS_HID_3c448 = 0x3c448, - BNXT_ULP_CLASS_HID_25638 = 0x25638, - BNXT_ULP_CLASS_HID_2c338 = 0x2c338, - BNXT_ULP_CLASS_HID_310ec = 0x310ec, - BNXT_ULP_CLASS_HID_39dec = 0x39dec, - BNXT_ULP_CLASS_HID_22998 = 0x22998, + BNXT_ULP_CLASS_HID_31a78 = 0x31a78, + BNXT_ULP_CLASS_HID_7584c = 0x7584c, + BNXT_ULP_CLASS_HID_71430 = 0x71430, + BNXT_ULP_CLASS_HID_75e08 = 0x75e08, + BNXT_ULP_CLASS_HID_71dec = 0x71dec, + BNXT_ULP_CLASS_HID_725e8 = 0x725e8, + BNXT_ULP_CLASS_HID_75d18 = 0x75d18, + BNXT_ULP_CLASS_HID_72ba4 = 0x72ba4, + BNXT_ULP_CLASS_HID_742d4 = 0x742d4, + BNXT_ULP_CLASS_HID_70194 = 0x70194, + BNXT_ULP_CLASS_HID_73884 = 0x73884, + BNXT_ULP_CLASS_HID_70750 = 0x70750, + BNXT_ULP_CLASS_HID_73e40 = 0x73e40, + BNXT_ULP_CLASS_HID_7467c = 0x7467c, + BNXT_ULP_CLASS_HID_70220 = 0x70220, + BNXT_ULP_CLASS_HID_710ec = 0x710ec, + BNXT_ULP_CLASS_HID_7081c = 0x7081c, + BNXT_ULP_CLASS_HID_7279c = 0x7279c, + BNXT_ULP_CLASS_HID_75e8c = 0x75e8c, + BNXT_ULP_CLASS_HID_72d58 = 0x72d58, + BNXT_ULP_CLASS_HID_74448 = 0x74448, + BNXT_ULP_CLASS_HID_73138 = 0x73138, + BNXT_ULP_CLASS_HID_72828 = 0x72828, + BNXT_ULP_CLASS_HID_736f4 = 0x736f4, + BNXT_ULP_CLASS_HID_751e4 = 0x751e4, + BNXT_ULP_CLASS_HID_74bf0 = 0x74bf0, + BNXT_ULP_CLASS_HID_707d4 = 0x707d4, + BNXT_ULP_CLASS_HID_71260 = 0x71260, + BNXT_ULP_CLASS_HID_70d90 = 0x70d90, + BNXT_ULP_CLASS_HID_7558c = 0x7558c, + BNXT_ULP_CLASS_HID_71170 = 0x71170, + BNXT_ULP_CLASS_HID_75b48 = 0x75b48, + BNXT_ULP_CLASS_HID_7172c = 0x7172c, BNXT_ULP_CLASS_HID_2d298 = 0x2d298, - BNXT_ULP_CLASS_HID_35f98 = 0x35f98, - BNXT_ULP_CLASS_HID_3c898 = 0x3c898, - BNXT_ULP_CLASS_HID_234a8 = 0x234a8, - BNXT_ULP_CLASS_HID_2a1a8 = 0x2a1a8, - BNXT_ULP_CLASS_HID_32aa8 = 0x32aa8, - BNXT_ULP_CLASS_HID_3d7a8 = 0x3d7a8, - BNXT_ULP_CLASS_HID_2319c = 0x2319c, - BNXT_ULP_CLASS_HID_2ba9c = 0x2ba9c, - BNXT_ULP_CLASS_HID_3279c = 0x3279c, - BNXT_ULP_CLASS_HID_3d09c = 0x3d09c, - BNXT_ULP_CLASS_HID_2224c = 0x2224c, - BNXT_ULP_CLASS_HID_2af4c = 0x2af4c, - BNXT_ULP_CLASS_HID_3584c = 0x3584c, - BNXT_ULP_CLASS_HID_3c54c = 0x3c54c, - BNXT_ULP_CLASS_HID_24dec = 0x24dec, + BNXT_ULP_CLASS_HID_2cd88 = 0x2cd88, + BNXT_ULP_CLASS_HID_2d854 = 0x2d854, + BNXT_ULP_CLASS_HID_29438 = 0x29438, + BNXT_ULP_CLASS_HID_2bc34 = 0x2bc34, + BNXT_ULP_CLASS_HID_2d724 = 0x2d724, + BNXT_ULP_CLASS_HID_2a5f0 = 0x2a5f0, + BNXT_ULP_CLASS_HID_2dce0 = 0x2dce0, BNXT_ULP_CLASS_HID_29ba0 = 0x29ba0, - BNXT_ULP_CLASS_HID_304a0 = 0x304a0, - BNXT_ULP_CLASS_HID_3b1a0 = 0x3b1a0, - BNXT_ULP_CLASS_HID_2593c = 0x2593c, + BNXT_ULP_CLASS_HID_2b2d0 = 0x2b2d0, + BNXT_ULP_CLASS_HID_2819c = 0x2819c, + BNXT_ULP_CLASS_HID_2b88c = 0x2b88c, + BNXT_ULP_CLASS_HID_2c088 = 0x2c088, + BNXT_ULP_CLASS_HID_29c6c = 0x29c6c, + BNXT_ULP_CLASS_HID_2c644 = 0x2c644, + BNXT_ULP_CLASS_HID_28228 = 0x28228, + BNXT_ULP_CLASS_HID_2a1a8 = 0x2a1a8, + BNXT_ULP_CLASS_HID_2d8d8 = 0x2d8d8, + BNXT_ULP_CLASS_HID_2a764 = 0x2a764, + BNXT_ULP_CLASS_HID_2de94 = 0x2de94, + BNXT_ULP_CLASS_HID_28b44 = 0x28b44, + BNXT_ULP_CLASS_HID_2a274 = 0x2a274, + BNXT_ULP_CLASS_HID_2b100 = 0x2b100, + BNXT_ULP_CLASS_HID_2a830 = 0x2a830, BNXT_ULP_CLASS_HID_2c23c = 0x2c23c, - BNXT_ULP_CLASS_HID_313f0 = 0x313f0, - BNXT_ULP_CLASS_HID_39cf0 = 0x39cf0, - BNXT_ULP_CLASS_HID_255f0 = 0x255f0, - BNXT_ULP_CLASS_HID_2def0 = 0x2def0, - BNXT_ULP_CLASS_HID_34bf0 = 0x34bf0, - BNXT_ULP_CLASS_HID_399a4 = 0x399a4, - BNXT_ULP_CLASS_HID_246a0 = 0x246a0, - BNXT_ULP_CLASS_HID_29494 = 0x29494, - BNXT_ULP_CLASS_HID_30194 = 0x30194, - BNXT_ULP_CLASS_HID_38a94 = 0x38a94, - BNXT_ULP_CLASS_HID_23334 = 0x23334, - BNXT_ULP_CLASS_HID_2bc34 = 0x2bc34, - BNXT_ULP_CLASS_HID_32934 = 0x32934, + BNXT_ULP_CLASS_HID_281e0 = 0x281e0, + BNXT_ULP_CLASS_HID_2cbf8 = 0x2cbf8, + BNXT_ULP_CLASS_HID_287dc = 0x287dc, + BNXT_ULP_CLASS_HID_2afd8 = 0x2afd8, + BNXT_ULP_CLASS_HID_2c6c8 = 0x2c6c8, + BNXT_ULP_CLASS_HID_2d594 = 0x2d594, + BNXT_ULP_CLASS_HID_29178 = 0x29178, + BNXT_ULP_CLASS_HID_6af4c = 0x6af4c, + BNXT_ULP_CLASS_HID_6c67c = 0x6c67c, + BNXT_ULP_CLASS_HID_6d508 = 0x6d508, + BNXT_ULP_CLASS_HID_690ec = 0x690ec, + BNXT_ULP_CLASS_HID_6b8e8 = 0x6b8e8, + BNXT_ULP_CLASS_HID_6d018 = 0x6d018, + BNXT_ULP_CLASS_HID_6bea4 = 0x6bea4, + BNXT_ULP_CLASS_HID_6d9d4 = 0x6d9d4, + BNXT_ULP_CLASS_HID_69494 = 0x69494, + BNXT_ULP_CLASS_HID_68f84 = 0x68f84, + BNXT_ULP_CLASS_HID_69a50 = 0x69a50, + BNXT_ULP_CLASS_HID_6b540 = 0x6b540, + BNXT_ULP_CLASS_HID_6dd7c = 0x6dd7c, + BNXT_ULP_CLASS_HID_69920 = 0x69920, + BNXT_ULP_CLASS_HID_6c338 = 0x6c338, + BNXT_ULP_CLASS_HID_69f1c = 0x69f1c, + BNXT_ULP_CLASS_HID_6ba9c = 0x6ba9c, + BNXT_ULP_CLASS_HID_6d58c = 0x6d58c, + BNXT_ULP_CLASS_HID_6a058 = 0x6a058, + BNXT_ULP_CLASS_HID_6db48 = 0x6db48, + BNXT_ULP_CLASS_HID_68438 = 0x68438, + BNXT_ULP_CLASS_HID_6bf28 = 0x6bf28, + BNXT_ULP_CLASS_HID_68df4 = 0x68df4, + BNXT_ULP_CLASS_HID_6a4e4 = 0x6a4e4, + BNXT_ULP_CLASS_HID_6def0 = 0x6def0, + BNXT_ULP_CLASS_HID_69ad4 = 0x69ad4, + BNXT_ULP_CLASS_HID_6c4ac = 0x6c4ac, + BNXT_ULP_CLASS_HID_68090 = 0x68090, + BNXT_ULP_CLASS_HID_6a88c = 0x6a88c, + BNXT_ULP_CLASS_HID_6c3bc = 0x6c3bc, + BNXT_ULP_CLASS_HID_6ae48 = 0x6ae48, + BNXT_ULP_CLASS_HID_6c978 = 0x6c978, + BNXT_ULP_CLASS_HID_3c898 = 0x3c898, + BNXT_ULP_CLASS_HID_3847c = 0x3847c, + BNXT_ULP_CLASS_HID_39308 = 0x39308, + BNXT_ULP_CLASS_HID_38a38 = 0x38a38, BNXT_ULP_CLASS_HID_3d234 = 0x3d234, - BNXT_ULP_CLASS_HID_21e44 = 0x21e44, - BNXT_ULP_CLASS_HID_28b44 = 0x28b44, - BNXT_ULP_CLASS_HID_33444 = 0x33444, - BNXT_ULP_CLASS_HID_3a144 = 0x3a144, - BNXT_ULP_CLASS_HID_21b38 = 0x21b38, - BNXT_ULP_CLASS_HID_28438 = 0x28438, - BNXT_ULP_CLASS_HID_33138 = 0x33138, - BNXT_ULP_CLASS_HID_3ba38 = 0x3ba38, - BNXT_ULP_CLASS_HID_20fe8 = 0x20fe8, - BNXT_ULP_CLASS_HID_2b8e8 = 0x2b8e8, - BNXT_ULP_CLASS_HID_325e8 = 0x325e8, - BNXT_ULP_CLASS_HID_3aee8 = 0x3aee8, - BNXT_ULP_CLASS_HID_25788 = 0x25788, - BNXT_ULP_CLASS_HID_2c088 = 0x2c088, - BNXT_ULP_CLASS_HID_34d88 = 0x34d88, + BNXT_ULP_CLASS_HID_3cd24 = 0x3cd24, + BNXT_ULP_CLASS_HID_3dbf0 = 0x3dbf0, + BNXT_ULP_CLASS_HID_397d4 = 0x397d4, + BNXT_ULP_CLASS_HID_3b1a0 = 0x3b1a0, + BNXT_ULP_CLASS_HID_3a8d0 = 0x3a8d0, + BNXT_ULP_CLASS_HID_3b79c = 0x3b79c, + BNXT_ULP_CLASS_HID_3ae8c = 0x3ae8c, BNXT_ULP_CLASS_HID_39b7c = 0x39b7c, - BNXT_ULP_CLASS_HID_222d8 = 0x222d8, - BNXT_ULP_CLASS_HID_2afd8 = 0x2afd8, - BNXT_ULP_CLASS_HID_358d8 = 0x358d8, + BNXT_ULP_CLASS_HID_3b26c = 0x3b26c, + BNXT_ULP_CLASS_HID_38138 = 0x38138, + BNXT_ULP_CLASS_HID_3b828 = 0x3b828, + BNXT_ULP_CLASS_HID_3d7a8 = 0x3d7a8, + BNXT_ULP_CLASS_HID_3938c = 0x3938c, + BNXT_ULP_CLASS_HID_3dd64 = 0x3dd64, + BNXT_ULP_CLASS_HID_39948 = 0x39948, + BNXT_ULP_CLASS_HID_3a144 = 0x3a144, + BNXT_ULP_CLASS_HID_3d874 = 0x3d874, + BNXT_ULP_CLASS_HID_3a700 = 0x3a700, + BNXT_ULP_CLASS_HID_3de30 = 0x3de30, + BNXT_ULP_CLASS_HID_39cf0 = 0x39cf0, + BNXT_ULP_CLASS_HID_3b7e0 = 0x3b7e0, + BNXT_ULP_CLASS_HID_382ac = 0x382ac, + BNXT_ULP_CLASS_HID_3bddc = 0x3bddc, BNXT_ULP_CLASS_HID_3c5d8 = 0x3c5d8, - BNXT_ULP_CLASS_HID_23f8c = 0x23f8c, - BNXT_ULP_CLASS_HID_2a88c = 0x2a88c, - BNXT_ULP_CLASS_HID_3558c = 0x3558c, - BNXT_ULP_CLASS_HID_3de8c = 0x3de8c, - BNXT_ULP_CLASS_HID_2507c = 0x2507c, - BNXT_ULP_CLASS_HID_2dd7c = 0x2dd7c, - BNXT_ULP_CLASS_HID_3467c = 0x3467c, - BNXT_ULP_CLASS_HID_39430 = 0x39430, + BNXT_ULP_CLASS_HID_381bc = 0x381bc, + BNXT_ULP_CLASS_HID_3cb94 = 0x3cb94, + BNXT_ULP_CLASS_HID_38778 = 0x38778, + BNXT_ULP_CLASS_HID_7c54c = 0x7c54c, + BNXT_ULP_CLASS_HID_78130 = 0x78130, + BNXT_ULP_CLASS_HID_7cb08 = 0x7cb08, + BNXT_ULP_CLASS_HID_786ec = 0x786ec, + BNXT_ULP_CLASS_HID_7aee8 = 0x7aee8, + BNXT_ULP_CLASS_HID_7c618 = 0x7c618, + BNXT_ULP_CLASS_HID_7d4a4 = 0x7d4a4, + BNXT_ULP_CLASS_HID_79088 = 0x79088, + BNXT_ULP_CLASS_HID_78a94 = 0x78a94, + BNXT_ULP_CLASS_HID_7a584 = 0x7a584, + BNXT_ULP_CLASS_HID_7b050 = 0x7b050, + BNXT_ULP_CLASS_HID_7ab40 = 0x7ab40, + BNXT_ULP_CLASS_HID_79430 = 0x79430, + BNXT_ULP_CLASS_HID_78f20 = 0x78f20, + BNXT_ULP_CLASS_HID_79dec = 0x79dec, + BNXT_ULP_CLASS_HID_7b51c = 0x7b51c, + BNXT_ULP_CLASS_HID_7d09c = 0x7d09c, + BNXT_ULP_CLASS_HID_7cb8c = 0x7cb8c, + BNXT_ULP_CLASS_HID_7d658 = 0x7d658, + BNXT_ULP_CLASS_HID_7923c = 0x7923c, + BNXT_ULP_CLASS_HID_7ba38 = 0x7ba38, + BNXT_ULP_CLASS_HID_7d528 = 0x7d528, + BNXT_ULP_CLASS_HID_7a3f4 = 0x7a3f4, + BNXT_ULP_CLASS_HID_7dae4 = 0x7dae4, + BNXT_ULP_CLASS_HID_799a4 = 0x799a4, + BNXT_ULP_CLASS_HID_7b0d4 = 0x7b0d4, + BNXT_ULP_CLASS_HID_79f60 = 0x79f60, + BNXT_ULP_CLASS_HID_7b690 = 0x7b690, + BNXT_ULP_CLASS_HID_7de8c = 0x7de8c, + BNXT_ULP_CLASS_HID_79a70 = 0x79a70, + BNXT_ULP_CLASS_HID_7c448 = 0x7c448, + BNXT_ULP_CLASS_HID_7802c = 0x7802c, + BNXT_ULP_CLASS_HID_86a0 = 0x86a0, + BNXT_ULP_CLASS_HID_a1b0 = 0xa1b0, + BNXT_ULP_CLASS_HID_8c6c = 0x8c6c, + BNXT_ULP_CLASS_HID_a77c = 0xa77c, + BNXT_ULP_CLASS_HID_900c = 0x900c, + BNXT_ULP_CLASS_HID_8b1c = 0x8b1c, + BNXT_ULP_CLASS_HID_99c8 = 0x99c8, + BNXT_ULP_CLASS_HID_b0d8 = 0xb0d8, + BNXT_ULP_CLASS_HID_aad4 = 0xaad4, + BNXT_ULP_CLASS_HID_c224 = 0xc224, + BNXT_ULP_CLASS_HID_d090 = 0xd090, + BNXT_ULP_CLASS_HID_cbe0 = 0xcbe0, + BNXT_ULP_CLASS_HID_b4b0 = 0xb4b0, + BNXT_ULP_CLASS_HID_af80 = 0xaf80, + BNXT_ULP_CLASS_HID_ba7c = 0xba7c, + BNXT_ULP_CLASS_HID_d54c = 0xd54c, + BNXT_ULP_CLASS_HID_48374 = 0x48374, + BNXT_ULP_CLASS_HID_4ba44 = 0x4ba44, + BNXT_ULP_CLASS_HID_48930 = 0x48930, + BNXT_ULP_CLASS_HID_4a000 = 0x4a000, + BNXT_ULP_CLASS_HID_4c80c = 0x4c80c, + BNXT_ULP_CLASS_HID_48420 = 0x48420, + BNXT_ULP_CLASS_HID_4929c = 0x4929c, + BNXT_ULP_CLASS_HID_48dec = 0x48dec, + BNXT_ULP_CLASS_HID_4a798 = 0x4a798, + BNXT_ULP_CLASS_HID_4dee8 = 0x4dee8, + BNXT_ULP_CLASS_HID_4ada4 = 0x4ada4, + BNXT_ULP_CLASS_HID_4c4b4 = 0x4c4b4, + BNXT_ULP_CLASS_HID_4b144 = 0x4b144, + BNXT_ULP_CLASS_HID_4a854 = 0x4a854, + BNXT_ULP_CLASS_HID_4b700 = 0x4b700, + BNXT_ULP_CLASS_HID_4ae10 = 0x4ae10, + BNXT_ULP_CLASS_HID_1bca0 = 0x1bca0, + BNXT_ULP_CLASS_HID_1d7b0 = 0x1d7b0, + BNXT_ULP_CLASS_HID_1a26c = 0x1a26c, + BNXT_ULP_CLASS_HID_1dd7c = 0x1dd7c, + BNXT_ULP_CLASS_HID_1860c = 0x1860c, + BNXT_ULP_CLASS_HID_1a11c = 0x1a11c, + BNXT_ULP_CLASS_HID_18fc8 = 0x18fc8, + BNXT_ULP_CLASS_HID_1a6d8 = 0x1a6d8, + BNXT_ULP_CLASS_HID_1c0d4 = 0x1c0d4, + BNXT_ULP_CLASS_HID_19ce8 = 0x19ce8, + BNXT_ULP_CLASS_HID_1c690 = 0x1c690, + BNXT_ULP_CLASS_HID_182b4 = 0x182b4, + BNXT_ULP_CLASS_HID_1aab0 = 0x1aab0, + BNXT_ULP_CLASS_HID_1c580 = 0x1c580, + BNXT_ULP_CLASS_HID_1d07c = 0x1d07c, + BNXT_ULP_CLASS_HID_1cb4c = 0x1cb4c, + BNXT_ULP_CLASS_HID_5b974 = 0x5b974, + BNXT_ULP_CLASS_HID_5d044 = 0x5d044, + BNXT_ULP_CLASS_HID_5bf30 = 0x5bf30, + BNXT_ULP_CLASS_HID_5d600 = 0x5d600, + BNXT_ULP_CLASS_HID_582d0 = 0x582d0, + BNXT_ULP_CLASS_HID_5ba20 = 0x5ba20, + BNXT_ULP_CLASS_HID_5889c = 0x5889c, + BNXT_ULP_CLASS_HID_5a3ec = 0x5a3ec, + BNXT_ULP_CLASS_HID_5dd98 = 0x5dd98, + BNXT_ULP_CLASS_HID_599bc = 0x599bc, + BNXT_ULP_CLASS_HID_5c3a4 = 0x5c3a4, + BNXT_ULP_CLASS_HID_59f78 = 0x59f78, + BNXT_ULP_CLASS_HID_5a744 = 0x5a744, + BNXT_ULP_CLASS_HID_5de54 = 0x5de54, + BNXT_ULP_CLASS_HID_5ad00 = 0x5ad00, + BNXT_ULP_CLASS_HID_5c410 = 0x5c410, + BNXT_ULP_CLASS_HID_cd20 = 0xcd20, + BNXT_ULP_CLASS_HID_e430 = 0xe430, + BNXT_ULP_CLASS_HID_f2ec = 0xf2ec, + BNXT_ULP_CLASS_HID_edfc = 0xedfc, + BNXT_ULP_CLASS_HID_d68c = 0xd68c, + BNXT_ULP_CLASS_HID_f19c = 0xf19c, + BNXT_ULP_CLASS_HID_dc48 = 0xdc48, + BNXT_ULP_CLASS_HID_f758 = 0xf758, + BNXT_ULP_CLASS_HID_d154 = 0xd154, + BNXT_ULP_CLASS_HID_c8a4 = 0xc8a4, + BNXT_ULP_CLASS_HID_d710 = 0xd710, + BNXT_ULP_CLASS_HID_d334 = 0xd334, + BNXT_ULP_CLASS_HID_fb30 = 0xfb30, + BNXT_ULP_CLASS_HID_d200 = 0xd200, + BNXT_ULP_CLASS_HID_e0fc = 0xe0fc, + BNXT_ULP_CLASS_HID_dbcc = 0xdbcc, + BNXT_ULP_CLASS_HID_4c9f4 = 0x4c9f4, + BNXT_ULP_CLASS_HID_4e0c4 = 0x4e0c4, + BNXT_ULP_CLASS_HID_4cfb0 = 0x4cfb0, + BNXT_ULP_CLASS_HID_4e680 = 0x4e680, + BNXT_ULP_CLASS_HID_4d350 = 0x4d350, + BNXT_ULP_CLASS_HID_4caa0 = 0x4caa0, + BNXT_ULP_CLASS_HID_4d91c = 0x4d91c, + BNXT_ULP_CLASS_HID_4f06c = 0x4f06c, + BNXT_ULP_CLASS_HID_4ea18 = 0x4ea18, + BNXT_ULP_CLASS_HID_4c568 = 0x4c568, + BNXT_ULP_CLASS_HID_4d024 = 0x4d024, + BNXT_ULP_CLASS_HID_4cb34 = 0x4cb34, + BNXT_ULP_CLASS_HID_4f7c4 = 0x4f7c4, + BNXT_ULP_CLASS_HID_4eed4 = 0x4eed4, + BNXT_ULP_CLASS_HID_4fd80 = 0x4fd80, + BNXT_ULP_CLASS_HID_4d490 = 0x4d490, + BNXT_ULP_CLASS_HID_1e320 = 0x1e320, + BNXT_ULP_CLASS_HID_1da30 = 0x1da30, + BNXT_ULP_CLASS_HID_1e8ec = 0x1e8ec, + BNXT_ULP_CLASS_HID_1c3fc = 0x1c3fc, + BNXT_ULP_CLASS_HID_1cc8c = 0x1cc8c, + BNXT_ULP_CLASS_HID_1e79c = 0x1e79c, + BNXT_ULP_CLASS_HID_1f248 = 0x1f248, + BNXT_ULP_CLASS_HID_1ed58 = 0x1ed58, + BNXT_ULP_CLASS_HID_1c754 = 0x1c754, + BNXT_ULP_CLASS_HID_1c368 = 0x1c368, + BNXT_ULP_CLASS_HID_1cd10 = 0x1cd10, + BNXT_ULP_CLASS_HID_1c934 = 0x1c934, + BNXT_ULP_CLASS_HID_1d130 = 0x1d130, + BNXT_ULP_CLASS_HID_1c800 = 0x1c800, + BNXT_ULP_CLASS_HID_1d6fc = 0x1d6fc, + BNXT_ULP_CLASS_HID_1d290 = 0x1d290, + BNXT_ULP_CLASS_HID_5fff4 = 0x5fff4, + BNXT_ULP_CLASS_HID_5d6c4 = 0x5d6c4, + BNXT_ULP_CLASS_HID_5e5b0 = 0x5e5b0, + BNXT_ULP_CLASS_HID_5dc80 = 0x5dc80, + BNXT_ULP_CLASS_HID_5c950 = 0x5c950, + BNXT_ULP_CLASS_HID_5e0a0 = 0x5e0a0, + BNXT_ULP_CLASS_HID_5cf1c = 0x5cf1c, + BNXT_ULP_CLASS_HID_5e66c = 0x5e66c, + BNXT_ULP_CLASS_HID_5c018 = 0x5c018, + BNXT_ULP_CLASS_HID_5dc3c = 0x5dc3c, + BNXT_ULP_CLASS_HID_5c624 = 0x5c624, + BNXT_ULP_CLASS_HID_5c5f8 = 0x5c5f8, + BNXT_ULP_CLASS_HID_5edc4 = 0x5edc4, + BNXT_ULP_CLASS_HID_5c4d4 = 0x5c4d4, + BNXT_ULP_CLASS_HID_5d380 = 0x5d380, + BNXT_ULP_CLASS_HID_5ca90 = 0x5ca90, + BNXT_ULP_CLASS_HID_abe0 = 0xabe0, + BNXT_ULP_CLASS_HID_a2f0 = 0xa2f0, + BNXT_ULP_CLASS_HID_b1ac = 0xb1ac, + BNXT_ULP_CLASS_HID_a8bc = 0xa8bc, + BNXT_ULP_CLASS_HID_b54c = 0xb54c, + BNXT_ULP_CLASS_HID_ac5c = 0xac5c, + BNXT_ULP_CLASS_HID_bb08 = 0xbb08, + BNXT_ULP_CLASS_HID_b218 = 0xb218, + BNXT_ULP_CLASS_HID_ac14 = 0xac14, + BNXT_ULP_CLASS_HID_e764 = 0xe764, + BNXT_ULP_CLASS_HID_f5d0 = 0xf5d0, + BNXT_ULP_CLASS_HID_b1f4 = 0xb1f4, + BNXT_ULP_CLASS_HID_b9f0 = 0xb9f0, + BNXT_ULP_CLASS_HID_f0c0 = 0xf0c0, + BNXT_ULP_CLASS_HID_bfbc = 0xbfbc, + BNXT_ULP_CLASS_HID_f68c = 0xf68c, + BNXT_ULP_CLASS_HID_4a4b4 = 0x4a4b4, + BNXT_ULP_CLASS_HID_4bf84 = 0x4bf84, + BNXT_ULP_CLASS_HID_4aa70 = 0x4aa70, + BNXT_ULP_CLASS_HID_4a540 = 0x4a540, + BNXT_ULP_CLASS_HID_4ed4c = 0x4ed4c, + BNXT_ULP_CLASS_HID_4a960 = 0x4a960, + BNXT_ULP_CLASS_HID_4b7dc = 0x4b7dc, + BNXT_ULP_CLASS_HID_4af2c = 0x4af2c, + BNXT_ULP_CLASS_HID_4a8d8 = 0x4a8d8, + BNXT_ULP_CLASS_HID_4e028 = 0x4e028, + BNXT_ULP_CLASS_HID_4aee4 = 0x4aee4, + BNXT_ULP_CLASS_HID_4e9f4 = 0x4e9f4, + BNXT_ULP_CLASS_HID_4b284 = 0x4b284, + BNXT_ULP_CLASS_HID_4ad94 = 0x4ad94, + BNXT_ULP_CLASS_HID_4b840 = 0x4b840, + BNXT_ULP_CLASS_HID_4f350 = 0x4f350, + BNXT_ULP_CLASS_HID_1a1e0 = 0x1a1e0, + BNXT_ULP_CLASS_HID_1f8f0 = 0x1f8f0, + BNXT_ULP_CLASS_HID_1a7ac = 0x1a7ac, + BNXT_ULP_CLASS_HID_1febc = 0x1febc, + BNXT_ULP_CLASS_HID_1ab4c = 0x1ab4c, + BNXT_ULP_CLASS_HID_1a25c = 0x1a25c, + BNXT_ULP_CLASS_HID_1b108 = 0x1b108, + BNXT_ULP_CLASS_HID_1a818 = 0x1a818, + BNXT_ULP_CLASS_HID_1e214 = 0x1e214, + BNXT_ULP_CLASS_HID_1be28 = 0x1be28, + BNXT_ULP_CLASS_HID_1ebd0 = 0x1ebd0, + BNXT_ULP_CLASS_HID_1a7f4 = 0x1a7f4, + BNXT_ULP_CLASS_HID_1aff0 = 0x1aff0, + BNXT_ULP_CLASS_HID_1e6c0 = 0x1e6c0, + BNXT_ULP_CLASS_HID_1f5bc = 0x1f5bc, + BNXT_ULP_CLASS_HID_1b150 = 0x1b150, + BNXT_ULP_CLASS_HID_5bab4 = 0x5bab4, + BNXT_ULP_CLASS_HID_5f584 = 0x5f584, + BNXT_ULP_CLASS_HID_5a070 = 0x5a070, + BNXT_ULP_CLASS_HID_5fb40 = 0x5fb40, + BNXT_ULP_CLASS_HID_5a410 = 0x5a410, + BNXT_ULP_CLASS_HID_5bf60 = 0x5bf60, + BNXT_ULP_CLASS_HID_5addc = 0x5addc, + BNXT_ULP_CLASS_HID_5a52c = 0x5a52c, + BNXT_ULP_CLASS_HID_5fed8 = 0x5fed8, + BNXT_ULP_CLASS_HID_5bafc = 0x5bafc, + BNXT_ULP_CLASS_HID_5e4e4 = 0x5e4e4, + BNXT_ULP_CLASS_HID_5a0b8 = 0x5a0b8, + BNXT_ULP_CLASS_HID_5a884 = 0x5a884, + BNXT_ULP_CLASS_HID_5e394 = 0x5e394, + BNXT_ULP_CLASS_HID_5ae40 = 0x5ae40, + BNXT_ULP_CLASS_HID_5e950 = 0x5e950, + BNXT_ULP_CLASS_HID_ee60 = 0xee60, + BNXT_ULP_CLASS_HID_e970 = 0xe970, + BNXT_ULP_CLASS_HID_f42c = 0xf42c, + BNXT_ULP_CLASS_HID_ef3c = 0xef3c, + BNXT_ULP_CLASS_HID_fbcc = 0xfbcc, + BNXT_ULP_CLASS_HID_f2dc = 0xf2dc, + BNXT_ULP_CLASS_HID_e188 = 0xe188, + BNXT_ULP_CLASS_HID_f898 = 0xf898, + BNXT_ULP_CLASS_HID_f294 = 0xf294, + BNXT_ULP_CLASS_HID_ede4 = 0xede4, + BNXT_ULP_CLASS_HID_f850 = 0xf850, + BNXT_ULP_CLASS_HID_f474 = 0xf474, + BNXT_ULP_CLASS_HID_fc70 = 0xfc70, + BNXT_ULP_CLASS_HID_f740 = 0xf740, + BNXT_ULP_CLASS_HID_e23c = 0xe23c, + BNXT_ULP_CLASS_HID_fd0c = 0xfd0c, + BNXT_ULP_CLASS_HID_4eb34 = 0x4eb34, + BNXT_ULP_CLASS_HID_4e204 = 0x4e204, + BNXT_ULP_CLASS_HID_4f0f0 = 0x4f0f0, + BNXT_ULP_CLASS_HID_4ebc0 = 0x4ebc0, + BNXT_ULP_CLASS_HID_4f490 = 0x4f490, + BNXT_ULP_CLASS_HID_4efe0 = 0x4efe0, + BNXT_ULP_CLASS_HID_4fa5c = 0x4fa5c, + BNXT_ULP_CLASS_HID_4f5ac = 0x4f5ac, + BNXT_ULP_CLASS_HID_4ef58 = 0x4ef58, + BNXT_ULP_CLASS_HID_4e6a8 = 0x4e6a8, + BNXT_ULP_CLASS_HID_4f564 = 0x4f564, + BNXT_ULP_CLASS_HID_4f138 = 0x4f138, + BNXT_ULP_CLASS_HID_4f904 = 0x4f904, + BNXT_ULP_CLASS_HID_4f014 = 0x4f014, + BNXT_ULP_CLASS_HID_4fec0 = 0x4fec0, + BNXT_ULP_CLASS_HID_4f9d0 = 0x4f9d0, + BNXT_ULP_CLASS_HID_1e460 = 0x1e460, + BNXT_ULP_CLASS_HID_1ff70 = 0x1ff70, + BNXT_ULP_CLASS_HID_1ea2c = 0x1ea2c, + BNXT_ULP_CLASS_HID_1e53c = 0x1e53c, + BNXT_ULP_CLASS_HID_1f1cc = 0x1f1cc, + BNXT_ULP_CLASS_HID_1e8dc = 0x1e8dc, + BNXT_ULP_CLASS_HID_1f788 = 0x1f788, + BNXT_ULP_CLASS_HID_1ee98 = 0x1ee98, + BNXT_ULP_CLASS_HID_1e894 = 0x1e894, + BNXT_ULP_CLASS_HID_1e4a8 = 0x1e4a8, + BNXT_ULP_CLASS_HID_1f364 = 0x1f364, + BNXT_ULP_CLASS_HID_1ea74 = 0x1ea74, + BNXT_ULP_CLASS_HID_1f270 = 0x1f270, + BNXT_ULP_CLASS_HID_1ed40 = 0x1ed40, + BNXT_ULP_CLASS_HID_1f83c = 0x1f83c, + BNXT_ULP_CLASS_HID_1f7d0 = 0x1f7d0, + BNXT_ULP_CLASS_HID_5e134 = 0x5e134, + BNXT_ULP_CLASS_HID_5f804 = 0x5f804, + BNXT_ULP_CLASS_HID_5e6f0 = 0x5e6f0, + BNXT_ULP_CLASS_HID_5e1c0 = 0x5e1c0, + BNXT_ULP_CLASS_HID_5ea90 = 0x5ea90, + BNXT_ULP_CLASS_HID_5e5e0 = 0x5e5e0, + BNXT_ULP_CLASS_HID_5f05c = 0x5f05c, + BNXT_ULP_CLASS_HID_5ebac = 0x5ebac, + BNXT_ULP_CLASS_HID_5e558 = 0x5e558, + BNXT_ULP_CLASS_HID_5e17c = 0x5e17c, + BNXT_ULP_CLASS_HID_5eb64 = 0x5eb64, + BNXT_ULP_CLASS_HID_5e738 = 0x5e738, + BNXT_ULP_CLASS_HID_5ef04 = 0x5ef04, + BNXT_ULP_CLASS_HID_5e614 = 0x5e614, + BNXT_ULP_CLASS_HID_5f4c0 = 0x5f4c0, + BNXT_ULP_CLASS_HID_5f0e4 = 0x5f0e4, + BNXT_ULP_CLASS_HID_5802 = 0x5802, + BNXT_ULP_CLASS_HID_5e46 = 0x5e46, + BNXT_ULP_CLASS_HID_1d76 = 0x1d76, + BNXT_ULP_CLASS_HID_02ba = 0x02ba, + BNXT_ULP_CLASS_HID_32a2 = 0x32a2, + BNXT_ULP_CLASS_HID_38e6 = 0x38e6, + BNXT_ULP_CLASS_HID_52ca = 0x52ca, + BNXT_ULP_CLASS_HID_580e = 0x580e, + BNXT_ULP_CLASS_HID_44996 = 0x44996, + BNXT_ULP_CLASS_HID_410e6 = 0x410e6, + BNXT_ULP_CLASS_HID_42036 = 0x42036, + BNXT_ULP_CLASS_HID_4264a = 0x4264a, + BNXT_ULP_CLASS_HID_45ffe = 0x45ffe, + BNXT_ULP_CLASS_HID_44532 = 0x44532, + BNXT_ULP_CLASS_HID_4399e = 0x4399e, + BNXT_ULP_CLASS_HID_43fd2 = 0x43fd2, + BNXT_ULP_CLASS_HID_23da0 = 0x23da0, + BNXT_ULP_CLASS_HID_2239c = 0x2239c, + BNXT_ULP_CLASS_HID_207fc = 0x207fc, + BNXT_ULP_CLASS_HID_20d38 = 0x20d38, + BNXT_ULP_CLASS_HID_25e34 = 0x25e34, + BNXT_ULP_CLASS_HID_24470 = 0x24470, + BNXT_ULP_CLASS_HID_22850 = 0x22850, + BNXT_ULP_CLASS_HID_2518c = 0x2518c, + BNXT_ULP_CLASS_HID_20970 = 0x20970, + BNXT_ULP_CLASS_HID_20eac = 0x20eac, + BNXT_ULP_CLASS_HID_2128c = 0x2128c, + BNXT_ULP_CLASS_HID_218c8 = 0x218c8, + BNXT_ULP_CLASS_HID_22dc4 = 0x22dc4, + BNXT_ULP_CLASS_HID_25300 = 0x25300, + BNXT_ULP_CLASS_HID_23760 = 0x23760, + BNXT_ULP_CLASS_HID_23d5c = 0x23d5c, + BNXT_ULP_CLASS_HID_63694 = 0x63694, + BNXT_ULP_CLASS_HID_63cd0 = 0x63cd0, + BNXT_ULP_CLASS_HID_60030 = 0x60030, + BNXT_ULP_CLASS_HID_6066c = 0x6066c, + BNXT_ULP_CLASS_HID_65b68 = 0x65b68, + BNXT_ULP_CLASS_HID_640a4 = 0x640a4, + BNXT_ULP_CLASS_HID_62484 = 0x62484, + BNXT_ULP_CLASS_HID_62ac0 = 0x62ac0, + BNXT_ULP_CLASS_HID_605a4 = 0x605a4, + BNXT_ULP_CLASS_HID_60be0 = 0x60be0, + BNXT_ULP_CLASS_HID_64a8c = 0x64a8c, + BNXT_ULP_CLASS_HID_6153c = 0x6153c, + BNXT_ULP_CLASS_HID_62638 = 0x62638, + BNXT_ULP_CLASS_HID_62c74 = 0x62c74, + BNXT_ULP_CLASS_HID_63054 = 0x63054, + BNXT_ULP_CLASS_HID_63990 = 0x63990, + BNXT_ULP_CLASS_HID_9a98 = 0x9a98, + BNXT_ULP_CLASS_HID_80a4 = 0x80a4, + BNXT_ULP_CLASS_HID_c3b0 = 0xc3b0, + BNXT_ULP_CLASS_HID_c9fc = 0xc9fc, + BNXT_ULP_CLASS_HID_bf0c = 0xbf0c, + BNXT_ULP_CLASS_HID_a548 = 0xa548, + BNXT_ULP_CLASS_HID_8968 = 0x8968, + BNXT_ULP_CLASS_HID_8eb4 = 0x8eb4, + BNXT_ULP_CLASS_HID_497ac = 0x497ac, + BNXT_ULP_CLASS_HID_49de8 = 0x49de8, + BNXT_ULP_CLASS_HID_4dcc4 = 0x4dcc4, + BNXT_ULP_CLASS_HID_4c200 = 0x4c200, + BNXT_ULP_CLASS_HID_4b850 = 0x4b850, + BNXT_ULP_CLASS_HID_4a19c = 0x4a19c, + BNXT_ULP_CLASS_HID_485bc = 0x485bc, + BNXT_ULP_CLASS_HID_48bf8 = 0x48bf8, + BNXT_ULP_CLASS_HID_1b098 = 0x1b098, + BNXT_ULP_CLASS_HID_1b6a4 = 0x1b6a4, + BNXT_ULP_CLASS_HID_19ac4 = 0x19ac4, + BNXT_ULP_CLASS_HID_18000 = 0x18000, + BNXT_ULP_CLASS_HID_1d50c = 0x1d50c, + BNXT_ULP_CLASS_HID_1db48 = 0x1db48, + BNXT_ULP_CLASS_HID_1bf68 = 0x1bf68, + BNXT_ULP_CLASS_HID_1a4b4 = 0x1a4b4, + BNXT_ULP_CLASS_HID_58dac = 0x58dac, + BNXT_ULP_CLASS_HID_5b3e8 = 0x5b3e8, + BNXT_ULP_CLASS_HID_59708 = 0x59708, + BNXT_ULP_CLASS_HID_59d54 = 0x59d54, + BNXT_ULP_CLASS_HID_5ae50 = 0x5ae50, + BNXT_ULP_CLASS_HID_5d79c = 0x5d79c, + BNXT_ULP_CLASS_HID_5bbbc = 0x5bbbc, + BNXT_ULP_CLASS_HID_5a1f8 = 0x5a1f8, + BNXT_ULP_CLASS_HID_5822 = 0x5822, + BNXT_ULP_CLASS_HID_5e66 = 0x5e66, + BNXT_ULP_CLASS_HID_1d56 = 0x1d56, + BNXT_ULP_CLASS_HID_029a = 0x029a, + BNXT_ULP_CLASS_HID_3282 = 0x3282, + BNXT_ULP_CLASS_HID_38c6 = 0x38c6, + BNXT_ULP_CLASS_HID_52ea = 0x52ea, + BNXT_ULP_CLASS_HID_582e = 0x582e, + BNXT_ULP_CLASS_HID_51ba = 0x51ba, + BNXT_ULP_CLASS_HID_57fe = 0x57fe, + BNXT_ULP_CLASS_HID_12ee = 0x12ee, + BNXT_ULP_CLASS_HID_1832 = 0x1832, + BNXT_ULP_CLASS_HID_081a = 0x081a, + BNXT_ULP_CLASS_HID_0e5e = 0x0e5e, + BNXT_ULP_CLASS_HID_2802 = 0x2802, + BNXT_ULP_CLASS_HID_2e46 = 0x2e46, + BNXT_ULP_CLASS_HID_4556e = 0x4556e, + BNXT_ULP_CLASS_HID_45ab2 = 0x45ab2, + BNXT_ULP_CLASS_HID_419a2 = 0x419a2, + BNXT_ULP_CLASS_HID_41fe6 = 0x41fe6, + BNXT_ULP_CLASS_HID_40fce = 0x40fce, + BNXT_ULP_CLASS_HID_43512 = 0x43512, + BNXT_ULP_CLASS_HID_42f36 = 0x42f36, + BNXT_ULP_CLASS_HID_4557a = 0x4557a, + BNXT_ULP_CLASS_HID_42a86 = 0x42a86, + BNXT_ULP_CLASS_HID_450ca = 0x450ca, + BNXT_ULP_CLASS_HID_44aee = 0x44aee, + BNXT_ULP_CLASS_HID_4157e = 0x4157e, + BNXT_ULP_CLASS_HID_40566 = 0x40566, + BNXT_ULP_CLASS_HID_40aaa = 0x40aaa, + BNXT_ULP_CLASS_HID_4254e = 0x4254e, + BNXT_ULP_CLASS_HID_42a92 = 0x42a92, + BNXT_ULP_CLASS_HID_449b6 = 0x449b6, + BNXT_ULP_CLASS_HID_410c6 = 0x410c6, + BNXT_ULP_CLASS_HID_42016 = 0x42016, + BNXT_ULP_CLASS_HID_4266a = 0x4266a, + BNXT_ULP_CLASS_HID_45fde = 0x45fde, + BNXT_ULP_CLASS_HID_44512 = 0x44512, + BNXT_ULP_CLASS_HID_439be = 0x439be, + BNXT_ULP_CLASS_HID_43ff2 = 0x43ff2, + BNXT_ULP_CLASS_HID_63682 = 0x63682, + BNXT_ULP_CLASS_HID_63cc6 = 0x63cc6, + BNXT_ULP_CLASS_HID_61162 = 0x61162, + BNXT_ULP_CLASS_HID_616a6 = 0x616a6, + BNXT_ULP_CLASS_HID_60c2a = 0x60c2a, + BNXT_ULP_CLASS_HID_6326e = 0x6326e, + BNXT_ULP_CLASS_HID_645be = 0x645be, + BNXT_ULP_CLASS_HID_64bf2 = 0x64bf2, + BNXT_ULP_CLASS_HID_50082 = 0x50082, + BNXT_ULP_CLASS_HID_506c6 = 0x506c6, + BNXT_ULP_CLASS_HID_55616 = 0x55616, + BNXT_ULP_CLASS_HID_55c6a = 0x55c6a, + BNXT_ULP_CLASS_HID_5162a = 0x5162a, + BNXT_ULP_CLASS_HID_51c6e = 0x51c6e, + BNXT_ULP_CLASS_HID_52fbe = 0x52fbe, + BNXT_ULP_CLASS_HID_555f2 = 0x555f2, + BNXT_ULP_CLASS_HID_72c82 = 0x72c82, + BNXT_ULP_CLASS_HID_752c6 = 0x752c6, + BNXT_ULP_CLASS_HID_70762 = 0x70762, + BNXT_ULP_CLASS_HID_70ca6 = 0x70ca6, + BNXT_ULP_CLASS_HID_7222a = 0x7222a, + BNXT_ULP_CLASS_HID_7286e = 0x7286e, + BNXT_ULP_CLASS_HID_71c8a = 0x71c8a, + BNXT_ULP_CLASS_HID_702ce = 0x702ce, + BNXT_ULP_CLASS_HID_5842 = 0x5842, + BNXT_ULP_CLASS_HID_5e06 = 0x5e06, + BNXT_ULP_CLASS_HID_1d36 = 0x1d36, + BNXT_ULP_CLASS_HID_02fa = 0x02fa, + BNXT_ULP_CLASS_HID_32e2 = 0x32e2, + BNXT_ULP_CLASS_HID_38a6 = 0x38a6, + BNXT_ULP_CLASS_HID_528a = 0x528a, + BNXT_ULP_CLASS_HID_584e = 0x584e, + BNXT_ULP_CLASS_HID_51da = 0x51da, + BNXT_ULP_CLASS_HID_579e = 0x579e, + BNXT_ULP_CLASS_HID_128e = 0x128e, + BNXT_ULP_CLASS_HID_1852 = 0x1852, + BNXT_ULP_CLASS_HID_087a = 0x087a, + BNXT_ULP_CLASS_HID_0e3e = 0x0e3e, + BNXT_ULP_CLASS_HID_2862 = 0x2862, + BNXT_ULP_CLASS_HID_2e26 = 0x2e26, + BNXT_ULP_CLASS_HID_4550e = 0x4550e, + BNXT_ULP_CLASS_HID_45ad2 = 0x45ad2, + BNXT_ULP_CLASS_HID_419c2 = 0x419c2, + BNXT_ULP_CLASS_HID_41f86 = 0x41f86, + BNXT_ULP_CLASS_HID_40fae = 0x40fae, + BNXT_ULP_CLASS_HID_43572 = 0x43572, + BNXT_ULP_CLASS_HID_42f56 = 0x42f56, + BNXT_ULP_CLASS_HID_4551a = 0x4551a, + BNXT_ULP_CLASS_HID_42ae6 = 0x42ae6, + BNXT_ULP_CLASS_HID_450aa = 0x450aa, + BNXT_ULP_CLASS_HID_44a8e = 0x44a8e, + BNXT_ULP_CLASS_HID_4151e = 0x4151e, + BNXT_ULP_CLASS_HID_40506 = 0x40506, + BNXT_ULP_CLASS_HID_40aca = 0x40aca, + BNXT_ULP_CLASS_HID_4252e = 0x4252e, + BNXT_ULP_CLASS_HID_42af2 = 0x42af2, + BNXT_ULP_CLASS_HID_449d6 = 0x449d6, + BNXT_ULP_CLASS_HID_410a6 = 0x410a6, + BNXT_ULP_CLASS_HID_42076 = 0x42076, + BNXT_ULP_CLASS_HID_4260a = 0x4260a, + BNXT_ULP_CLASS_HID_45fbe = 0x45fbe, + BNXT_ULP_CLASS_HID_44572 = 0x44572, + BNXT_ULP_CLASS_HID_439de = 0x439de, + BNXT_ULP_CLASS_HID_43f92 = 0x43f92, + BNXT_ULP_CLASS_HID_636e2 = 0x636e2, + BNXT_ULP_CLASS_HID_63ca6 = 0x63ca6, + BNXT_ULP_CLASS_HID_61102 = 0x61102, + BNXT_ULP_CLASS_HID_616c6 = 0x616c6, + BNXT_ULP_CLASS_HID_60c4a = 0x60c4a, + BNXT_ULP_CLASS_HID_6320e = 0x6320e, + BNXT_ULP_CLASS_HID_645de = 0x645de, + BNXT_ULP_CLASS_HID_64b92 = 0x64b92, + BNXT_ULP_CLASS_HID_500e2 = 0x500e2, + BNXT_ULP_CLASS_HID_506a6 = 0x506a6, + BNXT_ULP_CLASS_HID_55676 = 0x55676, + BNXT_ULP_CLASS_HID_55c0a = 0x55c0a, + BNXT_ULP_CLASS_HID_5164a = 0x5164a, + BNXT_ULP_CLASS_HID_51c0e = 0x51c0e, + BNXT_ULP_CLASS_HID_52fde = 0x52fde, + BNXT_ULP_CLASS_HID_55592 = 0x55592, + BNXT_ULP_CLASS_HID_72ce2 = 0x72ce2, + BNXT_ULP_CLASS_HID_752a6 = 0x752a6, + BNXT_ULP_CLASS_HID_70702 = 0x70702, + BNXT_ULP_CLASS_HID_70cc6 = 0x70cc6, + BNXT_ULP_CLASS_HID_7224a = 0x7224a, + BNXT_ULP_CLASS_HID_7280e = 0x7280e, + BNXT_ULP_CLASS_HID_71cea = 0x71cea, + BNXT_ULP_CLASS_HID_702ae = 0x702ae, + BNXT_ULP_CLASS_HID_23dc0 = 0x23dc0, + BNXT_ULP_CLASS_HID_223fc = 0x223fc, + BNXT_ULP_CLASS_HID_2079c = 0x2079c, + BNXT_ULP_CLASS_HID_20d58 = 0x20d58, + BNXT_ULP_CLASS_HID_25e54 = 0x25e54, + BNXT_ULP_CLASS_HID_24410 = 0x24410, + BNXT_ULP_CLASS_HID_22830 = 0x22830, + BNXT_ULP_CLASS_HID_251ec = 0x251ec, + BNXT_ULP_CLASS_HID_20910 = 0x20910, + BNXT_ULP_CLASS_HID_20ecc = 0x20ecc, + BNXT_ULP_CLASS_HID_212ec = 0x212ec, + BNXT_ULP_CLASS_HID_218a8 = 0x218a8, + BNXT_ULP_CLASS_HID_22da4 = 0x22da4, + BNXT_ULP_CLASS_HID_25360 = 0x25360, + BNXT_ULP_CLASS_HID_23700 = 0x23700, + BNXT_ULP_CLASS_HID_23d3c = 0x23d3c, + BNXT_ULP_CLASS_HID_636f4 = 0x636f4, + BNXT_ULP_CLASS_HID_63cb0 = 0x63cb0, + BNXT_ULP_CLASS_HID_60050 = 0x60050, + BNXT_ULP_CLASS_HID_6060c = 0x6060c, + BNXT_ULP_CLASS_HID_65b08 = 0x65b08, + BNXT_ULP_CLASS_HID_640c4 = 0x640c4, + BNXT_ULP_CLASS_HID_624e4 = 0x624e4, + BNXT_ULP_CLASS_HID_62aa0 = 0x62aa0, + BNXT_ULP_CLASS_HID_605c4 = 0x605c4, + BNXT_ULP_CLASS_HID_60b80 = 0x60b80, + BNXT_ULP_CLASS_HID_64aec = 0x64aec, + BNXT_ULP_CLASS_HID_6155c = 0x6155c, + BNXT_ULP_CLASS_HID_62658 = 0x62658, + BNXT_ULP_CLASS_HID_62c14 = 0x62c14, + BNXT_ULP_CLASS_HID_63034 = 0x63034, + BNXT_ULP_CLASS_HID_639f0 = 0x639f0, + BNXT_ULP_CLASS_HID_353c0 = 0x353c0, + BNXT_ULP_CLASS_HID_359fc = 0x359fc, + BNXT_ULP_CLASS_HID_33d9c = 0x33d9c, + BNXT_ULP_CLASS_HID_32358 = 0x32358, + BNXT_ULP_CLASS_HID_31908 = 0x31908, + BNXT_ULP_CLASS_HID_31ec4 = 0x31ec4, + BNXT_ULP_CLASS_HID_35e30 = 0x35e30, + BNXT_ULP_CLASS_HID_347ec = 0x347ec, + BNXT_ULP_CLASS_HID_33f10 = 0x33f10, + BNXT_ULP_CLASS_HID_324cc = 0x324cc, + BNXT_ULP_CLASS_HID_308ec = 0x308ec, + BNXT_ULP_CLASS_HID_30ea8 = 0x30ea8, + BNXT_ULP_CLASS_HID_343a4 = 0x343a4, + BNXT_ULP_CLASS_HID_34960 = 0x34960, + BNXT_ULP_CLASS_HID_32d00 = 0x32d00, + BNXT_ULP_CLASS_HID_3533c = 0x3533c, + BNXT_ULP_CLASS_HID_72cf4 = 0x72cf4, + BNXT_ULP_CLASS_HID_752b0 = 0x752b0, + BNXT_ULP_CLASS_HID_73650 = 0x73650, + BNXT_ULP_CLASS_HID_73c0c = 0x73c0c, + BNXT_ULP_CLASS_HID_7123c = 0x7123c, + BNXT_ULP_CLASS_HID_71bf8 = 0x71bf8, + BNXT_ULP_CLASS_HID_75ae4 = 0x75ae4, + BNXT_ULP_CLASS_HID_740a0 = 0x740a0, + BNXT_ULP_CLASS_HID_73bc4 = 0x73bc4, + BNXT_ULP_CLASS_HID_72180 = 0x72180, + BNXT_ULP_CLASS_HID_705a0 = 0x705a0, + BNXT_ULP_CLASS_HID_70b5c = 0x70b5c, + BNXT_ULP_CLASS_HID_75c58 = 0x75c58, + BNXT_ULP_CLASS_HID_74214 = 0x74214, + BNXT_ULP_CLASS_HID_72634 = 0x72634, + BNXT_ULP_CLASS_HID_72ff0 = 0x72ff0, + BNXT_ULP_CLASS_HID_2a6c0 = 0x2a6c0, + BNXT_ULP_CLASS_HID_2acfc = 0x2acfc, + BNXT_ULP_CLASS_HID_2b09c = 0x2b09c, + BNXT_ULP_CLASS_HID_2b658 = 0x2b658, + BNXT_ULP_CLASS_HID_2cb54 = 0x2cb54, + BNXT_ULP_CLASS_HID_295c4 = 0x295c4, + BNXT_ULP_CLASS_HID_2d530 = 0x2d530, + BNXT_ULP_CLASS_HID_2daec = 0x2daec, + BNXT_ULP_CLASS_HID_2b210 = 0x2b210, + BNXT_ULP_CLASS_HID_2bbcc = 0x2bbcc, + BNXT_ULP_CLASS_HID_29fec = 0x29fec, + BNXT_ULP_CLASS_HID_285a8 = 0x285a8, + BNXT_ULP_CLASS_HID_2d6a4 = 0x2d6a4, + BNXT_ULP_CLASS_HID_2dc60 = 0x2dc60, + BNXT_ULP_CLASS_HID_2a000 = 0x2a000, + BNXT_ULP_CLASS_HID_2a63c = 0x2a63c, + BNXT_ULP_CLASS_HID_6a3f4 = 0x6a3f4, + BNXT_ULP_CLASS_HID_6a9b0 = 0x6a9b0, + BNXT_ULP_CLASS_HID_68d50 = 0x68d50, + BNXT_ULP_CLASS_HID_6b30c = 0x6b30c, + BNXT_ULP_CLASS_HID_6c408 = 0x6c408, + BNXT_ULP_CLASS_HID_6cdc4 = 0x6cdc4, + BNXT_ULP_CLASS_HID_6d1e4 = 0x6d1e4, + BNXT_ULP_CLASS_HID_6d7a0 = 0x6d7a0, + BNXT_ULP_CLASS_HID_68ec4 = 0x68ec4, + BNXT_ULP_CLASS_HID_6b480 = 0x6b480, + BNXT_ULP_CLASS_HID_698a0 = 0x698a0, + BNXT_ULP_CLASS_HID_69e5c = 0x69e5c, + BNXT_ULP_CLASS_HID_6d358 = 0x6d358, + BNXT_ULP_CLASS_HID_6d914 = 0x6d914, + BNXT_ULP_CLASS_HID_6bd34 = 0x6bd34, + BNXT_ULP_CLASS_HID_6a2f0 = 0x6a2f0, + BNXT_ULP_CLASS_HID_3dcc0 = 0x3dcc0, + BNXT_ULP_CLASS_HID_3c2fc = 0x3c2fc, + BNXT_ULP_CLASS_HID_3a69c = 0x3a69c, + BNXT_ULP_CLASS_HID_3ac58 = 0x3ac58, + BNXT_ULP_CLASS_HID_38208 = 0x38208, + BNXT_ULP_CLASS_HID_38bc4 = 0x38bc4, + BNXT_ULP_CLASS_HID_3cb30 = 0x3cb30, + BNXT_ULP_CLASS_HID_395a0 = 0x395a0, + BNXT_ULP_CLASS_HID_3a810 = 0x3a810, + BNXT_ULP_CLASS_HID_3d1cc = 0x3d1cc, + BNXT_ULP_CLASS_HID_3b5ec = 0x3b5ec, + BNXT_ULP_CLASS_HID_3bba8 = 0x3bba8, + BNXT_ULP_CLASS_HID_39158 = 0x39158, + BNXT_ULP_CLASS_HID_39714 = 0x39714, + BNXT_ULP_CLASS_HID_3d600 = 0x3d600, + BNXT_ULP_CLASS_HID_3dc3c = 0x3dc3c, + BNXT_ULP_CLASS_HID_7d9f4 = 0x7d9f4, + BNXT_ULP_CLASS_HID_7dfb0 = 0x7dfb0, + BNXT_ULP_CLASS_HID_7a350 = 0x7a350, + BNXT_ULP_CLASS_HID_7a90c = 0x7a90c, + BNXT_ULP_CLASS_HID_79f3c = 0x79f3c, + BNXT_ULP_CLASS_HID_784f8 = 0x784f8, + BNXT_ULP_CLASS_HID_7c7e4 = 0x7c7e4, + BNXT_ULP_CLASS_HID_7cda0 = 0x7cda0, + BNXT_ULP_CLASS_HID_7a4c4 = 0x7a4c4, + BNXT_ULP_CLASS_HID_7aa80 = 0x7aa80, + BNXT_ULP_CLASS_HID_78ea0 = 0x78ea0, + BNXT_ULP_CLASS_HID_7b45c = 0x7b45c, + BNXT_ULP_CLASS_HID_7c958 = 0x7c958, + BNXT_ULP_CLASS_HID_793c8 = 0x793c8, + BNXT_ULP_CLASS_HID_7d334 = 0x7d334, + BNXT_ULP_CLASS_HID_7d8f0 = 0x7d8f0, + BNXT_ULP_CLASS_HID_9ab8 = 0x9ab8, + BNXT_ULP_CLASS_HID_8084 = 0x8084, + BNXT_ULP_CLASS_HID_c390 = 0xc390, + BNXT_ULP_CLASS_HID_c9dc = 0xc9dc, + BNXT_ULP_CLASS_HID_bf2c = 0xbf2c, + BNXT_ULP_CLASS_HID_a568 = 0xa568, + BNXT_ULP_CLASS_HID_8948 = 0x8948, + BNXT_ULP_CLASS_HID_8e94 = 0x8e94, + BNXT_ULP_CLASS_HID_4978c = 0x4978c, + BNXT_ULP_CLASS_HID_49dc8 = 0x49dc8, + BNXT_ULP_CLASS_HID_4dce4 = 0x4dce4, + BNXT_ULP_CLASS_HID_4c220 = 0x4c220, + BNXT_ULP_CLASS_HID_4b870 = 0x4b870, + BNXT_ULP_CLASS_HID_4a1bc = 0x4a1bc, + BNXT_ULP_CLASS_HID_4859c = 0x4859c, + BNXT_ULP_CLASS_HID_48bd8 = 0x48bd8, + BNXT_ULP_CLASS_HID_1b0b8 = 0x1b0b8, + BNXT_ULP_CLASS_HID_1b684 = 0x1b684, + BNXT_ULP_CLASS_HID_19ae4 = 0x19ae4, + BNXT_ULP_CLASS_HID_18020 = 0x18020, + BNXT_ULP_CLASS_HID_1d52c = 0x1d52c, + BNXT_ULP_CLASS_HID_1db68 = 0x1db68, + BNXT_ULP_CLASS_HID_1bf48 = 0x1bf48, + BNXT_ULP_CLASS_HID_1a494 = 0x1a494, + BNXT_ULP_CLASS_HID_58d8c = 0x58d8c, + BNXT_ULP_CLASS_HID_5b3c8 = 0x5b3c8, + BNXT_ULP_CLASS_HID_59728 = 0x59728, + BNXT_ULP_CLASS_HID_59d74 = 0x59d74, + BNXT_ULP_CLASS_HID_5ae70 = 0x5ae70, + BNXT_ULP_CLASS_HID_5d7bc = 0x5d7bc, + BNXT_ULP_CLASS_HID_5bb9c = 0x5bb9c, + BNXT_ULP_CLASS_HID_5a1d8 = 0x5a1d8, + BNXT_ULP_CLASS_HID_c138 = 0xc138, + BNXT_ULP_CLASS_HID_c704 = 0xc704, + BNXT_ULP_CLASS_HID_c610 = 0xc610, + BNXT_ULP_CLASS_HID_d0a0 = 0xd0a0, + BNXT_ULP_CLASS_HID_e5ac = 0xe5ac, + BNXT_ULP_CLASS_HID_ebe8 = 0xebe8, + BNXT_ULP_CLASS_HID_cfc8 = 0xcfc8, + BNXT_ULP_CLASS_HID_f514 = 0xf514, + BNXT_ULP_CLASS_HID_4da0c = 0x4da0c, + BNXT_ULP_CLASS_HID_4c048 = 0x4c048, + BNXT_ULP_CLASS_HID_4c364 = 0x4c364, + BNXT_ULP_CLASS_HID_4c8a0 = 0x4c8a0, + BNXT_ULP_CLASS_HID_4fef0 = 0x4fef0, + BNXT_ULP_CLASS_HID_4e43c = 0x4e43c, + BNXT_ULP_CLASS_HID_4c81c = 0x4c81c, + BNXT_ULP_CLASS_HID_4ce58 = 0x4ce58, + BNXT_ULP_CLASS_HID_1f738 = 0x1f738, + BNXT_ULP_CLASS_HID_1fd04 = 0x1fd04, + BNXT_ULP_CLASS_HID_1c164 = 0x1c164, + BNXT_ULP_CLASS_HID_1c6a0 = 0x1c6a0, + BNXT_ULP_CLASS_HID_1dbac = 0x1dbac, + BNXT_ULP_CLASS_HID_1c1e8 = 0x1c1e8, + BNXT_ULP_CLASS_HID_1e5c8 = 0x1e5c8, + BNXT_ULP_CLASS_HID_1eb14 = 0x1eb14, + BNXT_ULP_CLASS_HID_5f00c = 0x5f00c, + BNXT_ULP_CLASS_HID_5f648 = 0x5f648, + BNXT_ULP_CLASS_HID_5dda8 = 0x5dda8, + BNXT_ULP_CLASS_HID_5c3f4 = 0x5c3f4, + BNXT_ULP_CLASS_HID_5d4f0 = 0x5d4f0, + BNXT_ULP_CLASS_HID_5da3c = 0x5da3c, + BNXT_ULP_CLASS_HID_5fe1c = 0x5fe1c, + BNXT_ULP_CLASS_HID_5e458 = 0x5e458, + BNXT_ULP_CLASS_HID_bc78 = 0xbc78, + BNXT_ULP_CLASS_HID_a244 = 0xa244, + BNXT_ULP_CLASS_HID_e550 = 0xe550, + BNXT_ULP_CLASS_HID_ea9c = 0xea9c, + BNXT_ULP_CLASS_HID_a0ec = 0xa0ec, + BNXT_ULP_CLASS_HID_a628 = 0xa628, + BNXT_ULP_CLASS_HID_aa08 = 0xaa08, + BNXT_ULP_CLASS_HID_b054 = 0xb054, + BNXT_ULP_CLASS_HID_4b94c = 0x4b94c, + BNXT_ULP_CLASS_HID_4be88 = 0x4be88, + BNXT_ULP_CLASS_HID_4e1a4 = 0x4e1a4, + BNXT_ULP_CLASS_HID_4e7e0 = 0x4e7e0, + BNXT_ULP_CLASS_HID_4bd30 = 0x4bd30, + BNXT_ULP_CLASS_HID_4a37c = 0x4a37c, + BNXT_ULP_CLASS_HID_4a75c = 0x4a75c, + BNXT_ULP_CLASS_HID_4ac98 = 0x4ac98, + BNXT_ULP_CLASS_HID_1b278 = 0x1b278, + BNXT_ULP_CLASS_HID_1b844 = 0x1b844, + BNXT_ULP_CLASS_HID_1bfa4 = 0x1bfa4, + BNXT_ULP_CLASS_HID_1a5e0 = 0x1a5e0, + BNXT_ULP_CLASS_HID_1f6ec = 0x1f6ec, + BNXT_ULP_CLASS_HID_1fc28 = 0x1fc28, + BNXT_ULP_CLASS_HID_1a008 = 0x1a008, + BNXT_ULP_CLASS_HID_1a654 = 0x1a654, + BNXT_ULP_CLASS_HID_5af4c = 0x5af4c, + BNXT_ULP_CLASS_HID_5b488 = 0x5b488, + BNXT_ULP_CLASS_HID_5b8e8 = 0x5b8e8, + BNXT_ULP_CLASS_HID_5be34 = 0x5be34, + BNXT_ULP_CLASS_HID_5f330 = 0x5f330, + BNXT_ULP_CLASS_HID_5f97c = 0x5f97c, + BNXT_ULP_CLASS_HID_5bd5c = 0x5bd5c, + BNXT_ULP_CLASS_HID_5a298 = 0x5a298, + BNXT_ULP_CLASS_HID_e2f8 = 0xe2f8, + BNXT_ULP_CLASS_HID_e8c4 = 0xe8c4, + BNXT_ULP_CLASS_HID_ebd0 = 0xebd0, + BNXT_ULP_CLASS_HID_f260 = 0xf260, + BNXT_ULP_CLASS_HID_e76c = 0xe76c, + BNXT_ULP_CLASS_HID_eca8 = 0xeca8, + BNXT_ULP_CLASS_HID_f088 = 0xf088, + BNXT_ULP_CLASS_HID_f6d4 = 0xf6d4, + BNXT_ULP_CLASS_HID_4ffcc = 0x4ffcc, + BNXT_ULP_CLASS_HID_4e508 = 0x4e508, + BNXT_ULP_CLASS_HID_4e424 = 0x4e424, + BNXT_ULP_CLASS_HID_4ea60 = 0x4ea60, + BNXT_ULP_CLASS_HID_4e3b0 = 0x4e3b0, + BNXT_ULP_CLASS_HID_4e9fc = 0x4e9fc, + BNXT_ULP_CLASS_HID_4eddc = 0x4eddc, + BNXT_ULP_CLASS_HID_4f318 = 0x4f318, + BNXT_ULP_CLASS_HID_1f8f8 = 0x1f8f8, + BNXT_ULP_CLASS_HID_1fec4 = 0x1fec4, + BNXT_ULP_CLASS_HID_1e224 = 0x1e224, + BNXT_ULP_CLASS_HID_1e860 = 0x1e860, + BNXT_ULP_CLASS_HID_1fd6c = 0x1fd6c, + BNXT_ULP_CLASS_HID_1e2a8 = 0x1e2a8, + BNXT_ULP_CLASS_HID_1e688 = 0x1e688, + BNXT_ULP_CLASS_HID_1ecd4 = 0x1ecd4, + BNXT_ULP_CLASS_HID_5f5cc = 0x5f5cc, + BNXT_ULP_CLASS_HID_5fb08 = 0x5fb08, + BNXT_ULP_CLASS_HID_5ff68 = 0x5ff68, + BNXT_ULP_CLASS_HID_5e4b4 = 0x5e4b4, + BNXT_ULP_CLASS_HID_5f9b0 = 0x5f9b0, + BNXT_ULP_CLASS_HID_5fffc = 0x5fffc, + BNXT_ULP_CLASS_HID_5e3dc = 0x5e3dc, + BNXT_ULP_CLASS_HID_5e918 = 0x5e918, + BNXT_ULP_CLASS_HID_23de0 = 0x23de0, BNXT_ULP_CLASS_HID_223dc = 0x223dc, - BNXT_ULP_CLASS_HID_2acdc = 0x2acdc, - BNXT_ULP_CLASS_HID_359dc = 0x359dc, - BNXT_ULP_CLASS_HID_3c2dc = 0x3c2dc, - BNXT_ULP_CLASS_HID_20eec = 0x20eec, - BNXT_ULP_CLASS_HID_2bbec = 0x2bbec, - BNXT_ULP_CLASS_HID_324ec = 0x324ec, - BNXT_ULP_CLASS_HID_3d1ec = 0x3d1ec, - BNXT_ULP_CLASS_HID_20ba0 = 0x20ba0, - BNXT_ULP_CLASS_HID_2b4a0 = 0x2b4a0, - BNXT_ULP_CLASS_HID_321a0 = 0x321a0, - BNXT_ULP_CLASS_HID_3aaa0 = 0x3aaa0, - BNXT_ULP_CLASS_HID_23c90 = 0x23c90, - BNXT_ULP_CLASS_HID_2a990 = 0x2a990, - BNXT_ULP_CLASS_HID_35290 = 0x35290, - BNXT_ULP_CLASS_HID_3df90 = 0x3df90, + BNXT_ULP_CLASS_HID_207bc = 0x207bc, + BNXT_ULP_CLASS_HID_20d78 = 0x20d78, + BNXT_ULP_CLASS_HID_25e74 = 0x25e74, BNXT_ULP_CLASS_HID_24430 = 0x24430, - BNXT_ULP_CLASS_HID_295e4 = 0x295e4, - BNXT_ULP_CLASS_HID_31ee4 = 0x31ee4, - BNXT_ULP_CLASS_HID_38be4 = 0x38be4, + BNXT_ULP_CLASS_HID_22810 = 0x22810, + BNXT_ULP_CLASS_HID_251cc = 0x251cc, + BNXT_ULP_CLASS_HID_20930 = 0x20930, + BNXT_ULP_CLASS_HID_20eec = 0x20eec, + BNXT_ULP_CLASS_HID_212cc = 0x212cc, + BNXT_ULP_CLASS_HID_21888 = 0x21888, + BNXT_ULP_CLASS_HID_22d84 = 0x22d84, BNXT_ULP_CLASS_HID_25340 = 0x25340, - BNXT_ULP_CLASS_HID_2dc40 = 0x2dc40, - BNXT_ULP_CLASS_HID_34940 = 0x34940, - BNXT_ULP_CLASS_HID_39734 = 0x39734, - BNXT_ULP_CLASS_HID_22c34 = 0x22c34, - BNXT_ULP_CLASS_HID_2d934 = 0x2d934, - BNXT_ULP_CLASS_HID_34234 = 0x34234, - BNXT_ULP_CLASS_HID_393e8 = 0x393e8, - BNXT_ULP_CLASS_HID_240e4 = 0x240e4, - BNXT_ULP_CLASS_HID_2cde4 = 0x2cde4, - BNXT_ULP_CLASS_HID_31bd8 = 0x31bd8, - BNXT_ULP_CLASS_HID_384d8 = 0x384d8, - BNXT_ULP_CLASS_HID_23de0 = 0x23de0, - BNXT_ULP_CLASS_HID_2a6e0 = 0x2a6e0, + BNXT_ULP_CLASS_HID_23720 = 0x23720, + BNXT_ULP_CLASS_HID_23d1c = 0x23d1c, + BNXT_ULP_CLASS_HID_636d4 = 0x636d4, + BNXT_ULP_CLASS_HID_63c90 = 0x63c90, + BNXT_ULP_CLASS_HID_60070 = 0x60070, + BNXT_ULP_CLASS_HID_6062c = 0x6062c, + BNXT_ULP_CLASS_HID_65b28 = 0x65b28, + BNXT_ULP_CLASS_HID_640e4 = 0x640e4, + BNXT_ULP_CLASS_HID_624c4 = 0x624c4, + BNXT_ULP_CLASS_HID_62a80 = 0x62a80, + BNXT_ULP_CLASS_HID_605e4 = 0x605e4, + BNXT_ULP_CLASS_HID_60ba0 = 0x60ba0, + BNXT_ULP_CLASS_HID_64acc = 0x64acc, + BNXT_ULP_CLASS_HID_6157c = 0x6157c, + BNXT_ULP_CLASS_HID_62678 = 0x62678, + BNXT_ULP_CLASS_HID_62c34 = 0x62c34, + BNXT_ULP_CLASS_HID_63014 = 0x63014, + BNXT_ULP_CLASS_HID_639d0 = 0x639d0, BNXT_ULP_CLASS_HID_353e0 = 0x353e0, - BNXT_ULP_CLASS_HID_3dce0 = 0x3dce0, - BNXT_ULP_CLASS_HID_20930 = 0x20930, - BNXT_ULP_CLASS_HID_2b230 = 0x2b230, + BNXT_ULP_CLASS_HID_359dc = 0x359dc, + BNXT_ULP_CLASS_HID_33dbc = 0x33dbc, + BNXT_ULP_CLASS_HID_32378 = 0x32378, + BNXT_ULP_CLASS_HID_31928 = 0x31928, + BNXT_ULP_CLASS_HID_31ee4 = 0x31ee4, + BNXT_ULP_CLASS_HID_35e10 = 0x35e10, + BNXT_ULP_CLASS_HID_347cc = 0x347cc, BNXT_ULP_CLASS_HID_33f30 = 0x33f30, - BNXT_ULP_CLASS_HID_3a830 = 0x3a830, - BNXT_ULP_CLASS_HID_205e4 = 0x205e4, - BNXT_ULP_CLASS_HID_28ee4 = 0x28ee4, - BNXT_ULP_CLASS_HID_33be4 = 0x33be4, - BNXT_ULP_CLASS_HID_3a4e4 = 0x3a4e4, - BNXT_ULP_CLASS_HID_236d4 = 0x236d4, - BNXT_ULP_CLASS_HID_2a3d4 = 0x2a3d4, - BNXT_ULP_CLASS_HID_32cd4 = 0x32cd4, - BNXT_ULP_CLASS_HID_3d9d4 = 0x3d9d4, - BNXT_ULP_CLASS_HID_25e74 = 0x25e74, + BNXT_ULP_CLASS_HID_324ec = 0x324ec, + BNXT_ULP_CLASS_HID_308cc = 0x308cc, + BNXT_ULP_CLASS_HID_30e88 = 0x30e88, + BNXT_ULP_CLASS_HID_34384 = 0x34384, + BNXT_ULP_CLASS_HID_34940 = 0x34940, + BNXT_ULP_CLASS_HID_32d20 = 0x32d20, + BNXT_ULP_CLASS_HID_3531c = 0x3531c, + BNXT_ULP_CLASS_HID_72cd4 = 0x72cd4, + BNXT_ULP_CLASS_HID_75290 = 0x75290, + BNXT_ULP_CLASS_HID_73670 = 0x73670, + BNXT_ULP_CLASS_HID_73c2c = 0x73c2c, + BNXT_ULP_CLASS_HID_7121c = 0x7121c, + BNXT_ULP_CLASS_HID_71bd8 = 0x71bd8, + BNXT_ULP_CLASS_HID_75ac4 = 0x75ac4, + BNXT_ULP_CLASS_HID_74080 = 0x74080, + BNXT_ULP_CLASS_HID_73be4 = 0x73be4, + BNXT_ULP_CLASS_HID_721a0 = 0x721a0, + BNXT_ULP_CLASS_HID_70580 = 0x70580, + BNXT_ULP_CLASS_HID_70b7c = 0x70b7c, + BNXT_ULP_CLASS_HID_75c78 = 0x75c78, + BNXT_ULP_CLASS_HID_74234 = 0x74234, + BNXT_ULP_CLASS_HID_72614 = 0x72614, + BNXT_ULP_CLASS_HID_72fd0 = 0x72fd0, + BNXT_ULP_CLASS_HID_2a6e0 = 0x2a6e0, + BNXT_ULP_CLASS_HID_2acdc = 0x2acdc, + BNXT_ULP_CLASS_HID_2b0bc = 0x2b0bc, + BNXT_ULP_CLASS_HID_2b678 = 0x2b678, BNXT_ULP_CLASS_HID_2cb74 = 0x2cb74, - BNXT_ULP_CLASS_HID_31928 = 0x31928, - BNXT_ULP_CLASS_HID_38228 = 0x38228, - BNXT_ULP_CLASS_HID_22d84 = 0x22d84, + BNXT_ULP_CLASS_HID_295e4 = 0x295e4, + BNXT_ULP_CLASS_HID_2d510 = 0x2d510, + BNXT_ULP_CLASS_HID_2dacc = 0x2dacc, + BNXT_ULP_CLASS_HID_2b230 = 0x2b230, + BNXT_ULP_CLASS_HID_2bbec = 0x2bbec, + BNXT_ULP_CLASS_HID_29fcc = 0x29fcc, + BNXT_ULP_CLASS_HID_28588 = 0x28588, BNXT_ULP_CLASS_HID_2d684 = 0x2d684, - BNXT_ULP_CLASS_HID_34384 = 0x34384, + BNXT_ULP_CLASS_HID_2dc40 = 0x2dc40, + BNXT_ULP_CLASS_HID_2a020 = 0x2a020, + BNXT_ULP_CLASS_HID_2a61c = 0x2a61c, + BNXT_ULP_CLASS_HID_6a3d4 = 0x6a3d4, + BNXT_ULP_CLASS_HID_6a990 = 0x6a990, + BNXT_ULP_CLASS_HID_68d70 = 0x68d70, + BNXT_ULP_CLASS_HID_6b32c = 0x6b32c, + BNXT_ULP_CLASS_HID_6c428 = 0x6c428, + BNXT_ULP_CLASS_HID_6cde4 = 0x6cde4, + BNXT_ULP_CLASS_HID_6d1c4 = 0x6d1c4, + BNXT_ULP_CLASS_HID_6d780 = 0x6d780, + BNXT_ULP_CLASS_HID_68ee4 = 0x68ee4, + BNXT_ULP_CLASS_HID_6b4a0 = 0x6b4a0, + BNXT_ULP_CLASS_HID_69880 = 0x69880, + BNXT_ULP_CLASS_HID_69e7c = 0x69e7c, + BNXT_ULP_CLASS_HID_6d378 = 0x6d378, + BNXT_ULP_CLASS_HID_6d934 = 0x6d934, + BNXT_ULP_CLASS_HID_6bd14 = 0x6bd14, + BNXT_ULP_CLASS_HID_6a2d0 = 0x6a2d0, + BNXT_ULP_CLASS_HID_3dce0 = 0x3dce0, + BNXT_ULP_CLASS_HID_3c2dc = 0x3c2dc, + BNXT_ULP_CLASS_HID_3a6bc = 0x3a6bc, + BNXT_ULP_CLASS_HID_3ac78 = 0x3ac78, + BNXT_ULP_CLASS_HID_38228 = 0x38228, + BNXT_ULP_CLASS_HID_38be4 = 0x38be4, + BNXT_ULP_CLASS_HID_3cb10 = 0x3cb10, + BNXT_ULP_CLASS_HID_39580 = 0x39580, + BNXT_ULP_CLASS_HID_3a830 = 0x3a830, + BNXT_ULP_CLASS_HID_3d1ec = 0x3d1ec, + BNXT_ULP_CLASS_HID_3b5cc = 0x3b5cc, + BNXT_ULP_CLASS_HID_3bb88 = 0x3bb88, BNXT_ULP_CLASS_HID_39178 = 0x39178, - BNXT_ULP_CLASS_HID_22678 = 0x22678, - BNXT_ULP_CLASS_HID_2d378 = 0x2d378, - BNXT_ULP_CLASS_HID_35c78 = 0x35c78, - BNXT_ULP_CLASS_HID_3c978 = 0x3c978, - BNXT_ULP_CLASS_HID_25b28 = 0x25b28, - BNXT_ULP_CLASS_HID_2c428 = 0x2c428, - BNXT_ULP_CLASS_HID_3121c = 0x3121c, - BNXT_ULP_CLASS_HID_39f1c = 0x39f1c, + BNXT_ULP_CLASS_HID_39734 = 0x39734, + BNXT_ULP_CLASS_HID_3d620 = 0x3d620, + BNXT_ULP_CLASS_HID_3dc1c = 0x3dc1c, + BNXT_ULP_CLASS_HID_7d9d4 = 0x7d9d4, + BNXT_ULP_CLASS_HID_7df90 = 0x7df90, + BNXT_ULP_CLASS_HID_7a370 = 0x7a370, + BNXT_ULP_CLASS_HID_7a92c = 0x7a92c, + BNXT_ULP_CLASS_HID_79f1c = 0x79f1c, + BNXT_ULP_CLASS_HID_784d8 = 0x784d8, + BNXT_ULP_CLASS_HID_7c7c4 = 0x7c7c4, + BNXT_ULP_CLASS_HID_7cd80 = 0x7cd80, + BNXT_ULP_CLASS_HID_7a4e4 = 0x7a4e4, + BNXT_ULP_CLASS_HID_7aaa0 = 0x7aaa0, + BNXT_ULP_CLASS_HID_78e80 = 0x78e80, + BNXT_ULP_CLASS_HID_7b47c = 0x7b47c, + BNXT_ULP_CLASS_HID_7c978 = 0x7c978, + BNXT_ULP_CLASS_HID_793e8 = 0x793e8, + BNXT_ULP_CLASS_HID_7d314 = 0x7d314, + BNXT_ULP_CLASS_HID_7d8d0 = 0x7d8d0, + BNXT_ULP_CLASS_HID_9ad8 = 0x9ad8, + BNXT_ULP_CLASS_HID_80e4 = 0x80e4, + BNXT_ULP_CLASS_HID_c3f0 = 0xc3f0, + BNXT_ULP_CLASS_HID_c9bc = 0xc9bc, + BNXT_ULP_CLASS_HID_bf4c = 0xbf4c, + BNXT_ULP_CLASS_HID_a508 = 0xa508, + BNXT_ULP_CLASS_HID_8928 = 0x8928, + BNXT_ULP_CLASS_HID_8ef4 = 0x8ef4, + BNXT_ULP_CLASS_HID_497ec = 0x497ec, + BNXT_ULP_CLASS_HID_49da8 = 0x49da8, + BNXT_ULP_CLASS_HID_4dc84 = 0x4dc84, + BNXT_ULP_CLASS_HID_4c240 = 0x4c240, + BNXT_ULP_CLASS_HID_4b810 = 0x4b810, + BNXT_ULP_CLASS_HID_4a1dc = 0x4a1dc, + BNXT_ULP_CLASS_HID_485fc = 0x485fc, + BNXT_ULP_CLASS_HID_48bb8 = 0x48bb8, + BNXT_ULP_CLASS_HID_1b0d8 = 0x1b0d8, + BNXT_ULP_CLASS_HID_1b6e4 = 0x1b6e4, + BNXT_ULP_CLASS_HID_19a84 = 0x19a84, + BNXT_ULP_CLASS_HID_18040 = 0x18040, + BNXT_ULP_CLASS_HID_1d54c = 0x1d54c, + BNXT_ULP_CLASS_HID_1db08 = 0x1db08, + BNXT_ULP_CLASS_HID_1bf28 = 0x1bf28, + BNXT_ULP_CLASS_HID_1a4f4 = 0x1a4f4, + BNXT_ULP_CLASS_HID_58dec = 0x58dec, + BNXT_ULP_CLASS_HID_5b3a8 = 0x5b3a8, + BNXT_ULP_CLASS_HID_59748 = 0x59748, + BNXT_ULP_CLASS_HID_59d14 = 0x59d14, + BNXT_ULP_CLASS_HID_5ae10 = 0x5ae10, + BNXT_ULP_CLASS_HID_5d7dc = 0x5d7dc, + BNXT_ULP_CLASS_HID_5bbfc = 0x5bbfc, + BNXT_ULP_CLASS_HID_5a1b8 = 0x5a1b8, + BNXT_ULP_CLASS_HID_c158 = 0xc158, + BNXT_ULP_CLASS_HID_c764 = 0xc764, + BNXT_ULP_CLASS_HID_c670 = 0xc670, + BNXT_ULP_CLASS_HID_d0c0 = 0xd0c0, + BNXT_ULP_CLASS_HID_e5cc = 0xe5cc, + BNXT_ULP_CLASS_HID_eb88 = 0xeb88, + BNXT_ULP_CLASS_HID_cfa8 = 0xcfa8, + BNXT_ULP_CLASS_HID_f574 = 0xf574, + BNXT_ULP_CLASS_HID_4da6c = 0x4da6c, + BNXT_ULP_CLASS_HID_4c028 = 0x4c028, + BNXT_ULP_CLASS_HID_4c304 = 0x4c304, + BNXT_ULP_CLASS_HID_4c8c0 = 0x4c8c0, + BNXT_ULP_CLASS_HID_4fe90 = 0x4fe90, + BNXT_ULP_CLASS_HID_4e45c = 0x4e45c, + BNXT_ULP_CLASS_HID_4c87c = 0x4c87c, + BNXT_ULP_CLASS_HID_4ce38 = 0x4ce38, + BNXT_ULP_CLASS_HID_1f758 = 0x1f758, + BNXT_ULP_CLASS_HID_1fd64 = 0x1fd64, + BNXT_ULP_CLASS_HID_1c104 = 0x1c104, + BNXT_ULP_CLASS_HID_1c6c0 = 0x1c6c0, + BNXT_ULP_CLASS_HID_1dbcc = 0x1dbcc, + BNXT_ULP_CLASS_HID_1c188 = 0x1c188, + BNXT_ULP_CLASS_HID_1e5a8 = 0x1e5a8, + BNXT_ULP_CLASS_HID_1eb74 = 0x1eb74, + BNXT_ULP_CLASS_HID_5f06c = 0x5f06c, + BNXT_ULP_CLASS_HID_5f628 = 0x5f628, + BNXT_ULP_CLASS_HID_5ddc8 = 0x5ddc8, + BNXT_ULP_CLASS_HID_5c394 = 0x5c394, + BNXT_ULP_CLASS_HID_5d490 = 0x5d490, + BNXT_ULP_CLASS_HID_5da5c = 0x5da5c, + BNXT_ULP_CLASS_HID_5fe7c = 0x5fe7c, + BNXT_ULP_CLASS_HID_5e438 = 0x5e438, + BNXT_ULP_CLASS_HID_bc18 = 0xbc18, + BNXT_ULP_CLASS_HID_a224 = 0xa224, + BNXT_ULP_CLASS_HID_e530 = 0xe530, + BNXT_ULP_CLASS_HID_eafc = 0xeafc, + BNXT_ULP_CLASS_HID_a08c = 0xa08c, + BNXT_ULP_CLASS_HID_a648 = 0xa648, + BNXT_ULP_CLASS_HID_aa68 = 0xaa68, + BNXT_ULP_CLASS_HID_b034 = 0xb034, + BNXT_ULP_CLASS_HID_4b92c = 0x4b92c, + BNXT_ULP_CLASS_HID_4bee8 = 0x4bee8, + BNXT_ULP_CLASS_HID_4e1c4 = 0x4e1c4, + BNXT_ULP_CLASS_HID_4e780 = 0x4e780, + BNXT_ULP_CLASS_HID_4bd50 = 0x4bd50, + BNXT_ULP_CLASS_HID_4a31c = 0x4a31c, + BNXT_ULP_CLASS_HID_4a73c = 0x4a73c, + BNXT_ULP_CLASS_HID_4acf8 = 0x4acf8, + BNXT_ULP_CLASS_HID_1b218 = 0x1b218, + BNXT_ULP_CLASS_HID_1b824 = 0x1b824, + BNXT_ULP_CLASS_HID_1bfc4 = 0x1bfc4, + BNXT_ULP_CLASS_HID_1a580 = 0x1a580, + BNXT_ULP_CLASS_HID_1f68c = 0x1f68c, + BNXT_ULP_CLASS_HID_1fc48 = 0x1fc48, + BNXT_ULP_CLASS_HID_1a068 = 0x1a068, + BNXT_ULP_CLASS_HID_1a634 = 0x1a634, + BNXT_ULP_CLASS_HID_5af2c = 0x5af2c, + BNXT_ULP_CLASS_HID_5b4e8 = 0x5b4e8, + BNXT_ULP_CLASS_HID_5b888 = 0x5b888, + BNXT_ULP_CLASS_HID_5be54 = 0x5be54, + BNXT_ULP_CLASS_HID_5f350 = 0x5f350, + BNXT_ULP_CLASS_HID_5f91c = 0x5f91c, + BNXT_ULP_CLASS_HID_5bd3c = 0x5bd3c, + BNXT_ULP_CLASS_HID_5a2f8 = 0x5a2f8, + BNXT_ULP_CLASS_HID_e298 = 0xe298, + BNXT_ULP_CLASS_HID_e8a4 = 0xe8a4, + BNXT_ULP_CLASS_HID_ebb0 = 0xebb0, + BNXT_ULP_CLASS_HID_f200 = 0xf200, + BNXT_ULP_CLASS_HID_e70c = 0xe70c, + BNXT_ULP_CLASS_HID_ecc8 = 0xecc8, + BNXT_ULP_CLASS_HID_f0e8 = 0xf0e8, + BNXT_ULP_CLASS_HID_f6b4 = 0xf6b4, + BNXT_ULP_CLASS_HID_4ffac = 0x4ffac, + BNXT_ULP_CLASS_HID_4e568 = 0x4e568, + BNXT_ULP_CLASS_HID_4e444 = 0x4e444, + BNXT_ULP_CLASS_HID_4ea00 = 0x4ea00, + BNXT_ULP_CLASS_HID_4e3d0 = 0x4e3d0, + BNXT_ULP_CLASS_HID_4e99c = 0x4e99c, + BNXT_ULP_CLASS_HID_4edbc = 0x4edbc, + BNXT_ULP_CLASS_HID_4f378 = 0x4f378, + BNXT_ULP_CLASS_HID_1f898 = 0x1f898, + BNXT_ULP_CLASS_HID_1fea4 = 0x1fea4, + BNXT_ULP_CLASS_HID_1e244 = 0x1e244, + BNXT_ULP_CLASS_HID_1e800 = 0x1e800, + BNXT_ULP_CLASS_HID_1fd0c = 0x1fd0c, + BNXT_ULP_CLASS_HID_1e2c8 = 0x1e2c8, + BNXT_ULP_CLASS_HID_1e6e8 = 0x1e6e8, + BNXT_ULP_CLASS_HID_1ecb4 = 0x1ecb4, + BNXT_ULP_CLASS_HID_5f5ac = 0x5f5ac, + BNXT_ULP_CLASS_HID_5fb68 = 0x5fb68, + BNXT_ULP_CLASS_HID_5ff08 = 0x5ff08, + BNXT_ULP_CLASS_HID_5e4d4 = 0x5e4d4, + BNXT_ULP_CLASS_HID_5f9d0 = 0x5f9d0, + BNXT_ULP_CLASS_HID_5ff9c = 0x5ff9c, + BNXT_ULP_CLASS_HID_5e3bc = 0x5e3bc, + BNXT_ULP_CLASS_HID_5e978 = 0x5e978, + BNXT_ULP_CLASS_HID_34f6 = 0x34f6, + BNXT_ULP_CLASS_HID_3a3a = 0x3a3a, + BNXT_ULP_CLASS_HID_541e = 0x541e, + BNXT_ULP_CLASS_HID_5a22 = 0x5a22, + BNXT_ULP_CLASS_HID_34fe = 0x34fe, + BNXT_ULP_CLASS_HID_3a32 = 0x3a32, + BNXT_ULP_CLASS_HID_4a42 = 0x4a42, + BNXT_ULP_CLASS_HID_14d2 = 0x14d2, + BNXT_ULP_CLASS_HID_34c8 = 0x34c8, + BNXT_ULP_CLASS_HID_3a04 = 0x3a04, + BNXT_ULP_CLASS_HID_1e64 = 0x1e64, + BNXT_ULP_CLASS_HID_07a0 = 0x07a0, + BNXT_ULP_CLASS_HID_595c = 0x595c, + BNXT_ULP_CLASS_HID_5e98 = 0x5e98, + BNXT_ULP_CLASS_HID_22f8 = 0x22f8, + BNXT_ULP_CLASS_HID_2834 = 0x2834, + BNXT_ULP_CLASS_HID_0398 = 0x0398, + BNXT_ULP_CLASS_HID_09d4 = 0x09d4, + BNXT_ULP_CLASS_HID_48c0 = 0x48c0, + BNXT_ULP_CLASS_HID_1370 = 0x1370, + BNXT_ULP_CLASS_HID_246c = 0x246c, + BNXT_ULP_CLASS_HID_2da8 = 0x2da8, + BNXT_ULP_CLASS_HID_3188 = 0x3188, + BNXT_ULP_CLASS_HID_37c4 = 0x37c4, + BNXT_ULP_CLASS_HID_34f0 = 0x34f0, + BNXT_ULP_CLASS_HID_3a3c = 0x3a3c, + BNXT_ULP_CLASS_HID_1e5c = 0x1e5c, + BNXT_ULP_CLASS_HID_0798 = 0x0798, + BNXT_ULP_CLASS_HID_5964 = 0x5964, + BNXT_ULP_CLASS_HID_5ea0 = 0x5ea0, + BNXT_ULP_CLASS_HID_22c0 = 0x22c0, + BNXT_ULP_CLASS_HID_280c = 0x280c, + BNXT_ULP_CLASS_HID_43104 = 0x43104, + BNXT_ULP_CLASS_HID_43740 = 0x43740, + BNXT_ULP_CLASS_HID_41b60 = 0x41b60, + BNXT_ULP_CLASS_HID_400ac = 0x400ac, + BNXT_ULP_CLASS_HID_455a8 = 0x455a8, + BNXT_ULP_CLASS_HID_45bf4 = 0x45bf4, + BNXT_ULP_CLASS_HID_43f14 = 0x43f14, + BNXT_ULP_CLASS_HID_42550 = 0x42550, + BNXT_ULP_CLASS_HID_34d6 = 0x34d6, + BNXT_ULP_CLASS_HID_3a1a = 0x3a1a, + BNXT_ULP_CLASS_HID_543e = 0x543e, + BNXT_ULP_CLASS_HID_5a02 = 0x5a02, + BNXT_ULP_CLASS_HID_34de = 0x34de, + BNXT_ULP_CLASS_HID_3a12 = 0x3a12, + BNXT_ULP_CLASS_HID_4a62 = 0x4a62, + BNXT_ULP_CLASS_HID_14f2 = 0x14f2, + BNXT_ULP_CLASS_HID_34b6 = 0x34b6, + BNXT_ULP_CLASS_HID_3a7a = 0x3a7a, + BNXT_ULP_CLASS_HID_545e = 0x545e, + BNXT_ULP_CLASS_HID_5a62 = 0x5a62, + BNXT_ULP_CLASS_HID_34be = 0x34be, + BNXT_ULP_CLASS_HID_3a72 = 0x3a72, + BNXT_ULP_CLASS_HID_4a02 = 0x4a02, + BNXT_ULP_CLASS_HID_1492 = 0x1492, + BNXT_ULP_CLASS_HID_34a8 = 0x34a8, + BNXT_ULP_CLASS_HID_3a64 = 0x3a64, + BNXT_ULP_CLASS_HID_1e04 = 0x1e04, + BNXT_ULP_CLASS_HID_07c0 = 0x07c0, + BNXT_ULP_CLASS_HID_593c = 0x593c, + BNXT_ULP_CLASS_HID_5ef8 = 0x5ef8, + BNXT_ULP_CLASS_HID_2298 = 0x2298, + BNXT_ULP_CLASS_HID_2854 = 0x2854, + BNXT_ULP_CLASS_HID_03f8 = 0x03f8, + BNXT_ULP_CLASS_HID_09b4 = 0x09b4, + BNXT_ULP_CLASS_HID_48a0 = 0x48a0, + BNXT_ULP_CLASS_HID_1310 = 0x1310, + BNXT_ULP_CLASS_HID_240c = 0x240c, + BNXT_ULP_CLASS_HID_2dc8 = 0x2dc8, + BNXT_ULP_CLASS_HID_31e8 = 0x31e8, + BNXT_ULP_CLASS_HID_37a4 = 0x37a4, + BNXT_ULP_CLASS_HID_34d0 = 0x34d0, + BNXT_ULP_CLASS_HID_3a1c = 0x3a1c, + BNXT_ULP_CLASS_HID_1e7c = 0x1e7c, + BNXT_ULP_CLASS_HID_07b8 = 0x07b8, + BNXT_ULP_CLASS_HID_5944 = 0x5944, + BNXT_ULP_CLASS_HID_5e80 = 0x5e80, + BNXT_ULP_CLASS_HID_22e0 = 0x22e0, + BNXT_ULP_CLASS_HID_282c = 0x282c, + BNXT_ULP_CLASS_HID_43124 = 0x43124, + BNXT_ULP_CLASS_HID_43760 = 0x43760, + BNXT_ULP_CLASS_HID_41b40 = 0x41b40, + BNXT_ULP_CLASS_HID_4008c = 0x4008c, + BNXT_ULP_CLASS_HID_45588 = 0x45588, + BNXT_ULP_CLASS_HID_45bd4 = 0x45bd4, + BNXT_ULP_CLASS_HID_43f34 = 0x43f34, + BNXT_ULP_CLASS_HID_42570 = 0x42570, BNXT_ULP_CLASS_HID_3488 = 0x3488, BNXT_ULP_CLASS_HID_3a44 = 0x3a44, - BNXT_ULP_CLASS_HID_0994 = 0x0994, - BNXT_ULP_CLASS_HID_5ed8 = 0x5ed8, - BNXT_ULP_CLASS_HID_2de8 = 0x2de8, + BNXT_ULP_CLASS_HID_1e24 = 0x1e24, BNXT_ULP_CLASS_HID_07e0 = 0x07e0, - BNXT_ULP_CLASS_HID_1330 = 0x1330, + BNXT_ULP_CLASS_HID_591c = 0x591c, + BNXT_ULP_CLASS_HID_5ed8 = 0x5ed8, + BNXT_ULP_CLASS_HID_22b8 = 0x22b8, BNXT_ULP_CLASS_HID_2874 = 0x2874, - BNXT_ULP_CLASS_HID_3784 = 0x3784, BNXT_ULP_CLASS_HID_03d8 = 0x03d8, - BNXT_ULP_CLASS_HID_591c = 0x591c, - BNXT_ULP_CLASS_HID_242c = 0x242c, - BNXT_ULP_CLASS_HID_1e24 = 0x1e24, + BNXT_ULP_CLASS_HID_0994 = 0x0994, BNXT_ULP_CLASS_HID_4880 = 0x4880, - BNXT_ULP_CLASS_HID_22b8 = 0x22b8, - BNXT_ULP_CLASS_HID_31c8 = 0x31c8 + BNXT_ULP_CLASS_HID_1330 = 0x1330, + BNXT_ULP_CLASS_HID_242c = 0x242c, + BNXT_ULP_CLASS_HID_2de8 = 0x2de8, + BNXT_ULP_CLASS_HID_31c8 = 0x31c8, + BNXT_ULP_CLASS_HID_3784 = 0x3784, + BNXT_ULP_CLASS_HID_34b0 = 0x34b0, + BNXT_ULP_CLASS_HID_3a7c = 0x3a7c, + BNXT_ULP_CLASS_HID_1e1c = 0x1e1c, + BNXT_ULP_CLASS_HID_07d8 = 0x07d8, + BNXT_ULP_CLASS_HID_5924 = 0x5924, + BNXT_ULP_CLASS_HID_5ee0 = 0x5ee0, + BNXT_ULP_CLASS_HID_2280 = 0x2280, + BNXT_ULP_CLASS_HID_284c = 0x284c, + BNXT_ULP_CLASS_HID_43144 = 0x43144, + BNXT_ULP_CLASS_HID_43700 = 0x43700, + BNXT_ULP_CLASS_HID_41b20 = 0x41b20, + BNXT_ULP_CLASS_HID_400ec = 0x400ec, + BNXT_ULP_CLASS_HID_455e8 = 0x455e8, + BNXT_ULP_CLASS_HID_45bb4 = 0x45bb4, + BNXT_ULP_CLASS_HID_43f54 = 0x43f54, + BNXT_ULP_CLASS_HID_42510 = 0x42510 }; enum bnxt_ulp_act_hid { @@ -5095,11 +5693,8 @@ enum bnxt_ulp_act_hid { }; enum bnxt_ulp_df_tpl { - BNXT_ULP_DF_TPL_PORT_TO_VS = 3, - BNXT_ULP_DF_TPL_VS_TO_PORT = 4, - BNXT_ULP_DF_TPL_VFREP_TO_VF = 5, - BNXT_ULP_DF_TPL_VF_TO_VFREP = 6, - BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7 + BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3, + BNXT_ULP_DF_TPL_DEFAULT_VFR = 4 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h index f7dd91626a..3a3b609941 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ -/* date: Wed Dec 16 16:03:45 2020 */ +/* date: Wed Mar 3 12:15:37 2021 */ #ifndef ULP_HDR_FIELD_ENUMS_H_ #define ULP_HDR_FIELD_ENUMS_H_ @@ -19,6 +19,16 @@ enum bnxt_ulp_glb_hf { BNXT_ULP_GLB_HF_ID_I_ETH_TYPE, BNXT_ULP_GLB_HF_ID_T_GRE_VER, BNXT_ULP_GLB_HF_ID_T_GRE_PROTO_TYPE, + BNXT_ULP_GLB_HF_ID_O_ICMP_TYPE, + BNXT_ULP_GLB_HF_ID_I_ICMP_TYPE, + BNXT_ULP_GLB_HF_ID_O_ICMP_CODE, + BNXT_ULP_GLB_HF_ID_I_ICMP_CODE, + BNXT_ULP_GLB_HF_ID_O_ICMP_CSUM, + BNXT_ULP_GLB_HF_ID_I_ICMP_CSUM, + BNXT_ULP_GLB_HF_ID_O_ICMP_IDENT, + BNXT_ULP_GLB_HF_ID_I_ICMP_IDENT, + BNXT_ULP_GLB_HF_ID_O_ICMP_SEQ_NUM, + BNXT_ULP_GLB_HF_ID_I_ICMP_SEQ_NUM, BNXT_ULP_GLB_HF_ID_O_IPV4_VER, BNXT_ULP_GLB_HF_ID_I_IPV4_VER, BNXT_ULP_GLB_HF_ID_O_IPV4_TOS, @@ -55,16 +65,6 @@ enum bnxt_ulp_glb_hf { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR, BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR, BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR, - BNXT_ULP_GLB_HF_ID_O_L3_PROTO_ID, - BNXT_ULP_GLB_HF_ID_I_L3_PROTO_ID, - BNXT_ULP_GLB_HF_ID_O_L3_SRC_ADDR, - BNXT_ULP_GLB_HF_ID_I_L3_SRC_ADDR, - BNXT_ULP_GLB_HF_ID_O_L3_DST_ADDR, - BNXT_ULP_GLB_HF_ID_I_L3_DST_ADDR, - BNXT_ULP_GLB_HF_ID_O_L4_SRC_PORT, - BNXT_ULP_GLB_HF_ID_I_L4_SRC_PORT, - BNXT_ULP_GLB_HF_ID_O_L4_DST_PORT, - BNXT_ULP_GLB_HF_ID_I_L4_DST_PORT, BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT, BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT, BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT, @@ -115,16 +115,14 @@ enum bnxt_ulp_hf1_0_bitmask { BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 + BNXT_ULP_HF1_0_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 }; enum bnxt_ulp_hf1_1_bitmask { @@ -142,16 +140,7 @@ enum bnxt_ulp_hf1_1_bitmask { BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF1_1_BITMASK_O_TCP_URP = 0x0000010000000000 + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 }; enum bnxt_ulp_hf1_2_bitmask { @@ -160,20 +149,17 @@ enum bnxt_ulp_hf1_2_bitmask { BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_2_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF1_2_BITMASK_O_UDP_CSUM = 0x0000200000000000 + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 }; enum bnxt_ulp_hf1_3_bitmask { @@ -182,14 +168,19 @@ enum bnxt_ulp_hf1_3_bitmask { BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 }; enum bnxt_ulp_hf1_4_bitmask { @@ -223,18 +214,25 @@ enum bnxt_ulp_hf1_5_bitmask { BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM = 0x0000800000000000 + BNXT_ULP_HF1_5_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF1_5_BITMASK_O_TCP_URP = 0x0000010000000000 }; enum bnxt_ulp_hf1_6_bitmask { @@ -243,19 +241,18 @@ enum bnxt_ulp_hf1_6_bitmask { BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 + BNXT_ULP_HF1_6_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF1_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF1_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 }; enum bnxt_ulp_hf1_7_bitmask { @@ -264,28 +261,20 @@ enum bnxt_ulp_hf1_7_bitmask { BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF1_7_BITMASK_O_TCP_URP = 0x0000002000000000 + BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 }; enum bnxt_ulp_hf1_8_bitmask { @@ -297,20 +286,23 @@ enum bnxt_ulp_hf1_8_bitmask { BNXT_ULP_HF1_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF1_8_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF1_8_BITMASK_O_UDP_CSUM = 0x0000040000000000 + BNXT_ULP_HF1_8_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF1_8_BITMASK_O_TCP_URP = 0x0000008000000000 }; enum bnxt_ulp_hf1_9_bitmask { @@ -322,14 +314,25 @@ enum bnxt_ulp_hf1_9_bitmask { BNXT_ULP_HF1_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 + BNXT_ULP_HF1_9_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF1_9_BITMASK_O_TCP_URP = 0x0000002000000000 }; enum bnxt_ulp_hf1_10_bitmask { @@ -349,15 +352,10 @@ enum bnxt_ulp_hf1_10_bitmask { BNXT_ULP_HF1_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF1_10_BITMASK_O_TCP_URP = 0x0000008000000000 + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF1_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF1_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 }; enum bnxt_ulp_hf1_11_bitmask { @@ -369,18 +367,46 @@ enum bnxt_ulp_hf1_11_bitmask { BNXT_ULP_HF1_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF1_11_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF1_11_BITMASK_O_UDP_CSUM = 0x0000100000000000 + BNXT_ULP_HF1_11_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF1_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF1_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 +}; + +enum bnxt_ulp_hf1_12_bitmask { + BNXT_ULP_HF1_12_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF1_12_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF1_12_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF1_12_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF1_12_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF1_12_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF1_12_BITMASK_O_UDP_CSUM = 0x0000200000000000, + BNXT_ULP_HF1_12_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000, + BNXT_ULP_HF1_12_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000, + BNXT_ULP_HF1_12_BITMASK_T_VXLAN_VNI = 0x0000040000000000, + BNXT_ULP_HF1_12_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000 }; enum bnxt_ulp_hf2_0_bitmask { @@ -389,16 +415,14 @@ enum bnxt_ulp_hf2_0_bitmask { BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 + BNXT_ULP_HF2_0_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 }; enum bnxt_ulp_hf2_1_bitmask { @@ -416,16 +440,7 @@ enum bnxt_ulp_hf2_1_bitmask { BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, BNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF2_1_BITMASK_O_TCP_URP = 0x0000010000000000 + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 }; enum bnxt_ulp_hf2_2_bitmask { @@ -434,20 +449,17 @@ enum bnxt_ulp_hf2_2_bitmask { BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF2_2_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF2_2_BITMASK_O_UDP_CSUM = 0x0000200000000000 + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 }; enum bnxt_ulp_hf2_3_bitmask { @@ -456,14 +468,19 @@ enum bnxt_ulp_hf2_3_bitmask { BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 }; enum bnxt_ulp_hf2_4_bitmask { @@ -497,18 +514,25 @@ enum bnxt_ulp_hf2_5_bitmask { BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF2_5_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF2_5_BITMASK_O_UDP_CSUM = 0x0000800000000000 + BNXT_ULP_HF2_5_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF2_5_BITMASK_O_TCP_URP = 0x0000010000000000 }; enum bnxt_ulp_hf2_6_bitmask { @@ -517,19 +541,18 @@ enum bnxt_ulp_hf2_6_bitmask { BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 + BNXT_ULP_HF2_6_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 }; enum bnxt_ulp_hf2_7_bitmask { @@ -538,28 +561,20 @@ enum bnxt_ulp_hf2_7_bitmask { BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF2_7_BITMASK_O_TCP_URP = 0x0000002000000000 + BNXT_ULP_HF2_7_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 }; enum bnxt_ulp_hf2_8_bitmask { @@ -571,20 +586,23 @@ enum bnxt_ulp_hf2_8_bitmask { BNXT_ULP_HF2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF2_8_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF2_8_BITMASK_O_UDP_CSUM = 0x0000040000000000 + BNXT_ULP_HF2_8_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF2_8_BITMASK_O_TCP_URP = 0x0000008000000000 }; enum bnxt_ulp_hf2_9_bitmask { @@ -596,14 +614,25 @@ enum bnxt_ulp_hf2_9_bitmask { BNXT_ULP_HF2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 + BNXT_ULP_HF2_9_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF2_9_BITMASK_O_TCP_URP = 0x0000002000000000 }; enum bnxt_ulp_hf2_10_bitmask { @@ -623,15 +652,10 @@ enum bnxt_ulp_hf2_10_bitmask { BNXT_ULP_HF2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF2_10_BITMASK_O_TCP_URP = 0x0000008000000000 + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 }; enum bnxt_ulp_hf2_11_bitmask { @@ -643,17 +667,20 @@ enum bnxt_ulp_hf2_11_bitmask { BNXT_ULP_HF2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF2_11_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF2_11_BITMASK_O_UDP_CSUM = 0x0000100000000000 + BNXT_ULP_HF2_11_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 }; + #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c deleted file mode 100644 index 08f0e25b47..0000000000 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c +++ /dev/null @@ -1,709 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom - * All rights reserved. - */ - -/* date: Tue Dec 1 17:07:12 2020 */ - -#include "ulp_template_db_enum.h" -#include "ulp_template_db_field.h" -#include "ulp_template_struct.h" -#include "ulp_template_db_tbl.h" - -/* Mapper templates for header act list */ -struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[] = { - /* act_tid: 1, stingray, ingress */ - [1] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 4, - .start_tbl_idx = 0, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 0, - .cond_nums = 0 } - } -}; - -struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = { - { /* act_tid: 1, stingray, table: int_flow_counter_tbl.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 0, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 0, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* act_tid: 1, stingray, table: int_vtag_encap_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 1, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12 - }, - { /* act_tid: 1, stingray, table: int_full_act_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 13, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - }, - { /* act_tid: 1, stingray, table: ext_full_act_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, - .execute_info = { - .cond_true_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 39, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - } -}; - -struct bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[] = { - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_COUNT - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN - } -}; - -struct bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[] = { - /* act_tid: 1, stingray, table: int_flow_counter_tbl.0 */ - { - .description = "count", - .field_bit_size = 64, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* act_tid: 1, stingray, table: int_vtag_encap_record.0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "ecv_l3_type", - .field_bit_size = 3, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "ecv_l2_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} - }, - { - .description = "ecv_custom_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "ecv_valid", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "vtag_tpid", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "vtag_pcp", - .field_bit_size = 3, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} - }, - { - .description = "spare", - .field_bit_size = 80, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* act_tid: 1, stingray, table: int_full_act_record.0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST - }, - { - .description = "meter_id", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_SR_SYM_DECAP_FUNC_THRU_TUN}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_SR_SYM_DECAP_FUNC_NONE} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} - }, - { - .description = "meter", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} - }, - { - .description = "hit", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* act_tid: 1, stingray, table: ext_full_act_record.0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} - }, - { - .description = "age_enable", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} - }, - { - .description = "flow_cntr_ext", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "encap_rec_int", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST - }, - { - .description = "meter_id", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} - }, - { - .description = "decap_func", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_SR_SYM_DECAP_FUNC_THRU_TUN}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_SR_SYM_DECAP_FUNC_NONE} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} - }, - { - .description = "meter", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} - } -}; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index fd4ceb226c..e9799d0b90 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Jan 29 11:27:48 2021 */ +/* date: Thu Mar 4 10:12:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -91,34 +91,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .num_buckets = 8, .hash_tbl_entries = 1024, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE - } -}; - -/* device tables */ -const struct bnxt_ulp_template_device_tbls ulp_template_stingray_tbls[] = { - [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { - .tmpl_list = ulp_stingray_class_tmpl_list, - .tmpl_list_size = ULP_STINGRAY_CLASS_TMPL_LIST_SIZE, - .tbl_list = ulp_stingray_class_tbl_list, - .tbl_list_size = ULP_STINGRAY_CLASS_TBL_LIST_SIZE, - .key_info_list = ulp_stingray_class_key_info_list, - .key_info_list_size = ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE, - .ident_list = ulp_stingray_class_ident_list, - .ident_list_size = ULP_STINGRAY_CLASS_IDENT_LIST_SIZE, - .cond_list = ulp_stingray_class_cond_list, - .cond_list_size = ULP_STINGRAY_CLASS_COND_LIST_SIZE, - .result_field_list = ulp_stingray_class_result_field_list, - .result_field_list_size = ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE }, - [BNXT_ULP_TEMPLATE_TYPE_ACTION] = { - .tmpl_list = ulp_stingray_act_tmpl_list, - .tmpl_list_size = ULP_STINGRAY_ACT_TMPL_LIST_SIZE, - .tbl_list = ulp_stingray_act_tbl_list, - .tbl_list_size = ULP_STINGRAY_ACT_TBL_LIST_SIZE, - .cond_list = ulp_stingray_act_cond_list, - .cond_list_size = ULP_STINGRAY_ACT_COND_LIST_SIZE, - .result_field_list = ulp_stingray_act_result_field_list, - .result_field_list_size = ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_PORT_TABLE", + .result_num_entries = 1024, + .result_num_bytes = 18, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PORT_TABLE", + .result_num_entries = 1024, + .result_num_bytes = 18, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; @@ -154,6 +146,32 @@ const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { } }; +/* device tables */ +const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = { + [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { + .tmpl_list = ulp_thor_class_tmpl_list, + .tmpl_list_size = ULP_THOR_CLASS_TMPL_LIST_SIZE, + .tbl_list = ulp_thor_class_tbl_list, + .tbl_list_size = ULP_THOR_CLASS_TBL_LIST_SIZE, + .key_info_list = ulp_thor_class_key_info_list, + .key_info_list_size = ULP_THOR_CLASS_KEY_INFO_LIST_SIZE, + .ident_list = ulp_thor_class_ident_list, + .ident_list_size = ULP_THOR_CLASS_IDENT_LIST_SIZE, + .cond_list = ulp_thor_class_cond_list, + .cond_list_size = ULP_THOR_CLASS_COND_LIST_SIZE, + .result_field_list = ulp_thor_class_result_field_list, + .result_field_list_size = ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE + }, + [BNXT_ULP_TEMPLATE_TYPE_ACTION] = { + .tmpl_list = ulp_thor_act_tmpl_list, + .tmpl_list_size = ULP_THOR_ACT_TMPL_LIST_SIZE, + .tbl_list = ulp_thor_act_tbl_list, + .tbl_list_size = ULP_THOR_ACT_TBL_LIST_SIZE, + .result_field_list = ulp_thor_act_result_field_list, + .result_field_list_size = ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE + } +}; + /* List of device specific parameters */ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { [BNXT_ULP_DEVICE_ID_WH_PLUS] = { @@ -173,17 +191,18 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { .packet_count_mask = 0xffffffff00000000, .byte_count_shift = 0, .packet_count_shift = 36, + .dynamic_pad_en = 0, .dev_tbls = ulp_template_wh_plus_tbls }, - [BNXT_ULP_DEVICE_ID_STINGRAY] = { - .description = "Stingray", + [BNXT_ULP_DEVICE_ID_THOR] = { + .description = "Thor", .byte_order = BNXT_ULP_BYTE_ORDER_LE, .encap_byte_swap = 1, .int_flow_db_num_entries = 16384, .ext_flow_db_num_entries = 32768, - .mark_db_lfid_entries = 65536, - .mark_db_gfid_entries = 65536, - .flow_count_db_entries = 16384, + .mark_db_lfid_entries = 0, + .mark_db_gfid_entries = 0, + .flow_count_db_entries = 0, .fdb_parent_flow_entries = 2, .num_resources_per_flow = 8, .num_phy_ports = 2, @@ -192,7 +211,16 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { .packet_count_mask = 0xffffffff00000000, .byte_count_shift = 0, .packet_count_shift = 36, - .dev_tbls = ulp_template_stingray_tbls + .dynamic_pad_en = 1, + .em_blk_size_bits = 100, + .em_blk_align_bits = 128, + .em_key_align_bytes = 80, + .wc_slice_width = 160, + .wc_max_slices = 4, + .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f}, + .wc_mod_list_max_size = 4, + .wc_ctl_size_bits = 32, + .dev_tbls = ulp_template_thor_tbls } }; @@ -248,11 +276,6 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { } }; -/* Lists global action records */ -uint32_t ulp_glb_template_tbl[] = { - BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC -}; - /* Provides act_bitmask */ struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = { [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | @@ -360,85 +383,76 @@ uint8_t ulp_glb_field_tbl[] = { [2050] = 2, [2052] = 3, [2054] = 4, - [2058] = 5, - [2060] = 6, - [2062] = 7, - [2064] = 8, - [2066] = 9, - [2068] = 10, - [2070] = 11, - [2072] = 12, - [2074] = 13, - [2076] = 14, + [2088] = 5, + [2090] = 6, + [2092] = 7, + [2094] = 8, + [2096] = 9, + [2098] = 10, + [2100] = 11, + [2102] = 12, [2176] = 0, [2177] = 1, [2178] = 2, [2180] = 3, [2182] = 4, - [2186] = 5, - [2188] = 6, - [2190] = 7, - [2192] = 8, - [2194] = 9, - [2196] = 10, - [2198] = 11, - [2200] = 12, - [2202] = 13, - [2204] = 14, - [2232] = 15, - [2234] = 16, - [2236] = 17, - [2238] = 18, - [2240] = 19, - [2242] = 20, - [2244] = 21, - [2246] = 22, - [2248] = 23, + [2196] = 5, + [2198] = 6, + [2200] = 7, + [2202] = 8, + [2204] = 9, + [2206] = 10, + [2208] = 11, + [2210] = 12, + [2212] = 13, + [2214] = 14, [2304] = 0, [2305] = 1, [2306] = 2, [2308] = 3, [2310] = 4, - [2314] = 5, - [2316] = 6, - [2318] = 7, - [2320] = 8, - [2322] = 9, - [2324] = 10, - [2326] = 11, - [2328] = 12, - [2330] = 13, - [2332] = 14, - [2378] = 15, - [2380] = 16, - [2382] = 17, - [2384] = 18, + [2344] = 8, + [2346] = 9, + [2348] = 10, + [2350] = 11, + [2352] = 12, + [2354] = 13, + [2356] = 14, + [2358] = 15, + [2386] = 5, + [2390] = 6, + [2394] = 7, [2432] = 0, [2433] = 1, [2434] = 2, [2436] = 3, [2438] = 4, - [2462] = 5, - [2464] = 6, - [2466] = 7, - [2468] = 8, - [2470] = 9, - [2472] = 10, - [2474] = 11, - [2476] = 12, + [2452] = 8, + [2454] = 9, + [2456] = 10, + [2458] = 11, + [2460] = 12, + [2462] = 13, + [2464] = 14, + [2466] = 15, + [2468] = 16, + [2470] = 17, + [2514] = 5, + [2518] = 6, + [2522] = 7, [2560] = 0, [2561] = 1, [2562] = 2, [2564] = 3, [2566] = 4, - [2590] = 5, - [2592] = 6, - [2594] = 7, - [2596] = 8, - [2598] = 9, - [2600] = 10, - [2602] = 11, - [2604] = 12, + [2600] = 5, + [2602] = 6, + [2604] = 7, + [2606] = 8, + [2608] = 9, + [2610] = 10, + [2612] = 11, + [2614] = 12, [2616] = 13, [2618] = 14, [2620] = 15, @@ -453,82 +467,83 @@ uint8_t ulp_glb_field_tbl[] = { [2690] = 2, [2692] = 3, [2694] = 4, - [2718] = 5, - [2720] = 6, - [2722] = 7, - [2724] = 8, - [2726] = 9, - [2728] = 10, - [2730] = 11, - [2732] = 12, - [2762] = 13, - [2764] = 14, - [2766] = 15, - [2768] = 16, + [2708] = 5, + [2710] = 6, + [2712] = 7, + [2714] = 8, + [2716] = 9, + [2718] = 10, + [2720] = 11, + [2722] = 12, + [2724] = 13, + [2726] = 14, + [2744] = 15, + [2746] = 16, + [2748] = 17, + [2750] = 18, + [2752] = 19, + [2754] = 20, + [2756] = 21, + [2758] = 22, + [2760] = 23, [2816] = 0, [2817] = 1, [2818] = 2, [2820] = 3, [2822] = 4, - [2826] = 8, - [2828] = 9, - [2830] = 10, - [2832] = 11, - [2834] = 12, - [2836] = 13, - [2838] = 14, - [2840] = 15, - [2842] = 16, - [2844] = 17, - [2898] = 5, - [2902] = 6, - [2906] = 7, + [2856] = 5, + [2858] = 6, + [2860] = 7, + [2862] = 8, + [2864] = 9, + [2866] = 10, + [2868] = 11, + [2870] = 12, + [2890] = 13, + [2892] = 14, + [2894] = 15, + [2896] = 16, [2944] = 0, [2945] = 1, [2946] = 2, [2948] = 3, [2950] = 4, - [2954] = 8, - [2956] = 9, - [2958] = 10, - [2960] = 11, - [2962] = 12, - [2964] = 13, - [2966] = 14, - [2968] = 15, - [2970] = 16, - [2972] = 17, - [3000] = 18, - [3002] = 19, - [3004] = 20, - [3006] = 21, - [3008] = 22, - [3010] = 23, - [3012] = 24, - [3014] = 25, - [3016] = 26, - [3026] = 5, - [3030] = 6, - [3034] = 7, + [2964] = 5, + [2966] = 6, + [2968] = 7, + [2970] = 8, + [2972] = 9, + [2974] = 10, + [2976] = 11, + [2978] = 12, + [2980] = 13, + [2982] = 14, + [3018] = 15, + [3020] = 16, + [3022] = 17, + [3024] = 18, [3072] = 0, [3073] = 1, [3074] = 2, [3076] = 3, [3078] = 4, - [3082] = 8, - [3084] = 9, - [3086] = 10, - [3088] = 11, - [3090] = 12, - [3092] = 13, - [3094] = 14, - [3096] = 15, - [3098] = 16, - [3100] = 17, - [3146] = 18, - [3148] = 19, - [3150] = 20, - [3152] = 21, + [3112] = 8, + [3114] = 9, + [3116] = 10, + [3118] = 11, + [3120] = 12, + [3122] = 13, + [3124] = 14, + [3126] = 15, + [3128] = 16, + [3130] = 17, + [3132] = 18, + [3134] = 19, + [3136] = 20, + [3138] = 21, + [3140] = 22, + [3142] = 23, + [3144] = 24, [3154] = 5, [3158] = 6, [3162] = 7, @@ -537,14 +552,25 @@ uint8_t ulp_glb_field_tbl[] = { [3202] = 2, [3204] = 3, [3206] = 4, - [3230] = 8, - [3232] = 9, - [3234] = 10, - [3236] = 11, - [3238] = 12, - [3240] = 13, - [3242] = 14, - [3244] = 15, + [3220] = 8, + [3222] = 9, + [3224] = 10, + [3226] = 11, + [3228] = 12, + [3230] = 13, + [3232] = 14, + [3234] = 15, + [3236] = 16, + [3238] = 17, + [3256] = 18, + [3258] = 19, + [3260] = 20, + [3262] = 21, + [3264] = 22, + [3266] = 23, + [3268] = 24, + [3270] = 25, + [3272] = 26, [3282] = 5, [3286] = 6, [3290] = 7, @@ -553,23 +579,18 @@ uint8_t ulp_glb_field_tbl[] = { [3330] = 2, [3332] = 3, [3334] = 4, - [3358] = 8, - [3360] = 9, - [3362] = 10, - [3364] = 11, - [3366] = 12, - [3368] = 13, - [3370] = 14, - [3372] = 15, - [3384] = 16, - [3386] = 17, - [3388] = 18, - [3390] = 19, - [3392] = 20, - [3394] = 21, - [3396] = 22, - [3398] = 23, - [3400] = 24, + [3368] = 8, + [3370] = 9, + [3372] = 10, + [3374] = 11, + [3376] = 12, + [3378] = 13, + [3380] = 14, + [3382] = 15, + [3402] = 16, + [3404] = 17, + [3406] = 18, + [3408] = 19, [3410] = 5, [3414] = 6, [3418] = 7, @@ -578,105 +599,121 @@ uint8_t ulp_glb_field_tbl[] = { [3458] = 2, [3460] = 3, [3462] = 4, - [3486] = 8, - [3488] = 9, - [3490] = 10, - [3492] = 11, - [3494] = 12, - [3496] = 13, - [3498] = 14, - [3500] = 15, - [3530] = 16, - [3532] = 17, - [3534] = 18, - [3536] = 19, + [3476] = 8, + [3478] = 9, + [3480] = 10, + [3482] = 11, + [3484] = 12, + [3486] = 13, + [3488] = 14, + [3490] = 15, + [3492] = 16, + [3494] = 17, + [3530] = 18, + [3532] = 19, + [3534] = 20, + [3536] = 21, [3538] = 5, [3542] = 6, [3546] = 7, + [3584] = 0, + [3585] = 1, + [3586] = 2, + [3588] = 3, + [3590] = 4, + [3604] = 5, + [3606] = 6, + [3608] = 7, + [3610] = 8, + [3612] = 9, + [3614] = 10, + [3616] = 11, + [3618] = 12, + [3620] = 13, + [3622] = 14, + [3658] = 15, + [3660] = 16, + [3662] = 17, + [3664] = 18, + [3678] = 19, + [3679] = 20, + [3680] = 21, + [3681] = 22, [4096] = 0, [4097] = 1, [4098] = 2, [4100] = 3, [4102] = 4, - [4106] = 5, - [4108] = 6, - [4110] = 7, - [4112] = 8, - [4114] = 9, - [4116] = 10, - [4118] = 11, - [4120] = 12, - [4122] = 13, - [4124] = 14, + [4136] = 5, + [4138] = 6, + [4140] = 7, + [4142] = 8, + [4144] = 9, + [4146] = 10, + [4148] = 11, + [4150] = 12, [4224] = 0, [4225] = 1, [4226] = 2, [4228] = 3, [4230] = 4, - [4234] = 5, - [4236] = 6, - [4238] = 7, - [4240] = 8, - [4242] = 9, - [4244] = 10, - [4246] = 11, - [4248] = 12, - [4250] = 13, - [4252] = 14, - [4280] = 15, - [4282] = 16, - [4284] = 17, - [4286] = 18, - [4288] = 19, - [4290] = 20, - [4292] = 21, - [4294] = 22, - [4296] = 23, + [4244] = 5, + [4246] = 6, + [4248] = 7, + [4250] = 8, + [4252] = 9, + [4254] = 10, + [4256] = 11, + [4258] = 12, + [4260] = 13, + [4262] = 14, [4352] = 0, [4353] = 1, [4354] = 2, [4356] = 3, [4358] = 4, - [4362] = 5, - [4364] = 6, - [4366] = 7, - [4368] = 8, - [4370] = 9, - [4372] = 10, - [4374] = 11, - [4376] = 12, - [4378] = 13, - [4380] = 14, - [4426] = 15, - [4428] = 16, - [4430] = 17, - [4432] = 18, + [4392] = 8, + [4394] = 9, + [4396] = 10, + [4398] = 11, + [4400] = 12, + [4402] = 13, + [4404] = 14, + [4406] = 15, + [4434] = 5, + [4438] = 6, + [4442] = 7, [4480] = 0, [4481] = 1, [4482] = 2, [4484] = 3, [4486] = 4, - [4510] = 5, - [4512] = 6, - [4514] = 7, - [4516] = 8, - [4518] = 9, - [4520] = 10, - [4522] = 11, - [4524] = 12, + [4500] = 8, + [4502] = 9, + [4504] = 10, + [4506] = 11, + [4508] = 12, + [4510] = 13, + [4512] = 14, + [4514] = 15, + [4516] = 16, + [4518] = 17, + [4562] = 5, + [4566] = 6, + [4570] = 7, [4608] = 0, [4609] = 1, [4610] = 2, [4612] = 3, [4614] = 4, - [4638] = 5, - [4640] = 6, - [4642] = 7, - [4644] = 8, - [4646] = 9, - [4648] = 10, - [4650] = 11, - [4652] = 12, + [4648] = 5, + [4650] = 6, + [4652] = 7, + [4654] = 8, + [4656] = 9, + [4658] = 10, + [4660] = 11, + [4662] = 12, [4664] = 13, [4666] = 14, [4668] = 15, @@ -691,82 +728,83 @@ uint8_t ulp_glb_field_tbl[] = { [4738] = 2, [4740] = 3, [4742] = 4, - [4766] = 5, - [4768] = 6, - [4770] = 7, - [4772] = 8, - [4774] = 9, - [4776] = 10, - [4778] = 11, - [4780] = 12, - [4810] = 13, - [4812] = 14, - [4814] = 15, - [4816] = 16, + [4756] = 5, + [4758] = 6, + [4760] = 7, + [4762] = 8, + [4764] = 9, + [4766] = 10, + [4768] = 11, + [4770] = 12, + [4772] = 13, + [4774] = 14, + [4792] = 15, + [4794] = 16, + [4796] = 17, + [4798] = 18, + [4800] = 19, + [4802] = 20, + [4804] = 21, + [4806] = 22, + [4808] = 23, [4864] = 0, [4865] = 1, [4866] = 2, [4868] = 3, [4870] = 4, - [4874] = 8, - [4876] = 9, - [4878] = 10, - [4880] = 11, - [4882] = 12, - [4884] = 13, - [4886] = 14, - [4888] = 15, - [4890] = 16, - [4892] = 17, - [4946] = 5, - [4950] = 6, - [4954] = 7, + [4904] = 5, + [4906] = 6, + [4908] = 7, + [4910] = 8, + [4912] = 9, + [4914] = 10, + [4916] = 11, + [4918] = 12, + [4938] = 13, + [4940] = 14, + [4942] = 15, + [4944] = 16, [4992] = 0, [4993] = 1, [4994] = 2, [4996] = 3, [4998] = 4, - [5002] = 8, - [5004] = 9, - [5006] = 10, - [5008] = 11, - [5010] = 12, - [5012] = 13, - [5014] = 14, - [5016] = 15, - [5018] = 16, - [5020] = 17, - [5048] = 18, - [5050] = 19, - [5052] = 20, - [5054] = 21, - [5056] = 22, - [5058] = 23, - [5060] = 24, - [5062] = 25, - [5064] = 26, - [5074] = 5, - [5078] = 6, - [5082] = 7, + [5012] = 5, + [5014] = 6, + [5016] = 7, + [5018] = 8, + [5020] = 9, + [5022] = 10, + [5024] = 11, + [5026] = 12, + [5028] = 13, + [5030] = 14, + [5066] = 15, + [5068] = 16, + [5070] = 17, + [5072] = 18, [5120] = 0, [5121] = 1, [5122] = 2, [5124] = 3, [5126] = 4, - [5130] = 8, - [5132] = 9, - [5134] = 10, - [5136] = 11, - [5138] = 12, - [5140] = 13, - [5142] = 14, - [5144] = 15, - [5146] = 16, - [5148] = 17, - [5194] = 18, - [5196] = 19, - [5198] = 20, - [5200] = 21, + [5160] = 8, + [5162] = 9, + [5164] = 10, + [5166] = 11, + [5168] = 12, + [5170] = 13, + [5172] = 14, + [5174] = 15, + [5176] = 16, + [5178] = 17, + [5180] = 18, + [5182] = 19, + [5184] = 20, + [5186] = 21, + [5188] = 22, + [5190] = 23, + [5192] = 24, [5202] = 5, [5206] = 6, [5210] = 7, @@ -775,14 +813,25 @@ uint8_t ulp_glb_field_tbl[] = { [5250] = 2, [5252] = 3, [5254] = 4, - [5278] = 8, - [5280] = 9, - [5282] = 10, - [5284] = 11, - [5286] = 12, - [5288] = 13, - [5290] = 14, - [5292] = 15, + [5268] = 8, + [5270] = 9, + [5272] = 10, + [5274] = 11, + [5276] = 12, + [5278] = 13, + [5280] = 14, + [5282] = 15, + [5284] = 16, + [5286] = 17, + [5304] = 18, + [5306] = 19, + [5308] = 20, + [5310] = 21, + [5312] = 22, + [5314] = 23, + [5316] = 24, + [5318] = 25, + [5320] = 26, [5330] = 5, [5334] = 6, [5338] = 7, @@ -791,23 +840,18 @@ uint8_t ulp_glb_field_tbl[] = { [5378] = 2, [5380] = 3, [5382] = 4, - [5406] = 8, - [5408] = 9, - [5410] = 10, - [5412] = 11, - [5414] = 12, - [5416] = 13, - [5418] = 14, - [5420] = 15, - [5432] = 16, - [5434] = 17, - [5436] = 18, - [5438] = 19, - [5440] = 20, - [5442] = 21, - [5444] = 22, - [5446] = 23, - [5448] = 24, + [5416] = 8, + [5418] = 9, + [5420] = 10, + [5422] = 11, + [5424] = 12, + [5426] = 13, + [5428] = 14, + [5430] = 15, + [5450] = 16, + [5452] = 17, + [5454] = 18, + [5456] = 19, [5458] = 5, [5462] = 6, [5466] = 7, @@ -816,18 +860,20 @@ uint8_t ulp_glb_field_tbl[] = { [5506] = 2, [5508] = 3, [5510] = 4, - [5534] = 8, - [5536] = 9, - [5538] = 10, - [5540] = 11, - [5542] = 12, - [5544] = 13, - [5546] = 14, - [5548] = 15, - [5578] = 16, - [5580] = 17, - [5582] = 18, - [5584] = 19, + [5524] = 8, + [5526] = 9, + [5528] = 10, + [5530] = 11, + [5532] = 12, + [5534] = 13, + [5536] = 14, + [5538] = 15, + [5540] = 16, + [5542] = 17, + [5578] = 18, + [5580] = 19, + [5582] = 20, + [5584] = 21, [5586] = 5, [5590] = 6, [5594] = 7 diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h index 07f9075de7..328520c319 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -57,6 +57,10 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[]; +extern struct bnxt_ulp_mapper_key_info ulp_stingray_act_key_info_list[]; + +extern struct bnxt_ulp_mapper_ident_info ulp_stingray_act_ident_list[]; + extern struct bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[]; @@ -66,5 +70,43 @@ bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[]; extern struct bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[]; +/* Thor template table declarations */ +extern struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[]; + +extern struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[]; + +extern struct +bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[]; + +extern struct +bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[]; + +extern struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[]; + +extern struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[]; + +extern struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[]; + +extern struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[]; + +extern struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[]; + +extern struct +bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[]; + +extern struct +bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[]; + +extern struct +bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[]; + +extern struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[]; + +extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[]; + +/* Global declarations */ extern uint8_t ulp_glb_field_tbl[]; + +extern struct +bnxt_ulp_shared_act_info ulp_shared_act_info[]; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c new file mode 100644 index 0000000000..d0d96f32d4 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2021 Broadcom + * All rights reserved. + */ + +/* date: Mon Feb 8 09:17:37 2021 */ + +#include "ulp_template_db_enum.h" +#include "ulp_template_db_field.h" +#include "ulp_template_struct.h" +#include "ulp_template_db_tbl.h" + +/* Mapper templates for header act list */ +struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { + /* act_tid: 1, thor, ingress */ + [1] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR, + .num_tbls = 2, + .start_tbl_idx = 0, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 0, + .cond_nums = 0 } + } +}; + +struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { + { /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 0, + .result_bit_size = 64, + .result_num_fields = 1 + }, + { /* act_tid: 1, thor, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 1, + .result_bit_size = 128, + .result_num_fields = 17, + .encap_num_fields = 0 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { + /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + } +}; + +struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { + /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 1, thor, table: int_full_act_record.0 */ + { + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd1", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stats_op", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stats_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "use_default", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "cnd_copy", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_dlt_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } +}; + +struct +bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = { +}; + +struct +bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { +}; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c similarity index 55% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c rename to drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c index c2cb452770..4d3d1e24b4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Dec 2 12:05:11 2020 */ +/* date: Fri Feb 12 13:05:14 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -11,1159 +11,685 @@ #include "ulp_template_db_tbl.h" /* Mapper templates for header class list */ -struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = { - /* class_tid: 1, stingray, ingress */ +struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { + /* class_tid: 1, thor, ingress */ [1] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 9, + .device_name = BNXT_ULP_DEVICE_ID_THOR, + .num_tbls = 11, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, .cond_nums = 0 } }, - /* class_tid: 2, stingray, ingress */ + /* class_tid: 2, thor, ingress */ [2] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 6, - .start_tbl_idx = 9, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 4, - .cond_nums = 0 } - }, - /* class_tid: 3, stingray, egress */ - [3] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 8, - .start_tbl_idx = 15, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 4, - .cond_nums = 0 } - }, - /* class_tid: 4, stingray, egress */ - [4] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 7, - .start_tbl_idx = 23, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, - .cond_nums = 0 } - }, - /* class_tid: 5, stingray, egress */ - [5] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, - .num_tbls = 7, - .start_tbl_idx = 30, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, - .cond_nums = 0 } - }, - /* class_tid: 6, stingray, egress */ - [6] = { - .device_name = BNXT_ULP_DEVICE_ID_STINGRAY, + .device_name = BNXT_ULP_DEVICE_ID_THOR, .num_tbls = 1, - .start_tbl_idx = 37, + .start_tbl_idx = 11, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, + .cond_start_idx = 2, .cond_nums = 0 } } }; -struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = { - { /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */ +struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { + { /* class_tid: 1, thor, table: mac_addr_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 2, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 0, - .cond_nums = 1 }, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 0, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 0, - .ident_nums = 1 + .blob_key_bit_size = 56, + .key_bit_size = 56, + .key_num_fields = 2, + .result_start_idx = 0, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 1, thor, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 1 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ + { /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 1, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 0, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 1, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 2, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 4, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 0, .ident_nums = 1 }, - { /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ + { /* class_tid: 1, thor, table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 14, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .ident_start_idx = 2, - .ident_nums = 3 - }, - { /* class_tid: 1, stingray, table: branch.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, - .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID - }, - { /* class_tid: 1, stingray, table: profile_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 17, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 13, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 1 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 23, + .blob_key_bit_size = 56, + .key_bit_size = 56, + .key_num_fields = 2, + .result_start_idx = 10, + .result_bit_size = 62, + .result_num_fields = 4 }, - { /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ + { /* class_tid: 1, thor, table: profile_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 60, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 25, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 21, - .result_bit_size = 66, - .result_num_fields = 5, - .encap_num_fields = 0 + .ident_start_idx = 1, + .ident_nums = 5 }, - { /* class_tid: 1, stingray, table: em.int_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 2, - .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 63, - .blob_key_bit_size = 176, - .key_bit_size = 176, - .key_num_fields = 10, - .result_start_idx = 26, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 - }, - { /* class_tid: 1, stingray, table: eem.ext_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, + { /* class_tid: 1, thor, table: control.1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 3, + .cond_start_idx = 1, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 73, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 10, - .result_start_idx = 35, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0 - }, - { /* class_tid: 1, stingray, table: last */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 1, thor, table: fkb_select.wm */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 2, .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 14, + .result_bit_size = 106, + .result_num_fields = 106 }, - { /* class_tid: 2, stingray, table: int_full_act_record.0 */ + { /* class_tid: 1, thor, table: fkb_select.em */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .resource_type = TF_TBL_TYPE_EM_FKB, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 44, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 120, + .result_bit_size = 106, + .result_num_fields = 106 }, - { /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ + { /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 83, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 70, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 28, + .blob_key_bit_size = 94, + .key_bit_size = 94, + .key_num_fields = 43, + .result_start_idx = 226, + .result_bit_size = 33, + .result_num_fields = 8, .ident_start_idx = 6, - .ident_nums = 1 + .ident_nums = 2 }, - { /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 1, thor, table: profile_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 96, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 83, - .result_bit_size = 62, - .result_num_fields = 4, - .encap_num_fields = 0 + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 71, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 234, + .result_bit_size = 82, + .result_num_fields = 7 }, - { /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 87, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* class_tid: 2, stingray, table: parif_def_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 88, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* class_tid: 2, stingray, table: parif_def_err_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + { /* class_tid: 1, thor, table: em.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 2, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 89, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 74, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 241, + .result_bit_size = 0, + .result_num_fields = 6 }, - { /* class_tid: 3, stingray, table: int_full_act_record.0 */ + { /* class_tid: 2, thor, table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 90, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 247, .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .result_num_fields = 17 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { + /* cond_execute: class_tid: 1, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - { /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 4, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 97, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 116, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 7, - .ident_nums = 0 - }, - { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 5, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 110, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 7, - .ident_nums = 1 + /* cond_execute: class_tid: 1, control.1 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + } +}; + +struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { + /* class_tid: 1, thor, table: mac_addr_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } }, - { /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, - .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 111, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 129, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 8, - .ident_nums = 1 + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } }, - { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, - .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 124, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 142, - .result_bit_size = 62, - .result_num_fields = 4, - .encap_num_fields = 0 - }, - { /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 146, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 147, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 148, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* class_tid: 4, stingray, table: int_vtag_encap_record.egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 149, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12 - }, - { /* class_tid: 4, stingray, table: int_full_act_record.egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 161, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - }, - { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 125, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 187, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0 - }, - { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 138, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 200, - .result_bit_size = 62, - .result_num_fields = 4, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0 - }, - { /* class_tid: 4, stingray, table: int_full_act_record.ing0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 204, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - }, - { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 139, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 230, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0 - }, - { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 152, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 243, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 0 - }, - { /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 165, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 256, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 9, - .ident_nums = 1 - }, - { /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 178, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 269, - .result_bit_size = 62, - .result_num_fields = 4, - .encap_num_fields = 0 - }, - { /* class_tid: 5, stingray, table: parif_def_lkup_arec_ptr.egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 273, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* class_tid: 5, stingray, table: parif_def_arec_ptr.egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 274, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* class_tid: 5, stingray, table: parif_def_err_arec_ptr.egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 275, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0 - }, - { /* class_tid: 5, stingray, table: int_full_act_record.ing */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, - .result_start_idx = 276, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - }, - { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 179, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 302, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 10, - .ident_nums = 0 - }, - { /* class_tid: 6, stingray, table: int_full_act_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 315, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - } -}; - -struct bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[] = { - { - .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, - .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - } -}; - -struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { - /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */ - { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "sparif", + .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "sparif", + .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", + .description = "spif", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_num_vtags", + .description = "spif", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "key_type", + .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", + .description = "mpass_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1172,6 +698,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1180,17 +707,64 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} } }, - /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ + /* class_tid: 1, thor, table: mac_addr_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } + }, + /* class_tid: 1, thor, table: profile_tcam_cache.rd */ { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1199,6 +773,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1207,6 +782,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1215,17 +791,19 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1234,6 +812,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1241,17 +820,19 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 1, stingray, table: profile_tcam.0 */ + /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1260,6 +841,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1268,6 +850,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, @@ -1280,16 +863,17 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_SR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_SR_SYM_L4_HDR_TYPE_UDP} + ULP_THOR_SYM_L4_HDR_TYPE_UDP} } }, { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1298,6 +882,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1306,6 +891,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1314,22 +900,41 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_SR_SYM_L4_HDR_VALID_YES} + ULP_THOR_SYM_L4_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1338,12 +943,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1352,12 +959,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1366,6 +975,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1374,6 +984,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, .field_cond_opr = { ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, @@ -1386,16 +997,17 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_SR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_SR_SYM_L3_HDR_TYPE_IPV6} + ULP_THOR_SYM_L3_HDR_TYPE_IPV6} } }, { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1404,6 +1016,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1412,6 +1025,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1420,24 +1034,25 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_SR_SYM_L3_HDR_VALID_YES} + ULP_THOR_SYM_L3_HDR_VALID_YES} } }, { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1446,25 +1061,23 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1473,6 +1086,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1481,6 +1095,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1489,6 +1104,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1497,6 +1113,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1505,6 +1122,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1513,6 +1131,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1521,22 +1140,25 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_SR_SYM_L2_HDR_VALID_YES} + ULP_THOR_SYM_L2_HDR_VALID_YES} } }, { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1545,12 +1167,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1559,12 +1183,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1573,6 +1199,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1581,6 +1208,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1589,12 +1217,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1603,12 +1233,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1617,12 +1249,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1631,6 +1265,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1639,6 +1274,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1647,12 +1283,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1661,12 +1299,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1675,12 +1315,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1689,12 +1331,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1703,12 +1347,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1717,6 +1363,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1725,6 +1372,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1733,12 +1381,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1747,12 +1397,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1761,12 +1413,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1775,12 +1429,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1789,6 +1445,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1797,6 +1454,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1805,26 +1463,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1833,6 +1479,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1841,6 +1488,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { @@ -1852,28 +1500,30 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1882,12 +1532,14 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1896,6 +1548,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1904,6 +1557,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1912,6 +1566,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1920,17 +1575,19 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} } }, - /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ + /* class_tid: 1, thor, table: profile_tcam_cache.wr */ { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1939,6 +1596,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } @@ -1947,6 +1605,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1955,17 +1614,19 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1974,6 +1635,7 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -1981,1335 +1643,1503 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 1, stingray, table: em.int_0 */ + /* class_tid: 1, thor, table: em.ipv4 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_SR_SYM_IP_PROTO_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_SR_SYM_IP_PROTO_UDP} + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, 0xff} }, .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 1, stingray, table: eem.ext_0 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 275, + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "spare", - .field_bit_size = 275, + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_SR_SYM_IP_PROTO_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_SR_SYM_IP_PROTO_UDP} + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, 0xff, 0xff} }, .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_ovlan_vid", + .description = "tl2_ivv", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", + .description = "tl2_ivv", .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "sparif", + .description = "tl3_l3type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", + .description = "tl3_l3type", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tl3_sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tl3_sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tl3_dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tl3_dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl3_dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl3_dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "tl3_dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "tl3_dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "tl3_ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "tl3_ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "tl3_prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "tl3_prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl3_ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl3_ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tl3_ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tl3_ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tl3_ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tl3_ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl3_ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl3_ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "tl3_df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "tl3_df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "tl3_l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "tl3_l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "tl4_l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "tl4_l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl4_src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl4_src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl4_dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl4_dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl4_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl4_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl4_seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl4_seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl4_pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl4_pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl4_opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl4_opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl4_tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl4_tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl4_err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl4_err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac0_addr", + .description = "l2_dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac0_addr", + .description = "l2_dmac", .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "valid", + .description = "l2_ivd", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "valid", + .description = "l2_ivd", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -3317,1387 +3147,900 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l3_l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l3_l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l3_sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l3_sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "l3_sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "l3_sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l3_sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l3_sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l3_dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l3_dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l3_dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l3_dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l3_dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l3_dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 2} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3_ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3_ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l3_prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "l3_prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_SR_SYM_TUN_HDR_TYPE_NONE} + ULP_THOR_SYM_IP_PROTO_TCP}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_IP_PROTO_UDP} } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3_fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3_fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "l3_fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "l3_fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l3_qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l3_qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l3_ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l3_ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l3_ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l3_ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l3_ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l3_ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "l3_ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "l3_ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l3_ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l3_ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l3_ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l3_ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l3_ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l3_ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l3_ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l3_ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3_df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3_df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tun_hdr_type", + .description = "l3_l3err.ipv4", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", + .description = "l3_l3err.ipv4", .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_SR_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3_l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3_l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "l4_l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "l4_l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4_src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4_src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4_dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4_dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_opr = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l4_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l4_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l4_seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l4_seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "l4_ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "l4_ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l4_win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l4_win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l4_pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l4_pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l4_opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l4_opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l4_tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l4_tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l4_tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} - } - }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */ - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l4_tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l4_txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} - } - }, - { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l4_txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", + .description = "l4_err", .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "l4_err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_SKIP } } }; -struct bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[] = { - /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "default_pri", - .field_bit_size = 3, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "allowed_tpid", - .field_bit_size = 6, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "default_tpid", - .field_bit_size = 3, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "bd_act_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "byp_sp_lkup", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, stingray, table: profile_tcam.0 */ - { - .description = "wc_key_id", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "em_key_mask", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (125 >> 8) & 0xff, - 125 & 0xff} - }, - { - .description = "em_key_id", - .field_bit_size = 5, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, stingray, table: profile_tcam_cache.wr */ +struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { + /* class_tid: 1, thor, table: mac_addr_cache.rd */ { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} - }, - { - .description = "profile_tcam_index", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - }, - { - .description = "wm_profile_id", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "flow_sig_id", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} - }, - /* class_tid: 1, stingray, table: em.int_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - { - .description = "ext_flow_cntr", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "key_size", - .field_bit_size = 9, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "reserved", - .field_bit_size = 11, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - /* class_tid: 1, stingray, table: eem.ext_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 33, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - { - .description = "ext_flow_cntr", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_SR_SYM_EEM_EXT_FLOW_CNTR} - }, - { - .description = "act_rec_int", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "act_rec_size", - .field_bit_size = 5, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} - }, - { - .description = "key_size", - .field_bit_size = 9, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (173 >> 8) & 0xff, - 173 & 0xff} - }, - { - .description = "reserved", - .field_bit_size = 11, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "strength", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} - }, - { - .description = "l1_cacheable", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "valid", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - /* class_tid: 2, stingray, table: int_full_act_record.0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "age_enable", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "agg_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rate_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "flow_cntr_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_key", - .field_bit_size = 8, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_mir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meter_id", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_rdir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_rdir", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ttl_dec", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ttl_dec", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "mirror", - .field_bit_size = 2, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "type", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - }, - { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "parif", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ { - .description = "default_tpid", - .field_bit_size = 3, + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} }, { - .description = "bd_act_en", - .field_bit_size = 1, + .description = "ctxt_meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "sp_rec_ptr", + .description = "def_ctxt_data", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (4 >> 8) & 0xff, + 4 & 0xff} }, { - .description = "byp_sp_lkup", - .field_bit_size = 1, + .description = "ctxt_opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 1, thor, table: mac_addr_cache.wr */ { .description = "rid", .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4707,6 +4050,7 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4716,6 +4060,7 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -4725,1712 +4070,1849 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr.0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - /* class_tid: 2, stingray, table: parif_def_arec_ptr.0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - /* class_tid: 2, stingray, table: parif_def_err_arec_ptr.0 */ + /* class_tid: 1, thor, table: fkb_select.wm */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + 1} }, - /* class_tid: 3, stingray, table: int_full_act_record.0 */ { - .description = "flow_cntr_ptr", - .field_bit_size = 14, + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "age_enable", + .description = "spif.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "agg_cntr_en", + .description = "svif.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rate_cntr_en", + .description = "lcos.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "flow_cntr_en", + .description = "meta.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_key", - .field_bit_size = 8, + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_mir", + .description = "loopback.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_match", + .description = "tl2_l2type.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "encap_ptr", - .field_bit_size = 11, + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "dst_ip_ptr", - .field_bit_size = 10, + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_dst_port", - .field_bit_size = 16, + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_src_port", - .field_bit_size = 16, + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", + .description = "tl2_ovd.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_rdir", + .description = "tl2_ovv.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl_dec", + .description = "tl2_ovt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ttl_dec", + .description = "tl2_ivp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "decap_func", - .field_bit_size = 4, + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vnic_or_vport", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} - }, - { - .description = "pop_vlan", + .description = "tl2_ivv.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter", + .description = "tl2_ivt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "mirror", - .field_bit_size = 2, + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drop", + .description = "tl3_l3type.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "hit", + .description = "tl3_sip.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "type", + .description = "tl3_sip_selcmp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */ { - .description = "act_record_ptr", - .field_bit_size = 16, + .description = "tl3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", + .description = "tl3_dip_selcmp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_byp_lkup_en", + .description = "tl3_ttl.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} - }, - { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", + .description = "tl3_ieh_esp.en", .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "tl3_ieh_auth.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_byp_lkup_en", + .description = "tl3_ieh_1frag.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", + .description = "tl4_flags.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "tl4_pa.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */ { - .description = "rid", - .field_bit_size = 32, + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: int_vtag_encap_record.egr0 */ { - .description = "ecv_tun_type", - .field_bit_size = 3, + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_l4_type", - .field_bit_size = 3, + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_l3_type", - .field_bit_size = 3, + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_l2_en", + .description = "l2_dmac.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_vtag_type", - .field_bit_size = 4, + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_custom_en", + .description = "l2_dt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_valid", + .description = "l2_sa.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vtag_tpid", - .field_bit_size = 16, + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0x81, - 0x00} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vtag_vid", - .field_bit_size = 12, + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vtag_de", + .description = "l2_ovd.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vtag_pcp", - .field_bit_size = 3, + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "spare", - .field_bit_size = 80, + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: int_full_act_record.egr0 */ { - .description = "flow_cntr_ptr", - .field_bit_size = 14, + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "age_enable", + .description = "l2_ivd.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "agg_cntr_en", + .description = "l2_ivv.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rate_cntr_en", + .description = "l2_ivt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "flow_cntr_en", + .description = "l2_etype.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_key", - .field_bit_size = 8, + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_mir", + .description = "l3_sip.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tcpflags_match", + .description = "l3_sip_selcmp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "encap_ptr", - .field_bit_size = 11, + .description = "l3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + 1} }, { - .description = "dst_ip_ptr", - .field_bit_size = 10, + .description = "l3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_dst_port", - .field_bit_size = 16, + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tcp_src_port", - .field_bit_size = 16, + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", + .description = "l3_ieh_nonext.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_rdir", + .description = "l3_ieh_esp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl_dec", + .description = "l3_ieh_auth.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ttl_dec", + .description = "l3_ieh_dest.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "decap_func", - .field_bit_size = 4, + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vnic_or_vport", - .field_bit_size = 12, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (ULP_SR_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_SR_SYM_LOOPBACK_PORT & 0xff} - }, - { - .description = "pop_vlan", + .description = "l3_ieh_rthdr.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter", + .description = "l3_ieh_hop.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "mirror", - .field_bit_size = 2, + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drop", + .description = "l3_df.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "hit", + .description = "l3_l3err.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "type", + .description = "l4_l4type.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */ { - .description = "act_record_ptr", - .field_bit_size = 16, + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "reserved", + .description = "l4_dst.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "l2_byp_lkup_en", + .description = "l4_flags.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", + .description = "l4_tcpts.en", .field_bit_size = 1, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "l4_tsval.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */ + /* class_tid: 1, thor, table: fkb_select.em */ { - .description = "rid", - .field_bit_size = 32, + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + 1} }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: int_full_act_record.ing0 */ { - .description = "flow_cntr_ptr", - .field_bit_size = 14, + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "age_enable", + .description = "meta.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "agg_cntr_en", + .description = "rcyc_cnt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rate_cntr_en", + .description = "loopback.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "flow_cntr_en", + .description = "tl2_l2type.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_key", - .field_bit_size = 8, + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_mir", + .description = "tl2_smac.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_match", + .description = "tl2_dt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "encap_ptr", - .field_bit_size = 11, + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "dst_ip_ptr", - .field_bit_size = 10, + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_dst_port", - .field_bit_size = 16, + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_src_port", - .field_bit_size = 16, + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", + .description = "tl2_ivp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_rdir", + .description = "tl2_ivd.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl_dec", + .description = "tl2_ivv.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ttl_dec", + .description = "tl2_ivt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "decap_func", - .field_bit_size = 4, + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vnic_or_vport", - .field_bit_size = 12, + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pop_vlan", + .description = "tl3_sip.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter", + .description = "tl3_sip_selcmp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "mirror", - .field_bit_size = 2, + .description = "tl3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drop", + .description = "tl3_dip_selcmp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "hit", + .description = "tl3_ttl.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "type", + .description = "tl3_prot.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ { - .description = "act_record_ptr", - .field_bit_size = 16, + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", + .description = "tl3_qos.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_byp_lkup_en", + .description = "tl3_ieh_nonext.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", + .description = "tl3_ieh_hop.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "tl3_df.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */ { - .description = "act_record_ptr", - .field_bit_size = 16, + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", + .description = "tl4_dst.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_byp_lkup_en", + .description = "tl4_flags.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", + .description = "tuntype.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "tids.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_byp_lkup_en", + .description = "terr.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", + .description = "l2_nvt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "l2_ovd.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */ { - .description = "rid", - .field_bit_size = 32, + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: parif_def_lkup_arec_ptr.egr */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: parif_def_arec_ptr.egr */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: parif_def_err_arec_ptr.egr */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "l3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + 1} }, - /* class_tid: 5, stingray, table: int_full_act_record.ing */ { - .description = "flow_cntr_ptr", - .field_bit_size = 14, + .description = "l3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "age_enable", + .description = "l3_dip.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "agg_cntr_en", + .description = "l3_dip_selcmp.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rate_cntr_en", + .description = "l3_ttl.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "flow_cntr_en", + .description = "l3_prot.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tcpflags_key", - .field_bit_size = 8, + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_mir", + .description = "l3_qos.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_match", + .description = "l3_ieh_nonext.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "encap_ptr", - .field_bit_size = 11, + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "dst_ip_ptr", - .field_bit_size = 10, + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_dst_port", - .field_bit_size = 16, + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_src_port", - .field_bit_size = 16, + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", + .description = "l3_ieh_1frag.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_rdir", + .description = "l3_df.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl_dec", + .description = "l3_l3err.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ttl_dec", + .description = "l4_l4type.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "decap_func", - .field_bit_size = 4, + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "vnic_or_vport", - .field_bit_size = 12, + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + 1} }, { - .description = "pop_vlan", + .description = "l4_flags.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter", + .description = "l4_seq.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "mirror", - .field_bit_size = 2, + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drop", + .description = "l4_win.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "hit", + .description = "l4_pa.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "type", + .description = "l4_opt.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */ { - .description = "act_record_ptr", - .field_bit_size = 16, + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", + .description = "l4_tsval.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_byp_lkup_en", + .description = "l4_txecr.en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "wc_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "em_key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", - .field_bit_size = 1, + .description = "em_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff} }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "byp_sp_lkup", + .description = "em_search_en", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, thor, table: profile_tcam_cache.wr */ { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, - /* class_tid: 6, stingray, table: int_full_act_record.0 */ { - .description = "flow_cntr_ptr", - .field_bit_size = 14, + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} }, { - .description = "age_enable", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "agg_cntr_en", - .field_bit_size = 1, + .description = "em_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff} }, { - .description = "rate_cntr_en", - .field_bit_size = 1, + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 & 0xff} }, { - .description = "flow_cntr_en", - .field_bit_size = 1, + .description = "wc_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_KEY_ID_0 & 0xff} }, { - .description = "tcpflags_key", + .description = "flow_sig_id", .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, + /* class_tid: 1, thor, table: em.ipv4 */ { - .description = "tcpflags_mir", + .description = "valid", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tcpflags_match", - .field_bit_size = 1, + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "arec_ptr_or_md", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "encap_ptr", - .field_bit_size = 11, + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "dst_ip_ptr", - .field_bit_size = 10, + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, thor, table: int_full_act_record.0 */ { - .description = "tcp_dst_port", + .description = "sp_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, + .description = "encap_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_src_port", + .description = "mod_rec_ptr", .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, + .description = "rsvd1", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", - .field_bit_size = 1, + .description = "rsvd0", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_rdir", - .field_bit_size = 1, + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl_dec", - .field_bit_size = 1, + .description = "meter", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ttl_dec", + .description = "stats_op", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "decap_func", - .field_bit_size = 4, + .description = "stats_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", - .field_bit_size = 12, + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (ULP_SR_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_SR_SYM_LOOPBACK_PORT & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { - .description = "pop_vlan", + .description = "use_default", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter", + .description = "mirror", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "cnd_copy", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "mirror", + .description = "vlan_dlt_rpt", .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", - .field_bit_size = 1, + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }; -struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { - /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */ - { - .description = "l2_cntxt_id", - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 42 - }, - /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */ +struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { + /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_bit_pos = 29 }, - /* class_tid: 1, stingray, table: profile_tcam_cache.rd */ + /* class_tid: 1, thor, table: profile_tcam_cache.rd */ { - .description = "profile_tcam_index", - .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .ident_bit_size = 10, - .ident_bit_pos = 32 + .description = "em_key_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 50 }, { .description = "em_profile_id", @@ -6442,49 +5924,35 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, .ident_bit_size = 8, - .ident_bit_pos = 58 + .ident_bit_pos = 74 }, - /* class_tid: 1, stingray, table: profile_tcam.0 */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .description = "wc_key_id", + .regfile_idx = BNXT_ULP_RF_IDX_WC_KEY_ID_0, .ident_bit_size = 8, - .ident_bit_pos = 28 - }, - /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_bit_pos = 66 }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */ { - .description = "l2_cntxt_id", - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 42 + .description = "wc_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_WC_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 58 }, - /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */ + /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ { - .description = "l2_cntxt_id", + .description = "wc_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_type = TF_IDENT_TYPE_WC_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_WC_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 6 }, - /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */ { - .description = "l2_cntxt_id", + .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 23 } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 9483e29323..2655bfdb9d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ -/* date: Tue Jan 26 15:51:49 2021 */ +/* date: Wed Mar 3 16:36:04 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -84,13 +84,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 0, .blob_key_bit_size = 1, .key_bit_size = 1, @@ -107,7 +108,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 10, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, @@ -115,6 +116,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 0, .result_bit_size = 64, .result_num_fields = 1 @@ -129,7 +131,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 11, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, @@ -137,6 +139,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 1, .result_bit_size = 0, .result_num_fields = 0, @@ -160,6 +163,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 13, .result_bit_size = 128, .result_num_fields = 26, @@ -183,6 +187,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 39, .result_bit_size = 128, .result_num_fields = 26, @@ -199,7 +204,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, { /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -219,6 +225,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 77, .result_bit_size = 32, .result_num_fields = 6 @@ -232,7 +239,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 12, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, @@ -241,6 +248,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 83, .result_bit_size = 64, .result_num_fields = 1 @@ -264,6 +272,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 84, .result_bit_size = 128, .result_num_fields = 26, @@ -288,6 +297,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 110, .result_bit_size = 128, .result_num_fields = 26, @@ -310,6 +320,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 148, .result_bit_size = 32, .result_num_fields = 6 @@ -330,6 +341,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 1, .blob_key_bit_size = 1, .key_bit_size = 1, @@ -347,13 +359,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 13, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 156, .result_bit_size = 64, .result_num_fields = 1 @@ -367,13 +380,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 14, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 157, .result_bit_size = 32, .result_num_fields = 1 @@ -387,13 +401,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 15, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 158, .result_bit_size = 32, .result_num_fields = 1 @@ -414,6 +429,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 159, .result_bit_size = 0, .result_num_fields = 0, @@ -436,6 +452,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 171, .result_bit_size = 128, .result_num_fields = 26 @@ -457,6 +474,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 197, .result_bit_size = 128, .result_num_fields = 26, @@ -471,13 +489,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 16, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 235, .result_bit_size = 64, .result_num_fields = 1 @@ -492,13 +511,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 236, .result_bit_size = 0, .result_num_fields = 0, @@ -521,6 +541,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 248, .result_bit_size = 128, .result_num_fields = 26 @@ -535,13 +556,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 18, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 274, .result_bit_size = 128, .result_num_fields = 26, @@ -557,13 +579,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 19, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 312, .result_bit_size = 128, .result_num_fields = 26, @@ -578,13 +601,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 20, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 350, .result_bit_size = 64, .result_num_fields = 1 @@ -598,13 +622,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 351, .result_bit_size = 32, .result_num_fields = 1 @@ -618,13 +643,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 22, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 352, .result_bit_size = 32, .result_num_fields = 1 @@ -645,6 +671,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 353, .result_bit_size = 0, .result_num_fields = 0, @@ -667,6 +694,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 365, .result_bit_size = 128, .result_num_fields = 26 @@ -688,6 +716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 391, .result_bit_size = 128, .result_num_fields = 26, @@ -702,13 +731,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 23, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 429, .result_bit_size = 64, .result_num_fields = 1 @@ -722,13 +752,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 24, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 430, .result_bit_size = 0, .result_num_fields = 0, @@ -743,13 +774,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 25, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 433, .result_bit_size = 0, .result_num_fields = 0, @@ -772,6 +804,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 436, .result_bit_size = 0, .result_num_fields = 0, @@ -794,6 +827,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 448, .result_bit_size = 128, .result_num_fields = 26 @@ -815,6 +849,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 474, .result_bit_size = 128, .result_num_fields = 26, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 84f3900141..c636fd2aca 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2020 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ -/* date: Fri Jan 29 09:44:41 2021 */ +/* date: Wed Mar 3 16:36:04 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -15,71 +15,41 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 14, + .num_tbls = 17, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 0, - .cond_nums = 0 } + .cond_nums = 1 } }, /* class_tid: 2, wh_plus, egress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 14, - .start_tbl_idx = 14, + .start_tbl_idx = 17, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 6, - .cond_nums = 0 } + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 17, + .cond_nums = 1 } }, /* class_tid: 3, wh_plus, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 8, - .start_tbl_idx = 28, + .num_tbls = 23, + .start_tbl_idx = 31, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 12, + .cond_start_idx = 24, .cond_nums = 0 } }, /* class_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 14, - .start_tbl_idx = 36, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 13, - .cond_nums = 0 } - }, - /* class_tid: 5, wh_plus, egress */ - [5] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 9, - .start_tbl_idx = 50, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 18, - .cond_nums = 0 } - }, - /* class_tid: 6, wh_plus, egress */ - [6] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 9, - .start_tbl_idx = 59, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 19, - .cond_nums = 0 } - }, - /* class_tid: 7, wh_plus, egress */ - [7] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 1, - .start_tbl_idx = 68, + .num_tbls = 19, + .start_tbl_idx = 54, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, + .cond_start_idx = 30, .cond_nums = 0 } } }; @@ -94,13 +64,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 5, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 1, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 0, .blob_key_bit_size = 8, .key_bit_size = 8, @@ -117,19 +88,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 1, .blob_key_bit_size = 56, .key_bit_size = 56, .key_num_fields = 2, - .result_start_idx = 0, - .result_bit_size = 62, - .result_num_fields = 4 + .ident_start_idx = 1, + .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, @@ -137,12 +108,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 2, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -152,22 +124,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 3, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 4, + .result_start_idx = 0, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 1, + .ident_start_idx = 2, .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ @@ -179,17 +153,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 16, .blob_key_bit_size = 56, .key_bit_size = 56, .key_num_fields = 2, - .result_start_idx = 17, + .result_start_idx = 13, .result_bit_size = 62, .result_num_fields = 4 }, @@ -203,17 +178,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 18, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .ident_start_idx = 2, + .ident_start_idx = 3, .ident_nums = 3 }, { /* class_tid: 1, wh_plus, table: control.1 */ @@ -221,24 +197,25 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 4, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 2, + .cond_false_goto = 5, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 2, + .cond_true_goto = 3, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 3, - .cond_nums = 1 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 4, + .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, @@ -246,14 +223,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 21, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 21, + .result_start_idx = 17, .result_bit_size = 38, .result_num_fields = 17, - .ident_start_idx = 5, + .ident_start_idx = 6, .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ @@ -263,9 +241,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 6, + .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, @@ -273,14 +251,43 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 64, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 38, + .result_start_idx = 34, .result_bit_size = 38, .result_num_fields = 17, - .ident_start_idx = 6, + .ident_start_idx = 7, + .ident_nums = 1 + }, + { /* class_tid: 1, wh_plus, table: profile_tcam.vxlan */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 8, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 107, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 51, + .result_bit_size = 38, + .result_num_fields = 17, + .ident_start_idx = 8, .ident_nums = 1 }, { /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ @@ -293,17 +300,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 9, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 107, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 150, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 55, + .result_start_idx = 68, .result_bit_size = 74, .result_num_fields = 5 }, @@ -315,18 +323,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 4, - .cond_nums = 1 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 9, + .cond_nums = 2 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 110, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 153, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, - .result_start_idx = 60, + .result_start_idx = 73, .result_bit_size = 64, .result_num_fields = 9 }, @@ -338,18 +347,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 5, - .cond_nums = 1 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 11, + .cond_nums = 2 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 120, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 163, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, - .result_start_idx = 69, + .result_start_idx = 82, .result_bit_size = 64, .result_num_fields = 9 }, @@ -361,18 +371,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 13, + .cond_nums = 2 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 130, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 173, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, - .result_start_idx = 78, + .result_start_idx = 91, .result_bit_size = 64, .result_num_fields = 9 }, @@ -380,21 +391,69 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 2 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 184, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 11, + .result_start_idx = 100, + .result_bit_size = 64, + .result_num_fields = 9 + }, + { /* class_tid: 1, wh_plus, table: em.vxlan */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 195, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 109, + .result_bit_size = 64, + .result_num_fields = 9 + }, + { /* class_tid: 1, wh_plus, table: eem.vxlan */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, + .cond_start_idx = 17, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 141, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 206, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, - .result_start_idx = 87, + .result_start_idx = 118, .result_bit_size = 64, .result_num_fields = 9 }, @@ -406,18 +465,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 5, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 6, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 18, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 152, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 217, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 7, + .ident_start_idx = 9, .ident_nums = 1 }, { /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ @@ -429,19 +489,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 153, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 218, .blob_key_bit_size = 56, .key_bit_size = 56, .key_num_fields = 2, - .result_start_idx = 96, - .result_bit_size = 62, - .result_num_fields = 4 + .ident_start_idx = 10, + .ident_nums = 1 }, { /* class_tid: 2, wh_plus, table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, @@ -449,12 +509,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 7, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 19, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -464,7 +525,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -473,14 +534,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 155, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 220, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 100, + .result_start_idx = 127, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 8, + .ident_start_idx = 11, .ident_nums = 1 }, { /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ @@ -492,17 +554,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 168, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 233, .blob_key_bit_size = 56, .key_bit_size = 56, .key_num_fields = 2, - .result_start_idx = 113, + .result_start_idx = 140, .result_bit_size = 62, .result_num_fields = 4 }, @@ -515,17 +578,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 20, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 170, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 235, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .ident_start_idx = 9, + .ident_start_idx = 12, .ident_nums = 3 }, { /* class_tid: 2, wh_plus, table: control.1 */ @@ -534,12 +598,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 4, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 8, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 20, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, { /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -548,8 +613,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 2, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 9, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -558,14 +623,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 173, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 238, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 117, + .result_start_idx = 144, .result_bit_size = 38, .result_num_fields = 17, - .ident_start_idx = 12, + .ident_start_idx = 15, .ident_nums = 1 }, { /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ @@ -576,7 +642,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 22, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -585,14 +651,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 216, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 281, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 134, + .result_start_idx = 161, .result_bit_size = 38, .result_num_fields = 17, - .ident_start_idx = 13, + .ident_start_idx = 16, .ident_nums = 1 }, { /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ @@ -604,17 +671,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 22, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 259, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 324, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 151, + .result_start_idx = 178, .result_bit_size = 74, .result_num_fields = 5 }, @@ -626,18 +694,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 10, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 22, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 262, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 327, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, - .result_start_idx = 156, + .result_start_idx = 183, .result_bit_size = 64, .result_num_fields = 9 }, @@ -649,18 +718,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 11, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 23, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 272, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 337, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, - .result_start_idx = 165, + .result_start_idx = 192, .result_bit_size = 64, .result_num_fields = 9 }, @@ -673,17 +743,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 24, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 282, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 347, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, - .result_start_idx = 174, + .result_start_idx = 201, .result_bit_size = 64, .result_num_fields = 9 }, @@ -695,21 +766,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 24, .cond_nums = 0 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 293, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 358, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, - .result_start_idx = 183, + .result_start_idx = 210, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ + { /* class_tid: 3, wh_plus, table: port_table.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 24, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 369, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 219, + .result_bit_size = 144, + .result_num_fields = 4 + }, + { /* class_tid: 3, wh_plus, table: int_full_act_record.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -719,18 +815,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 24, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 192, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 223, .result_bit_size = 128, .result_num_fields = 26 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -739,33 +836,35 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 24, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 304, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 370, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 14, + .ident_start_idx = 17, .ident_nums = 0 }, - { /* class_tid: 3, wh_plus, table: control.0 */ + { /* class_tid: 3, wh_plus, table: control.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 12, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 24, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -773,7 +872,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 25, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -784,17 +883,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 305, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 371, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 218, + .result_start_idx = 249, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 14, + .ident_start_idx = 17, .ident_nums = 1 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -803,21 +903,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 25, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 318, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 384, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 231, + .result_start_idx = 262, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -825,17 +926,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 25, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 235, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 266, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -843,47 +945,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 25, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 236, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 267, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 25, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 237, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 268, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, wh_plus, table: control.0 */ + { /* class_tid: 3, wh_plus, table: control.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 6, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 13, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 25, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.vfr */ + { /* class_tid: 3, wh_plus, table: int_full_act_record.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -893,19 +998,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 26, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 238, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 269, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_rd_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -914,33 +1020,35 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 26, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 319, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 385, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 15, + .ident_start_idx = 18, .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: control.1 */ + { /* class_tid: 3, wh_plus, table: control.egr_1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 14, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 26, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -948,7 +1056,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 27, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -957,17 +1065,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 320, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 386, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 264, + .result_start_idx = 295, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 15, + .ident_start_idx = 18, .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -976,21 +1085,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 27, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 333, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 399, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 277, + .result_start_idx = 308, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -999,33 +1109,35 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, + .cond_start_idx = 27, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 334, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 400, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 15, + .ident_start_idx = 18, .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: control.2 */ + { /* class_tid: 3, wh_plus, table: control.egr_2 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 15, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 27, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1033,7 +1145,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1042,17 +1154,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 335, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 401, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 281, + .result_start_idx = 312, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 15, + .ident_start_idx = 18, .ident_nums = 1 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1061,21 +1174,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 28, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 348, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 414, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 294, + .result_start_idx = 325, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.0 */ + { /* class_tid: 3, wh_plus, table: int_full_act_record.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1085,19 +1199,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 298, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 329, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1105,17 +1220,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 324, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 355, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1123,17 +1239,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 325, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 356, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */ + { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1141,17 +1258,41 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 326, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 357, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ + { /* class_tid: 4, wh_plus, table: int_full_act_record.loopback */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 30, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 358, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 + }, + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_rd_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1160,33 +1301,35 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 349, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 415, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 16, + .ident_start_idx = 19, .ident_nums = 0 }, - { /* class_tid: 5, wh_plus, table: control.0 */ + { /* class_tid: 4, wh_plus, table: control.vf_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 18, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 30, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1194,7 +1337,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1203,17 +1346,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 350, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 416, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 327, + .result_start_idx = 384, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 16, - .ident_nums = 0 + .ident_start_idx = 19, + .ident_nums = 1 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1222,64 +1366,79 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 363, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 429, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 340, + .result_start_idx = 397, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + { /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, + .cond_start_idx = 31, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 344, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12 + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 401, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + { /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, + .cond_start_idx = 31, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 356, - .result_bit_size = 128, - .result_num_fields = 26 + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 402, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 31, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 403, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */ + { /* class_tid: 4, wh_plus, table: int_full_act_record.vf_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1289,18 +1448,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 382, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 404, .result_bit_size = 128, - .result_num_fields = 26 + .result_num_fields = 26, + .encap_num_fields = 0 }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vf_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1308,35 +1469,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 364, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 408, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 16, - .ident_nums = 0 - }, - { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1346,17 +1479,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 377, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 430, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 421, + .result_start_idx = 430, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 16, + .ident_start_idx = 20, .ident_nums = 0 }, - { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1365,33 +1499,35 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 390, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 443, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 16, + .ident_start_idx = 20, .ident_nums = 0 }, - { /* class_tid: 6, wh_plus, table: control.0 */ + { /* class_tid: 4, wh_plus, table: control.vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 19, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 31, .cond_nums = 1 }, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1399,7 +1535,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 32, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1408,17 +1544,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 391, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 444, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 434, + .result_start_idx = 443, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 16, - .ident_nums = 1 + .ident_start_idx = 20, + .ident_nums = 0 }, - { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1427,75 +1564,67 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 32, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 404, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 457, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 447, + .result_start_idx = 456, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 451, - .result_bit_size = 32, - .result_num_fields = 1 - }, - { /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + { /* class_tid: 4, wh_plus, table: int_vtag_encap_record.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 32, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 452, - .result_bit_size = 32, - .result_num_fields = 1 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 460, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12 }, - { /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + { /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 32, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 453, - .result_bit_size = 32, - .result_num_fields = 1 + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 472, + .result_bit_size = 128, + .result_num_fields = 26 }, - { /* class_tid: 6, wh_plus, table: int_full_act_record.ing */ + { /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1505,27 +1634,27 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 32, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, - .result_start_idx = 454, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 498, .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .result_num_fields = 26 }, - { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + { /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 32, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1535,41 +1664,54 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 405, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 458, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 480, + .result_start_idx = 524, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 17, + .ident_start_idx = 20, .ident_nums = 0 }, - { /* class_tid: 7, wh_plus, table: int_full_act_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, + { /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 32, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 493, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 471, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 537, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 20, + .ident_nums = 0 } }; struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { + /* cond_reject: wh_plus, class_tid: 1 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + }, /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, @@ -1590,16 +1732,65 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* cond_execute: class_tid: 1, profile_tcam.ipv6 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* cond_execute: class_tid: 1, profile_tcam.vxlan */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, /* cond_execute: class_tid: 1, em.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, /* cond_execute: class_tid: 1, eem.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* cond_execute: class_tid: 1, em.ipv6 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* cond_execute: class_tid: 1, eem.ipv6 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* cond_reject: wh_plus, class_tid: 2 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + }, /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, @@ -1630,27 +1821,27 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 3, control.0 */ + /* cond_execute: class_tid: 3, control.ing_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 4, control.0 */ + /* cond_execute: class_tid: 3, control.egr_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* cond_execute: class_tid: 4, control.1 */ + /* cond_execute: class_tid: 3, control.egr_1 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 4, control.2 */ + /* cond_execute: class_tid: 3, control.egr_2 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.wr */ + /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.egr_wr */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE @@ -1659,12 +1850,12 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 5, control.0 */ + /* cond_execute: class_tid: 4, control.vf_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 6, control.0 */ + /* cond_execute: class_tid: 4, control.vfr_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS @@ -1946,9 +2137,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -1966,7 +2155,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -2794,9 +2983,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", @@ -2828,9 +3015,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", @@ -2848,7 +3033,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -3565,9 +3750,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", @@ -3599,9 +3782,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", @@ -3619,7 +3800,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -3631,20 +3812,18 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + /* class_tid: 1, wh_plus, table: profile_tcam.vxlan */ { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3652,8 +3831,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l4_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -3661,27 +3840,19 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l4_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -3689,28 +3860,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 1, wh_plus, table: em.ipv4 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3718,15 +3885,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3734,111 +3901,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", - .field_bit_size = 16, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.sport", - .field_bit_size = 16, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, + .description = "l3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.ip_proto", - .field_bit_size = 8, + .description = "l3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3846,125 +3949,97 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "l3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "l3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.smac", - .field_bit_size = 48, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 1, wh_plus, table: eem.ipv4 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 275, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 275, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3972,15 +4047,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -3988,180 +4063,1492 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", - .field_bit_size = 16, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TL4_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TL3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TL2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "reserved", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: em.ipv4 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dst", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.dst", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.src", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.src", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: eem.ipv4 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 275, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 275, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dst", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.dst", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.src", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.src", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: em.ipv6 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, + .field_cond_opr = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dst", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.dst", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.src", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.src", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 1, wh_plus, table: eem.ipv6 */ + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "o_ipv4.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} } }, { .field_info_mask = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "l3.dst", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.dst", - .field_bit_size = 32, + .description = "l3.dst", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "l3.src", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.src", - .field_bit_size = 32, + .description = "l3.src", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.smac", + .description = "l2.smac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.smac", + .description = "l2.smac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -4207,7 +5594,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: em.ipv6 */ + /* class_tid: 1, wh_plus, table: em.vxlan */ { .field_info_mask = { .description = "spare", @@ -4242,110 +5629,46 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", + .description = "tl4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.dport", + .description = "tl4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", + .description = "tl4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.sport", + .description = "tl4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv6.ip_proto", + .description = "tl3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.ip_proto", + .description = "tl3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -4354,81 +5677,69 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv6.dst", - .field_bit_size = 128, + .description = "tl3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "o_ipv6.dst", - .field_bit_size = 128, + .description = "tl3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "o_ipv6.src", - .field_bit_size = 128, + .description = "tl3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.src", - .field_bit_size = 128, + .description = "tl3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.smac", + .description = "tl2.src", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.smac", + .description = "tl2.src", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.dmac", - .field_bit_size = 48, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.dmac", - .field_bit_size = 48, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -4477,18 +5788,18 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: eem.ipv6 */ + /* class_tid: 1, wh_plus, table: eem.vxlan */ { .field_info_mask = { .description = "spare", - .field_bit_size = 35, + .field_bit_size = 251, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", - .field_bit_size = 35, + .field_bit_size = 251, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -4512,110 +5823,46 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", + .description = "tl4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.dport", + .description = "tl4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", + .description = "tl4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_l4.sport", + .description = "tl4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv6.ip_proto", + .description = "tl3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.ip_proto", + .description = "tl3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -4624,81 +5871,69 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_ipv6.dst", - .field_bit_size = 128, + .description = "tl3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "o_ipv6.dst", - .field_bit_size = 128, + .description = "tl3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "o_ipv6.src", - .field_bit_size = 128, + .description = "tl3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.src", - .field_bit_size = 128, + .description = "tl3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.smac", + .description = "tl2.src", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.smac", + .description = "tl2.src", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.dmac", - .field_bit_size = 48, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.dmac", - .field_bit_size = 48, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -5021,9 +6256,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -5041,7 +6274,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -5869,9 +7102,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", @@ -5903,9 +7134,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", @@ -5923,7 +7152,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -6640,9 +7869,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", @@ -6674,9 +7901,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", @@ -6694,7 +7919,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -6809,180 +8034,165 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "o_ipv4.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} } }, { .field_info_mask = { - .description = "o_ipv4.dst", + .description = "l3.dst", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.dst", + .description = "l3.dst", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.src", + .description = "l3.src", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.src", + .description = "l3.src", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.dmac", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.dmac", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -7063,180 +8273,165 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "o_ipv4.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} } }, { .field_info_mask = { - .description = "o_ipv4.dst", + .description = "l3.dst", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.dst", + .description = "l3.dst", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv4.src", + .description = "l3.src", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv4.src", + .description = "l3.src", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.dmac", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.dmac", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -7317,170 +8512,147 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv6.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "o_ipv6.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} } }, { .field_info_mask = { - .description = "o_ipv6.dst", + .description = "l3.dst", .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.dst", + .description = "l3.dst", .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv6.src", + .description = "l3.src", .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.src", + .description = "l3.src", .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.smac", + .description = "l2.smac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.smac", + .description = "l2.smac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -7489,24 +8661,32 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_eth.dmac", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.dmac", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -7587,170 +8767,147 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.dport", + .description = "l4.dst", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + 0xff, + 0xff} }, .field_info_spec = { - .description = "o_l4.sport", + .description = "l4.src", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv6.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "o_ipv6.ip_proto", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} } }, { .field_info_mask = { - .description = "o_ipv6.dst", + .description = "l3.dst", .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.dst", + .description = "l3.dst", .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_ipv6.src", + .description = "l3.src", .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_ipv6.src", + .description = "l3.src", .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "o_eth.smac", + .description = "l2.smac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.smac", + .description = "l2.smac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, @@ -7759,24 +8916,32 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "o_eth.dmac", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "o_eth.dmac", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, + .field_cond_opr = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -7822,7 +8987,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 3, wh_plus, table: port_table.wr */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_rd */ { .field_info_mask = { .description = "svif", @@ -7844,7 +9031,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -8032,9 +9219,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -8052,7 +9237,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -8064,7 +9249,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_wr */ { .field_info_mask = { .description = "svif", @@ -8086,7 +9271,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_rd_vfr */ { .field_info_mask = { .description = "svif", @@ -8108,7 +9293,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.egr_vfr */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -8296,9 +9481,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -8316,7 +9499,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -8328,7 +9511,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .field_info_mask = { .description = "svif", @@ -8350,7 +9533,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { .description = "svif", @@ -8372,7 +9555,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -8560,9 +9743,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -8580,7 +9761,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -8592,7 +9773,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { .field_info_mask = { .description = "svif", @@ -8614,7 +9795,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_rd_egr */ { .field_info_mask = { .description = "svif", @@ -8632,11 +9813,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -8702,8 +9883,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { @@ -8824,9 +10005,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -8844,7 +10023,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -8856,7 +10035,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_egr_wr */ { .field_info_mask = { .description = "svif", @@ -8874,11 +10053,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vf_ing */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -8901,20 +10080,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -8950,8 +10123,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { @@ -9024,18 +10197,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 2} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9060,18 +10229,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9080,9 +10245,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -9100,7 +10263,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -9112,27 +10275,43 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_egr0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9258,18 +10437,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9294,18 +10469,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9314,9 +10485,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -9334,7 +10503,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -9346,7 +10515,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { .field_info_mask = { .description = "svif", @@ -9364,11 +10533,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -9391,14 +10560,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { @@ -9434,8 +10609,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { @@ -9508,14 +10683,18 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} } }, { @@ -9540,14 +10719,18 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -9556,9 +10739,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -9576,7 +10757,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -9588,43 +10769,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { + 0xff, 0xff} }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} - } - }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { @@ -9676,8 +10841,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { @@ -9750,14 +10915,18 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} } }, { @@ -9782,14 +10951,18 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -9798,9 +10971,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", @@ -9818,7 +10989,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { .description = "valid", @@ -9833,38 +11004,6 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }; struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { - /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ - { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "src_property_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -9970,43 +11109,190 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }, /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ { - .description = "rid", - .field_bit_size = 32, + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ + { + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + { + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + { + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff} + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} + }, + { + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} + }, + { + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + 3} }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "em_search_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + 1} }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "pl_byp_lkup_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -10042,10 +11328,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.2", @@ -10054,8 +11337,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, { .description = "em_key_mask.3", @@ -10064,15 +11347,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, { .description = "em_key_mask.4", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, { .description = "em_key_mask.5", @@ -10081,8 +11367,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff} }, { .description = "em_key_mask.6", @@ -10091,15 +11377,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} }, { .description = "em_key_mask.7", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} }, { .description = "em_key_mask.8", @@ -10122,7 +11411,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 7} }, { .description = "em_profile_id", @@ -10150,7 +11439,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ + /* class_tid: 1, wh_plus, table: profile_tcam.vxlan */ { .description = "wc_key_id", .field_bit_size = 4, @@ -10193,30 +11482,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.3", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.4", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + 1} }, { .description = "em_key_mask.5", @@ -10230,20 +11512,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.7", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.8", @@ -10266,7 +11542,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 7} + 20} }, { .description = "em_profile_id", @@ -10638,38 +11914,154 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ + /* class_tid: 1, wh_plus, table: em.vxlan */ { - .description = "rid", - .field_bit_size = 32, + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "ext_flow_cntr", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "act_rec_int", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "l1_cacheable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, wh_plus, table: eem.vxlan */ + { + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "ext_flow_cntr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + }, + { + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (197 >> 8) & 0xff, + 197 & 0xff} + }, + { + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "l1_cacheable", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -10886,7 +12278,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff} }, { .description = "em_key_mask.5", @@ -11037,7 +12432,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff} }, { .description = "em_key_mask.6", @@ -11450,9 +12848,51 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} + }, + /* class_tid: 3, wh_plus, table: port_table.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_PORT_TABLE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}, + .field_opr2 = { + (BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC & 0xff} + }, + { + .description = "drv_func.parent.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_PORT_TABLE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}, + .field_opr2 = { + (BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_MAC & 0xff} + }, + { + .description = "default_arec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: int_full_act_record.0 */ + /* class_tid: 3, wh_plus, table: int_full_act_record.ing_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -11638,7 +13078,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -11741,7 +13181,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_wr */ { .description = "rid", .field_bit_size = 32, @@ -11779,7 +13219,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -11790,7 +13230,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -11801,7 +13241,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -11812,7 +13252,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: int_full_act_record.vfr */ + /* class_tid: 3, wh_plus, table: int_full_act_record.egr_vfr */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -11998,7 +13438,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.egr_vfr */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -12099,7 +13539,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .description = "rid", .field_bit_size = 32, @@ -12134,7 +13574,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -12237,7 +13677,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { .description = "rid", .field_bit_size = 32, @@ -12275,7 +13715,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: int_full_act_record.0 */ + /* class_tid: 3, wh_plus, table: int_full_act_record.egr_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12461,7 +13901,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12472,7 +13912,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12483,7 +13923,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */ + /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12494,424 +13934,366 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */ + /* class_tid: 4, wh_plus, table: int_full_act_record.loopback */ { - .description = "act_record_ptr", - .field_bit_size = 16, + .description = "flow_cntr_ptr", + .field_bit_size = 14, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", + .description = "age_enable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_byp_lkup_en", + .description = "agg_cntr_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "allowed_pri", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "rate_cntr_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "flow_cntr_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "tcpflags_key", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", + .description = "tcpflags_mir", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "tcpflags_match", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "encap_ptr", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */ { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} - }, - { - .description = "l2_cntxt_tcam_index", + .description = "dst_ip_ptr", .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tcp_dst_port", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_property_ptr", + .description = "src_ip_ptr", .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */ { - .description = "ecv_tun_type", - .field_bit_size = 3, + .description = "tcp_src_port", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_l4_type", - .field_bit_size = 3, + .description = "meter_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_l3_type", - .field_bit_size = 3, + .description = "l3_rdir", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_l2_en", + .description = "tl3_rdir", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_vtag_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} - }, - { - .description = "ecv_custom_en", + .description = "l3_ttl_dec", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_valid", + .description = "tl3_ttl_dec", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vtag_tpid", - .field_bit_size = 16, + .description = "decap_func", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0x81, - 0x00} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vtag_vid", + .description = "vnic_or_vport", .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_WP_SYM_LOOPBACK_PORT & 0xff} }, { - .description = "vtag_de", + .description = "pop_vlan", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vtag_pcp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "spare", - .field_bit_size = 80, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, + .description = "meter", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "age_enable", - .field_bit_size = 1, + .description = "mirror", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "agg_cntr_en", + .description = "drop", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rate_cntr_en", + .description = "hit", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "flow_cntr_en", + .description = "type", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ { - .description = "tcpflags_key", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "tcpflags_mir", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { - .description = "tcpflags_match", + .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "encap_ptr", - .field_bit_size = 11, + .description = "parif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + ULP_WP_SYM_LOOPBACK_PARIF} }, { - .description = "tcp_dst_port", - .field_bit_size = 16, + .description = "allowed_pri", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_ip_ptr", - .field_bit_size = 10, + .description = "default_pri", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcp_src_port", - .field_bit_size = 16, + .description = "allowed_tpid", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, + .description = "default_tpid", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", + .description = "bd_act_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_rdir", - .field_bit_size = 1, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl_dec", + .description = "byp_sp_lkup", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tl3_ttl_dec", - .field_bit_size = 1, + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "decap_func", - .field_bit_size = 4, + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_egr_wr */ { - .description = "vnic_or_vport", - .field_bit_size = 12, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_WP_SYM_LOOPBACK_PORT & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "pop_vlan", - .field_bit_size = 1, + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { - .description = "meter", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "mirror", - .field_bit_size = 2, + .description = "src_property_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.vf_egr */ { - .description = "drop", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, + /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.vf_egr */ { - .description = "hit", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, + /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.vf_egr */ { - .description = "type", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */ + /* class_tid: 4, wh_plus, table: int_full_act_record.vf_ing */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13052,17 +14434,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", @@ -13099,7 +14479,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vf_ing */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -13198,16 +14578,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_egr0 */ { .description = "act_record_ptr", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", @@ -13265,7 +14642,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "sp_rec_ptr", @@ -13297,180 +14676,326 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { - .description = "l2_byp_lkup_en", + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 4, wh_plus, table: int_vtag_encap_record.vfr_egr0 */ + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", + .description = "ecv_vtag_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_LOOPBACK_PARIF} + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "ecv_custom_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_pri", + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0x81, + 0x00} + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "spare", + .field_bit_size = 80, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_egr0 */ + { + .description = "flow_cntr_ptr", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "age_enable", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "agg_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rate_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_cntr_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_key", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_mir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcpflags_match", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + }, + { + .description = "dst_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_dst_port", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ip_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, + .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tcp_src_port", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "meter_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", + .description = "l3_rdir", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "tl3_rdir", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", + .description = "l3_ttl_dec", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "tl3_ttl_dec", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "decap_func", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { - .description = "rid", - .field_bit_size = 32, + .description = "vnic_or_vport", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_WP_SYM_LOOPBACK_PORT & 0xff} }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "pop_vlan", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "meter", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "mirror", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "drop", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "hit", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "type", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: int_full_act_record.ing */ + /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_ing0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13611,15 +15136,17 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "meter", @@ -13656,7 +15183,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */ + /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -13755,188 +15282,101 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 7, wh_plus, table: int_full_act_record.0 */ - { - .description = "flow_cntr_ptr", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, + /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { - .description = "age_enable", - .field_bit_size = 1, + .description = "act_record_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "agg_cntr_en", + .description = "reserved", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rate_cntr_en", + .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "flow_cntr_en", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_key", + .description = "allowed_pri", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tcpflags_mir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcpflags_match", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "dst_ip_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcp_dst_port", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "src_ip_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tcp_src_port", - .field_bit_size = 16, + .description = "default_pri", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meter_id", - .field_bit_size = 10, + .description = "allowed_tpid", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_rdir", - .field_bit_size = 1, + .description = "default_tpid", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_rdir", + .description = "bd_act_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl_dec", - .field_bit_size = 1, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ttl_dec", + .description = "byp_sp_lkup", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "vnic_or_vport", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_WP_SYM_LOOPBACK_PORT & 0xff} - }, - { - .description = "pop_vlan", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meter", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + 1} }, { - .description = "mirror", + .description = "pri_anti_spoof_ctl", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "type", - .field_bit_size = 1, + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -13951,6 +15391,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 42 }, + /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -13997,6 +15444,15 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, + /* class_tid: 1, wh_plus, table: profile_tcam.vxlan */ + { + .description = "em_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 28 + }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ { .description = "l2_cntxt_id", @@ -14004,6 +15460,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 42 }, + /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", @@ -14050,7 +15513,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14059,7 +15522,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14068,7 +15531,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */ + /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 6e4d4d3ff3..b35846c7a9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -28,6 +28,7 @@ #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 #define BNXT_ULP_PROTO_HDR_GRE_NUM 6 +#define BNXT_ULP_PROTO_HDR_ICMP_NUM 5 #define BNXT_ULP_PROTO_HDR_MAX 128 #define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1 @@ -204,6 +205,16 @@ struct bnxt_ulp_device_params { uint64_t packet_count_mask; uint32_t byte_count_shift; uint32_t packet_count_shift; + uint32_t dynamic_pad_en; + uint16_t em_blk_size_bits; + uint16_t em_blk_align_bits; + uint16_t em_key_align_bytes; + uint16_t em_result_size_bits; + uint16_t wc_slice_width; + uint16_t wc_max_slices; + uint32_t wc_mode_list[4]; + uint32_t wc_mod_list_max_size; + uint32_t wc_ctl_size_bits; const struct bnxt_ulp_template_device_tbls *dev_tbls; }; @@ -226,6 +237,7 @@ struct bnxt_ulp_mapper_tbl_info { uint8_t direction; enum bnxt_ulp_pri_opc pri_opcode; uint32_t pri_operand; + enum bnxt_ulp_byte_order byte_order; /* conflict resoution opcode */ enum bnxt_ulp_accept_opc accept_opcode; diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h index 2516eaca2c..898071bfe7 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.h +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h @@ -16,10 +16,6 @@ #include "ulp_template_db_enum.h" #include "ulp_template_struct.h" -#if RTE_VERSION_NUM(17, 11, 10, 16) == RTE_VERSION -#define RTE_ETHER_ADDR_LEN ETHER_ADDR_LEN -#endif - #define BNXT_OUTER_TUN_FLOW(l3_tun, params) \ ((l3_tun) && \ ULP_BITMAP_ISSET((params)->act_bitmap.bits, \ diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index 095a66a0c7..5dc710338a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -3,6 +3,7 @@ * All rights reserved. */ +#include #include "ulp_utils.h" #include "bnxt_tf_common.h" @@ -232,6 +233,7 @@ ulp_bs_push_msb(uint8_t *bs, uint16_t pos, uint8_t len, uint8_t *val) * big endian. All fields are packed with this order. * * returns 0 on error or 1 on success + * Notes - If bitlen is zero then set it to max. */ uint32_t ulp_blob_init(struct ulp_blob *blob, @@ -243,7 +245,10 @@ ulp_blob_init(struct ulp_blob *blob, BNXT_TF_DBG(ERR, "invalid argument\n"); return 0; /* failure */ } - blob->bitlen = bitlen; + if (bitlen) + blob->bitlen = bitlen; + else + blob->bitlen = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS; blob->byte_order = order; blob->write_idx = 0; memset(blob->data, 0, sizeof(blob->data)); @@ -505,6 +510,31 @@ ulp_blob_pad_push(struct ulp_blob *blob, return datalen; } +/* + * Adds pad to an initialized blob at the current offset based on + * the alignment. + * + * blob [in] The blob that needs to be aligned + * + * align [in] Alignment in bits. + * + * returns the number of pad bits added, -1 on failure + */ +int32_t +ulp_blob_pad_align(struct ulp_blob *blob, + uint32_t align) +{ + int32_t pad = 0; + + pad = RTE_ALIGN(blob->write_idx, align) - blob->write_idx; + if (pad > (int32_t)(blob->bitlen - blob->write_idx)) { + BNXT_TF_DBG(ERR, "Pad too large for blob\n"); + return -1; + } + blob->write_idx += pad; + return pad; +} + /* Get data from src and put into dst using little-endian format */ static void ulp_bs_get_lsb(uint8_t *src, uint16_t bitpos, uint8_t bitlen, uint8_t *dst) @@ -668,6 +698,24 @@ ulp_blob_data_get(struct ulp_blob *blob, return blob->data; } +/* + * Get the data length of the binary blob. + * + * blob [in] The blob's data len to be retrieved. + * + * returns length of the binary blob + */ +uint16_t +ulp_blob_data_len_get(struct ulp_blob *blob) +{ + /* validate the arguments */ + if (!blob) { + BNXT_TF_DBG(ERR, "invalid argument\n"); + return 0; /* failure */ + } + return blob->write_idx; +} + /* * Set the encap swap start index of the binary blob. * @@ -731,14 +779,17 @@ ulp_blob_perform_encap_swap(struct ulp_blob *blob) * vice-versa. * * blob [in] The blob's data to be used for swap. + * chunk_size[in] the swap is done within the chunk in bytes * * returns void. */ void -ulp_blob_perform_byte_reverse(struct ulp_blob *blob) +ulp_blob_perform_byte_reverse(struct ulp_blob *blob, + uint32_t chunk_size) { - uint32_t idx = 0, num = 0; + uint32_t idx = 0, jdx = 0, num = 0; uint8_t xchar; + uint8_t *buff; /* validate the arguments */ if (!blob) { @@ -746,11 +797,15 @@ ulp_blob_perform_byte_reverse(struct ulp_blob *blob) return; /* failure */ } - num = ULP_BITS_2_BYTE_NR(blob->write_idx); - for (idx = 0; idx < (num / 2); idx++) { - xchar = blob->data[idx]; - blob->data[idx] = blob->data[(num - 1) - idx]; - blob->data[(num - 1) - idx] = xchar; + buff = blob->data; + num = ULP_BITS_2_BYTE(blob->write_idx) / chunk_size; + for (idx = 0; idx < num; idx++) { + for (jdx = 0; jdx < chunk_size / 2; jdx++) { + xchar = buff[jdx]; + buff[jdx] = buff[(chunk_size - 1) - jdx]; + buff[(chunk_size - 1) - jdx] = xchar; + } + buff += chunk_size; } } @@ -816,6 +871,122 @@ ulp_blob_perform_64B_byte_swap(struct ulp_blob *blob) } } +static int32_t +ulp_blob_msb_block_merge(struct ulp_blob *dst, struct ulp_blob *src, + uint32_t block_size, uint32_t pad) +{ + uint32_t i, k, write_bytes, remaining; + uint16_t num; + uint8_t *src_buf = ulp_blob_data_get(src, &num); + uint8_t bluff; + + for (i = 0; i < num;) { + if (((dst->write_idx % block_size) + (num - i)) > block_size) + write_bytes = block_size - dst->write_idx; + else + write_bytes = num - i; + for (k = 0; k < ULP_BITS_2_BYTE_NR(write_bytes); k++) { + ulp_bs_put_msb(dst->data, dst->write_idx, ULP_BLOB_BYTE, + *src_buf); + dst->write_idx += ULP_BLOB_BYTE; + src_buf++; + } + remaining = write_bytes % ULP_BLOB_BYTE; + if (remaining) { + bluff = (*src_buf) & ((uint8_t)-1 << + (ULP_BLOB_BYTE - remaining)); + ulp_bs_put_msb(dst->data, dst->write_idx, + ULP_BLOB_BYTE, bluff); + dst->write_idx += remaining; + } + if (write_bytes != (num - i)) { + /* add the padding */ + ulp_blob_pad_push(dst, pad); + if (remaining) { + ulp_bs_put_msb(dst->data, dst->write_idx, + ULP_BLOB_BYTE - remaining, + *src_buf); + dst->write_idx += ULP_BLOB_BYTE - remaining; + src_buf++; + } + } + i += write_bytes; + } + return 0; +} + +/* + * Perform the blob buffer merge. + * This api makes the src blob merged to the dst blob. + * The block size and pad size help in padding the dst blob + * + * dst [in] The destination blob, the blob to be merged. + * src [in] The src blob. + * block_size [in] The size of the block after which padding gets applied. + * pad [in] The size of the pad to be applied. + * + * returns 0 on success. + */ +int32_t +ulp_blob_block_merge(struct ulp_blob *dst, struct ulp_blob *src, + uint32_t block_size, uint32_t pad) +{ + if (dst->byte_order == BNXT_ULP_BYTE_ORDER_BE && + src->byte_order == BNXT_ULP_BYTE_ORDER_BE) + return ulp_blob_msb_block_merge(dst, src, block_size, pad); + + BNXT_TF_DBG(ERR, "block merge not implemented yet\n"); + return -EINVAL; +} + +int32_t +ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src, + uint16_t src_offset, uint16_t src_len) +{ + uint32_t k, remaining; + uint16_t num; + uint8_t bluff; + uint8_t *src_buf = ulp_blob_data_get(src, &num); + + if ((src_offset + src_len) > num) + return -EINVAL; + + /* Only supporting BE for now */ + if (src->byte_order != BNXT_ULP_BYTE_ORDER_BE || + dst->byte_order != BNXT_ULP_BYTE_ORDER_BE) + return -EINVAL; + + /* Handle if the source offset is not on a byte boundary */ + remaining = src_offset % ULP_BLOB_BYTE; + if (remaining) { + bluff = src_buf[src_offset / ULP_BLOB_BYTE] & ((uint8_t)-1 >> + (ULP_BLOB_BYTE - remaining)); + ulp_bs_put_msb(dst->data, dst->write_idx, + ULP_BLOB_BYTE, bluff); + dst->write_idx += remaining; + } + + /* Push the byte aligned pieces */ + for (k = 0; k < ULP_BITS_2_BYTE_NR(src_len); k++) { + ulp_bs_put_msb(dst->data, dst->write_idx, ULP_BLOB_BYTE, + *src_buf); + dst->write_idx += ULP_BLOB_BYTE; + src_buf++; + } + + /* Handle the remaining if length is not a byte boundary */ + remaining = src_len % ULP_BLOB_BYTE; + if (remaining) { + bluff = (*src_buf) & ((uint8_t)-1 << + (ULP_BLOB_BYTE - remaining)); + ulp_bs_put_msb(dst->data, dst->write_idx, + ULP_BLOB_BYTE, bluff); + dst->write_idx += remaining; + } + + return 0; +} + /* * Read data from the operand * diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h index 2d62b25060..a30361b8ae 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.h +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2019 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -9,10 +9,12 @@ #include "bnxt.h" #include "ulp_template_db_enum.h" +#define ULP_BUFFER_ALIGN_8_BITS 8 #define ULP_BUFFER_ALIGN_8_BYTE 8 #define ULP_BUFFER_ALIGN_16_BYTE 16 #define ULP_BUFFER_ALIGN_64_BYTE 64 #define ULP_64B_IN_BYTES 8 + /* * Macros for bitmap sets and gets * These macros can be used if the val are power of 2. @@ -289,6 +291,16 @@ uint8_t * ulp_blob_data_get(struct ulp_blob *blob, uint16_t *datalen); +/* + * Get the data length of the binary blob. + * + * blob [in] The blob's data len to be retrieved. + * + * returns length of the binary blob + */ +uint16_t +ulp_blob_data_len_get(struct ulp_blob *blob); + /* * Get data from the byte array in Little endian format. * @@ -356,6 +368,20 @@ int32_t ulp_blob_pad_push(struct ulp_blob *blob, uint32_t datalen); +/* + * Adds pad to an initialized blob at the current offset based on + * the alignment. + * + * blob [in] The blob that needs to be aligned + * + * align [in] Alignment in bits. + * + * returns the number of pad bits added, -1 on failure + */ +int32_t +ulp_blob_pad_align(struct ulp_blob *blob, + uint32_t align); + /* * Set the 64 bit swap start index of the binary blob. * @@ -383,11 +409,13 @@ ulp_blob_perform_encap_swap(struct ulp_blob *blob); * vice-versa. * * blob [in] The blob's data to be used for swap. + * chunk_size[in] the swap is done within the chunk in bytes * * returns void. */ void -ulp_blob_perform_byte_reverse(struct ulp_blob *blob); +ulp_blob_perform_byte_reverse(struct ulp_blob *blob, + uint32_t chunk_size); /* * Perform the blob buffer 64 bit word swap. @@ -413,6 +441,40 @@ ulp_blob_perform_64B_word_swap(struct ulp_blob *blob); void ulp_blob_perform_64B_byte_swap(struct ulp_blob *blob); +/* + * Perform the blob buffer merge. + * This api makes the src blob merged to the dst blob. + * The block size and pad size help in padding the dst blob + * + * dst [in] The destination blob, the blob to be merged. + * src [in] The src blob. + * block_size [in] The size of the block after which padding gets applied. + * pad [in] The size of the pad to be applied. + * + * returns 0 on success. + */ +int32_t +ulp_blob_block_merge(struct ulp_blob *dst, struct ulp_blob *src, + uint32_t block_size, uint32_t pad); + +/* + * Append bits from src blob to dst blob. + * Only works on BE blobs + * + * dst [in/out] The destination blob to append to + * + * src [in] The src blob to append from + * + * src_offset [in] The bit offset from src to start at + * + * src_len [in] The number of bits to append to dst + * + * returns 0 on success, non-zero on error + */ +int32_t +ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src, + uint16_t src_offset, uint16_t src_len); + /* * Read data from the operand * From patchwork Sun May 30 08:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93697 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 07668A0524; Tue, 1 Jun 2021 09:42:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 325B841145; Tue, 1 Jun 2021 09:40:10 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id B420F41102 for ; Sun, 30 May 2021 11:01:53 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 62D527DC0; Sun, 30 May 2021 02:01:50 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 62D527DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365313; bh=jVA6BtyCsdSQgUdt9d9LcN/BpaohswKVHsedC1QkaxA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K18Bw8QHTrORwm3TFixHp4wexp5Pv/ep1VhbcBjez5qZ3JRezy9DJkzUWQ7WRJ3C/ Xdyk1jdhyI3Fj9RBfSNExO6xddU9vQkxfDVwV1p63t4zMrQG4E/cVmQzL12Zii9ULQ 9Uw8SrGgqrjujWXa2yXP314tN31Xd/ryW+0UfVoU= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:18 +0530 Message-Id: <20210530085929.29695-48-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:54 +0200 Subject: [dpdk-dev] [PATCH 47/58] net/bnxt: refactor flow parser in ULP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha 1. Remove Ether type, Vlan type and IP proto type from pattern matching, since the header bits can be used for matching. This reduces the class template signatures by a factor of 8. 2. Remove the wild card bit in the pattern matching since same template can be used for both exact and wild card entries. 3. The action record pointers have to use higher range to not collide with the firmware action record pointers. Hence reduced the number of action record pointers for whitney platform. 4. The conditional update opcode provide functionality to reject flows for instance reject flows that do not adhere to flow signature match. 5. Added check to not populate protocol specifications if the protocol mask is null or zero. 6. Check that field array is not overrun. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 4 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 193 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_matcher.c | 4 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 926 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 7 + .../net/bnxt/tf_ulp/ulp_template_db_class.c | 96165 ++-------------- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 5307 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 31 +- .../bnxt/tf_ulp/ulp_template_db_thor_act.c | 1 - .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 220 +- .../tf_ulp/ulp_template_db_wh_plus_class.c | 302 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 13 +- drivers/net/bnxt/tf_ulp/ulp_utils.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_utils.h | 2 +- 15 files changed, 8494 insertions(+), 94685 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 141bc0c784..dd992a246b 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -94,7 +94,7 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp, /* Table Types */ res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 16384; + res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 8192; res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023; /* ENCAP */ @@ -130,7 +130,7 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp, /* Table Types */ res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 16384; + res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 8192; res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023; /* ENCAP */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 90ba38d05b..60c60564c4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -2844,45 +2844,6 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, return rc; } -/* - * Function to process the memtype opcode of the mapper table. - * returns 1 to skip the table. - * return 0 to continue processing the table. - * - * defaults to skip - */ -static int32_t -ulp_mapper_tbl_memtype_opcode_process(struct bnxt_ulp_mapper_parms *parms, - struct bnxt_ulp_mapper_tbl_info *tbl) -{ - enum bnxt_ulp_flow_mem_type mtype = BNXT_ULP_FLOW_MEM_TYPE_INT; - int32_t rc = 1; - - if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) { - BNXT_TF_DBG(ERR, "Failed to get the mem type\n"); - return rc; - } - - switch (tbl->mem_type_opcode) { - case BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT: - if (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) - rc = 0; - break; - case BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT: - if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT) - rc = 0; - break; - case BNXT_ULP_MEM_TYPE_OPC_NOP: - rc = 0; - break; - default: - BNXT_TF_DBG(ERR, - "Invalid arg in mapper in memtype opcode\n"); - break; - } - return rc; -} - /* * Common conditional opcode process routine that is used for both the template * rejection and table conditional execution. @@ -2893,6 +2854,7 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, uint32_t operand, int32_t *res) { + enum bnxt_ulp_flow_mem_type mtype = BNXT_ULP_FLOW_MEM_TYPE_INT; int32_t rc = 0; uint8_t bit; uint64_t regval; @@ -3002,6 +2964,20 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } break; + case BNXT_ULP_COND_OPC_EXT_MEM_IS_SET: + if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) { + BNXT_TF_DBG(ERR, "Failed to get the mem type\n"); + return -EINVAL; + } + *res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 0 : 1; + break; + case BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET: + if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) { + BNXT_TF_DBG(ERR, "Failed to get the mem type\n"); + return -EINVAL; + } + *res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0; + break; default: BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc); rc = -EINVAL; @@ -3010,6 +2986,113 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, return (rc); } +static int32_t +ulp_mapper_cc_upd_opr_compute(struct bnxt_ulp_mapper_parms *parms, + enum tf_dir dir, + enum bnxt_ulp_cc_upd_src cc_src, + uint16_t cc_opr, + uint64_t *result) +{ + uint64_t regval; + + *result = false; + switch (cc_src) { + case BNXT_ULP_CC_UPD_SRC_COMP_FIELD: + if (cc_opr >= BNXT_ULP_CF_IDX_LAST) { + BNXT_TF_DBG(ERR, "invalid index %u\n", cc_opr); + return -EINVAL; + } + *result = (uint64_t)ULP_COMP_FLD_IDX_RD(parms, cc_opr); + break; + case BNXT_ULP_CC_UPD_SRC_REGFILE: + if (!ulp_regfile_read(parms->regfile, cc_opr, ®val)) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", cc_opr); + return -EINVAL; + } + *result = tfp_be_to_cpu_64(regval); + break; + case BNXT_ULP_CC_UPD_SRC_GLB_REGFILE: + if (ulp_mapper_glb_resource_read(parms->mapper_data, dir, + cc_opr, ®val)) { + BNXT_TF_DBG(ERR, "global regfile[%d] read failed.\n", + cc_opr); + return -EINVAL; + } + *result = tfp_be_to_cpu_64(regval); + break; + default: + BNXT_TF_DBG(ERR, "invalid src code %u\n", cc_src); + return -EINVAL; + } + return 0; +} + +static int32_t +ulp_mapper_cc_upd_info_process(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl) +{ + struct bnxt_ulp_mapper_cc_upd_info *cc_upd = &tbl->cc_upd_info; + uint64_t res = 0, res1, res2; + int32_t rc = 0; + + if (cc_upd->cc_opc == BNXT_ULP_CC_UPD_OPC_NOP) + return rc; + + rc = ulp_mapper_cc_upd_opr_compute(parms, tbl->direction, + cc_upd->cc_src1, + cc_upd->cc_opr1, &res1); + if (rc) + return rc; + + rc = ulp_mapper_cc_upd_opr_compute(parms, tbl->direction, + cc_upd->cc_src2, + cc_upd->cc_opr2, &res2); + if (rc) + return rc; + + switch (cc_upd->cc_opc) { + case BNXT_ULP_CC_UPD_OPC_NOP: + res = 1; + break; + case BNXT_ULP_CC_UPD_OPC_EQ: + if (res1 == res2) + res = 1; + break; + case BNXT_ULP_CC_UPD_OPC_NE: + if (res1 != res2) + res = 1; + break; + case BNXT_ULP_CC_UPD_OPC_GE: + if (res1 >= res2) + res = 1; + break; + case BNXT_ULP_CC_UPD_OPC_GT: + if (res1 > res2) + res = 1; + break; + case BNXT_ULP_CC_UPD_OPC_LE: + if (res1 <= res2) + res = 1; + break; + case BNXT_ULP_CC_UPD_OPC_LT: + if (res1 < res2) + res = 1; + break; + case BNXT_ULP_CC_UPD_OPC_LAST: + BNXT_TF_DBG(ERR, "invalid code %u\n", cc_upd->cc_opc); + return -EINVAL; + } + if (ulp_regfile_write(parms->regfile, cc_upd->cc_dst_opr, + tfp_cpu_to_be_64(res))) { + BNXT_TF_DBG(ERR, "Failed write the cc_opc %u\n", + cc_upd->cc_dst_opr); + return -EINVAL; + } + + return rc; +} + + /* * Processes a list of conditions and returns both a status and result of the * list. The status must be checked prior to verifying the result. @@ -3045,6 +3128,7 @@ ulp_mapper_cond_opc_list_process(struct bnxt_ulp_mapper_parms *parms, default: BNXT_TF_DBG(ERR, "Invalid conditional list opcode %d\n", list_opc); + *res = 0; return -EINVAL; } @@ -3184,10 +3268,11 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) { tbl = &tbls[tbl_idx]; - /* Handle the table level opcodes to determine if required. */ - if (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) { - cond_goto = tbl->execute_info.cond_false_goto; - goto next_iteration; + /* Process the conditional code update opcodes */ + if (ulp_mapper_cc_upd_info_process(parms, tbl)) { + BNXT_TF_DBG(ERR, "Failed to process cond update\n"); + rc = -EINVAL; + goto error; } cond_tbls = ulp_mapper_tbl_execute_list_get(parms, tbl, @@ -3199,7 +3284,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) if (rc) { BNXT_TF_DBG(ERR, "Failed to process cond opc list " "(%d)\n", rc); - return rc; + goto error; } /* Skip the table if False */ if (!cond_rc) { @@ -3251,6 +3336,26 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) goto error; } next_iteration: + if (cond_goto == BNXT_ULP_COND_GOTO_REJECT) { + BNXT_TF_DBG(ERR, "reject the flow\n"); + rc = -EINVAL; + goto error; + } else if (cond_goto & BNXT_ULP_COND_GOTO_RF) { + uint32_t rf_idx; + uint64_t regval; + + /* least significant 16 bits from reg_file index */ + rf_idx = (uint32_t)(cond_goto & 0xFFFF); + if (!ulp_regfile_read(parms->regfile, rf_idx, + ®val)) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", + rf_idx); + rc = -EINVAL; + goto error; + } + cond_goto = (int32_t)regval; + } + if (cond_goto < 0 && ((int32_t)tbl_idx + cond_goto) < 0) { BNXT_TF_DBG(ERR, "invalid conditional goto %d\n", cond_goto); diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 8652dd203c..9432462404 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -26,7 +26,7 @@ struct bnxt_ulp_mapper_glb_resource_entry { struct bnxt_ulp_mapper_data { struct bnxt_ulp_mapper_glb_resource_entry - glb_res_tbl[TF_DIR_MAX][BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ]; + glb_res_tbl[TF_DIR_MAX][BNXT_ULP_GLB_RF_IDX_LAST]; struct ulp_mapper_gen_tbl_list gen_tbl_list[BNXT_ULP_GEN_TBL_MAX_SZ]; }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c index 46ac57ac00..8040fb7515 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c @@ -52,7 +52,7 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params, /* calculate the hash of the given flow */ class_hid = ulp_matcher_class_hash_calculate(params->hdr_bitmap.bits, - params->fld_bitmap.bits); + params->fld_s_bitmap.bits); /* validate the calculate hash values */ if (class_hid >= BNXT_ULP_CLASS_SIG_TBL_MAX_SZ) @@ -66,7 +66,7 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params, BNXT_TF_DBG(DEBUG, "Proto Header does not match\n"); goto error; } - if (ULP_BITMAP_CMP(¶ms->fld_bitmap, &class_match->field_sig)) { + if (ULP_BITMAP_CMP(¶ms->fld_s_bitmap, &class_match->field_sig)) { BNXT_TF_DBG(DEBUG, "Field signature does not match\n"); goto error; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 0e585e502e..0d52c0b93b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -42,13 +42,16 @@ ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment) /* Utility function to update the field_bitmap */ static void ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params, - uint32_t idx) + uint32_t idx, + enum bnxt_ulp_prsr_action prsr_act) { struct ulp_rte_hdr_field *field; field = ¶ms->hdr_field[idx]; if (ulp_bitmap_notzero(field->mask, field->size)) { ULP_INDEX_BITMAP_SET(params->fld_bitmap.bits, idx); + if (!(prsr_act & ULP_PRSR_ACT_MATCH_IGNORE)) + ULP_INDEX_BITMAP_SET(params->fld_s_bitmap.bits, idx); /* Not exact match */ if (!ulp_bitmap_is_ones(field->mask, field->size)) ULP_COMP_FLD_IDX_WR(params, @@ -58,40 +61,48 @@ ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params, } } -/* Utility function to copy field spec items */ -static struct ulp_rte_hdr_field * -ulp_rte_parser_fld_copy(struct ulp_rte_hdr_field *field, - const void *buffer, - uint32_t size) -{ - field->size = size; - memcpy(field->spec, buffer, field->size); - field++; - return field; -} - -/* Utility function to copy field masks items */ +#define ulp_deference_struct(x, y) ((x) ? &((x)->y) : NULL) +/* Utility function to copy field spec and masks items */ static void -ulp_rte_prsr_mask_copy(struct ulp_rte_parser_params *params, - uint32_t *idx, - const void *buffer, - uint32_t size) +ulp_rte_prsr_fld_mask(struct ulp_rte_parser_params *params, + uint32_t *idx, + uint32_t size, + const void *spec_buff, + const void *mask_buff, + enum bnxt_ulp_prsr_action prsr_act) { struct ulp_rte_hdr_field *field = ¶ms->hdr_field[*idx]; - memcpy(field->mask, buffer, size); - ulp_rte_parser_field_bitmap_update(params, *idx); + /* update the field size */ + field->size = size; + + /* copy the mask specifications only if mask is not null */ + if (!(prsr_act & ULP_PRSR_ACT_MASK_IGNORE) && mask_buff) { + memcpy(field->mask, mask_buff, size); + ulp_rte_parser_field_bitmap_update(params, *idx, prsr_act); + } + + /* copy the protocol specifications only if mask is not null*/ + if (spec_buff && mask_buff && ulp_bitmap_notzero(mask_buff, size)) + memcpy(field->spec, spec_buff, size); + + /* Increment the index */ *idx = *idx + 1; } -/* Utility function to ignore field masks items */ -static void -ulp_rte_prsr_mask_ignore(struct ulp_rte_parser_params *params __rte_unused, - uint32_t *idx, - const void *buffer __rte_unused, - uint32_t size __rte_unused) +/* Utility function to copy field spec and masks items */ +static int32_t +ulp_rte_prsr_fld_size_validate(struct ulp_rte_parser_params *params, + uint32_t *idx, + uint32_t size) { - *idx = *idx + 1; + if (params->field_idx + size >= BNXT_ULP_PROTO_HDR_MAX) { + BNXT_TF_DBG(ERR, "OOB for field processing %u\n", *idx); + return -EINVAL; + } + *idx = params->field_idx; + params->field_idx += size; + return 0; } /* @@ -649,48 +660,49 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, { const struct rte_flow_item_eth *eth_spec = item->spec; const struct rte_flow_item_eth *eth_mask = item->mask; - struct ulp_rte_hdr_field *field; - uint32_t idx = params->field_idx; + uint32_t idx = 0; uint32_t size; uint16_t eth_type = 0; uint32_t inner_flag = 0; - /* - * Copy the rte_flow_item for eth into hdr_field using ethernet - * header fields - */ + /* Perform validations */ if (eth_spec) { - size = sizeof(eth_spec->dst.addr_bytes); - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - eth_spec->dst.addr_bytes, - size); /* Todo: work around to avoid multicast and broadcast addr */ if (ulp_rte_parser_is_bcmc_addr(ð_spec->dst)) return BNXT_TF_RC_PARSE_ERR; - size = sizeof(eth_spec->src.addr_bytes); - field = ulp_rte_parser_fld_copy(field, - eth_spec->src.addr_bytes, - size); - /* Todo: work around to avoid multicast and broadcast addr */ if (ulp_rte_parser_is_bcmc_addr(ð_spec->src)) return BNXT_TF_RC_PARSE_ERR; - field = ulp_rte_parser_fld_copy(field, - ð_spec->type, - sizeof(eth_spec->type)); eth_type = eth_spec->type; } - if (eth_mask) { - ulp_rte_prsr_mask_copy(params, &idx, eth_mask->dst.addr_bytes, - sizeof(eth_mask->dst.addr_bytes)); - ulp_rte_prsr_mask_copy(params, &idx, eth_mask->src.addr_bytes, - sizeof(eth_mask->src.addr_bytes)); - ulp_rte_prsr_mask_copy(params, &idx, ð_mask->type, - sizeof(eth_mask->type)); + + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_ETH_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; } - /* Add number of Eth header elements */ - params->field_idx += BNXT_ULP_PROTO_HDR_ETH_NUM; + /* + * Copy the rte_flow_item for eth into hdr_field using ethernet + * header fields + */ + size = sizeof(((struct rte_flow_item_eth *)NULL)->dst.addr_bytes); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(eth_spec, dst.addr_bytes), + ulp_deference_struct(eth_mask, dst.addr_bytes), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_eth *)NULL)->src.addr_bytes); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(eth_spec, src.addr_bytes), + ulp_deference_struct(eth_mask, src.addr_bytes), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_eth *)NULL)->type); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(eth_spec, type), + ulp_deference_struct(eth_mask, type), + ULP_PRSR_ACT_MATCH_IGNORE); /* Update the protocol hdr bitmap */ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, @@ -721,42 +733,28 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, { const struct rte_flow_item_vlan *vlan_spec = item->spec; const struct rte_flow_item_vlan *vlan_mask = item->mask; - struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bit; - uint32_t idx = params->field_idx; - uint16_t vlan_tag, priority; + uint32_t idx = 0; + uint16_t vlan_tag = 0, priority = 0; + uint16_t vlan_tag_mask = 0, priority_mask = 0; uint32_t outer_vtag_num; uint32_t inner_vtag_num; uint16_t eth_type = 0; uint32_t inner_flag = 0; + uint32_t size; - /* - * Copy the rte_flow_item for vlan into hdr_field using Vlan - * header fields - */ if (vlan_spec) { vlan_tag = ntohs(vlan_spec->tci); priority = htons(vlan_tag >> ULP_VLAN_PRIORITY_SHIFT); vlan_tag &= ULP_VLAN_TAG_MASK; vlan_tag = htons(vlan_tag); - - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - &priority, - sizeof(priority)); - field = ulp_rte_parser_fld_copy(field, - &vlan_tag, - sizeof(vlan_tag)); - - field = ulp_rte_parser_fld_copy(field, - &vlan_spec->inner_type, - sizeof(vlan_spec->inner_type)); eth_type = vlan_spec->inner_type; } if (vlan_mask) { - vlan_tag = ntohs(vlan_mask->tci); - priority = htons(vlan_tag >> ULP_VLAN_PRIORITY_SHIFT); - vlan_tag &= 0xfff; + vlan_tag_mask = ntohs(vlan_mask->tci); + priority_mask = htons(vlan_tag_mask >> ULP_VLAN_PRIORITY_SHIFT); + vlan_tag_mask &= 0xfff; /* * the storage for priority and vlan tag is 2 bytes @@ -764,27 +762,44 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, * then make the rest bits 13 bits as 1's * so that it is matched as exact match. */ - if (priority == ULP_VLAN_PRIORITY_MASK) - priority |= ~ULP_VLAN_PRIORITY_MASK; - if (vlan_tag == ULP_VLAN_TAG_MASK) - vlan_tag |= ~ULP_VLAN_TAG_MASK; - vlan_tag = htons(vlan_tag); - - /* - * The priority field is ignored since OVS is setting it as - * wild card match and it is not supported. This is a work - * around and shall be addressed in the future. - */ - ulp_rte_prsr_mask_ignore(params, &idx, &priority, - sizeof(priority)); + if (priority_mask == ULP_VLAN_PRIORITY_MASK) + priority_mask |= ~ULP_VLAN_PRIORITY_MASK; + if (vlan_tag_mask == ULP_VLAN_TAG_MASK) + vlan_tag_mask |= ~ULP_VLAN_TAG_MASK; + vlan_tag_mask = htons(vlan_tag_mask); + } - ulp_rte_prsr_mask_copy(params, &idx, &vlan_tag, - sizeof(vlan_tag)); - ulp_rte_prsr_mask_copy(params, &idx, &vlan_mask->inner_type, - sizeof(vlan_mask->inner_type)); + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_S_VLAN_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; } - /* Set the field index to new incremented value */ - params->field_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM; + + /* + * Copy the rte_flow_item for vlan into hdr_field using Vlan + * header fields + */ + size = sizeof(((struct rte_flow_item_vlan *)NULL)->tci); + /* + * The priority field is ignored since OVS is setting it as + * wild card match and it is not supported. This is a work + * around and shall be addressed in the future. + */ + ulp_rte_prsr_fld_mask(params, &idx, size, + &priority, + &priority_mask, + ULP_PRSR_ACT_MASK_IGNORE); + + ulp_rte_prsr_fld_mask(params, &idx, size, + &vlan_tag, + &vlan_tag_mask, + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_vlan *)NULL)->inner_type); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(vlan_spec, inner_type), + ulp_deference_struct(vlan_mask, inner_type), + ULP_PRSR_ACT_MATCH_IGNORE); /* Get the outer tag and inner tag counts */ outer_vtag_num = ULP_COMP_FLD_IDX_RD(params, @@ -910,9 +925,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, { const struct rte_flow_item_ipv4 *ipv4_spec = item->spec; const struct rte_flow_item_ipv4 *ipv4_mask = item->mask; - struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = params->field_idx; + uint32_t idx = 0; uint32_t size; uint8_t proto = 0; uint32_t inner_flag = 0; @@ -941,94 +955,89 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, params->field_idx = idx; } + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_IPV4_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; + } + /* * Copy the rte_flow_item for ipv4 into hdr_field using ipv4 * header fields */ - if (ipv4_spec) { - size = sizeof(ipv4_spec->hdr.version_ihl); - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - &ipv4_spec->hdr.version_ihl, - size); - size = sizeof(ipv4_spec->hdr.type_of_service); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.type_of_service, - size); - size = sizeof(ipv4_spec->hdr.total_length); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.total_length, - size); - size = sizeof(ipv4_spec->hdr.packet_id); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.packet_id, - size); - size = sizeof(ipv4_spec->hdr.fragment_offset); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.fragment_offset, - size); - size = sizeof(ipv4_spec->hdr.time_to_live); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.time_to_live, - size); - size = sizeof(ipv4_spec->hdr.next_proto_id); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.next_proto_id, - size); + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.version_ihl); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, hdr.version_ihl), + ulp_deference_struct(ipv4_mask, hdr.version_ihl), + ULP_PRSR_ACT_DEFAULT); + + /* + * The tos field is ignored since OVS is setting it as wild card + * match and it is not supported. This is a work around and + * shall be addressed in the future. + */ + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.type_of_service); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, + hdr.type_of_service), + ulp_deference_struct(ipv4_mask, + hdr.type_of_service), + ULP_PRSR_ACT_MASK_IGNORE); + + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.total_length); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, hdr.total_length), + ulp_deference_struct(ipv4_mask, hdr.total_length), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.packet_id); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, hdr.packet_id), + ulp_deference_struct(ipv4_mask, hdr.packet_id), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.fragment_offset); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, + hdr.fragment_offset), + ulp_deference_struct(ipv4_mask, + hdr.fragment_offset), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.time_to_live); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, hdr.time_to_live), + ulp_deference_struct(ipv4_mask, hdr.time_to_live), + ULP_PRSR_ACT_DEFAULT); + + /* Ignore proto for matching templates */ + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.next_proto_id); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, + hdr.next_proto_id), + ulp_deference_struct(ipv4_mask, + hdr.next_proto_id), + ULP_PRSR_ACT_MATCH_IGNORE); + if (ipv4_spec) proto = ipv4_spec->hdr.next_proto_id; - size = sizeof(ipv4_spec->hdr.hdr_checksum); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.hdr_checksum, - size); - size = sizeof(ipv4_spec->hdr.src_addr); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.src_addr, - size); - size = sizeof(ipv4_spec->hdr.dst_addr); - field = ulp_rte_parser_fld_copy(field, - &ipv4_spec->hdr.dst_addr, - size); - } - if (ipv4_mask) { - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.version_ihl, - sizeof(ipv4_mask->hdr.version_ihl)); - /* - * The tos field is ignored since OVS is setting it as wild card - * match and it is not supported. This is a work around and - * shall be addressed in the future. - */ - ulp_rte_prsr_mask_ignore(params, &idx, - &ipv4_mask->hdr.type_of_service, - sizeof(ipv4_mask->hdr.type_of_service) - ); - - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.total_length, - sizeof(ipv4_mask->hdr.total_length)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.packet_id, - sizeof(ipv4_mask->hdr.packet_id)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.fragment_offset, - sizeof(ipv4_mask->hdr.fragment_offset)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.time_to_live, - sizeof(ipv4_mask->hdr.time_to_live)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.next_proto_id, - sizeof(ipv4_mask->hdr.next_proto_id)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.hdr_checksum, - sizeof(ipv4_mask->hdr.hdr_checksum)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.src_addr, - sizeof(ipv4_mask->hdr.src_addr)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv4_mask->hdr.dst_addr, - sizeof(ipv4_mask->hdr.dst_addr)); - } - /* Add the number of ipv4 header elements */ - params->field_idx += BNXT_ULP_PROTO_HDR_IPV4_NUM; + + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.hdr_checksum); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, hdr.hdr_checksum), + ulp_deference_struct(ipv4_mask, hdr.hdr_checksum), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.src_addr); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, hdr.src_addr), + ulp_deference_struct(ipv4_mask, hdr.src_addr), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.dst_addr); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv4_spec, hdr.dst_addr), + ulp_deference_struct(ipv4_mask, hdr.dst_addr), + ULP_PRSR_ACT_DEFAULT); /* Set the ipv4 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || @@ -1061,11 +1070,12 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, { const struct rte_flow_item_ipv6 *ipv6_spec = item->spec; const struct rte_flow_item_ipv6 *ipv6_mask = item->mask; - struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = params->field_idx; + uint32_t idx = 0; uint32_t size; - uint32_t vtcf, vtcf_mask; + uint32_t ver_spec = 0, ver_mask = 0; + uint32_t tc_spec = 0, tc_mask = 0; + uint32_t lab_spec = 0, lab_mask = 0; uint8_t proto = 0; uint32_t inner_flag = 0; uint32_t cnt; @@ -1093,87 +1103,79 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, params->field_idx = idx; } + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_IPV6_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; + } + /* * Copy the rte_flow_item for ipv6 into hdr_field using ipv6 * header fields */ if (ipv6_spec) { - size = sizeof(ipv6_spec->hdr.vtc_flow); - - vtcf = BNXT_ULP_GET_IPV6_VER(ipv6_spec->hdr.vtc_flow); - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - &vtcf, - size); - - vtcf = BNXT_ULP_GET_IPV6_TC(ipv6_spec->hdr.vtc_flow); - field = ulp_rte_parser_fld_copy(field, - &vtcf, - size); - - vtcf = BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_spec->hdr.vtc_flow); - field = ulp_rte_parser_fld_copy(field, - &vtcf, - size); - - size = sizeof(ipv6_spec->hdr.payload_len); - field = ulp_rte_parser_fld_copy(field, - &ipv6_spec->hdr.payload_len, - size); - size = sizeof(ipv6_spec->hdr.proto); - field = ulp_rte_parser_fld_copy(field, - &ipv6_spec->hdr.proto, - size); + ver_spec = BNXT_ULP_GET_IPV6_VER(ipv6_spec->hdr.vtc_flow); + tc_spec = BNXT_ULP_GET_IPV6_TC(ipv6_spec->hdr.vtc_flow); + lab_spec = BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_spec->hdr.vtc_flow); proto = ipv6_spec->hdr.proto; - size = sizeof(ipv6_spec->hdr.hop_limits); - field = ulp_rte_parser_fld_copy(field, - &ipv6_spec->hdr.hop_limits, - size); - size = sizeof(ipv6_spec->hdr.src_addr); - field = ulp_rte_parser_fld_copy(field, - &ipv6_spec->hdr.src_addr, - size); - size = sizeof(ipv6_spec->hdr.dst_addr); - field = ulp_rte_parser_fld_copy(field, - &ipv6_spec->hdr.dst_addr, - size); } + if (ipv6_mask) { - size = sizeof(ipv6_mask->hdr.vtc_flow); + ver_mask = BNXT_ULP_GET_IPV6_VER(ipv6_mask->hdr.vtc_flow); + tc_mask = BNXT_ULP_GET_IPV6_TC(ipv6_mask->hdr.vtc_flow); + lab_mask = BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_mask->hdr.vtc_flow); - vtcf_mask = BNXT_ULP_GET_IPV6_VER(ipv6_mask->hdr.vtc_flow); - ulp_rte_prsr_mask_copy(params, &idx, - &vtcf_mask, - size); - /* - * The TC and flow label field are ignored since OVS is - * setting it for match and it is not supported. - * This is a work around and - * shall be addressed in the future. + /* Some of the PMD applications may set the protocol field + * in the IPv6 spec but don't set the mask. So, consider + * the mask in proto value calculation. */ - vtcf_mask = BNXT_ULP_GET_IPV6_TC(ipv6_mask->hdr.vtc_flow); - ulp_rte_prsr_mask_ignore(params, &idx, &vtcf_mask, size); - vtcf_mask = - BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_mask->hdr.vtc_flow); - ulp_rte_prsr_mask_ignore(params, &idx, &vtcf_mask, size); - - ulp_rte_prsr_mask_copy(params, &idx, - &ipv6_mask->hdr.payload_len, - sizeof(ipv6_mask->hdr.payload_len)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv6_mask->hdr.proto, - sizeof(ipv6_mask->hdr.proto)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv6_mask->hdr.hop_limits, - sizeof(ipv6_mask->hdr.hop_limits)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv6_mask->hdr.src_addr, - sizeof(ipv6_mask->hdr.src_addr)); - ulp_rte_prsr_mask_copy(params, &idx, - &ipv6_mask->hdr.dst_addr, - sizeof(ipv6_mask->hdr.dst_addr)); - } - /* add number of ipv6 header elements */ - params->field_idx += BNXT_ULP_PROTO_HDR_IPV6_NUM; + proto &= ipv6_mask->hdr.proto; + } + + size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.vtc_flow); + ulp_rte_prsr_fld_mask(params, &idx, size, &ver_spec, &ver_mask, + ULP_PRSR_ACT_DEFAULT); + /* + * The TC and flow label field are ignored since OVS is + * setting it for match and it is not supported. + * This is a work around and + * shall be addressed in the future. + */ + ulp_rte_prsr_fld_mask(params, &idx, size, &tc_spec, &tc_mask, + ULP_PRSR_ACT_MASK_IGNORE); + ulp_rte_prsr_fld_mask(params, &idx, size, &lab_spec, &lab_mask, + ULP_PRSR_ACT_MASK_IGNORE); + + size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.payload_len); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv6_spec, hdr.payload_len), + ulp_deference_struct(ipv6_mask, hdr.payload_len), + ULP_PRSR_ACT_DEFAULT); + + /* Ignore proto for template matching */ + size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.proto); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv6_spec, hdr.proto), + ulp_deference_struct(ipv6_mask, hdr.proto), + ULP_PRSR_ACT_MATCH_IGNORE); + + size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.hop_limits); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv6_spec, hdr.hop_limits), + ulp_deference_struct(ipv6_mask, hdr.hop_limits), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.src_addr); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv6_spec, hdr.src_addr), + ulp_deference_struct(ipv6_mask, hdr.src_addr), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.dst_addr); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(ipv6_spec, hdr.dst_addr), + ulp_deference_struct(ipv6_mask, hdr.dst_addr), + ULP_PRSR_ACT_DEFAULT); /* Set the ipv6 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || @@ -1186,13 +1188,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } - /* Some of the PMD applications may set the protocol field - * in the IPv6 spec but don't set the mask. So, consider - * the mask in proto value calculation. - */ - if (ipv6_mask) - proto &= ipv6_mask->hdr.proto; - /* Update the field protocol hdr bitmap */ ulp_rte_l3_proto_type_update(params, proto, inner_flag); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); @@ -1214,7 +1209,6 @@ ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param, ULP_BITMAP_ISSET(param->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_GRE)) ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1); - } /* Function to handle the parsing of RTE Flow item UDP Header. */ @@ -1224,9 +1218,8 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, { const struct rte_flow_item_udp *udp_spec = item->spec; const struct rte_flow_item_udp *udp_mask = item->mask; - struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = params->field_idx; + uint32_t idx = 0; uint32_t size; uint16_t dport = 0, sport = 0; uint32_t cnt; @@ -1237,47 +1230,44 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, return BNXT_TF_RC_ERROR; } + if (udp_spec) { + sport = udp_spec->hdr.src_port; + dport = udp_spec->hdr.dst_port; + } + + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_UDP_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; + } + /* * Copy the rte_flow_item for ipv4 into hdr_field using ipv4 * header fields */ - if (udp_spec) { - size = sizeof(udp_spec->hdr.src_port); - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - &udp_spec->hdr.src_port, - size); - sport = udp_spec->hdr.src_port; - size = sizeof(udp_spec->hdr.dst_port); - field = ulp_rte_parser_fld_copy(field, - &udp_spec->hdr.dst_port, - size); - dport = udp_spec->hdr.dst_port; - size = sizeof(udp_spec->hdr.dgram_len); - field = ulp_rte_parser_fld_copy(field, - &udp_spec->hdr.dgram_len, - size); - size = sizeof(udp_spec->hdr.dgram_cksum); - field = ulp_rte_parser_fld_copy(field, - &udp_spec->hdr.dgram_cksum, - size); - } - if (udp_mask) { - ulp_rte_prsr_mask_copy(params, &idx, - &udp_mask->hdr.src_port, - sizeof(udp_mask->hdr.src_port)); - ulp_rte_prsr_mask_copy(params, &idx, - &udp_mask->hdr.dst_port, - sizeof(udp_mask->hdr.dst_port)); - ulp_rte_prsr_mask_copy(params, &idx, - &udp_mask->hdr.dgram_len, - sizeof(udp_mask->hdr.dgram_len)); - ulp_rte_prsr_mask_copy(params, &idx, - &udp_mask->hdr.dgram_cksum, - sizeof(udp_mask->hdr.dgram_cksum)); - } - - /* Add number of UDP header elements */ - params->field_idx += BNXT_ULP_PROTO_HDR_UDP_NUM; + size = sizeof(((struct rte_flow_item_udp *)NULL)->hdr.src_port); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(udp_spec, hdr.src_port), + ulp_deference_struct(udp_mask, hdr.src_port), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_udp *)NULL)->hdr.dst_port); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(udp_spec, hdr.dst_port), + ulp_deference_struct(udp_mask, hdr.dst_port), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_udp *)NULL)->hdr.dgram_len); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(udp_spec, hdr.dgram_len), + ulp_deference_struct(udp_mask, hdr.dgram_len), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_udp *)NULL)->hdr.dgram_cksum); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(udp_spec, hdr.dgram_cksum), + ulp_deference_struct(udp_mask, hdr.dgram_cksum), + ULP_PRSR_ACT_DEFAULT); /* Set the udp header bitmap and computed l4 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) || @@ -1334,9 +1324,8 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, { const struct rte_flow_item_tcp *tcp_spec = item->spec; const struct rte_flow_item_tcp *tcp_mask = item->mask; - struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = params->field_idx; + uint32_t idx = 0; uint16_t dport = 0, sport = 0; uint32_t size; uint32_t cnt; @@ -1347,84 +1336,74 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, return BNXT_TF_RC_ERROR; } + if (tcp_spec) { + sport = tcp_spec->hdr.src_port; + dport = tcp_spec->hdr.dst_port; + } + + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_TCP_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; + } + /* * Copy the rte_flow_item for ipv4 into hdr_field using ipv4 * header fields */ - if (tcp_spec) { - sport = tcp_spec->hdr.src_port; - size = sizeof(tcp_spec->hdr.src_port); - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - &tcp_spec->hdr.src_port, - size); - dport = tcp_spec->hdr.dst_port; - size = sizeof(tcp_spec->hdr.dst_port); - field = ulp_rte_parser_fld_copy(field, - &tcp_spec->hdr.dst_port, - size); - size = sizeof(tcp_spec->hdr.sent_seq); - field = ulp_rte_parser_fld_copy(field, - &tcp_spec->hdr.sent_seq, - size); - size = sizeof(tcp_spec->hdr.recv_ack); - field = ulp_rte_parser_fld_copy(field, - &tcp_spec->hdr.recv_ack, - size); - size = sizeof(tcp_spec->hdr.data_off); - field = ulp_rte_parser_fld_copy(field, - &tcp_spec->hdr.data_off, - size); - size = sizeof(tcp_spec->hdr.tcp_flags); - field = ulp_rte_parser_fld_copy(field, - &tcp_spec->hdr.tcp_flags, - size); - size = sizeof(tcp_spec->hdr.rx_win); - field = ulp_rte_parser_fld_copy(field, - &tcp_spec->hdr.rx_win, - size); - size = sizeof(tcp_spec->hdr.cksum); - field = ulp_rte_parser_fld_copy(field, - &tcp_spec->hdr.cksum, - size); - size = sizeof(tcp_spec->hdr.tcp_urp); - field = ulp_rte_parser_fld_copy(field, - &tcp_spec->hdr.tcp_urp, - size); - } else { - idx += BNXT_ULP_PROTO_HDR_TCP_NUM; - } - - if (tcp_mask) { - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.src_port, - sizeof(tcp_mask->hdr.src_port)); - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.dst_port, - sizeof(tcp_mask->hdr.dst_port)); - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.sent_seq, - sizeof(tcp_mask->hdr.sent_seq)); - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.recv_ack, - sizeof(tcp_mask->hdr.recv_ack)); - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.data_off, - sizeof(tcp_mask->hdr.data_off)); - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.tcp_flags, - sizeof(tcp_mask->hdr.tcp_flags)); - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.rx_win, - sizeof(tcp_mask->hdr.rx_win)); - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.cksum, - sizeof(tcp_mask->hdr.cksum)); - ulp_rte_prsr_mask_copy(params, &idx, - &tcp_mask->hdr.tcp_urp, - sizeof(tcp_mask->hdr.tcp_urp)); - } - /* add number of TCP header elements */ - params->field_idx += BNXT_ULP_PROTO_HDR_TCP_NUM; + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.src_port); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.src_port), + ulp_deference_struct(tcp_mask, hdr.src_port), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.dst_port); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.dst_port), + ulp_deference_struct(tcp_mask, hdr.dst_port), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.sent_seq); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.sent_seq), + ulp_deference_struct(tcp_mask, hdr.sent_seq), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.recv_ack); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.recv_ack), + ulp_deference_struct(tcp_mask, hdr.recv_ack), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.data_off); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.data_off), + ulp_deference_struct(tcp_mask, hdr.data_off), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.tcp_flags); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.tcp_flags), + ulp_deference_struct(tcp_mask, hdr.tcp_flags), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.rx_win); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.rx_win), + ulp_deference_struct(tcp_mask, hdr.rx_win), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.cksum); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.cksum), + ulp_deference_struct(tcp_mask, hdr.cksum), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_tcp *)NULL)->hdr.tcp_urp); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(tcp_spec, hdr.tcp_urp), + ulp_deference_struct(tcp_mask, hdr.tcp_urp), + ULP_PRSR_ACT_DEFAULT); /* Set the udp header bitmap and computed l4 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) || @@ -1478,49 +1457,43 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item, { const struct rte_flow_item_vxlan *vxlan_spec = item->spec; const struct rte_flow_item_vxlan *vxlan_mask = item->mask; - struct ulp_rte_hdr_field *field; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = params->field_idx; + uint32_t idx = 0; uint32_t size; + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_VXLAN_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; + } + /* * Copy the rte_flow_item for vxlan into hdr_field using vxlan * header fields */ - if (vxlan_spec) { - size = sizeof(vxlan_spec->flags); - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - &vxlan_spec->flags, - size); - size = sizeof(vxlan_spec->rsvd0); - field = ulp_rte_parser_fld_copy(field, - &vxlan_spec->rsvd0, - size); - size = sizeof(vxlan_spec->vni); - field = ulp_rte_parser_fld_copy(field, - &vxlan_spec->vni, - size); - size = sizeof(vxlan_spec->rsvd1); - field = ulp_rte_parser_fld_copy(field, - &vxlan_spec->rsvd1, - size); - } - if (vxlan_mask) { - ulp_rte_prsr_mask_copy(params, &idx, - &vxlan_mask->flags, - sizeof(vxlan_mask->flags)); - ulp_rte_prsr_mask_copy(params, &idx, - &vxlan_mask->rsvd0, - sizeof(vxlan_mask->rsvd0)); - ulp_rte_prsr_mask_copy(params, &idx, - &vxlan_mask->vni, - sizeof(vxlan_mask->vni)); - ulp_rte_prsr_mask_copy(params, &idx, - &vxlan_mask->rsvd1, - sizeof(vxlan_mask->rsvd1)); - } - /* Add number of vxlan header elements */ - params->field_idx += BNXT_ULP_PROTO_HDR_VXLAN_NUM; + size = sizeof(((struct rte_flow_item_vxlan *)NULL)->flags); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(vxlan_spec, flags), + ulp_deference_struct(vxlan_mask, flags), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_vxlan *)NULL)->rsvd0); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(vxlan_spec, rsvd0), + ulp_deference_struct(vxlan_mask, rsvd0), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_vxlan *)NULL)->vni); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(vxlan_spec, vni), + ulp_deference_struct(vxlan_mask, vni), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_vxlan *)NULL)->rsvd1); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(vxlan_spec, rsvd1), + ulp_deference_struct(vxlan_mask, rsvd1), + ULP_PRSR_ACT_DEFAULT); /* Update the hdr_bitmap with vxlan */ ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN); @@ -1531,35 +1504,31 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item, /* Function to handle the parsing of RTE Flow item GRE Header. */ int32_t ulp_rte_gre_hdr_handler(const struct rte_flow_item *item, - struct ulp_rte_parser_params *params) + struct ulp_rte_parser_params *params) { const struct rte_flow_item_gre *gre_spec = item->spec; const struct rte_flow_item_gre *gre_mask = item->mask; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = params->field_idx; + uint32_t idx = 0; uint32_t size; - struct ulp_rte_hdr_field *field; - if (gre_spec) { - size = sizeof(gre_spec->c_rsvd0_ver); - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - &gre_spec->c_rsvd0_ver, - size); - size = sizeof(gre_spec->protocol); - field = ulp_rte_parser_fld_copy(field, - &gre_spec->protocol, - size); - } - if (gre_mask) { - ulp_rte_prsr_mask_copy(params, &idx, - &gre_mask->c_rsvd0_ver, - sizeof(gre_mask->c_rsvd0_ver)); - ulp_rte_prsr_mask_copy(params, &idx, - &gre_mask->protocol, - sizeof(gre_mask->protocol)); - } - /* Add number of GRE header elements */ - params->field_idx += BNXT_ULP_PROTO_HDR_GRE_NUM; + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_GRE_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; + } + + size = sizeof(((struct rte_flow_item_gre *)NULL)->c_rsvd0_ver); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(gre_spec, c_rsvd0_ver), + ulp_deference_struct(gre_mask, c_rsvd0_ver), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_gre *)NULL)->protocol); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(gre_spec, protocol), + ulp_deference_struct(gre_mask, protocol), + ULP_PRSR_ACT_DEFAULT); /* Update the hdr_bitmap with GRE */ ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE); @@ -1583,51 +1552,44 @@ ulp_rte_icmp_hdr_handler(const struct rte_flow_item *item, const struct rte_flow_item_icmp *icmp_spec = item->spec; const struct rte_flow_item_icmp *icmp_mask = item->mask; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = params->field_idx; + uint32_t idx = 0; uint32_t size; - struct ulp_rte_hdr_field *field; - if (icmp_spec) { - size = sizeof(icmp_spec->hdr.icmp_type); - field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx], - &icmp_spec->hdr.icmp_type, - size); - size = sizeof(icmp_spec->hdr.icmp_code); - field = ulp_rte_parser_fld_copy(field, - &icmp_spec->hdr.icmp_code, - size); - size = sizeof(icmp_spec->hdr.icmp_cksum); - field = ulp_rte_parser_fld_copy(field, - &icmp_spec->hdr.icmp_cksum, - size); - size = sizeof(icmp_spec->hdr.icmp_ident); - field = ulp_rte_parser_fld_copy(field, - &icmp_spec->hdr.icmp_ident, - size); - size = sizeof(icmp_spec->hdr.icmp_seq_nb); - field = ulp_rte_parser_fld_copy(field, - &icmp_spec->hdr.icmp_seq_nb, - size); - } - if (icmp_mask) { - ulp_rte_prsr_mask_copy(params, &idx, - &icmp_mask->hdr.icmp_type, - sizeof(icmp_mask->hdr.icmp_type)); - ulp_rte_prsr_mask_copy(params, &idx, - &icmp_mask->hdr.icmp_code, - sizeof(icmp_mask->hdr.icmp_code)); - ulp_rte_prsr_mask_copy(params, &idx, - &icmp_mask->hdr.icmp_cksum, - sizeof(icmp_mask->hdr.icmp_cksum)); - ulp_rte_prsr_mask_copy(params, &idx, - &icmp_mask->hdr.icmp_ident, - sizeof(icmp_mask->hdr.icmp_ident)); - ulp_rte_prsr_mask_copy(params, &idx, - &icmp_mask->hdr.icmp_seq_nb, - sizeof(icmp_mask->hdr.icmp_seq_nb)); - } - /* Add number of GRE header elements */ - params->field_idx += BNXT_ULP_PROTO_HDR_ICMP_NUM; + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_ICMP_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; + } + + size = sizeof(((struct rte_flow_item_icmp *)NULL)->hdr.icmp_type); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(icmp_spec, hdr.icmp_type), + ulp_deference_struct(icmp_mask, hdr.icmp_type), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_icmp *)NULL)->hdr.icmp_code); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(icmp_spec, hdr.icmp_code), + ulp_deference_struct(icmp_mask, hdr.icmp_code), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_icmp *)NULL)->hdr.icmp_cksum); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(icmp_spec, hdr.icmp_cksum), + ulp_deference_struct(icmp_mask, hdr.icmp_cksum), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_icmp *)NULL)->hdr.icmp_ident); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(icmp_spec, hdr.icmp_ident), + ulp_deference_struct(icmp_mask, hdr.icmp_ident), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_icmp *)NULL)->hdr.icmp_seq_nb); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(icmp_spec, hdr.icmp_seq_nb), + ulp_deference_struct(icmp_mask, hdr.icmp_seq_nb), + ULP_PRSR_ACT_DEFAULT); /* Update the hdr_bitmap with ICMP */ if (ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) @@ -2121,7 +2083,8 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item, * offset must be added to the absolute first vf id of that port. */ if (ulp_port_db_dev_func_id_to_ulp_index(params->ulp_ctx, - bp->first_vf_id + vf_action->id, + bp->first_vf_id + + vf_action->id, &ifindex)) { BNXT_TF_DBG(ERR, "VF is not valid interface\n"); return BNXT_TF_RC_ERROR; @@ -2410,7 +2373,7 @@ ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *act __rte_unused, /* Function to handle the parsing of RTE Flow action JUMP */ int32_t ulp_rte_jump_act_handler(const struct rte_flow_action *action_item __rte_unused, - struct ulp_rte_parser_params *params) + struct ulp_rte_parser_params *params) { /* Update the act_bitmap with dec ttl */ ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP); @@ -2449,7 +2412,8 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item, ret = bnxt_ulp_rte_parser_act_parse(sample->actions, params); if (ret == BNXT_TF_RC_SUCCESS) /* Update the act_bitmap with sample */ - ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_SAMPLE); + ULP_BITMAP_SET(params->act_bitmap.bits, + BNXT_ULP_ACT_BIT_SAMPLE); return ret; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index 664878401a..66abe8e656 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -36,6 +36,13 @@ #define BNXT_ULP_PARSER_IPV6_TC 0x0ff00000 #define BNXT_ULP_PARSER_IPV6_FLOW_LABEL 0x000fffff +enum bnxt_ulp_prsr_action { + ULP_PRSR_ACT_DEFAULT = 0, + ULP_PRSR_ACT_MATCH_IGNORE = 1, + ULP_PRSR_ACT_MASK_IGNORE = 2, + ULP_PRSR_ACT_SPEC_IGNORE = 4 +}; + void bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, struct ulp_rte_parser_params *params, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index e9e7feb64c..7be8322b13 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 3 12:15:37 2021 */ +/* date: Fri Mar 5 12:31:34 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -16,4576 +16,698 @@ * maps hash id to ulp_class_match_list[] index */ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_05d1] = 1, - [BNXT_ULP_CLASS_HID_1229] = 2, - [BNXT_ULP_CLASS_HID_0bed] = 3, - [BNXT_ULP_CLASS_HID_1865] = 4, - [BNXT_ULP_CLASS_HID_25c9] = 5, - [BNXT_ULP_CLASS_HID_3241] = 6, - [BNXT_ULP_CLASS_HID_2c05] = 7, - [BNXT_ULP_CLASS_HID_389d] = 8, - [BNXT_ULP_CLASS_HID_3c3d] = 9, - [BNXT_ULP_CLASS_HID_48b5] = 10, - [BNXT_ULP_CLASS_HID_4279] = 11, - [BNXT_ULP_CLASS_HID_4ef1] = 12, - [BNXT_ULP_CLASS_HID_5c55] = 13, - [BNXT_ULP_CLASS_HID_0be1] = 14, - [BNXT_ULP_CLASS_HID_05a5] = 15, - [BNXT_ULP_CLASS_HID_123d] = 16, - [BNXT_ULP_CLASS_HID_4142d] = 17, - [BNXT_ULP_CLASS_HID_42095] = 18, - [BNXT_ULP_CLASS_HID_41a69] = 19, - [BNXT_ULP_CLASS_HID_426d1] = 20, - [BNXT_ULP_CLASS_HID_44a99] = 21, - [BNXT_ULP_CLASS_HID_45701] = 22, - [BNXT_ULP_CLASS_HID_450c5] = 23, - [BNXT_ULP_CLASS_HID_40071] = 24, - [BNXT_ULP_CLASS_HID_40a85] = 25, - [BNXT_ULP_CLASS_HID_4170d] = 26, - [BNXT_ULP_CLASS_HID_410c1] = 27, - [BNXT_ULP_CLASS_HID_41d49] = 28, - [BNXT_ULP_CLASS_HID_440f1] = 29, - [BNXT_ULP_CLASS_HID_44d79] = 30, - [BNXT_ULP_CLASS_HID_4473d] = 31, - [BNXT_ULP_CLASS_HID_453a5] = 32, - [BNXT_ULP_CLASS_HID_244e3] = 33, - [BNXT_ULP_CLASS_HID_2517b] = 34, - [BNXT_ULP_CLASS_HID_24b3f] = 35, - [BNXT_ULP_CLASS_HID_257b7] = 36, - [BNXT_ULP_CLASS_HID_22f5f] = 37, - [BNXT_ULP_CLASS_HID_23bd7] = 38, - [BNXT_ULP_CLASS_HID_2359b] = 39, - [BNXT_ULP_CLASS_HID_24213] = 40, - [BNXT_ULP_CLASS_HID_20bab] = 41, - [BNXT_ULP_CLASS_HID_21823] = 42, - [BNXT_ULP_CLASS_HID_211e7] = 43, - [BNXT_ULP_CLASS_HID_21e7f] = 44, - [BNXT_ULP_CLASS_HID_252f3] = 45, - [BNXT_ULP_CLASS_HID_2029f] = 46, - [BNXT_ULP_CLASS_HID_2590f] = 47, - [BNXT_ULP_CLASS_HID_208db] = 48, - [BNXT_ULP_CLASS_HID_231d3] = 49, - [BNXT_ULP_CLASS_HID_23e2b] = 50, - [BNXT_ULP_CLASS_HID_237ef] = 51, - [BNXT_ULP_CLASS_HID_24467] = 52, - [BNXT_ULP_CLASS_HID_21c0f] = 53, - [BNXT_ULP_CLASS_HID_22887] = 54, - [BNXT_ULP_CLASS_HID_2224b] = 55, - [BNXT_ULP_CLASS_HID_22ec3] = 56, - [BNXT_ULP_CLASS_HID_25547] = 57, - [BNXT_ULP_CLASS_HID_20513] = 58, - [BNXT_ULP_CLASS_HID_25b83] = 59, - [BNXT_ULP_CLASS_HID_20b2f] = 60, - [BNXT_ULP_CLASS_HID_23fa3] = 61, - [BNXT_ULP_CLASS_HID_24c3b] = 62, - [BNXT_ULP_CLASS_HID_245ff] = 63, - [BNXT_ULP_CLASS_HID_25277] = 64, - [BNXT_ULP_CLASS_HID_64037] = 65, - [BNXT_ULP_CLASS_HID_64c8f] = 66, - [BNXT_ULP_CLASS_HID_64673] = 67, - [BNXT_ULP_CLASS_HID_652cb] = 68, - [BNXT_ULP_CLASS_HID_62a93] = 69, - [BNXT_ULP_CLASS_HID_636eb] = 70, - [BNXT_ULP_CLASS_HID_630af] = 71, - [BNXT_ULP_CLASS_HID_63d27] = 72, - [BNXT_ULP_CLASS_HID_606ff] = 73, - [BNXT_ULP_CLASS_HID_61377] = 74, - [BNXT_ULP_CLASS_HID_60d3b] = 75, - [BNXT_ULP_CLASS_HID_619b3] = 76, - [BNXT_ULP_CLASS_HID_64e07] = 77, - [BNXT_ULP_CLASS_HID_65a9f] = 78, - [BNXT_ULP_CLASS_HID_65443] = 79, - [BNXT_ULP_CLASS_HID_603ef] = 80, - [BNXT_ULP_CLASS_HID_62ce7] = 81, - [BNXT_ULP_CLASS_HID_6397f] = 82, - [BNXT_ULP_CLASS_HID_63323] = 83, - [BNXT_ULP_CLASS_HID_63fbb] = 84, - [BNXT_ULP_CLASS_HID_61743] = 85, - [BNXT_ULP_CLASS_HID_623db] = 86, - [BNXT_ULP_CLASS_HID_61d9f] = 87, - [BNXT_ULP_CLASS_HID_62a17] = 88, - [BNXT_ULP_CLASS_HID_6509b] = 89, - [BNXT_ULP_CLASS_HID_60027] = 90, - [BNXT_ULP_CLASS_HID_656d7] = 91, - [BNXT_ULP_CLASS_HID_60663] = 92, - [BNXT_ULP_CLASS_HID_63af7] = 93, - [BNXT_ULP_CLASS_HID_6474f] = 94, - [BNXT_ULP_CLASS_HID_64133] = 95, - [BNXT_ULP_CLASS_HID_64d8b] = 96, - [BNXT_ULP_CLASS_HID_a3fb] = 97, - [BNXT_ULP_CLASS_HID_b063] = 98, - [BNXT_ULP_CLASS_HID_aa27] = 99, - [BNXT_ULP_CLASS_HID_b6af] = 100, - [BNXT_ULP_CLASS_HID_8e47] = 101, - [BNXT_ULP_CLASS_HID_9acf] = 102, - [BNXT_ULP_CLASS_HID_9483] = 103, - [BNXT_ULP_CLASS_HID_a10b] = 104, - [BNXT_ULP_CLASS_HID_c78f] = 105, - [BNXT_ULP_CLASS_HID_d3f7] = 106, - [BNXT_ULP_CLASS_HID_cdcb] = 107, - [BNXT_ULP_CLASS_HID_da33] = 108, - [BNXT_ULP_CLASS_HID_b1eb] = 109, - [BNXT_ULP_CLASS_HID_be53] = 110, - [BNXT_ULP_CLASS_HID_b817] = 111, - [BNXT_ULP_CLASS_HID_c49f] = 112, - [BNXT_ULP_CLASS_HID_49f2f] = 113, - [BNXT_ULP_CLASS_HID_4ab97] = 114, - [BNXT_ULP_CLASS_HID_4a56b] = 115, - [BNXT_ULP_CLASS_HID_4b1d3] = 116, - [BNXT_ULP_CLASS_HID_4898b] = 117, - [BNXT_ULP_CLASS_HID_495f3] = 118, - [BNXT_ULP_CLASS_HID_48fb7] = 119, - [BNXT_ULP_CLASS_HID_49c3f] = 120, - [BNXT_ULP_CLASS_HID_4c2b3] = 121, - [BNXT_ULP_CLASS_HID_4cf3b] = 122, - [BNXT_ULP_CLASS_HID_4c8ff] = 123, - [BNXT_ULP_CLASS_HID_4d567] = 124, - [BNXT_ULP_CLASS_HID_4ad1f] = 125, - [BNXT_ULP_CLASS_HID_4b987] = 126, - [BNXT_ULP_CLASS_HID_4b35b] = 127, - [BNXT_ULP_CLASS_HID_4bfc3] = 128, - [BNXT_ULP_CLASS_HID_1b9fb] = 129, - [BNXT_ULP_CLASS_HID_1c663] = 130, - [BNXT_ULP_CLASS_HID_1c027] = 131, - [BNXT_ULP_CLASS_HID_1ccaf] = 132, - [BNXT_ULP_CLASS_HID_1a447] = 133, - [BNXT_ULP_CLASS_HID_1b0cf] = 134, - [BNXT_ULP_CLASS_HID_1aa83] = 135, - [BNXT_ULP_CLASS_HID_1b70b] = 136, - [BNXT_ULP_CLASS_HID_180b3] = 137, - [BNXT_ULP_CLASS_HID_18d3b] = 138, - [BNXT_ULP_CLASS_HID_186ff] = 139, - [BNXT_ULP_CLASS_HID_19367] = 140, - [BNXT_ULP_CLASS_HID_1c7eb] = 141, - [BNXT_ULP_CLASS_HID_1d453] = 142, - [BNXT_ULP_CLASS_HID_1ce17] = 143, - [BNXT_ULP_CLASS_HID_1da9f] = 144, - [BNXT_ULP_CLASS_HID_5b52f] = 145, - [BNXT_ULP_CLASS_HID_5c197] = 146, - [BNXT_ULP_CLASS_HID_5bb6b] = 147, - [BNXT_ULP_CLASS_HID_5c7d3] = 148, - [BNXT_ULP_CLASS_HID_59f8b] = 149, - [BNXT_ULP_CLASS_HID_5abf3] = 150, - [BNXT_ULP_CLASS_HID_5a5b7] = 151, - [BNXT_ULP_CLASS_HID_5b23f] = 152, - [BNXT_ULP_CLASS_HID_5d8b3] = 153, - [BNXT_ULP_CLASS_HID_5886f] = 154, - [BNXT_ULP_CLASS_HID_58223] = 155, - [BNXT_ULP_CLASS_HID_58eab] = 156, - [BNXT_ULP_CLASS_HID_5c31f] = 157, - [BNXT_ULP_CLASS_HID_5cf87] = 158, - [BNXT_ULP_CLASS_HID_5c95b] = 159, - [BNXT_ULP_CLASS_HID_5d5c3] = 160, - [BNXT_ULP_CLASS_HID_05f1] = 161, - [BNXT_ULP_CLASS_HID_1209] = 162, - [BNXT_ULP_CLASS_HID_0bcd] = 163, - [BNXT_ULP_CLASS_HID_1845] = 164, - [BNXT_ULP_CLASS_HID_25e9] = 165, - [BNXT_ULP_CLASS_HID_3261] = 166, - [BNXT_ULP_CLASS_HID_2c25] = 167, - [BNXT_ULP_CLASS_HID_38bd] = 168, - [BNXT_ULP_CLASS_HID_3c1d] = 169, - [BNXT_ULP_CLASS_HID_4895] = 170, - [BNXT_ULP_CLASS_HID_4259] = 171, - [BNXT_ULP_CLASS_HID_4ed1] = 172, - [BNXT_ULP_CLASS_HID_5c75] = 173, - [BNXT_ULP_CLASS_HID_0bc1] = 174, - [BNXT_ULP_CLASS_HID_0585] = 175, - [BNXT_ULP_CLASS_HID_121d] = 176, - [BNXT_ULP_CLASS_HID_58c5] = 177, - [BNXT_ULP_CLASS_HID_0891] = 178, - [BNXT_ULP_CLASS_HID_0255] = 179, - [BNXT_ULP_CLASS_HID_0eed] = 180, - [BNXT_ULP_CLASS_HID_1c71] = 181, - [BNXT_ULP_CLASS_HID_2889] = 182, - [BNXT_ULP_CLASS_HID_224d] = 183, - [BNXT_ULP_CLASS_HID_2ec5] = 184, - [BNXT_ULP_CLASS_HID_32a5] = 185, - [BNXT_ULP_CLASS_HID_3f3d] = 186, - [BNXT_ULP_CLASS_HID_38e1] = 187, - [BNXT_ULP_CLASS_HID_4579] = 188, - [BNXT_ULP_CLASS_HID_529d] = 189, - [BNXT_ULP_CLASS_HID_0269] = 190, - [BNXT_ULP_CLASS_HID_58d9] = 191, - [BNXT_ULP_CLASS_HID_08a5] = 192, - [BNXT_ULP_CLASS_HID_400c5] = 193, - [BNXT_ULP_CLASS_HID_40d5d] = 194, - [BNXT_ULP_CLASS_HID_40701] = 195, - [BNXT_ULP_CLASS_HID_41399] = 196, - [BNXT_ULP_CLASS_HID_4213d] = 197, - [BNXT_ULP_CLASS_HID_42db5] = 198, - [BNXT_ULP_CLASS_HID_42779] = 199, - [BNXT_ULP_CLASS_HID_433f1] = 200, - [BNXT_ULP_CLASS_HID_43751] = 201, - [BNXT_ULP_CLASS_HID_443e9] = 202, - [BNXT_ULP_CLASS_HID_43dad] = 203, - [BNXT_ULP_CLASS_HID_44a25] = 204, - [BNXT_ULP_CLASS_HID_45749] = 205, - [BNXT_ULP_CLASS_HID_40715] = 206, - [BNXT_ULP_CLASS_HID_400d9] = 207, - [BNXT_ULP_CLASS_HID_40d51] = 208, - [BNXT_ULP_CLASS_HID_45419] = 209, - [BNXT_ULP_CLASS_HID_403e5] = 210, - [BNXT_ULP_CLASS_HID_45a55] = 211, - [BNXT_ULP_CLASS_HID_40a21] = 212, - [BNXT_ULP_CLASS_HID_41745] = 213, - [BNXT_ULP_CLASS_HID_423dd] = 214, - [BNXT_ULP_CLASS_HID_41d81] = 215, - [BNXT_ULP_CLASS_HID_42a19] = 216, - [BNXT_ULP_CLASS_HID_42df9] = 217, - [BNXT_ULP_CLASS_HID_43a71] = 218, - [BNXT_ULP_CLASS_HID_43435] = 219, - [BNXT_ULP_CLASS_HID_4404d] = 220, - [BNXT_ULP_CLASS_HID_44dd1] = 221, - [BNXT_ULP_CLASS_HID_45a69] = 222, - [BNXT_ULP_CLASS_HID_4542d] = 223, - [BNXT_ULP_CLASS_HID_403f9] = 224, - [BNXT_ULP_CLASS_HID_4140d] = 225, - [BNXT_ULP_CLASS_HID_420b5] = 226, - [BNXT_ULP_CLASS_HID_41a49] = 227, - [BNXT_ULP_CLASS_HID_426f1] = 228, - [BNXT_ULP_CLASS_HID_44ab9] = 229, - [BNXT_ULP_CLASS_HID_45721] = 230, - [BNXT_ULP_CLASS_HID_450e5] = 231, - [BNXT_ULP_CLASS_HID_40051] = 232, - [BNXT_ULP_CLASS_HID_40aa5] = 233, - [BNXT_ULP_CLASS_HID_4172d] = 234, - [BNXT_ULP_CLASS_HID_410e1] = 235, - [BNXT_ULP_CLASS_HID_41d69] = 236, - [BNXT_ULP_CLASS_HID_440d1] = 237, - [BNXT_ULP_CLASS_HID_44d59] = 238, - [BNXT_ULP_CLASS_HID_4471d] = 239, - [BNXT_ULP_CLASS_HID_45385] = 240, - [BNXT_ULP_CLASS_HID_6400d] = 241, - [BNXT_ULP_CLASS_HID_64cb5] = 242, - [BNXT_ULP_CLASS_HID_64649] = 243, - [BNXT_ULP_CLASS_HID_652f1] = 244, - [BNXT_ULP_CLASS_HID_619ed] = 245, - [BNXT_ULP_CLASS_HID_62615] = 246, - [BNXT_ULP_CLASS_HID_62029] = 247, - [BNXT_ULP_CLASS_HID_62c51] = 248, - [BNXT_ULP_CLASS_HID_636a5] = 249, - [BNXT_ULP_CLASS_HID_6432d] = 250, - [BNXT_ULP_CLASS_HID_63ce1] = 251, - [BNXT_ULP_CLASS_HID_64969] = 252, - [BNXT_ULP_CLASS_HID_61005] = 253, - [BNXT_ULP_CLASS_HID_61c8d] = 254, - [BNXT_ULP_CLASS_HID_61641] = 255, - [BNXT_ULP_CLASS_HID_622c9] = 256, - [BNXT_ULP_CLASS_HID_52a0d] = 257, - [BNXT_ULP_CLASS_HID_536b5] = 258, - [BNXT_ULP_CLASS_HID_53049] = 259, - [BNXT_ULP_CLASS_HID_53cf1] = 260, - [BNXT_ULP_CLASS_HID_503ed] = 261, - [BNXT_ULP_CLASS_HID_51015] = 262, - [BNXT_ULP_CLASS_HID_50a29] = 263, - [BNXT_ULP_CLASS_HID_51651] = 264, - [BNXT_ULP_CLASS_HID_520a5] = 265, - [BNXT_ULP_CLASS_HID_52d2d] = 266, - [BNXT_ULP_CLASS_HID_526e1] = 267, - [BNXT_ULP_CLASS_HID_53369] = 268, - [BNXT_ULP_CLASS_HID_556d1] = 269, - [BNXT_ULP_CLASS_HID_5068d] = 270, - [BNXT_ULP_CLASS_HID_50041] = 271, - [BNXT_ULP_CLASS_HID_50cc9] = 272, - [BNXT_ULP_CLASS_HID_7560d] = 273, - [BNXT_ULP_CLASS_HID_705f9] = 274, - [BNXT_ULP_CLASS_HID_75c49] = 275, - [BNXT_ULP_CLASS_HID_70c25] = 276, - [BNXT_ULP_CLASS_HID_72fed] = 277, - [BNXT_ULP_CLASS_HID_73c15] = 278, - [BNXT_ULP_CLASS_HID_73629] = 279, - [BNXT_ULP_CLASS_HID_74251] = 280, - [BNXT_ULP_CLASS_HID_74ca5] = 281, - [BNXT_ULP_CLASS_HID_7592d] = 282, - [BNXT_ULP_CLASS_HID_752e1] = 283, - [BNXT_ULP_CLASS_HID_7025d] = 284, - [BNXT_ULP_CLASS_HID_72605] = 285, - [BNXT_ULP_CLASS_HID_7328d] = 286, - [BNXT_ULP_CLASS_HID_72c41] = 287, - [BNXT_ULP_CLASS_HID_738c9] = 288, - [BNXT_ULP_CLASS_HID_0591] = 289, - [BNXT_ULP_CLASS_HID_1269] = 290, - [BNXT_ULP_CLASS_HID_0bad] = 291, - [BNXT_ULP_CLASS_HID_1825] = 292, - [BNXT_ULP_CLASS_HID_2589] = 293, - [BNXT_ULP_CLASS_HID_3201] = 294, - [BNXT_ULP_CLASS_HID_2c45] = 295, - [BNXT_ULP_CLASS_HID_38dd] = 296, - [BNXT_ULP_CLASS_HID_3c7d] = 297, - [BNXT_ULP_CLASS_HID_48f5] = 298, - [BNXT_ULP_CLASS_HID_4239] = 299, - [BNXT_ULP_CLASS_HID_4eb1] = 300, - [BNXT_ULP_CLASS_HID_5c15] = 301, - [BNXT_ULP_CLASS_HID_0ba1] = 302, - [BNXT_ULP_CLASS_HID_05e5] = 303, - [BNXT_ULP_CLASS_HID_127d] = 304, - [BNXT_ULP_CLASS_HID_58a5] = 305, - [BNXT_ULP_CLASS_HID_08f1] = 306, - [BNXT_ULP_CLASS_HID_0235] = 307, - [BNXT_ULP_CLASS_HID_0e8d] = 308, - [BNXT_ULP_CLASS_HID_1c11] = 309, - [BNXT_ULP_CLASS_HID_28e9] = 310, - [BNXT_ULP_CLASS_HID_222d] = 311, - [BNXT_ULP_CLASS_HID_2ea5] = 312, - [BNXT_ULP_CLASS_HID_32c5] = 313, - [BNXT_ULP_CLASS_HID_3f5d] = 314, - [BNXT_ULP_CLASS_HID_3881] = 315, - [BNXT_ULP_CLASS_HID_4519] = 316, - [BNXT_ULP_CLASS_HID_52fd] = 317, - [BNXT_ULP_CLASS_HID_0209] = 318, - [BNXT_ULP_CLASS_HID_58b9] = 319, - [BNXT_ULP_CLASS_HID_08c5] = 320, - [BNXT_ULP_CLASS_HID_400a5] = 321, - [BNXT_ULP_CLASS_HID_40d3d] = 322, - [BNXT_ULP_CLASS_HID_40761] = 323, - [BNXT_ULP_CLASS_HID_413f9] = 324, - [BNXT_ULP_CLASS_HID_4215d] = 325, - [BNXT_ULP_CLASS_HID_42dd5] = 326, - [BNXT_ULP_CLASS_HID_42719] = 327, - [BNXT_ULP_CLASS_HID_43391] = 328, - [BNXT_ULP_CLASS_HID_43731] = 329, - [BNXT_ULP_CLASS_HID_44389] = 330, - [BNXT_ULP_CLASS_HID_43dcd] = 331, - [BNXT_ULP_CLASS_HID_44a45] = 332, - [BNXT_ULP_CLASS_HID_45729] = 333, - [BNXT_ULP_CLASS_HID_40775] = 334, - [BNXT_ULP_CLASS_HID_400b9] = 335, - [BNXT_ULP_CLASS_HID_40d31] = 336, - [BNXT_ULP_CLASS_HID_45479] = 337, - [BNXT_ULP_CLASS_HID_40385] = 338, - [BNXT_ULP_CLASS_HID_45a35] = 339, - [BNXT_ULP_CLASS_HID_40a41] = 340, - [BNXT_ULP_CLASS_HID_41725] = 341, - [BNXT_ULP_CLASS_HID_423bd] = 342, - [BNXT_ULP_CLASS_HID_41de1] = 343, - [BNXT_ULP_CLASS_HID_42a79] = 344, - [BNXT_ULP_CLASS_HID_42d99] = 345, - [BNXT_ULP_CLASS_HID_43a11] = 346, - [BNXT_ULP_CLASS_HID_43455] = 347, - [BNXT_ULP_CLASS_HID_4402d] = 348, - [BNXT_ULP_CLASS_HID_44db1] = 349, - [BNXT_ULP_CLASS_HID_45a09] = 350, - [BNXT_ULP_CLASS_HID_4544d] = 351, - [BNXT_ULP_CLASS_HID_40399] = 352, - [BNXT_ULP_CLASS_HID_4146d] = 353, - [BNXT_ULP_CLASS_HID_420d5] = 354, - [BNXT_ULP_CLASS_HID_41a29] = 355, - [BNXT_ULP_CLASS_HID_42691] = 356, - [BNXT_ULP_CLASS_HID_44ad9] = 357, - [BNXT_ULP_CLASS_HID_45741] = 358, - [BNXT_ULP_CLASS_HID_45085] = 359, - [BNXT_ULP_CLASS_HID_40031] = 360, - [BNXT_ULP_CLASS_HID_40ac5] = 361, - [BNXT_ULP_CLASS_HID_4174d] = 362, - [BNXT_ULP_CLASS_HID_41081] = 363, - [BNXT_ULP_CLASS_HID_41d09] = 364, - [BNXT_ULP_CLASS_HID_440b1] = 365, - [BNXT_ULP_CLASS_HID_44d39] = 366, - [BNXT_ULP_CLASS_HID_4477d] = 367, - [BNXT_ULP_CLASS_HID_453e5] = 368, - [BNXT_ULP_CLASS_HID_6406d] = 369, - [BNXT_ULP_CLASS_HID_64cd5] = 370, - [BNXT_ULP_CLASS_HID_64629] = 371, - [BNXT_ULP_CLASS_HID_65291] = 372, - [BNXT_ULP_CLASS_HID_6198d] = 373, - [BNXT_ULP_CLASS_HID_62675] = 374, - [BNXT_ULP_CLASS_HID_62049] = 375, - [BNXT_ULP_CLASS_HID_62c31] = 376, - [BNXT_ULP_CLASS_HID_636c5] = 377, - [BNXT_ULP_CLASS_HID_6434d] = 378, - [BNXT_ULP_CLASS_HID_63c81] = 379, - [BNXT_ULP_CLASS_HID_64909] = 380, - [BNXT_ULP_CLASS_HID_61065] = 381, - [BNXT_ULP_CLASS_HID_61ced] = 382, - [BNXT_ULP_CLASS_HID_61621] = 383, - [BNXT_ULP_CLASS_HID_622a9] = 384, - [BNXT_ULP_CLASS_HID_52a6d] = 385, - [BNXT_ULP_CLASS_HID_536d5] = 386, - [BNXT_ULP_CLASS_HID_53029] = 387, - [BNXT_ULP_CLASS_HID_53c91] = 388, - [BNXT_ULP_CLASS_HID_5038d] = 389, - [BNXT_ULP_CLASS_HID_51075] = 390, - [BNXT_ULP_CLASS_HID_50a49] = 391, - [BNXT_ULP_CLASS_HID_51631] = 392, - [BNXT_ULP_CLASS_HID_520c5] = 393, - [BNXT_ULP_CLASS_HID_52d4d] = 394, - [BNXT_ULP_CLASS_HID_52681] = 395, - [BNXT_ULP_CLASS_HID_53309] = 396, - [BNXT_ULP_CLASS_HID_556b1] = 397, - [BNXT_ULP_CLASS_HID_506ed] = 398, - [BNXT_ULP_CLASS_HID_50021] = 399, - [BNXT_ULP_CLASS_HID_50ca9] = 400, - [BNXT_ULP_CLASS_HID_7566d] = 401, - [BNXT_ULP_CLASS_HID_70599] = 402, - [BNXT_ULP_CLASS_HID_75c29] = 403, - [BNXT_ULP_CLASS_HID_70c45] = 404, - [BNXT_ULP_CLASS_HID_72f8d] = 405, - [BNXT_ULP_CLASS_HID_73c75] = 406, - [BNXT_ULP_CLASS_HID_73649] = 407, - [BNXT_ULP_CLASS_HID_74231] = 408, - [BNXT_ULP_CLASS_HID_74cc5] = 409, - [BNXT_ULP_CLASS_HID_7594d] = 410, - [BNXT_ULP_CLASS_HID_75281] = 411, - [BNXT_ULP_CLASS_HID_7023d] = 412, - [BNXT_ULP_CLASS_HID_72665] = 413, - [BNXT_ULP_CLASS_HID_732ed] = 414, - [BNXT_ULP_CLASS_HID_72c21] = 415, - [BNXT_ULP_CLASS_HID_738a9] = 416, - [BNXT_ULP_CLASS_HID_244c3] = 417, - [BNXT_ULP_CLASS_HID_2515b] = 418, - [BNXT_ULP_CLASS_HID_24b1f] = 419, - [BNXT_ULP_CLASS_HID_25797] = 420, - [BNXT_ULP_CLASS_HID_22f7f] = 421, - [BNXT_ULP_CLASS_HID_23bf7] = 422, - [BNXT_ULP_CLASS_HID_235bb] = 423, - [BNXT_ULP_CLASS_HID_24233] = 424, - [BNXT_ULP_CLASS_HID_20b8b] = 425, - [BNXT_ULP_CLASS_HID_21803] = 426, - [BNXT_ULP_CLASS_HID_211c7] = 427, - [BNXT_ULP_CLASS_HID_21e5f] = 428, - [BNXT_ULP_CLASS_HID_252d3] = 429, - [BNXT_ULP_CLASS_HID_202bf] = 430, - [BNXT_ULP_CLASS_HID_2592f] = 431, - [BNXT_ULP_CLASS_HID_208fb] = 432, - [BNXT_ULP_CLASS_HID_231f3] = 433, - [BNXT_ULP_CLASS_HID_23e0b] = 434, - [BNXT_ULP_CLASS_HID_237cf] = 435, - [BNXT_ULP_CLASS_HID_24447] = 436, - [BNXT_ULP_CLASS_HID_21c2f] = 437, - [BNXT_ULP_CLASS_HID_228a7] = 438, - [BNXT_ULP_CLASS_HID_2226b] = 439, - [BNXT_ULP_CLASS_HID_22ee3] = 440, - [BNXT_ULP_CLASS_HID_25567] = 441, - [BNXT_ULP_CLASS_HID_20533] = 442, - [BNXT_ULP_CLASS_HID_25ba3] = 443, - [BNXT_ULP_CLASS_HID_20b0f] = 444, - [BNXT_ULP_CLASS_HID_23f83] = 445, - [BNXT_ULP_CLASS_HID_24c1b] = 446, - [BNXT_ULP_CLASS_HID_245df] = 447, - [BNXT_ULP_CLASS_HID_25257] = 448, - [BNXT_ULP_CLASS_HID_64017] = 449, - [BNXT_ULP_CLASS_HID_64caf] = 450, - [BNXT_ULP_CLASS_HID_64653] = 451, - [BNXT_ULP_CLASS_HID_652eb] = 452, - [BNXT_ULP_CLASS_HID_62ab3] = 453, - [BNXT_ULP_CLASS_HID_636cb] = 454, - [BNXT_ULP_CLASS_HID_6308f] = 455, - [BNXT_ULP_CLASS_HID_63d07] = 456, - [BNXT_ULP_CLASS_HID_606df] = 457, - [BNXT_ULP_CLASS_HID_61357] = 458, - [BNXT_ULP_CLASS_HID_60d1b] = 459, - [BNXT_ULP_CLASS_HID_61993] = 460, - [BNXT_ULP_CLASS_HID_64e27] = 461, - [BNXT_ULP_CLASS_HID_65abf] = 462, - [BNXT_ULP_CLASS_HID_65463] = 463, - [BNXT_ULP_CLASS_HID_603cf] = 464, - [BNXT_ULP_CLASS_HID_62cc7] = 465, - [BNXT_ULP_CLASS_HID_6395f] = 466, - [BNXT_ULP_CLASS_HID_63303] = 467, - [BNXT_ULP_CLASS_HID_63f9b] = 468, - [BNXT_ULP_CLASS_HID_61763] = 469, - [BNXT_ULP_CLASS_HID_623fb] = 470, - [BNXT_ULP_CLASS_HID_61dbf] = 471, - [BNXT_ULP_CLASS_HID_62a37] = 472, - [BNXT_ULP_CLASS_HID_650bb] = 473, - [BNXT_ULP_CLASS_HID_60007] = 474, - [BNXT_ULP_CLASS_HID_656f7] = 475, - [BNXT_ULP_CLASS_HID_60643] = 476, - [BNXT_ULP_CLASS_HID_63ad7] = 477, - [BNXT_ULP_CLASS_HID_6476f] = 478, - [BNXT_ULP_CLASS_HID_64113] = 479, - [BNXT_ULP_CLASS_HID_64dab] = 480, - [BNXT_ULP_CLASS_HID_35ac3] = 481, - [BNXT_ULP_CLASS_HID_30aaf] = 482, - [BNXT_ULP_CLASS_HID_30453] = 483, - [BNXT_ULP_CLASS_HID_310eb] = 484, - [BNXT_ULP_CLASS_HID_3457f] = 485, - [BNXT_ULP_CLASS_HID_351f7] = 486, - [BNXT_ULP_CLASS_HID_34bbb] = 487, - [BNXT_ULP_CLASS_HID_35833] = 488, - [BNXT_ULP_CLASS_HID_3218b] = 489, - [BNXT_ULP_CLASS_HID_32e03] = 490, - [BNXT_ULP_CLASS_HID_327c7] = 491, - [BNXT_ULP_CLASS_HID_3345f] = 492, - [BNXT_ULP_CLASS_HID_30c27] = 493, - [BNXT_ULP_CLASS_HID_318bf] = 494, - [BNXT_ULP_CLASS_HID_31263] = 495, - [BNXT_ULP_CLASS_HID_31efb] = 496, - [BNXT_ULP_CLASS_HID_347f3] = 497, - [BNXT_ULP_CLASS_HID_3540b] = 498, - [BNXT_ULP_CLASS_HID_34dcf] = 499, - [BNXT_ULP_CLASS_HID_35a47] = 500, - [BNXT_ULP_CLASS_HID_3322f] = 501, - [BNXT_ULP_CLASS_HID_33ea7] = 502, - [BNXT_ULP_CLASS_HID_3386b] = 503, - [BNXT_ULP_CLASS_HID_344e3] = 504, - [BNXT_ULP_CLASS_HID_30ebb] = 505, - [BNXT_ULP_CLASS_HID_31b33] = 506, - [BNXT_ULP_CLASS_HID_314f7] = 507, - [BNXT_ULP_CLASS_HID_3210f] = 508, - [BNXT_ULP_CLASS_HID_35583] = 509, - [BNXT_ULP_CLASS_HID_3056f] = 510, - [BNXT_ULP_CLASS_HID_35bdf] = 511, - [BNXT_ULP_CLASS_HID_30bab] = 512, - [BNXT_ULP_CLASS_HID_75617] = 513, - [BNXT_ULP_CLASS_HID_705e3] = 514, - [BNXT_ULP_CLASS_HID_75c53] = 515, - [BNXT_ULP_CLASS_HID_70c3f] = 516, - [BNXT_ULP_CLASS_HID_740b3] = 517, - [BNXT_ULP_CLASS_HID_74ccb] = 518, - [BNXT_ULP_CLASS_HID_7468f] = 519, - [BNXT_ULP_CLASS_HID_75307] = 520, - [BNXT_ULP_CLASS_HID_71cdf] = 521, - [BNXT_ULP_CLASS_HID_72957] = 522, - [BNXT_ULP_CLASS_HID_7231b] = 523, - [BNXT_ULP_CLASS_HID_72f93] = 524, - [BNXT_ULP_CLASS_HID_7077b] = 525, - [BNXT_ULP_CLASS_HID_713f3] = 526, - [BNXT_ULP_CLASS_HID_70db7] = 527, - [BNXT_ULP_CLASS_HID_719cf] = 528, - [BNXT_ULP_CLASS_HID_742c7] = 529, - [BNXT_ULP_CLASS_HID_74f5f] = 530, - [BNXT_ULP_CLASS_HID_74903] = 531, - [BNXT_ULP_CLASS_HID_7559b] = 532, - [BNXT_ULP_CLASS_HID_72d63] = 533, - [BNXT_ULP_CLASS_HID_739fb] = 534, - [BNXT_ULP_CLASS_HID_733bf] = 535, - [BNXT_ULP_CLASS_HID_74037] = 536, - [BNXT_ULP_CLASS_HID_7098f] = 537, - [BNXT_ULP_CLASS_HID_71607] = 538, - [BNXT_ULP_CLASS_HID_70fcb] = 539, - [BNXT_ULP_CLASS_HID_71c43] = 540, - [BNXT_ULP_CLASS_HID_750d7] = 541, - [BNXT_ULP_CLASS_HID_700a3] = 542, - [BNXT_ULP_CLASS_HID_75713] = 543, - [BNXT_ULP_CLASS_HID_706ff] = 544, - [BNXT_ULP_CLASS_HID_2cfc3] = 545, - [BNXT_ULP_CLASS_HID_2dc5b] = 546, - [BNXT_ULP_CLASS_HID_2d61f] = 547, - [BNXT_ULP_CLASS_HID_285eb] = 548, - [BNXT_ULP_CLASS_HID_2ba7f] = 549, - [BNXT_ULP_CLASS_HID_2c6f7] = 550, - [BNXT_ULP_CLASS_HID_2c0bb] = 551, - [BNXT_ULP_CLASS_HID_2cd33] = 552, - [BNXT_ULP_CLASS_HID_2968b] = 553, - [BNXT_ULP_CLASS_HID_2a303] = 554, - [BNXT_ULP_CLASS_HID_29cc7] = 555, - [BNXT_ULP_CLASS_HID_2a95f] = 556, - [BNXT_ULP_CLASS_HID_28127] = 557, - [BNXT_ULP_CLASS_HID_28dbf] = 558, - [BNXT_ULP_CLASS_HID_28763] = 559, - [BNXT_ULP_CLASS_HID_293fb] = 560, - [BNXT_ULP_CLASS_HID_2bcf3] = 561, - [BNXT_ULP_CLASS_HID_2c90b] = 562, - [BNXT_ULP_CLASS_HID_2c2cf] = 563, - [BNXT_ULP_CLASS_HID_2cf47] = 564, - [BNXT_ULP_CLASS_HID_2a72f] = 565, - [BNXT_ULP_CLASS_HID_2b3a7] = 566, - [BNXT_ULP_CLASS_HID_2ad6b] = 567, - [BNXT_ULP_CLASS_HID_2b9e3] = 568, - [BNXT_ULP_CLASS_HID_283bb] = 569, - [BNXT_ULP_CLASS_HID_29033] = 570, - [BNXT_ULP_CLASS_HID_289f7] = 571, - [BNXT_ULP_CLASS_HID_2960f] = 572, - [BNXT_ULP_CLASS_HID_2ca83] = 573, - [BNXT_ULP_CLASS_HID_2d71b] = 574, - [BNXT_ULP_CLASS_HID_2d0df] = 575, - [BNXT_ULP_CLASS_HID_280ab] = 576, - [BNXT_ULP_CLASS_HID_6cb17] = 577, - [BNXT_ULP_CLASS_HID_6d7af] = 578, - [BNXT_ULP_CLASS_HID_6d153] = 579, - [BNXT_ULP_CLASS_HID_6813f] = 580, - [BNXT_ULP_CLASS_HID_6b5b3] = 581, - [BNXT_ULP_CLASS_HID_6c1cb] = 582, - [BNXT_ULP_CLASS_HID_6bb8f] = 583, - [BNXT_ULP_CLASS_HID_6c807] = 584, - [BNXT_ULP_CLASS_HID_691df] = 585, - [BNXT_ULP_CLASS_HID_69e57] = 586, - [BNXT_ULP_CLASS_HID_6981b] = 587, - [BNXT_ULP_CLASS_HID_6a493] = 588, - [BNXT_ULP_CLASS_HID_6d927] = 589, - [BNXT_ULP_CLASS_HID_688f3] = 590, - [BNXT_ULP_CLASS_HID_682b7] = 591, - [BNXT_ULP_CLASS_HID_68ecf] = 592, - [BNXT_ULP_CLASS_HID_6b7c7] = 593, - [BNXT_ULP_CLASS_HID_6c45f] = 594, - [BNXT_ULP_CLASS_HID_6be03] = 595, - [BNXT_ULP_CLASS_HID_6ca9b] = 596, - [BNXT_ULP_CLASS_HID_6a263] = 597, - [BNXT_ULP_CLASS_HID_6aefb] = 598, - [BNXT_ULP_CLASS_HID_6a8bf] = 599, - [BNXT_ULP_CLASS_HID_6b537] = 600, - [BNXT_ULP_CLASS_HID_6dbbb] = 601, - [BNXT_ULP_CLASS_HID_68b07] = 602, - [BNXT_ULP_CLASS_HID_684cb] = 603, - [BNXT_ULP_CLASS_HID_69143] = 604, - [BNXT_ULP_CLASS_HID_6c5d7] = 605, - [BNXT_ULP_CLASS_HID_6d26f] = 606, - [BNXT_ULP_CLASS_HID_6cc13] = 607, - [BNXT_ULP_CLASS_HID_6d8ab] = 608, - [BNXT_ULP_CLASS_HID_38917] = 609, - [BNXT_ULP_CLASS_HID_395af] = 610, - [BNXT_ULP_CLASS_HID_38f53] = 611, - [BNXT_ULP_CLASS_HID_39beb] = 612, - [BNXT_ULP_CLASS_HID_3d07f] = 613, - [BNXT_ULP_CLASS_HID_3dcf7] = 614, - [BNXT_ULP_CLASS_HID_3d6bb] = 615, - [BNXT_ULP_CLASS_HID_38607] = 616, - [BNXT_ULP_CLASS_HID_3ac8b] = 617, - [BNXT_ULP_CLASS_HID_3b903] = 618, - [BNXT_ULP_CLASS_HID_3b2c7] = 619, - [BNXT_ULP_CLASS_HID_3bf5f] = 620, - [BNXT_ULP_CLASS_HID_39727] = 621, - [BNXT_ULP_CLASS_HID_3a3bf] = 622, - [BNXT_ULP_CLASS_HID_39d63] = 623, - [BNXT_ULP_CLASS_HID_3a9fb] = 624, - [BNXT_ULP_CLASS_HID_3d2f3] = 625, - [BNXT_ULP_CLASS_HID_3825f] = 626, - [BNXT_ULP_CLASS_HID_3d8cf] = 627, - [BNXT_ULP_CLASS_HID_3889b] = 628, - [BNXT_ULP_CLASS_HID_3bd2f] = 629, - [BNXT_ULP_CLASS_HID_3c9a7] = 630, - [BNXT_ULP_CLASS_HID_3c36b] = 631, - [BNXT_ULP_CLASS_HID_3cfe3] = 632, - [BNXT_ULP_CLASS_HID_399bb] = 633, - [BNXT_ULP_CLASS_HID_3a633] = 634, - [BNXT_ULP_CLASS_HID_39ff7] = 635, - [BNXT_ULP_CLASS_HID_3ac0f] = 636, - [BNXT_ULP_CLASS_HID_383d7] = 637, - [BNXT_ULP_CLASS_HID_3906f] = 638, - [BNXT_ULP_CLASS_HID_38a13] = 639, - [BNXT_ULP_CLASS_HID_396ab] = 640, - [BNXT_ULP_CLASS_HID_7846b] = 641, - [BNXT_ULP_CLASS_HID_790e3] = 642, - [BNXT_ULP_CLASS_HID_78aa7] = 643, - [BNXT_ULP_CLASS_HID_7973f] = 644, - [BNXT_ULP_CLASS_HID_7cbb3] = 645, - [BNXT_ULP_CLASS_HID_7d7cb] = 646, - [BNXT_ULP_CLASS_HID_7d18f] = 647, - [BNXT_ULP_CLASS_HID_7815b] = 648, - [BNXT_ULP_CLASS_HID_7a7df] = 649, - [BNXT_ULP_CLASS_HID_7b457] = 650, - [BNXT_ULP_CLASS_HID_7ae1b] = 651, - [BNXT_ULP_CLASS_HID_7ba93] = 652, - [BNXT_ULP_CLASS_HID_7927b] = 653, - [BNXT_ULP_CLASS_HID_79ef3] = 654, - [BNXT_ULP_CLASS_HID_798b7] = 655, - [BNXT_ULP_CLASS_HID_7a4cf] = 656, - [BNXT_ULP_CLASS_HID_7cdc7] = 657, - [BNXT_ULP_CLASS_HID_7da5f] = 658, - [BNXT_ULP_CLASS_HID_7d403] = 659, - [BNXT_ULP_CLASS_HID_783ef] = 660, - [BNXT_ULP_CLASS_HID_7b863] = 661, - [BNXT_ULP_CLASS_HID_7c4fb] = 662, - [BNXT_ULP_CLASS_HID_7bebf] = 663, - [BNXT_ULP_CLASS_HID_7cb37] = 664, - [BNXT_ULP_CLASS_HID_7948f] = 665, - [BNXT_ULP_CLASS_HID_7a107] = 666, - [BNXT_ULP_CLASS_HID_79acb] = 667, - [BNXT_ULP_CLASS_HID_7a743] = 668, - [BNXT_ULP_CLASS_HID_7dbd7] = 669, - [BNXT_ULP_CLASS_HID_78ba3] = 670, - [BNXT_ULP_CLASS_HID_78567] = 671, - [BNXT_ULP_CLASS_HID_791ff] = 672, - [BNXT_ULP_CLASS_HID_a3db] = 673, - [BNXT_ULP_CLASS_HID_b043] = 674, - [BNXT_ULP_CLASS_HID_aa07] = 675, - [BNXT_ULP_CLASS_HID_b68f] = 676, - [BNXT_ULP_CLASS_HID_8e67] = 677, - [BNXT_ULP_CLASS_HID_9aef] = 678, - [BNXT_ULP_CLASS_HID_94a3] = 679, - [BNXT_ULP_CLASS_HID_a12b] = 680, - [BNXT_ULP_CLASS_HID_c7af] = 681, - [BNXT_ULP_CLASS_HID_d3d7] = 682, - [BNXT_ULP_CLASS_HID_cdeb] = 683, - [BNXT_ULP_CLASS_HID_da13] = 684, - [BNXT_ULP_CLASS_HID_b1cb] = 685, - [BNXT_ULP_CLASS_HID_be73] = 686, - [BNXT_ULP_CLASS_HID_b837] = 687, - [BNXT_ULP_CLASS_HID_c4bf] = 688, - [BNXT_ULP_CLASS_HID_49f0f] = 689, - [BNXT_ULP_CLASS_HID_4abb7] = 690, - [BNXT_ULP_CLASS_HID_4a54b] = 691, - [BNXT_ULP_CLASS_HID_4b1f3] = 692, - [BNXT_ULP_CLASS_HID_489ab] = 693, - [BNXT_ULP_CLASS_HID_495d3] = 694, - [BNXT_ULP_CLASS_HID_48f97] = 695, - [BNXT_ULP_CLASS_HID_49c1f] = 696, - [BNXT_ULP_CLASS_HID_4c293] = 697, - [BNXT_ULP_CLASS_HID_4cf1b] = 698, - [BNXT_ULP_CLASS_HID_4c8df] = 699, - [BNXT_ULP_CLASS_HID_4d547] = 700, - [BNXT_ULP_CLASS_HID_4ad3f] = 701, - [BNXT_ULP_CLASS_HID_4b9a7] = 702, - [BNXT_ULP_CLASS_HID_4b37b] = 703, - [BNXT_ULP_CLASS_HID_4bfe3] = 704, - [BNXT_ULP_CLASS_HID_1b9db] = 705, - [BNXT_ULP_CLASS_HID_1c643] = 706, - [BNXT_ULP_CLASS_HID_1c007] = 707, - [BNXT_ULP_CLASS_HID_1cc8f] = 708, - [BNXT_ULP_CLASS_HID_1a467] = 709, - [BNXT_ULP_CLASS_HID_1b0ef] = 710, - [BNXT_ULP_CLASS_HID_1aaa3] = 711, - [BNXT_ULP_CLASS_HID_1b72b] = 712, - [BNXT_ULP_CLASS_HID_18093] = 713, - [BNXT_ULP_CLASS_HID_18d1b] = 714, - [BNXT_ULP_CLASS_HID_186df] = 715, - [BNXT_ULP_CLASS_HID_19347] = 716, - [BNXT_ULP_CLASS_HID_1c7cb] = 717, - [BNXT_ULP_CLASS_HID_1d473] = 718, - [BNXT_ULP_CLASS_HID_1ce37] = 719, - [BNXT_ULP_CLASS_HID_1dabf] = 720, - [BNXT_ULP_CLASS_HID_5b50f] = 721, - [BNXT_ULP_CLASS_HID_5c1b7] = 722, - [BNXT_ULP_CLASS_HID_5bb4b] = 723, - [BNXT_ULP_CLASS_HID_5c7f3] = 724, - [BNXT_ULP_CLASS_HID_59fab] = 725, - [BNXT_ULP_CLASS_HID_5abd3] = 726, - [BNXT_ULP_CLASS_HID_5a597] = 727, - [BNXT_ULP_CLASS_HID_5b21f] = 728, - [BNXT_ULP_CLASS_HID_5d893] = 729, - [BNXT_ULP_CLASS_HID_5884f] = 730, - [BNXT_ULP_CLASS_HID_58203] = 731, - [BNXT_ULP_CLASS_HID_58e8b] = 732, - [BNXT_ULP_CLASS_HID_5c33f] = 733, - [BNXT_ULP_CLASS_HID_5cfa7] = 734, - [BNXT_ULP_CLASS_HID_5c97b] = 735, - [BNXT_ULP_CLASS_HID_5d5e3] = 736, - [BNXT_ULP_CLASS_HID_e95b] = 737, - [BNXT_ULP_CLASS_HID_f5c3] = 738, - [BNXT_ULP_CLASS_HID_ef87] = 739, - [BNXT_ULP_CLASS_HID_fc0f] = 740, - [BNXT_ULP_CLASS_HID_d3e7] = 741, - [BNXT_ULP_CLASS_HID_e06f] = 742, - [BNXT_ULP_CLASS_HID_da23] = 743, - [BNXT_ULP_CLASS_HID_e6ab] = 744, - [BNXT_ULP_CLASS_HID_cd2f] = 745, - [BNXT_ULP_CLASS_HID_d957] = 746, - [BNXT_ULP_CLASS_HID_d36b] = 747, - [BNXT_ULP_CLASS_HID_c2c7] = 748, - [BNXT_ULP_CLASS_HID_f74b] = 749, - [BNXT_ULP_CLASS_HID_c3f3] = 750, - [BNXT_ULP_CLASS_HID_fdb7] = 751, - [BNXT_ULP_CLASS_HID_ca3f] = 752, - [BNXT_ULP_CLASS_HID_4e48f] = 753, - [BNXT_ULP_CLASS_HID_4f137] = 754, - [BNXT_ULP_CLASS_HID_4eacb] = 755, - [BNXT_ULP_CLASS_HID_4f773] = 756, - [BNXT_ULP_CLASS_HID_4cf2b] = 757, - [BNXT_ULP_CLASS_HID_4db53] = 758, - [BNXT_ULP_CLASS_HID_4d517] = 759, - [BNXT_ULP_CLASS_HID_4e19f] = 760, - [BNXT_ULP_CLASS_HID_4c813] = 761, - [BNXT_ULP_CLASS_HID_4d49b] = 762, - [BNXT_ULP_CLASS_HID_4ce5f] = 763, - [BNXT_ULP_CLASS_HID_4dac7] = 764, - [BNXT_ULP_CLASS_HID_4f2bf] = 765, - [BNXT_ULP_CLASS_HID_4ff27] = 766, - [BNXT_ULP_CLASS_HID_4f8fb] = 767, - [BNXT_ULP_CLASS_HID_4c563] = 768, - [BNXT_ULP_CLASS_HID_1ff5b] = 769, - [BNXT_ULP_CLASS_HID_1cbc3] = 770, - [BNXT_ULP_CLASS_HID_1c587] = 771, - [BNXT_ULP_CLASS_HID_1d20f] = 772, - [BNXT_ULP_CLASS_HID_1e9e7] = 773, - [BNXT_ULP_CLASS_HID_1f66f] = 774, - [BNXT_ULP_CLASS_HID_1f023] = 775, - [BNXT_ULP_CLASS_HID_1fcab] = 776, - [BNXT_ULP_CLASS_HID_1c613] = 777, - [BNXT_ULP_CLASS_HID_1d29b] = 778, - [BNXT_ULP_CLASS_HID_1cc5f] = 779, - [BNXT_ULP_CLASS_HID_1d8c7] = 780, - [BNXT_ULP_CLASS_HID_1cd4b] = 781, - [BNXT_ULP_CLASS_HID_1d9f3] = 782, - [BNXT_ULP_CLASS_HID_1d3b7] = 783, - [BNXT_ULP_CLASS_HID_1c363] = 784, - [BNXT_ULP_CLASS_HID_5fa8f] = 785, - [BNXT_ULP_CLASS_HID_5c737] = 786, - [BNXT_ULP_CLASS_HID_5c0cb] = 787, - [BNXT_ULP_CLASS_HID_5cd73] = 788, - [BNXT_ULP_CLASS_HID_5e52b] = 789, - [BNXT_ULP_CLASS_HID_5f153] = 790, - [BNXT_ULP_CLASS_HID_5eb17] = 791, - [BNXT_ULP_CLASS_HID_5f79f] = 792, - [BNXT_ULP_CLASS_HID_5c147] = 793, - [BNXT_ULP_CLASS_HID_5cdcf] = 794, - [BNXT_ULP_CLASS_HID_5c783] = 795, - [BNXT_ULP_CLASS_HID_5d40b] = 796, - [BNXT_ULP_CLASS_HID_5c8bf] = 797, - [BNXT_ULP_CLASS_HID_5d527] = 798, - [BNXT_ULP_CLASS_HID_5cefb] = 799, - [BNXT_ULP_CLASS_HID_5db63] = 800, - [BNXT_ULP_CLASS_HID_a69b] = 801, - [BNXT_ULP_CLASS_HID_b303] = 802, - [BNXT_ULP_CLASS_HID_acc7] = 803, - [BNXT_ULP_CLASS_HID_b94f] = 804, - [BNXT_ULP_CLASS_HID_b127] = 805, - [BNXT_ULP_CLASS_HID_bdaf] = 806, - [BNXT_ULP_CLASS_HID_b763] = 807, - [BNXT_ULP_CLASS_HID_a3eb] = 808, - [BNXT_ULP_CLASS_HID_ea6f] = 809, - [BNXT_ULP_CLASS_HID_f697] = 810, - [BNXT_ULP_CLASS_HID_f0ab] = 811, - [BNXT_ULP_CLASS_HID_a007] = 812, - [BNXT_ULP_CLASS_HID_b48b] = 813, - [BNXT_ULP_CLASS_HID_e133] = 814, - [BNXT_ULP_CLASS_HID_baf7] = 815, - [BNXT_ULP_CLASS_HID_e77f] = 816, - [BNXT_ULP_CLASS_HID_4a1cf] = 817, - [BNXT_ULP_CLASS_HID_4ae77] = 818, - [BNXT_ULP_CLASS_HID_4a80b] = 819, - [BNXT_ULP_CLASS_HID_4b4b3] = 820, - [BNXT_ULP_CLASS_HID_4ac6b] = 821, - [BNXT_ULP_CLASS_HID_4b893] = 822, - [BNXT_ULP_CLASS_HID_4b257] = 823, - [BNXT_ULP_CLASS_HID_4bedf] = 824, - [BNXT_ULP_CLASS_HID_4e553] = 825, - [BNXT_ULP_CLASS_HID_4f1db] = 826, - [BNXT_ULP_CLASS_HID_4eb9f] = 827, - [BNXT_ULP_CLASS_HID_4f807] = 828, - [BNXT_ULP_CLASS_HID_4afff] = 829, - [BNXT_ULP_CLASS_HID_4bc67] = 830, - [BNXT_ULP_CLASS_HID_4b63b] = 831, - [BNXT_ULP_CLASS_HID_4e2a3] = 832, - [BNXT_ULP_CLASS_HID_1bc9b] = 833, - [BNXT_ULP_CLASS_HID_1e903] = 834, - [BNXT_ULP_CLASS_HID_1e2c7] = 835, - [BNXT_ULP_CLASS_HID_1ef4f] = 836, - [BNXT_ULP_CLASS_HID_1a727] = 837, - [BNXT_ULP_CLASS_HID_1b3af] = 838, - [BNXT_ULP_CLASS_HID_1ad63] = 839, - [BNXT_ULP_CLASS_HID_1b9eb] = 840, - [BNXT_ULP_CLASS_HID_1a353] = 841, - [BNXT_ULP_CLASS_HID_1afdb] = 842, - [BNXT_ULP_CLASS_HID_1a99f] = 843, - [BNXT_ULP_CLASS_HID_1b607] = 844, - [BNXT_ULP_CLASS_HID_1ea8b] = 845, - [BNXT_ULP_CLASS_HID_1f733] = 846, - [BNXT_ULP_CLASS_HID_1f0f7] = 847, - [BNXT_ULP_CLASS_HID_1a0a3] = 848, - [BNXT_ULP_CLASS_HID_5b7cf] = 849, - [BNXT_ULP_CLASS_HID_5e477] = 850, - [BNXT_ULP_CLASS_HID_5be0b] = 851, - [BNXT_ULP_CLASS_HID_5eab3] = 852, - [BNXT_ULP_CLASS_HID_5a26b] = 853, - [BNXT_ULP_CLASS_HID_5ae93] = 854, - [BNXT_ULP_CLASS_HID_5a857] = 855, - [BNXT_ULP_CLASS_HID_5b4df] = 856, - [BNXT_ULP_CLASS_HID_5fb53] = 857, - [BNXT_ULP_CLASS_HID_5ab0f] = 858, - [BNXT_ULP_CLASS_HID_5a4c3] = 859, - [BNXT_ULP_CLASS_HID_5b14b] = 860, - [BNXT_ULP_CLASS_HID_5e5ff] = 861, - [BNXT_ULP_CLASS_HID_5f267] = 862, - [BNXT_ULP_CLASS_HID_5ec3b] = 863, - [BNXT_ULP_CLASS_HID_5f8a3] = 864, - [BNXT_ULP_CLASS_HID_ec1b] = 865, - [BNXT_ULP_CLASS_HID_f883] = 866, - [BNXT_ULP_CLASS_HID_f247] = 867, - [BNXT_ULP_CLASS_HID_fecf] = 868, - [BNXT_ULP_CLASS_HID_f6a7] = 869, - [BNXT_ULP_CLASS_HID_e32f] = 870, - [BNXT_ULP_CLASS_HID_fce3] = 871, - [BNXT_ULP_CLASS_HID_e96b] = 872, - [BNXT_ULP_CLASS_HID_efef] = 873, - [BNXT_ULP_CLASS_HID_fc17] = 874, - [BNXT_ULP_CLASS_HID_f62b] = 875, - [BNXT_ULP_CLASS_HID_e587] = 876, - [BNXT_ULP_CLASS_HID_fa0b] = 877, - [BNXT_ULP_CLASS_HID_e6b3] = 878, - [BNXT_ULP_CLASS_HID_e077] = 879, - [BNXT_ULP_CLASS_HID_ecff] = 880, - [BNXT_ULP_CLASS_HID_4e74f] = 881, - [BNXT_ULP_CLASS_HID_4f3f7] = 882, - [BNXT_ULP_CLASS_HID_4ed8b] = 883, - [BNXT_ULP_CLASS_HID_4fa33] = 884, - [BNXT_ULP_CLASS_HID_4f1eb] = 885, - [BNXT_ULP_CLASS_HID_4fe13] = 886, - [BNXT_ULP_CLASS_HID_4f7d7] = 887, - [BNXT_ULP_CLASS_HID_4e45f] = 888, - [BNXT_ULP_CLASS_HID_4ead3] = 889, - [BNXT_ULP_CLASS_HID_4f75b] = 890, - [BNXT_ULP_CLASS_HID_4f11f] = 891, - [BNXT_ULP_CLASS_HID_4e0cb] = 892, - [BNXT_ULP_CLASS_HID_4f57f] = 893, - [BNXT_ULP_CLASS_HID_4e1e7] = 894, - [BNXT_ULP_CLASS_HID_4fbbb] = 895, - [BNXT_ULP_CLASS_HID_4e823] = 896, - [BNXT_ULP_CLASS_HID_1e21b] = 897, - [BNXT_ULP_CLASS_HID_1ee83] = 898, - [BNXT_ULP_CLASS_HID_1e847] = 899, - [BNXT_ULP_CLASS_HID_1f4cf] = 900, - [BNXT_ULP_CLASS_HID_1eca7] = 901, - [BNXT_ULP_CLASS_HID_1f92f] = 902, - [BNXT_ULP_CLASS_HID_1f2e3] = 903, - [BNXT_ULP_CLASS_HID_1ff6b] = 904, - [BNXT_ULP_CLASS_HID_1e8d3] = 905, - [BNXT_ULP_CLASS_HID_1f55b] = 906, - [BNXT_ULP_CLASS_HID_1ef1f] = 907, - [BNXT_ULP_CLASS_HID_1fb87] = 908, - [BNXT_ULP_CLASS_HID_1f00b] = 909, - [BNXT_ULP_CLASS_HID_1fcb3] = 910, - [BNXT_ULP_CLASS_HID_1f677] = 911, - [BNXT_ULP_CLASS_HID_1e623] = 912, - [BNXT_ULP_CLASS_HID_5fd4f] = 913, - [BNXT_ULP_CLASS_HID_5e9f7] = 914, - [BNXT_ULP_CLASS_HID_5e38b] = 915, - [BNXT_ULP_CLASS_HID_5f033] = 916, - [BNXT_ULP_CLASS_HID_5e7eb] = 917, - [BNXT_ULP_CLASS_HID_5f413] = 918, - [BNXT_ULP_CLASS_HID_5edd7] = 919, - [BNXT_ULP_CLASS_HID_5fa5f] = 920, - [BNXT_ULP_CLASS_HID_5e407] = 921, - [BNXT_ULP_CLASS_HID_5f08f] = 922, - [BNXT_ULP_CLASS_HID_5ea43] = 923, - [BNXT_ULP_CLASS_HID_5f6cb] = 924, - [BNXT_ULP_CLASS_HID_5eb7f] = 925, - [BNXT_ULP_CLASS_HID_5f7e7] = 926, - [BNXT_ULP_CLASS_HID_5f1bb] = 927, - [BNXT_ULP_CLASS_HID_5e117] = 928, - [BNXT_ULP_CLASS_HID_244a3] = 929, - [BNXT_ULP_CLASS_HID_2513b] = 930, - [BNXT_ULP_CLASS_HID_24b7f] = 931, - [BNXT_ULP_CLASS_HID_257f7] = 932, - [BNXT_ULP_CLASS_HID_22f1f] = 933, - [BNXT_ULP_CLASS_HID_23b97] = 934, - [BNXT_ULP_CLASS_HID_235db] = 935, - [BNXT_ULP_CLASS_HID_24253] = 936, - [BNXT_ULP_CLASS_HID_20beb] = 937, - [BNXT_ULP_CLASS_HID_21863] = 938, - [BNXT_ULP_CLASS_HID_211a7] = 939, - [BNXT_ULP_CLASS_HID_21e3f] = 940, - [BNXT_ULP_CLASS_HID_252b3] = 941, - [BNXT_ULP_CLASS_HID_202df] = 942, - [BNXT_ULP_CLASS_HID_2594f] = 943, - [BNXT_ULP_CLASS_HID_2089b] = 944, - [BNXT_ULP_CLASS_HID_23193] = 945, - [BNXT_ULP_CLASS_HID_23e6b] = 946, - [BNXT_ULP_CLASS_HID_237af] = 947, - [BNXT_ULP_CLASS_HID_24427] = 948, - [BNXT_ULP_CLASS_HID_21c4f] = 949, - [BNXT_ULP_CLASS_HID_228c7] = 950, - [BNXT_ULP_CLASS_HID_2220b] = 951, - [BNXT_ULP_CLASS_HID_22e83] = 952, - [BNXT_ULP_CLASS_HID_25507] = 953, - [BNXT_ULP_CLASS_HID_20553] = 954, - [BNXT_ULP_CLASS_HID_25bc3] = 955, - [BNXT_ULP_CLASS_HID_20b6f] = 956, - [BNXT_ULP_CLASS_HID_23fe3] = 957, - [BNXT_ULP_CLASS_HID_24c7b] = 958, - [BNXT_ULP_CLASS_HID_245bf] = 959, - [BNXT_ULP_CLASS_HID_25237] = 960, - [BNXT_ULP_CLASS_HID_64077] = 961, - [BNXT_ULP_CLASS_HID_64ccf] = 962, - [BNXT_ULP_CLASS_HID_64633] = 963, - [BNXT_ULP_CLASS_HID_6528b] = 964, - [BNXT_ULP_CLASS_HID_62ad3] = 965, - [BNXT_ULP_CLASS_HID_636ab] = 966, - [BNXT_ULP_CLASS_HID_630ef] = 967, - [BNXT_ULP_CLASS_HID_63d67] = 968, - [BNXT_ULP_CLASS_HID_606bf] = 969, - [BNXT_ULP_CLASS_HID_61337] = 970, - [BNXT_ULP_CLASS_HID_60d7b] = 971, - [BNXT_ULP_CLASS_HID_619f3] = 972, - [BNXT_ULP_CLASS_HID_64e47] = 973, - [BNXT_ULP_CLASS_HID_65adf] = 974, - [BNXT_ULP_CLASS_HID_65403] = 975, - [BNXT_ULP_CLASS_HID_603af] = 976, - [BNXT_ULP_CLASS_HID_62ca7] = 977, - [BNXT_ULP_CLASS_HID_6393f] = 978, - [BNXT_ULP_CLASS_HID_63363] = 979, - [BNXT_ULP_CLASS_HID_63ffb] = 980, - [BNXT_ULP_CLASS_HID_61703] = 981, - [BNXT_ULP_CLASS_HID_6239b] = 982, - [BNXT_ULP_CLASS_HID_61ddf] = 983, - [BNXT_ULP_CLASS_HID_62a57] = 984, - [BNXT_ULP_CLASS_HID_650db] = 985, - [BNXT_ULP_CLASS_HID_60067] = 986, - [BNXT_ULP_CLASS_HID_65697] = 987, - [BNXT_ULP_CLASS_HID_60623] = 988, - [BNXT_ULP_CLASS_HID_63ab7] = 989, - [BNXT_ULP_CLASS_HID_6470f] = 990, - [BNXT_ULP_CLASS_HID_64173] = 991, - [BNXT_ULP_CLASS_HID_64dcb] = 992, - [BNXT_ULP_CLASS_HID_35aa3] = 993, - [BNXT_ULP_CLASS_HID_30acf] = 994, - [BNXT_ULP_CLASS_HID_30433] = 995, - [BNXT_ULP_CLASS_HID_3108b] = 996, - [BNXT_ULP_CLASS_HID_3451f] = 997, - [BNXT_ULP_CLASS_HID_35197] = 998, - [BNXT_ULP_CLASS_HID_34bdb] = 999, - [BNXT_ULP_CLASS_HID_35853] = 1000, - [BNXT_ULP_CLASS_HID_321eb] = 1001, - [BNXT_ULP_CLASS_HID_32e63] = 1002, - [BNXT_ULP_CLASS_HID_327a7] = 1003, - [BNXT_ULP_CLASS_HID_3343f] = 1004, - [BNXT_ULP_CLASS_HID_30c47] = 1005, - [BNXT_ULP_CLASS_HID_318df] = 1006, - [BNXT_ULP_CLASS_HID_31203] = 1007, - [BNXT_ULP_CLASS_HID_31e9b] = 1008, - [BNXT_ULP_CLASS_HID_34793] = 1009, - [BNXT_ULP_CLASS_HID_3546b] = 1010, - [BNXT_ULP_CLASS_HID_34daf] = 1011, - [BNXT_ULP_CLASS_HID_35a27] = 1012, - [BNXT_ULP_CLASS_HID_3324f] = 1013, - [BNXT_ULP_CLASS_HID_33ec7] = 1014, - [BNXT_ULP_CLASS_HID_3380b] = 1015, - [BNXT_ULP_CLASS_HID_34483] = 1016, - [BNXT_ULP_CLASS_HID_30edb] = 1017, - [BNXT_ULP_CLASS_HID_31b53] = 1018, - [BNXT_ULP_CLASS_HID_31497] = 1019, - [BNXT_ULP_CLASS_HID_3216f] = 1020, - [BNXT_ULP_CLASS_HID_355e3] = 1021, - [BNXT_ULP_CLASS_HID_3050f] = 1022, - [BNXT_ULP_CLASS_HID_35bbf] = 1023, - [BNXT_ULP_CLASS_HID_30bcb] = 1024, - [BNXT_ULP_CLASS_HID_75677] = 1025, - [BNXT_ULP_CLASS_HID_70583] = 1026, - [BNXT_ULP_CLASS_HID_75c33] = 1027, - [BNXT_ULP_CLASS_HID_70c5f] = 1028, - [BNXT_ULP_CLASS_HID_740d3] = 1029, - [BNXT_ULP_CLASS_HID_74cab] = 1030, - [BNXT_ULP_CLASS_HID_746ef] = 1031, - [BNXT_ULP_CLASS_HID_75367] = 1032, - [BNXT_ULP_CLASS_HID_71cbf] = 1033, - [BNXT_ULP_CLASS_HID_72937] = 1034, - [BNXT_ULP_CLASS_HID_7237b] = 1035, - [BNXT_ULP_CLASS_HID_72ff3] = 1036, - [BNXT_ULP_CLASS_HID_7071b] = 1037, - [BNXT_ULP_CLASS_HID_71393] = 1038, - [BNXT_ULP_CLASS_HID_70dd7] = 1039, - [BNXT_ULP_CLASS_HID_719af] = 1040, - [BNXT_ULP_CLASS_HID_742a7] = 1041, - [BNXT_ULP_CLASS_HID_74f3f] = 1042, - [BNXT_ULP_CLASS_HID_74963] = 1043, - [BNXT_ULP_CLASS_HID_755fb] = 1044, - [BNXT_ULP_CLASS_HID_72d03] = 1045, - [BNXT_ULP_CLASS_HID_7399b] = 1046, - [BNXT_ULP_CLASS_HID_733df] = 1047, - [BNXT_ULP_CLASS_HID_74057] = 1048, - [BNXT_ULP_CLASS_HID_709ef] = 1049, - [BNXT_ULP_CLASS_HID_71667] = 1050, - [BNXT_ULP_CLASS_HID_70fab] = 1051, - [BNXT_ULP_CLASS_HID_71c23] = 1052, - [BNXT_ULP_CLASS_HID_750b7] = 1053, - [BNXT_ULP_CLASS_HID_700c3] = 1054, - [BNXT_ULP_CLASS_HID_75773] = 1055, - [BNXT_ULP_CLASS_HID_7069f] = 1056, - [BNXT_ULP_CLASS_HID_2cfa3] = 1057, - [BNXT_ULP_CLASS_HID_2dc3b] = 1058, - [BNXT_ULP_CLASS_HID_2d67f] = 1059, - [BNXT_ULP_CLASS_HID_2858b] = 1060, - [BNXT_ULP_CLASS_HID_2ba1f] = 1061, - [BNXT_ULP_CLASS_HID_2c697] = 1062, - [BNXT_ULP_CLASS_HID_2c0db] = 1063, - [BNXT_ULP_CLASS_HID_2cd53] = 1064, - [BNXT_ULP_CLASS_HID_296eb] = 1065, - [BNXT_ULP_CLASS_HID_2a363] = 1066, - [BNXT_ULP_CLASS_HID_29ca7] = 1067, - [BNXT_ULP_CLASS_HID_2a93f] = 1068, - [BNXT_ULP_CLASS_HID_28147] = 1069, - [BNXT_ULP_CLASS_HID_28ddf] = 1070, - [BNXT_ULP_CLASS_HID_28703] = 1071, - [BNXT_ULP_CLASS_HID_2939b] = 1072, - [BNXT_ULP_CLASS_HID_2bc93] = 1073, - [BNXT_ULP_CLASS_HID_2c96b] = 1074, - [BNXT_ULP_CLASS_HID_2c2af] = 1075, - [BNXT_ULP_CLASS_HID_2cf27] = 1076, - [BNXT_ULP_CLASS_HID_2a74f] = 1077, - [BNXT_ULP_CLASS_HID_2b3c7] = 1078, - [BNXT_ULP_CLASS_HID_2ad0b] = 1079, - [BNXT_ULP_CLASS_HID_2b983] = 1080, - [BNXT_ULP_CLASS_HID_283db] = 1081, - [BNXT_ULP_CLASS_HID_29053] = 1082, - [BNXT_ULP_CLASS_HID_28997] = 1083, - [BNXT_ULP_CLASS_HID_2966f] = 1084, - [BNXT_ULP_CLASS_HID_2cae3] = 1085, - [BNXT_ULP_CLASS_HID_2d77b] = 1086, - [BNXT_ULP_CLASS_HID_2d0bf] = 1087, - [BNXT_ULP_CLASS_HID_280cb] = 1088, - [BNXT_ULP_CLASS_HID_6cb77] = 1089, - [BNXT_ULP_CLASS_HID_6d7cf] = 1090, - [BNXT_ULP_CLASS_HID_6d133] = 1091, - [BNXT_ULP_CLASS_HID_6815f] = 1092, - [BNXT_ULP_CLASS_HID_6b5d3] = 1093, - [BNXT_ULP_CLASS_HID_6c1ab] = 1094, - [BNXT_ULP_CLASS_HID_6bbef] = 1095, - [BNXT_ULP_CLASS_HID_6c867] = 1096, - [BNXT_ULP_CLASS_HID_691bf] = 1097, - [BNXT_ULP_CLASS_HID_69e37] = 1098, - [BNXT_ULP_CLASS_HID_6987b] = 1099, - [BNXT_ULP_CLASS_HID_6a4f3] = 1100, - [BNXT_ULP_CLASS_HID_6d947] = 1101, - [BNXT_ULP_CLASS_HID_68893] = 1102, - [BNXT_ULP_CLASS_HID_682d7] = 1103, - [BNXT_ULP_CLASS_HID_68eaf] = 1104, - [BNXT_ULP_CLASS_HID_6b7a7] = 1105, - [BNXT_ULP_CLASS_HID_6c43f] = 1106, - [BNXT_ULP_CLASS_HID_6be63] = 1107, - [BNXT_ULP_CLASS_HID_6cafb] = 1108, - [BNXT_ULP_CLASS_HID_6a203] = 1109, - [BNXT_ULP_CLASS_HID_6ae9b] = 1110, - [BNXT_ULP_CLASS_HID_6a8df] = 1111, - [BNXT_ULP_CLASS_HID_6b557] = 1112, - [BNXT_ULP_CLASS_HID_6dbdb] = 1113, - [BNXT_ULP_CLASS_HID_68b67] = 1114, - [BNXT_ULP_CLASS_HID_684ab] = 1115, - [BNXT_ULP_CLASS_HID_69123] = 1116, - [BNXT_ULP_CLASS_HID_6c5b7] = 1117, - [BNXT_ULP_CLASS_HID_6d20f] = 1118, - [BNXT_ULP_CLASS_HID_6cc73] = 1119, - [BNXT_ULP_CLASS_HID_6d8cb] = 1120, - [BNXT_ULP_CLASS_HID_38977] = 1121, - [BNXT_ULP_CLASS_HID_395cf] = 1122, - [BNXT_ULP_CLASS_HID_38f33] = 1123, - [BNXT_ULP_CLASS_HID_39b8b] = 1124, - [BNXT_ULP_CLASS_HID_3d01f] = 1125, - [BNXT_ULP_CLASS_HID_3dc97] = 1126, - [BNXT_ULP_CLASS_HID_3d6db] = 1127, - [BNXT_ULP_CLASS_HID_38667] = 1128, - [BNXT_ULP_CLASS_HID_3aceb] = 1129, - [BNXT_ULP_CLASS_HID_3b963] = 1130, - [BNXT_ULP_CLASS_HID_3b2a7] = 1131, - [BNXT_ULP_CLASS_HID_3bf3f] = 1132, - [BNXT_ULP_CLASS_HID_39747] = 1133, - [BNXT_ULP_CLASS_HID_3a3df] = 1134, - [BNXT_ULP_CLASS_HID_39d03] = 1135, - [BNXT_ULP_CLASS_HID_3a99b] = 1136, - [BNXT_ULP_CLASS_HID_3d293] = 1137, - [BNXT_ULP_CLASS_HID_3823f] = 1138, - [BNXT_ULP_CLASS_HID_3d8af] = 1139, - [BNXT_ULP_CLASS_HID_388fb] = 1140, - [BNXT_ULP_CLASS_HID_3bd4f] = 1141, - [BNXT_ULP_CLASS_HID_3c9c7] = 1142, - [BNXT_ULP_CLASS_HID_3c30b] = 1143, - [BNXT_ULP_CLASS_HID_3cf83] = 1144, - [BNXT_ULP_CLASS_HID_399db] = 1145, - [BNXT_ULP_CLASS_HID_3a653] = 1146, - [BNXT_ULP_CLASS_HID_39f97] = 1147, - [BNXT_ULP_CLASS_HID_3ac6f] = 1148, - [BNXT_ULP_CLASS_HID_383b7] = 1149, - [BNXT_ULP_CLASS_HID_3900f] = 1150, - [BNXT_ULP_CLASS_HID_38a73] = 1151, - [BNXT_ULP_CLASS_HID_396cb] = 1152, - [BNXT_ULP_CLASS_HID_7840b] = 1153, - [BNXT_ULP_CLASS_HID_79083] = 1154, - [BNXT_ULP_CLASS_HID_78ac7] = 1155, - [BNXT_ULP_CLASS_HID_7975f] = 1156, - [BNXT_ULP_CLASS_HID_7cbd3] = 1157, - [BNXT_ULP_CLASS_HID_7d7ab] = 1158, - [BNXT_ULP_CLASS_HID_7d1ef] = 1159, - [BNXT_ULP_CLASS_HID_7813b] = 1160, - [BNXT_ULP_CLASS_HID_7a7bf] = 1161, - [BNXT_ULP_CLASS_HID_7b437] = 1162, - [BNXT_ULP_CLASS_HID_7ae7b] = 1163, - [BNXT_ULP_CLASS_HID_7baf3] = 1164, - [BNXT_ULP_CLASS_HID_7921b] = 1165, - [BNXT_ULP_CLASS_HID_79e93] = 1166, - [BNXT_ULP_CLASS_HID_798d7] = 1167, - [BNXT_ULP_CLASS_HID_7a4af] = 1168, - [BNXT_ULP_CLASS_HID_7cda7] = 1169, - [BNXT_ULP_CLASS_HID_7da3f] = 1170, - [BNXT_ULP_CLASS_HID_7d463] = 1171, - [BNXT_ULP_CLASS_HID_7838f] = 1172, - [BNXT_ULP_CLASS_HID_7b803] = 1173, - [BNXT_ULP_CLASS_HID_7c49b] = 1174, - [BNXT_ULP_CLASS_HID_7bedf] = 1175, - [BNXT_ULP_CLASS_HID_7cb57] = 1176, - [BNXT_ULP_CLASS_HID_794ef] = 1177, - [BNXT_ULP_CLASS_HID_7a167] = 1178, - [BNXT_ULP_CLASS_HID_79aab] = 1179, - [BNXT_ULP_CLASS_HID_7a723] = 1180, - [BNXT_ULP_CLASS_HID_7dbb7] = 1181, - [BNXT_ULP_CLASS_HID_78bc3] = 1182, - [BNXT_ULP_CLASS_HID_78507] = 1183, - [BNXT_ULP_CLASS_HID_7919f] = 1184, - [BNXT_ULP_CLASS_HID_a3bb] = 1185, - [BNXT_ULP_CLASS_HID_b023] = 1186, - [BNXT_ULP_CLASS_HID_aa67] = 1187, - [BNXT_ULP_CLASS_HID_b6ef] = 1188, - [BNXT_ULP_CLASS_HID_8e07] = 1189, - [BNXT_ULP_CLASS_HID_9a8f] = 1190, - [BNXT_ULP_CLASS_HID_94c3] = 1191, - [BNXT_ULP_CLASS_HID_a14b] = 1192, - [BNXT_ULP_CLASS_HID_c7cf] = 1193, - [BNXT_ULP_CLASS_HID_d3b7] = 1194, - [BNXT_ULP_CLASS_HID_cd8b] = 1195, - [BNXT_ULP_CLASS_HID_da73] = 1196, - [BNXT_ULP_CLASS_HID_b1ab] = 1197, - [BNXT_ULP_CLASS_HID_be13] = 1198, - [BNXT_ULP_CLASS_HID_b857] = 1199, - [BNXT_ULP_CLASS_HID_c4df] = 1200, - [BNXT_ULP_CLASS_HID_49f6f] = 1201, - [BNXT_ULP_CLASS_HID_4abd7] = 1202, - [BNXT_ULP_CLASS_HID_4a52b] = 1203, - [BNXT_ULP_CLASS_HID_4b193] = 1204, - [BNXT_ULP_CLASS_HID_489cb] = 1205, - [BNXT_ULP_CLASS_HID_495b3] = 1206, - [BNXT_ULP_CLASS_HID_48ff7] = 1207, - [BNXT_ULP_CLASS_HID_49c7f] = 1208, - [BNXT_ULP_CLASS_HID_4c2f3] = 1209, - [BNXT_ULP_CLASS_HID_4cf7b] = 1210, - [BNXT_ULP_CLASS_HID_4c8bf] = 1211, - [BNXT_ULP_CLASS_HID_4d527] = 1212, - [BNXT_ULP_CLASS_HID_4ad5f] = 1213, - [BNXT_ULP_CLASS_HID_4b9c7] = 1214, - [BNXT_ULP_CLASS_HID_4b31b] = 1215, - [BNXT_ULP_CLASS_HID_4bf83] = 1216, - [BNXT_ULP_CLASS_HID_1b9bb] = 1217, - [BNXT_ULP_CLASS_HID_1c623] = 1218, - [BNXT_ULP_CLASS_HID_1c067] = 1219, - [BNXT_ULP_CLASS_HID_1ccef] = 1220, - [BNXT_ULP_CLASS_HID_1a407] = 1221, - [BNXT_ULP_CLASS_HID_1b08f] = 1222, - [BNXT_ULP_CLASS_HID_1aac3] = 1223, - [BNXT_ULP_CLASS_HID_1b74b] = 1224, - [BNXT_ULP_CLASS_HID_180f3] = 1225, - [BNXT_ULP_CLASS_HID_18d7b] = 1226, - [BNXT_ULP_CLASS_HID_186bf] = 1227, - [BNXT_ULP_CLASS_HID_19327] = 1228, - [BNXT_ULP_CLASS_HID_1c7ab] = 1229, - [BNXT_ULP_CLASS_HID_1d413] = 1230, - [BNXT_ULP_CLASS_HID_1ce57] = 1231, - [BNXT_ULP_CLASS_HID_1dadf] = 1232, - [BNXT_ULP_CLASS_HID_5b56f] = 1233, - [BNXT_ULP_CLASS_HID_5c1d7] = 1234, - [BNXT_ULP_CLASS_HID_5bb2b] = 1235, - [BNXT_ULP_CLASS_HID_5c793] = 1236, - [BNXT_ULP_CLASS_HID_59fcb] = 1237, - [BNXT_ULP_CLASS_HID_5abb3] = 1238, - [BNXT_ULP_CLASS_HID_5a5f7] = 1239, - [BNXT_ULP_CLASS_HID_5b27f] = 1240, - [BNXT_ULP_CLASS_HID_5d8f3] = 1241, - [BNXT_ULP_CLASS_HID_5882f] = 1242, - [BNXT_ULP_CLASS_HID_58263] = 1243, - [BNXT_ULP_CLASS_HID_58eeb] = 1244, - [BNXT_ULP_CLASS_HID_5c35f] = 1245, - [BNXT_ULP_CLASS_HID_5cfc7] = 1246, - [BNXT_ULP_CLASS_HID_5c91b] = 1247, - [BNXT_ULP_CLASS_HID_5d583] = 1248, - [BNXT_ULP_CLASS_HID_e93b] = 1249, - [BNXT_ULP_CLASS_HID_f5a3] = 1250, - [BNXT_ULP_CLASS_HID_efe7] = 1251, - [BNXT_ULP_CLASS_HID_fc6f] = 1252, - [BNXT_ULP_CLASS_HID_d387] = 1253, - [BNXT_ULP_CLASS_HID_e00f] = 1254, - [BNXT_ULP_CLASS_HID_da43] = 1255, - [BNXT_ULP_CLASS_HID_e6cb] = 1256, - [BNXT_ULP_CLASS_HID_cd4f] = 1257, - [BNXT_ULP_CLASS_HID_d937] = 1258, - [BNXT_ULP_CLASS_HID_d30b] = 1259, - [BNXT_ULP_CLASS_HID_c2a7] = 1260, - [BNXT_ULP_CLASS_HID_f72b] = 1261, - [BNXT_ULP_CLASS_HID_c393] = 1262, - [BNXT_ULP_CLASS_HID_fdd7] = 1263, - [BNXT_ULP_CLASS_HID_ca5f] = 1264, - [BNXT_ULP_CLASS_HID_4e4ef] = 1265, - [BNXT_ULP_CLASS_HID_4f157] = 1266, - [BNXT_ULP_CLASS_HID_4eaab] = 1267, - [BNXT_ULP_CLASS_HID_4f713] = 1268, - [BNXT_ULP_CLASS_HID_4cf4b] = 1269, - [BNXT_ULP_CLASS_HID_4db33] = 1270, - [BNXT_ULP_CLASS_HID_4d577] = 1271, - [BNXT_ULP_CLASS_HID_4e1ff] = 1272, - [BNXT_ULP_CLASS_HID_4c873] = 1273, - [BNXT_ULP_CLASS_HID_4d4fb] = 1274, - [BNXT_ULP_CLASS_HID_4ce3f] = 1275, - [BNXT_ULP_CLASS_HID_4daa7] = 1276, - [BNXT_ULP_CLASS_HID_4f2df] = 1277, - [BNXT_ULP_CLASS_HID_4ff47] = 1278, - [BNXT_ULP_CLASS_HID_4f89b] = 1279, - [BNXT_ULP_CLASS_HID_4c503] = 1280, - [BNXT_ULP_CLASS_HID_1ff3b] = 1281, - [BNXT_ULP_CLASS_HID_1cba3] = 1282, - [BNXT_ULP_CLASS_HID_1c5e7] = 1283, - [BNXT_ULP_CLASS_HID_1d26f] = 1284, - [BNXT_ULP_CLASS_HID_1e987] = 1285, - [BNXT_ULP_CLASS_HID_1f60f] = 1286, - [BNXT_ULP_CLASS_HID_1f043] = 1287, - [BNXT_ULP_CLASS_HID_1fccb] = 1288, - [BNXT_ULP_CLASS_HID_1c673] = 1289, - [BNXT_ULP_CLASS_HID_1d2fb] = 1290, - [BNXT_ULP_CLASS_HID_1cc3f] = 1291, - [BNXT_ULP_CLASS_HID_1d8a7] = 1292, - [BNXT_ULP_CLASS_HID_1cd2b] = 1293, - [BNXT_ULP_CLASS_HID_1d993] = 1294, - [BNXT_ULP_CLASS_HID_1d3d7] = 1295, - [BNXT_ULP_CLASS_HID_1c303] = 1296, - [BNXT_ULP_CLASS_HID_5faef] = 1297, - [BNXT_ULP_CLASS_HID_5c757] = 1298, - [BNXT_ULP_CLASS_HID_5c0ab] = 1299, - [BNXT_ULP_CLASS_HID_5cd13] = 1300, - [BNXT_ULP_CLASS_HID_5e54b] = 1301, - [BNXT_ULP_CLASS_HID_5f133] = 1302, - [BNXT_ULP_CLASS_HID_5eb77] = 1303, - [BNXT_ULP_CLASS_HID_5f7ff] = 1304, - [BNXT_ULP_CLASS_HID_5c127] = 1305, - [BNXT_ULP_CLASS_HID_5cdaf] = 1306, - [BNXT_ULP_CLASS_HID_5c7e3] = 1307, - [BNXT_ULP_CLASS_HID_5d46b] = 1308, - [BNXT_ULP_CLASS_HID_5c8df] = 1309, - [BNXT_ULP_CLASS_HID_5d547] = 1310, - [BNXT_ULP_CLASS_HID_5ce9b] = 1311, - [BNXT_ULP_CLASS_HID_5db03] = 1312, - [BNXT_ULP_CLASS_HID_a6fb] = 1313, - [BNXT_ULP_CLASS_HID_b363] = 1314, - [BNXT_ULP_CLASS_HID_aca7] = 1315, - [BNXT_ULP_CLASS_HID_b92f] = 1316, - [BNXT_ULP_CLASS_HID_b147] = 1317, - [BNXT_ULP_CLASS_HID_bdcf] = 1318, - [BNXT_ULP_CLASS_HID_b703] = 1319, - [BNXT_ULP_CLASS_HID_a38b] = 1320, - [BNXT_ULP_CLASS_HID_ea0f] = 1321, - [BNXT_ULP_CLASS_HID_f6f7] = 1322, - [BNXT_ULP_CLASS_HID_f0cb] = 1323, - [BNXT_ULP_CLASS_HID_a067] = 1324, - [BNXT_ULP_CLASS_HID_b4eb] = 1325, - [BNXT_ULP_CLASS_HID_e153] = 1326, - [BNXT_ULP_CLASS_HID_ba97] = 1327, - [BNXT_ULP_CLASS_HID_e71f] = 1328, - [BNXT_ULP_CLASS_HID_4a1af] = 1329, - [BNXT_ULP_CLASS_HID_4ae17] = 1330, - [BNXT_ULP_CLASS_HID_4a86b] = 1331, - [BNXT_ULP_CLASS_HID_4b4d3] = 1332, - [BNXT_ULP_CLASS_HID_4ac0b] = 1333, - [BNXT_ULP_CLASS_HID_4b8f3] = 1334, - [BNXT_ULP_CLASS_HID_4b237] = 1335, - [BNXT_ULP_CLASS_HID_4bebf] = 1336, - [BNXT_ULP_CLASS_HID_4e533] = 1337, - [BNXT_ULP_CLASS_HID_4f1bb] = 1338, - [BNXT_ULP_CLASS_HID_4ebff] = 1339, - [BNXT_ULP_CLASS_HID_4f867] = 1340, - [BNXT_ULP_CLASS_HID_4af9f] = 1341, - [BNXT_ULP_CLASS_HID_4bc07] = 1342, - [BNXT_ULP_CLASS_HID_4b65b] = 1343, - [BNXT_ULP_CLASS_HID_4e2c3] = 1344, - [BNXT_ULP_CLASS_HID_1bcfb] = 1345, - [BNXT_ULP_CLASS_HID_1e963] = 1346, - [BNXT_ULP_CLASS_HID_1e2a7] = 1347, - [BNXT_ULP_CLASS_HID_1ef2f] = 1348, - [BNXT_ULP_CLASS_HID_1a747] = 1349, - [BNXT_ULP_CLASS_HID_1b3cf] = 1350, - [BNXT_ULP_CLASS_HID_1ad03] = 1351, - [BNXT_ULP_CLASS_HID_1b98b] = 1352, - [BNXT_ULP_CLASS_HID_1a333] = 1353, - [BNXT_ULP_CLASS_HID_1afbb] = 1354, - [BNXT_ULP_CLASS_HID_1a9ff] = 1355, - [BNXT_ULP_CLASS_HID_1b667] = 1356, - [BNXT_ULP_CLASS_HID_1eaeb] = 1357, - [BNXT_ULP_CLASS_HID_1f753] = 1358, - [BNXT_ULP_CLASS_HID_1f097] = 1359, - [BNXT_ULP_CLASS_HID_1a0c3] = 1360, - [BNXT_ULP_CLASS_HID_5b7af] = 1361, - [BNXT_ULP_CLASS_HID_5e417] = 1362, - [BNXT_ULP_CLASS_HID_5be6b] = 1363, - [BNXT_ULP_CLASS_HID_5ead3] = 1364, - [BNXT_ULP_CLASS_HID_5a20b] = 1365, - [BNXT_ULP_CLASS_HID_5aef3] = 1366, - [BNXT_ULP_CLASS_HID_5a837] = 1367, - [BNXT_ULP_CLASS_HID_5b4bf] = 1368, - [BNXT_ULP_CLASS_HID_5fb33] = 1369, - [BNXT_ULP_CLASS_HID_5ab6f] = 1370, - [BNXT_ULP_CLASS_HID_5a4a3] = 1371, - [BNXT_ULP_CLASS_HID_5b12b] = 1372, - [BNXT_ULP_CLASS_HID_5e59f] = 1373, - [BNXT_ULP_CLASS_HID_5f207] = 1374, - [BNXT_ULP_CLASS_HID_5ec5b] = 1375, - [BNXT_ULP_CLASS_HID_5f8c3] = 1376, - [BNXT_ULP_CLASS_HID_ec7b] = 1377, - [BNXT_ULP_CLASS_HID_f8e3] = 1378, - [BNXT_ULP_CLASS_HID_f227] = 1379, - [BNXT_ULP_CLASS_HID_feaf] = 1380, - [BNXT_ULP_CLASS_HID_f6c7] = 1381, - [BNXT_ULP_CLASS_HID_e34f] = 1382, - [BNXT_ULP_CLASS_HID_fc83] = 1383, - [BNXT_ULP_CLASS_HID_e90b] = 1384, - [BNXT_ULP_CLASS_HID_ef8f] = 1385, - [BNXT_ULP_CLASS_HID_fc77] = 1386, - [BNXT_ULP_CLASS_HID_f64b] = 1387, - [BNXT_ULP_CLASS_HID_e5e7] = 1388, - [BNXT_ULP_CLASS_HID_fa6b] = 1389, - [BNXT_ULP_CLASS_HID_e6d3] = 1390, - [BNXT_ULP_CLASS_HID_e017] = 1391, - [BNXT_ULP_CLASS_HID_ec9f] = 1392, - [BNXT_ULP_CLASS_HID_4e72f] = 1393, - [BNXT_ULP_CLASS_HID_4f397] = 1394, - [BNXT_ULP_CLASS_HID_4edeb] = 1395, - [BNXT_ULP_CLASS_HID_4fa53] = 1396, - [BNXT_ULP_CLASS_HID_4f18b] = 1397, - [BNXT_ULP_CLASS_HID_4fe73] = 1398, - [BNXT_ULP_CLASS_HID_4f7b7] = 1399, - [BNXT_ULP_CLASS_HID_4e43f] = 1400, - [BNXT_ULP_CLASS_HID_4eab3] = 1401, - [BNXT_ULP_CLASS_HID_4f73b] = 1402, - [BNXT_ULP_CLASS_HID_4f17f] = 1403, - [BNXT_ULP_CLASS_HID_4e0ab] = 1404, - [BNXT_ULP_CLASS_HID_4f51f] = 1405, - [BNXT_ULP_CLASS_HID_4e187] = 1406, - [BNXT_ULP_CLASS_HID_4fbdb] = 1407, - [BNXT_ULP_CLASS_HID_4e843] = 1408, - [BNXT_ULP_CLASS_HID_1e27b] = 1409, - [BNXT_ULP_CLASS_HID_1eee3] = 1410, - [BNXT_ULP_CLASS_HID_1e827] = 1411, - [BNXT_ULP_CLASS_HID_1f4af] = 1412, - [BNXT_ULP_CLASS_HID_1ecc7] = 1413, - [BNXT_ULP_CLASS_HID_1f94f] = 1414, - [BNXT_ULP_CLASS_HID_1f283] = 1415, - [BNXT_ULP_CLASS_HID_1ff0b] = 1416, - [BNXT_ULP_CLASS_HID_1e8b3] = 1417, - [BNXT_ULP_CLASS_HID_1f53b] = 1418, - [BNXT_ULP_CLASS_HID_1ef7f] = 1419, - [BNXT_ULP_CLASS_HID_1fbe7] = 1420, - [BNXT_ULP_CLASS_HID_1f06b] = 1421, - [BNXT_ULP_CLASS_HID_1fcd3] = 1422, - [BNXT_ULP_CLASS_HID_1f617] = 1423, - [BNXT_ULP_CLASS_HID_1e643] = 1424, - [BNXT_ULP_CLASS_HID_5fd2f] = 1425, - [BNXT_ULP_CLASS_HID_5e997] = 1426, - [BNXT_ULP_CLASS_HID_5e3eb] = 1427, - [BNXT_ULP_CLASS_HID_5f053] = 1428, - [BNXT_ULP_CLASS_HID_5e78b] = 1429, - [BNXT_ULP_CLASS_HID_5f473] = 1430, - [BNXT_ULP_CLASS_HID_5edb7] = 1431, - [BNXT_ULP_CLASS_HID_5fa3f] = 1432, - [BNXT_ULP_CLASS_HID_5e467] = 1433, - [BNXT_ULP_CLASS_HID_5f0ef] = 1434, - [BNXT_ULP_CLASS_HID_5ea23] = 1435, - [BNXT_ULP_CLASS_HID_5f6ab] = 1436, - [BNXT_ULP_CLASS_HID_5eb1f] = 1437, - [BNXT_ULP_CLASS_HID_5f787] = 1438, - [BNXT_ULP_CLASS_HID_5f1db] = 1439, - [BNXT_ULP_CLASS_HID_5e177] = 1440, - [BNXT_ULP_CLASS_HID_498d] = 1441, - [BNXT_ULP_CLASS_HID_4fc9] = 1442, - [BNXT_ULP_CLASS_HID_0cf9] = 1443, - [BNXT_ULP_CLASS_HID_1335] = 1444, - [BNXT_ULP_CLASS_HID_232d] = 1445, - [BNXT_ULP_CLASS_HID_2969] = 1446, - [BNXT_ULP_CLASS_HID_4345] = 1447, - [BNXT_ULP_CLASS_HID_4981] = 1448, - [BNXT_ULP_CLASS_HID_45809] = 1449, - [BNXT_ULP_CLASS_HID_40179] = 1450, - [BNXT_ULP_CLASS_HID_431a9] = 1451, - [BNXT_ULP_CLASS_HID_437d5] = 1452, - [BNXT_ULP_CLASS_HID_44e61] = 1453, - [BNXT_ULP_CLASS_HID_454ad] = 1454, - [BNXT_ULP_CLASS_HID_42801] = 1455, - [BNXT_ULP_CLASS_HID_42e4d] = 1456, - [BNXT_ULP_CLASS_HID_22c13] = 1457, - [BNXT_ULP_CLASS_HID_2322f] = 1458, - [BNXT_ULP_CLASS_HID_2164f] = 1459, - [BNXT_ULP_CLASS_HID_21c8b] = 1460, - [BNXT_ULP_CLASS_HID_24f87] = 1461, - [BNXT_ULP_CLASS_HID_255c3] = 1462, - [BNXT_ULP_CLASS_HID_239e3] = 1463, - [BNXT_ULP_CLASS_HID_2403f] = 1464, - [BNXT_ULP_CLASS_HID_218c3] = 1465, - [BNXT_ULP_CLASS_HID_21f1f] = 1466, - [BNXT_ULP_CLASS_HID_2033f] = 1467, - [BNXT_ULP_CLASS_HID_2097b] = 1468, - [BNXT_ULP_CLASS_HID_23c77] = 1469, - [BNXT_ULP_CLASS_HID_242b3] = 1470, - [BNXT_ULP_CLASS_HID_226d3] = 1471, - [BNXT_ULP_CLASS_HID_22cef] = 1472, - [BNXT_ULP_CLASS_HID_62727] = 1473, - [BNXT_ULP_CLASS_HID_62d63] = 1474, - [BNXT_ULP_CLASS_HID_61183] = 1475, - [BNXT_ULP_CLASS_HID_617df] = 1476, - [BNXT_ULP_CLASS_HID_64adb] = 1477, - [BNXT_ULP_CLASS_HID_65117] = 1478, - [BNXT_ULP_CLASS_HID_63537] = 1479, - [BNXT_ULP_CLASS_HID_63b73] = 1480, - [BNXT_ULP_CLASS_HID_61417] = 1481, - [BNXT_ULP_CLASS_HID_61a53] = 1482, - [BNXT_ULP_CLASS_HID_65b3f] = 1483, - [BNXT_ULP_CLASS_HID_6048f] = 1484, - [BNXT_ULP_CLASS_HID_6378b] = 1485, - [BNXT_ULP_CLASS_HID_63dc7] = 1486, - [BNXT_ULP_CLASS_HID_621e7] = 1487, - [BNXT_ULP_CLASS_HID_62823] = 1488, - [BNXT_ULP_CLASS_HID_8b0b] = 1489, - [BNXT_ULP_CLASS_HID_9137] = 1490, - [BNXT_ULP_CLASS_HID_d223] = 1491, - [BNXT_ULP_CLASS_HID_d86f] = 1492, - [BNXT_ULP_CLASS_HID_ae9f] = 1493, - [BNXT_ULP_CLASS_HID_b4db] = 1494, - [BNXT_ULP_CLASS_HID_98fb] = 1495, - [BNXT_ULP_CLASS_HID_9f27] = 1496, - [BNXT_ULP_CLASS_HID_4863f] = 1497, - [BNXT_ULP_CLASS_HID_48c7b] = 1498, - [BNXT_ULP_CLASS_HID_4cd57] = 1499, - [BNXT_ULP_CLASS_HID_4d393] = 1500, - [BNXT_ULP_CLASS_HID_4a9c3] = 1501, - [BNXT_ULP_CLASS_HID_4b00f] = 1502, - [BNXT_ULP_CLASS_HID_4942f] = 1503, - [BNXT_ULP_CLASS_HID_49a6b] = 1504, - [BNXT_ULP_CLASS_HID_1a10b] = 1505, - [BNXT_ULP_CLASS_HID_1a737] = 1506, - [BNXT_ULP_CLASS_HID_18b57] = 1507, - [BNXT_ULP_CLASS_HID_19193] = 1508, - [BNXT_ULP_CLASS_HID_1c49f] = 1509, - [BNXT_ULP_CLASS_HID_1cadb] = 1510, - [BNXT_ULP_CLASS_HID_1aefb] = 1511, - [BNXT_ULP_CLASS_HID_1b527] = 1512, - [BNXT_ULP_CLASS_HID_59c3f] = 1513, - [BNXT_ULP_CLASS_HID_5a27b] = 1514, - [BNXT_ULP_CLASS_HID_5869b] = 1515, - [BNXT_ULP_CLASS_HID_58cc7] = 1516, - [BNXT_ULP_CLASS_HID_5bfc3] = 1517, - [BNXT_ULP_CLASS_HID_5c60f] = 1518, - [BNXT_ULP_CLASS_HID_5aa2f] = 1519, - [BNXT_ULP_CLASS_HID_5b06b] = 1520, - [BNXT_ULP_CLASS_HID_49ad] = 1521, - [BNXT_ULP_CLASS_HID_4fe9] = 1522, - [BNXT_ULP_CLASS_HID_0cd9] = 1523, - [BNXT_ULP_CLASS_HID_1315] = 1524, - [BNXT_ULP_CLASS_HID_230d] = 1525, - [BNXT_ULP_CLASS_HID_2949] = 1526, - [BNXT_ULP_CLASS_HID_4365] = 1527, - [BNXT_ULP_CLASS_HID_49a1] = 1528, - [BNXT_ULP_CLASS_HID_4035] = 1529, - [BNXT_ULP_CLASS_HID_4671] = 1530, - [BNXT_ULP_CLASS_HID_0361] = 1531, - [BNXT_ULP_CLASS_HID_09bd] = 1532, - [BNXT_ULP_CLASS_HID_1995] = 1533, - [BNXT_ULP_CLASS_HID_1fd1] = 1534, - [BNXT_ULP_CLASS_HID_398d] = 1535, - [BNXT_ULP_CLASS_HID_3fc9] = 1536, - [BNXT_ULP_CLASS_HID_444e1] = 1537, - [BNXT_ULP_CLASS_HID_44b3d] = 1538, - [BNXT_ULP_CLASS_HID_4082d] = 1539, - [BNXT_ULP_CLASS_HID_40e69] = 1540, - [BNXT_ULP_CLASS_HID_41e41] = 1541, - [BNXT_ULP_CLASS_HID_4249d] = 1542, - [BNXT_ULP_CLASS_HID_43eb9] = 1543, - [BNXT_ULP_CLASS_HID_444f5] = 1544, - [BNXT_ULP_CLASS_HID_43b09] = 1545, - [BNXT_ULP_CLASS_HID_44145] = 1546, - [BNXT_ULP_CLASS_HID_45b61] = 1547, - [BNXT_ULP_CLASS_HID_404f1] = 1548, - [BNXT_ULP_CLASS_HID_414e9] = 1549, - [BNXT_ULP_CLASS_HID_41b25] = 1550, - [BNXT_ULP_CLASS_HID_434c1] = 1551, - [BNXT_ULP_CLASS_HID_43b1d] = 1552, - [BNXT_ULP_CLASS_HID_45829] = 1553, - [BNXT_ULP_CLASS_HID_40159] = 1554, - [BNXT_ULP_CLASS_HID_43189] = 1555, - [BNXT_ULP_CLASS_HID_437f5] = 1556, - [BNXT_ULP_CLASS_HID_44e41] = 1557, - [BNXT_ULP_CLASS_HID_4548d] = 1558, - [BNXT_ULP_CLASS_HID_42821] = 1559, - [BNXT_ULP_CLASS_HID_42e6d] = 1560, - [BNXT_ULP_CLASS_HID_6271d] = 1561, - [BNXT_ULP_CLASS_HID_62d59] = 1562, - [BNXT_ULP_CLASS_HID_600fd] = 1563, - [BNXT_ULP_CLASS_HID_60739] = 1564, - [BNXT_ULP_CLASS_HID_61db5] = 1565, - [BNXT_ULP_CLASS_HID_623f1] = 1566, - [BNXT_ULP_CLASS_HID_65421] = 1567, - [BNXT_ULP_CLASS_HID_65a6d] = 1568, - [BNXT_ULP_CLASS_HID_5111d] = 1569, - [BNXT_ULP_CLASS_HID_51759] = 1570, - [BNXT_ULP_CLASS_HID_54789] = 1571, - [BNXT_ULP_CLASS_HID_54df5] = 1572, - [BNXT_ULP_CLASS_HID_507b5] = 1573, - [BNXT_ULP_CLASS_HID_50df1] = 1574, - [BNXT_ULP_CLASS_HID_53e21] = 1575, - [BNXT_ULP_CLASS_HID_5446d] = 1576, - [BNXT_ULP_CLASS_HID_73d1d] = 1577, - [BNXT_ULP_CLASS_HID_74359] = 1578, - [BNXT_ULP_CLASS_HID_716fd] = 1579, - [BNXT_ULP_CLASS_HID_71d39] = 1580, - [BNXT_ULP_CLASS_HID_733b5] = 1581, - [BNXT_ULP_CLASS_HID_739f1] = 1582, - [BNXT_ULP_CLASS_HID_70d15] = 1583, - [BNXT_ULP_CLASS_HID_71351] = 1584, - [BNXT_ULP_CLASS_HID_49cd] = 1585, - [BNXT_ULP_CLASS_HID_4f89] = 1586, - [BNXT_ULP_CLASS_HID_0cb9] = 1587, - [BNXT_ULP_CLASS_HID_1375] = 1588, - [BNXT_ULP_CLASS_HID_236d] = 1589, - [BNXT_ULP_CLASS_HID_2929] = 1590, - [BNXT_ULP_CLASS_HID_4305] = 1591, - [BNXT_ULP_CLASS_HID_49c1] = 1592, - [BNXT_ULP_CLASS_HID_4055] = 1593, - [BNXT_ULP_CLASS_HID_4611] = 1594, - [BNXT_ULP_CLASS_HID_0301] = 1595, - [BNXT_ULP_CLASS_HID_09dd] = 1596, - [BNXT_ULP_CLASS_HID_19f5] = 1597, - [BNXT_ULP_CLASS_HID_1fb1] = 1598, - [BNXT_ULP_CLASS_HID_39ed] = 1599, - [BNXT_ULP_CLASS_HID_3fa9] = 1600, - [BNXT_ULP_CLASS_HID_44481] = 1601, - [BNXT_ULP_CLASS_HID_44b5d] = 1602, - [BNXT_ULP_CLASS_HID_4084d] = 1603, - [BNXT_ULP_CLASS_HID_40e09] = 1604, - [BNXT_ULP_CLASS_HID_41e21] = 1605, - [BNXT_ULP_CLASS_HID_424fd] = 1606, - [BNXT_ULP_CLASS_HID_43ed9] = 1607, - [BNXT_ULP_CLASS_HID_44495] = 1608, - [BNXT_ULP_CLASS_HID_43b69] = 1609, - [BNXT_ULP_CLASS_HID_44125] = 1610, - [BNXT_ULP_CLASS_HID_45b01] = 1611, - [BNXT_ULP_CLASS_HID_40491] = 1612, - [BNXT_ULP_CLASS_HID_41489] = 1613, - [BNXT_ULP_CLASS_HID_41b45] = 1614, - [BNXT_ULP_CLASS_HID_434a1] = 1615, - [BNXT_ULP_CLASS_HID_43b7d] = 1616, - [BNXT_ULP_CLASS_HID_45849] = 1617, - [BNXT_ULP_CLASS_HID_40139] = 1618, - [BNXT_ULP_CLASS_HID_431e9] = 1619, - [BNXT_ULP_CLASS_HID_43795] = 1620, - [BNXT_ULP_CLASS_HID_44e21] = 1621, - [BNXT_ULP_CLASS_HID_454ed] = 1622, - [BNXT_ULP_CLASS_HID_42841] = 1623, - [BNXT_ULP_CLASS_HID_42e0d] = 1624, - [BNXT_ULP_CLASS_HID_6277d] = 1625, - [BNXT_ULP_CLASS_HID_62d39] = 1626, - [BNXT_ULP_CLASS_HID_6009d] = 1627, - [BNXT_ULP_CLASS_HID_60759] = 1628, - [BNXT_ULP_CLASS_HID_61dd5] = 1629, - [BNXT_ULP_CLASS_HID_62391] = 1630, - [BNXT_ULP_CLASS_HID_65441] = 1631, - [BNXT_ULP_CLASS_HID_65a0d] = 1632, - [BNXT_ULP_CLASS_HID_5117d] = 1633, - [BNXT_ULP_CLASS_HID_51739] = 1634, - [BNXT_ULP_CLASS_HID_547e9] = 1635, - [BNXT_ULP_CLASS_HID_54d95] = 1636, - [BNXT_ULP_CLASS_HID_507d5] = 1637, - [BNXT_ULP_CLASS_HID_50d91] = 1638, - [BNXT_ULP_CLASS_HID_53e41] = 1639, - [BNXT_ULP_CLASS_HID_5440d] = 1640, - [BNXT_ULP_CLASS_HID_73d7d] = 1641, - [BNXT_ULP_CLASS_HID_74339] = 1642, - [BNXT_ULP_CLASS_HID_7169d] = 1643, - [BNXT_ULP_CLASS_HID_71d59] = 1644, - [BNXT_ULP_CLASS_HID_733d5] = 1645, - [BNXT_ULP_CLASS_HID_73991] = 1646, - [BNXT_ULP_CLASS_HID_70d75] = 1647, - [BNXT_ULP_CLASS_HID_71331] = 1648, - [BNXT_ULP_CLASS_HID_22c33] = 1649, - [BNXT_ULP_CLASS_HID_2320f] = 1650, - [BNXT_ULP_CLASS_HID_2166f] = 1651, - [BNXT_ULP_CLASS_HID_21cab] = 1652, - [BNXT_ULP_CLASS_HID_24fa7] = 1653, - [BNXT_ULP_CLASS_HID_255e3] = 1654, - [BNXT_ULP_CLASS_HID_239c3] = 1655, - [BNXT_ULP_CLASS_HID_2401f] = 1656, - [BNXT_ULP_CLASS_HID_218e3] = 1657, - [BNXT_ULP_CLASS_HID_21f3f] = 1658, - [BNXT_ULP_CLASS_HID_2031f] = 1659, - [BNXT_ULP_CLASS_HID_2095b] = 1660, - [BNXT_ULP_CLASS_HID_23c57] = 1661, - [BNXT_ULP_CLASS_HID_24293] = 1662, - [BNXT_ULP_CLASS_HID_226f3] = 1663, - [BNXT_ULP_CLASS_HID_22ccf] = 1664, - [BNXT_ULP_CLASS_HID_62707] = 1665, - [BNXT_ULP_CLASS_HID_62d43] = 1666, - [BNXT_ULP_CLASS_HID_611a3] = 1667, - [BNXT_ULP_CLASS_HID_617ff] = 1668, - [BNXT_ULP_CLASS_HID_64afb] = 1669, - [BNXT_ULP_CLASS_HID_65137] = 1670, - [BNXT_ULP_CLASS_HID_63517] = 1671, - [BNXT_ULP_CLASS_HID_63b53] = 1672, - [BNXT_ULP_CLASS_HID_61437] = 1673, - [BNXT_ULP_CLASS_HID_61a73] = 1674, - [BNXT_ULP_CLASS_HID_65b1f] = 1675, - [BNXT_ULP_CLASS_HID_604af] = 1676, - [BNXT_ULP_CLASS_HID_637ab] = 1677, - [BNXT_ULP_CLASS_HID_63de7] = 1678, - [BNXT_ULP_CLASS_HID_621c7] = 1679, - [BNXT_ULP_CLASS_HID_62803] = 1680, - [BNXT_ULP_CLASS_HID_34233] = 1681, - [BNXT_ULP_CLASS_HID_3480f] = 1682, - [BNXT_ULP_CLASS_HID_32c6f] = 1683, - [BNXT_ULP_CLASS_HID_332ab] = 1684, - [BNXT_ULP_CLASS_HID_308fb] = 1685, - [BNXT_ULP_CLASS_HID_30f37] = 1686, - [BNXT_ULP_CLASS_HID_34fc3] = 1687, - [BNXT_ULP_CLASS_HID_3561f] = 1688, - [BNXT_ULP_CLASS_HID_32ee3] = 1689, - [BNXT_ULP_CLASS_HID_3353f] = 1690, - [BNXT_ULP_CLASS_HID_3191f] = 1691, - [BNXT_ULP_CLASS_HID_31f5b] = 1692, - [BNXT_ULP_CLASS_HID_35257] = 1693, - [BNXT_ULP_CLASS_HID_35893] = 1694, - [BNXT_ULP_CLASS_HID_33cf3] = 1695, - [BNXT_ULP_CLASS_HID_342cf] = 1696, - [BNXT_ULP_CLASS_HID_73d07] = 1697, - [BNXT_ULP_CLASS_HID_74343] = 1698, - [BNXT_ULP_CLASS_HID_727a3] = 1699, - [BNXT_ULP_CLASS_HID_72dff] = 1700, - [BNXT_ULP_CLASS_HID_703cf] = 1701, - [BNXT_ULP_CLASS_HID_70a0b] = 1702, - [BNXT_ULP_CLASS_HID_74b17] = 1703, - [BNXT_ULP_CLASS_HID_75153] = 1704, - [BNXT_ULP_CLASS_HID_72a37] = 1705, - [BNXT_ULP_CLASS_HID_73073] = 1706, - [BNXT_ULP_CLASS_HID_71453] = 1707, - [BNXT_ULP_CLASS_HID_71aaf] = 1708, - [BNXT_ULP_CLASS_HID_74dab] = 1709, - [BNXT_ULP_CLASS_HID_753e7] = 1710, - [BNXT_ULP_CLASS_HID_737c7] = 1711, - [BNXT_ULP_CLASS_HID_73e03] = 1712, - [BNXT_ULP_CLASS_HID_2b733] = 1713, - [BNXT_ULP_CLASS_HID_2bd0f] = 1714, - [BNXT_ULP_CLASS_HID_2a16f] = 1715, - [BNXT_ULP_CLASS_HID_2a7ab] = 1716, - [BNXT_ULP_CLASS_HID_2daa7] = 1717, - [BNXT_ULP_CLASS_HID_28437] = 1718, - [BNXT_ULP_CLASS_HID_2c4c3] = 1719, - [BNXT_ULP_CLASS_HID_2cb1f] = 1720, - [BNXT_ULP_CLASS_HID_2a3e3] = 1721, - [BNXT_ULP_CLASS_HID_2aa3f] = 1722, - [BNXT_ULP_CLASS_HID_28e1f] = 1723, - [BNXT_ULP_CLASS_HID_2945b] = 1724, - [BNXT_ULP_CLASS_HID_2c757] = 1725, - [BNXT_ULP_CLASS_HID_2cd93] = 1726, - [BNXT_ULP_CLASS_HID_2b1f3] = 1727, - [BNXT_ULP_CLASS_HID_2b7cf] = 1728, - [BNXT_ULP_CLASS_HID_6b207] = 1729, - [BNXT_ULP_CLASS_HID_6b843] = 1730, - [BNXT_ULP_CLASS_HID_69ca3] = 1731, - [BNXT_ULP_CLASS_HID_6a2ff] = 1732, - [BNXT_ULP_CLASS_HID_6d5fb] = 1733, - [BNXT_ULP_CLASS_HID_6dc37] = 1734, - [BNXT_ULP_CLASS_HID_6c017] = 1735, - [BNXT_ULP_CLASS_HID_6c653] = 1736, - [BNXT_ULP_CLASS_HID_69f37] = 1737, - [BNXT_ULP_CLASS_HID_6a573] = 1738, - [BNXT_ULP_CLASS_HID_68953] = 1739, - [BNXT_ULP_CLASS_HID_68faf] = 1740, - [BNXT_ULP_CLASS_HID_6c2ab] = 1741, - [BNXT_ULP_CLASS_HID_6c8e7] = 1742, - [BNXT_ULP_CLASS_HID_6acc7] = 1743, - [BNXT_ULP_CLASS_HID_6b303] = 1744, - [BNXT_ULP_CLASS_HID_3cd33] = 1745, - [BNXT_ULP_CLASS_HID_3d30f] = 1746, - [BNXT_ULP_CLASS_HID_3b76f] = 1747, - [BNXT_ULP_CLASS_HID_3bdab] = 1748, - [BNXT_ULP_CLASS_HID_393fb] = 1749, - [BNXT_ULP_CLASS_HID_39a37] = 1750, - [BNXT_ULP_CLASS_HID_3dac3] = 1751, - [BNXT_ULP_CLASS_HID_38453] = 1752, - [BNXT_ULP_CLASS_HID_3b9e3] = 1753, - [BNXT_ULP_CLASS_HID_3c03f] = 1754, - [BNXT_ULP_CLASS_HID_3a41f] = 1755, - [BNXT_ULP_CLASS_HID_3aa5b] = 1756, - [BNXT_ULP_CLASS_HID_380ab] = 1757, - [BNXT_ULP_CLASS_HID_386e7] = 1758, - [BNXT_ULP_CLASS_HID_3c7f3] = 1759, - [BNXT_ULP_CLASS_HID_3cdcf] = 1760, - [BNXT_ULP_CLASS_HID_7c807] = 1761, - [BNXT_ULP_CLASS_HID_7ce43] = 1762, - [BNXT_ULP_CLASS_HID_7b2a3] = 1763, - [BNXT_ULP_CLASS_HID_7b8ff] = 1764, - [BNXT_ULP_CLASS_HID_78ecf] = 1765, - [BNXT_ULP_CLASS_HID_7950b] = 1766, - [BNXT_ULP_CLASS_HID_7d617] = 1767, - [BNXT_ULP_CLASS_HID_7dc53] = 1768, - [BNXT_ULP_CLASS_HID_7b537] = 1769, - [BNXT_ULP_CLASS_HID_7bb73] = 1770, - [BNXT_ULP_CLASS_HID_79f53] = 1771, - [BNXT_ULP_CLASS_HID_7a5af] = 1772, - [BNXT_ULP_CLASS_HID_7d8ab] = 1773, - [BNXT_ULP_CLASS_HID_7823b] = 1774, - [BNXT_ULP_CLASS_HID_7c2c7] = 1775, - [BNXT_ULP_CLASS_HID_7c903] = 1776, - [BNXT_ULP_CLASS_HID_8b2b] = 1777, - [BNXT_ULP_CLASS_HID_9117] = 1778, - [BNXT_ULP_CLASS_HID_d203] = 1779, - [BNXT_ULP_CLASS_HID_d84f] = 1780, - [BNXT_ULP_CLASS_HID_aebf] = 1781, - [BNXT_ULP_CLASS_HID_b4fb] = 1782, - [BNXT_ULP_CLASS_HID_98db] = 1783, - [BNXT_ULP_CLASS_HID_9f07] = 1784, - [BNXT_ULP_CLASS_HID_4861f] = 1785, - [BNXT_ULP_CLASS_HID_48c5b] = 1786, - [BNXT_ULP_CLASS_HID_4cd77] = 1787, - [BNXT_ULP_CLASS_HID_4d3b3] = 1788, - [BNXT_ULP_CLASS_HID_4a9e3] = 1789, - [BNXT_ULP_CLASS_HID_4b02f] = 1790, - [BNXT_ULP_CLASS_HID_4940f] = 1791, - [BNXT_ULP_CLASS_HID_49a4b] = 1792, - [BNXT_ULP_CLASS_HID_1a12b] = 1793, - [BNXT_ULP_CLASS_HID_1a717] = 1794, - [BNXT_ULP_CLASS_HID_18b77] = 1795, - [BNXT_ULP_CLASS_HID_191b3] = 1796, - [BNXT_ULP_CLASS_HID_1c4bf] = 1797, - [BNXT_ULP_CLASS_HID_1cafb] = 1798, - [BNXT_ULP_CLASS_HID_1aedb] = 1799, - [BNXT_ULP_CLASS_HID_1b507] = 1800, - [BNXT_ULP_CLASS_HID_59c1f] = 1801, - [BNXT_ULP_CLASS_HID_5a25b] = 1802, - [BNXT_ULP_CLASS_HID_586bb] = 1803, - [BNXT_ULP_CLASS_HID_58ce7] = 1804, - [BNXT_ULP_CLASS_HID_5bfe3] = 1805, - [BNXT_ULP_CLASS_HID_5c62f] = 1806, - [BNXT_ULP_CLASS_HID_5aa0f] = 1807, - [BNXT_ULP_CLASS_HID_5b04b] = 1808, - [BNXT_ULP_CLASS_HID_d0ab] = 1809, - [BNXT_ULP_CLASS_HID_d697] = 1810, - [BNXT_ULP_CLASS_HID_d783] = 1811, - [BNXT_ULP_CLASS_HID_c133] = 1812, - [BNXT_ULP_CLASS_HID_f43f] = 1813, - [BNXT_ULP_CLASS_HID_fa7b] = 1814, - [BNXT_ULP_CLASS_HID_de5b] = 1815, - [BNXT_ULP_CLASS_HID_e487] = 1816, - [BNXT_ULP_CLASS_HID_4cb9f] = 1817, - [BNXT_ULP_CLASS_HID_4d1db] = 1818, - [BNXT_ULP_CLASS_HID_4d2f7] = 1819, - [BNXT_ULP_CLASS_HID_4d933] = 1820, - [BNXT_ULP_CLASS_HID_4ef63] = 1821, - [BNXT_ULP_CLASS_HID_4f5af] = 1822, - [BNXT_ULP_CLASS_HID_4d98f] = 1823, - [BNXT_ULP_CLASS_HID_4dfcb] = 1824, - [BNXT_ULP_CLASS_HID_1e6ab] = 1825, - [BNXT_ULP_CLASS_HID_1ec97] = 1826, - [BNXT_ULP_CLASS_HID_1d0f7] = 1827, - [BNXT_ULP_CLASS_HID_1d733] = 1828, - [BNXT_ULP_CLASS_HID_1ca3f] = 1829, - [BNXT_ULP_CLASS_HID_1d07b] = 1830, - [BNXT_ULP_CLASS_HID_1f45b] = 1831, - [BNXT_ULP_CLASS_HID_1fa87] = 1832, - [BNXT_ULP_CLASS_HID_5e19f] = 1833, - [BNXT_ULP_CLASS_HID_5e7db] = 1834, - [BNXT_ULP_CLASS_HID_5cc3b] = 1835, - [BNXT_ULP_CLASS_HID_5d267] = 1836, - [BNXT_ULP_CLASS_HID_5c563] = 1837, - [BNXT_ULP_CLASS_HID_5cbaf] = 1838, - [BNXT_ULP_CLASS_HID_5ef8f] = 1839, - [BNXT_ULP_CLASS_HID_5f5cb] = 1840, - [BNXT_ULP_CLASS_HID_adeb] = 1841, - [BNXT_ULP_CLASS_HID_b3d7] = 1842, - [BNXT_ULP_CLASS_HID_f4c3] = 1843, - [BNXT_ULP_CLASS_HID_fb0f] = 1844, - [BNXT_ULP_CLASS_HID_b17f] = 1845, - [BNXT_ULP_CLASS_HID_b7bb] = 1846, - [BNXT_ULP_CLASS_HID_bb9b] = 1847, - [BNXT_ULP_CLASS_HID_a1c7] = 1848, - [BNXT_ULP_CLASS_HID_4a8df] = 1849, - [BNXT_ULP_CLASS_HID_4af1b] = 1850, - [BNXT_ULP_CLASS_HID_4f037] = 1851, - [BNXT_ULP_CLASS_HID_4f673] = 1852, - [BNXT_ULP_CLASS_HID_4aca3] = 1853, - [BNXT_ULP_CLASS_HID_4b2ef] = 1854, - [BNXT_ULP_CLASS_HID_4b6cf] = 1855, - [BNXT_ULP_CLASS_HID_4bd0b] = 1856, - [BNXT_ULP_CLASS_HID_1a3eb] = 1857, - [BNXT_ULP_CLASS_HID_1a9d7] = 1858, - [BNXT_ULP_CLASS_HID_1ae37] = 1859, - [BNXT_ULP_CLASS_HID_1b473] = 1860, - [BNXT_ULP_CLASS_HID_1e77f] = 1861, - [BNXT_ULP_CLASS_HID_1edbb] = 1862, - [BNXT_ULP_CLASS_HID_1b19b] = 1863, - [BNXT_ULP_CLASS_HID_1b7c7] = 1864, - [BNXT_ULP_CLASS_HID_5bedf] = 1865, - [BNXT_ULP_CLASS_HID_5a51b] = 1866, - [BNXT_ULP_CLASS_HID_5a97b] = 1867, - [BNXT_ULP_CLASS_HID_5afa7] = 1868, - [BNXT_ULP_CLASS_HID_5e2a3] = 1869, - [BNXT_ULP_CLASS_HID_5e8ef] = 1870, - [BNXT_ULP_CLASS_HID_5accf] = 1871, - [BNXT_ULP_CLASS_HID_5b30b] = 1872, - [BNXT_ULP_CLASS_HID_f36b] = 1873, - [BNXT_ULP_CLASS_HID_f957] = 1874, - [BNXT_ULP_CLASS_HID_fa43] = 1875, - [BNXT_ULP_CLASS_HID_e3f3] = 1876, - [BNXT_ULP_CLASS_HID_f6ff] = 1877, - [BNXT_ULP_CLASS_HID_fd3b] = 1878, - [BNXT_ULP_CLASS_HID_e11b] = 1879, - [BNXT_ULP_CLASS_HID_e747] = 1880, - [BNXT_ULP_CLASS_HID_4ee5f] = 1881, - [BNXT_ULP_CLASS_HID_4f49b] = 1882, - [BNXT_ULP_CLASS_HID_4f5b7] = 1883, - [BNXT_ULP_CLASS_HID_4fbf3] = 1884, - [BNXT_ULP_CLASS_HID_4f223] = 1885, - [BNXT_ULP_CLASS_HID_4f86f] = 1886, - [BNXT_ULP_CLASS_HID_4fc4f] = 1887, - [BNXT_ULP_CLASS_HID_4e28b] = 1888, - [BNXT_ULP_CLASS_HID_1e96b] = 1889, - [BNXT_ULP_CLASS_HID_1ef57] = 1890, - [BNXT_ULP_CLASS_HID_1f3b7] = 1891, - [BNXT_ULP_CLASS_HID_1f9f3] = 1892, - [BNXT_ULP_CLASS_HID_1ecff] = 1893, - [BNXT_ULP_CLASS_HID_1f33b] = 1894, - [BNXT_ULP_CLASS_HID_1f71b] = 1895, - [BNXT_ULP_CLASS_HID_1fd47] = 1896, - [BNXT_ULP_CLASS_HID_5e45f] = 1897, - [BNXT_ULP_CLASS_HID_5ea9b] = 1898, - [BNXT_ULP_CLASS_HID_5eefb] = 1899, - [BNXT_ULP_CLASS_HID_5f527] = 1900, - [BNXT_ULP_CLASS_HID_5e823] = 1901, - [BNXT_ULP_CLASS_HID_5ee6f] = 1902, - [BNXT_ULP_CLASS_HID_5f24f] = 1903, - [BNXT_ULP_CLASS_HID_5f88b] = 1904, - [BNXT_ULP_CLASS_HID_22c53] = 1905, - [BNXT_ULP_CLASS_HID_2326f] = 1906, - [BNXT_ULP_CLASS_HID_2160f] = 1907, - [BNXT_ULP_CLASS_HID_21ccb] = 1908, - [BNXT_ULP_CLASS_HID_24fc7] = 1909, - [BNXT_ULP_CLASS_HID_25583] = 1910, - [BNXT_ULP_CLASS_HID_239a3] = 1911, - [BNXT_ULP_CLASS_HID_2407f] = 1912, - [BNXT_ULP_CLASS_HID_21883] = 1913, - [BNXT_ULP_CLASS_HID_21f5f] = 1914, - [BNXT_ULP_CLASS_HID_2037f] = 1915, - [BNXT_ULP_CLASS_HID_2093b] = 1916, - [BNXT_ULP_CLASS_HID_23c37] = 1917, - [BNXT_ULP_CLASS_HID_242f3] = 1918, - [BNXT_ULP_CLASS_HID_22693] = 1919, - [BNXT_ULP_CLASS_HID_22caf] = 1920, - [BNXT_ULP_CLASS_HID_62767] = 1921, - [BNXT_ULP_CLASS_HID_62d23] = 1922, - [BNXT_ULP_CLASS_HID_611c3] = 1923, - [BNXT_ULP_CLASS_HID_6179f] = 1924, - [BNXT_ULP_CLASS_HID_64a9b] = 1925, - [BNXT_ULP_CLASS_HID_65157] = 1926, - [BNXT_ULP_CLASS_HID_63577] = 1927, - [BNXT_ULP_CLASS_HID_63b33] = 1928, - [BNXT_ULP_CLASS_HID_61457] = 1929, - [BNXT_ULP_CLASS_HID_61a13] = 1930, - [BNXT_ULP_CLASS_HID_65b7f] = 1931, - [BNXT_ULP_CLASS_HID_604cf] = 1932, - [BNXT_ULP_CLASS_HID_637cb] = 1933, - [BNXT_ULP_CLASS_HID_63d87] = 1934, - [BNXT_ULP_CLASS_HID_621a7] = 1935, - [BNXT_ULP_CLASS_HID_62863] = 1936, - [BNXT_ULP_CLASS_HID_34253] = 1937, - [BNXT_ULP_CLASS_HID_3486f] = 1938, - [BNXT_ULP_CLASS_HID_32c0f] = 1939, - [BNXT_ULP_CLASS_HID_332cb] = 1940, - [BNXT_ULP_CLASS_HID_3089b] = 1941, - [BNXT_ULP_CLASS_HID_30f57] = 1942, - [BNXT_ULP_CLASS_HID_34fa3] = 1943, - [BNXT_ULP_CLASS_HID_3567f] = 1944, - [BNXT_ULP_CLASS_HID_32e83] = 1945, - [BNXT_ULP_CLASS_HID_3355f] = 1946, - [BNXT_ULP_CLASS_HID_3197f] = 1947, - [BNXT_ULP_CLASS_HID_31f3b] = 1948, - [BNXT_ULP_CLASS_HID_35237] = 1949, - [BNXT_ULP_CLASS_HID_358f3] = 1950, - [BNXT_ULP_CLASS_HID_33c93] = 1951, - [BNXT_ULP_CLASS_HID_342af] = 1952, - [BNXT_ULP_CLASS_HID_73d67] = 1953, - [BNXT_ULP_CLASS_HID_74323] = 1954, - [BNXT_ULP_CLASS_HID_727c3] = 1955, - [BNXT_ULP_CLASS_HID_72d9f] = 1956, - [BNXT_ULP_CLASS_HID_703af] = 1957, - [BNXT_ULP_CLASS_HID_70a6b] = 1958, - [BNXT_ULP_CLASS_HID_74b77] = 1959, - [BNXT_ULP_CLASS_HID_75133] = 1960, - [BNXT_ULP_CLASS_HID_72a57] = 1961, - [BNXT_ULP_CLASS_HID_73013] = 1962, - [BNXT_ULP_CLASS_HID_71433] = 1963, - [BNXT_ULP_CLASS_HID_71acf] = 1964, - [BNXT_ULP_CLASS_HID_74dcb] = 1965, - [BNXT_ULP_CLASS_HID_75387] = 1966, - [BNXT_ULP_CLASS_HID_737a7] = 1967, - [BNXT_ULP_CLASS_HID_73e63] = 1968, - [BNXT_ULP_CLASS_HID_2b753] = 1969, - [BNXT_ULP_CLASS_HID_2bd6f] = 1970, - [BNXT_ULP_CLASS_HID_2a10f] = 1971, - [BNXT_ULP_CLASS_HID_2a7cb] = 1972, - [BNXT_ULP_CLASS_HID_2dac7] = 1973, - [BNXT_ULP_CLASS_HID_28457] = 1974, - [BNXT_ULP_CLASS_HID_2c4a3] = 1975, - [BNXT_ULP_CLASS_HID_2cb7f] = 1976, - [BNXT_ULP_CLASS_HID_2a383] = 1977, - [BNXT_ULP_CLASS_HID_2aa5f] = 1978, - [BNXT_ULP_CLASS_HID_28e7f] = 1979, - [BNXT_ULP_CLASS_HID_2943b] = 1980, - [BNXT_ULP_CLASS_HID_2c737] = 1981, - [BNXT_ULP_CLASS_HID_2cdf3] = 1982, - [BNXT_ULP_CLASS_HID_2b193] = 1983, - [BNXT_ULP_CLASS_HID_2b7af] = 1984, - [BNXT_ULP_CLASS_HID_6b267] = 1985, - [BNXT_ULP_CLASS_HID_6b823] = 1986, - [BNXT_ULP_CLASS_HID_69cc3] = 1987, - [BNXT_ULP_CLASS_HID_6a29f] = 1988, - [BNXT_ULP_CLASS_HID_6d59b] = 1989, - [BNXT_ULP_CLASS_HID_6dc57] = 1990, - [BNXT_ULP_CLASS_HID_6c077] = 1991, - [BNXT_ULP_CLASS_HID_6c633] = 1992, - [BNXT_ULP_CLASS_HID_69f57] = 1993, - [BNXT_ULP_CLASS_HID_6a513] = 1994, - [BNXT_ULP_CLASS_HID_68933] = 1995, - [BNXT_ULP_CLASS_HID_68fcf] = 1996, - [BNXT_ULP_CLASS_HID_6c2cb] = 1997, - [BNXT_ULP_CLASS_HID_6c887] = 1998, - [BNXT_ULP_CLASS_HID_6aca7] = 1999, - [BNXT_ULP_CLASS_HID_6b363] = 2000, - [BNXT_ULP_CLASS_HID_3cd53] = 2001, - [BNXT_ULP_CLASS_HID_3d36f] = 2002, - [BNXT_ULP_CLASS_HID_3b70f] = 2003, - [BNXT_ULP_CLASS_HID_3bdcb] = 2004, - [BNXT_ULP_CLASS_HID_3939b] = 2005, - [BNXT_ULP_CLASS_HID_39a57] = 2006, - [BNXT_ULP_CLASS_HID_3daa3] = 2007, - [BNXT_ULP_CLASS_HID_38433] = 2008, - [BNXT_ULP_CLASS_HID_3b983] = 2009, - [BNXT_ULP_CLASS_HID_3c05f] = 2010, - [BNXT_ULP_CLASS_HID_3a47f] = 2011, - [BNXT_ULP_CLASS_HID_3aa3b] = 2012, - [BNXT_ULP_CLASS_HID_380cb] = 2013, - [BNXT_ULP_CLASS_HID_38687] = 2014, - [BNXT_ULP_CLASS_HID_3c793] = 2015, - [BNXT_ULP_CLASS_HID_3cdaf] = 2016, - [BNXT_ULP_CLASS_HID_7c867] = 2017, - [BNXT_ULP_CLASS_HID_7ce23] = 2018, - [BNXT_ULP_CLASS_HID_7b2c3] = 2019, - [BNXT_ULP_CLASS_HID_7b89f] = 2020, - [BNXT_ULP_CLASS_HID_78eaf] = 2021, - [BNXT_ULP_CLASS_HID_7956b] = 2022, - [BNXT_ULP_CLASS_HID_7d677] = 2023, - [BNXT_ULP_CLASS_HID_7dc33] = 2024, - [BNXT_ULP_CLASS_HID_7b557] = 2025, - [BNXT_ULP_CLASS_HID_7bb13] = 2026, - [BNXT_ULP_CLASS_HID_79f33] = 2027, - [BNXT_ULP_CLASS_HID_7a5cf] = 2028, - [BNXT_ULP_CLASS_HID_7d8cb] = 2029, - [BNXT_ULP_CLASS_HID_7825b] = 2030, - [BNXT_ULP_CLASS_HID_7c2a7] = 2031, - [BNXT_ULP_CLASS_HID_7c963] = 2032, - [BNXT_ULP_CLASS_HID_8b4b] = 2033, - [BNXT_ULP_CLASS_HID_9177] = 2034, - [BNXT_ULP_CLASS_HID_d263] = 2035, - [BNXT_ULP_CLASS_HID_d82f] = 2036, - [BNXT_ULP_CLASS_HID_aedf] = 2037, - [BNXT_ULP_CLASS_HID_b49b] = 2038, - [BNXT_ULP_CLASS_HID_98bb] = 2039, - [BNXT_ULP_CLASS_HID_9f67] = 2040, - [BNXT_ULP_CLASS_HID_4867f] = 2041, - [BNXT_ULP_CLASS_HID_48c3b] = 2042, - [BNXT_ULP_CLASS_HID_4cd17] = 2043, - [BNXT_ULP_CLASS_HID_4d3d3] = 2044, - [BNXT_ULP_CLASS_HID_4a983] = 2045, - [BNXT_ULP_CLASS_HID_4b04f] = 2046, - [BNXT_ULP_CLASS_HID_4946f] = 2047, - [BNXT_ULP_CLASS_HID_49a2b] = 2048, - [BNXT_ULP_CLASS_HID_1a14b] = 2049, - [BNXT_ULP_CLASS_HID_1a777] = 2050, - [BNXT_ULP_CLASS_HID_18b17] = 2051, - [BNXT_ULP_CLASS_HID_191d3] = 2052, - [BNXT_ULP_CLASS_HID_1c4df] = 2053, - [BNXT_ULP_CLASS_HID_1ca9b] = 2054, - [BNXT_ULP_CLASS_HID_1aebb] = 2055, - [BNXT_ULP_CLASS_HID_1b567] = 2056, - [BNXT_ULP_CLASS_HID_59c7f] = 2057, - [BNXT_ULP_CLASS_HID_5a23b] = 2058, - [BNXT_ULP_CLASS_HID_586db] = 2059, - [BNXT_ULP_CLASS_HID_58c87] = 2060, - [BNXT_ULP_CLASS_HID_5bf83] = 2061, - [BNXT_ULP_CLASS_HID_5c64f] = 2062, - [BNXT_ULP_CLASS_HID_5aa6f] = 2063, - [BNXT_ULP_CLASS_HID_5b02b] = 2064, - [BNXT_ULP_CLASS_HID_d0cb] = 2065, - [BNXT_ULP_CLASS_HID_d6f7] = 2066, - [BNXT_ULP_CLASS_HID_d7e3] = 2067, - [BNXT_ULP_CLASS_HID_c153] = 2068, - [BNXT_ULP_CLASS_HID_f45f] = 2069, - [BNXT_ULP_CLASS_HID_fa1b] = 2070, - [BNXT_ULP_CLASS_HID_de3b] = 2071, - [BNXT_ULP_CLASS_HID_e4e7] = 2072, - [BNXT_ULP_CLASS_HID_4cbff] = 2073, - [BNXT_ULP_CLASS_HID_4d1bb] = 2074, - [BNXT_ULP_CLASS_HID_4d297] = 2075, - [BNXT_ULP_CLASS_HID_4d953] = 2076, - [BNXT_ULP_CLASS_HID_4ef03] = 2077, - [BNXT_ULP_CLASS_HID_4f5cf] = 2078, - [BNXT_ULP_CLASS_HID_4d9ef] = 2079, - [BNXT_ULP_CLASS_HID_4dfab] = 2080, - [BNXT_ULP_CLASS_HID_1e6cb] = 2081, - [BNXT_ULP_CLASS_HID_1ecf7] = 2082, - [BNXT_ULP_CLASS_HID_1d097] = 2083, - [BNXT_ULP_CLASS_HID_1d753] = 2084, - [BNXT_ULP_CLASS_HID_1ca5f] = 2085, - [BNXT_ULP_CLASS_HID_1d01b] = 2086, - [BNXT_ULP_CLASS_HID_1f43b] = 2087, - [BNXT_ULP_CLASS_HID_1fae7] = 2088, - [BNXT_ULP_CLASS_HID_5e1ff] = 2089, - [BNXT_ULP_CLASS_HID_5e7bb] = 2090, - [BNXT_ULP_CLASS_HID_5cc5b] = 2091, - [BNXT_ULP_CLASS_HID_5d207] = 2092, - [BNXT_ULP_CLASS_HID_5c503] = 2093, - [BNXT_ULP_CLASS_HID_5cbcf] = 2094, - [BNXT_ULP_CLASS_HID_5efef] = 2095, - [BNXT_ULP_CLASS_HID_5f5ab] = 2096, - [BNXT_ULP_CLASS_HID_ad8b] = 2097, - [BNXT_ULP_CLASS_HID_b3b7] = 2098, - [BNXT_ULP_CLASS_HID_f4a3] = 2099, - [BNXT_ULP_CLASS_HID_fb6f] = 2100, - [BNXT_ULP_CLASS_HID_b11f] = 2101, - [BNXT_ULP_CLASS_HID_b7db] = 2102, - [BNXT_ULP_CLASS_HID_bbfb] = 2103, - [BNXT_ULP_CLASS_HID_a1a7] = 2104, - [BNXT_ULP_CLASS_HID_4a8bf] = 2105, - [BNXT_ULP_CLASS_HID_4af7b] = 2106, - [BNXT_ULP_CLASS_HID_4f057] = 2107, - [BNXT_ULP_CLASS_HID_4f613] = 2108, - [BNXT_ULP_CLASS_HID_4acc3] = 2109, - [BNXT_ULP_CLASS_HID_4b28f] = 2110, - [BNXT_ULP_CLASS_HID_4b6af] = 2111, - [BNXT_ULP_CLASS_HID_4bd6b] = 2112, - [BNXT_ULP_CLASS_HID_1a38b] = 2113, - [BNXT_ULP_CLASS_HID_1a9b7] = 2114, - [BNXT_ULP_CLASS_HID_1ae57] = 2115, - [BNXT_ULP_CLASS_HID_1b413] = 2116, - [BNXT_ULP_CLASS_HID_1e71f] = 2117, - [BNXT_ULP_CLASS_HID_1eddb] = 2118, - [BNXT_ULP_CLASS_HID_1b1fb] = 2119, - [BNXT_ULP_CLASS_HID_1b7a7] = 2120, - [BNXT_ULP_CLASS_HID_5bebf] = 2121, - [BNXT_ULP_CLASS_HID_5a57b] = 2122, - [BNXT_ULP_CLASS_HID_5a91b] = 2123, - [BNXT_ULP_CLASS_HID_5afc7] = 2124, - [BNXT_ULP_CLASS_HID_5e2c3] = 2125, - [BNXT_ULP_CLASS_HID_5e88f] = 2126, - [BNXT_ULP_CLASS_HID_5acaf] = 2127, - [BNXT_ULP_CLASS_HID_5b36b] = 2128, - [BNXT_ULP_CLASS_HID_f30b] = 2129, - [BNXT_ULP_CLASS_HID_f937] = 2130, - [BNXT_ULP_CLASS_HID_fa23] = 2131, - [BNXT_ULP_CLASS_HID_e393] = 2132, - [BNXT_ULP_CLASS_HID_f69f] = 2133, - [BNXT_ULP_CLASS_HID_fd5b] = 2134, - [BNXT_ULP_CLASS_HID_e17b] = 2135, - [BNXT_ULP_CLASS_HID_e727] = 2136, - [BNXT_ULP_CLASS_HID_4ee3f] = 2137, - [BNXT_ULP_CLASS_HID_4f4fb] = 2138, - [BNXT_ULP_CLASS_HID_4f5d7] = 2139, - [BNXT_ULP_CLASS_HID_4fb93] = 2140, - [BNXT_ULP_CLASS_HID_4f243] = 2141, - [BNXT_ULP_CLASS_HID_4f80f] = 2142, - [BNXT_ULP_CLASS_HID_4fc2f] = 2143, - [BNXT_ULP_CLASS_HID_4e2eb] = 2144, - [BNXT_ULP_CLASS_HID_1e90b] = 2145, - [BNXT_ULP_CLASS_HID_1ef37] = 2146, - [BNXT_ULP_CLASS_HID_1f3d7] = 2147, - [BNXT_ULP_CLASS_HID_1f993] = 2148, - [BNXT_ULP_CLASS_HID_1ec9f] = 2149, - [BNXT_ULP_CLASS_HID_1f35b] = 2150, - [BNXT_ULP_CLASS_HID_1f77b] = 2151, - [BNXT_ULP_CLASS_HID_1fd27] = 2152, - [BNXT_ULP_CLASS_HID_5e43f] = 2153, - [BNXT_ULP_CLASS_HID_5eafb] = 2154, - [BNXT_ULP_CLASS_HID_5ee9b] = 2155, - [BNXT_ULP_CLASS_HID_5f547] = 2156, - [BNXT_ULP_CLASS_HID_5e843] = 2157, - [BNXT_ULP_CLASS_HID_5ee0f] = 2158, - [BNXT_ULP_CLASS_HID_5f22f] = 2159, - [BNXT_ULP_CLASS_HID_5f8eb] = 2160, - [BNXT_ULP_CLASS_HID_2579] = 2161, - [BNXT_ULP_CLASS_HID_2bb5] = 2162, - [BNXT_ULP_CLASS_HID_4591] = 2163, - [BNXT_ULP_CLASS_HID_4bad] = 2164, - [BNXT_ULP_CLASS_HID_2561] = 2165, - [BNXT_ULP_CLASS_HID_2bad] = 2166, - [BNXT_ULP_CLASS_HID_5bdd] = 2167, - [BNXT_ULP_CLASS_HID_054d] = 2168, - [BNXT_ULP_CLASS_HID_257b] = 2169, - [BNXT_ULP_CLASS_HID_2bb7] = 2170, - [BNXT_ULP_CLASS_HID_0fd7] = 2171, - [BNXT_ULP_CLASS_HID_1613] = 2172, - [BNXT_ULP_CLASS_HID_48ef] = 2173, - [BNXT_ULP_CLASS_HID_4f2b] = 2174, - [BNXT_ULP_CLASS_HID_334b] = 2175, - [BNXT_ULP_CLASS_HID_3987] = 2176, - [BNXT_ULP_CLASS_HID_122b] = 2177, - [BNXT_ULP_CLASS_HID_1867] = 2178, - [BNXT_ULP_CLASS_HID_5973] = 2179, - [BNXT_ULP_CLASS_HID_02c3] = 2180, - [BNXT_ULP_CLASS_HID_35df] = 2181, - [BNXT_ULP_CLASS_HID_3c1b] = 2182, - [BNXT_ULP_CLASS_HID_203b] = 2183, - [BNXT_ULP_CLASS_HID_2677] = 2184, - [BNXT_ULP_CLASS_HID_2563] = 2185, - [BNXT_ULP_CLASS_HID_2baf] = 2186, - [BNXT_ULP_CLASS_HID_0fcf] = 2187, - [BNXT_ULP_CLASS_HID_160b] = 2188, - [BNXT_ULP_CLASS_HID_48f7] = 2189, - [BNXT_ULP_CLASS_HID_4f33] = 2190, - [BNXT_ULP_CLASS_HID_3353] = 2191, - [BNXT_ULP_CLASS_HID_399f] = 2192, - [BNXT_ULP_CLASS_HID_42097] = 2193, - [BNXT_ULP_CLASS_HID_426d3] = 2194, - [BNXT_ULP_CLASS_HID_40af3] = 2195, - [BNXT_ULP_CLASS_HID_4113f] = 2196, - [BNXT_ULP_CLASS_HID_4443b] = 2197, - [BNXT_ULP_CLASS_HID_44a67] = 2198, - [BNXT_ULP_CLASS_HID_42e87] = 2199, - [BNXT_ULP_CLASS_HID_434c3] = 2200, - [BNXT_ULP_CLASS_HID_2559] = 2201, - [BNXT_ULP_CLASS_HID_2b95] = 2202, - [BNXT_ULP_CLASS_HID_45b1] = 2203, - [BNXT_ULP_CLASS_HID_4b8d] = 2204, - [BNXT_ULP_CLASS_HID_2541] = 2205, - [BNXT_ULP_CLASS_HID_2b8d] = 2206, - [BNXT_ULP_CLASS_HID_5bfd] = 2207, - [BNXT_ULP_CLASS_HID_056d] = 2208, - [BNXT_ULP_CLASS_HID_2539] = 2209, - [BNXT_ULP_CLASS_HID_2bf5] = 2210, - [BNXT_ULP_CLASS_HID_45d1] = 2211, - [BNXT_ULP_CLASS_HID_4bed] = 2212, - [BNXT_ULP_CLASS_HID_2521] = 2213, - [BNXT_ULP_CLASS_HID_2bed] = 2214, - [BNXT_ULP_CLASS_HID_5b9d] = 2215, - [BNXT_ULP_CLASS_HID_050d] = 2216, - [BNXT_ULP_CLASS_HID_255b] = 2217, - [BNXT_ULP_CLASS_HID_2b97] = 2218, - [BNXT_ULP_CLASS_HID_0ff7] = 2219, - [BNXT_ULP_CLASS_HID_1633] = 2220, - [BNXT_ULP_CLASS_HID_48cf] = 2221, - [BNXT_ULP_CLASS_HID_4f0b] = 2222, - [BNXT_ULP_CLASS_HID_336b] = 2223, - [BNXT_ULP_CLASS_HID_39a7] = 2224, - [BNXT_ULP_CLASS_HID_120b] = 2225, - [BNXT_ULP_CLASS_HID_1847] = 2226, - [BNXT_ULP_CLASS_HID_5953] = 2227, - [BNXT_ULP_CLASS_HID_02e3] = 2228, - [BNXT_ULP_CLASS_HID_35ff] = 2229, - [BNXT_ULP_CLASS_HID_3c3b] = 2230, - [BNXT_ULP_CLASS_HID_201b] = 2231, - [BNXT_ULP_CLASS_HID_2657] = 2232, - [BNXT_ULP_CLASS_HID_2543] = 2233, - [BNXT_ULP_CLASS_HID_2b8f] = 2234, - [BNXT_ULP_CLASS_HID_0fef] = 2235, - [BNXT_ULP_CLASS_HID_162b] = 2236, - [BNXT_ULP_CLASS_HID_48d7] = 2237, - [BNXT_ULP_CLASS_HID_4f13] = 2238, - [BNXT_ULP_CLASS_HID_3373] = 2239, - [BNXT_ULP_CLASS_HID_39bf] = 2240, - [BNXT_ULP_CLASS_HID_420b7] = 2241, - [BNXT_ULP_CLASS_HID_426f3] = 2242, - [BNXT_ULP_CLASS_HID_40ad3] = 2243, - [BNXT_ULP_CLASS_HID_4111f] = 2244, - [BNXT_ULP_CLASS_HID_4441b] = 2245, - [BNXT_ULP_CLASS_HID_44a47] = 2246, - [BNXT_ULP_CLASS_HID_42ea7] = 2247, - [BNXT_ULP_CLASS_HID_434e3] = 2248, - [BNXT_ULP_CLASS_HID_253b] = 2249, - [BNXT_ULP_CLASS_HID_2bf7] = 2250, - [BNXT_ULP_CLASS_HID_0f97] = 2251, - [BNXT_ULP_CLASS_HID_1653] = 2252, - [BNXT_ULP_CLASS_HID_48af] = 2253, - [BNXT_ULP_CLASS_HID_4f6b] = 2254, - [BNXT_ULP_CLASS_HID_330b] = 2255, - [BNXT_ULP_CLASS_HID_39c7] = 2256, - [BNXT_ULP_CLASS_HID_126b] = 2257, - [BNXT_ULP_CLASS_HID_1827] = 2258, - [BNXT_ULP_CLASS_HID_5933] = 2259, - [BNXT_ULP_CLASS_HID_0283] = 2260, - [BNXT_ULP_CLASS_HID_359f] = 2261, - [BNXT_ULP_CLASS_HID_3c5b] = 2262, - [BNXT_ULP_CLASS_HID_207b] = 2263, - [BNXT_ULP_CLASS_HID_2637] = 2264, - [BNXT_ULP_CLASS_HID_2523] = 2265, - [BNXT_ULP_CLASS_HID_2bef] = 2266, - [BNXT_ULP_CLASS_HID_0f8f] = 2267, - [BNXT_ULP_CLASS_HID_164b] = 2268, - [BNXT_ULP_CLASS_HID_48b7] = 2269, - [BNXT_ULP_CLASS_HID_4f73] = 2270, - [BNXT_ULP_CLASS_HID_3313] = 2271, - [BNXT_ULP_CLASS_HID_39df] = 2272, - [BNXT_ULP_CLASS_HID_420d7] = 2273, - [BNXT_ULP_CLASS_HID_42693] = 2274, - [BNXT_ULP_CLASS_HID_40ab3] = 2275, - [BNXT_ULP_CLASS_HID_4117f] = 2276, - [BNXT_ULP_CLASS_HID_4447b] = 2277, - [BNXT_ULP_CLASS_HID_44a27] = 2278, - [BNXT_ULP_CLASS_HID_42ec7] = 2279, - [BNXT_ULP_CLASS_HID_43483] = 2280, - [BNXT_ULP_CLASS_HID_4156d] = 2281, - [BNXT_ULP_CLASS_HID_41b29] = 2282, - [BNXT_ULP_CLASS_HID_52b6d] = 2283, - [BNXT_ULP_CLASS_HID_53129] = 2284, - [BNXT_ULP_CLASS_HID_478a] = 2285, - [BNXT_ULP_CLASS_HID_03a6] = 2286, - [BNXT_ULP_CLASS_HID_4dce] = 2287, - [BNXT_ULP_CLASS_HID_09ea] = 2288, - [BNXT_ULP_CLASS_HID_08fe] = 2289, - [BNXT_ULP_CLASS_HID_23ce] = 2290, - [BNXT_ULP_CLASS_HID_0e02] = 2291, - [BNXT_ULP_CLASS_HID_2912] = 2292, - [BNXT_ULP_CLASS_HID_3e2a] = 2293, - [BNXT_ULP_CLASS_HID_593a] = 2294, - [BNXT_ULP_CLASS_HID_246e] = 2295, - [BNXT_ULP_CLASS_HID_5f7e] = 2296, - [BNXT_ULP_CLASS_HID_5e52] = 2297, - [BNXT_ULP_CLASS_HID_1a6e] = 2298, - [BNXT_ULP_CLASS_HID_4796] = 2299, - [BNXT_ULP_CLASS_HID_03b2] = 2300, - [BNXT_ULP_CLASS_HID_4163a] = 2301, - [BNXT_ULP_CLASS_HID_4310a] = 2302, - [BNXT_ULP_CLASS_HID_41c7e] = 2303, - [BNXT_ULP_CLASS_HID_4374e] = 2304, - [BNXT_ULP_CLASS_HID_42f8e] = 2305, - [BNXT_ULP_CLASS_HID_4469e] = 2306, - [BNXT_ULP_CLASS_HID_455c2] = 2307, - [BNXT_ULP_CLASS_HID_411ee] = 2308, - [BNXT_ULP_CLASS_HID_44b76] = 2309, - [BNXT_ULP_CLASS_HID_40692] = 2310, - [BNXT_ULP_CLASS_HID_415c6] = 2311, - [BNXT_ULP_CLASS_HID_40cd6] = 2312, - [BNXT_ULP_CLASS_HID_42516] = 2313, - [BNXT_ULP_CLASS_HID_45ce6] = 2314, - [BNXT_ULP_CLASS_HID_42b2a] = 2315, - [BNXT_ULP_CLASS_HID_4423a] = 2316, - [BNXT_ULP_CLASS_HID_229d8] = 2317, - [BNXT_ULP_CLASS_HID_240c8] = 2318, - [BNXT_ULP_CLASS_HID_22f14] = 2319, - [BNXT_ULP_CLASS_HID_24604] = 2320, - [BNXT_ULP_CLASS_HID_23374] = 2321, - [BNXT_ULP_CLASS_HID_22a64] = 2322, - [BNXT_ULP_CLASS_HID_238b0] = 2323, - [BNXT_ULP_CLASS_HID_253a0] = 2324, - [BNXT_ULP_CLASS_HID_24dac] = 2325, - [BNXT_ULP_CLASS_HID_20990] = 2326, - [BNXT_ULP_CLASS_HID_214dc] = 2327, - [BNXT_ULP_CLASS_HID_20fcc] = 2328, - [BNXT_ULP_CLASS_HID_257c8] = 2329, - [BNXT_ULP_CLASS_HID_2132c] = 2330, - [BNXT_ULP_CLASS_HID_25d04] = 2331, - [BNXT_ULP_CLASS_HID_21968] = 2332, - [BNXT_ULP_CLASS_HID_234e8] = 2333, - [BNXT_ULP_CLASS_HID_22f98] = 2334, - [BNXT_ULP_CLASS_HID_23a24] = 2335, - [BNXT_ULP_CLASS_HID_255d4] = 2336, - [BNXT_ULP_CLASS_HID_21e04] = 2337, - [BNXT_ULP_CLASS_HID_23934] = 2338, - [BNXT_ULP_CLASS_HID_20440] = 2339, - [BNXT_ULP_CLASS_HID_23f70] = 2340, - [BNXT_ULP_CLASS_HID_2597c] = 2341, - [BNXT_ULP_CLASS_HID_214a0] = 2342, - [BNXT_ULP_CLASS_HID_25eb8] = 2343, - [BNXT_ULP_CLASS_HID_21a9c] = 2344, - [BNXT_ULP_CLASS_HID_22298] = 2345, - [BNXT_ULP_CLASS_HID_25d88] = 2346, - [BNXT_ULP_CLASS_HID_228d4] = 2347, - [BNXT_ULP_CLASS_HID_243c4] = 2348, - [BNXT_ULP_CLASS_HID_6220c] = 2349, - [BNXT_ULP_CLASS_HID_65d3c] = 2350, - [BNXT_ULP_CLASS_HID_62848] = 2351, - [BNXT_ULP_CLASS_HID_64378] = 2352, - [BNXT_ULP_CLASS_HID_60fa8] = 2353, - [BNXT_ULP_CLASS_HID_62758] = 2354, - [BNXT_ULP_CLASS_HID_635e4] = 2355, - [BNXT_ULP_CLASS_HID_62c94] = 2356, - [BNXT_ULP_CLASS_HID_646e0] = 2357, - [BNXT_ULP_CLASS_HID_602c4] = 2358, - [BNXT_ULP_CLASS_HID_61110] = 2359, - [BNXT_ULP_CLASS_HID_60800] = 2360, - [BNXT_ULP_CLASS_HID_6503c] = 2361, - [BNXT_ULP_CLASS_HID_64b2c] = 2362, - [BNXT_ULP_CLASS_HID_65678] = 2363, - [BNXT_ULP_CLASS_HID_6125c] = 2364, - [BNXT_ULP_CLASS_HID_631dc] = 2365, - [BNXT_ULP_CLASS_HID_628cc] = 2366, - [BNXT_ULP_CLASS_HID_63718] = 2367, - [BNXT_ULP_CLASS_HID_62e08] = 2368, - [BNXT_ULP_CLASS_HID_61b78] = 2369, - [BNXT_ULP_CLASS_HID_63268] = 2370, - [BNXT_ULP_CLASS_HID_600b4] = 2371, - [BNXT_ULP_CLASS_HID_63ba4] = 2372, - [BNXT_ULP_CLASS_HID_655b0] = 2373, - [BNXT_ULP_CLASS_HID_61194] = 2374, - [BNXT_ULP_CLASS_HID_65bec] = 2375, - [BNXT_ULP_CLASS_HID_617d0] = 2376, - [BNXT_ULP_CLASS_HID_63fcc] = 2377, - [BNXT_ULP_CLASS_HID_656fc] = 2378, - [BNXT_ULP_CLASS_HID_62508] = 2379, - [BNXT_ULP_CLASS_HID_65c38] = 2380, - [BNXT_ULP_CLASS_HID_86e0] = 2381, - [BNXT_ULP_CLASS_HID_a1f0] = 2382, - [BNXT_ULP_CLASS_HID_8c2c] = 2383, - [BNXT_ULP_CLASS_HID_a73c] = 2384, - [BNXT_ULP_CLASS_HID_904c] = 2385, - [BNXT_ULP_CLASS_HID_8b5c] = 2386, - [BNXT_ULP_CLASS_HID_9988] = 2387, - [BNXT_ULP_CLASS_HID_b098] = 2388, - [BNXT_ULP_CLASS_HID_aa94] = 2389, - [BNXT_ULP_CLASS_HID_c264] = 2390, - [BNXT_ULP_CLASS_HID_d0d0] = 2391, - [BNXT_ULP_CLASS_HID_cba0] = 2392, - [BNXT_ULP_CLASS_HID_b4f0] = 2393, - [BNXT_ULP_CLASS_HID_afc0] = 2394, - [BNXT_ULP_CLASS_HID_ba3c] = 2395, - [BNXT_ULP_CLASS_HID_d50c] = 2396, - [BNXT_ULP_CLASS_HID_48334] = 2397, - [BNXT_ULP_CLASS_HID_4ba04] = 2398, - [BNXT_ULP_CLASS_HID_48970] = 2399, - [BNXT_ULP_CLASS_HID_4a040] = 2400, - [BNXT_ULP_CLASS_HID_4c84c] = 2401, - [BNXT_ULP_CLASS_HID_48460] = 2402, - [BNXT_ULP_CLASS_HID_492dc] = 2403, - [BNXT_ULP_CLASS_HID_48dac] = 2404, - [BNXT_ULP_CLASS_HID_4a7d8] = 2405, - [BNXT_ULP_CLASS_HID_4dea8] = 2406, - [BNXT_ULP_CLASS_HID_4ade4] = 2407, - [BNXT_ULP_CLASS_HID_4c4f4] = 2408, - [BNXT_ULP_CLASS_HID_4b104] = 2409, - [BNXT_ULP_CLASS_HID_4a814] = 2410, - [BNXT_ULP_CLASS_HID_4b740] = 2411, - [BNXT_ULP_CLASS_HID_4ae50] = 2412, - [BNXT_ULP_CLASS_HID_1bce0] = 2413, - [BNXT_ULP_CLASS_HID_1d7f0] = 2414, - [BNXT_ULP_CLASS_HID_1a22c] = 2415, - [BNXT_ULP_CLASS_HID_1dd3c] = 2416, - [BNXT_ULP_CLASS_HID_1864c] = 2417, - [BNXT_ULP_CLASS_HID_1a15c] = 2418, - [BNXT_ULP_CLASS_HID_18f88] = 2419, - [BNXT_ULP_CLASS_HID_1a698] = 2420, - [BNXT_ULP_CLASS_HID_1c094] = 2421, - [BNXT_ULP_CLASS_HID_19ca8] = 2422, - [BNXT_ULP_CLASS_HID_1c6d0] = 2423, - [BNXT_ULP_CLASS_HID_182f4] = 2424, - [BNXT_ULP_CLASS_HID_1aaf0] = 2425, - [BNXT_ULP_CLASS_HID_1c5c0] = 2426, - [BNXT_ULP_CLASS_HID_1d03c] = 2427, - [BNXT_ULP_CLASS_HID_1cb0c] = 2428, - [BNXT_ULP_CLASS_HID_5b934] = 2429, - [BNXT_ULP_CLASS_HID_5d004] = 2430, - [BNXT_ULP_CLASS_HID_5bf70] = 2431, - [BNXT_ULP_CLASS_HID_5d640] = 2432, - [BNXT_ULP_CLASS_HID_58290] = 2433, - [BNXT_ULP_CLASS_HID_5ba60] = 2434, - [BNXT_ULP_CLASS_HID_588dc] = 2435, - [BNXT_ULP_CLASS_HID_5a3ac] = 2436, - [BNXT_ULP_CLASS_HID_5ddd8] = 2437, - [BNXT_ULP_CLASS_HID_599fc] = 2438, - [BNXT_ULP_CLASS_HID_5c3e4] = 2439, - [BNXT_ULP_CLASS_HID_59f38] = 2440, - [BNXT_ULP_CLASS_HID_5a704] = 2441, - [BNXT_ULP_CLASS_HID_5de14] = 2442, - [BNXT_ULP_CLASS_HID_5ad40] = 2443, - [BNXT_ULP_CLASS_HID_5c450] = 2444, - [BNXT_ULP_CLASS_HID_47aa] = 2445, - [BNXT_ULP_CLASS_HID_0386] = 2446, - [BNXT_ULP_CLASS_HID_4dee] = 2447, - [BNXT_ULP_CLASS_HID_09ca] = 2448, - [BNXT_ULP_CLASS_HID_08de] = 2449, - [BNXT_ULP_CLASS_HID_23ee] = 2450, - [BNXT_ULP_CLASS_HID_0e22] = 2451, - [BNXT_ULP_CLASS_HID_2932] = 2452, - [BNXT_ULP_CLASS_HID_3e0a] = 2453, - [BNXT_ULP_CLASS_HID_591a] = 2454, - [BNXT_ULP_CLASS_HID_244e] = 2455, - [BNXT_ULP_CLASS_HID_5f5e] = 2456, - [BNXT_ULP_CLASS_HID_5e72] = 2457, - [BNXT_ULP_CLASS_HID_1a4e] = 2458, - [BNXT_ULP_CLASS_HID_47b6] = 2459, - [BNXT_ULP_CLASS_HID_0392] = 2460, - [BNXT_ULP_CLASS_HID_5dc2] = 2461, - [BNXT_ULP_CLASS_HID_191e] = 2462, - [BNXT_ULP_CLASS_HID_4306] = 2463, - [BNXT_ULP_CLASS_HID_1f62] = 2464, - [BNXT_ULP_CLASS_HID_1e76] = 2465, - [BNXT_ULP_CLASS_HID_3906] = 2466, - [BNXT_ULP_CLASS_HID_07ba] = 2467, - [BNXT_ULP_CLASS_HID_3f4a] = 2468, - [BNXT_ULP_CLASS_HID_37a2] = 2469, - [BNXT_ULP_CLASS_HID_2eb2] = 2470, - [BNXT_ULP_CLASS_HID_3de6] = 2471, - [BNXT_ULP_CLASS_HID_54f6] = 2472, - [BNXT_ULP_CLASS_HID_578a] = 2473, - [BNXT_ULP_CLASS_HID_13e6] = 2474, - [BNXT_ULP_CLASS_HID_5dce] = 2475, - [BNXT_ULP_CLASS_HID_192a] = 2476, - [BNXT_ULP_CLASS_HID_440f6] = 2477, - [BNXT_ULP_CLASS_HID_41cd2] = 2478, - [BNXT_ULP_CLASS_HID_4463a] = 2479, - [BNXT_ULP_CLASS_HID_40216] = 2480, - [BNXT_ULP_CLASS_HID_4052a] = 2481, - [BNXT_ULP_CLASS_HID_43c3a] = 2482, - [BNXT_ULP_CLASS_HID_40b6e] = 2483, - [BNXT_ULP_CLASS_HID_4227e] = 2484, - [BNXT_ULP_CLASS_HID_43b56] = 2485, - [BNXT_ULP_CLASS_HID_45266] = 2486, - [BNXT_ULP_CLASS_HID_4209a] = 2487, - [BNXT_ULP_CLASS_HID_45baa] = 2488, - [BNXT_ULP_CLASS_HID_45abe] = 2489, - [BNXT_ULP_CLASS_HID_4169a] = 2490, - [BNXT_ULP_CLASS_HID_44082] = 2491, - [BNXT_ULP_CLASS_HID_41cde] = 2492, - [BNXT_ULP_CLASS_HID_4560e] = 2493, - [BNXT_ULP_CLASS_HID_4126a] = 2494, - [BNXT_ULP_CLASS_HID_45c52] = 2495, - [BNXT_ULP_CLASS_HID_41bae] = 2496, - [BNXT_ULP_CLASS_HID_41b42] = 2497, - [BNXT_ULP_CLASS_HID_43252] = 2498, - [BNXT_ULP_CLASS_HID_40086] = 2499, - [BNXT_ULP_CLASS_HID_43b96] = 2500, - [BNXT_ULP_CLASS_HID_430ee] = 2501, - [BNXT_ULP_CLASS_HID_42bfe] = 2502, - [BNXT_ULP_CLASS_HID_43632] = 2503, - [BNXT_ULP_CLASS_HID_451c2] = 2504, - [BNXT_ULP_CLASS_HID_450d6] = 2505, - [BNXT_ULP_CLASS_HID_44be6] = 2506, - [BNXT_ULP_CLASS_HID_4561a] = 2507, - [BNXT_ULP_CLASS_HID_41276] = 2508, - [BNXT_ULP_CLASS_HID_4161a] = 2509, - [BNXT_ULP_CLASS_HID_4312a] = 2510, - [BNXT_ULP_CLASS_HID_41c5e] = 2511, - [BNXT_ULP_CLASS_HID_4376e] = 2512, - [BNXT_ULP_CLASS_HID_42fae] = 2513, - [BNXT_ULP_CLASS_HID_446be] = 2514, - [BNXT_ULP_CLASS_HID_455e2] = 2515, - [BNXT_ULP_CLASS_HID_411ce] = 2516, - [BNXT_ULP_CLASS_HID_44b56] = 2517, - [BNXT_ULP_CLASS_HID_406b2] = 2518, - [BNXT_ULP_CLASS_HID_415e6] = 2519, - [BNXT_ULP_CLASS_HID_40cf6] = 2520, - [BNXT_ULP_CLASS_HID_42536] = 2521, - [BNXT_ULP_CLASS_HID_45cc6] = 2522, - [BNXT_ULP_CLASS_HID_42b0a] = 2523, - [BNXT_ULP_CLASS_HID_4421a] = 2524, - [BNXT_ULP_CLASS_HID_6221a] = 2525, - [BNXT_ULP_CLASS_HID_65d2a] = 2526, - [BNXT_ULP_CLASS_HID_6285e] = 2527, - [BNXT_ULP_CLASS_HID_6436e] = 2528, - [BNXT_ULP_CLASS_HID_61cfa] = 2529, - [BNXT_ULP_CLASS_HID_6378a] = 2530, - [BNXT_ULP_CLASS_HID_6023e] = 2531, - [BNXT_ULP_CLASS_HID_63dce] = 2532, - [BNXT_ULP_CLASS_HID_63ba2] = 2533, - [BNXT_ULP_CLASS_HID_652b2] = 2534, - [BNXT_ULP_CLASS_HID_621e6] = 2535, - [BNXT_ULP_CLASS_HID_658f6] = 2536, - [BNXT_ULP_CLASS_HID_61202] = 2537, - [BNXT_ULP_CLASS_HID_60d12] = 2538, - [BNXT_ULP_CLASS_HID_61846] = 2539, - [BNXT_ULP_CLASS_HID_63356] = 2540, - [BNXT_ULP_CLASS_HID_50c1a] = 2541, - [BNXT_ULP_CLASS_HID_5272a] = 2542, - [BNXT_ULP_CLASS_HID_5325e] = 2543, - [BNXT_ULP_CLASS_HID_52d6e] = 2544, - [BNXT_ULP_CLASS_HID_545ae] = 2545, - [BNXT_ULP_CLASS_HID_5018a] = 2546, - [BNXT_ULP_CLASS_HID_54be2] = 2547, - [BNXT_ULP_CLASS_HID_507ce] = 2548, - [BNXT_ULP_CLASS_HID_505a2] = 2549, - [BNXT_ULP_CLASS_HID_53cb2] = 2550, - [BNXT_ULP_CLASS_HID_50be6] = 2551, - [BNXT_ULP_CLASS_HID_522f6] = 2552, - [BNXT_ULP_CLASS_HID_55b36] = 2553, - [BNXT_ULP_CLASS_HID_51712] = 2554, - [BNXT_ULP_CLASS_HID_5410a] = 2555, - [BNXT_ULP_CLASS_HID_51d56] = 2556, - [BNXT_ULP_CLASS_HID_7581a] = 2557, - [BNXT_ULP_CLASS_HID_71466] = 2558, - [BNXT_ULP_CLASS_HID_75e5e] = 2559, - [BNXT_ULP_CLASS_HID_71dba] = 2560, - [BNXT_ULP_CLASS_HID_732fa] = 2561, - [BNXT_ULP_CLASS_HID_72d8a] = 2562, - [BNXT_ULP_CLASS_HID_7383e] = 2563, - [BNXT_ULP_CLASS_HID_753ce] = 2564, - [BNXT_ULP_CLASS_HID_751a2] = 2565, - [BNXT_ULP_CLASS_HID_748b2] = 2566, - [BNXT_ULP_CLASS_HID_757e6] = 2567, - [BNXT_ULP_CLASS_HID_713c2] = 2568, - [BNXT_ULP_CLASS_HID_70802] = 2569, - [BNXT_ULP_CLASS_HID_72312] = 2570, - [BNXT_ULP_CLASS_HID_70e46] = 2571, - [BNXT_ULP_CLASS_HID_72956] = 2572, - [BNXT_ULP_CLASS_HID_47ca] = 2573, - [BNXT_ULP_CLASS_HID_03e6] = 2574, - [BNXT_ULP_CLASS_HID_4d8e] = 2575, - [BNXT_ULP_CLASS_HID_09aa] = 2576, - [BNXT_ULP_CLASS_HID_08be] = 2577, - [BNXT_ULP_CLASS_HID_238e] = 2578, - [BNXT_ULP_CLASS_HID_0e42] = 2579, - [BNXT_ULP_CLASS_HID_2952] = 2580, - [BNXT_ULP_CLASS_HID_3e6a] = 2581, - [BNXT_ULP_CLASS_HID_597a] = 2582, - [BNXT_ULP_CLASS_HID_242e] = 2583, - [BNXT_ULP_CLASS_HID_5f3e] = 2584, - [BNXT_ULP_CLASS_HID_5e12] = 2585, - [BNXT_ULP_CLASS_HID_1a2e] = 2586, - [BNXT_ULP_CLASS_HID_47d6] = 2587, - [BNXT_ULP_CLASS_HID_03f2] = 2588, - [BNXT_ULP_CLASS_HID_5da2] = 2589, - [BNXT_ULP_CLASS_HID_197e] = 2590, - [BNXT_ULP_CLASS_HID_4366] = 2591, - [BNXT_ULP_CLASS_HID_1f02] = 2592, - [BNXT_ULP_CLASS_HID_1e16] = 2593, - [BNXT_ULP_CLASS_HID_3966] = 2594, - [BNXT_ULP_CLASS_HID_07da] = 2595, - [BNXT_ULP_CLASS_HID_3f2a] = 2596, - [BNXT_ULP_CLASS_HID_37c2] = 2597, - [BNXT_ULP_CLASS_HID_2ed2] = 2598, - [BNXT_ULP_CLASS_HID_3d86] = 2599, - [BNXT_ULP_CLASS_HID_5496] = 2600, - [BNXT_ULP_CLASS_HID_57ea] = 2601, - [BNXT_ULP_CLASS_HID_1386] = 2602, - [BNXT_ULP_CLASS_HID_5dae] = 2603, - [BNXT_ULP_CLASS_HID_194a] = 2604, - [BNXT_ULP_CLASS_HID_44096] = 2605, - [BNXT_ULP_CLASS_HID_41cb2] = 2606, - [BNXT_ULP_CLASS_HID_4465a] = 2607, - [BNXT_ULP_CLASS_HID_40276] = 2608, - [BNXT_ULP_CLASS_HID_4054a] = 2609, - [BNXT_ULP_CLASS_HID_43c5a] = 2610, - [BNXT_ULP_CLASS_HID_40b0e] = 2611, - [BNXT_ULP_CLASS_HID_4221e] = 2612, - [BNXT_ULP_CLASS_HID_43b36] = 2613, - [BNXT_ULP_CLASS_HID_45206] = 2614, - [BNXT_ULP_CLASS_HID_420fa] = 2615, - [BNXT_ULP_CLASS_HID_45bca] = 2616, - [BNXT_ULP_CLASS_HID_45ade] = 2617, - [BNXT_ULP_CLASS_HID_416fa] = 2618, - [BNXT_ULP_CLASS_HID_440e2] = 2619, - [BNXT_ULP_CLASS_HID_41cbe] = 2620, - [BNXT_ULP_CLASS_HID_4566e] = 2621, - [BNXT_ULP_CLASS_HID_4120a] = 2622, - [BNXT_ULP_CLASS_HID_45c32] = 2623, - [BNXT_ULP_CLASS_HID_41bce] = 2624, - [BNXT_ULP_CLASS_HID_41b22] = 2625, - [BNXT_ULP_CLASS_HID_43232] = 2626, - [BNXT_ULP_CLASS_HID_400e6] = 2627, - [BNXT_ULP_CLASS_HID_43bf6] = 2628, - [BNXT_ULP_CLASS_HID_4308e] = 2629, - [BNXT_ULP_CLASS_HID_42b9e] = 2630, - [BNXT_ULP_CLASS_HID_43652] = 2631, - [BNXT_ULP_CLASS_HID_451a2] = 2632, - [BNXT_ULP_CLASS_HID_450b6] = 2633, - [BNXT_ULP_CLASS_HID_44b86] = 2634, - [BNXT_ULP_CLASS_HID_4567a] = 2635, - [BNXT_ULP_CLASS_HID_41216] = 2636, - [BNXT_ULP_CLASS_HID_4167a] = 2637, - [BNXT_ULP_CLASS_HID_4314a] = 2638, - [BNXT_ULP_CLASS_HID_41c3e] = 2639, - [BNXT_ULP_CLASS_HID_4370e] = 2640, - [BNXT_ULP_CLASS_HID_42fce] = 2641, - [BNXT_ULP_CLASS_HID_446de] = 2642, - [BNXT_ULP_CLASS_HID_45582] = 2643, - [BNXT_ULP_CLASS_HID_411ae] = 2644, - [BNXT_ULP_CLASS_HID_44b36] = 2645, - [BNXT_ULP_CLASS_HID_406d2] = 2646, - [BNXT_ULP_CLASS_HID_41586] = 2647, - [BNXT_ULP_CLASS_HID_40c96] = 2648, - [BNXT_ULP_CLASS_HID_42556] = 2649, - [BNXT_ULP_CLASS_HID_45ca6] = 2650, - [BNXT_ULP_CLASS_HID_42b6a] = 2651, - [BNXT_ULP_CLASS_HID_4427a] = 2652, - [BNXT_ULP_CLASS_HID_6227a] = 2653, - [BNXT_ULP_CLASS_HID_65d4a] = 2654, - [BNXT_ULP_CLASS_HID_6283e] = 2655, - [BNXT_ULP_CLASS_HID_6430e] = 2656, - [BNXT_ULP_CLASS_HID_61c9a] = 2657, - [BNXT_ULP_CLASS_HID_637ea] = 2658, - [BNXT_ULP_CLASS_HID_6025e] = 2659, - [BNXT_ULP_CLASS_HID_63dae] = 2660, - [BNXT_ULP_CLASS_HID_63bc2] = 2661, - [BNXT_ULP_CLASS_HID_652d2] = 2662, - [BNXT_ULP_CLASS_HID_62186] = 2663, - [BNXT_ULP_CLASS_HID_65896] = 2664, - [BNXT_ULP_CLASS_HID_61262] = 2665, - [BNXT_ULP_CLASS_HID_60d72] = 2666, - [BNXT_ULP_CLASS_HID_61826] = 2667, - [BNXT_ULP_CLASS_HID_63336] = 2668, - [BNXT_ULP_CLASS_HID_50c7a] = 2669, - [BNXT_ULP_CLASS_HID_5274a] = 2670, - [BNXT_ULP_CLASS_HID_5323e] = 2671, - [BNXT_ULP_CLASS_HID_52d0e] = 2672, - [BNXT_ULP_CLASS_HID_545ce] = 2673, - [BNXT_ULP_CLASS_HID_501ea] = 2674, - [BNXT_ULP_CLASS_HID_54b82] = 2675, - [BNXT_ULP_CLASS_HID_507ae] = 2676, - [BNXT_ULP_CLASS_HID_505c2] = 2677, - [BNXT_ULP_CLASS_HID_53cd2] = 2678, - [BNXT_ULP_CLASS_HID_50b86] = 2679, - [BNXT_ULP_CLASS_HID_52296] = 2680, - [BNXT_ULP_CLASS_HID_55b56] = 2681, - [BNXT_ULP_CLASS_HID_51772] = 2682, - [BNXT_ULP_CLASS_HID_5416a] = 2683, - [BNXT_ULP_CLASS_HID_51d36] = 2684, - [BNXT_ULP_CLASS_HID_7587a] = 2685, - [BNXT_ULP_CLASS_HID_71406] = 2686, - [BNXT_ULP_CLASS_HID_75e3e] = 2687, - [BNXT_ULP_CLASS_HID_71dda] = 2688, - [BNXT_ULP_CLASS_HID_7329a] = 2689, - [BNXT_ULP_CLASS_HID_72dea] = 2690, - [BNXT_ULP_CLASS_HID_7385e] = 2691, - [BNXT_ULP_CLASS_HID_753ae] = 2692, - [BNXT_ULP_CLASS_HID_751c2] = 2693, - [BNXT_ULP_CLASS_HID_748d2] = 2694, - [BNXT_ULP_CLASS_HID_75786] = 2695, - [BNXT_ULP_CLASS_HID_713a2] = 2696, - [BNXT_ULP_CLASS_HID_70862] = 2697, - [BNXT_ULP_CLASS_HID_72372] = 2698, - [BNXT_ULP_CLASS_HID_70e26] = 2699, - [BNXT_ULP_CLASS_HID_72936] = 2700, - [BNXT_ULP_CLASS_HID_229b8] = 2701, - [BNXT_ULP_CLASS_HID_240a8] = 2702, - [BNXT_ULP_CLASS_HID_22f74] = 2703, - [BNXT_ULP_CLASS_HID_24664] = 2704, - [BNXT_ULP_CLASS_HID_23314] = 2705, - [BNXT_ULP_CLASS_HID_22a04] = 2706, - [BNXT_ULP_CLASS_HID_238d0] = 2707, - [BNXT_ULP_CLASS_HID_253c0] = 2708, - [BNXT_ULP_CLASS_HID_24dcc] = 2709, - [BNXT_ULP_CLASS_HID_209f0] = 2710, - [BNXT_ULP_CLASS_HID_214bc] = 2711, - [BNXT_ULP_CLASS_HID_20fac] = 2712, - [BNXT_ULP_CLASS_HID_257a8] = 2713, - [BNXT_ULP_CLASS_HID_2134c] = 2714, - [BNXT_ULP_CLASS_HID_25d64] = 2715, - [BNXT_ULP_CLASS_HID_21908] = 2716, - [BNXT_ULP_CLASS_HID_23488] = 2717, - [BNXT_ULP_CLASS_HID_22ff8] = 2718, - [BNXT_ULP_CLASS_HID_23a44] = 2719, - [BNXT_ULP_CLASS_HID_255b4] = 2720, - [BNXT_ULP_CLASS_HID_21e64] = 2721, - [BNXT_ULP_CLASS_HID_23954] = 2722, - [BNXT_ULP_CLASS_HID_20420] = 2723, - [BNXT_ULP_CLASS_HID_23f10] = 2724, - [BNXT_ULP_CLASS_HID_2591c] = 2725, - [BNXT_ULP_CLASS_HID_214c0] = 2726, - [BNXT_ULP_CLASS_HID_25ed8] = 2727, - [BNXT_ULP_CLASS_HID_21afc] = 2728, - [BNXT_ULP_CLASS_HID_222f8] = 2729, - [BNXT_ULP_CLASS_HID_25de8] = 2730, - [BNXT_ULP_CLASS_HID_228b4] = 2731, - [BNXT_ULP_CLASS_HID_243a4] = 2732, - [BNXT_ULP_CLASS_HID_6226c] = 2733, - [BNXT_ULP_CLASS_HID_65d5c] = 2734, - [BNXT_ULP_CLASS_HID_62828] = 2735, - [BNXT_ULP_CLASS_HID_64318] = 2736, - [BNXT_ULP_CLASS_HID_60fc8] = 2737, - [BNXT_ULP_CLASS_HID_62738] = 2738, - [BNXT_ULP_CLASS_HID_63584] = 2739, - [BNXT_ULP_CLASS_HID_62cf4] = 2740, - [BNXT_ULP_CLASS_HID_64680] = 2741, - [BNXT_ULP_CLASS_HID_602a4] = 2742, - [BNXT_ULP_CLASS_HID_61170] = 2743, - [BNXT_ULP_CLASS_HID_60860] = 2744, - [BNXT_ULP_CLASS_HID_6505c] = 2745, - [BNXT_ULP_CLASS_HID_64b4c] = 2746, - [BNXT_ULP_CLASS_HID_65618] = 2747, - [BNXT_ULP_CLASS_HID_6123c] = 2748, - [BNXT_ULP_CLASS_HID_631bc] = 2749, - [BNXT_ULP_CLASS_HID_628ac] = 2750, - [BNXT_ULP_CLASS_HID_63778] = 2751, - [BNXT_ULP_CLASS_HID_62e68] = 2752, - [BNXT_ULP_CLASS_HID_61b18] = 2753, - [BNXT_ULP_CLASS_HID_63208] = 2754, - [BNXT_ULP_CLASS_HID_600d4] = 2755, - [BNXT_ULP_CLASS_HID_63bc4] = 2756, - [BNXT_ULP_CLASS_HID_655d0] = 2757, - [BNXT_ULP_CLASS_HID_611f4] = 2758, - [BNXT_ULP_CLASS_HID_65b8c] = 2759, - [BNXT_ULP_CLASS_HID_617b0] = 2760, - [BNXT_ULP_CLASS_HID_63fac] = 2761, - [BNXT_ULP_CLASS_HID_6569c] = 2762, - [BNXT_ULP_CLASS_HID_62568] = 2763, - [BNXT_ULP_CLASS_HID_65c58] = 2764, - [BNXT_ULP_CLASS_HID_35fb8] = 2765, - [BNXT_ULP_CLASS_HID_31b5c] = 2766, - [BNXT_ULP_CLASS_HID_34574] = 2767, - [BNXT_ULP_CLASS_HID_30118] = 2768, - [BNXT_ULP_CLASS_HID_32914] = 2769, - [BNXT_ULP_CLASS_HID_34004] = 2770, - [BNXT_ULP_CLASS_HID_32ed0] = 2771, - [BNXT_ULP_CLASS_HID_349c0] = 2772, - [BNXT_ULP_CLASS_HID_30480] = 2773, - [BNXT_ULP_CLASS_HID_33ff0] = 2774, - [BNXT_ULP_CLASS_HID_30abc] = 2775, - [BNXT_ULP_CLASS_HID_325ac] = 2776, - [BNXT_ULP_CLASS_HID_34da8] = 2777, - [BNXT_ULP_CLASS_HID_3094c] = 2778, - [BNXT_ULP_CLASS_HID_31418] = 2779, - [BNXT_ULP_CLASS_HID_30f08] = 2780, - [BNXT_ULP_CLASS_HID_32a88] = 2781, - [BNXT_ULP_CLASS_HID_345f8] = 2782, - [BNXT_ULP_CLASS_HID_35044] = 2783, - [BNXT_ULP_CLASS_HID_34bb4] = 2784, - [BNXT_ULP_CLASS_HID_33464] = 2785, - [BNXT_ULP_CLASS_HID_32f54] = 2786, - [BNXT_ULP_CLASS_HID_33a20] = 2787, - [BNXT_ULP_CLASS_HID_35510] = 2788, - [BNXT_ULP_CLASS_HID_313d0] = 2789, - [BNXT_ULP_CLASS_HID_30ac0] = 2790, - [BNXT_ULP_CLASS_HID_3198c] = 2791, - [BNXT_ULP_CLASS_HID_330fc] = 2792, - [BNXT_ULP_CLASS_HID_358f8] = 2793, - [BNXT_ULP_CLASS_HID_3149c] = 2794, - [BNXT_ULP_CLASS_HID_35eb4] = 2795, - [BNXT_ULP_CLASS_HID_31a58] = 2796, - [BNXT_ULP_CLASS_HID_7586c] = 2797, - [BNXT_ULP_CLASS_HID_71410] = 2798, - [BNXT_ULP_CLASS_HID_75e28] = 2799, - [BNXT_ULP_CLASS_HID_71dcc] = 2800, - [BNXT_ULP_CLASS_HID_725c8] = 2801, - [BNXT_ULP_CLASS_HID_75d38] = 2802, - [BNXT_ULP_CLASS_HID_72b84] = 2803, - [BNXT_ULP_CLASS_HID_742f4] = 2804, - [BNXT_ULP_CLASS_HID_701b4] = 2805, - [BNXT_ULP_CLASS_HID_738a4] = 2806, - [BNXT_ULP_CLASS_HID_70770] = 2807, - [BNXT_ULP_CLASS_HID_73e60] = 2808, - [BNXT_ULP_CLASS_HID_7465c] = 2809, - [BNXT_ULP_CLASS_HID_70200] = 2810, - [BNXT_ULP_CLASS_HID_710cc] = 2811, - [BNXT_ULP_CLASS_HID_7083c] = 2812, - [BNXT_ULP_CLASS_HID_727bc] = 2813, - [BNXT_ULP_CLASS_HID_75eac] = 2814, - [BNXT_ULP_CLASS_HID_72d78] = 2815, - [BNXT_ULP_CLASS_HID_74468] = 2816, - [BNXT_ULP_CLASS_HID_73118] = 2817, - [BNXT_ULP_CLASS_HID_72808] = 2818, - [BNXT_ULP_CLASS_HID_736d4] = 2819, - [BNXT_ULP_CLASS_HID_751c4] = 2820, - [BNXT_ULP_CLASS_HID_74bd0] = 2821, - [BNXT_ULP_CLASS_HID_707f4] = 2822, - [BNXT_ULP_CLASS_HID_71240] = 2823, - [BNXT_ULP_CLASS_HID_70db0] = 2824, - [BNXT_ULP_CLASS_HID_755ac] = 2825, - [BNXT_ULP_CLASS_HID_71150] = 2826, - [BNXT_ULP_CLASS_HID_75b68] = 2827, - [BNXT_ULP_CLASS_HID_7170c] = 2828, - [BNXT_ULP_CLASS_HID_2d2b8] = 2829, - [BNXT_ULP_CLASS_HID_2cda8] = 2830, - [BNXT_ULP_CLASS_HID_2d874] = 2831, - [BNXT_ULP_CLASS_HID_29418] = 2832, - [BNXT_ULP_CLASS_HID_2bc14] = 2833, - [BNXT_ULP_CLASS_HID_2d704] = 2834, - [BNXT_ULP_CLASS_HID_2a5d0] = 2835, - [BNXT_ULP_CLASS_HID_2dcc0] = 2836, - [BNXT_ULP_CLASS_HID_29b80] = 2837, - [BNXT_ULP_CLASS_HID_2b2f0] = 2838, - [BNXT_ULP_CLASS_HID_281bc] = 2839, - [BNXT_ULP_CLASS_HID_2b8ac] = 2840, - [BNXT_ULP_CLASS_HID_2c0a8] = 2841, - [BNXT_ULP_CLASS_HID_29c4c] = 2842, - [BNXT_ULP_CLASS_HID_2c664] = 2843, - [BNXT_ULP_CLASS_HID_28208] = 2844, - [BNXT_ULP_CLASS_HID_2a188] = 2845, - [BNXT_ULP_CLASS_HID_2d8f8] = 2846, - [BNXT_ULP_CLASS_HID_2a744] = 2847, - [BNXT_ULP_CLASS_HID_2deb4] = 2848, - [BNXT_ULP_CLASS_HID_28b64] = 2849, - [BNXT_ULP_CLASS_HID_2a254] = 2850, - [BNXT_ULP_CLASS_HID_2b120] = 2851, - [BNXT_ULP_CLASS_HID_2a810] = 2852, - [BNXT_ULP_CLASS_HID_2c21c] = 2853, - [BNXT_ULP_CLASS_HID_281c0] = 2854, - [BNXT_ULP_CLASS_HID_2cbd8] = 2855, - [BNXT_ULP_CLASS_HID_287fc] = 2856, - [BNXT_ULP_CLASS_HID_2aff8] = 2857, - [BNXT_ULP_CLASS_HID_2c6e8] = 2858, - [BNXT_ULP_CLASS_HID_2d5b4] = 2859, - [BNXT_ULP_CLASS_HID_29158] = 2860, - [BNXT_ULP_CLASS_HID_6af6c] = 2861, - [BNXT_ULP_CLASS_HID_6c65c] = 2862, - [BNXT_ULP_CLASS_HID_6d528] = 2863, - [BNXT_ULP_CLASS_HID_690cc] = 2864, - [BNXT_ULP_CLASS_HID_6b8c8] = 2865, - [BNXT_ULP_CLASS_HID_6d038] = 2866, - [BNXT_ULP_CLASS_HID_6be84] = 2867, - [BNXT_ULP_CLASS_HID_6d9f4] = 2868, - [BNXT_ULP_CLASS_HID_694b4] = 2869, - [BNXT_ULP_CLASS_HID_68fa4] = 2870, - [BNXT_ULP_CLASS_HID_69a70] = 2871, - [BNXT_ULP_CLASS_HID_6b560] = 2872, - [BNXT_ULP_CLASS_HID_6dd5c] = 2873, - [BNXT_ULP_CLASS_HID_69900] = 2874, - [BNXT_ULP_CLASS_HID_6c318] = 2875, - [BNXT_ULP_CLASS_HID_69f3c] = 2876, - [BNXT_ULP_CLASS_HID_6babc] = 2877, - [BNXT_ULP_CLASS_HID_6d5ac] = 2878, - [BNXT_ULP_CLASS_HID_6a078] = 2879, - [BNXT_ULP_CLASS_HID_6db68] = 2880, - [BNXT_ULP_CLASS_HID_68418] = 2881, - [BNXT_ULP_CLASS_HID_6bf08] = 2882, - [BNXT_ULP_CLASS_HID_68dd4] = 2883, - [BNXT_ULP_CLASS_HID_6a4c4] = 2884, - [BNXT_ULP_CLASS_HID_6ded0] = 2885, - [BNXT_ULP_CLASS_HID_69af4] = 2886, - [BNXT_ULP_CLASS_HID_6c48c] = 2887, - [BNXT_ULP_CLASS_HID_680b0] = 2888, - [BNXT_ULP_CLASS_HID_6a8ac] = 2889, - [BNXT_ULP_CLASS_HID_6c39c] = 2890, - [BNXT_ULP_CLASS_HID_6ae68] = 2891, - [BNXT_ULP_CLASS_HID_6c958] = 2892, - [BNXT_ULP_CLASS_HID_3c8b8] = 2893, - [BNXT_ULP_CLASS_HID_3845c] = 2894, - [BNXT_ULP_CLASS_HID_39328] = 2895, - [BNXT_ULP_CLASS_HID_38a18] = 2896, - [BNXT_ULP_CLASS_HID_3d214] = 2897, - [BNXT_ULP_CLASS_HID_3cd04] = 2898, - [BNXT_ULP_CLASS_HID_3dbd0] = 2899, - [BNXT_ULP_CLASS_HID_397f4] = 2900, - [BNXT_ULP_CLASS_HID_3b180] = 2901, - [BNXT_ULP_CLASS_HID_3a8f0] = 2902, - [BNXT_ULP_CLASS_HID_3b7bc] = 2903, - [BNXT_ULP_CLASS_HID_3aeac] = 2904, - [BNXT_ULP_CLASS_HID_39b5c] = 2905, - [BNXT_ULP_CLASS_HID_3b24c] = 2906, - [BNXT_ULP_CLASS_HID_38118] = 2907, - [BNXT_ULP_CLASS_HID_3b808] = 2908, - [BNXT_ULP_CLASS_HID_3d788] = 2909, - [BNXT_ULP_CLASS_HID_393ac] = 2910, - [BNXT_ULP_CLASS_HID_3dd44] = 2911, - [BNXT_ULP_CLASS_HID_39968] = 2912, - [BNXT_ULP_CLASS_HID_3a164] = 2913, - [BNXT_ULP_CLASS_HID_3d854] = 2914, - [BNXT_ULP_CLASS_HID_3a720] = 2915, - [BNXT_ULP_CLASS_HID_3de10] = 2916, - [BNXT_ULP_CLASS_HID_39cd0] = 2917, - [BNXT_ULP_CLASS_HID_3b7c0] = 2918, - [BNXT_ULP_CLASS_HID_3828c] = 2919, - [BNXT_ULP_CLASS_HID_3bdfc] = 2920, - [BNXT_ULP_CLASS_HID_3c5f8] = 2921, - [BNXT_ULP_CLASS_HID_3819c] = 2922, - [BNXT_ULP_CLASS_HID_3cbb4] = 2923, - [BNXT_ULP_CLASS_HID_38758] = 2924, - [BNXT_ULP_CLASS_HID_7c56c] = 2925, - [BNXT_ULP_CLASS_HID_78110] = 2926, - [BNXT_ULP_CLASS_HID_7cb28] = 2927, - [BNXT_ULP_CLASS_HID_786cc] = 2928, - [BNXT_ULP_CLASS_HID_7aec8] = 2929, - [BNXT_ULP_CLASS_HID_7c638] = 2930, - [BNXT_ULP_CLASS_HID_7d484] = 2931, - [BNXT_ULP_CLASS_HID_790a8] = 2932, - [BNXT_ULP_CLASS_HID_78ab4] = 2933, - [BNXT_ULP_CLASS_HID_7a5a4] = 2934, - [BNXT_ULP_CLASS_HID_7b070] = 2935, - [BNXT_ULP_CLASS_HID_7ab60] = 2936, - [BNXT_ULP_CLASS_HID_79410] = 2937, - [BNXT_ULP_CLASS_HID_78f00] = 2938, - [BNXT_ULP_CLASS_HID_79dcc] = 2939, - [BNXT_ULP_CLASS_HID_7b53c] = 2940, - [BNXT_ULP_CLASS_HID_7d0bc] = 2941, - [BNXT_ULP_CLASS_HID_7cbac] = 2942, - [BNXT_ULP_CLASS_HID_7d678] = 2943, - [BNXT_ULP_CLASS_HID_7921c] = 2944, - [BNXT_ULP_CLASS_HID_7ba18] = 2945, - [BNXT_ULP_CLASS_HID_7d508] = 2946, - [BNXT_ULP_CLASS_HID_7a3d4] = 2947, - [BNXT_ULP_CLASS_HID_7dac4] = 2948, - [BNXT_ULP_CLASS_HID_79984] = 2949, - [BNXT_ULP_CLASS_HID_7b0f4] = 2950, - [BNXT_ULP_CLASS_HID_79f40] = 2951, - [BNXT_ULP_CLASS_HID_7b6b0] = 2952, - [BNXT_ULP_CLASS_HID_7deac] = 2953, - [BNXT_ULP_CLASS_HID_79a50] = 2954, - [BNXT_ULP_CLASS_HID_7c468] = 2955, - [BNXT_ULP_CLASS_HID_7800c] = 2956, - [BNXT_ULP_CLASS_HID_86c0] = 2957, - [BNXT_ULP_CLASS_HID_a1d0] = 2958, - [BNXT_ULP_CLASS_HID_8c0c] = 2959, - [BNXT_ULP_CLASS_HID_a71c] = 2960, - [BNXT_ULP_CLASS_HID_906c] = 2961, - [BNXT_ULP_CLASS_HID_8b7c] = 2962, - [BNXT_ULP_CLASS_HID_99a8] = 2963, - [BNXT_ULP_CLASS_HID_b0b8] = 2964, - [BNXT_ULP_CLASS_HID_aab4] = 2965, - [BNXT_ULP_CLASS_HID_c244] = 2966, - [BNXT_ULP_CLASS_HID_d0f0] = 2967, - [BNXT_ULP_CLASS_HID_cb80] = 2968, - [BNXT_ULP_CLASS_HID_b4d0] = 2969, - [BNXT_ULP_CLASS_HID_afe0] = 2970, - [BNXT_ULP_CLASS_HID_ba1c] = 2971, - [BNXT_ULP_CLASS_HID_d52c] = 2972, - [BNXT_ULP_CLASS_HID_48314] = 2973, - [BNXT_ULP_CLASS_HID_4ba24] = 2974, - [BNXT_ULP_CLASS_HID_48950] = 2975, - [BNXT_ULP_CLASS_HID_4a060] = 2976, - [BNXT_ULP_CLASS_HID_4c86c] = 2977, - [BNXT_ULP_CLASS_HID_48440] = 2978, - [BNXT_ULP_CLASS_HID_492fc] = 2979, - [BNXT_ULP_CLASS_HID_48d8c] = 2980, - [BNXT_ULP_CLASS_HID_4a7f8] = 2981, - [BNXT_ULP_CLASS_HID_4de88] = 2982, - [BNXT_ULP_CLASS_HID_4adc4] = 2983, - [BNXT_ULP_CLASS_HID_4c4d4] = 2984, - [BNXT_ULP_CLASS_HID_4b124] = 2985, - [BNXT_ULP_CLASS_HID_4a834] = 2986, - [BNXT_ULP_CLASS_HID_4b760] = 2987, - [BNXT_ULP_CLASS_HID_4ae70] = 2988, - [BNXT_ULP_CLASS_HID_1bcc0] = 2989, - [BNXT_ULP_CLASS_HID_1d7d0] = 2990, - [BNXT_ULP_CLASS_HID_1a20c] = 2991, - [BNXT_ULP_CLASS_HID_1dd1c] = 2992, - [BNXT_ULP_CLASS_HID_1866c] = 2993, - [BNXT_ULP_CLASS_HID_1a17c] = 2994, - [BNXT_ULP_CLASS_HID_18fa8] = 2995, - [BNXT_ULP_CLASS_HID_1a6b8] = 2996, - [BNXT_ULP_CLASS_HID_1c0b4] = 2997, - [BNXT_ULP_CLASS_HID_19c88] = 2998, - [BNXT_ULP_CLASS_HID_1c6f0] = 2999, - [BNXT_ULP_CLASS_HID_182d4] = 3000, - [BNXT_ULP_CLASS_HID_1aad0] = 3001, - [BNXT_ULP_CLASS_HID_1c5e0] = 3002, - [BNXT_ULP_CLASS_HID_1d01c] = 3003, - [BNXT_ULP_CLASS_HID_1cb2c] = 3004, - [BNXT_ULP_CLASS_HID_5b914] = 3005, - [BNXT_ULP_CLASS_HID_5d024] = 3006, - [BNXT_ULP_CLASS_HID_5bf50] = 3007, - [BNXT_ULP_CLASS_HID_5d660] = 3008, - [BNXT_ULP_CLASS_HID_582b0] = 3009, - [BNXT_ULP_CLASS_HID_5ba40] = 3010, - [BNXT_ULP_CLASS_HID_588fc] = 3011, - [BNXT_ULP_CLASS_HID_5a38c] = 3012, - [BNXT_ULP_CLASS_HID_5ddf8] = 3013, - [BNXT_ULP_CLASS_HID_599dc] = 3014, - [BNXT_ULP_CLASS_HID_5c3c4] = 3015, - [BNXT_ULP_CLASS_HID_59f18] = 3016, - [BNXT_ULP_CLASS_HID_5a724] = 3017, - [BNXT_ULP_CLASS_HID_5de34] = 3018, - [BNXT_ULP_CLASS_HID_5ad60] = 3019, - [BNXT_ULP_CLASS_HID_5c470] = 3020, - [BNXT_ULP_CLASS_HID_cd40] = 3021, - [BNXT_ULP_CLASS_HID_e450] = 3022, - [BNXT_ULP_CLASS_HID_f28c] = 3023, - [BNXT_ULP_CLASS_HID_ed9c] = 3024, - [BNXT_ULP_CLASS_HID_d6ec] = 3025, - [BNXT_ULP_CLASS_HID_f1fc] = 3026, - [BNXT_ULP_CLASS_HID_dc28] = 3027, - [BNXT_ULP_CLASS_HID_f738] = 3028, - [BNXT_ULP_CLASS_HID_d134] = 3029, - [BNXT_ULP_CLASS_HID_c8c4] = 3030, - [BNXT_ULP_CLASS_HID_d770] = 3031, - [BNXT_ULP_CLASS_HID_d354] = 3032, - [BNXT_ULP_CLASS_HID_fb50] = 3033, - [BNXT_ULP_CLASS_HID_d260] = 3034, - [BNXT_ULP_CLASS_HID_e09c] = 3035, - [BNXT_ULP_CLASS_HID_dbac] = 3036, - [BNXT_ULP_CLASS_HID_4c994] = 3037, - [BNXT_ULP_CLASS_HID_4e0a4] = 3038, - [BNXT_ULP_CLASS_HID_4cfd0] = 3039, - [BNXT_ULP_CLASS_HID_4e6e0] = 3040, - [BNXT_ULP_CLASS_HID_4d330] = 3041, - [BNXT_ULP_CLASS_HID_4cac0] = 3042, - [BNXT_ULP_CLASS_HID_4d97c] = 3043, - [BNXT_ULP_CLASS_HID_4f00c] = 3044, - [BNXT_ULP_CLASS_HID_4ea78] = 3045, - [BNXT_ULP_CLASS_HID_4c508] = 3046, - [BNXT_ULP_CLASS_HID_4d044] = 3047, - [BNXT_ULP_CLASS_HID_4cb54] = 3048, - [BNXT_ULP_CLASS_HID_4f7a4] = 3049, - [BNXT_ULP_CLASS_HID_4eeb4] = 3050, - [BNXT_ULP_CLASS_HID_4fde0] = 3051, - [BNXT_ULP_CLASS_HID_4d4f0] = 3052, - [BNXT_ULP_CLASS_HID_1e340] = 3053, - [BNXT_ULP_CLASS_HID_1da50] = 3054, - [BNXT_ULP_CLASS_HID_1e88c] = 3055, - [BNXT_ULP_CLASS_HID_1c39c] = 3056, - [BNXT_ULP_CLASS_HID_1ccec] = 3057, - [BNXT_ULP_CLASS_HID_1e7fc] = 3058, - [BNXT_ULP_CLASS_HID_1f228] = 3059, - [BNXT_ULP_CLASS_HID_1ed38] = 3060, - [BNXT_ULP_CLASS_HID_1c734] = 3061, - [BNXT_ULP_CLASS_HID_1c308] = 3062, - [BNXT_ULP_CLASS_HID_1cd70] = 3063, - [BNXT_ULP_CLASS_HID_1c954] = 3064, - [BNXT_ULP_CLASS_HID_1d150] = 3065, - [BNXT_ULP_CLASS_HID_1c860] = 3066, - [BNXT_ULP_CLASS_HID_1d69c] = 3067, - [BNXT_ULP_CLASS_HID_1d2f0] = 3068, - [BNXT_ULP_CLASS_HID_5ff94] = 3069, - [BNXT_ULP_CLASS_HID_5d6a4] = 3070, - [BNXT_ULP_CLASS_HID_5e5d0] = 3071, - [BNXT_ULP_CLASS_HID_5dce0] = 3072, - [BNXT_ULP_CLASS_HID_5c930] = 3073, - [BNXT_ULP_CLASS_HID_5e0c0] = 3074, - [BNXT_ULP_CLASS_HID_5cf7c] = 3075, - [BNXT_ULP_CLASS_HID_5e60c] = 3076, - [BNXT_ULP_CLASS_HID_5c078] = 3077, - [BNXT_ULP_CLASS_HID_5dc5c] = 3078, - [BNXT_ULP_CLASS_HID_5c644] = 3079, - [BNXT_ULP_CLASS_HID_5c598] = 3080, - [BNXT_ULP_CLASS_HID_5eda4] = 3081, - [BNXT_ULP_CLASS_HID_5c4b4] = 3082, - [BNXT_ULP_CLASS_HID_5d3e0] = 3083, - [BNXT_ULP_CLASS_HID_5caf0] = 3084, - [BNXT_ULP_CLASS_HID_ab80] = 3085, - [BNXT_ULP_CLASS_HID_a290] = 3086, - [BNXT_ULP_CLASS_HID_b1cc] = 3087, - [BNXT_ULP_CLASS_HID_a8dc] = 3088, - [BNXT_ULP_CLASS_HID_b52c] = 3089, - [BNXT_ULP_CLASS_HID_ac3c] = 3090, - [BNXT_ULP_CLASS_HID_bb68] = 3091, - [BNXT_ULP_CLASS_HID_b278] = 3092, - [BNXT_ULP_CLASS_HID_ac74] = 3093, - [BNXT_ULP_CLASS_HID_e704] = 3094, - [BNXT_ULP_CLASS_HID_f5b0] = 3095, - [BNXT_ULP_CLASS_HID_b194] = 3096, - [BNXT_ULP_CLASS_HID_b990] = 3097, - [BNXT_ULP_CLASS_HID_f0a0] = 3098, - [BNXT_ULP_CLASS_HID_bfdc] = 3099, - [BNXT_ULP_CLASS_HID_f6ec] = 3100, - [BNXT_ULP_CLASS_HID_4a4d4] = 3101, - [BNXT_ULP_CLASS_HID_4bfe4] = 3102, - [BNXT_ULP_CLASS_HID_4aa10] = 3103, - [BNXT_ULP_CLASS_HID_4a520] = 3104, - [BNXT_ULP_CLASS_HID_4ed2c] = 3105, - [BNXT_ULP_CLASS_HID_4a900] = 3106, - [BNXT_ULP_CLASS_HID_4b7bc] = 3107, - [BNXT_ULP_CLASS_HID_4af4c] = 3108, - [BNXT_ULP_CLASS_HID_4a8b8] = 3109, - [BNXT_ULP_CLASS_HID_4e048] = 3110, - [BNXT_ULP_CLASS_HID_4ae84] = 3111, - [BNXT_ULP_CLASS_HID_4e994] = 3112, - [BNXT_ULP_CLASS_HID_4b2e4] = 3113, - [BNXT_ULP_CLASS_HID_4adf4] = 3114, - [BNXT_ULP_CLASS_HID_4b820] = 3115, - [BNXT_ULP_CLASS_HID_4f330] = 3116, - [BNXT_ULP_CLASS_HID_1a180] = 3117, - [BNXT_ULP_CLASS_HID_1f890] = 3118, - [BNXT_ULP_CLASS_HID_1a7cc] = 3119, - [BNXT_ULP_CLASS_HID_1fedc] = 3120, - [BNXT_ULP_CLASS_HID_1ab2c] = 3121, - [BNXT_ULP_CLASS_HID_1a23c] = 3122, - [BNXT_ULP_CLASS_HID_1b168] = 3123, - [BNXT_ULP_CLASS_HID_1a878] = 3124, - [BNXT_ULP_CLASS_HID_1e274] = 3125, - [BNXT_ULP_CLASS_HID_1be48] = 3126, - [BNXT_ULP_CLASS_HID_1ebb0] = 3127, - [BNXT_ULP_CLASS_HID_1a794] = 3128, - [BNXT_ULP_CLASS_HID_1af90] = 3129, - [BNXT_ULP_CLASS_HID_1e6a0] = 3130, - [BNXT_ULP_CLASS_HID_1f5dc] = 3131, - [BNXT_ULP_CLASS_HID_1b130] = 3132, - [BNXT_ULP_CLASS_HID_5bad4] = 3133, - [BNXT_ULP_CLASS_HID_5f5e4] = 3134, - [BNXT_ULP_CLASS_HID_5a010] = 3135, - [BNXT_ULP_CLASS_HID_5fb20] = 3136, - [BNXT_ULP_CLASS_HID_5a470] = 3137, - [BNXT_ULP_CLASS_HID_5bf00] = 3138, - [BNXT_ULP_CLASS_HID_5adbc] = 3139, - [BNXT_ULP_CLASS_HID_5a54c] = 3140, - [BNXT_ULP_CLASS_HID_5feb8] = 3141, - [BNXT_ULP_CLASS_HID_5ba9c] = 3142, - [BNXT_ULP_CLASS_HID_5e484] = 3143, - [BNXT_ULP_CLASS_HID_5a0d8] = 3144, - [BNXT_ULP_CLASS_HID_5a8e4] = 3145, - [BNXT_ULP_CLASS_HID_5e3f4] = 3146, - [BNXT_ULP_CLASS_HID_5ae20] = 3147, - [BNXT_ULP_CLASS_HID_5e930] = 3148, - [BNXT_ULP_CLASS_HID_ee00] = 3149, - [BNXT_ULP_CLASS_HID_e910] = 3150, - [BNXT_ULP_CLASS_HID_f44c] = 3151, - [BNXT_ULP_CLASS_HID_ef5c] = 3152, - [BNXT_ULP_CLASS_HID_fbac] = 3153, - [BNXT_ULP_CLASS_HID_f2bc] = 3154, - [BNXT_ULP_CLASS_HID_e1e8] = 3155, - [BNXT_ULP_CLASS_HID_f8f8] = 3156, - [BNXT_ULP_CLASS_HID_f2f4] = 3157, - [BNXT_ULP_CLASS_HID_ed84] = 3158, - [BNXT_ULP_CLASS_HID_f830] = 3159, - [BNXT_ULP_CLASS_HID_f414] = 3160, - [BNXT_ULP_CLASS_HID_fc10] = 3161, - [BNXT_ULP_CLASS_HID_f720] = 3162, - [BNXT_ULP_CLASS_HID_e25c] = 3163, - [BNXT_ULP_CLASS_HID_fd6c] = 3164, - [BNXT_ULP_CLASS_HID_4eb54] = 3165, - [BNXT_ULP_CLASS_HID_4e264] = 3166, - [BNXT_ULP_CLASS_HID_4f090] = 3167, - [BNXT_ULP_CLASS_HID_4eba0] = 3168, - [BNXT_ULP_CLASS_HID_4f4f0] = 3169, - [BNXT_ULP_CLASS_HID_4ef80] = 3170, - [BNXT_ULP_CLASS_HID_4fa3c] = 3171, - [BNXT_ULP_CLASS_HID_4f5cc] = 3172, - [BNXT_ULP_CLASS_HID_4ef38] = 3173, - [BNXT_ULP_CLASS_HID_4e6c8] = 3174, - [BNXT_ULP_CLASS_HID_4f504] = 3175, - [BNXT_ULP_CLASS_HID_4f158] = 3176, - [BNXT_ULP_CLASS_HID_4f964] = 3177, - [BNXT_ULP_CLASS_HID_4f074] = 3178, - [BNXT_ULP_CLASS_HID_4fea0] = 3179, - [BNXT_ULP_CLASS_HID_4f9b0] = 3180, - [BNXT_ULP_CLASS_HID_1e400] = 3181, - [BNXT_ULP_CLASS_HID_1ff10] = 3182, - [BNXT_ULP_CLASS_HID_1ea4c] = 3183, - [BNXT_ULP_CLASS_HID_1e55c] = 3184, - [BNXT_ULP_CLASS_HID_1f1ac] = 3185, - [BNXT_ULP_CLASS_HID_1e8bc] = 3186, - [BNXT_ULP_CLASS_HID_1f7e8] = 3187, - [BNXT_ULP_CLASS_HID_1eef8] = 3188, - [BNXT_ULP_CLASS_HID_1e8f4] = 3189, - [BNXT_ULP_CLASS_HID_1e4c8] = 3190, - [BNXT_ULP_CLASS_HID_1f304] = 3191, - [BNXT_ULP_CLASS_HID_1ea14] = 3192, - [BNXT_ULP_CLASS_HID_1f210] = 3193, - [BNXT_ULP_CLASS_HID_1ed20] = 3194, - [BNXT_ULP_CLASS_HID_1f85c] = 3195, - [BNXT_ULP_CLASS_HID_1f7b0] = 3196, - [BNXT_ULP_CLASS_HID_5e154] = 3197, - [BNXT_ULP_CLASS_HID_5f864] = 3198, - [BNXT_ULP_CLASS_HID_5e690] = 3199, - [BNXT_ULP_CLASS_HID_5e1a0] = 3200, - [BNXT_ULP_CLASS_HID_5eaf0] = 3201, - [BNXT_ULP_CLASS_HID_5e580] = 3202, - [BNXT_ULP_CLASS_HID_5f03c] = 3203, - [BNXT_ULP_CLASS_HID_5ebcc] = 3204, - [BNXT_ULP_CLASS_HID_5e538] = 3205, - [BNXT_ULP_CLASS_HID_5e11c] = 3206, - [BNXT_ULP_CLASS_HID_5eb04] = 3207, - [BNXT_ULP_CLASS_HID_5e758] = 3208, - [BNXT_ULP_CLASS_HID_5ef64] = 3209, - [BNXT_ULP_CLASS_HID_5e674] = 3210, - [BNXT_ULP_CLASS_HID_5f4a0] = 3211, - [BNXT_ULP_CLASS_HID_5f084] = 3212, - [BNXT_ULP_CLASS_HID_22998] = 3213, - [BNXT_ULP_CLASS_HID_24088] = 3214, - [BNXT_ULP_CLASS_HID_22f54] = 3215, - [BNXT_ULP_CLASS_HID_24644] = 3216, - [BNXT_ULP_CLASS_HID_23334] = 3217, - [BNXT_ULP_CLASS_HID_22a24] = 3218, - [BNXT_ULP_CLASS_HID_238f0] = 3219, - [BNXT_ULP_CLASS_HID_253e0] = 3220, - [BNXT_ULP_CLASS_HID_24dec] = 3221, - [BNXT_ULP_CLASS_HID_209d0] = 3222, - [BNXT_ULP_CLASS_HID_2149c] = 3223, - [BNXT_ULP_CLASS_HID_20f8c] = 3224, - [BNXT_ULP_CLASS_HID_25788] = 3225, - [BNXT_ULP_CLASS_HID_2136c] = 3226, - [BNXT_ULP_CLASS_HID_25d44] = 3227, - [BNXT_ULP_CLASS_HID_21928] = 3228, - [BNXT_ULP_CLASS_HID_234a8] = 3229, - [BNXT_ULP_CLASS_HID_22fd8] = 3230, - [BNXT_ULP_CLASS_HID_23a64] = 3231, - [BNXT_ULP_CLASS_HID_25594] = 3232, - [BNXT_ULP_CLASS_HID_21e44] = 3233, - [BNXT_ULP_CLASS_HID_23974] = 3234, - [BNXT_ULP_CLASS_HID_20400] = 3235, - [BNXT_ULP_CLASS_HID_23f30] = 3236, - [BNXT_ULP_CLASS_HID_2593c] = 3237, - [BNXT_ULP_CLASS_HID_214e0] = 3238, - [BNXT_ULP_CLASS_HID_25ef8] = 3239, - [BNXT_ULP_CLASS_HID_21adc] = 3240, - [BNXT_ULP_CLASS_HID_222d8] = 3241, - [BNXT_ULP_CLASS_HID_25dc8] = 3242, - [BNXT_ULP_CLASS_HID_22894] = 3243, - [BNXT_ULP_CLASS_HID_24384] = 3244, - [BNXT_ULP_CLASS_HID_6224c] = 3245, - [BNXT_ULP_CLASS_HID_65d7c] = 3246, - [BNXT_ULP_CLASS_HID_62808] = 3247, - [BNXT_ULP_CLASS_HID_64338] = 3248, - [BNXT_ULP_CLASS_HID_60fe8] = 3249, - [BNXT_ULP_CLASS_HID_62718] = 3250, - [BNXT_ULP_CLASS_HID_635a4] = 3251, - [BNXT_ULP_CLASS_HID_62cd4] = 3252, - [BNXT_ULP_CLASS_HID_646a0] = 3253, - [BNXT_ULP_CLASS_HID_60284] = 3254, - [BNXT_ULP_CLASS_HID_61150] = 3255, - [BNXT_ULP_CLASS_HID_60840] = 3256, - [BNXT_ULP_CLASS_HID_6507c] = 3257, - [BNXT_ULP_CLASS_HID_64b6c] = 3258, - [BNXT_ULP_CLASS_HID_65638] = 3259, - [BNXT_ULP_CLASS_HID_6121c] = 3260, - [BNXT_ULP_CLASS_HID_6319c] = 3261, - [BNXT_ULP_CLASS_HID_6288c] = 3262, - [BNXT_ULP_CLASS_HID_63758] = 3263, - [BNXT_ULP_CLASS_HID_62e48] = 3264, - [BNXT_ULP_CLASS_HID_61b38] = 3265, - [BNXT_ULP_CLASS_HID_63228] = 3266, - [BNXT_ULP_CLASS_HID_600f4] = 3267, - [BNXT_ULP_CLASS_HID_63be4] = 3268, - [BNXT_ULP_CLASS_HID_655f0] = 3269, - [BNXT_ULP_CLASS_HID_611d4] = 3270, - [BNXT_ULP_CLASS_HID_65bac] = 3271, - [BNXT_ULP_CLASS_HID_61790] = 3272, - [BNXT_ULP_CLASS_HID_63f8c] = 3273, - [BNXT_ULP_CLASS_HID_656bc] = 3274, - [BNXT_ULP_CLASS_HID_62548] = 3275, - [BNXT_ULP_CLASS_HID_65c78] = 3276, - [BNXT_ULP_CLASS_HID_35f98] = 3277, - [BNXT_ULP_CLASS_HID_31b7c] = 3278, - [BNXT_ULP_CLASS_HID_34554] = 3279, - [BNXT_ULP_CLASS_HID_30138] = 3280, - [BNXT_ULP_CLASS_HID_32934] = 3281, - [BNXT_ULP_CLASS_HID_34024] = 3282, - [BNXT_ULP_CLASS_HID_32ef0] = 3283, - [BNXT_ULP_CLASS_HID_349e0] = 3284, - [BNXT_ULP_CLASS_HID_304a0] = 3285, - [BNXT_ULP_CLASS_HID_33fd0] = 3286, - [BNXT_ULP_CLASS_HID_30a9c] = 3287, - [BNXT_ULP_CLASS_HID_3258c] = 3288, - [BNXT_ULP_CLASS_HID_34d88] = 3289, - [BNXT_ULP_CLASS_HID_3096c] = 3290, - [BNXT_ULP_CLASS_HID_31438] = 3291, - [BNXT_ULP_CLASS_HID_30f28] = 3292, - [BNXT_ULP_CLASS_HID_32aa8] = 3293, - [BNXT_ULP_CLASS_HID_345d8] = 3294, - [BNXT_ULP_CLASS_HID_35064] = 3295, - [BNXT_ULP_CLASS_HID_34b94] = 3296, - [BNXT_ULP_CLASS_HID_33444] = 3297, - [BNXT_ULP_CLASS_HID_32f74] = 3298, - [BNXT_ULP_CLASS_HID_33a00] = 3299, - [BNXT_ULP_CLASS_HID_35530] = 3300, - [BNXT_ULP_CLASS_HID_313f0] = 3301, - [BNXT_ULP_CLASS_HID_30ae0] = 3302, - [BNXT_ULP_CLASS_HID_319ac] = 3303, - [BNXT_ULP_CLASS_HID_330dc] = 3304, - [BNXT_ULP_CLASS_HID_358d8] = 3305, - [BNXT_ULP_CLASS_HID_314bc] = 3306, - [BNXT_ULP_CLASS_HID_35e94] = 3307, - [BNXT_ULP_CLASS_HID_31a78] = 3308, - [BNXT_ULP_CLASS_HID_7584c] = 3309, - [BNXT_ULP_CLASS_HID_71430] = 3310, - [BNXT_ULP_CLASS_HID_75e08] = 3311, - [BNXT_ULP_CLASS_HID_71dec] = 3312, - [BNXT_ULP_CLASS_HID_725e8] = 3313, - [BNXT_ULP_CLASS_HID_75d18] = 3314, - [BNXT_ULP_CLASS_HID_72ba4] = 3315, - [BNXT_ULP_CLASS_HID_742d4] = 3316, - [BNXT_ULP_CLASS_HID_70194] = 3317, - [BNXT_ULP_CLASS_HID_73884] = 3318, - [BNXT_ULP_CLASS_HID_70750] = 3319, - [BNXT_ULP_CLASS_HID_73e40] = 3320, - [BNXT_ULP_CLASS_HID_7467c] = 3321, - [BNXT_ULP_CLASS_HID_70220] = 3322, - [BNXT_ULP_CLASS_HID_710ec] = 3323, - [BNXT_ULP_CLASS_HID_7081c] = 3324, - [BNXT_ULP_CLASS_HID_7279c] = 3325, - [BNXT_ULP_CLASS_HID_75e8c] = 3326, - [BNXT_ULP_CLASS_HID_72d58] = 3327, - [BNXT_ULP_CLASS_HID_74448] = 3328, - [BNXT_ULP_CLASS_HID_73138] = 3329, - [BNXT_ULP_CLASS_HID_72828] = 3330, - [BNXT_ULP_CLASS_HID_736f4] = 3331, - [BNXT_ULP_CLASS_HID_751e4] = 3332, - [BNXT_ULP_CLASS_HID_74bf0] = 3333, - [BNXT_ULP_CLASS_HID_707d4] = 3334, - [BNXT_ULP_CLASS_HID_71260] = 3335, - [BNXT_ULP_CLASS_HID_70d90] = 3336, - [BNXT_ULP_CLASS_HID_7558c] = 3337, - [BNXT_ULP_CLASS_HID_71170] = 3338, - [BNXT_ULP_CLASS_HID_75b48] = 3339, - [BNXT_ULP_CLASS_HID_7172c] = 3340, - [BNXT_ULP_CLASS_HID_2d298] = 3341, - [BNXT_ULP_CLASS_HID_2cd88] = 3342, - [BNXT_ULP_CLASS_HID_2d854] = 3343, - [BNXT_ULP_CLASS_HID_29438] = 3344, - [BNXT_ULP_CLASS_HID_2bc34] = 3345, - [BNXT_ULP_CLASS_HID_2d724] = 3346, - [BNXT_ULP_CLASS_HID_2a5f0] = 3347, - [BNXT_ULP_CLASS_HID_2dce0] = 3348, - [BNXT_ULP_CLASS_HID_29ba0] = 3349, - [BNXT_ULP_CLASS_HID_2b2d0] = 3350, - [BNXT_ULP_CLASS_HID_2819c] = 3351, - [BNXT_ULP_CLASS_HID_2b88c] = 3352, - [BNXT_ULP_CLASS_HID_2c088] = 3353, - [BNXT_ULP_CLASS_HID_29c6c] = 3354, - [BNXT_ULP_CLASS_HID_2c644] = 3355, - [BNXT_ULP_CLASS_HID_28228] = 3356, - [BNXT_ULP_CLASS_HID_2a1a8] = 3357, - [BNXT_ULP_CLASS_HID_2d8d8] = 3358, - [BNXT_ULP_CLASS_HID_2a764] = 3359, - [BNXT_ULP_CLASS_HID_2de94] = 3360, - [BNXT_ULP_CLASS_HID_28b44] = 3361, - [BNXT_ULP_CLASS_HID_2a274] = 3362, - [BNXT_ULP_CLASS_HID_2b100] = 3363, - [BNXT_ULP_CLASS_HID_2a830] = 3364, - [BNXT_ULP_CLASS_HID_2c23c] = 3365, - [BNXT_ULP_CLASS_HID_281e0] = 3366, - [BNXT_ULP_CLASS_HID_2cbf8] = 3367, - [BNXT_ULP_CLASS_HID_287dc] = 3368, - [BNXT_ULP_CLASS_HID_2afd8] = 3369, - [BNXT_ULP_CLASS_HID_2c6c8] = 3370, - [BNXT_ULP_CLASS_HID_2d594] = 3371, - [BNXT_ULP_CLASS_HID_29178] = 3372, - [BNXT_ULP_CLASS_HID_6af4c] = 3373, - [BNXT_ULP_CLASS_HID_6c67c] = 3374, - [BNXT_ULP_CLASS_HID_6d508] = 3375, - [BNXT_ULP_CLASS_HID_690ec] = 3376, - [BNXT_ULP_CLASS_HID_6b8e8] = 3377, - [BNXT_ULP_CLASS_HID_6d018] = 3378, - [BNXT_ULP_CLASS_HID_6bea4] = 3379, - [BNXT_ULP_CLASS_HID_6d9d4] = 3380, - [BNXT_ULP_CLASS_HID_69494] = 3381, - [BNXT_ULP_CLASS_HID_68f84] = 3382, - [BNXT_ULP_CLASS_HID_69a50] = 3383, - [BNXT_ULP_CLASS_HID_6b540] = 3384, - [BNXT_ULP_CLASS_HID_6dd7c] = 3385, - [BNXT_ULP_CLASS_HID_69920] = 3386, - [BNXT_ULP_CLASS_HID_6c338] = 3387, - [BNXT_ULP_CLASS_HID_69f1c] = 3388, - [BNXT_ULP_CLASS_HID_6ba9c] = 3389, - [BNXT_ULP_CLASS_HID_6d58c] = 3390, - [BNXT_ULP_CLASS_HID_6a058] = 3391, - [BNXT_ULP_CLASS_HID_6db48] = 3392, - [BNXT_ULP_CLASS_HID_68438] = 3393, - [BNXT_ULP_CLASS_HID_6bf28] = 3394, - [BNXT_ULP_CLASS_HID_68df4] = 3395, - [BNXT_ULP_CLASS_HID_6a4e4] = 3396, - [BNXT_ULP_CLASS_HID_6def0] = 3397, - [BNXT_ULP_CLASS_HID_69ad4] = 3398, - [BNXT_ULP_CLASS_HID_6c4ac] = 3399, - [BNXT_ULP_CLASS_HID_68090] = 3400, - [BNXT_ULP_CLASS_HID_6a88c] = 3401, - [BNXT_ULP_CLASS_HID_6c3bc] = 3402, - [BNXT_ULP_CLASS_HID_6ae48] = 3403, - [BNXT_ULP_CLASS_HID_6c978] = 3404, - [BNXT_ULP_CLASS_HID_3c898] = 3405, - [BNXT_ULP_CLASS_HID_3847c] = 3406, - [BNXT_ULP_CLASS_HID_39308] = 3407, - [BNXT_ULP_CLASS_HID_38a38] = 3408, - [BNXT_ULP_CLASS_HID_3d234] = 3409, - [BNXT_ULP_CLASS_HID_3cd24] = 3410, - [BNXT_ULP_CLASS_HID_3dbf0] = 3411, - [BNXT_ULP_CLASS_HID_397d4] = 3412, - [BNXT_ULP_CLASS_HID_3b1a0] = 3413, - [BNXT_ULP_CLASS_HID_3a8d0] = 3414, - [BNXT_ULP_CLASS_HID_3b79c] = 3415, - [BNXT_ULP_CLASS_HID_3ae8c] = 3416, - [BNXT_ULP_CLASS_HID_39b7c] = 3417, - [BNXT_ULP_CLASS_HID_3b26c] = 3418, - [BNXT_ULP_CLASS_HID_38138] = 3419, - [BNXT_ULP_CLASS_HID_3b828] = 3420, - [BNXT_ULP_CLASS_HID_3d7a8] = 3421, - [BNXT_ULP_CLASS_HID_3938c] = 3422, - [BNXT_ULP_CLASS_HID_3dd64] = 3423, - [BNXT_ULP_CLASS_HID_39948] = 3424, - [BNXT_ULP_CLASS_HID_3a144] = 3425, - [BNXT_ULP_CLASS_HID_3d874] = 3426, - [BNXT_ULP_CLASS_HID_3a700] = 3427, - [BNXT_ULP_CLASS_HID_3de30] = 3428, - [BNXT_ULP_CLASS_HID_39cf0] = 3429, - [BNXT_ULP_CLASS_HID_3b7e0] = 3430, - [BNXT_ULP_CLASS_HID_382ac] = 3431, - [BNXT_ULP_CLASS_HID_3bddc] = 3432, - [BNXT_ULP_CLASS_HID_3c5d8] = 3433, - [BNXT_ULP_CLASS_HID_381bc] = 3434, - [BNXT_ULP_CLASS_HID_3cb94] = 3435, - [BNXT_ULP_CLASS_HID_38778] = 3436, - [BNXT_ULP_CLASS_HID_7c54c] = 3437, - [BNXT_ULP_CLASS_HID_78130] = 3438, - [BNXT_ULP_CLASS_HID_7cb08] = 3439, - [BNXT_ULP_CLASS_HID_786ec] = 3440, - [BNXT_ULP_CLASS_HID_7aee8] = 3441, - [BNXT_ULP_CLASS_HID_7c618] = 3442, - [BNXT_ULP_CLASS_HID_7d4a4] = 3443, - [BNXT_ULP_CLASS_HID_79088] = 3444, - [BNXT_ULP_CLASS_HID_78a94] = 3445, - [BNXT_ULP_CLASS_HID_7a584] = 3446, - [BNXT_ULP_CLASS_HID_7b050] = 3447, - [BNXT_ULP_CLASS_HID_7ab40] = 3448, - [BNXT_ULP_CLASS_HID_79430] = 3449, - [BNXT_ULP_CLASS_HID_78f20] = 3450, - [BNXT_ULP_CLASS_HID_79dec] = 3451, - [BNXT_ULP_CLASS_HID_7b51c] = 3452, - [BNXT_ULP_CLASS_HID_7d09c] = 3453, - [BNXT_ULP_CLASS_HID_7cb8c] = 3454, - [BNXT_ULP_CLASS_HID_7d658] = 3455, - [BNXT_ULP_CLASS_HID_7923c] = 3456, - [BNXT_ULP_CLASS_HID_7ba38] = 3457, - [BNXT_ULP_CLASS_HID_7d528] = 3458, - [BNXT_ULP_CLASS_HID_7a3f4] = 3459, - [BNXT_ULP_CLASS_HID_7dae4] = 3460, - [BNXT_ULP_CLASS_HID_799a4] = 3461, - [BNXT_ULP_CLASS_HID_7b0d4] = 3462, - [BNXT_ULP_CLASS_HID_79f60] = 3463, - [BNXT_ULP_CLASS_HID_7b690] = 3464, - [BNXT_ULP_CLASS_HID_7de8c] = 3465, - [BNXT_ULP_CLASS_HID_79a70] = 3466, - [BNXT_ULP_CLASS_HID_7c448] = 3467, - [BNXT_ULP_CLASS_HID_7802c] = 3468, - [BNXT_ULP_CLASS_HID_86a0] = 3469, - [BNXT_ULP_CLASS_HID_a1b0] = 3470, - [BNXT_ULP_CLASS_HID_8c6c] = 3471, - [BNXT_ULP_CLASS_HID_a77c] = 3472, - [BNXT_ULP_CLASS_HID_900c] = 3473, - [BNXT_ULP_CLASS_HID_8b1c] = 3474, - [BNXT_ULP_CLASS_HID_99c8] = 3475, - [BNXT_ULP_CLASS_HID_b0d8] = 3476, - [BNXT_ULP_CLASS_HID_aad4] = 3477, - [BNXT_ULP_CLASS_HID_c224] = 3478, - [BNXT_ULP_CLASS_HID_d090] = 3479, - [BNXT_ULP_CLASS_HID_cbe0] = 3480, - [BNXT_ULP_CLASS_HID_b4b0] = 3481, - [BNXT_ULP_CLASS_HID_af80] = 3482, - [BNXT_ULP_CLASS_HID_ba7c] = 3483, - [BNXT_ULP_CLASS_HID_d54c] = 3484, - [BNXT_ULP_CLASS_HID_48374] = 3485, - [BNXT_ULP_CLASS_HID_4ba44] = 3486, - [BNXT_ULP_CLASS_HID_48930] = 3487, - [BNXT_ULP_CLASS_HID_4a000] = 3488, - [BNXT_ULP_CLASS_HID_4c80c] = 3489, - [BNXT_ULP_CLASS_HID_48420] = 3490, - [BNXT_ULP_CLASS_HID_4929c] = 3491, - [BNXT_ULP_CLASS_HID_48dec] = 3492, - [BNXT_ULP_CLASS_HID_4a798] = 3493, - [BNXT_ULP_CLASS_HID_4dee8] = 3494, - [BNXT_ULP_CLASS_HID_4ada4] = 3495, - [BNXT_ULP_CLASS_HID_4c4b4] = 3496, - [BNXT_ULP_CLASS_HID_4b144] = 3497, - [BNXT_ULP_CLASS_HID_4a854] = 3498, - [BNXT_ULP_CLASS_HID_4b700] = 3499, - [BNXT_ULP_CLASS_HID_4ae10] = 3500, - [BNXT_ULP_CLASS_HID_1bca0] = 3501, - [BNXT_ULP_CLASS_HID_1d7b0] = 3502, - [BNXT_ULP_CLASS_HID_1a26c] = 3503, - [BNXT_ULP_CLASS_HID_1dd7c] = 3504, - [BNXT_ULP_CLASS_HID_1860c] = 3505, - [BNXT_ULP_CLASS_HID_1a11c] = 3506, - [BNXT_ULP_CLASS_HID_18fc8] = 3507, - [BNXT_ULP_CLASS_HID_1a6d8] = 3508, - [BNXT_ULP_CLASS_HID_1c0d4] = 3509, - [BNXT_ULP_CLASS_HID_19ce8] = 3510, - [BNXT_ULP_CLASS_HID_1c690] = 3511, - [BNXT_ULP_CLASS_HID_182b4] = 3512, - [BNXT_ULP_CLASS_HID_1aab0] = 3513, - [BNXT_ULP_CLASS_HID_1c580] = 3514, - [BNXT_ULP_CLASS_HID_1d07c] = 3515, - [BNXT_ULP_CLASS_HID_1cb4c] = 3516, - [BNXT_ULP_CLASS_HID_5b974] = 3517, - [BNXT_ULP_CLASS_HID_5d044] = 3518, - [BNXT_ULP_CLASS_HID_5bf30] = 3519, - [BNXT_ULP_CLASS_HID_5d600] = 3520, - [BNXT_ULP_CLASS_HID_582d0] = 3521, - [BNXT_ULP_CLASS_HID_5ba20] = 3522, - [BNXT_ULP_CLASS_HID_5889c] = 3523, - [BNXT_ULP_CLASS_HID_5a3ec] = 3524, - [BNXT_ULP_CLASS_HID_5dd98] = 3525, - [BNXT_ULP_CLASS_HID_599bc] = 3526, - [BNXT_ULP_CLASS_HID_5c3a4] = 3527, - [BNXT_ULP_CLASS_HID_59f78] = 3528, - [BNXT_ULP_CLASS_HID_5a744] = 3529, - [BNXT_ULP_CLASS_HID_5de54] = 3530, - [BNXT_ULP_CLASS_HID_5ad00] = 3531, - [BNXT_ULP_CLASS_HID_5c410] = 3532, - [BNXT_ULP_CLASS_HID_cd20] = 3533, - [BNXT_ULP_CLASS_HID_e430] = 3534, - [BNXT_ULP_CLASS_HID_f2ec] = 3535, - [BNXT_ULP_CLASS_HID_edfc] = 3536, - [BNXT_ULP_CLASS_HID_d68c] = 3537, - [BNXT_ULP_CLASS_HID_f19c] = 3538, - [BNXT_ULP_CLASS_HID_dc48] = 3539, - [BNXT_ULP_CLASS_HID_f758] = 3540, - [BNXT_ULP_CLASS_HID_d154] = 3541, - [BNXT_ULP_CLASS_HID_c8a4] = 3542, - [BNXT_ULP_CLASS_HID_d710] = 3543, - [BNXT_ULP_CLASS_HID_d334] = 3544, - [BNXT_ULP_CLASS_HID_fb30] = 3545, - [BNXT_ULP_CLASS_HID_d200] = 3546, - [BNXT_ULP_CLASS_HID_e0fc] = 3547, - [BNXT_ULP_CLASS_HID_dbcc] = 3548, - [BNXT_ULP_CLASS_HID_4c9f4] = 3549, - [BNXT_ULP_CLASS_HID_4e0c4] = 3550, - [BNXT_ULP_CLASS_HID_4cfb0] = 3551, - [BNXT_ULP_CLASS_HID_4e680] = 3552, - [BNXT_ULP_CLASS_HID_4d350] = 3553, - [BNXT_ULP_CLASS_HID_4caa0] = 3554, - [BNXT_ULP_CLASS_HID_4d91c] = 3555, - [BNXT_ULP_CLASS_HID_4f06c] = 3556, - [BNXT_ULP_CLASS_HID_4ea18] = 3557, - [BNXT_ULP_CLASS_HID_4c568] = 3558, - [BNXT_ULP_CLASS_HID_4d024] = 3559, - [BNXT_ULP_CLASS_HID_4cb34] = 3560, - [BNXT_ULP_CLASS_HID_4f7c4] = 3561, - [BNXT_ULP_CLASS_HID_4eed4] = 3562, - [BNXT_ULP_CLASS_HID_4fd80] = 3563, - [BNXT_ULP_CLASS_HID_4d490] = 3564, - [BNXT_ULP_CLASS_HID_1e320] = 3565, - [BNXT_ULP_CLASS_HID_1da30] = 3566, - [BNXT_ULP_CLASS_HID_1e8ec] = 3567, - [BNXT_ULP_CLASS_HID_1c3fc] = 3568, - [BNXT_ULP_CLASS_HID_1cc8c] = 3569, - [BNXT_ULP_CLASS_HID_1e79c] = 3570, - [BNXT_ULP_CLASS_HID_1f248] = 3571, - [BNXT_ULP_CLASS_HID_1ed58] = 3572, - [BNXT_ULP_CLASS_HID_1c754] = 3573, - [BNXT_ULP_CLASS_HID_1c368] = 3574, - [BNXT_ULP_CLASS_HID_1cd10] = 3575, - [BNXT_ULP_CLASS_HID_1c934] = 3576, - [BNXT_ULP_CLASS_HID_1d130] = 3577, - [BNXT_ULP_CLASS_HID_1c800] = 3578, - [BNXT_ULP_CLASS_HID_1d6fc] = 3579, - [BNXT_ULP_CLASS_HID_1d290] = 3580, - [BNXT_ULP_CLASS_HID_5fff4] = 3581, - [BNXT_ULP_CLASS_HID_5d6c4] = 3582, - [BNXT_ULP_CLASS_HID_5e5b0] = 3583, - [BNXT_ULP_CLASS_HID_5dc80] = 3584, - [BNXT_ULP_CLASS_HID_5c950] = 3585, - [BNXT_ULP_CLASS_HID_5e0a0] = 3586, - [BNXT_ULP_CLASS_HID_5cf1c] = 3587, - [BNXT_ULP_CLASS_HID_5e66c] = 3588, - [BNXT_ULP_CLASS_HID_5c018] = 3589, - [BNXT_ULP_CLASS_HID_5dc3c] = 3590, - [BNXT_ULP_CLASS_HID_5c624] = 3591, - [BNXT_ULP_CLASS_HID_5c5f8] = 3592, - [BNXT_ULP_CLASS_HID_5edc4] = 3593, - [BNXT_ULP_CLASS_HID_5c4d4] = 3594, - [BNXT_ULP_CLASS_HID_5d380] = 3595, - [BNXT_ULP_CLASS_HID_5ca90] = 3596, - [BNXT_ULP_CLASS_HID_abe0] = 3597, - [BNXT_ULP_CLASS_HID_a2f0] = 3598, - [BNXT_ULP_CLASS_HID_b1ac] = 3599, - [BNXT_ULP_CLASS_HID_a8bc] = 3600, - [BNXT_ULP_CLASS_HID_b54c] = 3601, - [BNXT_ULP_CLASS_HID_ac5c] = 3602, - [BNXT_ULP_CLASS_HID_bb08] = 3603, - [BNXT_ULP_CLASS_HID_b218] = 3604, - [BNXT_ULP_CLASS_HID_ac14] = 3605, - [BNXT_ULP_CLASS_HID_e764] = 3606, - [BNXT_ULP_CLASS_HID_f5d0] = 3607, - [BNXT_ULP_CLASS_HID_b1f4] = 3608, - [BNXT_ULP_CLASS_HID_b9f0] = 3609, - [BNXT_ULP_CLASS_HID_f0c0] = 3610, - [BNXT_ULP_CLASS_HID_bfbc] = 3611, - [BNXT_ULP_CLASS_HID_f68c] = 3612, - [BNXT_ULP_CLASS_HID_4a4b4] = 3613, - [BNXT_ULP_CLASS_HID_4bf84] = 3614, - [BNXT_ULP_CLASS_HID_4aa70] = 3615, - [BNXT_ULP_CLASS_HID_4a540] = 3616, - [BNXT_ULP_CLASS_HID_4ed4c] = 3617, - [BNXT_ULP_CLASS_HID_4a960] = 3618, - [BNXT_ULP_CLASS_HID_4b7dc] = 3619, - [BNXT_ULP_CLASS_HID_4af2c] = 3620, - [BNXT_ULP_CLASS_HID_4a8d8] = 3621, - [BNXT_ULP_CLASS_HID_4e028] = 3622, - [BNXT_ULP_CLASS_HID_4aee4] = 3623, - [BNXT_ULP_CLASS_HID_4e9f4] = 3624, - [BNXT_ULP_CLASS_HID_4b284] = 3625, - [BNXT_ULP_CLASS_HID_4ad94] = 3626, - [BNXT_ULP_CLASS_HID_4b840] = 3627, - [BNXT_ULP_CLASS_HID_4f350] = 3628, - [BNXT_ULP_CLASS_HID_1a1e0] = 3629, - [BNXT_ULP_CLASS_HID_1f8f0] = 3630, - [BNXT_ULP_CLASS_HID_1a7ac] = 3631, - [BNXT_ULP_CLASS_HID_1febc] = 3632, - [BNXT_ULP_CLASS_HID_1ab4c] = 3633, - [BNXT_ULP_CLASS_HID_1a25c] = 3634, - [BNXT_ULP_CLASS_HID_1b108] = 3635, - [BNXT_ULP_CLASS_HID_1a818] = 3636, - [BNXT_ULP_CLASS_HID_1e214] = 3637, - [BNXT_ULP_CLASS_HID_1be28] = 3638, - [BNXT_ULP_CLASS_HID_1ebd0] = 3639, - [BNXT_ULP_CLASS_HID_1a7f4] = 3640, - [BNXT_ULP_CLASS_HID_1aff0] = 3641, - [BNXT_ULP_CLASS_HID_1e6c0] = 3642, - [BNXT_ULP_CLASS_HID_1f5bc] = 3643, - [BNXT_ULP_CLASS_HID_1b150] = 3644, - [BNXT_ULP_CLASS_HID_5bab4] = 3645, - [BNXT_ULP_CLASS_HID_5f584] = 3646, - [BNXT_ULP_CLASS_HID_5a070] = 3647, - [BNXT_ULP_CLASS_HID_5fb40] = 3648, - [BNXT_ULP_CLASS_HID_5a410] = 3649, - [BNXT_ULP_CLASS_HID_5bf60] = 3650, - [BNXT_ULP_CLASS_HID_5addc] = 3651, - [BNXT_ULP_CLASS_HID_5a52c] = 3652, - [BNXT_ULP_CLASS_HID_5fed8] = 3653, - [BNXT_ULP_CLASS_HID_5bafc] = 3654, - [BNXT_ULP_CLASS_HID_5e4e4] = 3655, - [BNXT_ULP_CLASS_HID_5a0b8] = 3656, - [BNXT_ULP_CLASS_HID_5a884] = 3657, - [BNXT_ULP_CLASS_HID_5e394] = 3658, - [BNXT_ULP_CLASS_HID_5ae40] = 3659, - [BNXT_ULP_CLASS_HID_5e950] = 3660, - [BNXT_ULP_CLASS_HID_ee60] = 3661, - [BNXT_ULP_CLASS_HID_e970] = 3662, - [BNXT_ULP_CLASS_HID_f42c] = 3663, - [BNXT_ULP_CLASS_HID_ef3c] = 3664, - [BNXT_ULP_CLASS_HID_fbcc] = 3665, - [BNXT_ULP_CLASS_HID_f2dc] = 3666, - [BNXT_ULP_CLASS_HID_e188] = 3667, - [BNXT_ULP_CLASS_HID_f898] = 3668, - [BNXT_ULP_CLASS_HID_f294] = 3669, - [BNXT_ULP_CLASS_HID_ede4] = 3670, - [BNXT_ULP_CLASS_HID_f850] = 3671, - [BNXT_ULP_CLASS_HID_f474] = 3672, - [BNXT_ULP_CLASS_HID_fc70] = 3673, - [BNXT_ULP_CLASS_HID_f740] = 3674, - [BNXT_ULP_CLASS_HID_e23c] = 3675, - [BNXT_ULP_CLASS_HID_fd0c] = 3676, - [BNXT_ULP_CLASS_HID_4eb34] = 3677, - [BNXT_ULP_CLASS_HID_4e204] = 3678, - [BNXT_ULP_CLASS_HID_4f0f0] = 3679, - [BNXT_ULP_CLASS_HID_4ebc0] = 3680, - [BNXT_ULP_CLASS_HID_4f490] = 3681, - [BNXT_ULP_CLASS_HID_4efe0] = 3682, - [BNXT_ULP_CLASS_HID_4fa5c] = 3683, - [BNXT_ULP_CLASS_HID_4f5ac] = 3684, - [BNXT_ULP_CLASS_HID_4ef58] = 3685, - [BNXT_ULP_CLASS_HID_4e6a8] = 3686, - [BNXT_ULP_CLASS_HID_4f564] = 3687, - [BNXT_ULP_CLASS_HID_4f138] = 3688, - [BNXT_ULP_CLASS_HID_4f904] = 3689, - [BNXT_ULP_CLASS_HID_4f014] = 3690, - [BNXT_ULP_CLASS_HID_4fec0] = 3691, - [BNXT_ULP_CLASS_HID_4f9d0] = 3692, - [BNXT_ULP_CLASS_HID_1e460] = 3693, - [BNXT_ULP_CLASS_HID_1ff70] = 3694, - [BNXT_ULP_CLASS_HID_1ea2c] = 3695, - [BNXT_ULP_CLASS_HID_1e53c] = 3696, - [BNXT_ULP_CLASS_HID_1f1cc] = 3697, - [BNXT_ULP_CLASS_HID_1e8dc] = 3698, - [BNXT_ULP_CLASS_HID_1f788] = 3699, - [BNXT_ULP_CLASS_HID_1ee98] = 3700, - [BNXT_ULP_CLASS_HID_1e894] = 3701, - [BNXT_ULP_CLASS_HID_1e4a8] = 3702, - [BNXT_ULP_CLASS_HID_1f364] = 3703, - [BNXT_ULP_CLASS_HID_1ea74] = 3704, - [BNXT_ULP_CLASS_HID_1f270] = 3705, - [BNXT_ULP_CLASS_HID_1ed40] = 3706, - [BNXT_ULP_CLASS_HID_1f83c] = 3707, - [BNXT_ULP_CLASS_HID_1f7d0] = 3708, - [BNXT_ULP_CLASS_HID_5e134] = 3709, - [BNXT_ULP_CLASS_HID_5f804] = 3710, - [BNXT_ULP_CLASS_HID_5e6f0] = 3711, - [BNXT_ULP_CLASS_HID_5e1c0] = 3712, - [BNXT_ULP_CLASS_HID_5ea90] = 3713, - [BNXT_ULP_CLASS_HID_5e5e0] = 3714, - [BNXT_ULP_CLASS_HID_5f05c] = 3715, - [BNXT_ULP_CLASS_HID_5ebac] = 3716, - [BNXT_ULP_CLASS_HID_5e558] = 3717, - [BNXT_ULP_CLASS_HID_5e17c] = 3718, - [BNXT_ULP_CLASS_HID_5eb64] = 3719, - [BNXT_ULP_CLASS_HID_5e738] = 3720, - [BNXT_ULP_CLASS_HID_5ef04] = 3721, - [BNXT_ULP_CLASS_HID_5e614] = 3722, - [BNXT_ULP_CLASS_HID_5f4c0] = 3723, - [BNXT_ULP_CLASS_HID_5f0e4] = 3724, - [BNXT_ULP_CLASS_HID_5802] = 3725, - [BNXT_ULP_CLASS_HID_5e46] = 3726, - [BNXT_ULP_CLASS_HID_1d76] = 3727, - [BNXT_ULP_CLASS_HID_02ba] = 3728, - [BNXT_ULP_CLASS_HID_32a2] = 3729, - [BNXT_ULP_CLASS_HID_38e6] = 3730, - [BNXT_ULP_CLASS_HID_52ca] = 3731, - [BNXT_ULP_CLASS_HID_580e] = 3732, - [BNXT_ULP_CLASS_HID_44996] = 3733, - [BNXT_ULP_CLASS_HID_410e6] = 3734, - [BNXT_ULP_CLASS_HID_42036] = 3735, - [BNXT_ULP_CLASS_HID_4264a] = 3736, - [BNXT_ULP_CLASS_HID_45ffe] = 3737, - [BNXT_ULP_CLASS_HID_44532] = 3738, - [BNXT_ULP_CLASS_HID_4399e] = 3739, - [BNXT_ULP_CLASS_HID_43fd2] = 3740, - [BNXT_ULP_CLASS_HID_23da0] = 3741, - [BNXT_ULP_CLASS_HID_2239c] = 3742, - [BNXT_ULP_CLASS_HID_207fc] = 3743, - [BNXT_ULP_CLASS_HID_20d38] = 3744, - [BNXT_ULP_CLASS_HID_25e34] = 3745, - [BNXT_ULP_CLASS_HID_24470] = 3746, - [BNXT_ULP_CLASS_HID_22850] = 3747, - [BNXT_ULP_CLASS_HID_2518c] = 3748, - [BNXT_ULP_CLASS_HID_20970] = 3749, - [BNXT_ULP_CLASS_HID_20eac] = 3750, - [BNXT_ULP_CLASS_HID_2128c] = 3751, - [BNXT_ULP_CLASS_HID_218c8] = 3752, - [BNXT_ULP_CLASS_HID_22dc4] = 3753, - [BNXT_ULP_CLASS_HID_25300] = 3754, - [BNXT_ULP_CLASS_HID_23760] = 3755, - [BNXT_ULP_CLASS_HID_23d5c] = 3756, - [BNXT_ULP_CLASS_HID_63694] = 3757, - [BNXT_ULP_CLASS_HID_63cd0] = 3758, - [BNXT_ULP_CLASS_HID_60030] = 3759, - [BNXT_ULP_CLASS_HID_6066c] = 3760, - [BNXT_ULP_CLASS_HID_65b68] = 3761, - [BNXT_ULP_CLASS_HID_640a4] = 3762, - [BNXT_ULP_CLASS_HID_62484] = 3763, - [BNXT_ULP_CLASS_HID_62ac0] = 3764, - [BNXT_ULP_CLASS_HID_605a4] = 3765, - [BNXT_ULP_CLASS_HID_60be0] = 3766, - [BNXT_ULP_CLASS_HID_64a8c] = 3767, - [BNXT_ULP_CLASS_HID_6153c] = 3768, - [BNXT_ULP_CLASS_HID_62638] = 3769, - [BNXT_ULP_CLASS_HID_62c74] = 3770, - [BNXT_ULP_CLASS_HID_63054] = 3771, - [BNXT_ULP_CLASS_HID_63990] = 3772, - [BNXT_ULP_CLASS_HID_9a98] = 3773, - [BNXT_ULP_CLASS_HID_80a4] = 3774, - [BNXT_ULP_CLASS_HID_c3b0] = 3775, - [BNXT_ULP_CLASS_HID_c9fc] = 3776, - [BNXT_ULP_CLASS_HID_bf0c] = 3777, - [BNXT_ULP_CLASS_HID_a548] = 3778, - [BNXT_ULP_CLASS_HID_8968] = 3779, - [BNXT_ULP_CLASS_HID_8eb4] = 3780, - [BNXT_ULP_CLASS_HID_497ac] = 3781, - [BNXT_ULP_CLASS_HID_49de8] = 3782, - [BNXT_ULP_CLASS_HID_4dcc4] = 3783, - [BNXT_ULP_CLASS_HID_4c200] = 3784, - [BNXT_ULP_CLASS_HID_4b850] = 3785, - [BNXT_ULP_CLASS_HID_4a19c] = 3786, - [BNXT_ULP_CLASS_HID_485bc] = 3787, - [BNXT_ULP_CLASS_HID_48bf8] = 3788, - [BNXT_ULP_CLASS_HID_1b098] = 3789, - [BNXT_ULP_CLASS_HID_1b6a4] = 3790, - [BNXT_ULP_CLASS_HID_19ac4] = 3791, - [BNXT_ULP_CLASS_HID_18000] = 3792, - [BNXT_ULP_CLASS_HID_1d50c] = 3793, - [BNXT_ULP_CLASS_HID_1db48] = 3794, - [BNXT_ULP_CLASS_HID_1bf68] = 3795, - [BNXT_ULP_CLASS_HID_1a4b4] = 3796, - [BNXT_ULP_CLASS_HID_58dac] = 3797, - [BNXT_ULP_CLASS_HID_5b3e8] = 3798, - [BNXT_ULP_CLASS_HID_59708] = 3799, - [BNXT_ULP_CLASS_HID_59d54] = 3800, - [BNXT_ULP_CLASS_HID_5ae50] = 3801, - [BNXT_ULP_CLASS_HID_5d79c] = 3802, - [BNXT_ULP_CLASS_HID_5bbbc] = 3803, - [BNXT_ULP_CLASS_HID_5a1f8] = 3804, - [BNXT_ULP_CLASS_HID_5822] = 3805, - [BNXT_ULP_CLASS_HID_5e66] = 3806, - [BNXT_ULP_CLASS_HID_1d56] = 3807, - [BNXT_ULP_CLASS_HID_029a] = 3808, - [BNXT_ULP_CLASS_HID_3282] = 3809, - [BNXT_ULP_CLASS_HID_38c6] = 3810, - [BNXT_ULP_CLASS_HID_52ea] = 3811, - [BNXT_ULP_CLASS_HID_582e] = 3812, - [BNXT_ULP_CLASS_HID_51ba] = 3813, - [BNXT_ULP_CLASS_HID_57fe] = 3814, - [BNXT_ULP_CLASS_HID_12ee] = 3815, - [BNXT_ULP_CLASS_HID_1832] = 3816, - [BNXT_ULP_CLASS_HID_081a] = 3817, - [BNXT_ULP_CLASS_HID_0e5e] = 3818, - [BNXT_ULP_CLASS_HID_2802] = 3819, - [BNXT_ULP_CLASS_HID_2e46] = 3820, - [BNXT_ULP_CLASS_HID_4556e] = 3821, - [BNXT_ULP_CLASS_HID_45ab2] = 3822, - [BNXT_ULP_CLASS_HID_419a2] = 3823, - [BNXT_ULP_CLASS_HID_41fe6] = 3824, - [BNXT_ULP_CLASS_HID_40fce] = 3825, - [BNXT_ULP_CLASS_HID_43512] = 3826, - [BNXT_ULP_CLASS_HID_42f36] = 3827, - [BNXT_ULP_CLASS_HID_4557a] = 3828, - [BNXT_ULP_CLASS_HID_42a86] = 3829, - [BNXT_ULP_CLASS_HID_450ca] = 3830, - [BNXT_ULP_CLASS_HID_44aee] = 3831, - [BNXT_ULP_CLASS_HID_4157e] = 3832, - [BNXT_ULP_CLASS_HID_40566] = 3833, - [BNXT_ULP_CLASS_HID_40aaa] = 3834, - [BNXT_ULP_CLASS_HID_4254e] = 3835, - [BNXT_ULP_CLASS_HID_42a92] = 3836, - [BNXT_ULP_CLASS_HID_449b6] = 3837, - [BNXT_ULP_CLASS_HID_410c6] = 3838, - [BNXT_ULP_CLASS_HID_42016] = 3839, - [BNXT_ULP_CLASS_HID_4266a] = 3840, - [BNXT_ULP_CLASS_HID_45fde] = 3841, - [BNXT_ULP_CLASS_HID_44512] = 3842, - [BNXT_ULP_CLASS_HID_439be] = 3843, - [BNXT_ULP_CLASS_HID_43ff2] = 3844, - [BNXT_ULP_CLASS_HID_63682] = 3845, - [BNXT_ULP_CLASS_HID_63cc6] = 3846, - [BNXT_ULP_CLASS_HID_61162] = 3847, - [BNXT_ULP_CLASS_HID_616a6] = 3848, - [BNXT_ULP_CLASS_HID_60c2a] = 3849, - [BNXT_ULP_CLASS_HID_6326e] = 3850, - [BNXT_ULP_CLASS_HID_645be] = 3851, - [BNXT_ULP_CLASS_HID_64bf2] = 3852, - [BNXT_ULP_CLASS_HID_50082] = 3853, - [BNXT_ULP_CLASS_HID_506c6] = 3854, - [BNXT_ULP_CLASS_HID_55616] = 3855, - [BNXT_ULP_CLASS_HID_55c6a] = 3856, - [BNXT_ULP_CLASS_HID_5162a] = 3857, - [BNXT_ULP_CLASS_HID_51c6e] = 3858, - [BNXT_ULP_CLASS_HID_52fbe] = 3859, - [BNXT_ULP_CLASS_HID_555f2] = 3860, - [BNXT_ULP_CLASS_HID_72c82] = 3861, - [BNXT_ULP_CLASS_HID_752c6] = 3862, - [BNXT_ULP_CLASS_HID_70762] = 3863, - [BNXT_ULP_CLASS_HID_70ca6] = 3864, - [BNXT_ULP_CLASS_HID_7222a] = 3865, - [BNXT_ULP_CLASS_HID_7286e] = 3866, - [BNXT_ULP_CLASS_HID_71c8a] = 3867, - [BNXT_ULP_CLASS_HID_702ce] = 3868, - [BNXT_ULP_CLASS_HID_5842] = 3869, - [BNXT_ULP_CLASS_HID_5e06] = 3870, - [BNXT_ULP_CLASS_HID_1d36] = 3871, - [BNXT_ULP_CLASS_HID_02fa] = 3872, - [BNXT_ULP_CLASS_HID_32e2] = 3873, - [BNXT_ULP_CLASS_HID_38a6] = 3874, - [BNXT_ULP_CLASS_HID_528a] = 3875, - [BNXT_ULP_CLASS_HID_584e] = 3876, - [BNXT_ULP_CLASS_HID_51da] = 3877, - [BNXT_ULP_CLASS_HID_579e] = 3878, - [BNXT_ULP_CLASS_HID_128e] = 3879, - [BNXT_ULP_CLASS_HID_1852] = 3880, - [BNXT_ULP_CLASS_HID_087a] = 3881, - [BNXT_ULP_CLASS_HID_0e3e] = 3882, - [BNXT_ULP_CLASS_HID_2862] = 3883, - [BNXT_ULP_CLASS_HID_2e26] = 3884, - [BNXT_ULP_CLASS_HID_4550e] = 3885, - [BNXT_ULP_CLASS_HID_45ad2] = 3886, - [BNXT_ULP_CLASS_HID_419c2] = 3887, - [BNXT_ULP_CLASS_HID_41f86] = 3888, - [BNXT_ULP_CLASS_HID_40fae] = 3889, - [BNXT_ULP_CLASS_HID_43572] = 3890, - [BNXT_ULP_CLASS_HID_42f56] = 3891, - [BNXT_ULP_CLASS_HID_4551a] = 3892, - [BNXT_ULP_CLASS_HID_42ae6] = 3893, - [BNXT_ULP_CLASS_HID_450aa] = 3894, - [BNXT_ULP_CLASS_HID_44a8e] = 3895, - [BNXT_ULP_CLASS_HID_4151e] = 3896, - [BNXT_ULP_CLASS_HID_40506] = 3897, - [BNXT_ULP_CLASS_HID_40aca] = 3898, - [BNXT_ULP_CLASS_HID_4252e] = 3899, - [BNXT_ULP_CLASS_HID_42af2] = 3900, - [BNXT_ULP_CLASS_HID_449d6] = 3901, - [BNXT_ULP_CLASS_HID_410a6] = 3902, - [BNXT_ULP_CLASS_HID_42076] = 3903, - [BNXT_ULP_CLASS_HID_4260a] = 3904, - [BNXT_ULP_CLASS_HID_45fbe] = 3905, - [BNXT_ULP_CLASS_HID_44572] = 3906, - [BNXT_ULP_CLASS_HID_439de] = 3907, - [BNXT_ULP_CLASS_HID_43f92] = 3908, - [BNXT_ULP_CLASS_HID_636e2] = 3909, - [BNXT_ULP_CLASS_HID_63ca6] = 3910, - [BNXT_ULP_CLASS_HID_61102] = 3911, - [BNXT_ULP_CLASS_HID_616c6] = 3912, - [BNXT_ULP_CLASS_HID_60c4a] = 3913, - [BNXT_ULP_CLASS_HID_6320e] = 3914, - [BNXT_ULP_CLASS_HID_645de] = 3915, - [BNXT_ULP_CLASS_HID_64b92] = 3916, - [BNXT_ULP_CLASS_HID_500e2] = 3917, - [BNXT_ULP_CLASS_HID_506a6] = 3918, - [BNXT_ULP_CLASS_HID_55676] = 3919, - [BNXT_ULP_CLASS_HID_55c0a] = 3920, - [BNXT_ULP_CLASS_HID_5164a] = 3921, - [BNXT_ULP_CLASS_HID_51c0e] = 3922, - [BNXT_ULP_CLASS_HID_52fde] = 3923, - [BNXT_ULP_CLASS_HID_55592] = 3924, - [BNXT_ULP_CLASS_HID_72ce2] = 3925, - [BNXT_ULP_CLASS_HID_752a6] = 3926, - [BNXT_ULP_CLASS_HID_70702] = 3927, - [BNXT_ULP_CLASS_HID_70cc6] = 3928, - [BNXT_ULP_CLASS_HID_7224a] = 3929, - [BNXT_ULP_CLASS_HID_7280e] = 3930, - [BNXT_ULP_CLASS_HID_71cea] = 3931, - [BNXT_ULP_CLASS_HID_702ae] = 3932, - [BNXT_ULP_CLASS_HID_23dc0] = 3933, - [BNXT_ULP_CLASS_HID_223fc] = 3934, - [BNXT_ULP_CLASS_HID_2079c] = 3935, - [BNXT_ULP_CLASS_HID_20d58] = 3936, - [BNXT_ULP_CLASS_HID_25e54] = 3937, - [BNXT_ULP_CLASS_HID_24410] = 3938, - [BNXT_ULP_CLASS_HID_22830] = 3939, - [BNXT_ULP_CLASS_HID_251ec] = 3940, - [BNXT_ULP_CLASS_HID_20910] = 3941, - [BNXT_ULP_CLASS_HID_20ecc] = 3942, - [BNXT_ULP_CLASS_HID_212ec] = 3943, - [BNXT_ULP_CLASS_HID_218a8] = 3944, - [BNXT_ULP_CLASS_HID_22da4] = 3945, - [BNXT_ULP_CLASS_HID_25360] = 3946, - [BNXT_ULP_CLASS_HID_23700] = 3947, - [BNXT_ULP_CLASS_HID_23d3c] = 3948, - [BNXT_ULP_CLASS_HID_636f4] = 3949, - [BNXT_ULP_CLASS_HID_63cb0] = 3950, - [BNXT_ULP_CLASS_HID_60050] = 3951, - [BNXT_ULP_CLASS_HID_6060c] = 3952, - [BNXT_ULP_CLASS_HID_65b08] = 3953, - [BNXT_ULP_CLASS_HID_640c4] = 3954, - [BNXT_ULP_CLASS_HID_624e4] = 3955, - [BNXT_ULP_CLASS_HID_62aa0] = 3956, - [BNXT_ULP_CLASS_HID_605c4] = 3957, - [BNXT_ULP_CLASS_HID_60b80] = 3958, - [BNXT_ULP_CLASS_HID_64aec] = 3959, - [BNXT_ULP_CLASS_HID_6155c] = 3960, - [BNXT_ULP_CLASS_HID_62658] = 3961, - [BNXT_ULP_CLASS_HID_62c14] = 3962, - [BNXT_ULP_CLASS_HID_63034] = 3963, - [BNXT_ULP_CLASS_HID_639f0] = 3964, - [BNXT_ULP_CLASS_HID_353c0] = 3965, - [BNXT_ULP_CLASS_HID_359fc] = 3966, - [BNXT_ULP_CLASS_HID_33d9c] = 3967, - [BNXT_ULP_CLASS_HID_32358] = 3968, - [BNXT_ULP_CLASS_HID_31908] = 3969, - [BNXT_ULP_CLASS_HID_31ec4] = 3970, - [BNXT_ULP_CLASS_HID_35e30] = 3971, - [BNXT_ULP_CLASS_HID_347ec] = 3972, - [BNXT_ULP_CLASS_HID_33f10] = 3973, - [BNXT_ULP_CLASS_HID_324cc] = 3974, - [BNXT_ULP_CLASS_HID_308ec] = 3975, - [BNXT_ULP_CLASS_HID_30ea8] = 3976, - [BNXT_ULP_CLASS_HID_343a4] = 3977, - [BNXT_ULP_CLASS_HID_34960] = 3978, - [BNXT_ULP_CLASS_HID_32d00] = 3979, - [BNXT_ULP_CLASS_HID_3533c] = 3980, - [BNXT_ULP_CLASS_HID_72cf4] = 3981, - [BNXT_ULP_CLASS_HID_752b0] = 3982, - [BNXT_ULP_CLASS_HID_73650] = 3983, - [BNXT_ULP_CLASS_HID_73c0c] = 3984, - [BNXT_ULP_CLASS_HID_7123c] = 3985, - [BNXT_ULP_CLASS_HID_71bf8] = 3986, - [BNXT_ULP_CLASS_HID_75ae4] = 3987, - [BNXT_ULP_CLASS_HID_740a0] = 3988, - [BNXT_ULP_CLASS_HID_73bc4] = 3989, - [BNXT_ULP_CLASS_HID_72180] = 3990, - [BNXT_ULP_CLASS_HID_705a0] = 3991, - [BNXT_ULP_CLASS_HID_70b5c] = 3992, - [BNXT_ULP_CLASS_HID_75c58] = 3993, - [BNXT_ULP_CLASS_HID_74214] = 3994, - [BNXT_ULP_CLASS_HID_72634] = 3995, - [BNXT_ULP_CLASS_HID_72ff0] = 3996, - [BNXT_ULP_CLASS_HID_2a6c0] = 3997, - [BNXT_ULP_CLASS_HID_2acfc] = 3998, - [BNXT_ULP_CLASS_HID_2b09c] = 3999, - [BNXT_ULP_CLASS_HID_2b658] = 4000, - [BNXT_ULP_CLASS_HID_2cb54] = 4001, - [BNXT_ULP_CLASS_HID_295c4] = 4002, - [BNXT_ULP_CLASS_HID_2d530] = 4003, - [BNXT_ULP_CLASS_HID_2daec] = 4004, - [BNXT_ULP_CLASS_HID_2b210] = 4005, - [BNXT_ULP_CLASS_HID_2bbcc] = 4006, - [BNXT_ULP_CLASS_HID_29fec] = 4007, - [BNXT_ULP_CLASS_HID_285a8] = 4008, - [BNXT_ULP_CLASS_HID_2d6a4] = 4009, - [BNXT_ULP_CLASS_HID_2dc60] = 4010, - [BNXT_ULP_CLASS_HID_2a000] = 4011, - [BNXT_ULP_CLASS_HID_2a63c] = 4012, - [BNXT_ULP_CLASS_HID_6a3f4] = 4013, - [BNXT_ULP_CLASS_HID_6a9b0] = 4014, - [BNXT_ULP_CLASS_HID_68d50] = 4015, - [BNXT_ULP_CLASS_HID_6b30c] = 4016, - [BNXT_ULP_CLASS_HID_6c408] = 4017, - [BNXT_ULP_CLASS_HID_6cdc4] = 4018, - [BNXT_ULP_CLASS_HID_6d1e4] = 4019, - [BNXT_ULP_CLASS_HID_6d7a0] = 4020, - [BNXT_ULP_CLASS_HID_68ec4] = 4021, - [BNXT_ULP_CLASS_HID_6b480] = 4022, - [BNXT_ULP_CLASS_HID_698a0] = 4023, - [BNXT_ULP_CLASS_HID_69e5c] = 4024, - [BNXT_ULP_CLASS_HID_6d358] = 4025, - [BNXT_ULP_CLASS_HID_6d914] = 4026, - [BNXT_ULP_CLASS_HID_6bd34] = 4027, - [BNXT_ULP_CLASS_HID_6a2f0] = 4028, - [BNXT_ULP_CLASS_HID_3dcc0] = 4029, - [BNXT_ULP_CLASS_HID_3c2fc] = 4030, - [BNXT_ULP_CLASS_HID_3a69c] = 4031, - [BNXT_ULP_CLASS_HID_3ac58] = 4032, - [BNXT_ULP_CLASS_HID_38208] = 4033, - [BNXT_ULP_CLASS_HID_38bc4] = 4034, - [BNXT_ULP_CLASS_HID_3cb30] = 4035, - [BNXT_ULP_CLASS_HID_395a0] = 4036, - [BNXT_ULP_CLASS_HID_3a810] = 4037, - [BNXT_ULP_CLASS_HID_3d1cc] = 4038, - [BNXT_ULP_CLASS_HID_3b5ec] = 4039, - [BNXT_ULP_CLASS_HID_3bba8] = 4040, - [BNXT_ULP_CLASS_HID_39158] = 4041, - [BNXT_ULP_CLASS_HID_39714] = 4042, - [BNXT_ULP_CLASS_HID_3d600] = 4043, - [BNXT_ULP_CLASS_HID_3dc3c] = 4044, - [BNXT_ULP_CLASS_HID_7d9f4] = 4045, - [BNXT_ULP_CLASS_HID_7dfb0] = 4046, - [BNXT_ULP_CLASS_HID_7a350] = 4047, - [BNXT_ULP_CLASS_HID_7a90c] = 4048, - [BNXT_ULP_CLASS_HID_79f3c] = 4049, - [BNXT_ULP_CLASS_HID_784f8] = 4050, - [BNXT_ULP_CLASS_HID_7c7e4] = 4051, - [BNXT_ULP_CLASS_HID_7cda0] = 4052, - [BNXT_ULP_CLASS_HID_7a4c4] = 4053, - [BNXT_ULP_CLASS_HID_7aa80] = 4054, - [BNXT_ULP_CLASS_HID_78ea0] = 4055, - [BNXT_ULP_CLASS_HID_7b45c] = 4056, - [BNXT_ULP_CLASS_HID_7c958] = 4057, - [BNXT_ULP_CLASS_HID_793c8] = 4058, - [BNXT_ULP_CLASS_HID_7d334] = 4059, - [BNXT_ULP_CLASS_HID_7d8f0] = 4060, - [BNXT_ULP_CLASS_HID_9ab8] = 4061, - [BNXT_ULP_CLASS_HID_8084] = 4062, - [BNXT_ULP_CLASS_HID_c390] = 4063, - [BNXT_ULP_CLASS_HID_c9dc] = 4064, - [BNXT_ULP_CLASS_HID_bf2c] = 4065, - [BNXT_ULP_CLASS_HID_a568] = 4066, - [BNXT_ULP_CLASS_HID_8948] = 4067, - [BNXT_ULP_CLASS_HID_8e94] = 4068, - [BNXT_ULP_CLASS_HID_4978c] = 4069, - [BNXT_ULP_CLASS_HID_49dc8] = 4070, - [BNXT_ULP_CLASS_HID_4dce4] = 4071, - [BNXT_ULP_CLASS_HID_4c220] = 4072, - [BNXT_ULP_CLASS_HID_4b870] = 4073, - [BNXT_ULP_CLASS_HID_4a1bc] = 4074, - [BNXT_ULP_CLASS_HID_4859c] = 4075, - [BNXT_ULP_CLASS_HID_48bd8] = 4076, - [BNXT_ULP_CLASS_HID_1b0b8] = 4077, - [BNXT_ULP_CLASS_HID_1b684] = 4078, - [BNXT_ULP_CLASS_HID_19ae4] = 4079, - [BNXT_ULP_CLASS_HID_18020] = 4080, - [BNXT_ULP_CLASS_HID_1d52c] = 4081, - [BNXT_ULP_CLASS_HID_1db68] = 4082, - [BNXT_ULP_CLASS_HID_1bf48] = 4083, - [BNXT_ULP_CLASS_HID_1a494] = 4084, - [BNXT_ULP_CLASS_HID_58d8c] = 4085, - [BNXT_ULP_CLASS_HID_5b3c8] = 4086, - [BNXT_ULP_CLASS_HID_59728] = 4087, - [BNXT_ULP_CLASS_HID_59d74] = 4088, - [BNXT_ULP_CLASS_HID_5ae70] = 4089, - [BNXT_ULP_CLASS_HID_5d7bc] = 4090, - [BNXT_ULP_CLASS_HID_5bb9c] = 4091, - [BNXT_ULP_CLASS_HID_5a1d8] = 4092, - [BNXT_ULP_CLASS_HID_c138] = 4093, - [BNXT_ULP_CLASS_HID_c704] = 4094, - [BNXT_ULP_CLASS_HID_c610] = 4095, - [BNXT_ULP_CLASS_HID_d0a0] = 4096, - [BNXT_ULP_CLASS_HID_e5ac] = 4097, - [BNXT_ULP_CLASS_HID_ebe8] = 4098, - [BNXT_ULP_CLASS_HID_cfc8] = 4099, - [BNXT_ULP_CLASS_HID_f514] = 4100, - [BNXT_ULP_CLASS_HID_4da0c] = 4101, - [BNXT_ULP_CLASS_HID_4c048] = 4102, - [BNXT_ULP_CLASS_HID_4c364] = 4103, - [BNXT_ULP_CLASS_HID_4c8a0] = 4104, - [BNXT_ULP_CLASS_HID_4fef0] = 4105, - [BNXT_ULP_CLASS_HID_4e43c] = 4106, - [BNXT_ULP_CLASS_HID_4c81c] = 4107, - [BNXT_ULP_CLASS_HID_4ce58] = 4108, - [BNXT_ULP_CLASS_HID_1f738] = 4109, - [BNXT_ULP_CLASS_HID_1fd04] = 4110, - [BNXT_ULP_CLASS_HID_1c164] = 4111, - [BNXT_ULP_CLASS_HID_1c6a0] = 4112, - [BNXT_ULP_CLASS_HID_1dbac] = 4113, - [BNXT_ULP_CLASS_HID_1c1e8] = 4114, - [BNXT_ULP_CLASS_HID_1e5c8] = 4115, - [BNXT_ULP_CLASS_HID_1eb14] = 4116, - [BNXT_ULP_CLASS_HID_5f00c] = 4117, - [BNXT_ULP_CLASS_HID_5f648] = 4118, - [BNXT_ULP_CLASS_HID_5dda8] = 4119, - [BNXT_ULP_CLASS_HID_5c3f4] = 4120, - [BNXT_ULP_CLASS_HID_5d4f0] = 4121, - [BNXT_ULP_CLASS_HID_5da3c] = 4122, - [BNXT_ULP_CLASS_HID_5fe1c] = 4123, - [BNXT_ULP_CLASS_HID_5e458] = 4124, - [BNXT_ULP_CLASS_HID_bc78] = 4125, - [BNXT_ULP_CLASS_HID_a244] = 4126, - [BNXT_ULP_CLASS_HID_e550] = 4127, - [BNXT_ULP_CLASS_HID_ea9c] = 4128, - [BNXT_ULP_CLASS_HID_a0ec] = 4129, - [BNXT_ULP_CLASS_HID_a628] = 4130, - [BNXT_ULP_CLASS_HID_aa08] = 4131, - [BNXT_ULP_CLASS_HID_b054] = 4132, - [BNXT_ULP_CLASS_HID_4b94c] = 4133, - [BNXT_ULP_CLASS_HID_4be88] = 4134, - [BNXT_ULP_CLASS_HID_4e1a4] = 4135, - [BNXT_ULP_CLASS_HID_4e7e0] = 4136, - [BNXT_ULP_CLASS_HID_4bd30] = 4137, - [BNXT_ULP_CLASS_HID_4a37c] = 4138, - [BNXT_ULP_CLASS_HID_4a75c] = 4139, - [BNXT_ULP_CLASS_HID_4ac98] = 4140, - [BNXT_ULP_CLASS_HID_1b278] = 4141, - [BNXT_ULP_CLASS_HID_1b844] = 4142, - [BNXT_ULP_CLASS_HID_1bfa4] = 4143, - [BNXT_ULP_CLASS_HID_1a5e0] = 4144, - [BNXT_ULP_CLASS_HID_1f6ec] = 4145, - [BNXT_ULP_CLASS_HID_1fc28] = 4146, - [BNXT_ULP_CLASS_HID_1a008] = 4147, - [BNXT_ULP_CLASS_HID_1a654] = 4148, - [BNXT_ULP_CLASS_HID_5af4c] = 4149, - [BNXT_ULP_CLASS_HID_5b488] = 4150, - [BNXT_ULP_CLASS_HID_5b8e8] = 4151, - [BNXT_ULP_CLASS_HID_5be34] = 4152, - [BNXT_ULP_CLASS_HID_5f330] = 4153, - [BNXT_ULP_CLASS_HID_5f97c] = 4154, - [BNXT_ULP_CLASS_HID_5bd5c] = 4155, - [BNXT_ULP_CLASS_HID_5a298] = 4156, - [BNXT_ULP_CLASS_HID_e2f8] = 4157, - [BNXT_ULP_CLASS_HID_e8c4] = 4158, - [BNXT_ULP_CLASS_HID_ebd0] = 4159, - [BNXT_ULP_CLASS_HID_f260] = 4160, - [BNXT_ULP_CLASS_HID_e76c] = 4161, - [BNXT_ULP_CLASS_HID_eca8] = 4162, - [BNXT_ULP_CLASS_HID_f088] = 4163, - [BNXT_ULP_CLASS_HID_f6d4] = 4164, - [BNXT_ULP_CLASS_HID_4ffcc] = 4165, - [BNXT_ULP_CLASS_HID_4e508] = 4166, - [BNXT_ULP_CLASS_HID_4e424] = 4167, - [BNXT_ULP_CLASS_HID_4ea60] = 4168, - [BNXT_ULP_CLASS_HID_4e3b0] = 4169, - [BNXT_ULP_CLASS_HID_4e9fc] = 4170, - [BNXT_ULP_CLASS_HID_4eddc] = 4171, - [BNXT_ULP_CLASS_HID_4f318] = 4172, - [BNXT_ULP_CLASS_HID_1f8f8] = 4173, - [BNXT_ULP_CLASS_HID_1fec4] = 4174, - [BNXT_ULP_CLASS_HID_1e224] = 4175, - [BNXT_ULP_CLASS_HID_1e860] = 4176, - [BNXT_ULP_CLASS_HID_1fd6c] = 4177, - [BNXT_ULP_CLASS_HID_1e2a8] = 4178, - [BNXT_ULP_CLASS_HID_1e688] = 4179, - [BNXT_ULP_CLASS_HID_1ecd4] = 4180, - [BNXT_ULP_CLASS_HID_5f5cc] = 4181, - [BNXT_ULP_CLASS_HID_5fb08] = 4182, - [BNXT_ULP_CLASS_HID_5ff68] = 4183, - [BNXT_ULP_CLASS_HID_5e4b4] = 4184, - [BNXT_ULP_CLASS_HID_5f9b0] = 4185, - [BNXT_ULP_CLASS_HID_5fffc] = 4186, - [BNXT_ULP_CLASS_HID_5e3dc] = 4187, - [BNXT_ULP_CLASS_HID_5e918] = 4188, - [BNXT_ULP_CLASS_HID_23de0] = 4189, - [BNXT_ULP_CLASS_HID_223dc] = 4190, - [BNXT_ULP_CLASS_HID_207bc] = 4191, - [BNXT_ULP_CLASS_HID_20d78] = 4192, - [BNXT_ULP_CLASS_HID_25e74] = 4193, - [BNXT_ULP_CLASS_HID_24430] = 4194, - [BNXT_ULP_CLASS_HID_22810] = 4195, - [BNXT_ULP_CLASS_HID_251cc] = 4196, - [BNXT_ULP_CLASS_HID_20930] = 4197, - [BNXT_ULP_CLASS_HID_20eec] = 4198, - [BNXT_ULP_CLASS_HID_212cc] = 4199, - [BNXT_ULP_CLASS_HID_21888] = 4200, - [BNXT_ULP_CLASS_HID_22d84] = 4201, - [BNXT_ULP_CLASS_HID_25340] = 4202, - [BNXT_ULP_CLASS_HID_23720] = 4203, - [BNXT_ULP_CLASS_HID_23d1c] = 4204, - [BNXT_ULP_CLASS_HID_636d4] = 4205, - [BNXT_ULP_CLASS_HID_63c90] = 4206, - [BNXT_ULP_CLASS_HID_60070] = 4207, - [BNXT_ULP_CLASS_HID_6062c] = 4208, - [BNXT_ULP_CLASS_HID_65b28] = 4209, - [BNXT_ULP_CLASS_HID_640e4] = 4210, - [BNXT_ULP_CLASS_HID_624c4] = 4211, - [BNXT_ULP_CLASS_HID_62a80] = 4212, - [BNXT_ULP_CLASS_HID_605e4] = 4213, - [BNXT_ULP_CLASS_HID_60ba0] = 4214, - [BNXT_ULP_CLASS_HID_64acc] = 4215, - [BNXT_ULP_CLASS_HID_6157c] = 4216, - [BNXT_ULP_CLASS_HID_62678] = 4217, - [BNXT_ULP_CLASS_HID_62c34] = 4218, - [BNXT_ULP_CLASS_HID_63014] = 4219, - [BNXT_ULP_CLASS_HID_639d0] = 4220, - [BNXT_ULP_CLASS_HID_353e0] = 4221, - [BNXT_ULP_CLASS_HID_359dc] = 4222, - [BNXT_ULP_CLASS_HID_33dbc] = 4223, - [BNXT_ULP_CLASS_HID_32378] = 4224, - [BNXT_ULP_CLASS_HID_31928] = 4225, - [BNXT_ULP_CLASS_HID_31ee4] = 4226, - [BNXT_ULP_CLASS_HID_35e10] = 4227, - [BNXT_ULP_CLASS_HID_347cc] = 4228, - [BNXT_ULP_CLASS_HID_33f30] = 4229, - [BNXT_ULP_CLASS_HID_324ec] = 4230, - [BNXT_ULP_CLASS_HID_308cc] = 4231, - [BNXT_ULP_CLASS_HID_30e88] = 4232, - [BNXT_ULP_CLASS_HID_34384] = 4233, - [BNXT_ULP_CLASS_HID_34940] = 4234, - [BNXT_ULP_CLASS_HID_32d20] = 4235, - [BNXT_ULP_CLASS_HID_3531c] = 4236, - [BNXT_ULP_CLASS_HID_72cd4] = 4237, - [BNXT_ULP_CLASS_HID_75290] = 4238, - [BNXT_ULP_CLASS_HID_73670] = 4239, - [BNXT_ULP_CLASS_HID_73c2c] = 4240, - [BNXT_ULP_CLASS_HID_7121c] = 4241, - [BNXT_ULP_CLASS_HID_71bd8] = 4242, - [BNXT_ULP_CLASS_HID_75ac4] = 4243, - [BNXT_ULP_CLASS_HID_74080] = 4244, - [BNXT_ULP_CLASS_HID_73be4] = 4245, - [BNXT_ULP_CLASS_HID_721a0] = 4246, - [BNXT_ULP_CLASS_HID_70580] = 4247, - [BNXT_ULP_CLASS_HID_70b7c] = 4248, - [BNXT_ULP_CLASS_HID_75c78] = 4249, - [BNXT_ULP_CLASS_HID_74234] = 4250, - [BNXT_ULP_CLASS_HID_72614] = 4251, - [BNXT_ULP_CLASS_HID_72fd0] = 4252, - [BNXT_ULP_CLASS_HID_2a6e0] = 4253, - [BNXT_ULP_CLASS_HID_2acdc] = 4254, - [BNXT_ULP_CLASS_HID_2b0bc] = 4255, - [BNXT_ULP_CLASS_HID_2b678] = 4256, - [BNXT_ULP_CLASS_HID_2cb74] = 4257, - [BNXT_ULP_CLASS_HID_295e4] = 4258, - [BNXT_ULP_CLASS_HID_2d510] = 4259, - [BNXT_ULP_CLASS_HID_2dacc] = 4260, - [BNXT_ULP_CLASS_HID_2b230] = 4261, - [BNXT_ULP_CLASS_HID_2bbec] = 4262, - [BNXT_ULP_CLASS_HID_29fcc] = 4263, - [BNXT_ULP_CLASS_HID_28588] = 4264, - [BNXT_ULP_CLASS_HID_2d684] = 4265, - [BNXT_ULP_CLASS_HID_2dc40] = 4266, - [BNXT_ULP_CLASS_HID_2a020] = 4267, - [BNXT_ULP_CLASS_HID_2a61c] = 4268, - [BNXT_ULP_CLASS_HID_6a3d4] = 4269, - [BNXT_ULP_CLASS_HID_6a990] = 4270, - [BNXT_ULP_CLASS_HID_68d70] = 4271, - [BNXT_ULP_CLASS_HID_6b32c] = 4272, - [BNXT_ULP_CLASS_HID_6c428] = 4273, - [BNXT_ULP_CLASS_HID_6cde4] = 4274, - [BNXT_ULP_CLASS_HID_6d1c4] = 4275, - [BNXT_ULP_CLASS_HID_6d780] = 4276, - [BNXT_ULP_CLASS_HID_68ee4] = 4277, - [BNXT_ULP_CLASS_HID_6b4a0] = 4278, - [BNXT_ULP_CLASS_HID_69880] = 4279, - [BNXT_ULP_CLASS_HID_69e7c] = 4280, - [BNXT_ULP_CLASS_HID_6d378] = 4281, - [BNXT_ULP_CLASS_HID_6d934] = 4282, - [BNXT_ULP_CLASS_HID_6bd14] = 4283, - [BNXT_ULP_CLASS_HID_6a2d0] = 4284, - [BNXT_ULP_CLASS_HID_3dce0] = 4285, - [BNXT_ULP_CLASS_HID_3c2dc] = 4286, - [BNXT_ULP_CLASS_HID_3a6bc] = 4287, - [BNXT_ULP_CLASS_HID_3ac78] = 4288, - [BNXT_ULP_CLASS_HID_38228] = 4289, - [BNXT_ULP_CLASS_HID_38be4] = 4290, - [BNXT_ULP_CLASS_HID_3cb10] = 4291, - [BNXT_ULP_CLASS_HID_39580] = 4292, - [BNXT_ULP_CLASS_HID_3a830] = 4293, - [BNXT_ULP_CLASS_HID_3d1ec] = 4294, - [BNXT_ULP_CLASS_HID_3b5cc] = 4295, - [BNXT_ULP_CLASS_HID_3bb88] = 4296, - [BNXT_ULP_CLASS_HID_39178] = 4297, - [BNXT_ULP_CLASS_HID_39734] = 4298, - [BNXT_ULP_CLASS_HID_3d620] = 4299, - [BNXT_ULP_CLASS_HID_3dc1c] = 4300, - [BNXT_ULP_CLASS_HID_7d9d4] = 4301, - [BNXT_ULP_CLASS_HID_7df90] = 4302, - [BNXT_ULP_CLASS_HID_7a370] = 4303, - [BNXT_ULP_CLASS_HID_7a92c] = 4304, - [BNXT_ULP_CLASS_HID_79f1c] = 4305, - [BNXT_ULP_CLASS_HID_784d8] = 4306, - [BNXT_ULP_CLASS_HID_7c7c4] = 4307, - [BNXT_ULP_CLASS_HID_7cd80] = 4308, - [BNXT_ULP_CLASS_HID_7a4e4] = 4309, - [BNXT_ULP_CLASS_HID_7aaa0] = 4310, - [BNXT_ULP_CLASS_HID_78e80] = 4311, - [BNXT_ULP_CLASS_HID_7b47c] = 4312, - [BNXT_ULP_CLASS_HID_7c978] = 4313, - [BNXT_ULP_CLASS_HID_793e8] = 4314, - [BNXT_ULP_CLASS_HID_7d314] = 4315, - [BNXT_ULP_CLASS_HID_7d8d0] = 4316, - [BNXT_ULP_CLASS_HID_9ad8] = 4317, - [BNXT_ULP_CLASS_HID_80e4] = 4318, - [BNXT_ULP_CLASS_HID_c3f0] = 4319, - [BNXT_ULP_CLASS_HID_c9bc] = 4320, - [BNXT_ULP_CLASS_HID_bf4c] = 4321, - [BNXT_ULP_CLASS_HID_a508] = 4322, - [BNXT_ULP_CLASS_HID_8928] = 4323, - [BNXT_ULP_CLASS_HID_8ef4] = 4324, - [BNXT_ULP_CLASS_HID_497ec] = 4325, - [BNXT_ULP_CLASS_HID_49da8] = 4326, - [BNXT_ULP_CLASS_HID_4dc84] = 4327, - [BNXT_ULP_CLASS_HID_4c240] = 4328, - [BNXT_ULP_CLASS_HID_4b810] = 4329, - [BNXT_ULP_CLASS_HID_4a1dc] = 4330, - [BNXT_ULP_CLASS_HID_485fc] = 4331, - [BNXT_ULP_CLASS_HID_48bb8] = 4332, - [BNXT_ULP_CLASS_HID_1b0d8] = 4333, - [BNXT_ULP_CLASS_HID_1b6e4] = 4334, - [BNXT_ULP_CLASS_HID_19a84] = 4335, - [BNXT_ULP_CLASS_HID_18040] = 4336, - [BNXT_ULP_CLASS_HID_1d54c] = 4337, - [BNXT_ULP_CLASS_HID_1db08] = 4338, - [BNXT_ULP_CLASS_HID_1bf28] = 4339, - [BNXT_ULP_CLASS_HID_1a4f4] = 4340, - [BNXT_ULP_CLASS_HID_58dec] = 4341, - [BNXT_ULP_CLASS_HID_5b3a8] = 4342, - [BNXT_ULP_CLASS_HID_59748] = 4343, - [BNXT_ULP_CLASS_HID_59d14] = 4344, - [BNXT_ULP_CLASS_HID_5ae10] = 4345, - [BNXT_ULP_CLASS_HID_5d7dc] = 4346, - [BNXT_ULP_CLASS_HID_5bbfc] = 4347, - [BNXT_ULP_CLASS_HID_5a1b8] = 4348, - [BNXT_ULP_CLASS_HID_c158] = 4349, - [BNXT_ULP_CLASS_HID_c764] = 4350, - [BNXT_ULP_CLASS_HID_c670] = 4351, - [BNXT_ULP_CLASS_HID_d0c0] = 4352, - [BNXT_ULP_CLASS_HID_e5cc] = 4353, - [BNXT_ULP_CLASS_HID_eb88] = 4354, - [BNXT_ULP_CLASS_HID_cfa8] = 4355, - [BNXT_ULP_CLASS_HID_f574] = 4356, - [BNXT_ULP_CLASS_HID_4da6c] = 4357, - [BNXT_ULP_CLASS_HID_4c028] = 4358, - [BNXT_ULP_CLASS_HID_4c304] = 4359, - [BNXT_ULP_CLASS_HID_4c8c0] = 4360, - [BNXT_ULP_CLASS_HID_4fe90] = 4361, - [BNXT_ULP_CLASS_HID_4e45c] = 4362, - [BNXT_ULP_CLASS_HID_4c87c] = 4363, - [BNXT_ULP_CLASS_HID_4ce38] = 4364, - [BNXT_ULP_CLASS_HID_1f758] = 4365, - [BNXT_ULP_CLASS_HID_1fd64] = 4366, - [BNXT_ULP_CLASS_HID_1c104] = 4367, - [BNXT_ULP_CLASS_HID_1c6c0] = 4368, - [BNXT_ULP_CLASS_HID_1dbcc] = 4369, - [BNXT_ULP_CLASS_HID_1c188] = 4370, - [BNXT_ULP_CLASS_HID_1e5a8] = 4371, - [BNXT_ULP_CLASS_HID_1eb74] = 4372, - [BNXT_ULP_CLASS_HID_5f06c] = 4373, - [BNXT_ULP_CLASS_HID_5f628] = 4374, - [BNXT_ULP_CLASS_HID_5ddc8] = 4375, - [BNXT_ULP_CLASS_HID_5c394] = 4376, - [BNXT_ULP_CLASS_HID_5d490] = 4377, - [BNXT_ULP_CLASS_HID_5da5c] = 4378, - [BNXT_ULP_CLASS_HID_5fe7c] = 4379, - [BNXT_ULP_CLASS_HID_5e438] = 4380, - [BNXT_ULP_CLASS_HID_bc18] = 4381, - [BNXT_ULP_CLASS_HID_a224] = 4382, - [BNXT_ULP_CLASS_HID_e530] = 4383, - [BNXT_ULP_CLASS_HID_eafc] = 4384, - [BNXT_ULP_CLASS_HID_a08c] = 4385, - [BNXT_ULP_CLASS_HID_a648] = 4386, - [BNXT_ULP_CLASS_HID_aa68] = 4387, - [BNXT_ULP_CLASS_HID_b034] = 4388, - [BNXT_ULP_CLASS_HID_4b92c] = 4389, - [BNXT_ULP_CLASS_HID_4bee8] = 4390, - [BNXT_ULP_CLASS_HID_4e1c4] = 4391, - [BNXT_ULP_CLASS_HID_4e780] = 4392, - [BNXT_ULP_CLASS_HID_4bd50] = 4393, - [BNXT_ULP_CLASS_HID_4a31c] = 4394, - [BNXT_ULP_CLASS_HID_4a73c] = 4395, - [BNXT_ULP_CLASS_HID_4acf8] = 4396, - [BNXT_ULP_CLASS_HID_1b218] = 4397, - [BNXT_ULP_CLASS_HID_1b824] = 4398, - [BNXT_ULP_CLASS_HID_1bfc4] = 4399, - [BNXT_ULP_CLASS_HID_1a580] = 4400, - [BNXT_ULP_CLASS_HID_1f68c] = 4401, - [BNXT_ULP_CLASS_HID_1fc48] = 4402, - [BNXT_ULP_CLASS_HID_1a068] = 4403, - [BNXT_ULP_CLASS_HID_1a634] = 4404, - [BNXT_ULP_CLASS_HID_5af2c] = 4405, - [BNXT_ULP_CLASS_HID_5b4e8] = 4406, - [BNXT_ULP_CLASS_HID_5b888] = 4407, - [BNXT_ULP_CLASS_HID_5be54] = 4408, - [BNXT_ULP_CLASS_HID_5f350] = 4409, - [BNXT_ULP_CLASS_HID_5f91c] = 4410, - [BNXT_ULP_CLASS_HID_5bd3c] = 4411, - [BNXT_ULP_CLASS_HID_5a2f8] = 4412, - [BNXT_ULP_CLASS_HID_e298] = 4413, - [BNXT_ULP_CLASS_HID_e8a4] = 4414, - [BNXT_ULP_CLASS_HID_ebb0] = 4415, - [BNXT_ULP_CLASS_HID_f200] = 4416, - [BNXT_ULP_CLASS_HID_e70c] = 4417, - [BNXT_ULP_CLASS_HID_ecc8] = 4418, - [BNXT_ULP_CLASS_HID_f0e8] = 4419, - [BNXT_ULP_CLASS_HID_f6b4] = 4420, - [BNXT_ULP_CLASS_HID_4ffac] = 4421, - [BNXT_ULP_CLASS_HID_4e568] = 4422, - [BNXT_ULP_CLASS_HID_4e444] = 4423, - [BNXT_ULP_CLASS_HID_4ea00] = 4424, - [BNXT_ULP_CLASS_HID_4e3d0] = 4425, - [BNXT_ULP_CLASS_HID_4e99c] = 4426, - [BNXT_ULP_CLASS_HID_4edbc] = 4427, - [BNXT_ULP_CLASS_HID_4f378] = 4428, - [BNXT_ULP_CLASS_HID_1f898] = 4429, - [BNXT_ULP_CLASS_HID_1fea4] = 4430, - [BNXT_ULP_CLASS_HID_1e244] = 4431, - [BNXT_ULP_CLASS_HID_1e800] = 4432, - [BNXT_ULP_CLASS_HID_1fd0c] = 4433, - [BNXT_ULP_CLASS_HID_1e2c8] = 4434, - [BNXT_ULP_CLASS_HID_1e6e8] = 4435, - [BNXT_ULP_CLASS_HID_1ecb4] = 4436, - [BNXT_ULP_CLASS_HID_5f5ac] = 4437, - [BNXT_ULP_CLASS_HID_5fb68] = 4438, - [BNXT_ULP_CLASS_HID_5ff08] = 4439, - [BNXT_ULP_CLASS_HID_5e4d4] = 4440, - [BNXT_ULP_CLASS_HID_5f9d0] = 4441, - [BNXT_ULP_CLASS_HID_5ff9c] = 4442, - [BNXT_ULP_CLASS_HID_5e3bc] = 4443, - [BNXT_ULP_CLASS_HID_5e978] = 4444, - [BNXT_ULP_CLASS_HID_34f6] = 4445, - [BNXT_ULP_CLASS_HID_3a3a] = 4446, - [BNXT_ULP_CLASS_HID_541e] = 4447, - [BNXT_ULP_CLASS_HID_5a22] = 4448, - [BNXT_ULP_CLASS_HID_34fe] = 4449, - [BNXT_ULP_CLASS_HID_3a32] = 4450, - [BNXT_ULP_CLASS_HID_4a42] = 4451, - [BNXT_ULP_CLASS_HID_14d2] = 4452, - [BNXT_ULP_CLASS_HID_34c8] = 4453, - [BNXT_ULP_CLASS_HID_3a04] = 4454, - [BNXT_ULP_CLASS_HID_1e64] = 4455, - [BNXT_ULP_CLASS_HID_07a0] = 4456, - [BNXT_ULP_CLASS_HID_595c] = 4457, - [BNXT_ULP_CLASS_HID_5e98] = 4458, - [BNXT_ULP_CLASS_HID_22f8] = 4459, - [BNXT_ULP_CLASS_HID_2834] = 4460, - [BNXT_ULP_CLASS_HID_0398] = 4461, - [BNXT_ULP_CLASS_HID_09d4] = 4462, - [BNXT_ULP_CLASS_HID_48c0] = 4463, - [BNXT_ULP_CLASS_HID_1370] = 4464, - [BNXT_ULP_CLASS_HID_246c] = 4465, - [BNXT_ULP_CLASS_HID_2da8] = 4466, - [BNXT_ULP_CLASS_HID_3188] = 4467, - [BNXT_ULP_CLASS_HID_37c4] = 4468, - [BNXT_ULP_CLASS_HID_34f0] = 4469, - [BNXT_ULP_CLASS_HID_3a3c] = 4470, - [BNXT_ULP_CLASS_HID_1e5c] = 4471, - [BNXT_ULP_CLASS_HID_0798] = 4472, - [BNXT_ULP_CLASS_HID_5964] = 4473, - [BNXT_ULP_CLASS_HID_5ea0] = 4474, - [BNXT_ULP_CLASS_HID_22c0] = 4475, - [BNXT_ULP_CLASS_HID_280c] = 4476, - [BNXT_ULP_CLASS_HID_43104] = 4477, - [BNXT_ULP_CLASS_HID_43740] = 4478, - [BNXT_ULP_CLASS_HID_41b60] = 4479, - [BNXT_ULP_CLASS_HID_400ac] = 4480, - [BNXT_ULP_CLASS_HID_455a8] = 4481, - [BNXT_ULP_CLASS_HID_45bf4] = 4482, - [BNXT_ULP_CLASS_HID_43f14] = 4483, - [BNXT_ULP_CLASS_HID_42550] = 4484, - [BNXT_ULP_CLASS_HID_34d6] = 4485, - [BNXT_ULP_CLASS_HID_3a1a] = 4486, - [BNXT_ULP_CLASS_HID_543e] = 4487, - [BNXT_ULP_CLASS_HID_5a02] = 4488, - [BNXT_ULP_CLASS_HID_34de] = 4489, - [BNXT_ULP_CLASS_HID_3a12] = 4490, - [BNXT_ULP_CLASS_HID_4a62] = 4491, - [BNXT_ULP_CLASS_HID_14f2] = 4492, - [BNXT_ULP_CLASS_HID_34b6] = 4493, - [BNXT_ULP_CLASS_HID_3a7a] = 4494, - [BNXT_ULP_CLASS_HID_545e] = 4495, - [BNXT_ULP_CLASS_HID_5a62] = 4496, - [BNXT_ULP_CLASS_HID_34be] = 4497, - [BNXT_ULP_CLASS_HID_3a72] = 4498, - [BNXT_ULP_CLASS_HID_4a02] = 4499, - [BNXT_ULP_CLASS_HID_1492] = 4500, - [BNXT_ULP_CLASS_HID_34a8] = 4501, - [BNXT_ULP_CLASS_HID_3a64] = 4502, - [BNXT_ULP_CLASS_HID_1e04] = 4503, - [BNXT_ULP_CLASS_HID_07c0] = 4504, - [BNXT_ULP_CLASS_HID_593c] = 4505, - [BNXT_ULP_CLASS_HID_5ef8] = 4506, - [BNXT_ULP_CLASS_HID_2298] = 4507, - [BNXT_ULP_CLASS_HID_2854] = 4508, - [BNXT_ULP_CLASS_HID_03f8] = 4509, - [BNXT_ULP_CLASS_HID_09b4] = 4510, - [BNXT_ULP_CLASS_HID_48a0] = 4511, - [BNXT_ULP_CLASS_HID_1310] = 4512, - [BNXT_ULP_CLASS_HID_240c] = 4513, - [BNXT_ULP_CLASS_HID_2dc8] = 4514, - [BNXT_ULP_CLASS_HID_31e8] = 4515, - [BNXT_ULP_CLASS_HID_37a4] = 4516, - [BNXT_ULP_CLASS_HID_34d0] = 4517, - [BNXT_ULP_CLASS_HID_3a1c] = 4518, - [BNXT_ULP_CLASS_HID_1e7c] = 4519, - [BNXT_ULP_CLASS_HID_07b8] = 4520, - [BNXT_ULP_CLASS_HID_5944] = 4521, - [BNXT_ULP_CLASS_HID_5e80] = 4522, - [BNXT_ULP_CLASS_HID_22e0] = 4523, - [BNXT_ULP_CLASS_HID_282c] = 4524, - [BNXT_ULP_CLASS_HID_43124] = 4525, - [BNXT_ULP_CLASS_HID_43760] = 4526, - [BNXT_ULP_CLASS_HID_41b40] = 4527, - [BNXT_ULP_CLASS_HID_4008c] = 4528, - [BNXT_ULP_CLASS_HID_45588] = 4529, - [BNXT_ULP_CLASS_HID_45bd4] = 4530, - [BNXT_ULP_CLASS_HID_43f34] = 4531, - [BNXT_ULP_CLASS_HID_42570] = 4532, - [BNXT_ULP_CLASS_HID_3488] = 4533, - [BNXT_ULP_CLASS_HID_3a44] = 4534, - [BNXT_ULP_CLASS_HID_1e24] = 4535, - [BNXT_ULP_CLASS_HID_07e0] = 4536, - [BNXT_ULP_CLASS_HID_591c] = 4537, - [BNXT_ULP_CLASS_HID_5ed8] = 4538, - [BNXT_ULP_CLASS_HID_22b8] = 4539, - [BNXT_ULP_CLASS_HID_2874] = 4540, - [BNXT_ULP_CLASS_HID_03d8] = 4541, - [BNXT_ULP_CLASS_HID_0994] = 4542, - [BNXT_ULP_CLASS_HID_4880] = 4543, - [BNXT_ULP_CLASS_HID_1330] = 4544, - [BNXT_ULP_CLASS_HID_242c] = 4545, - [BNXT_ULP_CLASS_HID_2de8] = 4546, - [BNXT_ULP_CLASS_HID_31c8] = 4547, - [BNXT_ULP_CLASS_HID_3784] = 4548, - [BNXT_ULP_CLASS_HID_34b0] = 4549, - [BNXT_ULP_CLASS_HID_3a7c] = 4550, - [BNXT_ULP_CLASS_HID_1e1c] = 4551, - [BNXT_ULP_CLASS_HID_07d8] = 4552, - [BNXT_ULP_CLASS_HID_5924] = 4553, - [BNXT_ULP_CLASS_HID_5ee0] = 4554, - [BNXT_ULP_CLASS_HID_2280] = 4555, - [BNXT_ULP_CLASS_HID_284c] = 4556, - [BNXT_ULP_CLASS_HID_43144] = 4557, - [BNXT_ULP_CLASS_HID_43700] = 4558, - [BNXT_ULP_CLASS_HID_41b20] = 4559, - [BNXT_ULP_CLASS_HID_400ec] = 4560, - [BNXT_ULP_CLASS_HID_455e8] = 4561, - [BNXT_ULP_CLASS_HID_45bb4] = 4562, - [BNXT_ULP_CLASS_HID_43f54] = 4563, - [BNXT_ULP_CLASS_HID_42510] = 4564 + [BNXT_ULP_CLASS_HID_55dd] = 1, + [BNXT_ULP_CLASS_HID_1df1] = 2, + [BNXT_ULP_CLASS_HID_3e55] = 3, + [BNXT_ULP_CLASS_HID_0649] = 4, + [BNXT_ULP_CLASS_HID_1011] = 5, + [BNXT_ULP_CLASS_HID_40e9] = 6, + [BNXT_ULP_CLASS_HID_3e99] = 7, + [BNXT_ULP_CLASS_HID_06ad] = 8, + [BNXT_ULP_CLASS_HID_38c7] = 9, + [BNXT_ULP_CLASS_HID_00fb] = 10, + [BNXT_ULP_CLASS_HID_24d3] = 11, + [BNXT_ULP_CLASS_HID_559b] = 12, + [BNXT_ULP_CLASS_HID_5003] = 13, + [BNXT_ULP_CLASS_HID_1837] = 14, + [BNXT_ULP_CLASS_HID_3bef] = 15, + [BNXT_ULP_CLASS_HID_0403] = 16, + [BNXT_ULP_CLASS_HID_3d3f] = 17, + [BNXT_ULP_CLASS_HID_0543] = 18, + [BNXT_ULP_CLASS_HID_292b] = 19, + [BNXT_ULP_CLASS_HID_59e3] = 20, + [BNXT_ULP_CLASS_HID_5d3b] = 21, + [BNXT_ULP_CLASS_HID_254f] = 22, + [BNXT_ULP_CLASS_HID_4917] = 23, + [BNXT_ULP_CLASS_HID_113b] = 24, + [BNXT_ULP_CLASS_HID_55fd] = 25, + [BNXT_ULP_CLASS_HID_1dd1] = 26, + [BNXT_ULP_CLASS_HID_3e75] = 27, + [BNXT_ULP_CLASS_HID_0669] = 28, + [BNXT_ULP_CLASS_HID_1ba1] = 29, + [BNXT_ULP_CLASS_HID_4c69] = 30, + [BNXT_ULP_CLASS_HID_0439] = 31, + [BNXT_ULP_CLASS_HID_34e1] = 32, + [BNXT_ULP_CLASS_HID_0465] = 33, + [BNXT_ULP_CLASS_HID_352d] = 34, + [BNXT_ULP_CLASS_HID_55b1] = 35, + [BNXT_ULP_CLASS_HID_1da5] = 36, + [BNXT_ULP_CLASS_HID_32fd] = 37, + [BNXT_ULP_CLASS_HID_63a5] = 38, + [BNXT_ULP_CLASS_HID_1b75] = 39, + [BNXT_ULP_CLASS_HID_4c3d] = 40, + [BNXT_ULP_CLASS_HID_1031] = 41, + [BNXT_ULP_CLASS_HID_40c9] = 42, + [BNXT_ULP_CLASS_HID_3eb9] = 43, + [BNXT_ULP_CLASS_HID_068d] = 44, + [BNXT_ULP_CLASS_HID_5039] = 45, + [BNXT_ULP_CLASS_HID_180d] = 46, + [BNXT_ULP_CLASS_HID_15fd] = 47, + [BNXT_ULP_CLASS_HID_46b5] = 48, + [BNXT_ULP_CLASS_HID_303d] = 49, + [BNXT_ULP_CLASS_HID_60f5] = 50, + [BNXT_ULP_CLASS_HID_5ea5] = 51, + [BNXT_ULP_CLASS_HID_2689] = 52, + [BNXT_ULP_CLASS_HID_0771] = 53, + [BNXT_ULP_CLASS_HID_3809] = 54, + [BNXT_ULP_CLASS_HID_35f9] = 55, + [BNXT_ULP_CLASS_HID_66b1] = 56, + [BNXT_ULP_CLASS_HID_559d] = 57, + [BNXT_ULP_CLASS_HID_1db1] = 58, + [BNXT_ULP_CLASS_HID_3e15] = 59, + [BNXT_ULP_CLASS_HID_0609] = 60, + [BNXT_ULP_CLASS_HID_1bc1] = 61, + [BNXT_ULP_CLASS_HID_4c09] = 62, + [BNXT_ULP_CLASS_HID_0459] = 63, + [BNXT_ULP_CLASS_HID_3481] = 64, + [BNXT_ULP_CLASS_HID_0405] = 65, + [BNXT_ULP_CLASS_HID_354d] = 66, + [BNXT_ULP_CLASS_HID_55d1] = 67, + [BNXT_ULP_CLASS_HID_1dc5] = 68, + [BNXT_ULP_CLASS_HID_329d] = 69, + [BNXT_ULP_CLASS_HID_63c5] = 70, + [BNXT_ULP_CLASS_HID_1b15] = 71, + [BNXT_ULP_CLASS_HID_4c5d] = 72, + [BNXT_ULP_CLASS_HID_1051] = 73, + [BNXT_ULP_CLASS_HID_40a9] = 74, + [BNXT_ULP_CLASS_HID_3ed9] = 75, + [BNXT_ULP_CLASS_HID_06ed] = 76, + [BNXT_ULP_CLASS_HID_5059] = 77, + [BNXT_ULP_CLASS_HID_186d] = 78, + [BNXT_ULP_CLASS_HID_159d] = 79, + [BNXT_ULP_CLASS_HID_46d5] = 80, + [BNXT_ULP_CLASS_HID_305d] = 81, + [BNXT_ULP_CLASS_HID_6095] = 82, + [BNXT_ULP_CLASS_HID_5ec5] = 83, + [BNXT_ULP_CLASS_HID_26e9] = 84, + [BNXT_ULP_CLASS_HID_0711] = 85, + [BNXT_ULP_CLASS_HID_3869] = 86, + [BNXT_ULP_CLASS_HID_3599] = 87, + [BNXT_ULP_CLASS_HID_66d1] = 88, + [BNXT_ULP_CLASS_HID_38e7] = 89, + [BNXT_ULP_CLASS_HID_00db] = 90, + [BNXT_ULP_CLASS_HID_24f3] = 91, + [BNXT_ULP_CLASS_HID_55bb] = 92, + [BNXT_ULP_CLASS_HID_5023] = 93, + [BNXT_ULP_CLASS_HID_1817] = 94, + [BNXT_ULP_CLASS_HID_3bcf] = 95, + [BNXT_ULP_CLASS_HID_0423] = 96, + [BNXT_ULP_CLASS_HID_58e3] = 97, + [BNXT_ULP_CLASS_HID_20d7] = 98, + [BNXT_ULP_CLASS_HID_448f] = 99, + [BNXT_ULP_CLASS_HID_0ce3] = 100, + [BNXT_ULP_CLASS_HID_076b] = 101, + [BNXT_ULP_CLASS_HID_3813] = 102, + [BNXT_ULP_CLASS_HID_5bcb] = 103, + [BNXT_ULP_CLASS_HID_243f] = 104, + [BNXT_ULP_CLASS_HID_144b] = 105, + [BNXT_ULP_CLASS_HID_4573] = 106, + [BNXT_ULP_CLASS_HID_0057] = 107, + [BNXT_ULP_CLASS_HID_311f] = 108, + [BNXT_ULP_CLASS_HID_2b87] = 109, + [BNXT_ULP_CLASS_HID_5c4f] = 110, + [BNXT_ULP_CLASS_HID_1793] = 111, + [BNXT_ULP_CLASS_HID_485b] = 112, + [BNXT_ULP_CLASS_HID_3447] = 113, + [BNXT_ULP_CLASS_HID_650f] = 114, + [BNXT_ULP_CLASS_HID_2053] = 115, + [BNXT_ULP_CLASS_HID_511b] = 116, + [BNXT_ULP_CLASS_HID_4b83] = 117, + [BNXT_ULP_CLASS_HID_13f7] = 118, + [BNXT_ULP_CLASS_HID_37af] = 119, + [BNXT_ULP_CLASS_HID_6857] = 120, + [BNXT_ULP_CLASS_HID_3d1f] = 121, + [BNXT_ULP_CLASS_HID_0563] = 122, + [BNXT_ULP_CLASS_HID_290b] = 123, + [BNXT_ULP_CLASS_HID_59c3] = 124, + [BNXT_ULP_CLASS_HID_5d1b] = 125, + [BNXT_ULP_CLASS_HID_256f] = 126, + [BNXT_ULP_CLASS_HID_4937] = 127, + [BNXT_ULP_CLASS_HID_111b] = 128, + [BNXT_ULP_CLASS_HID_5f4b] = 129, + [BNXT_ULP_CLASS_HID_275f] = 130, + [BNXT_ULP_CLASS_HID_4b67] = 131, + [BNXT_ULP_CLASS_HID_134b] = 132, + [BNXT_ULP_CLASS_HID_1683] = 133, + [BNXT_ULP_CLASS_HID_475b] = 134, + [BNXT_ULP_CLASS_HID_02bf] = 135, + [BNXT_ULP_CLASS_HID_3377] = 136, + [BNXT_ULP_CLASS_HID_19db] = 137, + [BNXT_ULP_CLASS_HID_4a93] = 138, + [BNXT_ULP_CLASS_HID_05f7] = 139, + [BNXT_ULP_CLASS_HID_368f] = 140, + [BNXT_ULP_CLASS_HID_39c7] = 141, + [BNXT_ULP_CLASS_HID_022b] = 142, + [BNXT_ULP_CLASS_HID_25f3] = 143, + [BNXT_ULP_CLASS_HID_568b] = 144, + [BNXT_ULP_CLASS_HID_3c37] = 145, + [BNXT_ULP_CLASS_HID_041b] = 146, + [BNXT_ULP_CLASS_HID_2823] = 147, + [BNXT_ULP_CLASS_HID_58fb] = 148, + [BNXT_ULP_CLASS_HID_5c33] = 149, + [BNXT_ULP_CLASS_HID_2407] = 150, + [BNXT_ULP_CLASS_HID_482f] = 151, + [BNXT_ULP_CLASS_HID_1033] = 152, + [BNXT_ULP_CLASS_HID_3887] = 153, + [BNXT_ULP_CLASS_HID_00bb] = 154, + [BNXT_ULP_CLASS_HID_2493] = 155, + [BNXT_ULP_CLASS_HID_55db] = 156, + [BNXT_ULP_CLASS_HID_5043] = 157, + [BNXT_ULP_CLASS_HID_1877] = 158, + [BNXT_ULP_CLASS_HID_3baf] = 159, + [BNXT_ULP_CLASS_HID_0443] = 160, + [BNXT_ULP_CLASS_HID_5883] = 161, + [BNXT_ULP_CLASS_HID_20b7] = 162, + [BNXT_ULP_CLASS_HID_44ef] = 163, + [BNXT_ULP_CLASS_HID_0c83] = 164, + [BNXT_ULP_CLASS_HID_070b] = 165, + [BNXT_ULP_CLASS_HID_3873] = 166, + [BNXT_ULP_CLASS_HID_5bab] = 167, + [BNXT_ULP_CLASS_HID_245f] = 168, + [BNXT_ULP_CLASS_HID_142b] = 169, + [BNXT_ULP_CLASS_HID_4513] = 170, + [BNXT_ULP_CLASS_HID_0037] = 171, + [BNXT_ULP_CLASS_HID_317f] = 172, + [BNXT_ULP_CLASS_HID_2be7] = 173, + [BNXT_ULP_CLASS_HID_5c2f] = 174, + [BNXT_ULP_CLASS_HID_17f3] = 175, + [BNXT_ULP_CLASS_HID_483b] = 176, + [BNXT_ULP_CLASS_HID_3427] = 177, + [BNXT_ULP_CLASS_HID_656f] = 178, + [BNXT_ULP_CLASS_HID_2033] = 179, + [BNXT_ULP_CLASS_HID_517b] = 180, + [BNXT_ULP_CLASS_HID_4be3] = 181, + [BNXT_ULP_CLASS_HID_1397] = 182, + [BNXT_ULP_CLASS_HID_37cf] = 183, + [BNXT_ULP_CLASS_HID_6837] = 184, + [BNXT_ULP_CLASS_HID_3d7f] = 185, + [BNXT_ULP_CLASS_HID_0503] = 186, + [BNXT_ULP_CLASS_HID_296b] = 187, + [BNXT_ULP_CLASS_HID_59a3] = 188, + [BNXT_ULP_CLASS_HID_5d7b] = 189, + [BNXT_ULP_CLASS_HID_250f] = 190, + [BNXT_ULP_CLASS_HID_4957] = 191, + [BNXT_ULP_CLASS_HID_117b] = 192, + [BNXT_ULP_CLASS_HID_5f2b] = 193, + [BNXT_ULP_CLASS_HID_273f] = 194, + [BNXT_ULP_CLASS_HID_4b07] = 195, + [BNXT_ULP_CLASS_HID_132b] = 196, + [BNXT_ULP_CLASS_HID_16e3] = 197, + [BNXT_ULP_CLASS_HID_473b] = 198, + [BNXT_ULP_CLASS_HID_02df] = 199, + [BNXT_ULP_CLASS_HID_3317] = 200, + [BNXT_ULP_CLASS_HID_19bb] = 201, + [BNXT_ULP_CLASS_HID_4af3] = 202, + [BNXT_ULP_CLASS_HID_0597] = 203, + [BNXT_ULP_CLASS_HID_36ef] = 204, + [BNXT_ULP_CLASS_HID_39a7] = 205, + [BNXT_ULP_CLASS_HID_024b] = 206, + [BNXT_ULP_CLASS_HID_2593] = 207, + [BNXT_ULP_CLASS_HID_56eb] = 208, + [BNXT_ULP_CLASS_HID_3c57] = 209, + [BNXT_ULP_CLASS_HID_047b] = 210, + [BNXT_ULP_CLASS_HID_2843] = 211, + [BNXT_ULP_CLASS_HID_589b] = 212, + [BNXT_ULP_CLASS_HID_5c53] = 213, + [BNXT_ULP_CLASS_HID_2467] = 214, + [BNXT_ULP_CLASS_HID_484f] = 215, + [BNXT_ULP_CLASS_HID_1053] = 216, + [BNXT_ULP_CLASS_HID_5ce1] = 217, + [BNXT_ULP_CLASS_HID_4579] = 218, + [BNXT_ULP_CLASS_HID_1735] = 219, + [BNXT_ULP_CLASS_HID_45bd] = 220, + [BNXT_ULP_CLASS_HID_3feb] = 221, + [BNXT_ULP_CLASS_HID_2bf7] = 222, + [BNXT_ULP_CLASS_HID_5727] = 223, + [BNXT_ULP_CLASS_HID_4333] = 224, + [BNXT_ULP_CLASS_HID_4453] = 225, + [BNXT_ULP_CLASS_HID_304f] = 226, + [BNXT_ULP_CLASS_HID_645f] = 227, + [BNXT_ULP_CLASS_HID_504b] = 228, + [BNXT_ULP_CLASS_HID_5cc1] = 229, + [BNXT_ULP_CLASS_HID_4559] = 230, + [BNXT_ULP_CLASS_HID_2285] = 231, + [BNXT_ULP_CLASS_HID_0b1d] = 232, + [BNXT_ULP_CLASS_HID_0b49] = 233, + [BNXT_ULP_CLASS_HID_5c95] = 234, + [BNXT_ULP_CLASS_HID_39c1] = 235, + [BNXT_ULP_CLASS_HID_2259] = 236, + [BNXT_ULP_CLASS_HID_1715] = 237, + [BNXT_ULP_CLASS_HID_459d] = 238, + [BNXT_ULP_CLASS_HID_571d] = 239, + [BNXT_ULP_CLASS_HID_1cd1] = 240, + [BNXT_ULP_CLASS_HID_3711] = 241, + [BNXT_ULP_CLASS_HID_6599] = 242, + [BNXT_ULP_CLASS_HID_0e55] = 243, + [BNXT_ULP_CLASS_HID_3cdd] = 244, + [BNXT_ULP_CLASS_HID_5ca1] = 245, + [BNXT_ULP_CLASS_HID_4539] = 246, + [BNXT_ULP_CLASS_HID_22e5] = 247, + [BNXT_ULP_CLASS_HID_0b7d] = 248, + [BNXT_ULP_CLASS_HID_0b29] = 249, + [BNXT_ULP_CLASS_HID_5cf5] = 250, + [BNXT_ULP_CLASS_HID_39a1] = 251, + [BNXT_ULP_CLASS_HID_2239] = 252, + [BNXT_ULP_CLASS_HID_1775] = 253, + [BNXT_ULP_CLASS_HID_45fd] = 254, + [BNXT_ULP_CLASS_HID_577d] = 255, + [BNXT_ULP_CLASS_HID_1cb1] = 256, + [BNXT_ULP_CLASS_HID_3771] = 257, + [BNXT_ULP_CLASS_HID_65f9] = 258, + [BNXT_ULP_CLASS_HID_0e35] = 259, + [BNXT_ULP_CLASS_HID_3cbd] = 260, + [BNXT_ULP_CLASS_HID_3fcb] = 261, + [BNXT_ULP_CLASS_HID_2bd7] = 262, + [BNXT_ULP_CLASS_HID_5707] = 263, + [BNXT_ULP_CLASS_HID_4313] = 264, + [BNXT_ULP_CLASS_HID_5fc7] = 265, + [BNXT_ULP_CLASS_HID_4bd3] = 266, + [BNXT_ULP_CLASS_HID_0e4f] = 267, + [BNXT_ULP_CLASS_HID_632f] = 268, + [BNXT_ULP_CLASS_HID_1baf] = 269, + [BNXT_ULP_CLASS_HID_07bb] = 270, + [BNXT_ULP_CLASS_HID_32eb] = 271, + [BNXT_ULP_CLASS_HID_1ef7] = 272, + [BNXT_ULP_CLASS_HID_3bab] = 273, + [BNXT_ULP_CLASS_HID_27b7] = 274, + [BNXT_ULP_CLASS_HID_52e7] = 275, + [BNXT_ULP_CLASS_HID_3ef3] = 276, + [BNXT_ULP_CLASS_HID_4473] = 277, + [BNXT_ULP_CLASS_HID_306f] = 278, + [BNXT_ULP_CLASS_HID_647f] = 279, + [BNXT_ULP_CLASS_HID_506b] = 280, + [BNXT_ULP_CLASS_HID_66af] = 281, + [BNXT_ULP_CLASS_HID_525b] = 282, + [BNXT_ULP_CLASS_HID_1de7] = 283, + [BNXT_ULP_CLASS_HID_0993] = 284, + [BNXT_ULP_CLASS_HID_213f] = 285, + [BNXT_ULP_CLASS_HID_0d2b] = 286, + [BNXT_ULP_CLASS_HID_413b] = 287, + [BNXT_ULP_CLASS_HID_2cd7] = 288, + [BNXT_ULP_CLASS_HID_436b] = 289, + [BNXT_ULP_CLASS_HID_2f07] = 290, + [BNXT_ULP_CLASS_HID_6317] = 291, + [BNXT_ULP_CLASS_HID_4f03] = 292, + [BNXT_ULP_CLASS_HID_3fab] = 293, + [BNXT_ULP_CLASS_HID_2bb7] = 294, + [BNXT_ULP_CLASS_HID_5767] = 295, + [BNXT_ULP_CLASS_HID_4373] = 296, + [BNXT_ULP_CLASS_HID_5fa7] = 297, + [BNXT_ULP_CLASS_HID_4bb3] = 298, + [BNXT_ULP_CLASS_HID_0e2f] = 299, + [BNXT_ULP_CLASS_HID_634f] = 300, + [BNXT_ULP_CLASS_HID_1bcf] = 301, + [BNXT_ULP_CLASS_HID_07db] = 302, + [BNXT_ULP_CLASS_HID_328b] = 303, + [BNXT_ULP_CLASS_HID_1e97] = 304, + [BNXT_ULP_CLASS_HID_3bcb] = 305, + [BNXT_ULP_CLASS_HID_27d7] = 306, + [BNXT_ULP_CLASS_HID_5287] = 307, + [BNXT_ULP_CLASS_HID_3e93] = 308, + [BNXT_ULP_CLASS_HID_4413] = 309, + [BNXT_ULP_CLASS_HID_300f] = 310, + [BNXT_ULP_CLASS_HID_641f] = 311, + [BNXT_ULP_CLASS_HID_500b] = 312, + [BNXT_ULP_CLASS_HID_66cf] = 313, + [BNXT_ULP_CLASS_HID_523b] = 314, + [BNXT_ULP_CLASS_HID_1d87] = 315, + [BNXT_ULP_CLASS_HID_09f3] = 316, + [BNXT_ULP_CLASS_HID_215f] = 317, + [BNXT_ULP_CLASS_HID_0d4b] = 318, + [BNXT_ULP_CLASS_HID_415b] = 319, + [BNXT_ULP_CLASS_HID_2cb7] = 320, + [BNXT_ULP_CLASS_HID_430b] = 321, + [BNXT_ULP_CLASS_HID_2f67] = 322, + [BNXT_ULP_CLASS_HID_6377] = 323, + [BNXT_ULP_CLASS_HID_4f63] = 324, + [BNXT_ULP_CLASS_HID_29b5] = 325, + [BNXT_ULP_CLASS_HID_29ad] = 326, + [BNXT_ULP_CLASS_HID_29b7] = 327, + [BNXT_ULP_CLASS_HID_1583] = 328, + [BNXT_ULP_CLASS_HID_29af] = 329, + [BNXT_ULP_CLASS_HID_159b] = 330, + [BNXT_ULP_CLASS_HID_2995] = 331, + [BNXT_ULP_CLASS_HID_298d] = 332, + [BNXT_ULP_CLASS_HID_29f5] = 333, + [BNXT_ULP_CLASS_HID_29ed] = 334, + [BNXT_ULP_CLASS_HID_2997] = 335, + [BNXT_ULP_CLASS_HID_15a3] = 336, + [BNXT_ULP_CLASS_HID_298f] = 337, + [BNXT_ULP_CLASS_HID_15bb] = 338, + [BNXT_ULP_CLASS_HID_29f7] = 339, + [BNXT_ULP_CLASS_HID_15c3] = 340, + [BNXT_ULP_CLASS_HID_29ef] = 341, + [BNXT_ULP_CLASS_HID_15db] = 342, + [BNXT_ULP_CLASS_HID_1151] = 343, + [BNXT_ULP_CLASS_HID_315d] = 344, + [BNXT_ULP_CLASS_HID_34c6] = 345, + [BNXT_ULP_CLASS_HID_0c22] = 346, + [BNXT_ULP_CLASS_HID_1cbe] = 347, + [BNXT_ULP_CLASS_HID_179a] = 348, + [BNXT_ULP_CLASS_HID_59be] = 349, + [BNXT_ULP_CLASS_HID_515a] = 350, + [BNXT_ULP_CLASS_HID_1c72] = 351, + [BNXT_ULP_CLASS_HID_171e] = 352, + [BNXT_ULP_CLASS_HID_19c8] = 353, + [BNXT_ULP_CLASS_HID_112c] = 354, + [BNXT_ULP_CLASS_HID_4d68] = 355, + [BNXT_ULP_CLASS_HID_444c] = 356, + [BNXT_ULP_CLASS_HID_0e8c] = 357, + [BNXT_ULP_CLASS_HID_09e0] = 358, + [BNXT_ULP_CLASS_HID_1af0] = 359, + [BNXT_ULP_CLASS_HID_15d4] = 360, + [BNXT_ULP_CLASS_HID_1dd0] = 361, + [BNXT_ULP_CLASS_HID_14f4] = 362, + [BNXT_ULP_CLASS_HID_70b0] = 363, + [BNXT_ULP_CLASS_HID_4854] = 364, + [BNXT_ULP_CLASS_HID_3dd4] = 365, + [BNXT_ULP_CLASS_HID_34f8] = 366, + [BNXT_ULP_CLASS_HID_09e8] = 367, + [BNXT_ULP_CLASS_HID_008c] = 368, + [BNXT_ULP_CLASS_HID_34e6] = 369, + [BNXT_ULP_CLASS_HID_0c02] = 370, + [BNXT_ULP_CLASS_HID_1c9e] = 371, + [BNXT_ULP_CLASS_HID_17ba] = 372, + [BNXT_ULP_CLASS_HID_429e] = 373, + [BNXT_ULP_CLASS_HID_5dba] = 374, + [BNXT_ULP_CLASS_HID_2a16] = 375, + [BNXT_ULP_CLASS_HID_2532] = 376, + [BNXT_ULP_CLASS_HID_2da2] = 377, + [BNXT_ULP_CLASS_HID_24fe] = 378, + [BNXT_ULP_CLASS_HID_355a] = 379, + [BNXT_ULP_CLASS_HID_0c76] = 380, + [BNXT_ULP_CLASS_HID_13e6] = 381, + [BNXT_ULP_CLASS_HID_7276] = 382, + [BNXT_ULP_CLASS_HID_42d2] = 383, + [BNXT_ULP_CLASS_HID_5dee] = 384, + [BNXT_ULP_CLASS_HID_59de] = 385, + [BNXT_ULP_CLASS_HID_513a] = 386, + [BNXT_ULP_CLASS_HID_1c12] = 387, + [BNXT_ULP_CLASS_HID_177e] = 388, + [BNXT_ULP_CLASS_HID_0e92] = 389, + [BNXT_ULP_CLASS_HID_09fe] = 390, + [BNXT_ULP_CLASS_HID_5c1a] = 391, + [BNXT_ULP_CLASS_HID_5746] = 392, + [BNXT_ULP_CLASS_HID_79da] = 393, + [BNXT_ULP_CLASS_HID_7106] = 394, + [BNXT_ULP_CLASS_HID_3c1e] = 395, + [BNXT_ULP_CLASS_HID_377a] = 396, + [BNXT_ULP_CLASS_HID_2e9e] = 397, + [BNXT_ULP_CLASS_HID_29fa] = 398, + [BNXT_ULP_CLASS_HID_14d2] = 399, + [BNXT_ULP_CLASS_HID_7742] = 400, + [BNXT_ULP_CLASS_HID_3706] = 401, + [BNXT_ULP_CLASS_HID_0fe2] = 402, + [BNXT_ULP_CLASS_HID_1f7e] = 403, + [BNXT_ULP_CLASS_HID_145a] = 404, + [BNXT_ULP_CLASS_HID_417e] = 405, + [BNXT_ULP_CLASS_HID_5e5a] = 406, + [BNXT_ULP_CLASS_HID_29f6] = 407, + [BNXT_ULP_CLASS_HID_26d2] = 408, + [BNXT_ULP_CLASS_HID_2e42] = 409, + [BNXT_ULP_CLASS_HID_271e] = 410, + [BNXT_ULP_CLASS_HID_36ba] = 411, + [BNXT_ULP_CLASS_HID_0f96] = 412, + [BNXT_ULP_CLASS_HID_1006] = 413, + [BNXT_ULP_CLASS_HID_7196] = 414, + [BNXT_ULP_CLASS_HID_4132] = 415, + [BNXT_ULP_CLASS_HID_5e0e] = 416, + [BNXT_ULP_CLASS_HID_59fe] = 417, + [BNXT_ULP_CLASS_HID_511a] = 418, + [BNXT_ULP_CLASS_HID_1c32] = 419, + [BNXT_ULP_CLASS_HID_175e] = 420, + [BNXT_ULP_CLASS_HID_0eb2] = 421, + [BNXT_ULP_CLASS_HID_09de] = 422, + [BNXT_ULP_CLASS_HID_5c3a] = 423, + [BNXT_ULP_CLASS_HID_5766] = 424, + [BNXT_ULP_CLASS_HID_79fa] = 425, + [BNXT_ULP_CLASS_HID_7126] = 426, + [BNXT_ULP_CLASS_HID_3c3e] = 427, + [BNXT_ULP_CLASS_HID_375a] = 428, + [BNXT_ULP_CLASS_HID_2ebe] = 429, + [BNXT_ULP_CLASS_HID_29da] = 430, + [BNXT_ULP_CLASS_HID_14f2] = 431, + [BNXT_ULP_CLASS_HID_7762] = 432, + [BNXT_ULP_CLASS_HID_19e8] = 433, + [BNXT_ULP_CLASS_HID_110c] = 434, + [BNXT_ULP_CLASS_HID_4d48] = 435, + [BNXT_ULP_CLASS_HID_446c] = 436, + [BNXT_ULP_CLASS_HID_0eac] = 437, + [BNXT_ULP_CLASS_HID_09c0] = 438, + [BNXT_ULP_CLASS_HID_1ad0] = 439, + [BNXT_ULP_CLASS_HID_15f4] = 440, + [BNXT_ULP_CLASS_HID_39ec] = 441, + [BNXT_ULP_CLASS_HID_3100] = 442, + [BNXT_ULP_CLASS_HID_0210] = 443, + [BNXT_ULP_CLASS_HID_1d34] = 444, + [BNXT_ULP_CLASS_HID_2ea0] = 445, + [BNXT_ULP_CLASS_HID_29c4] = 446, + [BNXT_ULP_CLASS_HID_3ad4] = 447, + [BNXT_ULP_CLASS_HID_35e8] = 448, + [BNXT_ULP_CLASS_HID_5d80] = 449, + [BNXT_ULP_CLASS_HID_54a4] = 450, + [BNXT_ULP_CLASS_HID_29b4] = 451, + [BNXT_ULP_CLASS_HID_20c8] = 452, + [BNXT_ULP_CLASS_HID_7244] = 453, + [BNXT_ULP_CLASS_HID_4d98] = 454, + [BNXT_ULP_CLASS_HID_5e68] = 455, + [BNXT_ULP_CLASS_HID_598c] = 456, + [BNXT_ULP_CLASS_HID_1248] = 457, + [BNXT_ULP_CLASS_HID_74d8] = 458, + [BNXT_ULP_CLASS_HID_49a8] = 459, + [BNXT_ULP_CLASS_HID_40cc] = 460, + [BNXT_ULP_CLASS_HID_0b0c] = 461, + [BNXT_ULP_CLASS_HID_0220] = 462, + [BNXT_ULP_CLASS_HID_1730] = 463, + [BNXT_ULP_CLASS_HID_7980] = 464, + [BNXT_ULP_CLASS_HID_1db0] = 465, + [BNXT_ULP_CLASS_HID_1494] = 466, + [BNXT_ULP_CLASS_HID_70d0] = 467, + [BNXT_ULP_CLASS_HID_4834] = 468, + [BNXT_ULP_CLASS_HID_3db4] = 469, + [BNXT_ULP_CLASS_HID_3498] = 470, + [BNXT_ULP_CLASS_HID_0988] = 471, + [BNXT_ULP_CLASS_HID_00ec] = 472, + [BNXT_ULP_CLASS_HID_3f44] = 473, + [BNXT_ULP_CLASS_HID_36a8] = 474, + [BNXT_ULP_CLASS_HID_0b58] = 475, + [BNXT_ULP_CLASS_HID_02bc] = 476, + [BNXT_ULP_CLASS_HID_5f48] = 477, + [BNXT_ULP_CLASS_HID_56ac] = 478, + [BNXT_ULP_CLASS_HID_2b5c] = 479, + [BNXT_ULP_CLASS_HID_2280] = 480, + [BNXT_ULP_CLASS_HID_4000] = 481, + [BNXT_ULP_CLASS_HID_5b64] = 482, + [BNXT_ULP_CLASS_HID_2c14] = 483, + [BNXT_ULP_CLASS_HID_2778] = 484, + [BNXT_ULP_CLASS_HID_18f8] = 485, + [BNXT_ULP_CLASS_HID_13dc] = 486, + [BNXT_ULP_CLASS_HID_4c18] = 487, + [BNXT_ULP_CLASS_HID_477c] = 488, + [BNXT_ULP_CLASS_HID_1a88] = 489, + [BNXT_ULP_CLASS_HID_15ec] = 490, + [BNXT_ULP_CLASS_HID_4e28] = 491, + [BNXT_ULP_CLASS_HID_490c] = 492, + [BNXT_ULP_CLASS_HID_3a8c] = 493, + [BNXT_ULP_CLASS_HID_35f0] = 494, + [BNXT_ULP_CLASS_HID_06e0] = 495, + [BNXT_ULP_CLASS_HID_01c4] = 496, + [BNXT_ULP_CLASS_HID_1a08] = 497, + [BNXT_ULP_CLASS_HID_12ec] = 498, + [BNXT_ULP_CLASS_HID_4ea8] = 499, + [BNXT_ULP_CLASS_HID_478c] = 500, + [BNXT_ULP_CLASS_HID_0d4c] = 501, + [BNXT_ULP_CLASS_HID_0a20] = 502, + [BNXT_ULP_CLASS_HID_1930] = 503, + [BNXT_ULP_CLASS_HID_1614] = 504, + [BNXT_ULP_CLASS_HID_3a0c] = 505, + [BNXT_ULP_CLASS_HID_32e0] = 506, + [BNXT_ULP_CLASS_HID_01f0] = 507, + [BNXT_ULP_CLASS_HID_1ed4] = 508, + [BNXT_ULP_CLASS_HID_2d40] = 509, + [BNXT_ULP_CLASS_HID_2a24] = 510, + [BNXT_ULP_CLASS_HID_3934] = 511, + [BNXT_ULP_CLASS_HID_3608] = 512, + [BNXT_ULP_CLASS_HID_5e60] = 513, + [BNXT_ULP_CLASS_HID_5744] = 514, + [BNXT_ULP_CLASS_HID_2a54] = 515, + [BNXT_ULP_CLASS_HID_2328] = 516, + [BNXT_ULP_CLASS_HID_71a4] = 517, + [BNXT_ULP_CLASS_HID_4e78] = 518, + [BNXT_ULP_CLASS_HID_5d88] = 519, + [BNXT_ULP_CLASS_HID_5a6c] = 520, + [BNXT_ULP_CLASS_HID_11a8] = 521, + [BNXT_ULP_CLASS_HID_7738] = 522, + [BNXT_ULP_CLASS_HID_4a48] = 523, + [BNXT_ULP_CLASS_HID_432c] = 524, + [BNXT_ULP_CLASS_HID_08ec] = 525, + [BNXT_ULP_CLASS_HID_01c0] = 526, + [BNXT_ULP_CLASS_HID_14d0] = 527, + [BNXT_ULP_CLASS_HID_7a60] = 528, + [BNXT_ULP_CLASS_HID_1d90] = 529, + [BNXT_ULP_CLASS_HID_14b4] = 530, + [BNXT_ULP_CLASS_HID_70f0] = 531, + [BNXT_ULP_CLASS_HID_4814] = 532, + [BNXT_ULP_CLASS_HID_3d94] = 533, + [BNXT_ULP_CLASS_HID_34b8] = 534, + [BNXT_ULP_CLASS_HID_09a8] = 535, + [BNXT_ULP_CLASS_HID_00cc] = 536, + [BNXT_ULP_CLASS_HID_3f64] = 537, + [BNXT_ULP_CLASS_HID_3688] = 538, + [BNXT_ULP_CLASS_HID_0b78] = 539, + [BNXT_ULP_CLASS_HID_029c] = 540, + [BNXT_ULP_CLASS_HID_5f68] = 541, + [BNXT_ULP_CLASS_HID_568c] = 542, + [BNXT_ULP_CLASS_HID_2b7c] = 543, + [BNXT_ULP_CLASS_HID_22a0] = 544, + [BNXT_ULP_CLASS_HID_4020] = 545, + [BNXT_ULP_CLASS_HID_5b44] = 546, + [BNXT_ULP_CLASS_HID_2c34] = 547, + [BNXT_ULP_CLASS_HID_2758] = 548, + [BNXT_ULP_CLASS_HID_18d8] = 549, + [BNXT_ULP_CLASS_HID_13fc] = 550, + [BNXT_ULP_CLASS_HID_4c38] = 551, + [BNXT_ULP_CLASS_HID_475c] = 552, + [BNXT_ULP_CLASS_HID_1aa8] = 553, + [BNXT_ULP_CLASS_HID_15cc] = 554, + [BNXT_ULP_CLASS_HID_4e08] = 555, + [BNXT_ULP_CLASS_HID_492c] = 556, + [BNXT_ULP_CLASS_HID_3aac] = 557, + [BNXT_ULP_CLASS_HID_35d0] = 558, + [BNXT_ULP_CLASS_HID_06c0] = 559, + [BNXT_ULP_CLASS_HID_01e4] = 560, + [BNXT_ULP_CLASS_HID_4d32] = 561, + [BNXT_ULP_CLASS_HID_54aa] = 562, + [BNXT_ULP_CLASS_HID_0686] = 563, + [BNXT_ULP_CLASS_HID_540e] = 564, + [BNXT_ULP_CLASS_HID_2e3c] = 565, + [BNXT_ULP_CLASS_HID_3a20] = 566, + [BNXT_ULP_CLASS_HID_46f0] = 567, + [BNXT_ULP_CLASS_HID_52e4] = 568, + [BNXT_ULP_CLASS_HID_55e4] = 569, + [BNXT_ULP_CLASS_HID_21f8] = 570, + [BNXT_ULP_CLASS_HID_75e8] = 571, + [BNXT_ULP_CLASS_HID_41fc] = 572, + [BNXT_ULP_CLASS_HID_4d12] = 573, + [BNXT_ULP_CLASS_HID_548a] = 574, + [BNXT_ULP_CLASS_HID_3356] = 575, + [BNXT_ULP_CLASS_HID_1ace] = 576, + [BNXT_ULP_CLASS_HID_1a9a] = 577, + [BNXT_ULP_CLASS_HID_4d46] = 578, + [BNXT_ULP_CLASS_HID_2812] = 579, + [BNXT_ULP_CLASS_HID_338a] = 580, + [BNXT_ULP_CLASS_HID_06e6] = 581, + [BNXT_ULP_CLASS_HID_546e] = 582, + [BNXT_ULP_CLASS_HID_46ee] = 583, + [BNXT_ULP_CLASS_HID_0d22] = 584, + [BNXT_ULP_CLASS_HID_26e2] = 585, + [BNXT_ULP_CLASS_HID_746a] = 586, + [BNXT_ULP_CLASS_HID_1fa6] = 587, + [BNXT_ULP_CLASS_HID_2d2e] = 588, + [BNXT_ULP_CLASS_HID_4ef2] = 589, + [BNXT_ULP_CLASS_HID_576a] = 590, + [BNXT_ULP_CLASS_HID_30b6] = 591, + [BNXT_ULP_CLASS_HID_192e] = 592, + [BNXT_ULP_CLASS_HID_197a] = 593, + [BNXT_ULP_CLASS_HID_4ea6] = 594, + [BNXT_ULP_CLASS_HID_2bf2] = 595, + [BNXT_ULP_CLASS_HID_306a] = 596, + [BNXT_ULP_CLASS_HID_06c6] = 597, + [BNXT_ULP_CLASS_HID_544e] = 598, + [BNXT_ULP_CLASS_HID_46ce] = 599, + [BNXT_ULP_CLASS_HID_0d02] = 600, + [BNXT_ULP_CLASS_HID_26c2] = 601, + [BNXT_ULP_CLASS_HID_744a] = 602, + [BNXT_ULP_CLASS_HID_1f86] = 603, + [BNXT_ULP_CLASS_HID_2d0e] = 604, + [BNXT_ULP_CLASS_HID_2e1c] = 605, + [BNXT_ULP_CLASS_HID_3a00] = 606, + [BNXT_ULP_CLASS_HID_46d0] = 607, + [BNXT_ULP_CLASS_HID_52c4] = 608, + [BNXT_ULP_CLASS_HID_4e10] = 609, + [BNXT_ULP_CLASS_HID_5a04] = 610, + [BNXT_ULP_CLASS_HID_1f98] = 611, + [BNXT_ULP_CLASS_HID_72f8] = 612, + [BNXT_ULP_CLASS_HID_0a78] = 613, + [BNXT_ULP_CLASS_HID_166c] = 614, + [BNXT_ULP_CLASS_HID_233c] = 615, + [BNXT_ULP_CLASS_HID_0f20] = 616, + [BNXT_ULP_CLASS_HID_2a7c] = 617, + [BNXT_ULP_CLASS_HID_3660] = 618, + [BNXT_ULP_CLASS_HID_4330] = 619, + [BNXT_ULP_CLASS_HID_2f24] = 620, + [BNXT_ULP_CLASS_HID_5584] = 621, + [BNXT_ULP_CLASS_HID_2198] = 622, + [BNXT_ULP_CLASS_HID_7588] = 623, + [BNXT_ULP_CLASS_HID_419c] = 624, + [BNXT_ULP_CLASS_HID_7758] = 625, + [BNXT_ULP_CLASS_HID_43ac] = 626, + [BNXT_ULP_CLASS_HID_0c10] = 627, + [BNXT_ULP_CLASS_HID_1864] = 628, + [BNXT_ULP_CLASS_HID_30c8] = 629, + [BNXT_ULP_CLASS_HID_1cdc] = 630, + [BNXT_ULP_CLASS_HID_50cc] = 631, + [BNXT_ULP_CLASS_HID_3d20] = 632, + [BNXT_ULP_CLASS_HID_529c] = 633, + [BNXT_ULP_CLASS_HID_3ef0] = 634, + [BNXT_ULP_CLASS_HID_72e0] = 635, + [BNXT_ULP_CLASS_HID_5ef4] = 636, + [BNXT_ULP_CLASS_HID_2dfc] = 637, + [BNXT_ULP_CLASS_HID_39e0] = 638, + [BNXT_ULP_CLASS_HID_4530] = 639, + [BNXT_ULP_CLASS_HID_5124] = 640, + [BNXT_ULP_CLASS_HID_4df0] = 641, + [BNXT_ULP_CLASS_HID_59e4] = 642, + [BNXT_ULP_CLASS_HID_1c78] = 643, + [BNXT_ULP_CLASS_HID_7118] = 644, + [BNXT_ULP_CLASS_HID_0998] = 645, + [BNXT_ULP_CLASS_HID_158c] = 646, + [BNXT_ULP_CLASS_HID_20dc] = 647, + [BNXT_ULP_CLASS_HID_0cc0] = 648, + [BNXT_ULP_CLASS_HID_299c] = 649, + [BNXT_ULP_CLASS_HID_3580] = 650, + [BNXT_ULP_CLASS_HID_40d0] = 651, + [BNXT_ULP_CLASS_HID_2cc4] = 652, + [BNXT_ULP_CLASS_HID_55a4] = 653, + [BNXT_ULP_CLASS_HID_21b8] = 654, + [BNXT_ULP_CLASS_HID_75a8] = 655, + [BNXT_ULP_CLASS_HID_41bc] = 656, + [BNXT_ULP_CLASS_HID_7778] = 657, + [BNXT_ULP_CLASS_HID_438c] = 658, + [BNXT_ULP_CLASS_HID_0c30] = 659, + [BNXT_ULP_CLASS_HID_1844] = 660, + [BNXT_ULP_CLASS_HID_30e8] = 661, + [BNXT_ULP_CLASS_HID_1cfc] = 662, + [BNXT_ULP_CLASS_HID_50ec] = 663, + [BNXT_ULP_CLASS_HID_3d00] = 664, + [BNXT_ULP_CLASS_HID_52bc] = 665, + [BNXT_ULP_CLASS_HID_3ed0] = 666, + [BNXT_ULP_CLASS_HID_72c0] = 667, + [BNXT_ULP_CLASS_HID_5ed4] = 668, + [BNXT_ULP_CLASS_HID_3866] = 669, + [BNXT_ULP_CLASS_HID_381e] = 670, + [BNXT_ULP_CLASS_HID_3860] = 671, + [BNXT_ULP_CLASS_HID_0454] = 672, + [BNXT_ULP_CLASS_HID_3818] = 673, + [BNXT_ULP_CLASS_HID_042c] = 674, + [BNXT_ULP_CLASS_HID_3846] = 675, + [BNXT_ULP_CLASS_HID_387e] = 676, + [BNXT_ULP_CLASS_HID_3ba6] = 677, + [BNXT_ULP_CLASS_HID_385e] = 678, + [BNXT_ULP_CLASS_HID_3840] = 679, + [BNXT_ULP_CLASS_HID_0474] = 680, + [BNXT_ULP_CLASS_HID_3878] = 681, + [BNXT_ULP_CLASS_HID_044c] = 682, + [BNXT_ULP_CLASS_HID_3ba0] = 683, + [BNXT_ULP_CLASS_HID_0794] = 684, + [BNXT_ULP_CLASS_HID_3858] = 685, + [BNXT_ULP_CLASS_HID_046c] = 686 }; /* Array for the proto matcher list */ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { [1] = { - .class_hid = BNXT_ULP_CLASS_HID_05d1, + .class_hid = BNXT_ULP_CLASS_HID_55dd, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 4096, @@ -4596,11 +718,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } }, [2] = { - .class_hid = BNXT_ULP_CLASS_HID_1229, + .class_hid = BNXT_ULP_CLASS_HID_1df1, .class_tid = 1, .hdr_sig_id = 0, .flow_sig_id = 4104, @@ -4612,14 +733,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } }, [3] = { - .class_hid = BNXT_ULP_CLASS_HID_0bed, + .class_hid = BNXT_ULP_CLASS_HID_3e55, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -4627,15 +747,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } }, [4] = { - .class_hid = BNXT_ULP_CLASS_HID_1865, + .class_hid = BNXT_ULP_CLASS_HID_0649, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4104, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -4644,6176 +763,5673 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .field_sig = { .bits = BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } }, [5] = { - .class_hid = BNXT_ULP_CLASS_HID_25c9, + .class_hid = BNXT_ULP_CLASS_HID_1011, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4096, + .hdr_sig_id = 1, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } }, [6] = { - .class_hid = BNXT_ULP_CLASS_HID_3241, + .class_hid = BNXT_ULP_CLASS_HID_40e9, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4104, + .hdr_sig_id = 1, + .flow_sig_id = 16392, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } }, [7] = { - .class_hid = BNXT_ULP_CLASS_HID_2c05, + .class_hid = BNXT_ULP_CLASS_HID_3e99, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4096, + .hdr_sig_id = 1, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } }, [8] = { - .class_hid = BNXT_ULP_CLASS_HID_389d, + .class_hid = BNXT_ULP_CLASS_HID_06ad, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4104, + .hdr_sig_id = 1, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } }, [9] = { - .class_hid = BNXT_ULP_CLASS_HID_3c3d, + .class_hid = BNXT_ULP_CLASS_HID_38c7, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [10] = { - .class_hid = BNXT_ULP_CLASS_HID_48b5, + .class_hid = BNXT_ULP_CLASS_HID_00fb, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6152, + .hdr_sig_id = 2, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [11] = { - .class_hid = BNXT_ULP_CLASS_HID_4279, + .class_hid = BNXT_ULP_CLASS_HID_24d3, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [12] = { - .class_hid = BNXT_ULP_CLASS_HID_4ef1, + .class_hid = BNXT_ULP_CLASS_HID_559b, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6152, + .hdr_sig_id = 2, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [13] = { - .class_hid = BNXT_ULP_CLASS_HID_5c55, + .class_hid = BNXT_ULP_CLASS_HID_5003, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [14] = { - .class_hid = BNXT_ULP_CLASS_HID_0be1, + .class_hid = BNXT_ULP_CLASS_HID_1837, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6152, + .hdr_sig_id = 2, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [15] = { - .class_hid = BNXT_ULP_CLASS_HID_05a5, + .class_hid = BNXT_ULP_CLASS_HID_3bef, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144, + .hdr_sig_id = 2, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [16] = { - .class_hid = BNXT_ULP_CLASS_HID_123d, + .class_hid = BNXT_ULP_CLASS_HID_0403, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6152, + .hdr_sig_id = 2, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [17] = { - .class_hid = BNXT_ULP_CLASS_HID_4142d, + .class_hid = BNXT_ULP_CLASS_HID_3d3f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384, + .hdr_sig_id = 3, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [18] = { - .class_hid = BNXT_ULP_CLASS_HID_42095, + .class_hid = BNXT_ULP_CLASS_HID_0543, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16392, + .hdr_sig_id = 3, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [19] = { - .class_hid = BNXT_ULP_CLASS_HID_41a69, + .class_hid = BNXT_ULP_CLASS_HID_292b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384, + .hdr_sig_id = 3, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [20] = { - .class_hid = BNXT_ULP_CLASS_HID_426d1, + .class_hid = BNXT_ULP_CLASS_HID_59e3, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16392, + .hdr_sig_id = 3, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [21] = { - .class_hid = BNXT_ULP_CLASS_HID_44a99, + .class_hid = BNXT_ULP_CLASS_HID_5d3b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384, + .hdr_sig_id = 3, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [22] = { - .class_hid = BNXT_ULP_CLASS_HID_45701, + .class_hid = BNXT_ULP_CLASS_HID_254f, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16392, + .hdr_sig_id = 3, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [23] = { - .class_hid = BNXT_ULP_CLASS_HID_450c5, + .class_hid = BNXT_ULP_CLASS_HID_4917, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384, + .hdr_sig_id = 3, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [24] = { - .class_hid = BNXT_ULP_CLASS_HID_40071, + .class_hid = BNXT_ULP_CLASS_HID_113b, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16392, + .hdr_sig_id = 3, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [25] = { - .class_hid = BNXT_ULP_CLASS_HID_40a85, + .class_hid = BNXT_ULP_CLASS_HID_55fd, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576, + .hdr_sig_id = 4, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } }, [26] = { - .class_hid = BNXT_ULP_CLASS_HID_4170d, + .class_hid = BNXT_ULP_CLASS_HID_1dd1, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24584, + .hdr_sig_id = 4, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } }, [27] = { - .class_hid = BNXT_ULP_CLASS_HID_410c1, + .class_hid = BNXT_ULP_CLASS_HID_3e75, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576, + .hdr_sig_id = 4, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } }, [28] = { - .class_hid = BNXT_ULP_CLASS_HID_41d49, + .class_hid = BNXT_ULP_CLASS_HID_0669, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24584, + .hdr_sig_id = 4, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } }, [29] = { - .class_hid = BNXT_ULP_CLASS_HID_440f1, + .class_hid = BNXT_ULP_CLASS_HID_1ba1, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576, + .hdr_sig_id = 4, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } }, [30] = { - .class_hid = BNXT_ULP_CLASS_HID_44d79, + .class_hid = BNXT_ULP_CLASS_HID_4c69, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24584, + .hdr_sig_id = 4, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } }, [31] = { - .class_hid = BNXT_ULP_CLASS_HID_4473d, + .class_hid = BNXT_ULP_CLASS_HID_0439, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576, + .hdr_sig_id = 4, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } }, [32] = { - .class_hid = BNXT_ULP_CLASS_HID_453a5, + .class_hid = BNXT_ULP_CLASS_HID_34e1, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24584, + .hdr_sig_id = 4, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } }, [33] = { - .class_hid = BNXT_ULP_CLASS_HID_244e3, + .class_hid = BNXT_ULP_CLASS_HID_0465, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, + .hdr_sig_id = 4, + .flow_sig_id = 20480, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [34] = { - .class_hid = BNXT_ULP_CLASS_HID_2517b, + .class_hid = BNXT_ULP_CLASS_HID_352d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776, + .hdr_sig_id = 4, + .flow_sig_id = 20488, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [35] = { - .class_hid = BNXT_ULP_CLASS_HID_24b3f, + .class_hid = BNXT_ULP_CLASS_HID_55b1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, + .hdr_sig_id = 4, + .flow_sig_id = 22528, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [36] = { - .class_hid = BNXT_ULP_CLASS_HID_257b7, + .class_hid = BNXT_ULP_CLASS_HID_1da5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776, + .hdr_sig_id = 4, + .flow_sig_id = 22536, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [37] = { - .class_hid = BNXT_ULP_CLASS_HID_22f5f, + .class_hid = BNXT_ULP_CLASS_HID_32fd, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, + .hdr_sig_id = 4, + .flow_sig_id = 28672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [38] = { - .class_hid = BNXT_ULP_CLASS_HID_23bd7, + .class_hid = BNXT_ULP_CLASS_HID_63a5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840, + .hdr_sig_id = 4, + .flow_sig_id = 28680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [39] = { - .class_hid = BNXT_ULP_CLASS_HID_2359b, + .class_hid = BNXT_ULP_CLASS_HID_1b75, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, + .hdr_sig_id = 4, + .flow_sig_id = 30720, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [40] = { - .class_hid = BNXT_ULP_CLASS_HID_24213, + .class_hid = BNXT_ULP_CLASS_HID_4c3d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840, + .hdr_sig_id = 4, + .flow_sig_id = 30728, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [41] = { - .class_hid = BNXT_ULP_CLASS_HID_20bab, + .class_hid = BNXT_ULP_CLASS_HID_1031, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, + .hdr_sig_id = 5, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } }, [42] = { - .class_hid = BNXT_ULP_CLASS_HID_21823, + .class_hid = BNXT_ULP_CLASS_HID_40c9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776, + .hdr_sig_id = 5, + .flow_sig_id = 16392, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } }, [43] = { - .class_hid = BNXT_ULP_CLASS_HID_211e7, + .class_hid = BNXT_ULP_CLASS_HID_3eb9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, + .hdr_sig_id = 5, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } }, [44] = { - .class_hid = BNXT_ULP_CLASS_HID_21e7f, + .class_hid = BNXT_ULP_CLASS_HID_068d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776, + .hdr_sig_id = 5, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } }, [45] = { - .class_hid = BNXT_ULP_CLASS_HID_252f3, + .class_hid = BNXT_ULP_CLASS_HID_5039, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, + .hdr_sig_id = 5, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } }, [46] = { - .class_hid = BNXT_ULP_CLASS_HID_2029f, + .class_hid = BNXT_ULP_CLASS_HID_180d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840, + .hdr_sig_id = 5, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } }, [47] = { - .class_hid = BNXT_ULP_CLASS_HID_2590f, + .class_hid = BNXT_ULP_CLASS_HID_15fd, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, + .hdr_sig_id = 5, + .flow_sig_id = 57344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } }, [48] = { - .class_hid = BNXT_ULP_CLASS_HID_208db, + .class_hid = BNXT_ULP_CLASS_HID_46b5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840, + .hdr_sig_id = 5, + .flow_sig_id = 57352, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } }, [49] = { - .class_hid = BNXT_ULP_CLASS_HID_231d3, + .class_hid = BNXT_ULP_CLASS_HID_303d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, + .hdr_sig_id = 5, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [50] = { - .class_hid = BNXT_ULP_CLASS_HID_23e2b, + .class_hid = BNXT_ULP_CLASS_HID_60f5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776, + .hdr_sig_id = 5, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [51] = { - .class_hid = BNXT_ULP_CLASS_HID_237ef, + .class_hid = BNXT_ULP_CLASS_HID_5ea5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, + .hdr_sig_id = 5, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [52] = { - .class_hid = BNXT_ULP_CLASS_HID_24467, + .class_hid = BNXT_ULP_CLASS_HID_2689, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776, + .hdr_sig_id = 5, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [53] = { - .class_hid = BNXT_ULP_CLASS_HID_21c0f, + .class_hid = BNXT_ULP_CLASS_HID_0771, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, + .hdr_sig_id = 5, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [54] = { - .class_hid = BNXT_ULP_CLASS_HID_22887, + .class_hid = BNXT_ULP_CLASS_HID_3809, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840, + .hdr_sig_id = 5, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [55] = { - .class_hid = BNXT_ULP_CLASS_HID_2224b, + .class_hid = BNXT_ULP_CLASS_HID_35f9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, + .hdr_sig_id = 5, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [56] = { - .class_hid = BNXT_ULP_CLASS_HID_22ec3, + .class_hid = BNXT_ULP_CLASS_HID_66b1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840, + .hdr_sig_id = 5, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [57] = { - .class_hid = BNXT_ULP_CLASS_HID_25547, + .class_hid = BNXT_ULP_CLASS_HID_559d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, + .hdr_sig_id = 6, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } }, [58] = { - .class_hid = BNXT_ULP_CLASS_HID_20513, + .class_hid = BNXT_ULP_CLASS_HID_1db1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776, + .hdr_sig_id = 6, + .flow_sig_id = 4104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } }, [59] = { - .class_hid = BNXT_ULP_CLASS_HID_25b83, + .class_hid = BNXT_ULP_CLASS_HID_3e15, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, + .hdr_sig_id = 6, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } }, [60] = { - .class_hid = BNXT_ULP_CLASS_HID_20b2f, + .class_hid = BNXT_ULP_CLASS_HID_0609, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776, + .hdr_sig_id = 6, + .flow_sig_id = 6152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } }, [61] = { - .class_hid = BNXT_ULP_CLASS_HID_23fa3, + .class_hid = BNXT_ULP_CLASS_HID_1bc1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, + .hdr_sig_id = 6, + .flow_sig_id = 12288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } }, [62] = { - .class_hid = BNXT_ULP_CLASS_HID_24c3b, + .class_hid = BNXT_ULP_CLASS_HID_4c09, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840, + .hdr_sig_id = 6, + .flow_sig_id = 12296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } }, [63] = { - .class_hid = BNXT_ULP_CLASS_HID_245ff, + .class_hid = BNXT_ULP_CLASS_HID_0459, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, + .hdr_sig_id = 6, + .flow_sig_id = 14336, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } }, [64] = { - .class_hid = BNXT_ULP_CLASS_HID_25277, + .class_hid = BNXT_ULP_CLASS_HID_3481, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840, + .hdr_sig_id = 6, + .flow_sig_id = 14344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } }, [65] = { - .class_hid = BNXT_ULP_CLASS_HID_64037, + .class_hid = BNXT_ULP_CLASS_HID_0405, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, + .hdr_sig_id = 6, + .flow_sig_id = 20480, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [66] = { - .class_hid = BNXT_ULP_CLASS_HID_64c8f, + .class_hid = BNXT_ULP_CLASS_HID_354d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160, + .hdr_sig_id = 6, + .flow_sig_id = 20488, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [67] = { - .class_hid = BNXT_ULP_CLASS_HID_64673, + .class_hid = BNXT_ULP_CLASS_HID_55d1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, + .hdr_sig_id = 6, + .flow_sig_id = 22528, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [68] = { - .class_hid = BNXT_ULP_CLASS_HID_652cb, + .class_hid = BNXT_ULP_CLASS_HID_1dc5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160, + .hdr_sig_id = 6, + .flow_sig_id = 22536, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [69] = { - .class_hid = BNXT_ULP_CLASS_HID_62a93, + .class_hid = BNXT_ULP_CLASS_HID_329d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, + .hdr_sig_id = 6, + .flow_sig_id = 28672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [70] = { - .class_hid = BNXT_ULP_CLASS_HID_636eb, + .class_hid = BNXT_ULP_CLASS_HID_63c5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49224, + .hdr_sig_id = 6, + .flow_sig_id = 28680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [71] = { - .class_hid = BNXT_ULP_CLASS_HID_630af, + .class_hid = BNXT_ULP_CLASS_HID_1b15, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, + .hdr_sig_id = 6, + .flow_sig_id = 30720, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [72] = { - .class_hid = BNXT_ULP_CLASS_HID_63d27, + .class_hid = BNXT_ULP_CLASS_HID_4c5d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49224, + .hdr_sig_id = 6, + .flow_sig_id = 30728, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [73] = { - .class_hid = BNXT_ULP_CLASS_HID_606ff, + .class_hid = BNXT_ULP_CLASS_HID_1051, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, + .hdr_sig_id = 7, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } }, [74] = { - .class_hid = BNXT_ULP_CLASS_HID_61377, + .class_hid = BNXT_ULP_CLASS_HID_40a9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160, + .hdr_sig_id = 7, + .flow_sig_id = 16392, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } }, [75] = { - .class_hid = BNXT_ULP_CLASS_HID_60d3b, + .class_hid = BNXT_ULP_CLASS_HID_3ed9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, + .hdr_sig_id = 7, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } }, [76] = { - .class_hid = BNXT_ULP_CLASS_HID_619b3, + .class_hid = BNXT_ULP_CLASS_HID_06ed, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160, + .hdr_sig_id = 7, + .flow_sig_id = 24584, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } }, [77] = { - .class_hid = BNXT_ULP_CLASS_HID_64e07, + .class_hid = BNXT_ULP_CLASS_HID_5059, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, + .hdr_sig_id = 7, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } }, [78] = { - .class_hid = BNXT_ULP_CLASS_HID_65a9f, + .class_hid = BNXT_ULP_CLASS_HID_186d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49224, + .hdr_sig_id = 7, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } }, [79] = { - .class_hid = BNXT_ULP_CLASS_HID_65443, + .class_hid = BNXT_ULP_CLASS_HID_159d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, + .hdr_sig_id = 7, + .flow_sig_id = 57344, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } }, [80] = { - .class_hid = BNXT_ULP_CLASS_HID_603ef, + .class_hid = BNXT_ULP_CLASS_HID_46d5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49224, + .hdr_sig_id = 7, + .flow_sig_id = 57352, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } }, [81] = { - .class_hid = BNXT_ULP_CLASS_HID_62ce7, + .class_hid = BNXT_ULP_CLASS_HID_305d, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, + .hdr_sig_id = 7, + .flow_sig_id = 81920, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [82] = { - .class_hid = BNXT_ULP_CLASS_HID_6397f, + .class_hid = BNXT_ULP_CLASS_HID_6095, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160, + .hdr_sig_id = 7, + .flow_sig_id = 81928, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [83] = { - .class_hid = BNXT_ULP_CLASS_HID_63323, + .class_hid = BNXT_ULP_CLASS_HID_5ec5, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, + .hdr_sig_id = 7, + .flow_sig_id = 90112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [84] = { - .class_hid = BNXT_ULP_CLASS_HID_63fbb, + .class_hid = BNXT_ULP_CLASS_HID_26e9, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160, + .hdr_sig_id = 7, + .flow_sig_id = 90120, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [85] = { - .class_hid = BNXT_ULP_CLASS_HID_61743, + .class_hid = BNXT_ULP_CLASS_HID_0711, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, + .hdr_sig_id = 7, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [86] = { - .class_hid = BNXT_ULP_CLASS_HID_623db, + .class_hid = BNXT_ULP_CLASS_HID_3869, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49224, + .hdr_sig_id = 7, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [87] = { - .class_hid = BNXT_ULP_CLASS_HID_61d9f, + .class_hid = BNXT_ULP_CLASS_HID_3599, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, + .hdr_sig_id = 7, + .flow_sig_id = 122880, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [88] = { - .class_hid = BNXT_ULP_CLASS_HID_62a17, + .class_hid = BNXT_ULP_CLASS_HID_66d1, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49224, + .hdr_sig_id = 7, + .flow_sig_id = 122888, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [89] = { - .class_hid = BNXT_ULP_CLASS_HID_6509b, + .class_hid = BNXT_ULP_CLASS_HID_38e7, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, + .hdr_sig_id = 8, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [90] = { - .class_hid = BNXT_ULP_CLASS_HID_60027, + .class_hid = BNXT_ULP_CLASS_HID_00db, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160, + .hdr_sig_id = 8, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [91] = { - .class_hid = BNXT_ULP_CLASS_HID_656d7, + .class_hid = BNXT_ULP_CLASS_HID_24f3, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, + .hdr_sig_id = 8, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [92] = { - .class_hid = BNXT_ULP_CLASS_HID_60663, + .class_hid = BNXT_ULP_CLASS_HID_55bb, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160, + .hdr_sig_id = 8, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [93] = { - .class_hid = BNXT_ULP_CLASS_HID_63af7, + .class_hid = BNXT_ULP_CLASS_HID_5023, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, + .hdr_sig_id = 8, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [94] = { - .class_hid = BNXT_ULP_CLASS_HID_6474f, + .class_hid = BNXT_ULP_CLASS_HID_1817, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49224, + .hdr_sig_id = 8, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [95] = { - .class_hid = BNXT_ULP_CLASS_HID_64133, + .class_hid = BNXT_ULP_CLASS_HID_3bcf, .class_tid = 1, - .hdr_sig_id = 2, + .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [96] = { - .class_hid = BNXT_ULP_CLASS_HID_64d8b, + .class_hid = BNXT_ULP_CLASS_HID_0423, .class_tid = 1, - .hdr_sig_id = 2, + .hdr_sig_id = 8, .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [97] = { - .class_hid = BNXT_ULP_CLASS_HID_a3fb, + .class_hid = BNXT_ULP_CLASS_HID_58e3, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, + .hdr_sig_id = 8, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [98] = { - .class_hid = BNXT_ULP_CLASS_HID_b063, + .class_hid = BNXT_ULP_CLASS_HID_20d7, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131080, + .hdr_sig_id = 8, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [99] = { - .class_hid = BNXT_ULP_CLASS_HID_aa27, + .class_hid = BNXT_ULP_CLASS_HID_448f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, + .hdr_sig_id = 8, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [100] = { - .class_hid = BNXT_ULP_CLASS_HID_b6af, + .class_hid = BNXT_ULP_CLASS_HID_0ce3, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131080, + .hdr_sig_id = 8, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [101] = { - .class_hid = BNXT_ULP_CLASS_HID_8e47, + .class_hid = BNXT_ULP_CLASS_HID_076b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, + .hdr_sig_id = 8, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [102] = { - .class_hid = BNXT_ULP_CLASS_HID_9acf, + .class_hid = BNXT_ULP_CLASS_HID_3813, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144, + .hdr_sig_id = 8, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [103] = { - .class_hid = BNXT_ULP_CLASS_HID_9483, + .class_hid = BNXT_ULP_CLASS_HID_5bcb, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, + .hdr_sig_id = 8, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [104] = { - .class_hid = BNXT_ULP_CLASS_HID_a10b, + .class_hid = BNXT_ULP_CLASS_HID_243f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144, + .hdr_sig_id = 8, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [105] = { - .class_hid = BNXT_ULP_CLASS_HID_c78f, + .class_hid = BNXT_ULP_CLASS_HID_144b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, + .hdr_sig_id = 8, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [106] = { - .class_hid = BNXT_ULP_CLASS_HID_d3f7, + .class_hid = BNXT_ULP_CLASS_HID_4573, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131080, + .hdr_sig_id = 8, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [107] = { - .class_hid = BNXT_ULP_CLASS_HID_cdcb, + .class_hid = BNXT_ULP_CLASS_HID_0057, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, + .hdr_sig_id = 8, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [108] = { - .class_hid = BNXT_ULP_CLASS_HID_da33, + .class_hid = BNXT_ULP_CLASS_HID_311f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131080, + .hdr_sig_id = 8, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [109] = { - .class_hid = BNXT_ULP_CLASS_HID_b1eb, + .class_hid = BNXT_ULP_CLASS_HID_2b87, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, + .hdr_sig_id = 8, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [110] = { - .class_hid = BNXT_ULP_CLASS_HID_be53, + .class_hid = BNXT_ULP_CLASS_HID_5c4f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144, + .hdr_sig_id = 8, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [111] = { - .class_hid = BNXT_ULP_CLASS_HID_b817, + .class_hid = BNXT_ULP_CLASS_HID_1793, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, + .hdr_sig_id = 8, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [112] = { - .class_hid = BNXT_ULP_CLASS_HID_c49f, + .class_hid = BNXT_ULP_CLASS_HID_485b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144, + .hdr_sig_id = 8, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [113] = { - .class_hid = BNXT_ULP_CLASS_HID_49f2f, + .class_hid = BNXT_ULP_CLASS_HID_3447, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, + .hdr_sig_id = 8, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [114] = { - .class_hid = BNXT_ULP_CLASS_HID_4ab97, + .class_hid = BNXT_ULP_CLASS_HID_650f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131080, + .hdr_sig_id = 8, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [115] = { - .class_hid = BNXT_ULP_CLASS_HID_4a56b, + .class_hid = BNXT_ULP_CLASS_HID_2053, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, + .hdr_sig_id = 8, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [116] = { - .class_hid = BNXT_ULP_CLASS_HID_4b1d3, + .class_hid = BNXT_ULP_CLASS_HID_511b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131080, + .hdr_sig_id = 8, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [117] = { - .class_hid = BNXT_ULP_CLASS_HID_4898b, + .class_hid = BNXT_ULP_CLASS_HID_4b83, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, + .hdr_sig_id = 8, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [118] = { - .class_hid = BNXT_ULP_CLASS_HID_495f3, + .class_hid = BNXT_ULP_CLASS_HID_13f7, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144, + .hdr_sig_id = 8, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [119] = { - .class_hid = BNXT_ULP_CLASS_HID_48fb7, + .class_hid = BNXT_ULP_CLASS_HID_37af, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, + .hdr_sig_id = 8, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [120] = { - .class_hid = BNXT_ULP_CLASS_HID_49c3f, + .class_hid = BNXT_ULP_CLASS_HID_6857, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144, + .hdr_sig_id = 8, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [121] = { - .class_hid = BNXT_ULP_CLASS_HID_4c2b3, + .class_hid = BNXT_ULP_CLASS_HID_3d1f, .class_tid = 1, - .hdr_sig_id = 3, + .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [122] = { - .class_hid = BNXT_ULP_CLASS_HID_4cf3b, + .class_hid = BNXT_ULP_CLASS_HID_0563, .class_tid = 1, - .hdr_sig_id = 3, + .hdr_sig_id = 9, .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [123] = { - .class_hid = BNXT_ULP_CLASS_HID_4c8ff, + .class_hid = BNXT_ULP_CLASS_HID_290b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, + .hdr_sig_id = 9, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [124] = { - .class_hid = BNXT_ULP_CLASS_HID_4d567, + .class_hid = BNXT_ULP_CLASS_HID_59c3, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131080, + .hdr_sig_id = 9, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [125] = { - .class_hid = BNXT_ULP_CLASS_HID_4ad1f, + .class_hid = BNXT_ULP_CLASS_HID_5d1b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, + .hdr_sig_id = 9, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [126] = { - .class_hid = BNXT_ULP_CLASS_HID_4b987, + .class_hid = BNXT_ULP_CLASS_HID_256f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144, + .hdr_sig_id = 9, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [127] = { - .class_hid = BNXT_ULP_CLASS_HID_4b35b, + .class_hid = BNXT_ULP_CLASS_HID_4937, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, + .hdr_sig_id = 9, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [128] = { - .class_hid = BNXT_ULP_CLASS_HID_4bfc3, + .class_hid = BNXT_ULP_CLASS_HID_111b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144, + .hdr_sig_id = 9, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [129] = { - .class_hid = BNXT_ULP_CLASS_HID_1b9fb, + .class_hid = BNXT_ULP_CLASS_HID_5f4b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, + .hdr_sig_id = 9, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [130] = { - .class_hid = BNXT_ULP_CLASS_HID_1c663, + .class_hid = BNXT_ULP_CLASS_HID_275f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616, + .hdr_sig_id = 9, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [131] = { - .class_hid = BNXT_ULP_CLASS_HID_1c027, + .class_hid = BNXT_ULP_CLASS_HID_4b67, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, + .hdr_sig_id = 9, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [132] = { - .class_hid = BNXT_ULP_CLASS_HID_1ccaf, + .class_hid = BNXT_ULP_CLASS_HID_134b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616, + .hdr_sig_id = 9, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [133] = { - .class_hid = BNXT_ULP_CLASS_HID_1a447, + .class_hid = BNXT_ULP_CLASS_HID_1683, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, + .hdr_sig_id = 9, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [134] = { - .class_hid = BNXT_ULP_CLASS_HID_1b0cf, + .class_hid = BNXT_ULP_CLASS_HID_475b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680, + .hdr_sig_id = 9, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [135] = { - .class_hid = BNXT_ULP_CLASS_HID_1aa83, + .class_hid = BNXT_ULP_CLASS_HID_02bf, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, + .hdr_sig_id = 9, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [136] = { - .class_hid = BNXT_ULP_CLASS_HID_1b70b, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + }, + [136] = { + .class_hid = BNXT_ULP_CLASS_HID_3377, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680, + .hdr_sig_id = 9, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [137] = { - .class_hid = BNXT_ULP_CLASS_HID_180b3, + .class_hid = BNXT_ULP_CLASS_HID_19db, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, + .hdr_sig_id = 9, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [138] = { - .class_hid = BNXT_ULP_CLASS_HID_18d3b, + .class_hid = BNXT_ULP_CLASS_HID_4a93, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616, + .hdr_sig_id = 9, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [139] = { - .class_hid = BNXT_ULP_CLASS_HID_186ff, + .class_hid = BNXT_ULP_CLASS_HID_05f7, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, + .hdr_sig_id = 9, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [140] = { - .class_hid = BNXT_ULP_CLASS_HID_19367, + .class_hid = BNXT_ULP_CLASS_HID_368f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616, + .hdr_sig_id = 9, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [141] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7eb, + .class_hid = BNXT_ULP_CLASS_HID_39c7, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, + .hdr_sig_id = 9, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [142] = { - .class_hid = BNXT_ULP_CLASS_HID_1d453, + .class_hid = BNXT_ULP_CLASS_HID_022b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680, + .hdr_sig_id = 9, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [143] = { - .class_hid = BNXT_ULP_CLASS_HID_1ce17, + .class_hid = BNXT_ULP_CLASS_HID_25f3, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, + .hdr_sig_id = 9, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [144] = { - .class_hid = BNXT_ULP_CLASS_HID_1da9f, + .class_hid = BNXT_ULP_CLASS_HID_568b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680, + .hdr_sig_id = 9, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [145] = { - .class_hid = BNXT_ULP_CLASS_HID_5b52f, + .class_hid = BNXT_ULP_CLASS_HID_3c37, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, + .hdr_sig_id = 9, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [146] = { - .class_hid = BNXT_ULP_CLASS_HID_5c197, + .class_hid = BNXT_ULP_CLASS_HID_041b, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616, + .hdr_sig_id = 9, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [147] = { - .class_hid = BNXT_ULP_CLASS_HID_5bb6b, + .class_hid = BNXT_ULP_CLASS_HID_2823, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, + .hdr_sig_id = 9, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [148] = { - .class_hid = BNXT_ULP_CLASS_HID_5c7d3, + .class_hid = BNXT_ULP_CLASS_HID_58fb, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616, + .hdr_sig_id = 9, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [149] = { - .class_hid = BNXT_ULP_CLASS_HID_59f8b, + .class_hid = BNXT_ULP_CLASS_HID_5c33, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, + .hdr_sig_id = 9, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [150] = { - .class_hid = BNXT_ULP_CLASS_HID_5abf3, + .class_hid = BNXT_ULP_CLASS_HID_2407, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680, + .hdr_sig_id = 9, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [151] = { - .class_hid = BNXT_ULP_CLASS_HID_5a5b7, + .class_hid = BNXT_ULP_CLASS_HID_482f, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, + .hdr_sig_id = 9, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [152] = { - .class_hid = BNXT_ULP_CLASS_HID_5b23f, + .class_hid = BNXT_ULP_CLASS_HID_1033, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680, + .hdr_sig_id = 9, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [153] = { - .class_hid = BNXT_ULP_CLASS_HID_5d8b3, + .class_hid = BNXT_ULP_CLASS_HID_3887, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, + .hdr_sig_id = 10, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [154] = { - .class_hid = BNXT_ULP_CLASS_HID_5886f, + .class_hid = BNXT_ULP_CLASS_HID_00bb, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616, + .hdr_sig_id = 10, + .flow_sig_id = 32776, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [155] = { - .class_hid = BNXT_ULP_CLASS_HID_58223, + .class_hid = BNXT_ULP_CLASS_HID_2493, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, + .hdr_sig_id = 10, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [156] = { - .class_hid = BNXT_ULP_CLASS_HID_58eab, + .class_hid = BNXT_ULP_CLASS_HID_55db, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616, + .hdr_sig_id = 10, + .flow_sig_id = 32840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [157] = { - .class_hid = BNXT_ULP_CLASS_HID_5c31f, + .class_hid = BNXT_ULP_CLASS_HID_5043, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, + .hdr_sig_id = 10, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [158] = { - .class_hid = BNXT_ULP_CLASS_HID_5cf87, + .class_hid = BNXT_ULP_CLASS_HID_1877, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680, + .hdr_sig_id = 10, + .flow_sig_id = 49160, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [159] = { - .class_hid = BNXT_ULP_CLASS_HID_5c95b, + .class_hid = BNXT_ULP_CLASS_HID_3baf, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, + .hdr_sig_id = 10, + .flow_sig_id = 49216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [160] = { - .class_hid = BNXT_ULP_CLASS_HID_5d5c3, + .class_hid = BNXT_ULP_CLASS_HID_0443, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680, + .hdr_sig_id = 10, + .flow_sig_id = 49224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [161] = { - .class_hid = BNXT_ULP_CLASS_HID_05f1, + .class_hid = BNXT_ULP_CLASS_HID_5883, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096, + .hdr_sig_id = 10, + .flow_sig_id = 98304, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [162] = { - .class_hid = BNXT_ULP_CLASS_HID_1209, + .class_hid = BNXT_ULP_CLASS_HID_20b7, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4104, + .hdr_sig_id = 10, + .flow_sig_id = 98312, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [163] = { - .class_hid = BNXT_ULP_CLASS_HID_0bcd, + .class_hid = BNXT_ULP_CLASS_HID_44ef, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096, + .hdr_sig_id = 10, + .flow_sig_id = 98368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [164] = { - .class_hid = BNXT_ULP_CLASS_HID_1845, + .class_hid = BNXT_ULP_CLASS_HID_0c83, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4104, + .hdr_sig_id = 10, + .flow_sig_id = 98376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [165] = { - .class_hid = BNXT_ULP_CLASS_HID_25e9, + .class_hid = BNXT_ULP_CLASS_HID_070b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096, + .hdr_sig_id = 10, + .flow_sig_id = 114688, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [166] = { - .class_hid = BNXT_ULP_CLASS_HID_3261, + .class_hid = BNXT_ULP_CLASS_HID_3873, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4104, + .hdr_sig_id = 10, + .flow_sig_id = 114696, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [167] = { - .class_hid = BNXT_ULP_CLASS_HID_2c25, + .class_hid = BNXT_ULP_CLASS_HID_5bab, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096, + .hdr_sig_id = 10, + .flow_sig_id = 114752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [168] = { - .class_hid = BNXT_ULP_CLASS_HID_38bd, + .class_hid = BNXT_ULP_CLASS_HID_245f, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4104, + .hdr_sig_id = 10, + .flow_sig_id = 114760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [169] = { - .class_hid = BNXT_ULP_CLASS_HID_3c1d, + .class_hid = BNXT_ULP_CLASS_HID_142b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144, + .hdr_sig_id = 10, + .flow_sig_id = 163840, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [170] = { - .class_hid = BNXT_ULP_CLASS_HID_4895, + .class_hid = BNXT_ULP_CLASS_HID_4513, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6152, + .hdr_sig_id = 10, + .flow_sig_id = 163848, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [171] = { - .class_hid = BNXT_ULP_CLASS_HID_4259, + .class_hid = BNXT_ULP_CLASS_HID_0037, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144, + .hdr_sig_id = 10, + .flow_sig_id = 163904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [172] = { - .class_hid = BNXT_ULP_CLASS_HID_4ed1, + .class_hid = BNXT_ULP_CLASS_HID_317f, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6152, + .hdr_sig_id = 10, + .flow_sig_id = 163912, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [173] = { - .class_hid = BNXT_ULP_CLASS_HID_5c75, + .class_hid = BNXT_ULP_CLASS_HID_2be7, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144, + .hdr_sig_id = 10, + .flow_sig_id = 180224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [174] = { - .class_hid = BNXT_ULP_CLASS_HID_0bc1, + .class_hid = BNXT_ULP_CLASS_HID_5c2f, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6152, + .hdr_sig_id = 10, + .flow_sig_id = 180232, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [175] = { - .class_hid = BNXT_ULP_CLASS_HID_0585, + .class_hid = BNXT_ULP_CLASS_HID_17f3, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144, + .hdr_sig_id = 10, + .flow_sig_id = 180288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [176] = { - .class_hid = BNXT_ULP_CLASS_HID_121d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6152, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + }, + [176] = { + .class_hid = BNXT_ULP_CLASS_HID_483b, + .class_tid = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180296, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [177] = { - .class_hid = BNXT_ULP_CLASS_HID_58c5, + .class_hid = BNXT_ULP_CLASS_HID_3427, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288, + .hdr_sig_id = 10, + .flow_sig_id = 229376, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [178] = { - .class_hid = BNXT_ULP_CLASS_HID_0891, + .class_hid = BNXT_ULP_CLASS_HID_656f, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12296, + .hdr_sig_id = 10, + .flow_sig_id = 229384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [179] = { - .class_hid = BNXT_ULP_CLASS_HID_0255, + .class_hid = BNXT_ULP_CLASS_HID_2033, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288, + .hdr_sig_id = 10, + .flow_sig_id = 229440, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [180] = { - .class_hid = BNXT_ULP_CLASS_HID_0eed, + .class_hid = BNXT_ULP_CLASS_HID_517b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12296, + .hdr_sig_id = 10, + .flow_sig_id = 229448, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [181] = { - .class_hid = BNXT_ULP_CLASS_HID_1c71, + .class_hid = BNXT_ULP_CLASS_HID_4be3, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288, + .hdr_sig_id = 10, + .flow_sig_id = 245760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [182] = { - .class_hid = BNXT_ULP_CLASS_HID_2889, + .class_hid = BNXT_ULP_CLASS_HID_1397, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12296, + .hdr_sig_id = 10, + .flow_sig_id = 245768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [183] = { - .class_hid = BNXT_ULP_CLASS_HID_224d, + .class_hid = BNXT_ULP_CLASS_HID_37cf, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288, + .hdr_sig_id = 10, + .flow_sig_id = 245824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [184] = { - .class_hid = BNXT_ULP_CLASS_HID_2ec5, + .class_hid = BNXT_ULP_CLASS_HID_6837, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12296, + .hdr_sig_id = 10, + .flow_sig_id = 245832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [185] = { - .class_hid = BNXT_ULP_CLASS_HID_32a5, + .class_hid = BNXT_ULP_CLASS_HID_3d7f, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336, + .hdr_sig_id = 11, + .flow_sig_id = 131072, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [186] = { - .class_hid = BNXT_ULP_CLASS_HID_3f3d, + .class_hid = BNXT_ULP_CLASS_HID_0503, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14344, + .hdr_sig_id = 11, + .flow_sig_id = 131080, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [187] = { - .class_hid = BNXT_ULP_CLASS_HID_38e1, + .class_hid = BNXT_ULP_CLASS_HID_296b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336, + .hdr_sig_id = 11, + .flow_sig_id = 131136, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [188] = { - .class_hid = BNXT_ULP_CLASS_HID_4579, + .class_hid = BNXT_ULP_CLASS_HID_59a3, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14344, + .hdr_sig_id = 11, + .flow_sig_id = 131144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [189] = { - .class_hid = BNXT_ULP_CLASS_HID_529d, + .class_hid = BNXT_ULP_CLASS_HID_5d7b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336, + .hdr_sig_id = 11, + .flow_sig_id = 196608, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [190] = { - .class_hid = BNXT_ULP_CLASS_HID_0269, + .class_hid = BNXT_ULP_CLASS_HID_250f, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14344, + .hdr_sig_id = 11, + .flow_sig_id = 196616, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [191] = { - .class_hid = BNXT_ULP_CLASS_HID_58d9, + .class_hid = BNXT_ULP_CLASS_HID_4957, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336, + .hdr_sig_id = 11, + .flow_sig_id = 196672, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [192] = { - .class_hid = BNXT_ULP_CLASS_HID_08a5, + .class_hid = BNXT_ULP_CLASS_HID_117b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14344, + .hdr_sig_id = 11, + .flow_sig_id = 196680, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [193] = { - .class_hid = BNXT_ULP_CLASS_HID_400c5, + .class_hid = BNXT_ULP_CLASS_HID_5f2b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480, + .hdr_sig_id = 11, + .flow_sig_id = 393216, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [194] = { - .class_hid = BNXT_ULP_CLASS_HID_40d5d, + .class_hid = BNXT_ULP_CLASS_HID_273f, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20488, + .hdr_sig_id = 11, + .flow_sig_id = 393224, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [195] = { - .class_hid = BNXT_ULP_CLASS_HID_40701, + .class_hid = BNXT_ULP_CLASS_HID_4b07, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480, + .hdr_sig_id = 11, + .flow_sig_id = 393280, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [196] = { - .class_hid = BNXT_ULP_CLASS_HID_41399, + .class_hid = BNXT_ULP_CLASS_HID_132b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20488, + .hdr_sig_id = 11, + .flow_sig_id = 393288, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [197] = { - .class_hid = BNXT_ULP_CLASS_HID_4213d, + .class_hid = BNXT_ULP_CLASS_HID_16e3, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480, + .hdr_sig_id = 11, + .flow_sig_id = 458752, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [198] = { - .class_hid = BNXT_ULP_CLASS_HID_42db5, + .class_hid = BNXT_ULP_CLASS_HID_473b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20488, + .hdr_sig_id = 11, + .flow_sig_id = 458760, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [199] = { - .class_hid = BNXT_ULP_CLASS_HID_42779, + .class_hid = BNXT_ULP_CLASS_HID_02df, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480, + .hdr_sig_id = 11, + .flow_sig_id = 458816, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [200] = { - .class_hid = BNXT_ULP_CLASS_HID_433f1, + .class_hid = BNXT_ULP_CLASS_HID_3317, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20488, + .hdr_sig_id = 11, + .flow_sig_id = 458824, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [201] = { - .class_hid = BNXT_ULP_CLASS_HID_43751, + .class_hid = BNXT_ULP_CLASS_HID_19bb, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528, + .hdr_sig_id = 11, + .flow_sig_id = 655360, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [202] = { - .class_hid = BNXT_ULP_CLASS_HID_443e9, + .class_hid = BNXT_ULP_CLASS_HID_4af3, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22536, + .hdr_sig_id = 11, + .flow_sig_id = 655368, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [203] = { - .class_hid = BNXT_ULP_CLASS_HID_43dad, + .class_hid = BNXT_ULP_CLASS_HID_0597, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528, + .hdr_sig_id = 11, + .flow_sig_id = 655424, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [204] = { - .class_hid = BNXT_ULP_CLASS_HID_44a25, + .class_hid = BNXT_ULP_CLASS_HID_36ef, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22536, + .hdr_sig_id = 11, + .flow_sig_id = 655432, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [205] = { - .class_hid = BNXT_ULP_CLASS_HID_45749, + .class_hid = BNXT_ULP_CLASS_HID_39a7, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528, + .hdr_sig_id = 11, + .flow_sig_id = 720896, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [206] = { - .class_hid = BNXT_ULP_CLASS_HID_40715, + .class_hid = BNXT_ULP_CLASS_HID_024b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22536, + .hdr_sig_id = 11, + .flow_sig_id = 720904, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [207] = { - .class_hid = BNXT_ULP_CLASS_HID_400d9, + .class_hid = BNXT_ULP_CLASS_HID_2593, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528, + .hdr_sig_id = 11, + .flow_sig_id = 720960, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [208] = { - .class_hid = BNXT_ULP_CLASS_HID_40d51, + .class_hid = BNXT_ULP_CLASS_HID_56eb, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22536, + .hdr_sig_id = 11, + .flow_sig_id = 720968, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [209] = { - .class_hid = BNXT_ULP_CLASS_HID_45419, + .class_hid = BNXT_ULP_CLASS_HID_3c57, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672, + .hdr_sig_id = 11, + .flow_sig_id = 917504, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [210] = { - .class_hid = BNXT_ULP_CLASS_HID_403e5, + .class_hid = BNXT_ULP_CLASS_HID_047b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28680, + .hdr_sig_id = 11, + .flow_sig_id = 917512, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [211] = { - .class_hid = BNXT_ULP_CLASS_HID_45a55, + .class_hid = BNXT_ULP_CLASS_HID_2843, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672, + .hdr_sig_id = 11, + .flow_sig_id = 917568, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [212] = { - .class_hid = BNXT_ULP_CLASS_HID_40a21, + .class_hid = BNXT_ULP_CLASS_HID_589b, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28680, + .hdr_sig_id = 11, + .flow_sig_id = 917576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [213] = { - .class_hid = BNXT_ULP_CLASS_HID_41745, + .class_hid = BNXT_ULP_CLASS_HID_5c53, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672, + .hdr_sig_id = 11, + .flow_sig_id = 983040, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [214] = { - .class_hid = BNXT_ULP_CLASS_HID_423dd, + .class_hid = BNXT_ULP_CLASS_HID_2467, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28680, + .hdr_sig_id = 11, + .flow_sig_id = 983048, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [215] = { - .class_hid = BNXT_ULP_CLASS_HID_41d81, + .class_hid = BNXT_ULP_CLASS_HID_484f, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672, + .hdr_sig_id = 11, + .flow_sig_id = 983104, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [216] = { - .class_hid = BNXT_ULP_CLASS_HID_42a19, + .class_hid = BNXT_ULP_CLASS_HID_1053, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28680, + .hdr_sig_id = 11, + .flow_sig_id = 983112, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [217] = { - .class_hid = BNXT_ULP_CLASS_HID_42df9, + .class_hid = BNXT_ULP_CLASS_HID_5ce1, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } }, [218] = { - .class_hid = BNXT_ULP_CLASS_HID_43a71, + .class_hid = BNXT_ULP_CLASS_HID_4579, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30728, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } }, [219] = { - .class_hid = BNXT_ULP_CLASS_HID_43435, + .class_hid = BNXT_ULP_CLASS_HID_1735, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } }, [220] = { - .class_hid = BNXT_ULP_CLASS_HID_4404d, + .class_hid = BNXT_ULP_CLASS_HID_45bd, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30728, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } }, [221] = { - .class_hid = BNXT_ULP_CLASS_HID_44dd1, + .class_hid = BNXT_ULP_CLASS_HID_3feb, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [222] = { - .class_hid = BNXT_ULP_CLASS_HID_45a69, + .class_hid = BNXT_ULP_CLASS_HID_2bf7, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30728, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [223] = { - .class_hid = BNXT_ULP_CLASS_HID_4542d, + .class_hid = BNXT_ULP_CLASS_HID_5727, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [224] = { - .class_hid = BNXT_ULP_CLASS_HID_403f9, + .class_hid = BNXT_ULP_CLASS_HID_4333, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30728, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } }, [225] = { - .class_hid = BNXT_ULP_CLASS_HID_4140d, + .class_hid = BNXT_ULP_CLASS_HID_4453, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [226] = { - .class_hid = BNXT_ULP_CLASS_HID_420b5, + .class_hid = BNXT_ULP_CLASS_HID_304f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16392, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [227] = { - .class_hid = BNXT_ULP_CLASS_HID_41a49, + .class_hid = BNXT_ULP_CLASS_HID_645f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [228] = { - .class_hid = BNXT_ULP_CLASS_HID_426f1, + .class_hid = BNXT_ULP_CLASS_HID_504b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16392, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } }, [229] = { - .class_hid = BNXT_ULP_CLASS_HID_44ab9, + .class_hid = BNXT_ULP_CLASS_HID_5cc1, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } }, [230] = { - .class_hid = BNXT_ULP_CLASS_HID_45721, + .class_hid = BNXT_ULP_CLASS_HID_4559, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16392, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } }, [231] = { - .class_hid = BNXT_ULP_CLASS_HID_450e5, + .class_hid = BNXT_ULP_CLASS_HID_2285, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } }, [232] = { - .class_hid = BNXT_ULP_CLASS_HID_40051, + .class_hid = BNXT_ULP_CLASS_HID_0b1d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16392, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } }, [233] = { - .class_hid = BNXT_ULP_CLASS_HID_40aa5, + .class_hid = BNXT_ULP_CLASS_HID_0b49, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [234] = { - .class_hid = BNXT_ULP_CLASS_HID_4172d, + .class_hid = BNXT_ULP_CLASS_HID_5c95, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24584, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [235] = { - .class_hid = BNXT_ULP_CLASS_HID_410e1, + .class_hid = BNXT_ULP_CLASS_HID_39c1, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [236] = { - .class_hid = BNXT_ULP_CLASS_HID_41d69, + .class_hid = BNXT_ULP_CLASS_HID_2259, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24584, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } }, [237] = { - .class_hid = BNXT_ULP_CLASS_HID_440d1, + .class_hid = BNXT_ULP_CLASS_HID_1715, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 0, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } }, [238] = { - .class_hid = BNXT_ULP_CLASS_HID_44d59, + .class_hid = BNXT_ULP_CLASS_HID_459d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24584, - .flow_pattern_id = 0, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } }, [239] = { - .class_hid = BNXT_ULP_CLASS_HID_4471d, + .class_hid = BNXT_ULP_CLASS_HID_571d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 0, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } }, [240] = { - .class_hid = BNXT_ULP_CLASS_HID_45385, + .class_hid = BNXT_ULP_CLASS_HID_1cd1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24584, - .flow_pattern_id = 0, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } }, [241] = { - .class_hid = BNXT_ULP_CLASS_HID_6400d, + .class_hid = BNXT_ULP_CLASS_HID_3711, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 0, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [242] = { - .class_hid = BNXT_ULP_CLASS_HID_64cb5, + .class_hid = BNXT_ULP_CLASS_HID_6599, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49160, - .flow_pattern_id = 0, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [243] = { - .class_hid = BNXT_ULP_CLASS_HID_64649, + .class_hid = BNXT_ULP_CLASS_HID_0e55, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 0, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [244] = { - .class_hid = BNXT_ULP_CLASS_HID_652f1, + .class_hid = BNXT_ULP_CLASS_HID_3cdd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49160, - .flow_pattern_id = 0, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } }, [245] = { - .class_hid = BNXT_ULP_CLASS_HID_619ed, + .class_hid = BNXT_ULP_CLASS_HID_5ca1, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } }, [246] = { - .class_hid = BNXT_ULP_CLASS_HID_62615, + .class_hid = BNXT_ULP_CLASS_HID_4539, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49160, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } }, [247] = { - .class_hid = BNXT_ULP_CLASS_HID_62029, + .class_hid = BNXT_ULP_CLASS_HID_22e5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } }, [248] = { - .class_hid = BNXT_ULP_CLASS_HID_62c51, + .class_hid = BNXT_ULP_CLASS_HID_0b7d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49160, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } }, [249] = { - .class_hid = BNXT_ULP_CLASS_HID_636a5, + .class_hid = BNXT_ULP_CLASS_HID_0b29, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [250] = { - .class_hid = BNXT_ULP_CLASS_HID_6432d, + .class_hid = BNXT_ULP_CLASS_HID_5cf5, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57352, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [251] = { - .class_hid = BNXT_ULP_CLASS_HID_63ce1, + .class_hid = BNXT_ULP_CLASS_HID_39a1, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [252] = { - .class_hid = BNXT_ULP_CLASS_HID_64969, + .class_hid = BNXT_ULP_CLASS_HID_2239, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57352, - .flow_pattern_id = 0, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } }, [253] = { - .class_hid = BNXT_ULP_CLASS_HID_61005, + .class_hid = BNXT_ULP_CLASS_HID_1775, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } }, [254] = { - .class_hid = BNXT_ULP_CLASS_HID_61c8d, + .class_hid = BNXT_ULP_CLASS_HID_45fd, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57352, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } }, [255] = { - .class_hid = BNXT_ULP_CLASS_HID_61641, + .class_hid = BNXT_ULP_CLASS_HID_577d, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } }, [256] = { - .class_hid = BNXT_ULP_CLASS_HID_622c9, + .class_hid = BNXT_ULP_CLASS_HID_1cb1, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57352, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } }, [257] = { - .class_hid = BNXT_ULP_CLASS_HID_52a0d, + .class_hid = BNXT_ULP_CLASS_HID_3771, .class_tid = 1, - .hdr_sig_id = 5, + .hdr_sig_id = 7, .flow_sig_id = 81920, - .flow_pattern_id = 0, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [258] = { - .class_hid = BNXT_ULP_CLASS_HID_536b5, + .class_hid = BNXT_ULP_CLASS_HID_65f9, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81928, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [259] = { - .class_hid = BNXT_ULP_CLASS_HID_53049, + .class_hid = BNXT_ULP_CLASS_HID_0e35, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [260] = { - .class_hid = BNXT_ULP_CLASS_HID_53cf1, + .class_hid = BNXT_ULP_CLASS_HID_3cbd, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81928, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } }, [261] = { - .class_hid = BNXT_ULP_CLASS_HID_503ed, + .class_hid = BNXT_ULP_CLASS_HID_3fcb, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [262] = { - .class_hid = BNXT_ULP_CLASS_HID_51015, + .class_hid = BNXT_ULP_CLASS_HID_2bd7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81928, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [263] = { - .class_hid = BNXT_ULP_CLASS_HID_50a29, + .class_hid = BNXT_ULP_CLASS_HID_5707, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [264] = { - .class_hid = BNXT_ULP_CLASS_HID_51651, + .class_hid = BNXT_ULP_CLASS_HID_4313, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81928, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } }, [265] = { - .class_hid = BNXT_ULP_CLASS_HID_520a5, + .class_hid = BNXT_ULP_CLASS_HID_5fc7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [266] = { - .class_hid = BNXT_ULP_CLASS_HID_52d2d, + .class_hid = BNXT_ULP_CLASS_HID_4bd3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90120, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [267] = { - .class_hid = BNXT_ULP_CLASS_HID_526e1, + .class_hid = BNXT_ULP_CLASS_HID_0e4f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [268] = { - .class_hid = BNXT_ULP_CLASS_HID_53369, + .class_hid = BNXT_ULP_CLASS_HID_632f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90120, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } }, [269] = { - .class_hid = BNXT_ULP_CLASS_HID_556d1, + .class_hid = BNXT_ULP_CLASS_HID_1baf, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [270] = { - .class_hid = BNXT_ULP_CLASS_HID_5068d, + .class_hid = BNXT_ULP_CLASS_HID_07bb, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90120, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [271] = { - .class_hid = BNXT_ULP_CLASS_HID_50041, + .class_hid = BNXT_ULP_CLASS_HID_32eb, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [272] = { - .class_hid = BNXT_ULP_CLASS_HID_50cc9, + .class_hid = BNXT_ULP_CLASS_HID_1ef7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90120, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [273] = { - .class_hid = BNXT_ULP_CLASS_HID_7560d, + .class_hid = BNXT_ULP_CLASS_HID_3bab, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [274] = { - .class_hid = BNXT_ULP_CLASS_HID_705f9, + .class_hid = BNXT_ULP_CLASS_HID_27b7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114696, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [275] = { - .class_hid = BNXT_ULP_CLASS_HID_75c49, + .class_hid = BNXT_ULP_CLASS_HID_52e7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [276] = { - .class_hid = BNXT_ULP_CLASS_HID_70c25, + .class_hid = BNXT_ULP_CLASS_HID_3ef3, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114696, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } }, [277] = { - .class_hid = BNXT_ULP_CLASS_HID_72fed, + .class_hid = BNXT_ULP_CLASS_HID_4473, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [278] = { - .class_hid = BNXT_ULP_CLASS_HID_73c15, + .class_hid = BNXT_ULP_CLASS_HID_306f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114696, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [279] = { - .class_hid = BNXT_ULP_CLASS_HID_73629, + .class_hid = BNXT_ULP_CLASS_HID_647f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [280] = { - .class_hid = BNXT_ULP_CLASS_HID_74251, + .class_hid = BNXT_ULP_CLASS_HID_506b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114696, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } }, [281] = { - .class_hid = BNXT_ULP_CLASS_HID_74ca5, + .class_hid = BNXT_ULP_CLASS_HID_66af, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [282] = { - .class_hid = BNXT_ULP_CLASS_HID_7592d, + .class_hid = BNXT_ULP_CLASS_HID_525b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122888, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [283] = { - .class_hid = BNXT_ULP_CLASS_HID_752e1, + .class_hid = BNXT_ULP_CLASS_HID_1de7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [284] = { - .class_hid = BNXT_ULP_CLASS_HID_7025d, + .class_hid = BNXT_ULP_CLASS_HID_0993, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122888, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } }, [285] = { - .class_hid = BNXT_ULP_CLASS_HID_72605, + .class_hid = BNXT_ULP_CLASS_HID_213f, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [286] = { - .class_hid = BNXT_ULP_CLASS_HID_7328d, + .class_hid = BNXT_ULP_CLASS_HID_0d2b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122888, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [287] = { - .class_hid = BNXT_ULP_CLASS_HID_72c41, + .class_hid = BNXT_ULP_CLASS_HID_413b, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [288] = { - .class_hid = BNXT_ULP_CLASS_HID_738c9, + .class_hid = BNXT_ULP_CLASS_HID_2cd7, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122888, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [289] = { - .class_hid = BNXT_ULP_CLASS_HID_0591, + .class_hid = BNXT_ULP_CLASS_HID_436b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [290] = { - .class_hid = BNXT_ULP_CLASS_HID_1269, + .class_hid = BNXT_ULP_CLASS_HID_2f07, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4104, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [291] = { - .class_hid = BNXT_ULP_CLASS_HID_0bad, + .class_hid = BNXT_ULP_CLASS_HID_6317, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [292] = { - .class_hid = BNXT_ULP_CLASS_HID_1825, + .class_hid = BNXT_ULP_CLASS_HID_4f03, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4104, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } }, [293] = { - .class_hid = BNXT_ULP_CLASS_HID_2589, + .class_hid = BNXT_ULP_CLASS_HID_3fab, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [294] = { - .class_hid = BNXT_ULP_CLASS_HID_3201, + .class_hid = BNXT_ULP_CLASS_HID_2bb7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4104, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [295] = { - .class_hid = BNXT_ULP_CLASS_HID_2c45, + .class_hid = BNXT_ULP_CLASS_HID_5767, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [296] = { - .class_hid = BNXT_ULP_CLASS_HID_38dd, + .class_hid = BNXT_ULP_CLASS_HID_4373, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4104, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } }, [297] = { - .class_hid = BNXT_ULP_CLASS_HID_3c7d, + .class_hid = BNXT_ULP_CLASS_HID_5fa7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [298] = { - .class_hid = BNXT_ULP_CLASS_HID_48f5, + .class_hid = BNXT_ULP_CLASS_HID_4bb3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6152, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [299] = { - .class_hid = BNXT_ULP_CLASS_HID_4239, + .class_hid = BNXT_ULP_CLASS_HID_0e2f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [300] = { - .class_hid = BNXT_ULP_CLASS_HID_4eb1, + .class_hid = BNXT_ULP_CLASS_HID_634f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6152, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } }, [301] = { - .class_hid = BNXT_ULP_CLASS_HID_5c15, + .class_hid = BNXT_ULP_CLASS_HID_1bcf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [302] = { - .class_hid = BNXT_ULP_CLASS_HID_0ba1, + .class_hid = BNXT_ULP_CLASS_HID_07db, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6152, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [303] = { - .class_hid = BNXT_ULP_CLASS_HID_05e5, + .class_hid = BNXT_ULP_CLASS_HID_328b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [304] = { - .class_hid = BNXT_ULP_CLASS_HID_127d, + .class_hid = BNXT_ULP_CLASS_HID_1e97, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6152, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [305] = { - .class_hid = BNXT_ULP_CLASS_HID_58a5, + .class_hid = BNXT_ULP_CLASS_HID_3bcb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [306] = { - .class_hid = BNXT_ULP_CLASS_HID_08f1, + .class_hid = BNXT_ULP_CLASS_HID_27d7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12296, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [307] = { - .class_hid = BNXT_ULP_CLASS_HID_0235, + .class_hid = BNXT_ULP_CLASS_HID_5287, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [308] = { - .class_hid = BNXT_ULP_CLASS_HID_0e8d, + .class_hid = BNXT_ULP_CLASS_HID_3e93, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12296, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } }, [309] = { - .class_hid = BNXT_ULP_CLASS_HID_1c11, + .class_hid = BNXT_ULP_CLASS_HID_4413, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [310] = { - .class_hid = BNXT_ULP_CLASS_HID_28e9, + .class_hid = BNXT_ULP_CLASS_HID_300f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12296, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [311] = { - .class_hid = BNXT_ULP_CLASS_HID_222d, + .class_hid = BNXT_ULP_CLASS_HID_641f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [312] = { - .class_hid = BNXT_ULP_CLASS_HID_2ea5, + .class_hid = BNXT_ULP_CLASS_HID_500b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12296, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } }, [313] = { - .class_hid = BNXT_ULP_CLASS_HID_32c5, + .class_hid = BNXT_ULP_CLASS_HID_66cf, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [314] = { - .class_hid = BNXT_ULP_CLASS_HID_3f5d, + .class_hid = BNXT_ULP_CLASS_HID_523b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14344, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [315] = { - .class_hid = BNXT_ULP_CLASS_HID_3881, + .class_hid = BNXT_ULP_CLASS_HID_1d87, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [316] = { - .class_hid = BNXT_ULP_CLASS_HID_4519, + .class_hid = BNXT_ULP_CLASS_HID_09f3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14344, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } }, [317] = { - .class_hid = BNXT_ULP_CLASS_HID_52fd, + .class_hid = BNXT_ULP_CLASS_HID_215f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [318] = { - .class_hid = BNXT_ULP_CLASS_HID_0209, + .class_hid = BNXT_ULP_CLASS_HID_0d4b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14344, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [319] = { - .class_hid = BNXT_ULP_CLASS_HID_58b9, + .class_hid = BNXT_ULP_CLASS_HID_415b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [320] = { - .class_hid = BNXT_ULP_CLASS_HID_08c5, + .class_hid = BNXT_ULP_CLASS_HID_2cb7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14344, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [321] = { - .class_hid = BNXT_ULP_CLASS_HID_400a5, + .class_hid = BNXT_ULP_CLASS_HID_430b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [322] = { - .class_hid = BNXT_ULP_CLASS_HID_40d3d, + .class_hid = BNXT_ULP_CLASS_HID_2f67, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20488, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [323] = { - .class_hid = BNXT_ULP_CLASS_HID_40761, + .class_hid = BNXT_ULP_CLASS_HID_6377, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [324] = { - .class_hid = BNXT_ULP_CLASS_HID_413f9, + .class_hid = BNXT_ULP_CLASS_HID_4f63, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20488, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } }, [325] = { - .class_hid = BNXT_ULP_CLASS_HID_4215d, + .class_hid = BNXT_ULP_CLASS_HID_29b5, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 0, + .hdr_sig_id = 0, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC } }, [326] = { - .class_hid = BNXT_ULP_CLASS_HID_42dd5, + .class_hid = BNXT_ULP_CLASS_HID_29ad, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20488, - .flow_pattern_id = 0, + .hdr_sig_id = 1, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC } }, [327] = { - .class_hid = BNXT_ULP_CLASS_HID_42719, + .class_hid = BNXT_ULP_CLASS_HID_29b7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC } }, [328] = { - .class_hid = BNXT_ULP_CLASS_HID_43391, + .class_hid = BNXT_ULP_CLASS_HID_1583, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20488, - .flow_pattern_id = 0, + .hdr_sig_id = 2, + .flow_sig_id = 72, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID } }, [329] = { - .class_hid = BNXT_ULP_CLASS_HID_43731, + .class_hid = BNXT_ULP_CLASS_HID_29af, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC } }, [330] = { - .class_hid = BNXT_ULP_CLASS_HID_44389, + .class_hid = BNXT_ULP_CLASS_HID_159b, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22536, - .flow_pattern_id = 0, + .hdr_sig_id = 3, + .flow_sig_id = 72, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID } }, [331] = { - .class_hid = BNXT_ULP_CLASS_HID_43dcd, + .class_hid = BNXT_ULP_CLASS_HID_2995, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 0, + .hdr_sig_id = 4, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC } }, [332] = { - .class_hid = BNXT_ULP_CLASS_HID_44a45, + .class_hid = BNXT_ULP_CLASS_HID_298d, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22536, - .flow_pattern_id = 0, + .hdr_sig_id = 5, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC } }, [333] = { - .class_hid = BNXT_ULP_CLASS_HID_45729, + .class_hid = BNXT_ULP_CLASS_HID_29f5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 0, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | @@ -10821,81331 +6437,3442 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC } }, [334] = { - .class_hid = BNXT_ULP_CLASS_HID_40775, + .class_hid = BNXT_ULP_CLASS_HID_29ed, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22536, - .flow_pattern_id = 0, + .hdr_sig_id = 7, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC } }, [335] = { - .class_hid = BNXT_ULP_CLASS_HID_400b9, + .class_hid = BNXT_ULP_CLASS_HID_2997, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC } }, [336] = { - .class_hid = BNXT_ULP_CLASS_HID_40d31, + .class_hid = BNXT_ULP_CLASS_HID_15a3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22536, - .flow_pattern_id = 0, + .hdr_sig_id = 8, + .flow_sig_id = 72, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID } }, [337] = { - .class_hid = BNXT_ULP_CLASS_HID_45479, + .class_hid = BNXT_ULP_CLASS_HID_298f, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC } }, [338] = { - .class_hid = BNXT_ULP_CLASS_HID_40385, + .class_hid = BNXT_ULP_CLASS_HID_15bb, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28680, - .flow_pattern_id = 0, + .hdr_sig_id = 9, + .flow_sig_id = 72, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID } }, [339] = { - .class_hid = BNXT_ULP_CLASS_HID_45a35, + .class_hid = BNXT_ULP_CLASS_HID_29f7, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC } }, [340] = { - .class_hid = BNXT_ULP_CLASS_HID_40a41, + .class_hid = BNXT_ULP_CLASS_HID_15c3, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28680, - .flow_pattern_id = 0, + .hdr_sig_id = 10, + .flow_sig_id = 72, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID } }, [341] = { - .class_hid = BNXT_ULP_CLASS_HID_41725, + .class_hid = BNXT_ULP_CLASS_HID_29ef, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 8, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC } }, [342] = { - .class_hid = BNXT_ULP_CLASS_HID_423bd, + .class_hid = BNXT_ULP_CLASS_HID_15db, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28680, - .flow_pattern_id = 0, + .hdr_sig_id = 11, + .flow_sig_id = 72, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID } }, [343] = { - .class_hid = BNXT_ULP_CLASS_HID_41de1, + .class_hid = BNXT_ULP_CLASS_HID_1151, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 0, + .hdr_sig_id = 12, + .flow_sig_id = 16384, + .flow_pattern_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR } }, [344] = { - .class_hid = BNXT_ULP_CLASS_HID_42a79, + .class_hid = BNXT_ULP_CLASS_HID_315d, .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28680, - .flow_pattern_id = 0, + .hdr_sig_id = 12, + .flow_sig_id = 81920, + .flow_pattern_id = 3, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT } }, [345] = { - .class_hid = BNXT_ULP_CLASS_HID_42d99, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720, + .class_hid = BNXT_ULP_CLASS_HID_34c6, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4096, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } }, [346] = { - .class_hid = BNXT_ULP_CLASS_HID_43a11, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30728, + .class_hid = BNXT_ULP_CLASS_HID_0c22, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4100, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } }, [347] = { - .class_hid = BNXT_ULP_CLASS_HID_43455, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720, + .class_hid = BNXT_ULP_CLASS_HID_1cbe, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6144, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } }, [348] = { - .class_hid = BNXT_ULP_CLASS_HID_4402d, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30728, + .class_hid = BNXT_ULP_CLASS_HID_179a, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6148, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } }, [349] = { - .class_hid = BNXT_ULP_CLASS_HID_44db1, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720, + .class_hid = BNXT_ULP_CLASS_HID_59be, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16384, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } }, [350] = { - .class_hid = BNXT_ULP_CLASS_HID_45a09, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30728, + .class_hid = BNXT_ULP_CLASS_HID_515a, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16388, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } }, [351] = { - .class_hid = BNXT_ULP_CLASS_HID_4544d, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720, + .class_hid = BNXT_ULP_CLASS_HID_1c72, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24576, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } }, [352] = { - .class_hid = BNXT_ULP_CLASS_HID_40399, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30728, + .class_hid = BNXT_ULP_CLASS_HID_171e, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24580, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } }, [353] = { - .class_hid = BNXT_ULP_CLASS_HID_4146d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384, + .class_hid = BNXT_ULP_CLASS_HID_19c8, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32768, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, [354] = { - .class_hid = BNXT_ULP_CLASS_HID_420d5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16392, + .class_hid = BNXT_ULP_CLASS_HID_112c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32772, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, [355] = { - .class_hid = BNXT_ULP_CLASS_HID_41a29, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384, + .class_hid = BNXT_ULP_CLASS_HID_4d68, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32832, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, [356] = { - .class_hid = BNXT_ULP_CLASS_HID_42691, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16392, + .class_hid = BNXT_ULP_CLASS_HID_444c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32836, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, [357] = { - .class_hid = BNXT_ULP_CLASS_HID_44ad9, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384, + .class_hid = BNXT_ULP_CLASS_HID_0e8c, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49152, .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, [358] = { - .class_hid = BNXT_ULP_CLASS_HID_45741, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16392, + .class_hid = BNXT_ULP_CLASS_HID_09e0, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 49156, .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [359] = { - .class_hid = BNXT_ULP_CLASS_HID_45085, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [360] = { - .class_hid = BNXT_ULP_CLASS_HID_40031, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16392, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [361] = { - .class_hid = BNXT_ULP_CLASS_HID_40ac5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [362] = { - .class_hid = BNXT_ULP_CLASS_HID_4174d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24584, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [363] = { - .class_hid = BNXT_ULP_CLASS_HID_41081, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [364] = { - .class_hid = BNXT_ULP_CLASS_HID_41d09, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24584, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [365] = { - .class_hid = BNXT_ULP_CLASS_HID_440b1, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [366] = { - .class_hid = BNXT_ULP_CLASS_HID_44d39, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24584, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [367] = { - .class_hid = BNXT_ULP_CLASS_HID_4477d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [368] = { - .class_hid = BNXT_ULP_CLASS_HID_453e5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24584, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [369] = { - .class_hid = BNXT_ULP_CLASS_HID_6406d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [370] = { - .class_hid = BNXT_ULP_CLASS_HID_64cd5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [371] = { - .class_hid = BNXT_ULP_CLASS_HID_64629, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [372] = { - .class_hid = BNXT_ULP_CLASS_HID_65291, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [373] = { - .class_hid = BNXT_ULP_CLASS_HID_6198d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [374] = { - .class_hid = BNXT_ULP_CLASS_HID_62675, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [375] = { - .class_hid = BNXT_ULP_CLASS_HID_62049, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [376] = { - .class_hid = BNXT_ULP_CLASS_HID_62c31, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [377] = { - .class_hid = BNXT_ULP_CLASS_HID_636c5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [378] = { - .class_hid = BNXT_ULP_CLASS_HID_6434d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57352, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [379] = { - .class_hid = BNXT_ULP_CLASS_HID_63c81, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [380] = { - .class_hid = BNXT_ULP_CLASS_HID_64909, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57352, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [381] = { - .class_hid = BNXT_ULP_CLASS_HID_61065, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [382] = { - .class_hid = BNXT_ULP_CLASS_HID_61ced, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57352, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [383] = { - .class_hid = BNXT_ULP_CLASS_HID_61621, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [384] = { - .class_hid = BNXT_ULP_CLASS_HID_622a9, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57352, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [385] = { - .class_hid = BNXT_ULP_CLASS_HID_52a6d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [386] = { - .class_hid = BNXT_ULP_CLASS_HID_536d5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81928, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [387] = { - .class_hid = BNXT_ULP_CLASS_HID_53029, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [388] = { - .class_hid = BNXT_ULP_CLASS_HID_53c91, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81928, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [389] = { - .class_hid = BNXT_ULP_CLASS_HID_5038d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [390] = { - .class_hid = BNXT_ULP_CLASS_HID_51075, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81928, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [391] = { - .class_hid = BNXT_ULP_CLASS_HID_50a49, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [392] = { - .class_hid = BNXT_ULP_CLASS_HID_51631, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81928, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [393] = { - .class_hid = BNXT_ULP_CLASS_HID_520c5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [394] = { - .class_hid = BNXT_ULP_CLASS_HID_52d4d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90120, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [395] = { - .class_hid = BNXT_ULP_CLASS_HID_52681, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [396] = { - .class_hid = BNXT_ULP_CLASS_HID_53309, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90120, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [397] = { - .class_hid = BNXT_ULP_CLASS_HID_556b1, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [398] = { - .class_hid = BNXT_ULP_CLASS_HID_506ed, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90120, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [399] = { - .class_hid = BNXT_ULP_CLASS_HID_50021, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [400] = { - .class_hid = BNXT_ULP_CLASS_HID_50ca9, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90120, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [401] = { - .class_hid = BNXT_ULP_CLASS_HID_7566d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [402] = { - .class_hid = BNXT_ULP_CLASS_HID_70599, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [403] = { - .class_hid = BNXT_ULP_CLASS_HID_75c29, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [404] = { - .class_hid = BNXT_ULP_CLASS_HID_70c45, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [405] = { - .class_hid = BNXT_ULP_CLASS_HID_72f8d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [406] = { - .class_hid = BNXT_ULP_CLASS_HID_73c75, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [407] = { - .class_hid = BNXT_ULP_CLASS_HID_73649, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [408] = { - .class_hid = BNXT_ULP_CLASS_HID_74231, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [409] = { - .class_hid = BNXT_ULP_CLASS_HID_74cc5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [410] = { - .class_hid = BNXT_ULP_CLASS_HID_7594d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122888, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [411] = { - .class_hid = BNXT_ULP_CLASS_HID_75281, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [412] = { - .class_hid = BNXT_ULP_CLASS_HID_7023d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122888, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [413] = { - .class_hid = BNXT_ULP_CLASS_HID_72665, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [414] = { - .class_hid = BNXT_ULP_CLASS_HID_732ed, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122888, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [415] = { - .class_hid = BNXT_ULP_CLASS_HID_72c21, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [416] = { - .class_hid = BNXT_ULP_CLASS_HID_738a9, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122888, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [417] = { - .class_hid = BNXT_ULP_CLASS_HID_244c3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [418] = { - .class_hid = BNXT_ULP_CLASS_HID_2515b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [419] = { - .class_hid = BNXT_ULP_CLASS_HID_24b1f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [420] = { - .class_hid = BNXT_ULP_CLASS_HID_25797, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [421] = { - .class_hid = BNXT_ULP_CLASS_HID_22f7f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [422] = { - .class_hid = BNXT_ULP_CLASS_HID_23bf7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [423] = { - .class_hid = BNXT_ULP_CLASS_HID_235bb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [424] = { - .class_hid = BNXT_ULP_CLASS_HID_24233, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [425] = { - .class_hid = BNXT_ULP_CLASS_HID_20b8b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [426] = { - .class_hid = BNXT_ULP_CLASS_HID_21803, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [427] = { - .class_hid = BNXT_ULP_CLASS_HID_211c7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [428] = { - .class_hid = BNXT_ULP_CLASS_HID_21e5f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [429] = { - .class_hid = BNXT_ULP_CLASS_HID_252d3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [430] = { - .class_hid = BNXT_ULP_CLASS_HID_202bf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [431] = { - .class_hid = BNXT_ULP_CLASS_HID_2592f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [432] = { - .class_hid = BNXT_ULP_CLASS_HID_208fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [433] = { - .class_hid = BNXT_ULP_CLASS_HID_231f3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [434] = { - .class_hid = BNXT_ULP_CLASS_HID_23e0b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [435] = { - .class_hid = BNXT_ULP_CLASS_HID_237cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [436] = { - .class_hid = BNXT_ULP_CLASS_HID_24447, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [437] = { - .class_hid = BNXT_ULP_CLASS_HID_21c2f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [438] = { - .class_hid = BNXT_ULP_CLASS_HID_228a7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [439] = { - .class_hid = BNXT_ULP_CLASS_HID_2226b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [440] = { - .class_hid = BNXT_ULP_CLASS_HID_22ee3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [441] = { - .class_hid = BNXT_ULP_CLASS_HID_25567, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [442] = { - .class_hid = BNXT_ULP_CLASS_HID_20533, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [443] = { - .class_hid = BNXT_ULP_CLASS_HID_25ba3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [444] = { - .class_hid = BNXT_ULP_CLASS_HID_20b0f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [445] = { - .class_hid = BNXT_ULP_CLASS_HID_23f83, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [446] = { - .class_hid = BNXT_ULP_CLASS_HID_24c1b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [447] = { - .class_hid = BNXT_ULP_CLASS_HID_245df, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [448] = { - .class_hid = BNXT_ULP_CLASS_HID_25257, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [449] = { - .class_hid = BNXT_ULP_CLASS_HID_64017, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [450] = { - .class_hid = BNXT_ULP_CLASS_HID_64caf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [451] = { - .class_hid = BNXT_ULP_CLASS_HID_64653, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [452] = { - .class_hid = BNXT_ULP_CLASS_HID_652eb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [453] = { - .class_hid = BNXT_ULP_CLASS_HID_62ab3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [454] = { - .class_hid = BNXT_ULP_CLASS_HID_636cb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [455] = { - .class_hid = BNXT_ULP_CLASS_HID_6308f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [456] = { - .class_hid = BNXT_ULP_CLASS_HID_63d07, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [457] = { - .class_hid = BNXT_ULP_CLASS_HID_606df, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [458] = { - .class_hid = BNXT_ULP_CLASS_HID_61357, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [459] = { - .class_hid = BNXT_ULP_CLASS_HID_60d1b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [460] = { - .class_hid = BNXT_ULP_CLASS_HID_61993, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [461] = { - .class_hid = BNXT_ULP_CLASS_HID_64e27, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [462] = { - .class_hid = BNXT_ULP_CLASS_HID_65abf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [463] = { - .class_hid = BNXT_ULP_CLASS_HID_65463, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [464] = { - .class_hid = BNXT_ULP_CLASS_HID_603cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [465] = { - .class_hid = BNXT_ULP_CLASS_HID_62cc7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [466] = { - .class_hid = BNXT_ULP_CLASS_HID_6395f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [467] = { - .class_hid = BNXT_ULP_CLASS_HID_63303, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [468] = { - .class_hid = BNXT_ULP_CLASS_HID_63f9b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [469] = { - .class_hid = BNXT_ULP_CLASS_HID_61763, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [470] = { - .class_hid = BNXT_ULP_CLASS_HID_623fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [471] = { - .class_hid = BNXT_ULP_CLASS_HID_61dbf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [472] = { - .class_hid = BNXT_ULP_CLASS_HID_62a37, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [473] = { - .class_hid = BNXT_ULP_CLASS_HID_650bb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [474] = { - .class_hid = BNXT_ULP_CLASS_HID_60007, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [475] = { - .class_hid = BNXT_ULP_CLASS_HID_656f7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [476] = { - .class_hid = BNXT_ULP_CLASS_HID_60643, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [477] = { - .class_hid = BNXT_ULP_CLASS_HID_63ad7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [478] = { - .class_hid = BNXT_ULP_CLASS_HID_6476f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [479] = { - .class_hid = BNXT_ULP_CLASS_HID_64113, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [480] = { - .class_hid = BNXT_ULP_CLASS_HID_64dab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [481] = { - .class_hid = BNXT_ULP_CLASS_HID_35ac3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [482] = { - .class_hid = BNXT_ULP_CLASS_HID_30aaf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [483] = { - .class_hid = BNXT_ULP_CLASS_HID_30453, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [484] = { - .class_hid = BNXT_ULP_CLASS_HID_310eb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [485] = { - .class_hid = BNXT_ULP_CLASS_HID_3457f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [486] = { - .class_hid = BNXT_ULP_CLASS_HID_351f7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [487] = { - .class_hid = BNXT_ULP_CLASS_HID_34bbb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [488] = { - .class_hid = BNXT_ULP_CLASS_HID_35833, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [489] = { - .class_hid = BNXT_ULP_CLASS_HID_3218b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [490] = { - .class_hid = BNXT_ULP_CLASS_HID_32e03, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [491] = { - .class_hid = BNXT_ULP_CLASS_HID_327c7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [492] = { - .class_hid = BNXT_ULP_CLASS_HID_3345f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [493] = { - .class_hid = BNXT_ULP_CLASS_HID_30c27, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [494] = { - .class_hid = BNXT_ULP_CLASS_HID_318bf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [495] = { - .class_hid = BNXT_ULP_CLASS_HID_31263, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [496] = { - .class_hid = BNXT_ULP_CLASS_HID_31efb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [497] = { - .class_hid = BNXT_ULP_CLASS_HID_347f3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [498] = { - .class_hid = BNXT_ULP_CLASS_HID_3540b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [499] = { - .class_hid = BNXT_ULP_CLASS_HID_34dcf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [500] = { - .class_hid = BNXT_ULP_CLASS_HID_35a47, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [501] = { - .class_hid = BNXT_ULP_CLASS_HID_3322f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [502] = { - .class_hid = BNXT_ULP_CLASS_HID_33ea7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [503] = { - .class_hid = BNXT_ULP_CLASS_HID_3386b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [504] = { - .class_hid = BNXT_ULP_CLASS_HID_344e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [505] = { - .class_hid = BNXT_ULP_CLASS_HID_30ebb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [506] = { - .class_hid = BNXT_ULP_CLASS_HID_31b33, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [507] = { - .class_hid = BNXT_ULP_CLASS_HID_314f7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [508] = { - .class_hid = BNXT_ULP_CLASS_HID_3210f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [509] = { - .class_hid = BNXT_ULP_CLASS_HID_35583, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [510] = { - .class_hid = BNXT_ULP_CLASS_HID_3056f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [511] = { - .class_hid = BNXT_ULP_CLASS_HID_35bdf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [512] = { - .class_hid = BNXT_ULP_CLASS_HID_30bab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [513] = { - .class_hid = BNXT_ULP_CLASS_HID_75617, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [514] = { - .class_hid = BNXT_ULP_CLASS_HID_705e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [515] = { - .class_hid = BNXT_ULP_CLASS_HID_75c53, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [516] = { - .class_hid = BNXT_ULP_CLASS_HID_70c3f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [517] = { - .class_hid = BNXT_ULP_CLASS_HID_740b3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [518] = { - .class_hid = BNXT_ULP_CLASS_HID_74ccb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [519] = { - .class_hid = BNXT_ULP_CLASS_HID_7468f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [520] = { - .class_hid = BNXT_ULP_CLASS_HID_75307, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [521] = { - .class_hid = BNXT_ULP_CLASS_HID_71cdf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [522] = { - .class_hid = BNXT_ULP_CLASS_HID_72957, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [523] = { - .class_hid = BNXT_ULP_CLASS_HID_7231b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [524] = { - .class_hid = BNXT_ULP_CLASS_HID_72f93, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [525] = { - .class_hid = BNXT_ULP_CLASS_HID_7077b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [526] = { - .class_hid = BNXT_ULP_CLASS_HID_713f3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [527] = { - .class_hid = BNXT_ULP_CLASS_HID_70db7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [528] = { - .class_hid = BNXT_ULP_CLASS_HID_719cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [529] = { - .class_hid = BNXT_ULP_CLASS_HID_742c7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [530] = { - .class_hid = BNXT_ULP_CLASS_HID_74f5f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [531] = { - .class_hid = BNXT_ULP_CLASS_HID_74903, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [532] = { - .class_hid = BNXT_ULP_CLASS_HID_7559b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [533] = { - .class_hid = BNXT_ULP_CLASS_HID_72d63, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [534] = { - .class_hid = BNXT_ULP_CLASS_HID_739fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [535] = { - .class_hid = BNXT_ULP_CLASS_HID_733bf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [536] = { - .class_hid = BNXT_ULP_CLASS_HID_74037, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [537] = { - .class_hid = BNXT_ULP_CLASS_HID_7098f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [538] = { - .class_hid = BNXT_ULP_CLASS_HID_71607, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [539] = { - .class_hid = BNXT_ULP_CLASS_HID_70fcb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [540] = { - .class_hid = BNXT_ULP_CLASS_HID_71c43, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [541] = { - .class_hid = BNXT_ULP_CLASS_HID_750d7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [542] = { - .class_hid = BNXT_ULP_CLASS_HID_700a3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [543] = { - .class_hid = BNXT_ULP_CLASS_HID_75713, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [544] = { - .class_hid = BNXT_ULP_CLASS_HID_706ff, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [545] = { - .class_hid = BNXT_ULP_CLASS_HID_2cfc3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [546] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc5b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [547] = { - .class_hid = BNXT_ULP_CLASS_HID_2d61f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [548] = { - .class_hid = BNXT_ULP_CLASS_HID_285eb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [549] = { - .class_hid = BNXT_ULP_CLASS_HID_2ba7f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [550] = { - .class_hid = BNXT_ULP_CLASS_HID_2c6f7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [551] = { - .class_hid = BNXT_ULP_CLASS_HID_2c0bb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [552] = { - .class_hid = BNXT_ULP_CLASS_HID_2cd33, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [553] = { - .class_hid = BNXT_ULP_CLASS_HID_2968b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [554] = { - .class_hid = BNXT_ULP_CLASS_HID_2a303, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [555] = { - .class_hid = BNXT_ULP_CLASS_HID_29cc7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [556] = { - .class_hid = BNXT_ULP_CLASS_HID_2a95f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [557] = { - .class_hid = BNXT_ULP_CLASS_HID_28127, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [558] = { - .class_hid = BNXT_ULP_CLASS_HID_28dbf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [559] = { - .class_hid = BNXT_ULP_CLASS_HID_28763, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [560] = { - .class_hid = BNXT_ULP_CLASS_HID_293fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [561] = { - .class_hid = BNXT_ULP_CLASS_HID_2bcf3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [562] = { - .class_hid = BNXT_ULP_CLASS_HID_2c90b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [563] = { - .class_hid = BNXT_ULP_CLASS_HID_2c2cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [564] = { - .class_hid = BNXT_ULP_CLASS_HID_2cf47, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [565] = { - .class_hid = BNXT_ULP_CLASS_HID_2a72f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [566] = { - .class_hid = BNXT_ULP_CLASS_HID_2b3a7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [567] = { - .class_hid = BNXT_ULP_CLASS_HID_2ad6b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [568] = { - .class_hid = BNXT_ULP_CLASS_HID_2b9e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [569] = { - .class_hid = BNXT_ULP_CLASS_HID_283bb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [570] = { - .class_hid = BNXT_ULP_CLASS_HID_29033, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [571] = { - .class_hid = BNXT_ULP_CLASS_HID_289f7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [572] = { - .class_hid = BNXT_ULP_CLASS_HID_2960f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [573] = { - .class_hid = BNXT_ULP_CLASS_HID_2ca83, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [574] = { - .class_hid = BNXT_ULP_CLASS_HID_2d71b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [575] = { - .class_hid = BNXT_ULP_CLASS_HID_2d0df, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [576] = { - .class_hid = BNXT_ULP_CLASS_HID_280ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [577] = { - .class_hid = BNXT_ULP_CLASS_HID_6cb17, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [578] = { - .class_hid = BNXT_ULP_CLASS_HID_6d7af, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [579] = { - .class_hid = BNXT_ULP_CLASS_HID_6d153, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [580] = { - .class_hid = BNXT_ULP_CLASS_HID_6813f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [581] = { - .class_hid = BNXT_ULP_CLASS_HID_6b5b3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [582] = { - .class_hid = BNXT_ULP_CLASS_HID_6c1cb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [583] = { - .class_hid = BNXT_ULP_CLASS_HID_6bb8f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [584] = { - .class_hid = BNXT_ULP_CLASS_HID_6c807, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [585] = { - .class_hid = BNXT_ULP_CLASS_HID_691df, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [586] = { - .class_hid = BNXT_ULP_CLASS_HID_69e57, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [587] = { - .class_hid = BNXT_ULP_CLASS_HID_6981b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [588] = { - .class_hid = BNXT_ULP_CLASS_HID_6a493, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [589] = { - .class_hid = BNXT_ULP_CLASS_HID_6d927, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [590] = { - .class_hid = BNXT_ULP_CLASS_HID_688f3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [591] = { - .class_hid = BNXT_ULP_CLASS_HID_682b7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [592] = { - .class_hid = BNXT_ULP_CLASS_HID_68ecf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [593] = { - .class_hid = BNXT_ULP_CLASS_HID_6b7c7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [594] = { - .class_hid = BNXT_ULP_CLASS_HID_6c45f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [595] = { - .class_hid = BNXT_ULP_CLASS_HID_6be03, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [596] = { - .class_hid = BNXT_ULP_CLASS_HID_6ca9b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [597] = { - .class_hid = BNXT_ULP_CLASS_HID_6a263, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [598] = { - .class_hid = BNXT_ULP_CLASS_HID_6aefb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [599] = { - .class_hid = BNXT_ULP_CLASS_HID_6a8bf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [600] = { - .class_hid = BNXT_ULP_CLASS_HID_6b537, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [601] = { - .class_hid = BNXT_ULP_CLASS_HID_6dbbb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [602] = { - .class_hid = BNXT_ULP_CLASS_HID_68b07, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [603] = { - .class_hid = BNXT_ULP_CLASS_HID_684cb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [604] = { - .class_hid = BNXT_ULP_CLASS_HID_69143, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [605] = { - .class_hid = BNXT_ULP_CLASS_HID_6c5d7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [606] = { - .class_hid = BNXT_ULP_CLASS_HID_6d26f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [607] = { - .class_hid = BNXT_ULP_CLASS_HID_6cc13, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [608] = { - .class_hid = BNXT_ULP_CLASS_HID_6d8ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [609] = { - .class_hid = BNXT_ULP_CLASS_HID_38917, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [610] = { - .class_hid = BNXT_ULP_CLASS_HID_395af, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [611] = { - .class_hid = BNXT_ULP_CLASS_HID_38f53, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [612] = { - .class_hid = BNXT_ULP_CLASS_HID_39beb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [613] = { - .class_hid = BNXT_ULP_CLASS_HID_3d07f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [614] = { - .class_hid = BNXT_ULP_CLASS_HID_3dcf7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [615] = { - .class_hid = BNXT_ULP_CLASS_HID_3d6bb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [616] = { - .class_hid = BNXT_ULP_CLASS_HID_38607, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [617] = { - .class_hid = BNXT_ULP_CLASS_HID_3ac8b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [618] = { - .class_hid = BNXT_ULP_CLASS_HID_3b903, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [619] = { - .class_hid = BNXT_ULP_CLASS_HID_3b2c7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [620] = { - .class_hid = BNXT_ULP_CLASS_HID_3bf5f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [621] = { - .class_hid = BNXT_ULP_CLASS_HID_39727, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [622] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3bf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [623] = { - .class_hid = BNXT_ULP_CLASS_HID_39d63, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [624] = { - .class_hid = BNXT_ULP_CLASS_HID_3a9fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [625] = { - .class_hid = BNXT_ULP_CLASS_HID_3d2f3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [626] = { - .class_hid = BNXT_ULP_CLASS_HID_3825f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [627] = { - .class_hid = BNXT_ULP_CLASS_HID_3d8cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [628] = { - .class_hid = BNXT_ULP_CLASS_HID_3889b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [629] = { - .class_hid = BNXT_ULP_CLASS_HID_3bd2f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [630] = { - .class_hid = BNXT_ULP_CLASS_HID_3c9a7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [631] = { - .class_hid = BNXT_ULP_CLASS_HID_3c36b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [632] = { - .class_hid = BNXT_ULP_CLASS_HID_3cfe3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [633] = { - .class_hid = BNXT_ULP_CLASS_HID_399bb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [634] = { - .class_hid = BNXT_ULP_CLASS_HID_3a633, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [635] = { - .class_hid = BNXT_ULP_CLASS_HID_39ff7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [636] = { - .class_hid = BNXT_ULP_CLASS_HID_3ac0f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [637] = { - .class_hid = BNXT_ULP_CLASS_HID_383d7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [638] = { - .class_hid = BNXT_ULP_CLASS_HID_3906f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [639] = { - .class_hid = BNXT_ULP_CLASS_HID_38a13, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [640] = { - .class_hid = BNXT_ULP_CLASS_HID_396ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [641] = { - .class_hid = BNXT_ULP_CLASS_HID_7846b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [642] = { - .class_hid = BNXT_ULP_CLASS_HID_790e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [643] = { - .class_hid = BNXT_ULP_CLASS_HID_78aa7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [644] = { - .class_hid = BNXT_ULP_CLASS_HID_7973f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [645] = { - .class_hid = BNXT_ULP_CLASS_HID_7cbb3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [646] = { - .class_hid = BNXT_ULP_CLASS_HID_7d7cb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [647] = { - .class_hid = BNXT_ULP_CLASS_HID_7d18f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [648] = { - .class_hid = BNXT_ULP_CLASS_HID_7815b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [649] = { - .class_hid = BNXT_ULP_CLASS_HID_7a7df, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [650] = { - .class_hid = BNXT_ULP_CLASS_HID_7b457, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [651] = { - .class_hid = BNXT_ULP_CLASS_HID_7ae1b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [652] = { - .class_hid = BNXT_ULP_CLASS_HID_7ba93, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [653] = { - .class_hid = BNXT_ULP_CLASS_HID_7927b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [654] = { - .class_hid = BNXT_ULP_CLASS_HID_79ef3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [655] = { - .class_hid = BNXT_ULP_CLASS_HID_798b7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [656] = { - .class_hid = BNXT_ULP_CLASS_HID_7a4cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [657] = { - .class_hid = BNXT_ULP_CLASS_HID_7cdc7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [658] = { - .class_hid = BNXT_ULP_CLASS_HID_7da5f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [659] = { - .class_hid = BNXT_ULP_CLASS_HID_7d403, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [660] = { - .class_hid = BNXT_ULP_CLASS_HID_783ef, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [661] = { - .class_hid = BNXT_ULP_CLASS_HID_7b863, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [662] = { - .class_hid = BNXT_ULP_CLASS_HID_7c4fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [663] = { - .class_hid = BNXT_ULP_CLASS_HID_7bebf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [664] = { - .class_hid = BNXT_ULP_CLASS_HID_7cb37, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [665] = { - .class_hid = BNXT_ULP_CLASS_HID_7948f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [666] = { - .class_hid = BNXT_ULP_CLASS_HID_7a107, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [667] = { - .class_hid = BNXT_ULP_CLASS_HID_79acb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [668] = { - .class_hid = BNXT_ULP_CLASS_HID_7a743, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [669] = { - .class_hid = BNXT_ULP_CLASS_HID_7dbd7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [670] = { - .class_hid = BNXT_ULP_CLASS_HID_78ba3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [671] = { - .class_hid = BNXT_ULP_CLASS_HID_78567, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [672] = { - .class_hid = BNXT_ULP_CLASS_HID_791ff, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [673] = { - .class_hid = BNXT_ULP_CLASS_HID_a3db, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [674] = { - .class_hid = BNXT_ULP_CLASS_HID_b043, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [675] = { - .class_hid = BNXT_ULP_CLASS_HID_aa07, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [676] = { - .class_hid = BNXT_ULP_CLASS_HID_b68f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [677] = { - .class_hid = BNXT_ULP_CLASS_HID_8e67, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [678] = { - .class_hid = BNXT_ULP_CLASS_HID_9aef, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [679] = { - .class_hid = BNXT_ULP_CLASS_HID_94a3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [680] = { - .class_hid = BNXT_ULP_CLASS_HID_a12b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [681] = { - .class_hid = BNXT_ULP_CLASS_HID_c7af, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [682] = { - .class_hid = BNXT_ULP_CLASS_HID_d3d7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [683] = { - .class_hid = BNXT_ULP_CLASS_HID_cdeb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [684] = { - .class_hid = BNXT_ULP_CLASS_HID_da13, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [685] = { - .class_hid = BNXT_ULP_CLASS_HID_b1cb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [686] = { - .class_hid = BNXT_ULP_CLASS_HID_be73, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [687] = { - .class_hid = BNXT_ULP_CLASS_HID_b837, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [688] = { - .class_hid = BNXT_ULP_CLASS_HID_c4bf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [689] = { - .class_hid = BNXT_ULP_CLASS_HID_49f0f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [690] = { - .class_hid = BNXT_ULP_CLASS_HID_4abb7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [691] = { - .class_hid = BNXT_ULP_CLASS_HID_4a54b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [692] = { - .class_hid = BNXT_ULP_CLASS_HID_4b1f3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [693] = { - .class_hid = BNXT_ULP_CLASS_HID_489ab, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [694] = { - .class_hid = BNXT_ULP_CLASS_HID_495d3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [695] = { - .class_hid = BNXT_ULP_CLASS_HID_48f97, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [696] = { - .class_hid = BNXT_ULP_CLASS_HID_49c1f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [697] = { - .class_hid = BNXT_ULP_CLASS_HID_4c293, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [698] = { - .class_hid = BNXT_ULP_CLASS_HID_4cf1b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [699] = { - .class_hid = BNXT_ULP_CLASS_HID_4c8df, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [700] = { - .class_hid = BNXT_ULP_CLASS_HID_4d547, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [701] = { - .class_hid = BNXT_ULP_CLASS_HID_4ad3f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [702] = { - .class_hid = BNXT_ULP_CLASS_HID_4b9a7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [703] = { - .class_hid = BNXT_ULP_CLASS_HID_4b37b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [704] = { - .class_hid = BNXT_ULP_CLASS_HID_4bfe3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [705] = { - .class_hid = BNXT_ULP_CLASS_HID_1b9db, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [706] = { - .class_hid = BNXT_ULP_CLASS_HID_1c643, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [707] = { - .class_hid = BNXT_ULP_CLASS_HID_1c007, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [708] = { - .class_hid = BNXT_ULP_CLASS_HID_1cc8f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [709] = { - .class_hid = BNXT_ULP_CLASS_HID_1a467, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [710] = { - .class_hid = BNXT_ULP_CLASS_HID_1b0ef, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [711] = { - .class_hid = BNXT_ULP_CLASS_HID_1aaa3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [712] = { - .class_hid = BNXT_ULP_CLASS_HID_1b72b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [713] = { - .class_hid = BNXT_ULP_CLASS_HID_18093, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [714] = { - .class_hid = BNXT_ULP_CLASS_HID_18d1b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [715] = { - .class_hid = BNXT_ULP_CLASS_HID_186df, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [716] = { - .class_hid = BNXT_ULP_CLASS_HID_19347, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [717] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7cb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [718] = { - .class_hid = BNXT_ULP_CLASS_HID_1d473, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [719] = { - .class_hid = BNXT_ULP_CLASS_HID_1ce37, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [720] = { - .class_hid = BNXT_ULP_CLASS_HID_1dabf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [721] = { - .class_hid = BNXT_ULP_CLASS_HID_5b50f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [722] = { - .class_hid = BNXT_ULP_CLASS_HID_5c1b7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [723] = { - .class_hid = BNXT_ULP_CLASS_HID_5bb4b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [724] = { - .class_hid = BNXT_ULP_CLASS_HID_5c7f3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [725] = { - .class_hid = BNXT_ULP_CLASS_HID_59fab, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [726] = { - .class_hid = BNXT_ULP_CLASS_HID_5abd3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [727] = { - .class_hid = BNXT_ULP_CLASS_HID_5a597, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [728] = { - .class_hid = BNXT_ULP_CLASS_HID_5b21f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [729] = { - .class_hid = BNXT_ULP_CLASS_HID_5d893, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [730] = { - .class_hid = BNXT_ULP_CLASS_HID_5884f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [731] = { - .class_hid = BNXT_ULP_CLASS_HID_58203, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [732] = { - .class_hid = BNXT_ULP_CLASS_HID_58e8b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [733] = { - .class_hid = BNXT_ULP_CLASS_HID_5c33f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [734] = { - .class_hid = BNXT_ULP_CLASS_HID_5cfa7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [735] = { - .class_hid = BNXT_ULP_CLASS_HID_5c97b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [736] = { - .class_hid = BNXT_ULP_CLASS_HID_5d5e3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [737] = { - .class_hid = BNXT_ULP_CLASS_HID_e95b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [738] = { - .class_hid = BNXT_ULP_CLASS_HID_f5c3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [739] = { - .class_hid = BNXT_ULP_CLASS_HID_ef87, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [740] = { - .class_hid = BNXT_ULP_CLASS_HID_fc0f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [741] = { - .class_hid = BNXT_ULP_CLASS_HID_d3e7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [742] = { - .class_hid = BNXT_ULP_CLASS_HID_e06f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [743] = { - .class_hid = BNXT_ULP_CLASS_HID_da23, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [744] = { - .class_hid = BNXT_ULP_CLASS_HID_e6ab, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [745] = { - .class_hid = BNXT_ULP_CLASS_HID_cd2f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [746] = { - .class_hid = BNXT_ULP_CLASS_HID_d957, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [747] = { - .class_hid = BNXT_ULP_CLASS_HID_d36b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [748] = { - .class_hid = BNXT_ULP_CLASS_HID_c2c7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [749] = { - .class_hid = BNXT_ULP_CLASS_HID_f74b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [750] = { - .class_hid = BNXT_ULP_CLASS_HID_c3f3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [751] = { - .class_hid = BNXT_ULP_CLASS_HID_fdb7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [752] = { - .class_hid = BNXT_ULP_CLASS_HID_ca3f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [753] = { - .class_hid = BNXT_ULP_CLASS_HID_4e48f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [754] = { - .class_hid = BNXT_ULP_CLASS_HID_4f137, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [755] = { - .class_hid = BNXT_ULP_CLASS_HID_4eacb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [756] = { - .class_hid = BNXT_ULP_CLASS_HID_4f773, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [757] = { - .class_hid = BNXT_ULP_CLASS_HID_4cf2b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [758] = { - .class_hid = BNXT_ULP_CLASS_HID_4db53, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [759] = { - .class_hid = BNXT_ULP_CLASS_HID_4d517, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [760] = { - .class_hid = BNXT_ULP_CLASS_HID_4e19f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [761] = { - .class_hid = BNXT_ULP_CLASS_HID_4c813, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [762] = { - .class_hid = BNXT_ULP_CLASS_HID_4d49b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [763] = { - .class_hid = BNXT_ULP_CLASS_HID_4ce5f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [764] = { - .class_hid = BNXT_ULP_CLASS_HID_4dac7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [765] = { - .class_hid = BNXT_ULP_CLASS_HID_4f2bf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [766] = { - .class_hid = BNXT_ULP_CLASS_HID_4ff27, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [767] = { - .class_hid = BNXT_ULP_CLASS_HID_4f8fb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [768] = { - .class_hid = BNXT_ULP_CLASS_HID_4c563, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [769] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff5b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [770] = { - .class_hid = BNXT_ULP_CLASS_HID_1cbc3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [771] = { - .class_hid = BNXT_ULP_CLASS_HID_1c587, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [772] = { - .class_hid = BNXT_ULP_CLASS_HID_1d20f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [773] = { - .class_hid = BNXT_ULP_CLASS_HID_1e9e7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [774] = { - .class_hid = BNXT_ULP_CLASS_HID_1f66f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [775] = { - .class_hid = BNXT_ULP_CLASS_HID_1f023, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [776] = { - .class_hid = BNXT_ULP_CLASS_HID_1fcab, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [777] = { - .class_hid = BNXT_ULP_CLASS_HID_1c613, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [778] = { - .class_hid = BNXT_ULP_CLASS_HID_1d29b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [779] = { - .class_hid = BNXT_ULP_CLASS_HID_1cc5f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [780] = { - .class_hid = BNXT_ULP_CLASS_HID_1d8c7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [781] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd4b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [782] = { - .class_hid = BNXT_ULP_CLASS_HID_1d9f3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [783] = { - .class_hid = BNXT_ULP_CLASS_HID_1d3b7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [784] = { - .class_hid = BNXT_ULP_CLASS_HID_1c363, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [785] = { - .class_hid = BNXT_ULP_CLASS_HID_5fa8f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [786] = { - .class_hid = BNXT_ULP_CLASS_HID_5c737, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [787] = { - .class_hid = BNXT_ULP_CLASS_HID_5c0cb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [788] = { - .class_hid = BNXT_ULP_CLASS_HID_5cd73, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [789] = { - .class_hid = BNXT_ULP_CLASS_HID_5e52b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [790] = { - .class_hid = BNXT_ULP_CLASS_HID_5f153, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [791] = { - .class_hid = BNXT_ULP_CLASS_HID_5eb17, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [792] = { - .class_hid = BNXT_ULP_CLASS_HID_5f79f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [793] = { - .class_hid = BNXT_ULP_CLASS_HID_5c147, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [794] = { - .class_hid = BNXT_ULP_CLASS_HID_5cdcf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [795] = { - .class_hid = BNXT_ULP_CLASS_HID_5c783, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [796] = { - .class_hid = BNXT_ULP_CLASS_HID_5d40b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [797] = { - .class_hid = BNXT_ULP_CLASS_HID_5c8bf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [798] = { - .class_hid = BNXT_ULP_CLASS_HID_5d527, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [799] = { - .class_hid = BNXT_ULP_CLASS_HID_5cefb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [800] = { - .class_hid = BNXT_ULP_CLASS_HID_5db63, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [801] = { - .class_hid = BNXT_ULP_CLASS_HID_a69b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [802] = { - .class_hid = BNXT_ULP_CLASS_HID_b303, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [803] = { - .class_hid = BNXT_ULP_CLASS_HID_acc7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [804] = { - .class_hid = BNXT_ULP_CLASS_HID_b94f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [805] = { - .class_hid = BNXT_ULP_CLASS_HID_b127, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [806] = { - .class_hid = BNXT_ULP_CLASS_HID_bdaf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [807] = { - .class_hid = BNXT_ULP_CLASS_HID_b763, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [808] = { - .class_hid = BNXT_ULP_CLASS_HID_a3eb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [809] = { - .class_hid = BNXT_ULP_CLASS_HID_ea6f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [810] = { - .class_hid = BNXT_ULP_CLASS_HID_f697, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [811] = { - .class_hid = BNXT_ULP_CLASS_HID_f0ab, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [812] = { - .class_hid = BNXT_ULP_CLASS_HID_a007, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [813] = { - .class_hid = BNXT_ULP_CLASS_HID_b48b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [814] = { - .class_hid = BNXT_ULP_CLASS_HID_e133, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [815] = { - .class_hid = BNXT_ULP_CLASS_HID_baf7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [816] = { - .class_hid = BNXT_ULP_CLASS_HID_e77f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [817] = { - .class_hid = BNXT_ULP_CLASS_HID_4a1cf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [818] = { - .class_hid = BNXT_ULP_CLASS_HID_4ae77, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [819] = { - .class_hid = BNXT_ULP_CLASS_HID_4a80b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [820] = { - .class_hid = BNXT_ULP_CLASS_HID_4b4b3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [821] = { - .class_hid = BNXT_ULP_CLASS_HID_4ac6b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [822] = { - .class_hid = BNXT_ULP_CLASS_HID_4b893, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [823] = { - .class_hid = BNXT_ULP_CLASS_HID_4b257, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [824] = { - .class_hid = BNXT_ULP_CLASS_HID_4bedf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [825] = { - .class_hid = BNXT_ULP_CLASS_HID_4e553, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [826] = { - .class_hid = BNXT_ULP_CLASS_HID_4f1db, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [827] = { - .class_hid = BNXT_ULP_CLASS_HID_4eb9f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [828] = { - .class_hid = BNXT_ULP_CLASS_HID_4f807, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [829] = { - .class_hid = BNXT_ULP_CLASS_HID_4afff, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [830] = { - .class_hid = BNXT_ULP_CLASS_HID_4bc67, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [831] = { - .class_hid = BNXT_ULP_CLASS_HID_4b63b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [832] = { - .class_hid = BNXT_ULP_CLASS_HID_4e2a3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [833] = { - .class_hid = BNXT_ULP_CLASS_HID_1bc9b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [834] = { - .class_hid = BNXT_ULP_CLASS_HID_1e903, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [835] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2c7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [836] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef4f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [837] = { - .class_hid = BNXT_ULP_CLASS_HID_1a727, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [838] = { - .class_hid = BNXT_ULP_CLASS_HID_1b3af, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [839] = { - .class_hid = BNXT_ULP_CLASS_HID_1ad63, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [840] = { - .class_hid = BNXT_ULP_CLASS_HID_1b9eb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [841] = { - .class_hid = BNXT_ULP_CLASS_HID_1a353, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [842] = { - .class_hid = BNXT_ULP_CLASS_HID_1afdb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [843] = { - .class_hid = BNXT_ULP_CLASS_HID_1a99f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [844] = { - .class_hid = BNXT_ULP_CLASS_HID_1b607, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [845] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea8b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [846] = { - .class_hid = BNXT_ULP_CLASS_HID_1f733, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [847] = { - .class_hid = BNXT_ULP_CLASS_HID_1f0f7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [848] = { - .class_hid = BNXT_ULP_CLASS_HID_1a0a3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [849] = { - .class_hid = BNXT_ULP_CLASS_HID_5b7cf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [850] = { - .class_hid = BNXT_ULP_CLASS_HID_5e477, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [851] = { - .class_hid = BNXT_ULP_CLASS_HID_5be0b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [852] = { - .class_hid = BNXT_ULP_CLASS_HID_5eab3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [853] = { - .class_hid = BNXT_ULP_CLASS_HID_5a26b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [854] = { - .class_hid = BNXT_ULP_CLASS_HID_5ae93, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [855] = { - .class_hid = BNXT_ULP_CLASS_HID_5a857, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [856] = { - .class_hid = BNXT_ULP_CLASS_HID_5b4df, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [857] = { - .class_hid = BNXT_ULP_CLASS_HID_5fb53, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [858] = { - .class_hid = BNXT_ULP_CLASS_HID_5ab0f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [859] = { - .class_hid = BNXT_ULP_CLASS_HID_5a4c3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [860] = { - .class_hid = BNXT_ULP_CLASS_HID_5b14b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [861] = { - .class_hid = BNXT_ULP_CLASS_HID_5e5ff, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [862] = { - .class_hid = BNXT_ULP_CLASS_HID_5f267, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [863] = { - .class_hid = BNXT_ULP_CLASS_HID_5ec3b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [864] = { - .class_hid = BNXT_ULP_CLASS_HID_5f8a3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [865] = { - .class_hid = BNXT_ULP_CLASS_HID_ec1b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [866] = { - .class_hid = BNXT_ULP_CLASS_HID_f883, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [867] = { - .class_hid = BNXT_ULP_CLASS_HID_f247, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [868] = { - .class_hid = BNXT_ULP_CLASS_HID_fecf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [869] = { - .class_hid = BNXT_ULP_CLASS_HID_f6a7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [870] = { - .class_hid = BNXT_ULP_CLASS_HID_e32f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [871] = { - .class_hid = BNXT_ULP_CLASS_HID_fce3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [872] = { - .class_hid = BNXT_ULP_CLASS_HID_e96b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [873] = { - .class_hid = BNXT_ULP_CLASS_HID_efef, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [874] = { - .class_hid = BNXT_ULP_CLASS_HID_fc17, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [875] = { - .class_hid = BNXT_ULP_CLASS_HID_f62b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [876] = { - .class_hid = BNXT_ULP_CLASS_HID_e587, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [877] = { - .class_hid = BNXT_ULP_CLASS_HID_fa0b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [878] = { - .class_hid = BNXT_ULP_CLASS_HID_e6b3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [879] = { - .class_hid = BNXT_ULP_CLASS_HID_e077, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [880] = { - .class_hid = BNXT_ULP_CLASS_HID_ecff, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [881] = { - .class_hid = BNXT_ULP_CLASS_HID_4e74f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [882] = { - .class_hid = BNXT_ULP_CLASS_HID_4f3f7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [883] = { - .class_hid = BNXT_ULP_CLASS_HID_4ed8b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [884] = { - .class_hid = BNXT_ULP_CLASS_HID_4fa33, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [885] = { - .class_hid = BNXT_ULP_CLASS_HID_4f1eb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [886] = { - .class_hid = BNXT_ULP_CLASS_HID_4fe13, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [887] = { - .class_hid = BNXT_ULP_CLASS_HID_4f7d7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [888] = { - .class_hid = BNXT_ULP_CLASS_HID_4e45f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [889] = { - .class_hid = BNXT_ULP_CLASS_HID_4ead3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [890] = { - .class_hid = BNXT_ULP_CLASS_HID_4f75b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [891] = { - .class_hid = BNXT_ULP_CLASS_HID_4f11f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [892] = { - .class_hid = BNXT_ULP_CLASS_HID_4e0cb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [893] = { - .class_hid = BNXT_ULP_CLASS_HID_4f57f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [894] = { - .class_hid = BNXT_ULP_CLASS_HID_4e1e7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [895] = { - .class_hid = BNXT_ULP_CLASS_HID_4fbbb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [896] = { - .class_hid = BNXT_ULP_CLASS_HID_4e823, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [897] = { - .class_hid = BNXT_ULP_CLASS_HID_1e21b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [898] = { - .class_hid = BNXT_ULP_CLASS_HID_1ee83, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [899] = { - .class_hid = BNXT_ULP_CLASS_HID_1e847, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [900] = { - .class_hid = BNXT_ULP_CLASS_HID_1f4cf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [901] = { - .class_hid = BNXT_ULP_CLASS_HID_1eca7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [902] = { - .class_hid = BNXT_ULP_CLASS_HID_1f92f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [903] = { - .class_hid = BNXT_ULP_CLASS_HID_1f2e3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [904] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff6b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [905] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8d3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [906] = { - .class_hid = BNXT_ULP_CLASS_HID_1f55b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [907] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef1f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [908] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb87, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [909] = { - .class_hid = BNXT_ULP_CLASS_HID_1f00b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [910] = { - .class_hid = BNXT_ULP_CLASS_HID_1fcb3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [911] = { - .class_hid = BNXT_ULP_CLASS_HID_1f677, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [912] = { - .class_hid = BNXT_ULP_CLASS_HID_1e623, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [913] = { - .class_hid = BNXT_ULP_CLASS_HID_5fd4f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [914] = { - .class_hid = BNXT_ULP_CLASS_HID_5e9f7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [915] = { - .class_hid = BNXT_ULP_CLASS_HID_5e38b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [916] = { - .class_hid = BNXT_ULP_CLASS_HID_5f033, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [917] = { - .class_hid = BNXT_ULP_CLASS_HID_5e7eb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [918] = { - .class_hid = BNXT_ULP_CLASS_HID_5f413, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [919] = { - .class_hid = BNXT_ULP_CLASS_HID_5edd7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [920] = { - .class_hid = BNXT_ULP_CLASS_HID_5fa5f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [921] = { - .class_hid = BNXT_ULP_CLASS_HID_5e407, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [922] = { - .class_hid = BNXT_ULP_CLASS_HID_5f08f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [923] = { - .class_hid = BNXT_ULP_CLASS_HID_5ea43, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [924] = { - .class_hid = BNXT_ULP_CLASS_HID_5f6cb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [925] = { - .class_hid = BNXT_ULP_CLASS_HID_5eb7f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [926] = { - .class_hid = BNXT_ULP_CLASS_HID_5f7e7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [927] = { - .class_hid = BNXT_ULP_CLASS_HID_5f1bb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [928] = { - .class_hid = BNXT_ULP_CLASS_HID_5e117, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [929] = { - .class_hid = BNXT_ULP_CLASS_HID_244a3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [930] = { - .class_hid = BNXT_ULP_CLASS_HID_2513b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [931] = { - .class_hid = BNXT_ULP_CLASS_HID_24b7f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [932] = { - .class_hid = BNXT_ULP_CLASS_HID_257f7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [933] = { - .class_hid = BNXT_ULP_CLASS_HID_22f1f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [934] = { - .class_hid = BNXT_ULP_CLASS_HID_23b97, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [935] = { - .class_hid = BNXT_ULP_CLASS_HID_235db, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [936] = { - .class_hid = BNXT_ULP_CLASS_HID_24253, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [937] = { - .class_hid = BNXT_ULP_CLASS_HID_20beb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [938] = { - .class_hid = BNXT_ULP_CLASS_HID_21863, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [939] = { - .class_hid = BNXT_ULP_CLASS_HID_211a7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [940] = { - .class_hid = BNXT_ULP_CLASS_HID_21e3f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [941] = { - .class_hid = BNXT_ULP_CLASS_HID_252b3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [942] = { - .class_hid = BNXT_ULP_CLASS_HID_202df, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [943] = { - .class_hid = BNXT_ULP_CLASS_HID_2594f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [944] = { - .class_hid = BNXT_ULP_CLASS_HID_2089b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [945] = { - .class_hid = BNXT_ULP_CLASS_HID_23193, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [946] = { - .class_hid = BNXT_ULP_CLASS_HID_23e6b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [947] = { - .class_hid = BNXT_ULP_CLASS_HID_237af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [948] = { - .class_hid = BNXT_ULP_CLASS_HID_24427, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [949] = { - .class_hid = BNXT_ULP_CLASS_HID_21c4f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [950] = { - .class_hid = BNXT_ULP_CLASS_HID_228c7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [951] = { - .class_hid = BNXT_ULP_CLASS_HID_2220b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [952] = { - .class_hid = BNXT_ULP_CLASS_HID_22e83, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [953] = { - .class_hid = BNXT_ULP_CLASS_HID_25507, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [954] = { - .class_hid = BNXT_ULP_CLASS_HID_20553, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [955] = { - .class_hid = BNXT_ULP_CLASS_HID_25bc3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [956] = { - .class_hid = BNXT_ULP_CLASS_HID_20b6f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [957] = { - .class_hid = BNXT_ULP_CLASS_HID_23fe3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [958] = { - .class_hid = BNXT_ULP_CLASS_HID_24c7b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [959] = { - .class_hid = BNXT_ULP_CLASS_HID_245bf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [960] = { - .class_hid = BNXT_ULP_CLASS_HID_25237, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [961] = { - .class_hid = BNXT_ULP_CLASS_HID_64077, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [962] = { - .class_hid = BNXT_ULP_CLASS_HID_64ccf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [963] = { - .class_hid = BNXT_ULP_CLASS_HID_64633, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [964] = { - .class_hid = BNXT_ULP_CLASS_HID_6528b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [965] = { - .class_hid = BNXT_ULP_CLASS_HID_62ad3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [966] = { - .class_hid = BNXT_ULP_CLASS_HID_636ab, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [967] = { - .class_hid = BNXT_ULP_CLASS_HID_630ef, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [968] = { - .class_hid = BNXT_ULP_CLASS_HID_63d67, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [969] = { - .class_hid = BNXT_ULP_CLASS_HID_606bf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [970] = { - .class_hid = BNXT_ULP_CLASS_HID_61337, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [971] = { - .class_hid = BNXT_ULP_CLASS_HID_60d7b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [972] = { - .class_hid = BNXT_ULP_CLASS_HID_619f3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [973] = { - .class_hid = BNXT_ULP_CLASS_HID_64e47, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [974] = { - .class_hid = BNXT_ULP_CLASS_HID_65adf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [975] = { - .class_hid = BNXT_ULP_CLASS_HID_65403, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [976] = { - .class_hid = BNXT_ULP_CLASS_HID_603af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [977] = { - .class_hid = BNXT_ULP_CLASS_HID_62ca7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [978] = { - .class_hid = BNXT_ULP_CLASS_HID_6393f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [979] = { - .class_hid = BNXT_ULP_CLASS_HID_63363, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [980] = { - .class_hid = BNXT_ULP_CLASS_HID_63ffb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [981] = { - .class_hid = BNXT_ULP_CLASS_HID_61703, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [982] = { - .class_hid = BNXT_ULP_CLASS_HID_6239b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [983] = { - .class_hid = BNXT_ULP_CLASS_HID_61ddf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [984] = { - .class_hid = BNXT_ULP_CLASS_HID_62a57, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [985] = { - .class_hid = BNXT_ULP_CLASS_HID_650db, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [986] = { - .class_hid = BNXT_ULP_CLASS_HID_60067, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [987] = { - .class_hid = BNXT_ULP_CLASS_HID_65697, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [988] = { - .class_hid = BNXT_ULP_CLASS_HID_60623, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [989] = { - .class_hid = BNXT_ULP_CLASS_HID_63ab7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [990] = { - .class_hid = BNXT_ULP_CLASS_HID_6470f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [991] = { - .class_hid = BNXT_ULP_CLASS_HID_64173, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [992] = { - .class_hid = BNXT_ULP_CLASS_HID_64dcb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [993] = { - .class_hid = BNXT_ULP_CLASS_HID_35aa3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [994] = { - .class_hid = BNXT_ULP_CLASS_HID_30acf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [995] = { - .class_hid = BNXT_ULP_CLASS_HID_30433, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [996] = { - .class_hid = BNXT_ULP_CLASS_HID_3108b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [997] = { - .class_hid = BNXT_ULP_CLASS_HID_3451f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [998] = { - .class_hid = BNXT_ULP_CLASS_HID_35197, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [999] = { - .class_hid = BNXT_ULP_CLASS_HID_34bdb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1000] = { - .class_hid = BNXT_ULP_CLASS_HID_35853, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1001] = { - .class_hid = BNXT_ULP_CLASS_HID_321eb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1002] = { - .class_hid = BNXT_ULP_CLASS_HID_32e63, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1003] = { - .class_hid = BNXT_ULP_CLASS_HID_327a7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1004] = { - .class_hid = BNXT_ULP_CLASS_HID_3343f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1005] = { - .class_hid = BNXT_ULP_CLASS_HID_30c47, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1006] = { - .class_hid = BNXT_ULP_CLASS_HID_318df, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1007] = { - .class_hid = BNXT_ULP_CLASS_HID_31203, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1008] = { - .class_hid = BNXT_ULP_CLASS_HID_31e9b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1009] = { - .class_hid = BNXT_ULP_CLASS_HID_34793, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1010] = { - .class_hid = BNXT_ULP_CLASS_HID_3546b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1011] = { - .class_hid = BNXT_ULP_CLASS_HID_34daf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1012] = { - .class_hid = BNXT_ULP_CLASS_HID_35a27, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1013] = { - .class_hid = BNXT_ULP_CLASS_HID_3324f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1014] = { - .class_hid = BNXT_ULP_CLASS_HID_33ec7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1015] = { - .class_hid = BNXT_ULP_CLASS_HID_3380b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1016] = { - .class_hid = BNXT_ULP_CLASS_HID_34483, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1017] = { - .class_hid = BNXT_ULP_CLASS_HID_30edb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1018] = { - .class_hid = BNXT_ULP_CLASS_HID_31b53, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1019] = { - .class_hid = BNXT_ULP_CLASS_HID_31497, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1020] = { - .class_hid = BNXT_ULP_CLASS_HID_3216f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1021] = { - .class_hid = BNXT_ULP_CLASS_HID_355e3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1022] = { - .class_hid = BNXT_ULP_CLASS_HID_3050f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1023] = { - .class_hid = BNXT_ULP_CLASS_HID_35bbf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1024] = { - .class_hid = BNXT_ULP_CLASS_HID_30bcb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1025] = { - .class_hid = BNXT_ULP_CLASS_HID_75677, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1026] = { - .class_hid = BNXT_ULP_CLASS_HID_70583, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1027] = { - .class_hid = BNXT_ULP_CLASS_HID_75c33, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1028] = { - .class_hid = BNXT_ULP_CLASS_HID_70c5f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1029] = { - .class_hid = BNXT_ULP_CLASS_HID_740d3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1030] = { - .class_hid = BNXT_ULP_CLASS_HID_74cab, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1031] = { - .class_hid = BNXT_ULP_CLASS_HID_746ef, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1032] = { - .class_hid = BNXT_ULP_CLASS_HID_75367, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1033] = { - .class_hid = BNXT_ULP_CLASS_HID_71cbf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1034] = { - .class_hid = BNXT_ULP_CLASS_HID_72937, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1035] = { - .class_hid = BNXT_ULP_CLASS_HID_7237b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1036] = { - .class_hid = BNXT_ULP_CLASS_HID_72ff3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1037] = { - .class_hid = BNXT_ULP_CLASS_HID_7071b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1038] = { - .class_hid = BNXT_ULP_CLASS_HID_71393, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1039] = { - .class_hid = BNXT_ULP_CLASS_HID_70dd7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1040] = { - .class_hid = BNXT_ULP_CLASS_HID_719af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1041] = { - .class_hid = BNXT_ULP_CLASS_HID_742a7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1042] = { - .class_hid = BNXT_ULP_CLASS_HID_74f3f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1043] = { - .class_hid = BNXT_ULP_CLASS_HID_74963, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1044] = { - .class_hid = BNXT_ULP_CLASS_HID_755fb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1045] = { - .class_hid = BNXT_ULP_CLASS_HID_72d03, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1046] = { - .class_hid = BNXT_ULP_CLASS_HID_7399b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1047] = { - .class_hid = BNXT_ULP_CLASS_HID_733df, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1048] = { - .class_hid = BNXT_ULP_CLASS_HID_74057, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1049] = { - .class_hid = BNXT_ULP_CLASS_HID_709ef, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1050] = { - .class_hid = BNXT_ULP_CLASS_HID_71667, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1051] = { - .class_hid = BNXT_ULP_CLASS_HID_70fab, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1052] = { - .class_hid = BNXT_ULP_CLASS_HID_71c23, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1053] = { - .class_hid = BNXT_ULP_CLASS_HID_750b7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1054] = { - .class_hid = BNXT_ULP_CLASS_HID_700c3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1055] = { - .class_hid = BNXT_ULP_CLASS_HID_75773, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1056] = { - .class_hid = BNXT_ULP_CLASS_HID_7069f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1057] = { - .class_hid = BNXT_ULP_CLASS_HID_2cfa3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1058] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc3b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1059] = { - .class_hid = BNXT_ULP_CLASS_HID_2d67f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1060] = { - .class_hid = BNXT_ULP_CLASS_HID_2858b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1061] = { - .class_hid = BNXT_ULP_CLASS_HID_2ba1f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1062] = { - .class_hid = BNXT_ULP_CLASS_HID_2c697, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1063] = { - .class_hid = BNXT_ULP_CLASS_HID_2c0db, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1064] = { - .class_hid = BNXT_ULP_CLASS_HID_2cd53, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1065] = { - .class_hid = BNXT_ULP_CLASS_HID_296eb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1066] = { - .class_hid = BNXT_ULP_CLASS_HID_2a363, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1067] = { - .class_hid = BNXT_ULP_CLASS_HID_29ca7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1068] = { - .class_hid = BNXT_ULP_CLASS_HID_2a93f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1069] = { - .class_hid = BNXT_ULP_CLASS_HID_28147, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1070] = { - .class_hid = BNXT_ULP_CLASS_HID_28ddf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1071] = { - .class_hid = BNXT_ULP_CLASS_HID_28703, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1072] = { - .class_hid = BNXT_ULP_CLASS_HID_2939b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1073] = { - .class_hid = BNXT_ULP_CLASS_HID_2bc93, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1074] = { - .class_hid = BNXT_ULP_CLASS_HID_2c96b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1075] = { - .class_hid = BNXT_ULP_CLASS_HID_2c2af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1076] = { - .class_hid = BNXT_ULP_CLASS_HID_2cf27, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1077] = { - .class_hid = BNXT_ULP_CLASS_HID_2a74f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1078] = { - .class_hid = BNXT_ULP_CLASS_HID_2b3c7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1079] = { - .class_hid = BNXT_ULP_CLASS_HID_2ad0b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1080] = { - .class_hid = BNXT_ULP_CLASS_HID_2b983, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1081] = { - .class_hid = BNXT_ULP_CLASS_HID_283db, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1082] = { - .class_hid = BNXT_ULP_CLASS_HID_29053, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1083] = { - .class_hid = BNXT_ULP_CLASS_HID_28997, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1084] = { - .class_hid = BNXT_ULP_CLASS_HID_2966f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1085] = { - .class_hid = BNXT_ULP_CLASS_HID_2cae3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1086] = { - .class_hid = BNXT_ULP_CLASS_HID_2d77b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1087] = { - .class_hid = BNXT_ULP_CLASS_HID_2d0bf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1088] = { - .class_hid = BNXT_ULP_CLASS_HID_280cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1089] = { - .class_hid = BNXT_ULP_CLASS_HID_6cb77, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1090] = { - .class_hid = BNXT_ULP_CLASS_HID_6d7cf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1091] = { - .class_hid = BNXT_ULP_CLASS_HID_6d133, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1092] = { - .class_hid = BNXT_ULP_CLASS_HID_6815f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1093] = { - .class_hid = BNXT_ULP_CLASS_HID_6b5d3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1094] = { - .class_hid = BNXT_ULP_CLASS_HID_6c1ab, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1095] = { - .class_hid = BNXT_ULP_CLASS_HID_6bbef, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1096] = { - .class_hid = BNXT_ULP_CLASS_HID_6c867, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1097] = { - .class_hid = BNXT_ULP_CLASS_HID_691bf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1098] = { - .class_hid = BNXT_ULP_CLASS_HID_69e37, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1099] = { - .class_hid = BNXT_ULP_CLASS_HID_6987b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1100] = { - .class_hid = BNXT_ULP_CLASS_HID_6a4f3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1101] = { - .class_hid = BNXT_ULP_CLASS_HID_6d947, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1102] = { - .class_hid = BNXT_ULP_CLASS_HID_68893, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1103] = { - .class_hid = BNXT_ULP_CLASS_HID_682d7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1104] = { - .class_hid = BNXT_ULP_CLASS_HID_68eaf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1105] = { - .class_hid = BNXT_ULP_CLASS_HID_6b7a7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1106] = { - .class_hid = BNXT_ULP_CLASS_HID_6c43f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1107] = { - .class_hid = BNXT_ULP_CLASS_HID_6be63, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1108] = { - .class_hid = BNXT_ULP_CLASS_HID_6cafb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1109] = { - .class_hid = BNXT_ULP_CLASS_HID_6a203, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1110] = { - .class_hid = BNXT_ULP_CLASS_HID_6ae9b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1111] = { - .class_hid = BNXT_ULP_CLASS_HID_6a8df, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1112] = { - .class_hid = BNXT_ULP_CLASS_HID_6b557, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1113] = { - .class_hid = BNXT_ULP_CLASS_HID_6dbdb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1114] = { - .class_hid = BNXT_ULP_CLASS_HID_68b67, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1115] = { - .class_hid = BNXT_ULP_CLASS_HID_684ab, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1116] = { - .class_hid = BNXT_ULP_CLASS_HID_69123, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1117] = { - .class_hid = BNXT_ULP_CLASS_HID_6c5b7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1118] = { - .class_hid = BNXT_ULP_CLASS_HID_6d20f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1119] = { - .class_hid = BNXT_ULP_CLASS_HID_6cc73, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1120] = { - .class_hid = BNXT_ULP_CLASS_HID_6d8cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1121] = { - .class_hid = BNXT_ULP_CLASS_HID_38977, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1122] = { - .class_hid = BNXT_ULP_CLASS_HID_395cf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1123] = { - .class_hid = BNXT_ULP_CLASS_HID_38f33, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1124] = { - .class_hid = BNXT_ULP_CLASS_HID_39b8b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1125] = { - .class_hid = BNXT_ULP_CLASS_HID_3d01f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1126] = { - .class_hid = BNXT_ULP_CLASS_HID_3dc97, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1127] = { - .class_hid = BNXT_ULP_CLASS_HID_3d6db, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1128] = { - .class_hid = BNXT_ULP_CLASS_HID_38667, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1129] = { - .class_hid = BNXT_ULP_CLASS_HID_3aceb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1130] = { - .class_hid = BNXT_ULP_CLASS_HID_3b963, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1131] = { - .class_hid = BNXT_ULP_CLASS_HID_3b2a7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1132] = { - .class_hid = BNXT_ULP_CLASS_HID_3bf3f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1133] = { - .class_hid = BNXT_ULP_CLASS_HID_39747, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1134] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3df, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1135] = { - .class_hid = BNXT_ULP_CLASS_HID_39d03, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1136] = { - .class_hid = BNXT_ULP_CLASS_HID_3a99b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1137] = { - .class_hid = BNXT_ULP_CLASS_HID_3d293, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1138] = { - .class_hid = BNXT_ULP_CLASS_HID_3823f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1139] = { - .class_hid = BNXT_ULP_CLASS_HID_3d8af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1140] = { - .class_hid = BNXT_ULP_CLASS_HID_388fb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1141] = { - .class_hid = BNXT_ULP_CLASS_HID_3bd4f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1142] = { - .class_hid = BNXT_ULP_CLASS_HID_3c9c7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1143] = { - .class_hid = BNXT_ULP_CLASS_HID_3c30b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1144] = { - .class_hid = BNXT_ULP_CLASS_HID_3cf83, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1145] = { - .class_hid = BNXT_ULP_CLASS_HID_399db, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1146] = { - .class_hid = BNXT_ULP_CLASS_HID_3a653, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1147] = { - .class_hid = BNXT_ULP_CLASS_HID_39f97, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1148] = { - .class_hid = BNXT_ULP_CLASS_HID_3ac6f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1149] = { - .class_hid = BNXT_ULP_CLASS_HID_383b7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1150] = { - .class_hid = BNXT_ULP_CLASS_HID_3900f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1151] = { - .class_hid = BNXT_ULP_CLASS_HID_38a73, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1152] = { - .class_hid = BNXT_ULP_CLASS_HID_396cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1153] = { - .class_hid = BNXT_ULP_CLASS_HID_7840b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1154] = { - .class_hid = BNXT_ULP_CLASS_HID_79083, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1155] = { - .class_hid = BNXT_ULP_CLASS_HID_78ac7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1156] = { - .class_hid = BNXT_ULP_CLASS_HID_7975f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1157] = { - .class_hid = BNXT_ULP_CLASS_HID_7cbd3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1158] = { - .class_hid = BNXT_ULP_CLASS_HID_7d7ab, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1159] = { - .class_hid = BNXT_ULP_CLASS_HID_7d1ef, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1160] = { - .class_hid = BNXT_ULP_CLASS_HID_7813b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1161] = { - .class_hid = BNXT_ULP_CLASS_HID_7a7bf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1162] = { - .class_hid = BNXT_ULP_CLASS_HID_7b437, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1163] = { - .class_hid = BNXT_ULP_CLASS_HID_7ae7b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1164] = { - .class_hid = BNXT_ULP_CLASS_HID_7baf3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1165] = { - .class_hid = BNXT_ULP_CLASS_HID_7921b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1166] = { - .class_hid = BNXT_ULP_CLASS_HID_79e93, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1167] = { - .class_hid = BNXT_ULP_CLASS_HID_798d7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1168] = { - .class_hid = BNXT_ULP_CLASS_HID_7a4af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1169] = { - .class_hid = BNXT_ULP_CLASS_HID_7cda7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1170] = { - .class_hid = BNXT_ULP_CLASS_HID_7da3f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1171] = { - .class_hid = BNXT_ULP_CLASS_HID_7d463, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1172] = { - .class_hid = BNXT_ULP_CLASS_HID_7838f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1173] = { - .class_hid = BNXT_ULP_CLASS_HID_7b803, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1174] = { - .class_hid = BNXT_ULP_CLASS_HID_7c49b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1175] = { - .class_hid = BNXT_ULP_CLASS_HID_7bedf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1176] = { - .class_hid = BNXT_ULP_CLASS_HID_7cb57, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1177] = { - .class_hid = BNXT_ULP_CLASS_HID_794ef, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1178] = { - .class_hid = BNXT_ULP_CLASS_HID_7a167, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1179] = { - .class_hid = BNXT_ULP_CLASS_HID_79aab, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1180] = { - .class_hid = BNXT_ULP_CLASS_HID_7a723, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1181] = { - .class_hid = BNXT_ULP_CLASS_HID_7dbb7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1182] = { - .class_hid = BNXT_ULP_CLASS_HID_78bc3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1183] = { - .class_hid = BNXT_ULP_CLASS_HID_78507, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1184] = { - .class_hid = BNXT_ULP_CLASS_HID_7919f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1185] = { - .class_hid = BNXT_ULP_CLASS_HID_a3bb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1186] = { - .class_hid = BNXT_ULP_CLASS_HID_b023, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1187] = { - .class_hid = BNXT_ULP_CLASS_HID_aa67, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1188] = { - .class_hid = BNXT_ULP_CLASS_HID_b6ef, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1189] = { - .class_hid = BNXT_ULP_CLASS_HID_8e07, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1190] = { - .class_hid = BNXT_ULP_CLASS_HID_9a8f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1191] = { - .class_hid = BNXT_ULP_CLASS_HID_94c3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1192] = { - .class_hid = BNXT_ULP_CLASS_HID_a14b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1193] = { - .class_hid = BNXT_ULP_CLASS_HID_c7cf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1194] = { - .class_hid = BNXT_ULP_CLASS_HID_d3b7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1195] = { - .class_hid = BNXT_ULP_CLASS_HID_cd8b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1196] = { - .class_hid = BNXT_ULP_CLASS_HID_da73, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1197] = { - .class_hid = BNXT_ULP_CLASS_HID_b1ab, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1198] = { - .class_hid = BNXT_ULP_CLASS_HID_be13, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1199] = { - .class_hid = BNXT_ULP_CLASS_HID_b857, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1200] = { - .class_hid = BNXT_ULP_CLASS_HID_c4df, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1201] = { - .class_hid = BNXT_ULP_CLASS_HID_49f6f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1202] = { - .class_hid = BNXT_ULP_CLASS_HID_4abd7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1203] = { - .class_hid = BNXT_ULP_CLASS_HID_4a52b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1204] = { - .class_hid = BNXT_ULP_CLASS_HID_4b193, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1205] = { - .class_hid = BNXT_ULP_CLASS_HID_489cb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1206] = { - .class_hid = BNXT_ULP_CLASS_HID_495b3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1207] = { - .class_hid = BNXT_ULP_CLASS_HID_48ff7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1208] = { - .class_hid = BNXT_ULP_CLASS_HID_49c7f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1209] = { - .class_hid = BNXT_ULP_CLASS_HID_4c2f3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1210] = { - .class_hid = BNXT_ULP_CLASS_HID_4cf7b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1211] = { - .class_hid = BNXT_ULP_CLASS_HID_4c8bf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1212] = { - .class_hid = BNXT_ULP_CLASS_HID_4d527, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1213] = { - .class_hid = BNXT_ULP_CLASS_HID_4ad5f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1214] = { - .class_hid = BNXT_ULP_CLASS_HID_4b9c7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1215] = { - .class_hid = BNXT_ULP_CLASS_HID_4b31b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1216] = { - .class_hid = BNXT_ULP_CLASS_HID_4bf83, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1217] = { - .class_hid = BNXT_ULP_CLASS_HID_1b9bb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1218] = { - .class_hid = BNXT_ULP_CLASS_HID_1c623, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1219] = { - .class_hid = BNXT_ULP_CLASS_HID_1c067, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1220] = { - .class_hid = BNXT_ULP_CLASS_HID_1ccef, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1221] = { - .class_hid = BNXT_ULP_CLASS_HID_1a407, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1222] = { - .class_hid = BNXT_ULP_CLASS_HID_1b08f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1223] = { - .class_hid = BNXT_ULP_CLASS_HID_1aac3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1224] = { - .class_hid = BNXT_ULP_CLASS_HID_1b74b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1225] = { - .class_hid = BNXT_ULP_CLASS_HID_180f3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1226] = { - .class_hid = BNXT_ULP_CLASS_HID_18d7b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1227] = { - .class_hid = BNXT_ULP_CLASS_HID_186bf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1228] = { - .class_hid = BNXT_ULP_CLASS_HID_19327, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1229] = { - .class_hid = BNXT_ULP_CLASS_HID_1c7ab, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1230] = { - .class_hid = BNXT_ULP_CLASS_HID_1d413, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1231] = { - .class_hid = BNXT_ULP_CLASS_HID_1ce57, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1232] = { - .class_hid = BNXT_ULP_CLASS_HID_1dadf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1233] = { - .class_hid = BNXT_ULP_CLASS_HID_5b56f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1234] = { - .class_hid = BNXT_ULP_CLASS_HID_5c1d7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1235] = { - .class_hid = BNXT_ULP_CLASS_HID_5bb2b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1236] = { - .class_hid = BNXT_ULP_CLASS_HID_5c793, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1237] = { - .class_hid = BNXT_ULP_CLASS_HID_59fcb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1238] = { - .class_hid = BNXT_ULP_CLASS_HID_5abb3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1239] = { - .class_hid = BNXT_ULP_CLASS_HID_5a5f7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1240] = { - .class_hid = BNXT_ULP_CLASS_HID_5b27f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1241] = { - .class_hid = BNXT_ULP_CLASS_HID_5d8f3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1242] = { - .class_hid = BNXT_ULP_CLASS_HID_5882f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1243] = { - .class_hid = BNXT_ULP_CLASS_HID_58263, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1244] = { - .class_hid = BNXT_ULP_CLASS_HID_58eeb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1245] = { - .class_hid = BNXT_ULP_CLASS_HID_5c35f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1246] = { - .class_hid = BNXT_ULP_CLASS_HID_5cfc7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1247] = { - .class_hid = BNXT_ULP_CLASS_HID_5c91b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1248] = { - .class_hid = BNXT_ULP_CLASS_HID_5d583, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1249] = { - .class_hid = BNXT_ULP_CLASS_HID_e93b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1250] = { - .class_hid = BNXT_ULP_CLASS_HID_f5a3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1251] = { - .class_hid = BNXT_ULP_CLASS_HID_efe7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1252] = { - .class_hid = BNXT_ULP_CLASS_HID_fc6f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1253] = { - .class_hid = BNXT_ULP_CLASS_HID_d387, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1254] = { - .class_hid = BNXT_ULP_CLASS_HID_e00f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1255] = { - .class_hid = BNXT_ULP_CLASS_HID_da43, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1256] = { - .class_hid = BNXT_ULP_CLASS_HID_e6cb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1257] = { - .class_hid = BNXT_ULP_CLASS_HID_cd4f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1258] = { - .class_hid = BNXT_ULP_CLASS_HID_d937, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1259] = { - .class_hid = BNXT_ULP_CLASS_HID_d30b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1260] = { - .class_hid = BNXT_ULP_CLASS_HID_c2a7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1261] = { - .class_hid = BNXT_ULP_CLASS_HID_f72b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1262] = { - .class_hid = BNXT_ULP_CLASS_HID_c393, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1263] = { - .class_hid = BNXT_ULP_CLASS_HID_fdd7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1264] = { - .class_hid = BNXT_ULP_CLASS_HID_ca5f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1265] = { - .class_hid = BNXT_ULP_CLASS_HID_4e4ef, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1266] = { - .class_hid = BNXT_ULP_CLASS_HID_4f157, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1267] = { - .class_hid = BNXT_ULP_CLASS_HID_4eaab, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1268] = { - .class_hid = BNXT_ULP_CLASS_HID_4f713, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1269] = { - .class_hid = BNXT_ULP_CLASS_HID_4cf4b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1270] = { - .class_hid = BNXT_ULP_CLASS_HID_4db33, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1271] = { - .class_hid = BNXT_ULP_CLASS_HID_4d577, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1272] = { - .class_hid = BNXT_ULP_CLASS_HID_4e1ff, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1273] = { - .class_hid = BNXT_ULP_CLASS_HID_4c873, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1274] = { - .class_hid = BNXT_ULP_CLASS_HID_4d4fb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1275] = { - .class_hid = BNXT_ULP_CLASS_HID_4ce3f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1276] = { - .class_hid = BNXT_ULP_CLASS_HID_4daa7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1277] = { - .class_hid = BNXT_ULP_CLASS_HID_4f2df, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1278] = { - .class_hid = BNXT_ULP_CLASS_HID_4ff47, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1279] = { - .class_hid = BNXT_ULP_CLASS_HID_4f89b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1280] = { - .class_hid = BNXT_ULP_CLASS_HID_4c503, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1281] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff3b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1282] = { - .class_hid = BNXT_ULP_CLASS_HID_1cba3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1283] = { - .class_hid = BNXT_ULP_CLASS_HID_1c5e7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1284] = { - .class_hid = BNXT_ULP_CLASS_HID_1d26f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1285] = { - .class_hid = BNXT_ULP_CLASS_HID_1e987, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1286] = { - .class_hid = BNXT_ULP_CLASS_HID_1f60f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1287] = { - .class_hid = BNXT_ULP_CLASS_HID_1f043, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1288] = { - .class_hid = BNXT_ULP_CLASS_HID_1fccb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1289] = { - .class_hid = BNXT_ULP_CLASS_HID_1c673, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1290] = { - .class_hid = BNXT_ULP_CLASS_HID_1d2fb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1291] = { - .class_hid = BNXT_ULP_CLASS_HID_1cc3f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1292] = { - .class_hid = BNXT_ULP_CLASS_HID_1d8a7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1293] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd2b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1294] = { - .class_hid = BNXT_ULP_CLASS_HID_1d993, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1295] = { - .class_hid = BNXT_ULP_CLASS_HID_1d3d7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1296] = { - .class_hid = BNXT_ULP_CLASS_HID_1c303, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1297] = { - .class_hid = BNXT_ULP_CLASS_HID_5faef, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1298] = { - .class_hid = BNXT_ULP_CLASS_HID_5c757, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1299] = { - .class_hid = BNXT_ULP_CLASS_HID_5c0ab, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1300] = { - .class_hid = BNXT_ULP_CLASS_HID_5cd13, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1301] = { - .class_hid = BNXT_ULP_CLASS_HID_5e54b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1302] = { - .class_hid = BNXT_ULP_CLASS_HID_5f133, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1303] = { - .class_hid = BNXT_ULP_CLASS_HID_5eb77, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1304] = { - .class_hid = BNXT_ULP_CLASS_HID_5f7ff, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1305] = { - .class_hid = BNXT_ULP_CLASS_HID_5c127, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1306] = { - .class_hid = BNXT_ULP_CLASS_HID_5cdaf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1307] = { - .class_hid = BNXT_ULP_CLASS_HID_5c7e3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1308] = { - .class_hid = BNXT_ULP_CLASS_HID_5d46b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1309] = { - .class_hid = BNXT_ULP_CLASS_HID_5c8df, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1310] = { - .class_hid = BNXT_ULP_CLASS_HID_5d547, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1311] = { - .class_hid = BNXT_ULP_CLASS_HID_5ce9b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1312] = { - .class_hid = BNXT_ULP_CLASS_HID_5db03, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1313] = { - .class_hid = BNXT_ULP_CLASS_HID_a6fb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1314] = { - .class_hid = BNXT_ULP_CLASS_HID_b363, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1315] = { - .class_hid = BNXT_ULP_CLASS_HID_aca7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1316] = { - .class_hid = BNXT_ULP_CLASS_HID_b92f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1317] = { - .class_hid = BNXT_ULP_CLASS_HID_b147, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1318] = { - .class_hid = BNXT_ULP_CLASS_HID_bdcf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1319] = { - .class_hid = BNXT_ULP_CLASS_HID_b703, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1320] = { - .class_hid = BNXT_ULP_CLASS_HID_a38b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1321] = { - .class_hid = BNXT_ULP_CLASS_HID_ea0f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1322] = { - .class_hid = BNXT_ULP_CLASS_HID_f6f7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1323] = { - .class_hid = BNXT_ULP_CLASS_HID_f0cb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1324] = { - .class_hid = BNXT_ULP_CLASS_HID_a067, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1325] = { - .class_hid = BNXT_ULP_CLASS_HID_b4eb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1326] = { - .class_hid = BNXT_ULP_CLASS_HID_e153, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1327] = { - .class_hid = BNXT_ULP_CLASS_HID_ba97, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1328] = { - .class_hid = BNXT_ULP_CLASS_HID_e71f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1329] = { - .class_hid = BNXT_ULP_CLASS_HID_4a1af, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1330] = { - .class_hid = BNXT_ULP_CLASS_HID_4ae17, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1331] = { - .class_hid = BNXT_ULP_CLASS_HID_4a86b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1332] = { - .class_hid = BNXT_ULP_CLASS_HID_4b4d3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1333] = { - .class_hid = BNXT_ULP_CLASS_HID_4ac0b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1334] = { - .class_hid = BNXT_ULP_CLASS_HID_4b8f3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1335] = { - .class_hid = BNXT_ULP_CLASS_HID_4b237, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1336] = { - .class_hid = BNXT_ULP_CLASS_HID_4bebf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1337] = { - .class_hid = BNXT_ULP_CLASS_HID_4e533, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1338] = { - .class_hid = BNXT_ULP_CLASS_HID_4f1bb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1339] = { - .class_hid = BNXT_ULP_CLASS_HID_4ebff, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1340] = { - .class_hid = BNXT_ULP_CLASS_HID_4f867, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1341] = { - .class_hid = BNXT_ULP_CLASS_HID_4af9f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1342] = { - .class_hid = BNXT_ULP_CLASS_HID_4bc07, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1343] = { - .class_hid = BNXT_ULP_CLASS_HID_4b65b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1344] = { - .class_hid = BNXT_ULP_CLASS_HID_4e2c3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1345] = { - .class_hid = BNXT_ULP_CLASS_HID_1bcfb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1346] = { - .class_hid = BNXT_ULP_CLASS_HID_1e963, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1347] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2a7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1348] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef2f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1349] = { - .class_hid = BNXT_ULP_CLASS_HID_1a747, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1350] = { - .class_hid = BNXT_ULP_CLASS_HID_1b3cf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1351] = { - .class_hid = BNXT_ULP_CLASS_HID_1ad03, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1352] = { - .class_hid = BNXT_ULP_CLASS_HID_1b98b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1353] = { - .class_hid = BNXT_ULP_CLASS_HID_1a333, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1354] = { - .class_hid = BNXT_ULP_CLASS_HID_1afbb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1355] = { - .class_hid = BNXT_ULP_CLASS_HID_1a9ff, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1356] = { - .class_hid = BNXT_ULP_CLASS_HID_1b667, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1357] = { - .class_hid = BNXT_ULP_CLASS_HID_1eaeb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1358] = { - .class_hid = BNXT_ULP_CLASS_HID_1f753, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1359] = { - .class_hid = BNXT_ULP_CLASS_HID_1f097, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1360] = { - .class_hid = BNXT_ULP_CLASS_HID_1a0c3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1361] = { - .class_hid = BNXT_ULP_CLASS_HID_5b7af, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1362] = { - .class_hid = BNXT_ULP_CLASS_HID_5e417, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1363] = { - .class_hid = BNXT_ULP_CLASS_HID_5be6b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1364] = { - .class_hid = BNXT_ULP_CLASS_HID_5ead3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1365] = { - .class_hid = BNXT_ULP_CLASS_HID_5a20b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1366] = { - .class_hid = BNXT_ULP_CLASS_HID_5aef3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1367] = { - .class_hid = BNXT_ULP_CLASS_HID_5a837, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1368] = { - .class_hid = BNXT_ULP_CLASS_HID_5b4bf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1369] = { - .class_hid = BNXT_ULP_CLASS_HID_5fb33, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1370] = { - .class_hid = BNXT_ULP_CLASS_HID_5ab6f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1371] = { - .class_hid = BNXT_ULP_CLASS_HID_5a4a3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1372] = { - .class_hid = BNXT_ULP_CLASS_HID_5b12b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1373] = { - .class_hid = BNXT_ULP_CLASS_HID_5e59f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1374] = { - .class_hid = BNXT_ULP_CLASS_HID_5f207, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1375] = { - .class_hid = BNXT_ULP_CLASS_HID_5ec5b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1376] = { - .class_hid = BNXT_ULP_CLASS_HID_5f8c3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1377] = { - .class_hid = BNXT_ULP_CLASS_HID_ec7b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1378] = { - .class_hid = BNXT_ULP_CLASS_HID_f8e3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1379] = { - .class_hid = BNXT_ULP_CLASS_HID_f227, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1380] = { - .class_hid = BNXT_ULP_CLASS_HID_feaf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1381] = { - .class_hid = BNXT_ULP_CLASS_HID_f6c7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1382] = { - .class_hid = BNXT_ULP_CLASS_HID_e34f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1383] = { - .class_hid = BNXT_ULP_CLASS_HID_fc83, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1384] = { - .class_hid = BNXT_ULP_CLASS_HID_e90b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1385] = { - .class_hid = BNXT_ULP_CLASS_HID_ef8f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1386] = { - .class_hid = BNXT_ULP_CLASS_HID_fc77, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1387] = { - .class_hid = BNXT_ULP_CLASS_HID_f64b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1388] = { - .class_hid = BNXT_ULP_CLASS_HID_e5e7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1389] = { - .class_hid = BNXT_ULP_CLASS_HID_fa6b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1390] = { - .class_hid = BNXT_ULP_CLASS_HID_e6d3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1391] = { - .class_hid = BNXT_ULP_CLASS_HID_e017, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1392] = { - .class_hid = BNXT_ULP_CLASS_HID_ec9f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1393] = { - .class_hid = BNXT_ULP_CLASS_HID_4e72f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1394] = { - .class_hid = BNXT_ULP_CLASS_HID_4f397, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1395] = { - .class_hid = BNXT_ULP_CLASS_HID_4edeb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1396] = { - .class_hid = BNXT_ULP_CLASS_HID_4fa53, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1397] = { - .class_hid = BNXT_ULP_CLASS_HID_4f18b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1398] = { - .class_hid = BNXT_ULP_CLASS_HID_4fe73, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1399] = { - .class_hid = BNXT_ULP_CLASS_HID_4f7b7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1400] = { - .class_hid = BNXT_ULP_CLASS_HID_4e43f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1401] = { - .class_hid = BNXT_ULP_CLASS_HID_4eab3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1402] = { - .class_hid = BNXT_ULP_CLASS_HID_4f73b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1403] = { - .class_hid = BNXT_ULP_CLASS_HID_4f17f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1404] = { - .class_hid = BNXT_ULP_CLASS_HID_4e0ab, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1405] = { - .class_hid = BNXT_ULP_CLASS_HID_4f51f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1406] = { - .class_hid = BNXT_ULP_CLASS_HID_4e187, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1407] = { - .class_hid = BNXT_ULP_CLASS_HID_4fbdb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1408] = { - .class_hid = BNXT_ULP_CLASS_HID_4e843, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1409] = { - .class_hid = BNXT_ULP_CLASS_HID_1e27b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1410] = { - .class_hid = BNXT_ULP_CLASS_HID_1eee3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1411] = { - .class_hid = BNXT_ULP_CLASS_HID_1e827, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1412] = { - .class_hid = BNXT_ULP_CLASS_HID_1f4af, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1413] = { - .class_hid = BNXT_ULP_CLASS_HID_1ecc7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1414] = { - .class_hid = BNXT_ULP_CLASS_HID_1f94f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1415] = { - .class_hid = BNXT_ULP_CLASS_HID_1f283, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1416] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff0b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1417] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8b3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1418] = { - .class_hid = BNXT_ULP_CLASS_HID_1f53b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1419] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef7f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1420] = { - .class_hid = BNXT_ULP_CLASS_HID_1fbe7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1421] = { - .class_hid = BNXT_ULP_CLASS_HID_1f06b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1422] = { - .class_hid = BNXT_ULP_CLASS_HID_1fcd3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1423] = { - .class_hid = BNXT_ULP_CLASS_HID_1f617, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1424] = { - .class_hid = BNXT_ULP_CLASS_HID_1e643, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1425] = { - .class_hid = BNXT_ULP_CLASS_HID_5fd2f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1426] = { - .class_hid = BNXT_ULP_CLASS_HID_5e997, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1427] = { - .class_hid = BNXT_ULP_CLASS_HID_5e3eb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1428] = { - .class_hid = BNXT_ULP_CLASS_HID_5f053, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1429] = { - .class_hid = BNXT_ULP_CLASS_HID_5e78b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1430] = { - .class_hid = BNXT_ULP_CLASS_HID_5f473, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1431] = { - .class_hid = BNXT_ULP_CLASS_HID_5edb7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1432] = { - .class_hid = BNXT_ULP_CLASS_HID_5fa3f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1433] = { - .class_hid = BNXT_ULP_CLASS_HID_5e467, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1434] = { - .class_hid = BNXT_ULP_CLASS_HID_5f0ef, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1435] = { - .class_hid = BNXT_ULP_CLASS_HID_5ea23, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1436] = { - .class_hid = BNXT_ULP_CLASS_HID_5f6ab, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1437] = { - .class_hid = BNXT_ULP_CLASS_HID_5eb1f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1438] = { - .class_hid = BNXT_ULP_CLASS_HID_5f787, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1439] = { - .class_hid = BNXT_ULP_CLASS_HID_5f1db, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1440] = { - .class_hid = BNXT_ULP_CLASS_HID_5e177, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1441] = { - .class_hid = BNXT_ULP_CLASS_HID_498d, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1442] = { - .class_hid = BNXT_ULP_CLASS_HID_4fc9, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1443] = { - .class_hid = BNXT_ULP_CLASS_HID_0cf9, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1444] = { - .class_hid = BNXT_ULP_CLASS_HID_1335, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1445] = { - .class_hid = BNXT_ULP_CLASS_HID_232d, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1446] = { - .class_hid = BNXT_ULP_CLASS_HID_2969, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1447] = { - .class_hid = BNXT_ULP_CLASS_HID_4345, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1448] = { - .class_hid = BNXT_ULP_CLASS_HID_4981, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1449] = { - .class_hid = BNXT_ULP_CLASS_HID_45809, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1450] = { - .class_hid = BNXT_ULP_CLASS_HID_40179, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1451] = { - .class_hid = BNXT_ULP_CLASS_HID_431a9, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1452] = { - .class_hid = BNXT_ULP_CLASS_HID_437d5, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1453] = { - .class_hid = BNXT_ULP_CLASS_HID_44e61, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1454] = { - .class_hid = BNXT_ULP_CLASS_HID_454ad, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1455] = { - .class_hid = BNXT_ULP_CLASS_HID_42801, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1456] = { - .class_hid = BNXT_ULP_CLASS_HID_42e4d, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1457] = { - .class_hid = BNXT_ULP_CLASS_HID_22c13, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1458] = { - .class_hid = BNXT_ULP_CLASS_HID_2322f, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1459] = { - .class_hid = BNXT_ULP_CLASS_HID_2164f, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1460] = { - .class_hid = BNXT_ULP_CLASS_HID_21c8b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1461] = { - .class_hid = BNXT_ULP_CLASS_HID_24f87, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1462] = { - .class_hid = BNXT_ULP_CLASS_HID_255c3, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1463] = { - .class_hid = BNXT_ULP_CLASS_HID_239e3, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1464] = { - .class_hid = BNXT_ULP_CLASS_HID_2403f, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1465] = { - .class_hid = BNXT_ULP_CLASS_HID_218c3, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1466] = { - .class_hid = BNXT_ULP_CLASS_HID_21f1f, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1467] = { - .class_hid = BNXT_ULP_CLASS_HID_2033f, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1468] = { - .class_hid = BNXT_ULP_CLASS_HID_2097b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1469] = { - .class_hid = BNXT_ULP_CLASS_HID_23c77, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1470] = { - .class_hid = BNXT_ULP_CLASS_HID_242b3, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1471] = { - .class_hid = BNXT_ULP_CLASS_HID_226d3, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1472] = { - .class_hid = BNXT_ULP_CLASS_HID_22cef, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1473] = { - .class_hid = BNXT_ULP_CLASS_HID_62727, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1474] = { - .class_hid = BNXT_ULP_CLASS_HID_62d63, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1475] = { - .class_hid = BNXT_ULP_CLASS_HID_61183, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1476] = { - .class_hid = BNXT_ULP_CLASS_HID_617df, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1477] = { - .class_hid = BNXT_ULP_CLASS_HID_64adb, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1478] = { - .class_hid = BNXT_ULP_CLASS_HID_65117, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1479] = { - .class_hid = BNXT_ULP_CLASS_HID_63537, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1480] = { - .class_hid = BNXT_ULP_CLASS_HID_63b73, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1481] = { - .class_hid = BNXT_ULP_CLASS_HID_61417, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1482] = { - .class_hid = BNXT_ULP_CLASS_HID_61a53, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1483] = { - .class_hid = BNXT_ULP_CLASS_HID_65b3f, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1484] = { - .class_hid = BNXT_ULP_CLASS_HID_6048f, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1485] = { - .class_hid = BNXT_ULP_CLASS_HID_6378b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1486] = { - .class_hid = BNXT_ULP_CLASS_HID_63dc7, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1487] = { - .class_hid = BNXT_ULP_CLASS_HID_621e7, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1488] = { - .class_hid = BNXT_ULP_CLASS_HID_62823, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1489] = { - .class_hid = BNXT_ULP_CLASS_HID_8b0b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1490] = { - .class_hid = BNXT_ULP_CLASS_HID_9137, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1491] = { - .class_hid = BNXT_ULP_CLASS_HID_d223, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1492] = { - .class_hid = BNXT_ULP_CLASS_HID_d86f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1493] = { - .class_hid = BNXT_ULP_CLASS_HID_ae9f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1494] = { - .class_hid = BNXT_ULP_CLASS_HID_b4db, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1495] = { - .class_hid = BNXT_ULP_CLASS_HID_98fb, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1496] = { - .class_hid = BNXT_ULP_CLASS_HID_9f27, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1497] = { - .class_hid = BNXT_ULP_CLASS_HID_4863f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1498] = { - .class_hid = BNXT_ULP_CLASS_HID_48c7b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1499] = { - .class_hid = BNXT_ULP_CLASS_HID_4cd57, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1500] = { - .class_hid = BNXT_ULP_CLASS_HID_4d393, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1501] = { - .class_hid = BNXT_ULP_CLASS_HID_4a9c3, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1502] = { - .class_hid = BNXT_ULP_CLASS_HID_4b00f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1503] = { - .class_hid = BNXT_ULP_CLASS_HID_4942f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1504] = { - .class_hid = BNXT_ULP_CLASS_HID_49a6b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1505] = { - .class_hid = BNXT_ULP_CLASS_HID_1a10b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1506] = { - .class_hid = BNXT_ULP_CLASS_HID_1a737, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1507] = { - .class_hid = BNXT_ULP_CLASS_HID_18b57, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1508] = { - .class_hid = BNXT_ULP_CLASS_HID_19193, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1509] = { - .class_hid = BNXT_ULP_CLASS_HID_1c49f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1510] = { - .class_hid = BNXT_ULP_CLASS_HID_1cadb, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1511] = { - .class_hid = BNXT_ULP_CLASS_HID_1aefb, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1512] = { - .class_hid = BNXT_ULP_CLASS_HID_1b527, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1513] = { - .class_hid = BNXT_ULP_CLASS_HID_59c3f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1514] = { - .class_hid = BNXT_ULP_CLASS_HID_5a27b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1515] = { - .class_hid = BNXT_ULP_CLASS_HID_5869b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1516] = { - .class_hid = BNXT_ULP_CLASS_HID_58cc7, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1517] = { - .class_hid = BNXT_ULP_CLASS_HID_5bfc3, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1518] = { - .class_hid = BNXT_ULP_CLASS_HID_5c60f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1519] = { - .class_hid = BNXT_ULP_CLASS_HID_5aa2f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1520] = { - .class_hid = BNXT_ULP_CLASS_HID_5b06b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1521] = { - .class_hid = BNXT_ULP_CLASS_HID_49ad, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1522] = { - .class_hid = BNXT_ULP_CLASS_HID_4fe9, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1523] = { - .class_hid = BNXT_ULP_CLASS_HID_0cd9, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1524] = { - .class_hid = BNXT_ULP_CLASS_HID_1315, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1525] = { - .class_hid = BNXT_ULP_CLASS_HID_230d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1526] = { - .class_hid = BNXT_ULP_CLASS_HID_2949, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1527] = { - .class_hid = BNXT_ULP_CLASS_HID_4365, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1528] = { - .class_hid = BNXT_ULP_CLASS_HID_49a1, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1529] = { - .class_hid = BNXT_ULP_CLASS_HID_4035, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1530] = { - .class_hid = BNXT_ULP_CLASS_HID_4671, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1531] = { - .class_hid = BNXT_ULP_CLASS_HID_0361, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1532] = { - .class_hid = BNXT_ULP_CLASS_HID_09bd, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1533] = { - .class_hid = BNXT_ULP_CLASS_HID_1995, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1534] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd1, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1535] = { - .class_hid = BNXT_ULP_CLASS_HID_398d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1536] = { - .class_hid = BNXT_ULP_CLASS_HID_3fc9, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1537] = { - .class_hid = BNXT_ULP_CLASS_HID_444e1, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1538] = { - .class_hid = BNXT_ULP_CLASS_HID_44b3d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1539] = { - .class_hid = BNXT_ULP_CLASS_HID_4082d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1540] = { - .class_hid = BNXT_ULP_CLASS_HID_40e69, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1541] = { - .class_hid = BNXT_ULP_CLASS_HID_41e41, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1542] = { - .class_hid = BNXT_ULP_CLASS_HID_4249d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1543] = { - .class_hid = BNXT_ULP_CLASS_HID_43eb9, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1544] = { - .class_hid = BNXT_ULP_CLASS_HID_444f5, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1545] = { - .class_hid = BNXT_ULP_CLASS_HID_43b09, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1546] = { - .class_hid = BNXT_ULP_CLASS_HID_44145, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1547] = { - .class_hid = BNXT_ULP_CLASS_HID_45b61, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1548] = { - .class_hid = BNXT_ULP_CLASS_HID_404f1, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1549] = { - .class_hid = BNXT_ULP_CLASS_HID_414e9, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1550] = { - .class_hid = BNXT_ULP_CLASS_HID_41b25, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1551] = { - .class_hid = BNXT_ULP_CLASS_HID_434c1, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1552] = { - .class_hid = BNXT_ULP_CLASS_HID_43b1d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1553] = { - .class_hid = BNXT_ULP_CLASS_HID_45829, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1554] = { - .class_hid = BNXT_ULP_CLASS_HID_40159, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1555] = { - .class_hid = BNXT_ULP_CLASS_HID_43189, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1556] = { - .class_hid = BNXT_ULP_CLASS_HID_437f5, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1557] = { - .class_hid = BNXT_ULP_CLASS_HID_44e41, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1558] = { - .class_hid = BNXT_ULP_CLASS_HID_4548d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1559] = { - .class_hid = BNXT_ULP_CLASS_HID_42821, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1560] = { - .class_hid = BNXT_ULP_CLASS_HID_42e6d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1561] = { - .class_hid = BNXT_ULP_CLASS_HID_6271d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1562] = { - .class_hid = BNXT_ULP_CLASS_HID_62d59, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1563] = { - .class_hid = BNXT_ULP_CLASS_HID_600fd, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1564] = { - .class_hid = BNXT_ULP_CLASS_HID_60739, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1565] = { - .class_hid = BNXT_ULP_CLASS_HID_61db5, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1566] = { - .class_hid = BNXT_ULP_CLASS_HID_623f1, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1567] = { - .class_hid = BNXT_ULP_CLASS_HID_65421, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1568] = { - .class_hid = BNXT_ULP_CLASS_HID_65a6d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1569] = { - .class_hid = BNXT_ULP_CLASS_HID_5111d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1570] = { - .class_hid = BNXT_ULP_CLASS_HID_51759, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1571] = { - .class_hid = BNXT_ULP_CLASS_HID_54789, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1572] = { - .class_hid = BNXT_ULP_CLASS_HID_54df5, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1573] = { - .class_hid = BNXT_ULP_CLASS_HID_507b5, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1574] = { - .class_hid = BNXT_ULP_CLASS_HID_50df1, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1575] = { - .class_hid = BNXT_ULP_CLASS_HID_53e21, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1576] = { - .class_hid = BNXT_ULP_CLASS_HID_5446d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1577] = { - .class_hid = BNXT_ULP_CLASS_HID_73d1d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1578] = { - .class_hid = BNXT_ULP_CLASS_HID_74359, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1579] = { - .class_hid = BNXT_ULP_CLASS_HID_716fd, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1580] = { - .class_hid = BNXT_ULP_CLASS_HID_71d39, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1581] = { - .class_hid = BNXT_ULP_CLASS_HID_733b5, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1582] = { - .class_hid = BNXT_ULP_CLASS_HID_739f1, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1583] = { - .class_hid = BNXT_ULP_CLASS_HID_70d15, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1584] = { - .class_hid = BNXT_ULP_CLASS_HID_71351, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1585] = { - .class_hid = BNXT_ULP_CLASS_HID_49cd, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1586] = { - .class_hid = BNXT_ULP_CLASS_HID_4f89, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1587] = { - .class_hid = BNXT_ULP_CLASS_HID_0cb9, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1588] = { - .class_hid = BNXT_ULP_CLASS_HID_1375, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1589] = { - .class_hid = BNXT_ULP_CLASS_HID_236d, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1590] = { - .class_hid = BNXT_ULP_CLASS_HID_2929, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1591] = { - .class_hid = BNXT_ULP_CLASS_HID_4305, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1592] = { - .class_hid = BNXT_ULP_CLASS_HID_49c1, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1593] = { - .class_hid = BNXT_ULP_CLASS_HID_4055, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1594] = { - .class_hid = BNXT_ULP_CLASS_HID_4611, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1595] = { - .class_hid = BNXT_ULP_CLASS_HID_0301, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1596] = { - .class_hid = BNXT_ULP_CLASS_HID_09dd, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1597] = { - .class_hid = BNXT_ULP_CLASS_HID_19f5, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1598] = { - .class_hid = BNXT_ULP_CLASS_HID_1fb1, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1599] = { - .class_hid = BNXT_ULP_CLASS_HID_39ed, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1600] = { - .class_hid = BNXT_ULP_CLASS_HID_3fa9, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1601] = { - .class_hid = BNXT_ULP_CLASS_HID_44481, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1602] = { - .class_hid = BNXT_ULP_CLASS_HID_44b5d, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1603] = { - .class_hid = BNXT_ULP_CLASS_HID_4084d, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1604] = { - .class_hid = BNXT_ULP_CLASS_HID_40e09, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1605] = { - .class_hid = BNXT_ULP_CLASS_HID_41e21, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1606] = { - .class_hid = BNXT_ULP_CLASS_HID_424fd, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1607] = { - .class_hid = BNXT_ULP_CLASS_HID_43ed9, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1608] = { - .class_hid = BNXT_ULP_CLASS_HID_44495, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1609] = { - .class_hid = BNXT_ULP_CLASS_HID_43b69, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1610] = { - .class_hid = BNXT_ULP_CLASS_HID_44125, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1611] = { - .class_hid = BNXT_ULP_CLASS_HID_45b01, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1612] = { - .class_hid = BNXT_ULP_CLASS_HID_40491, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1613] = { - .class_hid = BNXT_ULP_CLASS_HID_41489, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1614] = { - .class_hid = BNXT_ULP_CLASS_HID_41b45, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1615] = { - .class_hid = BNXT_ULP_CLASS_HID_434a1, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1616] = { - .class_hid = BNXT_ULP_CLASS_HID_43b7d, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1617] = { - .class_hid = BNXT_ULP_CLASS_HID_45849, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1618] = { - .class_hid = BNXT_ULP_CLASS_HID_40139, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1619] = { - .class_hid = BNXT_ULP_CLASS_HID_431e9, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1620] = { - .class_hid = BNXT_ULP_CLASS_HID_43795, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1621] = { - .class_hid = BNXT_ULP_CLASS_HID_44e21, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1622] = { - .class_hid = BNXT_ULP_CLASS_HID_454ed, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1623] = { - .class_hid = BNXT_ULP_CLASS_HID_42841, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1624] = { - .class_hid = BNXT_ULP_CLASS_HID_42e0d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1625] = { - .class_hid = BNXT_ULP_CLASS_HID_6277d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1626] = { - .class_hid = BNXT_ULP_CLASS_HID_62d39, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1627] = { - .class_hid = BNXT_ULP_CLASS_HID_6009d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1628] = { - .class_hid = BNXT_ULP_CLASS_HID_60759, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1629] = { - .class_hid = BNXT_ULP_CLASS_HID_61dd5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1630] = { - .class_hid = BNXT_ULP_CLASS_HID_62391, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1631] = { - .class_hid = BNXT_ULP_CLASS_HID_65441, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1632] = { - .class_hid = BNXT_ULP_CLASS_HID_65a0d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1633] = { - .class_hid = BNXT_ULP_CLASS_HID_5117d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1634] = { - .class_hid = BNXT_ULP_CLASS_HID_51739, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1635] = { - .class_hid = BNXT_ULP_CLASS_HID_547e9, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1636] = { - .class_hid = BNXT_ULP_CLASS_HID_54d95, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1637] = { - .class_hid = BNXT_ULP_CLASS_HID_507d5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1638] = { - .class_hid = BNXT_ULP_CLASS_HID_50d91, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1639] = { - .class_hid = BNXT_ULP_CLASS_HID_53e41, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1640] = { - .class_hid = BNXT_ULP_CLASS_HID_5440d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1641] = { - .class_hid = BNXT_ULP_CLASS_HID_73d7d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1642] = { - .class_hid = BNXT_ULP_CLASS_HID_74339, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1643] = { - .class_hid = BNXT_ULP_CLASS_HID_7169d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1644] = { - .class_hid = BNXT_ULP_CLASS_HID_71d59, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1645] = { - .class_hid = BNXT_ULP_CLASS_HID_733d5, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1646] = { - .class_hid = BNXT_ULP_CLASS_HID_73991, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1647] = { - .class_hid = BNXT_ULP_CLASS_HID_70d75, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1648] = { - .class_hid = BNXT_ULP_CLASS_HID_71331, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1649] = { - .class_hid = BNXT_ULP_CLASS_HID_22c33, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1650] = { - .class_hid = BNXT_ULP_CLASS_HID_2320f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1651] = { - .class_hid = BNXT_ULP_CLASS_HID_2166f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1652] = { - .class_hid = BNXT_ULP_CLASS_HID_21cab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1653] = { - .class_hid = BNXT_ULP_CLASS_HID_24fa7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1654] = { - .class_hid = BNXT_ULP_CLASS_HID_255e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1655] = { - .class_hid = BNXT_ULP_CLASS_HID_239c3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1656] = { - .class_hid = BNXT_ULP_CLASS_HID_2401f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1657] = { - .class_hid = BNXT_ULP_CLASS_HID_218e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1658] = { - .class_hid = BNXT_ULP_CLASS_HID_21f3f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1659] = { - .class_hid = BNXT_ULP_CLASS_HID_2031f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1660] = { - .class_hid = BNXT_ULP_CLASS_HID_2095b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1661] = { - .class_hid = BNXT_ULP_CLASS_HID_23c57, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1662] = { - .class_hid = BNXT_ULP_CLASS_HID_24293, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1663] = { - .class_hid = BNXT_ULP_CLASS_HID_226f3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1664] = { - .class_hid = BNXT_ULP_CLASS_HID_22ccf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1665] = { - .class_hid = BNXT_ULP_CLASS_HID_62707, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1666] = { - .class_hid = BNXT_ULP_CLASS_HID_62d43, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1667] = { - .class_hid = BNXT_ULP_CLASS_HID_611a3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1668] = { - .class_hid = BNXT_ULP_CLASS_HID_617ff, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1669] = { - .class_hid = BNXT_ULP_CLASS_HID_64afb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1670] = { - .class_hid = BNXT_ULP_CLASS_HID_65137, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1671] = { - .class_hid = BNXT_ULP_CLASS_HID_63517, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1672] = { - .class_hid = BNXT_ULP_CLASS_HID_63b53, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1673] = { - .class_hid = BNXT_ULP_CLASS_HID_61437, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1674] = { - .class_hid = BNXT_ULP_CLASS_HID_61a73, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1675] = { - .class_hid = BNXT_ULP_CLASS_HID_65b1f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1676] = { - .class_hid = BNXT_ULP_CLASS_HID_604af, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1677] = { - .class_hid = BNXT_ULP_CLASS_HID_637ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1678] = { - .class_hid = BNXT_ULP_CLASS_HID_63de7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1679] = { - .class_hid = BNXT_ULP_CLASS_HID_621c7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1680] = { - .class_hid = BNXT_ULP_CLASS_HID_62803, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1681] = { - .class_hid = BNXT_ULP_CLASS_HID_34233, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1682] = { - .class_hid = BNXT_ULP_CLASS_HID_3480f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1683] = { - .class_hid = BNXT_ULP_CLASS_HID_32c6f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1684] = { - .class_hid = BNXT_ULP_CLASS_HID_332ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1685] = { - .class_hid = BNXT_ULP_CLASS_HID_308fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1686] = { - .class_hid = BNXT_ULP_CLASS_HID_30f37, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1687] = { - .class_hid = BNXT_ULP_CLASS_HID_34fc3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1688] = { - .class_hid = BNXT_ULP_CLASS_HID_3561f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1689] = { - .class_hid = BNXT_ULP_CLASS_HID_32ee3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1690] = { - .class_hid = BNXT_ULP_CLASS_HID_3353f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1691] = { - .class_hid = BNXT_ULP_CLASS_HID_3191f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1692] = { - .class_hid = BNXT_ULP_CLASS_HID_31f5b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1693] = { - .class_hid = BNXT_ULP_CLASS_HID_35257, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1694] = { - .class_hid = BNXT_ULP_CLASS_HID_35893, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1695] = { - .class_hid = BNXT_ULP_CLASS_HID_33cf3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1696] = { - .class_hid = BNXT_ULP_CLASS_HID_342cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1697] = { - .class_hid = BNXT_ULP_CLASS_HID_73d07, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1698] = { - .class_hid = BNXT_ULP_CLASS_HID_74343, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1699] = { - .class_hid = BNXT_ULP_CLASS_HID_727a3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1700] = { - .class_hid = BNXT_ULP_CLASS_HID_72dff, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1701] = { - .class_hid = BNXT_ULP_CLASS_HID_703cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1702] = { - .class_hid = BNXT_ULP_CLASS_HID_70a0b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1703] = { - .class_hid = BNXT_ULP_CLASS_HID_74b17, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1704] = { - .class_hid = BNXT_ULP_CLASS_HID_75153, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1705] = { - .class_hid = BNXT_ULP_CLASS_HID_72a37, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1706] = { - .class_hid = BNXT_ULP_CLASS_HID_73073, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1707] = { - .class_hid = BNXT_ULP_CLASS_HID_71453, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1708] = { - .class_hid = BNXT_ULP_CLASS_HID_71aaf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1709] = { - .class_hid = BNXT_ULP_CLASS_HID_74dab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1710] = { - .class_hid = BNXT_ULP_CLASS_HID_753e7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1711] = { - .class_hid = BNXT_ULP_CLASS_HID_737c7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1712] = { - .class_hid = BNXT_ULP_CLASS_HID_73e03, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1713] = { - .class_hid = BNXT_ULP_CLASS_HID_2b733, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1714] = { - .class_hid = BNXT_ULP_CLASS_HID_2bd0f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1715] = { - .class_hid = BNXT_ULP_CLASS_HID_2a16f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1716] = { - .class_hid = BNXT_ULP_CLASS_HID_2a7ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1717] = { - .class_hid = BNXT_ULP_CLASS_HID_2daa7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1718] = { - .class_hid = BNXT_ULP_CLASS_HID_28437, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1719] = { - .class_hid = BNXT_ULP_CLASS_HID_2c4c3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1720] = { - .class_hid = BNXT_ULP_CLASS_HID_2cb1f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1721] = { - .class_hid = BNXT_ULP_CLASS_HID_2a3e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1722] = { - .class_hid = BNXT_ULP_CLASS_HID_2aa3f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1723] = { - .class_hid = BNXT_ULP_CLASS_HID_28e1f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1724] = { - .class_hid = BNXT_ULP_CLASS_HID_2945b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1725] = { - .class_hid = BNXT_ULP_CLASS_HID_2c757, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1726] = { - .class_hid = BNXT_ULP_CLASS_HID_2cd93, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1727] = { - .class_hid = BNXT_ULP_CLASS_HID_2b1f3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1728] = { - .class_hid = BNXT_ULP_CLASS_HID_2b7cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1729] = { - .class_hid = BNXT_ULP_CLASS_HID_6b207, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1730] = { - .class_hid = BNXT_ULP_CLASS_HID_6b843, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1731] = { - .class_hid = BNXT_ULP_CLASS_HID_69ca3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1732] = { - .class_hid = BNXT_ULP_CLASS_HID_6a2ff, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1733] = { - .class_hid = BNXT_ULP_CLASS_HID_6d5fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1734] = { - .class_hid = BNXT_ULP_CLASS_HID_6dc37, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1735] = { - .class_hid = BNXT_ULP_CLASS_HID_6c017, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1736] = { - .class_hid = BNXT_ULP_CLASS_HID_6c653, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1737] = { - .class_hid = BNXT_ULP_CLASS_HID_69f37, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1738] = { - .class_hid = BNXT_ULP_CLASS_HID_6a573, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1739] = { - .class_hid = BNXT_ULP_CLASS_HID_68953, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1740] = { - .class_hid = BNXT_ULP_CLASS_HID_68faf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1741] = { - .class_hid = BNXT_ULP_CLASS_HID_6c2ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1742] = { - .class_hid = BNXT_ULP_CLASS_HID_6c8e7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1743] = { - .class_hid = BNXT_ULP_CLASS_HID_6acc7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1744] = { - .class_hid = BNXT_ULP_CLASS_HID_6b303, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1745] = { - .class_hid = BNXT_ULP_CLASS_HID_3cd33, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1746] = { - .class_hid = BNXT_ULP_CLASS_HID_3d30f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1747] = { - .class_hid = BNXT_ULP_CLASS_HID_3b76f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1748] = { - .class_hid = BNXT_ULP_CLASS_HID_3bdab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1749] = { - .class_hid = BNXT_ULP_CLASS_HID_393fb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1750] = { - .class_hid = BNXT_ULP_CLASS_HID_39a37, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1751] = { - .class_hid = BNXT_ULP_CLASS_HID_3dac3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1752] = { - .class_hid = BNXT_ULP_CLASS_HID_38453, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1753] = { - .class_hid = BNXT_ULP_CLASS_HID_3b9e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1754] = { - .class_hid = BNXT_ULP_CLASS_HID_3c03f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1755] = { - .class_hid = BNXT_ULP_CLASS_HID_3a41f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1756] = { - .class_hid = BNXT_ULP_CLASS_HID_3aa5b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1757] = { - .class_hid = BNXT_ULP_CLASS_HID_380ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1758] = { - .class_hid = BNXT_ULP_CLASS_HID_386e7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1759] = { - .class_hid = BNXT_ULP_CLASS_HID_3c7f3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1760] = { - .class_hid = BNXT_ULP_CLASS_HID_3cdcf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1761] = { - .class_hid = BNXT_ULP_CLASS_HID_7c807, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1762] = { - .class_hid = BNXT_ULP_CLASS_HID_7ce43, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1763] = { - .class_hid = BNXT_ULP_CLASS_HID_7b2a3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1764] = { - .class_hid = BNXT_ULP_CLASS_HID_7b8ff, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1765] = { - .class_hid = BNXT_ULP_CLASS_HID_78ecf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1766] = { - .class_hid = BNXT_ULP_CLASS_HID_7950b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1767] = { - .class_hid = BNXT_ULP_CLASS_HID_7d617, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1768] = { - .class_hid = BNXT_ULP_CLASS_HID_7dc53, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1769] = { - .class_hid = BNXT_ULP_CLASS_HID_7b537, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1770] = { - .class_hid = BNXT_ULP_CLASS_HID_7bb73, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1771] = { - .class_hid = BNXT_ULP_CLASS_HID_79f53, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1772] = { - .class_hid = BNXT_ULP_CLASS_HID_7a5af, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1773] = { - .class_hid = BNXT_ULP_CLASS_HID_7d8ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1774] = { - .class_hid = BNXT_ULP_CLASS_HID_7823b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1775] = { - .class_hid = BNXT_ULP_CLASS_HID_7c2c7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1776] = { - .class_hid = BNXT_ULP_CLASS_HID_7c903, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1777] = { - .class_hid = BNXT_ULP_CLASS_HID_8b2b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1778] = { - .class_hid = BNXT_ULP_CLASS_HID_9117, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1779] = { - .class_hid = BNXT_ULP_CLASS_HID_d203, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1780] = { - .class_hid = BNXT_ULP_CLASS_HID_d84f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1781] = { - .class_hid = BNXT_ULP_CLASS_HID_aebf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1782] = { - .class_hid = BNXT_ULP_CLASS_HID_b4fb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1783] = { - .class_hid = BNXT_ULP_CLASS_HID_98db, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1784] = { - .class_hid = BNXT_ULP_CLASS_HID_9f07, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1785] = { - .class_hid = BNXT_ULP_CLASS_HID_4861f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1786] = { - .class_hid = BNXT_ULP_CLASS_HID_48c5b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1787] = { - .class_hid = BNXT_ULP_CLASS_HID_4cd77, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1788] = { - .class_hid = BNXT_ULP_CLASS_HID_4d3b3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1789] = { - .class_hid = BNXT_ULP_CLASS_HID_4a9e3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1790] = { - .class_hid = BNXT_ULP_CLASS_HID_4b02f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1791] = { - .class_hid = BNXT_ULP_CLASS_HID_4940f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1792] = { - .class_hid = BNXT_ULP_CLASS_HID_49a4b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1793] = { - .class_hid = BNXT_ULP_CLASS_HID_1a12b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1794] = { - .class_hid = BNXT_ULP_CLASS_HID_1a717, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1795] = { - .class_hid = BNXT_ULP_CLASS_HID_18b77, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1796] = { - .class_hid = BNXT_ULP_CLASS_HID_191b3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1797] = { - .class_hid = BNXT_ULP_CLASS_HID_1c4bf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1798] = { - .class_hid = BNXT_ULP_CLASS_HID_1cafb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1799] = { - .class_hid = BNXT_ULP_CLASS_HID_1aedb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1800] = { - .class_hid = BNXT_ULP_CLASS_HID_1b507, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1801] = { - .class_hid = BNXT_ULP_CLASS_HID_59c1f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1802] = { - .class_hid = BNXT_ULP_CLASS_HID_5a25b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1803] = { - .class_hid = BNXT_ULP_CLASS_HID_586bb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1804] = { - .class_hid = BNXT_ULP_CLASS_HID_58ce7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1805] = { - .class_hid = BNXT_ULP_CLASS_HID_5bfe3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1806] = { - .class_hid = BNXT_ULP_CLASS_HID_5c62f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1807] = { - .class_hid = BNXT_ULP_CLASS_HID_5aa0f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1808] = { - .class_hid = BNXT_ULP_CLASS_HID_5b04b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1809] = { - .class_hid = BNXT_ULP_CLASS_HID_d0ab, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1810] = { - .class_hid = BNXT_ULP_CLASS_HID_d697, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1811] = { - .class_hid = BNXT_ULP_CLASS_HID_d783, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1812] = { - .class_hid = BNXT_ULP_CLASS_HID_c133, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1813] = { - .class_hid = BNXT_ULP_CLASS_HID_f43f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1814] = { - .class_hid = BNXT_ULP_CLASS_HID_fa7b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1815] = { - .class_hid = BNXT_ULP_CLASS_HID_de5b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1816] = { - .class_hid = BNXT_ULP_CLASS_HID_e487, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1817] = { - .class_hid = BNXT_ULP_CLASS_HID_4cb9f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1818] = { - .class_hid = BNXT_ULP_CLASS_HID_4d1db, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1819] = { - .class_hid = BNXT_ULP_CLASS_HID_4d2f7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1820] = { - .class_hid = BNXT_ULP_CLASS_HID_4d933, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1821] = { - .class_hid = BNXT_ULP_CLASS_HID_4ef63, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1822] = { - .class_hid = BNXT_ULP_CLASS_HID_4f5af, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1823] = { - .class_hid = BNXT_ULP_CLASS_HID_4d98f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1824] = { - .class_hid = BNXT_ULP_CLASS_HID_4dfcb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1825] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6ab, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1826] = { - .class_hid = BNXT_ULP_CLASS_HID_1ec97, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1827] = { - .class_hid = BNXT_ULP_CLASS_HID_1d0f7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1828] = { - .class_hid = BNXT_ULP_CLASS_HID_1d733, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1829] = { - .class_hid = BNXT_ULP_CLASS_HID_1ca3f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1830] = { - .class_hid = BNXT_ULP_CLASS_HID_1d07b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1831] = { - .class_hid = BNXT_ULP_CLASS_HID_1f45b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1832] = { - .class_hid = BNXT_ULP_CLASS_HID_1fa87, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1833] = { - .class_hid = BNXT_ULP_CLASS_HID_5e19f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1834] = { - .class_hid = BNXT_ULP_CLASS_HID_5e7db, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1835] = { - .class_hid = BNXT_ULP_CLASS_HID_5cc3b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1836] = { - .class_hid = BNXT_ULP_CLASS_HID_5d267, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1837] = { - .class_hid = BNXT_ULP_CLASS_HID_5c563, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1838] = { - .class_hid = BNXT_ULP_CLASS_HID_5cbaf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1839] = { - .class_hid = BNXT_ULP_CLASS_HID_5ef8f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1840] = { - .class_hid = BNXT_ULP_CLASS_HID_5f5cb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1841] = { - .class_hid = BNXT_ULP_CLASS_HID_adeb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1842] = { - .class_hid = BNXT_ULP_CLASS_HID_b3d7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1843] = { - .class_hid = BNXT_ULP_CLASS_HID_f4c3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1844] = { - .class_hid = BNXT_ULP_CLASS_HID_fb0f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1845] = { - .class_hid = BNXT_ULP_CLASS_HID_b17f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1846] = { - .class_hid = BNXT_ULP_CLASS_HID_b7bb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1847] = { - .class_hid = BNXT_ULP_CLASS_HID_bb9b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1848] = { - .class_hid = BNXT_ULP_CLASS_HID_a1c7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1849] = { - .class_hid = BNXT_ULP_CLASS_HID_4a8df, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1850] = { - .class_hid = BNXT_ULP_CLASS_HID_4af1b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1851] = { - .class_hid = BNXT_ULP_CLASS_HID_4f037, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1852] = { - .class_hid = BNXT_ULP_CLASS_HID_4f673, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1853] = { - .class_hid = BNXT_ULP_CLASS_HID_4aca3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1854] = { - .class_hid = BNXT_ULP_CLASS_HID_4b2ef, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1855] = { - .class_hid = BNXT_ULP_CLASS_HID_4b6cf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1856] = { - .class_hid = BNXT_ULP_CLASS_HID_4bd0b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1857] = { - .class_hid = BNXT_ULP_CLASS_HID_1a3eb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1858] = { - .class_hid = BNXT_ULP_CLASS_HID_1a9d7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1859] = { - .class_hid = BNXT_ULP_CLASS_HID_1ae37, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1860] = { - .class_hid = BNXT_ULP_CLASS_HID_1b473, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1861] = { - .class_hid = BNXT_ULP_CLASS_HID_1e77f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1862] = { - .class_hid = BNXT_ULP_CLASS_HID_1edbb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1863] = { - .class_hid = BNXT_ULP_CLASS_HID_1b19b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1864] = { - .class_hid = BNXT_ULP_CLASS_HID_1b7c7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1865] = { - .class_hid = BNXT_ULP_CLASS_HID_5bedf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1866] = { - .class_hid = BNXT_ULP_CLASS_HID_5a51b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1867] = { - .class_hid = BNXT_ULP_CLASS_HID_5a97b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1868] = { - .class_hid = BNXT_ULP_CLASS_HID_5afa7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1869] = { - .class_hid = BNXT_ULP_CLASS_HID_5e2a3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1870] = { - .class_hid = BNXT_ULP_CLASS_HID_5e8ef, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1871] = { - .class_hid = BNXT_ULP_CLASS_HID_5accf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1872] = { - .class_hid = BNXT_ULP_CLASS_HID_5b30b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1873] = { - .class_hid = BNXT_ULP_CLASS_HID_f36b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1874] = { - .class_hid = BNXT_ULP_CLASS_HID_f957, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1875] = { - .class_hid = BNXT_ULP_CLASS_HID_fa43, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1876] = { - .class_hid = BNXT_ULP_CLASS_HID_e3f3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1877] = { - .class_hid = BNXT_ULP_CLASS_HID_f6ff, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1878] = { - .class_hid = BNXT_ULP_CLASS_HID_fd3b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1879] = { - .class_hid = BNXT_ULP_CLASS_HID_e11b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1880] = { - .class_hid = BNXT_ULP_CLASS_HID_e747, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1881] = { - .class_hid = BNXT_ULP_CLASS_HID_4ee5f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1882] = { - .class_hid = BNXT_ULP_CLASS_HID_4f49b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1883] = { - .class_hid = BNXT_ULP_CLASS_HID_4f5b7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1884] = { - .class_hid = BNXT_ULP_CLASS_HID_4fbf3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1885] = { - .class_hid = BNXT_ULP_CLASS_HID_4f223, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1886] = { - .class_hid = BNXT_ULP_CLASS_HID_4f86f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1887] = { - .class_hid = BNXT_ULP_CLASS_HID_4fc4f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1888] = { - .class_hid = BNXT_ULP_CLASS_HID_4e28b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1889] = { - .class_hid = BNXT_ULP_CLASS_HID_1e96b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1890] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef57, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1891] = { - .class_hid = BNXT_ULP_CLASS_HID_1f3b7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1892] = { - .class_hid = BNXT_ULP_CLASS_HID_1f9f3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1893] = { - .class_hid = BNXT_ULP_CLASS_HID_1ecff, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1894] = { - .class_hid = BNXT_ULP_CLASS_HID_1f33b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1895] = { - .class_hid = BNXT_ULP_CLASS_HID_1f71b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1896] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd47, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1897] = { - .class_hid = BNXT_ULP_CLASS_HID_5e45f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1898] = { - .class_hid = BNXT_ULP_CLASS_HID_5ea9b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1899] = { - .class_hid = BNXT_ULP_CLASS_HID_5eefb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1900] = { - .class_hid = BNXT_ULP_CLASS_HID_5f527, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1901] = { - .class_hid = BNXT_ULP_CLASS_HID_5e823, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1902] = { - .class_hid = BNXT_ULP_CLASS_HID_5ee6f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1903] = { - .class_hid = BNXT_ULP_CLASS_HID_5f24f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1904] = { - .class_hid = BNXT_ULP_CLASS_HID_5f88b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1905] = { - .class_hid = BNXT_ULP_CLASS_HID_22c53, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1906] = { - .class_hid = BNXT_ULP_CLASS_HID_2326f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1907] = { - .class_hid = BNXT_ULP_CLASS_HID_2160f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1908] = { - .class_hid = BNXT_ULP_CLASS_HID_21ccb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1909] = { - .class_hid = BNXT_ULP_CLASS_HID_24fc7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1910] = { - .class_hid = BNXT_ULP_CLASS_HID_25583, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1911] = { - .class_hid = BNXT_ULP_CLASS_HID_239a3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1912] = { - .class_hid = BNXT_ULP_CLASS_HID_2407f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1913] = { - .class_hid = BNXT_ULP_CLASS_HID_21883, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1914] = { - .class_hid = BNXT_ULP_CLASS_HID_21f5f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1915] = { - .class_hid = BNXT_ULP_CLASS_HID_2037f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1916] = { - .class_hid = BNXT_ULP_CLASS_HID_2093b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1917] = { - .class_hid = BNXT_ULP_CLASS_HID_23c37, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1918] = { - .class_hid = BNXT_ULP_CLASS_HID_242f3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1919] = { - .class_hid = BNXT_ULP_CLASS_HID_22693, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1920] = { - .class_hid = BNXT_ULP_CLASS_HID_22caf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1921] = { - .class_hid = BNXT_ULP_CLASS_HID_62767, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1922] = { - .class_hid = BNXT_ULP_CLASS_HID_62d23, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1923] = { - .class_hid = BNXT_ULP_CLASS_HID_611c3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1924] = { - .class_hid = BNXT_ULP_CLASS_HID_6179f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1925] = { - .class_hid = BNXT_ULP_CLASS_HID_64a9b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1926] = { - .class_hid = BNXT_ULP_CLASS_HID_65157, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1927] = { - .class_hid = BNXT_ULP_CLASS_HID_63577, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1928] = { - .class_hid = BNXT_ULP_CLASS_HID_63b33, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1929] = { - .class_hid = BNXT_ULP_CLASS_HID_61457, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1930] = { - .class_hid = BNXT_ULP_CLASS_HID_61a13, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1931] = { - .class_hid = BNXT_ULP_CLASS_HID_65b7f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1932] = { - .class_hid = BNXT_ULP_CLASS_HID_604cf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1933] = { - .class_hid = BNXT_ULP_CLASS_HID_637cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1934] = { - .class_hid = BNXT_ULP_CLASS_HID_63d87, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1935] = { - .class_hid = BNXT_ULP_CLASS_HID_621a7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1936] = { - .class_hid = BNXT_ULP_CLASS_HID_62863, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1937] = { - .class_hid = BNXT_ULP_CLASS_HID_34253, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1938] = { - .class_hid = BNXT_ULP_CLASS_HID_3486f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1939] = { - .class_hid = BNXT_ULP_CLASS_HID_32c0f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1940] = { - .class_hid = BNXT_ULP_CLASS_HID_332cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1941] = { - .class_hid = BNXT_ULP_CLASS_HID_3089b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1942] = { - .class_hid = BNXT_ULP_CLASS_HID_30f57, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1943] = { - .class_hid = BNXT_ULP_CLASS_HID_34fa3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1944] = { - .class_hid = BNXT_ULP_CLASS_HID_3567f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1945] = { - .class_hid = BNXT_ULP_CLASS_HID_32e83, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1946] = { - .class_hid = BNXT_ULP_CLASS_HID_3355f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1947] = { - .class_hid = BNXT_ULP_CLASS_HID_3197f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1948] = { - .class_hid = BNXT_ULP_CLASS_HID_31f3b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1949] = { - .class_hid = BNXT_ULP_CLASS_HID_35237, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1950] = { - .class_hid = BNXT_ULP_CLASS_HID_358f3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1951] = { - .class_hid = BNXT_ULP_CLASS_HID_33c93, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1952] = { - .class_hid = BNXT_ULP_CLASS_HID_342af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1953] = { - .class_hid = BNXT_ULP_CLASS_HID_73d67, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1954] = { - .class_hid = BNXT_ULP_CLASS_HID_74323, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1955] = { - .class_hid = BNXT_ULP_CLASS_HID_727c3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1956] = { - .class_hid = BNXT_ULP_CLASS_HID_72d9f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1957] = { - .class_hid = BNXT_ULP_CLASS_HID_703af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1958] = { - .class_hid = BNXT_ULP_CLASS_HID_70a6b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1959] = { - .class_hid = BNXT_ULP_CLASS_HID_74b77, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1960] = { - .class_hid = BNXT_ULP_CLASS_HID_75133, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1961] = { - .class_hid = BNXT_ULP_CLASS_HID_72a57, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1962] = { - .class_hid = BNXT_ULP_CLASS_HID_73013, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1963] = { - .class_hid = BNXT_ULP_CLASS_HID_71433, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1964] = { - .class_hid = BNXT_ULP_CLASS_HID_71acf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1965] = { - .class_hid = BNXT_ULP_CLASS_HID_74dcb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1966] = { - .class_hid = BNXT_ULP_CLASS_HID_75387, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1967] = { - .class_hid = BNXT_ULP_CLASS_HID_737a7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1968] = { - .class_hid = BNXT_ULP_CLASS_HID_73e63, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1969] = { - .class_hid = BNXT_ULP_CLASS_HID_2b753, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1970] = { - .class_hid = BNXT_ULP_CLASS_HID_2bd6f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1971] = { - .class_hid = BNXT_ULP_CLASS_HID_2a10f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1972] = { - .class_hid = BNXT_ULP_CLASS_HID_2a7cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1973] = { - .class_hid = BNXT_ULP_CLASS_HID_2dac7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1974] = { - .class_hid = BNXT_ULP_CLASS_HID_28457, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1975] = { - .class_hid = BNXT_ULP_CLASS_HID_2c4a3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1976] = { - .class_hid = BNXT_ULP_CLASS_HID_2cb7f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1977] = { - .class_hid = BNXT_ULP_CLASS_HID_2a383, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1978] = { - .class_hid = BNXT_ULP_CLASS_HID_2aa5f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1979] = { - .class_hid = BNXT_ULP_CLASS_HID_28e7f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1980] = { - .class_hid = BNXT_ULP_CLASS_HID_2943b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1981] = { - .class_hid = BNXT_ULP_CLASS_HID_2c737, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1982] = { - .class_hid = BNXT_ULP_CLASS_HID_2cdf3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1983] = { - .class_hid = BNXT_ULP_CLASS_HID_2b193, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1984] = { - .class_hid = BNXT_ULP_CLASS_HID_2b7af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1985] = { - .class_hid = BNXT_ULP_CLASS_HID_6b267, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1986] = { - .class_hid = BNXT_ULP_CLASS_HID_6b823, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1987] = { - .class_hid = BNXT_ULP_CLASS_HID_69cc3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1988] = { - .class_hid = BNXT_ULP_CLASS_HID_6a29f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1989] = { - .class_hid = BNXT_ULP_CLASS_HID_6d59b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1990] = { - .class_hid = BNXT_ULP_CLASS_HID_6dc57, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1991] = { - .class_hid = BNXT_ULP_CLASS_HID_6c077, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1992] = { - .class_hid = BNXT_ULP_CLASS_HID_6c633, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1993] = { - .class_hid = BNXT_ULP_CLASS_HID_69f57, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1994] = { - .class_hid = BNXT_ULP_CLASS_HID_6a513, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1995] = { - .class_hid = BNXT_ULP_CLASS_HID_68933, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1996] = { - .class_hid = BNXT_ULP_CLASS_HID_68fcf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1997] = { - .class_hid = BNXT_ULP_CLASS_HID_6c2cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1998] = { - .class_hid = BNXT_ULP_CLASS_HID_6c887, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [1999] = { - .class_hid = BNXT_ULP_CLASS_HID_6aca7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2000] = { - .class_hid = BNXT_ULP_CLASS_HID_6b363, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2001] = { - .class_hid = BNXT_ULP_CLASS_HID_3cd53, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2002] = { - .class_hid = BNXT_ULP_CLASS_HID_3d36f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2003] = { - .class_hid = BNXT_ULP_CLASS_HID_3b70f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2004] = { - .class_hid = BNXT_ULP_CLASS_HID_3bdcb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2005] = { - .class_hid = BNXT_ULP_CLASS_HID_3939b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2006] = { - .class_hid = BNXT_ULP_CLASS_HID_39a57, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2007] = { - .class_hid = BNXT_ULP_CLASS_HID_3daa3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2008] = { - .class_hid = BNXT_ULP_CLASS_HID_38433, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2009] = { - .class_hid = BNXT_ULP_CLASS_HID_3b983, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2010] = { - .class_hid = BNXT_ULP_CLASS_HID_3c05f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2011] = { - .class_hid = BNXT_ULP_CLASS_HID_3a47f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2012] = { - .class_hid = BNXT_ULP_CLASS_HID_3aa3b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2013] = { - .class_hid = BNXT_ULP_CLASS_HID_380cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2014] = { - .class_hid = BNXT_ULP_CLASS_HID_38687, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2015] = { - .class_hid = BNXT_ULP_CLASS_HID_3c793, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2016] = { - .class_hid = BNXT_ULP_CLASS_HID_3cdaf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2017] = { - .class_hid = BNXT_ULP_CLASS_HID_7c867, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2018] = { - .class_hid = BNXT_ULP_CLASS_HID_7ce23, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2019] = { - .class_hid = BNXT_ULP_CLASS_HID_7b2c3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2020] = { - .class_hid = BNXT_ULP_CLASS_HID_7b89f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2021] = { - .class_hid = BNXT_ULP_CLASS_HID_78eaf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2022] = { - .class_hid = BNXT_ULP_CLASS_HID_7956b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2023] = { - .class_hid = BNXT_ULP_CLASS_HID_7d677, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2024] = { - .class_hid = BNXT_ULP_CLASS_HID_7dc33, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2025] = { - .class_hid = BNXT_ULP_CLASS_HID_7b557, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2026] = { - .class_hid = BNXT_ULP_CLASS_HID_7bb13, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2027] = { - .class_hid = BNXT_ULP_CLASS_HID_79f33, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2028] = { - .class_hid = BNXT_ULP_CLASS_HID_7a5cf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2029] = { - .class_hid = BNXT_ULP_CLASS_HID_7d8cb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2030] = { - .class_hid = BNXT_ULP_CLASS_HID_7825b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2031] = { - .class_hid = BNXT_ULP_CLASS_HID_7c2a7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2032] = { - .class_hid = BNXT_ULP_CLASS_HID_7c963, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2033] = { - .class_hid = BNXT_ULP_CLASS_HID_8b4b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2034] = { - .class_hid = BNXT_ULP_CLASS_HID_9177, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2035] = { - .class_hid = BNXT_ULP_CLASS_HID_d263, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2036] = { - .class_hid = BNXT_ULP_CLASS_HID_d82f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2037] = { - .class_hid = BNXT_ULP_CLASS_HID_aedf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2038] = { - .class_hid = BNXT_ULP_CLASS_HID_b49b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2039] = { - .class_hid = BNXT_ULP_CLASS_HID_98bb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2040] = { - .class_hid = BNXT_ULP_CLASS_HID_9f67, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2041] = { - .class_hid = BNXT_ULP_CLASS_HID_4867f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2042] = { - .class_hid = BNXT_ULP_CLASS_HID_48c3b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2043] = { - .class_hid = BNXT_ULP_CLASS_HID_4cd17, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2044] = { - .class_hid = BNXT_ULP_CLASS_HID_4d3d3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2045] = { - .class_hid = BNXT_ULP_CLASS_HID_4a983, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2046] = { - .class_hid = BNXT_ULP_CLASS_HID_4b04f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2047] = { - .class_hid = BNXT_ULP_CLASS_HID_4946f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2048] = { - .class_hid = BNXT_ULP_CLASS_HID_49a2b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2049] = { - .class_hid = BNXT_ULP_CLASS_HID_1a14b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2050] = { - .class_hid = BNXT_ULP_CLASS_HID_1a777, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2051] = { - .class_hid = BNXT_ULP_CLASS_HID_18b17, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2052] = { - .class_hid = BNXT_ULP_CLASS_HID_191d3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2053] = { - .class_hid = BNXT_ULP_CLASS_HID_1c4df, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2054] = { - .class_hid = BNXT_ULP_CLASS_HID_1ca9b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2055] = { - .class_hid = BNXT_ULP_CLASS_HID_1aebb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2056] = { - .class_hid = BNXT_ULP_CLASS_HID_1b567, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2057] = { - .class_hid = BNXT_ULP_CLASS_HID_59c7f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2058] = { - .class_hid = BNXT_ULP_CLASS_HID_5a23b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2059] = { - .class_hid = BNXT_ULP_CLASS_HID_586db, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2060] = { - .class_hid = BNXT_ULP_CLASS_HID_58c87, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2061] = { - .class_hid = BNXT_ULP_CLASS_HID_5bf83, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2062] = { - .class_hid = BNXT_ULP_CLASS_HID_5c64f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2063] = { - .class_hid = BNXT_ULP_CLASS_HID_5aa6f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2064] = { - .class_hid = BNXT_ULP_CLASS_HID_5b02b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2065] = { - .class_hid = BNXT_ULP_CLASS_HID_d0cb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2066] = { - .class_hid = BNXT_ULP_CLASS_HID_d6f7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2067] = { - .class_hid = BNXT_ULP_CLASS_HID_d7e3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2068] = { - .class_hid = BNXT_ULP_CLASS_HID_c153, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2069] = { - .class_hid = BNXT_ULP_CLASS_HID_f45f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2070] = { - .class_hid = BNXT_ULP_CLASS_HID_fa1b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2071] = { - .class_hid = BNXT_ULP_CLASS_HID_de3b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2072] = { - .class_hid = BNXT_ULP_CLASS_HID_e4e7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2073] = { - .class_hid = BNXT_ULP_CLASS_HID_4cbff, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2074] = { - .class_hid = BNXT_ULP_CLASS_HID_4d1bb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2075] = { - .class_hid = BNXT_ULP_CLASS_HID_4d297, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2076] = { - .class_hid = BNXT_ULP_CLASS_HID_4d953, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2077] = { - .class_hid = BNXT_ULP_CLASS_HID_4ef03, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2078] = { - .class_hid = BNXT_ULP_CLASS_HID_4f5cf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2079] = { - .class_hid = BNXT_ULP_CLASS_HID_4d9ef, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2080] = { - .class_hid = BNXT_ULP_CLASS_HID_4dfab, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2081] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6cb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2082] = { - .class_hid = BNXT_ULP_CLASS_HID_1ecf7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2083] = { - .class_hid = BNXT_ULP_CLASS_HID_1d097, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2084] = { - .class_hid = BNXT_ULP_CLASS_HID_1d753, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2085] = { - .class_hid = BNXT_ULP_CLASS_HID_1ca5f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2086] = { - .class_hid = BNXT_ULP_CLASS_HID_1d01b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2087] = { - .class_hid = BNXT_ULP_CLASS_HID_1f43b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2088] = { - .class_hid = BNXT_ULP_CLASS_HID_1fae7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2089] = { - .class_hid = BNXT_ULP_CLASS_HID_5e1ff, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2090] = { - .class_hid = BNXT_ULP_CLASS_HID_5e7bb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2091] = { - .class_hid = BNXT_ULP_CLASS_HID_5cc5b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2092] = { - .class_hid = BNXT_ULP_CLASS_HID_5d207, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2093] = { - .class_hid = BNXT_ULP_CLASS_HID_5c503, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2094] = { - .class_hid = BNXT_ULP_CLASS_HID_5cbcf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2095] = { - .class_hid = BNXT_ULP_CLASS_HID_5efef, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2096] = { - .class_hid = BNXT_ULP_CLASS_HID_5f5ab, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2097] = { - .class_hid = BNXT_ULP_CLASS_HID_ad8b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2098] = { - .class_hid = BNXT_ULP_CLASS_HID_b3b7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2099] = { - .class_hid = BNXT_ULP_CLASS_HID_f4a3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2100] = { - .class_hid = BNXT_ULP_CLASS_HID_fb6f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2101] = { - .class_hid = BNXT_ULP_CLASS_HID_b11f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2102] = { - .class_hid = BNXT_ULP_CLASS_HID_b7db, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2103] = { - .class_hid = BNXT_ULP_CLASS_HID_bbfb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2104] = { - .class_hid = BNXT_ULP_CLASS_HID_a1a7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2105] = { - .class_hid = BNXT_ULP_CLASS_HID_4a8bf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2106] = { - .class_hid = BNXT_ULP_CLASS_HID_4af7b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2107] = { - .class_hid = BNXT_ULP_CLASS_HID_4f057, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2108] = { - .class_hid = BNXT_ULP_CLASS_HID_4f613, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2109] = { - .class_hid = BNXT_ULP_CLASS_HID_4acc3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2110] = { - .class_hid = BNXT_ULP_CLASS_HID_4b28f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2111] = { - .class_hid = BNXT_ULP_CLASS_HID_4b6af, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2112] = { - .class_hid = BNXT_ULP_CLASS_HID_4bd6b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2113] = { - .class_hid = BNXT_ULP_CLASS_HID_1a38b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2114] = { - .class_hid = BNXT_ULP_CLASS_HID_1a9b7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2115] = { - .class_hid = BNXT_ULP_CLASS_HID_1ae57, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2116] = { - .class_hid = BNXT_ULP_CLASS_HID_1b413, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2117] = { - .class_hid = BNXT_ULP_CLASS_HID_1e71f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2118] = { - .class_hid = BNXT_ULP_CLASS_HID_1eddb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2119] = { - .class_hid = BNXT_ULP_CLASS_HID_1b1fb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2120] = { - .class_hid = BNXT_ULP_CLASS_HID_1b7a7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2121] = { - .class_hid = BNXT_ULP_CLASS_HID_5bebf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2122] = { - .class_hid = BNXT_ULP_CLASS_HID_5a57b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2123] = { - .class_hid = BNXT_ULP_CLASS_HID_5a91b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2124] = { - .class_hid = BNXT_ULP_CLASS_HID_5afc7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2125] = { - .class_hid = BNXT_ULP_CLASS_HID_5e2c3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2126] = { - .class_hid = BNXT_ULP_CLASS_HID_5e88f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2127] = { - .class_hid = BNXT_ULP_CLASS_HID_5acaf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2128] = { - .class_hid = BNXT_ULP_CLASS_HID_5b36b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2129] = { - .class_hid = BNXT_ULP_CLASS_HID_f30b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2130] = { - .class_hid = BNXT_ULP_CLASS_HID_f937, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2131] = { - .class_hid = BNXT_ULP_CLASS_HID_fa23, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2132] = { - .class_hid = BNXT_ULP_CLASS_HID_e393, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2133] = { - .class_hid = BNXT_ULP_CLASS_HID_f69f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2134] = { - .class_hid = BNXT_ULP_CLASS_HID_fd5b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2135] = { - .class_hid = BNXT_ULP_CLASS_HID_e17b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2136] = { - .class_hid = BNXT_ULP_CLASS_HID_e727, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2137] = { - .class_hid = BNXT_ULP_CLASS_HID_4ee3f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2138] = { - .class_hid = BNXT_ULP_CLASS_HID_4f4fb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2139] = { - .class_hid = BNXT_ULP_CLASS_HID_4f5d7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2140] = { - .class_hid = BNXT_ULP_CLASS_HID_4fb93, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2141] = { - .class_hid = BNXT_ULP_CLASS_HID_4f243, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2142] = { - .class_hid = BNXT_ULP_CLASS_HID_4f80f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2143] = { - .class_hid = BNXT_ULP_CLASS_HID_4fc2f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2144] = { - .class_hid = BNXT_ULP_CLASS_HID_4e2eb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2145] = { - .class_hid = BNXT_ULP_CLASS_HID_1e90b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2146] = { - .class_hid = BNXT_ULP_CLASS_HID_1ef37, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2147] = { - .class_hid = BNXT_ULP_CLASS_HID_1f3d7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2148] = { - .class_hid = BNXT_ULP_CLASS_HID_1f993, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2149] = { - .class_hid = BNXT_ULP_CLASS_HID_1ec9f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2150] = { - .class_hid = BNXT_ULP_CLASS_HID_1f35b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2151] = { - .class_hid = BNXT_ULP_CLASS_HID_1f77b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2152] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd27, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2153] = { - .class_hid = BNXT_ULP_CLASS_HID_5e43f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2154] = { - .class_hid = BNXT_ULP_CLASS_HID_5eafb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2155] = { - .class_hid = BNXT_ULP_CLASS_HID_5ee9b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2156] = { - .class_hid = BNXT_ULP_CLASS_HID_5f547, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2157] = { - .class_hid = BNXT_ULP_CLASS_HID_5e843, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2158] = { - .class_hid = BNXT_ULP_CLASS_HID_5ee0f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2159] = { - .class_hid = BNXT_ULP_CLASS_HID_5f22f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2160] = { - .class_hid = BNXT_ULP_CLASS_HID_5f8eb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2161] = { - .class_hid = BNXT_ULP_CLASS_HID_2579, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2162] = { - .class_hid = BNXT_ULP_CLASS_HID_2bb5, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2163] = { - .class_hid = BNXT_ULP_CLASS_HID_4591, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2164] = { - .class_hid = BNXT_ULP_CLASS_HID_4bad, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2165] = { - .class_hid = BNXT_ULP_CLASS_HID_2561, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2166] = { - .class_hid = BNXT_ULP_CLASS_HID_2bad, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2167] = { - .class_hid = BNXT_ULP_CLASS_HID_5bdd, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2168] = { - .class_hid = BNXT_ULP_CLASS_HID_054d, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2169] = { - .class_hid = BNXT_ULP_CLASS_HID_257b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2170] = { - .class_hid = BNXT_ULP_CLASS_HID_2bb7, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2171] = { - .class_hid = BNXT_ULP_CLASS_HID_0fd7, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2172] = { - .class_hid = BNXT_ULP_CLASS_HID_1613, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2173] = { - .class_hid = BNXT_ULP_CLASS_HID_48ef, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2174] = { - .class_hid = BNXT_ULP_CLASS_HID_4f2b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2175] = { - .class_hid = BNXT_ULP_CLASS_HID_334b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2176] = { - .class_hid = BNXT_ULP_CLASS_HID_3987, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2177] = { - .class_hid = BNXT_ULP_CLASS_HID_122b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2178] = { - .class_hid = BNXT_ULP_CLASS_HID_1867, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2179] = { - .class_hid = BNXT_ULP_CLASS_HID_5973, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2180] = { - .class_hid = BNXT_ULP_CLASS_HID_02c3, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2181] = { - .class_hid = BNXT_ULP_CLASS_HID_35df, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2182] = { - .class_hid = BNXT_ULP_CLASS_HID_3c1b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2183] = { - .class_hid = BNXT_ULP_CLASS_HID_203b, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2184] = { - .class_hid = BNXT_ULP_CLASS_HID_2677, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2185] = { - .class_hid = BNXT_ULP_CLASS_HID_2563, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2186] = { - .class_hid = BNXT_ULP_CLASS_HID_2baf, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2187] = { - .class_hid = BNXT_ULP_CLASS_HID_0fcf, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2188] = { - .class_hid = BNXT_ULP_CLASS_HID_160b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2189] = { - .class_hid = BNXT_ULP_CLASS_HID_48f7, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2190] = { - .class_hid = BNXT_ULP_CLASS_HID_4f33, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2191] = { - .class_hid = BNXT_ULP_CLASS_HID_3353, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2192] = { - .class_hid = BNXT_ULP_CLASS_HID_399f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2193] = { - .class_hid = BNXT_ULP_CLASS_HID_42097, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2194] = { - .class_hid = BNXT_ULP_CLASS_HID_426d3, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2195] = { - .class_hid = BNXT_ULP_CLASS_HID_40af3, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2196] = { - .class_hid = BNXT_ULP_CLASS_HID_4113f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2197] = { - .class_hid = BNXT_ULP_CLASS_HID_4443b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2198] = { - .class_hid = BNXT_ULP_CLASS_HID_44a67, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2199] = { - .class_hid = BNXT_ULP_CLASS_HID_42e87, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2200] = { - .class_hid = BNXT_ULP_CLASS_HID_434c3, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2201] = { - .class_hid = BNXT_ULP_CLASS_HID_2559, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2202] = { - .class_hid = BNXT_ULP_CLASS_HID_2b95, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2203] = { - .class_hid = BNXT_ULP_CLASS_HID_45b1, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2204] = { - .class_hid = BNXT_ULP_CLASS_HID_4b8d, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2205] = { - .class_hid = BNXT_ULP_CLASS_HID_2541, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2206] = { - .class_hid = BNXT_ULP_CLASS_HID_2b8d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2207] = { - .class_hid = BNXT_ULP_CLASS_HID_5bfd, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2208] = { - .class_hid = BNXT_ULP_CLASS_HID_056d, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2209] = { - .class_hid = BNXT_ULP_CLASS_HID_2539, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2210] = { - .class_hid = BNXT_ULP_CLASS_HID_2bf5, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2211] = { - .class_hid = BNXT_ULP_CLASS_HID_45d1, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2212] = { - .class_hid = BNXT_ULP_CLASS_HID_4bed, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2213] = { - .class_hid = BNXT_ULP_CLASS_HID_2521, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2214] = { - .class_hid = BNXT_ULP_CLASS_HID_2bed, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2215] = { - .class_hid = BNXT_ULP_CLASS_HID_5b9d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2216] = { - .class_hid = BNXT_ULP_CLASS_HID_050d, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2217] = { - .class_hid = BNXT_ULP_CLASS_HID_255b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2218] = { - .class_hid = BNXT_ULP_CLASS_HID_2b97, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2219] = { - .class_hid = BNXT_ULP_CLASS_HID_0ff7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2220] = { - .class_hid = BNXT_ULP_CLASS_HID_1633, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2221] = { - .class_hid = BNXT_ULP_CLASS_HID_48cf, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2222] = { - .class_hid = BNXT_ULP_CLASS_HID_4f0b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2223] = { - .class_hid = BNXT_ULP_CLASS_HID_336b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2224] = { - .class_hid = BNXT_ULP_CLASS_HID_39a7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2225] = { - .class_hid = BNXT_ULP_CLASS_HID_120b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2226] = { - .class_hid = BNXT_ULP_CLASS_HID_1847, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2227] = { - .class_hid = BNXT_ULP_CLASS_HID_5953, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2228] = { - .class_hid = BNXT_ULP_CLASS_HID_02e3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2229] = { - .class_hid = BNXT_ULP_CLASS_HID_35ff, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2230] = { - .class_hid = BNXT_ULP_CLASS_HID_3c3b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2231] = { - .class_hid = BNXT_ULP_CLASS_HID_201b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2232] = { - .class_hid = BNXT_ULP_CLASS_HID_2657, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2233] = { - .class_hid = BNXT_ULP_CLASS_HID_2543, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2234] = { - .class_hid = BNXT_ULP_CLASS_HID_2b8f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2235] = { - .class_hid = BNXT_ULP_CLASS_HID_0fef, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2236] = { - .class_hid = BNXT_ULP_CLASS_HID_162b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2237] = { - .class_hid = BNXT_ULP_CLASS_HID_48d7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2238] = { - .class_hid = BNXT_ULP_CLASS_HID_4f13, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2239] = { - .class_hid = BNXT_ULP_CLASS_HID_3373, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2240] = { - .class_hid = BNXT_ULP_CLASS_HID_39bf, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2241] = { - .class_hid = BNXT_ULP_CLASS_HID_420b7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2242] = { - .class_hid = BNXT_ULP_CLASS_HID_426f3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2243] = { - .class_hid = BNXT_ULP_CLASS_HID_40ad3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2244] = { - .class_hid = BNXT_ULP_CLASS_HID_4111f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2245] = { - .class_hid = BNXT_ULP_CLASS_HID_4441b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2246] = { - .class_hid = BNXT_ULP_CLASS_HID_44a47, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2247] = { - .class_hid = BNXT_ULP_CLASS_HID_42ea7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2248] = { - .class_hid = BNXT_ULP_CLASS_HID_434e3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2249] = { - .class_hid = BNXT_ULP_CLASS_HID_253b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2250] = { - .class_hid = BNXT_ULP_CLASS_HID_2bf7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2251] = { - .class_hid = BNXT_ULP_CLASS_HID_0f97, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2252] = { - .class_hid = BNXT_ULP_CLASS_HID_1653, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2253] = { - .class_hid = BNXT_ULP_CLASS_HID_48af, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2254] = { - .class_hid = BNXT_ULP_CLASS_HID_4f6b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2255] = { - .class_hid = BNXT_ULP_CLASS_HID_330b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2256] = { - .class_hid = BNXT_ULP_CLASS_HID_39c7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2257] = { - .class_hid = BNXT_ULP_CLASS_HID_126b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2258] = { - .class_hid = BNXT_ULP_CLASS_HID_1827, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2259] = { - .class_hid = BNXT_ULP_CLASS_HID_5933, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2260] = { - .class_hid = BNXT_ULP_CLASS_HID_0283, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2261] = { - .class_hid = BNXT_ULP_CLASS_HID_359f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2262] = { - .class_hid = BNXT_ULP_CLASS_HID_3c5b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2263] = { - .class_hid = BNXT_ULP_CLASS_HID_207b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2264] = { - .class_hid = BNXT_ULP_CLASS_HID_2637, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2265] = { - .class_hid = BNXT_ULP_CLASS_HID_2523, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2266] = { - .class_hid = BNXT_ULP_CLASS_HID_2bef, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2267] = { - .class_hid = BNXT_ULP_CLASS_HID_0f8f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2268] = { - .class_hid = BNXT_ULP_CLASS_HID_164b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2269] = { - .class_hid = BNXT_ULP_CLASS_HID_48b7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2270] = { - .class_hid = BNXT_ULP_CLASS_HID_4f73, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2271] = { - .class_hid = BNXT_ULP_CLASS_HID_3313, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2272] = { - .class_hid = BNXT_ULP_CLASS_HID_39df, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2273] = { - .class_hid = BNXT_ULP_CLASS_HID_420d7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2274] = { - .class_hid = BNXT_ULP_CLASS_HID_42693, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2275] = { - .class_hid = BNXT_ULP_CLASS_HID_40ab3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2276] = { - .class_hid = BNXT_ULP_CLASS_HID_4117f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2277] = { - .class_hid = BNXT_ULP_CLASS_HID_4447b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2278] = { - .class_hid = BNXT_ULP_CLASS_HID_44a27, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2279] = { - .class_hid = BNXT_ULP_CLASS_HID_42ec7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2280] = { - .class_hid = BNXT_ULP_CLASS_HID_43483, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2281] = { - .class_hid = BNXT_ULP_CLASS_HID_4156d, - .class_tid = 1, - .hdr_sig_id = 12, - .flow_sig_id = 16384, - .flow_pattern_id = 3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2282] = { - .class_hid = BNXT_ULP_CLASS_HID_41b29, - .class_tid = 1, - .hdr_sig_id = 12, - .flow_sig_id = 16384, - .flow_pattern_id = 3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_12_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2283] = { - .class_hid = BNXT_ULP_CLASS_HID_52b6d, - .class_tid = 1, - .hdr_sig_id = 12, - .flow_sig_id = 81920, - .flow_pattern_id = 3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2284] = { - .class_hid = BNXT_ULP_CLASS_HID_53129, - .class_tid = 1, - .hdr_sig_id = 12, - .flow_sig_id = 81920, - .flow_pattern_id = 3, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_12_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2285] = { - .class_hid = BNXT_ULP_CLASS_HID_478a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2286] = { - .class_hid = BNXT_ULP_CLASS_HID_03a6, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2287] = { - .class_hid = BNXT_ULP_CLASS_HID_4dce, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2288] = { - .class_hid = BNXT_ULP_CLASS_HID_09ea, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2289] = { - .class_hid = BNXT_ULP_CLASS_HID_08fe, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2290] = { - .class_hid = BNXT_ULP_CLASS_HID_23ce, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2291] = { - .class_hid = BNXT_ULP_CLASS_HID_0e02, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2292] = { - .class_hid = BNXT_ULP_CLASS_HID_2912, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2293] = { - .class_hid = BNXT_ULP_CLASS_HID_3e2a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2294] = { - .class_hid = BNXT_ULP_CLASS_HID_593a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2295] = { - .class_hid = BNXT_ULP_CLASS_HID_246e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2296] = { - .class_hid = BNXT_ULP_CLASS_HID_5f7e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2297] = { - .class_hid = BNXT_ULP_CLASS_HID_5e52, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2298] = { - .class_hid = BNXT_ULP_CLASS_HID_1a6e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2299] = { - .class_hid = BNXT_ULP_CLASS_HID_4796, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2300] = { - .class_hid = BNXT_ULP_CLASS_HID_03b2, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2301] = { - .class_hid = BNXT_ULP_CLASS_HID_4163a, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2302] = { - .class_hid = BNXT_ULP_CLASS_HID_4310a, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2303] = { - .class_hid = BNXT_ULP_CLASS_HID_41c7e, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2304] = { - .class_hid = BNXT_ULP_CLASS_HID_4374e, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2305] = { - .class_hid = BNXT_ULP_CLASS_HID_42f8e, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2306] = { - .class_hid = BNXT_ULP_CLASS_HID_4469e, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2307] = { - .class_hid = BNXT_ULP_CLASS_HID_455c2, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2308] = { - .class_hid = BNXT_ULP_CLASS_HID_411ee, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2309] = { - .class_hid = BNXT_ULP_CLASS_HID_44b76, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2310] = { - .class_hid = BNXT_ULP_CLASS_HID_40692, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2311] = { - .class_hid = BNXT_ULP_CLASS_HID_415c6, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2312] = { - .class_hid = BNXT_ULP_CLASS_HID_40cd6, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2313] = { - .class_hid = BNXT_ULP_CLASS_HID_42516, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2314] = { - .class_hid = BNXT_ULP_CLASS_HID_45ce6, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2315] = { - .class_hid = BNXT_ULP_CLASS_HID_42b2a, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2316] = { - .class_hid = BNXT_ULP_CLASS_HID_4423a, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2317] = { - .class_hid = BNXT_ULP_CLASS_HID_229d8, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2318] = { - .class_hid = BNXT_ULP_CLASS_HID_240c8, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2319] = { - .class_hid = BNXT_ULP_CLASS_HID_22f14, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2320] = { - .class_hid = BNXT_ULP_CLASS_HID_24604, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2321] = { - .class_hid = BNXT_ULP_CLASS_HID_23374, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2322] = { - .class_hid = BNXT_ULP_CLASS_HID_22a64, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2323] = { - .class_hid = BNXT_ULP_CLASS_HID_238b0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2324] = { - .class_hid = BNXT_ULP_CLASS_HID_253a0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2325] = { - .class_hid = BNXT_ULP_CLASS_HID_24dac, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2326] = { - .class_hid = BNXT_ULP_CLASS_HID_20990, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2327] = { - .class_hid = BNXT_ULP_CLASS_HID_214dc, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2328] = { - .class_hid = BNXT_ULP_CLASS_HID_20fcc, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2329] = { - .class_hid = BNXT_ULP_CLASS_HID_257c8, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2330] = { - .class_hid = BNXT_ULP_CLASS_HID_2132c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2331] = { - .class_hid = BNXT_ULP_CLASS_HID_25d04, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2332] = { - .class_hid = BNXT_ULP_CLASS_HID_21968, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2333] = { - .class_hid = BNXT_ULP_CLASS_HID_234e8, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2334] = { - .class_hid = BNXT_ULP_CLASS_HID_22f98, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2335] = { - .class_hid = BNXT_ULP_CLASS_HID_23a24, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2336] = { - .class_hid = BNXT_ULP_CLASS_HID_255d4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2337] = { - .class_hid = BNXT_ULP_CLASS_HID_21e04, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2338] = { - .class_hid = BNXT_ULP_CLASS_HID_23934, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2339] = { - .class_hid = BNXT_ULP_CLASS_HID_20440, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2340] = { - .class_hid = BNXT_ULP_CLASS_HID_23f70, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2341] = { - .class_hid = BNXT_ULP_CLASS_HID_2597c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2342] = { - .class_hid = BNXT_ULP_CLASS_HID_214a0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2343] = { - .class_hid = BNXT_ULP_CLASS_HID_25eb8, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2344] = { - .class_hid = BNXT_ULP_CLASS_HID_21a9c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2345] = { - .class_hid = BNXT_ULP_CLASS_HID_22298, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2346] = { - .class_hid = BNXT_ULP_CLASS_HID_25d88, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2347] = { - .class_hid = BNXT_ULP_CLASS_HID_228d4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2348] = { - .class_hid = BNXT_ULP_CLASS_HID_243c4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2349] = { - .class_hid = BNXT_ULP_CLASS_HID_6220c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2350] = { - .class_hid = BNXT_ULP_CLASS_HID_65d3c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2351] = { - .class_hid = BNXT_ULP_CLASS_HID_62848, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2352] = { - .class_hid = BNXT_ULP_CLASS_HID_64378, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2353] = { - .class_hid = BNXT_ULP_CLASS_HID_60fa8, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2354] = { - .class_hid = BNXT_ULP_CLASS_HID_62758, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2355] = { - .class_hid = BNXT_ULP_CLASS_HID_635e4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2356] = { - .class_hid = BNXT_ULP_CLASS_HID_62c94, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2357] = { - .class_hid = BNXT_ULP_CLASS_HID_646e0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2358] = { - .class_hid = BNXT_ULP_CLASS_HID_602c4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2359] = { - .class_hid = BNXT_ULP_CLASS_HID_61110, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2360] = { - .class_hid = BNXT_ULP_CLASS_HID_60800, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2361] = { - .class_hid = BNXT_ULP_CLASS_HID_6503c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2362] = { - .class_hid = BNXT_ULP_CLASS_HID_64b2c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2363] = { - .class_hid = BNXT_ULP_CLASS_HID_65678, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2364] = { - .class_hid = BNXT_ULP_CLASS_HID_6125c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2365] = { - .class_hid = BNXT_ULP_CLASS_HID_631dc, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2366] = { - .class_hid = BNXT_ULP_CLASS_HID_628cc, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2367] = { - .class_hid = BNXT_ULP_CLASS_HID_63718, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2368] = { - .class_hid = BNXT_ULP_CLASS_HID_62e08, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2369] = { - .class_hid = BNXT_ULP_CLASS_HID_61b78, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2370] = { - .class_hid = BNXT_ULP_CLASS_HID_63268, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2371] = { - .class_hid = BNXT_ULP_CLASS_HID_600b4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2372] = { - .class_hid = BNXT_ULP_CLASS_HID_63ba4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2373] = { - .class_hid = BNXT_ULP_CLASS_HID_655b0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2374] = { - .class_hid = BNXT_ULP_CLASS_HID_61194, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2375] = { - .class_hid = BNXT_ULP_CLASS_HID_65bec, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2376] = { - .class_hid = BNXT_ULP_CLASS_HID_617d0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2377] = { - .class_hid = BNXT_ULP_CLASS_HID_63fcc, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2378] = { - .class_hid = BNXT_ULP_CLASS_HID_656fc, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2379] = { - .class_hid = BNXT_ULP_CLASS_HID_62508, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2380] = { - .class_hid = BNXT_ULP_CLASS_HID_65c38, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2381] = { - .class_hid = BNXT_ULP_CLASS_HID_86e0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2382] = { - .class_hid = BNXT_ULP_CLASS_HID_a1f0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2383] = { - .class_hid = BNXT_ULP_CLASS_HID_8c2c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2384] = { - .class_hid = BNXT_ULP_CLASS_HID_a73c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2385] = { - .class_hid = BNXT_ULP_CLASS_HID_904c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2386] = { - .class_hid = BNXT_ULP_CLASS_HID_8b5c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2387] = { - .class_hid = BNXT_ULP_CLASS_HID_9988, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2388] = { - .class_hid = BNXT_ULP_CLASS_HID_b098, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2389] = { - .class_hid = BNXT_ULP_CLASS_HID_aa94, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2390] = { - .class_hid = BNXT_ULP_CLASS_HID_c264, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2391] = { - .class_hid = BNXT_ULP_CLASS_HID_d0d0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2392] = { - .class_hid = BNXT_ULP_CLASS_HID_cba0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2393] = { - .class_hid = BNXT_ULP_CLASS_HID_b4f0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2394] = { - .class_hid = BNXT_ULP_CLASS_HID_afc0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2395] = { - .class_hid = BNXT_ULP_CLASS_HID_ba3c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2396] = { - .class_hid = BNXT_ULP_CLASS_HID_d50c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2397] = { - .class_hid = BNXT_ULP_CLASS_HID_48334, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2398] = { - .class_hid = BNXT_ULP_CLASS_HID_4ba04, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2399] = { - .class_hid = BNXT_ULP_CLASS_HID_48970, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2400] = { - .class_hid = BNXT_ULP_CLASS_HID_4a040, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2401] = { - .class_hid = BNXT_ULP_CLASS_HID_4c84c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2402] = { - .class_hid = BNXT_ULP_CLASS_HID_48460, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2403] = { - .class_hid = BNXT_ULP_CLASS_HID_492dc, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2404] = { - .class_hid = BNXT_ULP_CLASS_HID_48dac, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2405] = { - .class_hid = BNXT_ULP_CLASS_HID_4a7d8, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2406] = { - .class_hid = BNXT_ULP_CLASS_HID_4dea8, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2407] = { - .class_hid = BNXT_ULP_CLASS_HID_4ade4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2408] = { - .class_hid = BNXT_ULP_CLASS_HID_4c4f4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2409] = { - .class_hid = BNXT_ULP_CLASS_HID_4b104, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2410] = { - .class_hid = BNXT_ULP_CLASS_HID_4a814, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2411] = { - .class_hid = BNXT_ULP_CLASS_HID_4b740, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2412] = { - .class_hid = BNXT_ULP_CLASS_HID_4ae50, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2413] = { - .class_hid = BNXT_ULP_CLASS_HID_1bce0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2414] = { - .class_hid = BNXT_ULP_CLASS_HID_1d7f0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2415] = { - .class_hid = BNXT_ULP_CLASS_HID_1a22c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2416] = { - .class_hid = BNXT_ULP_CLASS_HID_1dd3c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2417] = { - .class_hid = BNXT_ULP_CLASS_HID_1864c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2418] = { - .class_hid = BNXT_ULP_CLASS_HID_1a15c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2419] = { - .class_hid = BNXT_ULP_CLASS_HID_18f88, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2420] = { - .class_hid = BNXT_ULP_CLASS_HID_1a698, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2421] = { - .class_hid = BNXT_ULP_CLASS_HID_1c094, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2422] = { - .class_hid = BNXT_ULP_CLASS_HID_19ca8, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2423] = { - .class_hid = BNXT_ULP_CLASS_HID_1c6d0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2424] = { - .class_hid = BNXT_ULP_CLASS_HID_182f4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2425] = { - .class_hid = BNXT_ULP_CLASS_HID_1aaf0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2426] = { - .class_hid = BNXT_ULP_CLASS_HID_1c5c0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2427] = { - .class_hid = BNXT_ULP_CLASS_HID_1d03c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2428] = { - .class_hid = BNXT_ULP_CLASS_HID_1cb0c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2429] = { - .class_hid = BNXT_ULP_CLASS_HID_5b934, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2430] = { - .class_hid = BNXT_ULP_CLASS_HID_5d004, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2431] = { - .class_hid = BNXT_ULP_CLASS_HID_5bf70, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2432] = { - .class_hid = BNXT_ULP_CLASS_HID_5d640, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2433] = { - .class_hid = BNXT_ULP_CLASS_HID_58290, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2434] = { - .class_hid = BNXT_ULP_CLASS_HID_5ba60, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2435] = { - .class_hid = BNXT_ULP_CLASS_HID_588dc, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2436] = { - .class_hid = BNXT_ULP_CLASS_HID_5a3ac, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2437] = { - .class_hid = BNXT_ULP_CLASS_HID_5ddd8, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2438] = { - .class_hid = BNXT_ULP_CLASS_HID_599fc, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2439] = { - .class_hid = BNXT_ULP_CLASS_HID_5c3e4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2440] = { - .class_hid = BNXT_ULP_CLASS_HID_59f38, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2441] = { - .class_hid = BNXT_ULP_CLASS_HID_5a704, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2442] = { - .class_hid = BNXT_ULP_CLASS_HID_5de14, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2443] = { - .class_hid = BNXT_ULP_CLASS_HID_5ad40, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2444] = { - .class_hid = BNXT_ULP_CLASS_HID_5c450, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2445] = { - .class_hid = BNXT_ULP_CLASS_HID_47aa, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2446] = { - .class_hid = BNXT_ULP_CLASS_HID_0386, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2447] = { - .class_hid = BNXT_ULP_CLASS_HID_4dee, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2448] = { - .class_hid = BNXT_ULP_CLASS_HID_09ca, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2449] = { - .class_hid = BNXT_ULP_CLASS_HID_08de, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2450] = { - .class_hid = BNXT_ULP_CLASS_HID_23ee, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2451] = { - .class_hid = BNXT_ULP_CLASS_HID_0e22, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2452] = { - .class_hid = BNXT_ULP_CLASS_HID_2932, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2453] = { - .class_hid = BNXT_ULP_CLASS_HID_3e0a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2454] = { - .class_hid = BNXT_ULP_CLASS_HID_591a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2455] = { - .class_hid = BNXT_ULP_CLASS_HID_244e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2456] = { - .class_hid = BNXT_ULP_CLASS_HID_5f5e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2457] = { - .class_hid = BNXT_ULP_CLASS_HID_5e72, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2458] = { - .class_hid = BNXT_ULP_CLASS_HID_1a4e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2459] = { - .class_hid = BNXT_ULP_CLASS_HID_47b6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2460] = { - .class_hid = BNXT_ULP_CLASS_HID_0392, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2461] = { - .class_hid = BNXT_ULP_CLASS_HID_5dc2, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2462] = { - .class_hid = BNXT_ULP_CLASS_HID_191e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2463] = { - .class_hid = BNXT_ULP_CLASS_HID_4306, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2464] = { - .class_hid = BNXT_ULP_CLASS_HID_1f62, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2465] = { - .class_hid = BNXT_ULP_CLASS_HID_1e76, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2466] = { - .class_hid = BNXT_ULP_CLASS_HID_3906, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2467] = { - .class_hid = BNXT_ULP_CLASS_HID_07ba, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2468] = { - .class_hid = BNXT_ULP_CLASS_HID_3f4a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2469] = { - .class_hid = BNXT_ULP_CLASS_HID_37a2, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2470] = { - .class_hid = BNXT_ULP_CLASS_HID_2eb2, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14340, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2471] = { - .class_hid = BNXT_ULP_CLASS_HID_3de6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2472] = { - .class_hid = BNXT_ULP_CLASS_HID_54f6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14340, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2473] = { - .class_hid = BNXT_ULP_CLASS_HID_578a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2474] = { - .class_hid = BNXT_ULP_CLASS_HID_13e6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14340, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2475] = { - .class_hid = BNXT_ULP_CLASS_HID_5dce, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2476] = { - .class_hid = BNXT_ULP_CLASS_HID_192a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14340, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2477] = { - .class_hid = BNXT_ULP_CLASS_HID_440f6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2478] = { - .class_hid = BNXT_ULP_CLASS_HID_41cd2, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20484, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2479] = { - .class_hid = BNXT_ULP_CLASS_HID_4463a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2480] = { - .class_hid = BNXT_ULP_CLASS_HID_40216, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20484, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2481] = { - .class_hid = BNXT_ULP_CLASS_HID_4052a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2482] = { - .class_hid = BNXT_ULP_CLASS_HID_43c3a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20484, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2483] = { - .class_hid = BNXT_ULP_CLASS_HID_40b6e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2484] = { - .class_hid = BNXT_ULP_CLASS_HID_4227e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20484, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2485] = { - .class_hid = BNXT_ULP_CLASS_HID_43b56, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2486] = { - .class_hid = BNXT_ULP_CLASS_HID_45266, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22532, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2487] = { - .class_hid = BNXT_ULP_CLASS_HID_4209a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2488] = { - .class_hid = BNXT_ULP_CLASS_HID_45baa, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22532, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2489] = { - .class_hid = BNXT_ULP_CLASS_HID_45abe, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2490] = { - .class_hid = BNXT_ULP_CLASS_HID_4169a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22532, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2491] = { - .class_hid = BNXT_ULP_CLASS_HID_44082, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2492] = { - .class_hid = BNXT_ULP_CLASS_HID_41cde, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22532, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2493] = { - .class_hid = BNXT_ULP_CLASS_HID_4560e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2494] = { - .class_hid = BNXT_ULP_CLASS_HID_4126a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2495] = { - .class_hid = BNXT_ULP_CLASS_HID_45c52, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2496] = { - .class_hid = BNXT_ULP_CLASS_HID_41bae, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2497] = { - .class_hid = BNXT_ULP_CLASS_HID_41b42, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2498] = { - .class_hid = BNXT_ULP_CLASS_HID_43252, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2499] = { - .class_hid = BNXT_ULP_CLASS_HID_40086, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2500] = { - .class_hid = BNXT_ULP_CLASS_HID_43b96, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2501] = { - .class_hid = BNXT_ULP_CLASS_HID_430ee, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2502] = { - .class_hid = BNXT_ULP_CLASS_HID_42bfe, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30724, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2503] = { - .class_hid = BNXT_ULP_CLASS_HID_43632, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2504] = { - .class_hid = BNXT_ULP_CLASS_HID_451c2, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30724, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2505] = { - .class_hid = BNXT_ULP_CLASS_HID_450d6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2506] = { - .class_hid = BNXT_ULP_CLASS_HID_44be6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30724, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2507] = { - .class_hid = BNXT_ULP_CLASS_HID_4561a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2508] = { - .class_hid = BNXT_ULP_CLASS_HID_41276, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30724, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2509] = { - .class_hid = BNXT_ULP_CLASS_HID_4161a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2510] = { - .class_hid = BNXT_ULP_CLASS_HID_4312a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2511] = { - .class_hid = BNXT_ULP_CLASS_HID_41c5e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2512] = { - .class_hid = BNXT_ULP_CLASS_HID_4376e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2513] = { - .class_hid = BNXT_ULP_CLASS_HID_42fae, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2514] = { - .class_hid = BNXT_ULP_CLASS_HID_446be, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2515] = { - .class_hid = BNXT_ULP_CLASS_HID_455e2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2516] = { - .class_hid = BNXT_ULP_CLASS_HID_411ce, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2517] = { - .class_hid = BNXT_ULP_CLASS_HID_44b56, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2518] = { - .class_hid = BNXT_ULP_CLASS_HID_406b2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2519] = { - .class_hid = BNXT_ULP_CLASS_HID_415e6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2520] = { - .class_hid = BNXT_ULP_CLASS_HID_40cf6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2521] = { - .class_hid = BNXT_ULP_CLASS_HID_42536, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2522] = { - .class_hid = BNXT_ULP_CLASS_HID_45cc6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2523] = { - .class_hid = BNXT_ULP_CLASS_HID_42b0a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2524] = { - .class_hid = BNXT_ULP_CLASS_HID_4421a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2525] = { - .class_hid = BNXT_ULP_CLASS_HID_6221a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2526] = { - .class_hid = BNXT_ULP_CLASS_HID_65d2a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2527] = { - .class_hid = BNXT_ULP_CLASS_HID_6285e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2528] = { - .class_hid = BNXT_ULP_CLASS_HID_6436e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2529] = { - .class_hid = BNXT_ULP_CLASS_HID_61cfa, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2530] = { - .class_hid = BNXT_ULP_CLASS_HID_6378a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2531] = { - .class_hid = BNXT_ULP_CLASS_HID_6023e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2532] = { - .class_hid = BNXT_ULP_CLASS_HID_63dce, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2533] = { - .class_hid = BNXT_ULP_CLASS_HID_63ba2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2534] = { - .class_hid = BNXT_ULP_CLASS_HID_652b2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57348, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2535] = { - .class_hid = BNXT_ULP_CLASS_HID_621e6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2536] = { - .class_hid = BNXT_ULP_CLASS_HID_658f6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57348, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2537] = { - .class_hid = BNXT_ULP_CLASS_HID_61202, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2538] = { - .class_hid = BNXT_ULP_CLASS_HID_60d12, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57348, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2539] = { - .class_hid = BNXT_ULP_CLASS_HID_61846, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2540] = { - .class_hid = BNXT_ULP_CLASS_HID_63356, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57348, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2541] = { - .class_hid = BNXT_ULP_CLASS_HID_50c1a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2542] = { - .class_hid = BNXT_ULP_CLASS_HID_5272a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81924, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2543] = { - .class_hid = BNXT_ULP_CLASS_HID_5325e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2544] = { - .class_hid = BNXT_ULP_CLASS_HID_52d6e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81924, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2545] = { - .class_hid = BNXT_ULP_CLASS_HID_545ae, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2546] = { - .class_hid = BNXT_ULP_CLASS_HID_5018a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81924, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2547] = { - .class_hid = BNXT_ULP_CLASS_HID_54be2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2548] = { - .class_hid = BNXT_ULP_CLASS_HID_507ce, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81924, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2549] = { - .class_hid = BNXT_ULP_CLASS_HID_505a2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2550] = { - .class_hid = BNXT_ULP_CLASS_HID_53cb2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90116, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2551] = { - .class_hid = BNXT_ULP_CLASS_HID_50be6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2552] = { - .class_hid = BNXT_ULP_CLASS_HID_522f6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90116, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2553] = { - .class_hid = BNXT_ULP_CLASS_HID_55b36, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2554] = { - .class_hid = BNXT_ULP_CLASS_HID_51712, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90116, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2555] = { - .class_hid = BNXT_ULP_CLASS_HID_5410a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2556] = { - .class_hid = BNXT_ULP_CLASS_HID_51d56, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90116, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2557] = { - .class_hid = BNXT_ULP_CLASS_HID_7581a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2558] = { - .class_hid = BNXT_ULP_CLASS_HID_71466, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2559] = { - .class_hid = BNXT_ULP_CLASS_HID_75e5e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2560] = { - .class_hid = BNXT_ULP_CLASS_HID_71dba, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2561] = { - .class_hid = BNXT_ULP_CLASS_HID_732fa, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2562] = { - .class_hid = BNXT_ULP_CLASS_HID_72d8a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2563] = { - .class_hid = BNXT_ULP_CLASS_HID_7383e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2564] = { - .class_hid = BNXT_ULP_CLASS_HID_753ce, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2565] = { - .class_hid = BNXT_ULP_CLASS_HID_751a2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2566] = { - .class_hid = BNXT_ULP_CLASS_HID_748b2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122884, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2567] = { - .class_hid = BNXT_ULP_CLASS_HID_757e6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2568] = { - .class_hid = BNXT_ULP_CLASS_HID_713c2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122884, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2569] = { - .class_hid = BNXT_ULP_CLASS_HID_70802, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2570] = { - .class_hid = BNXT_ULP_CLASS_HID_72312, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122884, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2571] = { - .class_hid = BNXT_ULP_CLASS_HID_70e46, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2572] = { - .class_hid = BNXT_ULP_CLASS_HID_72956, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122884, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2573] = { - .class_hid = BNXT_ULP_CLASS_HID_47ca, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2574] = { - .class_hid = BNXT_ULP_CLASS_HID_03e6, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2575] = { - .class_hid = BNXT_ULP_CLASS_HID_4d8e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2576] = { - .class_hid = BNXT_ULP_CLASS_HID_09aa, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2577] = { - .class_hid = BNXT_ULP_CLASS_HID_08be, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2578] = { - .class_hid = BNXT_ULP_CLASS_HID_238e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2579] = { - .class_hid = BNXT_ULP_CLASS_HID_0e42, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2580] = { - .class_hid = BNXT_ULP_CLASS_HID_2952, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4100, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2581] = { - .class_hid = BNXT_ULP_CLASS_HID_3e6a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2582] = { - .class_hid = BNXT_ULP_CLASS_HID_597a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2583] = { - .class_hid = BNXT_ULP_CLASS_HID_242e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2584] = { - .class_hid = BNXT_ULP_CLASS_HID_5f3e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2585] = { - .class_hid = BNXT_ULP_CLASS_HID_5e12, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2586] = { - .class_hid = BNXT_ULP_CLASS_HID_1a2e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2587] = { - .class_hid = BNXT_ULP_CLASS_HID_47d6, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2588] = { - .class_hid = BNXT_ULP_CLASS_HID_03f2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6148, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2589] = { - .class_hid = BNXT_ULP_CLASS_HID_5da2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2590] = { - .class_hid = BNXT_ULP_CLASS_HID_197e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2591] = { - .class_hid = BNXT_ULP_CLASS_HID_4366, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2592] = { - .class_hid = BNXT_ULP_CLASS_HID_1f02, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2593] = { - .class_hid = BNXT_ULP_CLASS_HID_1e16, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2594] = { - .class_hid = BNXT_ULP_CLASS_HID_3966, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2595] = { - .class_hid = BNXT_ULP_CLASS_HID_07da, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2596] = { - .class_hid = BNXT_ULP_CLASS_HID_3f2a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2597] = { - .class_hid = BNXT_ULP_CLASS_HID_37c2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2598] = { - .class_hid = BNXT_ULP_CLASS_HID_2ed2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14340, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2599] = { - .class_hid = BNXT_ULP_CLASS_HID_3d86, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2600] = { - .class_hid = BNXT_ULP_CLASS_HID_5496, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14340, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2601] = { - .class_hid = BNXT_ULP_CLASS_HID_57ea, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2602] = { - .class_hid = BNXT_ULP_CLASS_HID_1386, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14340, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2603] = { - .class_hid = BNXT_ULP_CLASS_HID_5dae, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2604] = { - .class_hid = BNXT_ULP_CLASS_HID_194a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14340, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2605] = { - .class_hid = BNXT_ULP_CLASS_HID_44096, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2606] = { - .class_hid = BNXT_ULP_CLASS_HID_41cb2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20484, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2607] = { - .class_hid = BNXT_ULP_CLASS_HID_4465a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2608] = { - .class_hid = BNXT_ULP_CLASS_HID_40276, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20484, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2609] = { - .class_hid = BNXT_ULP_CLASS_HID_4054a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2610] = { - .class_hid = BNXT_ULP_CLASS_HID_43c5a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20484, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2611] = { - .class_hid = BNXT_ULP_CLASS_HID_40b0e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2612] = { - .class_hid = BNXT_ULP_CLASS_HID_4221e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20484, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2613] = { - .class_hid = BNXT_ULP_CLASS_HID_43b36, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2614] = { - .class_hid = BNXT_ULP_CLASS_HID_45206, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22532, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2615] = { - .class_hid = BNXT_ULP_CLASS_HID_420fa, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2616] = { - .class_hid = BNXT_ULP_CLASS_HID_45bca, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22532, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2617] = { - .class_hid = BNXT_ULP_CLASS_HID_45ade, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2618] = { - .class_hid = BNXT_ULP_CLASS_HID_416fa, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22532, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2619] = { - .class_hid = BNXT_ULP_CLASS_HID_440e2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2620] = { - .class_hid = BNXT_ULP_CLASS_HID_41cbe, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22532, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2621] = { - .class_hid = BNXT_ULP_CLASS_HID_4566e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2622] = { - .class_hid = BNXT_ULP_CLASS_HID_4120a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2623] = { - .class_hid = BNXT_ULP_CLASS_HID_45c32, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2624] = { - .class_hid = BNXT_ULP_CLASS_HID_41bce, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2625] = { - .class_hid = BNXT_ULP_CLASS_HID_41b22, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2626] = { - .class_hid = BNXT_ULP_CLASS_HID_43232, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2627] = { - .class_hid = BNXT_ULP_CLASS_HID_400e6, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2628] = { - .class_hid = BNXT_ULP_CLASS_HID_43bf6, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2629] = { - .class_hid = BNXT_ULP_CLASS_HID_4308e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2630] = { - .class_hid = BNXT_ULP_CLASS_HID_42b9e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30724, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2631] = { - .class_hid = BNXT_ULP_CLASS_HID_43652, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2632] = { - .class_hid = BNXT_ULP_CLASS_HID_451a2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30724, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2633] = { - .class_hid = BNXT_ULP_CLASS_HID_450b6, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2634] = { - .class_hid = BNXT_ULP_CLASS_HID_44b86, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30724, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2635] = { - .class_hid = BNXT_ULP_CLASS_HID_4567a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2636] = { - .class_hid = BNXT_ULP_CLASS_HID_41216, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30724, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2637] = { - .class_hid = BNXT_ULP_CLASS_HID_4167a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2638] = { - .class_hid = BNXT_ULP_CLASS_HID_4314a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2639] = { - .class_hid = BNXT_ULP_CLASS_HID_41c3e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2640] = { - .class_hid = BNXT_ULP_CLASS_HID_4370e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2641] = { - .class_hid = BNXT_ULP_CLASS_HID_42fce, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2642] = { - .class_hid = BNXT_ULP_CLASS_HID_446de, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2643] = { - .class_hid = BNXT_ULP_CLASS_HID_45582, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2644] = { - .class_hid = BNXT_ULP_CLASS_HID_411ae, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16388, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2645] = { - .class_hid = BNXT_ULP_CLASS_HID_44b36, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2646] = { - .class_hid = BNXT_ULP_CLASS_HID_406d2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2647] = { - .class_hid = BNXT_ULP_CLASS_HID_41586, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2648] = { - .class_hid = BNXT_ULP_CLASS_HID_40c96, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2649] = { - .class_hid = BNXT_ULP_CLASS_HID_42556, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2650] = { - .class_hid = BNXT_ULP_CLASS_HID_45ca6, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2651] = { - .class_hid = BNXT_ULP_CLASS_HID_42b6a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2652] = { - .class_hid = BNXT_ULP_CLASS_HID_4427a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24580, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2653] = { - .class_hid = BNXT_ULP_CLASS_HID_6227a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2654] = { - .class_hid = BNXT_ULP_CLASS_HID_65d4a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2655] = { - .class_hid = BNXT_ULP_CLASS_HID_6283e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2656] = { - .class_hid = BNXT_ULP_CLASS_HID_6430e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2657] = { - .class_hid = BNXT_ULP_CLASS_HID_61c9a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2658] = { - .class_hid = BNXT_ULP_CLASS_HID_637ea, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2659] = { - .class_hid = BNXT_ULP_CLASS_HID_6025e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2660] = { - .class_hid = BNXT_ULP_CLASS_HID_63dae, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2661] = { - .class_hid = BNXT_ULP_CLASS_HID_63bc2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2662] = { - .class_hid = BNXT_ULP_CLASS_HID_652d2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57348, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2663] = { - .class_hid = BNXT_ULP_CLASS_HID_62186, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2664] = { - .class_hid = BNXT_ULP_CLASS_HID_65896, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57348, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2665] = { - .class_hid = BNXT_ULP_CLASS_HID_61262, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2666] = { - .class_hid = BNXT_ULP_CLASS_HID_60d72, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57348, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2667] = { - .class_hid = BNXT_ULP_CLASS_HID_61826, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2668] = { - .class_hid = BNXT_ULP_CLASS_HID_63336, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57348, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2669] = { - .class_hid = BNXT_ULP_CLASS_HID_50c7a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2670] = { - .class_hid = BNXT_ULP_CLASS_HID_5274a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81924, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2671] = { - .class_hid = BNXT_ULP_CLASS_HID_5323e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2672] = { - .class_hid = BNXT_ULP_CLASS_HID_52d0e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81924, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2673] = { - .class_hid = BNXT_ULP_CLASS_HID_545ce, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2674] = { - .class_hid = BNXT_ULP_CLASS_HID_501ea, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81924, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2675] = { - .class_hid = BNXT_ULP_CLASS_HID_54b82, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2676] = { - .class_hid = BNXT_ULP_CLASS_HID_507ae, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81924, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2677] = { - .class_hid = BNXT_ULP_CLASS_HID_505c2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2678] = { - .class_hid = BNXT_ULP_CLASS_HID_53cd2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90116, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2679] = { - .class_hid = BNXT_ULP_CLASS_HID_50b86, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2680] = { - .class_hid = BNXT_ULP_CLASS_HID_52296, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90116, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2681] = { - .class_hid = BNXT_ULP_CLASS_HID_55b56, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2682] = { - .class_hid = BNXT_ULP_CLASS_HID_51772, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90116, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2683] = { - .class_hid = BNXT_ULP_CLASS_HID_5416a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2684] = { - .class_hid = BNXT_ULP_CLASS_HID_51d36, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90116, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2685] = { - .class_hid = BNXT_ULP_CLASS_HID_7587a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2686] = { - .class_hid = BNXT_ULP_CLASS_HID_71406, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2687] = { - .class_hid = BNXT_ULP_CLASS_HID_75e3e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2688] = { - .class_hid = BNXT_ULP_CLASS_HID_71dda, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2689] = { - .class_hid = BNXT_ULP_CLASS_HID_7329a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2690] = { - .class_hid = BNXT_ULP_CLASS_HID_72dea, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2691] = { - .class_hid = BNXT_ULP_CLASS_HID_7385e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2692] = { - .class_hid = BNXT_ULP_CLASS_HID_753ae, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2693] = { - .class_hid = BNXT_ULP_CLASS_HID_751c2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2694] = { - .class_hid = BNXT_ULP_CLASS_HID_748d2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122884, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2695] = { - .class_hid = BNXT_ULP_CLASS_HID_75786, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2696] = { - .class_hid = BNXT_ULP_CLASS_HID_713a2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122884, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2697] = { - .class_hid = BNXT_ULP_CLASS_HID_70862, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2698] = { - .class_hid = BNXT_ULP_CLASS_HID_72372, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122884, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2699] = { - .class_hid = BNXT_ULP_CLASS_HID_70e26, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2700] = { - .class_hid = BNXT_ULP_CLASS_HID_72936, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122884, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2701] = { - .class_hid = BNXT_ULP_CLASS_HID_229b8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2702] = { - .class_hid = BNXT_ULP_CLASS_HID_240a8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2703] = { - .class_hid = BNXT_ULP_CLASS_HID_22f74, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2704] = { - .class_hid = BNXT_ULP_CLASS_HID_24664, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2705] = { - .class_hid = BNXT_ULP_CLASS_HID_23314, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2706] = { - .class_hid = BNXT_ULP_CLASS_HID_22a04, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2707] = { - .class_hid = BNXT_ULP_CLASS_HID_238d0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2708] = { - .class_hid = BNXT_ULP_CLASS_HID_253c0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2709] = { - .class_hid = BNXT_ULP_CLASS_HID_24dcc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2710] = { - .class_hid = BNXT_ULP_CLASS_HID_209f0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2711] = { - .class_hid = BNXT_ULP_CLASS_HID_214bc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2712] = { - .class_hid = BNXT_ULP_CLASS_HID_20fac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2713] = { - .class_hid = BNXT_ULP_CLASS_HID_257a8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2714] = { - .class_hid = BNXT_ULP_CLASS_HID_2134c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2715] = { - .class_hid = BNXT_ULP_CLASS_HID_25d64, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2716] = { - .class_hid = BNXT_ULP_CLASS_HID_21908, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2717] = { - .class_hid = BNXT_ULP_CLASS_HID_23488, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2718] = { - .class_hid = BNXT_ULP_CLASS_HID_22ff8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2719] = { - .class_hid = BNXT_ULP_CLASS_HID_23a44, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2720] = { - .class_hid = BNXT_ULP_CLASS_HID_255b4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2721] = { - .class_hid = BNXT_ULP_CLASS_HID_21e64, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2722] = { - .class_hid = BNXT_ULP_CLASS_HID_23954, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2723] = { - .class_hid = BNXT_ULP_CLASS_HID_20420, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2724] = { - .class_hid = BNXT_ULP_CLASS_HID_23f10, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2725] = { - .class_hid = BNXT_ULP_CLASS_HID_2591c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2726] = { - .class_hid = BNXT_ULP_CLASS_HID_214c0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2727] = { - .class_hid = BNXT_ULP_CLASS_HID_25ed8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2728] = { - .class_hid = BNXT_ULP_CLASS_HID_21afc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2729] = { - .class_hid = BNXT_ULP_CLASS_HID_222f8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2730] = { - .class_hid = BNXT_ULP_CLASS_HID_25de8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2731] = { - .class_hid = BNXT_ULP_CLASS_HID_228b4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2732] = { - .class_hid = BNXT_ULP_CLASS_HID_243a4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2733] = { - .class_hid = BNXT_ULP_CLASS_HID_6226c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2734] = { - .class_hid = BNXT_ULP_CLASS_HID_65d5c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2735] = { - .class_hid = BNXT_ULP_CLASS_HID_62828, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2736] = { - .class_hid = BNXT_ULP_CLASS_HID_64318, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2737] = { - .class_hid = BNXT_ULP_CLASS_HID_60fc8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2738] = { - .class_hid = BNXT_ULP_CLASS_HID_62738, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2739] = { - .class_hid = BNXT_ULP_CLASS_HID_63584, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2740] = { - .class_hid = BNXT_ULP_CLASS_HID_62cf4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2741] = { - .class_hid = BNXT_ULP_CLASS_HID_64680, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2742] = { - .class_hid = BNXT_ULP_CLASS_HID_602a4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2743] = { - .class_hid = BNXT_ULP_CLASS_HID_61170, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2744] = { - .class_hid = BNXT_ULP_CLASS_HID_60860, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2745] = { - .class_hid = BNXT_ULP_CLASS_HID_6505c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2746] = { - .class_hid = BNXT_ULP_CLASS_HID_64b4c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2747] = { - .class_hid = BNXT_ULP_CLASS_HID_65618, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2748] = { - .class_hid = BNXT_ULP_CLASS_HID_6123c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2749] = { - .class_hid = BNXT_ULP_CLASS_HID_631bc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2750] = { - .class_hid = BNXT_ULP_CLASS_HID_628ac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2751] = { - .class_hid = BNXT_ULP_CLASS_HID_63778, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2752] = { - .class_hid = BNXT_ULP_CLASS_HID_62e68, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2753] = { - .class_hid = BNXT_ULP_CLASS_HID_61b18, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2754] = { - .class_hid = BNXT_ULP_CLASS_HID_63208, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2755] = { - .class_hid = BNXT_ULP_CLASS_HID_600d4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2756] = { - .class_hid = BNXT_ULP_CLASS_HID_63bc4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2757] = { - .class_hid = BNXT_ULP_CLASS_HID_655d0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2758] = { - .class_hid = BNXT_ULP_CLASS_HID_611f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2759] = { - .class_hid = BNXT_ULP_CLASS_HID_65b8c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2760] = { - .class_hid = BNXT_ULP_CLASS_HID_617b0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2761] = { - .class_hid = BNXT_ULP_CLASS_HID_63fac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2762] = { - .class_hid = BNXT_ULP_CLASS_HID_6569c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2763] = { - .class_hid = BNXT_ULP_CLASS_HID_62568, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2764] = { - .class_hid = BNXT_ULP_CLASS_HID_65c58, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2765] = { - .class_hid = BNXT_ULP_CLASS_HID_35fb8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2766] = { - .class_hid = BNXT_ULP_CLASS_HID_31b5c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2767] = { - .class_hid = BNXT_ULP_CLASS_HID_34574, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2768] = { - .class_hid = BNXT_ULP_CLASS_HID_30118, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2769] = { - .class_hid = BNXT_ULP_CLASS_HID_32914, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2770] = { - .class_hid = BNXT_ULP_CLASS_HID_34004, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2771] = { - .class_hid = BNXT_ULP_CLASS_HID_32ed0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2772] = { - .class_hid = BNXT_ULP_CLASS_HID_349c0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2773] = { - .class_hid = BNXT_ULP_CLASS_HID_30480, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2774] = { - .class_hid = BNXT_ULP_CLASS_HID_33ff0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2775] = { - .class_hid = BNXT_ULP_CLASS_HID_30abc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2776] = { - .class_hid = BNXT_ULP_CLASS_HID_325ac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2777] = { - .class_hid = BNXT_ULP_CLASS_HID_34da8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2778] = { - .class_hid = BNXT_ULP_CLASS_HID_3094c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2779] = { - .class_hid = BNXT_ULP_CLASS_HID_31418, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2780] = { - .class_hid = BNXT_ULP_CLASS_HID_30f08, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2781] = { - .class_hid = BNXT_ULP_CLASS_HID_32a88, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2782] = { - .class_hid = BNXT_ULP_CLASS_HID_345f8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2783] = { - .class_hid = BNXT_ULP_CLASS_HID_35044, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2784] = { - .class_hid = BNXT_ULP_CLASS_HID_34bb4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2785] = { - .class_hid = BNXT_ULP_CLASS_HID_33464, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2786] = { - .class_hid = BNXT_ULP_CLASS_HID_32f54, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2787] = { - .class_hid = BNXT_ULP_CLASS_HID_33a20, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2788] = { - .class_hid = BNXT_ULP_CLASS_HID_35510, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2789] = { - .class_hid = BNXT_ULP_CLASS_HID_313d0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2790] = { - .class_hid = BNXT_ULP_CLASS_HID_30ac0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2791] = { - .class_hid = BNXT_ULP_CLASS_HID_3198c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2792] = { - .class_hid = BNXT_ULP_CLASS_HID_330fc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2793] = { - .class_hid = BNXT_ULP_CLASS_HID_358f8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2794] = { - .class_hid = BNXT_ULP_CLASS_HID_3149c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2795] = { - .class_hid = BNXT_ULP_CLASS_HID_35eb4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2796] = { - .class_hid = BNXT_ULP_CLASS_HID_31a58, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2797] = { - .class_hid = BNXT_ULP_CLASS_HID_7586c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2798] = { - .class_hid = BNXT_ULP_CLASS_HID_71410, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2799] = { - .class_hid = BNXT_ULP_CLASS_HID_75e28, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2800] = { - .class_hid = BNXT_ULP_CLASS_HID_71dcc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2801] = { - .class_hid = BNXT_ULP_CLASS_HID_725c8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2802] = { - .class_hid = BNXT_ULP_CLASS_HID_75d38, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2803] = { - .class_hid = BNXT_ULP_CLASS_HID_72b84, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2804] = { - .class_hid = BNXT_ULP_CLASS_HID_742f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2805] = { - .class_hid = BNXT_ULP_CLASS_HID_701b4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2806] = { - .class_hid = BNXT_ULP_CLASS_HID_738a4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2807] = { - .class_hid = BNXT_ULP_CLASS_HID_70770, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2808] = { - .class_hid = BNXT_ULP_CLASS_HID_73e60, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2809] = { - .class_hid = BNXT_ULP_CLASS_HID_7465c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2810] = { - .class_hid = BNXT_ULP_CLASS_HID_70200, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2811] = { - .class_hid = BNXT_ULP_CLASS_HID_710cc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2812] = { - .class_hid = BNXT_ULP_CLASS_HID_7083c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2813] = { - .class_hid = BNXT_ULP_CLASS_HID_727bc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2814] = { - .class_hid = BNXT_ULP_CLASS_HID_75eac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2815] = { - .class_hid = BNXT_ULP_CLASS_HID_72d78, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2816] = { - .class_hid = BNXT_ULP_CLASS_HID_74468, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2817] = { - .class_hid = BNXT_ULP_CLASS_HID_73118, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2818] = { - .class_hid = BNXT_ULP_CLASS_HID_72808, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2819] = { - .class_hid = BNXT_ULP_CLASS_HID_736d4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2820] = { - .class_hid = BNXT_ULP_CLASS_HID_751c4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2821] = { - .class_hid = BNXT_ULP_CLASS_HID_74bd0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2822] = { - .class_hid = BNXT_ULP_CLASS_HID_707f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2823] = { - .class_hid = BNXT_ULP_CLASS_HID_71240, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2824] = { - .class_hid = BNXT_ULP_CLASS_HID_70db0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2825] = { - .class_hid = BNXT_ULP_CLASS_HID_755ac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2826] = { - .class_hid = BNXT_ULP_CLASS_HID_71150, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2827] = { - .class_hid = BNXT_ULP_CLASS_HID_75b68, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2828] = { - .class_hid = BNXT_ULP_CLASS_HID_7170c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2829] = { - .class_hid = BNXT_ULP_CLASS_HID_2d2b8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2830] = { - .class_hid = BNXT_ULP_CLASS_HID_2cda8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2831] = { - .class_hid = BNXT_ULP_CLASS_HID_2d874, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2832] = { - .class_hid = BNXT_ULP_CLASS_HID_29418, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2833] = { - .class_hid = BNXT_ULP_CLASS_HID_2bc14, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2834] = { - .class_hid = BNXT_ULP_CLASS_HID_2d704, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2835] = { - .class_hid = BNXT_ULP_CLASS_HID_2a5d0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2836] = { - .class_hid = BNXT_ULP_CLASS_HID_2dcc0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2837] = { - .class_hid = BNXT_ULP_CLASS_HID_29b80, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2838] = { - .class_hid = BNXT_ULP_CLASS_HID_2b2f0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2839] = { - .class_hid = BNXT_ULP_CLASS_HID_281bc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2840] = { - .class_hid = BNXT_ULP_CLASS_HID_2b8ac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2841] = { - .class_hid = BNXT_ULP_CLASS_HID_2c0a8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2842] = { - .class_hid = BNXT_ULP_CLASS_HID_29c4c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2843] = { - .class_hid = BNXT_ULP_CLASS_HID_2c664, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2844] = { - .class_hid = BNXT_ULP_CLASS_HID_28208, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2845] = { - .class_hid = BNXT_ULP_CLASS_HID_2a188, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2846] = { - .class_hid = BNXT_ULP_CLASS_HID_2d8f8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2847] = { - .class_hid = BNXT_ULP_CLASS_HID_2a744, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2848] = { - .class_hid = BNXT_ULP_CLASS_HID_2deb4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2849] = { - .class_hid = BNXT_ULP_CLASS_HID_28b64, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2850] = { - .class_hid = BNXT_ULP_CLASS_HID_2a254, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2851] = { - .class_hid = BNXT_ULP_CLASS_HID_2b120, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2852] = { - .class_hid = BNXT_ULP_CLASS_HID_2a810, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2853] = { - .class_hid = BNXT_ULP_CLASS_HID_2c21c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2854] = { - .class_hid = BNXT_ULP_CLASS_HID_281c0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2855] = { - .class_hid = BNXT_ULP_CLASS_HID_2cbd8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2856] = { - .class_hid = BNXT_ULP_CLASS_HID_287fc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2857] = { - .class_hid = BNXT_ULP_CLASS_HID_2aff8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2858] = { - .class_hid = BNXT_ULP_CLASS_HID_2c6e8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2859] = { - .class_hid = BNXT_ULP_CLASS_HID_2d5b4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2860] = { - .class_hid = BNXT_ULP_CLASS_HID_29158, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2861] = { - .class_hid = BNXT_ULP_CLASS_HID_6af6c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2862] = { - .class_hid = BNXT_ULP_CLASS_HID_6c65c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2863] = { - .class_hid = BNXT_ULP_CLASS_HID_6d528, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2864] = { - .class_hid = BNXT_ULP_CLASS_HID_690cc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2865] = { - .class_hid = BNXT_ULP_CLASS_HID_6b8c8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2866] = { - .class_hid = BNXT_ULP_CLASS_HID_6d038, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2867] = { - .class_hid = BNXT_ULP_CLASS_HID_6be84, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2868] = { - .class_hid = BNXT_ULP_CLASS_HID_6d9f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2869] = { - .class_hid = BNXT_ULP_CLASS_HID_694b4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2870] = { - .class_hid = BNXT_ULP_CLASS_HID_68fa4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2871] = { - .class_hid = BNXT_ULP_CLASS_HID_69a70, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2872] = { - .class_hid = BNXT_ULP_CLASS_HID_6b560, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2873] = { - .class_hid = BNXT_ULP_CLASS_HID_6dd5c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2874] = { - .class_hid = BNXT_ULP_CLASS_HID_69900, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2875] = { - .class_hid = BNXT_ULP_CLASS_HID_6c318, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2876] = { - .class_hid = BNXT_ULP_CLASS_HID_69f3c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2877] = { - .class_hid = BNXT_ULP_CLASS_HID_6babc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2878] = { - .class_hid = BNXT_ULP_CLASS_HID_6d5ac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2879] = { - .class_hid = BNXT_ULP_CLASS_HID_6a078, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2880] = { - .class_hid = BNXT_ULP_CLASS_HID_6db68, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2881] = { - .class_hid = BNXT_ULP_CLASS_HID_68418, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2882] = { - .class_hid = BNXT_ULP_CLASS_HID_6bf08, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2883] = { - .class_hid = BNXT_ULP_CLASS_HID_68dd4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2884] = { - .class_hid = BNXT_ULP_CLASS_HID_6a4c4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2885] = { - .class_hid = BNXT_ULP_CLASS_HID_6ded0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2886] = { - .class_hid = BNXT_ULP_CLASS_HID_69af4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2887] = { - .class_hid = BNXT_ULP_CLASS_HID_6c48c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2888] = { - .class_hid = BNXT_ULP_CLASS_HID_680b0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2889] = { - .class_hid = BNXT_ULP_CLASS_HID_6a8ac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2890] = { - .class_hid = BNXT_ULP_CLASS_HID_6c39c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2891] = { - .class_hid = BNXT_ULP_CLASS_HID_6ae68, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2892] = { - .class_hid = BNXT_ULP_CLASS_HID_6c958, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2893] = { - .class_hid = BNXT_ULP_CLASS_HID_3c8b8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2894] = { - .class_hid = BNXT_ULP_CLASS_HID_3845c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2895] = { - .class_hid = BNXT_ULP_CLASS_HID_39328, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2896] = { - .class_hid = BNXT_ULP_CLASS_HID_38a18, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2897] = { - .class_hid = BNXT_ULP_CLASS_HID_3d214, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2898] = { - .class_hid = BNXT_ULP_CLASS_HID_3cd04, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2899] = { - .class_hid = BNXT_ULP_CLASS_HID_3dbd0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2900] = { - .class_hid = BNXT_ULP_CLASS_HID_397f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2901] = { - .class_hid = BNXT_ULP_CLASS_HID_3b180, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2902] = { - .class_hid = BNXT_ULP_CLASS_HID_3a8f0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2903] = { - .class_hid = BNXT_ULP_CLASS_HID_3b7bc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2904] = { - .class_hid = BNXT_ULP_CLASS_HID_3aeac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2905] = { - .class_hid = BNXT_ULP_CLASS_HID_39b5c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2906] = { - .class_hid = BNXT_ULP_CLASS_HID_3b24c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2907] = { - .class_hid = BNXT_ULP_CLASS_HID_38118, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2908] = { - .class_hid = BNXT_ULP_CLASS_HID_3b808, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2909] = { - .class_hid = BNXT_ULP_CLASS_HID_3d788, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2910] = { - .class_hid = BNXT_ULP_CLASS_HID_393ac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2911] = { - .class_hid = BNXT_ULP_CLASS_HID_3dd44, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2912] = { - .class_hid = BNXT_ULP_CLASS_HID_39968, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2913] = { - .class_hid = BNXT_ULP_CLASS_HID_3a164, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2914] = { - .class_hid = BNXT_ULP_CLASS_HID_3d854, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2915] = { - .class_hid = BNXT_ULP_CLASS_HID_3a720, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2916] = { - .class_hid = BNXT_ULP_CLASS_HID_3de10, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2917] = { - .class_hid = BNXT_ULP_CLASS_HID_39cd0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2918] = { - .class_hid = BNXT_ULP_CLASS_HID_3b7c0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2919] = { - .class_hid = BNXT_ULP_CLASS_HID_3828c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2920] = { - .class_hid = BNXT_ULP_CLASS_HID_3bdfc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2921] = { - .class_hid = BNXT_ULP_CLASS_HID_3c5f8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2922] = { - .class_hid = BNXT_ULP_CLASS_HID_3819c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2923] = { - .class_hid = BNXT_ULP_CLASS_HID_3cbb4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2924] = { - .class_hid = BNXT_ULP_CLASS_HID_38758, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2925] = { - .class_hid = BNXT_ULP_CLASS_HID_7c56c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2926] = { - .class_hid = BNXT_ULP_CLASS_HID_78110, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2927] = { - .class_hid = BNXT_ULP_CLASS_HID_7cb28, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2928] = { - .class_hid = BNXT_ULP_CLASS_HID_786cc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2929] = { - .class_hid = BNXT_ULP_CLASS_HID_7aec8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2930] = { - .class_hid = BNXT_ULP_CLASS_HID_7c638, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2931] = { - .class_hid = BNXT_ULP_CLASS_HID_7d484, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2932] = { - .class_hid = BNXT_ULP_CLASS_HID_790a8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2933] = { - .class_hid = BNXT_ULP_CLASS_HID_78ab4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2934] = { - .class_hid = BNXT_ULP_CLASS_HID_7a5a4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2935] = { - .class_hid = BNXT_ULP_CLASS_HID_7b070, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2936] = { - .class_hid = BNXT_ULP_CLASS_HID_7ab60, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2937] = { - .class_hid = BNXT_ULP_CLASS_HID_79410, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2938] = { - .class_hid = BNXT_ULP_CLASS_HID_78f00, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2939] = { - .class_hid = BNXT_ULP_CLASS_HID_79dcc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2940] = { - .class_hid = BNXT_ULP_CLASS_HID_7b53c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2941] = { - .class_hid = BNXT_ULP_CLASS_HID_7d0bc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2942] = { - .class_hid = BNXT_ULP_CLASS_HID_7cbac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2943] = { - .class_hid = BNXT_ULP_CLASS_HID_7d678, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2944] = { - .class_hid = BNXT_ULP_CLASS_HID_7921c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2945] = { - .class_hid = BNXT_ULP_CLASS_HID_7ba18, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2946] = { - .class_hid = BNXT_ULP_CLASS_HID_7d508, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2947] = { - .class_hid = BNXT_ULP_CLASS_HID_7a3d4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2948] = { - .class_hid = BNXT_ULP_CLASS_HID_7dac4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2949] = { - .class_hid = BNXT_ULP_CLASS_HID_79984, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2950] = { - .class_hid = BNXT_ULP_CLASS_HID_7b0f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2951] = { - .class_hid = BNXT_ULP_CLASS_HID_79f40, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2952] = { - .class_hid = BNXT_ULP_CLASS_HID_7b6b0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2953] = { - .class_hid = BNXT_ULP_CLASS_HID_7deac, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2954] = { - .class_hid = BNXT_ULP_CLASS_HID_79a50, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2955] = { - .class_hid = BNXT_ULP_CLASS_HID_7c468, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2956] = { - .class_hid = BNXT_ULP_CLASS_HID_7800c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2957] = { - .class_hid = BNXT_ULP_CLASS_HID_86c0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2958] = { - .class_hid = BNXT_ULP_CLASS_HID_a1d0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2959] = { - .class_hid = BNXT_ULP_CLASS_HID_8c0c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2960] = { - .class_hid = BNXT_ULP_CLASS_HID_a71c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2961] = { - .class_hid = BNXT_ULP_CLASS_HID_906c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2962] = { - .class_hid = BNXT_ULP_CLASS_HID_8b7c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2963] = { - .class_hid = BNXT_ULP_CLASS_HID_99a8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2964] = { - .class_hid = BNXT_ULP_CLASS_HID_b0b8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2965] = { - .class_hid = BNXT_ULP_CLASS_HID_aab4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2966] = { - .class_hid = BNXT_ULP_CLASS_HID_c244, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2967] = { - .class_hid = BNXT_ULP_CLASS_HID_d0f0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2968] = { - .class_hid = BNXT_ULP_CLASS_HID_cb80, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2969] = { - .class_hid = BNXT_ULP_CLASS_HID_b4d0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2970] = { - .class_hid = BNXT_ULP_CLASS_HID_afe0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2971] = { - .class_hid = BNXT_ULP_CLASS_HID_ba1c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2972] = { - .class_hid = BNXT_ULP_CLASS_HID_d52c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2973] = { - .class_hid = BNXT_ULP_CLASS_HID_48314, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2974] = { - .class_hid = BNXT_ULP_CLASS_HID_4ba24, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2975] = { - .class_hid = BNXT_ULP_CLASS_HID_48950, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2976] = { - .class_hid = BNXT_ULP_CLASS_HID_4a060, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2977] = { - .class_hid = BNXT_ULP_CLASS_HID_4c86c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2978] = { - .class_hid = BNXT_ULP_CLASS_HID_48440, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2979] = { - .class_hid = BNXT_ULP_CLASS_HID_492fc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2980] = { - .class_hid = BNXT_ULP_CLASS_HID_48d8c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2981] = { - .class_hid = BNXT_ULP_CLASS_HID_4a7f8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2982] = { - .class_hid = BNXT_ULP_CLASS_HID_4de88, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2983] = { - .class_hid = BNXT_ULP_CLASS_HID_4adc4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2984] = { - .class_hid = BNXT_ULP_CLASS_HID_4c4d4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2985] = { - .class_hid = BNXT_ULP_CLASS_HID_4b124, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2986] = { - .class_hid = BNXT_ULP_CLASS_HID_4a834, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2987] = { - .class_hid = BNXT_ULP_CLASS_HID_4b760, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2988] = { - .class_hid = BNXT_ULP_CLASS_HID_4ae70, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2989] = { - .class_hid = BNXT_ULP_CLASS_HID_1bcc0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2990] = { - .class_hid = BNXT_ULP_CLASS_HID_1d7d0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2991] = { - .class_hid = BNXT_ULP_CLASS_HID_1a20c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2992] = { - .class_hid = BNXT_ULP_CLASS_HID_1dd1c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2993] = { - .class_hid = BNXT_ULP_CLASS_HID_1866c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2994] = { - .class_hid = BNXT_ULP_CLASS_HID_1a17c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2995] = { - .class_hid = BNXT_ULP_CLASS_HID_18fa8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2996] = { - .class_hid = BNXT_ULP_CLASS_HID_1a6b8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2997] = { - .class_hid = BNXT_ULP_CLASS_HID_1c0b4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2998] = { - .class_hid = BNXT_ULP_CLASS_HID_19c88, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [2999] = { - .class_hid = BNXT_ULP_CLASS_HID_1c6f0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3000] = { - .class_hid = BNXT_ULP_CLASS_HID_182d4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3001] = { - .class_hid = BNXT_ULP_CLASS_HID_1aad0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3002] = { - .class_hid = BNXT_ULP_CLASS_HID_1c5e0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3003] = { - .class_hid = BNXT_ULP_CLASS_HID_1d01c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3004] = { - .class_hid = BNXT_ULP_CLASS_HID_1cb2c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3005] = { - .class_hid = BNXT_ULP_CLASS_HID_5b914, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3006] = { - .class_hid = BNXT_ULP_CLASS_HID_5d024, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3007] = { - .class_hid = BNXT_ULP_CLASS_HID_5bf50, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3008] = { - .class_hid = BNXT_ULP_CLASS_HID_5d660, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3009] = { - .class_hid = BNXT_ULP_CLASS_HID_582b0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3010] = { - .class_hid = BNXT_ULP_CLASS_HID_5ba40, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3011] = { - .class_hid = BNXT_ULP_CLASS_HID_588fc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3012] = { - .class_hid = BNXT_ULP_CLASS_HID_5a38c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3013] = { - .class_hid = BNXT_ULP_CLASS_HID_5ddf8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3014] = { - .class_hid = BNXT_ULP_CLASS_HID_599dc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3015] = { - .class_hid = BNXT_ULP_CLASS_HID_5c3c4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3016] = { - .class_hid = BNXT_ULP_CLASS_HID_59f18, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3017] = { - .class_hid = BNXT_ULP_CLASS_HID_5a724, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3018] = { - .class_hid = BNXT_ULP_CLASS_HID_5de34, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3019] = { - .class_hid = BNXT_ULP_CLASS_HID_5ad60, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3020] = { - .class_hid = BNXT_ULP_CLASS_HID_5c470, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3021] = { - .class_hid = BNXT_ULP_CLASS_HID_cd40, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3022] = { - .class_hid = BNXT_ULP_CLASS_HID_e450, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3023] = { - .class_hid = BNXT_ULP_CLASS_HID_f28c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3024] = { - .class_hid = BNXT_ULP_CLASS_HID_ed9c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3025] = { - .class_hid = BNXT_ULP_CLASS_HID_d6ec, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3026] = { - .class_hid = BNXT_ULP_CLASS_HID_f1fc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3027] = { - .class_hid = BNXT_ULP_CLASS_HID_dc28, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3028] = { - .class_hid = BNXT_ULP_CLASS_HID_f738, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3029] = { - .class_hid = BNXT_ULP_CLASS_HID_d134, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3030] = { - .class_hid = BNXT_ULP_CLASS_HID_c8c4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3031] = { - .class_hid = BNXT_ULP_CLASS_HID_d770, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3032] = { - .class_hid = BNXT_ULP_CLASS_HID_d354, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3033] = { - .class_hid = BNXT_ULP_CLASS_HID_fb50, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3034] = { - .class_hid = BNXT_ULP_CLASS_HID_d260, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3035] = { - .class_hid = BNXT_ULP_CLASS_HID_e09c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3036] = { - .class_hid = BNXT_ULP_CLASS_HID_dbac, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3037] = { - .class_hid = BNXT_ULP_CLASS_HID_4c994, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3038] = { - .class_hid = BNXT_ULP_CLASS_HID_4e0a4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3039] = { - .class_hid = BNXT_ULP_CLASS_HID_4cfd0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3040] = { - .class_hid = BNXT_ULP_CLASS_HID_4e6e0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3041] = { - .class_hid = BNXT_ULP_CLASS_HID_4d330, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3042] = { - .class_hid = BNXT_ULP_CLASS_HID_4cac0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3043] = { - .class_hid = BNXT_ULP_CLASS_HID_4d97c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3044] = { - .class_hid = BNXT_ULP_CLASS_HID_4f00c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3045] = { - .class_hid = BNXT_ULP_CLASS_HID_4ea78, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3046] = { - .class_hid = BNXT_ULP_CLASS_HID_4c508, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3047] = { - .class_hid = BNXT_ULP_CLASS_HID_4d044, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3048] = { - .class_hid = BNXT_ULP_CLASS_HID_4cb54, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3049] = { - .class_hid = BNXT_ULP_CLASS_HID_4f7a4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3050] = { - .class_hid = BNXT_ULP_CLASS_HID_4eeb4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3051] = { - .class_hid = BNXT_ULP_CLASS_HID_4fde0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3052] = { - .class_hid = BNXT_ULP_CLASS_HID_4d4f0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3053] = { - .class_hid = BNXT_ULP_CLASS_HID_1e340, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3054] = { - .class_hid = BNXT_ULP_CLASS_HID_1da50, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3055] = { - .class_hid = BNXT_ULP_CLASS_HID_1e88c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3056] = { - .class_hid = BNXT_ULP_CLASS_HID_1c39c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3057] = { - .class_hid = BNXT_ULP_CLASS_HID_1ccec, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3058] = { - .class_hid = BNXT_ULP_CLASS_HID_1e7fc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3059] = { - .class_hid = BNXT_ULP_CLASS_HID_1f228, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3060] = { - .class_hid = BNXT_ULP_CLASS_HID_1ed38, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3061] = { - .class_hid = BNXT_ULP_CLASS_HID_1c734, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3062] = { - .class_hid = BNXT_ULP_CLASS_HID_1c308, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3063] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd70, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3064] = { - .class_hid = BNXT_ULP_CLASS_HID_1c954, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3065] = { - .class_hid = BNXT_ULP_CLASS_HID_1d150, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3066] = { - .class_hid = BNXT_ULP_CLASS_HID_1c860, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3067] = { - .class_hid = BNXT_ULP_CLASS_HID_1d69c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3068] = { - .class_hid = BNXT_ULP_CLASS_HID_1d2f0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3069] = { - .class_hid = BNXT_ULP_CLASS_HID_5ff94, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3070] = { - .class_hid = BNXT_ULP_CLASS_HID_5d6a4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3071] = { - .class_hid = BNXT_ULP_CLASS_HID_5e5d0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3072] = { - .class_hid = BNXT_ULP_CLASS_HID_5dce0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3073] = { - .class_hid = BNXT_ULP_CLASS_HID_5c930, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3074] = { - .class_hid = BNXT_ULP_CLASS_HID_5e0c0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3075] = { - .class_hid = BNXT_ULP_CLASS_HID_5cf7c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3076] = { - .class_hid = BNXT_ULP_CLASS_HID_5e60c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3077] = { - .class_hid = BNXT_ULP_CLASS_HID_5c078, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3078] = { - .class_hid = BNXT_ULP_CLASS_HID_5dc5c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3079] = { - .class_hid = BNXT_ULP_CLASS_HID_5c644, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3080] = { - .class_hid = BNXT_ULP_CLASS_HID_5c598, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3081] = { - .class_hid = BNXT_ULP_CLASS_HID_5eda4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3082] = { - .class_hid = BNXT_ULP_CLASS_HID_5c4b4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3083] = { - .class_hid = BNXT_ULP_CLASS_HID_5d3e0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3084] = { - .class_hid = BNXT_ULP_CLASS_HID_5caf0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3085] = { - .class_hid = BNXT_ULP_CLASS_HID_ab80, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3086] = { - .class_hid = BNXT_ULP_CLASS_HID_a290, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3087] = { - .class_hid = BNXT_ULP_CLASS_HID_b1cc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3088] = { - .class_hid = BNXT_ULP_CLASS_HID_a8dc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3089] = { - .class_hid = BNXT_ULP_CLASS_HID_b52c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3090] = { - .class_hid = BNXT_ULP_CLASS_HID_ac3c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3091] = { - .class_hid = BNXT_ULP_CLASS_HID_bb68, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3092] = { - .class_hid = BNXT_ULP_CLASS_HID_b278, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3093] = { - .class_hid = BNXT_ULP_CLASS_HID_ac74, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3094] = { - .class_hid = BNXT_ULP_CLASS_HID_e704, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3095] = { - .class_hid = BNXT_ULP_CLASS_HID_f5b0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3096] = { - .class_hid = BNXT_ULP_CLASS_HID_b194, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3097] = { - .class_hid = BNXT_ULP_CLASS_HID_b990, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3098] = { - .class_hid = BNXT_ULP_CLASS_HID_f0a0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3099] = { - .class_hid = BNXT_ULP_CLASS_HID_bfdc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3100] = { - .class_hid = BNXT_ULP_CLASS_HID_f6ec, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3101] = { - .class_hid = BNXT_ULP_CLASS_HID_4a4d4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3102] = { - .class_hid = BNXT_ULP_CLASS_HID_4bfe4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3103] = { - .class_hid = BNXT_ULP_CLASS_HID_4aa10, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3104] = { - .class_hid = BNXT_ULP_CLASS_HID_4a520, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3105] = { - .class_hid = BNXT_ULP_CLASS_HID_4ed2c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3106] = { - .class_hid = BNXT_ULP_CLASS_HID_4a900, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3107] = { - .class_hid = BNXT_ULP_CLASS_HID_4b7bc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3108] = { - .class_hid = BNXT_ULP_CLASS_HID_4af4c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3109] = { - .class_hid = BNXT_ULP_CLASS_HID_4a8b8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3110] = { - .class_hid = BNXT_ULP_CLASS_HID_4e048, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3111] = { - .class_hid = BNXT_ULP_CLASS_HID_4ae84, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3112] = { - .class_hid = BNXT_ULP_CLASS_HID_4e994, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3113] = { - .class_hid = BNXT_ULP_CLASS_HID_4b2e4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3114] = { - .class_hid = BNXT_ULP_CLASS_HID_4adf4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3115] = { - .class_hid = BNXT_ULP_CLASS_HID_4b820, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3116] = { - .class_hid = BNXT_ULP_CLASS_HID_4f330, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3117] = { - .class_hid = BNXT_ULP_CLASS_HID_1a180, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3118] = { - .class_hid = BNXT_ULP_CLASS_HID_1f890, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3119] = { - .class_hid = BNXT_ULP_CLASS_HID_1a7cc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3120] = { - .class_hid = BNXT_ULP_CLASS_HID_1fedc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3121] = { - .class_hid = BNXT_ULP_CLASS_HID_1ab2c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3122] = { - .class_hid = BNXT_ULP_CLASS_HID_1a23c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3123] = { - .class_hid = BNXT_ULP_CLASS_HID_1b168, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3124] = { - .class_hid = BNXT_ULP_CLASS_HID_1a878, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3125] = { - .class_hid = BNXT_ULP_CLASS_HID_1e274, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3126] = { - .class_hid = BNXT_ULP_CLASS_HID_1be48, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3127] = { - .class_hid = BNXT_ULP_CLASS_HID_1ebb0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3128] = { - .class_hid = BNXT_ULP_CLASS_HID_1a794, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3129] = { - .class_hid = BNXT_ULP_CLASS_HID_1af90, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3130] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6a0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3131] = { - .class_hid = BNXT_ULP_CLASS_HID_1f5dc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3132] = { - .class_hid = BNXT_ULP_CLASS_HID_1b130, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3133] = { - .class_hid = BNXT_ULP_CLASS_HID_5bad4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3134] = { - .class_hid = BNXT_ULP_CLASS_HID_5f5e4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3135] = { - .class_hid = BNXT_ULP_CLASS_HID_5a010, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3136] = { - .class_hid = BNXT_ULP_CLASS_HID_5fb20, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3137] = { - .class_hid = BNXT_ULP_CLASS_HID_5a470, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3138] = { - .class_hid = BNXT_ULP_CLASS_HID_5bf00, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3139] = { - .class_hid = BNXT_ULP_CLASS_HID_5adbc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3140] = { - .class_hid = BNXT_ULP_CLASS_HID_5a54c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3141] = { - .class_hid = BNXT_ULP_CLASS_HID_5feb8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3142] = { - .class_hid = BNXT_ULP_CLASS_HID_5ba9c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3143] = { - .class_hid = BNXT_ULP_CLASS_HID_5e484, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3144] = { - .class_hid = BNXT_ULP_CLASS_HID_5a0d8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3145] = { - .class_hid = BNXT_ULP_CLASS_HID_5a8e4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3146] = { - .class_hid = BNXT_ULP_CLASS_HID_5e3f4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3147] = { - .class_hid = BNXT_ULP_CLASS_HID_5ae20, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3148] = { - .class_hid = BNXT_ULP_CLASS_HID_5e930, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3149] = { - .class_hid = BNXT_ULP_CLASS_HID_ee00, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3150] = { - .class_hid = BNXT_ULP_CLASS_HID_e910, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3151] = { - .class_hid = BNXT_ULP_CLASS_HID_f44c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3152] = { - .class_hid = BNXT_ULP_CLASS_HID_ef5c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3153] = { - .class_hid = BNXT_ULP_CLASS_HID_fbac, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3154] = { - .class_hid = BNXT_ULP_CLASS_HID_f2bc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3155] = { - .class_hid = BNXT_ULP_CLASS_HID_e1e8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3156] = { - .class_hid = BNXT_ULP_CLASS_HID_f8f8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3157] = { - .class_hid = BNXT_ULP_CLASS_HID_f2f4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3158] = { - .class_hid = BNXT_ULP_CLASS_HID_ed84, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3159] = { - .class_hid = BNXT_ULP_CLASS_HID_f830, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3160] = { - .class_hid = BNXT_ULP_CLASS_HID_f414, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3161] = { - .class_hid = BNXT_ULP_CLASS_HID_fc10, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3162] = { - .class_hid = BNXT_ULP_CLASS_HID_f720, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3163] = { - .class_hid = BNXT_ULP_CLASS_HID_e25c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3164] = { - .class_hid = BNXT_ULP_CLASS_HID_fd6c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3165] = { - .class_hid = BNXT_ULP_CLASS_HID_4eb54, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3166] = { - .class_hid = BNXT_ULP_CLASS_HID_4e264, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3167] = { - .class_hid = BNXT_ULP_CLASS_HID_4f090, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3168] = { - .class_hid = BNXT_ULP_CLASS_HID_4eba0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3169] = { - .class_hid = BNXT_ULP_CLASS_HID_4f4f0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3170] = { - .class_hid = BNXT_ULP_CLASS_HID_4ef80, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3171] = { - .class_hid = BNXT_ULP_CLASS_HID_4fa3c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3172] = { - .class_hid = BNXT_ULP_CLASS_HID_4f5cc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3173] = { - .class_hid = BNXT_ULP_CLASS_HID_4ef38, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3174] = { - .class_hid = BNXT_ULP_CLASS_HID_4e6c8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3175] = { - .class_hid = BNXT_ULP_CLASS_HID_4f504, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3176] = { - .class_hid = BNXT_ULP_CLASS_HID_4f158, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3177] = { - .class_hid = BNXT_ULP_CLASS_HID_4f964, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3178] = { - .class_hid = BNXT_ULP_CLASS_HID_4f074, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3179] = { - .class_hid = BNXT_ULP_CLASS_HID_4fea0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3180] = { - .class_hid = BNXT_ULP_CLASS_HID_4f9b0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3181] = { - .class_hid = BNXT_ULP_CLASS_HID_1e400, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3182] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff10, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3183] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea4c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3184] = { - .class_hid = BNXT_ULP_CLASS_HID_1e55c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3185] = { - .class_hid = BNXT_ULP_CLASS_HID_1f1ac, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3186] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8bc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3187] = { - .class_hid = BNXT_ULP_CLASS_HID_1f7e8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3188] = { - .class_hid = BNXT_ULP_CLASS_HID_1eef8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3189] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8f4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3190] = { - .class_hid = BNXT_ULP_CLASS_HID_1e4c8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3191] = { - .class_hid = BNXT_ULP_CLASS_HID_1f304, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3192] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea14, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3193] = { - .class_hid = BNXT_ULP_CLASS_HID_1f210, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3194] = { - .class_hid = BNXT_ULP_CLASS_HID_1ed20, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3195] = { - .class_hid = BNXT_ULP_CLASS_HID_1f85c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3196] = { - .class_hid = BNXT_ULP_CLASS_HID_1f7b0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3197] = { - .class_hid = BNXT_ULP_CLASS_HID_5e154, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3198] = { - .class_hid = BNXT_ULP_CLASS_HID_5f864, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3199] = { - .class_hid = BNXT_ULP_CLASS_HID_5e690, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3200] = { - .class_hid = BNXT_ULP_CLASS_HID_5e1a0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3201] = { - .class_hid = BNXT_ULP_CLASS_HID_5eaf0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3202] = { - .class_hid = BNXT_ULP_CLASS_HID_5e580, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3203] = { - .class_hid = BNXT_ULP_CLASS_HID_5f03c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3204] = { - .class_hid = BNXT_ULP_CLASS_HID_5ebcc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3205] = { - .class_hid = BNXT_ULP_CLASS_HID_5e538, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3206] = { - .class_hid = BNXT_ULP_CLASS_HID_5e11c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3207] = { - .class_hid = BNXT_ULP_CLASS_HID_5eb04, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3208] = { - .class_hid = BNXT_ULP_CLASS_HID_5e758, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3209] = { - .class_hid = BNXT_ULP_CLASS_HID_5ef64, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3210] = { - .class_hid = BNXT_ULP_CLASS_HID_5e674, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3211] = { - .class_hid = BNXT_ULP_CLASS_HID_5f4a0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3212] = { - .class_hid = BNXT_ULP_CLASS_HID_5f084, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3213] = { - .class_hid = BNXT_ULP_CLASS_HID_22998, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3214] = { - .class_hid = BNXT_ULP_CLASS_HID_24088, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3215] = { - .class_hid = BNXT_ULP_CLASS_HID_22f54, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3216] = { - .class_hid = BNXT_ULP_CLASS_HID_24644, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3217] = { - .class_hid = BNXT_ULP_CLASS_HID_23334, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3218] = { - .class_hid = BNXT_ULP_CLASS_HID_22a24, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3219] = { - .class_hid = BNXT_ULP_CLASS_HID_238f0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3220] = { - .class_hid = BNXT_ULP_CLASS_HID_253e0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3221] = { - .class_hid = BNXT_ULP_CLASS_HID_24dec, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3222] = { - .class_hid = BNXT_ULP_CLASS_HID_209d0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3223] = { - .class_hid = BNXT_ULP_CLASS_HID_2149c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3224] = { - .class_hid = BNXT_ULP_CLASS_HID_20f8c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3225] = { - .class_hid = BNXT_ULP_CLASS_HID_25788, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3226] = { - .class_hid = BNXT_ULP_CLASS_HID_2136c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3227] = { - .class_hid = BNXT_ULP_CLASS_HID_25d44, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3228] = { - .class_hid = BNXT_ULP_CLASS_HID_21928, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3229] = { - .class_hid = BNXT_ULP_CLASS_HID_234a8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3230] = { - .class_hid = BNXT_ULP_CLASS_HID_22fd8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3231] = { - .class_hid = BNXT_ULP_CLASS_HID_23a64, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3232] = { - .class_hid = BNXT_ULP_CLASS_HID_25594, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3233] = { - .class_hid = BNXT_ULP_CLASS_HID_21e44, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3234] = { - .class_hid = BNXT_ULP_CLASS_HID_23974, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3235] = { - .class_hid = BNXT_ULP_CLASS_HID_20400, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3236] = { - .class_hid = BNXT_ULP_CLASS_HID_23f30, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3237] = { - .class_hid = BNXT_ULP_CLASS_HID_2593c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3238] = { - .class_hid = BNXT_ULP_CLASS_HID_214e0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3239] = { - .class_hid = BNXT_ULP_CLASS_HID_25ef8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3240] = { - .class_hid = BNXT_ULP_CLASS_HID_21adc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32772, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3241] = { - .class_hid = BNXT_ULP_CLASS_HID_222d8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3242] = { - .class_hid = BNXT_ULP_CLASS_HID_25dc8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3243] = { - .class_hid = BNXT_ULP_CLASS_HID_22894, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3244] = { - .class_hid = BNXT_ULP_CLASS_HID_24384, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32836, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3245] = { - .class_hid = BNXT_ULP_CLASS_HID_6224c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3246] = { - .class_hid = BNXT_ULP_CLASS_HID_65d7c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3247] = { - .class_hid = BNXT_ULP_CLASS_HID_62808, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3248] = { - .class_hid = BNXT_ULP_CLASS_HID_64338, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3249] = { - .class_hid = BNXT_ULP_CLASS_HID_60fe8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3250] = { - .class_hid = BNXT_ULP_CLASS_HID_62718, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3251] = { - .class_hid = BNXT_ULP_CLASS_HID_635a4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3252] = { - .class_hid = BNXT_ULP_CLASS_HID_62cd4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3253] = { - .class_hid = BNXT_ULP_CLASS_HID_646a0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3254] = { - .class_hid = BNXT_ULP_CLASS_HID_60284, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3255] = { - .class_hid = BNXT_ULP_CLASS_HID_61150, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3256] = { - .class_hid = BNXT_ULP_CLASS_HID_60840, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3257] = { - .class_hid = BNXT_ULP_CLASS_HID_6507c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3258] = { - .class_hid = BNXT_ULP_CLASS_HID_64b6c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3259] = { - .class_hid = BNXT_ULP_CLASS_HID_65638, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3260] = { - .class_hid = BNXT_ULP_CLASS_HID_6121c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3261] = { - .class_hid = BNXT_ULP_CLASS_HID_6319c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3262] = { - .class_hid = BNXT_ULP_CLASS_HID_6288c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3263] = { - .class_hid = BNXT_ULP_CLASS_HID_63758, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3264] = { - .class_hid = BNXT_ULP_CLASS_HID_62e48, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3265] = { - .class_hid = BNXT_ULP_CLASS_HID_61b38, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3266] = { - .class_hid = BNXT_ULP_CLASS_HID_63228, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3267] = { - .class_hid = BNXT_ULP_CLASS_HID_600f4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3268] = { - .class_hid = BNXT_ULP_CLASS_HID_63be4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3269] = { - .class_hid = BNXT_ULP_CLASS_HID_655f0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3270] = { - .class_hid = BNXT_ULP_CLASS_HID_611d4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3271] = { - .class_hid = BNXT_ULP_CLASS_HID_65bac, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3272] = { - .class_hid = BNXT_ULP_CLASS_HID_61790, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49156, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3273] = { - .class_hid = BNXT_ULP_CLASS_HID_63f8c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3274] = { - .class_hid = BNXT_ULP_CLASS_HID_656bc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3275] = { - .class_hid = BNXT_ULP_CLASS_HID_62548, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3276] = { - .class_hid = BNXT_ULP_CLASS_HID_65c78, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3277] = { - .class_hid = BNXT_ULP_CLASS_HID_35f98, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3278] = { - .class_hid = BNXT_ULP_CLASS_HID_31b7c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3279] = { - .class_hid = BNXT_ULP_CLASS_HID_34554, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3280] = { - .class_hid = BNXT_ULP_CLASS_HID_30138, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3281] = { - .class_hid = BNXT_ULP_CLASS_HID_32934, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3282] = { - .class_hid = BNXT_ULP_CLASS_HID_34024, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3283] = { - .class_hid = BNXT_ULP_CLASS_HID_32ef0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3284] = { - .class_hid = BNXT_ULP_CLASS_HID_349e0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3285] = { - .class_hid = BNXT_ULP_CLASS_HID_304a0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3286] = { - .class_hid = BNXT_ULP_CLASS_HID_33fd0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3287] = { - .class_hid = BNXT_ULP_CLASS_HID_30a9c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3288] = { - .class_hid = BNXT_ULP_CLASS_HID_3258c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3289] = { - .class_hid = BNXT_ULP_CLASS_HID_34d88, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3290] = { - .class_hid = BNXT_ULP_CLASS_HID_3096c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3291] = { - .class_hid = BNXT_ULP_CLASS_HID_31438, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3292] = { - .class_hid = BNXT_ULP_CLASS_HID_30f28, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3293] = { - .class_hid = BNXT_ULP_CLASS_HID_32aa8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3294] = { - .class_hid = BNXT_ULP_CLASS_HID_345d8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3295] = { - .class_hid = BNXT_ULP_CLASS_HID_35064, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3296] = { - .class_hid = BNXT_ULP_CLASS_HID_34b94, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3297] = { - .class_hid = BNXT_ULP_CLASS_HID_33444, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3298] = { - .class_hid = BNXT_ULP_CLASS_HID_32f74, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3299] = { - .class_hid = BNXT_ULP_CLASS_HID_33a00, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3300] = { - .class_hid = BNXT_ULP_CLASS_HID_35530, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3301] = { - .class_hid = BNXT_ULP_CLASS_HID_313f0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3302] = { - .class_hid = BNXT_ULP_CLASS_HID_30ae0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3303] = { - .class_hid = BNXT_ULP_CLASS_HID_319ac, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3304] = { - .class_hid = BNXT_ULP_CLASS_HID_330dc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98308, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3305] = { - .class_hid = BNXT_ULP_CLASS_HID_358d8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3306] = { - .class_hid = BNXT_ULP_CLASS_HID_314bc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3307] = { - .class_hid = BNXT_ULP_CLASS_HID_35e94, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3308] = { - .class_hid = BNXT_ULP_CLASS_HID_31a78, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98372, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3309] = { - .class_hid = BNXT_ULP_CLASS_HID_7584c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3310] = { - .class_hid = BNXT_ULP_CLASS_HID_71430, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3311] = { - .class_hid = BNXT_ULP_CLASS_HID_75e08, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3312] = { - .class_hid = BNXT_ULP_CLASS_HID_71dec, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3313] = { - .class_hid = BNXT_ULP_CLASS_HID_725e8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3314] = { - .class_hid = BNXT_ULP_CLASS_HID_75d18, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3315] = { - .class_hid = BNXT_ULP_CLASS_HID_72ba4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3316] = { - .class_hid = BNXT_ULP_CLASS_HID_742d4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3317] = { - .class_hid = BNXT_ULP_CLASS_HID_70194, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3318] = { - .class_hid = BNXT_ULP_CLASS_HID_73884, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3319] = { - .class_hid = BNXT_ULP_CLASS_HID_70750, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3320] = { - .class_hid = BNXT_ULP_CLASS_HID_73e40, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3321] = { - .class_hid = BNXT_ULP_CLASS_HID_7467c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3322] = { - .class_hid = BNXT_ULP_CLASS_HID_70220, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3323] = { - .class_hid = BNXT_ULP_CLASS_HID_710ec, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3324] = { - .class_hid = BNXT_ULP_CLASS_HID_7081c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3325] = { - .class_hid = BNXT_ULP_CLASS_HID_7279c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3326] = { - .class_hid = BNXT_ULP_CLASS_HID_75e8c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3327] = { - .class_hid = BNXT_ULP_CLASS_HID_72d58, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3328] = { - .class_hid = BNXT_ULP_CLASS_HID_74448, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3329] = { - .class_hid = BNXT_ULP_CLASS_HID_73138, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3330] = { - .class_hid = BNXT_ULP_CLASS_HID_72828, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3331] = { - .class_hid = BNXT_ULP_CLASS_HID_736f4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3332] = { - .class_hid = BNXT_ULP_CLASS_HID_751e4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3333] = { - .class_hid = BNXT_ULP_CLASS_HID_74bf0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3334] = { - .class_hid = BNXT_ULP_CLASS_HID_707d4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3335] = { - .class_hid = BNXT_ULP_CLASS_HID_71260, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3336] = { - .class_hid = BNXT_ULP_CLASS_HID_70d90, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114692, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3337] = { - .class_hid = BNXT_ULP_CLASS_HID_7558c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3338] = { - .class_hid = BNXT_ULP_CLASS_HID_71170, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3339] = { - .class_hid = BNXT_ULP_CLASS_HID_75b48, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3340] = { - .class_hid = BNXT_ULP_CLASS_HID_7172c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3341] = { - .class_hid = BNXT_ULP_CLASS_HID_2d298, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3342] = { - .class_hid = BNXT_ULP_CLASS_HID_2cd88, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3343] = { - .class_hid = BNXT_ULP_CLASS_HID_2d854, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3344] = { - .class_hid = BNXT_ULP_CLASS_HID_29438, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3345] = { - .class_hid = BNXT_ULP_CLASS_HID_2bc34, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3346] = { - .class_hid = BNXT_ULP_CLASS_HID_2d724, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3347] = { - .class_hid = BNXT_ULP_CLASS_HID_2a5f0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3348] = { - .class_hid = BNXT_ULP_CLASS_HID_2dce0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3349] = { - .class_hid = BNXT_ULP_CLASS_HID_29ba0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3350] = { - .class_hid = BNXT_ULP_CLASS_HID_2b2d0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3351] = { - .class_hid = BNXT_ULP_CLASS_HID_2819c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3352] = { - .class_hid = BNXT_ULP_CLASS_HID_2b88c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3353] = { - .class_hid = BNXT_ULP_CLASS_HID_2c088, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3354] = { - .class_hid = BNXT_ULP_CLASS_HID_29c6c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3355] = { - .class_hid = BNXT_ULP_CLASS_HID_2c644, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3356] = { - .class_hid = BNXT_ULP_CLASS_HID_28228, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3357] = { - .class_hid = BNXT_ULP_CLASS_HID_2a1a8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3358] = { - .class_hid = BNXT_ULP_CLASS_HID_2d8d8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3359] = { - .class_hid = BNXT_ULP_CLASS_HID_2a764, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3360] = { - .class_hid = BNXT_ULP_CLASS_HID_2de94, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3361] = { - .class_hid = BNXT_ULP_CLASS_HID_28b44, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3362] = { - .class_hid = BNXT_ULP_CLASS_HID_2a274, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3363] = { - .class_hid = BNXT_ULP_CLASS_HID_2b100, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3364] = { - .class_hid = BNXT_ULP_CLASS_HID_2a830, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3365] = { - .class_hid = BNXT_ULP_CLASS_HID_2c23c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3366] = { - .class_hid = BNXT_ULP_CLASS_HID_281e0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3367] = { - .class_hid = BNXT_ULP_CLASS_HID_2cbf8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3368] = { - .class_hid = BNXT_ULP_CLASS_HID_287dc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163844, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3369] = { - .class_hid = BNXT_ULP_CLASS_HID_2afd8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3370] = { - .class_hid = BNXT_ULP_CLASS_HID_2c6c8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3371] = { - .class_hid = BNXT_ULP_CLASS_HID_2d594, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3372] = { - .class_hid = BNXT_ULP_CLASS_HID_29178, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163908, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3373] = { - .class_hid = BNXT_ULP_CLASS_HID_6af4c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3374] = { - .class_hid = BNXT_ULP_CLASS_HID_6c67c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3375] = { - .class_hid = BNXT_ULP_CLASS_HID_6d508, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3376] = { - .class_hid = BNXT_ULP_CLASS_HID_690ec, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3377] = { - .class_hid = BNXT_ULP_CLASS_HID_6b8e8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3378] = { - .class_hid = BNXT_ULP_CLASS_HID_6d018, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3379] = { - .class_hid = BNXT_ULP_CLASS_HID_6bea4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3380] = { - .class_hid = BNXT_ULP_CLASS_HID_6d9d4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3381] = { - .class_hid = BNXT_ULP_CLASS_HID_69494, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3382] = { - .class_hid = BNXT_ULP_CLASS_HID_68f84, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3383] = { - .class_hid = BNXT_ULP_CLASS_HID_69a50, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3384] = { - .class_hid = BNXT_ULP_CLASS_HID_6b540, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3385] = { - .class_hid = BNXT_ULP_CLASS_HID_6dd7c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3386] = { - .class_hid = BNXT_ULP_CLASS_HID_69920, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3387] = { - .class_hid = BNXT_ULP_CLASS_HID_6c338, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3388] = { - .class_hid = BNXT_ULP_CLASS_HID_69f1c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3389] = { - .class_hid = BNXT_ULP_CLASS_HID_6ba9c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3390] = { - .class_hid = BNXT_ULP_CLASS_HID_6d58c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3391] = { - .class_hid = BNXT_ULP_CLASS_HID_6a058, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3392] = { - .class_hid = BNXT_ULP_CLASS_HID_6db48, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3393] = { - .class_hid = BNXT_ULP_CLASS_HID_68438, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3394] = { - .class_hid = BNXT_ULP_CLASS_HID_6bf28, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3395] = { - .class_hid = BNXT_ULP_CLASS_HID_68df4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3396] = { - .class_hid = BNXT_ULP_CLASS_HID_6a4e4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3397] = { - .class_hid = BNXT_ULP_CLASS_HID_6def0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3398] = { - .class_hid = BNXT_ULP_CLASS_HID_69ad4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3399] = { - .class_hid = BNXT_ULP_CLASS_HID_6c4ac, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3400] = { - .class_hid = BNXT_ULP_CLASS_HID_68090, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180228, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3401] = { - .class_hid = BNXT_ULP_CLASS_HID_6a88c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3402] = { - .class_hid = BNXT_ULP_CLASS_HID_6c3bc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3403] = { - .class_hid = BNXT_ULP_CLASS_HID_6ae48, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3404] = { - .class_hid = BNXT_ULP_CLASS_HID_6c978, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180292, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3405] = { - .class_hid = BNXT_ULP_CLASS_HID_3c898, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3406] = { - .class_hid = BNXT_ULP_CLASS_HID_3847c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3407] = { - .class_hid = BNXT_ULP_CLASS_HID_39308, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3408] = { - .class_hid = BNXT_ULP_CLASS_HID_38a38, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3409] = { - .class_hid = BNXT_ULP_CLASS_HID_3d234, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3410] = { - .class_hid = BNXT_ULP_CLASS_HID_3cd24, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3411] = { - .class_hid = BNXT_ULP_CLASS_HID_3dbf0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3412] = { - .class_hid = BNXT_ULP_CLASS_HID_397d4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3413] = { - .class_hid = BNXT_ULP_CLASS_HID_3b1a0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3414] = { - .class_hid = BNXT_ULP_CLASS_HID_3a8d0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3415] = { - .class_hid = BNXT_ULP_CLASS_HID_3b79c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3416] = { - .class_hid = BNXT_ULP_CLASS_HID_3ae8c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3417] = { - .class_hid = BNXT_ULP_CLASS_HID_39b7c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3418] = { - .class_hid = BNXT_ULP_CLASS_HID_3b26c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3419] = { - .class_hid = BNXT_ULP_CLASS_HID_38138, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3420] = { - .class_hid = BNXT_ULP_CLASS_HID_3b828, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3421] = { - .class_hid = BNXT_ULP_CLASS_HID_3d7a8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3422] = { - .class_hid = BNXT_ULP_CLASS_HID_3938c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3423] = { - .class_hid = BNXT_ULP_CLASS_HID_3dd64, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3424] = { - .class_hid = BNXT_ULP_CLASS_HID_39948, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3425] = { - .class_hid = BNXT_ULP_CLASS_HID_3a144, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3426] = { - .class_hid = BNXT_ULP_CLASS_HID_3d874, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3427] = { - .class_hid = BNXT_ULP_CLASS_HID_3a700, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3428] = { - .class_hid = BNXT_ULP_CLASS_HID_3de30, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3429] = { - .class_hid = BNXT_ULP_CLASS_HID_39cf0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3430] = { - .class_hid = BNXT_ULP_CLASS_HID_3b7e0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3431] = { - .class_hid = BNXT_ULP_CLASS_HID_382ac, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3432] = { - .class_hid = BNXT_ULP_CLASS_HID_3bddc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229380, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3433] = { - .class_hid = BNXT_ULP_CLASS_HID_3c5d8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3434] = { - .class_hid = BNXT_ULP_CLASS_HID_381bc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3435] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb94, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3436] = { - .class_hid = BNXT_ULP_CLASS_HID_38778, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229444, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3437] = { - .class_hid = BNXT_ULP_CLASS_HID_7c54c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3438] = { - .class_hid = BNXT_ULP_CLASS_HID_78130, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3439] = { - .class_hid = BNXT_ULP_CLASS_HID_7cb08, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3440] = { - .class_hid = BNXT_ULP_CLASS_HID_786ec, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3441] = { - .class_hid = BNXT_ULP_CLASS_HID_7aee8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3442] = { - .class_hid = BNXT_ULP_CLASS_HID_7c618, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3443] = { - .class_hid = BNXT_ULP_CLASS_HID_7d4a4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3444] = { - .class_hid = BNXT_ULP_CLASS_HID_79088, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3445] = { - .class_hid = BNXT_ULP_CLASS_HID_78a94, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3446] = { - .class_hid = BNXT_ULP_CLASS_HID_7a584, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3447] = { - .class_hid = BNXT_ULP_CLASS_HID_7b050, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3448] = { - .class_hid = BNXT_ULP_CLASS_HID_7ab40, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3449] = { - .class_hid = BNXT_ULP_CLASS_HID_79430, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3450] = { - .class_hid = BNXT_ULP_CLASS_HID_78f20, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3451] = { - .class_hid = BNXT_ULP_CLASS_HID_79dec, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3452] = { - .class_hid = BNXT_ULP_CLASS_HID_7b51c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3453] = { - .class_hid = BNXT_ULP_CLASS_HID_7d09c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3454] = { - .class_hid = BNXT_ULP_CLASS_HID_7cb8c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3455] = { - .class_hid = BNXT_ULP_CLASS_HID_7d658, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3456] = { - .class_hid = BNXT_ULP_CLASS_HID_7923c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3457] = { - .class_hid = BNXT_ULP_CLASS_HID_7ba38, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3458] = { - .class_hid = BNXT_ULP_CLASS_HID_7d528, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3459] = { - .class_hid = BNXT_ULP_CLASS_HID_7a3f4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3460] = { - .class_hid = BNXT_ULP_CLASS_HID_7dae4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3461] = { - .class_hid = BNXT_ULP_CLASS_HID_799a4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3462] = { - .class_hid = BNXT_ULP_CLASS_HID_7b0d4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3463] = { - .class_hid = BNXT_ULP_CLASS_HID_79f60, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3464] = { - .class_hid = BNXT_ULP_CLASS_HID_7b690, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245764, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3465] = { - .class_hid = BNXT_ULP_CLASS_HID_7de8c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3466] = { - .class_hid = BNXT_ULP_CLASS_HID_79a70, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3467] = { - .class_hid = BNXT_ULP_CLASS_HID_7c448, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3468] = { - .class_hid = BNXT_ULP_CLASS_HID_7802c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245828, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3469] = { - .class_hid = BNXT_ULP_CLASS_HID_86a0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3470] = { - .class_hid = BNXT_ULP_CLASS_HID_a1b0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3471] = { - .class_hid = BNXT_ULP_CLASS_HID_8c6c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3472] = { - .class_hid = BNXT_ULP_CLASS_HID_a77c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3473] = { - .class_hid = BNXT_ULP_CLASS_HID_900c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3474] = { - .class_hid = BNXT_ULP_CLASS_HID_8b1c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3475] = { - .class_hid = BNXT_ULP_CLASS_HID_99c8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3476] = { - .class_hid = BNXT_ULP_CLASS_HID_b0d8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3477] = { - .class_hid = BNXT_ULP_CLASS_HID_aad4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3478] = { - .class_hid = BNXT_ULP_CLASS_HID_c224, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3479] = { - .class_hid = BNXT_ULP_CLASS_HID_d090, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3480] = { - .class_hid = BNXT_ULP_CLASS_HID_cbe0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3481] = { - .class_hid = BNXT_ULP_CLASS_HID_b4b0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3482] = { - .class_hid = BNXT_ULP_CLASS_HID_af80, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3483] = { - .class_hid = BNXT_ULP_CLASS_HID_ba7c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3484] = { - .class_hid = BNXT_ULP_CLASS_HID_d54c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3485] = { - .class_hid = BNXT_ULP_CLASS_HID_48374, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3486] = { - .class_hid = BNXT_ULP_CLASS_HID_4ba44, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3487] = { - .class_hid = BNXT_ULP_CLASS_HID_48930, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3488] = { - .class_hid = BNXT_ULP_CLASS_HID_4a000, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3489] = { - .class_hid = BNXT_ULP_CLASS_HID_4c80c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3490] = { - .class_hid = BNXT_ULP_CLASS_HID_48420, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3491] = { - .class_hid = BNXT_ULP_CLASS_HID_4929c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3492] = { - .class_hid = BNXT_ULP_CLASS_HID_48dec, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3493] = { - .class_hid = BNXT_ULP_CLASS_HID_4a798, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3494] = { - .class_hid = BNXT_ULP_CLASS_HID_4dee8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3495] = { - .class_hid = BNXT_ULP_CLASS_HID_4ada4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3496] = { - .class_hid = BNXT_ULP_CLASS_HID_4c4b4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131076, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3497] = { - .class_hid = BNXT_ULP_CLASS_HID_4b144, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3498] = { - .class_hid = BNXT_ULP_CLASS_HID_4a854, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3499] = { - .class_hid = BNXT_ULP_CLASS_HID_4b700, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3500] = { - .class_hid = BNXT_ULP_CLASS_HID_4ae10, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131140, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3501] = { - .class_hid = BNXT_ULP_CLASS_HID_1bca0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3502] = { - .class_hid = BNXT_ULP_CLASS_HID_1d7b0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3503] = { - .class_hid = BNXT_ULP_CLASS_HID_1a26c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3504] = { - .class_hid = BNXT_ULP_CLASS_HID_1dd7c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3505] = { - .class_hid = BNXT_ULP_CLASS_HID_1860c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3506] = { - .class_hid = BNXT_ULP_CLASS_HID_1a11c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3507] = { - .class_hid = BNXT_ULP_CLASS_HID_18fc8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3508] = { - .class_hid = BNXT_ULP_CLASS_HID_1a6d8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3509] = { - .class_hid = BNXT_ULP_CLASS_HID_1c0d4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3510] = { - .class_hid = BNXT_ULP_CLASS_HID_19ce8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3511] = { - .class_hid = BNXT_ULP_CLASS_HID_1c690, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3512] = { - .class_hid = BNXT_ULP_CLASS_HID_182b4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3513] = { - .class_hid = BNXT_ULP_CLASS_HID_1aab0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3514] = { - .class_hid = BNXT_ULP_CLASS_HID_1c580, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3515] = { - .class_hid = BNXT_ULP_CLASS_HID_1d07c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3516] = { - .class_hid = BNXT_ULP_CLASS_HID_1cb4c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3517] = { - .class_hid = BNXT_ULP_CLASS_HID_5b974, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3518] = { - .class_hid = BNXT_ULP_CLASS_HID_5d044, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3519] = { - .class_hid = BNXT_ULP_CLASS_HID_5bf30, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3520] = { - .class_hid = BNXT_ULP_CLASS_HID_5d600, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3521] = { - .class_hid = BNXT_ULP_CLASS_HID_582d0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3522] = { - .class_hid = BNXT_ULP_CLASS_HID_5ba20, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3523] = { - .class_hid = BNXT_ULP_CLASS_HID_5889c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3524] = { - .class_hid = BNXT_ULP_CLASS_HID_5a3ec, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3525] = { - .class_hid = BNXT_ULP_CLASS_HID_5dd98, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3526] = { - .class_hid = BNXT_ULP_CLASS_HID_599bc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3527] = { - .class_hid = BNXT_ULP_CLASS_HID_5c3a4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3528] = { - .class_hid = BNXT_ULP_CLASS_HID_59f78, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196612, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3529] = { - .class_hid = BNXT_ULP_CLASS_HID_5a744, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3530] = { - .class_hid = BNXT_ULP_CLASS_HID_5de54, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3531] = { - .class_hid = BNXT_ULP_CLASS_HID_5ad00, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3532] = { - .class_hid = BNXT_ULP_CLASS_HID_5c410, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196676, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3533] = { - .class_hid = BNXT_ULP_CLASS_HID_cd20, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3534] = { - .class_hid = BNXT_ULP_CLASS_HID_e430, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3535] = { - .class_hid = BNXT_ULP_CLASS_HID_f2ec, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3536] = { - .class_hid = BNXT_ULP_CLASS_HID_edfc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3537] = { - .class_hid = BNXT_ULP_CLASS_HID_d68c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3538] = { - .class_hid = BNXT_ULP_CLASS_HID_f19c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3539] = { - .class_hid = BNXT_ULP_CLASS_HID_dc48, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3540] = { - .class_hid = BNXT_ULP_CLASS_HID_f758, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3541] = { - .class_hid = BNXT_ULP_CLASS_HID_d154, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3542] = { - .class_hid = BNXT_ULP_CLASS_HID_c8a4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3543] = { - .class_hid = BNXT_ULP_CLASS_HID_d710, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3544] = { - .class_hid = BNXT_ULP_CLASS_HID_d334, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3545] = { - .class_hid = BNXT_ULP_CLASS_HID_fb30, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3546] = { - .class_hid = BNXT_ULP_CLASS_HID_d200, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3547] = { - .class_hid = BNXT_ULP_CLASS_HID_e0fc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3548] = { - .class_hid = BNXT_ULP_CLASS_HID_dbcc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3549] = { - .class_hid = BNXT_ULP_CLASS_HID_4c9f4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3550] = { - .class_hid = BNXT_ULP_CLASS_HID_4e0c4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3551] = { - .class_hid = BNXT_ULP_CLASS_HID_4cfb0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3552] = { - .class_hid = BNXT_ULP_CLASS_HID_4e680, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3553] = { - .class_hid = BNXT_ULP_CLASS_HID_4d350, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3554] = { - .class_hid = BNXT_ULP_CLASS_HID_4caa0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3555] = { - .class_hid = BNXT_ULP_CLASS_HID_4d91c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3556] = { - .class_hid = BNXT_ULP_CLASS_HID_4f06c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3557] = { - .class_hid = BNXT_ULP_CLASS_HID_4ea18, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3558] = { - .class_hid = BNXT_ULP_CLASS_HID_4c568, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3559] = { - .class_hid = BNXT_ULP_CLASS_HID_4d024, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3560] = { - .class_hid = BNXT_ULP_CLASS_HID_4cb34, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393220, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3561] = { - .class_hid = BNXT_ULP_CLASS_HID_4f7c4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3562] = { - .class_hid = BNXT_ULP_CLASS_HID_4eed4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3563] = { - .class_hid = BNXT_ULP_CLASS_HID_4fd80, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3564] = { - .class_hid = BNXT_ULP_CLASS_HID_4d490, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393284, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3565] = { - .class_hid = BNXT_ULP_CLASS_HID_1e320, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3566] = { - .class_hid = BNXT_ULP_CLASS_HID_1da30, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3567] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8ec, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3568] = { - .class_hid = BNXT_ULP_CLASS_HID_1c3fc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3569] = { - .class_hid = BNXT_ULP_CLASS_HID_1cc8c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3570] = { - .class_hid = BNXT_ULP_CLASS_HID_1e79c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3571] = { - .class_hid = BNXT_ULP_CLASS_HID_1f248, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3572] = { - .class_hid = BNXT_ULP_CLASS_HID_1ed58, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3573] = { - .class_hid = BNXT_ULP_CLASS_HID_1c754, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3574] = { - .class_hid = BNXT_ULP_CLASS_HID_1c368, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3575] = { - .class_hid = BNXT_ULP_CLASS_HID_1cd10, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3576] = { - .class_hid = BNXT_ULP_CLASS_HID_1c934, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3577] = { - .class_hid = BNXT_ULP_CLASS_HID_1d130, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3578] = { - .class_hid = BNXT_ULP_CLASS_HID_1c800, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3579] = { - .class_hid = BNXT_ULP_CLASS_HID_1d6fc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3580] = { - .class_hid = BNXT_ULP_CLASS_HID_1d290, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3581] = { - .class_hid = BNXT_ULP_CLASS_HID_5fff4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3582] = { - .class_hid = BNXT_ULP_CLASS_HID_5d6c4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3583] = { - .class_hid = BNXT_ULP_CLASS_HID_5e5b0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3584] = { - .class_hid = BNXT_ULP_CLASS_HID_5dc80, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3585] = { - .class_hid = BNXT_ULP_CLASS_HID_5c950, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3586] = { - .class_hid = BNXT_ULP_CLASS_HID_5e0a0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3587] = { - .class_hid = BNXT_ULP_CLASS_HID_5cf1c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3588] = { - .class_hid = BNXT_ULP_CLASS_HID_5e66c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3589] = { - .class_hid = BNXT_ULP_CLASS_HID_5c018, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3590] = { - .class_hid = BNXT_ULP_CLASS_HID_5dc3c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3591] = { - .class_hid = BNXT_ULP_CLASS_HID_5c624, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3592] = { - .class_hid = BNXT_ULP_CLASS_HID_5c5f8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458756, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3593] = { - .class_hid = BNXT_ULP_CLASS_HID_5edc4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3594] = { - .class_hid = BNXT_ULP_CLASS_HID_5c4d4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3595] = { - .class_hid = BNXT_ULP_CLASS_HID_5d380, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3596] = { - .class_hid = BNXT_ULP_CLASS_HID_5ca90, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458820, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3597] = { - .class_hid = BNXT_ULP_CLASS_HID_abe0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3598] = { - .class_hid = BNXT_ULP_CLASS_HID_a2f0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3599] = { - .class_hid = BNXT_ULP_CLASS_HID_b1ac, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3600] = { - .class_hid = BNXT_ULP_CLASS_HID_a8bc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3601] = { - .class_hid = BNXT_ULP_CLASS_HID_b54c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3602] = { - .class_hid = BNXT_ULP_CLASS_HID_ac5c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3603] = { - .class_hid = BNXT_ULP_CLASS_HID_bb08, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3604] = { - .class_hid = BNXT_ULP_CLASS_HID_b218, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3605] = { - .class_hid = BNXT_ULP_CLASS_HID_ac14, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3606] = { - .class_hid = BNXT_ULP_CLASS_HID_e764, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3607] = { - .class_hid = BNXT_ULP_CLASS_HID_f5d0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3608] = { - .class_hid = BNXT_ULP_CLASS_HID_b1f4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3609] = { - .class_hid = BNXT_ULP_CLASS_HID_b9f0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3610] = { - .class_hid = BNXT_ULP_CLASS_HID_f0c0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3611] = { - .class_hid = BNXT_ULP_CLASS_HID_bfbc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3612] = { - .class_hid = BNXT_ULP_CLASS_HID_f68c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3613] = { - .class_hid = BNXT_ULP_CLASS_HID_4a4b4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3614] = { - .class_hid = BNXT_ULP_CLASS_HID_4bf84, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3615] = { - .class_hid = BNXT_ULP_CLASS_HID_4aa70, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3616] = { - .class_hid = BNXT_ULP_CLASS_HID_4a540, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3617] = { - .class_hid = BNXT_ULP_CLASS_HID_4ed4c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3618] = { - .class_hid = BNXT_ULP_CLASS_HID_4a960, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3619] = { - .class_hid = BNXT_ULP_CLASS_HID_4b7dc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3620] = { - .class_hid = BNXT_ULP_CLASS_HID_4af2c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3621] = { - .class_hid = BNXT_ULP_CLASS_HID_4a8d8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3622] = { - .class_hid = BNXT_ULP_CLASS_HID_4e028, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3623] = { - .class_hid = BNXT_ULP_CLASS_HID_4aee4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3624] = { - .class_hid = BNXT_ULP_CLASS_HID_4e9f4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655364, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3625] = { - .class_hid = BNXT_ULP_CLASS_HID_4b284, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3626] = { - .class_hid = BNXT_ULP_CLASS_HID_4ad94, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3627] = { - .class_hid = BNXT_ULP_CLASS_HID_4b840, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3628] = { - .class_hid = BNXT_ULP_CLASS_HID_4f350, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655428, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3629] = { - .class_hid = BNXT_ULP_CLASS_HID_1a1e0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3630] = { - .class_hid = BNXT_ULP_CLASS_HID_1f8f0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3631] = { - .class_hid = BNXT_ULP_CLASS_HID_1a7ac, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3632] = { - .class_hid = BNXT_ULP_CLASS_HID_1febc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3633] = { - .class_hid = BNXT_ULP_CLASS_HID_1ab4c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3634] = { - .class_hid = BNXT_ULP_CLASS_HID_1a25c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3635] = { - .class_hid = BNXT_ULP_CLASS_HID_1b108, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3636] = { - .class_hid = BNXT_ULP_CLASS_HID_1a818, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3637] = { - .class_hid = BNXT_ULP_CLASS_HID_1e214, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3638] = { - .class_hid = BNXT_ULP_CLASS_HID_1be28, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3639] = { - .class_hid = BNXT_ULP_CLASS_HID_1ebd0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3640] = { - .class_hid = BNXT_ULP_CLASS_HID_1a7f4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3641] = { - .class_hid = BNXT_ULP_CLASS_HID_1aff0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3642] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6c0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3643] = { - .class_hid = BNXT_ULP_CLASS_HID_1f5bc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3644] = { - .class_hid = BNXT_ULP_CLASS_HID_1b150, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3645] = { - .class_hid = BNXT_ULP_CLASS_HID_5bab4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3646] = { - .class_hid = BNXT_ULP_CLASS_HID_5f584, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3647] = { - .class_hid = BNXT_ULP_CLASS_HID_5a070, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3648] = { - .class_hid = BNXT_ULP_CLASS_HID_5fb40, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3649] = { - .class_hid = BNXT_ULP_CLASS_HID_5a410, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3650] = { - .class_hid = BNXT_ULP_CLASS_HID_5bf60, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3651] = { - .class_hid = BNXT_ULP_CLASS_HID_5addc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3652] = { - .class_hid = BNXT_ULP_CLASS_HID_5a52c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3653] = { - .class_hid = BNXT_ULP_CLASS_HID_5fed8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3654] = { - .class_hid = BNXT_ULP_CLASS_HID_5bafc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3655] = { - .class_hid = BNXT_ULP_CLASS_HID_5e4e4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3656] = { - .class_hid = BNXT_ULP_CLASS_HID_5a0b8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720900, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3657] = { - .class_hid = BNXT_ULP_CLASS_HID_5a884, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3658] = { - .class_hid = BNXT_ULP_CLASS_HID_5e394, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3659] = { - .class_hid = BNXT_ULP_CLASS_HID_5ae40, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3660] = { - .class_hid = BNXT_ULP_CLASS_HID_5e950, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720964, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3661] = { - .class_hid = BNXT_ULP_CLASS_HID_ee60, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3662] = { - .class_hid = BNXT_ULP_CLASS_HID_e970, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3663] = { - .class_hid = BNXT_ULP_CLASS_HID_f42c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3664] = { - .class_hid = BNXT_ULP_CLASS_HID_ef3c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3665] = { - .class_hid = BNXT_ULP_CLASS_HID_fbcc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3666] = { - .class_hid = BNXT_ULP_CLASS_HID_f2dc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3667] = { - .class_hid = BNXT_ULP_CLASS_HID_e188, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3668] = { - .class_hid = BNXT_ULP_CLASS_HID_f898, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3669] = { - .class_hid = BNXT_ULP_CLASS_HID_f294, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3670] = { - .class_hid = BNXT_ULP_CLASS_HID_ede4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3671] = { - .class_hid = BNXT_ULP_CLASS_HID_f850, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3672] = { - .class_hid = BNXT_ULP_CLASS_HID_f474, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3673] = { - .class_hid = BNXT_ULP_CLASS_HID_fc70, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3674] = { - .class_hid = BNXT_ULP_CLASS_HID_f740, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3675] = { - .class_hid = BNXT_ULP_CLASS_HID_e23c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3676] = { - .class_hid = BNXT_ULP_CLASS_HID_fd0c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3677] = { - .class_hid = BNXT_ULP_CLASS_HID_4eb34, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3678] = { - .class_hid = BNXT_ULP_CLASS_HID_4e204, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3679] = { - .class_hid = BNXT_ULP_CLASS_HID_4f0f0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3680] = { - .class_hid = BNXT_ULP_CLASS_HID_4ebc0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3681] = { - .class_hid = BNXT_ULP_CLASS_HID_4f490, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3682] = { - .class_hid = BNXT_ULP_CLASS_HID_4efe0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3683] = { - .class_hid = BNXT_ULP_CLASS_HID_4fa5c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3684] = { - .class_hid = BNXT_ULP_CLASS_HID_4f5ac, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3685] = { - .class_hid = BNXT_ULP_CLASS_HID_4ef58, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3686] = { - .class_hid = BNXT_ULP_CLASS_HID_4e6a8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3687] = { - .class_hid = BNXT_ULP_CLASS_HID_4f564, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3688] = { - .class_hid = BNXT_ULP_CLASS_HID_4f138, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917508, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3689] = { - .class_hid = BNXT_ULP_CLASS_HID_4f904, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3690] = { - .class_hid = BNXT_ULP_CLASS_HID_4f014, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3691] = { - .class_hid = BNXT_ULP_CLASS_HID_4fec0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3692] = { - .class_hid = BNXT_ULP_CLASS_HID_4f9d0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917572, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3693] = { - .class_hid = BNXT_ULP_CLASS_HID_1e460, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3694] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff70, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3695] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea2c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3696] = { - .class_hid = BNXT_ULP_CLASS_HID_1e53c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3697] = { - .class_hid = BNXT_ULP_CLASS_HID_1f1cc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3698] = { - .class_hid = BNXT_ULP_CLASS_HID_1e8dc, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3699] = { - .class_hid = BNXT_ULP_CLASS_HID_1f788, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3700] = { - .class_hid = BNXT_ULP_CLASS_HID_1ee98, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3701] = { - .class_hid = BNXT_ULP_CLASS_HID_1e894, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3702] = { - .class_hid = BNXT_ULP_CLASS_HID_1e4a8, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3703] = { - .class_hid = BNXT_ULP_CLASS_HID_1f364, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3704] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea74, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3705] = { - .class_hid = BNXT_ULP_CLASS_HID_1f270, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3706] = { - .class_hid = BNXT_ULP_CLASS_HID_1ed40, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3707] = { - .class_hid = BNXT_ULP_CLASS_HID_1f83c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3708] = { - .class_hid = BNXT_ULP_CLASS_HID_1f7d0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3709] = { - .class_hid = BNXT_ULP_CLASS_HID_5e134, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3710] = { - .class_hid = BNXT_ULP_CLASS_HID_5f804, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3711] = { - .class_hid = BNXT_ULP_CLASS_HID_5e6f0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3712] = { - .class_hid = BNXT_ULP_CLASS_HID_5e1c0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3713] = { - .class_hid = BNXT_ULP_CLASS_HID_5ea90, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3714] = { - .class_hid = BNXT_ULP_CLASS_HID_5e5e0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3715] = { - .class_hid = BNXT_ULP_CLASS_HID_5f05c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3716] = { - .class_hid = BNXT_ULP_CLASS_HID_5ebac, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3717] = { - .class_hid = BNXT_ULP_CLASS_HID_5e558, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3718] = { - .class_hid = BNXT_ULP_CLASS_HID_5e17c, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3719] = { - .class_hid = BNXT_ULP_CLASS_HID_5eb64, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3720] = { - .class_hid = BNXT_ULP_CLASS_HID_5e738, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983044, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3721] = { - .class_hid = BNXT_ULP_CLASS_HID_5ef04, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3722] = { - .class_hid = BNXT_ULP_CLASS_HID_5e614, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3723] = { - .class_hid = BNXT_ULP_CLASS_HID_5f4c0, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3724] = { - .class_hid = BNXT_ULP_CLASS_HID_5f0e4, - .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 983108, - .flow_pattern_id = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3725] = { - .class_hid = BNXT_ULP_CLASS_HID_5802, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3726] = { - .class_hid = BNXT_ULP_CLASS_HID_5e46, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3727] = { - .class_hid = BNXT_ULP_CLASS_HID_1d76, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3728] = { - .class_hid = BNXT_ULP_CLASS_HID_02ba, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3729] = { - .class_hid = BNXT_ULP_CLASS_HID_32a2, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3730] = { - .class_hid = BNXT_ULP_CLASS_HID_38e6, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3731] = { - .class_hid = BNXT_ULP_CLASS_HID_52ca, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3732] = { - .class_hid = BNXT_ULP_CLASS_HID_580e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3733] = { - .class_hid = BNXT_ULP_CLASS_HID_44996, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3734] = { - .class_hid = BNXT_ULP_CLASS_HID_410e6, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3735] = { - .class_hid = BNXT_ULP_CLASS_HID_42036, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3736] = { - .class_hid = BNXT_ULP_CLASS_HID_4264a, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3737] = { - .class_hid = BNXT_ULP_CLASS_HID_45ffe, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3738] = { - .class_hid = BNXT_ULP_CLASS_HID_44532, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3739] = { - .class_hid = BNXT_ULP_CLASS_HID_4399e, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3740] = { - .class_hid = BNXT_ULP_CLASS_HID_43fd2, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3741] = { - .class_hid = BNXT_ULP_CLASS_HID_23da0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3742] = { - .class_hid = BNXT_ULP_CLASS_HID_2239c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3743] = { - .class_hid = BNXT_ULP_CLASS_HID_207fc, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3744] = { - .class_hid = BNXT_ULP_CLASS_HID_20d38, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3745] = { - .class_hid = BNXT_ULP_CLASS_HID_25e34, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3746] = { - .class_hid = BNXT_ULP_CLASS_HID_24470, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3747] = { - .class_hid = BNXT_ULP_CLASS_HID_22850, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3748] = { - .class_hid = BNXT_ULP_CLASS_HID_2518c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3749] = { - .class_hid = BNXT_ULP_CLASS_HID_20970, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3750] = { - .class_hid = BNXT_ULP_CLASS_HID_20eac, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3751] = { - .class_hid = BNXT_ULP_CLASS_HID_2128c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3752] = { - .class_hid = BNXT_ULP_CLASS_HID_218c8, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3753] = { - .class_hid = BNXT_ULP_CLASS_HID_22dc4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3754] = { - .class_hid = BNXT_ULP_CLASS_HID_25300, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3755] = { - .class_hid = BNXT_ULP_CLASS_HID_23760, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3756] = { - .class_hid = BNXT_ULP_CLASS_HID_23d5c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3757] = { - .class_hid = BNXT_ULP_CLASS_HID_63694, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3758] = { - .class_hid = BNXT_ULP_CLASS_HID_63cd0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3759] = { - .class_hid = BNXT_ULP_CLASS_HID_60030, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3760] = { - .class_hid = BNXT_ULP_CLASS_HID_6066c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3761] = { - .class_hid = BNXT_ULP_CLASS_HID_65b68, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3762] = { - .class_hid = BNXT_ULP_CLASS_HID_640a4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3763] = { - .class_hid = BNXT_ULP_CLASS_HID_62484, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3764] = { - .class_hid = BNXT_ULP_CLASS_HID_62ac0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3765] = { - .class_hid = BNXT_ULP_CLASS_HID_605a4, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3766] = { - .class_hid = BNXT_ULP_CLASS_HID_60be0, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3767] = { - .class_hid = BNXT_ULP_CLASS_HID_64a8c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3768] = { - .class_hid = BNXT_ULP_CLASS_HID_6153c, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3769] = { - .class_hid = BNXT_ULP_CLASS_HID_62638, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3770] = { - .class_hid = BNXT_ULP_CLASS_HID_62c74, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3771] = { - .class_hid = BNXT_ULP_CLASS_HID_63054, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3772] = { - .class_hid = BNXT_ULP_CLASS_HID_63990, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3773] = { - .class_hid = BNXT_ULP_CLASS_HID_9a98, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3774] = { - .class_hid = BNXT_ULP_CLASS_HID_80a4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3775] = { - .class_hid = BNXT_ULP_CLASS_HID_c3b0, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3776] = { - .class_hid = BNXT_ULP_CLASS_HID_c9fc, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3777] = { - .class_hid = BNXT_ULP_CLASS_HID_bf0c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3778] = { - .class_hid = BNXT_ULP_CLASS_HID_a548, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3779] = { - .class_hid = BNXT_ULP_CLASS_HID_8968, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3780] = { - .class_hid = BNXT_ULP_CLASS_HID_8eb4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3781] = { - .class_hid = BNXT_ULP_CLASS_HID_497ac, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3782] = { - .class_hid = BNXT_ULP_CLASS_HID_49de8, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3783] = { - .class_hid = BNXT_ULP_CLASS_HID_4dcc4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3784] = { - .class_hid = BNXT_ULP_CLASS_HID_4c200, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3785] = { - .class_hid = BNXT_ULP_CLASS_HID_4b850, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3786] = { - .class_hid = BNXT_ULP_CLASS_HID_4a19c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3787] = { - .class_hid = BNXT_ULP_CLASS_HID_485bc, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3788] = { - .class_hid = BNXT_ULP_CLASS_HID_48bf8, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3789] = { - .class_hid = BNXT_ULP_CLASS_HID_1b098, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3790] = { - .class_hid = BNXT_ULP_CLASS_HID_1b6a4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3791] = { - .class_hid = BNXT_ULP_CLASS_HID_19ac4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3792] = { - .class_hid = BNXT_ULP_CLASS_HID_18000, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3793] = { - .class_hid = BNXT_ULP_CLASS_HID_1d50c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3794] = { - .class_hid = BNXT_ULP_CLASS_HID_1db48, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3795] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf68, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3796] = { - .class_hid = BNXT_ULP_CLASS_HID_1a4b4, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3797] = { - .class_hid = BNXT_ULP_CLASS_HID_58dac, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3798] = { - .class_hid = BNXT_ULP_CLASS_HID_5b3e8, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3799] = { - .class_hid = BNXT_ULP_CLASS_HID_59708, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3800] = { - .class_hid = BNXT_ULP_CLASS_HID_59d54, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3801] = { - .class_hid = BNXT_ULP_CLASS_HID_5ae50, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3802] = { - .class_hid = BNXT_ULP_CLASS_HID_5d79c, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3803] = { - .class_hid = BNXT_ULP_CLASS_HID_5bbbc, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3804] = { - .class_hid = BNXT_ULP_CLASS_HID_5a1f8, - .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3805] = { - .class_hid = BNXT_ULP_CLASS_HID_5822, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3806] = { - .class_hid = BNXT_ULP_CLASS_HID_5e66, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3807] = { - .class_hid = BNXT_ULP_CLASS_HID_1d56, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3808] = { - .class_hid = BNXT_ULP_CLASS_HID_029a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3809] = { - .class_hid = BNXT_ULP_CLASS_HID_3282, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3810] = { - .class_hid = BNXT_ULP_CLASS_HID_38c6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3811] = { - .class_hid = BNXT_ULP_CLASS_HID_52ea, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3812] = { - .class_hid = BNXT_ULP_CLASS_HID_582e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3813] = { - .class_hid = BNXT_ULP_CLASS_HID_51ba, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3814] = { - .class_hid = BNXT_ULP_CLASS_HID_57fe, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3815] = { - .class_hid = BNXT_ULP_CLASS_HID_12ee, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3816] = { - .class_hid = BNXT_ULP_CLASS_HID_1832, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3817] = { - .class_hid = BNXT_ULP_CLASS_HID_081a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3818] = { - .class_hid = BNXT_ULP_CLASS_HID_0e5e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3819] = { - .class_hid = BNXT_ULP_CLASS_HID_2802, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3820] = { - .class_hid = BNXT_ULP_CLASS_HID_2e46, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3821] = { - .class_hid = BNXT_ULP_CLASS_HID_4556e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3822] = { - .class_hid = BNXT_ULP_CLASS_HID_45ab2, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3823] = { - .class_hid = BNXT_ULP_CLASS_HID_419a2, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3824] = { - .class_hid = BNXT_ULP_CLASS_HID_41fe6, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3825] = { - .class_hid = BNXT_ULP_CLASS_HID_40fce, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3826] = { - .class_hid = BNXT_ULP_CLASS_HID_43512, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3827] = { - .class_hid = BNXT_ULP_CLASS_HID_42f36, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3828] = { - .class_hid = BNXT_ULP_CLASS_HID_4557a, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3829] = { - .class_hid = BNXT_ULP_CLASS_HID_42a86, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3830] = { - .class_hid = BNXT_ULP_CLASS_HID_450ca, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3831] = { - .class_hid = BNXT_ULP_CLASS_HID_44aee, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3832] = { - .class_hid = BNXT_ULP_CLASS_HID_4157e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3833] = { - .class_hid = BNXT_ULP_CLASS_HID_40566, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3834] = { - .class_hid = BNXT_ULP_CLASS_HID_40aaa, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3835] = { - .class_hid = BNXT_ULP_CLASS_HID_4254e, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3836] = { - .class_hid = BNXT_ULP_CLASS_HID_42a92, - .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3837] = { - .class_hid = BNXT_ULP_CLASS_HID_449b6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3838] = { - .class_hid = BNXT_ULP_CLASS_HID_410c6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3839] = { - .class_hid = BNXT_ULP_CLASS_HID_42016, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3840] = { - .class_hid = BNXT_ULP_CLASS_HID_4266a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3841] = { - .class_hid = BNXT_ULP_CLASS_HID_45fde, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3842] = { - .class_hid = BNXT_ULP_CLASS_HID_44512, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3843] = { - .class_hid = BNXT_ULP_CLASS_HID_439be, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3844] = { - .class_hid = BNXT_ULP_CLASS_HID_43ff2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3845] = { - .class_hid = BNXT_ULP_CLASS_HID_63682, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3846] = { - .class_hid = BNXT_ULP_CLASS_HID_63cc6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3847] = { - .class_hid = BNXT_ULP_CLASS_HID_61162, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3848] = { - .class_hid = BNXT_ULP_CLASS_HID_616a6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3849] = { - .class_hid = BNXT_ULP_CLASS_HID_60c2a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3850] = { - .class_hid = BNXT_ULP_CLASS_HID_6326e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3851] = { - .class_hid = BNXT_ULP_CLASS_HID_645be, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3852] = { - .class_hid = BNXT_ULP_CLASS_HID_64bf2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3853] = { - .class_hid = BNXT_ULP_CLASS_HID_50082, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3854] = { - .class_hid = BNXT_ULP_CLASS_HID_506c6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3855] = { - .class_hid = BNXT_ULP_CLASS_HID_55616, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3856] = { - .class_hid = BNXT_ULP_CLASS_HID_55c6a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3857] = { - .class_hid = BNXT_ULP_CLASS_HID_5162a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3858] = { - .class_hid = BNXT_ULP_CLASS_HID_51c6e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3859] = { - .class_hid = BNXT_ULP_CLASS_HID_52fbe, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3860] = { - .class_hid = BNXT_ULP_CLASS_HID_555f2, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3861] = { - .class_hid = BNXT_ULP_CLASS_HID_72c82, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3862] = { - .class_hid = BNXT_ULP_CLASS_HID_752c6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3863] = { - .class_hid = BNXT_ULP_CLASS_HID_70762, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3864] = { - .class_hid = BNXT_ULP_CLASS_HID_70ca6, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3865] = { - .class_hid = BNXT_ULP_CLASS_HID_7222a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3866] = { - .class_hid = BNXT_ULP_CLASS_HID_7286e, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3867] = { - .class_hid = BNXT_ULP_CLASS_HID_71c8a, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3868] = { - .class_hid = BNXT_ULP_CLASS_HID_702ce, - .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3869] = { - .class_hid = BNXT_ULP_CLASS_HID_5842, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3870] = { - .class_hid = BNXT_ULP_CLASS_HID_5e06, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3871] = { - .class_hid = BNXT_ULP_CLASS_HID_1d36, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3872] = { - .class_hid = BNXT_ULP_CLASS_HID_02fa, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4096, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3873] = { - .class_hid = BNXT_ULP_CLASS_HID_32e2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3874] = { - .class_hid = BNXT_ULP_CLASS_HID_38a6, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3875] = { - .class_hid = BNXT_ULP_CLASS_HID_528a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3876] = { - .class_hid = BNXT_ULP_CLASS_HID_584e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 6144, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3877] = { - .class_hid = BNXT_ULP_CLASS_HID_51da, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3878] = { - .class_hid = BNXT_ULP_CLASS_HID_579e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3879] = { - .class_hid = BNXT_ULP_CLASS_HID_128e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3880] = { - .class_hid = BNXT_ULP_CLASS_HID_1852, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 12288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3881] = { - .class_hid = BNXT_ULP_CLASS_HID_087a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3882] = { - .class_hid = BNXT_ULP_CLASS_HID_0e3e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3883] = { - .class_hid = BNXT_ULP_CLASS_HID_2862, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3884] = { - .class_hid = BNXT_ULP_CLASS_HID_2e26, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 14336, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3885] = { - .class_hid = BNXT_ULP_CLASS_HID_4550e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3886] = { - .class_hid = BNXT_ULP_CLASS_HID_45ad2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3887] = { - .class_hid = BNXT_ULP_CLASS_HID_419c2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3888] = { - .class_hid = BNXT_ULP_CLASS_HID_41f86, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 20480, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3889] = { - .class_hid = BNXT_ULP_CLASS_HID_40fae, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3890] = { - .class_hid = BNXT_ULP_CLASS_HID_43572, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3891] = { - .class_hid = BNXT_ULP_CLASS_HID_42f56, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3892] = { - .class_hid = BNXT_ULP_CLASS_HID_4551a, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 22528, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3893] = { - .class_hid = BNXT_ULP_CLASS_HID_42ae6, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3894] = { - .class_hid = BNXT_ULP_CLASS_HID_450aa, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3895] = { - .class_hid = BNXT_ULP_CLASS_HID_44a8e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3896] = { - .class_hid = BNXT_ULP_CLASS_HID_4151e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 28672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3897] = { - .class_hid = BNXT_ULP_CLASS_HID_40506, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3898] = { - .class_hid = BNXT_ULP_CLASS_HID_40aca, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3899] = { - .class_hid = BNXT_ULP_CLASS_HID_4252e, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3900] = { - .class_hid = BNXT_ULP_CLASS_HID_42af2, - .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 30720, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3901] = { - .class_hid = BNXT_ULP_CLASS_HID_449d6, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3902] = { - .class_hid = BNXT_ULP_CLASS_HID_410a6, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3903] = { - .class_hid = BNXT_ULP_CLASS_HID_42076, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3904] = { - .class_hid = BNXT_ULP_CLASS_HID_4260a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 16384, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3905] = { - .class_hid = BNXT_ULP_CLASS_HID_45fbe, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3906] = { - .class_hid = BNXT_ULP_CLASS_HID_44572, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3907] = { - .class_hid = BNXT_ULP_CLASS_HID_439de, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3908] = { - .class_hid = BNXT_ULP_CLASS_HID_43f92, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 24576, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3909] = { - .class_hid = BNXT_ULP_CLASS_HID_636e2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3910] = { - .class_hid = BNXT_ULP_CLASS_HID_63ca6, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3911] = { - .class_hid = BNXT_ULP_CLASS_HID_61102, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3912] = { - .class_hid = BNXT_ULP_CLASS_HID_616c6, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3913] = { - .class_hid = BNXT_ULP_CLASS_HID_60c4a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3914] = { - .class_hid = BNXT_ULP_CLASS_HID_6320e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3915] = { - .class_hid = BNXT_ULP_CLASS_HID_645de, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3916] = { - .class_hid = BNXT_ULP_CLASS_HID_64b92, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 57344, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3917] = { - .class_hid = BNXT_ULP_CLASS_HID_500e2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3918] = { - .class_hid = BNXT_ULP_CLASS_HID_506a6, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3919] = { - .class_hid = BNXT_ULP_CLASS_HID_55676, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3920] = { - .class_hid = BNXT_ULP_CLASS_HID_55c0a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 81920, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3921] = { - .class_hid = BNXT_ULP_CLASS_HID_5164a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3922] = { - .class_hid = BNXT_ULP_CLASS_HID_51c0e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3923] = { - .class_hid = BNXT_ULP_CLASS_HID_52fde, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3924] = { - .class_hid = BNXT_ULP_CLASS_HID_55592, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 90112, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3925] = { - .class_hid = BNXT_ULP_CLASS_HID_72ce2, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3926] = { - .class_hid = BNXT_ULP_CLASS_HID_752a6, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3927] = { - .class_hid = BNXT_ULP_CLASS_HID_70702, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3928] = { - .class_hid = BNXT_ULP_CLASS_HID_70cc6, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3929] = { - .class_hid = BNXT_ULP_CLASS_HID_7224a, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3930] = { - .class_hid = BNXT_ULP_CLASS_HID_7280e, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3931] = { - .class_hid = BNXT_ULP_CLASS_HID_71cea, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3932] = { - .class_hid = BNXT_ULP_CLASS_HID_702ae, - .class_tid = 2, - .hdr_sig_id = 7, - .flow_sig_id = 122880, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3933] = { - .class_hid = BNXT_ULP_CLASS_HID_23dc0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3934] = { - .class_hid = BNXT_ULP_CLASS_HID_223fc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3935] = { - .class_hid = BNXT_ULP_CLASS_HID_2079c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3936] = { - .class_hid = BNXT_ULP_CLASS_HID_20d58, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3937] = { - .class_hid = BNXT_ULP_CLASS_HID_25e54, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3938] = { - .class_hid = BNXT_ULP_CLASS_HID_24410, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3939] = { - .class_hid = BNXT_ULP_CLASS_HID_22830, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3940] = { - .class_hid = BNXT_ULP_CLASS_HID_251ec, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3941] = { - .class_hid = BNXT_ULP_CLASS_HID_20910, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3942] = { - .class_hid = BNXT_ULP_CLASS_HID_20ecc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3943] = { - .class_hid = BNXT_ULP_CLASS_HID_212ec, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3944] = { - .class_hid = BNXT_ULP_CLASS_HID_218a8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3945] = { - .class_hid = BNXT_ULP_CLASS_HID_22da4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3946] = { - .class_hid = BNXT_ULP_CLASS_HID_25360, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3947] = { - .class_hid = BNXT_ULP_CLASS_HID_23700, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3948] = { - .class_hid = BNXT_ULP_CLASS_HID_23d3c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3949] = { - .class_hid = BNXT_ULP_CLASS_HID_636f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3950] = { - .class_hid = BNXT_ULP_CLASS_HID_63cb0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3951] = { - .class_hid = BNXT_ULP_CLASS_HID_60050, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3952] = { - .class_hid = BNXT_ULP_CLASS_HID_6060c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3953] = { - .class_hid = BNXT_ULP_CLASS_HID_65b08, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3954] = { - .class_hid = BNXT_ULP_CLASS_HID_640c4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3955] = { - .class_hid = BNXT_ULP_CLASS_HID_624e4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3956] = { - .class_hid = BNXT_ULP_CLASS_HID_62aa0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3957] = { - .class_hid = BNXT_ULP_CLASS_HID_605c4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3958] = { - .class_hid = BNXT_ULP_CLASS_HID_60b80, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3959] = { - .class_hid = BNXT_ULP_CLASS_HID_64aec, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3960] = { - .class_hid = BNXT_ULP_CLASS_HID_6155c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3961] = { - .class_hid = BNXT_ULP_CLASS_HID_62658, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3962] = { - .class_hid = BNXT_ULP_CLASS_HID_62c14, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3963] = { - .class_hid = BNXT_ULP_CLASS_HID_63034, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3964] = { - .class_hid = BNXT_ULP_CLASS_HID_639f0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3965] = { - .class_hid = BNXT_ULP_CLASS_HID_353c0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3966] = { - .class_hid = BNXT_ULP_CLASS_HID_359fc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3967] = { - .class_hid = BNXT_ULP_CLASS_HID_33d9c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3968] = { - .class_hid = BNXT_ULP_CLASS_HID_32358, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3969] = { - .class_hid = BNXT_ULP_CLASS_HID_31908, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3970] = { - .class_hid = BNXT_ULP_CLASS_HID_31ec4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3971] = { - .class_hid = BNXT_ULP_CLASS_HID_35e30, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3972] = { - .class_hid = BNXT_ULP_CLASS_HID_347ec, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3973] = { - .class_hid = BNXT_ULP_CLASS_HID_33f10, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3974] = { - .class_hid = BNXT_ULP_CLASS_HID_324cc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3975] = { - .class_hid = BNXT_ULP_CLASS_HID_308ec, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3976] = { - .class_hid = BNXT_ULP_CLASS_HID_30ea8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3977] = { - .class_hid = BNXT_ULP_CLASS_HID_343a4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3978] = { - .class_hid = BNXT_ULP_CLASS_HID_34960, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3979] = { - .class_hid = BNXT_ULP_CLASS_HID_32d00, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3980] = { - .class_hid = BNXT_ULP_CLASS_HID_3533c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3981] = { - .class_hid = BNXT_ULP_CLASS_HID_72cf4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3982] = { - .class_hid = BNXT_ULP_CLASS_HID_752b0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3983] = { - .class_hid = BNXT_ULP_CLASS_HID_73650, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3984] = { - .class_hid = BNXT_ULP_CLASS_HID_73c0c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3985] = { - .class_hid = BNXT_ULP_CLASS_HID_7123c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3986] = { - .class_hid = BNXT_ULP_CLASS_HID_71bf8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3987] = { - .class_hid = BNXT_ULP_CLASS_HID_75ae4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3988] = { - .class_hid = BNXT_ULP_CLASS_HID_740a0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3989] = { - .class_hid = BNXT_ULP_CLASS_HID_73bc4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3990] = { - .class_hid = BNXT_ULP_CLASS_HID_72180, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3991] = { - .class_hid = BNXT_ULP_CLASS_HID_705a0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3992] = { - .class_hid = BNXT_ULP_CLASS_HID_70b5c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3993] = { - .class_hid = BNXT_ULP_CLASS_HID_75c58, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3994] = { - .class_hid = BNXT_ULP_CLASS_HID_74214, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3995] = { - .class_hid = BNXT_ULP_CLASS_HID_72634, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3996] = { - .class_hid = BNXT_ULP_CLASS_HID_72ff0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3997] = { - .class_hid = BNXT_ULP_CLASS_HID_2a6c0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3998] = { - .class_hid = BNXT_ULP_CLASS_HID_2acfc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [3999] = { - .class_hid = BNXT_ULP_CLASS_HID_2b09c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4000] = { - .class_hid = BNXT_ULP_CLASS_HID_2b658, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4001] = { - .class_hid = BNXT_ULP_CLASS_HID_2cb54, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4002] = { - .class_hid = BNXT_ULP_CLASS_HID_295c4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4003] = { - .class_hid = BNXT_ULP_CLASS_HID_2d530, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4004] = { - .class_hid = BNXT_ULP_CLASS_HID_2daec, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4005] = { - .class_hid = BNXT_ULP_CLASS_HID_2b210, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4006] = { - .class_hid = BNXT_ULP_CLASS_HID_2bbcc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4007] = { - .class_hid = BNXT_ULP_CLASS_HID_29fec, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4008] = { - .class_hid = BNXT_ULP_CLASS_HID_285a8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4009] = { - .class_hid = BNXT_ULP_CLASS_HID_2d6a4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4010] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc60, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163840, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4011] = { - .class_hid = BNXT_ULP_CLASS_HID_2a000, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4012] = { - .class_hid = BNXT_ULP_CLASS_HID_2a63c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 163904, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4013] = { - .class_hid = BNXT_ULP_CLASS_HID_6a3f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4014] = { - .class_hid = BNXT_ULP_CLASS_HID_6a9b0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4015] = { - .class_hid = BNXT_ULP_CLASS_HID_68d50, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4016] = { - .class_hid = BNXT_ULP_CLASS_HID_6b30c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4017] = { - .class_hid = BNXT_ULP_CLASS_HID_6c408, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4018] = { - .class_hid = BNXT_ULP_CLASS_HID_6cdc4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4019] = { - .class_hid = BNXT_ULP_CLASS_HID_6d1e4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4020] = { - .class_hid = BNXT_ULP_CLASS_HID_6d7a0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4021] = { - .class_hid = BNXT_ULP_CLASS_HID_68ec4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4022] = { - .class_hid = BNXT_ULP_CLASS_HID_6b480, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4023] = { - .class_hid = BNXT_ULP_CLASS_HID_698a0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4024] = { - .class_hid = BNXT_ULP_CLASS_HID_69e5c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4025] = { - .class_hid = BNXT_ULP_CLASS_HID_6d358, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4026] = { - .class_hid = BNXT_ULP_CLASS_HID_6d914, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180224, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4027] = { - .class_hid = BNXT_ULP_CLASS_HID_6bd34, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4028] = { - .class_hid = BNXT_ULP_CLASS_HID_6a2f0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 180288, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4029] = { - .class_hid = BNXT_ULP_CLASS_HID_3dcc0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4030] = { - .class_hid = BNXT_ULP_CLASS_HID_3c2fc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4031] = { - .class_hid = BNXT_ULP_CLASS_HID_3a69c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4032] = { - .class_hid = BNXT_ULP_CLASS_HID_3ac58, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4033] = { - .class_hid = BNXT_ULP_CLASS_HID_38208, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4034] = { - .class_hid = BNXT_ULP_CLASS_HID_38bc4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4035] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb30, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4036] = { - .class_hid = BNXT_ULP_CLASS_HID_395a0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4037] = { - .class_hid = BNXT_ULP_CLASS_HID_3a810, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4038] = { - .class_hid = BNXT_ULP_CLASS_HID_3d1cc, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4039] = { - .class_hid = BNXT_ULP_CLASS_HID_3b5ec, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4040] = { - .class_hid = BNXT_ULP_CLASS_HID_3bba8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4041] = { - .class_hid = BNXT_ULP_CLASS_HID_39158, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4042] = { - .class_hid = BNXT_ULP_CLASS_HID_39714, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229376, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4043] = { - .class_hid = BNXT_ULP_CLASS_HID_3d600, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4044] = { - .class_hid = BNXT_ULP_CLASS_HID_3dc3c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 229440, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4045] = { - .class_hid = BNXT_ULP_CLASS_HID_7d9f4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4046] = { - .class_hid = BNXT_ULP_CLASS_HID_7dfb0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4047] = { - .class_hid = BNXT_ULP_CLASS_HID_7a350, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4048] = { - .class_hid = BNXT_ULP_CLASS_HID_7a90c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4049] = { - .class_hid = BNXT_ULP_CLASS_HID_79f3c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4050] = { - .class_hid = BNXT_ULP_CLASS_HID_784f8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4051] = { - .class_hid = BNXT_ULP_CLASS_HID_7c7e4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4052] = { - .class_hid = BNXT_ULP_CLASS_HID_7cda0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4053] = { - .class_hid = BNXT_ULP_CLASS_HID_7a4c4, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4054] = { - .class_hid = BNXT_ULP_CLASS_HID_7aa80, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4055] = { - .class_hid = BNXT_ULP_CLASS_HID_78ea0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4056] = { - .class_hid = BNXT_ULP_CLASS_HID_7b45c, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4057] = { - .class_hid = BNXT_ULP_CLASS_HID_7c958, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4058] = { - .class_hid = BNXT_ULP_CLASS_HID_793c8, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245760, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4059] = { - .class_hid = BNXT_ULP_CLASS_HID_7d334, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4060] = { - .class_hid = BNXT_ULP_CLASS_HID_7d8f0, - .class_tid = 2, - .hdr_sig_id = 8, - .flow_sig_id = 245824, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4061] = { - .class_hid = BNXT_ULP_CLASS_HID_9ab8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4062] = { - .class_hid = BNXT_ULP_CLASS_HID_8084, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4063] = { - .class_hid = BNXT_ULP_CLASS_HID_c390, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4064] = { - .class_hid = BNXT_ULP_CLASS_HID_c9dc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4065] = { - .class_hid = BNXT_ULP_CLASS_HID_bf2c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4066] = { - .class_hid = BNXT_ULP_CLASS_HID_a568, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4067] = { - .class_hid = BNXT_ULP_CLASS_HID_8948, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4068] = { - .class_hid = BNXT_ULP_CLASS_HID_8e94, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4069] = { - .class_hid = BNXT_ULP_CLASS_HID_4978c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4070] = { - .class_hid = BNXT_ULP_CLASS_HID_49dc8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4071] = { - .class_hid = BNXT_ULP_CLASS_HID_4dce4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4072] = { - .class_hid = BNXT_ULP_CLASS_HID_4c220, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4073] = { - .class_hid = BNXT_ULP_CLASS_HID_4b870, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4074] = { - .class_hid = BNXT_ULP_CLASS_HID_4a1bc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131072, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4075] = { - .class_hid = BNXT_ULP_CLASS_HID_4859c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4076] = { - .class_hid = BNXT_ULP_CLASS_HID_48bd8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 131136, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4077] = { - .class_hid = BNXT_ULP_CLASS_HID_1b0b8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4078] = { - .class_hid = BNXT_ULP_CLASS_HID_1b684, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4079] = { - .class_hid = BNXT_ULP_CLASS_HID_19ae4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4080] = { - .class_hid = BNXT_ULP_CLASS_HID_18020, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4081] = { - .class_hid = BNXT_ULP_CLASS_HID_1d52c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4082] = { - .class_hid = BNXT_ULP_CLASS_HID_1db68, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4083] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf48, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4084] = { - .class_hid = BNXT_ULP_CLASS_HID_1a494, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4085] = { - .class_hid = BNXT_ULP_CLASS_HID_58d8c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4086] = { - .class_hid = BNXT_ULP_CLASS_HID_5b3c8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4087] = { - .class_hid = BNXT_ULP_CLASS_HID_59728, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4088] = { - .class_hid = BNXT_ULP_CLASS_HID_59d74, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4089] = { - .class_hid = BNXT_ULP_CLASS_HID_5ae70, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4090] = { - .class_hid = BNXT_ULP_CLASS_HID_5d7bc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196608, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4091] = { - .class_hid = BNXT_ULP_CLASS_HID_5bb9c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4092] = { - .class_hid = BNXT_ULP_CLASS_HID_5a1d8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 196672, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4093] = { - .class_hid = BNXT_ULP_CLASS_HID_c138, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4094] = { - .class_hid = BNXT_ULP_CLASS_HID_c704, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4095] = { - .class_hid = BNXT_ULP_CLASS_HID_c610, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4096] = { - .class_hid = BNXT_ULP_CLASS_HID_d0a0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4097] = { - .class_hid = BNXT_ULP_CLASS_HID_e5ac, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4098] = { - .class_hid = BNXT_ULP_CLASS_HID_ebe8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4099] = { - .class_hid = BNXT_ULP_CLASS_HID_cfc8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4100] = { - .class_hid = BNXT_ULP_CLASS_HID_f514, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4101] = { - .class_hid = BNXT_ULP_CLASS_HID_4da0c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4102] = { - .class_hid = BNXT_ULP_CLASS_HID_4c048, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4103] = { - .class_hid = BNXT_ULP_CLASS_HID_4c364, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4104] = { - .class_hid = BNXT_ULP_CLASS_HID_4c8a0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4105] = { - .class_hid = BNXT_ULP_CLASS_HID_4fef0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4106] = { - .class_hid = BNXT_ULP_CLASS_HID_4e43c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4107] = { - .class_hid = BNXT_ULP_CLASS_HID_4c81c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4108] = { - .class_hid = BNXT_ULP_CLASS_HID_4ce58, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 393280, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4109] = { - .class_hid = BNXT_ULP_CLASS_HID_1f738, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4110] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd04, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4111] = { - .class_hid = BNXT_ULP_CLASS_HID_1c164, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4112] = { - .class_hid = BNXT_ULP_CLASS_HID_1c6a0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4113] = { - .class_hid = BNXT_ULP_CLASS_HID_1dbac, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4114] = { - .class_hid = BNXT_ULP_CLASS_HID_1c1e8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4115] = { - .class_hid = BNXT_ULP_CLASS_HID_1e5c8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4116] = { - .class_hid = BNXT_ULP_CLASS_HID_1eb14, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4117] = { - .class_hid = BNXT_ULP_CLASS_HID_5f00c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4118] = { - .class_hid = BNXT_ULP_CLASS_HID_5f648, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4119] = { - .class_hid = BNXT_ULP_CLASS_HID_5dda8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4120] = { - .class_hid = BNXT_ULP_CLASS_HID_5c3f4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4121] = { - .class_hid = BNXT_ULP_CLASS_HID_5d4f0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4122] = { - .class_hid = BNXT_ULP_CLASS_HID_5da3c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4123] = { - .class_hid = BNXT_ULP_CLASS_HID_5fe1c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4124] = { - .class_hid = BNXT_ULP_CLASS_HID_5e458, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 458816, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4125] = { - .class_hid = BNXT_ULP_CLASS_HID_bc78, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4126] = { - .class_hid = BNXT_ULP_CLASS_HID_a244, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4127] = { - .class_hid = BNXT_ULP_CLASS_HID_e550, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4128] = { - .class_hid = BNXT_ULP_CLASS_HID_ea9c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4129] = { - .class_hid = BNXT_ULP_CLASS_HID_a0ec, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4130] = { - .class_hid = BNXT_ULP_CLASS_HID_a628, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4131] = { - .class_hid = BNXT_ULP_CLASS_HID_aa08, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4132] = { - .class_hid = BNXT_ULP_CLASS_HID_b054, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4133] = { - .class_hid = BNXT_ULP_CLASS_HID_4b94c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4134] = { - .class_hid = BNXT_ULP_CLASS_HID_4be88, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4135] = { - .class_hid = BNXT_ULP_CLASS_HID_4e1a4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4136] = { - .class_hid = BNXT_ULP_CLASS_HID_4e7e0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4137] = { - .class_hid = BNXT_ULP_CLASS_HID_4bd30, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4138] = { - .class_hid = BNXT_ULP_CLASS_HID_4a37c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655360, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4139] = { - .class_hid = BNXT_ULP_CLASS_HID_4a75c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4140] = { - .class_hid = BNXT_ULP_CLASS_HID_4ac98, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 655424, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4141] = { - .class_hid = BNXT_ULP_CLASS_HID_1b278, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4142] = { - .class_hid = BNXT_ULP_CLASS_HID_1b844, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4143] = { - .class_hid = BNXT_ULP_CLASS_HID_1bfa4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4144] = { - .class_hid = BNXT_ULP_CLASS_HID_1a5e0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4145] = { - .class_hid = BNXT_ULP_CLASS_HID_1f6ec, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4146] = { - .class_hid = BNXT_ULP_CLASS_HID_1fc28, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4147] = { - .class_hid = BNXT_ULP_CLASS_HID_1a008, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4148] = { - .class_hid = BNXT_ULP_CLASS_HID_1a654, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4149] = { - .class_hid = BNXT_ULP_CLASS_HID_5af4c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4150] = { - .class_hid = BNXT_ULP_CLASS_HID_5b488, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4151] = { - .class_hid = BNXT_ULP_CLASS_HID_5b8e8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4152] = { - .class_hid = BNXT_ULP_CLASS_HID_5be34, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4153] = { - .class_hid = BNXT_ULP_CLASS_HID_5f330, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4154] = { - .class_hid = BNXT_ULP_CLASS_HID_5f97c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720896, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4155] = { - .class_hid = BNXT_ULP_CLASS_HID_5bd5c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4156] = { - .class_hid = BNXT_ULP_CLASS_HID_5a298, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 720960, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4157] = { - .class_hid = BNXT_ULP_CLASS_HID_e2f8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4158] = { - .class_hid = BNXT_ULP_CLASS_HID_e8c4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4159] = { - .class_hid = BNXT_ULP_CLASS_HID_ebd0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4160] = { - .class_hid = BNXT_ULP_CLASS_HID_f260, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4161] = { - .class_hid = BNXT_ULP_CLASS_HID_e76c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4162] = { - .class_hid = BNXT_ULP_CLASS_HID_eca8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4163] = { - .class_hid = BNXT_ULP_CLASS_HID_f088, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4164] = { - .class_hid = BNXT_ULP_CLASS_HID_f6d4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4165] = { - .class_hid = BNXT_ULP_CLASS_HID_4ffcc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4166] = { - .class_hid = BNXT_ULP_CLASS_HID_4e508, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4167] = { - .class_hid = BNXT_ULP_CLASS_HID_4e424, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4168] = { - .class_hid = BNXT_ULP_CLASS_HID_4ea60, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4169] = { - .class_hid = BNXT_ULP_CLASS_HID_4e3b0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4170] = { - .class_hid = BNXT_ULP_CLASS_HID_4e9fc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917504, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4171] = { - .class_hid = BNXT_ULP_CLASS_HID_4eddc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4172] = { - .class_hid = BNXT_ULP_CLASS_HID_4f318, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 917568, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4173] = { - .class_hid = BNXT_ULP_CLASS_HID_1f8f8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4174] = { - .class_hid = BNXT_ULP_CLASS_HID_1fec4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4175] = { - .class_hid = BNXT_ULP_CLASS_HID_1e224, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4176] = { - .class_hid = BNXT_ULP_CLASS_HID_1e860, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4177] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd6c, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4178] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2a8, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4179] = { - .class_hid = BNXT_ULP_CLASS_HID_1e688, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4180] = { - .class_hid = BNXT_ULP_CLASS_HID_1ecd4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4181] = { - .class_hid = BNXT_ULP_CLASS_HID_5f5cc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4182] = { - .class_hid = BNXT_ULP_CLASS_HID_5fb08, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4183] = { - .class_hid = BNXT_ULP_CLASS_HID_5ff68, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4184] = { - .class_hid = BNXT_ULP_CLASS_HID_5e4b4, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4185] = { - .class_hid = BNXT_ULP_CLASS_HID_5f9b0, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4186] = { - .class_hid = BNXT_ULP_CLASS_HID_5fffc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983040, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4187] = { - .class_hid = BNXT_ULP_CLASS_HID_5e3dc, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4188] = { - .class_hid = BNXT_ULP_CLASS_HID_5e918, - .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4189] = { - .class_hid = BNXT_ULP_CLASS_HID_23de0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4190] = { - .class_hid = BNXT_ULP_CLASS_HID_223dc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4191] = { - .class_hid = BNXT_ULP_CLASS_HID_207bc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4192] = { - .class_hid = BNXT_ULP_CLASS_HID_20d78, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4193] = { - .class_hid = BNXT_ULP_CLASS_HID_25e74, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4194] = { - .class_hid = BNXT_ULP_CLASS_HID_24430, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4195] = { - .class_hid = BNXT_ULP_CLASS_HID_22810, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4196] = { - .class_hid = BNXT_ULP_CLASS_HID_251cc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4197] = { - .class_hid = BNXT_ULP_CLASS_HID_20930, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4198] = { - .class_hid = BNXT_ULP_CLASS_HID_20eec, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4199] = { - .class_hid = BNXT_ULP_CLASS_HID_212cc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4200] = { - .class_hid = BNXT_ULP_CLASS_HID_21888, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4201] = { - .class_hid = BNXT_ULP_CLASS_HID_22d84, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4202] = { - .class_hid = BNXT_ULP_CLASS_HID_25340, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32768, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4203] = { - .class_hid = BNXT_ULP_CLASS_HID_23720, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4204] = { - .class_hid = BNXT_ULP_CLASS_HID_23d1c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 32832, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4205] = { - .class_hid = BNXT_ULP_CLASS_HID_636d4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4206] = { - .class_hid = BNXT_ULP_CLASS_HID_63c90, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4207] = { - .class_hid = BNXT_ULP_CLASS_HID_60070, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4208] = { - .class_hid = BNXT_ULP_CLASS_HID_6062c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4209] = { - .class_hid = BNXT_ULP_CLASS_HID_65b28, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4210] = { - .class_hid = BNXT_ULP_CLASS_HID_640e4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4211] = { - .class_hid = BNXT_ULP_CLASS_HID_624c4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4212] = { - .class_hid = BNXT_ULP_CLASS_HID_62a80, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4213] = { - .class_hid = BNXT_ULP_CLASS_HID_605e4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4214] = { - .class_hid = BNXT_ULP_CLASS_HID_60ba0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4215] = { - .class_hid = BNXT_ULP_CLASS_HID_64acc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4216] = { - .class_hid = BNXT_ULP_CLASS_HID_6157c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4217] = { - .class_hid = BNXT_ULP_CLASS_HID_62678, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4218] = { - .class_hid = BNXT_ULP_CLASS_HID_62c34, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49152, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4219] = { - .class_hid = BNXT_ULP_CLASS_HID_63014, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4220] = { - .class_hid = BNXT_ULP_CLASS_HID_639d0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 49216, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4221] = { - .class_hid = BNXT_ULP_CLASS_HID_353e0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4222] = { - .class_hid = BNXT_ULP_CLASS_HID_359dc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4223] = { - .class_hid = BNXT_ULP_CLASS_HID_33dbc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4224] = { - .class_hid = BNXT_ULP_CLASS_HID_32378, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4225] = { - .class_hid = BNXT_ULP_CLASS_HID_31928, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4226] = { - .class_hid = BNXT_ULP_CLASS_HID_31ee4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4227] = { - .class_hid = BNXT_ULP_CLASS_HID_35e10, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4228] = { - .class_hid = BNXT_ULP_CLASS_HID_347cc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4229] = { - .class_hid = BNXT_ULP_CLASS_HID_33f30, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4230] = { - .class_hid = BNXT_ULP_CLASS_HID_324ec, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4231] = { - .class_hid = BNXT_ULP_CLASS_HID_308cc, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4232] = { - .class_hid = BNXT_ULP_CLASS_HID_30e88, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4233] = { - .class_hid = BNXT_ULP_CLASS_HID_34384, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4234] = { - .class_hid = BNXT_ULP_CLASS_HID_34940, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98304, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4235] = { - .class_hid = BNXT_ULP_CLASS_HID_32d20, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4236] = { - .class_hid = BNXT_ULP_CLASS_HID_3531c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 98368, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4237] = { - .class_hid = BNXT_ULP_CLASS_HID_72cd4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4238] = { - .class_hid = BNXT_ULP_CLASS_HID_75290, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4239] = { - .class_hid = BNXT_ULP_CLASS_HID_73670, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4240] = { - .class_hid = BNXT_ULP_CLASS_HID_73c2c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4241] = { - .class_hid = BNXT_ULP_CLASS_HID_7121c, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4242] = { - .class_hid = BNXT_ULP_CLASS_HID_71bd8, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4243] = { - .class_hid = BNXT_ULP_CLASS_HID_75ac4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4244] = { - .class_hid = BNXT_ULP_CLASS_HID_74080, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4245] = { - .class_hid = BNXT_ULP_CLASS_HID_73be4, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4246] = { - .class_hid = BNXT_ULP_CLASS_HID_721a0, - .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, - [4247] = { - .class_hid = BNXT_ULP_CLASS_HID_70580, + [359] = { + .class_hid = BNXT_ULP_CLASS_HID_1af0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, + .hdr_sig_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, - [4248] = { - .class_hid = BNXT_ULP_CLASS_HID_70b7c, + [360] = { + .class_hid = BNXT_ULP_CLASS_HID_15d4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, + .hdr_sig_id = 2, + .flow_sig_id = 49220, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, - [4249] = { - .class_hid = BNXT_ULP_CLASS_HID_75c78, + [361] = { + .class_hid = BNXT_ULP_CLASS_HID_1dd0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4250] = { - .class_hid = BNXT_ULP_CLASS_HID_74234, + [362] = { + .class_hid = BNXT_ULP_CLASS_HID_14f4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114688, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131076, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4251] = { - .class_hid = BNXT_ULP_CLASS_HID_72614, + [363] = { + .class_hid = BNXT_ULP_CLASS_HID_70b0, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4252] = { - .class_hid = BNXT_ULP_CLASS_HID_72fd0, + [364] = { + .class_hid = BNXT_ULP_CLASS_HID_4854, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 114752, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 131140, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4253] = { - .class_hid = BNXT_ULP_CLASS_HID_2a6e0, + [365] = { + .class_hid = BNXT_ULP_CLASS_HID_3dd4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4254] = { - .class_hid = BNXT_ULP_CLASS_HID_2acdc, + [366] = { + .class_hid = BNXT_ULP_CLASS_HID_34f8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4255] = { - .class_hid = BNXT_ULP_CLASS_HID_2b0bc, + [367] = { + .class_hid = BNXT_ULP_CLASS_HID_09e8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4256] = { - .class_hid = BNXT_ULP_CLASS_HID_2b678, + [368] = { + .class_hid = BNXT_ULP_CLASS_HID_008c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, + .hdr_sig_id = 3, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4257] = { - .class_hid = BNXT_ULP_CLASS_HID_2cb74, + [369] = { + .class_hid = BNXT_ULP_CLASS_HID_34e6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } }, - [4258] = { - .class_hid = BNXT_ULP_CLASS_HID_295e4, + [370] = { + .class_hid = BNXT_ULP_CLASS_HID_0c02, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 4100, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } }, - [4259] = { - .class_hid = BNXT_ULP_CLASS_HID_2d510, + [371] = { + .class_hid = BNXT_ULP_CLASS_HID_1c9e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } }, - [4260] = { - .class_hid = BNXT_ULP_CLASS_HID_2dacc, + [372] = { + .class_hid = BNXT_ULP_CLASS_HID_17ba, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 6148, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } }, - [4261] = { - .class_hid = BNXT_ULP_CLASS_HID_2b230, + [373] = { + .class_hid = BNXT_ULP_CLASS_HID_429e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } }, - [4262] = { - .class_hid = BNXT_ULP_CLASS_HID_2bbec, + [374] = { + .class_hid = BNXT_ULP_CLASS_HID_5dba, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 12292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } }, - [4263] = { - .class_hid = BNXT_ULP_CLASS_HID_29fcc, + [375] = { + .class_hid = BNXT_ULP_CLASS_HID_2a16, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } }, - [4264] = { - .class_hid = BNXT_ULP_CLASS_HID_28588, + [376] = { + .class_hid = BNXT_ULP_CLASS_HID_2532, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 14340, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } }, - [4265] = { - .class_hid = BNXT_ULP_CLASS_HID_2d684, + [377] = { + .class_hid = BNXT_ULP_CLASS_HID_2da2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4266] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc40, + [378] = { + .class_hid = BNXT_ULP_CLASS_HID_24fe, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163840, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 20484, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4267] = { - .class_hid = BNXT_ULP_CLASS_HID_2a020, + [379] = { + .class_hid = BNXT_ULP_CLASS_HID_355a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4268] = { - .class_hid = BNXT_ULP_CLASS_HID_2a61c, + [380] = { + .class_hid = BNXT_ULP_CLASS_HID_0c76, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 163904, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 22532, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4269] = { - .class_hid = BNXT_ULP_CLASS_HID_6a3d4, + [381] = { + .class_hid = BNXT_ULP_CLASS_HID_13e6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4270] = { - .class_hid = BNXT_ULP_CLASS_HID_6a990, + [382] = { + .class_hid = BNXT_ULP_CLASS_HID_7276, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 28676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4271] = { - .class_hid = BNXT_ULP_CLASS_HID_68d70, + [383] = { + .class_hid = BNXT_ULP_CLASS_HID_42d2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4272] = { - .class_hid = BNXT_ULP_CLASS_HID_6b32c, + [384] = { + .class_hid = BNXT_ULP_CLASS_HID_5dee, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, + .hdr_sig_id = 4, + .flow_sig_id = 30724, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4273] = { - .class_hid = BNXT_ULP_CLASS_HID_6c428, + [385] = { + .class_hid = BNXT_ULP_CLASS_HID_59de, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } }, - [4274] = { - .class_hid = BNXT_ULP_CLASS_HID_6cde4, + [386] = { + .class_hid = BNXT_ULP_CLASS_HID_513a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 16388, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } }, - [4275] = { - .class_hid = BNXT_ULP_CLASS_HID_6d1c4, + [387] = { + .class_hid = BNXT_ULP_CLASS_HID_1c12, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } }, - [4276] = { - .class_hid = BNXT_ULP_CLASS_HID_6d780, + [388] = { + .class_hid = BNXT_ULP_CLASS_HID_177e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 24580, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } }, - [4277] = { - .class_hid = BNXT_ULP_CLASS_HID_68ee4, + [389] = { + .class_hid = BNXT_ULP_CLASS_HID_0e92, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } }, - [4278] = { - .class_hid = BNXT_ULP_CLASS_HID_6b4a0, + [390] = { + .class_hid = BNXT_ULP_CLASS_HID_09fe, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 49156, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } }, - [4279] = { - .class_hid = BNXT_ULP_CLASS_HID_69880, + [391] = { + .class_hid = BNXT_ULP_CLASS_HID_5c1a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } }, - [4280] = { - .class_hid = BNXT_ULP_CLASS_HID_69e7c, + [392] = { + .class_hid = BNXT_ULP_CLASS_HID_5746, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 57348, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } }, - [4281] = { - .class_hid = BNXT_ULP_CLASS_HID_6d378, + [393] = { + .class_hid = BNXT_ULP_CLASS_HID_79da, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4282] = { - .class_hid = BNXT_ULP_CLASS_HID_6d934, + [394] = { + .class_hid = BNXT_ULP_CLASS_HID_7106, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180224, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 81924, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4283] = { - .class_hid = BNXT_ULP_CLASS_HID_6bd14, + [395] = { + .class_hid = BNXT_ULP_CLASS_HID_3c1e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4284] = { - .class_hid = BNXT_ULP_CLASS_HID_6a2d0, + [396] = { + .class_hid = BNXT_ULP_CLASS_HID_377a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 180288, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 90116, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4285] = { - .class_hid = BNXT_ULP_CLASS_HID_3dce0, + [397] = { + .class_hid = BNXT_ULP_CLASS_HID_2e9e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4286] = { - .class_hid = BNXT_ULP_CLASS_HID_3c2dc, + [398] = { + .class_hid = BNXT_ULP_CLASS_HID_29fa, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4287] = { - .class_hid = BNXT_ULP_CLASS_HID_3a6bc, + [399] = { + .class_hid = BNXT_ULP_CLASS_HID_14d2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 122880, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4288] = { - .class_hid = BNXT_ULP_CLASS_HID_3ac78, + [400] = { + .class_hid = BNXT_ULP_CLASS_HID_7742, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, + .hdr_sig_id = 5, + .flow_sig_id = 122884, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4289] = { - .class_hid = BNXT_ULP_CLASS_HID_38228, + [401] = { + .class_hid = BNXT_ULP_CLASS_HID_3706, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 4096, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } }, - [4290] = { - .class_hid = BNXT_ULP_CLASS_HID_38be4, + [402] = { + .class_hid = BNXT_ULP_CLASS_HID_0fe2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 4100, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } }, - [4291] = { - .class_hid = BNXT_ULP_CLASS_HID_3cb10, + [403] = { + .class_hid = BNXT_ULP_CLASS_HID_1f7e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 6144, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } }, - [4292] = { - .class_hid = BNXT_ULP_CLASS_HID_39580, + [404] = { + .class_hid = BNXT_ULP_CLASS_HID_145a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 6148, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } }, - [4293] = { - .class_hid = BNXT_ULP_CLASS_HID_3a830, + [405] = { + .class_hid = BNXT_ULP_CLASS_HID_417e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } }, - [4294] = { - .class_hid = BNXT_ULP_CLASS_HID_3d1ec, + [406] = { + .class_hid = BNXT_ULP_CLASS_HID_5e5a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 12292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } }, - [4295] = { - .class_hid = BNXT_ULP_CLASS_HID_3b5cc, + [407] = { + .class_hid = BNXT_ULP_CLASS_HID_29f6, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } }, - [4296] = { - .class_hid = BNXT_ULP_CLASS_HID_3bb88, + [408] = { + .class_hid = BNXT_ULP_CLASS_HID_26d2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 14340, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } }, - [4297] = { - .class_hid = BNXT_ULP_CLASS_HID_39178, + [409] = { + .class_hid = BNXT_ULP_CLASS_HID_2e42, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4298] = { - .class_hid = BNXT_ULP_CLASS_HID_39734, + [410] = { + .class_hid = BNXT_ULP_CLASS_HID_271e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229376, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 20484, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4299] = { - .class_hid = BNXT_ULP_CLASS_HID_3d620, + [411] = { + .class_hid = BNXT_ULP_CLASS_HID_36ba, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4300] = { - .class_hid = BNXT_ULP_CLASS_HID_3dc1c, + [412] = { + .class_hid = BNXT_ULP_CLASS_HID_0f96, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 229440, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 22532, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4301] = { - .class_hid = BNXT_ULP_CLASS_HID_7d9d4, + [413] = { + .class_hid = BNXT_ULP_CLASS_HID_1006, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4302] = { - .class_hid = BNXT_ULP_CLASS_HID_7df90, + [414] = { + .class_hid = BNXT_ULP_CLASS_HID_7196, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 28676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4303] = { - .class_hid = BNXT_ULP_CLASS_HID_7a370, + [415] = { + .class_hid = BNXT_ULP_CLASS_HID_4132, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4304] = { - .class_hid = BNXT_ULP_CLASS_HID_7a92c, + [416] = { + .class_hid = BNXT_ULP_CLASS_HID_5e0e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, + .hdr_sig_id = 6, + .flow_sig_id = 30724, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4305] = { - .class_hid = BNXT_ULP_CLASS_HID_79f1c, + [417] = { + .class_hid = BNXT_ULP_CLASS_HID_59fe, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } }, - [4306] = { - .class_hid = BNXT_ULP_CLASS_HID_784d8, + [418] = { + .class_hid = BNXT_ULP_CLASS_HID_511a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 16388, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } }, - [4307] = { - .class_hid = BNXT_ULP_CLASS_HID_7c7c4, + [419] = { + .class_hid = BNXT_ULP_CLASS_HID_1c32, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 24576, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } }, - [4308] = { - .class_hid = BNXT_ULP_CLASS_HID_7cd80, + [420] = { + .class_hid = BNXT_ULP_CLASS_HID_175e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 24580, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } }, - [4309] = { - .class_hid = BNXT_ULP_CLASS_HID_7a4e4, + [421] = { + .class_hid = BNXT_ULP_CLASS_HID_0eb2, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 49152, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } }, - [4310] = { - .class_hid = BNXT_ULP_CLASS_HID_7aaa0, + [422] = { + .class_hid = BNXT_ULP_CLASS_HID_09de, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 49156, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } }, - [4311] = { - .class_hid = BNXT_ULP_CLASS_HID_78e80, + [423] = { + .class_hid = BNXT_ULP_CLASS_HID_5c3a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } }, - [4312] = { - .class_hid = BNXT_ULP_CLASS_HID_7b47c, + [424] = { + .class_hid = BNXT_ULP_CLASS_HID_5766, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 57348, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } }, - [4313] = { - .class_hid = BNXT_ULP_CLASS_HID_7c978, + [425] = { + .class_hid = BNXT_ULP_CLASS_HID_79fa, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81920, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4314] = { - .class_hid = BNXT_ULP_CLASS_HID_793e8, + [426] = { + .class_hid = BNXT_ULP_CLASS_HID_7126, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245760, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 81924, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4315] = { - .class_hid = BNXT_ULP_CLASS_HID_7d314, + [427] = { + .class_hid = BNXT_ULP_CLASS_HID_3c3e, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90112, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4316] = { - .class_hid = BNXT_ULP_CLASS_HID_7d8d0, + [428] = { + .class_hid = BNXT_ULP_CLASS_HID_375a, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 245824, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 90116, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4317] = { - .class_hid = BNXT_ULP_CLASS_HID_9ad8, + [429] = { + .class_hid = BNXT_ULP_CLASS_HID_2ebe, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4318] = { - .class_hid = BNXT_ULP_CLASS_HID_80e4, + [430] = { + .class_hid = BNXT_ULP_CLASS_HID_29da, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4319] = { - .class_hid = BNXT_ULP_CLASS_HID_c3f0, + [431] = { + .class_hid = BNXT_ULP_CLASS_HID_14f2, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 122880, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4320] = { - .class_hid = BNXT_ULP_CLASS_HID_c9bc, + [432] = { + .class_hid = BNXT_ULP_CLASS_HID_7762, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, + .hdr_sig_id = 7, + .flow_sig_id = 122884, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4321] = { - .class_hid = BNXT_ULP_CLASS_HID_bf4c, + [433] = { + .class_hid = BNXT_ULP_CLASS_HID_19e8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4322] = { - .class_hid = BNXT_ULP_CLASS_HID_a508, + [434] = { + .class_hid = BNXT_ULP_CLASS_HID_110c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32772, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4323] = { - .class_hid = BNXT_ULP_CLASS_HID_8928, + [435] = { + .class_hid = BNXT_ULP_CLASS_HID_4d48, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4324] = { - .class_hid = BNXT_ULP_CLASS_HID_8ef4, + [436] = { + .class_hid = BNXT_ULP_CLASS_HID_446c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 32836, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4325] = { - .class_hid = BNXT_ULP_CLASS_HID_497ec, + [437] = { + .class_hid = BNXT_ULP_CLASS_HID_0eac, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 49152, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4326] = { - .class_hid = BNXT_ULP_CLASS_HID_49da8, + [438] = { + .class_hid = BNXT_ULP_CLASS_HID_09c0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 49156, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4327] = { - .class_hid = BNXT_ULP_CLASS_HID_4dc84, + [439] = { + .class_hid = BNXT_ULP_CLASS_HID_1ad0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 49216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4328] = { - .class_hid = BNXT_ULP_CLASS_HID_4c240, + [440] = { + .class_hid = BNXT_ULP_CLASS_HID_15f4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 49220, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4329] = { - .class_hid = BNXT_ULP_CLASS_HID_4b810, + [441] = { + .class_hid = BNXT_ULP_CLASS_HID_39ec, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4330] = { - .class_hid = BNXT_ULP_CLASS_HID_4a1dc, + [442] = { + .class_hid = BNXT_ULP_CLASS_HID_3100, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131072, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4331] = { - .class_hid = BNXT_ULP_CLASS_HID_485fc, + [443] = { + .class_hid = BNXT_ULP_CLASS_HID_0210, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4332] = { - .class_hid = BNXT_ULP_CLASS_HID_48bb8, + [444] = { + .class_hid = BNXT_ULP_CLASS_HID_1d34, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 131136, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4333] = { - .class_hid = BNXT_ULP_CLASS_HID_1b0d8, + [445] = { + .class_hid = BNXT_ULP_CLASS_HID_2ea0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4334] = { - .class_hid = BNXT_ULP_CLASS_HID_1b6e4, + [446] = { + .class_hid = BNXT_ULP_CLASS_HID_29c4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4335] = { - .class_hid = BNXT_ULP_CLASS_HID_19a84, + [447] = { + .class_hid = BNXT_ULP_CLASS_HID_3ad4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4336] = { - .class_hid = BNXT_ULP_CLASS_HID_18040, + [448] = { + .class_hid = BNXT_ULP_CLASS_HID_35e8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 114756, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4337] = { - .class_hid = BNXT_ULP_CLASS_HID_1d54c, + [449] = { + .class_hid = BNXT_ULP_CLASS_HID_5d80, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 163840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4338] = { - .class_hid = BNXT_ULP_CLASS_HID_1db08, + [450] = { + .class_hid = BNXT_ULP_CLASS_HID_54a4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 163844, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4339] = { - .class_hid = BNXT_ULP_CLASS_HID_1bf28, + [451] = { + .class_hid = BNXT_ULP_CLASS_HID_29b4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 163904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4340] = { - .class_hid = BNXT_ULP_CLASS_HID_1a4f4, + [452] = { + .class_hid = BNXT_ULP_CLASS_HID_20c8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 163908, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4341] = { - .class_hid = BNXT_ULP_CLASS_HID_58dec, + [453] = { + .class_hid = BNXT_ULP_CLASS_HID_7244, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 180224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4342] = { - .class_hid = BNXT_ULP_CLASS_HID_5b3a8, + [454] = { + .class_hid = BNXT_ULP_CLASS_HID_4d98, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 180228, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4343] = { - .class_hid = BNXT_ULP_CLASS_HID_59748, + [455] = { + .class_hid = BNXT_ULP_CLASS_HID_5e68, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 180288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4344] = { - .class_hid = BNXT_ULP_CLASS_HID_59d14, + [456] = { + .class_hid = BNXT_ULP_CLASS_HID_598c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 180292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4345] = { - .class_hid = BNXT_ULP_CLASS_HID_5ae10, + [457] = { + .class_hid = BNXT_ULP_CLASS_HID_1248, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4346] = { - .class_hid = BNXT_ULP_CLASS_HID_5d7dc, + [458] = { + .class_hid = BNXT_ULP_CLASS_HID_74d8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196608, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4347] = { - .class_hid = BNXT_ULP_CLASS_HID_5bbfc, + [459] = { + .class_hid = BNXT_ULP_CLASS_HID_49a8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4348] = { - .class_hid = BNXT_ULP_CLASS_HID_5a1b8, + [460] = { + .class_hid = BNXT_ULP_CLASS_HID_40cc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 196672, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4349] = { - .class_hid = BNXT_ULP_CLASS_HID_c158, + [461] = { + .class_hid = BNXT_ULP_CLASS_HID_0b0c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4350] = { - .class_hid = BNXT_ULP_CLASS_HID_c764, + [462] = { + .class_hid = BNXT_ULP_CLASS_HID_0220, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4351] = { - .class_hid = BNXT_ULP_CLASS_HID_c670, + [463] = { + .class_hid = BNXT_ULP_CLASS_HID_1730, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4352] = { - .class_hid = BNXT_ULP_CLASS_HID_d0c0, + [464] = { + .class_hid = BNXT_ULP_CLASS_HID_7980, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, + .hdr_sig_id = 8, + .flow_sig_id = 245828, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4353] = { - .class_hid = BNXT_ULP_CLASS_HID_e5cc, + [465] = { + .class_hid = BNXT_ULP_CLASS_HID_1db0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4354] = { - .class_hid = BNXT_ULP_CLASS_HID_eb88, + [466] = { + .class_hid = BNXT_ULP_CLASS_HID_1494, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 131076, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4355] = { - .class_hid = BNXT_ULP_CLASS_HID_cfa8, + [467] = { + .class_hid = BNXT_ULP_CLASS_HID_70d0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4356] = { - .class_hid = BNXT_ULP_CLASS_HID_f574, + [468] = { + .class_hid = BNXT_ULP_CLASS_HID_4834, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 131140, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4357] = { - .class_hid = BNXT_ULP_CLASS_HID_4da6c, + [469] = { + .class_hid = BNXT_ULP_CLASS_HID_3db4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4358] = { - .class_hid = BNXT_ULP_CLASS_HID_4c028, + [470] = { + .class_hid = BNXT_ULP_CLASS_HID_3498, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4359] = { - .class_hid = BNXT_ULP_CLASS_HID_4c304, + [471] = { + .class_hid = BNXT_ULP_CLASS_HID_0988, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4360] = { - .class_hid = BNXT_ULP_CLASS_HID_4c8c0, + [472] = { + .class_hid = BNXT_ULP_CLASS_HID_00ec, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4361] = { - .class_hid = BNXT_ULP_CLASS_HID_4fe90, + [473] = { + .class_hid = BNXT_ULP_CLASS_HID_3f44, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 9, .flow_sig_id = 393216, - .flow_pattern_id = 1, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4362] = { - .class_hid = BNXT_ULP_CLASS_HID_4e45c, + [474] = { + .class_hid = BNXT_ULP_CLASS_HID_36a8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393216, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 393220, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4363] = { - .class_hid = BNXT_ULP_CLASS_HID_4c87c, + [475] = { + .class_hid = BNXT_ULP_CLASS_HID_0b58, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 9, .flow_sig_id = 393280, - .flow_pattern_id = 1, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4364] = { - .class_hid = BNXT_ULP_CLASS_HID_4ce38, + [476] = { + .class_hid = BNXT_ULP_CLASS_HID_02bc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 393280, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 393284, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4365] = { - .class_hid = BNXT_ULP_CLASS_HID_1f758, + [477] = { + .class_hid = BNXT_ULP_CLASS_HID_5f48, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 9, .flow_sig_id = 458752, - .flow_pattern_id = 1, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4366] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd64, + [478] = { + .class_hid = BNXT_ULP_CLASS_HID_56ac, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 458756, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4367] = { - .class_hid = BNXT_ULP_CLASS_HID_1c104, + [479] = { + .class_hid = BNXT_ULP_CLASS_HID_2b5c, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 9, .flow_sig_id = 458816, - .flow_pattern_id = 1, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4368] = { - .class_hid = BNXT_ULP_CLASS_HID_1c6c0, + [480] = { + .class_hid = BNXT_ULP_CLASS_HID_2280, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 458820, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4369] = { - .class_hid = BNXT_ULP_CLASS_HID_1dbcc, + [481] = { + .class_hid = BNXT_ULP_CLASS_HID_4000, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4370] = { - .class_hid = BNXT_ULP_CLASS_HID_1c188, + [482] = { + .class_hid = BNXT_ULP_CLASS_HID_5b64, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655364, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4371] = { - .class_hid = BNXT_ULP_CLASS_HID_1e5a8, + [483] = { + .class_hid = BNXT_ULP_CLASS_HID_2c14, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4372] = { - .class_hid = BNXT_ULP_CLASS_HID_1eb74, + [484] = { + .class_hid = BNXT_ULP_CLASS_HID_2778, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 655428, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4373] = { - .class_hid = BNXT_ULP_CLASS_HID_5f06c, + [485] = { + .class_hid = BNXT_ULP_CLASS_HID_18f8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4374] = { - .class_hid = BNXT_ULP_CLASS_HID_5f628, + [486] = { + .class_hid = BNXT_ULP_CLASS_HID_13dc, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720900, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4375] = { - .class_hid = BNXT_ULP_CLASS_HID_5ddc8, + [487] = { + .class_hid = BNXT_ULP_CLASS_HID_4c18, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4376] = { - .class_hid = BNXT_ULP_CLASS_HID_5c394, + [488] = { + .class_hid = BNXT_ULP_CLASS_HID_477c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 720964, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4377] = { - .class_hid = BNXT_ULP_CLASS_HID_5d490, + [489] = { + .class_hid = BNXT_ULP_CLASS_HID_1a88, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917504, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4378] = { - .class_hid = BNXT_ULP_CLASS_HID_5da5c, + [490] = { + .class_hid = BNXT_ULP_CLASS_HID_15ec, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458752, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917508, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4379] = { - .class_hid = BNXT_ULP_CLASS_HID_5fe7c, + [491] = { + .class_hid = BNXT_ULP_CLASS_HID_4e28, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917568, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4380] = { - .class_hid = BNXT_ULP_CLASS_HID_5e438, + [492] = { + .class_hid = BNXT_ULP_CLASS_HID_490c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 458816, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 917572, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4381] = { - .class_hid = BNXT_ULP_CLASS_HID_bc18, + [493] = { + .class_hid = BNXT_ULP_CLASS_HID_3a8c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4382] = { - .class_hid = BNXT_ULP_CLASS_HID_a224, + [494] = { + .class_hid = BNXT_ULP_CLASS_HID_35f0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 983044, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4383] = { - .class_hid = BNXT_ULP_CLASS_HID_e530, + [495] = { + .class_hid = BNXT_ULP_CLASS_HID_06e0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4384] = { - .class_hid = BNXT_ULP_CLASS_HID_eafc, + [496] = { + .class_hid = BNXT_ULP_CLASS_HID_01c4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, + .hdr_sig_id = 9, + .flow_sig_id = 983108, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4385] = { - .class_hid = BNXT_ULP_CLASS_HID_a08c, + [497] = { + .class_hid = BNXT_ULP_CLASS_HID_1a08, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 32768, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } }, - [4386] = { - .class_hid = BNXT_ULP_CLASS_HID_a648, + [498] = { + .class_hid = BNXT_ULP_CLASS_HID_12ec, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 32772, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } }, - [4387] = { - .class_hid = BNXT_ULP_CLASS_HID_aa68, + [499] = { + .class_hid = BNXT_ULP_CLASS_HID_4ea8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 32832, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } }, - [4388] = { - .class_hid = BNXT_ULP_CLASS_HID_b034, + [500] = { + .class_hid = BNXT_ULP_CLASS_HID_478c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 32836, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } }, - [4389] = { - .class_hid = BNXT_ULP_CLASS_HID_4b92c, + [501] = { + .class_hid = BNXT_ULP_CLASS_HID_0d4c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 49152, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } }, - [4390] = { - .class_hid = BNXT_ULP_CLASS_HID_4bee8, + [502] = { + .class_hid = BNXT_ULP_CLASS_HID_0a20, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 49156, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } }, - [4391] = { - .class_hid = BNXT_ULP_CLASS_HID_4e1c4, + [503] = { + .class_hid = BNXT_ULP_CLASS_HID_1930, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 49216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } }, - [4392] = { - .class_hid = BNXT_ULP_CLASS_HID_4e780, + [504] = { + .class_hid = BNXT_ULP_CLASS_HID_1614, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 49220, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } }, - [4393] = { - .class_hid = BNXT_ULP_CLASS_HID_4bd50, + [505] = { + .class_hid = BNXT_ULP_CLASS_HID_3a0c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 98304, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4394] = { - .class_hid = BNXT_ULP_CLASS_HID_4a31c, + [506] = { + .class_hid = BNXT_ULP_CLASS_HID_32e0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655360, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 98308, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4395] = { - .class_hid = BNXT_ULP_CLASS_HID_4a73c, + [507] = { + .class_hid = BNXT_ULP_CLASS_HID_01f0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 98368, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4396] = { - .class_hid = BNXT_ULP_CLASS_HID_4acf8, + [508] = { + .class_hid = BNXT_ULP_CLASS_HID_1ed4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 655424, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 98372, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4397] = { - .class_hid = BNXT_ULP_CLASS_HID_1b218, + [509] = { + .class_hid = BNXT_ULP_CLASS_HID_2d40, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4398] = { - .class_hid = BNXT_ULP_CLASS_HID_1b824, + [510] = { + .class_hid = BNXT_ULP_CLASS_HID_2a24, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 114692, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4399] = { - .class_hid = BNXT_ULP_CLASS_HID_1bfc4, + [511] = { + .class_hid = BNXT_ULP_CLASS_HID_3934, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4400] = { - .class_hid = BNXT_ULP_CLASS_HID_1a580, + [512] = { + .class_hid = BNXT_ULP_CLASS_HID_3608, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 114756, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4401] = { - .class_hid = BNXT_ULP_CLASS_HID_1f68c, + [513] = { + .class_hid = BNXT_ULP_CLASS_HID_5e60, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4402] = { - .class_hid = BNXT_ULP_CLASS_HID_1fc48, + [514] = { + .class_hid = BNXT_ULP_CLASS_HID_5744, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 163844, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4403] = { - .class_hid = BNXT_ULP_CLASS_HID_1a068, + [515] = { + .class_hid = BNXT_ULP_CLASS_HID_2a54, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4404] = { - .class_hid = BNXT_ULP_CLASS_HID_1a634, + [516] = { + .class_hid = BNXT_ULP_CLASS_HID_2328, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 163908, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4405] = { - .class_hid = BNXT_ULP_CLASS_HID_5af2c, + [517] = { + .class_hid = BNXT_ULP_CLASS_HID_71a4, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4406] = { - .class_hid = BNXT_ULP_CLASS_HID_5b4e8, + [518] = { + .class_hid = BNXT_ULP_CLASS_HID_4e78, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180228, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4407] = { - .class_hid = BNXT_ULP_CLASS_HID_5b888, + [519] = { + .class_hid = BNXT_ULP_CLASS_HID_5d88, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4408] = { - .class_hid = BNXT_ULP_CLASS_HID_5be54, + [520] = { + .class_hid = BNXT_ULP_CLASS_HID_5a6c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 180292, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4409] = { - .class_hid = BNXT_ULP_CLASS_HID_5f350, + [521] = { + .class_hid = BNXT_ULP_CLASS_HID_11a8, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229376, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4410] = { - .class_hid = BNXT_ULP_CLASS_HID_5f91c, + [522] = { + .class_hid = BNXT_ULP_CLASS_HID_7738, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720896, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229380, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4411] = { - .class_hid = BNXT_ULP_CLASS_HID_5bd3c, + [523] = { + .class_hid = BNXT_ULP_CLASS_HID_4a48, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229440, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4412] = { - .class_hid = BNXT_ULP_CLASS_HID_5a2f8, + [524] = { + .class_hid = BNXT_ULP_CLASS_HID_432c, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 720960, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 229444, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4413] = { - .class_hid = BNXT_ULP_CLASS_HID_e298, + [525] = { + .class_hid = BNXT_ULP_CLASS_HID_08ec, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245760, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4414] = { - .class_hid = BNXT_ULP_CLASS_HID_e8a4, + [526] = { + .class_hid = BNXT_ULP_CLASS_HID_01c0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245764, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4415] = { - .class_hid = BNXT_ULP_CLASS_HID_ebb0, + [527] = { + .class_hid = BNXT_ULP_CLASS_HID_14d0, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245824, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4416] = { - .class_hid = BNXT_ULP_CLASS_HID_f200, + [528] = { + .class_hid = BNXT_ULP_CLASS_HID_7a60, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, + .hdr_sig_id = 10, + .flow_sig_id = 245828, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4417] = { - .class_hid = BNXT_ULP_CLASS_HID_e70c, + [529] = { + .class_hid = BNXT_ULP_CLASS_HID_1d90, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, + .flow_sig_id = 131072, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92153,18 +9880,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4418] = { - .class_hid = BNXT_ULP_CLASS_HID_ecc8, + [530] = { + .class_hid = BNXT_ULP_CLASS_HID_14b4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, + .flow_sig_id = 131076, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92172,19 +9896,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4419] = { - .class_hid = BNXT_ULP_CLASS_HID_f0e8, + [531] = { + .class_hid = BNXT_ULP_CLASS_HID_70f0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, + .flow_sig_id = 131136, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92192,19 +9913,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4420] = { - .class_hid = BNXT_ULP_CLASS_HID_f6b4, + [532] = { + .class_hid = BNXT_ULP_CLASS_HID_4814, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, + .flow_sig_id = 131140, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92212,20 +9930,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4421] = { - .class_hid = BNXT_ULP_CLASS_HID_4ffac, + [533] = { + .class_hid = BNXT_ULP_CLASS_HID_3d94, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, + .flow_sig_id = 196608, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92233,18 +9948,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4422] = { - .class_hid = BNXT_ULP_CLASS_HID_4e568, + [534] = { + .class_hid = BNXT_ULP_CLASS_HID_34b8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, + .flow_sig_id = 196612, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92252,19 +9965,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4423] = { - .class_hid = BNXT_ULP_CLASS_HID_4e444, + [535] = { + .class_hid = BNXT_ULP_CLASS_HID_09a8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, + .flow_sig_id = 196672, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92272,19 +9983,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4424] = { - .class_hid = BNXT_ULP_CLASS_HID_4ea00, + [536] = { + .class_hid = BNXT_ULP_CLASS_HID_00cc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, + .flow_sig_id = 196676, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92292,20 +10001,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4425] = { - .class_hid = BNXT_ULP_CLASS_HID_4e3d0, + [537] = { + .class_hid = BNXT_ULP_CLASS_HID_3f64, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, + .flow_sig_id = 393216, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92313,19 +10020,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4426] = { - .class_hid = BNXT_ULP_CLASS_HID_4e99c, + [538] = { + .class_hid = BNXT_ULP_CLASS_HID_3688, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917504, - .flow_pattern_id = 1, + .flow_sig_id = 393220, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92333,20 +10037,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4427] = { - .class_hid = BNXT_ULP_CLASS_HID_4edbc, + [539] = { + .class_hid = BNXT_ULP_CLASS_HID_0b78, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, + .flow_sig_id = 393280, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92354,20 +10055,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4428] = { - .class_hid = BNXT_ULP_CLASS_HID_4f378, + [540] = { + .class_hid = BNXT_ULP_CLASS_HID_029c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 917568, - .flow_pattern_id = 1, + .flow_sig_id = 393284, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92375,21 +10073,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4429] = { - .class_hid = BNXT_ULP_CLASS_HID_1f898, + [541] = { + .class_hid = BNXT_ULP_CLASS_HID_5f68, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, + .flow_sig_id = 458752, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92397,18 +10092,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4430] = { - .class_hid = BNXT_ULP_CLASS_HID_1fea4, + [542] = { + .class_hid = BNXT_ULP_CLASS_HID_568c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, + .flow_sig_id = 458756, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92416,19 +10110,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4431] = { - .class_hid = BNXT_ULP_CLASS_HID_1e244, + [543] = { + .class_hid = BNXT_ULP_CLASS_HID_2b7c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, + .flow_sig_id = 458816, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92436,19 +10129,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4432] = { - .class_hid = BNXT_ULP_CLASS_HID_1e800, + [544] = { + .class_hid = BNXT_ULP_CLASS_HID_22a0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, + .flow_sig_id = 458820, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92456,20 +10148,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4433] = { - .class_hid = BNXT_ULP_CLASS_HID_1fd0c, + [545] = { + .class_hid = BNXT_ULP_CLASS_HID_4020, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, + .flow_sig_id = 655360, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92477,19 +10168,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4434] = { - .class_hid = BNXT_ULP_CLASS_HID_1e2c8, + [546] = { + .class_hid = BNXT_ULP_CLASS_HID_5b44, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, + .flow_sig_id = 655364, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92497,20 +10185,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4435] = { - .class_hid = BNXT_ULP_CLASS_HID_1e6e8, + [547] = { + .class_hid = BNXT_ULP_CLASS_HID_2c34, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, + .flow_sig_id = 655424, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92518,20 +10203,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4436] = { - .class_hid = BNXT_ULP_CLASS_HID_1ecb4, + [548] = { + .class_hid = BNXT_ULP_CLASS_HID_2758, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, + .flow_sig_id = 655428, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92539,21 +10221,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4437] = { - .class_hid = BNXT_ULP_CLASS_HID_5f5ac, + [549] = { + .class_hid = BNXT_ULP_CLASS_HID_18d8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, + .flow_sig_id = 720896, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92561,19 +10240,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4438] = { - .class_hid = BNXT_ULP_CLASS_HID_5fb68, + [550] = { + .class_hid = BNXT_ULP_CLASS_HID_13fc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, + .flow_sig_id = 720900, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92581,20 +10258,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4439] = { - .class_hid = BNXT_ULP_CLASS_HID_5ff08, + [551] = { + .class_hid = BNXT_ULP_CLASS_HID_4c38, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, + .flow_sig_id = 720960, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92602,20 +10277,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4440] = { - .class_hid = BNXT_ULP_CLASS_HID_5e4d4, + [552] = { + .class_hid = BNXT_ULP_CLASS_HID_475c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, + .flow_sig_id = 720964, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92623,21 +10296,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4441] = { - .class_hid = BNXT_ULP_CLASS_HID_5f9d0, + [553] = { + .class_hid = BNXT_ULP_CLASS_HID_1aa8, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, + .flow_sig_id = 917504, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92645,20 +10316,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4442] = { - .class_hid = BNXT_ULP_CLASS_HID_5ff9c, + [554] = { + .class_hid = BNXT_ULP_CLASS_HID_15cc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983040, - .flow_pattern_id = 1, + .flow_sig_id = 917508, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92666,21 +10334,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4443] = { - .class_hid = BNXT_ULP_CLASS_HID_5e3bc, + [555] = { + .class_hid = BNXT_ULP_CLASS_HID_4e08, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, + .flow_sig_id = 917568, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -92688,1020 +10353,788 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4444] = { - .class_hid = BNXT_ULP_CLASS_HID_5e978, + [556] = { + .class_hid = BNXT_ULP_CLASS_HID_492c, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 983104, - .flow_pattern_id = 1, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4445] = { - .class_hid = BNXT_ULP_CLASS_HID_34f6, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4446] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3a, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4447] = { - .class_hid = BNXT_ULP_CLASS_HID_541e, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4448] = { - .class_hid = BNXT_ULP_CLASS_HID_5a22, - .class_tid = 2, - .hdr_sig_id = 0, - .flow_sig_id = 4, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4449] = { - .class_hid = BNXT_ULP_CLASS_HID_34fe, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4450] = { - .class_hid = BNXT_ULP_CLASS_HID_3a32, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4451] = { - .class_hid = BNXT_ULP_CLASS_HID_4a42, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4452] = { - .class_hid = BNXT_ULP_CLASS_HID_14d2, - .class_tid = 2, - .hdr_sig_id = 1, - .flow_sig_id = 4, - .flow_pattern_id = 2, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - }, - [4453] = { - .class_hid = BNXT_ULP_CLASS_HID_34c8, - .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 917572, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4454] = { - .class_hid = BNXT_ULP_CLASS_HID_3a04, + [557] = { + .class_hid = BNXT_ULP_CLASS_HID_3aac, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 983040, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4455] = { - .class_hid = BNXT_ULP_CLASS_HID_1e64, + [558] = { + .class_hid = BNXT_ULP_CLASS_HID_35d0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 983044, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4456] = { - .class_hid = BNXT_ULP_CLASS_HID_07a0, + [559] = { + .class_hid = BNXT_ULP_CLASS_HID_06c0, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 983104, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4457] = { - .class_hid = BNXT_ULP_CLASS_HID_595c, + [560] = { + .class_hid = BNXT_ULP_CLASS_HID_01e4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 983108, + .flow_pattern_id = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4458] = { - .class_hid = BNXT_ULP_CLASS_HID_5e98, + [561] = { + .class_hid = BNXT_ULP_CLASS_HID_4d32, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 0, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } }, - [4459] = { - .class_hid = BNXT_ULP_CLASS_HID_22f8, + [562] = { + .class_hid = BNXT_ULP_CLASS_HID_54aa, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 0, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } }, - [4460] = { - .class_hid = BNXT_ULP_CLASS_HID_2834, + [563] = { + .class_hid = BNXT_ULP_CLASS_HID_0686, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 1, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } }, - [4461] = { - .class_hid = BNXT_ULP_CLASS_HID_0398, + [564] = { + .class_hid = BNXT_ULP_CLASS_HID_540e, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 1, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } }, - [4462] = { - .class_hid = BNXT_ULP_CLASS_HID_09d4, + [565] = { + .class_hid = BNXT_ULP_CLASS_HID_2e3c, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, - [4463] = { - .class_hid = BNXT_ULP_CLASS_HID_48c0, + [566] = { + .class_hid = BNXT_ULP_CLASS_HID_3a20, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, - [4464] = { - .class_hid = BNXT_ULP_CLASS_HID_1370, + [567] = { + .class_hid = BNXT_ULP_CLASS_HID_46f0, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, - [4465] = { - .class_hid = BNXT_ULP_CLASS_HID_246c, + [568] = { + .class_hid = BNXT_ULP_CLASS_HID_52e4, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } }, - [4466] = { - .class_hid = BNXT_ULP_CLASS_HID_2da8, + [569] = { + .class_hid = BNXT_ULP_CLASS_HID_55e4, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4467] = { - .class_hid = BNXT_ULP_CLASS_HID_3188, + [570] = { + .class_hid = BNXT_ULP_CLASS_HID_21f8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4468] = { - .class_hid = BNXT_ULP_CLASS_HID_37c4, + [571] = { + .class_hid = BNXT_ULP_CLASS_HID_75e8, .class_tid = 2, - .hdr_sig_id = 2, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 3, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4469] = { - .class_hid = BNXT_ULP_CLASS_HID_34f0, + [572] = { + .class_hid = BNXT_ULP_CLASS_HID_41fc, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } }, - [4470] = { - .class_hid = BNXT_ULP_CLASS_HID_3a3c, + [573] = { + .class_hid = BNXT_ULP_CLASS_HID_4d12, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } }, - [4471] = { - .class_hid = BNXT_ULP_CLASS_HID_1e5c, + [574] = { + .class_hid = BNXT_ULP_CLASS_HID_548a, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } }, - [4472] = { - .class_hid = BNXT_ULP_CLASS_HID_0798, + [575] = { + .class_hid = BNXT_ULP_CLASS_HID_3356, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 4, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } }, - [4473] = { - .class_hid = BNXT_ULP_CLASS_HID_5964, + [576] = { + .class_hid = BNXT_ULP_CLASS_HID_1ace, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 4, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } }, - [4474] = { - .class_hid = BNXT_ULP_CLASS_HID_5ea0, + [577] = { + .class_hid = BNXT_ULP_CLASS_HID_1a9a, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 4, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4475] = { - .class_hid = BNXT_ULP_CLASS_HID_22c0, + [578] = { + .class_hid = BNXT_ULP_CLASS_HID_4d46, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 4, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4476] = { - .class_hid = BNXT_ULP_CLASS_HID_280c, + [579] = { + .class_hid = BNXT_ULP_CLASS_HID_2812, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 4, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } }, - [4477] = { - .class_hid = BNXT_ULP_CLASS_HID_43104, + [580] = { + .class_hid = BNXT_ULP_CLASS_HID_338a, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 4, + .flow_sig_id = 30720, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + }, + [581] = { + .class_hid = BNXT_ULP_CLASS_HID_06e6, + .class_tid = 2, + .hdr_sig_id = 5, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } }, - [4478] = { - .class_hid = BNXT_ULP_CLASS_HID_43740, + [582] = { + .class_hid = BNXT_ULP_CLASS_HID_546e, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } }, - [4479] = { - .class_hid = BNXT_ULP_CLASS_HID_41b60, + [583] = { + .class_hid = BNXT_ULP_CLASS_HID_46ee, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } }, - [4480] = { - .class_hid = BNXT_ULP_CLASS_HID_400ac, + [584] = { + .class_hid = BNXT_ULP_CLASS_HID_0d22, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } }, - [4481] = { - .class_hid = BNXT_ULP_CLASS_HID_455a8, + [585] = { + .class_hid = BNXT_ULP_CLASS_HID_26e2, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4482] = { - .class_hid = BNXT_ULP_CLASS_HID_45bf4, + [586] = { + .class_hid = BNXT_ULP_CLASS_HID_746a, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4483] = { - .class_hid = BNXT_ULP_CLASS_HID_43f14, + [587] = { + .class_hid = BNXT_ULP_CLASS_HID_1fa6, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4484] = { - .class_hid = BNXT_ULP_CLASS_HID_42550, + [588] = { + .class_hid = BNXT_ULP_CLASS_HID_2d2e, .class_tid = 2, - .hdr_sig_id = 3, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 5, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } }, - [4485] = { - .class_hid = BNXT_ULP_CLASS_HID_34d6, + [589] = { + .class_hid = BNXT_ULP_CLASS_HID_4ef2, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4096, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } }, - [4486] = { - .class_hid = BNXT_ULP_CLASS_HID_3a1a, + [590] = { + .class_hid = BNXT_ULP_CLASS_HID_576a, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 6144, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } }, - [4487] = { - .class_hid = BNXT_ULP_CLASS_HID_543e, + [591] = { + .class_hid = BNXT_ULP_CLASS_HID_30b6, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 12288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } }, - [4488] = { - .class_hid = BNXT_ULP_CLASS_HID_5a02, + [592] = { + .class_hid = BNXT_ULP_CLASS_HID_192e, .class_tid = 2, - .hdr_sig_id = 4, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 14336, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } }, - [4489] = { - .class_hid = BNXT_ULP_CLASS_HID_34de, + [593] = { + .class_hid = BNXT_ULP_CLASS_HID_197a, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 20480, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4490] = { - .class_hid = BNXT_ULP_CLASS_HID_3a12, + [594] = { + .class_hid = BNXT_ULP_CLASS_HID_4ea6, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 22528, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4491] = { - .class_hid = BNXT_ULP_CLASS_HID_4a62, + [595] = { + .class_hid = BNXT_ULP_CLASS_HID_2bf2, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 28672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4492] = { - .class_hid = BNXT_ULP_CLASS_HID_14f2, + [596] = { + .class_hid = BNXT_ULP_CLASS_HID_306a, .class_tid = 2, - .hdr_sig_id = 5, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 6, + .flow_sig_id = 30720, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } }, - [4493] = { - .class_hid = BNXT_ULP_CLASS_HID_34b6, + [597] = { + .class_hid = BNXT_ULP_CLASS_HID_06c6, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 16384, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } }, - [4494] = { - .class_hid = BNXT_ULP_CLASS_HID_3a7a, + [598] = { + .class_hid = BNXT_ULP_CLASS_HID_544e, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 24576, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } }, - [4495] = { - .class_hid = BNXT_ULP_CLASS_HID_545e, + [599] = { + .class_hid = BNXT_ULP_CLASS_HID_46ce, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } }, - [4496] = { - .class_hid = BNXT_ULP_CLASS_HID_5a62, + [600] = { + .class_hid = BNXT_ULP_CLASS_HID_0d02, .class_tid = 2, - .hdr_sig_id = 6, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 7, + .flow_sig_id = 57344, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } }, - [4497] = { - .class_hid = BNXT_ULP_CLASS_HID_34be, + [601] = { + .class_hid = BNXT_ULP_CLASS_HID_26c2, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 81920, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4498] = { - .class_hid = BNXT_ULP_CLASS_HID_3a72, + [602] = { + .class_hid = BNXT_ULP_CLASS_HID_744a, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 90112, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4499] = { - .class_hid = BNXT_ULP_CLASS_HID_4a02, + [603] = { + .class_hid = BNXT_ULP_CLASS_HID_1f86, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4500] = { - .class_hid = BNXT_ULP_CLASS_HID_1492, + [604] = { + .class_hid = BNXT_ULP_CLASS_HID_2d0e, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 122880, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } }, - [4501] = { - .class_hid = BNXT_ULP_CLASS_HID_34a8, + [605] = { + .class_hid = BNXT_ULP_CLASS_HID_2e1c, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 32768, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93709,16 +11142,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4502] = { - .class_hid = BNXT_ULP_CLASS_HID_3a64, + [606] = { + .class_hid = BNXT_ULP_CLASS_HID_3a00, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 32832, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93726,17 +11157,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4503] = { - .class_hid = BNXT_ULP_CLASS_HID_1e04, + [607] = { + .class_hid = BNXT_ULP_CLASS_HID_46d0, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 49152, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93744,17 +11173,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4504] = { - .class_hid = BNXT_ULP_CLASS_HID_07c0, + [608] = { + .class_hid = BNXT_ULP_CLASS_HID_52c4, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 49216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93762,18 +11189,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } }, - [4505] = { - .class_hid = BNXT_ULP_CLASS_HID_593c, + [609] = { + .class_hid = BNXT_ULP_CLASS_HID_4e10, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 98304, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93781,17 +11206,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4506] = { - .class_hid = BNXT_ULP_CLASS_HID_5ef8, + [610] = { + .class_hid = BNXT_ULP_CLASS_HID_5a04, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 98368, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93799,18 +11222,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4507] = { - .class_hid = BNXT_ULP_CLASS_HID_2298, + [611] = { + .class_hid = BNXT_ULP_CLASS_HID_1f98, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93818,18 +11239,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4508] = { - .class_hid = BNXT_ULP_CLASS_HID_2854, + [612] = { + .class_hid = BNXT_ULP_CLASS_HID_72f8, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93837,19 +11256,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } }, - [4509] = { - .class_hid = BNXT_ULP_CLASS_HID_03f8, + [613] = { + .class_hid = BNXT_ULP_CLASS_HID_0a78, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93857,17 +11274,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4510] = { - .class_hid = BNXT_ULP_CLASS_HID_09b4, + [614] = { + .class_hid = BNXT_ULP_CLASS_HID_166c, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93875,18 +11290,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4511] = { - .class_hid = BNXT_ULP_CLASS_HID_48a0, + [615] = { + .class_hid = BNXT_ULP_CLASS_HID_233c, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93894,18 +11307,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4512] = { - .class_hid = BNXT_ULP_CLASS_HID_1310, + [616] = { + .class_hid = BNXT_ULP_CLASS_HID_0f20, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93913,19 +11324,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4513] = { - .class_hid = BNXT_ULP_CLASS_HID_240c, + [617] = { + .class_hid = BNXT_ULP_CLASS_HID_2a7c, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93933,18 +11342,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4514] = { - .class_hid = BNXT_ULP_CLASS_HID_2dc8, + [618] = { + .class_hid = BNXT_ULP_CLASS_HID_3660, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93952,19 +11359,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4515] = { - .class_hid = BNXT_ULP_CLASS_HID_31e8, + [619] = { + .class_hid = BNXT_ULP_CLASS_HID_4330, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93972,19 +11377,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } }, - [4516] = { - .class_hid = BNXT_ULP_CLASS_HID_37a4, + [620] = { + .class_hid = BNXT_ULP_CLASS_HID_2f24, .class_tid = 2, .hdr_sig_id = 8, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -93992,20 +11395,33 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + }, + [621] = { + .class_hid = BNXT_ULP_CLASS_HID_5584, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 131072, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4517] = { - .class_hid = BNXT_ULP_CLASS_HID_34d0, + [622] = { + .class_hid = BNXT_ULP_CLASS_HID_2198, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94013,16 +11429,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4518] = { - .class_hid = BNXT_ULP_CLASS_HID_3a1c, + [623] = { + .class_hid = BNXT_ULP_CLASS_HID_7588, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94030,17 +11445,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4519] = { - .class_hid = BNXT_ULP_CLASS_HID_1e7c, + [624] = { + .class_hid = BNXT_ULP_CLASS_HID_419c, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94048,17 +11461,32 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } }, - [4520] = { - .class_hid = BNXT_ULP_CLASS_HID_07b8, + [625] = { + .class_hid = BNXT_ULP_CLASS_HID_7758, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 393216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + }, + [626] = { + .class_hid = BNXT_ULP_CLASS_HID_43ac, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94066,18 +11494,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4521] = { - .class_hid = BNXT_ULP_CLASS_HID_5944, + [627] = { + .class_hid = BNXT_ULP_CLASS_HID_0c10, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94085,17 +11511,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4522] = { - .class_hid = BNXT_ULP_CLASS_HID_5e80, + [628] = { + .class_hid = BNXT_ULP_CLASS_HID_1864, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94103,18 +11528,33 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } }, - [4523] = { - .class_hid = BNXT_ULP_CLASS_HID_22e0, + [629] = { + .class_hid = BNXT_ULP_CLASS_HID_30c8, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 655360, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + }, + [630] = { + .class_hid = BNXT_ULP_CLASS_HID_1cdc, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94122,18 +11562,33 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4524] = { - .class_hid = BNXT_ULP_CLASS_HID_282c, + [631] = { + .class_hid = BNXT_ULP_CLASS_HID_50cc, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 720896, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + }, + [632] = { + .class_hid = BNXT_ULP_CLASS_HID_3d20, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94141,19 +11596,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4525] = { - .class_hid = BNXT_ULP_CLASS_HID_43124, + [633] = { + .class_hid = BNXT_ULP_CLASS_HID_529c, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94161,17 +11614,52 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } }, - [4526] = { - .class_hid = BNXT_ULP_CLASS_HID_43760, + [634] = { + .class_hid = BNXT_ULP_CLASS_HID_3ef0, .class_tid = 2, .hdr_sig_id = 9, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 917568, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + }, + [635] = { + .class_hid = BNXT_ULP_CLASS_HID_72e0, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 983040, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + }, + [636] = { + .class_hid = BNXT_ULP_CLASS_HID_5ef4, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94179,137 +11667,218 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + }, + [637] = { + .class_hid = BNXT_ULP_CLASS_HID_2dfc, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 32768, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + }, + [638] = { + .class_hid = BNXT_ULP_CLASS_HID_39e0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 32832, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + }, + [639] = { + .class_hid = BNXT_ULP_CLASS_HID_4530, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 49152, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + }, + [640] = { + .class_hid = BNXT_ULP_CLASS_HID_5124, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 49216, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + }, + [641] = { + .class_hid = BNXT_ULP_CLASS_HID_4df0, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 98304, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + }, + [642] = { + .class_hid = BNXT_ULP_CLASS_HID_59e4, + .class_tid = 2, + .hdr_sig_id = 10, + .flow_sig_id = 98368, + .flow_pattern_id = 1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4527] = { - .class_hid = BNXT_ULP_CLASS_HID_41b40, + [643] = { + .class_hid = BNXT_ULP_CLASS_HID_1c78, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 114688, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4528] = { - .class_hid = BNXT_ULP_CLASS_HID_4008c, + [644] = { + .class_hid = BNXT_ULP_CLASS_HID_7118, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 114752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } }, - [4529] = { - .class_hid = BNXT_ULP_CLASS_HID_45588, + [645] = { + .class_hid = BNXT_ULP_CLASS_HID_0998, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163840, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4530] = { - .class_hid = BNXT_ULP_CLASS_HID_45bd4, + [646] = { + .class_hid = BNXT_ULP_CLASS_HID_158c, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 163904, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4531] = { - .class_hid = BNXT_ULP_CLASS_HID_43f34, + [647] = { + .class_hid = BNXT_ULP_CLASS_HID_20dc, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180224, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4532] = { - .class_hid = BNXT_ULP_CLASS_HID_42570, + [648] = { + .class_hid = BNXT_ULP_CLASS_HID_0cc0, .class_tid = 2, - .hdr_sig_id = 9, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 10, + .flow_sig_id = 180288, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4533] = { - .class_hid = BNXT_ULP_CLASS_HID_3488, + [649] = { + .class_hid = BNXT_ULP_CLASS_HID_299c, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 229376, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94317,16 +11886,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4534] = { - .class_hid = BNXT_ULP_CLASS_HID_3a44, + [650] = { + .class_hid = BNXT_ULP_CLASS_HID_3580, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 229440, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94334,17 +11903,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4535] = { - .class_hid = BNXT_ULP_CLASS_HID_1e24, + [651] = { + .class_hid = BNXT_ULP_CLASS_HID_40d0, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 245760, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94352,17 +11921,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4536] = { - .class_hid = BNXT_ULP_CLASS_HID_07e0, + [652] = { + .class_hid = BNXT_ULP_CLASS_HID_2cc4, .class_tid = 2, .hdr_sig_id = 10, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 245824, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94370,250 +11939,218 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } }, - [4537] = { - .class_hid = BNXT_ULP_CLASS_HID_591c, + [653] = { + .class_hid = BNXT_ULP_CLASS_HID_55a4, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131072, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4538] = { - .class_hid = BNXT_ULP_CLASS_HID_5ed8, + [654] = { + .class_hid = BNXT_ULP_CLASS_HID_21b8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 131136, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4539] = { - .class_hid = BNXT_ULP_CLASS_HID_22b8, + [655] = { + .class_hid = BNXT_ULP_CLASS_HID_75a8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196608, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4540] = { - .class_hid = BNXT_ULP_CLASS_HID_2874, + [656] = { + .class_hid = BNXT_ULP_CLASS_HID_41bc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 196672, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } }, - [4541] = { - .class_hid = BNXT_ULP_CLASS_HID_03d8, + [657] = { + .class_hid = BNXT_ULP_CLASS_HID_7778, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 393216, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4542] = { - .class_hid = BNXT_ULP_CLASS_HID_0994, + [658] = { + .class_hid = BNXT_ULP_CLASS_HID_438c, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 393280, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4543] = { - .class_hid = BNXT_ULP_CLASS_HID_4880, + [659] = { + .class_hid = BNXT_ULP_CLASS_HID_0c30, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458752, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4544] = { - .class_hid = BNXT_ULP_CLASS_HID_1330, + [660] = { + .class_hid = BNXT_ULP_CLASS_HID_1844, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 458816, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } }, - [4545] = { - .class_hid = BNXT_ULP_CLASS_HID_242c, + [661] = { + .class_hid = BNXT_ULP_CLASS_HID_30e8, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655360, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4546] = { - .class_hid = BNXT_ULP_CLASS_HID_2de8, + [662] = { + .class_hid = BNXT_ULP_CLASS_HID_1cfc, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 655424, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4547] = { - .class_hid = BNXT_ULP_CLASS_HID_31c8, + [663] = { + .class_hid = BNXT_ULP_CLASS_HID_50ec, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 720896, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4548] = { - .class_hid = BNXT_ULP_CLASS_HID_3784, + [664] = { + .class_hid = BNXT_ULP_CLASS_HID_3d00, .class_tid = 2, - .hdr_sig_id = 10, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .hdr_sig_id = 11, + .flow_sig_id = 720960, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4549] = { - .class_hid = BNXT_ULP_CLASS_HID_34b0, + [665] = { + .class_hid = BNXT_ULP_CLASS_HID_52bc, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 917504, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94621,16 +12158,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4550] = { - .class_hid = BNXT_ULP_CLASS_HID_3a7c, + [666] = { + .class_hid = BNXT_ULP_CLASS_HID_3ed0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 4, - .flow_pattern_id = 2, + .flow_sig_id = 917568, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94638,17 +12175,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4551] = { - .class_hid = BNXT_ULP_CLASS_HID_1e1c, + [667] = { + .class_hid = BNXT_ULP_CLASS_HID_72c0, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 983040, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94656,17 +12193,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4552] = { - .class_hid = BNXT_ULP_CLASS_HID_07d8, + [668] = { + .class_hid = BNXT_ULP_CLASS_HID_5ed4, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 68, - .flow_pattern_id = 2, + .flow_sig_id = 983104, + .flow_pattern_id = 1, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -94674,208 +12211,266 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } }, - [4553] = { - .class_hid = BNXT_ULP_CLASS_HID_5924, + [669] = { + .class_hid = BNXT_ULP_CLASS_HID_3866, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 0, + .flow_sig_id = 4, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC } + }, + [670] = { + .class_hid = BNXT_ULP_CLASS_HID_381e, + .class_tid = 2, + .hdr_sig_id = 1, .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC } }, - [4554] = { - .class_hid = BNXT_ULP_CLASS_HID_5ee0, + [671] = { + .class_hid = BNXT_ULP_CLASS_HID_3860, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 2, .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC } }, - [4555] = { - .class_hid = BNXT_ULP_CLASS_HID_2280, + [672] = { + .class_hid = BNXT_ULP_CLASS_HID_0454, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 2, .flow_sig_id = 68, .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID } + }, + [673] = { + .class_hid = BNXT_ULP_CLASS_HID_3818, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC } }, - [4556] = { - .class_hid = BNXT_ULP_CLASS_HID_284c, + [674] = { + .class_hid = BNXT_ULP_CLASS_HID_042c, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 3, .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID } }, - [4557] = { - .class_hid = BNXT_ULP_CLASS_HID_43144, + [675] = { + .class_hid = BNXT_ULP_CLASS_HID_3846, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 4, + .flow_sig_id = 4, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC } + }, + [676] = { + .class_hid = BNXT_ULP_CLASS_HID_387e, + .class_tid = 2, + .hdr_sig_id = 5, .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC } + }, + [677] = { + .class_hid = BNXT_ULP_CLASS_HID_3ba6, + .class_tid = 2, + .hdr_sig_id = 6, + .flow_sig_id = 4, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC } }, - [4558] = { - .class_hid = BNXT_ULP_CLASS_HID_43700, + [678] = { + .class_hid = BNXT_ULP_CLASS_HID_385e, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 7, .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC } }, - [4559] = { - .class_hid = BNXT_ULP_CLASS_HID_41b20, + [679] = { + .class_hid = BNXT_ULP_CLASS_HID_3840, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 8, + .flow_sig_id = 4, + .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC } + }, + [680] = { + .class_hid = BNXT_ULP_CLASS_HID_0474, + .class_tid = 2, + .hdr_sig_id = 8, .flow_sig_id = 68, .flow_pattern_id = 2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID } + }, + [681] = { + .class_hid = BNXT_ULP_CLASS_HID_3878, + .class_tid = 2, + .hdr_sig_id = 9, + .flow_sig_id = 4, + .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC } }, - [4560] = { - .class_hid = BNXT_ULP_CLASS_HID_400ec, + [682] = { + .class_hid = BNXT_ULP_CLASS_HID_044c, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 9, .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID } }, - [4561] = { - .class_hid = BNXT_ULP_CLASS_HID_455e8, + [683] = { + .class_hid = BNXT_ULP_CLASS_HID_3ba0, .class_tid = 2, - .hdr_sig_id = 11, + .hdr_sig_id = 10, .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC } }, - [4562] = { - .class_hid = BNXT_ULP_CLASS_HID_45bb4, + [684] = { + .class_hid = BNXT_ULP_CLASS_HID_0794, .class_tid = 2, - .hdr_sig_id = 11, - .flow_sig_id = 4, + .hdr_sig_id = 10, + .flow_sig_id = 68, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID } }, - [4563] = { - .class_hid = BNXT_ULP_CLASS_HID_43f54, + [685] = { + .class_hid = BNXT_ULP_CLASS_HID_3858, .class_tid = 2, .hdr_sig_id = 11, - .flow_sig_id = 68, + .flow_sig_id = 4, .flow_pattern_id = 2, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | @@ -94885,14 +12480,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC } }, - [4564] = { - .class_hid = BNXT_ULP_CLASS_HID_42510, + [686] = { + .class_hid = BNXT_ULP_CLASS_HID_046c, .class_tid = 2, .hdr_sig_id = 11, .flow_sig_id = 68, @@ -94906,10 +12497,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .field_sig = { .bits = BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID } } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 866fff74c4..a3d8c716f3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Mar 4 10:12:06 2021 */ +/* date: Tue Mar 9 19:13:26 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -12,13 +12,13 @@ #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 #define BNXT_ULP_GEN_TBL_MAX_SZ 10 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 524288 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4565 -#define BNXT_ULP_CLASS_HID_LOW_PRIME 5939 -#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7669 -#define BNXT_ULP_CLASS_HID_SHFTR 31 -#define BNXT_ULP_CLASS_HID_SHFTL 31 -#define BNXT_ULP_CLASS_HID_MASK 524287 +#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687 +#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701 +#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907 +#define BNXT_ULP_CLASS_HID_SHFTR 23 +#define BNXT_ULP_CLASS_HID_SHFTL 23 +#define BNXT_ULP_CLASS_HID_MASK 32767 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 @@ -26,16 +26,19 @@ #define BNXT_ULP_ACT_HID_SHFTR 27 #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 11 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 10 +#define BNXT_ULP_COND_GOTO_REJECT 1023 +#define BNXT_ULP_COND_GOTO_RF 0x10000 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 #define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595 #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 73 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74 #define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 484 #define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20 #define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 550 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 32 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 41 #define ULP_THOR_CLASS_TMPL_LIST_SIZE 5 #define ULP_THOR_CLASS_TBL_LIST_SIZE 26 #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 90 @@ -47,7 +50,7 @@ #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 26 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7 #define ULP_THOR_ACT_TBL_LIST_SIZE 0 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 0 @@ -128,6 +131,24 @@ enum bnxt_ulp_byte_order { BNXT_ULP_BYTE_ORDER_LAST = 2 }; +enum bnxt_ulp_cc_upd_opc { + BNXT_ULP_CC_UPD_OPC_NOP = 0, + BNXT_ULP_CC_UPD_OPC_EQ = 1, + BNXT_ULP_CC_UPD_OPC_NE = 2, + BNXT_ULP_CC_UPD_OPC_GT = 3, + BNXT_ULP_CC_UPD_OPC_GE = 4, + BNXT_ULP_CC_UPD_OPC_LT = 5, + BNXT_ULP_CC_UPD_OPC_LE = 6, + BNXT_ULP_CC_UPD_OPC_LAST = 7 +}; + +enum bnxt_ulp_cc_upd_src { + BNXT_ULP_CC_UPD_SRC_REGFILE = 0, + BNXT_ULP_CC_UPD_SRC_GLB_REGFILE = 1, + BNXT_ULP_CC_UPD_SRC_COMP_FIELD = 2, + BNXT_ULP_CC_UPD_SRC_LAST = 3 +}; + enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_NOT_USED = 0, BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1, @@ -215,7 +236,9 @@ enum bnxt_ulp_cond_opc { BNXT_ULP_COND_OPC_RF_NOT_SET = 9, BNXT_ULP_COND_OPC_FLOW_PAT_MATCH = 10, BNXT_ULP_COND_OPC_ACT_PAT_MATCH = 11, - BNXT_ULP_COND_OPC_LAST = 12 + BNXT_ULP_COND_OPC_EXT_MEM_IS_SET = 12, + BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET = 13, + BNXT_ULP_COND_OPC_LAST = 14 }; enum bnxt_ulp_critical_resource { @@ -319,7 +342,13 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 3, BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4, BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5, - BNXT_ULP_GLB_RF_IDX_LAST = 6 + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 6, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 7, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 8, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 9, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 10, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 11, + BNXT_ULP_GLB_RF_IDX_LAST = 12 }; enum bnxt_ulp_hdr_type { @@ -362,13 +391,6 @@ enum bnxt_ulp_match_type { BNXT_ULP_MATCH_TYPE_LAST = 2 }; -enum bnxt_ulp_mem_type_opc { - BNXT_ULP_MEM_TYPE_OPC_NOP = 0, - BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT = 1, - BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT = 2, - BNXT_ULP_MEM_TYPE_OPC_LAST = 3 -}; - enum bnxt_ulp_port_table { BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_MAC = 0, BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC = 1, @@ -464,11 +486,6 @@ enum bnxt_ulp_flow_dir_bitmask { BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000 }; -enum bnxt_ulp_match_type_bitmask { - BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000, - BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x8000000000000000 -}; - enum bnxt_ulp_resource_func { BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00, BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20, @@ -1038,4570 +1055,692 @@ enum ulp_thor_sym { }; enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_05d1 = 0x05d1, - BNXT_ULP_CLASS_HID_1229 = 0x1229, - BNXT_ULP_CLASS_HID_0bed = 0x0bed, - BNXT_ULP_CLASS_HID_1865 = 0x1865, - BNXT_ULP_CLASS_HID_25c9 = 0x25c9, - BNXT_ULP_CLASS_HID_3241 = 0x3241, - BNXT_ULP_CLASS_HID_2c05 = 0x2c05, - BNXT_ULP_CLASS_HID_389d = 0x389d, - BNXT_ULP_CLASS_HID_3c3d = 0x3c3d, - BNXT_ULP_CLASS_HID_48b5 = 0x48b5, - BNXT_ULP_CLASS_HID_4279 = 0x4279, - BNXT_ULP_CLASS_HID_4ef1 = 0x4ef1, - BNXT_ULP_CLASS_HID_5c55 = 0x5c55, - BNXT_ULP_CLASS_HID_0be1 = 0x0be1, - BNXT_ULP_CLASS_HID_05a5 = 0x05a5, - BNXT_ULP_CLASS_HID_123d = 0x123d, - BNXT_ULP_CLASS_HID_4142d = 0x4142d, - BNXT_ULP_CLASS_HID_42095 = 0x42095, - BNXT_ULP_CLASS_HID_41a69 = 0x41a69, - BNXT_ULP_CLASS_HID_426d1 = 0x426d1, - BNXT_ULP_CLASS_HID_44a99 = 0x44a99, - BNXT_ULP_CLASS_HID_45701 = 0x45701, - BNXT_ULP_CLASS_HID_450c5 = 0x450c5, - BNXT_ULP_CLASS_HID_40071 = 0x40071, - BNXT_ULP_CLASS_HID_40a85 = 0x40a85, - BNXT_ULP_CLASS_HID_4170d = 0x4170d, - BNXT_ULP_CLASS_HID_410c1 = 0x410c1, - BNXT_ULP_CLASS_HID_41d49 = 0x41d49, - BNXT_ULP_CLASS_HID_440f1 = 0x440f1, - BNXT_ULP_CLASS_HID_44d79 = 0x44d79, - BNXT_ULP_CLASS_HID_4473d = 0x4473d, - BNXT_ULP_CLASS_HID_453a5 = 0x453a5, - BNXT_ULP_CLASS_HID_244e3 = 0x244e3, - BNXT_ULP_CLASS_HID_2517b = 0x2517b, - BNXT_ULP_CLASS_HID_24b3f = 0x24b3f, - BNXT_ULP_CLASS_HID_257b7 = 0x257b7, - BNXT_ULP_CLASS_HID_22f5f = 0x22f5f, - BNXT_ULP_CLASS_HID_23bd7 = 0x23bd7, - BNXT_ULP_CLASS_HID_2359b = 0x2359b, - BNXT_ULP_CLASS_HID_24213 = 0x24213, - BNXT_ULP_CLASS_HID_20bab = 0x20bab, - BNXT_ULP_CLASS_HID_21823 = 0x21823, - BNXT_ULP_CLASS_HID_211e7 = 0x211e7, - BNXT_ULP_CLASS_HID_21e7f = 0x21e7f, - BNXT_ULP_CLASS_HID_252f3 = 0x252f3, - BNXT_ULP_CLASS_HID_2029f = 0x2029f, - BNXT_ULP_CLASS_HID_2590f = 0x2590f, - BNXT_ULP_CLASS_HID_208db = 0x208db, - BNXT_ULP_CLASS_HID_231d3 = 0x231d3, - BNXT_ULP_CLASS_HID_23e2b = 0x23e2b, - BNXT_ULP_CLASS_HID_237ef = 0x237ef, - BNXT_ULP_CLASS_HID_24467 = 0x24467, - BNXT_ULP_CLASS_HID_21c0f = 0x21c0f, - BNXT_ULP_CLASS_HID_22887 = 0x22887, - BNXT_ULP_CLASS_HID_2224b = 0x2224b, - BNXT_ULP_CLASS_HID_22ec3 = 0x22ec3, - BNXT_ULP_CLASS_HID_25547 = 0x25547, - BNXT_ULP_CLASS_HID_20513 = 0x20513, - BNXT_ULP_CLASS_HID_25b83 = 0x25b83, - BNXT_ULP_CLASS_HID_20b2f = 0x20b2f, - BNXT_ULP_CLASS_HID_23fa3 = 0x23fa3, - BNXT_ULP_CLASS_HID_24c3b = 0x24c3b, - BNXT_ULP_CLASS_HID_245ff = 0x245ff, - BNXT_ULP_CLASS_HID_25277 = 0x25277, - BNXT_ULP_CLASS_HID_64037 = 0x64037, - BNXT_ULP_CLASS_HID_64c8f = 0x64c8f, - BNXT_ULP_CLASS_HID_64673 = 0x64673, - BNXT_ULP_CLASS_HID_652cb = 0x652cb, - BNXT_ULP_CLASS_HID_62a93 = 0x62a93, - BNXT_ULP_CLASS_HID_636eb = 0x636eb, - BNXT_ULP_CLASS_HID_630af = 0x630af, - BNXT_ULP_CLASS_HID_63d27 = 0x63d27, - BNXT_ULP_CLASS_HID_606ff = 0x606ff, - BNXT_ULP_CLASS_HID_61377 = 0x61377, - BNXT_ULP_CLASS_HID_60d3b = 0x60d3b, - BNXT_ULP_CLASS_HID_619b3 = 0x619b3, - BNXT_ULP_CLASS_HID_64e07 = 0x64e07, - BNXT_ULP_CLASS_HID_65a9f = 0x65a9f, - BNXT_ULP_CLASS_HID_65443 = 0x65443, - BNXT_ULP_CLASS_HID_603ef = 0x603ef, - BNXT_ULP_CLASS_HID_62ce7 = 0x62ce7, - BNXT_ULP_CLASS_HID_6397f = 0x6397f, - BNXT_ULP_CLASS_HID_63323 = 0x63323, - BNXT_ULP_CLASS_HID_63fbb = 0x63fbb, - BNXT_ULP_CLASS_HID_61743 = 0x61743, - BNXT_ULP_CLASS_HID_623db = 0x623db, - BNXT_ULP_CLASS_HID_61d9f = 0x61d9f, - BNXT_ULP_CLASS_HID_62a17 = 0x62a17, - BNXT_ULP_CLASS_HID_6509b = 0x6509b, - BNXT_ULP_CLASS_HID_60027 = 0x60027, - BNXT_ULP_CLASS_HID_656d7 = 0x656d7, - BNXT_ULP_CLASS_HID_60663 = 0x60663, - BNXT_ULP_CLASS_HID_63af7 = 0x63af7, - BNXT_ULP_CLASS_HID_6474f = 0x6474f, - BNXT_ULP_CLASS_HID_64133 = 0x64133, - BNXT_ULP_CLASS_HID_64d8b = 0x64d8b, - BNXT_ULP_CLASS_HID_a3fb = 0xa3fb, - BNXT_ULP_CLASS_HID_b063 = 0xb063, - BNXT_ULP_CLASS_HID_aa27 = 0xaa27, - BNXT_ULP_CLASS_HID_b6af = 0xb6af, - BNXT_ULP_CLASS_HID_8e47 = 0x8e47, - BNXT_ULP_CLASS_HID_9acf = 0x9acf, - BNXT_ULP_CLASS_HID_9483 = 0x9483, - BNXT_ULP_CLASS_HID_a10b = 0xa10b, - BNXT_ULP_CLASS_HID_c78f = 0xc78f, - BNXT_ULP_CLASS_HID_d3f7 = 0xd3f7, - BNXT_ULP_CLASS_HID_cdcb = 0xcdcb, - BNXT_ULP_CLASS_HID_da33 = 0xda33, - BNXT_ULP_CLASS_HID_b1eb = 0xb1eb, - BNXT_ULP_CLASS_HID_be53 = 0xbe53, - BNXT_ULP_CLASS_HID_b817 = 0xb817, - BNXT_ULP_CLASS_HID_c49f = 0xc49f, - BNXT_ULP_CLASS_HID_49f2f = 0x49f2f, - BNXT_ULP_CLASS_HID_4ab97 = 0x4ab97, - BNXT_ULP_CLASS_HID_4a56b = 0x4a56b, - BNXT_ULP_CLASS_HID_4b1d3 = 0x4b1d3, - BNXT_ULP_CLASS_HID_4898b = 0x4898b, - BNXT_ULP_CLASS_HID_495f3 = 0x495f3, - BNXT_ULP_CLASS_HID_48fb7 = 0x48fb7, - BNXT_ULP_CLASS_HID_49c3f = 0x49c3f, - BNXT_ULP_CLASS_HID_4c2b3 = 0x4c2b3, - BNXT_ULP_CLASS_HID_4cf3b = 0x4cf3b, - BNXT_ULP_CLASS_HID_4c8ff = 0x4c8ff, - BNXT_ULP_CLASS_HID_4d567 = 0x4d567, - BNXT_ULP_CLASS_HID_4ad1f = 0x4ad1f, - BNXT_ULP_CLASS_HID_4b987 = 0x4b987, - BNXT_ULP_CLASS_HID_4b35b = 0x4b35b, - BNXT_ULP_CLASS_HID_4bfc3 = 0x4bfc3, - BNXT_ULP_CLASS_HID_1b9fb = 0x1b9fb, - BNXT_ULP_CLASS_HID_1c663 = 0x1c663, - BNXT_ULP_CLASS_HID_1c027 = 0x1c027, - BNXT_ULP_CLASS_HID_1ccaf = 0x1ccaf, - BNXT_ULP_CLASS_HID_1a447 = 0x1a447, - BNXT_ULP_CLASS_HID_1b0cf = 0x1b0cf, - BNXT_ULP_CLASS_HID_1aa83 = 0x1aa83, - BNXT_ULP_CLASS_HID_1b70b = 0x1b70b, - BNXT_ULP_CLASS_HID_180b3 = 0x180b3, - BNXT_ULP_CLASS_HID_18d3b = 0x18d3b, - BNXT_ULP_CLASS_HID_186ff = 0x186ff, - BNXT_ULP_CLASS_HID_19367 = 0x19367, - BNXT_ULP_CLASS_HID_1c7eb = 0x1c7eb, - BNXT_ULP_CLASS_HID_1d453 = 0x1d453, - BNXT_ULP_CLASS_HID_1ce17 = 0x1ce17, - BNXT_ULP_CLASS_HID_1da9f = 0x1da9f, - BNXT_ULP_CLASS_HID_5b52f = 0x5b52f, - BNXT_ULP_CLASS_HID_5c197 = 0x5c197, - BNXT_ULP_CLASS_HID_5bb6b = 0x5bb6b, - BNXT_ULP_CLASS_HID_5c7d3 = 0x5c7d3, - BNXT_ULP_CLASS_HID_59f8b = 0x59f8b, - BNXT_ULP_CLASS_HID_5abf3 = 0x5abf3, - BNXT_ULP_CLASS_HID_5a5b7 = 0x5a5b7, - BNXT_ULP_CLASS_HID_5b23f = 0x5b23f, - BNXT_ULP_CLASS_HID_5d8b3 = 0x5d8b3, - BNXT_ULP_CLASS_HID_5886f = 0x5886f, - BNXT_ULP_CLASS_HID_58223 = 0x58223, - BNXT_ULP_CLASS_HID_58eab = 0x58eab, - BNXT_ULP_CLASS_HID_5c31f = 0x5c31f, - BNXT_ULP_CLASS_HID_5cf87 = 0x5cf87, - BNXT_ULP_CLASS_HID_5c95b = 0x5c95b, - BNXT_ULP_CLASS_HID_5d5c3 = 0x5d5c3, - BNXT_ULP_CLASS_HID_05f1 = 0x05f1, - BNXT_ULP_CLASS_HID_1209 = 0x1209, - BNXT_ULP_CLASS_HID_0bcd = 0x0bcd, - BNXT_ULP_CLASS_HID_1845 = 0x1845, - BNXT_ULP_CLASS_HID_25e9 = 0x25e9, - BNXT_ULP_CLASS_HID_3261 = 0x3261, - BNXT_ULP_CLASS_HID_2c25 = 0x2c25, - BNXT_ULP_CLASS_HID_38bd = 0x38bd, - BNXT_ULP_CLASS_HID_3c1d = 0x3c1d, - BNXT_ULP_CLASS_HID_4895 = 0x4895, - BNXT_ULP_CLASS_HID_4259 = 0x4259, - BNXT_ULP_CLASS_HID_4ed1 = 0x4ed1, - BNXT_ULP_CLASS_HID_5c75 = 0x5c75, - BNXT_ULP_CLASS_HID_0bc1 = 0x0bc1, - BNXT_ULP_CLASS_HID_0585 = 0x0585, - BNXT_ULP_CLASS_HID_121d = 0x121d, - BNXT_ULP_CLASS_HID_58c5 = 0x58c5, - BNXT_ULP_CLASS_HID_0891 = 0x0891, - BNXT_ULP_CLASS_HID_0255 = 0x0255, - BNXT_ULP_CLASS_HID_0eed = 0x0eed, - BNXT_ULP_CLASS_HID_1c71 = 0x1c71, - BNXT_ULP_CLASS_HID_2889 = 0x2889, - BNXT_ULP_CLASS_HID_224d = 0x224d, - BNXT_ULP_CLASS_HID_2ec5 = 0x2ec5, - BNXT_ULP_CLASS_HID_32a5 = 0x32a5, - BNXT_ULP_CLASS_HID_3f3d = 0x3f3d, - BNXT_ULP_CLASS_HID_38e1 = 0x38e1, - BNXT_ULP_CLASS_HID_4579 = 0x4579, - BNXT_ULP_CLASS_HID_529d = 0x529d, - BNXT_ULP_CLASS_HID_0269 = 0x0269, - BNXT_ULP_CLASS_HID_58d9 = 0x58d9, - BNXT_ULP_CLASS_HID_08a5 = 0x08a5, - BNXT_ULP_CLASS_HID_400c5 = 0x400c5, - BNXT_ULP_CLASS_HID_40d5d = 0x40d5d, - BNXT_ULP_CLASS_HID_40701 = 0x40701, - BNXT_ULP_CLASS_HID_41399 = 0x41399, - BNXT_ULP_CLASS_HID_4213d = 0x4213d, - BNXT_ULP_CLASS_HID_42db5 = 0x42db5, - BNXT_ULP_CLASS_HID_42779 = 0x42779, - BNXT_ULP_CLASS_HID_433f1 = 0x433f1, - BNXT_ULP_CLASS_HID_43751 = 0x43751, - BNXT_ULP_CLASS_HID_443e9 = 0x443e9, - BNXT_ULP_CLASS_HID_43dad = 0x43dad, - BNXT_ULP_CLASS_HID_44a25 = 0x44a25, - BNXT_ULP_CLASS_HID_45749 = 0x45749, - BNXT_ULP_CLASS_HID_40715 = 0x40715, - BNXT_ULP_CLASS_HID_400d9 = 0x400d9, - BNXT_ULP_CLASS_HID_40d51 = 0x40d51, - BNXT_ULP_CLASS_HID_45419 = 0x45419, - BNXT_ULP_CLASS_HID_403e5 = 0x403e5, - BNXT_ULP_CLASS_HID_45a55 = 0x45a55, - BNXT_ULP_CLASS_HID_40a21 = 0x40a21, - BNXT_ULP_CLASS_HID_41745 = 0x41745, - BNXT_ULP_CLASS_HID_423dd = 0x423dd, - BNXT_ULP_CLASS_HID_41d81 = 0x41d81, - BNXT_ULP_CLASS_HID_42a19 = 0x42a19, - BNXT_ULP_CLASS_HID_42df9 = 0x42df9, - BNXT_ULP_CLASS_HID_43a71 = 0x43a71, - BNXT_ULP_CLASS_HID_43435 = 0x43435, - BNXT_ULP_CLASS_HID_4404d = 0x4404d, - BNXT_ULP_CLASS_HID_44dd1 = 0x44dd1, - BNXT_ULP_CLASS_HID_45a69 = 0x45a69, - BNXT_ULP_CLASS_HID_4542d = 0x4542d, - BNXT_ULP_CLASS_HID_403f9 = 0x403f9, - BNXT_ULP_CLASS_HID_4140d = 0x4140d, - BNXT_ULP_CLASS_HID_420b5 = 0x420b5, - BNXT_ULP_CLASS_HID_41a49 = 0x41a49, - BNXT_ULP_CLASS_HID_426f1 = 0x426f1, - BNXT_ULP_CLASS_HID_44ab9 = 0x44ab9, - BNXT_ULP_CLASS_HID_45721 = 0x45721, - BNXT_ULP_CLASS_HID_450e5 = 0x450e5, - BNXT_ULP_CLASS_HID_40051 = 0x40051, - BNXT_ULP_CLASS_HID_40aa5 = 0x40aa5, - BNXT_ULP_CLASS_HID_4172d = 0x4172d, - BNXT_ULP_CLASS_HID_410e1 = 0x410e1, - BNXT_ULP_CLASS_HID_41d69 = 0x41d69, - BNXT_ULP_CLASS_HID_440d1 = 0x440d1, - BNXT_ULP_CLASS_HID_44d59 = 0x44d59, - BNXT_ULP_CLASS_HID_4471d = 0x4471d, - BNXT_ULP_CLASS_HID_45385 = 0x45385, - BNXT_ULP_CLASS_HID_6400d = 0x6400d, - BNXT_ULP_CLASS_HID_64cb5 = 0x64cb5, - BNXT_ULP_CLASS_HID_64649 = 0x64649, - BNXT_ULP_CLASS_HID_652f1 = 0x652f1, - BNXT_ULP_CLASS_HID_619ed = 0x619ed, - BNXT_ULP_CLASS_HID_62615 = 0x62615, - BNXT_ULP_CLASS_HID_62029 = 0x62029, - BNXT_ULP_CLASS_HID_62c51 = 0x62c51, - BNXT_ULP_CLASS_HID_636a5 = 0x636a5, - BNXT_ULP_CLASS_HID_6432d = 0x6432d, - BNXT_ULP_CLASS_HID_63ce1 = 0x63ce1, - BNXT_ULP_CLASS_HID_64969 = 0x64969, - BNXT_ULP_CLASS_HID_61005 = 0x61005, - BNXT_ULP_CLASS_HID_61c8d = 0x61c8d, - BNXT_ULP_CLASS_HID_61641 = 0x61641, - BNXT_ULP_CLASS_HID_622c9 = 0x622c9, - BNXT_ULP_CLASS_HID_52a0d = 0x52a0d, - BNXT_ULP_CLASS_HID_536b5 = 0x536b5, - BNXT_ULP_CLASS_HID_53049 = 0x53049, - BNXT_ULP_CLASS_HID_53cf1 = 0x53cf1, - BNXT_ULP_CLASS_HID_503ed = 0x503ed, - BNXT_ULP_CLASS_HID_51015 = 0x51015, - BNXT_ULP_CLASS_HID_50a29 = 0x50a29, - BNXT_ULP_CLASS_HID_51651 = 0x51651, - BNXT_ULP_CLASS_HID_520a5 = 0x520a5, - BNXT_ULP_CLASS_HID_52d2d = 0x52d2d, - BNXT_ULP_CLASS_HID_526e1 = 0x526e1, - BNXT_ULP_CLASS_HID_53369 = 0x53369, - BNXT_ULP_CLASS_HID_556d1 = 0x556d1, - BNXT_ULP_CLASS_HID_5068d = 0x5068d, - BNXT_ULP_CLASS_HID_50041 = 0x50041, - BNXT_ULP_CLASS_HID_50cc9 = 0x50cc9, - BNXT_ULP_CLASS_HID_7560d = 0x7560d, - BNXT_ULP_CLASS_HID_705f9 = 0x705f9, - BNXT_ULP_CLASS_HID_75c49 = 0x75c49, - BNXT_ULP_CLASS_HID_70c25 = 0x70c25, - BNXT_ULP_CLASS_HID_72fed = 0x72fed, - BNXT_ULP_CLASS_HID_73c15 = 0x73c15, - BNXT_ULP_CLASS_HID_73629 = 0x73629, - BNXT_ULP_CLASS_HID_74251 = 0x74251, - BNXT_ULP_CLASS_HID_74ca5 = 0x74ca5, - BNXT_ULP_CLASS_HID_7592d = 0x7592d, - BNXT_ULP_CLASS_HID_752e1 = 0x752e1, - BNXT_ULP_CLASS_HID_7025d = 0x7025d, - BNXT_ULP_CLASS_HID_72605 = 0x72605, - BNXT_ULP_CLASS_HID_7328d = 0x7328d, - BNXT_ULP_CLASS_HID_72c41 = 0x72c41, - BNXT_ULP_CLASS_HID_738c9 = 0x738c9, - BNXT_ULP_CLASS_HID_0591 = 0x0591, - BNXT_ULP_CLASS_HID_1269 = 0x1269, - BNXT_ULP_CLASS_HID_0bad = 0x0bad, - BNXT_ULP_CLASS_HID_1825 = 0x1825, - BNXT_ULP_CLASS_HID_2589 = 0x2589, - BNXT_ULP_CLASS_HID_3201 = 0x3201, - BNXT_ULP_CLASS_HID_2c45 = 0x2c45, - BNXT_ULP_CLASS_HID_38dd = 0x38dd, - BNXT_ULP_CLASS_HID_3c7d = 0x3c7d, - BNXT_ULP_CLASS_HID_48f5 = 0x48f5, - BNXT_ULP_CLASS_HID_4239 = 0x4239, - BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1, - BNXT_ULP_CLASS_HID_5c15 = 0x5c15, - BNXT_ULP_CLASS_HID_0ba1 = 0x0ba1, - BNXT_ULP_CLASS_HID_05e5 = 0x05e5, - BNXT_ULP_CLASS_HID_127d = 0x127d, - BNXT_ULP_CLASS_HID_58a5 = 0x58a5, - BNXT_ULP_CLASS_HID_08f1 = 0x08f1, - BNXT_ULP_CLASS_HID_0235 = 0x0235, - BNXT_ULP_CLASS_HID_0e8d = 0x0e8d, - BNXT_ULP_CLASS_HID_1c11 = 0x1c11, - BNXT_ULP_CLASS_HID_28e9 = 0x28e9, - BNXT_ULP_CLASS_HID_222d = 0x222d, - BNXT_ULP_CLASS_HID_2ea5 = 0x2ea5, - BNXT_ULP_CLASS_HID_32c5 = 0x32c5, - BNXT_ULP_CLASS_HID_3f5d = 0x3f5d, - BNXT_ULP_CLASS_HID_3881 = 0x3881, - BNXT_ULP_CLASS_HID_4519 = 0x4519, - BNXT_ULP_CLASS_HID_52fd = 0x52fd, - BNXT_ULP_CLASS_HID_0209 = 0x0209, - BNXT_ULP_CLASS_HID_58b9 = 0x58b9, - BNXT_ULP_CLASS_HID_08c5 = 0x08c5, - BNXT_ULP_CLASS_HID_400a5 = 0x400a5, - BNXT_ULP_CLASS_HID_40d3d = 0x40d3d, - BNXT_ULP_CLASS_HID_40761 = 0x40761, - BNXT_ULP_CLASS_HID_413f9 = 0x413f9, - BNXT_ULP_CLASS_HID_4215d = 0x4215d, - BNXT_ULP_CLASS_HID_42dd5 = 0x42dd5, - BNXT_ULP_CLASS_HID_42719 = 0x42719, - BNXT_ULP_CLASS_HID_43391 = 0x43391, - BNXT_ULP_CLASS_HID_43731 = 0x43731, - BNXT_ULP_CLASS_HID_44389 = 0x44389, - BNXT_ULP_CLASS_HID_43dcd = 0x43dcd, - BNXT_ULP_CLASS_HID_44a45 = 0x44a45, - BNXT_ULP_CLASS_HID_45729 = 0x45729, - BNXT_ULP_CLASS_HID_40775 = 0x40775, - BNXT_ULP_CLASS_HID_400b9 = 0x400b9, - BNXT_ULP_CLASS_HID_40d31 = 0x40d31, - BNXT_ULP_CLASS_HID_45479 = 0x45479, - BNXT_ULP_CLASS_HID_40385 = 0x40385, - BNXT_ULP_CLASS_HID_45a35 = 0x45a35, - BNXT_ULP_CLASS_HID_40a41 = 0x40a41, - BNXT_ULP_CLASS_HID_41725 = 0x41725, - BNXT_ULP_CLASS_HID_423bd = 0x423bd, - BNXT_ULP_CLASS_HID_41de1 = 0x41de1, - BNXT_ULP_CLASS_HID_42a79 = 0x42a79, - BNXT_ULP_CLASS_HID_42d99 = 0x42d99, - BNXT_ULP_CLASS_HID_43a11 = 0x43a11, - BNXT_ULP_CLASS_HID_43455 = 0x43455, - BNXT_ULP_CLASS_HID_4402d = 0x4402d, - BNXT_ULP_CLASS_HID_44db1 = 0x44db1, - BNXT_ULP_CLASS_HID_45a09 = 0x45a09, - BNXT_ULP_CLASS_HID_4544d = 0x4544d, - BNXT_ULP_CLASS_HID_40399 = 0x40399, - BNXT_ULP_CLASS_HID_4146d = 0x4146d, - BNXT_ULP_CLASS_HID_420d5 = 0x420d5, - BNXT_ULP_CLASS_HID_41a29 = 0x41a29, - BNXT_ULP_CLASS_HID_42691 = 0x42691, - BNXT_ULP_CLASS_HID_44ad9 = 0x44ad9, - BNXT_ULP_CLASS_HID_45741 = 0x45741, - BNXT_ULP_CLASS_HID_45085 = 0x45085, - BNXT_ULP_CLASS_HID_40031 = 0x40031, - BNXT_ULP_CLASS_HID_40ac5 = 0x40ac5, - BNXT_ULP_CLASS_HID_4174d = 0x4174d, - BNXT_ULP_CLASS_HID_41081 = 0x41081, - BNXT_ULP_CLASS_HID_41d09 = 0x41d09, - BNXT_ULP_CLASS_HID_440b1 = 0x440b1, - BNXT_ULP_CLASS_HID_44d39 = 0x44d39, - BNXT_ULP_CLASS_HID_4477d = 0x4477d, - BNXT_ULP_CLASS_HID_453e5 = 0x453e5, - BNXT_ULP_CLASS_HID_6406d = 0x6406d, - BNXT_ULP_CLASS_HID_64cd5 = 0x64cd5, - BNXT_ULP_CLASS_HID_64629 = 0x64629, - BNXT_ULP_CLASS_HID_65291 = 0x65291, - BNXT_ULP_CLASS_HID_6198d = 0x6198d, - BNXT_ULP_CLASS_HID_62675 = 0x62675, - BNXT_ULP_CLASS_HID_62049 = 0x62049, - BNXT_ULP_CLASS_HID_62c31 = 0x62c31, - BNXT_ULP_CLASS_HID_636c5 = 0x636c5, - BNXT_ULP_CLASS_HID_6434d = 0x6434d, - BNXT_ULP_CLASS_HID_63c81 = 0x63c81, - BNXT_ULP_CLASS_HID_64909 = 0x64909, - BNXT_ULP_CLASS_HID_61065 = 0x61065, - BNXT_ULP_CLASS_HID_61ced = 0x61ced, - BNXT_ULP_CLASS_HID_61621 = 0x61621, - BNXT_ULP_CLASS_HID_622a9 = 0x622a9, - BNXT_ULP_CLASS_HID_52a6d = 0x52a6d, - BNXT_ULP_CLASS_HID_536d5 = 0x536d5, - BNXT_ULP_CLASS_HID_53029 = 0x53029, - BNXT_ULP_CLASS_HID_53c91 = 0x53c91, - BNXT_ULP_CLASS_HID_5038d = 0x5038d, - BNXT_ULP_CLASS_HID_51075 = 0x51075, - BNXT_ULP_CLASS_HID_50a49 = 0x50a49, - BNXT_ULP_CLASS_HID_51631 = 0x51631, - BNXT_ULP_CLASS_HID_520c5 = 0x520c5, - BNXT_ULP_CLASS_HID_52d4d = 0x52d4d, - BNXT_ULP_CLASS_HID_52681 = 0x52681, - BNXT_ULP_CLASS_HID_53309 = 0x53309, - BNXT_ULP_CLASS_HID_556b1 = 0x556b1, - BNXT_ULP_CLASS_HID_506ed = 0x506ed, - BNXT_ULP_CLASS_HID_50021 = 0x50021, - BNXT_ULP_CLASS_HID_50ca9 = 0x50ca9, - BNXT_ULP_CLASS_HID_7566d = 0x7566d, - BNXT_ULP_CLASS_HID_70599 = 0x70599, - BNXT_ULP_CLASS_HID_75c29 = 0x75c29, - BNXT_ULP_CLASS_HID_70c45 = 0x70c45, - BNXT_ULP_CLASS_HID_72f8d = 0x72f8d, - BNXT_ULP_CLASS_HID_73c75 = 0x73c75, - BNXT_ULP_CLASS_HID_73649 = 0x73649, - BNXT_ULP_CLASS_HID_74231 = 0x74231, - BNXT_ULP_CLASS_HID_74cc5 = 0x74cc5, - BNXT_ULP_CLASS_HID_7594d = 0x7594d, - BNXT_ULP_CLASS_HID_75281 = 0x75281, - BNXT_ULP_CLASS_HID_7023d = 0x7023d, - BNXT_ULP_CLASS_HID_72665 = 0x72665, - BNXT_ULP_CLASS_HID_732ed = 0x732ed, - BNXT_ULP_CLASS_HID_72c21 = 0x72c21, - BNXT_ULP_CLASS_HID_738a9 = 0x738a9, - BNXT_ULP_CLASS_HID_244c3 = 0x244c3, - BNXT_ULP_CLASS_HID_2515b = 0x2515b, - BNXT_ULP_CLASS_HID_24b1f = 0x24b1f, - BNXT_ULP_CLASS_HID_25797 = 0x25797, - BNXT_ULP_CLASS_HID_22f7f = 0x22f7f, - BNXT_ULP_CLASS_HID_23bf7 = 0x23bf7, - BNXT_ULP_CLASS_HID_235bb = 0x235bb, - BNXT_ULP_CLASS_HID_24233 = 0x24233, - BNXT_ULP_CLASS_HID_20b8b = 0x20b8b, - BNXT_ULP_CLASS_HID_21803 = 0x21803, - BNXT_ULP_CLASS_HID_211c7 = 0x211c7, - BNXT_ULP_CLASS_HID_21e5f = 0x21e5f, - BNXT_ULP_CLASS_HID_252d3 = 0x252d3, - BNXT_ULP_CLASS_HID_202bf = 0x202bf, - BNXT_ULP_CLASS_HID_2592f = 0x2592f, - BNXT_ULP_CLASS_HID_208fb = 0x208fb, - BNXT_ULP_CLASS_HID_231f3 = 0x231f3, - BNXT_ULP_CLASS_HID_23e0b = 0x23e0b, - BNXT_ULP_CLASS_HID_237cf = 0x237cf, - BNXT_ULP_CLASS_HID_24447 = 0x24447, - BNXT_ULP_CLASS_HID_21c2f = 0x21c2f, - BNXT_ULP_CLASS_HID_228a7 = 0x228a7, - BNXT_ULP_CLASS_HID_2226b = 0x2226b, - BNXT_ULP_CLASS_HID_22ee3 = 0x22ee3, - BNXT_ULP_CLASS_HID_25567 = 0x25567, - BNXT_ULP_CLASS_HID_20533 = 0x20533, - BNXT_ULP_CLASS_HID_25ba3 = 0x25ba3, - BNXT_ULP_CLASS_HID_20b0f = 0x20b0f, - BNXT_ULP_CLASS_HID_23f83 = 0x23f83, - BNXT_ULP_CLASS_HID_24c1b = 0x24c1b, - BNXT_ULP_CLASS_HID_245df = 0x245df, - BNXT_ULP_CLASS_HID_25257 = 0x25257, - BNXT_ULP_CLASS_HID_64017 = 0x64017, - BNXT_ULP_CLASS_HID_64caf = 0x64caf, - BNXT_ULP_CLASS_HID_64653 = 0x64653, - BNXT_ULP_CLASS_HID_652eb = 0x652eb, - BNXT_ULP_CLASS_HID_62ab3 = 0x62ab3, - BNXT_ULP_CLASS_HID_636cb = 0x636cb, - BNXT_ULP_CLASS_HID_6308f = 0x6308f, - BNXT_ULP_CLASS_HID_63d07 = 0x63d07, - BNXT_ULP_CLASS_HID_606df = 0x606df, - BNXT_ULP_CLASS_HID_61357 = 0x61357, - BNXT_ULP_CLASS_HID_60d1b = 0x60d1b, - BNXT_ULP_CLASS_HID_61993 = 0x61993, - BNXT_ULP_CLASS_HID_64e27 = 0x64e27, - BNXT_ULP_CLASS_HID_65abf = 0x65abf, - BNXT_ULP_CLASS_HID_65463 = 0x65463, - BNXT_ULP_CLASS_HID_603cf = 0x603cf, - BNXT_ULP_CLASS_HID_62cc7 = 0x62cc7, - BNXT_ULP_CLASS_HID_6395f = 0x6395f, - BNXT_ULP_CLASS_HID_63303 = 0x63303, - BNXT_ULP_CLASS_HID_63f9b = 0x63f9b, - BNXT_ULP_CLASS_HID_61763 = 0x61763, - BNXT_ULP_CLASS_HID_623fb = 0x623fb, - BNXT_ULP_CLASS_HID_61dbf = 0x61dbf, - BNXT_ULP_CLASS_HID_62a37 = 0x62a37, - BNXT_ULP_CLASS_HID_650bb = 0x650bb, - BNXT_ULP_CLASS_HID_60007 = 0x60007, - BNXT_ULP_CLASS_HID_656f7 = 0x656f7, - BNXT_ULP_CLASS_HID_60643 = 0x60643, - BNXT_ULP_CLASS_HID_63ad7 = 0x63ad7, - BNXT_ULP_CLASS_HID_6476f = 0x6476f, - BNXT_ULP_CLASS_HID_64113 = 0x64113, - BNXT_ULP_CLASS_HID_64dab = 0x64dab, - BNXT_ULP_CLASS_HID_35ac3 = 0x35ac3, - BNXT_ULP_CLASS_HID_30aaf = 0x30aaf, - BNXT_ULP_CLASS_HID_30453 = 0x30453, - BNXT_ULP_CLASS_HID_310eb = 0x310eb, - BNXT_ULP_CLASS_HID_3457f = 0x3457f, - BNXT_ULP_CLASS_HID_351f7 = 0x351f7, - BNXT_ULP_CLASS_HID_34bbb = 0x34bbb, - BNXT_ULP_CLASS_HID_35833 = 0x35833, - BNXT_ULP_CLASS_HID_3218b = 0x3218b, - BNXT_ULP_CLASS_HID_32e03 = 0x32e03, - BNXT_ULP_CLASS_HID_327c7 = 0x327c7, - BNXT_ULP_CLASS_HID_3345f = 0x3345f, - BNXT_ULP_CLASS_HID_30c27 = 0x30c27, - BNXT_ULP_CLASS_HID_318bf = 0x318bf, - BNXT_ULP_CLASS_HID_31263 = 0x31263, - BNXT_ULP_CLASS_HID_31efb = 0x31efb, - BNXT_ULP_CLASS_HID_347f3 = 0x347f3, - BNXT_ULP_CLASS_HID_3540b = 0x3540b, - BNXT_ULP_CLASS_HID_34dcf = 0x34dcf, - BNXT_ULP_CLASS_HID_35a47 = 0x35a47, - BNXT_ULP_CLASS_HID_3322f = 0x3322f, - BNXT_ULP_CLASS_HID_33ea7 = 0x33ea7, - BNXT_ULP_CLASS_HID_3386b = 0x3386b, - BNXT_ULP_CLASS_HID_344e3 = 0x344e3, - BNXT_ULP_CLASS_HID_30ebb = 0x30ebb, - BNXT_ULP_CLASS_HID_31b33 = 0x31b33, - BNXT_ULP_CLASS_HID_314f7 = 0x314f7, - BNXT_ULP_CLASS_HID_3210f = 0x3210f, - BNXT_ULP_CLASS_HID_35583 = 0x35583, - BNXT_ULP_CLASS_HID_3056f = 0x3056f, - BNXT_ULP_CLASS_HID_35bdf = 0x35bdf, - BNXT_ULP_CLASS_HID_30bab = 0x30bab, - BNXT_ULP_CLASS_HID_75617 = 0x75617, - BNXT_ULP_CLASS_HID_705e3 = 0x705e3, - BNXT_ULP_CLASS_HID_75c53 = 0x75c53, - BNXT_ULP_CLASS_HID_70c3f = 0x70c3f, - BNXT_ULP_CLASS_HID_740b3 = 0x740b3, - BNXT_ULP_CLASS_HID_74ccb = 0x74ccb, - BNXT_ULP_CLASS_HID_7468f = 0x7468f, - BNXT_ULP_CLASS_HID_75307 = 0x75307, - BNXT_ULP_CLASS_HID_71cdf = 0x71cdf, - BNXT_ULP_CLASS_HID_72957 = 0x72957, - BNXT_ULP_CLASS_HID_7231b = 0x7231b, - BNXT_ULP_CLASS_HID_72f93 = 0x72f93, - BNXT_ULP_CLASS_HID_7077b = 0x7077b, - BNXT_ULP_CLASS_HID_713f3 = 0x713f3, - BNXT_ULP_CLASS_HID_70db7 = 0x70db7, - BNXT_ULP_CLASS_HID_719cf = 0x719cf, - BNXT_ULP_CLASS_HID_742c7 = 0x742c7, - BNXT_ULP_CLASS_HID_74f5f = 0x74f5f, - BNXT_ULP_CLASS_HID_74903 = 0x74903, - BNXT_ULP_CLASS_HID_7559b = 0x7559b, - BNXT_ULP_CLASS_HID_72d63 = 0x72d63, - BNXT_ULP_CLASS_HID_739fb = 0x739fb, - BNXT_ULP_CLASS_HID_733bf = 0x733bf, - BNXT_ULP_CLASS_HID_74037 = 0x74037, - BNXT_ULP_CLASS_HID_7098f = 0x7098f, - BNXT_ULP_CLASS_HID_71607 = 0x71607, - BNXT_ULP_CLASS_HID_70fcb = 0x70fcb, - BNXT_ULP_CLASS_HID_71c43 = 0x71c43, - BNXT_ULP_CLASS_HID_750d7 = 0x750d7, - BNXT_ULP_CLASS_HID_700a3 = 0x700a3, - BNXT_ULP_CLASS_HID_75713 = 0x75713, - BNXT_ULP_CLASS_HID_706ff = 0x706ff, - BNXT_ULP_CLASS_HID_2cfc3 = 0x2cfc3, - BNXT_ULP_CLASS_HID_2dc5b = 0x2dc5b, - BNXT_ULP_CLASS_HID_2d61f = 0x2d61f, - BNXT_ULP_CLASS_HID_285eb = 0x285eb, - BNXT_ULP_CLASS_HID_2ba7f = 0x2ba7f, - BNXT_ULP_CLASS_HID_2c6f7 = 0x2c6f7, - BNXT_ULP_CLASS_HID_2c0bb = 0x2c0bb, - BNXT_ULP_CLASS_HID_2cd33 = 0x2cd33, - BNXT_ULP_CLASS_HID_2968b = 0x2968b, - BNXT_ULP_CLASS_HID_2a303 = 0x2a303, - BNXT_ULP_CLASS_HID_29cc7 = 0x29cc7, - BNXT_ULP_CLASS_HID_2a95f = 0x2a95f, - BNXT_ULP_CLASS_HID_28127 = 0x28127, - BNXT_ULP_CLASS_HID_28dbf = 0x28dbf, - BNXT_ULP_CLASS_HID_28763 = 0x28763, - BNXT_ULP_CLASS_HID_293fb = 0x293fb, - BNXT_ULP_CLASS_HID_2bcf3 = 0x2bcf3, - BNXT_ULP_CLASS_HID_2c90b = 0x2c90b, - BNXT_ULP_CLASS_HID_2c2cf = 0x2c2cf, - BNXT_ULP_CLASS_HID_2cf47 = 0x2cf47, - BNXT_ULP_CLASS_HID_2a72f = 0x2a72f, - BNXT_ULP_CLASS_HID_2b3a7 = 0x2b3a7, - BNXT_ULP_CLASS_HID_2ad6b = 0x2ad6b, - BNXT_ULP_CLASS_HID_2b9e3 = 0x2b9e3, - BNXT_ULP_CLASS_HID_283bb = 0x283bb, - BNXT_ULP_CLASS_HID_29033 = 0x29033, - BNXT_ULP_CLASS_HID_289f7 = 0x289f7, - BNXT_ULP_CLASS_HID_2960f = 0x2960f, - BNXT_ULP_CLASS_HID_2ca83 = 0x2ca83, - BNXT_ULP_CLASS_HID_2d71b = 0x2d71b, - BNXT_ULP_CLASS_HID_2d0df = 0x2d0df, - BNXT_ULP_CLASS_HID_280ab = 0x280ab, - BNXT_ULP_CLASS_HID_6cb17 = 0x6cb17, - BNXT_ULP_CLASS_HID_6d7af = 0x6d7af, - BNXT_ULP_CLASS_HID_6d153 = 0x6d153, - BNXT_ULP_CLASS_HID_6813f = 0x6813f, - BNXT_ULP_CLASS_HID_6b5b3 = 0x6b5b3, - BNXT_ULP_CLASS_HID_6c1cb = 0x6c1cb, - BNXT_ULP_CLASS_HID_6bb8f = 0x6bb8f, - BNXT_ULP_CLASS_HID_6c807 = 0x6c807, - BNXT_ULP_CLASS_HID_691df = 0x691df, - BNXT_ULP_CLASS_HID_69e57 = 0x69e57, - BNXT_ULP_CLASS_HID_6981b = 0x6981b, - BNXT_ULP_CLASS_HID_6a493 = 0x6a493, - BNXT_ULP_CLASS_HID_6d927 = 0x6d927, - BNXT_ULP_CLASS_HID_688f3 = 0x688f3, - BNXT_ULP_CLASS_HID_682b7 = 0x682b7, - BNXT_ULP_CLASS_HID_68ecf = 0x68ecf, - BNXT_ULP_CLASS_HID_6b7c7 = 0x6b7c7, - BNXT_ULP_CLASS_HID_6c45f = 0x6c45f, - BNXT_ULP_CLASS_HID_6be03 = 0x6be03, - BNXT_ULP_CLASS_HID_6ca9b = 0x6ca9b, - BNXT_ULP_CLASS_HID_6a263 = 0x6a263, - BNXT_ULP_CLASS_HID_6aefb = 0x6aefb, - BNXT_ULP_CLASS_HID_6a8bf = 0x6a8bf, - BNXT_ULP_CLASS_HID_6b537 = 0x6b537, - BNXT_ULP_CLASS_HID_6dbbb = 0x6dbbb, - BNXT_ULP_CLASS_HID_68b07 = 0x68b07, - BNXT_ULP_CLASS_HID_684cb = 0x684cb, - BNXT_ULP_CLASS_HID_69143 = 0x69143, - BNXT_ULP_CLASS_HID_6c5d7 = 0x6c5d7, - BNXT_ULP_CLASS_HID_6d26f = 0x6d26f, - BNXT_ULP_CLASS_HID_6cc13 = 0x6cc13, - BNXT_ULP_CLASS_HID_6d8ab = 0x6d8ab, - BNXT_ULP_CLASS_HID_38917 = 0x38917, - BNXT_ULP_CLASS_HID_395af = 0x395af, - BNXT_ULP_CLASS_HID_38f53 = 0x38f53, - BNXT_ULP_CLASS_HID_39beb = 0x39beb, - BNXT_ULP_CLASS_HID_3d07f = 0x3d07f, - BNXT_ULP_CLASS_HID_3dcf7 = 0x3dcf7, - BNXT_ULP_CLASS_HID_3d6bb = 0x3d6bb, - BNXT_ULP_CLASS_HID_38607 = 0x38607, - BNXT_ULP_CLASS_HID_3ac8b = 0x3ac8b, - BNXT_ULP_CLASS_HID_3b903 = 0x3b903, - BNXT_ULP_CLASS_HID_3b2c7 = 0x3b2c7, - BNXT_ULP_CLASS_HID_3bf5f = 0x3bf5f, - BNXT_ULP_CLASS_HID_39727 = 0x39727, - BNXT_ULP_CLASS_HID_3a3bf = 0x3a3bf, - BNXT_ULP_CLASS_HID_39d63 = 0x39d63, - BNXT_ULP_CLASS_HID_3a9fb = 0x3a9fb, - BNXT_ULP_CLASS_HID_3d2f3 = 0x3d2f3, - BNXT_ULP_CLASS_HID_3825f = 0x3825f, - BNXT_ULP_CLASS_HID_3d8cf = 0x3d8cf, - BNXT_ULP_CLASS_HID_3889b = 0x3889b, - BNXT_ULP_CLASS_HID_3bd2f = 0x3bd2f, - BNXT_ULP_CLASS_HID_3c9a7 = 0x3c9a7, - BNXT_ULP_CLASS_HID_3c36b = 0x3c36b, - BNXT_ULP_CLASS_HID_3cfe3 = 0x3cfe3, - BNXT_ULP_CLASS_HID_399bb = 0x399bb, - BNXT_ULP_CLASS_HID_3a633 = 0x3a633, - BNXT_ULP_CLASS_HID_39ff7 = 0x39ff7, - BNXT_ULP_CLASS_HID_3ac0f = 0x3ac0f, - BNXT_ULP_CLASS_HID_383d7 = 0x383d7, - BNXT_ULP_CLASS_HID_3906f = 0x3906f, - BNXT_ULP_CLASS_HID_38a13 = 0x38a13, - BNXT_ULP_CLASS_HID_396ab = 0x396ab, - BNXT_ULP_CLASS_HID_7846b = 0x7846b, - BNXT_ULP_CLASS_HID_790e3 = 0x790e3, - BNXT_ULP_CLASS_HID_78aa7 = 0x78aa7, - BNXT_ULP_CLASS_HID_7973f = 0x7973f, - BNXT_ULP_CLASS_HID_7cbb3 = 0x7cbb3, - BNXT_ULP_CLASS_HID_7d7cb = 0x7d7cb, - BNXT_ULP_CLASS_HID_7d18f = 0x7d18f, - BNXT_ULP_CLASS_HID_7815b = 0x7815b, - BNXT_ULP_CLASS_HID_7a7df = 0x7a7df, - BNXT_ULP_CLASS_HID_7b457 = 0x7b457, - BNXT_ULP_CLASS_HID_7ae1b = 0x7ae1b, - BNXT_ULP_CLASS_HID_7ba93 = 0x7ba93, - BNXT_ULP_CLASS_HID_7927b = 0x7927b, - BNXT_ULP_CLASS_HID_79ef3 = 0x79ef3, - BNXT_ULP_CLASS_HID_798b7 = 0x798b7, - BNXT_ULP_CLASS_HID_7a4cf = 0x7a4cf, - BNXT_ULP_CLASS_HID_7cdc7 = 0x7cdc7, - BNXT_ULP_CLASS_HID_7da5f = 0x7da5f, - BNXT_ULP_CLASS_HID_7d403 = 0x7d403, - BNXT_ULP_CLASS_HID_783ef = 0x783ef, - BNXT_ULP_CLASS_HID_7b863 = 0x7b863, - BNXT_ULP_CLASS_HID_7c4fb = 0x7c4fb, - BNXT_ULP_CLASS_HID_7bebf = 0x7bebf, - BNXT_ULP_CLASS_HID_7cb37 = 0x7cb37, - BNXT_ULP_CLASS_HID_7948f = 0x7948f, - BNXT_ULP_CLASS_HID_7a107 = 0x7a107, - BNXT_ULP_CLASS_HID_79acb = 0x79acb, - BNXT_ULP_CLASS_HID_7a743 = 0x7a743, - BNXT_ULP_CLASS_HID_7dbd7 = 0x7dbd7, - BNXT_ULP_CLASS_HID_78ba3 = 0x78ba3, - BNXT_ULP_CLASS_HID_78567 = 0x78567, - BNXT_ULP_CLASS_HID_791ff = 0x791ff, - BNXT_ULP_CLASS_HID_a3db = 0xa3db, - BNXT_ULP_CLASS_HID_b043 = 0xb043, - BNXT_ULP_CLASS_HID_aa07 = 0xaa07, - BNXT_ULP_CLASS_HID_b68f = 0xb68f, - BNXT_ULP_CLASS_HID_8e67 = 0x8e67, - BNXT_ULP_CLASS_HID_9aef = 0x9aef, - BNXT_ULP_CLASS_HID_94a3 = 0x94a3, - BNXT_ULP_CLASS_HID_a12b = 0xa12b, - BNXT_ULP_CLASS_HID_c7af = 0xc7af, - BNXT_ULP_CLASS_HID_d3d7 = 0xd3d7, - BNXT_ULP_CLASS_HID_cdeb = 0xcdeb, - BNXT_ULP_CLASS_HID_da13 = 0xda13, - BNXT_ULP_CLASS_HID_b1cb = 0xb1cb, - BNXT_ULP_CLASS_HID_be73 = 0xbe73, - BNXT_ULP_CLASS_HID_b837 = 0xb837, - BNXT_ULP_CLASS_HID_c4bf = 0xc4bf, - BNXT_ULP_CLASS_HID_49f0f = 0x49f0f, - BNXT_ULP_CLASS_HID_4abb7 = 0x4abb7, - BNXT_ULP_CLASS_HID_4a54b = 0x4a54b, - BNXT_ULP_CLASS_HID_4b1f3 = 0x4b1f3, - BNXT_ULP_CLASS_HID_489ab = 0x489ab, - BNXT_ULP_CLASS_HID_495d3 = 0x495d3, - BNXT_ULP_CLASS_HID_48f97 = 0x48f97, - BNXT_ULP_CLASS_HID_49c1f = 0x49c1f, - BNXT_ULP_CLASS_HID_4c293 = 0x4c293, - BNXT_ULP_CLASS_HID_4cf1b = 0x4cf1b, - BNXT_ULP_CLASS_HID_4c8df = 0x4c8df, - BNXT_ULP_CLASS_HID_4d547 = 0x4d547, - BNXT_ULP_CLASS_HID_4ad3f = 0x4ad3f, - BNXT_ULP_CLASS_HID_4b9a7 = 0x4b9a7, - BNXT_ULP_CLASS_HID_4b37b = 0x4b37b, - BNXT_ULP_CLASS_HID_4bfe3 = 0x4bfe3, - BNXT_ULP_CLASS_HID_1b9db = 0x1b9db, - BNXT_ULP_CLASS_HID_1c643 = 0x1c643, - BNXT_ULP_CLASS_HID_1c007 = 0x1c007, - BNXT_ULP_CLASS_HID_1cc8f = 0x1cc8f, - BNXT_ULP_CLASS_HID_1a467 = 0x1a467, - BNXT_ULP_CLASS_HID_1b0ef = 0x1b0ef, - BNXT_ULP_CLASS_HID_1aaa3 = 0x1aaa3, - BNXT_ULP_CLASS_HID_1b72b = 0x1b72b, - BNXT_ULP_CLASS_HID_18093 = 0x18093, - BNXT_ULP_CLASS_HID_18d1b = 0x18d1b, - BNXT_ULP_CLASS_HID_186df = 0x186df, - BNXT_ULP_CLASS_HID_19347 = 0x19347, - BNXT_ULP_CLASS_HID_1c7cb = 0x1c7cb, - BNXT_ULP_CLASS_HID_1d473 = 0x1d473, - BNXT_ULP_CLASS_HID_1ce37 = 0x1ce37, - BNXT_ULP_CLASS_HID_1dabf = 0x1dabf, - BNXT_ULP_CLASS_HID_5b50f = 0x5b50f, - BNXT_ULP_CLASS_HID_5c1b7 = 0x5c1b7, - BNXT_ULP_CLASS_HID_5bb4b = 0x5bb4b, - BNXT_ULP_CLASS_HID_5c7f3 = 0x5c7f3, - BNXT_ULP_CLASS_HID_59fab = 0x59fab, - BNXT_ULP_CLASS_HID_5abd3 = 0x5abd3, - BNXT_ULP_CLASS_HID_5a597 = 0x5a597, - BNXT_ULP_CLASS_HID_5b21f = 0x5b21f, - BNXT_ULP_CLASS_HID_5d893 = 0x5d893, - BNXT_ULP_CLASS_HID_5884f = 0x5884f, - BNXT_ULP_CLASS_HID_58203 = 0x58203, - BNXT_ULP_CLASS_HID_58e8b = 0x58e8b, - BNXT_ULP_CLASS_HID_5c33f = 0x5c33f, - BNXT_ULP_CLASS_HID_5cfa7 = 0x5cfa7, - BNXT_ULP_CLASS_HID_5c97b = 0x5c97b, - BNXT_ULP_CLASS_HID_5d5e3 = 0x5d5e3, - BNXT_ULP_CLASS_HID_e95b = 0xe95b, - BNXT_ULP_CLASS_HID_f5c3 = 0xf5c3, - BNXT_ULP_CLASS_HID_ef87 = 0xef87, - BNXT_ULP_CLASS_HID_fc0f = 0xfc0f, - BNXT_ULP_CLASS_HID_d3e7 = 0xd3e7, - BNXT_ULP_CLASS_HID_e06f = 0xe06f, - BNXT_ULP_CLASS_HID_da23 = 0xda23, - BNXT_ULP_CLASS_HID_e6ab = 0xe6ab, - BNXT_ULP_CLASS_HID_cd2f = 0xcd2f, - BNXT_ULP_CLASS_HID_d957 = 0xd957, - BNXT_ULP_CLASS_HID_d36b = 0xd36b, - BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7, - BNXT_ULP_CLASS_HID_f74b = 0xf74b, - BNXT_ULP_CLASS_HID_c3f3 = 0xc3f3, - BNXT_ULP_CLASS_HID_fdb7 = 0xfdb7, - BNXT_ULP_CLASS_HID_ca3f = 0xca3f, - BNXT_ULP_CLASS_HID_4e48f = 0x4e48f, - BNXT_ULP_CLASS_HID_4f137 = 0x4f137, - BNXT_ULP_CLASS_HID_4eacb = 0x4eacb, - BNXT_ULP_CLASS_HID_4f773 = 0x4f773, - BNXT_ULP_CLASS_HID_4cf2b = 0x4cf2b, - BNXT_ULP_CLASS_HID_4db53 = 0x4db53, - BNXT_ULP_CLASS_HID_4d517 = 0x4d517, - BNXT_ULP_CLASS_HID_4e19f = 0x4e19f, - BNXT_ULP_CLASS_HID_4c813 = 0x4c813, - BNXT_ULP_CLASS_HID_4d49b = 0x4d49b, - BNXT_ULP_CLASS_HID_4ce5f = 0x4ce5f, - BNXT_ULP_CLASS_HID_4dac7 = 0x4dac7, - BNXT_ULP_CLASS_HID_4f2bf = 0x4f2bf, - BNXT_ULP_CLASS_HID_4ff27 = 0x4ff27, - BNXT_ULP_CLASS_HID_4f8fb = 0x4f8fb, - BNXT_ULP_CLASS_HID_4c563 = 0x4c563, - BNXT_ULP_CLASS_HID_1ff5b = 0x1ff5b, - BNXT_ULP_CLASS_HID_1cbc3 = 0x1cbc3, - BNXT_ULP_CLASS_HID_1c587 = 0x1c587, - BNXT_ULP_CLASS_HID_1d20f = 0x1d20f, - BNXT_ULP_CLASS_HID_1e9e7 = 0x1e9e7, - BNXT_ULP_CLASS_HID_1f66f = 0x1f66f, - BNXT_ULP_CLASS_HID_1f023 = 0x1f023, - BNXT_ULP_CLASS_HID_1fcab = 0x1fcab, - BNXT_ULP_CLASS_HID_1c613 = 0x1c613, - BNXT_ULP_CLASS_HID_1d29b = 0x1d29b, - BNXT_ULP_CLASS_HID_1cc5f = 0x1cc5f, - BNXT_ULP_CLASS_HID_1d8c7 = 0x1d8c7, - BNXT_ULP_CLASS_HID_1cd4b = 0x1cd4b, - BNXT_ULP_CLASS_HID_1d9f3 = 0x1d9f3, - BNXT_ULP_CLASS_HID_1d3b7 = 0x1d3b7, - BNXT_ULP_CLASS_HID_1c363 = 0x1c363, - BNXT_ULP_CLASS_HID_5fa8f = 0x5fa8f, - BNXT_ULP_CLASS_HID_5c737 = 0x5c737, - BNXT_ULP_CLASS_HID_5c0cb = 0x5c0cb, - BNXT_ULP_CLASS_HID_5cd73 = 0x5cd73, - BNXT_ULP_CLASS_HID_5e52b = 0x5e52b, - BNXT_ULP_CLASS_HID_5f153 = 0x5f153, - BNXT_ULP_CLASS_HID_5eb17 = 0x5eb17, - BNXT_ULP_CLASS_HID_5f79f = 0x5f79f, - BNXT_ULP_CLASS_HID_5c147 = 0x5c147, - BNXT_ULP_CLASS_HID_5cdcf = 0x5cdcf, - BNXT_ULP_CLASS_HID_5c783 = 0x5c783, - BNXT_ULP_CLASS_HID_5d40b = 0x5d40b, - BNXT_ULP_CLASS_HID_5c8bf = 0x5c8bf, - BNXT_ULP_CLASS_HID_5d527 = 0x5d527, - BNXT_ULP_CLASS_HID_5cefb = 0x5cefb, - BNXT_ULP_CLASS_HID_5db63 = 0x5db63, - BNXT_ULP_CLASS_HID_a69b = 0xa69b, - BNXT_ULP_CLASS_HID_b303 = 0xb303, - BNXT_ULP_CLASS_HID_acc7 = 0xacc7, - BNXT_ULP_CLASS_HID_b94f = 0xb94f, - BNXT_ULP_CLASS_HID_b127 = 0xb127, - BNXT_ULP_CLASS_HID_bdaf = 0xbdaf, - BNXT_ULP_CLASS_HID_b763 = 0xb763, - BNXT_ULP_CLASS_HID_a3eb = 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BNXT_ULP_CLASS_HID_5c62f = 0x5c62f, - BNXT_ULP_CLASS_HID_5aa0f = 0x5aa0f, - BNXT_ULP_CLASS_HID_5b04b = 0x5b04b, - BNXT_ULP_CLASS_HID_d0ab = 0xd0ab, - BNXT_ULP_CLASS_HID_d697 = 0xd697, - BNXT_ULP_CLASS_HID_d783 = 0xd783, - BNXT_ULP_CLASS_HID_c133 = 0xc133, - BNXT_ULP_CLASS_HID_f43f = 0xf43f, - BNXT_ULP_CLASS_HID_fa7b = 0xfa7b, - BNXT_ULP_CLASS_HID_de5b = 0xde5b, - BNXT_ULP_CLASS_HID_e487 = 0xe487, - BNXT_ULP_CLASS_HID_4cb9f = 0x4cb9f, - BNXT_ULP_CLASS_HID_4d1db = 0x4d1db, - BNXT_ULP_CLASS_HID_4d2f7 = 0x4d2f7, - BNXT_ULP_CLASS_HID_4d933 = 0x4d933, - BNXT_ULP_CLASS_HID_4ef63 = 0x4ef63, - BNXT_ULP_CLASS_HID_4f5af = 0x4f5af, - BNXT_ULP_CLASS_HID_4d98f = 0x4d98f, - BNXT_ULP_CLASS_HID_4dfcb = 0x4dfcb, - BNXT_ULP_CLASS_HID_1e6ab = 0x1e6ab, - BNXT_ULP_CLASS_HID_1ec97 = 0x1ec97, - BNXT_ULP_CLASS_HID_1d0f7 = 0x1d0f7, - BNXT_ULP_CLASS_HID_1d733 = 0x1d733, - BNXT_ULP_CLASS_HID_1ca3f = 0x1ca3f, - BNXT_ULP_CLASS_HID_1d07b = 0x1d07b, - BNXT_ULP_CLASS_HID_1f45b = 0x1f45b, - BNXT_ULP_CLASS_HID_1fa87 = 0x1fa87, - BNXT_ULP_CLASS_HID_5e19f = 0x5e19f, - BNXT_ULP_CLASS_HID_5e7db = 0x5e7db, - BNXT_ULP_CLASS_HID_5cc3b = 0x5cc3b, - BNXT_ULP_CLASS_HID_5d267 = 0x5d267, - BNXT_ULP_CLASS_HID_5c563 = 0x5c563, - BNXT_ULP_CLASS_HID_5cbaf = 0x5cbaf, - BNXT_ULP_CLASS_HID_5ef8f = 0x5ef8f, - BNXT_ULP_CLASS_HID_5f5cb = 0x5f5cb, - BNXT_ULP_CLASS_HID_adeb = 0xadeb, - BNXT_ULP_CLASS_HID_b3d7 = 0xb3d7, - BNXT_ULP_CLASS_HID_f4c3 = 0xf4c3, - BNXT_ULP_CLASS_HID_fb0f = 0xfb0f, - BNXT_ULP_CLASS_HID_b17f = 0xb17f, - BNXT_ULP_CLASS_HID_b7bb = 0xb7bb, - BNXT_ULP_CLASS_HID_bb9b = 0xbb9b, - BNXT_ULP_CLASS_HID_a1c7 = 0xa1c7, - BNXT_ULP_CLASS_HID_4a8df = 0x4a8df, - BNXT_ULP_CLASS_HID_4af1b = 0x4af1b, - BNXT_ULP_CLASS_HID_4f037 = 0x4f037, - BNXT_ULP_CLASS_HID_4f673 = 0x4f673, - BNXT_ULP_CLASS_HID_4aca3 = 0x4aca3, - BNXT_ULP_CLASS_HID_4b2ef = 0x4b2ef, - BNXT_ULP_CLASS_HID_4b6cf = 0x4b6cf, - BNXT_ULP_CLASS_HID_4bd0b = 0x4bd0b, - BNXT_ULP_CLASS_HID_1a3eb = 0x1a3eb, - BNXT_ULP_CLASS_HID_1a9d7 = 0x1a9d7, - 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0x4f223, - BNXT_ULP_CLASS_HID_4f86f = 0x4f86f, - BNXT_ULP_CLASS_HID_4fc4f = 0x4fc4f, - BNXT_ULP_CLASS_HID_4e28b = 0x4e28b, - BNXT_ULP_CLASS_HID_1e96b = 0x1e96b, - BNXT_ULP_CLASS_HID_1ef57 = 0x1ef57, - BNXT_ULP_CLASS_HID_1f3b7 = 0x1f3b7, - BNXT_ULP_CLASS_HID_1f9f3 = 0x1f9f3, - BNXT_ULP_CLASS_HID_1ecff = 0x1ecff, - BNXT_ULP_CLASS_HID_1f33b = 0x1f33b, - BNXT_ULP_CLASS_HID_1f71b = 0x1f71b, - BNXT_ULP_CLASS_HID_1fd47 = 0x1fd47, - BNXT_ULP_CLASS_HID_5e45f = 0x5e45f, - BNXT_ULP_CLASS_HID_5ea9b = 0x5ea9b, - BNXT_ULP_CLASS_HID_5eefb = 0x5eefb, - BNXT_ULP_CLASS_HID_5f527 = 0x5f527, - BNXT_ULP_CLASS_HID_5e823 = 0x5e823, - BNXT_ULP_CLASS_HID_5ee6f = 0x5ee6f, - BNXT_ULP_CLASS_HID_5f24f = 0x5f24f, - BNXT_ULP_CLASS_HID_5f88b = 0x5f88b, - BNXT_ULP_CLASS_HID_22c53 = 0x22c53, - BNXT_ULP_CLASS_HID_2326f = 0x2326f, - BNXT_ULP_CLASS_HID_2160f = 0x2160f, - BNXT_ULP_CLASS_HID_21ccb = 0x21ccb, - BNXT_ULP_CLASS_HID_24fc7 = 0x24fc7, - BNXT_ULP_CLASS_HID_25583 = 0x25583, - BNXT_ULP_CLASS_HID_239a3 = 0x239a3, - BNXT_ULP_CLASS_HID_2407f = 0x2407f, - BNXT_ULP_CLASS_HID_21883 = 0x21883, - BNXT_ULP_CLASS_HID_21f5f = 0x21f5f, - BNXT_ULP_CLASS_HID_2037f = 0x2037f, - BNXT_ULP_CLASS_HID_2093b = 0x2093b, - BNXT_ULP_CLASS_HID_23c37 = 0x23c37, - BNXT_ULP_CLASS_HID_242f3 = 0x242f3, - BNXT_ULP_CLASS_HID_22693 = 0x22693, - BNXT_ULP_CLASS_HID_22caf = 0x22caf, - BNXT_ULP_CLASS_HID_62767 = 0x62767, - BNXT_ULP_CLASS_HID_62d23 = 0x62d23, - BNXT_ULP_CLASS_HID_611c3 = 0x611c3, - BNXT_ULP_CLASS_HID_6179f = 0x6179f, - BNXT_ULP_CLASS_HID_64a9b = 0x64a9b, - BNXT_ULP_CLASS_HID_65157 = 0x65157, - BNXT_ULP_CLASS_HID_63577 = 0x63577, - BNXT_ULP_CLASS_HID_63b33 = 0x63b33, - BNXT_ULP_CLASS_HID_61457 = 0x61457, - BNXT_ULP_CLASS_HID_61a13 = 0x61a13, - BNXT_ULP_CLASS_HID_65b7f = 0x65b7f, - BNXT_ULP_CLASS_HID_604cf = 0x604cf, - BNXT_ULP_CLASS_HID_637cb = 0x637cb, - BNXT_ULP_CLASS_HID_63d87 = 0x63d87, - BNXT_ULP_CLASS_HID_621a7 = 0x621a7, - BNXT_ULP_CLASS_HID_62863 = 0x62863, - BNXT_ULP_CLASS_HID_34253 = 0x34253, - BNXT_ULP_CLASS_HID_3486f = 0x3486f, - BNXT_ULP_CLASS_HID_32c0f = 0x32c0f, - BNXT_ULP_CLASS_HID_332cb = 0x332cb, - BNXT_ULP_CLASS_HID_3089b = 0x3089b, - BNXT_ULP_CLASS_HID_30f57 = 0x30f57, - BNXT_ULP_CLASS_HID_34fa3 = 0x34fa3, - BNXT_ULP_CLASS_HID_3567f = 0x3567f, - BNXT_ULP_CLASS_HID_32e83 = 0x32e83, - BNXT_ULP_CLASS_HID_3355f = 0x3355f, - BNXT_ULP_CLASS_HID_3197f = 0x3197f, - BNXT_ULP_CLASS_HID_31f3b = 0x31f3b, - BNXT_ULP_CLASS_HID_35237 = 0x35237, - BNXT_ULP_CLASS_HID_358f3 = 0x358f3, - BNXT_ULP_CLASS_HID_33c93 = 0x33c93, - BNXT_ULP_CLASS_HID_342af = 0x342af, - BNXT_ULP_CLASS_HID_73d67 = 0x73d67, - BNXT_ULP_CLASS_HID_74323 = 0x74323, - BNXT_ULP_CLASS_HID_727c3 = 0x727c3, - BNXT_ULP_CLASS_HID_72d9f = 0x72d9f, - BNXT_ULP_CLASS_HID_703af = 0x703af, - BNXT_ULP_CLASS_HID_70a6b = 0x70a6b, - BNXT_ULP_CLASS_HID_74b77 = 0x74b77, - BNXT_ULP_CLASS_HID_75133 = 0x75133, - BNXT_ULP_CLASS_HID_72a57 = 0x72a57, - BNXT_ULP_CLASS_HID_73013 = 0x73013, - BNXT_ULP_CLASS_HID_71433 = 0x71433, - BNXT_ULP_CLASS_HID_71acf = 0x71acf, - BNXT_ULP_CLASS_HID_74dcb = 0x74dcb, - BNXT_ULP_CLASS_HID_75387 = 0x75387, - BNXT_ULP_CLASS_HID_737a7 = 0x737a7, - BNXT_ULP_CLASS_HID_73e63 = 0x73e63, - BNXT_ULP_CLASS_HID_2b753 = 0x2b753, - BNXT_ULP_CLASS_HID_2bd6f = 0x2bd6f, - BNXT_ULP_CLASS_HID_2a10f = 0x2a10f, - BNXT_ULP_CLASS_HID_2a7cb = 0x2a7cb, - BNXT_ULP_CLASS_HID_2dac7 = 0x2dac7, - BNXT_ULP_CLASS_HID_28457 = 0x28457, - BNXT_ULP_CLASS_HID_2c4a3 = 0x2c4a3, - BNXT_ULP_CLASS_HID_2cb7f = 0x2cb7f, - BNXT_ULP_CLASS_HID_2a383 = 0x2a383, - BNXT_ULP_CLASS_HID_2aa5f = 0x2aa5f, - BNXT_ULP_CLASS_HID_28e7f = 0x28e7f, - BNXT_ULP_CLASS_HID_2943b = 0x2943b, - BNXT_ULP_CLASS_HID_2c737 = 0x2c737, - BNXT_ULP_CLASS_HID_2cdf3 = 0x2cdf3, - BNXT_ULP_CLASS_HID_2b193 = 0x2b193, - BNXT_ULP_CLASS_HID_2b7af = 0x2b7af, - BNXT_ULP_CLASS_HID_6b267 = 0x6b267, - BNXT_ULP_CLASS_HID_6b823 = 0x6b823, - BNXT_ULP_CLASS_HID_69cc3 = 0x69cc3, - BNXT_ULP_CLASS_HID_6a29f = 0x6a29f, - BNXT_ULP_CLASS_HID_6d59b = 0x6d59b, - BNXT_ULP_CLASS_HID_6dc57 = 0x6dc57, - BNXT_ULP_CLASS_HID_6c077 = 0x6c077, - BNXT_ULP_CLASS_HID_6c633 = 0x6c633, - BNXT_ULP_CLASS_HID_69f57 = 0x69f57, - BNXT_ULP_CLASS_HID_6a513 = 0x6a513, - BNXT_ULP_CLASS_HID_68933 = 0x68933, - BNXT_ULP_CLASS_HID_68fcf = 0x68fcf, - BNXT_ULP_CLASS_HID_6c2cb = 0x6c2cb, - BNXT_ULP_CLASS_HID_6c887 = 0x6c887, - BNXT_ULP_CLASS_HID_6aca7 = 0x6aca7, - BNXT_ULP_CLASS_HID_6b363 = 0x6b363, - BNXT_ULP_CLASS_HID_3cd53 = 0x3cd53, - BNXT_ULP_CLASS_HID_3d36f = 0x3d36f, - BNXT_ULP_CLASS_HID_3b70f = 0x3b70f, - BNXT_ULP_CLASS_HID_3bdcb = 0x3bdcb, - BNXT_ULP_CLASS_HID_3939b = 0x3939b, - BNXT_ULP_CLASS_HID_39a57 = 0x39a57, - BNXT_ULP_CLASS_HID_3daa3 = 0x3daa3, - BNXT_ULP_CLASS_HID_38433 = 0x38433, - BNXT_ULP_CLASS_HID_3b983 = 0x3b983, - BNXT_ULP_CLASS_HID_3c05f = 0x3c05f, - BNXT_ULP_CLASS_HID_3a47f = 0x3a47f, - BNXT_ULP_CLASS_HID_3aa3b = 0x3aa3b, - BNXT_ULP_CLASS_HID_380cb = 0x380cb, - BNXT_ULP_CLASS_HID_38687 = 0x38687, - BNXT_ULP_CLASS_HID_3c793 = 0x3c793, - BNXT_ULP_CLASS_HID_3cdaf = 0x3cdaf, - BNXT_ULP_CLASS_HID_7c867 = 0x7c867, - BNXT_ULP_CLASS_HID_7ce23 = 0x7ce23, - BNXT_ULP_CLASS_HID_7b2c3 = 0x7b2c3, - BNXT_ULP_CLASS_HID_7b89f = 0x7b89f, - BNXT_ULP_CLASS_HID_78eaf = 0x78eaf, - BNXT_ULP_CLASS_HID_7956b = 0x7956b, - BNXT_ULP_CLASS_HID_7d677 = 0x7d677, - BNXT_ULP_CLASS_HID_7dc33 = 0x7dc33, - BNXT_ULP_CLASS_HID_7b557 = 0x7b557, - BNXT_ULP_CLASS_HID_7bb13 = 0x7bb13, - BNXT_ULP_CLASS_HID_79f33 = 0x79f33, - BNXT_ULP_CLASS_HID_7a5cf = 0x7a5cf, - BNXT_ULP_CLASS_HID_7d8cb = 0x7d8cb, - BNXT_ULP_CLASS_HID_7825b = 0x7825b, - BNXT_ULP_CLASS_HID_7c2a7 = 0x7c2a7, - BNXT_ULP_CLASS_HID_7c963 = 0x7c963, - BNXT_ULP_CLASS_HID_8b4b = 0x8b4b, - BNXT_ULP_CLASS_HID_9177 = 0x9177, - BNXT_ULP_CLASS_HID_d263 = 0xd263, - BNXT_ULP_CLASS_HID_d82f = 0xd82f, - BNXT_ULP_CLASS_HID_aedf = 0xaedf, - BNXT_ULP_CLASS_HID_b49b = 0xb49b, - BNXT_ULP_CLASS_HID_98bb = 0x98bb, - BNXT_ULP_CLASS_HID_9f67 = 0x9f67, - BNXT_ULP_CLASS_HID_4867f = 0x4867f, - BNXT_ULP_CLASS_HID_48c3b = 0x48c3b, - BNXT_ULP_CLASS_HID_4cd17 = 0x4cd17, - BNXT_ULP_CLASS_HID_4d3d3 = 0x4d3d3, - BNXT_ULP_CLASS_HID_4a983 = 0x4a983, - BNXT_ULP_CLASS_HID_4b04f = 0x4b04f, - BNXT_ULP_CLASS_HID_4946f = 0x4946f, - BNXT_ULP_CLASS_HID_49a2b = 0x49a2b, - BNXT_ULP_CLASS_HID_1a14b = 0x1a14b, - BNXT_ULP_CLASS_HID_1a777 = 0x1a777, - BNXT_ULP_CLASS_HID_18b17 = 0x18b17, - BNXT_ULP_CLASS_HID_191d3 = 0x191d3, - BNXT_ULP_CLASS_HID_1c4df = 0x1c4df, - BNXT_ULP_CLASS_HID_1ca9b = 0x1ca9b, - BNXT_ULP_CLASS_HID_1aebb = 0x1aebb, - BNXT_ULP_CLASS_HID_1b567 = 0x1b567, - BNXT_ULP_CLASS_HID_59c7f = 0x59c7f, - BNXT_ULP_CLASS_HID_5a23b = 0x5a23b, - BNXT_ULP_CLASS_HID_586db = 0x586db, - BNXT_ULP_CLASS_HID_58c87 = 0x58c87, - BNXT_ULP_CLASS_HID_5bf83 = 0x5bf83, - BNXT_ULP_CLASS_HID_5c64f = 0x5c64f, - BNXT_ULP_CLASS_HID_5aa6f = 0x5aa6f, - BNXT_ULP_CLASS_HID_5b02b = 0x5b02b, - BNXT_ULP_CLASS_HID_d0cb = 0xd0cb, - BNXT_ULP_CLASS_HID_d6f7 = 0xd6f7, - BNXT_ULP_CLASS_HID_d7e3 = 0xd7e3, - BNXT_ULP_CLASS_HID_c153 = 0xc153, - BNXT_ULP_CLASS_HID_f45f = 0xf45f, - BNXT_ULP_CLASS_HID_fa1b = 0xfa1b, - BNXT_ULP_CLASS_HID_de3b = 0xde3b, - BNXT_ULP_CLASS_HID_e4e7 = 0xe4e7, - BNXT_ULP_CLASS_HID_4cbff = 0x4cbff, - BNXT_ULP_CLASS_HID_4d1bb = 0x4d1bb, - BNXT_ULP_CLASS_HID_4d297 = 0x4d297, - BNXT_ULP_CLASS_HID_4d953 = 0x4d953, - BNXT_ULP_CLASS_HID_4ef03 = 0x4ef03, - BNXT_ULP_CLASS_HID_4f5cf = 0x4f5cf, - BNXT_ULP_CLASS_HID_4d9ef = 0x4d9ef, - BNXT_ULP_CLASS_HID_4dfab = 0x4dfab, - BNXT_ULP_CLASS_HID_1e6cb = 0x1e6cb, - BNXT_ULP_CLASS_HID_1ecf7 = 0x1ecf7, - BNXT_ULP_CLASS_HID_1d097 = 0x1d097, - BNXT_ULP_CLASS_HID_1d753 = 0x1d753, - BNXT_ULP_CLASS_HID_1ca5f = 0x1ca5f, - BNXT_ULP_CLASS_HID_1d01b = 0x1d01b, - BNXT_ULP_CLASS_HID_1f43b = 0x1f43b, - BNXT_ULP_CLASS_HID_1fae7 = 0x1fae7, - BNXT_ULP_CLASS_HID_5e1ff = 0x5e1ff, - BNXT_ULP_CLASS_HID_5e7bb = 0x5e7bb, - BNXT_ULP_CLASS_HID_5cc5b = 0x5cc5b, - BNXT_ULP_CLASS_HID_5d207 = 0x5d207, - BNXT_ULP_CLASS_HID_5c503 = 0x5c503, - BNXT_ULP_CLASS_HID_5cbcf = 0x5cbcf, - BNXT_ULP_CLASS_HID_5efef = 0x5efef, - BNXT_ULP_CLASS_HID_5f5ab = 0x5f5ab, - BNXT_ULP_CLASS_HID_ad8b = 0xad8b, - BNXT_ULP_CLASS_HID_b3b7 = 0xb3b7, - BNXT_ULP_CLASS_HID_f4a3 = 0xf4a3, - BNXT_ULP_CLASS_HID_fb6f = 0xfb6f, - BNXT_ULP_CLASS_HID_b11f = 0xb11f, - BNXT_ULP_CLASS_HID_b7db = 0xb7db, - BNXT_ULP_CLASS_HID_bbfb = 0xbbfb, - BNXT_ULP_CLASS_HID_a1a7 = 0xa1a7, - BNXT_ULP_CLASS_HID_4a8bf = 0x4a8bf, - BNXT_ULP_CLASS_HID_4af7b = 0x4af7b, - BNXT_ULP_CLASS_HID_4f057 = 0x4f057, - BNXT_ULP_CLASS_HID_4f613 = 0x4f613, - BNXT_ULP_CLASS_HID_4acc3 = 0x4acc3, - BNXT_ULP_CLASS_HID_4b28f = 0x4b28f, - BNXT_ULP_CLASS_HID_4b6af = 0x4b6af, - BNXT_ULP_CLASS_HID_4bd6b = 0x4bd6b, - BNXT_ULP_CLASS_HID_1a38b = 0x1a38b, - BNXT_ULP_CLASS_HID_1a9b7 = 0x1a9b7, - BNXT_ULP_CLASS_HID_1ae57 = 0x1ae57, - BNXT_ULP_CLASS_HID_1b413 = 0x1b413, - BNXT_ULP_CLASS_HID_1e71f = 0x1e71f, - BNXT_ULP_CLASS_HID_1eddb = 0x1eddb, - BNXT_ULP_CLASS_HID_1b1fb = 0x1b1fb, - BNXT_ULP_CLASS_HID_1b7a7 = 0x1b7a7, - BNXT_ULP_CLASS_HID_5bebf = 0x5bebf, - BNXT_ULP_CLASS_HID_5a57b = 0x5a57b, - BNXT_ULP_CLASS_HID_5a91b = 0x5a91b, - BNXT_ULP_CLASS_HID_5afc7 = 0x5afc7, - BNXT_ULP_CLASS_HID_5e2c3 = 0x5e2c3, - BNXT_ULP_CLASS_HID_5e88f = 0x5e88f, - BNXT_ULP_CLASS_HID_5acaf = 0x5acaf, - BNXT_ULP_CLASS_HID_5b36b = 0x5b36b, - BNXT_ULP_CLASS_HID_f30b = 0xf30b, - BNXT_ULP_CLASS_HID_f937 = 0xf937, - BNXT_ULP_CLASS_HID_fa23 = 0xfa23, - BNXT_ULP_CLASS_HID_e393 = 0xe393, - BNXT_ULP_CLASS_HID_f69f = 0xf69f, - BNXT_ULP_CLASS_HID_fd5b = 0xfd5b, - BNXT_ULP_CLASS_HID_e17b = 0xe17b, - BNXT_ULP_CLASS_HID_e727 = 0xe727, - BNXT_ULP_CLASS_HID_4ee3f = 0x4ee3f, - BNXT_ULP_CLASS_HID_4f4fb = 0x4f4fb, - BNXT_ULP_CLASS_HID_4f5d7 = 0x4f5d7, - BNXT_ULP_CLASS_HID_4fb93 = 0x4fb93, - BNXT_ULP_CLASS_HID_4f243 = 0x4f243, - BNXT_ULP_CLASS_HID_4f80f = 0x4f80f, - BNXT_ULP_CLASS_HID_4fc2f = 0x4fc2f, - BNXT_ULP_CLASS_HID_4e2eb = 0x4e2eb, - BNXT_ULP_CLASS_HID_1e90b = 0x1e90b, - BNXT_ULP_CLASS_HID_1ef37 = 0x1ef37, - BNXT_ULP_CLASS_HID_1f3d7 = 0x1f3d7, - BNXT_ULP_CLASS_HID_1f993 = 0x1f993, - BNXT_ULP_CLASS_HID_1ec9f = 0x1ec9f, - BNXT_ULP_CLASS_HID_1f35b = 0x1f35b, - BNXT_ULP_CLASS_HID_1f77b = 0x1f77b, - BNXT_ULP_CLASS_HID_1fd27 = 0x1fd27, - BNXT_ULP_CLASS_HID_5e43f = 0x5e43f, - BNXT_ULP_CLASS_HID_5eafb = 0x5eafb, - BNXT_ULP_CLASS_HID_5ee9b = 0x5ee9b, - BNXT_ULP_CLASS_HID_5f547 = 0x5f547, - BNXT_ULP_CLASS_HID_5e843 = 0x5e843, - BNXT_ULP_CLASS_HID_5ee0f = 0x5ee0f, - BNXT_ULP_CLASS_HID_5f22f = 0x5f22f, - BNXT_ULP_CLASS_HID_5f8eb = 0x5f8eb, - BNXT_ULP_CLASS_HID_2579 = 0x2579, - BNXT_ULP_CLASS_HID_2bb5 = 0x2bb5, - BNXT_ULP_CLASS_HID_4591 = 0x4591, - BNXT_ULP_CLASS_HID_4bad = 0x4bad, - BNXT_ULP_CLASS_HID_2561 = 0x2561, - BNXT_ULP_CLASS_HID_2bad = 0x2bad, - BNXT_ULP_CLASS_HID_5bdd = 0x5bdd, - BNXT_ULP_CLASS_HID_054d = 0x054d, - BNXT_ULP_CLASS_HID_257b = 0x257b, - BNXT_ULP_CLASS_HID_2bb7 = 0x2bb7, - BNXT_ULP_CLASS_HID_0fd7 = 0x0fd7, - BNXT_ULP_CLASS_HID_1613 = 0x1613, - BNXT_ULP_CLASS_HID_48ef = 0x48ef, - BNXT_ULP_CLASS_HID_4f2b = 0x4f2b, - BNXT_ULP_CLASS_HID_334b = 0x334b, - BNXT_ULP_CLASS_HID_3987 = 0x3987, - BNXT_ULP_CLASS_HID_122b = 0x122b, - BNXT_ULP_CLASS_HID_1867 = 0x1867, - BNXT_ULP_CLASS_HID_5973 = 0x5973, - BNXT_ULP_CLASS_HID_02c3 = 0x02c3, - BNXT_ULP_CLASS_HID_35df = 0x35df, - BNXT_ULP_CLASS_HID_3c1b = 0x3c1b, - BNXT_ULP_CLASS_HID_203b = 0x203b, - BNXT_ULP_CLASS_HID_2677 = 0x2677, - BNXT_ULP_CLASS_HID_2563 = 0x2563, - BNXT_ULP_CLASS_HID_2baf = 0x2baf, - BNXT_ULP_CLASS_HID_0fcf = 0x0fcf, - BNXT_ULP_CLASS_HID_160b = 0x160b, - BNXT_ULP_CLASS_HID_48f7 = 0x48f7, - BNXT_ULP_CLASS_HID_4f33 = 0x4f33, - BNXT_ULP_CLASS_HID_3353 = 0x3353, - BNXT_ULP_CLASS_HID_399f = 0x399f, - BNXT_ULP_CLASS_HID_42097 = 0x42097, - BNXT_ULP_CLASS_HID_426d3 = 0x426d3, - BNXT_ULP_CLASS_HID_40af3 = 0x40af3, - BNXT_ULP_CLASS_HID_4113f = 0x4113f, - BNXT_ULP_CLASS_HID_4443b = 0x4443b, - BNXT_ULP_CLASS_HID_44a67 = 0x44a67, - BNXT_ULP_CLASS_HID_42e87 = 0x42e87, - BNXT_ULP_CLASS_HID_434c3 = 0x434c3, - BNXT_ULP_CLASS_HID_2559 = 0x2559, - BNXT_ULP_CLASS_HID_2b95 = 0x2b95, - BNXT_ULP_CLASS_HID_45b1 = 0x45b1, - BNXT_ULP_CLASS_HID_4b8d = 0x4b8d, - BNXT_ULP_CLASS_HID_2541 = 0x2541, - BNXT_ULP_CLASS_HID_2b8d = 0x2b8d, - BNXT_ULP_CLASS_HID_5bfd = 0x5bfd, - BNXT_ULP_CLASS_HID_056d = 0x056d, - BNXT_ULP_CLASS_HID_2539 = 0x2539, - BNXT_ULP_CLASS_HID_2bf5 = 0x2bf5, - BNXT_ULP_CLASS_HID_45d1 = 0x45d1, - BNXT_ULP_CLASS_HID_4bed = 0x4bed, - BNXT_ULP_CLASS_HID_2521 = 0x2521, - BNXT_ULP_CLASS_HID_2bed = 0x2bed, - BNXT_ULP_CLASS_HID_5b9d = 0x5b9d, - BNXT_ULP_CLASS_HID_050d = 0x050d, - BNXT_ULP_CLASS_HID_255b = 0x255b, - BNXT_ULP_CLASS_HID_2b97 = 0x2b97, - BNXT_ULP_CLASS_HID_0ff7 = 0x0ff7, - BNXT_ULP_CLASS_HID_1633 = 0x1633, - BNXT_ULP_CLASS_HID_48cf = 0x48cf, - BNXT_ULP_CLASS_HID_4f0b = 0x4f0b, - BNXT_ULP_CLASS_HID_336b = 0x336b, + BNXT_ULP_CLASS_HID_55dd = 0x55dd, + BNXT_ULP_CLASS_HID_1df1 = 0x1df1, + BNXT_ULP_CLASS_HID_3e55 = 0x3e55, + BNXT_ULP_CLASS_HID_0649 = 0x0649, + BNXT_ULP_CLASS_HID_1011 = 0x1011, + BNXT_ULP_CLASS_HID_40e9 = 0x40e9, + BNXT_ULP_CLASS_HID_3e99 = 0x3e99, + BNXT_ULP_CLASS_HID_06ad = 0x06ad, + BNXT_ULP_CLASS_HID_38c7 = 0x38c7, + BNXT_ULP_CLASS_HID_00fb = 0x00fb, + BNXT_ULP_CLASS_HID_24d3 = 0x24d3, + BNXT_ULP_CLASS_HID_559b = 0x559b, + BNXT_ULP_CLASS_HID_5003 = 0x5003, + BNXT_ULP_CLASS_HID_1837 = 0x1837, + BNXT_ULP_CLASS_HID_3bef = 0x3bef, + BNXT_ULP_CLASS_HID_0403 = 0x0403, + BNXT_ULP_CLASS_HID_3d3f = 0x3d3f, + BNXT_ULP_CLASS_HID_0543 = 0x0543, + BNXT_ULP_CLASS_HID_292b = 0x292b, + BNXT_ULP_CLASS_HID_59e3 = 0x59e3, + BNXT_ULP_CLASS_HID_5d3b = 0x5d3b, + BNXT_ULP_CLASS_HID_254f = 0x254f, + BNXT_ULP_CLASS_HID_4917 = 0x4917, + BNXT_ULP_CLASS_HID_113b = 0x113b, + BNXT_ULP_CLASS_HID_55fd = 0x55fd, + BNXT_ULP_CLASS_HID_1dd1 = 0x1dd1, + BNXT_ULP_CLASS_HID_3e75 = 0x3e75, + BNXT_ULP_CLASS_HID_0669 = 0x0669, + BNXT_ULP_CLASS_HID_1ba1 = 0x1ba1, + BNXT_ULP_CLASS_HID_4c69 = 0x4c69, + BNXT_ULP_CLASS_HID_0439 = 0x0439, + BNXT_ULP_CLASS_HID_34e1 = 0x34e1, + BNXT_ULP_CLASS_HID_0465 = 0x0465, + BNXT_ULP_CLASS_HID_352d = 0x352d, + BNXT_ULP_CLASS_HID_55b1 = 0x55b1, + BNXT_ULP_CLASS_HID_1da5 = 0x1da5, + BNXT_ULP_CLASS_HID_32fd = 0x32fd, + BNXT_ULP_CLASS_HID_63a5 = 0x63a5, + BNXT_ULP_CLASS_HID_1b75 = 0x1b75, + BNXT_ULP_CLASS_HID_4c3d = 0x4c3d, + BNXT_ULP_CLASS_HID_1031 = 0x1031, + BNXT_ULP_CLASS_HID_40c9 = 0x40c9, + BNXT_ULP_CLASS_HID_3eb9 = 0x3eb9, + BNXT_ULP_CLASS_HID_068d = 0x068d, + BNXT_ULP_CLASS_HID_5039 = 0x5039, + BNXT_ULP_CLASS_HID_180d = 0x180d, + BNXT_ULP_CLASS_HID_15fd = 0x15fd, + BNXT_ULP_CLASS_HID_46b5 = 0x46b5, + BNXT_ULP_CLASS_HID_303d = 0x303d, + BNXT_ULP_CLASS_HID_60f5 = 0x60f5, + BNXT_ULP_CLASS_HID_5ea5 = 0x5ea5, + BNXT_ULP_CLASS_HID_2689 = 0x2689, + BNXT_ULP_CLASS_HID_0771 = 0x0771, + BNXT_ULP_CLASS_HID_3809 = 0x3809, + BNXT_ULP_CLASS_HID_35f9 = 0x35f9, + BNXT_ULP_CLASS_HID_66b1 = 0x66b1, + BNXT_ULP_CLASS_HID_559d = 0x559d, + BNXT_ULP_CLASS_HID_1db1 = 0x1db1, + BNXT_ULP_CLASS_HID_3e15 = 0x3e15, + BNXT_ULP_CLASS_HID_0609 = 0x0609, + BNXT_ULP_CLASS_HID_1bc1 = 0x1bc1, + BNXT_ULP_CLASS_HID_4c09 = 0x4c09, + BNXT_ULP_CLASS_HID_0459 = 0x0459, + BNXT_ULP_CLASS_HID_3481 = 0x3481, + BNXT_ULP_CLASS_HID_0405 = 0x0405, + BNXT_ULP_CLASS_HID_354d = 0x354d, + BNXT_ULP_CLASS_HID_55d1 = 0x55d1, + BNXT_ULP_CLASS_HID_1dc5 = 0x1dc5, + BNXT_ULP_CLASS_HID_329d = 0x329d, + BNXT_ULP_CLASS_HID_63c5 = 0x63c5, + BNXT_ULP_CLASS_HID_1b15 = 0x1b15, + BNXT_ULP_CLASS_HID_4c5d = 0x4c5d, + BNXT_ULP_CLASS_HID_1051 = 0x1051, + BNXT_ULP_CLASS_HID_40a9 = 0x40a9, + BNXT_ULP_CLASS_HID_3ed9 = 0x3ed9, + BNXT_ULP_CLASS_HID_06ed = 0x06ed, + BNXT_ULP_CLASS_HID_5059 = 0x5059, + BNXT_ULP_CLASS_HID_186d = 0x186d, + BNXT_ULP_CLASS_HID_159d = 0x159d, + BNXT_ULP_CLASS_HID_46d5 = 0x46d5, + BNXT_ULP_CLASS_HID_305d = 0x305d, + BNXT_ULP_CLASS_HID_6095 = 0x6095, + BNXT_ULP_CLASS_HID_5ec5 = 0x5ec5, + BNXT_ULP_CLASS_HID_26e9 = 0x26e9, + BNXT_ULP_CLASS_HID_0711 = 0x0711, + BNXT_ULP_CLASS_HID_3869 = 0x3869, + BNXT_ULP_CLASS_HID_3599 = 0x3599, + BNXT_ULP_CLASS_HID_66d1 = 0x66d1, + BNXT_ULP_CLASS_HID_38e7 = 0x38e7, + BNXT_ULP_CLASS_HID_00db = 0x00db, + BNXT_ULP_CLASS_HID_24f3 = 0x24f3, + BNXT_ULP_CLASS_HID_55bb = 0x55bb, + BNXT_ULP_CLASS_HID_5023 = 0x5023, + BNXT_ULP_CLASS_HID_1817 = 0x1817, + BNXT_ULP_CLASS_HID_3bcf = 0x3bcf, + BNXT_ULP_CLASS_HID_0423 = 0x0423, + BNXT_ULP_CLASS_HID_58e3 = 0x58e3, + BNXT_ULP_CLASS_HID_20d7 = 0x20d7, + BNXT_ULP_CLASS_HID_448f = 0x448f, + BNXT_ULP_CLASS_HID_0ce3 = 0x0ce3, + BNXT_ULP_CLASS_HID_076b = 0x076b, + BNXT_ULP_CLASS_HID_3813 = 0x3813, + BNXT_ULP_CLASS_HID_5bcb = 0x5bcb, + BNXT_ULP_CLASS_HID_243f = 0x243f, + BNXT_ULP_CLASS_HID_144b = 0x144b, + BNXT_ULP_CLASS_HID_4573 = 0x4573, + BNXT_ULP_CLASS_HID_0057 = 0x0057, + BNXT_ULP_CLASS_HID_311f = 0x311f, + BNXT_ULP_CLASS_HID_2b87 = 0x2b87, + BNXT_ULP_CLASS_HID_5c4f = 0x5c4f, + BNXT_ULP_CLASS_HID_1793 = 0x1793, + BNXT_ULP_CLASS_HID_485b = 0x485b, + BNXT_ULP_CLASS_HID_3447 = 0x3447, + BNXT_ULP_CLASS_HID_650f = 0x650f, + BNXT_ULP_CLASS_HID_2053 = 0x2053, + BNXT_ULP_CLASS_HID_511b = 0x511b, + BNXT_ULP_CLASS_HID_4b83 = 0x4b83, + BNXT_ULP_CLASS_HID_13f7 = 0x13f7, + BNXT_ULP_CLASS_HID_37af = 0x37af, + BNXT_ULP_CLASS_HID_6857 = 0x6857, + BNXT_ULP_CLASS_HID_3d1f = 0x3d1f, + BNXT_ULP_CLASS_HID_0563 = 0x0563, + BNXT_ULP_CLASS_HID_290b = 0x290b, + BNXT_ULP_CLASS_HID_59c3 = 0x59c3, + BNXT_ULP_CLASS_HID_5d1b = 0x5d1b, + BNXT_ULP_CLASS_HID_256f = 0x256f, + BNXT_ULP_CLASS_HID_4937 = 0x4937, + BNXT_ULP_CLASS_HID_111b = 0x111b, + BNXT_ULP_CLASS_HID_5f4b = 0x5f4b, + BNXT_ULP_CLASS_HID_275f = 0x275f, + BNXT_ULP_CLASS_HID_4b67 = 0x4b67, + BNXT_ULP_CLASS_HID_134b = 0x134b, + BNXT_ULP_CLASS_HID_1683 = 0x1683, + BNXT_ULP_CLASS_HID_475b = 0x475b, + BNXT_ULP_CLASS_HID_02bf = 0x02bf, + BNXT_ULP_CLASS_HID_3377 = 0x3377, + BNXT_ULP_CLASS_HID_19db = 0x19db, + BNXT_ULP_CLASS_HID_4a93 = 0x4a93, + BNXT_ULP_CLASS_HID_05f7 = 0x05f7, + BNXT_ULP_CLASS_HID_368f = 0x368f, + BNXT_ULP_CLASS_HID_39c7 = 0x39c7, + BNXT_ULP_CLASS_HID_022b = 0x022b, + BNXT_ULP_CLASS_HID_25f3 = 0x25f3, + BNXT_ULP_CLASS_HID_568b = 0x568b, + BNXT_ULP_CLASS_HID_3c37 = 0x3c37, + BNXT_ULP_CLASS_HID_041b = 0x041b, + BNXT_ULP_CLASS_HID_2823 = 0x2823, + BNXT_ULP_CLASS_HID_58fb = 0x58fb, + BNXT_ULP_CLASS_HID_5c33 = 0x5c33, + BNXT_ULP_CLASS_HID_2407 = 0x2407, + BNXT_ULP_CLASS_HID_482f = 0x482f, + BNXT_ULP_CLASS_HID_1033 = 0x1033, + BNXT_ULP_CLASS_HID_3887 = 0x3887, + BNXT_ULP_CLASS_HID_00bb = 0x00bb, + BNXT_ULP_CLASS_HID_2493 = 0x2493, + BNXT_ULP_CLASS_HID_55db = 0x55db, + BNXT_ULP_CLASS_HID_5043 = 0x5043, + BNXT_ULP_CLASS_HID_1877 = 0x1877, + BNXT_ULP_CLASS_HID_3baf = 0x3baf, + BNXT_ULP_CLASS_HID_0443 = 0x0443, + BNXT_ULP_CLASS_HID_5883 = 0x5883, + BNXT_ULP_CLASS_HID_20b7 = 0x20b7, + BNXT_ULP_CLASS_HID_44ef = 0x44ef, + BNXT_ULP_CLASS_HID_0c83 = 0x0c83, + BNXT_ULP_CLASS_HID_070b = 0x070b, + BNXT_ULP_CLASS_HID_3873 = 0x3873, + BNXT_ULP_CLASS_HID_5bab = 0x5bab, + BNXT_ULP_CLASS_HID_245f = 0x245f, + BNXT_ULP_CLASS_HID_142b = 0x142b, + BNXT_ULP_CLASS_HID_4513 = 0x4513, + BNXT_ULP_CLASS_HID_0037 = 0x0037, + BNXT_ULP_CLASS_HID_317f = 0x317f, + BNXT_ULP_CLASS_HID_2be7 = 0x2be7, + BNXT_ULP_CLASS_HID_5c2f = 0x5c2f, + BNXT_ULP_CLASS_HID_17f3 = 0x17f3, + BNXT_ULP_CLASS_HID_483b = 0x483b, + BNXT_ULP_CLASS_HID_3427 = 0x3427, + BNXT_ULP_CLASS_HID_656f = 0x656f, + BNXT_ULP_CLASS_HID_2033 = 0x2033, + BNXT_ULP_CLASS_HID_517b = 0x517b, + BNXT_ULP_CLASS_HID_4be3 = 0x4be3, + BNXT_ULP_CLASS_HID_1397 = 0x1397, + BNXT_ULP_CLASS_HID_37cf = 0x37cf, + BNXT_ULP_CLASS_HID_6837 = 0x6837, + BNXT_ULP_CLASS_HID_3d7f = 0x3d7f, + BNXT_ULP_CLASS_HID_0503 = 0x0503, + BNXT_ULP_CLASS_HID_296b = 0x296b, + BNXT_ULP_CLASS_HID_59a3 = 0x59a3, + BNXT_ULP_CLASS_HID_5d7b = 0x5d7b, + BNXT_ULP_CLASS_HID_250f = 0x250f, + BNXT_ULP_CLASS_HID_4957 = 0x4957, + BNXT_ULP_CLASS_HID_117b = 0x117b, + BNXT_ULP_CLASS_HID_5f2b = 0x5f2b, + BNXT_ULP_CLASS_HID_273f = 0x273f, + BNXT_ULP_CLASS_HID_4b07 = 0x4b07, + BNXT_ULP_CLASS_HID_132b = 0x132b, + BNXT_ULP_CLASS_HID_16e3 = 0x16e3, + BNXT_ULP_CLASS_HID_473b = 0x473b, + BNXT_ULP_CLASS_HID_02df = 0x02df, + BNXT_ULP_CLASS_HID_3317 = 0x3317, + BNXT_ULP_CLASS_HID_19bb = 0x19bb, + BNXT_ULP_CLASS_HID_4af3 = 0x4af3, + BNXT_ULP_CLASS_HID_0597 = 0x0597, + BNXT_ULP_CLASS_HID_36ef = 0x36ef, BNXT_ULP_CLASS_HID_39a7 = 0x39a7, - BNXT_ULP_CLASS_HID_120b = 0x120b, - BNXT_ULP_CLASS_HID_1847 = 0x1847, - BNXT_ULP_CLASS_HID_5953 = 0x5953, - BNXT_ULP_CLASS_HID_02e3 = 0x02e3, - BNXT_ULP_CLASS_HID_35ff = 0x35ff, - BNXT_ULP_CLASS_HID_3c3b = 0x3c3b, - BNXT_ULP_CLASS_HID_201b = 0x201b, - BNXT_ULP_CLASS_HID_2657 = 0x2657, - BNXT_ULP_CLASS_HID_2543 = 0x2543, - BNXT_ULP_CLASS_HID_2b8f = 0x2b8f, - BNXT_ULP_CLASS_HID_0fef = 0x0fef, - BNXT_ULP_CLASS_HID_162b = 0x162b, - BNXT_ULP_CLASS_HID_48d7 = 0x48d7, - BNXT_ULP_CLASS_HID_4f13 = 0x4f13, - BNXT_ULP_CLASS_HID_3373 = 0x3373, - BNXT_ULP_CLASS_HID_39bf = 0x39bf, - BNXT_ULP_CLASS_HID_420b7 = 0x420b7, - BNXT_ULP_CLASS_HID_426f3 = 0x426f3, - BNXT_ULP_CLASS_HID_40ad3 = 0x40ad3, - BNXT_ULP_CLASS_HID_4111f = 0x4111f, - BNXT_ULP_CLASS_HID_4441b = 0x4441b, - BNXT_ULP_CLASS_HID_44a47 = 0x44a47, - BNXT_ULP_CLASS_HID_42ea7 = 0x42ea7, - BNXT_ULP_CLASS_HID_434e3 = 0x434e3, - BNXT_ULP_CLASS_HID_253b = 0x253b, + BNXT_ULP_CLASS_HID_024b = 0x024b, + BNXT_ULP_CLASS_HID_2593 = 0x2593, + BNXT_ULP_CLASS_HID_56eb = 0x56eb, + BNXT_ULP_CLASS_HID_3c57 = 0x3c57, + BNXT_ULP_CLASS_HID_047b = 0x047b, + BNXT_ULP_CLASS_HID_2843 = 0x2843, + BNXT_ULP_CLASS_HID_589b = 0x589b, + BNXT_ULP_CLASS_HID_5c53 = 0x5c53, + BNXT_ULP_CLASS_HID_2467 = 0x2467, + BNXT_ULP_CLASS_HID_484f = 0x484f, + BNXT_ULP_CLASS_HID_1053 = 0x1053, + BNXT_ULP_CLASS_HID_5ce1 = 0x5ce1, + BNXT_ULP_CLASS_HID_4579 = 0x4579, + BNXT_ULP_CLASS_HID_1735 = 0x1735, + BNXT_ULP_CLASS_HID_45bd = 0x45bd, + BNXT_ULP_CLASS_HID_3feb = 0x3feb, BNXT_ULP_CLASS_HID_2bf7 = 0x2bf7, - BNXT_ULP_CLASS_HID_0f97 = 0x0f97, - BNXT_ULP_CLASS_HID_1653 = 0x1653, - BNXT_ULP_CLASS_HID_48af = 0x48af, - BNXT_ULP_CLASS_HID_4f6b = 0x4f6b, - BNXT_ULP_CLASS_HID_330b = 0x330b, - BNXT_ULP_CLASS_HID_39c7 = 0x39c7, - BNXT_ULP_CLASS_HID_126b = 0x126b, - BNXT_ULP_CLASS_HID_1827 = 0x1827, - BNXT_ULP_CLASS_HID_5933 = 0x5933, - BNXT_ULP_CLASS_HID_0283 = 0x0283, - BNXT_ULP_CLASS_HID_359f = 0x359f, - BNXT_ULP_CLASS_HID_3c5b = 0x3c5b, - BNXT_ULP_CLASS_HID_207b = 0x207b, - BNXT_ULP_CLASS_HID_2637 = 0x2637, - BNXT_ULP_CLASS_HID_2523 = 0x2523, - BNXT_ULP_CLASS_HID_2bef = 0x2bef, - BNXT_ULP_CLASS_HID_0f8f = 0x0f8f, - BNXT_ULP_CLASS_HID_164b = 0x164b, - BNXT_ULP_CLASS_HID_48b7 = 0x48b7, - BNXT_ULP_CLASS_HID_4f73 = 0x4f73, - BNXT_ULP_CLASS_HID_3313 = 0x3313, - BNXT_ULP_CLASS_HID_39df = 0x39df, - BNXT_ULP_CLASS_HID_420d7 = 0x420d7, - BNXT_ULP_CLASS_HID_42693 = 0x42693, - BNXT_ULP_CLASS_HID_40ab3 = 0x40ab3, - BNXT_ULP_CLASS_HID_4117f = 0x4117f, - BNXT_ULP_CLASS_HID_4447b = 0x4447b, - BNXT_ULP_CLASS_HID_44a27 = 0x44a27, - BNXT_ULP_CLASS_HID_42ec7 = 0x42ec7, - BNXT_ULP_CLASS_HID_43483 = 0x43483, - BNXT_ULP_CLASS_HID_4156d = 0x4156d, - BNXT_ULP_CLASS_HID_41b29 = 0x41b29, - BNXT_ULP_CLASS_HID_52b6d = 0x52b6d, - BNXT_ULP_CLASS_HID_53129 = 0x53129, - BNXT_ULP_CLASS_HID_478a = 0x478a, - BNXT_ULP_CLASS_HID_03a6 = 0x03a6, - BNXT_ULP_CLASS_HID_4dce = 0x4dce, - BNXT_ULP_CLASS_HID_09ea = 0x09ea, - BNXT_ULP_CLASS_HID_08fe = 0x08fe, - BNXT_ULP_CLASS_HID_23ce = 0x23ce, - BNXT_ULP_CLASS_HID_0e02 = 0x0e02, - BNXT_ULP_CLASS_HID_2912 = 0x2912, - BNXT_ULP_CLASS_HID_3e2a = 0x3e2a, - BNXT_ULP_CLASS_HID_593a = 0x593a, - BNXT_ULP_CLASS_HID_246e = 0x246e, - BNXT_ULP_CLASS_HID_5f7e = 0x5f7e, - BNXT_ULP_CLASS_HID_5e52 = 0x5e52, - BNXT_ULP_CLASS_HID_1a6e = 0x1a6e, - BNXT_ULP_CLASS_HID_4796 = 0x4796, - BNXT_ULP_CLASS_HID_03b2 = 0x03b2, - BNXT_ULP_CLASS_HID_4163a = 0x4163a, - BNXT_ULP_CLASS_HID_4310a = 0x4310a, - BNXT_ULP_CLASS_HID_41c7e = 0x41c7e, - BNXT_ULP_CLASS_HID_4374e = 0x4374e, - BNXT_ULP_CLASS_HID_42f8e = 0x42f8e, - BNXT_ULP_CLASS_HID_4469e = 0x4469e, - BNXT_ULP_CLASS_HID_455c2 = 0x455c2, - BNXT_ULP_CLASS_HID_411ee = 0x411ee, - BNXT_ULP_CLASS_HID_44b76 = 0x44b76, - BNXT_ULP_CLASS_HID_40692 = 0x40692, - BNXT_ULP_CLASS_HID_415c6 = 0x415c6, - BNXT_ULP_CLASS_HID_40cd6 = 0x40cd6, - BNXT_ULP_CLASS_HID_42516 = 0x42516, - BNXT_ULP_CLASS_HID_45ce6 = 0x45ce6, - BNXT_ULP_CLASS_HID_42b2a = 0x42b2a, - BNXT_ULP_CLASS_HID_4423a = 0x4423a, - BNXT_ULP_CLASS_HID_229d8 = 0x229d8, - BNXT_ULP_CLASS_HID_240c8 = 0x240c8, - BNXT_ULP_CLASS_HID_22f14 = 0x22f14, - BNXT_ULP_CLASS_HID_24604 = 0x24604, - BNXT_ULP_CLASS_HID_23374 = 0x23374, - BNXT_ULP_CLASS_HID_22a64 = 0x22a64, - BNXT_ULP_CLASS_HID_238b0 = 0x238b0, - BNXT_ULP_CLASS_HID_253a0 = 0x253a0, - BNXT_ULP_CLASS_HID_24dac = 0x24dac, - BNXT_ULP_CLASS_HID_20990 = 0x20990, - BNXT_ULP_CLASS_HID_214dc = 0x214dc, - BNXT_ULP_CLASS_HID_20fcc = 0x20fcc, - BNXT_ULP_CLASS_HID_257c8 = 0x257c8, - BNXT_ULP_CLASS_HID_2132c = 0x2132c, - BNXT_ULP_CLASS_HID_25d04 = 0x25d04, - BNXT_ULP_CLASS_HID_21968 = 0x21968, - BNXT_ULP_CLASS_HID_234e8 = 0x234e8, - BNXT_ULP_CLASS_HID_22f98 = 0x22f98, - BNXT_ULP_CLASS_HID_23a24 = 0x23a24, - BNXT_ULP_CLASS_HID_255d4 = 0x255d4, - BNXT_ULP_CLASS_HID_21e04 = 0x21e04, - BNXT_ULP_CLASS_HID_23934 = 0x23934, - BNXT_ULP_CLASS_HID_20440 = 0x20440, - BNXT_ULP_CLASS_HID_23f70 = 0x23f70, - BNXT_ULP_CLASS_HID_2597c = 0x2597c, - BNXT_ULP_CLASS_HID_214a0 = 0x214a0, - BNXT_ULP_CLASS_HID_25eb8 = 0x25eb8, - BNXT_ULP_CLASS_HID_21a9c = 0x21a9c, - BNXT_ULP_CLASS_HID_22298 = 0x22298, - BNXT_ULP_CLASS_HID_25d88 = 0x25d88, - BNXT_ULP_CLASS_HID_228d4 = 0x228d4, - BNXT_ULP_CLASS_HID_243c4 = 0x243c4, - BNXT_ULP_CLASS_HID_6220c = 0x6220c, - BNXT_ULP_CLASS_HID_65d3c = 0x65d3c, - BNXT_ULP_CLASS_HID_62848 = 0x62848, - BNXT_ULP_CLASS_HID_64378 = 0x64378, - BNXT_ULP_CLASS_HID_60fa8 = 0x60fa8, - BNXT_ULP_CLASS_HID_62758 = 0x62758, - BNXT_ULP_CLASS_HID_635e4 = 0x635e4, - BNXT_ULP_CLASS_HID_62c94 = 0x62c94, - BNXT_ULP_CLASS_HID_646e0 = 0x646e0, - BNXT_ULP_CLASS_HID_602c4 = 0x602c4, - BNXT_ULP_CLASS_HID_61110 = 0x61110, - BNXT_ULP_CLASS_HID_60800 = 0x60800, - BNXT_ULP_CLASS_HID_6503c = 0x6503c, - BNXT_ULP_CLASS_HID_64b2c = 0x64b2c, - BNXT_ULP_CLASS_HID_65678 = 0x65678, - BNXT_ULP_CLASS_HID_6125c = 0x6125c, - BNXT_ULP_CLASS_HID_631dc = 0x631dc, - BNXT_ULP_CLASS_HID_628cc = 0x628cc, - BNXT_ULP_CLASS_HID_63718 = 0x63718, - BNXT_ULP_CLASS_HID_62e08 = 0x62e08, - BNXT_ULP_CLASS_HID_61b78 = 0x61b78, - BNXT_ULP_CLASS_HID_63268 = 0x63268, - BNXT_ULP_CLASS_HID_600b4 = 0x600b4, - BNXT_ULP_CLASS_HID_63ba4 = 0x63ba4, - BNXT_ULP_CLASS_HID_655b0 = 0x655b0, - BNXT_ULP_CLASS_HID_61194 = 0x61194, - BNXT_ULP_CLASS_HID_65bec = 0x65bec, - BNXT_ULP_CLASS_HID_617d0 = 0x617d0, - BNXT_ULP_CLASS_HID_63fcc = 0x63fcc, - BNXT_ULP_CLASS_HID_656fc = 0x656fc, - BNXT_ULP_CLASS_HID_62508 = 0x62508, - BNXT_ULP_CLASS_HID_65c38 = 0x65c38, - BNXT_ULP_CLASS_HID_86e0 = 0x86e0, - BNXT_ULP_CLASS_HID_a1f0 = 0xa1f0, - BNXT_ULP_CLASS_HID_8c2c = 0x8c2c, - BNXT_ULP_CLASS_HID_a73c = 0xa73c, - BNXT_ULP_CLASS_HID_904c = 0x904c, - BNXT_ULP_CLASS_HID_8b5c = 0x8b5c, - BNXT_ULP_CLASS_HID_9988 = 0x9988, - BNXT_ULP_CLASS_HID_b098 = 0xb098, - BNXT_ULP_CLASS_HID_aa94 = 0xaa94, - BNXT_ULP_CLASS_HID_c264 = 0xc264, - BNXT_ULP_CLASS_HID_d0d0 = 0xd0d0, - BNXT_ULP_CLASS_HID_cba0 = 0xcba0, - BNXT_ULP_CLASS_HID_b4f0 = 0xb4f0, - BNXT_ULP_CLASS_HID_afc0 = 0xafc0, - BNXT_ULP_CLASS_HID_ba3c = 0xba3c, - BNXT_ULP_CLASS_HID_d50c = 0xd50c, - BNXT_ULP_CLASS_HID_48334 = 0x48334, - BNXT_ULP_CLASS_HID_4ba04 = 0x4ba04, - BNXT_ULP_CLASS_HID_48970 = 0x48970, - BNXT_ULP_CLASS_HID_4a040 = 0x4a040, - BNXT_ULP_CLASS_HID_4c84c = 0x4c84c, - BNXT_ULP_CLASS_HID_48460 = 0x48460, - BNXT_ULP_CLASS_HID_492dc = 0x492dc, - BNXT_ULP_CLASS_HID_48dac = 0x48dac, - BNXT_ULP_CLASS_HID_4a7d8 = 0x4a7d8, - BNXT_ULP_CLASS_HID_4dea8 = 0x4dea8, - BNXT_ULP_CLASS_HID_4ade4 = 0x4ade4, - BNXT_ULP_CLASS_HID_4c4f4 = 0x4c4f4, - BNXT_ULP_CLASS_HID_4b104 = 0x4b104, - BNXT_ULP_CLASS_HID_4a814 = 0x4a814, - BNXT_ULP_CLASS_HID_4b740 = 0x4b740, - BNXT_ULP_CLASS_HID_4ae50 = 0x4ae50, - BNXT_ULP_CLASS_HID_1bce0 = 0x1bce0, - BNXT_ULP_CLASS_HID_1d7f0 = 0x1d7f0, - BNXT_ULP_CLASS_HID_1a22c = 0x1a22c, - BNXT_ULP_CLASS_HID_1dd3c = 0x1dd3c, - BNXT_ULP_CLASS_HID_1864c = 0x1864c, - BNXT_ULP_CLASS_HID_1a15c = 0x1a15c, - BNXT_ULP_CLASS_HID_18f88 = 0x18f88, - BNXT_ULP_CLASS_HID_1a698 = 0x1a698, - BNXT_ULP_CLASS_HID_1c094 = 0x1c094, - BNXT_ULP_CLASS_HID_19ca8 = 0x19ca8, - BNXT_ULP_CLASS_HID_1c6d0 = 0x1c6d0, - BNXT_ULP_CLASS_HID_182f4 = 0x182f4, - BNXT_ULP_CLASS_HID_1aaf0 = 0x1aaf0, - BNXT_ULP_CLASS_HID_1c5c0 = 0x1c5c0, - BNXT_ULP_CLASS_HID_1d03c = 0x1d03c, - BNXT_ULP_CLASS_HID_1cb0c = 0x1cb0c, - BNXT_ULP_CLASS_HID_5b934 = 0x5b934, - BNXT_ULP_CLASS_HID_5d004 = 0x5d004, - BNXT_ULP_CLASS_HID_5bf70 = 0x5bf70, - BNXT_ULP_CLASS_HID_5d640 = 0x5d640, - BNXT_ULP_CLASS_HID_58290 = 0x58290, - BNXT_ULP_CLASS_HID_5ba60 = 0x5ba60, - BNXT_ULP_CLASS_HID_588dc = 0x588dc, - BNXT_ULP_CLASS_HID_5a3ac = 0x5a3ac, - BNXT_ULP_CLASS_HID_5ddd8 = 0x5ddd8, - BNXT_ULP_CLASS_HID_599fc = 0x599fc, - BNXT_ULP_CLASS_HID_5c3e4 = 0x5c3e4, - BNXT_ULP_CLASS_HID_59f38 = 0x59f38, - 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BNXT_ULP_CLASS_HID_6be84 = 0x6be84, - BNXT_ULP_CLASS_HID_6d9f4 = 0x6d9f4, - BNXT_ULP_CLASS_HID_694b4 = 0x694b4, - BNXT_ULP_CLASS_HID_68fa4 = 0x68fa4, - BNXT_ULP_CLASS_HID_69a70 = 0x69a70, - BNXT_ULP_CLASS_HID_6b560 = 0x6b560, - BNXT_ULP_CLASS_HID_6dd5c = 0x6dd5c, - BNXT_ULP_CLASS_HID_69900 = 0x69900, - BNXT_ULP_CLASS_HID_6c318 = 0x6c318, - BNXT_ULP_CLASS_HID_69f3c = 0x69f3c, - BNXT_ULP_CLASS_HID_6babc = 0x6babc, - BNXT_ULP_CLASS_HID_6d5ac = 0x6d5ac, - BNXT_ULP_CLASS_HID_6a078 = 0x6a078, - BNXT_ULP_CLASS_HID_6db68 = 0x6db68, - BNXT_ULP_CLASS_HID_68418 = 0x68418, - BNXT_ULP_CLASS_HID_6bf08 = 0x6bf08, - BNXT_ULP_CLASS_HID_68dd4 = 0x68dd4, - BNXT_ULP_CLASS_HID_6a4c4 = 0x6a4c4, - BNXT_ULP_CLASS_HID_6ded0 = 0x6ded0, - BNXT_ULP_CLASS_HID_69af4 = 0x69af4, - BNXT_ULP_CLASS_HID_6c48c = 0x6c48c, - BNXT_ULP_CLASS_HID_680b0 = 0x680b0, - BNXT_ULP_CLASS_HID_6a8ac = 0x6a8ac, - BNXT_ULP_CLASS_HID_6c39c = 0x6c39c, - BNXT_ULP_CLASS_HID_6ae68 = 0x6ae68, - BNXT_ULP_CLASS_HID_6c958 = 0x6c958, - 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BNXT_ULP_CLASS_HID_3828c = 0x3828c, - BNXT_ULP_CLASS_HID_3bdfc = 0x3bdfc, - BNXT_ULP_CLASS_HID_3c5f8 = 0x3c5f8, - BNXT_ULP_CLASS_HID_3819c = 0x3819c, - BNXT_ULP_CLASS_HID_3cbb4 = 0x3cbb4, - BNXT_ULP_CLASS_HID_38758 = 0x38758, - BNXT_ULP_CLASS_HID_7c56c = 0x7c56c, - BNXT_ULP_CLASS_HID_78110 = 0x78110, - BNXT_ULP_CLASS_HID_7cb28 = 0x7cb28, - BNXT_ULP_CLASS_HID_786cc = 0x786cc, - BNXT_ULP_CLASS_HID_7aec8 = 0x7aec8, - BNXT_ULP_CLASS_HID_7c638 = 0x7c638, - BNXT_ULP_CLASS_HID_7d484 = 0x7d484, - BNXT_ULP_CLASS_HID_790a8 = 0x790a8, - BNXT_ULP_CLASS_HID_78ab4 = 0x78ab4, - BNXT_ULP_CLASS_HID_7a5a4 = 0x7a5a4, - BNXT_ULP_CLASS_HID_7b070 = 0x7b070, - BNXT_ULP_CLASS_HID_7ab60 = 0x7ab60, - BNXT_ULP_CLASS_HID_79410 = 0x79410, - BNXT_ULP_CLASS_HID_78f00 = 0x78f00, - BNXT_ULP_CLASS_HID_79dcc = 0x79dcc, - BNXT_ULP_CLASS_HID_7b53c = 0x7b53c, - BNXT_ULP_CLASS_HID_7d0bc = 0x7d0bc, - BNXT_ULP_CLASS_HID_7cbac = 0x7cbac, - BNXT_ULP_CLASS_HID_7d678 = 0x7d678, - BNXT_ULP_CLASS_HID_7921c = 0x7921c, - BNXT_ULP_CLASS_HID_7ba18 = 0x7ba18, - BNXT_ULP_CLASS_HID_7d508 = 0x7d508, - BNXT_ULP_CLASS_HID_7a3d4 = 0x7a3d4, - BNXT_ULP_CLASS_HID_7dac4 = 0x7dac4, - BNXT_ULP_CLASS_HID_79984 = 0x79984, - BNXT_ULP_CLASS_HID_7b0f4 = 0x7b0f4, - BNXT_ULP_CLASS_HID_79f40 = 0x79f40, - BNXT_ULP_CLASS_HID_7b6b0 = 0x7b6b0, - BNXT_ULP_CLASS_HID_7deac = 0x7deac, - BNXT_ULP_CLASS_HID_79a50 = 0x79a50, - BNXT_ULP_CLASS_HID_7c468 = 0x7c468, - BNXT_ULP_CLASS_HID_7800c = 0x7800c, - BNXT_ULP_CLASS_HID_86c0 = 0x86c0, - BNXT_ULP_CLASS_HID_a1d0 = 0xa1d0, - BNXT_ULP_CLASS_HID_8c0c = 0x8c0c, - BNXT_ULP_CLASS_HID_a71c = 0xa71c, - BNXT_ULP_CLASS_HID_906c = 0x906c, - BNXT_ULP_CLASS_HID_8b7c = 0x8b7c, - BNXT_ULP_CLASS_HID_99a8 = 0x99a8, - BNXT_ULP_CLASS_HID_b0b8 = 0xb0b8, - BNXT_ULP_CLASS_HID_aab4 = 0xaab4, - BNXT_ULP_CLASS_HID_c244 = 0xc244, - BNXT_ULP_CLASS_HID_d0f0 = 0xd0f0, - BNXT_ULP_CLASS_HID_cb80 = 0xcb80, - BNXT_ULP_CLASS_HID_b4d0 = 0xb4d0, - BNXT_ULP_CLASS_HID_afe0 = 0xafe0, - BNXT_ULP_CLASS_HID_ba1c = 0xba1c, - BNXT_ULP_CLASS_HID_d52c = 0xd52c, - BNXT_ULP_CLASS_HID_48314 = 0x48314, - BNXT_ULP_CLASS_HID_4ba24 = 0x4ba24, - BNXT_ULP_CLASS_HID_48950 = 0x48950, - BNXT_ULP_CLASS_HID_4a060 = 0x4a060, - BNXT_ULP_CLASS_HID_4c86c = 0x4c86c, - BNXT_ULP_CLASS_HID_48440 = 0x48440, - BNXT_ULP_CLASS_HID_492fc = 0x492fc, - BNXT_ULP_CLASS_HID_48d8c = 0x48d8c, - BNXT_ULP_CLASS_HID_4a7f8 = 0x4a7f8, - BNXT_ULP_CLASS_HID_4de88 = 0x4de88, - BNXT_ULP_CLASS_HID_4adc4 = 0x4adc4, - BNXT_ULP_CLASS_HID_4c4d4 = 0x4c4d4, - BNXT_ULP_CLASS_HID_4b124 = 0x4b124, - BNXT_ULP_CLASS_HID_4a834 = 0x4a834, - BNXT_ULP_CLASS_HID_4b760 = 0x4b760, - BNXT_ULP_CLASS_HID_4ae70 = 0x4ae70, - BNXT_ULP_CLASS_HID_1bcc0 = 0x1bcc0, - BNXT_ULP_CLASS_HID_1d7d0 = 0x1d7d0, - BNXT_ULP_CLASS_HID_1a20c = 0x1a20c, - BNXT_ULP_CLASS_HID_1dd1c = 0x1dd1c, - BNXT_ULP_CLASS_HID_1866c = 0x1866c, - BNXT_ULP_CLASS_HID_1a17c = 0x1a17c, - BNXT_ULP_CLASS_HID_18fa8 = 0x18fa8, - BNXT_ULP_CLASS_HID_1a6b8 = 0x1a6b8, - BNXT_ULP_CLASS_HID_1c0b4 = 0x1c0b4, - BNXT_ULP_CLASS_HID_19c88 = 0x19c88, - BNXT_ULP_CLASS_HID_1c6f0 = 0x1c6f0, - BNXT_ULP_CLASS_HID_182d4 = 0x182d4, - BNXT_ULP_CLASS_HID_1aad0 = 0x1aad0, - BNXT_ULP_CLASS_HID_1c5e0 = 0x1c5e0, - BNXT_ULP_CLASS_HID_1d01c = 0x1d01c, - BNXT_ULP_CLASS_HID_1cb2c = 0x1cb2c, - BNXT_ULP_CLASS_HID_5b914 = 0x5b914, - BNXT_ULP_CLASS_HID_5d024 = 0x5d024, - BNXT_ULP_CLASS_HID_5bf50 = 0x5bf50, - BNXT_ULP_CLASS_HID_5d660 = 0x5d660, - BNXT_ULP_CLASS_HID_582b0 = 0x582b0, - BNXT_ULP_CLASS_HID_5ba40 = 0x5ba40, - BNXT_ULP_CLASS_HID_588fc = 0x588fc, - BNXT_ULP_CLASS_HID_5a38c = 0x5a38c, - BNXT_ULP_CLASS_HID_5ddf8 = 0x5ddf8, - BNXT_ULP_CLASS_HID_599dc = 0x599dc, - BNXT_ULP_CLASS_HID_5c3c4 = 0x5c3c4, - BNXT_ULP_CLASS_HID_59f18 = 0x59f18, - BNXT_ULP_CLASS_HID_5a724 = 0x5a724, - BNXT_ULP_CLASS_HID_5de34 = 0x5de34, - BNXT_ULP_CLASS_HID_5ad60 = 0x5ad60, - BNXT_ULP_CLASS_HID_5c470 = 0x5c470, - BNXT_ULP_CLASS_HID_cd40 = 0xcd40, - BNXT_ULP_CLASS_HID_e450 = 0xe450, - BNXT_ULP_CLASS_HID_f28c = 0xf28c, - BNXT_ULP_CLASS_HID_ed9c = 0xed9c, - BNXT_ULP_CLASS_HID_d6ec = 0xd6ec, - BNXT_ULP_CLASS_HID_f1fc = 0xf1fc, - BNXT_ULP_CLASS_HID_dc28 = 0xdc28, - BNXT_ULP_CLASS_HID_f738 = 0xf738, - BNXT_ULP_CLASS_HID_d134 = 0xd134, - BNXT_ULP_CLASS_HID_c8c4 = 0xc8c4, - BNXT_ULP_CLASS_HID_d770 = 0xd770, - BNXT_ULP_CLASS_HID_d354 = 0xd354, - BNXT_ULP_CLASS_HID_fb50 = 0xfb50, - BNXT_ULP_CLASS_HID_d260 = 0xd260, - BNXT_ULP_CLASS_HID_e09c = 0xe09c, - BNXT_ULP_CLASS_HID_dbac = 0xdbac, - BNXT_ULP_CLASS_HID_4c994 = 0x4c994, - BNXT_ULP_CLASS_HID_4e0a4 = 0x4e0a4, - BNXT_ULP_CLASS_HID_4cfd0 = 0x4cfd0, - BNXT_ULP_CLASS_HID_4e6e0 = 0x4e6e0, - BNXT_ULP_CLASS_HID_4d330 = 0x4d330, - BNXT_ULP_CLASS_HID_4cac0 = 0x4cac0, - BNXT_ULP_CLASS_HID_4d97c = 0x4d97c, - BNXT_ULP_CLASS_HID_4f00c = 0x4f00c, - BNXT_ULP_CLASS_HID_4ea78 = 0x4ea78, - BNXT_ULP_CLASS_HID_4c508 = 0x4c508, - BNXT_ULP_CLASS_HID_4d044 = 0x4d044, - BNXT_ULP_CLASS_HID_4cb54 = 0x4cb54, - BNXT_ULP_CLASS_HID_4f7a4 = 0x4f7a4, - BNXT_ULP_CLASS_HID_4eeb4 = 0x4eeb4, - BNXT_ULP_CLASS_HID_4fde0 = 0x4fde0, - BNXT_ULP_CLASS_HID_4d4f0 = 0x4d4f0, - BNXT_ULP_CLASS_HID_1e340 = 0x1e340, - BNXT_ULP_CLASS_HID_1da50 = 0x1da50, - BNXT_ULP_CLASS_HID_1e88c = 0x1e88c, - BNXT_ULP_CLASS_HID_1c39c = 0x1c39c, - BNXT_ULP_CLASS_HID_1ccec = 0x1ccec, - BNXT_ULP_CLASS_HID_1e7fc = 0x1e7fc, - BNXT_ULP_CLASS_HID_1f228 = 0x1f228, - BNXT_ULP_CLASS_HID_1ed38 = 0x1ed38, - BNXT_ULP_CLASS_HID_1c734 = 0x1c734, - BNXT_ULP_CLASS_HID_1c308 = 0x1c308, - BNXT_ULP_CLASS_HID_1cd70 = 0x1cd70, - BNXT_ULP_CLASS_HID_1c954 = 0x1c954, - BNXT_ULP_CLASS_HID_1d150 = 0x1d150, - BNXT_ULP_CLASS_HID_1c860 = 0x1c860, - BNXT_ULP_CLASS_HID_1d69c = 0x1d69c, - BNXT_ULP_CLASS_HID_1d2f0 = 0x1d2f0, - BNXT_ULP_CLASS_HID_5ff94 = 0x5ff94, - BNXT_ULP_CLASS_HID_5d6a4 = 0x5d6a4, - BNXT_ULP_CLASS_HID_5e5d0 = 0x5e5d0, - BNXT_ULP_CLASS_HID_5dce0 = 0x5dce0, - BNXT_ULP_CLASS_HID_5c930 = 0x5c930, - BNXT_ULP_CLASS_HID_5e0c0 = 0x5e0c0, - BNXT_ULP_CLASS_HID_5cf7c = 0x5cf7c, - BNXT_ULP_CLASS_HID_5e60c = 0x5e60c, - BNXT_ULP_CLASS_HID_5c078 = 0x5c078, - BNXT_ULP_CLASS_HID_5dc5c = 0x5dc5c, - BNXT_ULP_CLASS_HID_5c644 = 0x5c644, - BNXT_ULP_CLASS_HID_5c598 = 0x5c598, - BNXT_ULP_CLASS_HID_5eda4 = 0x5eda4, - BNXT_ULP_CLASS_HID_5c4b4 = 0x5c4b4, - BNXT_ULP_CLASS_HID_5d3e0 = 0x5d3e0, - BNXT_ULP_CLASS_HID_5caf0 = 0x5caf0, - BNXT_ULP_CLASS_HID_ab80 = 0xab80, - BNXT_ULP_CLASS_HID_a290 = 0xa290, - BNXT_ULP_CLASS_HID_b1cc = 0xb1cc, - BNXT_ULP_CLASS_HID_a8dc = 0xa8dc, - BNXT_ULP_CLASS_HID_b52c = 0xb52c, - BNXT_ULP_CLASS_HID_ac3c = 0xac3c, - BNXT_ULP_CLASS_HID_bb68 = 0xbb68, - BNXT_ULP_CLASS_HID_b278 = 0xb278, - BNXT_ULP_CLASS_HID_ac74 = 0xac74, - BNXT_ULP_CLASS_HID_e704 = 0xe704, - BNXT_ULP_CLASS_HID_f5b0 = 0xf5b0, - BNXT_ULP_CLASS_HID_b194 = 0xb194, - BNXT_ULP_CLASS_HID_b990 = 0xb990, - BNXT_ULP_CLASS_HID_f0a0 = 0xf0a0, - BNXT_ULP_CLASS_HID_bfdc = 0xbfdc, - BNXT_ULP_CLASS_HID_f6ec = 0xf6ec, - BNXT_ULP_CLASS_HID_4a4d4 = 0x4a4d4, - BNXT_ULP_CLASS_HID_4bfe4 = 0x4bfe4, - BNXT_ULP_CLASS_HID_4aa10 = 0x4aa10, - BNXT_ULP_CLASS_HID_4a520 = 0x4a520, - BNXT_ULP_CLASS_HID_4ed2c = 0x4ed2c, - BNXT_ULP_CLASS_HID_4a900 = 0x4a900, - BNXT_ULP_CLASS_HID_4b7bc = 0x4b7bc, - BNXT_ULP_CLASS_HID_4af4c = 0x4af4c, - BNXT_ULP_CLASS_HID_4a8b8 = 0x4a8b8, - BNXT_ULP_CLASS_HID_4e048 = 0x4e048, - BNXT_ULP_CLASS_HID_4ae84 = 0x4ae84, - BNXT_ULP_CLASS_HID_4e994 = 0x4e994, - BNXT_ULP_CLASS_HID_4b2e4 = 0x4b2e4, - BNXT_ULP_CLASS_HID_4adf4 = 0x4adf4, - BNXT_ULP_CLASS_HID_4b820 = 0x4b820, - BNXT_ULP_CLASS_HID_4f330 = 0x4f330, - BNXT_ULP_CLASS_HID_1a180 = 0x1a180, - BNXT_ULP_CLASS_HID_1f890 = 0x1f890, - BNXT_ULP_CLASS_HID_1a7cc = 0x1a7cc, - BNXT_ULP_CLASS_HID_1fedc = 0x1fedc, - BNXT_ULP_CLASS_HID_1ab2c = 0x1ab2c, - BNXT_ULP_CLASS_HID_1a23c = 0x1a23c, - BNXT_ULP_CLASS_HID_1b168 = 0x1b168, - BNXT_ULP_CLASS_HID_1a878 = 0x1a878, - BNXT_ULP_CLASS_HID_1e274 = 0x1e274, - BNXT_ULP_CLASS_HID_1be48 = 0x1be48, - BNXT_ULP_CLASS_HID_1ebb0 = 0x1ebb0, - BNXT_ULP_CLASS_HID_1a794 = 0x1a794, - BNXT_ULP_CLASS_HID_1af90 = 0x1af90, - BNXT_ULP_CLASS_HID_1e6a0 = 0x1e6a0, - BNXT_ULP_CLASS_HID_1f5dc = 0x1f5dc, - BNXT_ULP_CLASS_HID_1b130 = 0x1b130, - BNXT_ULP_CLASS_HID_5bad4 = 0x5bad4, - BNXT_ULP_CLASS_HID_5f5e4 = 0x5f5e4, - BNXT_ULP_CLASS_HID_5a010 = 0x5a010, - BNXT_ULP_CLASS_HID_5fb20 = 0x5fb20, - BNXT_ULP_CLASS_HID_5a470 = 0x5a470, - BNXT_ULP_CLASS_HID_5bf00 = 0x5bf00, - BNXT_ULP_CLASS_HID_5adbc = 0x5adbc, - BNXT_ULP_CLASS_HID_5a54c = 0x5a54c, - BNXT_ULP_CLASS_HID_5feb8 = 0x5feb8, - BNXT_ULP_CLASS_HID_5ba9c = 0x5ba9c, - BNXT_ULP_CLASS_HID_5e484 = 0x5e484, - BNXT_ULP_CLASS_HID_5a0d8 = 0x5a0d8, - BNXT_ULP_CLASS_HID_5a8e4 = 0x5a8e4, - BNXT_ULP_CLASS_HID_5e3f4 = 0x5e3f4, - BNXT_ULP_CLASS_HID_5ae20 = 0x5ae20, - BNXT_ULP_CLASS_HID_5e930 = 0x5e930, - BNXT_ULP_CLASS_HID_ee00 = 0xee00, - BNXT_ULP_CLASS_HID_e910 = 0xe910, - BNXT_ULP_CLASS_HID_f44c = 0xf44c, - BNXT_ULP_CLASS_HID_ef5c = 0xef5c, - BNXT_ULP_CLASS_HID_fbac = 0xfbac, - BNXT_ULP_CLASS_HID_f2bc = 0xf2bc, - BNXT_ULP_CLASS_HID_e1e8 = 0xe1e8, - BNXT_ULP_CLASS_HID_f8f8 = 0xf8f8, - BNXT_ULP_CLASS_HID_f2f4 = 0xf2f4, - BNXT_ULP_CLASS_HID_ed84 = 0xed84, - BNXT_ULP_CLASS_HID_f830 = 0xf830, - BNXT_ULP_CLASS_HID_f414 = 0xf414, - BNXT_ULP_CLASS_HID_fc10 = 0xfc10, - BNXT_ULP_CLASS_HID_f720 = 0xf720, - BNXT_ULP_CLASS_HID_e25c = 0xe25c, - BNXT_ULP_CLASS_HID_fd6c = 0xfd6c, - BNXT_ULP_CLASS_HID_4eb54 = 0x4eb54, - BNXT_ULP_CLASS_HID_4e264 = 0x4e264, - BNXT_ULP_CLASS_HID_4f090 = 0x4f090, - BNXT_ULP_CLASS_HID_4eba0 = 0x4eba0, - BNXT_ULP_CLASS_HID_4f4f0 = 0x4f4f0, - BNXT_ULP_CLASS_HID_4ef80 = 0x4ef80, - BNXT_ULP_CLASS_HID_4fa3c = 0x4fa3c, - BNXT_ULP_CLASS_HID_4f5cc = 0x4f5cc, - BNXT_ULP_CLASS_HID_4ef38 = 0x4ef38, - BNXT_ULP_CLASS_HID_4e6c8 = 0x4e6c8, - BNXT_ULP_CLASS_HID_4f504 = 0x4f504, - BNXT_ULP_CLASS_HID_4f158 = 0x4f158, - BNXT_ULP_CLASS_HID_4f964 = 0x4f964, - BNXT_ULP_CLASS_HID_4f074 = 0x4f074, - BNXT_ULP_CLASS_HID_4fea0 = 0x4fea0, - BNXT_ULP_CLASS_HID_4f9b0 = 0x4f9b0, - BNXT_ULP_CLASS_HID_1e400 = 0x1e400, - BNXT_ULP_CLASS_HID_1ff10 = 0x1ff10, - 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BNXT_ULP_CLASS_HID_86a0 = 0x86a0, - BNXT_ULP_CLASS_HID_a1b0 = 0xa1b0, - BNXT_ULP_CLASS_HID_8c6c = 0x8c6c, - BNXT_ULP_CLASS_HID_a77c = 0xa77c, - BNXT_ULP_CLASS_HID_900c = 0x900c, - BNXT_ULP_CLASS_HID_8b1c = 0x8b1c, - BNXT_ULP_CLASS_HID_99c8 = 0x99c8, - BNXT_ULP_CLASS_HID_b0d8 = 0xb0d8, - BNXT_ULP_CLASS_HID_aad4 = 0xaad4, - BNXT_ULP_CLASS_HID_c224 = 0xc224, - BNXT_ULP_CLASS_HID_d090 = 0xd090, - BNXT_ULP_CLASS_HID_cbe0 = 0xcbe0, - BNXT_ULP_CLASS_HID_b4b0 = 0xb4b0, - BNXT_ULP_CLASS_HID_af80 = 0xaf80, - BNXT_ULP_CLASS_HID_ba7c = 0xba7c, - BNXT_ULP_CLASS_HID_d54c = 0xd54c, - BNXT_ULP_CLASS_HID_48374 = 0x48374, - BNXT_ULP_CLASS_HID_4ba44 = 0x4ba44, - BNXT_ULP_CLASS_HID_48930 = 0x48930, - BNXT_ULP_CLASS_HID_4a000 = 0x4a000, - BNXT_ULP_CLASS_HID_4c80c = 0x4c80c, - BNXT_ULP_CLASS_HID_48420 = 0x48420, - BNXT_ULP_CLASS_HID_4929c = 0x4929c, - BNXT_ULP_CLASS_HID_48dec = 0x48dec, - BNXT_ULP_CLASS_HID_4a798 = 0x4a798, - BNXT_ULP_CLASS_HID_4dee8 = 0x4dee8, - BNXT_ULP_CLASS_HID_4ada4 = 0x4ada4, - BNXT_ULP_CLASS_HID_4c4b4 = 0x4c4b4, - BNXT_ULP_CLASS_HID_4b144 = 0x4b144, - BNXT_ULP_CLASS_HID_4a854 = 0x4a854, - BNXT_ULP_CLASS_HID_4b700 = 0x4b700, - BNXT_ULP_CLASS_HID_4ae10 = 0x4ae10, - BNXT_ULP_CLASS_HID_1bca0 = 0x1bca0, - BNXT_ULP_CLASS_HID_1d7b0 = 0x1d7b0, - BNXT_ULP_CLASS_HID_1a26c = 0x1a26c, - BNXT_ULP_CLASS_HID_1dd7c = 0x1dd7c, - BNXT_ULP_CLASS_HID_1860c = 0x1860c, - BNXT_ULP_CLASS_HID_1a11c = 0x1a11c, - BNXT_ULP_CLASS_HID_18fc8 = 0x18fc8, - BNXT_ULP_CLASS_HID_1a6d8 = 0x1a6d8, - BNXT_ULP_CLASS_HID_1c0d4 = 0x1c0d4, - BNXT_ULP_CLASS_HID_19ce8 = 0x19ce8, - BNXT_ULP_CLASS_HID_1c690 = 0x1c690, - BNXT_ULP_CLASS_HID_182b4 = 0x182b4, - BNXT_ULP_CLASS_HID_1aab0 = 0x1aab0, - BNXT_ULP_CLASS_HID_1c580 = 0x1c580, - BNXT_ULP_CLASS_HID_1d07c = 0x1d07c, - BNXT_ULP_CLASS_HID_1cb4c = 0x1cb4c, - BNXT_ULP_CLASS_HID_5b974 = 0x5b974, - BNXT_ULP_CLASS_HID_5d044 = 0x5d044, - BNXT_ULP_CLASS_HID_5bf30 = 0x5bf30, - BNXT_ULP_CLASS_HID_5d600 = 0x5d600, - BNXT_ULP_CLASS_HID_582d0 = 0x582d0, - BNXT_ULP_CLASS_HID_5ba20 = 0x5ba20, - BNXT_ULP_CLASS_HID_5889c = 0x5889c, - BNXT_ULP_CLASS_HID_5a3ec = 0x5a3ec, - BNXT_ULP_CLASS_HID_5dd98 = 0x5dd98, - BNXT_ULP_CLASS_HID_599bc = 0x599bc, - BNXT_ULP_CLASS_HID_5c3a4 = 0x5c3a4, - BNXT_ULP_CLASS_HID_59f78 = 0x59f78, - BNXT_ULP_CLASS_HID_5a744 = 0x5a744, - BNXT_ULP_CLASS_HID_5de54 = 0x5de54, - BNXT_ULP_CLASS_HID_5ad00 = 0x5ad00, - BNXT_ULP_CLASS_HID_5c410 = 0x5c410, - BNXT_ULP_CLASS_HID_cd20 = 0xcd20, - BNXT_ULP_CLASS_HID_e430 = 0xe430, - BNXT_ULP_CLASS_HID_f2ec = 0xf2ec, - BNXT_ULP_CLASS_HID_edfc = 0xedfc, - BNXT_ULP_CLASS_HID_d68c = 0xd68c, - BNXT_ULP_CLASS_HID_f19c = 0xf19c, - BNXT_ULP_CLASS_HID_dc48 = 0xdc48, - BNXT_ULP_CLASS_HID_f758 = 0xf758, - BNXT_ULP_CLASS_HID_d154 = 0xd154, - BNXT_ULP_CLASS_HID_c8a4 = 0xc8a4, - BNXT_ULP_CLASS_HID_d710 = 0xd710, - BNXT_ULP_CLASS_HID_d334 = 0xd334, - BNXT_ULP_CLASS_HID_fb30 = 0xfb30, - BNXT_ULP_CLASS_HID_d200 = 0xd200, - BNXT_ULP_CLASS_HID_e0fc = 0xe0fc, - BNXT_ULP_CLASS_HID_dbcc = 0xdbcc, - BNXT_ULP_CLASS_HID_4c9f4 = 0x4c9f4, - BNXT_ULP_CLASS_HID_4e0c4 = 0x4e0c4, - BNXT_ULP_CLASS_HID_4cfb0 = 0x4cfb0, - BNXT_ULP_CLASS_HID_4e680 = 0x4e680, - BNXT_ULP_CLASS_HID_4d350 = 0x4d350, - BNXT_ULP_CLASS_HID_4caa0 = 0x4caa0, - BNXT_ULP_CLASS_HID_4d91c = 0x4d91c, - BNXT_ULP_CLASS_HID_4f06c = 0x4f06c, - BNXT_ULP_CLASS_HID_4ea18 = 0x4ea18, - BNXT_ULP_CLASS_HID_4c568 = 0x4c568, - BNXT_ULP_CLASS_HID_4d024 = 0x4d024, - BNXT_ULP_CLASS_HID_4cb34 = 0x4cb34, - BNXT_ULP_CLASS_HID_4f7c4 = 0x4f7c4, - BNXT_ULP_CLASS_HID_4eed4 = 0x4eed4, - BNXT_ULP_CLASS_HID_4fd80 = 0x4fd80, - BNXT_ULP_CLASS_HID_4d490 = 0x4d490, - BNXT_ULP_CLASS_HID_1e320 = 0x1e320, - BNXT_ULP_CLASS_HID_1da30 = 0x1da30, - BNXT_ULP_CLASS_HID_1e8ec = 0x1e8ec, - BNXT_ULP_CLASS_HID_1c3fc = 0x1c3fc, - BNXT_ULP_CLASS_HID_1cc8c = 0x1cc8c, - BNXT_ULP_CLASS_HID_1e79c = 0x1e79c, - BNXT_ULP_CLASS_HID_1f248 = 0x1f248, - BNXT_ULP_CLASS_HID_1ed58 = 0x1ed58, - BNXT_ULP_CLASS_HID_1c754 = 0x1c754, - BNXT_ULP_CLASS_HID_1c368 = 0x1c368, - BNXT_ULP_CLASS_HID_1cd10 = 0x1cd10, - BNXT_ULP_CLASS_HID_1c934 = 0x1c934, - BNXT_ULP_CLASS_HID_1d130 = 0x1d130, - BNXT_ULP_CLASS_HID_1c800 = 0x1c800, - BNXT_ULP_CLASS_HID_1d6fc = 0x1d6fc, - BNXT_ULP_CLASS_HID_1d290 = 0x1d290, - BNXT_ULP_CLASS_HID_5fff4 = 0x5fff4, - BNXT_ULP_CLASS_HID_5d6c4 = 0x5d6c4, - BNXT_ULP_CLASS_HID_5e5b0 = 0x5e5b0, - BNXT_ULP_CLASS_HID_5dc80 = 0x5dc80, - BNXT_ULP_CLASS_HID_5c950 = 0x5c950, - BNXT_ULP_CLASS_HID_5e0a0 = 0x5e0a0, - BNXT_ULP_CLASS_HID_5cf1c = 0x5cf1c, - BNXT_ULP_CLASS_HID_5e66c = 0x5e66c, - BNXT_ULP_CLASS_HID_5c018 = 0x5c018, - BNXT_ULP_CLASS_HID_5dc3c = 0x5dc3c, - BNXT_ULP_CLASS_HID_5c624 = 0x5c624, - BNXT_ULP_CLASS_HID_5c5f8 = 0x5c5f8, - BNXT_ULP_CLASS_HID_5edc4 = 0x5edc4, - BNXT_ULP_CLASS_HID_5c4d4 = 0x5c4d4, - BNXT_ULP_CLASS_HID_5d380 = 0x5d380, - BNXT_ULP_CLASS_HID_5ca90 = 0x5ca90, - BNXT_ULP_CLASS_HID_abe0 = 0xabe0, - BNXT_ULP_CLASS_HID_a2f0 = 0xa2f0, - BNXT_ULP_CLASS_HID_b1ac = 0xb1ac, - BNXT_ULP_CLASS_HID_a8bc = 0xa8bc, - BNXT_ULP_CLASS_HID_b54c = 0xb54c, - BNXT_ULP_CLASS_HID_ac5c = 0xac5c, - BNXT_ULP_CLASS_HID_bb08 = 0xbb08, - BNXT_ULP_CLASS_HID_b218 = 0xb218, - BNXT_ULP_CLASS_HID_ac14 = 0xac14, - BNXT_ULP_CLASS_HID_e764 = 0xe764, - BNXT_ULP_CLASS_HID_f5d0 = 0xf5d0, - BNXT_ULP_CLASS_HID_b1f4 = 0xb1f4, - BNXT_ULP_CLASS_HID_b9f0 = 0xb9f0, - BNXT_ULP_CLASS_HID_f0c0 = 0xf0c0, - BNXT_ULP_CLASS_HID_bfbc = 0xbfbc, - BNXT_ULP_CLASS_HID_f68c = 0xf68c, - BNXT_ULP_CLASS_HID_4a4b4 = 0x4a4b4, - BNXT_ULP_CLASS_HID_4bf84 = 0x4bf84, - BNXT_ULP_CLASS_HID_4aa70 = 0x4aa70, - BNXT_ULP_CLASS_HID_4a540 = 0x4a540, - BNXT_ULP_CLASS_HID_4ed4c = 0x4ed4c, - BNXT_ULP_CLASS_HID_4a960 = 0x4a960, - BNXT_ULP_CLASS_HID_4b7dc = 0x4b7dc, - BNXT_ULP_CLASS_HID_4af2c = 0x4af2c, - BNXT_ULP_CLASS_HID_4a8d8 = 0x4a8d8, - BNXT_ULP_CLASS_HID_4e028 = 0x4e028, - BNXT_ULP_CLASS_HID_4aee4 = 0x4aee4, - BNXT_ULP_CLASS_HID_4e9f4 = 0x4e9f4, - BNXT_ULP_CLASS_HID_4b284 = 0x4b284, - BNXT_ULP_CLASS_HID_4ad94 = 0x4ad94, - BNXT_ULP_CLASS_HID_4b840 = 0x4b840, - BNXT_ULP_CLASS_HID_4f350 = 0x4f350, - BNXT_ULP_CLASS_HID_1a1e0 = 0x1a1e0, - BNXT_ULP_CLASS_HID_1f8f0 = 0x1f8f0, - BNXT_ULP_CLASS_HID_1a7ac = 0x1a7ac, - BNXT_ULP_CLASS_HID_1febc = 0x1febc, - BNXT_ULP_CLASS_HID_1ab4c = 0x1ab4c, - BNXT_ULP_CLASS_HID_1a25c = 0x1a25c, - BNXT_ULP_CLASS_HID_1b108 = 0x1b108, - BNXT_ULP_CLASS_HID_1a818 = 0x1a818, - BNXT_ULP_CLASS_HID_1e214 = 0x1e214, - BNXT_ULP_CLASS_HID_1be28 = 0x1be28, - BNXT_ULP_CLASS_HID_1ebd0 = 0x1ebd0, - BNXT_ULP_CLASS_HID_1a7f4 = 0x1a7f4, - BNXT_ULP_CLASS_HID_1aff0 = 0x1aff0, - BNXT_ULP_CLASS_HID_1e6c0 = 0x1e6c0, - BNXT_ULP_CLASS_HID_1f5bc = 0x1f5bc, - BNXT_ULP_CLASS_HID_1b150 = 0x1b150, - BNXT_ULP_CLASS_HID_5bab4 = 0x5bab4, - BNXT_ULP_CLASS_HID_5f584 = 0x5f584, - BNXT_ULP_CLASS_HID_5a070 = 0x5a070, - BNXT_ULP_CLASS_HID_5fb40 = 0x5fb40, - BNXT_ULP_CLASS_HID_5a410 = 0x5a410, - BNXT_ULP_CLASS_HID_5bf60 = 0x5bf60, - BNXT_ULP_CLASS_HID_5addc = 0x5addc, - BNXT_ULP_CLASS_HID_5a52c = 0x5a52c, - BNXT_ULP_CLASS_HID_5fed8 = 0x5fed8, - BNXT_ULP_CLASS_HID_5bafc = 0x5bafc, - BNXT_ULP_CLASS_HID_5e4e4 = 0x5e4e4, - BNXT_ULP_CLASS_HID_5a0b8 = 0x5a0b8, - BNXT_ULP_CLASS_HID_5a884 = 0x5a884, - BNXT_ULP_CLASS_HID_5e394 = 0x5e394, - BNXT_ULP_CLASS_HID_5ae40 = 0x5ae40, - BNXT_ULP_CLASS_HID_5e950 = 0x5e950, - BNXT_ULP_CLASS_HID_ee60 = 0xee60, - BNXT_ULP_CLASS_HID_e970 = 0xe970, - BNXT_ULP_CLASS_HID_f42c = 0xf42c, - BNXT_ULP_CLASS_HID_ef3c = 0xef3c, - BNXT_ULP_CLASS_HID_fbcc = 0xfbcc, - BNXT_ULP_CLASS_HID_f2dc = 0xf2dc, - BNXT_ULP_CLASS_HID_e188 = 0xe188, - BNXT_ULP_CLASS_HID_f898 = 0xf898, - BNXT_ULP_CLASS_HID_f294 = 0xf294, - BNXT_ULP_CLASS_HID_ede4 = 0xede4, - BNXT_ULP_CLASS_HID_f850 = 0xf850, - BNXT_ULP_CLASS_HID_f474 = 0xf474, - BNXT_ULP_CLASS_HID_fc70 = 0xfc70, - BNXT_ULP_CLASS_HID_f740 = 0xf740, - BNXT_ULP_CLASS_HID_e23c = 0xe23c, - BNXT_ULP_CLASS_HID_fd0c = 0xfd0c, - BNXT_ULP_CLASS_HID_4eb34 = 0x4eb34, - BNXT_ULP_CLASS_HID_4e204 = 0x4e204, - BNXT_ULP_CLASS_HID_4f0f0 = 0x4f0f0, - BNXT_ULP_CLASS_HID_4ebc0 = 0x4ebc0, - BNXT_ULP_CLASS_HID_4f490 = 0x4f490, - BNXT_ULP_CLASS_HID_4efe0 = 0x4efe0, - BNXT_ULP_CLASS_HID_4fa5c = 0x4fa5c, - BNXT_ULP_CLASS_HID_4f5ac = 0x4f5ac, - BNXT_ULP_CLASS_HID_4ef58 = 0x4ef58, - BNXT_ULP_CLASS_HID_4e6a8 = 0x4e6a8, - BNXT_ULP_CLASS_HID_4f564 = 0x4f564, - BNXT_ULP_CLASS_HID_4f138 = 0x4f138, - BNXT_ULP_CLASS_HID_4f904 = 0x4f904, - BNXT_ULP_CLASS_HID_4f014 = 0x4f014, - BNXT_ULP_CLASS_HID_4fec0 = 0x4fec0, - BNXT_ULP_CLASS_HID_4f9d0 = 0x4f9d0, - BNXT_ULP_CLASS_HID_1e460 = 0x1e460, - BNXT_ULP_CLASS_HID_1ff70 = 0x1ff70, - BNXT_ULP_CLASS_HID_1ea2c = 0x1ea2c, - BNXT_ULP_CLASS_HID_1e53c = 0x1e53c, - BNXT_ULP_CLASS_HID_1f1cc = 0x1f1cc, - BNXT_ULP_CLASS_HID_1e8dc = 0x1e8dc, - BNXT_ULP_CLASS_HID_1f788 = 0x1f788, - BNXT_ULP_CLASS_HID_1ee98 = 0x1ee98, - BNXT_ULP_CLASS_HID_1e894 = 0x1e894, - BNXT_ULP_CLASS_HID_1e4a8 = 0x1e4a8, - BNXT_ULP_CLASS_HID_1f364 = 0x1f364, - BNXT_ULP_CLASS_HID_1ea74 = 0x1ea74, - BNXT_ULP_CLASS_HID_1f270 = 0x1f270, - BNXT_ULP_CLASS_HID_1ed40 = 0x1ed40, - BNXT_ULP_CLASS_HID_1f83c = 0x1f83c, - BNXT_ULP_CLASS_HID_1f7d0 = 0x1f7d0, - BNXT_ULP_CLASS_HID_5e134 = 0x5e134, - BNXT_ULP_CLASS_HID_5f804 = 0x5f804, - BNXT_ULP_CLASS_HID_5e6f0 = 0x5e6f0, - BNXT_ULP_CLASS_HID_5e1c0 = 0x5e1c0, - BNXT_ULP_CLASS_HID_5ea90 = 0x5ea90, - BNXT_ULP_CLASS_HID_5e5e0 = 0x5e5e0, - BNXT_ULP_CLASS_HID_5f05c = 0x5f05c, - BNXT_ULP_CLASS_HID_5ebac = 0x5ebac, - BNXT_ULP_CLASS_HID_5e558 = 0x5e558, - BNXT_ULP_CLASS_HID_5e17c = 0x5e17c, - BNXT_ULP_CLASS_HID_5eb64 = 0x5eb64, - BNXT_ULP_CLASS_HID_5e738 = 0x5e738, - BNXT_ULP_CLASS_HID_5ef04 = 0x5ef04, - BNXT_ULP_CLASS_HID_5e614 = 0x5e614, - BNXT_ULP_CLASS_HID_5f4c0 = 0x5f4c0, - BNXT_ULP_CLASS_HID_5f0e4 = 0x5f0e4, - BNXT_ULP_CLASS_HID_5802 = 0x5802, - BNXT_ULP_CLASS_HID_5e46 = 0x5e46, - BNXT_ULP_CLASS_HID_1d76 = 0x1d76, - BNXT_ULP_CLASS_HID_02ba = 0x02ba, - BNXT_ULP_CLASS_HID_32a2 = 0x32a2, - BNXT_ULP_CLASS_HID_38e6 = 0x38e6, - BNXT_ULP_CLASS_HID_52ca = 0x52ca, - BNXT_ULP_CLASS_HID_580e = 0x580e, - BNXT_ULP_CLASS_HID_44996 = 0x44996, - BNXT_ULP_CLASS_HID_410e6 = 0x410e6, - BNXT_ULP_CLASS_HID_42036 = 0x42036, - BNXT_ULP_CLASS_HID_4264a = 0x4264a, - BNXT_ULP_CLASS_HID_45ffe = 0x45ffe, - BNXT_ULP_CLASS_HID_44532 = 0x44532, - BNXT_ULP_CLASS_HID_4399e = 0x4399e, - BNXT_ULP_CLASS_HID_43fd2 = 0x43fd2, - BNXT_ULP_CLASS_HID_23da0 = 0x23da0, - BNXT_ULP_CLASS_HID_2239c = 0x2239c, - BNXT_ULP_CLASS_HID_207fc = 0x207fc, - BNXT_ULP_CLASS_HID_20d38 = 0x20d38, - BNXT_ULP_CLASS_HID_25e34 = 0x25e34, - BNXT_ULP_CLASS_HID_24470 = 0x24470, - BNXT_ULP_CLASS_HID_22850 = 0x22850, - BNXT_ULP_CLASS_HID_2518c = 0x2518c, - BNXT_ULP_CLASS_HID_20970 = 0x20970, - BNXT_ULP_CLASS_HID_20eac = 0x20eac, - BNXT_ULP_CLASS_HID_2128c = 0x2128c, - BNXT_ULP_CLASS_HID_218c8 = 0x218c8, - BNXT_ULP_CLASS_HID_22dc4 = 0x22dc4, - BNXT_ULP_CLASS_HID_25300 = 0x25300, - BNXT_ULP_CLASS_HID_23760 = 0x23760, - BNXT_ULP_CLASS_HID_23d5c = 0x23d5c, - BNXT_ULP_CLASS_HID_63694 = 0x63694, - BNXT_ULP_CLASS_HID_63cd0 = 0x63cd0, - BNXT_ULP_CLASS_HID_60030 = 0x60030, - BNXT_ULP_CLASS_HID_6066c = 0x6066c, - BNXT_ULP_CLASS_HID_65b68 = 0x65b68, - BNXT_ULP_CLASS_HID_640a4 = 0x640a4, - BNXT_ULP_CLASS_HID_62484 = 0x62484, - BNXT_ULP_CLASS_HID_62ac0 = 0x62ac0, - BNXT_ULP_CLASS_HID_605a4 = 0x605a4, - BNXT_ULP_CLASS_HID_60be0 = 0x60be0, - BNXT_ULP_CLASS_HID_64a8c = 0x64a8c, - BNXT_ULP_CLASS_HID_6153c = 0x6153c, - BNXT_ULP_CLASS_HID_62638 = 0x62638, - BNXT_ULP_CLASS_HID_62c74 = 0x62c74, - BNXT_ULP_CLASS_HID_63054 = 0x63054, - BNXT_ULP_CLASS_HID_63990 = 0x63990, - BNXT_ULP_CLASS_HID_9a98 = 0x9a98, - BNXT_ULP_CLASS_HID_80a4 = 0x80a4, - BNXT_ULP_CLASS_HID_c3b0 = 0xc3b0, - BNXT_ULP_CLASS_HID_c9fc = 0xc9fc, - BNXT_ULP_CLASS_HID_bf0c = 0xbf0c, - BNXT_ULP_CLASS_HID_a548 = 0xa548, - BNXT_ULP_CLASS_HID_8968 = 0x8968, - BNXT_ULP_CLASS_HID_8eb4 = 0x8eb4, - BNXT_ULP_CLASS_HID_497ac = 0x497ac, - BNXT_ULP_CLASS_HID_49de8 = 0x49de8, - BNXT_ULP_CLASS_HID_4dcc4 = 0x4dcc4, - BNXT_ULP_CLASS_HID_4c200 = 0x4c200, - BNXT_ULP_CLASS_HID_4b850 = 0x4b850, - BNXT_ULP_CLASS_HID_4a19c = 0x4a19c, - BNXT_ULP_CLASS_HID_485bc = 0x485bc, - BNXT_ULP_CLASS_HID_48bf8 = 0x48bf8, - BNXT_ULP_CLASS_HID_1b098 = 0x1b098, - BNXT_ULP_CLASS_HID_1b6a4 = 0x1b6a4, - BNXT_ULP_CLASS_HID_19ac4 = 0x19ac4, - BNXT_ULP_CLASS_HID_18000 = 0x18000, - BNXT_ULP_CLASS_HID_1d50c = 0x1d50c, - BNXT_ULP_CLASS_HID_1db48 = 0x1db48, - BNXT_ULP_CLASS_HID_1bf68 = 0x1bf68, - BNXT_ULP_CLASS_HID_1a4b4 = 0x1a4b4, - BNXT_ULP_CLASS_HID_58dac = 0x58dac, - BNXT_ULP_CLASS_HID_5b3e8 = 0x5b3e8, - BNXT_ULP_CLASS_HID_59708 = 0x59708, - BNXT_ULP_CLASS_HID_59d54 = 0x59d54, - BNXT_ULP_CLASS_HID_5ae50 = 0x5ae50, - BNXT_ULP_CLASS_HID_5d79c = 0x5d79c, - BNXT_ULP_CLASS_HID_5bbbc = 0x5bbbc, - BNXT_ULP_CLASS_HID_5a1f8 = 0x5a1f8, - BNXT_ULP_CLASS_HID_5822 = 0x5822, - BNXT_ULP_CLASS_HID_5e66 = 0x5e66, - BNXT_ULP_CLASS_HID_1d56 = 0x1d56, - BNXT_ULP_CLASS_HID_029a = 0x029a, - BNXT_ULP_CLASS_HID_3282 = 0x3282, - BNXT_ULP_CLASS_HID_38c6 = 0x38c6, - BNXT_ULP_CLASS_HID_52ea = 0x52ea, - BNXT_ULP_CLASS_HID_582e = 0x582e, - BNXT_ULP_CLASS_HID_51ba = 0x51ba, - BNXT_ULP_CLASS_HID_57fe = 0x57fe, - BNXT_ULP_CLASS_HID_12ee = 0x12ee, - BNXT_ULP_CLASS_HID_1832 = 0x1832, - BNXT_ULP_CLASS_HID_081a = 0x081a, - BNXT_ULP_CLASS_HID_0e5e = 0x0e5e, - BNXT_ULP_CLASS_HID_2802 = 0x2802, - BNXT_ULP_CLASS_HID_2e46 = 0x2e46, - BNXT_ULP_CLASS_HID_4556e = 0x4556e, - BNXT_ULP_CLASS_HID_45ab2 = 0x45ab2, - BNXT_ULP_CLASS_HID_419a2 = 0x419a2, - BNXT_ULP_CLASS_HID_41fe6 = 0x41fe6, - BNXT_ULP_CLASS_HID_40fce = 0x40fce, - BNXT_ULP_CLASS_HID_43512 = 0x43512, - BNXT_ULP_CLASS_HID_42f36 = 0x42f36, - BNXT_ULP_CLASS_HID_4557a = 0x4557a, - BNXT_ULP_CLASS_HID_42a86 = 0x42a86, - BNXT_ULP_CLASS_HID_450ca = 0x450ca, - BNXT_ULP_CLASS_HID_44aee = 0x44aee, - BNXT_ULP_CLASS_HID_4157e = 0x4157e, - BNXT_ULP_CLASS_HID_40566 = 0x40566, - BNXT_ULP_CLASS_HID_40aaa = 0x40aaa, - BNXT_ULP_CLASS_HID_4254e = 0x4254e, - BNXT_ULP_CLASS_HID_42a92 = 0x42a92, - BNXT_ULP_CLASS_HID_449b6 = 0x449b6, - BNXT_ULP_CLASS_HID_410c6 = 0x410c6, - BNXT_ULP_CLASS_HID_42016 = 0x42016, - BNXT_ULP_CLASS_HID_4266a = 0x4266a, - BNXT_ULP_CLASS_HID_45fde = 0x45fde, - BNXT_ULP_CLASS_HID_44512 = 0x44512, - BNXT_ULP_CLASS_HID_439be = 0x439be, - BNXT_ULP_CLASS_HID_43ff2 = 0x43ff2, - BNXT_ULP_CLASS_HID_63682 = 0x63682, - BNXT_ULP_CLASS_HID_63cc6 = 0x63cc6, - BNXT_ULP_CLASS_HID_61162 = 0x61162, - BNXT_ULP_CLASS_HID_616a6 = 0x616a6, - BNXT_ULP_CLASS_HID_60c2a = 0x60c2a, - BNXT_ULP_CLASS_HID_6326e = 0x6326e, - BNXT_ULP_CLASS_HID_645be = 0x645be, - BNXT_ULP_CLASS_HID_64bf2 = 0x64bf2, - BNXT_ULP_CLASS_HID_50082 = 0x50082, - BNXT_ULP_CLASS_HID_506c6 = 0x506c6, - BNXT_ULP_CLASS_HID_55616 = 0x55616, - BNXT_ULP_CLASS_HID_55c6a = 0x55c6a, - BNXT_ULP_CLASS_HID_5162a = 0x5162a, - BNXT_ULP_CLASS_HID_51c6e = 0x51c6e, - BNXT_ULP_CLASS_HID_52fbe = 0x52fbe, - BNXT_ULP_CLASS_HID_555f2 = 0x555f2, - BNXT_ULP_CLASS_HID_72c82 = 0x72c82, - BNXT_ULP_CLASS_HID_752c6 = 0x752c6, - BNXT_ULP_CLASS_HID_70762 = 0x70762, - BNXT_ULP_CLASS_HID_70ca6 = 0x70ca6, - BNXT_ULP_CLASS_HID_7222a = 0x7222a, - BNXT_ULP_CLASS_HID_7286e = 0x7286e, - BNXT_ULP_CLASS_HID_71c8a = 0x71c8a, - BNXT_ULP_CLASS_HID_702ce = 0x702ce, - BNXT_ULP_CLASS_HID_5842 = 0x5842, - BNXT_ULP_CLASS_HID_5e06 = 0x5e06, - BNXT_ULP_CLASS_HID_1d36 = 0x1d36, - BNXT_ULP_CLASS_HID_02fa = 0x02fa, - BNXT_ULP_CLASS_HID_32e2 = 0x32e2, - BNXT_ULP_CLASS_HID_38a6 = 0x38a6, - BNXT_ULP_CLASS_HID_528a = 0x528a, - BNXT_ULP_CLASS_HID_584e = 0x584e, - BNXT_ULP_CLASS_HID_51da = 0x51da, - BNXT_ULP_CLASS_HID_579e = 0x579e, - BNXT_ULP_CLASS_HID_128e = 0x128e, - BNXT_ULP_CLASS_HID_1852 = 0x1852, - BNXT_ULP_CLASS_HID_087a = 0x087a, - BNXT_ULP_CLASS_HID_0e3e = 0x0e3e, - BNXT_ULP_CLASS_HID_2862 = 0x2862, - BNXT_ULP_CLASS_HID_2e26 = 0x2e26, - BNXT_ULP_CLASS_HID_4550e = 0x4550e, - BNXT_ULP_CLASS_HID_45ad2 = 0x45ad2, - BNXT_ULP_CLASS_HID_419c2 = 0x419c2, - BNXT_ULP_CLASS_HID_41f86 = 0x41f86, - BNXT_ULP_CLASS_HID_40fae = 0x40fae, - BNXT_ULP_CLASS_HID_43572 = 0x43572, - BNXT_ULP_CLASS_HID_42f56 = 0x42f56, - BNXT_ULP_CLASS_HID_4551a = 0x4551a, - BNXT_ULP_CLASS_HID_42ae6 = 0x42ae6, - BNXT_ULP_CLASS_HID_450aa = 0x450aa, - BNXT_ULP_CLASS_HID_44a8e = 0x44a8e, - BNXT_ULP_CLASS_HID_4151e = 0x4151e, - BNXT_ULP_CLASS_HID_40506 = 0x40506, - BNXT_ULP_CLASS_HID_40aca = 0x40aca, - BNXT_ULP_CLASS_HID_4252e = 0x4252e, - BNXT_ULP_CLASS_HID_42af2 = 0x42af2, - BNXT_ULP_CLASS_HID_449d6 = 0x449d6, - BNXT_ULP_CLASS_HID_410a6 = 0x410a6, - BNXT_ULP_CLASS_HID_42076 = 0x42076, - BNXT_ULP_CLASS_HID_4260a = 0x4260a, - BNXT_ULP_CLASS_HID_45fbe = 0x45fbe, - BNXT_ULP_CLASS_HID_44572 = 0x44572, - BNXT_ULP_CLASS_HID_439de = 0x439de, - BNXT_ULP_CLASS_HID_43f92 = 0x43f92, - BNXT_ULP_CLASS_HID_636e2 = 0x636e2, - BNXT_ULP_CLASS_HID_63ca6 = 0x63ca6, - BNXT_ULP_CLASS_HID_61102 = 0x61102, - BNXT_ULP_CLASS_HID_616c6 = 0x616c6, - BNXT_ULP_CLASS_HID_60c4a = 0x60c4a, - BNXT_ULP_CLASS_HID_6320e = 0x6320e, - BNXT_ULP_CLASS_HID_645de = 0x645de, - BNXT_ULP_CLASS_HID_64b92 = 0x64b92, - BNXT_ULP_CLASS_HID_500e2 = 0x500e2, - BNXT_ULP_CLASS_HID_506a6 = 0x506a6, - BNXT_ULP_CLASS_HID_55676 = 0x55676, - BNXT_ULP_CLASS_HID_55c0a = 0x55c0a, - BNXT_ULP_CLASS_HID_5164a = 0x5164a, - BNXT_ULP_CLASS_HID_51c0e = 0x51c0e, - BNXT_ULP_CLASS_HID_52fde = 0x52fde, - BNXT_ULP_CLASS_HID_55592 = 0x55592, - BNXT_ULP_CLASS_HID_72ce2 = 0x72ce2, - BNXT_ULP_CLASS_HID_752a6 = 0x752a6, - BNXT_ULP_CLASS_HID_70702 = 0x70702, - BNXT_ULP_CLASS_HID_70cc6 = 0x70cc6, - BNXT_ULP_CLASS_HID_7224a = 0x7224a, - BNXT_ULP_CLASS_HID_7280e = 0x7280e, - BNXT_ULP_CLASS_HID_71cea = 0x71cea, - BNXT_ULP_CLASS_HID_702ae = 0x702ae, - BNXT_ULP_CLASS_HID_23dc0 = 0x23dc0, - BNXT_ULP_CLASS_HID_223fc = 0x223fc, - BNXT_ULP_CLASS_HID_2079c = 0x2079c, - BNXT_ULP_CLASS_HID_20d58 = 0x20d58, - BNXT_ULP_CLASS_HID_25e54 = 0x25e54, - BNXT_ULP_CLASS_HID_24410 = 0x24410, - BNXT_ULP_CLASS_HID_22830 = 0x22830, - BNXT_ULP_CLASS_HID_251ec = 0x251ec, - BNXT_ULP_CLASS_HID_20910 = 0x20910, - BNXT_ULP_CLASS_HID_20ecc = 0x20ecc, - BNXT_ULP_CLASS_HID_212ec = 0x212ec, - BNXT_ULP_CLASS_HID_218a8 = 0x218a8, - BNXT_ULP_CLASS_HID_22da4 = 0x22da4, - BNXT_ULP_CLASS_HID_25360 = 0x25360, - BNXT_ULP_CLASS_HID_23700 = 0x23700, - BNXT_ULP_CLASS_HID_23d3c = 0x23d3c, - BNXT_ULP_CLASS_HID_636f4 = 0x636f4, - BNXT_ULP_CLASS_HID_63cb0 = 0x63cb0, - BNXT_ULP_CLASS_HID_60050 = 0x60050, - BNXT_ULP_CLASS_HID_6060c = 0x6060c, - BNXT_ULP_CLASS_HID_65b08 = 0x65b08, - BNXT_ULP_CLASS_HID_640c4 = 0x640c4, - BNXT_ULP_CLASS_HID_624e4 = 0x624e4, - BNXT_ULP_CLASS_HID_62aa0 = 0x62aa0, - BNXT_ULP_CLASS_HID_605c4 = 0x605c4, - BNXT_ULP_CLASS_HID_60b80 = 0x60b80, - BNXT_ULP_CLASS_HID_64aec = 0x64aec, - BNXT_ULP_CLASS_HID_6155c = 0x6155c, - BNXT_ULP_CLASS_HID_62658 = 0x62658, - BNXT_ULP_CLASS_HID_62c14 = 0x62c14, - BNXT_ULP_CLASS_HID_63034 = 0x63034, - BNXT_ULP_CLASS_HID_639f0 = 0x639f0, - BNXT_ULP_CLASS_HID_353c0 = 0x353c0, - BNXT_ULP_CLASS_HID_359fc = 0x359fc, - BNXT_ULP_CLASS_HID_33d9c = 0x33d9c, - BNXT_ULP_CLASS_HID_32358 = 0x32358, - BNXT_ULP_CLASS_HID_31908 = 0x31908, - BNXT_ULP_CLASS_HID_31ec4 = 0x31ec4, - BNXT_ULP_CLASS_HID_35e30 = 0x35e30, - BNXT_ULP_CLASS_HID_347ec = 0x347ec, - BNXT_ULP_CLASS_HID_33f10 = 0x33f10, - BNXT_ULP_CLASS_HID_324cc = 0x324cc, - BNXT_ULP_CLASS_HID_308ec = 0x308ec, - BNXT_ULP_CLASS_HID_30ea8 = 0x30ea8, - BNXT_ULP_CLASS_HID_343a4 = 0x343a4, - BNXT_ULP_CLASS_HID_34960 = 0x34960, - BNXT_ULP_CLASS_HID_32d00 = 0x32d00, - BNXT_ULP_CLASS_HID_3533c = 0x3533c, - BNXT_ULP_CLASS_HID_72cf4 = 0x72cf4, - BNXT_ULP_CLASS_HID_752b0 = 0x752b0, - BNXT_ULP_CLASS_HID_73650 = 0x73650, - BNXT_ULP_CLASS_HID_73c0c = 0x73c0c, - BNXT_ULP_CLASS_HID_7123c = 0x7123c, - BNXT_ULP_CLASS_HID_71bf8 = 0x71bf8, - BNXT_ULP_CLASS_HID_75ae4 = 0x75ae4, - BNXT_ULP_CLASS_HID_740a0 = 0x740a0, - BNXT_ULP_CLASS_HID_73bc4 = 0x73bc4, - BNXT_ULP_CLASS_HID_72180 = 0x72180, - BNXT_ULP_CLASS_HID_705a0 = 0x705a0, - BNXT_ULP_CLASS_HID_70b5c = 0x70b5c, - BNXT_ULP_CLASS_HID_75c58 = 0x75c58, - BNXT_ULP_CLASS_HID_74214 = 0x74214, - BNXT_ULP_CLASS_HID_72634 = 0x72634, - BNXT_ULP_CLASS_HID_72ff0 = 0x72ff0, - BNXT_ULP_CLASS_HID_2a6c0 = 0x2a6c0, - BNXT_ULP_CLASS_HID_2acfc = 0x2acfc, - BNXT_ULP_CLASS_HID_2b09c = 0x2b09c, - BNXT_ULP_CLASS_HID_2b658 = 0x2b658, - BNXT_ULP_CLASS_HID_2cb54 = 0x2cb54, - BNXT_ULP_CLASS_HID_295c4 = 0x295c4, - BNXT_ULP_CLASS_HID_2d530 = 0x2d530, - BNXT_ULP_CLASS_HID_2daec = 0x2daec, - BNXT_ULP_CLASS_HID_2b210 = 0x2b210, - BNXT_ULP_CLASS_HID_2bbcc = 0x2bbcc, - BNXT_ULP_CLASS_HID_29fec = 0x29fec, - BNXT_ULP_CLASS_HID_285a8 = 0x285a8, - BNXT_ULP_CLASS_HID_2d6a4 = 0x2d6a4, - BNXT_ULP_CLASS_HID_2dc60 = 0x2dc60, - BNXT_ULP_CLASS_HID_2a000 = 0x2a000, - BNXT_ULP_CLASS_HID_2a63c = 0x2a63c, - BNXT_ULP_CLASS_HID_6a3f4 = 0x6a3f4, - BNXT_ULP_CLASS_HID_6a9b0 = 0x6a9b0, - BNXT_ULP_CLASS_HID_68d50 = 0x68d50, - BNXT_ULP_CLASS_HID_6b30c = 0x6b30c, - BNXT_ULP_CLASS_HID_6c408 = 0x6c408, - BNXT_ULP_CLASS_HID_6cdc4 = 0x6cdc4, - BNXT_ULP_CLASS_HID_6d1e4 = 0x6d1e4, - BNXT_ULP_CLASS_HID_6d7a0 = 0x6d7a0, - BNXT_ULP_CLASS_HID_68ec4 = 0x68ec4, - BNXT_ULP_CLASS_HID_6b480 = 0x6b480, - BNXT_ULP_CLASS_HID_698a0 = 0x698a0, - BNXT_ULP_CLASS_HID_69e5c = 0x69e5c, - BNXT_ULP_CLASS_HID_6d358 = 0x6d358, - BNXT_ULP_CLASS_HID_6d914 = 0x6d914, - BNXT_ULP_CLASS_HID_6bd34 = 0x6bd34, - BNXT_ULP_CLASS_HID_6a2f0 = 0x6a2f0, - BNXT_ULP_CLASS_HID_3dcc0 = 0x3dcc0, - BNXT_ULP_CLASS_HID_3c2fc = 0x3c2fc, - BNXT_ULP_CLASS_HID_3a69c = 0x3a69c, - BNXT_ULP_CLASS_HID_3ac58 = 0x3ac58, - BNXT_ULP_CLASS_HID_38208 = 0x38208, - BNXT_ULP_CLASS_HID_38bc4 = 0x38bc4, - BNXT_ULP_CLASS_HID_3cb30 = 0x3cb30, - BNXT_ULP_CLASS_HID_395a0 = 0x395a0, - BNXT_ULP_CLASS_HID_3a810 = 0x3a810, - BNXT_ULP_CLASS_HID_3d1cc = 0x3d1cc, - BNXT_ULP_CLASS_HID_3b5ec = 0x3b5ec, - BNXT_ULP_CLASS_HID_3bba8 = 0x3bba8, - BNXT_ULP_CLASS_HID_39158 = 0x39158, - BNXT_ULP_CLASS_HID_39714 = 0x39714, - BNXT_ULP_CLASS_HID_3d600 = 0x3d600, - BNXT_ULP_CLASS_HID_3dc3c = 0x3dc3c, - BNXT_ULP_CLASS_HID_7d9f4 = 0x7d9f4, - BNXT_ULP_CLASS_HID_7dfb0 = 0x7dfb0, - BNXT_ULP_CLASS_HID_7a350 = 0x7a350, - BNXT_ULP_CLASS_HID_7a90c = 0x7a90c, - BNXT_ULP_CLASS_HID_79f3c = 0x79f3c, - BNXT_ULP_CLASS_HID_784f8 = 0x784f8, - BNXT_ULP_CLASS_HID_7c7e4 = 0x7c7e4, - BNXT_ULP_CLASS_HID_7cda0 = 0x7cda0, - BNXT_ULP_CLASS_HID_7a4c4 = 0x7a4c4, - BNXT_ULP_CLASS_HID_7aa80 = 0x7aa80, - BNXT_ULP_CLASS_HID_78ea0 = 0x78ea0, - BNXT_ULP_CLASS_HID_7b45c = 0x7b45c, - BNXT_ULP_CLASS_HID_7c958 = 0x7c958, - BNXT_ULP_CLASS_HID_793c8 = 0x793c8, - BNXT_ULP_CLASS_HID_7d334 = 0x7d334, - BNXT_ULP_CLASS_HID_7d8f0 = 0x7d8f0, - BNXT_ULP_CLASS_HID_9ab8 = 0x9ab8, - BNXT_ULP_CLASS_HID_8084 = 0x8084, - BNXT_ULP_CLASS_HID_c390 = 0xc390, - BNXT_ULP_CLASS_HID_c9dc = 0xc9dc, - BNXT_ULP_CLASS_HID_bf2c = 0xbf2c, - BNXT_ULP_CLASS_HID_a568 = 0xa568, - BNXT_ULP_CLASS_HID_8948 = 0x8948, - BNXT_ULP_CLASS_HID_8e94 = 0x8e94, - BNXT_ULP_CLASS_HID_4978c = 0x4978c, - BNXT_ULP_CLASS_HID_49dc8 = 0x49dc8, - BNXT_ULP_CLASS_HID_4dce4 = 0x4dce4, - BNXT_ULP_CLASS_HID_4c220 = 0x4c220, - BNXT_ULP_CLASS_HID_4b870 = 0x4b870, - BNXT_ULP_CLASS_HID_4a1bc = 0x4a1bc, - BNXT_ULP_CLASS_HID_4859c = 0x4859c, - BNXT_ULP_CLASS_HID_48bd8 = 0x48bd8, - BNXT_ULP_CLASS_HID_1b0b8 = 0x1b0b8, - BNXT_ULP_CLASS_HID_1b684 = 0x1b684, - BNXT_ULP_CLASS_HID_19ae4 = 0x19ae4, - BNXT_ULP_CLASS_HID_18020 = 0x18020, - BNXT_ULP_CLASS_HID_1d52c = 0x1d52c, - BNXT_ULP_CLASS_HID_1db68 = 0x1db68, - BNXT_ULP_CLASS_HID_1bf48 = 0x1bf48, - BNXT_ULP_CLASS_HID_1a494 = 0x1a494, - BNXT_ULP_CLASS_HID_58d8c = 0x58d8c, - BNXT_ULP_CLASS_HID_5b3c8 = 0x5b3c8, - BNXT_ULP_CLASS_HID_59728 = 0x59728, - BNXT_ULP_CLASS_HID_59d74 = 0x59d74, - BNXT_ULP_CLASS_HID_5ae70 = 0x5ae70, - BNXT_ULP_CLASS_HID_5d7bc = 0x5d7bc, - BNXT_ULP_CLASS_HID_5bb9c = 0x5bb9c, - BNXT_ULP_CLASS_HID_5a1d8 = 0x5a1d8, - BNXT_ULP_CLASS_HID_c138 = 0xc138, - BNXT_ULP_CLASS_HID_c704 = 0xc704, - BNXT_ULP_CLASS_HID_c610 = 0xc610, - BNXT_ULP_CLASS_HID_d0a0 = 0xd0a0, - BNXT_ULP_CLASS_HID_e5ac = 0xe5ac, - BNXT_ULP_CLASS_HID_ebe8 = 0xebe8, - BNXT_ULP_CLASS_HID_cfc8 = 0xcfc8, - BNXT_ULP_CLASS_HID_f514 = 0xf514, - BNXT_ULP_CLASS_HID_4da0c = 0x4da0c, - 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BNXT_ULP_CLASS_HID_4ce38 = 0x4ce38, - BNXT_ULP_CLASS_HID_1f758 = 0x1f758, - BNXT_ULP_CLASS_HID_1fd64 = 0x1fd64, - BNXT_ULP_CLASS_HID_1c104 = 0x1c104, - BNXT_ULP_CLASS_HID_1c6c0 = 0x1c6c0, - BNXT_ULP_CLASS_HID_1dbcc = 0x1dbcc, - BNXT_ULP_CLASS_HID_1c188 = 0x1c188, - BNXT_ULP_CLASS_HID_1e5a8 = 0x1e5a8, - BNXT_ULP_CLASS_HID_1eb74 = 0x1eb74, - BNXT_ULP_CLASS_HID_5f06c = 0x5f06c, - BNXT_ULP_CLASS_HID_5f628 = 0x5f628, - BNXT_ULP_CLASS_HID_5ddc8 = 0x5ddc8, - BNXT_ULP_CLASS_HID_5c394 = 0x5c394, - BNXT_ULP_CLASS_HID_5d490 = 0x5d490, - BNXT_ULP_CLASS_HID_5da5c = 0x5da5c, - BNXT_ULP_CLASS_HID_5fe7c = 0x5fe7c, - BNXT_ULP_CLASS_HID_5e438 = 0x5e438, - BNXT_ULP_CLASS_HID_bc18 = 0xbc18, - BNXT_ULP_CLASS_HID_a224 = 0xa224, - BNXT_ULP_CLASS_HID_e530 = 0xe530, - BNXT_ULP_CLASS_HID_eafc = 0xeafc, - BNXT_ULP_CLASS_HID_a08c = 0xa08c, - BNXT_ULP_CLASS_HID_a648 = 0xa648, - BNXT_ULP_CLASS_HID_aa68 = 0xaa68, - BNXT_ULP_CLASS_HID_b034 = 0xb034, - BNXT_ULP_CLASS_HID_4b92c = 0x4b92c, - BNXT_ULP_CLASS_HID_4bee8 = 0x4bee8, - BNXT_ULP_CLASS_HID_4e1c4 = 0x4e1c4, - BNXT_ULP_CLASS_HID_4e780 = 0x4e780, - BNXT_ULP_CLASS_HID_4bd50 = 0x4bd50, - BNXT_ULP_CLASS_HID_4a31c = 0x4a31c, - BNXT_ULP_CLASS_HID_4a73c = 0x4a73c, - BNXT_ULP_CLASS_HID_4acf8 = 0x4acf8, - BNXT_ULP_CLASS_HID_1b218 = 0x1b218, - BNXT_ULP_CLASS_HID_1b824 = 0x1b824, - BNXT_ULP_CLASS_HID_1bfc4 = 0x1bfc4, - BNXT_ULP_CLASS_HID_1a580 = 0x1a580, - BNXT_ULP_CLASS_HID_1f68c = 0x1f68c, - BNXT_ULP_CLASS_HID_1fc48 = 0x1fc48, - BNXT_ULP_CLASS_HID_1a068 = 0x1a068, - BNXT_ULP_CLASS_HID_1a634 = 0x1a634, - BNXT_ULP_CLASS_HID_5af2c = 0x5af2c, - BNXT_ULP_CLASS_HID_5b4e8 = 0x5b4e8, - BNXT_ULP_CLASS_HID_5b888 = 0x5b888, - BNXT_ULP_CLASS_HID_5be54 = 0x5be54, - BNXT_ULP_CLASS_HID_5f350 = 0x5f350, - BNXT_ULP_CLASS_HID_5f91c = 0x5f91c, - BNXT_ULP_CLASS_HID_5bd3c = 0x5bd3c, - BNXT_ULP_CLASS_HID_5a2f8 = 0x5a2f8, - BNXT_ULP_CLASS_HID_e298 = 0xe298, - BNXT_ULP_CLASS_HID_e8a4 = 0xe8a4, - BNXT_ULP_CLASS_HID_ebb0 = 0xebb0, - BNXT_ULP_CLASS_HID_f200 = 0xf200, - BNXT_ULP_CLASS_HID_e70c = 0xe70c, - BNXT_ULP_CLASS_HID_ecc8 = 0xecc8, - BNXT_ULP_CLASS_HID_f0e8 = 0xf0e8, - BNXT_ULP_CLASS_HID_f6b4 = 0xf6b4, - BNXT_ULP_CLASS_HID_4ffac = 0x4ffac, - BNXT_ULP_CLASS_HID_4e568 = 0x4e568, - BNXT_ULP_CLASS_HID_4e444 = 0x4e444, - BNXT_ULP_CLASS_HID_4ea00 = 0x4ea00, - BNXT_ULP_CLASS_HID_4e3d0 = 0x4e3d0, - BNXT_ULP_CLASS_HID_4e99c = 0x4e99c, - BNXT_ULP_CLASS_HID_4edbc = 0x4edbc, - BNXT_ULP_CLASS_HID_4f378 = 0x4f378, - BNXT_ULP_CLASS_HID_1f898 = 0x1f898, - BNXT_ULP_CLASS_HID_1fea4 = 0x1fea4, - BNXT_ULP_CLASS_HID_1e244 = 0x1e244, - BNXT_ULP_CLASS_HID_1e800 = 0x1e800, - BNXT_ULP_CLASS_HID_1fd0c = 0x1fd0c, - BNXT_ULP_CLASS_HID_1e2c8 = 0x1e2c8, - BNXT_ULP_CLASS_HID_1e6e8 = 0x1e6e8, - BNXT_ULP_CLASS_HID_1ecb4 = 0x1ecb4, - BNXT_ULP_CLASS_HID_5f5ac = 0x5f5ac, - BNXT_ULP_CLASS_HID_5fb68 = 0x5fb68, - BNXT_ULP_CLASS_HID_5ff08 = 0x5ff08, - BNXT_ULP_CLASS_HID_5e4d4 = 0x5e4d4, - BNXT_ULP_CLASS_HID_5f9d0 = 0x5f9d0, - BNXT_ULP_CLASS_HID_5ff9c = 0x5ff9c, - BNXT_ULP_CLASS_HID_5e3bc = 0x5e3bc, - BNXT_ULP_CLASS_HID_5e978 = 0x5e978, - BNXT_ULP_CLASS_HID_34f6 = 0x34f6, - BNXT_ULP_CLASS_HID_3a3a = 0x3a3a, - BNXT_ULP_CLASS_HID_541e = 0x541e, - BNXT_ULP_CLASS_HID_5a22 = 0x5a22, - BNXT_ULP_CLASS_HID_34fe = 0x34fe, - BNXT_ULP_CLASS_HID_3a32 = 0x3a32, - BNXT_ULP_CLASS_HID_4a42 = 0x4a42, + BNXT_ULP_CLASS_HID_7276 = 0x7276, + BNXT_ULP_CLASS_HID_42d2 = 0x42d2, + BNXT_ULP_CLASS_HID_5dee = 0x5dee, + BNXT_ULP_CLASS_HID_59de = 0x59de, + BNXT_ULP_CLASS_HID_513a = 0x513a, + BNXT_ULP_CLASS_HID_1c12 = 0x1c12, + BNXT_ULP_CLASS_HID_177e = 0x177e, + BNXT_ULP_CLASS_HID_0e92 = 0x0e92, + BNXT_ULP_CLASS_HID_09fe = 0x09fe, + BNXT_ULP_CLASS_HID_5c1a = 0x5c1a, + BNXT_ULP_CLASS_HID_5746 = 0x5746, + BNXT_ULP_CLASS_HID_79da = 0x79da, + BNXT_ULP_CLASS_HID_7106 = 0x7106, + BNXT_ULP_CLASS_HID_3c1e = 0x3c1e, + BNXT_ULP_CLASS_HID_377a = 0x377a, + BNXT_ULP_CLASS_HID_2e9e = 0x2e9e, + BNXT_ULP_CLASS_HID_29fa = 0x29fa, BNXT_ULP_CLASS_HID_14d2 = 0x14d2, - BNXT_ULP_CLASS_HID_34c8 = 0x34c8, - BNXT_ULP_CLASS_HID_3a04 = 0x3a04, - BNXT_ULP_CLASS_HID_1e64 = 0x1e64, - BNXT_ULP_CLASS_HID_07a0 = 0x07a0, - BNXT_ULP_CLASS_HID_595c = 0x595c, - BNXT_ULP_CLASS_HID_5e98 = 0x5e98, - BNXT_ULP_CLASS_HID_22f8 = 0x22f8, - BNXT_ULP_CLASS_HID_2834 = 0x2834, - BNXT_ULP_CLASS_HID_0398 = 0x0398, - BNXT_ULP_CLASS_HID_09d4 = 0x09d4, - BNXT_ULP_CLASS_HID_48c0 = 0x48c0, - BNXT_ULP_CLASS_HID_1370 = 0x1370, - BNXT_ULP_CLASS_HID_246c = 0x246c, - BNXT_ULP_CLASS_HID_2da8 = 0x2da8, - BNXT_ULP_CLASS_HID_3188 = 0x3188, - BNXT_ULP_CLASS_HID_37c4 = 0x37c4, - BNXT_ULP_CLASS_HID_34f0 = 0x34f0, - BNXT_ULP_CLASS_HID_3a3c = 0x3a3c, - BNXT_ULP_CLASS_HID_1e5c = 0x1e5c, - BNXT_ULP_CLASS_HID_0798 = 0x0798, - BNXT_ULP_CLASS_HID_5964 = 0x5964, - BNXT_ULP_CLASS_HID_5ea0 = 0x5ea0, - BNXT_ULP_CLASS_HID_22c0 = 0x22c0, - BNXT_ULP_CLASS_HID_280c = 0x280c, - BNXT_ULP_CLASS_HID_43104 = 0x43104, - BNXT_ULP_CLASS_HID_43740 = 0x43740, - BNXT_ULP_CLASS_HID_41b60 = 0x41b60, - BNXT_ULP_CLASS_HID_400ac = 0x400ac, - BNXT_ULP_CLASS_HID_455a8 = 0x455a8, - BNXT_ULP_CLASS_HID_45bf4 = 0x45bf4, - BNXT_ULP_CLASS_HID_43f14 = 0x43f14, - BNXT_ULP_CLASS_HID_42550 = 0x42550, - BNXT_ULP_CLASS_HID_34d6 = 0x34d6, - BNXT_ULP_CLASS_HID_3a1a = 0x3a1a, - BNXT_ULP_CLASS_HID_543e = 0x543e, - BNXT_ULP_CLASS_HID_5a02 = 0x5a02, - BNXT_ULP_CLASS_HID_34de = 0x34de, - BNXT_ULP_CLASS_HID_3a12 = 0x3a12, - BNXT_ULP_CLASS_HID_4a62 = 0x4a62, + BNXT_ULP_CLASS_HID_7742 = 0x7742, + BNXT_ULP_CLASS_HID_3706 = 0x3706, + BNXT_ULP_CLASS_HID_0fe2 = 0x0fe2, + BNXT_ULP_CLASS_HID_1f7e = 0x1f7e, + BNXT_ULP_CLASS_HID_145a = 0x145a, + BNXT_ULP_CLASS_HID_417e = 0x417e, + BNXT_ULP_CLASS_HID_5e5a = 0x5e5a, + BNXT_ULP_CLASS_HID_29f6 = 0x29f6, + BNXT_ULP_CLASS_HID_26d2 = 0x26d2, + BNXT_ULP_CLASS_HID_2e42 = 0x2e42, + BNXT_ULP_CLASS_HID_271e = 0x271e, + BNXT_ULP_CLASS_HID_36ba = 0x36ba, + BNXT_ULP_CLASS_HID_0f96 = 0x0f96, + BNXT_ULP_CLASS_HID_1006 = 0x1006, + BNXT_ULP_CLASS_HID_7196 = 0x7196, + BNXT_ULP_CLASS_HID_4132 = 0x4132, + BNXT_ULP_CLASS_HID_5e0e = 0x5e0e, + BNXT_ULP_CLASS_HID_59fe = 0x59fe, + BNXT_ULP_CLASS_HID_511a = 0x511a, + BNXT_ULP_CLASS_HID_1c32 = 0x1c32, + BNXT_ULP_CLASS_HID_175e = 0x175e, + BNXT_ULP_CLASS_HID_0eb2 = 0x0eb2, + BNXT_ULP_CLASS_HID_09de = 0x09de, + BNXT_ULP_CLASS_HID_5c3a = 0x5c3a, + BNXT_ULP_CLASS_HID_5766 = 0x5766, + BNXT_ULP_CLASS_HID_79fa = 0x79fa, + BNXT_ULP_CLASS_HID_7126 = 0x7126, + BNXT_ULP_CLASS_HID_3c3e = 0x3c3e, + BNXT_ULP_CLASS_HID_375a = 0x375a, + BNXT_ULP_CLASS_HID_2ebe = 0x2ebe, + BNXT_ULP_CLASS_HID_29da = 0x29da, BNXT_ULP_CLASS_HID_14f2 = 0x14f2, - BNXT_ULP_CLASS_HID_34b6 = 0x34b6, - BNXT_ULP_CLASS_HID_3a7a = 0x3a7a, - BNXT_ULP_CLASS_HID_545e = 0x545e, - BNXT_ULP_CLASS_HID_5a62 = 0x5a62, - BNXT_ULP_CLASS_HID_34be = 0x34be, - BNXT_ULP_CLASS_HID_3a72 = 0x3a72, - BNXT_ULP_CLASS_HID_4a02 = 0x4a02, - BNXT_ULP_CLASS_HID_1492 = 0x1492, - BNXT_ULP_CLASS_HID_34a8 = 0x34a8, - BNXT_ULP_CLASS_HID_3a64 = 0x3a64, - BNXT_ULP_CLASS_HID_1e04 = 0x1e04, - BNXT_ULP_CLASS_HID_07c0 = 0x07c0, - BNXT_ULP_CLASS_HID_593c = 0x593c, - BNXT_ULP_CLASS_HID_5ef8 = 0x5ef8, - BNXT_ULP_CLASS_HID_2298 = 0x2298, - BNXT_ULP_CLASS_HID_2854 = 0x2854, - BNXT_ULP_CLASS_HID_03f8 = 0x03f8, - BNXT_ULP_CLASS_HID_09b4 = 0x09b4, - BNXT_ULP_CLASS_HID_48a0 = 0x48a0, - BNXT_ULP_CLASS_HID_1310 = 0x1310, - BNXT_ULP_CLASS_HID_240c = 0x240c, - BNXT_ULP_CLASS_HID_2dc8 = 0x2dc8, - BNXT_ULP_CLASS_HID_31e8 = 0x31e8, - BNXT_ULP_CLASS_HID_37a4 = 0x37a4, - BNXT_ULP_CLASS_HID_34d0 = 0x34d0, - BNXT_ULP_CLASS_HID_3a1c = 0x3a1c, - BNXT_ULP_CLASS_HID_1e7c = 0x1e7c, - BNXT_ULP_CLASS_HID_07b8 = 0x07b8, - BNXT_ULP_CLASS_HID_5944 = 0x5944, - BNXT_ULP_CLASS_HID_5e80 = 0x5e80, - BNXT_ULP_CLASS_HID_22e0 = 0x22e0, - BNXT_ULP_CLASS_HID_282c = 0x282c, - BNXT_ULP_CLASS_HID_43124 = 0x43124, - BNXT_ULP_CLASS_HID_43760 = 0x43760, - BNXT_ULP_CLASS_HID_41b40 = 0x41b40, - BNXT_ULP_CLASS_HID_4008c = 0x4008c, - BNXT_ULP_CLASS_HID_45588 = 0x45588, - BNXT_ULP_CLASS_HID_45bd4 = 0x45bd4, - BNXT_ULP_CLASS_HID_43f34 = 0x43f34, - BNXT_ULP_CLASS_HID_42570 = 0x42570, - BNXT_ULP_CLASS_HID_3488 = 0x3488, - BNXT_ULP_CLASS_HID_3a44 = 0x3a44, - BNXT_ULP_CLASS_HID_1e24 = 0x1e24, - BNXT_ULP_CLASS_HID_07e0 = 0x07e0, - BNXT_ULP_CLASS_HID_591c = 0x591c, - BNXT_ULP_CLASS_HID_5ed8 = 0x5ed8, - BNXT_ULP_CLASS_HID_22b8 = 0x22b8, - BNXT_ULP_CLASS_HID_2874 = 0x2874, - BNXT_ULP_CLASS_HID_03d8 = 0x03d8, - BNXT_ULP_CLASS_HID_0994 = 0x0994, - BNXT_ULP_CLASS_HID_4880 = 0x4880, - BNXT_ULP_CLASS_HID_1330 = 0x1330, - BNXT_ULP_CLASS_HID_242c = 0x242c, - BNXT_ULP_CLASS_HID_2de8 = 0x2de8, - BNXT_ULP_CLASS_HID_31c8 = 0x31c8, - BNXT_ULP_CLASS_HID_3784 = 0x3784, - BNXT_ULP_CLASS_HID_34b0 = 0x34b0, - BNXT_ULP_CLASS_HID_3a7c = 0x3a7c, - BNXT_ULP_CLASS_HID_1e1c = 0x1e1c, - BNXT_ULP_CLASS_HID_07d8 = 0x07d8, - BNXT_ULP_CLASS_HID_5924 = 0x5924, - BNXT_ULP_CLASS_HID_5ee0 = 0x5ee0, + BNXT_ULP_CLASS_HID_7762 = 0x7762, + BNXT_ULP_CLASS_HID_19e8 = 0x19e8, + BNXT_ULP_CLASS_HID_110c = 0x110c, + BNXT_ULP_CLASS_HID_4d48 = 0x4d48, + BNXT_ULP_CLASS_HID_446c = 0x446c, + BNXT_ULP_CLASS_HID_0eac = 0x0eac, + BNXT_ULP_CLASS_HID_09c0 = 0x09c0, + BNXT_ULP_CLASS_HID_1ad0 = 0x1ad0, + BNXT_ULP_CLASS_HID_15f4 = 0x15f4, + BNXT_ULP_CLASS_HID_39ec = 0x39ec, + BNXT_ULP_CLASS_HID_3100 = 0x3100, + BNXT_ULP_CLASS_HID_0210 = 0x0210, + BNXT_ULP_CLASS_HID_1d34 = 0x1d34, + BNXT_ULP_CLASS_HID_2ea0 = 0x2ea0, + BNXT_ULP_CLASS_HID_29c4 = 0x29c4, + BNXT_ULP_CLASS_HID_3ad4 = 0x3ad4, + BNXT_ULP_CLASS_HID_35e8 = 0x35e8, + BNXT_ULP_CLASS_HID_5d80 = 0x5d80, + BNXT_ULP_CLASS_HID_54a4 = 0x54a4, + BNXT_ULP_CLASS_HID_29b4 = 0x29b4, + BNXT_ULP_CLASS_HID_20c8 = 0x20c8, + BNXT_ULP_CLASS_HID_7244 = 0x7244, + BNXT_ULP_CLASS_HID_4d98 = 0x4d98, + BNXT_ULP_CLASS_HID_5e68 = 0x5e68, + BNXT_ULP_CLASS_HID_598c = 0x598c, + BNXT_ULP_CLASS_HID_1248 = 0x1248, + BNXT_ULP_CLASS_HID_74d8 = 0x74d8, + BNXT_ULP_CLASS_HID_49a8 = 0x49a8, + BNXT_ULP_CLASS_HID_40cc = 0x40cc, + BNXT_ULP_CLASS_HID_0b0c = 0x0b0c, + BNXT_ULP_CLASS_HID_0220 = 0x0220, + BNXT_ULP_CLASS_HID_1730 = 0x1730, + BNXT_ULP_CLASS_HID_7980 = 0x7980, + BNXT_ULP_CLASS_HID_1db0 = 0x1db0, + BNXT_ULP_CLASS_HID_1494 = 0x1494, + BNXT_ULP_CLASS_HID_70d0 = 0x70d0, + BNXT_ULP_CLASS_HID_4834 = 0x4834, + BNXT_ULP_CLASS_HID_3db4 = 0x3db4, + BNXT_ULP_CLASS_HID_3498 = 0x3498, + BNXT_ULP_CLASS_HID_0988 = 0x0988, + BNXT_ULP_CLASS_HID_00ec = 0x00ec, + BNXT_ULP_CLASS_HID_3f44 = 0x3f44, + BNXT_ULP_CLASS_HID_36a8 = 0x36a8, + BNXT_ULP_CLASS_HID_0b58 = 0x0b58, + BNXT_ULP_CLASS_HID_02bc = 0x02bc, + BNXT_ULP_CLASS_HID_5f48 = 0x5f48, + BNXT_ULP_CLASS_HID_56ac = 0x56ac, + BNXT_ULP_CLASS_HID_2b5c = 0x2b5c, BNXT_ULP_CLASS_HID_2280 = 0x2280, - BNXT_ULP_CLASS_HID_284c = 0x284c, - BNXT_ULP_CLASS_HID_43144 = 0x43144, - BNXT_ULP_CLASS_HID_43700 = 0x43700, - BNXT_ULP_CLASS_HID_41b20 = 0x41b20, - BNXT_ULP_CLASS_HID_400ec = 0x400ec, - BNXT_ULP_CLASS_HID_455e8 = 0x455e8, - BNXT_ULP_CLASS_HID_45bb4 = 0x45bb4, - BNXT_ULP_CLASS_HID_43f54 = 0x43f54, - BNXT_ULP_CLASS_HID_42510 = 0x42510 + BNXT_ULP_CLASS_HID_4000 = 0x4000, + BNXT_ULP_CLASS_HID_5b64 = 0x5b64, + BNXT_ULP_CLASS_HID_2c14 = 0x2c14, + BNXT_ULP_CLASS_HID_2778 = 0x2778, + BNXT_ULP_CLASS_HID_18f8 = 0x18f8, + BNXT_ULP_CLASS_HID_13dc = 0x13dc, + BNXT_ULP_CLASS_HID_4c18 = 0x4c18, + BNXT_ULP_CLASS_HID_477c = 0x477c, + BNXT_ULP_CLASS_HID_1a88 = 0x1a88, + BNXT_ULP_CLASS_HID_15ec = 0x15ec, + BNXT_ULP_CLASS_HID_4e28 = 0x4e28, + BNXT_ULP_CLASS_HID_490c = 0x490c, + BNXT_ULP_CLASS_HID_3a8c = 0x3a8c, + BNXT_ULP_CLASS_HID_35f0 = 0x35f0, + BNXT_ULP_CLASS_HID_06e0 = 0x06e0, + BNXT_ULP_CLASS_HID_01c4 = 0x01c4, + BNXT_ULP_CLASS_HID_1a08 = 0x1a08, + BNXT_ULP_CLASS_HID_12ec = 0x12ec, + BNXT_ULP_CLASS_HID_4ea8 = 0x4ea8, + BNXT_ULP_CLASS_HID_478c = 0x478c, + BNXT_ULP_CLASS_HID_0d4c = 0x0d4c, + BNXT_ULP_CLASS_HID_0a20 = 0x0a20, + BNXT_ULP_CLASS_HID_1930 = 0x1930, + BNXT_ULP_CLASS_HID_1614 = 0x1614, + BNXT_ULP_CLASS_HID_3a0c = 0x3a0c, + BNXT_ULP_CLASS_HID_32e0 = 0x32e0, + BNXT_ULP_CLASS_HID_01f0 = 0x01f0, + BNXT_ULP_CLASS_HID_1ed4 = 0x1ed4, + BNXT_ULP_CLASS_HID_2d40 = 0x2d40, + BNXT_ULP_CLASS_HID_2a24 = 0x2a24, + BNXT_ULP_CLASS_HID_3934 = 0x3934, + BNXT_ULP_CLASS_HID_3608 = 0x3608, + BNXT_ULP_CLASS_HID_5e60 = 0x5e60, + BNXT_ULP_CLASS_HID_5744 = 0x5744, + BNXT_ULP_CLASS_HID_2a54 = 0x2a54, + BNXT_ULP_CLASS_HID_2328 = 0x2328, + BNXT_ULP_CLASS_HID_71a4 = 0x71a4, + BNXT_ULP_CLASS_HID_4e78 = 0x4e78, + BNXT_ULP_CLASS_HID_5d88 = 0x5d88, + BNXT_ULP_CLASS_HID_5a6c = 0x5a6c, + BNXT_ULP_CLASS_HID_11a8 = 0x11a8, + BNXT_ULP_CLASS_HID_7738 = 0x7738, + BNXT_ULP_CLASS_HID_4a48 = 0x4a48, + BNXT_ULP_CLASS_HID_432c = 0x432c, + BNXT_ULP_CLASS_HID_08ec = 0x08ec, + BNXT_ULP_CLASS_HID_01c0 = 0x01c0, + BNXT_ULP_CLASS_HID_14d0 = 0x14d0, + BNXT_ULP_CLASS_HID_7a60 = 0x7a60, + BNXT_ULP_CLASS_HID_1d90 = 0x1d90, + BNXT_ULP_CLASS_HID_14b4 = 0x14b4, + BNXT_ULP_CLASS_HID_70f0 = 0x70f0, + BNXT_ULP_CLASS_HID_4814 = 0x4814, + BNXT_ULP_CLASS_HID_3d94 = 0x3d94, + BNXT_ULP_CLASS_HID_34b8 = 0x34b8, + BNXT_ULP_CLASS_HID_09a8 = 0x09a8, + BNXT_ULP_CLASS_HID_00cc = 0x00cc, + BNXT_ULP_CLASS_HID_3f64 = 0x3f64, + BNXT_ULP_CLASS_HID_3688 = 0x3688, + BNXT_ULP_CLASS_HID_0b78 = 0x0b78, + BNXT_ULP_CLASS_HID_029c = 0x029c, + BNXT_ULP_CLASS_HID_5f68 = 0x5f68, + BNXT_ULP_CLASS_HID_568c = 0x568c, + BNXT_ULP_CLASS_HID_2b7c = 0x2b7c, + BNXT_ULP_CLASS_HID_22a0 = 0x22a0, + BNXT_ULP_CLASS_HID_4020 = 0x4020, + BNXT_ULP_CLASS_HID_5b44 = 0x5b44, + BNXT_ULP_CLASS_HID_2c34 = 0x2c34, + BNXT_ULP_CLASS_HID_2758 = 0x2758, + BNXT_ULP_CLASS_HID_18d8 = 0x18d8, + BNXT_ULP_CLASS_HID_13fc = 0x13fc, + BNXT_ULP_CLASS_HID_4c38 = 0x4c38, + BNXT_ULP_CLASS_HID_475c = 0x475c, + BNXT_ULP_CLASS_HID_1aa8 = 0x1aa8, + BNXT_ULP_CLASS_HID_15cc = 0x15cc, + BNXT_ULP_CLASS_HID_4e08 = 0x4e08, + BNXT_ULP_CLASS_HID_492c = 0x492c, + BNXT_ULP_CLASS_HID_3aac = 0x3aac, + BNXT_ULP_CLASS_HID_35d0 = 0x35d0, + BNXT_ULP_CLASS_HID_06c0 = 0x06c0, + BNXT_ULP_CLASS_HID_01e4 = 0x01e4, + BNXT_ULP_CLASS_HID_4d32 = 0x4d32, + BNXT_ULP_CLASS_HID_54aa = 0x54aa, + BNXT_ULP_CLASS_HID_0686 = 0x0686, + BNXT_ULP_CLASS_HID_540e = 0x540e, + BNXT_ULP_CLASS_HID_2e3c = 0x2e3c, + BNXT_ULP_CLASS_HID_3a20 = 0x3a20, + BNXT_ULP_CLASS_HID_46f0 = 0x46f0, + BNXT_ULP_CLASS_HID_52e4 = 0x52e4, + BNXT_ULP_CLASS_HID_55e4 = 0x55e4, + BNXT_ULP_CLASS_HID_21f8 = 0x21f8, + BNXT_ULP_CLASS_HID_75e8 = 0x75e8, + BNXT_ULP_CLASS_HID_41fc = 0x41fc, + BNXT_ULP_CLASS_HID_4d12 = 0x4d12, + BNXT_ULP_CLASS_HID_548a = 0x548a, + BNXT_ULP_CLASS_HID_3356 = 0x3356, + BNXT_ULP_CLASS_HID_1ace = 0x1ace, + BNXT_ULP_CLASS_HID_1a9a = 0x1a9a, + BNXT_ULP_CLASS_HID_4d46 = 0x4d46, + BNXT_ULP_CLASS_HID_2812 = 0x2812, + BNXT_ULP_CLASS_HID_338a = 0x338a, + BNXT_ULP_CLASS_HID_06e6 = 0x06e6, + BNXT_ULP_CLASS_HID_546e = 0x546e, + BNXT_ULP_CLASS_HID_46ee = 0x46ee, + BNXT_ULP_CLASS_HID_0d22 = 0x0d22, + BNXT_ULP_CLASS_HID_26e2 = 0x26e2, + BNXT_ULP_CLASS_HID_746a = 0x746a, + BNXT_ULP_CLASS_HID_1fa6 = 0x1fa6, + BNXT_ULP_CLASS_HID_2d2e = 0x2d2e, + BNXT_ULP_CLASS_HID_4ef2 = 0x4ef2, + BNXT_ULP_CLASS_HID_576a = 0x576a, + BNXT_ULP_CLASS_HID_30b6 = 0x30b6, + BNXT_ULP_CLASS_HID_192e = 0x192e, + BNXT_ULP_CLASS_HID_197a = 0x197a, + BNXT_ULP_CLASS_HID_4ea6 = 0x4ea6, + BNXT_ULP_CLASS_HID_2bf2 = 0x2bf2, + BNXT_ULP_CLASS_HID_306a = 0x306a, + BNXT_ULP_CLASS_HID_06c6 = 0x06c6, + BNXT_ULP_CLASS_HID_544e = 0x544e, + BNXT_ULP_CLASS_HID_46ce = 0x46ce, + BNXT_ULP_CLASS_HID_0d02 = 0x0d02, + BNXT_ULP_CLASS_HID_26c2 = 0x26c2, + BNXT_ULP_CLASS_HID_744a = 0x744a, + BNXT_ULP_CLASS_HID_1f86 = 0x1f86, + BNXT_ULP_CLASS_HID_2d0e = 0x2d0e, + BNXT_ULP_CLASS_HID_2e1c = 0x2e1c, + BNXT_ULP_CLASS_HID_3a00 = 0x3a00, + BNXT_ULP_CLASS_HID_46d0 = 0x46d0, + BNXT_ULP_CLASS_HID_52c4 = 0x52c4, + BNXT_ULP_CLASS_HID_4e10 = 0x4e10, + BNXT_ULP_CLASS_HID_5a04 = 0x5a04, + BNXT_ULP_CLASS_HID_1f98 = 0x1f98, + BNXT_ULP_CLASS_HID_72f8 = 0x72f8, + BNXT_ULP_CLASS_HID_0a78 = 0x0a78, + BNXT_ULP_CLASS_HID_166c = 0x166c, + BNXT_ULP_CLASS_HID_233c = 0x233c, + BNXT_ULP_CLASS_HID_0f20 = 0x0f20, + BNXT_ULP_CLASS_HID_2a7c = 0x2a7c, + BNXT_ULP_CLASS_HID_3660 = 0x3660, + BNXT_ULP_CLASS_HID_4330 = 0x4330, + BNXT_ULP_CLASS_HID_2f24 = 0x2f24, + BNXT_ULP_CLASS_HID_5584 = 0x5584, + BNXT_ULP_CLASS_HID_2198 = 0x2198, + BNXT_ULP_CLASS_HID_7588 = 0x7588, + BNXT_ULP_CLASS_HID_419c = 0x419c, + BNXT_ULP_CLASS_HID_7758 = 0x7758, + BNXT_ULP_CLASS_HID_43ac = 0x43ac, + BNXT_ULP_CLASS_HID_0c10 = 0x0c10, + BNXT_ULP_CLASS_HID_1864 = 0x1864, + BNXT_ULP_CLASS_HID_30c8 = 0x30c8, + BNXT_ULP_CLASS_HID_1cdc = 0x1cdc, + BNXT_ULP_CLASS_HID_50cc = 0x50cc, + BNXT_ULP_CLASS_HID_3d20 = 0x3d20, + BNXT_ULP_CLASS_HID_529c = 0x529c, + BNXT_ULP_CLASS_HID_3ef0 = 0x3ef0, + BNXT_ULP_CLASS_HID_72e0 = 0x72e0, + BNXT_ULP_CLASS_HID_5ef4 = 0x5ef4, + BNXT_ULP_CLASS_HID_2dfc = 0x2dfc, + BNXT_ULP_CLASS_HID_39e0 = 0x39e0, + BNXT_ULP_CLASS_HID_4530 = 0x4530, + BNXT_ULP_CLASS_HID_5124 = 0x5124, + BNXT_ULP_CLASS_HID_4df0 = 0x4df0, + BNXT_ULP_CLASS_HID_59e4 = 0x59e4, + BNXT_ULP_CLASS_HID_1c78 = 0x1c78, + BNXT_ULP_CLASS_HID_7118 = 0x7118, + BNXT_ULP_CLASS_HID_0998 = 0x0998, + BNXT_ULP_CLASS_HID_158c = 0x158c, + BNXT_ULP_CLASS_HID_20dc = 0x20dc, + BNXT_ULP_CLASS_HID_0cc0 = 0x0cc0, + BNXT_ULP_CLASS_HID_299c = 0x299c, + BNXT_ULP_CLASS_HID_3580 = 0x3580, + BNXT_ULP_CLASS_HID_40d0 = 0x40d0, + BNXT_ULP_CLASS_HID_2cc4 = 0x2cc4, + BNXT_ULP_CLASS_HID_55a4 = 0x55a4, + BNXT_ULP_CLASS_HID_21b8 = 0x21b8, + BNXT_ULP_CLASS_HID_75a8 = 0x75a8, + BNXT_ULP_CLASS_HID_41bc = 0x41bc, + BNXT_ULP_CLASS_HID_7778 = 0x7778, + BNXT_ULP_CLASS_HID_438c = 0x438c, + BNXT_ULP_CLASS_HID_0c30 = 0x0c30, + BNXT_ULP_CLASS_HID_1844 = 0x1844, + BNXT_ULP_CLASS_HID_30e8 = 0x30e8, + BNXT_ULP_CLASS_HID_1cfc = 0x1cfc, + BNXT_ULP_CLASS_HID_50ec = 0x50ec, + BNXT_ULP_CLASS_HID_3d00 = 0x3d00, + BNXT_ULP_CLASS_HID_52bc = 0x52bc, + BNXT_ULP_CLASS_HID_3ed0 = 0x3ed0, + BNXT_ULP_CLASS_HID_72c0 = 0x72c0, + BNXT_ULP_CLASS_HID_5ed4 = 0x5ed4, + BNXT_ULP_CLASS_HID_3866 = 0x3866, + BNXT_ULP_CLASS_HID_381e = 0x381e, + BNXT_ULP_CLASS_HID_3860 = 0x3860, + BNXT_ULP_CLASS_HID_0454 = 0x0454, + BNXT_ULP_CLASS_HID_3818 = 0x3818, + BNXT_ULP_CLASS_HID_042c = 0x042c, + BNXT_ULP_CLASS_HID_3846 = 0x3846, + BNXT_ULP_CLASS_HID_387e = 0x387e, + BNXT_ULP_CLASS_HID_3ba6 = 0x3ba6, + BNXT_ULP_CLASS_HID_385e = 0x385e, + BNXT_ULP_CLASS_HID_3840 = 0x3840, + BNXT_ULP_CLASS_HID_0474 = 0x0474, + BNXT_ULP_CLASS_HID_3878 = 0x3878, + BNXT_ULP_CLASS_HID_044c = 0x044c, + BNXT_ULP_CLASS_HID_3ba0 = 0x3ba0, + BNXT_ULP_CLASS_HID_0794 = 0x0794, + BNXT_ULP_CLASS_HID_3858 = 0x3858, + BNXT_ULP_CLASS_HID_046c = 0x046c }; enum bnxt_ulp_act_hid { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index e9799d0b90..dd23635c57 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Mar 4 10:12:06 2021 */ +/* date: Mon Mar 8 17:37:39 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -227,52 +227,81 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { /* List of device specific parameters */ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { [0] = { + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, [1] = { + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_TX }, [2] = { + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .direction = TF_DIR_TX }, [3] = { + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, [4] = { + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_TX }, [5] = { + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, .direction = TF_DIR_RX }, [6] = { + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_RX }, [7] = { + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_TX + }, + [8] = { + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [9] = { + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + [10] = { + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c index d0d96f32d4..e5a401e3f8 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c @@ -53,7 +53,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 2655bfdb9d..cb128e5695 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 3 16:36:04 2021 */ +/* date: Tue Mar 9 19:13:26 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -29,7 +29,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .start_tbl_idx = 5, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 0 } }, /* act_tid: 3, wh_plus, ingress */ @@ -39,7 +39,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .start_tbl_idx = 12, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 0 } }, /* act_tid: 4, wh_plus, egress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .start_tbl_idx = 18, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 16, + .cond_start_idx = 20, .cond_nums = 0 } }, /* act_tid: 5, wh_plus, egress */ @@ -59,7 +59,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .start_tbl_idx = 23, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, + .cond_start_idx = 28, .cond_nums = 0 } }, /* act_tid: 6, wh_plus, egress */ @@ -69,7 +69,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .start_tbl_idx = 29, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 23, + .cond_start_idx = 33, .cond_nums = 0 } } }; @@ -89,7 +89,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 0, @@ -113,7 +112,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -127,7 +125,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, @@ -136,7 +133,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -151,16 +147,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 12, - .cond_nums = 0 }, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -175,16 +169,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 13, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -200,9 +192,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -217,11 +208,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -240,11 +230,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 12, + .cond_start_idx = 14, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -259,16 +248,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -284,16 +271,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -313,11 +298,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -335,11 +319,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 1, @@ -360,11 +343,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 15, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 156, @@ -381,11 +363,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 16, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 157, @@ -402,11 +383,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, + .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 158, @@ -423,11 +403,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 159, @@ -441,16 +420,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 18, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 171, @@ -463,16 +440,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 19, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 197, @@ -490,11 +465,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 20, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 235, @@ -507,16 +481,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, - .cond_nums = 1 }, + .cond_start_idx = 21, + .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 236, @@ -530,16 +502,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 23, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 248, @@ -552,16 +522,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, - .cond_nums = 1 }, + .cond_start_idx = 24, + .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 274, @@ -575,16 +543,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, - .cond_nums = 1 }, + .cond_start_idx = 26, + .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 312, @@ -602,11 +568,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 28, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 350, @@ -623,11 +588,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 29, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 351, @@ -644,11 +608,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 30, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 352, @@ -665,11 +628,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 23, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 353, @@ -683,16 +645,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 23, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 31, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 365, @@ -705,16 +665,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 23, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 32, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 391, @@ -732,11 +690,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 33, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 429, @@ -753,11 +710,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 34, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 430, @@ -775,11 +731,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 35, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 433, @@ -793,16 +748,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 36, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 436, @@ -816,16 +769,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 37, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 448, @@ -838,16 +789,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, - .cond_nums = 0 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 38, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 474, @@ -910,6 +859,14 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, + /* cond_execute: act_tid: 1, int_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + /* cond_execute: act_tid: 1, ext_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, + }, /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -930,6 +887,14 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST }, + /* cond_execute: act_tid: 3, int_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + /* cond_execute: act_tid: 3, ext_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, + }, /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -937,16 +902,29 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { }, /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, + /* cond_execute: act_tid: 4, int_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, /* cond_execute: act_tid: 4, ext_full_act_record.no_tag */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, /* cond_execute: act_tid: 4, ext_full_act_record.one_tag */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, @@ -965,6 +943,14 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST }, + /* cond_execute: act_tid: 5, int_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + /* cond_execute: act_tid: 5, ext_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, + }, /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -979,6 +965,18 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG + }, + /* cond_execute: act_tid: 6, int_tun_encap_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + /* cond_execute: act_tid: 6, int_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + /* cond_execute: act_tid: 6, ext_full_act_record_vxlan.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index c636fd2aca..fba5b777f7 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 3 16:36:04 2021 */ +/* date: Mon Mar 8 17:37:39 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 1, wh_plus, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 17, + .num_tbls = 18, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, @@ -26,30 +26,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 14, - .start_tbl_idx = 17, + .start_tbl_idx = 18, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 23, .cond_nums = 1 } }, /* class_tid: 3, wh_plus, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 23, - .start_tbl_idx = 31, + .start_tbl_idx = 32, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 24, + .cond_start_idx = 33, .cond_nums = 0 } }, /* class_tid: 4, wh_plus, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 19, - .start_tbl_idx = 54, + .start_tbl_idx = 55, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 30, + .cond_start_idx = 39, .cond_nums = 0 } } }; @@ -69,7 +69,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 0, @@ -92,7 +91,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 1, @@ -111,7 +109,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 2, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -128,7 +125,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, @@ -157,7 +153,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 16, @@ -182,7 +177,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 18, @@ -196,16 +190,34 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 5, + .cond_true_goto = 2, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 3, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, + { /* class_tid: 1, wh_plus, table: control.2 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 5, + .cond_false_goto = 1023, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 4, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .cc_upd_info = { + .cc_opc = BNXT_ULP_CC_UPD_OPC_EQ, + .cc_src1 = BNXT_ULP_CC_UPD_SRC_REGFILE, + .cc_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .cc_src2 = BNXT_ULP_CC_UPD_SRC_COMP_FIELD, + .cc_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .cc_dst_opr = BNXT_ULP_RF_IDX_CC }, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, @@ -214,11 +226,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 3, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 5, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -242,11 +253,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, + .cond_start_idx = 7, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -270,11 +280,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -300,11 +309,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, + .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 150, @@ -319,14 +327,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, - .cond_nums = 2 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .cond_start_idx = 10, + .cond_nums = 3 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -343,14 +349,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 11, - .cond_nums = 2 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .cond_start_idx = 13, + .cond_nums = 3 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -367,14 +371,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, - .cond_nums = 2 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .cond_start_idx = 16, + .cond_nums = 3 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -395,9 +397,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, - .cond_nums = 2 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .cond_start_idx = 19, + .cond_nums = 3 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -414,14 +415,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, - .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 22, + .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -442,9 +441,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, + .cond_start_idx = 23, .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -466,11 +464,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, + .cond_start_idx = 24, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 217, @@ -489,11 +486,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, + .cond_start_idx = 25, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 218, @@ -510,9 +506,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 25, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -525,11 +520,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 26, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, @@ -554,11 +548,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 26, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 233, @@ -578,11 +571,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 26, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 235, @@ -599,9 +591,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 26, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -614,11 +605,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 27, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -642,11 +632,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 22, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -671,11 +660,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 22, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 324, @@ -690,14 +678,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, - .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .cond_start_idx = 28, + .cond_nums = 2 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -714,14 +700,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, - .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .cond_start_idx = 30, + .cond_nums = 2 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -738,14 +722,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, - .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 24, - .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 32, + .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -766,9 +748,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 24, + .cond_start_idx = 33, .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -790,11 +771,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 24, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 369, @@ -815,11 +795,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 24, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -836,11 +815,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 24, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 370, @@ -857,9 +835,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 33, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -872,11 +849,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 25, + .cond_start_idx = 34, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, @@ -903,11 +879,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 25, + .cond_start_idx = 34, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 384, @@ -926,11 +901,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 25, + .cond_start_idx = 34, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 266, @@ -945,11 +919,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 25, + .cond_start_idx = 34, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 267, @@ -964,11 +937,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 25, + .cond_start_idx = 34, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 268, @@ -982,9 +954,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 34, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, @@ -998,11 +969,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -1020,11 +990,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 385, @@ -1041,9 +1010,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 35, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -1056,11 +1024,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, @@ -1085,11 +1052,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 399, @@ -1109,11 +1075,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 400, @@ -1130,9 +1095,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 36, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -1145,11 +1109,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 28, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, @@ -1174,11 +1137,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 37, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 414, @@ -1199,11 +1161,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 39, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -1220,11 +1181,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 39, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 355, @@ -1239,11 +1199,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 39, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 356, @@ -1258,11 +1217,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 39, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 357, @@ -1279,11 +1237,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 39, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -1301,11 +1258,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 39, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 415, @@ -1322,9 +1278,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 39, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -1337,11 +1292,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, @@ -1366,11 +1320,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 429, @@ -1389,11 +1342,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 401, @@ -1408,11 +1360,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 402, @@ -1427,11 +1378,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 403, @@ -1448,11 +1398,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -1469,11 +1418,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, @@ -1499,11 +1447,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 443, @@ -1520,9 +1467,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 40, .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -1535,11 +1481,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, @@ -1564,11 +1509,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 457, @@ -1589,11 +1533,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -1612,11 +1555,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -1634,11 +1576,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, @@ -1654,11 +1595,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, @@ -1683,11 +1623,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, @@ -1727,6 +1666,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* cond_execute: class_tid: 1, control.2 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_CC + }, /* cond_execute: class_tid: 1, profile_tcam.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, @@ -1752,6 +1696,9 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 1, em.ipv4 */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, @@ -1761,6 +1708,9 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 1, eem.ipv4 */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, @@ -1770,6 +1720,9 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 1, em.ipv6 */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, @@ -1779,6 +1732,9 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 1, eem.ipv6 */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, @@ -1786,6 +1742,10 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, + /* cond_execute: class_tid: 1, em.vxlan */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, /* cond_reject: wh_plus, class_tid: 2 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, @@ -1813,14 +1773,24 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }, /* cond_execute: class_tid: 2, em.ipv4 */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, /* cond_execute: class_tid: 2, eem.ipv4 */ { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, + }, + { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* cond_execute: class_tid: 2, em.ipv6 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, /* cond_execute: class_tid: 3, control.ing_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index b35846c7a9..b5bc433810 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -68,6 +68,7 @@ struct ulp_rte_parser_params { struct ulp_rte_hdr_bitmap hdr_bitmap; struct ulp_rte_hdr_bitmap hdr_fp_bit; struct ulp_rte_field_bitmap fld_bitmap; + struct ulp_rte_field_bitmap fld_s_bitmap; struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX]; uint32_t comp_fld[BNXT_ULP_CF_IDX_LAST]; uint32_t field_idx; @@ -172,6 +173,15 @@ struct bnxt_ulp_mapper_cond_list_info { int32_t cond_false_goto; }; +struct bnxt_ulp_mapper_cc_upd_info { + enum bnxt_ulp_cc_upd_opc cc_opc; + enum bnxt_ulp_cc_upd_src cc_src1; + enum bnxt_ulp_cc_upd_src cc_src2; + uint16_t cc_opr1; + uint16_t cc_opr2; + uint16_t cc_dst_opr; +}; + struct bnxt_ulp_template_device_tbls { struct bnxt_ulp_mapper_tmpl_info *tmpl_list; uint32_t tmpl_list_size; @@ -231,9 +241,9 @@ struct bnxt_ulp_mapper_tbl_info { uint32_t resource_type; /* TF_ enum type */ enum bnxt_ulp_resource_sub_type resource_sub_type; struct bnxt_ulp_mapper_cond_list_info execute_info; + struct bnxt_ulp_mapper_cc_upd_info cc_upd_info; enum bnxt_ulp_cond_opc cond_opcode; uint32_t cond_operand; - enum bnxt_ulp_mem_type_opc mem_type_opcode; uint8_t direction; enum bnxt_ulp_pri_opc pri_opcode; uint32_t pri_operand; @@ -302,6 +312,7 @@ struct bnxt_ulp_mapper_ident_info { }; struct bnxt_ulp_glb_resource_info { + enum bnxt_ulp_device_id device_id; enum bnxt_ulp_resource_func resource_func; uint32_t resource_type; /* TF_ enum type */ enum bnxt_ulp_glb_rf_idx glb_regfile_index; diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index 5dc710338a..329799ea6a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -1085,7 +1085,7 @@ uint32_t ulp_bitmap_is_ones(uint8_t *bitmap, int32_t size) } /* Function to check if bitmap is not zero. Return 1 on success */ -uint32_t ulp_bitmap_notzero(uint8_t *bitmap, int32_t size) +uint32_t ulp_bitmap_notzero(const uint8_t *bitmap, int32_t size) { while (size-- > 0) { if (*bitmap != 0) diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h index a30361b8ae..5dd22cf8c3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.h +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h @@ -521,7 +521,7 @@ uint32_t ulp_bitmap_is_zero(uint8_t *bitmap, int32_t size); uint32_t ulp_bitmap_is_ones(uint8_t *bitmap, int32_t size); /* Function to check if bitmap is not zero. Return 1 on success */ -uint32_t ulp_bitmap_notzero(uint8_t *bitmap, int32_t size); +uint32_t ulp_bitmap_notzero(const uint8_t *bitmap, int32_t size); /* returns 0 if input is power of 2 */ int32_t ulp_util_is_power_of_2(uint64_t x); From patchwork Sun May 30 08:59:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93590 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 27DA3A0524; Sun, 30 May 2021 11:06:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3807E4111D; Sun, 30 May 2021 11:01:57 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 401B2410F0 for ; Sun, 30 May 2021 11:01:55 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id D0CA57DAF; Sun, 30 May 2021 02:01:53 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com D0CA57DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365314; bh=SRGLuVbkNFXujfT/AcN5km3BOh9N2N/j0Wbh/UlFPxU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m9waqH7EhgXNUrEND0+WLNaTixPPyF7LhCY55q7vNNzknBsP8Mr4n8blTU7ZO78Jk s8TNKw4zUVdVeDz4IdQIx7uDtu3o10pWPBl/wSS/+rfTdB9NDhsoE/KJzTJuLYL8Xj 5mRLZFG6W0dJZMUESTIp1/+L2pi2SFp94o8Cyv9s= From: Venkat Duvvuru To: dev@dpdk.org Cc: Mike Baucom , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:19 +0530 Message-Id: <20210530085929.29695-49-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 48/58] net/bnxt: add shared session support to ULP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Mike Baucom Shared session permits cooperative sharing of prescribed resources between applications. - devargs added for app-id in order to enable sharing session resources across applications - shared session management added - tf resource reservations are now app and device dependent Signed-off-by: Mike Baucom Signed-off-by: Venkat Duvvuru Reviewed-by: Kishore Padmanabha --- drivers/net/bnxt/bnxt.h | 2 + drivers/net/bnxt/bnxt_ethdev.c | 50 + drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 645 +++-- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 39 + drivers/net/bnxt/tf_ulp/ulp_mapper.c | 186 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 1 + .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 13 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 2177 +++++++++++++++++ drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 33 + 9 files changed, 2909 insertions(+), 237 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 246f51fddf..9309eb68b7 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -831,9 +831,11 @@ struct bnxt { uint16_t port_svif; struct tf tfp; + struct tf tfp_shared; struct bnxt_ulp_context *ulp_ctx; struct bnxt_flow_stat_info *flow_stat; uint16_t max_num_kflows; + uint8_t app_id; uint16_t tx_cfa_action; }; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 1c0eeb76b7..fdde9b2720 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -97,6 +97,7 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" +#define BNXT_DEVARG_APP_ID "app-id" static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, @@ -109,6 +110,7 @@ static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REP_Q_F2R, BNXT_DEVARG_REP_FC_R2F, BNXT_DEVARG_REP_FC_F2R, + BNXT_DEVARG_APP_ID, NULL }; @@ -118,6 +120,11 @@ static const char *const bnxt_dev_args[] = { */ #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) +/* + * app-id = an non-negative 8-bit number + */ +#define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255) + /* * flow_xstat == false to disable the feature * flow_xstat == true to enable the feature @@ -5351,6 +5358,42 @@ bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, return 0; } +static int +bnxt_parse_devarg_app_id(__rte_unused const char *key, + const char *value, void *opaque_arg) +{ + struct bnxt *bp = opaque_arg; + unsigned long app_id; + char *end = NULL; + + if (!value || !opaque_arg) { + PMD_DRV_LOG(ERR, + "Invalid parameter passed to app-id " + "devargs.\n"); + return -EINVAL; + } + + app_id = strtoul(value, &end, 10); + if (end == NULL || *end != '\0' || + (app_id == ULONG_MAX && errno == ERANGE)) { + PMD_DRV_LOG(ERR, + "Invalid parameter passed to app_id " + "devargs.\n"); + return -EINVAL; + } + + if (BNXT_DEVARG_APP_ID_INVALID(app_id)) { + PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n", + (uint16_t)app_id); + return -EINVAL; + } + + bp->app_id = app_id; + PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id); + + return 0; +} + static int bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -5612,6 +5655,13 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) goto err; err: + /* + * Handler for "app-id" devarg. + * Invoked as for ex: "-a 000:00:0d.0,app-id=1" + */ + rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID, + bnxt_parse_devarg_app_id, bp); + rte_kvargs_free(kvlist); return ret; } diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index dd992a246b..632334674c 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -68,240 +68,336 @@ bnxt_ulp_devid_get(struct bnxt *bp, return 0; } +struct bnxt_ulp_app_capabilities_info * +bnxt_ulp_app_cap_list_get(uint32_t *num_entries) +{ + if (!num_entries) + return NULL; + *num_entries = BNXT_ULP_APP_CAP_TBL_MAX_SZ; + return ulp_app_cap_info_list; +} + +struct bnxt_ulp_resource_resv_info * +bnxt_ulp_resource_resv_list_get(uint32_t *num_entries) +{ + if (!num_entries) + return NULL; + *num_entries = BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ; + return ulp_resource_resv_list; +} + +struct bnxt_ulp_glb_resource_info * +bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries) +{ + if (!num_entries) + return NULL; + *num_entries = BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ; + return ulp_app_glb_resource_tbl; +} + static int32_t -bnxt_ulp_tf_session_resources_get(struct bnxt *bp, - struct tf_session_resources *res) +bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, + struct tf_session_resources *res) { - uint32_t dev_id; + struct bnxt_ulp_resource_resv_info *info = NULL; + uint32_t dev_id, res_type, i, num; + enum tf_dir dir; + uint8_t app_id; + int32_t rc = 0; + + if (!ulp_ctx || !res) { + BNXT_TF_DBG(ERR, "Invalid arguments to get resources.\n"); + return -EINVAL; + } + + info = bnxt_ulp_resource_resv_list_get(&num); + if (!info) { + BNXT_TF_DBG(ERR, "Unable to get resource reservation list.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to get the device id from ulp.\n"); + return -EINVAL; + } + + for (i = 0; i < num; i++) { + if (app_id != info[i].app_id || dev_id != info[i].device_id) + continue; + dir = info[i].direction; + res_type = info[i].resource_type; + + switch (info[i].resource_func) { + case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: + res->ident_cnt[dir].cnt[res_type] = info[i].count; + break; + case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: + res->tbl_cnt[dir].cnt[res_type] = info[i].count; + break; + case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: + res->tcam_cnt[dir].cnt[res_type] = info[i].count; + break; + case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: + res->em_cnt[dir].cnt[res_type] = info[i].count; + break; + default: + break; + } + } + + return 0; +} + +static int32_t +bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, + struct tf_session_resources *res) +{ + struct bnxt_ulp_glb_resource_info *info; + uint32_t dev_id, res_type, i, num; + enum tf_dir dir; + uint8_t app_id; int32_t rc; - uint16_t *tmp_cnt; - rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id); + rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n"); return -EINVAL; } - switch (dev_id) { - case BNXT_ULP_DEVICE_ID_WH_PLUS: - /** RX **/ - /* Identifiers */ - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 422; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 6; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 192; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 192; - - /* Table Types */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 8192; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023; - - /* ENCAP */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 511; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 63; - - /* TCAMs */ - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = - 422; - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = - 6; - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960; - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 88; - - /* EM */ - res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13168; - - /* EEM */ - res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_TBL_SCOPE] = 1; - - /* SP */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 255; - - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1; - - /** TX **/ - /* Identifiers */ - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 292; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 148; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 192; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 192; - - /* Table Types */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 8192; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023; - - /* ENCAP */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 511; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 223; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 255; - - /* TCAMs */ - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = - 292; - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = - 144; - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960; - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 928; - - /* EM */ - res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 15232; - - /* EEM */ - res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_TBL_SCOPE] = 1; - - /* SP */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 511; - - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1; + /* Make sure the resources are zero before accumulating. */ + memset(res, 0, sizeof(struct tf_session_resources)); + /* Get the list and tally the resources. */ + info = bnxt_ulp_app_glb_resource_info_list_get(&num); + if (!info) { + BNXT_TF_DBG(ERR, "Unable to get app global resource list\n"); + return -EINVAL; + } + for (i = 0; i < num; i++) { + if (dev_id != info[i].device_id || app_id != info[i].app_id) + continue; + dir = info[i].direction; + res_type = info[i].resource_type; + + switch (info[i].resource_func) { + case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: + res->ident_cnt[dir].cnt[res_type]++; + break; + case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: + res->tbl_cnt[dir].cnt[res_type]++; + break; + case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: + res->tcam_cnt[dir].cnt[res_type]++; + break; + case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: + res->em_cnt[dir].cnt[res_type]++; + break; + default: + BNXT_TF_DBG(ERR, "Unknown resource func (0x%x)\n,", + info[i].resource_func); + continue; + } + } + + return 0; +} + +int32_t +bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, + uint8_t app_id, uint32_t dev_id) +{ + struct bnxt_ulp_app_capabilities_info *info; + uint32_t num = 0; + uint16_t i; + bool found = false; + + if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { + BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + return -EINVAL; + } + + info = bnxt_ulp_app_cap_list_get(&num); + if (!info || !num) { + BNXT_TF_DBG(ERR, "Failed to get app capabilities.\n"); + return -EINVAL; + } + + for (i = 0; i < num; i++) { + if (info[i].app_id != app_id || info[i].device_id != dev_id) + continue; + found = true; + if (info[i].flags & BNXT_ULP_APP_CAP_SHARED_EN) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_SHARED_SESSION_ENABLED; + } + if (!found) { + BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_DEV_UNSUPPORTED; + return -EINVAL; + } + + return 0; +} + +static void +ulp_ctx_shared_session_close(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + struct tf *tfp; + int32_t rc; + + if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) + return; + + tfp = bnxt_ulp_cntxt_shared_tfp_get(bp->ulp_ctx); + if (!tfp) { + /* + * Log it under debug since this is likely a case of the + * shared session not being created. For example, a failed + * initialization. + */ + BNXT_TF_DBG(DEBUG, "Failed to get shared tfp on close.\n"); + return; + } + rc = tf_close_session(tfp); + if (rc) + BNXT_TF_DBG(ERR, "Failed to close the shared session rc=%d.\n", + rc); + (void)bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, NULL); + + session->g_shared_tfp.session = NULL; +} + +static int32_t +ulp_ctx_shared_session_open(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + struct rte_eth_dev *ethdev = bp->eth_dev; + struct tf_session_resources *resources; + struct tf_open_session_parms parms; + size_t copy_num_bytes; + uint32_t ulp_dev_id; + int32_t rc = 0; + + /* only perform this if shared session is enabled. */ + if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) + return 0; + + memset(&parms, 0, sizeof(parms)); + + rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id, + parms.ctrl_chan_name); + if (rc) { + BNXT_TF_DBG(ERR, "Invalid port %d, rc = %d\n", + ethdev->data->port_id, rc); + return rc; + } + resources = &parms.resources; + + /* + * Need to account for size of ctrl_chan_name and 1 extra for Null + * terminator + */ + copy_num_bytes = sizeof(parms.ctrl_chan_name) - + strlen(parms.ctrl_chan_name) - 1; + + /* Build the ctrl_chan_name with shared token */ + strncat(parms.ctrl_chan_name, "-tf_shared", copy_num_bytes); + + rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, resources); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to get shared resource count.\n"); + return rc; + } + + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n"); + return rc; + } + + switch (ulp_dev_id) { + case BNXT_ULP_DEVICE_ID_WH_PLUS: + parms.device_type = TF_DEVICE_TYPE_WH; break; case BNXT_ULP_DEVICE_ID_STINGRAY: - /** RX **/ - /* Identifiers */ - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 315; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 6; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 192; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 192; - - /* Table Types */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 16384; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023; - - /* ENCAP */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 511; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 63; - - /* TCAMs */ - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = - 315; - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = - 6; - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960; - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 112; - - /* EM */ - res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13200; - - /* EEM */ - res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_TBL_SCOPE] = 1; - - /* SP */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 256; - - /** TX **/ - /* Identifiers */ - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 292; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 127; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 192; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 192; - - /* Table Types */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 16384; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023; - - /* ENCAP */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 367; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 223; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 255; - - /* TCAMs */ - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = - 292; - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = - 127; - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960; - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 928; - - /* EM */ - res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 15232; - - /* EEM */ - res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_TBL_SCOPE] = 1; - - /* SP */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 512; + parms.device_type = TF_DEVICE_TYPE_SR; break; case BNXT_ULP_DEVICE_ID_THOR: - /** RX **/ - /* Identifiers */ - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 26; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 6; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 32; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 32; - res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 32; - - /* Table Types */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 1024; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 512; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 14; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_EM_FKB] = 32; - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_WC_FKB] = 32; - - /* ENCAP */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 64; - - /* TCAMs */ - tmp_cnt = &res->tcam_cnt[TF_DIR_RX].cnt[0]; - tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = 300; - tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = 6; - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 128; - res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 112; - - /* EM */ - res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13200; - - /* SP */ - res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 64; - - /** TX **/ - /* Identifiers */ - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 26; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 26; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 32; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 63; - res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 32; - - /* Table Types */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 1024; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 512; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 14; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_EM_FKB] = 32; - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_WC_FKB] = 32; - - /* ENCAP */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 64; - - /* TCAMs */ - tmp_cnt = &res->tcam_cnt[TF_DIR_TX].cnt[0]; - - tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = 200; - tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = 110; - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 128; - res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 128; - - /* EM */ - res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 15232; - - /* SP */ - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 100; - - res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1; - + parms.device_type = TF_DEVICE_TYPE_THOR; break; default: - return -EINVAL; + BNXT_TF_DBG(ERR, "Unable to determine device for " + "opening session.\n"); + return rc; } - return 0; + parms.shadow_copy = true; + parms.bp = bp; + + /* + * Open the session here, but the collect the resources during the + * mapper initialization. + */ + rc = tf_open_session(&bp->tfp_shared, &parms); + if (rc) + return rc; + + if (parms.shared_session_creator) + BNXT_TF_DBG(DEBUG, "Shared session creator.\n"); + else + BNXT_TF_DBG(DEBUG, "Shared session attached.\n"); + + /* Save the shared session in global data */ + if (!session->g_shared_tfp.session) + session->g_shared_tfp.session = bp->tfp_shared.session; + + rc = bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, &bp->tfp_shared); + if (rc) + BNXT_TF_DBG(ERR, "Failed to add shared tfp to ulp (%d)\n", rc); + + return rc; +} + +static int32_t +ulp_ctx_shared_session_attach(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + int32_t rc = 0; + + /* Simply return success if shared session not enabled */ + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { + bp->tfp_shared.session = session->g_shared_tfp.session; + rc = ulp_ctx_shared_session_open(bp, session); + } + + return rc; +} + +static void +ulp_ctx_shared_session_detach(struct bnxt *bp) +{ + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { + if (bp->tfp_shared.session) { + tf_close_session(&bp->tfp_shared); + bp->tfp_shared.session = NULL; + } + } } /* @@ -360,7 +456,7 @@ ulp_ctx_session_open(struct bnxt *bp, } resources = ¶ms.resources; - rc = bnxt_ulp_tf_session_resources_get(bp, resources); + rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx, resources); if (rc) { BNXT_TF_DBG(ERR, "Unable to determine tf resources for " "session open.\n"); @@ -557,6 +653,9 @@ ulp_ctx_deinit(struct bnxt *bp, /* close the tf session */ ulp_ctx_session_close(bp, session); + /* The shared session must be closed last. */ + ulp_ctx_shared_session_close(bp, session); + /* Free the contents */ if (session->cfg_data) { rte_free(session->cfg_data); @@ -601,6 +700,29 @@ ulp_ctx_init(struct bnxt *bp, goto error_deinit; } + rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n"); + goto error_deinit; + } + + rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to set capabilities for " + " app(%x)/dev(%x)\n", bp->app_id, devid); + goto error_deinit; + } + + /* + * Shared session must be created before first regular session but after + * the ulp_ctx is valid. + */ + rc = ulp_ctx_shared_session_open(bp, session); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n", rc); + goto error_deinit; + } + /* Open the ulp session. */ rc = ulp_ctx_session_open(bp, session); if (rc) @@ -677,6 +799,8 @@ ulp_ctx_attach(struct bnxt *bp, struct bnxt_ulp_session_state *session) { int32_t rc = 0; + uint32_t flags, dev_id; + uint8_t app_id; /* Increment the ulp context data reference count usage. */ bp->ulp_ctx->cfg_data = session->cfg_data; @@ -685,6 +809,29 @@ ulp_ctx_attach(struct bnxt *bp, /* update the session details in bnxt tfp */ bp->tfp.session = session->g_tfp->session; + /* + * The supported flag will be set during the init. Use it now to + * know if we should go through the attach. + */ + rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable do get the dev_id.\n"); + return -EINVAL; + } + + flags = bp->ulp_ctx->cfg_data->ulp_flags; + if (ULP_APP_DEV_UNSUPPORTED_ENABLED(flags)) { + BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + return -EINVAL; + } + /* Create a TF Client */ rc = ulp_ctx_session_open(bp, session); if (rc) { @@ -1126,6 +1273,18 @@ bnxt_ulp_port_init(struct bnxt *bp) BNXT_TF_DBG(ERR, "Failed to attach the ulp context\n"); goto jump_to_error; } + + /* + * Attach to the shared session, must be called after the + * ulp_ctx_attach in order to ensure that ulp data is available + * for attaching. + */ + rc = ulp_ctx_shared_session_attach(bp, session); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed attach to shared session (%d)", rc); + goto jump_to_error; + } } else { rc = bnxt_ulp_init(bp, session); if (rc) { @@ -1224,6 +1383,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp) /* close the session associated with this port */ ulp_ctx_detach(bp); + + /* always detach/close shared after the session. */ + ulp_ctx_shared_session_detach(bp); } else { /* Perform ulp ctx deinit */ bnxt_ulp_deinit(bp, session); @@ -1264,6 +1426,31 @@ bnxt_ulp_cntxt_ptr2_mark_db_get(struct bnxt_ulp_context *ulp_ctx) return ulp_ctx->cfg_data->mark_tbl; } +bool +bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx) +{ + return ULP_SHARED_SESSION_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags); +} + +int32_t +bnxt_ulp_cntxt_app_id_set(struct bnxt_ulp_context *ulp_ctx, uint8_t app_id) +{ + if (!ulp_ctx) + return -EINVAL; + ulp_ctx->cfg_data->app_id = app_id; + return 0; +} + +int32_t +bnxt_ulp_cntxt_app_id_get(struct bnxt_ulp_context *ulp_ctx, uint8_t *app_id) +{ + /* Default APP id is zero */ + if (!ulp_ctx || !app_id) + return -EINVAL; + *app_id = ulp_ctx->cfg_data->app_id; + return 0; +} + /* Function to set the device id of the hardware. */ int32_t bnxt_ulp_cntxt_dev_id_set(struct bnxt_ulp_context *ulp_ctx, @@ -1341,6 +1528,30 @@ bnxt_ulp_cntxt_tbl_scope_id_set(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } +/* Function to set the shared tfp session details from the ulp context. */ +int32_t +bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp) +{ + if (!ulp) { + BNXT_TF_DBG(ERR, "Invalid arguments\n"); + return -EINVAL; + } + + ulp->g_shared_tfp = tfp; + return 0; +} + +/* Function to get the shared tfp session details from the ulp context. */ +struct tf * +bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp) +{ + if (!ulp) { + BNXT_TF_DBG(ERR, "Invalid arguments\n"); + return NULL; + } + return ulp->g_shared_tfp; +} + /* Function to set the tfp session details from the ulp context. */ int32_t bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 854eca24c3..648fb2ab37 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -29,7 +29,13 @@ /* defines for the ulp_flags */ #define BNXT_ULP_VF_REP_ENABLED 0x1 +#define BNXT_ULP_SHARED_SESSION_ENABLED 0x2 +#define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) +#define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ + BNXT_ULP_SHARED_SESSION_ENABLED) +#define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag) ((flag) &\ + BNXT_ULP_APP_DEV_UNSUPPORTED) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -67,11 +73,13 @@ struct bnxt_ulp_data { #define BNXT_ULP_MAX_TUN_CACHE_ENTRIES 16 struct bnxt_tun_cache_entry tun_tbl[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; bool accum_stats; + uint8_t app_id; }; struct bnxt_ulp_context { struct bnxt_ulp_data *cfg_data; struct tf *g_tfp; + struct tf *g_shared_tfp; }; struct bnxt_ulp_pci_info { @@ -86,6 +94,7 @@ struct bnxt_ulp_session_state { struct bnxt_ulp_pci_info pci_info; struct bnxt_ulp_data *cfg_data; struct tf *g_tfp; + struct tf g_shared_tfp; uint32_t session_opened; }; @@ -135,6 +144,14 @@ int32_t bnxt_ulp_cntxt_tbl_scope_id_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *tbl_scope_id); +/* Function to set the tfp session details in the ulp context. */ +int32_t +bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp); + +/* Function to get the tfp session details from ulp context. */ +struct tf * +bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp); + /* Function to set the tfp session details in the ulp context. */ int32_t bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp); @@ -233,4 +250,26 @@ bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx); int32_t ulp_post_process_tun_flow(struct ulp_rte_parser_params *params); +struct bnxt_ulp_glb_resource_info * +bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries); + +int32_t +bnxt_ulp_cntxt_app_id_set(struct bnxt_ulp_context *ulp_ctx, uint8_t app_id); + +int32_t +bnxt_ulp_cntxt_app_id_get(struct bnxt_ulp_context *ulp_ctx, uint8_t *app_id); + +bool +bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx); + +struct bnxt_ulp_app_capabilities_info * +bnxt_ulp_app_cap_list_get(uint32_t *num_entries); + +int32_t +bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, + uint8_t app_id, uint32_t dev_id); + +struct bnxt_ulp_resource_resv_info * +bnxt_ulp_resource_resv_list_get(uint32_t *num_entries); + #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 60c60564c4..58104eeedf 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -58,13 +58,15 @@ static int32_t ulp_mapper_glb_resource_read(struct bnxt_ulp_mapper_data *mapper_data, enum tf_dir dir, uint16_t idx, - uint64_t *regval) + uint64_t *regval, + bool *shared) { - if (!mapper_data || !regval || + if (!mapper_data || !regval || !shared || dir >= TF_DIR_MAX || idx >= BNXT_ULP_GLB_RF_IDX_LAST) return -EINVAL; *regval = mapper_data->glb_res_tbl[dir][idx].resource_hndl; + *shared = mapper_data->glb_res_tbl[dir][idx].shared; return 0; } @@ -78,7 +80,7 @@ ulp_mapper_glb_resource_read(struct bnxt_ulp_mapper_data *mapper_data, static int32_t ulp_mapper_glb_resource_write(struct bnxt_ulp_mapper_data *data, struct bnxt_ulp_glb_resource_info *res, - uint64_t regval) + uint64_t regval, bool shared) { struct bnxt_ulp_mapper_glb_resource_entry *ent; @@ -92,6 +94,7 @@ ulp_mapper_glb_resource_write(struct bnxt_ulp_mapper_data *data, ent->resource_func = res->resource_func; ent->resource_type = res->resource_type; ent->resource_hndl = regval; + ent->shared = shared; return 0; } @@ -129,8 +132,12 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx, /* entries are stored as big-endian format */ regval = tfp_cpu_to_be_64((uint64_t)iparms.id); - /* write to the mapper global resource */ - rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval); + /* + * write to the mapper global resource + * Shared resources are never allocated through this method, so the + * shared flag is always false. + */ + rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, false); if (rc) { BNXT_TF_DBG(ERR, "Failed to write to global resource id\n"); /* Free the identifier when update failed */ @@ -186,8 +193,12 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, /* entries are stored as big-endian format */ regval = tfp_cpu_to_be_64((uint64_t)aparms.idx); - /* write to the mapper global resource */ - rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval); + /* + * write to the mapper global resource + * Shared resources are never allocated through this method, so the + * shared flag is always false. + */ + rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, false); if (rc) { BNXT_TF_DBG(ERR, "Failed to write to global resource id\n"); /* Free the identifier when update failed */ @@ -963,6 +974,7 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, uint32_t update_flag = 0; uint64_t src1_val64; uint32_t port_id; + bool shared; /* process the field opcode */ if (fld->field_opc != BNXT_ULP_FIELD_OPC_COND_OP) { @@ -1244,9 +1256,8 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } idx = tfp_be_to_cpu_16(idx); - if (ulp_mapper_glb_resource_read(parms->mapper_data, - dir, - idx, ®val)) { + if (ulp_mapper_glb_resource_read(parms->mapper_data, dir, + idx, ®val, &shared)) { BNXT_TF_DBG(ERR, "%s global regfile[%d] read failed.\n", name, idx); return -EINVAL; @@ -2215,6 +2226,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, bool write = false; bool global = false; uint64_t act_rec_size; + bool shared = false; /* use the max size if encap is enabled */ if (tbl->encap_num_fields) @@ -2293,7 +2305,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, if (ulp_mapper_glb_resource_read(parms->mapper_data, tbl->direction, tbl->tbl_operand, - ®val)) { + ®val, &shared)) { BNXT_TF_DBG(ERR, "Failed to get tbl idx from Global " "regfile[%d].\n", @@ -2400,8 +2412,13 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, regval = tfp_cpu_to_be_64(regval); if (global) { + /* + * Shared resources are never allocated through this + * method, so the shared flag is always false. + */ rc = ulp_mapper_glb_resource_write(parms->mapper_data, - &glb_res, regval); + &glb_res, regval, + false); } else { rc = ulp_regfile_write(parms->regfile, tbl->tbl_operand, regval); @@ -2422,6 +2439,8 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, sparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen); sparms.idx = index; sparms.tbl_scope_id = tbl_scope_id; + if (shared) + tfp = bnxt_ulp_cntxt_shared_tfp_get(parms->ulp_ctx); rc = tf_set_tbl_entry(tfp, &sparms); if (rc) { BNXT_TF_DBG(ERR, @@ -2469,6 +2488,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, } return rc; error: + /* Shared resources are not freed */ + if (shared) + return rc; /* * Free the allocated resource since we failed to either * write to the entry or link the flow @@ -2810,7 +2832,8 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_mapper_data *mapper_data) { struct bnxt_ulp_glb_resource_info *glb_res; - uint32_t num_glb_res_ids, idx; + uint32_t num_glb_res_ids, idx, dev_id; + uint8_t app_id; int32_t rc = 0; glb_res = ulp_mapper_glb_resource_info_list_get(&num_glb_res_ids); @@ -2819,8 +2842,25 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } + rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to get device id for " + "global init (%d)\n", rc); + return rc; + } + + rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to get app id for " + "global init (%d)\n", rc); + return rc; + } + /* Iterate the global resources and process each one */ for (idx = 0; idx < num_glb_res_ids; idx++) { + if (dev_id != glb_res[idx].device_id || + glb_res[idx].app_id != app_id) + continue; switch (glb_res[idx].resource_func) { case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: rc = ulp_mapper_resource_ident_allocate(ulp_ctx, @@ -2844,6 +2884,104 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, return rc; } +/* + * Iterate over the shared resources assigned during tf_open_session and store + * them in the global regfile with the shared flag. + */ +static int32_t +ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, + struct bnxt_ulp_mapper_data *mapper_data) +{ + struct bnxt_ulp_glb_resource_info *glb_res; + struct tf_get_session_info_parms sparms; + uint32_t num_entries, i, dev_id, res; + struct tf_resource_info *res_info; + uint64_t regval; + enum tf_dir dir; + int32_t rc = 0; + struct tf *tfp; + uint8_t app_id; + + memset(&sparms, 0, sizeof(sparms)); + + glb_res = bnxt_ulp_app_glb_resource_info_list_get(&num_entries); + if (!glb_res || !num_entries) { + BNXT_TF_DBG(ERR, "Invalid Arguments\n"); + return -EINVAL; + } + + tfp = bnxt_ulp_cntxt_shared_tfp_get(ulp_ctx); + if (!tfp) { + BNXT_TF_DBG(ERR, "Failed to get tfp for app global init"); + return -EINVAL; + } + /* + * Retrieve the resources that were assigned during the shared session + * creation. + */ + rc = tf_get_session_info(tfp, &sparms); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to get session info (%d)\n", rc); + return rc; + } + + rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to get the app id in global init " + "(%d).\n", rc); + return rc; + } + + rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to get device id for app " + "global init (%d)\n", rc); + return rc; + } + + /* Store all the app global resources */ + for (i = 0; i < num_entries; i++) { + if (dev_id != glb_res[i].device_id || + app_id != glb_res[i].app_id) + continue; + dir = glb_res[i].direction; + res = glb_res[i].resource_type; + + switch (glb_res[i].resource_func) { + case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: + res_info = &sparms.session_info.ident[dir].info[res]; + break; + case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: + res_info = &sparms.session_info.tbl[dir].info[res]; + break; + case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: + res_info = &sparms.session_info.tcam[dir].info[res]; + break; + case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: + res_info = &sparms.session_info.em[dir].info[res]; + break; + default: + BNXT_TF_DBG(ERR, "Unknown resource func (0x%x)\n", + glb_res[i].resource_func); + continue; + } + + regval = tfp_cpu_to_be_64((uint64_t)res_info->start); + res_info->start++; + + /* + * All resources written to the global regfile are shared for + * this function. + */ + rc = ulp_mapper_glb_resource_write(mapper_data, &glb_res[i], + regval, true); + if (rc) + return rc; + } + + return rc; +} + /* * Common conditional opcode process routine that is used for both the template * rejection and table conditional execution. @@ -2994,6 +3132,7 @@ ulp_mapper_cc_upd_opr_compute(struct bnxt_ulp_mapper_parms *parms, uint64_t *result) { uint64_t regval; + bool shared; *result = false; switch (cc_src) { @@ -3013,7 +3152,7 @@ ulp_mapper_cc_upd_opr_compute(struct bnxt_ulp_mapper_parms *parms, break; case BNXT_ULP_CC_UPD_SRC_GLB_REGFILE: if (ulp_mapper_glb_resource_read(parms->mapper_data, dir, - cc_opr, ®val)) { + cc_opr, ®val, &shared)) { BNXT_TF_DBG(ERR, "global regfile[%d] read failed.\n", cc_opr); return -EINVAL; @@ -3493,11 +3632,11 @@ ulp_mapper_glb_resource_info_deinit(struct bnxt_ulp_context *ulp_ctx, /* Iterate the global resources and process each one */ for (dir = TF_DIR_RX; dir < TF_DIR_MAX; dir++) { - for (idx = 0; idx < BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ; - idx++) { + for (idx = 0; idx < BNXT_ULP_GLB_RF_IDX_LAST; idx++) { ent = &mapper_data->glb_res_tbl[dir][idx]; if (ent->resource_func == - BNXT_ULP_RESOURCE_FUNC_INVALID) + BNXT_ULP_RESOURCE_FUNC_INVALID || + ent->shared) continue; memset(&res, 0, sizeof(struct ulp_flow_db_res_params)); res.resource_func = ent->resource_func; @@ -3673,6 +3812,19 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx) goto error; } + /* + * Only initialize the app global resources if a shared session was + * created. + */ + if (bnxt_ulp_cntxt_shared_session_enabled(ulp_ctx)) { + rc = ulp_mapper_app_glb_resource_info_init(ulp_ctx, data); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to initialize app " + "global resources\n"); + goto error; + } + } + /* Allocate the generic table list */ rc = ulp_mapper_generic_tbl_list_init(data); if (rc) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 9432462404..6e4d9e8522 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -22,6 +22,7 @@ struct bnxt_ulp_mapper_glb_resource_entry { enum bnxt_ulp_resource_func resource_func; uint32_t resource_type; /* TF_ enum type */ uint64_t resource_hndl; + bool shared; }; struct bnxt_ulp_mapper_data { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index a3d8c716f3..3037547179 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -26,8 +26,10 @@ #define BNXT_ULP_ACT_HID_SHFTR 27 #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 11 -#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 10 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 33 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 27 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 219 +#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 2 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 @@ -348,7 +350,8 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 9, BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 10, BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 11, - BNXT_ULP_GLB_RF_IDX_LAST = 12 + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 12, + BNXT_ULP_GLB_RF_IDX_LAST = 13 }; enum bnxt_ulp_hdr_type { @@ -476,6 +479,10 @@ enum bnxt_ulp_template_type { BNXT_ULP_TEMPLATE_TYPE_LAST = 2 }; +enum bnxt_ulp_app_cap { + BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001 +}; + enum bnxt_ulp_fdb_resource_flags { BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00, BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01 diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index dd23635c57..c8ab14a843 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -224,9 +224,244 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { } }; +/* List of device specific parameters */ +struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { + [0] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = 0 + }, + [1] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = 0 + }, +}; + +/* List of device specific parameters */ +struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { + [0] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, + .direction = TF_DIR_RX + }, + [1] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX + }, + [2] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + [3] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + [4] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + [5] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, + .direction = TF_DIR_RX + }, + [6] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX + }, + [7] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + [8] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + [9] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + [10] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + [11] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_TX + }, + [12] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_TX + }, + [13] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_TX + }, + [14] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, + .direction = TF_DIR_RX + }, + [15] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX + }, + [16] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + [17] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + [18] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, + .direction = TF_DIR_RX + }, + [19] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX + }, + [20] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + [21] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + [22] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + [23] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + [24] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_TX + }, + [25] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_TX + }, + [26] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_TX + } +}; + /* List of device specific parameters */ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { [0] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -234,6 +469,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, [1] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -241,6 +477,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, [2] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -248,6 +485,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, [3] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -255,6 +493,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, [4] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -262,6 +501,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, [5] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -269,6 +509,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, [6] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -276,6 +517,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, [7] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -283,6 +525,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, [8] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -290,6 +533,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, [9] = { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -297,11 +541,1944 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, [10] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + [11] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [12] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + [13] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + [14] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [15] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + [16] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [17] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + [18] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + [19] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [20] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + [21] = { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .direction = TF_DIR_TX + }, + [22] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [23] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + [24] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + [25] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [26] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + [27] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [28] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + [29] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + [30] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [31] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + [32] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + } +}; + +/* List of tf resources required to be reserved per app/device */ +struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + [0] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 422 + }, + [1] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + [2] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 192 + }, + [3] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 64 + }, + [4] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + [5] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + [6] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 16384 + }, + [7] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + [8] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 511 + }, + [9] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 63 + }, + [10] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 255 + }, + [11] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [12] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 422 + }, + [13] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + [14] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + [15] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 88 + }, + [16] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13168 + }, + [17] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + [18] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 292 + }, + [19] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 148 + }, + [20] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 192 + }, + [21] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 64 + }, + [22] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + [23] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + [24] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 16384 + }, + [25] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + [26] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 511 + }, + [27] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 223 + }, + [28] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 255 + }, + [29] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 488 + }, + [30] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 511 + }, + [31] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [32] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 292 + }, + [33] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 144 + }, + [34] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + [35] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 928 + }, + [36] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + [37] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + [38] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 26 + }, + [39] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + [40] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + [41] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 32 + }, + [42] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + [43] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 1024 + }, + [44] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 512 + }, + [45] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 14 + }, + [46] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + [47] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + [48] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 64 + }, + [49] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 64 + }, + [50] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 300 + }, + [51] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + [52] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + [53] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 112 + }, + [54] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13200 + }, + [55] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 26 + }, + [56] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 26 + }, + [57] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + [58] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + [59] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + [60] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 1024 + }, + [61] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 512 + }, + [62] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 14 + }, + [63] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + [64] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + [65] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 64 + }, + [66] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 100 + }, + [67] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [68] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 200 + }, + [69] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 110 + }, + [70] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + [71] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + [72] = { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + [73] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 422 + }, + [74] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + [75] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 192 + }, + [76] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 64 + }, + [77] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + [78] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + [79] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 16384 + }, + [80] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + [81] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 511 + }, + [82] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 63 + }, + [83] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 255 + }, + [84] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [85] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 422 + }, + [86] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + [87] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + [88] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 88 + }, + [89] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13168 + }, + [90] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + [91] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 292 + }, + [92] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 148 + }, + [93] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 192 + }, + [94] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 64 + }, + [95] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + [96] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + [97] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 16384 + }, + [98] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + [99] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 511 + }, + [100] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 223 + }, + [101] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 255 + }, + [102] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 488 + }, + [103] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 511 + }, + [104] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [105] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 292 + }, + [106] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 144 + }, + [107] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + [108] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 928 + }, + [109] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + [110] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + [111] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 26 + }, + [112] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + [113] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + [114] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 32 + }, + [115] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + [116] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 1024 + }, + [117] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 512 + }, + [118] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 14 + }, + [119] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + [120] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + [121] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 64 + }, + [122] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 64 + }, + [123] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 300 + }, + [124] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + [125] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + [126] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 112 + }, + [127] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13200 + }, + [128] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 26 + }, + [129] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 26 + }, + [130] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + [131] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + [132] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + [133] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 1024 + }, + [134] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 512 + }, + [135] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 14 + }, + [136] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + [137] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + [138] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 64 + }, + [139] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 100 + }, + [140] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [141] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 200 + }, + [142] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 110 + }, + [143] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + [144] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + [145] = { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + [146] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 422 + }, + [147] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + [148] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 192 + }, + [149] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 64 + }, + [150] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + [151] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + [152] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 16384 + }, + [153] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + [154] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 511 + }, + [155] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 63 + }, + [156] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 255 + }, + [157] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [158] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 422 + }, + [159] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + [160] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + [161] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 88 + }, + [162] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13168 + }, + [163] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + [164] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 292 + }, + [165] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 148 + }, + [166] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 192 + }, + [167] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 64 + }, + [168] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + [169] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + [170] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 16384 + }, + [171] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + [172] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 511 + }, + [173] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 223 + }, + [174] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 255 + }, + [175] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 488 + }, + [176] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 511 + }, + [177] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [178] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 292 + }, + [179] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 144 + }, + [180] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + [181] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 928 + }, + [182] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + [183] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + [184] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 26 + }, + [185] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + [186] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + [187] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 32 + }, + [188] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + [189] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 1024 + }, + [190] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 512 + }, + [191] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 14 + }, + [192] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + [193] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + [194] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 64 + }, + [195] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 64 + }, + [196] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 300 + }, + [197] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + [198] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + [199] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 112 + }, + [200] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13200 + }, + [201] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 26 + }, + [202] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 26 + }, + [203] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + [204] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + [205] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + [206] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 1024 + }, + [207] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 512 + }, + [208] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 14 + }, + [209] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + [210] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + [211] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 64 + }, + [212] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 100 + }, + [213] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + [214] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 200 + }, + [215] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 110 + }, + [216] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + [217] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + [218] = { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index b5bc433810..f5f01c0bcf 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -312,11 +312,27 @@ struct bnxt_ulp_mapper_ident_info { }; struct bnxt_ulp_glb_resource_info { + uint8_t app_id; enum bnxt_ulp_device_id device_id; + enum tf_dir direction; enum bnxt_ulp_resource_func resource_func; uint32_t resource_type; /* TF_ enum type */ enum bnxt_ulp_glb_rf_idx glb_regfile_index; +}; + +struct bnxt_ulp_resource_resv_info { + uint8_t app_id; + enum bnxt_ulp_device_id device_id; enum tf_dir direction; + enum bnxt_ulp_resource_func resource_func; + uint32_t resource_type; /* TF_ enum type */ + uint32_t count; +}; + +struct bnxt_ulp_app_capabilities_info { + uint8_t app_id; + enum bnxt_ulp_device_id device_id; + uint32_t flags; }; struct bnxt_ulp_cache_tbl_params { @@ -361,6 +377,23 @@ extern uint32_t ulp_act_prop_map_table[]; */ extern struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[]; +/* + * The ulp_app_glb_resource_tbl provides the list of shared resources required + * in the event that shared session is enabled. + */ +extern struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[]; + +/* + * The ulp_resource_resv_list provides the list of tf resources required when + * calling tf_open. + */ +extern struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[]; + +/* + * The_app_cap_info_list provides the list of ULP capabilities per app/device. + */ +extern struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[]; + /* * The ulp_cache_tbl_parms table provides the sizes of the cache tables the * mapper must dynamically allocate during initialization. From patchwork Sun May 30 08:59:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93698 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E8BDA0524; Tue, 1 Jun 2021 09:43:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 730D54114B; Tue, 1 Jun 2021 09:40:12 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 32DB141102 for ; Sun, 30 May 2021 11:01:57 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 5BF6A7DC2; Sun, 30 May 2021 02:01:55 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 5BF6A7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365316; bh=gNzjj1FyToeErsA5Fb69Yj8mrNYYfQHTNogvx02Gx4g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V5Go9F/zIaVSyngzo3AtrNYh0Q/wM11YXTv9gV7PGpp5UyRyu/dpmdI469O0MW/oT CdXN5RB+tWq7WAznqqWUjoRTAEx6/gXBeb9uLy4O4ZzD/RoAHo4hN9dbdQk/g7iL5R HEX1KNvJEf8lpUkgu8GKs9MNXI24oVfcDat0KlM8= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:20 +0530 Message-Id: <20210530085929.29695-50-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:54 +0200 Subject: [dpdk-dev] [PATCH 49/58] net/bnxt: add field opcodes in ULP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Add field opcodes that perform logical evaluation of multiple conditions. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 806 +- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 73 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 622 +- .../bnxt/tf_ulp/ulp_template_db_thor_act.c | 196 - .../bnxt/tf_ulp/ulp_template_db_thor_class.c | 6009 ++------------- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 1734 ++--- .../tf_ulp/ulp_template_db_wh_plus_class.c | 6487 +++++++---------- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 5 +- drivers/net/bnxt/tf_ulp/ulp_utils.c | 6 +- drivers/net/bnxt/tf_ulp/ulp_utils.h | 2 +- 10 files changed, 4514 insertions(+), 11426 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 58104eeedf..05e2106c38 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -20,11 +20,18 @@ #include "ulp_template_db_tbl.h" #include "ulp_port_db.h" +static uint8_t mapper_fld_zeros[16] = { 0 }; + static uint8_t mapper_fld_ones[16] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; +static uint8_t mapper_fld_one[16] = { + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 +}; + static const char * ulp_mapper_tmpl_name_str(enum bnxt_ulp_template_type tmpl_type) { @@ -882,7 +889,6 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, static int32_t ulp_mapper_field_port_db_process(struct bnxt_ulp_mapper_parms *parms, - struct bnxt_ulp_mapper_field_info *fld, uint32_t port_id, uint16_t val16, uint8_t **val) @@ -912,332 +918,122 @@ ulp_mapper_field_port_db_process(struct bnxt_ulp_mapper_parms *parms, } break; default: - BNXT_TF_DBG(ERR, "Invalid port_data %s\n", fld->description); - return -EINVAL; - } - return 0; -} - -static int32_t -ulp_mapper_field_process_inc_dec(struct bnxt_ulp_mapper_field_info *fld, - struct ulp_blob *blob, - uint64_t *val64, - uint16_t const_val16, - uint32_t bitlen, - uint32_t *update_flag) -{ - uint64_t l_val64 = *val64; - - if (fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST || - fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST) { - l_val64 += const_val16; - l_val64 = tfp_be_to_cpu_64(l_val64); - ulp_blob_push_64(blob, &l_val64, bitlen); - } else if (fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST || - fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST_POST) { - l_val64 -= const_val16; - l_val64 = tfp_be_to_cpu_64(l_val64); - ulp_blob_push_64(blob, &l_val64, bitlen); - } else { - BNXT_TF_DBG(ERR, "Invalid field opcode %u\n", fld->field_opc); + BNXT_TF_DBG(ERR, "Invalid port_data %d\n", port_data); return -EINVAL; } - - if (fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST_POST || - fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST) { - *val64 = l_val64; - *update_flag = 1; - } return 0; } static int32_t -ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, - enum tf_dir dir, - struct bnxt_ulp_mapper_field_info *fld, - struct ulp_blob *blob, - uint8_t is_key, - const char *name) +ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms, + enum bnxt_ulp_field_src field_src, + uint8_t *field_opr, + enum tf_dir dir, + uint8_t is_key, + uint32_t bitlen, + uint8_t **val, + uint32_t *val_len, + uint64_t *value) { - uint32_t val_size = 0, field_size = 0; - uint64_t hdr_bit, act_bit, regval; - uint16_t write_idx = blob->write_idx; - uint16_t idx, size_idx, bitlen, offset; - uint8_t *val = NULL; - uint8_t tmpval[16]; + struct bnxt_ulp_mapper_data *m; uint8_t bit; - uint32_t src1_sel = 0; - enum bnxt_ulp_field_src fld_src; - uint8_t *fld_src_oper; - enum bnxt_ulp_field_cond_src field_cond_src; - uint16_t const_val = 0; - uint32_t update_flag = 0; - uint64_t src1_val64; - uint32_t port_id; + uint32_t port_id, val_size, field_size; + uint16_t idx, size_idx, offset; + uint32_t bytelen = ULP_BITS_2_BYTE(bitlen); + uint8_t *buffer; + uint64_t lregval; bool shared; - /* process the field opcode */ - if (fld->field_opc != BNXT_ULP_FIELD_OPC_COND_OP) { - field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE; - /* Read the constant from the second operand */ - memcpy(&const_val, fld->field_opr2, sizeof(uint16_t)); - const_val = tfp_be_to_cpu_16(const_val); - } else { - field_cond_src = fld->field_cond_src; - } - - bitlen = fld->field_bit_size; - /* Evaluate the condition */ - switch (field_cond_src) { - case BNXT_ULP_FIELD_COND_SRC_TRUE: - src1_sel = 1; - break; - case BNXT_ULP_FIELD_COND_SRC_CF: - if (!ulp_operand_read(fld->field_cond_opr, - (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - if (idx >= BNXT_ULP_CF_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s invalid index %u\n", name, idx); - return -EINVAL; - } - /* check if the computed field is set */ - if (ULP_COMP_FLD_IDX_RD(parms, idx)) - src1_sel = 1; - break; - case BNXT_ULP_FIELD_COND_SRC_RF: - if (!ulp_operand_read(fld->field_cond_opr, - (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - - idx = tfp_be_to_cpu_16(idx); - /* Uninitialized regfile entries return 0 */ - if (!ulp_regfile_read(parms->regfile, idx, ®val)) { - BNXT_TF_DBG(ERR, "%s regfile[%d] read oob\n", - name, idx); - return -EINVAL; - } - if (regval) - src1_sel = 1; - break; - case BNXT_ULP_FIELD_COND_SRC_ACT_BIT: - if (!ulp_operand_read(fld->field_cond_opr, - (uint8_t *)&act_bit, sizeof(uint64_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - act_bit = tfp_be_to_cpu_64(act_bit); - if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) - src1_sel = 1; - break; - case BNXT_ULP_FIELD_COND_SRC_HDR_BIT: - if (!ulp_operand_read(fld->field_cond_opr, - (uint8_t *)&hdr_bit, sizeof(uint64_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - hdr_bit = tfp_be_to_cpu_64(hdr_bit); - if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) - src1_sel = 1; - break; - case BNXT_ULP_FIELD_COND_SRC_FIELD_BIT: - if (!ulp_operand_read(fld->field_cond_opr, (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); - return -EINVAL; - } - idx = tfp_be_to_cpu_16(idx); - /* get the index from the global field list */ - if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) { - BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", - idx); - return -EINVAL; - } - if (bit && (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit))) - src1_sel = 1; - break; - default: - BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n", - name, fld->field_cond_src, write_idx); - return -EINVAL; - } - - /* pick the selected source */ - if (src1_sel) { - fld_src = fld->field_src1; - fld_src_oper = fld->field_opr1; - } else { - fld_src = fld->field_src2; - fld_src_oper = fld->field_opr2; - } - + *val_len = bitlen; + *value = 0; /* Perform the action */ - switch (fld_src) { + switch (field_src) { case BNXT_ULP_FIELD_SRC_ZERO: - if (ulp_blob_pad_push(blob, bitlen) < 0) { - BNXT_TF_DBG(ERR, "%s too large for blob\n", name); - return -EINVAL; - } + *val = mapper_fld_zeros; break; case BNXT_ULP_FIELD_SRC_CONST: - val = fld_src_oper; - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); - return -EINVAL; - } + *val = field_opr; break; case BNXT_ULP_FIELD_SRC_ONES: - val = mapper_fld_ones; - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s too large for blob\n", name); - return -EINVAL; - } + *val = mapper_fld_ones; + *value = 1; break; case BNXT_ULP_FIELD_SRC_CF: - if (!ulp_operand_read(fld_src_oper, + if (!ulp_operand_read(field_opr, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed.\n", - name); + BNXT_TF_DBG(ERR, "CF operand read failed\n"); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); - if (idx >= BNXT_ULP_CF_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s comp field [%d] read oob\n", - name, idx); + if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) { + BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx, + bytelen); return -EINVAL; } - if (fld->field_opc == BNXT_ULP_FIELD_OPC_COND_OP) { - val = ulp_blob_push_32(blob, &parms->comp_fld[idx], - bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", - name); - return -EINVAL; - } - } else if (fld->field_opc == BNXT_ULP_FIELD_OPC_PORT_TABLE) { - port_id = ULP_COMP_FLD_IDX_RD(parms, idx); - if (ulp_mapper_field_port_db_process(parms, fld, - port_id, const_val, - &val)) { - BNXT_TF_DBG(ERR, "%s field port table failed\n", - name); - return -EINVAL; - } - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", - name); - return -EINVAL; - } - } else { - src1_val64 = ULP_COMP_FLD_IDX_RD(parms, idx); - if (ulp_mapper_field_process_inc_dec(fld, blob, - &src1_val64, - const_val, - bitlen, - &update_flag)) { - BNXT_TF_DBG(ERR, "%s field cond opc failed\n", - name); - return -EINVAL; - } - if (update_flag) { - BNXT_TF_DBG(ERR, "%s invalid field cond opc\n", - name); - return -EINVAL; - } - } + buffer = (uint8_t *)&parms->comp_fld[idx]; + *val = &buffer[sizeof(uint32_t) - bytelen]; + *value = ULP_COMP_FLD_IDX_RD(parms, idx); break; case BNXT_ULP_FIELD_SRC_RF: - if (!ulp_operand_read(fld_src_oper, + if (!ulp_operand_read(field_opr, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + BNXT_TF_DBG(ERR, "RF operand read failed\n"); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); /* Uninitialized regfile entries return 0 */ - if (!ulp_regfile_read(parms->regfile, idx, ®val)) { - BNXT_TF_DBG(ERR, "%s regfile[%d] read oob\n", - name, idx); + if (!ulp_regfile_read(parms->regfile, idx, &lregval) || + sizeof(uint64_t) < bytelen) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob %u\n", idx, + bytelen); return -EINVAL; } - if (fld->field_opc == BNXT_ULP_FIELD_OPC_COND_OP) { - val = ulp_blob_push_64(blob, ®val, bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", - name); - return -EINVAL; - } - } else { - if (ulp_mapper_field_process_inc_dec(fld, blob, - ®val, - const_val, - bitlen, - &update_flag)) { - BNXT_TF_DBG(ERR, "%s field cond opc failed\n", - name); - return -EINVAL; - } - if (update_flag) { - regval = tfp_cpu_to_be_64(regval); - if (ulp_regfile_write(parms->regfile, idx, - regval)) { - BNXT_TF_DBG(ERR, - "Write regfile[%d] fail\n", - idx); - return -EINVAL; - } - } - } + buffer = (uint8_t *)&parms->regfile->entry[idx].data; + *val = &buffer[sizeof(uint64_t) - bytelen]; + *value = tfp_be_to_cpu_64(lregval); break; case BNXT_ULP_FIELD_SRC_ACT_PROP: - if (!ulp_operand_read(fld_src_oper, + if (!ulp_operand_read(field_opr, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + BNXT_TF_DBG(ERR, "Action operand read failed\n"); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); - if (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s act_prop[%d] oob\n", name, idx); + BNXT_TF_DBG(ERR, "act_prop[%d] oob\n", idx); return -EINVAL; } - val = &parms->act_prop->act_details[idx]; + buffer = &parms->act_prop->act_details[idx]; field_size = ulp_mapper_act_prop_size_get(idx); - if (bitlen < ULP_BYTE_2_BITS(field_size)) { - field_size = field_size - ((bitlen + 7) / 8); - val += field_size; - } - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + if (bytelen > field_size) { + BNXT_TF_DBG(ERR, "act_prop[%d] field size small %u\n", + idx, field_size); return -EINVAL; } + *val = &buffer[field_size - bytelen]; break; case BNXT_ULP_FIELD_SRC_ACT_PROP_SZ: - if (!ulp_operand_read(fld_src_oper, + if (!ulp_operand_read(field_opr, (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + BNXT_TF_DBG(ERR, "Action sz operand read failed\n"); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); if (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { - BNXT_TF_DBG(ERR, "%s act_prop[%d] oob\n", name, idx); + BNXT_TF_DBG(ERR, "act_prop_sz[%d] oob\n", idx); return -EINVAL; } - val = &parms->act_prop->act_details[idx]; + *val = &parms->act_prop->act_details[idx]; /* get the size index next */ - if (!ulp_operand_read(&fld_src_oper[sizeof(uint16_t)], + if (!ulp_operand_read(&field_opr[sizeof(uint16_t)], (uint8_t *)&size_idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + BNXT_TF_DBG(ERR, "Action sz operand read failed\n"); return -EINVAL; } size_idx = tfp_be_to_cpu_16(size_idx); - if (size_idx >= BNXT_ULP_ACT_PROP_IDX_LAST) { BNXT_TF_DBG(ERR, "act_prop[%d] oob\n", size_idx); return -EINVAL; @@ -1245,51 +1041,32 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, memcpy(&val_size, &parms->act_prop->act_details[size_idx], sizeof(uint32_t)); val_size = tfp_be_to_cpu_32(val_size); - val_size = ULP_BYTE_2_BITS(val_size); - ulp_blob_push_encap(blob, val, val_size); + *val_len = ULP_BYTE_2_BITS(val_size); break; case BNXT_ULP_FIELD_SRC_GLB_RF: - if (!ulp_operand_read(fld_src_oper, - (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); + if (!ulp_operand_read(field_opr, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "Global regfile read failed\n"); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); - if (ulp_mapper_glb_resource_read(parms->mapper_data, dir, - idx, ®val, &shared)) { - BNXT_TF_DBG(ERR, "%s global regfile[%d] read failed.\n", - name, idx); + if (ulp_mapper_glb_resource_read(parms->mapper_data, + dir, idx, &lregval, &shared) || + sizeof(uint64_t) < bytelen) { + BNXT_TF_DBG(ERR, "Global regfile[%d] read failed %u\n", + idx, bytelen); return -EINVAL; } - if (fld->field_opc == BNXT_ULP_FIELD_OPC_COND_OP) { - val = ulp_blob_push_64(blob, ®val, bitlen); - if (!val) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", - name); - return -EINVAL; - } - } else { - if (ulp_mapper_field_process_inc_dec(fld, blob, - ®val, - const_val, - bitlen, - &update_flag)) { - BNXT_TF_DBG(ERR, "%s field cond opc failed\n", - name); - return -EINVAL; - } - if (update_flag) { - BNXT_TF_DBG(ERR, "%s invalid field cond opc\n", - name); - return -EINVAL; - } - } + m = parms->mapper_data; + buffer = (uint8_t *)&m->glb_res_tbl[dir][idx].resource_hndl; + *val = &buffer[sizeof(uint64_t) - bytelen]; + *value = tfp_be_to_cpu_64(lregval); break; case BNXT_ULP_FIELD_SRC_HF: - if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); + case BNXT_ULP_FIELD_SRC_SUB_HF: + if (!ulp_operand_read(field_opr, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "Header field read failed\n"); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); @@ -1300,69 +1077,67 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } if (is_key) - val = parms->hdr_field[bit].spec; + buffer = parms->hdr_field[bit].spec; else - val = parms->hdr_field[bit].mask; + buffer = parms->hdr_field[bit].mask; - /* - * Need to account for how much data was pushed to the header - * field vs how much is to be inserted in the key/mask. - */ field_size = parms->hdr_field[bit].size; - if (bitlen < ULP_BYTE_2_BITS(field_size)) { - field_size = field_size - ((bitlen + 7) / 8); - val += field_size; - } - - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + if (bytelen > field_size) { + BNXT_TF_DBG(ERR, "Hdr field[%d] size small %u\n", + bit, field_size); return -EINVAL; } + if (field_src == BNXT_ULP_FIELD_SRC_HF) { + *val = &buffer[field_size - bytelen]; + } else { + /* get the offset next */ + if (!ulp_operand_read(&field_opr[sizeof(uint16_t)], + (uint8_t *)&offset, + sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "Hdr fld size read failed\n"); + return -EINVAL; + } + offset = tfp_be_to_cpu_16(offset); + offset = ULP_BITS_2_BYTE_NR(offset); + if ((offset + bytelen) > field_size) { + BNXT_TF_DBG(ERR, "Hdr field[%d] oob\n", bit); + return -EINVAL; + } + *val = &buffer[offset]; + } break; case BNXT_ULP_FIELD_SRC_HDR_BIT: - if (!ulp_operand_read(fld_src_oper, - (uint8_t *)&hdr_bit, sizeof(uint64_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - hdr_bit = tfp_be_to_cpu_64(hdr_bit); - memset(tmpval, 0, sizeof(tmpval)); - if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) - tmpval[0] = 1; - if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) { - BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); + if (!ulp_operand_read(field_opr, + (uint8_t *)&lregval, sizeof(uint64_t))) { + BNXT_TF_DBG(ERR, "Header bit read failed\n"); return -EINVAL; } - if (!ulp_blob_push(blob, tmpval, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); - return -EINVAL; + lregval = tfp_be_to_cpu_64(lregval); + if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, lregval)) { + *val = mapper_fld_one; + *value = 1; + } else { + *val = mapper_fld_zeros; } - val = tmpval; break; case BNXT_ULP_FIELD_SRC_ACT_BIT: - if (!ulp_operand_read(fld_src_oper, - (uint8_t *)&act_bit, sizeof(uint64_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); - return -EINVAL; - } - act_bit = tfp_be_to_cpu_64(act_bit); - memset(tmpval, 0, sizeof(tmpval)); - if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) - tmpval[0] = 1; - if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) { - BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); + if (!ulp_operand_read(field_opr, + (uint8_t *)&lregval, sizeof(uint64_t))) { + BNXT_TF_DBG(ERR, "Action bit read failed\n"); return -EINVAL; } - if (!ulp_blob_push(blob, tmpval, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); - return -EINVAL; + lregval = tfp_be_to_cpu_64(lregval); + if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, lregval)) { + *val = mapper_fld_one; + *value = 1; + } else { + *val = mapper_fld_zeros; } - val = tmpval; break; case BNXT_ULP_FIELD_SRC_FIELD_BIT: - if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx, - sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed.\n", name); + if (!ulp_operand_read(field_opr, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "Field bit read failed\n"); return -EINVAL; } idx = tfp_be_to_cpu_16(idx); @@ -1372,70 +1147,294 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, idx); return -EINVAL; } - memset(tmpval, 0, sizeof(tmpval)); - if (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit)) - tmpval[0] = 1; - if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) { - BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name); + if (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit)) { + *val = mapper_fld_one; + *value = 1; + } else { + *val = mapper_fld_zeros; + } + break; + case BNXT_ULP_FIELD_SRC_PORT_TABLE: + /* The port id is present in the comp field list */ + port_id = ULP_COMP_FLD_IDX_RD(parms, + BNXT_ULP_CF_IDX_DEV_PORT_ID); + /* get the port table enum */ + if (!ulp_operand_read(field_opr, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "Port table enum read failed\n"); return -EINVAL; } - if (!ulp_blob_push(blob, tmpval, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + idx = tfp_be_to_cpu_16(idx); + if (ulp_mapper_field_port_db_process(parms, port_id, idx, + val)) { + BNXT_TF_DBG(ERR, "field port table failed\n"); return -EINVAL; } - val = tmpval; - break; case BNXT_ULP_FIELD_SRC_SKIP: /* do nothing */ break; case BNXT_ULP_FIELD_SRC_REJECT: return -EINVAL; - case BNXT_ULP_FIELD_SRC_SUB_HF: - if (!ulp_operand_read(fld_src_oper, - (uint8_t *)&idx, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + default: + BNXT_TF_DBG(ERR, "invalid field opcode 0x%x\n", field_src); + return -EINVAL; + } + return 0; +} + +static int32_t ulp_mapper_field_buffer_eval(uint8_t *buffer, uint32_t bitlen, + uint64_t *output) +{ + uint16_t val_16; + uint32_t val_32; + uint64_t val_64; + uint32_t bytelen; + + bytelen = ULP_BITS_2_BYTE(bitlen); + if (bytelen == sizeof(uint8_t)) { + *output = *((uint8_t *)buffer); + } else if (bytelen == sizeof(uint16_t)) { + val_16 = *((uint16_t *)buffer); + *output = tfp_be_to_cpu_16(val_16); + } else if (bytelen == sizeof(uint32_t)) { + val_32 = *((uint32_t *)buffer); + *output = tfp_be_to_cpu_32(val_32); + } else if (bytelen == sizeof(val_64)) { + val_64 = *((uint64_t *)buffer); + *output = tfp_be_to_cpu_64(val_64); + } else { + *output = 0; + return -EINVAL; + } + return 0; +} + +static int32_t ulp_mapper_field_blob_write(enum bnxt_ulp_field_src fld_src, + struct ulp_blob *blob, + uint8_t *val, + uint32_t val_len, + uint8_t **out_val) +{ + if (fld_src == BNXT_ULP_FIELD_SRC_ZERO) { + if (ulp_blob_pad_push(blob, val_len) < 0) { + BNXT_TF_DBG(ERR, "too large for blob\n"); return -EINVAL; } - idx = tfp_be_to_cpu_16(idx); - /* get the index from the global field list */ - if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) { - BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", - idx); + } else if (fld_src == BNXT_ULP_FIELD_SRC_ACT_PROP_SZ) { + if (ulp_blob_push_encap(blob, val, val_len) < 0) { + BNXT_TF_DBG(ERR, "encap blob push failed\n"); return -EINVAL; } - - /* get the offset next */ - if (!ulp_operand_read(&fld_src_oper[sizeof(uint16_t)], - (uint8_t *)&offset, sizeof(uint16_t))) { - BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + } else { + if (!ulp_blob_push(blob, val, val_len)) { + BNXT_TF_DBG(ERR, "push of val1 failed\n"); return -EINVAL; } - offset = tfp_be_to_cpu_16(offset); - if ((offset + bitlen) > - ULP_BYTE_2_BITS(parms->hdr_field[bit].size) || - ULP_BITS_IS_BYTE_NOT_ALIGNED(offset)) { - BNXT_TF_DBG(ERR, "Hdr field[%s] oob\n", name); - return -EINVAL; + } + *out_val = val; + return 0; +} + +static int32_t +ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms, + enum tf_dir dir, + struct bnxt_ulp_mapper_field_info *fld, + struct ulp_blob *blob, + uint8_t is_key, + const char *name) +{ + uint16_t write_idx = blob->write_idx; + uint8_t *val = NULL, *val1, *val2, *val3; + uint32_t val_len = 0, val1_len = 0, val2_len = 0, val3_len = 0; + uint8_t process_src1 = 0, process_src2 = 0, process_src3 = 0; + uint8_t eval_src1 = 0, eval_src2 = 0, eval_src3 = 0; + uint64_t val_int = 0, val1_int = 0, val2_int = 0, val3_int = 0; + uint64_t value1 = 0, value2 = 0, value3 = 0; + int32_t rc = 0; + + /* prepare the field source and values */ + switch (fld->field_opc) { + case BNXT_ULP_FIELD_OPC_SRC1: + process_src1 = 1; + break; + case BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3: + process_src1 = 1; + break; + case BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2_OR_SRC3: + case BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3: + process_src3 = 1; + eval_src3 = 1; + process_src1 = 1; + process_src2 = 1; + eval_src1 = 1; + eval_src2 = 1; + break; + case BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2: + case BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2: + case BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST: + case BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2_POST: + case BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2: + case BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2: + process_src1 = 1; + process_src2 = 1; + eval_src1 = 1; + eval_src2 = 1; + break; + default: + break; + } + + /* process the src1 opcode */ + if (process_src1) { + if (ulp_mapper_field_src_process(parms, fld->field_src1, + fld->field_opr1, dir, is_key, + fld->field_bit_size, &val1, + &val1_len, &value1)) { + BNXT_TF_DBG(ERR, "fld src1 process failed\n"); + goto error; + } + if (eval_src1) { + if (ulp_mapper_field_buffer_eval(val1, val1_len, + &val1_int)) { + BNXT_TF_DBG(ERR, "fld src1 eval failed\n"); + goto error; + } } - offset = ULP_BITS_2_BYTE_NR(offset); + } - /* write the value into blob */ - if (is_key) - val = &parms->hdr_field[bit].spec[offset]; + /* for "if then clause" set the correct process */ + if (fld->field_opc == BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3) { + if (value1) + process_src2 = 1; else - val = &parms->hdr_field[bit].mask[offset]; + process_src3 = 1; + } - if (!ulp_blob_push(blob, val, bitlen)) { - BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); - return -EINVAL; + /* process src2 opcode */ + if (process_src2) { + if (ulp_mapper_field_src_process(parms, fld->field_src2, + fld->field_opr2, dir, is_key, + fld->field_bit_size, &val2, + &val2_len, &value2)) { + BNXT_TF_DBG(ERR, "fld src2 process failed\n"); + goto error; + } + if (eval_src2) { + if (ulp_mapper_field_buffer_eval(val2, val2_len, + &val2_int)) { + BNXT_TF_DBG(ERR, "fld src2 eval failed\n"); + goto error; + } + } + } + + /* process src3 opcode */ + if (process_src3) { + if (ulp_mapper_field_src_process(parms, fld->field_src3, + fld->field_opr3, dir, is_key, + fld->field_bit_size, &val3, + &val3_len, &value3)) { + BNXT_TF_DBG(ERR, "fld src3 process failed\n"); + goto error; + } + if (eval_src3) { + if (ulp_mapper_field_buffer_eval(val3, val3_len, + &val3_int)) { + BNXT_TF_DBG(ERR, "fld src3 eval failed\n"); + goto error; + } + } + } + + val_len = fld->field_bit_size; + /* process the field opcodes */ + switch (fld->field_opc) { + case BNXT_ULP_FIELD_OPC_SRC1: + if (ulp_mapper_field_blob_write(fld->field_src1, + blob, val1, val1_len, &val)) + goto error; + val_len = val1_len; + break; + case BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3: + if (value1) { + if (ulp_mapper_field_blob_write(fld->field_src2, blob, + val2, val2_len, &val)) + goto error; + val_len = val2_len; + } else { + if (ulp_mapper_field_blob_write(fld->field_src3, blob, + val3, val3_len, &val)) + goto error; + val_len = val3_len; } break; + case BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2: + case BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST: + val_int = val1_int + val2_int; + val_int = tfp_cpu_to_be_64(val_int); + val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); + if (!val) { + BNXT_TF_DBG(ERR, "push to blob failed\n"); + goto error; + } + break; + case BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2: + case BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2_POST: + val_int = val1_int - val2_int; + val_int = tfp_cpu_to_be_64(val_int); + val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); + if (!val) { + BNXT_TF_DBG(ERR, "push to blob failed\n"); + goto error; + } + break; + case BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2: + val_int = val1_int | val2_int; + val_int = tfp_cpu_to_be_64(val_int); + val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); + if (!val) { + BNXT_TF_DBG(ERR, "push to blob failed\n"); + goto error; + } + break; + case BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2_OR_SRC3: + val_int = val1_int | val2_int | val3_int; + val_int = tfp_cpu_to_be_64(val_int); + val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); + if (!val) { + BNXT_TF_DBG(ERR, "push to blob failed\n"); + goto error; + } + break; + case BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2: + val_int = val1_int & val2_int; + val_int = tfp_cpu_to_be_64(val_int); + val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); + if (!val) { + BNXT_TF_DBG(ERR, "push to blob failed\n"); + goto error; + } + break; + case BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3: + val_int = val1_int & (val2_int | val3_int); + val_int = tfp_cpu_to_be_64(val_int); + val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); + if (!val) { + BNXT_TF_DBG(ERR, "push to blob failed\n"); + goto error; + } + break; + case BNXT_ULP_FIELD_OPC_SKIP: + break; default: - BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n", - name, fld_src, write_idx); - return -EINVAL; + break; } - return 0; + + return rc; +error: + BNXT_TF_DBG(ERR, "Error in %s:%s process %u:%u\n", name, + fld->description, (val) ? write_idx : 0, val_len); + return -EINVAL; } /* @@ -1474,8 +1473,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms, ulp_blob_encap_swap_idx_set(data); /* Process the result fields */ - rc = ulp_mapper_field_process(parms, tbl->direction, - &dflds[i], data, 0, name); + rc = ulp_mapper_field_opc_process(parms, tbl->direction, + &dflds[i], data, 0, name); if (rc) { BNXT_TF_DBG(ERR, "data field failed\n"); return rc; @@ -1877,9 +1876,9 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, */ for (i = 0; i < num_kflds; i++) { /* Setup the key */ - rc = ulp_mapper_field_process(parms, tbl->direction, - &kflds[i].field_info_spec, - key, 1, "TCAM Key"); + rc = ulp_mapper_field_opc_process(parms, tbl->direction, + &kflds[i].field_info_spec, + key, 1, "TCAM Key"); if (rc) { BNXT_TF_DBG(ERR, "Key field set failed %s\n", kflds[i].field_info_spec.description); @@ -1887,9 +1886,9 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, } /* Setup the mask */ - rc = ulp_mapper_field_process(parms, tbl->direction, - &kflds[i].field_info_mask, - mask, 0, "TCAM Mask"); + rc = ulp_mapper_field_opc_process(parms, tbl->direction, + &kflds[i].field_info_mask, + mask, 0, "TCAM Mask"); if (rc) { BNXT_TF_DBG(ERR, "Mask field set failed %s\n", kflds[i].field_info_mask.description); @@ -2077,9 +2076,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* create the key */ for (i = 0; i < num_kflds; i++) { /* Setup the key */ - rc = ulp_mapper_field_process(parms, tbl->direction, - &kflds[i].field_info_spec, - &key, 1, "EM Key"); + rc = ulp_mapper_field_opc_process(parms, tbl->direction, + &kflds[i].field_info_spec, + &key, 1, "EM Key"); if (rc) { BNXT_TF_DBG(ERR, "Key field set failed.\n"); return rc; @@ -2645,9 +2644,9 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, } for (i = 0; i < num_kflds; i++) { /* Setup the key */ - rc = ulp_mapper_field_process(parms, tbl->direction, - &kflds[i].field_info_spec, - &key, 1, "Gen Tbl Key"); + rc = ulp_mapper_field_opc_process(parms, tbl->direction, + &kflds[i].field_info_spec, + &key, 1, "Gen Tbl Key"); if (rc) { BNXT_TF_DBG(ERR, "Failed to create key for Gen tbl rc=%d\n", @@ -3159,6 +3158,9 @@ ulp_mapper_cc_upd_opr_compute(struct bnxt_ulp_mapper_parms *parms, } *result = tfp_be_to_cpu_64(regval); break; + case BNXT_ULP_CC_UPD_SRC_CONST: + *result = cc_opr; + break; default: BNXT_TF_DBG(ERR, "invalid src code %u\n", cc_src); return -EINVAL; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 3037547179..0058908c70 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,12 +3,12 @@ * All rights reserved. */ -/* date: Tue Mar 9 19:13:26 2021 */ +/* date: Sun Mar 14 12:41:59 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 38 +#define BNXT_ULP_REGFILE_MAX_SZ 40 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 #define BNXT_ULP_GEN_TBL_MAX_SZ 10 @@ -29,7 +29,7 @@ #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 33 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 27 #define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 219 -#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 2 +#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 @@ -37,16 +37,16 @@ #define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595 #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5 #define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 484 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495 #define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 550 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 41 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43 #define ULP_THOR_CLASS_TMPL_LIST_SIZE 5 -#define ULP_THOR_CLASS_TBL_LIST_SIZE 26 -#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 90 -#define ULP_THOR_CLASS_IDENT_LIST_SIZE 3 -#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 138 -#define ULP_THOR_CLASS_COND_LIST_SIZE 6 +#define ULP_THOR_CLASS_TBL_LIST_SIZE 13 +#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 0 +#define ULP_THOR_CLASS_IDENT_LIST_SIZE 0 +#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 102 +#define ULP_THOR_CLASS_COND_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 @@ -148,7 +148,8 @@ enum bnxt_ulp_cc_upd_src { BNXT_ULP_CC_UPD_SRC_REGFILE = 0, BNXT_ULP_CC_UPD_SRC_GLB_REGFILE = 1, BNXT_ULP_CC_UPD_SRC_COMP_FIELD = 2, - BNXT_ULP_CC_UPD_SRC_LAST = 3 + BNXT_ULP_CC_UPD_SRC_CONST = 3, + BNXT_ULP_CC_UPD_SRC_LAST = 4 }; enum bnxt_ulp_cf_idx { @@ -283,26 +284,19 @@ enum bnxt_ulp_fdb_type { BNXT_ULP_FDB_TYPE_LAST = 3 }; -enum bnxt_ulp_field_cond_src { - BNXT_ULP_FIELD_COND_SRC_TRUE = 0, - BNXT_ULP_FIELD_COND_SRC_CF = 1, - BNXT_ULP_FIELD_COND_SRC_RF = 2, - BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3, - BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4, - BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5, - BNXT_ULP_FIELD_COND_SRC_FLOW_PAT_MATCH = 6, - BNXT_ULP_FIELD_COND_SRC_ACT_PAT_MATCH = 7, - BNXT_ULP_FIELD_COND_SRC_LAST = 8 -}; - enum bnxt_ulp_field_opc { - BNXT_ULP_FIELD_OPC_COND_OP = 0, - BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST = 1, - BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST = 2, - BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST = 3, - BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST_POST = 4, - BNXT_ULP_FIELD_OPC_PORT_TABLE = 5, - BNXT_ULP_FIELD_OPC_LAST = 6 + BNXT_ULP_FIELD_OPC_SRC1 = 0, + BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3 = 1, + BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2 = 2, + BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2 = 3, + BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST = 4, + BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2_POST = 5, + BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2 = 6, + BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2_OR_SRC3 = 7, + BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2 = 8, + BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3 = 9, + BNXT_ULP_FIELD_OPC_SKIP = 10, + BNXT_ULP_FIELD_OPC_LAST = 11 }; enum bnxt_ulp_field_src { @@ -321,7 +315,8 @@ enum bnxt_ulp_field_src { BNXT_ULP_FIELD_SRC_FIELD_BIT = 12, BNXT_ULP_FIELD_SRC_SKIP = 13, BNXT_ULP_FIELD_SRC_REJECT = 14, - BNXT_ULP_FIELD_SRC_LAST = 15 + BNXT_ULP_FIELD_SRC_PORT_TABLE = 15, + BNXT_ULP_FIELD_SRC_LAST = 16 }; enum bnxt_ulp_generic_tbl_lkup_type { @@ -346,11 +341,11 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 6, BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 7, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 8, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 9, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 10, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 11, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 12, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 8, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 9, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 10, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 11, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 12, BNXT_ULP_GLB_RF_IDX_LAST = 13 }; @@ -461,7 +456,9 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC = 35, BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR = 36, BNXT_ULP_RF_IDX_CC = 37, - BNXT_ULP_RF_IDX_LAST = 38 + BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 38, + BNXT_ULP_RF_IDX_PHY_PORT_VPORT = 39, + BNXT_ULP_RF_IDX_LAST = 40 }; enum bnxt_ulp_tcam_tbl_opc { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index c8ab14a843..67bb8b116b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Mar 8 17:37:39 2021 */ +/* date: Mon Mar 15 10:26:20 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -56,7 +56,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { BNXT_ULP_DIRECTION_INGRESS] = { .name = "INGRESS GENERIC_TABLE_SHARED_MIRROR", .result_num_entries = 16, - .result_num_bytes = 16, + .result_num_bytes = 8, .key_num_bytes = 0, .num_buckets = 0, .hash_tbl_entries = 0, @@ -66,7 +66,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { BNXT_ULP_DIRECTION_EGRESS] = { .name = "EGRESS GENERIC_TABLE_SHARED_MIRROR", .result_num_entries = 16, - .result_num_bytes = 16, + .result_num_bytes = 8, .key_num_bytes = 0, .num_buckets = 0, .hash_tbl_entries = 0, @@ -77,7 +77,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE", .result_num_entries = 256, .result_num_bytes = 8, - .key_num_bytes = 7, + .key_num_bytes = 9, .num_buckets = 8, .hash_tbl_entries = 1024, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -87,7 +87,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE", .result_num_entries = 256, .result_num_bytes = 8, - .key_num_bytes = 7, + .key_num_bytes = 9, .num_buckets = 8, .hash_tbl_entries = 1024, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -96,7 +96,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { BNXT_ULP_DIRECTION_INGRESS] = { .name = "INGRESS GENERIC_TABLE_PORT_TABLE", .result_num_entries = 1024, - .result_num_bytes = 18, + .result_num_bytes = 19, .key_num_bytes = 0, .num_buckets = 0, .hash_tbl_entries = 0, @@ -106,7 +106,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { BNXT_ULP_DIRECTION_EGRESS] = { .name = "EGRESS GENERIC_TABLE_PORT_TABLE", .result_num_entries = 1024, - .result_num_bytes = 18, + .result_num_bytes = 19, .key_num_bytes = 0, .num_buckets = 0, .hash_tbl_entries = 0, @@ -217,30 +217,62 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { .em_key_align_bytes = 80, .wc_slice_width = 160, .wc_max_slices = 4, - .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f}, + .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f}, .wc_mod_list_max_size = 4, .wc_ctl_size_bits = 32, .dev_tbls = ulp_template_thor_tbls } }; +/* Provides act_bitmask */ +struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = { + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .act_bitmask = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .act_bitmask = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + } +}; + /* List of device specific parameters */ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { - [0] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .flags = 0 }, - [1] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = 0 }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN + } }; /* List of device specific parameters */ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { - [0] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -248,7 +280,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, - [1] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -256,7 +288,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, - [2] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -264,7 +296,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, - [3] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -272,7 +304,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX }, - [4] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -280,7 +312,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, - [5] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -288,7 +320,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, - [6] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -296,7 +328,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, - [7] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -304,7 +336,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX }, - [8] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -312,7 +344,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, - [9] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -320,7 +352,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, .direction = TF_DIR_RX }, - [10] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -328,7 +360,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, .direction = TF_DIR_RX }, - [11] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -336,7 +368,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, .direction = TF_DIR_TX }, - [12] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -344,7 +376,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_TX }, - [13] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -352,7 +384,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_TX }, - [14] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -360,7 +392,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, - [15] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -368,7 +400,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, - [16] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -376,7 +408,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX }, - [17] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -384,7 +416,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, - [18] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -392,7 +424,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, - [19] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -400,7 +432,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, - [20] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -408,7 +440,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX }, - [21] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -416,7 +448,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, - [22] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -424,7 +456,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, .direction = TF_DIR_RX }, - [23] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -432,7 +464,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, .direction = TF_DIR_RX }, - [24] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -440,7 +472,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, .direction = TF_DIR_TX }, - [25] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -448,7 +480,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_TX }, - [26] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -460,7 +492,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { /* List of device specific parameters */ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { - [0] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -468,7 +500,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [1] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -476,7 +508,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [2] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -484,7 +516,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .direction = TF_DIR_TX }, - [3] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -492,7 +524,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [4] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -500,7 +532,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [5] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -508,7 +540,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [6] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -516,7 +548,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_RX }, - [7] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -524,7 +556,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_TX }, - [8] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -532,7 +564,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [9] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -540,7 +572,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [10] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -548,7 +580,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .direction = TF_DIR_TX }, - [11] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -556,7 +588,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [12] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -564,7 +596,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [13] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -572,7 +604,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .direction = TF_DIR_TX }, - [14] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -580,7 +612,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [15] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -588,7 +620,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [16] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -596,7 +628,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [17] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -604,7 +636,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_RX }, - [18] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -612,7 +644,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_TX }, - [19] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -620,7 +652,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [20] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -628,7 +660,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [21] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -636,7 +668,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .direction = TF_DIR_TX }, - [22] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -644,7 +676,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [23] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -652,7 +684,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [24] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -660,7 +692,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .direction = TF_DIR_TX }, - [25] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -668,7 +700,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [26] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -676,7 +708,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [27] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -684,7 +716,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [28] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -692,7 +724,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_RX }, - [29] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -700,7 +732,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, .direction = TF_DIR_TX }, - [30] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -708,7 +740,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, - [31] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -716,7 +748,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_TX }, - [32] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -728,7 +760,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { /* List of tf resources required to be reserved per app/device */ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { - [0] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -736,7 +768,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 422 }, - [1] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -744,7 +776,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 6 }, - [2] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -752,7 +784,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 192 }, - [3] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -760,7 +792,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 64 }, - [4] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -768,7 +800,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 192 }, - [5] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -776,7 +808,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 8192 }, - [6] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -784,7 +816,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 16384 }, - [7] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -792,7 +824,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .count = 1023 }, - [8] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -800,7 +832,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .count = 511 }, - [9] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -808,7 +840,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .count = 63 }, - [10] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -816,7 +848,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, .count = 255 }, - [11] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -824,7 +856,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [12] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -832,7 +864,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 422 }, - [13] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -840,7 +872,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 6 }, - [14] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -848,7 +880,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 960 }, - [15] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -856,7 +888,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 88 }, - [16] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -864,7 +896,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 13168 }, - [17] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -872,7 +904,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, .count = 1 }, - [18] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -880,7 +912,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 292 }, - [19] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -888,7 +920,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 148 }, - [20] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -896,7 +928,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 192 }, - [21] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -904,7 +936,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 64 }, - [22] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -912,7 +944,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 192 }, - [23] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -920,7 +952,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 8192 }, - [24] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -928,7 +960,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 16384 }, - [25] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -936,7 +968,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .count = 1023 }, - [26] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -944,7 +976,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 511 }, - [27] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -952,7 +984,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .count = 223 }, - [28] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -960,7 +992,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .count = 255 }, - [29] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -968,7 +1000,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 488 }, - [30] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -976,7 +1008,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, .count = 511 }, - [31] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -984,7 +1016,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [32] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -992,7 +1024,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 292 }, - [33] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1000,7 +1032,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 144 }, - [34] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1008,7 +1040,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 960 }, - [35] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1016,7 +1048,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 928 }, - [36] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1024,7 +1056,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 15232 }, - [37] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1032,7 +1064,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, .count = 1 }, - [38] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1040,7 +1072,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 26 }, - [39] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1048,7 +1080,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 6 }, - [40] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1056,7 +1088,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 32 }, - [41] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1064,7 +1096,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 32 }, - [42] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1072,7 +1104,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 32 }, - [43] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1080,7 +1112,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 1024 }, - [44] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1088,7 +1120,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, - [45] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1096,7 +1128,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 14 }, - [46] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1104,7 +1136,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_EM_FKB, .count = 32 }, - [47] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1112,7 +1144,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_WC_FKB, .count = 32 }, - [48] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1120,7 +1152,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 64 }, - [49] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1128,7 +1160,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 64 }, - [50] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1136,7 +1168,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 300 }, - [51] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1144,7 +1176,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 6 }, - [52] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1152,7 +1184,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 128 }, - [53] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1160,7 +1192,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 112 }, - [54] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1168,7 +1200,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 13200 }, - [55] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1176,7 +1208,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 26 }, - [56] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1184,7 +1216,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 26 }, - [57] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1192,7 +1224,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 32 }, - [58] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1200,7 +1232,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 63 }, - [59] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1208,7 +1240,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 32 }, - [60] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1216,7 +1248,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 1024 }, - [61] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1224,7 +1256,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, - [62] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1232,7 +1264,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 14 }, - [63] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1240,7 +1272,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_EM_FKB, .count = 32 }, - [64] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1248,7 +1280,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_WC_FKB, .count = 32 }, - [65] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1256,7 +1288,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 64 }, - [66] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1264,7 +1296,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 100 }, - [67] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1272,7 +1304,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [68] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1280,7 +1312,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 200 }, - [69] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1288,7 +1320,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 110 }, - [70] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1296,7 +1328,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 128 }, - [71] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1304,7 +1336,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 128 }, - [72] = { + { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1312,7 +1344,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 15232 }, - [73] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1320,7 +1352,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 422 }, - [74] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1328,7 +1360,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 6 }, - [75] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1336,7 +1368,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 192 }, - [76] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1344,7 +1376,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 64 }, - [77] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1352,7 +1384,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 192 }, - [78] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1360,7 +1392,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 8192 }, - [79] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1368,7 +1400,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 16384 }, - [80] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1376,7 +1408,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .count = 1023 }, - [81] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1384,7 +1416,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .count = 511 }, - [82] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1392,7 +1424,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .count = 63 }, - [83] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1400,7 +1432,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, .count = 255 }, - [84] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1408,7 +1440,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [85] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1416,7 +1448,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 422 }, - [86] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1424,7 +1456,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 6 }, - [87] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1432,7 +1464,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 960 }, - [88] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1440,7 +1472,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 88 }, - [89] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1448,7 +1480,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 13168 }, - [90] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1456,7 +1488,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, .count = 1 }, - [91] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1464,7 +1496,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 292 }, - [92] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1472,7 +1504,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 148 }, - [93] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1480,7 +1512,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 192 }, - [94] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1488,7 +1520,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 64 }, - [95] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1496,7 +1528,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 192 }, - [96] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1504,7 +1536,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 8192 }, - [97] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1512,7 +1544,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 16384 }, - [98] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1520,7 +1552,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .count = 1023 }, - [99] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1528,7 +1560,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 511 }, - [100] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1536,7 +1568,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .count = 223 }, - [101] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1544,7 +1576,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .count = 255 }, - [102] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1552,7 +1584,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 488 }, - [103] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1560,7 +1592,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, .count = 511 }, - [104] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1568,7 +1600,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [105] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1576,7 +1608,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 292 }, - [106] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1584,7 +1616,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 144 }, - [107] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1592,7 +1624,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 960 }, - [108] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1600,7 +1632,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 928 }, - [109] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1608,7 +1640,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 15232 }, - [110] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -1616,7 +1648,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, .count = 1 }, - [111] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1624,7 +1656,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 26 }, - [112] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1632,7 +1664,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 6 }, - [113] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1640,7 +1672,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 32 }, - [114] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1648,7 +1680,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 32 }, - [115] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1656,7 +1688,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 32 }, - [116] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1664,7 +1696,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 1024 }, - [117] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1672,7 +1704,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, - [118] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1680,7 +1712,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 14 }, - [119] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1688,7 +1720,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_EM_FKB, .count = 32 }, - [120] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1696,7 +1728,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_WC_FKB, .count = 32 }, - [121] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1704,7 +1736,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 64 }, - [122] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1712,7 +1744,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 64 }, - [123] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1720,7 +1752,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 300 }, - [124] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1728,7 +1760,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 6 }, - [125] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1736,7 +1768,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 128 }, - [126] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1744,7 +1776,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 112 }, - [127] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -1752,7 +1784,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 13200 }, - [128] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1760,7 +1792,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 26 }, - [129] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1768,7 +1800,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 26 }, - [130] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1776,7 +1808,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 32 }, - [131] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1784,7 +1816,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 63 }, - [132] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1792,7 +1824,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 32 }, - [133] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1800,7 +1832,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 1024 }, - [134] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1808,7 +1840,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, - [135] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1816,7 +1848,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 14 }, - [136] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1824,7 +1856,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_EM_FKB, .count = 32 }, - [137] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1832,7 +1864,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_WC_FKB, .count = 32 }, - [138] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1840,7 +1872,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 64 }, - [139] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1848,7 +1880,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 100 }, - [140] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1856,7 +1888,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [141] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1864,7 +1896,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 200 }, - [142] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1872,7 +1904,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 110 }, - [143] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1880,7 +1912,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 128 }, - [144] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1888,7 +1920,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 128 }, - [145] = { + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -1896,7 +1928,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 15232 }, - [146] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1904,7 +1936,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 422 }, - [147] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1912,7 +1944,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 6 }, - [148] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1920,7 +1952,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 192 }, - [149] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1928,7 +1960,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 64 }, - [150] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1936,7 +1968,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 192 }, - [151] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1944,7 +1976,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 8192 }, - [152] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1952,7 +1984,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 16384 }, - [153] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1960,7 +1992,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .count = 1023 }, - [154] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1968,7 +2000,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .count = 511 }, - [155] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1976,7 +2008,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .count = 63 }, - [156] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1984,7 +2016,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, .count = 255 }, - [157] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -1992,7 +2024,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [158] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -2000,7 +2032,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 422 }, - [159] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -2008,7 +2040,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 6 }, - [160] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -2016,7 +2048,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 960 }, - [161] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -2024,7 +2056,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 88 }, - [162] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -2032,7 +2064,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 13168 }, - [163] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, @@ -2040,7 +2072,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, .count = 1 }, - [164] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2048,7 +2080,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 292 }, - [165] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2056,7 +2088,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 148 }, - [166] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2064,7 +2096,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 192 }, - [167] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2072,7 +2104,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 64 }, - [168] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2080,7 +2112,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 192 }, - [169] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2088,7 +2120,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 8192 }, - [170] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2096,7 +2128,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 16384 }, - [171] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2104,7 +2136,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .count = 1023 }, - [172] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2112,7 +2144,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 511 }, - [173] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2120,7 +2152,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .count = 223 }, - [174] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2128,7 +2160,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .count = 255 }, - [175] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2136,7 +2168,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 488 }, - [176] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2144,7 +2176,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, .count = 511 }, - [177] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2152,7 +2184,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [178] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2160,7 +2192,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 292 }, - [179] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2168,7 +2200,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 144 }, - [180] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2176,7 +2208,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 960 }, - [181] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2184,7 +2216,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 928 }, - [182] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2192,7 +2224,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 15232 }, - [183] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, @@ -2200,7 +2232,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, .count = 1 }, - [184] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2208,7 +2240,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 26 }, - [185] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2216,7 +2248,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 6 }, - [186] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2224,7 +2256,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 32 }, - [187] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2232,7 +2264,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 32 }, - [188] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2240,7 +2272,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 32 }, - [189] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2248,7 +2280,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 1024 }, - [190] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2256,7 +2288,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, - [191] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2264,7 +2296,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 14 }, - [192] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2272,7 +2304,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_EM_FKB, .count = 32 }, - [193] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2280,7 +2312,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_WC_FKB, .count = 32 }, - [194] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2288,7 +2320,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 64 }, - [195] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2296,7 +2328,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 64 }, - [196] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2304,7 +2336,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 300 }, - [197] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2312,7 +2344,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 6 }, - [198] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2320,7 +2352,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 128 }, - [199] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2328,7 +2360,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 112 }, - [200] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, @@ -2336,7 +2368,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_EM_TBL_TYPE_EM_RECORD, .count = 13200 }, - [201] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2344,7 +2376,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .count = 26 }, - [202] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2352,7 +2384,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, .count = 26 }, - [203] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2360,7 +2392,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_WC_PROF, .count = 32 }, - [204] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2368,7 +2400,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_PROF_FUNC, .count = 63 }, - [205] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2376,7 +2408,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_IDENT_TYPE_EM_PROF, .count = 32 }, - [206] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2384,7 +2416,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .count = 1024 }, - [207] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2392,7 +2424,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, - [208] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2400,7 +2432,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 14 }, - [209] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2408,7 +2440,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_EM_FKB, .count = 32 }, - [210] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2416,7 +2448,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_WC_FKB, .count = 32 }, - [211] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2424,7 +2456,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .count = 64 }, - [212] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2432,7 +2464,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .count = 100 }, - [213] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2440,7 +2472,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .count = 1 }, - [214] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2448,7 +2480,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 200 }, - [215] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2456,7 +2488,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 110 }, - [216] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2464,7 +2496,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .count = 128 }, - [217] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2472,7 +2504,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 128 }, - [218] = { + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, @@ -2482,18 +2514,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { } }; -/* Provides act_bitmask */ -struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = { - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | - BNXT_ULP_DIRECTION_INGRESS] = { - .act_bitmask = BNXT_ULP_ACT_BIT_SHARED_SAMPLE - }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | - BNXT_ULP_DIRECTION_EGRESS] = { - .act_bitmask = BNXT_ULP_ACT_BIT_SHARED_SAMPLE - } -}; - uint32_t ulp_act_prop_map_table[] = { [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] = BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c index e5a401e3f8..73df10a575 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c @@ -12,211 +12,15 @@ /* Mapper templates for header act list */ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { - /* act_tid: 1, thor, ingress */ - [1] = { - .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 2, - .start_tbl_idx = 0, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 0, - .cond_nums = 0 } - } }; struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { - { /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 0, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 0, - .result_bit_size = 64, - .result_num_fields = 1 - }, - { /* act_tid: 1, thor, table: int_full_act_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 1, - .result_bit_size = 128, - .result_num_fields = 17, - .encap_num_fields = 0 - } }; struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { - /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_COUNT - } }; struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { - /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */ - { - .description = "count", - .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* act_tid: 1, thor, table: int_full_act_record.0 */ - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "encap_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "mod_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rsvd1", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rsvd0", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meter", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "stats_op", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "stats_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} - }, - { - .description = "vnic_or_vport", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} - }, - { - .description = "use_default", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "mirror", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "cnd_copy", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "vlan_dlt_rpt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "drop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "hit", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "type", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } }; struct diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c index 4d3d1e24b4..d20e630980 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Feb 12 13:05:14 2021 */ +/* date: Sun Mar 14 12:41:59 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -12,33 +12,34 @@ /* Mapper templates for header class list */ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { - /* class_tid: 1, thor, ingress */ - [1] = { + /* class_tid: 3, thor, ingress */ + [3] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 11, + .num_tbls = 7, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, .cond_nums = 0 } }, - /* class_tid: 2, thor, ingress */ - [2] = { + /* class_tid: 4, thor, egress */ + [4] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 1, - .start_tbl_idx = 11, + .num_tbls = 6, + .start_tbl_idx = 7, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 } } }; struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { - { /* class_tid: 1, thor, table: mac_addr_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + { /* class_tid: 3, thor, table: int_full_act_record.ing_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, @@ -46,5913 +47,943 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 0, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 0, - .blob_key_bit_size = 56, - .key_bit_size = 56, - .key_num_fields = 2, .result_start_idx = 0, - .result_bit_size = 62, - .result_num_fields = 4 + .result_bit_size = 128, + .result_num_fields = 17 }, - { /* class_tid: 1, thor, table: control.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + { /* class_tid: 3, thor, table: parif_def_arec_ptr.ing_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 0, - .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 17, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + { /* class_tid: 3, thor, table: parif_def_err_arec_ptr.ing_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 2, - .blob_key_bit_size = 213, - .key_bit_size = 213, - .key_num_fields = 21, - .result_start_idx = 4, - .result_bit_size = 43, - .result_num_fields = 6, - .ident_start_idx = 0, - .ident_nums = 1 + .result_start_idx = 18, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: mac_addr_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + { /* class_tid: 3, thor, table: control.egr_1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 0, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 3, thor, table: int_full_act_record.egr_vfr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 23, - .blob_key_bit_size = 56, - .key_bit_size = 56, - .key_num_fields = 2, - .result_start_idx = 10, - .result_bit_size = 62, - .result_num_fields = 4 + .result_start_idx = 19, + .result_bit_size = 128, + .result_num_fields = 17, + .encap_num_fields = 0 }, - { /* class_tid: 1, thor, table: profile_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, + { /* class_tid: 3, thor, table: parif_def_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 25, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .ident_start_idx = 1, - .ident_nums = 5 - }, - { /* class_tid: 1, thor, table: control.1 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, + .result_start_idx = 36, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 3, thor, table: parif_def_err_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 5, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 1, - .cond_nums = 1 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 37, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: fkb_select.wm */ + { /* class_tid: 4, thor, table: int_full_act_record.loopback */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .direction = TF_DIR_RX, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 14, - .result_bit_size = 106, - .result_num_fields = 106 + .result_start_idx = 38, + .result_bit_size = 128, + .result_num_fields = 17, + .encap_num_fields = 0 }, - { /* class_tid: 1, thor, table: fkb_select.em */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .direction = TF_DIR_RX, + { /* class_tid: 4, thor, table: parif_def_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 120, - .result_bit_size = 106, - .result_num_fields = 106 - }, - { /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, + .result_start_idx = 55, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 4, thor, table: parif_def_err_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 28, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 226, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 6, - .ident_nums = 2 + .result_start_idx = 56, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: profile_tcam_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + { /* class_tid: 4, thor, table: int_full_act_record.vf_ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 71, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .result_start_idx = 234, - .result_bit_size = 82, - .result_num_fields = 7 + .result_start_idx = 57, + .result_bit_size = 128, + .result_num_fields = 17, + .encap_num_fields = 0 }, - { /* class_tid: 1, thor, table: em.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .direction = TF_DIR_RX, + { /* class_tid: 4, thor, table: vtag_encap_record.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 74, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 241, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 74, .result_bit_size = 0, - .result_num_fields = 6 + .result_num_fields = 0, + .encap_num_fields = 11 }, - { /* class_tid: 2, thor, table: int_full_act_record.0 */ + { /* class_tid: 4, thor, table: int_full_act_record.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 247, + .result_start_idx = 85, .result_bit_size = 128, .result_num_fields = 17 } }; struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_execute: class_tid: 1, control.0 */ + /* cond_execute: class_tid: 3, control.egr_1 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 1, control.1 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE } }; -struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { - /* class_tid: 1, thor, table: mac_addr_cache.rd */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ - { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } - }, - { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: mac_addr_cache.wr */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } - }, - /* class_tid: 1, thor, table: profile_tcam_cache.rd */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_UDP} - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L4_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, +struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { + /* class_tid: 3, thor, table: int_full_act_record.ing_0 */ { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "encap_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "mod_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "rsvd1", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "rsvd0", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "meter", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} - } + .description = "stats_op", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "stats_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "use_default", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "mirror", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .description = "cond_copy", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: profile_tcam_cache.wr */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} - } + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: em.ipv4 */ { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl3_sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl3_sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl3_sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl3_dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl3_dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl3_dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl3_fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl3_fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3_l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl4_src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl4_dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl4_flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tl4_seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4_err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} - }, - .field_info_spec = { - .description = "l3_sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} - } - }, - { - .field_info_mask = { - .description = "l3_sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l3_sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l3_sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} - }, - .field_info_spec = { - .description = "l3_dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} - } - }, - { - .field_info_mask = { - .description = "l3_dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l3_dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l3_dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_IP_PROTO_TCP}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_IP_PROTO_UDP} - } - }, - { - .field_info_mask = { - .description = "l3_fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l3_fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l3_fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3_l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} - }, - .field_info_spec = { - .description = "l4_src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} - } - }, - { - .field_info_mask = { - .description = "l4_dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - }, - .field_info_spec = { - .description = "l4_dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - } - }, - { - .field_info_mask = { - .description = "l4_flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4_flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4_seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4_ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4_win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4_tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4_txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4_err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_SKIP - } - } -}; - -struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { - /* class_tid: 1, thor, table: mac_addr_cache.rd */ - { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "src_property_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} - }, - { - .description = "ctxt_meta_prof", + .description = "type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "def_ctxt_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (4 >> 8) & 0xff, - 4 & 0xff} - }, - { - .description = "ctxt_opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: mac_addr_cache.wr */ - { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} - }, - { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "src_property_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: fkb_select.wm */ - { - .description = "l2_cntxt_id.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "parif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "spif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "svif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "lcos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rcyc_cnt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "loopback.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tuntype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tflags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tids.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tqos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "terr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_ack.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_win.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_tsval.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_txecr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: fkb_select.em */ - { - .description = "l2_cntxt_id.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "parif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "spif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "svif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "lcos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rcyc_cnt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "loopback.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tuntype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tflags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tids.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 3, thor, table: parif_def_arec_ptr.ing_0 */ { - .description = "tqos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 3, thor, table: parif_def_err_arec_ptr.ing_0 */ { - .description = "terr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 3, thor, table: int_full_act_record.egr_vfr */ { - .description = "l2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "encap_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "mod_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "rsvd1", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "rsvd0", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "meter", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovd.en", + .description = "stats_op", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "stats_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} }, { - .description = "l2_ivp.en", + .description = "use_default", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "mirror", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivv.en", + .description = "cond_copy", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_etype.en", + .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_l3type.en", + .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, + /* class_tid: 3, thor, table: parif_def_arec_ptr.egr_0 */ { - .description = "l3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 3, thor, table: parif_def_err_arec_ptr.egr_0 */ { - .description = "l3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 1} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 4, thor, table: int_full_act_record.loopback */ { - .description = "l3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "encap_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .description = "mod_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "rsvd1", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "rsvd0", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "meter", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_auth.en", + .description = "stats_op", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "stats_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_THOR_SYM_LOOPBACK_PORT & 0xff} }, { - .description = "l3_ieh_rthdr.en", + .description = "use_default", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "mirror", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_1frag.en", + .description = "cond_copy", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_l3err.en", + .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_l4type.en", + .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, + /* class_tid: 4, thor, table: parif_def_arec_ptr.vf_egr */ { - .description = "l4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, + /* class_tid: 4, thor, table: parif_def_err_arec_ptr.vf_egr */ { - .description = "l4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "act_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, + /* class_tid: 4, thor, table: int_full_act_record.vf_ing */ { - .description = "l4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_ack.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "encap_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_win.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "mod_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "rsvd1", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "rsvd0", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_tsval.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "meter", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_txecr.en", + .description = "stats_op", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "stats_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ { - .description = "wc_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + }, + { + .description = "use_default", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "mirror", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_search_en", + .description = "cond_copy", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_type", + .description = "vlan_del_rpt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - }, - { - .description = "em_search_en", + .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: profile_tcam_cache.wr */ { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + 1} }, + /* class_tid: 4, thor, table: vtag_encap_record.vfr_egr0 */ { - .description = "profile_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff} + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 & 0xff} + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_key_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_WC_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_WC_KEY_ID_0 & 0xff} + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { - .description = "flow_sig_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} + .description = "rsrvd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: em.ipv4 */ { - .description = "valid", + .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "vtag_tpid", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 0x81, + 0x00} }, { - .description = "arec_ptr_or_md", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} }, { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meta_prof", + .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, - /* class_tid: 2, thor, table: int_full_act_record.0 */ + /* class_tid: 4, thor, table: int_full_act_record.vfr_egr0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "mod_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rsvd1", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rsvd0", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "stats_op", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "stats_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_THOR_SYM_LOOPBACK_PORT & 0xff} }, { .description = "use_default", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "cnd_copy", + .description = "cond_copy", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vlan_dlt_rpt", + .description = "vlan_del_rpt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} } }; +struct +bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { +}; + struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { - /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 29 - }, - /* class_tid: 1, thor, table: profile_tcam_cache.rd */ - { - .description = "em_key_id", - .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 50 - }, - { - .description = "em_profile_id", - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 42 - }, - { - .description = "flow_sig_id", - .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 8, - .ident_bit_pos = 74 - }, - { - .description = "wc_key_id", - .regfile_idx = BNXT_ULP_RF_IDX_WC_KEY_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 66 - }, - { - .description = "wc_profile_id", - .regfile_idx = BNXT_ULP_RF_IDX_WC_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 58 - }, - /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ - { - .description = "wc_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_WC_PROF, - .regfile_idx = BNXT_ULP_RF_IDX_WC_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 6 - }, - { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 23 - } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index cb128e5695..1d21cd3e38 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Mar 9 19:13:26 2021 */ +/* date: Sun Mar 14 12:41:59 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -986,17 +986,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { .field_info_mask = { .description = "shared_index", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "shared_index", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, @@ -1008,17 +1006,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { .field_info_mask = { .description = "shared_index", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "shared_index", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, @@ -1032,44 +1028,38 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "count", .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} @@ -1077,15 +1067,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -1093,8 +1081,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, @@ -1103,8 +1090,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, @@ -1113,15 +1099,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, @@ -1130,16 +1114,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "spare", .field_bit_size = 80, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -1148,29 +1130,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -1185,29 +1163,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, @@ -1216,8 +1190,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, @@ -1226,9 +1199,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, @@ -1237,17 +1210,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, @@ -1256,9 +1228,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, @@ -1267,38 +1239,34 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -1307,8 +1275,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -1317,9 +1284,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, @@ -1328,18 +1295,17 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, @@ -1348,8 +1314,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, @@ -1364,16 +1329,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, @@ -1382,17 +1346,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, @@ -1407,23 +1370,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -1432,29 +1392,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -1469,50 +1425,43 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, @@ -1521,9 +1470,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, @@ -1532,17 +1481,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, @@ -1551,9 +1499,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, @@ -1562,38 +1510,34 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -1602,8 +1546,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -1612,9 +1555,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, @@ -1623,18 +1566,17 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, @@ -1643,8 +1585,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, @@ -1659,15 +1600,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, @@ -1676,8 +1615,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, @@ -1692,29 +1630,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L2_EN_YES} @@ -1722,72 +1656,62 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ { .description = "act_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -1795,45 +1719,39 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "copy", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ign_drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 2, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -1842,29 +1760,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -1879,106 +1793,91 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, @@ -1987,25 +1886,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { 1} @@ -2013,30 +1906,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 2, wh_plus, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -2045,29 +1934,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -2082,120 +1967,103 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, @@ -2204,8 +2072,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, @@ -2220,18 +2087,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { 1} @@ -2239,36 +2101,31 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L2_EN_YES} @@ -2276,65 +2133,56 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 2, wh_plus, table: mirror_tbl.wr */ { .description = "act_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -2343,8 +2191,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -2352,37 +2199,32 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "copy", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ign_drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -2391,11 +2233,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "mirror_id", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { (1 >> 8) & 0xff, @@ -2405,16 +2243,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "count", .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */ { .description = "ipv4_addr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, @@ -2424,8 +2260,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv4_addr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, @@ -2435,29 +2270,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L2_EN_YES} @@ -2465,22 +2296,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -2488,44 +2316,38 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 80, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 3, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -2534,29 +2356,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -2571,29 +2389,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, @@ -2602,8 +2416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, @@ -2612,9 +2425,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, @@ -2623,17 +2436,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, @@ -2642,9 +2454,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, @@ -2653,38 +2465,34 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -2693,8 +2501,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -2703,9 +2510,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, @@ -2714,18 +2521,17 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, @@ -2734,51 +2540,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 3, wh_plus, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -2787,29 +2586,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -2824,36 +2619,31 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, @@ -2862,8 +2652,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -2871,8 +2660,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, @@ -2881,9 +2669,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, @@ -2892,17 +2680,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, @@ -2911,9 +2698,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, @@ -2922,38 +2709,34 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -2962,8 +2745,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -2972,9 +2754,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, @@ -2983,18 +2765,17 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, @@ -3003,57 +2784,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L2_EN_YES} @@ -3061,101 +2834,87 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} @@ -3163,15 +2922,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -3179,8 +2936,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, @@ -3189,8 +2945,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, @@ -3199,15 +2954,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, @@ -3216,16 +2969,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "spare", .field_bit_size = 80, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 4, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -3234,29 +2985,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -3271,29 +3018,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, @@ -3302,57 +3045,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -3361,8 +3096,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -3371,15 +3105,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, @@ -3388,29 +3120,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, @@ -3425,23 +3153,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -3450,29 +3175,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -3487,99 +3208,85 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -3588,8 +3295,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -3598,15 +3304,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, @@ -3615,29 +3319,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, @@ -3652,29 +3352,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L2_EN_YES} @@ -3682,65 +3378,56 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -3749,29 +3436,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -3786,99 +3469,85 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -3887,8 +3556,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -3897,15 +3565,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, @@ -3914,8 +3580,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, @@ -3930,22 +3595,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, @@ -3960,36 +3622,31 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} @@ -3997,15 +3654,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -4013,8 +3668,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, @@ -4023,8 +3677,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, @@ -4033,15 +3686,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, @@ -4050,24 +3701,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "spare", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */ { .description = "ipv4_addr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, @@ -4077,8 +3725,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv4_addr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, @@ -4088,29 +3735,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L2_EN_YES} @@ -4118,22 +3761,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -4141,44 +3781,38 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 80, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 5, wh_plus, table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -4187,29 +3821,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -4224,29 +3854,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, @@ -4255,8 +3881,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, @@ -4265,9 +3890,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, @@ -4276,17 +3901,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, @@ -4295,9 +3919,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, @@ -4306,38 +3930,34 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -4346,8 +3966,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -4356,9 +3975,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, @@ -4367,18 +3986,17 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, @@ -4387,51 +4005,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 5, wh_plus, table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -4440,29 +4051,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -4477,36 +4084,31 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, @@ -4515,8 +4117,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -4524,8 +4125,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, @@ -4534,9 +4134,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, @@ -4545,17 +4145,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, @@ -4564,9 +4163,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, @@ -4575,38 +4174,34 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr1 = { + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, @@ -4615,8 +4210,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, @@ -4625,9 +4219,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, @@ -4636,18 +4230,17 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, @@ -4656,57 +4249,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L2_EN_YES} @@ -4714,73 +4299,63 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */ { .description = "smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, @@ -4789,8 +4364,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv4_src_addr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, @@ -4799,16 +4373,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "reserved", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */ { .description = "smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, @@ -4817,8 +4389,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ipv6_src_addr", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, @@ -4827,16 +4398,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "reserved", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_TUN_TYPE_VXLAN} @@ -4844,8 +4413,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM} @@ -4853,8 +4421,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, @@ -4863,8 +4430,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -4872,8 +4438,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, @@ -4882,15 +4447,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -4898,8 +4461,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_l2_dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, @@ -4908,8 +4470,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_vtag", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, @@ -4920,8 +4481,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ip", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, @@ -4932,8 +4492,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_udp", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, @@ -4942,8 +4501,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_tun", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, @@ -4955,8 +4513,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -4965,29 +4522,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -5002,29 +4555,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, @@ -5033,78 +4582,67 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, @@ -5113,51 +4651,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, @@ -5166,29 +4697,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, @@ -5203,120 +4730,103 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "flow_cntr_ext", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, @@ -5325,36 +4835,31 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_TUN_TYPE_VXLAN} @@ -5362,8 +4867,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM} @@ -5371,8 +4875,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, @@ -5381,8 +4884,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -5390,8 +4892,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, @@ -5400,15 +4901,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -5416,8 +4915,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_l2_dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, @@ -5426,8 +4924,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_vtag", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, @@ -5438,8 +4935,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_ip", .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, @@ -5450,8 +4946,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_udp", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, @@ -5460,8 +4955,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { { .description = "encap_tun", .field_bit_size = 80, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index fba5b777f7..4e0cd66126 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Mar 8 17:37:39 2021 */ +/* date: Mon Mar 15 10:26:20 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -25,21 +25,21 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { /* class_tid: 2, wh_plus, egress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 14, + .num_tbls = 15, .start_tbl_idx = 18, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 24, .cond_nums = 1 } }, /* class_tid: 3, wh_plus, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 23, - .start_tbl_idx = 32, + .num_tbls = 22, + .start_tbl_idx = 33, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 } }, /* class_tid: 4, wh_plus, egress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .start_tbl_idx = 55, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 39, + .cond_start_idx = 41, .cond_nums = 0 } } }; @@ -94,9 +94,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 1, - .blob_key_bit_size = 56, - .key_bit_size = 56, - .key_num_fields = 2, + .blob_key_bit_size = 70, + .key_bit_size = 70, + .key_num_fields = 5, .ident_start_idx = 1, .ident_nums = 1 }, @@ -130,7 +130,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 3, + .key_start_idx = 6, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -155,10 +155,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 16, - .blob_key_bit_size = 56, - .key_bit_size = 56, - .key_num_fields = 2, + .key_start_idx = 19, + .blob_key_bit_size = 70, + .key_bit_size = 70, + .key_num_fields = 5, .result_start_idx = 13, .result_bit_size = 62, .result_num_fields = 4 @@ -179,7 +179,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 18, + .key_start_idx = 24, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, @@ -213,8 +213,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cc_opc = BNXT_ULP_CC_UPD_OPC_EQ, .cc_src1 = BNXT_ULP_CC_UPD_SRC_REGFILE, .cc_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .cc_src2 = BNXT_ULP_CC_UPD_SRC_COMP_FIELD, - .cc_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .cc_src2 = BNXT_ULP_CC_UPD_SRC_REGFILE, + .cc_opr2 = BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID, .cc_dst_opr = BNXT_ULP_RF_IDX_CC }, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, @@ -235,7 +235,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 21, + .key_start_idx = 27, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -262,7 +262,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 64, + .key_start_idx = 70, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -272,7 +272,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 7, .ident_nums = 1 }, - { /* class_tid: 1, wh_plus, table: profile_tcam.vxlan */ + { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -281,7 +281,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 9, - .cond_nums = 1 }, + .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, @@ -289,7 +289,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 107, + .key_start_idx = 113, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -309,13 +309,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 150, + .key_start_idx = 156, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, @@ -331,13 +331,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, + .cond_start_idx = 11, .cond_nums = 3 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 153, + .key_start_idx = 159, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, @@ -353,13 +353,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 14, .cond_nums = 3 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 163, + .key_start_idx = 169, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, @@ -375,13 +375,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 17, .cond_nums = 3 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 173, + .key_start_idx = 179, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, @@ -397,13 +397,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 20, .cond_nums = 3 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 184, + .key_start_idx = 190, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, @@ -419,13 +419,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 23, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 195, + .key_start_idx = 201, .blob_key_bit_size = 200, .key_bit_size = 200, .key_num_fields = 11, @@ -441,13 +441,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 23, + .cond_start_idx = 24, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 206, + .key_start_idx = 212, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, @@ -464,13 +464,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 25, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 217, + .key_start_idx = 223, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -486,16 +486,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 25, + .cond_start_idx = 26, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 218, - .blob_key_bit_size = 56, - .key_bit_size = 56, - .key_num_fields = 2, + .key_start_idx = 224, + .blob_key_bit_size = 70, + .key_bit_size = 70, + .key_num_fields = 5, .ident_start_idx = 10, .ident_nums = 1 }, @@ -506,7 +506,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 26, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, @@ -520,7 +520,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 220, + .key_start_idx = 229, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, @@ -548,16 +548,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 233, - .blob_key_bit_size = 56, - .key_bit_size = 56, - .key_num_fields = 2, + .key_start_idx = 242, + .blob_key_bit_size = 70, + .key_bit_size = 70, + .key_num_fields = 5, .result_start_idx = 140, .result_bit_size = 62, .result_num_fields = 4 @@ -571,32 +571,51 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 235, + .key_start_idx = 247, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, .ident_start_idx = 12, .ident_nums = 3 }, - { /* class_tid: 2, wh_plus, table: control.1 */ + { /* class_tid: 2, wh_plus, table: control.gen_tbl_miss */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 4, + .cond_true_goto = 2, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, + { /* class_tid: 2, wh_plus, table: control.conflict_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 4, + .cond_false_goto = 1023, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 28, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .cc_upd_info = { + .cc_opc = BNXT_ULP_CC_UPD_OPC_EQ, + .cc_src1 = BNXT_ULP_CC_UPD_SRC_REGFILE, + .cc_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .cc_src2 = BNXT_ULP_CC_UPD_SRC_COMP_FIELD, + .cc_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .cc_dst_opr = BNXT_ULP_RF_IDX_CC }, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, { /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, @@ -605,7 +624,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 29, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -614,7 +633,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 238, + .key_start_idx = 250, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -632,7 +651,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -641,7 +660,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 281, + .key_start_idx = 293, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, @@ -660,13 +679,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 324, + .key_start_idx = 336, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, @@ -682,13 +701,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 2 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 327, + .key_start_idx = 339, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 10, @@ -704,13 +723,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 32, .cond_nums = 2 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 337, + .key_start_idx = 349, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 10, @@ -726,13 +745,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 347, + .key_start_idx = 359, .blob_key_bit_size = 416, .key_bit_size = 416, .key_num_fields = 11, @@ -748,13 +767,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 358, + .key_start_idx = 370, .blob_key_bit_size = 448, .key_bit_size = 448, .key_num_fields = 11, @@ -762,29 +781,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 3, wh_plus, table: port_table.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 33, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 369, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 219, - .result_bit_size = 144, - .result_num_fields = 4 - }, { /* class_tid: 3, wh_plus, table: int_full_act_record.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -795,14 +791,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 223, + .result_start_idx = 219, .result_bit_size = 128, .result_num_fields = 26 }, @@ -815,13 +811,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 370, + .key_start_idx = 381, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -835,7 +831,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, @@ -849,7 +845,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -860,11 +856,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 371, + .key_start_idx = 382, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 249, + .result_start_idx = 245, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 17, @@ -879,17 +875,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 384, + .key_start_idx = 395, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 262, + .result_start_idx = 258, .result_bit_size = 62, .result_num_fields = 4 }, @@ -901,13 +897,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 266, + .result_start_idx = 262, .result_bit_size = 32, .result_num_fields = 1 }, @@ -919,13 +915,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 267, + .result_start_idx = 263, .result_bit_size = 32, .result_num_fields = 1 }, @@ -937,13 +933,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 268, + .result_start_idx = 264, .result_bit_size = 32, .result_num_fields = 1 }, @@ -954,7 +950,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -969,14 +965,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 269, + .result_start_idx = 265, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -990,13 +986,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 385, + .key_start_idx = 396, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1010,7 +1006,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, @@ -1024,7 +1020,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1033,11 +1029,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 386, + .key_start_idx = 397, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 295, + .result_start_idx = 291, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 18, @@ -1052,17 +1048,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 399, + .key_start_idx = 410, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 308, + .result_start_idx = 304, .result_bit_size = 62, .result_num_fields = 4 }, @@ -1075,13 +1071,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 400, + .key_start_idx = 411, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1095,7 +1091,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, @@ -1109,7 +1105,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 37, + .cond_start_idx = 39, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1118,11 +1114,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 401, + .key_start_idx = 412, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 312, + .result_start_idx = 308, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 18, @@ -1137,17 +1133,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 39, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 414, + .key_start_idx = 425, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 325, + .result_start_idx = 321, .result_bit_size = 62, .result_num_fields = 4 }, @@ -1161,14 +1157,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 329, + .result_start_idx = 325, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -1181,13 +1177,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 355, + .result_start_idx = 351, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1199,13 +1195,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 356, + .result_start_idx = 352, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1217,13 +1213,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 357, + .result_start_idx = 353, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1237,14 +1233,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 358, + .result_start_idx = 354, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -1258,13 +1254,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 41, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 415, + .key_start_idx = 426, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1278,7 +1274,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 41, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, @@ -1292,7 +1288,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1301,11 +1297,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 416, + .key_start_idx = 427, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 384, + .result_start_idx = 380, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 19, @@ -1320,17 +1316,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 429, + .key_start_idx = 440, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 397, + .result_start_idx = 393, .result_bit_size = 62, .result_num_fields = 4 }, @@ -1342,13 +1338,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 401, + .result_start_idx = 397, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1360,13 +1356,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 402, + .result_start_idx = 398, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1378,13 +1374,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 403, + .result_start_idx = 399, .result_bit_size = 32, .result_num_fields = 1 }, @@ -1398,14 +1394,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 404, + .result_start_idx = 400, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 @@ -1418,7 +1414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1428,11 +1424,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 430, + .key_start_idx = 441, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 430, + .result_start_idx = 426, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 20, @@ -1447,13 +1443,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 443, + .key_start_idx = 454, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, @@ -1467,7 +1463,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, + .cond_start_idx = 42, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, @@ -1481,7 +1477,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1490,11 +1486,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 444, + .key_start_idx = 455, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 443, + .result_start_idx = 439, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 20, @@ -1509,17 +1505,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 457, + .key_start_idx = 468, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 456, + .result_start_idx = 452, .result_bit_size = 62, .result_num_fields = 4 }, @@ -1533,14 +1529,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 460, + .result_start_idx = 456, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 12 @@ -1555,14 +1551,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 472, + .result_start_idx = 468, .result_bit_size = 128, .result_num_fields = 26 }, @@ -1576,14 +1572,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 498, + .result_start_idx = 494, .result_bit_size = 128, .result_num_fields = 26 }, @@ -1595,7 +1591,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1605,11 +1601,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 458, + .key_start_idx = 469, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 524, + .result_start_idx = 520, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 20, @@ -1623,7 +1619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1633,11 +1629,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 471, + .key_start_idx = 482, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 537, + .result_start_idx = 533, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 20, @@ -1689,11 +1685,15 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, - /* cond_execute: class_tid: 1, profile_tcam.vxlan */ + /* cond_execute: class_tid: 1, profile_tcam.ipv4_vxlan */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, /* cond_execute: class_tid: 1, em.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, @@ -1761,11 +1761,16 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 2, control.1 */ + /* cond_execute: class_tid: 2, control.gen_tbl_miss */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* cond_execute: class_tid: 2, control.conflict_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_CC + }, /* cond_execute: class_tid: 2, profile_tcam.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, @@ -1838,8 +1843,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -1848,8 +1852,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -1861,8 +1864,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -1871,8 +1873,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -1880,11 +1881,85 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { } }, { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { .field_info_mask = { .description = "mac_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -1893,8 +1968,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "mac_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -1906,37 +1980,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -1944,8 +2036,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -1954,8 +2045,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -1966,8 +2056,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -1976,8 +2065,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -1988,15 +2076,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2004,15 +2090,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2020,15 +2104,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2036,15 +2118,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2052,17 +2132,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, @@ -2073,15 +2151,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2089,15 +2165,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2105,15 +2179,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2121,8 +2193,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -2130,8 +2201,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -2142,8 +2212,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -2152,8 +2221,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -2161,11 +2229,85 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { } }, { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { .field_info_mask = { .description = "mac_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -2174,8 +2316,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "mac_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -2187,17 +2328,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2205,26 +2344,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } @@ -2233,17 +2371,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, @@ -2255,15 +2391,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2271,20 +2405,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, @@ -2293,11 +2427,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, @@ -2305,8 +2439,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -2315,8 +2448,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2324,8 +2456,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -2334,8 +2465,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -2346,15 +2476,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2362,15 +2490,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2378,15 +2504,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2394,17 +2518,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2412,17 +2534,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2430,17 +2550,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L3_HDR_VALID_YES} @@ -2450,17 +2568,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2468,17 +2584,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, @@ -2489,17 +2603,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2507,17 +2619,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2525,17 +2635,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2543,17 +2651,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L2_HDR_VALID_YES} @@ -2563,15 +2669,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2579,15 +2683,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2595,15 +2697,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2611,17 +2711,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2629,15 +2727,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2645,15 +2741,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2661,15 +2755,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2677,17 +2769,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2695,15 +2785,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2711,15 +2799,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2727,15 +2813,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2743,15 +2827,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2759,15 +2841,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2775,17 +2855,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2793,15 +2871,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2809,15 +2885,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2825,15 +2899,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2841,15 +2913,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2857,17 +2927,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2875,15 +2943,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2891,15 +2957,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2907,26 +2971,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } @@ -2935,15 +2998,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2951,15 +3012,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2967,15 +3026,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2983,15 +3040,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2999,8 +3054,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -3008,8 +3062,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -3020,15 +3073,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3036,20 +3087,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, @@ -3058,11 +3109,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, @@ -3070,8 +3121,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -3080,8 +3130,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3089,8 +3138,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -3099,8 +3147,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -3111,15 +3158,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3127,15 +3172,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3143,15 +3186,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3159,17 +3200,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L3_HDR_TYPE_IPV6} @@ -3179,17 +3218,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3197,17 +3234,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L3_HDR_VALID_YES} @@ -3217,17 +3252,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3235,17 +3268,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, @@ -3256,17 +3287,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3274,17 +3303,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3292,17 +3319,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3310,17 +3335,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L2_HDR_VALID_YES} @@ -3330,15 +3353,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3346,15 +3367,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3362,15 +3381,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3378,17 +3395,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3396,15 +3411,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3412,15 +3425,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3428,15 +3439,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3444,17 +3453,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3462,15 +3469,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3478,15 +3483,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3494,15 +3497,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3510,15 +3511,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3526,15 +3525,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3542,17 +3539,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3560,15 +3555,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3576,15 +3569,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3592,15 +3583,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3608,15 +3597,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3624,17 +3611,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3642,15 +3627,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3658,15 +3641,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3674,26 +3655,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } @@ -3702,15 +3682,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3718,15 +3696,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3734,15 +3710,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3750,15 +3724,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3766,8 +3738,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -3775,27 +3746,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} } }, - /* class_tid: 1, wh_plus, table: profile_tcam.vxlan */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3803,17 +3771,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3823,17 +3789,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3841,15 +3805,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3857,15 +3819,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3873,15 +3833,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3889,15 +3847,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3905,15 +3861,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3921,17 +3875,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3939,15 +3891,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3955,15 +3905,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3971,15 +3919,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -3987,15 +3933,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4003,15 +3947,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4019,15 +3961,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4035,15 +3975,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4051,15 +3989,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4067,17 +4003,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4085,15 +4019,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4101,17 +4033,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_TUN_HDR_VALID_YES} @@ -4121,15 +4051,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4137,15 +4065,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4153,15 +4079,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4169,17 +4093,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_TL4_HDR_VALID_YES} @@ -4189,15 +4111,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4205,15 +4125,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4221,15 +4139,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4237,15 +4153,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4253,15 +4169,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4269,17 +4183,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_TL3_HDR_VALID_YES} @@ -4289,15 +4201,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4305,15 +4215,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4321,17 +4229,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4339,15 +4245,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4355,17 +4259,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_TL2_HDR_VALID_YES} @@ -4375,15 +4277,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4391,15 +4291,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4407,17 +4305,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, @@ -4428,15 +4324,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4444,15 +4338,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4460,15 +4352,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4476,15 +4366,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4492,8 +4380,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -4501,8 +4388,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -4513,17 +4399,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4531,26 +4415,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } @@ -4559,17 +4442,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, @@ -4581,15 +4462,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4597,15 +4476,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4613,9 +4490,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -4623,25 +4499,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -4649,136 +4524,108 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "l3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -4786,8 +4633,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -4798,17 +4644,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -4820,15 +4664,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 275, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 275, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4836,15 +4678,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4852,9 +4692,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -4862,25 +4701,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -4888,136 +4726,108 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "l3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5025,8 +4835,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -5037,17 +4846,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -5059,15 +4866,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5075,15 +4880,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5091,9 +4894,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5101,25 +4903,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5127,142 +4928,113 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.dst", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "l3.src", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { .field_info_mask = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5270,9 +5042,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5280,8 +5051,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -5292,17 +5062,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -5314,15 +5082,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 35, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 35, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5330,15 +5096,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5346,9 +5110,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5356,25 +5119,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5382,142 +5144,113 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.dst", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "l3.src", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { .field_info_mask = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5525,9 +5258,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5535,8 +5267,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -5547,17 +5278,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -5569,15 +5298,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5585,15 +5312,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5601,15 +5326,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5617,40 +5340,45 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "tl4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (4789 >> 8) & 0xff, + 4789 & 0xff} } }, { .field_info_mask = { .description = "tl3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 17} } }, { .field_info_mask = { .description = "tl3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, @@ -5659,8 +5387,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tl3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, @@ -5671,15 +5398,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5687,15 +5412,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2.src", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2.src", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5703,15 +5426,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_id", .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_id", .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5719,9 +5440,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5729,8 +5449,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -5741,17 +5460,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -5763,15 +5480,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 251, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 251, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5779,15 +5494,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5795,31 +5508,33 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { .description = "tl4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (4789 >> 8) & 0xff, + 4789 & 0xff} } }, { .field_info_mask = { .description = "tl4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5827,24 +5542,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { .description = "tl3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 17} } }, { .field_info_mask = { .description = "tl3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, @@ -5853,8 +5569,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "tl3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, @@ -5865,15 +5580,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5881,15 +5594,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2.src", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2.src", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5897,15 +5608,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_id", .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_id", .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5913,9 +5622,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -5923,8 +5631,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -5935,17 +5642,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -5957,8 +5662,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -5967,8 +5671,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -5980,8 +5683,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -5990,8 +5692,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -5999,11 +5700,85 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { } }, { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { .field_info_mask = { .description = "mac_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -6012,8 +5787,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "mac_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -6025,37 +5799,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff} + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6063,8 +5855,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -6073,8 +5864,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -6085,8 +5875,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -6095,8 +5884,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -6107,15 +5895,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6123,15 +5909,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6139,15 +5923,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6155,15 +5937,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6171,17 +5951,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, @@ -6192,15 +5970,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6208,15 +5984,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6224,15 +5998,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6240,8 +6012,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -6249,8 +6020,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -6261,8 +6031,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -6271,8 +6040,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, @@ -6280,11 +6048,85 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { } }, { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { .field_info_mask = { .description = "mac_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -6293,8 +6135,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "mac_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -6306,17 +6147,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6324,26 +6163,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } @@ -6352,17 +6190,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, @@ -6374,15 +6210,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6390,20 +6224,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, @@ -6412,11 +6246,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, @@ -6424,8 +6258,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -6434,8 +6267,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6443,8 +6275,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -6453,8 +6284,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -6465,15 +6295,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6481,15 +6309,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6497,15 +6323,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6513,17 +6337,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6531,17 +6353,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6549,17 +6369,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L3_HDR_VALID_YES} @@ -6569,17 +6387,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6587,17 +6403,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, @@ -6608,17 +6422,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6626,17 +6438,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6644,17 +6454,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6662,17 +6470,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L2_HDR_VALID_YES} @@ -6682,15 +6488,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6698,15 +6502,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6714,15 +6516,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6730,17 +6530,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6748,15 +6546,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6764,15 +6560,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6780,15 +6574,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6796,17 +6588,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6814,15 +6604,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6830,15 +6618,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6846,15 +6632,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6862,15 +6646,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6878,15 +6660,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6894,17 +6674,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6912,15 +6690,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6928,15 +6704,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6944,15 +6718,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6960,15 +6732,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6976,17 +6746,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6994,15 +6762,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7010,15 +6776,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7026,26 +6790,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } @@ -7054,15 +6817,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7070,15 +6831,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7086,15 +6845,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7102,15 +6859,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7118,8 +6873,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -7127,8 +6881,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -7139,15 +6892,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7155,20 +6906,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, @@ -7177,11 +6928,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, @@ -7189,8 +6940,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -7199,8 +6949,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7208,8 +6957,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -7218,8 +6966,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, @@ -7230,15 +6977,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7246,15 +6991,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7262,15 +7005,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7278,17 +7019,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L3_HDR_TYPE_IPV6} @@ -7298,17 +7037,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7316,17 +7053,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L3_HDR_VALID_YES} @@ -7336,17 +7071,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7354,17 +7087,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, @@ -7375,17 +7106,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7393,17 +7122,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7411,17 +7138,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7429,17 +7154,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_L2_HDR_VALID_YES} @@ -7449,15 +7172,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_flags", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7465,15 +7186,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7481,15 +7200,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_err", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7497,17 +7214,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tun_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7515,15 +7230,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_is_udp_tcp", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7531,15 +7244,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7547,15 +7258,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl4_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7563,17 +7272,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl4_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7581,15 +7288,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_dst", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7597,15 +7302,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_ipv6_cmp_src", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7613,15 +7316,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_isIP", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7629,15 +7330,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7645,15 +7344,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl3_hdr_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7661,17 +7358,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl3_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7679,15 +7374,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_two_vtags", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7695,15 +7388,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_vtag_present", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7711,15 +7402,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_uc_mc_bc", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7727,15 +7416,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_hdr_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7743,17 +7430,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tl2_hdr_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7761,15 +7446,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "hrec_next", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7777,15 +7460,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "reserved", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7793,26 +7474,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } @@ -7821,15 +7501,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "agg_error", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7837,15 +7515,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7853,15 +7529,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_0", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7869,15 +7543,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "pkt_type_1", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7885,8 +7557,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -7894,8 +7565,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -7906,17 +7576,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "recycle_cnt", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7924,26 +7592,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } @@ -7952,17 +7619,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "hdr_sig_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, @@ -7974,15 +7639,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7990,15 +7653,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8006,9 +7667,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8016,25 +7676,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8042,136 +7701,108 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "l3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8179,8 +7810,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -8191,17 +7821,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -8213,15 +7841,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 275, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 275, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8229,15 +7855,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8245,9 +7869,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8255,25 +7878,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8281,136 +7903,108 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "l3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8418,8 +8012,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -8430,17 +8023,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -8452,15 +8043,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8468,15 +8057,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8484,9 +8071,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8494,25 +8080,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8520,112 +8105,93 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.dst", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "l3.src", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8633,39 +8199,28 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8673,8 +8228,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -8685,17 +8239,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -8707,15 +8259,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "spare", .field_bit_size = 35, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "spare", .field_bit_size = 35, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8723,15 +8273,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "local_cos", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8739,9 +8287,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8749,25 +8296,24 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.dst", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8775,112 +8321,93 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l4.src", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "l3.dst", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { .field_info_mask = { .description = "l3.src", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { .field_info_mask = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2.smac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8888,39 +8415,28 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "l2.dmac", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT, - .field_cond_opr = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -8928,8 +8444,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -8940,61 +8455,35 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 3, wh_plus, table: port_table.wr */ - { - .field_info_mask = { - .description = "dev.port_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "dev.port_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } - }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_rd */ { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, @@ -9006,15 +8495,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9022,15 +8509,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9038,15 +8523,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9054,17 +8537,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, @@ -9075,15 +8556,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9091,15 +8570,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9107,15 +8584,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9123,15 +8598,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9139,15 +8612,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9155,15 +8626,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9171,15 +8640,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9187,15 +8654,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9203,8 +8668,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -9212,8 +8676,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -9224,17 +8687,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, @@ -9246,17 +8707,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -9268,15 +8727,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9284,15 +8741,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9300,15 +8755,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9316,17 +8769,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -9337,15 +8788,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9353,15 +8802,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9369,15 +8816,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9385,15 +8830,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9401,15 +8844,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9417,15 +8858,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9433,15 +8872,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9449,15 +8886,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9465,8 +8900,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -9474,8 +8908,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -9486,17 +8919,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -9508,17 +8939,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -9530,15 +8959,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9546,15 +8973,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9562,15 +8987,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9578,17 +9001,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -9599,15 +9020,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9615,15 +9034,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9631,15 +9048,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9647,15 +9062,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9663,15 +9076,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9679,15 +9090,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9695,15 +9104,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9711,15 +9118,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9727,8 +9132,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -9736,8 +9140,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -9748,17 +9151,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -9770,17 +9171,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, @@ -9792,15 +9191,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9808,15 +9205,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9824,15 +9219,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9840,17 +9233,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, @@ -9861,15 +9252,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9877,15 +9266,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9893,15 +9280,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9909,15 +9294,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9925,15 +9308,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9941,15 +9322,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9957,15 +9336,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9973,15 +9350,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9989,8 +9364,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -9998,8 +9372,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10010,17 +9383,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, @@ -10032,15 +9403,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10048,15 +9417,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10064,15 +9431,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10080,17 +9445,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, @@ -10101,15 +9464,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10117,15 +9478,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10133,15 +9492,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10149,15 +9506,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10165,15 +9520,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10181,15 +9534,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10197,15 +9548,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10213,15 +9562,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10229,8 +9576,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10238,8 +9584,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10250,17 +9595,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -10272,15 +9615,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10288,15 +9629,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10304,15 +9643,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10320,17 +9657,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -10341,15 +9676,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10357,15 +9690,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10373,15 +9704,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10389,15 +9718,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10405,15 +9732,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10421,15 +9746,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10437,15 +9760,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10453,15 +9774,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10469,8 +9788,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10478,8 +9796,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10490,17 +9807,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -10512,15 +9827,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10528,9 +9841,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -10538,8 +9850,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, @@ -10550,15 +9861,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10566,17 +9875,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -10587,15 +9894,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10603,15 +9908,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10619,15 +9922,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10635,15 +9936,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10651,17 +9950,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 2} @@ -10671,15 +9968,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10687,17 +9982,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_TUN_HDR_TYPE_NONE} @@ -10707,15 +10000,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10723,8 +10014,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10732,8 +10022,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10744,9 +10033,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff, 0xff} @@ -10754,8 +10042,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "l2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, @@ -10766,15 +10053,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10782,15 +10067,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10798,17 +10081,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "svif", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, @@ -10819,15 +10100,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10835,15 +10114,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ivlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10851,15 +10128,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_ovlan_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10867,15 +10142,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac1_addr", .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10883,17 +10156,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10903,15 +10174,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tl2_num_vtags", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10919,17 +10188,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_TUN_HDR_TYPE_NONE} @@ -10939,15 +10206,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "key_type", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10955,8 +10220,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_mask = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10964,8 +10228,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_info_spec = { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -10978,8 +10241,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -10988,8 +10250,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, @@ -10998,15 +10259,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, @@ -11015,50 +10274,43 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11066,23 +10318,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -11091,18 +10340,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -11111,37 +10355,32 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ { .description = "wc_key_id", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.0", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11149,8 +10388,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.1", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -11159,8 +10397,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.2", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, @@ -11169,8 +10406,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.3", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, @@ -11179,59 +10415,68 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.4", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} }, { .description = "em_key_mask.5", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} }, { .description = "em_key_mask.6", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} }, { .description = "em_key_mask.7", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.8", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.9", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -11239,8 +10484,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -11249,8 +10493,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11258,37 +10501,32 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ { .description = "wc_key_id", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.0", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11296,15 +10534,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.1", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.2", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, @@ -11313,8 +10549,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.3", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, @@ -11323,8 +10558,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.4", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, @@ -11333,52 +10567,62 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.5", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} }, { .description = "em_key_mask.6", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} }, { .description = "em_key_mask.7", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} }, { .description = "em_key_mask.8", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.9", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 7} @@ -11386,8 +10630,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -11396,8 +10639,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11405,37 +10647,32 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.vxlan */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ { .description = "wc_key_id", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.0", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11443,29 +10680,25 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.1", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.2", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.3", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.4", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11473,43 +10706,41 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.5", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "em_key_mask.6", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { .description = "em_key_mask.7", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.8", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.9", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 20} @@ -11517,8 +10748,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -11527,8 +10757,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11536,16 +10765,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -11554,8 +10781,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "profile_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, @@ -11564,8 +10790,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -11574,15 +10799,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "wc_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_sig_id", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, @@ -11592,8 +10815,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -11602,43 +10824,37 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -11646,15 +10862,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11663,8 +10877,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -11673,22 +10886,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, @@ -11697,8 +10907,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { (173 >> 8) & 0xff, @@ -11707,15 +10916,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -11723,15 +10930,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11740,8 +10945,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -11750,43 +10954,37 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -11794,15 +10992,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11811,8 +11007,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -11821,22 +11016,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, @@ -11845,8 +11037,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { (413 >> 8) & 0xff, @@ -11855,15 +11046,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -11871,15 +11060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11888,8 +11075,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -11898,43 +11084,37 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -11942,15 +11122,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -11959,8 +11137,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -11969,22 +11146,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, @@ -11993,8 +11167,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { (197 >> 8) & 0xff, @@ -12003,15 +11176,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -12019,15 +11190,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12036,8 +11205,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -12046,8 +11214,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, @@ -12056,66 +11223,59 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF, - .field_cond_opr = { + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff}, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_LOOPBACK_PARIF}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { + ULP_WP_SYM_LOOPBACK_PARIF}, + .field_src3 = BNXT_ULP_FIELD_SRC_CF, + .field_opr3 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff, @@ -12124,8 +11284,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12133,23 +11292,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -12158,8 +11314,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, @@ -12168,8 +11323,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -12178,37 +11332,32 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ { .description = "wc_key_id", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.0", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12216,8 +11365,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.1", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -12226,8 +11374,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.2", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, @@ -12236,8 +11383,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.3", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, @@ -12246,59 +11392,68 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.4", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} }, { .description = "em_key_mask.5", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} }, { .description = "em_key_mask.6", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} }, { .description = "em_key_mask.7", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.8", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.9", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 4} @@ -12306,8 +11461,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -12316,8 +11470,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12325,37 +11478,32 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ { .description = "wc_key_id", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "wc_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.0", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12363,8 +11511,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.1", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, @@ -12373,15 +11520,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.2", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.3", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, @@ -12390,8 +11535,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.4", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, @@ -12400,52 +11544,62 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_key_mask.5", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} }, { .description = "em_key_mask.6", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} }, { .description = "em_key_mask.7", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} }, { .description = "em_key_mask.8", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_mask.9", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "em_key_id", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 7} @@ -12453,8 +11607,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -12463,8 +11616,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_search_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12472,16 +11624,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pl_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -12490,8 +11640,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "profile_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, @@ -12500,8 +11649,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "em_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, @@ -12510,15 +11658,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "wc_profile_id", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_sig_id", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, @@ -12528,8 +11674,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -12538,43 +11683,37 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -12582,15 +11721,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12599,8 +11736,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -12609,22 +11745,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, @@ -12633,8 +11766,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { (173 >> 8) & 0xff, @@ -12643,15 +11775,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -12659,15 +11789,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12676,8 +11804,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -12686,43 +11813,37 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -12730,15 +11851,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -12747,8 +11866,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 33, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -12757,22 +11875,19 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ext_flow_cntr", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_int", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "act_rec_size", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, @@ -12781,8 +11896,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "key_size", .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { (413 >> 8) & 0xff, @@ -12791,15 +11905,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "strength", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 3} @@ -12807,200 +11919,136 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, - /* class_tid: 3, wh_plus, table: port_table.wr */ - { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "drv_func.mac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_PORT_TABLE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}, - .field_opr2 = { - (BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC >> 8) & 0xff, - BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC & 0xff} - }, - { - .description = "drv_func.parent.mac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_PORT_TABLE, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}, - .field_opr2 = { - (BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_MAC & 0xff} - }, - { - .description = "default_arec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} - }, /* class_tid: 3, wh_plus, table: int_full_act_record.ing_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, @@ -13009,51 +12057,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -13062,8 +12103,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -13072,15 +12112,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, @@ -13089,50 +12127,43 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -13140,23 +12171,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_wr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -13165,8 +12193,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, @@ -13175,8 +12202,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -13185,16 +12211,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -13204,8 +12228,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -13215,8 +12238,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -13226,141 +12248,121 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, @@ -13369,65 +12371,56 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.egr_vfr */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -13435,8 +12428,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, @@ -13445,36 +12437,31 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -13482,15 +12469,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -13498,23 +12483,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -13523,8 +12505,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, @@ -13533,23 +12514,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -13558,8 +12536,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -13568,15 +12545,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, @@ -13585,50 +12560,43 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -13636,23 +12604,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -13661,8 +12626,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, @@ -13671,8 +12635,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -13681,149 +12644,128 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: int_full_act_record.egr_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, @@ -13832,51 +12774,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -13886,8 +12821,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -13897,8 +12831,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -13908,141 +12841,121 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, @@ -14051,51 +12964,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -14104,8 +13010,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "prof_func_id", .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -14114,15 +13019,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_LOOPBACK_PARIF} @@ -14130,50 +13033,43 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -14181,23 +13077,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_egr_wr */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -14206,8 +13099,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, @@ -14216,8 +13108,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, @@ -14226,16 +13117,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "src_property_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, @@ -14245,8 +13134,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, @@ -14256,8 +13144,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "act_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, @@ -14267,141 +13154,121 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, @@ -14410,51 +13277,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vf_ing */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -14463,15 +13323,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -14479,57 +13337,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -14537,37 +13387,32 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_egr0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "reserved", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -14575,43 +13420,37 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -14619,15 +13458,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -14635,23 +13472,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, @@ -14660,8 +13494,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_tcam_index", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, @@ -14670,51 +13503,44 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "l2_cntxt_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_property_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: int_vtag_encap_record.vfr_egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l3_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_l2_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_vtag_type", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} @@ -14722,15 +13548,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "ecv_valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -14738,8 +13562,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vtag_tpid", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 0x81, @@ -14748,8 +13571,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vtag_vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, @@ -14758,86 +13580,74 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "vtag_de", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vtag_pcp", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "spare", .field_bit_size = 80, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_egr0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, @@ -14846,78 +13656,67 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, @@ -14926,184 +13725,158 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_ing0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "age_enable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "agg_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rate_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "flow_cntr_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_key", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_mir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcpflags_match", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "encap_ptr", .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "dst_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_dst_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "src_ip_ptr", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tcp_src_port", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter_id", .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_rdir", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tl3_ttl_dec", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "decap_func", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "vnic_or_vport", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, @@ -15112,8 +13885,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pop_vlan", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -15121,44 +13893,38 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "meter", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "mirror", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "drop", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "hit", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "type", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -15167,15 +13933,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -15183,57 +13947,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -15241,23 +13997,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -15266,15 +14019,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "reserved", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_byp_lkup_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -15282,57 +14033,49 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "parif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_pri", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_pri", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "allowed_tpid", .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "default_tpid", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "bd_act_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "sp_rec_ptr", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "byp_sp_lkup", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} @@ -15340,15 +14083,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { { .description = "pri_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "tpid_anti_spoof_ctl", .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_COND_OP, - .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }; @@ -15414,7 +14155,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 1, wh_plus, table: profile_tcam.vxlan */ + /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index f5f01c0bcf..938bcbfe56 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -287,13 +287,12 @@ struct bnxt_ulp_mapper_field_info { uint8_t description[64]; uint16_t field_bit_size; enum bnxt_ulp_field_opc field_opc; - enum bnxt_ulp_field_cond_src field_cond_src; - uint8_t field_cond_opr[16]; enum bnxt_ulp_field_src field_src1; uint8_t field_opr1[16]; enum bnxt_ulp_field_src field_src2; uint8_t field_opr2[16]; - + enum bnxt_ulp_field_src field_src3; + uint8_t field_opr3[16]; }; struct bnxt_ulp_mapper_key_info { diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index 329799ea6a..1649e157f2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -448,7 +448,7 @@ ulp_blob_push_32(struct ulp_blob *blob, * The offset of the data is updated after each push of data. * NULL returned on error, pointer pushed value otherwise. */ -uint32_t +int32_t ulp_blob_push_encap(struct ulp_blob *blob, uint8_t *data, uint32_t datalen) @@ -460,7 +460,7 @@ ulp_blob_push_encap(struct ulp_blob *blob, if (!blob || !data || datalen > (uint32_t)(blob->bitlen - blob->write_idx)) { BNXT_TF_DBG(ERR, "invalid argument\n"); - return 0; + return -1; } initial_size = ULP_BYTE_2_BITS(sizeof(uint64_t)) - @@ -479,7 +479,7 @@ ulp_blob_push_encap(struct ulp_blob *blob, } if (!ulp_blob_push(blob, val, size)) { BNXT_TF_DBG(ERR, "push field failed\n"); - return 0; + return -1; } val += ULP_BITS_2_BYTE(size); write_size -= size; diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h index 5dd22cf8c3..209c8fa6a4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.h +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h @@ -272,7 +272,7 @@ ulp_blob_push_32(struct ulp_blob *blob, * The offset of the data is updated after each push of data. * NULL returned on error, pointer pushed value otherwise. */ -uint32_t +int32_t ulp_blob_push_encap(struct ulp_blob *blob, uint8_t *data, uint32_t datalen); From patchwork Sun May 30 08:59:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93591 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8B2A3A0524; Sun, 30 May 2021 11:06:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3E9AE40395; Sun, 30 May 2021 11:02:01 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id E725441174 for ; Sun, 30 May 2021 11:01:58 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 5080B7DC0; Sun, 30 May 2021 02:01:57 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 5080B7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365318; bh=qg0NcZY07973bRHq261NomUjNKM64WPUlricf3AhKeE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u7y8DqtpCU6P9yE6zAtOjkcAsmFBwpVirlRgiE8mNHl5VK2Pf1AbZDVahzypc4+o1 48P/Las5B/Hz9UCegARw45CexGr3X6hEpes6A/IhydUvZar6XpcqWUwnx8M/eDde7k OTA5/nazDlEOIANwZKvH7mS7nLrVWyBpnrS4KkUE= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:21 +0530 Message-Id: <20210530085929.29695-51-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 50/58] net/bnxt: add support for application ID in ULP matcher X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The application id in the ulp matcher makes the template matching restrict to only flows that are support for that application. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Shahaji Bhosle --- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 11 + drivers/net/bnxt/tf_ulp/ulp_mapper.c | 61 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 3 +- drivers/net/bnxt/tf_ulp/ulp_matcher.c | 28 +- drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 87 +- .../net/bnxt/tf_ulp/ulp_template_db_class.c | 5690 +++++++++-------- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 21 +- .../net/bnxt/tf_ulp/ulp_template_db_field.h | 1050 +-- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 14 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 3 + 10 files changed, 3886 insertions(+), 3082 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 63fb4b5973..42dc9bef71 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -99,6 +99,7 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, mapper_cparms->fld_bitmap = ¶ms->fld_bitmap; mapper_cparms->flow_pattern_id = params->flow_pattern_id; mapper_cparms->act_pattern_id = params->act_pattern_id; + mapper_cparms->app_id = params->app_id; /* update the signature fields into the computed field list */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID, @@ -140,6 +141,11 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, memset(¶ms, 0, sizeof(struct ulp_rte_parser_params)); params.ulp_ctx = ulp_ctx; + if (bnxt_ulp_cntxt_app_id_get(params.ulp_ctx, ¶ms.app_id)) { + BNXT_TF_DBG(ERR, "failed to get the app id\n"); + goto flow_error; + } + /* Set the flow attributes */ bnxt_ulp_set_dir_attributes(¶ms, attr); @@ -258,6 +264,11 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev, memset(¶ms, 0, sizeof(struct ulp_rte_parser_params)); params.ulp_ctx = ulp_ctx; + if (bnxt_ulp_cntxt_app_id_get(params.ulp_ctx, ¶ms.app_id)) { + BNXT_TF_DBG(ERR, "failed to get the app id\n"); + goto parse_error; + } + /* Set the flow attributes */ bnxt_ulp_set_dir_attributes(¶ms, attr); diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 05e2106c38..8fd8a329bf 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -225,8 +225,11 @@ ulp_mapper_glb_field_tbl_get(struct bnxt_ulp_mapper_parms *parms, { uint32_t t_idx; - t_idx = parms->class_tid << (BNXT_ULP_HDR_SIG_ID_SHIFT + - BNXT_ULP_GLB_FIELD_TBL_SHIFT); + t_idx = parms->app_id << (BNXT_ULP_APP_ID_SHIFT + + BNXT_ULP_HDR_SIG_ID_SHIFT + + BNXT_ULP_GLB_FIELD_TBL_SHIFT); + t_idx += parms->class_tid << (BNXT_ULP_HDR_SIG_ID_SHIFT + + BNXT_ULP_GLB_FIELD_TBL_SHIFT); t_idx += ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_HDR_SIG_ID) << BNXT_ULP_GLB_FIELD_TBL_SHIFT; t_idx += operand; @@ -1350,21 +1353,18 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms, /* process the field opcodes */ switch (fld->field_opc) { case BNXT_ULP_FIELD_OPC_SRC1: - if (ulp_mapper_field_blob_write(fld->field_src1, - blob, val1, val1_len, &val)) - goto error; + rc = ulp_mapper_field_blob_write(fld->field_src1, + blob, val1, val1_len, &val); val_len = val1_len; break; case BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3: if (value1) { - if (ulp_mapper_field_blob_write(fld->field_src2, blob, - val2, val2_len, &val)) - goto error; + rc = ulp_mapper_field_blob_write(fld->field_src2, blob, + val2, val2_len, &val); val_len = val2_len; } else { - if (ulp_mapper_field_blob_write(fld->field_src3, blob, - val3, val3_len, &val)) - goto error; + rc = ulp_mapper_field_blob_write(fld->field_src3, blob, + val3, val3_len, &val); val_len = val3_len; } break; @@ -1373,60 +1373,50 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms, val_int = val1_int + val2_int; val_int = tfp_cpu_to_be_64(val_int); val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); - if (!val) { - BNXT_TF_DBG(ERR, "push to blob failed\n"); - goto error; - } + if (!val) + rc = -EINVAL; break; case BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2: case BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2_POST: val_int = val1_int - val2_int; val_int = tfp_cpu_to_be_64(val_int); val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); - if (!val) { - BNXT_TF_DBG(ERR, "push to blob failed\n"); - goto error; - } + if (!val) + rc = -EINVAL; break; case BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2: val_int = val1_int | val2_int; val_int = tfp_cpu_to_be_64(val_int); val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); - if (!val) { - BNXT_TF_DBG(ERR, "push to blob failed\n"); - goto error; - } + if (!val) + rc = -EINVAL; break; case BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2_OR_SRC3: val_int = val1_int | val2_int | val3_int; val_int = tfp_cpu_to_be_64(val_int); val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); - if (!val) { - BNXT_TF_DBG(ERR, "push to blob failed\n"); - goto error; - } + if (!val) + rc = -EINVAL; break; case BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2: val_int = val1_int & val2_int; val_int = tfp_cpu_to_be_64(val_int); val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); - if (!val) { - BNXT_TF_DBG(ERR, "push to blob failed\n"); - goto error; - } + if (!val) + rc = -EINVAL; break; case BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3: val_int = val1_int & (val2_int | val3_int); val_int = tfp_cpu_to_be_64(val_int); val = ulp_blob_push_64(blob, &val_int, fld->field_bit_size); - if (!val) { - BNXT_TF_DBG(ERR, "push to blob failed\n"); - goto error; - } + if (!val) + rc = -EINVAL; break; case BNXT_ULP_FIELD_OPC_SKIP: break; default: + BNXT_TF_DBG(ERR, "Invalid fld opcode %u\n", fld->field_opc); + rc = -EINVAL; break; } @@ -3703,6 +3693,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, parms.app_priority = cparms->app_priority; parms.flow_pattern_id = cparms->flow_pattern_id; parms.act_pattern_id = cparms->act_pattern_id; + parms.app_id = cparms->app_id; /* Get the device id from the ulp context */ if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 6e4d9e8522..edd5978ac6 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -61,6 +61,7 @@ struct bnxt_ulp_mapper_parms { uint64_t shared_hndl; uint32_t flow_pattern_id; uint32_t act_pattern_id; + uint8_t app_id; }; struct bnxt_ulp_mapper_create_parms { @@ -88,7 +89,7 @@ struct bnxt_ulp_mapper_create_parms { /* support pattern based rejection */ uint32_t flow_pattern_id; uint32_t act_pattern_id; - + uint8_t app_id; }; /* Function to initialize any dynamic mapper data. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c index 8040fb7515..67fa61fc7c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c @@ -23,13 +23,15 @@ ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig) /* Utility function to calculate the action matcher hash */ static uint32_t -ulp_matcher_action_hash_calculate(uint64_t hi_sig) +ulp_matcher_action_hash_calculate(uint64_t hi_sig, uint64_t app_id) { uint64_t hash; hi_sig |= ((hi_sig % BNXT_ULP_ACT_HID_HIGH_PRIME) << BNXT_ULP_ACT_HID_SHFTL); - hash = hi_sig; + app_id |= ((app_id % BNXT_ULP_CLASS_HID_LOW_PRIME) << + (BNXT_ULP_CLASS_HID_SHFTL + 2)); + hash = hi_sig ^ app_id; hash = (hash >> BNXT_ULP_ACT_HID_SHFTR) & BNXT_ULP_ACT_HID_MASK; return (uint32_t)hash; } @@ -51,7 +53,8 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params, vf_to_vf = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_VF_TO_VF); /* calculate the hash of the given flow */ - class_hid = ulp_matcher_class_hash_calculate(params->hdr_bitmap.bits, + class_hid = ulp_matcher_class_hash_calculate((params->hdr_bitmap.bits ^ + params->app_id), params->fld_s_bitmap.bits); /* validate the calculate hash values */ @@ -70,6 +73,14 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params, BNXT_TF_DBG(DEBUG, "Field signature does not match\n"); goto error; } + + /* Match the application id before proceeding */ + if (params->app_id != class_match->app_sig) { + BNXT_TF_DBG(DEBUG, "Field to match the app id %u:%u\n", + params->app_id, class_match->app_sig); + goto error; + } + if (vf_to_vf != class_match->act_vnic) { BNXT_TF_DBG(DEBUG, "Vnic Match failed\n"); goto error; @@ -101,7 +112,8 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params, struct bnxt_ulp_act_match_info *act_match; /* calculate the hash of the given flow action */ - act_hid = ulp_matcher_action_hash_calculate(params->act_bitmap.bits); + act_hid = ulp_matcher_action_hash_calculate(params->act_bitmap.bits, + params->app_id); /* validate the calculate hash values */ if (act_hid >= BNXT_ULP_ACT_SIG_TBL_MAX_SZ) @@ -115,6 +127,14 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params, BNXT_TF_DBG(DEBUG, "Action Header does not match\n"); goto error; } + + /* Match the application id before proceeding */ + if (params->app_id != act_match->app_sig) { + BNXT_TF_DBG(DEBUG, "Field to match the app id %u:%u\n", + params->app_id, act_match->app_sig); + goto error; + } + *act_id = act_match->act_tid; params->act_pattern_id = act_match->act_pattern_id; BNXT_TF_DBG(DEBUG, "Found matching action template %u\n", *act_id); diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index 500bf215d9..e18f314856 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jan 26 15:51:49 2021 */ +/* date: Wed Mar 17 11:31:19 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -107,6 +107,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [1] = { .act_hid = BNXT_ULP_ACT_HID_0000, .act_pattern_id = 0, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 @@ -114,6 +115,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [2] = { .act_hid = BNXT_ULP_ACT_HID_0001, .act_pattern_id = 1, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -122,6 +124,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [3] = { .act_hid = BNXT_ULP_ACT_HID_0400, .act_pattern_id = 2, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -130,6 +133,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [4] = { .act_hid = BNXT_ULP_ACT_HID_01ab, .act_pattern_id = 3, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -138,6 +142,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [5] = { .act_hid = BNXT_ULP_ACT_HID_0010, .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -146,6 +151,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [6] = { .act_hid = BNXT_ULP_ACT_HID_05ab, .act_pattern_id = 5, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -155,6 +161,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [7] = { .act_hid = BNXT_ULP_ACT_HID_01bb, .act_pattern_id = 6, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -164,6 +171,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [8] = { .act_hid = BNXT_ULP_ACT_HID_0002, .act_pattern_id = 7, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -172,6 +180,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [9] = { .act_hid = BNXT_ULP_ACT_HID_0003, .act_pattern_id = 8, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DROP | @@ -181,6 +190,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [10] = { .act_hid = BNXT_ULP_ACT_HID_0402, .act_pattern_id = 9, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -190,6 +200,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [11] = { .act_hid = BNXT_ULP_ACT_HID_01ad, .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -199,6 +210,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [12] = { .act_hid = BNXT_ULP_ACT_HID_0012, .act_pattern_id = 11, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -208,6 +220,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [13] = { .act_hid = BNXT_ULP_ACT_HID_05ad, .act_pattern_id = 12, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -218,6 +231,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [14] = { .act_hid = BNXT_ULP_ACT_HID_01bd, .act_pattern_id = 13, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -228,6 +242,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [15] = { .act_hid = BNXT_ULP_ACT_HID_0613, .act_pattern_id = 14, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DROP | @@ -237,6 +252,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [16] = { .act_hid = BNXT_ULP_ACT_HID_02a9, .act_pattern_id = 15, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_POP_VLAN | @@ -246,6 +262,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [17] = { .act_hid = BNXT_ULP_ACT_HID_0054, .act_pattern_id = 16, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -255,6 +272,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [18] = { .act_hid = BNXT_ULP_ACT_HID_0622, .act_pattern_id = 17, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -264,6 +282,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [19] = { .act_hid = BNXT_ULP_ACT_HID_0454, .act_pattern_id = 18, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -274,6 +293,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [20] = { .act_hid = BNXT_ULP_ACT_HID_0064, .act_pattern_id = 19, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_VXLAN_DECAP | @@ -284,6 +304,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [21] = { .act_hid = BNXT_ULP_ACT_HID_0614, .act_pattern_id = 20, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -293,6 +314,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [22] = { .act_hid = BNXT_ULP_ACT_HID_0615, .act_pattern_id = 21, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -303,6 +325,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [23] = { .act_hid = BNXT_ULP_ACT_HID_02ab, .act_pattern_id = 22, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -313,6 +336,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [24] = { .act_hid = BNXT_ULP_ACT_HID_0056, .act_pattern_id = 23, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -323,6 +347,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [25] = { .act_hid = BNXT_ULP_ACT_HID_0624, .act_pattern_id = 24, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -333,6 +358,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [26] = { .act_hid = BNXT_ULP_ACT_HID_0456, .act_pattern_id = 25, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -344,6 +370,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [27] = { .act_hid = BNXT_ULP_ACT_HID_0066, .act_pattern_id = 26, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | @@ -355,6 +382,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [28] = { .act_hid = BNXT_ULP_ACT_HID_048d, .act_pattern_id = 0, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED | BNXT_ULP_ACT_BIT_SAMPLE | @@ -364,6 +392,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [29] = { .act_hid = BNXT_ULP_ACT_HID_048f, .act_pattern_id = 1, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED | BNXT_ULP_ACT_BIT_SAMPLE | @@ -374,6 +403,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [30] = { .act_hid = BNXT_ULP_ACT_HID_04bc, .act_pattern_id = 0, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -382,6 +412,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [31] = { .act_hid = BNXT_ULP_ACT_HID_00a9, .act_pattern_id = 1, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -391,6 +422,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [32] = { .act_hid = BNXT_ULP_ACT_HID_020f, .act_pattern_id = 2, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, @@ -399,6 +431,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [33] = { .act_hid = BNXT_ULP_ACT_HID_04a9, .act_pattern_id = 3, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -409,6 +442,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [34] = { .act_hid = BNXT_ULP_ACT_HID_01fc, .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -420,6 +454,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [35] = { .act_hid = BNXT_ULP_ACT_HID_04be, .act_pattern_id = 5, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -429,6 +464,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [36] = { .act_hid = BNXT_ULP_ACT_HID_00ab, .act_pattern_id = 6, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -439,6 +475,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [37] = { .act_hid = BNXT_ULP_ACT_HID_0211, .act_pattern_id = 7, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -448,6 +485,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [38] = { .act_hid = BNXT_ULP_ACT_HID_04ab, .act_pattern_id = 8, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -459,6 +497,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [39] = { .act_hid = BNXT_ULP_ACT_HID_01fe, .act_pattern_id = 9, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -471,6 +510,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [40] = { .act_hid = BNXT_ULP_ACT_HID_0667, .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -480,6 +520,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [41] = { .act_hid = BNXT_ULP_ACT_HID_0254, .act_pattern_id = 11, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -490,6 +531,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [42] = { .act_hid = BNXT_ULP_ACT_HID_03ba, .act_pattern_id = 12, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -499,6 +541,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [43] = { .act_hid = BNXT_ULP_ACT_HID_0654, .act_pattern_id = 13, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -510,6 +553,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [44] = { .act_hid = BNXT_ULP_ACT_HID_03a7, .act_pattern_id = 14, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -522,6 +566,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [45] = { .act_hid = BNXT_ULP_ACT_HID_0669, .act_pattern_id = 15, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -532,6 +577,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [46] = { .act_hid = BNXT_ULP_ACT_HID_0256, .act_pattern_id = 16, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -543,6 +589,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [47] = { .act_hid = BNXT_ULP_ACT_HID_03bc, .act_pattern_id = 17, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -553,6 +600,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [48] = { .act_hid = BNXT_ULP_ACT_HID_0656, .act_pattern_id = 18, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -565,6 +613,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [49] = { .act_hid = BNXT_ULP_ACT_HID_03a9, .act_pattern_id = 19, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -578,6 +627,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [50] = { .act_hid = BNXT_ULP_ACT_HID_021b, .act_pattern_id = 0, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 @@ -585,6 +635,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [51] = { .act_hid = BNXT_ULP_ACT_HID_021c, .act_pattern_id = 1, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -593,6 +644,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [52] = { .act_hid = BNXT_ULP_ACT_HID_021e, .act_pattern_id = 2, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_ACT_BIT_COUNT | @@ -602,6 +654,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [53] = { .act_hid = BNXT_ULP_ACT_HID_063f, .act_pattern_id = 3, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_VLAN_PCP | BNXT_ULP_ACT_BIT_SET_VLAN_VID | @@ -612,6 +665,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [54] = { .act_hid = BNXT_ULP_ACT_HID_0510, .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_VLAN_VID | BNXT_ULP_ACT_BIT_PUSH_VLAN | @@ -621,6 +675,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [55] = { .act_hid = BNXT_ULP_ACT_HID_03c6, .act_pattern_id = 5, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -629,6 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [56] = { .act_hid = BNXT_ULP_ACT_HID_0082, .act_pattern_id = 6, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_VLAN_PCP | @@ -640,6 +696,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [57] = { .act_hid = BNXT_ULP_ACT_HID_06bb, .act_pattern_id = 7, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_VLAN_VID | @@ -650,6 +707,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [58] = { .act_hid = BNXT_ULP_ACT_HID_021d, .act_pattern_id = 8, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -658,6 +716,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [59] = { .act_hid = BNXT_ULP_ACT_HID_0641, .act_pattern_id = 9, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_VLAN_PCP | @@ -669,6 +728,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [60] = { .act_hid = BNXT_ULP_ACT_HID_0512, .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_VLAN_VID | @@ -679,6 +739,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [61] = { .act_hid = BNXT_ULP_ACT_HID_03c8, .act_pattern_id = 11, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -688,6 +749,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [62] = { .act_hid = BNXT_ULP_ACT_HID_0084, .act_pattern_id = 12, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -700,6 +762,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [63] = { .act_hid = BNXT_ULP_ACT_HID_06bd, .act_pattern_id = 13, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | @@ -711,6 +774,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [64] = { .act_hid = BNXT_ULP_ACT_HID_06d7, .act_pattern_id = 0, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -719,6 +783,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [65] = { .act_hid = BNXT_ULP_ACT_HID_02c4, .act_pattern_id = 1, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -728,6 +793,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [66] = { .act_hid = BNXT_ULP_ACT_HID_042a, .act_pattern_id = 2, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -736,6 +802,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [67] = { .act_hid = BNXT_ULP_ACT_HID_06c4, .act_pattern_id = 3, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -746,6 +813,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [68] = { .act_hid = BNXT_ULP_ACT_HID_0417, .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -757,6 +825,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [69] = { .act_hid = BNXT_ULP_ACT_HID_06d9, .act_pattern_id = 5, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -766,6 +835,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [70] = { .act_hid = BNXT_ULP_ACT_HID_02c6, .act_pattern_id = 6, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -776,6 +846,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [71] = { .act_hid = BNXT_ULP_ACT_HID_042c, .act_pattern_id = 7, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -785,6 +856,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [72] = { .act_hid = BNXT_ULP_ACT_HID_06c6, .act_pattern_id = 8, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -796,6 +868,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [73] = { .act_hid = BNXT_ULP_ACT_HID_0419, .act_pattern_id = 9, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -808,6 +881,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [74] = { .act_hid = BNXT_ULP_ACT_HID_0119, .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -817,6 +891,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [75] = { .act_hid = BNXT_ULP_ACT_HID_046f, .act_pattern_id = 11, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -827,6 +902,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [76] = { .act_hid = BNXT_ULP_ACT_HID_05d5, .act_pattern_id = 12, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -836,6 +912,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [77] = { .act_hid = BNXT_ULP_ACT_HID_0106, .act_pattern_id = 13, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -847,6 +924,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [78] = { .act_hid = BNXT_ULP_ACT_HID_05c2, .act_pattern_id = 14, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -859,6 +937,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [79] = { .act_hid = BNXT_ULP_ACT_HID_011b, .act_pattern_id = 15, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -869,6 +948,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [80] = { .act_hid = BNXT_ULP_ACT_HID_0471, .act_pattern_id = 16, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -880,6 +960,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [81] = { .act_hid = BNXT_ULP_ACT_HID_05d7, .act_pattern_id = 17, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -890,6 +971,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [82] = { .act_hid = BNXT_ULP_ACT_HID_0108, .act_pattern_id = 18, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -902,6 +984,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [83] = { .act_hid = BNXT_ULP_ACT_HID_05c4, .act_pattern_id = 19, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | @@ -915,6 +998,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [84] = { .act_hid = BNXT_ULP_ACT_HID_00a2, .act_pattern_id = 0, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_ENCAP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, @@ -923,6 +1007,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [85] = { .act_hid = BNXT_ULP_ACT_HID_00a4, .act_pattern_id = 1, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_ENCAP | BNXT_ULP_ACT_BIT_COUNT | diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index 7be8322b13..9c419f6a15 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Mar 5 12:31:34 2021 */ +/* date: Wed Mar 17 11:31:19 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -712,13 +712,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 4096, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } }, [2] = { .class_hid = BNXT_ULP_CLASS_HID_1df1, @@ -726,14 +727,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 4104, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } }, [3] = { .class_hid = BNXT_ULP_CLASS_HID_3e55, @@ -741,14 +743,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 6144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } }, [4] = { .class_hid = BNXT_ULP_CLASS_HID_0649, @@ -756,15 +759,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 6152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } }, [5] = { .class_hid = BNXT_ULP_CLASS_HID_1011, @@ -772,13 +776,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 16384, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } }, [6] = { .class_hid = BNXT_ULP_CLASS_HID_40e9, @@ -786,14 +791,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 16392, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } }, [7] = { .class_hid = BNXT_ULP_CLASS_HID_3e99, @@ -801,14 +807,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 24576, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } }, [8] = { .class_hid = BNXT_ULP_CLASS_HID_06ad, @@ -816,15 +823,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 24584, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } }, [9] = { .class_hid = BNXT_ULP_CLASS_HID_38c7, @@ -832,14 +840,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32768, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [10] = { .class_hid = BNXT_ULP_CLASS_HID_00fb, @@ -847,15 +856,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32776, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [11] = { .class_hid = BNXT_ULP_CLASS_HID_24d3, @@ -863,15 +873,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32832, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [12] = { .class_hid = BNXT_ULP_CLASS_HID_559b, @@ -879,16 +890,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32840, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [13] = { .class_hid = BNXT_ULP_CLASS_HID_5003, @@ -896,15 +908,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [14] = { .class_hid = BNXT_ULP_CLASS_HID_1837, @@ -912,16 +925,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49160, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [15] = { .class_hid = BNXT_ULP_CLASS_HID_3bef, @@ -929,16 +943,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [16] = { .class_hid = BNXT_ULP_CLASS_HID_0403, @@ -946,17 +961,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [17] = { .class_hid = BNXT_ULP_CLASS_HID_3d3f, @@ -964,14 +980,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131072, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [18] = { .class_hid = BNXT_ULP_CLASS_HID_0543, @@ -979,15 +996,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131080, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [19] = { .class_hid = BNXT_ULP_CLASS_HID_292b, @@ -995,15 +1013,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131136, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [20] = { .class_hid = BNXT_ULP_CLASS_HID_59e3, @@ -1011,16 +1030,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [21] = { .class_hid = BNXT_ULP_CLASS_HID_5d3b, @@ -1028,15 +1048,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196608, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [22] = { .class_hid = BNXT_ULP_CLASS_HID_254f, @@ -1044,16 +1065,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196616, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [23] = { .class_hid = BNXT_ULP_CLASS_HID_4917, @@ -1061,16 +1083,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [24] = { .class_hid = BNXT_ULP_CLASS_HID_113b, @@ -1078,17 +1101,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196680, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [25] = { .class_hid = BNXT_ULP_CLASS_HID_55fd, @@ -1096,14 +1120,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 4096, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } }, [26] = { .class_hid = BNXT_ULP_CLASS_HID_1dd1, @@ -1111,15 +1136,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 4104, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } }, [27] = { .class_hid = BNXT_ULP_CLASS_HID_3e75, @@ -1127,15 +1153,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 6144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } }, [28] = { .class_hid = BNXT_ULP_CLASS_HID_0669, @@ -1143,16 +1170,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 6152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } }, [29] = { .class_hid = BNXT_ULP_CLASS_HID_1ba1, @@ -1160,15 +1188,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 12288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } }, [30] = { .class_hid = BNXT_ULP_CLASS_HID_4c69, @@ -1176,16 +1205,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 12296, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } }, [31] = { .class_hid = BNXT_ULP_CLASS_HID_0439, @@ -1193,16 +1223,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 14336, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } }, [32] = { .class_hid = BNXT_ULP_CLASS_HID_34e1, @@ -1210,17 +1241,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 14344, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } }, [33] = { .class_hid = BNXT_ULP_CLASS_HID_0465, @@ -1228,15 +1260,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 20480, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [34] = { .class_hid = BNXT_ULP_CLASS_HID_352d, @@ -1244,16 +1277,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 20488, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [35] = { .class_hid = BNXT_ULP_CLASS_HID_55b1, @@ -1261,16 +1295,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 22528, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [36] = { .class_hid = BNXT_ULP_CLASS_HID_1da5, @@ -1278,17 +1313,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 22536, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [37] = { .class_hid = BNXT_ULP_CLASS_HID_32fd, @@ -1296,16 +1332,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 28672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [38] = { .class_hid = BNXT_ULP_CLASS_HID_63a5, @@ -1313,17 +1350,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 28680, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [39] = { .class_hid = BNXT_ULP_CLASS_HID_1b75, @@ -1331,17 +1369,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 30720, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [40] = { .class_hid = BNXT_ULP_CLASS_HID_4c3d, @@ -1349,18 +1388,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 30728, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [41] = { .class_hid = BNXT_ULP_CLASS_HID_1031, @@ -1368,14 +1408,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 16384, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } }, [42] = { .class_hid = BNXT_ULP_CLASS_HID_40c9, @@ -1383,15 +1424,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 16392, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } }, [43] = { .class_hid = BNXT_ULP_CLASS_HID_3eb9, @@ -1399,15 +1441,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 24576, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } }, [44] = { .class_hid = BNXT_ULP_CLASS_HID_068d, @@ -1415,16 +1458,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 24584, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } }, [45] = { .class_hid = BNXT_ULP_CLASS_HID_5039, @@ -1432,15 +1476,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } }, [46] = { .class_hid = BNXT_ULP_CLASS_HID_180d, @@ -1448,16 +1493,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 49160, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } }, [47] = { .class_hid = BNXT_ULP_CLASS_HID_15fd, @@ -1465,16 +1511,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 57344, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } }, [48] = { .class_hid = BNXT_ULP_CLASS_HID_46b5, @@ -1482,17 +1529,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 57352, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } }, [49] = { .class_hid = BNXT_ULP_CLASS_HID_303d, @@ -1500,15 +1548,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 81920, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [50] = { .class_hid = BNXT_ULP_CLASS_HID_60f5, @@ -1516,16 +1565,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 81928, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [51] = { .class_hid = BNXT_ULP_CLASS_HID_5ea5, @@ -1533,16 +1583,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 90112, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [52] = { .class_hid = BNXT_ULP_CLASS_HID_2689, @@ -1550,17 +1601,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 90120, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [53] = { .class_hid = BNXT_ULP_CLASS_HID_0771, @@ -1568,16 +1620,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 114688, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [54] = { .class_hid = BNXT_ULP_CLASS_HID_3809, @@ -1585,17 +1638,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 114696, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [55] = { .class_hid = BNXT_ULP_CLASS_HID_35f9, @@ -1603,17 +1657,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 122880, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [56] = { .class_hid = BNXT_ULP_CLASS_HID_66b1, @@ -1621,18 +1676,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 122888, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [57] = { .class_hid = BNXT_ULP_CLASS_HID_559d, @@ -1640,14 +1696,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 4096, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } }, [58] = { .class_hid = BNXT_ULP_CLASS_HID_1db1, @@ -1655,15 +1712,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 4104, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } }, [59] = { .class_hid = BNXT_ULP_CLASS_HID_3e15, @@ -1671,15 +1729,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 6144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } }, [60] = { .class_hid = BNXT_ULP_CLASS_HID_0609, @@ -1687,16 +1746,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 6152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } }, [61] = { .class_hid = BNXT_ULP_CLASS_HID_1bc1, @@ -1704,15 +1764,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 12288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } }, [62] = { .class_hid = BNXT_ULP_CLASS_HID_4c09, @@ -1720,16 +1781,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 12296, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } }, [63] = { .class_hid = BNXT_ULP_CLASS_HID_0459, @@ -1737,16 +1799,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 14336, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } }, [64] = { .class_hid = BNXT_ULP_CLASS_HID_3481, @@ -1754,17 +1817,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 14344, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } }, [65] = { .class_hid = BNXT_ULP_CLASS_HID_0405, @@ -1772,15 +1836,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 20480, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [66] = { .class_hid = BNXT_ULP_CLASS_HID_354d, @@ -1788,16 +1853,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 20488, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [67] = { .class_hid = BNXT_ULP_CLASS_HID_55d1, @@ -1805,16 +1871,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 22528, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [68] = { .class_hid = BNXT_ULP_CLASS_HID_1dc5, @@ -1822,17 +1889,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 22536, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [69] = { .class_hid = BNXT_ULP_CLASS_HID_329d, @@ -1840,16 +1908,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 28672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [70] = { .class_hid = BNXT_ULP_CLASS_HID_63c5, @@ -1857,17 +1926,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 28680, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [71] = { .class_hid = BNXT_ULP_CLASS_HID_1b15, @@ -1875,17 +1945,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 30720, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [72] = { .class_hid = BNXT_ULP_CLASS_HID_4c5d, @@ -1893,18 +1964,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 30728, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [73] = { .class_hid = BNXT_ULP_CLASS_HID_1051, @@ -1912,14 +1984,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 16384, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } }, [74] = { .class_hid = BNXT_ULP_CLASS_HID_40a9, @@ -1927,15 +2000,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 16392, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } }, [75] = { .class_hid = BNXT_ULP_CLASS_HID_3ed9, @@ -1943,15 +2017,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 24576, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } }, [76] = { .class_hid = BNXT_ULP_CLASS_HID_06ed, @@ -1959,16 +2034,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 24584, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } }, [77] = { .class_hid = BNXT_ULP_CLASS_HID_5059, @@ -1976,15 +2052,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } }, [78] = { .class_hid = BNXT_ULP_CLASS_HID_186d, @@ -1992,16 +2069,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 49160, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } }, [79] = { .class_hid = BNXT_ULP_CLASS_HID_159d, @@ -2009,16 +2087,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 57344, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } }, [80] = { .class_hid = BNXT_ULP_CLASS_HID_46d5, @@ -2026,17 +2105,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 57352, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } }, [81] = { .class_hid = BNXT_ULP_CLASS_HID_305d, @@ -2044,15 +2124,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 81920, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [82] = { .class_hid = BNXT_ULP_CLASS_HID_6095, @@ -2060,16 +2141,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 81928, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [83] = { .class_hid = BNXT_ULP_CLASS_HID_5ec5, @@ -2077,16 +2159,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 90112, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [84] = { .class_hid = BNXT_ULP_CLASS_HID_26e9, @@ -2094,17 +2177,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 90120, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [85] = { .class_hid = BNXT_ULP_CLASS_HID_0711, @@ -2112,16 +2196,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 114688, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [86] = { .class_hid = BNXT_ULP_CLASS_HID_3869, @@ -2129,17 +2214,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 114696, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [87] = { .class_hid = BNXT_ULP_CLASS_HID_3599, @@ -2147,17 +2233,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 122880, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [88] = { .class_hid = BNXT_ULP_CLASS_HID_66d1, @@ -2165,18 +2252,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 122888, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [89] = { .class_hid = BNXT_ULP_CLASS_HID_38e7, @@ -2184,6 +2272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32768, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2191,8 +2280,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [90] = { .class_hid = BNXT_ULP_CLASS_HID_00db, @@ -2200,6 +2289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32776, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2207,9 +2297,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [91] = { .class_hid = BNXT_ULP_CLASS_HID_24f3, @@ -2217,6 +2307,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32832, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2224,9 +2315,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [92] = { .class_hid = BNXT_ULP_CLASS_HID_55bb, @@ -2234,6 +2325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32840, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2241,10 +2333,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [93] = { .class_hid = BNXT_ULP_CLASS_HID_5023, @@ -2252,6 +2344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2259,9 +2352,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [94] = { .class_hid = BNXT_ULP_CLASS_HID_1817, @@ -2269,6 +2362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49160, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2276,10 +2370,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [95] = { .class_hid = BNXT_ULP_CLASS_HID_3bcf, @@ -2287,6 +2381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2294,10 +2389,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [96] = { .class_hid = BNXT_ULP_CLASS_HID_0423, @@ -2305,6 +2400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2312,11 +2408,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [97] = { .class_hid = BNXT_ULP_CLASS_HID_58e3, @@ -2324,6 +2420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98304, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2331,9 +2428,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [98] = { .class_hid = BNXT_ULP_CLASS_HID_20d7, @@ -2341,6 +2438,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98312, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2348,10 +2446,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [99] = { .class_hid = BNXT_ULP_CLASS_HID_448f, @@ -2359,6 +2457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98368, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2366,10 +2465,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [100] = { .class_hid = BNXT_ULP_CLASS_HID_0ce3, @@ -2377,6 +2476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98376, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2384,11 +2484,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [101] = { .class_hid = BNXT_ULP_CLASS_HID_076b, @@ -2396,6 +2496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114688, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2403,10 +2504,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [102] = { .class_hid = BNXT_ULP_CLASS_HID_3813, @@ -2414,6 +2515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114696, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2421,11 +2523,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [103] = { .class_hid = BNXT_ULP_CLASS_HID_5bcb, @@ -2433,6 +2535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114752, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2440,11 +2543,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [104] = { .class_hid = BNXT_ULP_CLASS_HID_243f, @@ -2452,6 +2555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114760, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2459,12 +2563,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [105] = { .class_hid = BNXT_ULP_CLASS_HID_144b, @@ -2472,6 +2576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163840, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2479,9 +2584,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [106] = { .class_hid = BNXT_ULP_CLASS_HID_4573, @@ -2489,6 +2594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163848, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2496,10 +2602,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [107] = { .class_hid = BNXT_ULP_CLASS_HID_0057, @@ -2507,6 +2613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163904, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2514,10 +2621,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [108] = { .class_hid = BNXT_ULP_CLASS_HID_311f, @@ -2525,6 +2632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163912, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2532,11 +2640,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [109] = { .class_hid = BNXT_ULP_CLASS_HID_2b87, @@ -2544,6 +2652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2551,10 +2660,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [110] = { .class_hid = BNXT_ULP_CLASS_HID_5c4f, @@ -2562,6 +2671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180232, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2569,11 +2679,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [111] = { .class_hid = BNXT_ULP_CLASS_HID_1793, @@ -2581,6 +2691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2588,11 +2699,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [112] = { .class_hid = BNXT_ULP_CLASS_HID_485b, @@ -2600,6 +2711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180296, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2607,12 +2719,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [113] = { .class_hid = BNXT_ULP_CLASS_HID_3447, @@ -2620,6 +2732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229376, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2627,10 +2740,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [114] = { .class_hid = BNXT_ULP_CLASS_HID_650f, @@ -2638,6 +2751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229384, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2645,11 +2759,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [115] = { .class_hid = BNXT_ULP_CLASS_HID_2053, @@ -2657,6 +2771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229440, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2664,11 +2779,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [116] = { .class_hid = BNXT_ULP_CLASS_HID_511b, @@ -2676,6 +2791,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229448, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2683,12 +2799,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [117] = { .class_hid = BNXT_ULP_CLASS_HID_4b83, @@ -2696,6 +2812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245760, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2703,11 +2820,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [118] = { .class_hid = BNXT_ULP_CLASS_HID_13f7, @@ -2715,6 +2832,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245768, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2722,12 +2840,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [119] = { .class_hid = BNXT_ULP_CLASS_HID_37af, @@ -2735,6 +2853,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245824, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2742,12 +2861,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [120] = { .class_hid = BNXT_ULP_CLASS_HID_6857, @@ -2755,6 +2874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245832, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2762,13 +2882,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [121] = { .class_hid = BNXT_ULP_CLASS_HID_3d1f, @@ -2776,6 +2896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2783,8 +2904,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [122] = { .class_hid = BNXT_ULP_CLASS_HID_0563, @@ -2792,6 +2913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131080, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2799,9 +2921,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [123] = { .class_hid = BNXT_ULP_CLASS_HID_290b, @@ -2809,6 +2931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131136, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2816,9 +2939,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [124] = { .class_hid = BNXT_ULP_CLASS_HID_59c3, @@ -2826,6 +2949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2833,10 +2957,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [125] = { .class_hid = BNXT_ULP_CLASS_HID_5d1b, @@ -2844,6 +2968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196608, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2851,9 +2976,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [126] = { .class_hid = BNXT_ULP_CLASS_HID_256f, @@ -2861,6 +2986,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196616, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2868,10 +2994,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [127] = { .class_hid = BNXT_ULP_CLASS_HID_4937, @@ -2879,6 +3005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2886,10 +3013,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [128] = { .class_hid = BNXT_ULP_CLASS_HID_111b, @@ -2897,6 +3024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196680, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2904,11 +3032,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [129] = { .class_hid = BNXT_ULP_CLASS_HID_5f4b, @@ -2916,6 +3044,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2923,9 +3052,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [130] = { .class_hid = BNXT_ULP_CLASS_HID_275f, @@ -2933,6 +3062,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2940,10 +3070,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [131] = { .class_hid = BNXT_ULP_CLASS_HID_4b67, @@ -2951,6 +3081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393280, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2958,10 +3089,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [132] = { .class_hid = BNXT_ULP_CLASS_HID_134b, @@ -2969,6 +3100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2976,11 +3108,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [133] = { .class_hid = BNXT_ULP_CLASS_HID_1683, @@ -2988,6 +3120,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458752, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -2995,10 +3128,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [134] = { .class_hid = BNXT_ULP_CLASS_HID_475b, @@ -3006,6 +3139,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458760, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3013,11 +3147,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [135] = { .class_hid = BNXT_ULP_CLASS_HID_02bf, @@ -3025,6 +3159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458816, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3032,11 +3167,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [136] = { .class_hid = BNXT_ULP_CLASS_HID_3377, @@ -3044,6 +3179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458824, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3051,12 +3187,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [137] = { .class_hid = BNXT_ULP_CLASS_HID_19db, @@ -3064,6 +3200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655360, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3071,9 +3208,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [138] = { .class_hid = BNXT_ULP_CLASS_HID_4a93, @@ -3081,6 +3218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655368, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3088,10 +3226,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [139] = { .class_hid = BNXT_ULP_CLASS_HID_05f7, @@ -3099,6 +3237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655424, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3106,10 +3245,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [140] = { .class_hid = BNXT_ULP_CLASS_HID_368f, @@ -3117,6 +3256,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655432, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3124,11 +3264,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [141] = { .class_hid = BNXT_ULP_CLASS_HID_39c7, @@ -3136,6 +3276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720896, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3143,10 +3284,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [142] = { .class_hid = BNXT_ULP_CLASS_HID_022b, @@ -3154,6 +3295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720904, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3161,11 +3303,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [143] = { .class_hid = BNXT_ULP_CLASS_HID_25f3, @@ -3173,6 +3315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720960, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3180,11 +3323,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [144] = { .class_hid = BNXT_ULP_CLASS_HID_568b, @@ -3192,6 +3335,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720968, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3199,12 +3343,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [145] = { .class_hid = BNXT_ULP_CLASS_HID_3c37, @@ -3212,6 +3356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917504, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3219,10 +3364,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [146] = { .class_hid = BNXT_ULP_CLASS_HID_041b, @@ -3230,6 +3375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917512, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3237,11 +3383,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [147] = { .class_hid = BNXT_ULP_CLASS_HID_2823, @@ -3249,6 +3395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917568, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3256,11 +3403,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [148] = { .class_hid = BNXT_ULP_CLASS_HID_58fb, @@ -3268,6 +3415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917576, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3275,12 +3423,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [149] = { .class_hid = BNXT_ULP_CLASS_HID_5c33, @@ -3288,6 +3436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983040, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3295,11 +3444,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [150] = { .class_hid = BNXT_ULP_CLASS_HID_2407, @@ -3307,6 +3456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983048, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3314,12 +3464,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [151] = { .class_hid = BNXT_ULP_CLASS_HID_482f, @@ -3327,6 +3477,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983104, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3334,12 +3485,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [152] = { .class_hid = BNXT_ULP_CLASS_HID_1033, @@ -3347,6 +3498,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983112, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3354,13 +3506,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [153] = { .class_hid = BNXT_ULP_CLASS_HID_3887, @@ -3368,6 +3520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32768, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3375,8 +3528,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [154] = { .class_hid = BNXT_ULP_CLASS_HID_00bb, @@ -3384,6 +3537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32776, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3391,9 +3545,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [155] = { .class_hid = BNXT_ULP_CLASS_HID_2493, @@ -3401,6 +3555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32832, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3408,9 +3563,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [156] = { .class_hid = BNXT_ULP_CLASS_HID_55db, @@ -3418,6 +3573,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32840, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3425,10 +3581,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [157] = { .class_hid = BNXT_ULP_CLASS_HID_5043, @@ -3436,6 +3592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3443,9 +3600,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [158] = { .class_hid = BNXT_ULP_CLASS_HID_1877, @@ -3453,6 +3610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49160, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3460,10 +3618,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [159] = { .class_hid = BNXT_ULP_CLASS_HID_3baf, @@ -3471,6 +3629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3478,10 +3637,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [160] = { .class_hid = BNXT_ULP_CLASS_HID_0443, @@ -3489,6 +3648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3496,11 +3656,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [161] = { .class_hid = BNXT_ULP_CLASS_HID_5883, @@ -3508,6 +3668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98304, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3515,9 +3676,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [162] = { .class_hid = BNXT_ULP_CLASS_HID_20b7, @@ -3525,6 +3686,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98312, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3532,10 +3694,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [163] = { .class_hid = BNXT_ULP_CLASS_HID_44ef, @@ -3543,6 +3705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98368, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3550,10 +3713,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [164] = { .class_hid = BNXT_ULP_CLASS_HID_0c83, @@ -3561,6 +3724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98376, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3568,11 +3732,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [165] = { .class_hid = BNXT_ULP_CLASS_HID_070b, @@ -3580,6 +3744,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114688, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3587,10 +3752,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [166] = { .class_hid = BNXT_ULP_CLASS_HID_3873, @@ -3598,6 +3763,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114696, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3605,11 +3771,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [167] = { .class_hid = BNXT_ULP_CLASS_HID_5bab, @@ -3617,6 +3783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114752, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3624,11 +3791,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [168] = { .class_hid = BNXT_ULP_CLASS_HID_245f, @@ -3636,6 +3803,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114760, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3643,12 +3811,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [169] = { .class_hid = BNXT_ULP_CLASS_HID_142b, @@ -3656,6 +3824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163840, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3663,9 +3832,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [170] = { .class_hid = BNXT_ULP_CLASS_HID_4513, @@ -3673,6 +3842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163848, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3680,10 +3850,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [171] = { .class_hid = BNXT_ULP_CLASS_HID_0037, @@ -3691,6 +3861,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163904, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3698,10 +3869,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [172] = { .class_hid = BNXT_ULP_CLASS_HID_317f, @@ -3709,6 +3880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163912, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3716,11 +3888,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [173] = { .class_hid = BNXT_ULP_CLASS_HID_2be7, @@ -3728,6 +3900,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3735,10 +3908,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [174] = { .class_hid = BNXT_ULP_CLASS_HID_5c2f, @@ -3746,6 +3919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180232, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3753,11 +3927,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [175] = { .class_hid = BNXT_ULP_CLASS_HID_17f3, @@ -3765,6 +3939,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3772,11 +3947,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [176] = { .class_hid = BNXT_ULP_CLASS_HID_483b, @@ -3784,6 +3959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180296, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3791,12 +3967,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [177] = { .class_hid = BNXT_ULP_CLASS_HID_3427, @@ -3804,6 +3980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229376, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3811,10 +3988,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [178] = { .class_hid = BNXT_ULP_CLASS_HID_656f, @@ -3822,6 +3999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229384, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3829,11 +4007,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [179] = { .class_hid = BNXT_ULP_CLASS_HID_2033, @@ -3841,6 +4019,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229440, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3848,11 +4027,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [180] = { .class_hid = BNXT_ULP_CLASS_HID_517b, @@ -3860,6 +4039,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229448, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3867,12 +4047,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [181] = { .class_hid = BNXT_ULP_CLASS_HID_4be3, @@ -3880,6 +4060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245760, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3887,11 +4068,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [182] = { .class_hid = BNXT_ULP_CLASS_HID_1397, @@ -3899,6 +4080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245768, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3906,12 +4088,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [183] = { .class_hid = BNXT_ULP_CLASS_HID_37cf, @@ -3919,6 +4101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245824, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3926,12 +4109,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [184] = { .class_hid = BNXT_ULP_CLASS_HID_6837, @@ -3939,6 +4122,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245832, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3946,13 +4130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [185] = { .class_hid = BNXT_ULP_CLASS_HID_3d7f, @@ -3960,6 +4144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131072, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3967,8 +4152,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [186] = { .class_hid = BNXT_ULP_CLASS_HID_0503, @@ -3976,6 +4161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131080, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -3983,9 +4169,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [187] = { .class_hid = BNXT_ULP_CLASS_HID_296b, @@ -3993,6 +4179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131136, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4000,9 +4187,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [188] = { .class_hid = BNXT_ULP_CLASS_HID_59a3, @@ -4010,6 +4197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4017,10 +4205,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [189] = { .class_hid = BNXT_ULP_CLASS_HID_5d7b, @@ -4028,6 +4216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196608, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4035,9 +4224,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [190] = { .class_hid = BNXT_ULP_CLASS_HID_250f, @@ -4045,6 +4234,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196616, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4052,10 +4242,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [191] = { .class_hid = BNXT_ULP_CLASS_HID_4957, @@ -4063,6 +4253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4070,10 +4261,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [192] = { .class_hid = BNXT_ULP_CLASS_HID_117b, @@ -4081,6 +4272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196680, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4088,11 +4280,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [193] = { .class_hid = BNXT_ULP_CLASS_HID_5f2b, @@ -4100,6 +4292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4107,9 +4300,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [194] = { .class_hid = BNXT_ULP_CLASS_HID_273f, @@ -4117,6 +4310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4124,10 +4318,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [195] = { .class_hid = BNXT_ULP_CLASS_HID_4b07, @@ -4135,6 +4329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393280, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4142,10 +4337,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [196] = { .class_hid = BNXT_ULP_CLASS_HID_132b, @@ -4153,6 +4348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4160,11 +4356,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [197] = { .class_hid = BNXT_ULP_CLASS_HID_16e3, @@ -4172,6 +4368,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458752, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4179,10 +4376,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [198] = { .class_hid = BNXT_ULP_CLASS_HID_473b, @@ -4190,6 +4387,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458760, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4197,11 +4395,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [199] = { .class_hid = BNXT_ULP_CLASS_HID_02df, @@ -4209,6 +4407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458816, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4216,11 +4415,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [200] = { .class_hid = BNXT_ULP_CLASS_HID_3317, @@ -4228,6 +4427,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458824, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4235,12 +4435,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [201] = { .class_hid = BNXT_ULP_CLASS_HID_19bb, @@ -4248,6 +4448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655360, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4255,9 +4456,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [202] = { .class_hid = BNXT_ULP_CLASS_HID_4af3, @@ -4265,6 +4466,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655368, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4272,10 +4474,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [203] = { .class_hid = BNXT_ULP_CLASS_HID_0597, @@ -4283,6 +4485,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655424, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4290,10 +4493,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [204] = { .class_hid = BNXT_ULP_CLASS_HID_36ef, @@ -4301,6 +4504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655432, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4308,11 +4512,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [205] = { .class_hid = BNXT_ULP_CLASS_HID_39a7, @@ -4320,6 +4524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720896, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4327,10 +4532,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [206] = { .class_hid = BNXT_ULP_CLASS_HID_024b, @@ -4338,6 +4543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720904, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4345,11 +4551,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [207] = { .class_hid = BNXT_ULP_CLASS_HID_2593, @@ -4357,6 +4563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720960, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4364,11 +4571,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [208] = { .class_hid = BNXT_ULP_CLASS_HID_56eb, @@ -4376,6 +4583,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720968, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4383,12 +4591,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [209] = { .class_hid = BNXT_ULP_CLASS_HID_3c57, @@ -4396,6 +4604,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917504, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4403,10 +4612,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [210] = { .class_hid = BNXT_ULP_CLASS_HID_047b, @@ -4414,6 +4623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917512, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4421,11 +4631,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [211] = { .class_hid = BNXT_ULP_CLASS_HID_2843, @@ -4433,6 +4643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917568, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4440,11 +4651,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [212] = { .class_hid = BNXT_ULP_CLASS_HID_589b, @@ -4452,6 +4663,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917576, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4459,12 +4671,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [213] = { .class_hid = BNXT_ULP_CLASS_HID_5c53, @@ -4472,6 +4684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983040, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4479,11 +4692,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [214] = { .class_hid = BNXT_ULP_CLASS_HID_2467, @@ -4491,6 +4704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983048, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4498,12 +4712,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [215] = { .class_hid = BNXT_ULP_CLASS_HID_484f, @@ -4511,6 +4725,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983104, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4518,12 +4733,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [216] = { .class_hid = BNXT_ULP_CLASS_HID_1053, @@ -4531,6 +4746,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983112, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -4538,13 +4754,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [217] = { .class_hid = BNXT_ULP_CLASS_HID_5ce1, @@ -4552,12 +4768,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 4096, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } }, [218] = { .class_hid = BNXT_ULP_CLASS_HID_4579, @@ -4565,13 +4782,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 6144, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } }, [219] = { .class_hid = BNXT_ULP_CLASS_HID_1735, @@ -4579,12 +4797,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 16384, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } }, [220] = { .class_hid = BNXT_ULP_CLASS_HID_45bd, @@ -4592,13 +4811,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 24576, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } }, [221] = { .class_hid = BNXT_ULP_CLASS_HID_3feb, @@ -4606,13 +4826,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32768, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [222] = { .class_hid = BNXT_ULP_CLASS_HID_2bf7, @@ -4620,14 +4841,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32832, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [223] = { .class_hid = BNXT_ULP_CLASS_HID_5727, @@ -4635,14 +4857,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [224] = { .class_hid = BNXT_ULP_CLASS_HID_4333, @@ -4650,15 +4873,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } }, [225] = { .class_hid = BNXT_ULP_CLASS_HID_4453, @@ -4666,13 +4890,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131072, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [226] = { .class_hid = BNXT_ULP_CLASS_HID_304f, @@ -4680,14 +4905,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131136, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [227] = { .class_hid = BNXT_ULP_CLASS_HID_645f, @@ -4695,14 +4921,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196608, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [228] = { .class_hid = BNXT_ULP_CLASS_HID_504b, @@ -4710,15 +4937,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } }, [229] = { .class_hid = BNXT_ULP_CLASS_HID_5cc1, @@ -4726,13 +4954,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 4096, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } }, [230] = { .class_hid = BNXT_ULP_CLASS_HID_4559, @@ -4740,14 +4969,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 6144, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } }, [231] = { .class_hid = BNXT_ULP_CLASS_HID_2285, @@ -4755,14 +4985,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 12288, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } }, [232] = { .class_hid = BNXT_ULP_CLASS_HID_0b1d, @@ -4770,15 +5001,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 14336, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } }, [233] = { .class_hid = BNXT_ULP_CLASS_HID_0b49, @@ -4786,14 +5018,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 20480, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [234] = { .class_hid = BNXT_ULP_CLASS_HID_5c95, @@ -4801,15 +5034,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 22528, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [235] = { .class_hid = BNXT_ULP_CLASS_HID_39c1, @@ -4817,15 +5051,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 28672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [236] = { .class_hid = BNXT_ULP_CLASS_HID_2259, @@ -4833,16 +5068,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 30720, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } }, [237] = { .class_hid = BNXT_ULP_CLASS_HID_1715, @@ -4850,13 +5086,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 16384, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } }, [238] = { .class_hid = BNXT_ULP_CLASS_HID_459d, @@ -4864,14 +5101,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 24576, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } }, [239] = { .class_hid = BNXT_ULP_CLASS_HID_571d, @@ -4879,14 +5117,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } }, [240] = { .class_hid = BNXT_ULP_CLASS_HID_1cd1, @@ -4894,15 +5133,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 57344, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } }, [241] = { .class_hid = BNXT_ULP_CLASS_HID_3711, @@ -4910,14 +5150,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 81920, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [242] = { .class_hid = BNXT_ULP_CLASS_HID_6599, @@ -4925,15 +5166,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 90112, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [243] = { .class_hid = BNXT_ULP_CLASS_HID_0e55, @@ -4941,15 +5183,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 114688, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [244] = { .class_hid = BNXT_ULP_CLASS_HID_3cdd, @@ -4957,16 +5200,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 122880, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } }, [245] = { .class_hid = BNXT_ULP_CLASS_HID_5ca1, @@ -4974,13 +5218,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 4096, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } }, [246] = { .class_hid = BNXT_ULP_CLASS_HID_4539, @@ -4988,14 +5233,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 6144, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } }, [247] = { .class_hid = BNXT_ULP_CLASS_HID_22e5, @@ -5003,14 +5249,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 12288, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } }, [248] = { .class_hid = BNXT_ULP_CLASS_HID_0b7d, @@ -5018,15 +5265,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 14336, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } }, [249] = { .class_hid = BNXT_ULP_CLASS_HID_0b29, @@ -5034,14 +5282,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 20480, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [250] = { .class_hid = BNXT_ULP_CLASS_HID_5cf5, @@ -5049,15 +5298,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 22528, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [251] = { .class_hid = BNXT_ULP_CLASS_HID_39a1, @@ -5065,15 +5315,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 28672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [252] = { .class_hid = BNXT_ULP_CLASS_HID_2239, @@ -5081,16 +5332,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 30720, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } }, [253] = { .class_hid = BNXT_ULP_CLASS_HID_1775, @@ -5098,13 +5350,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 16384, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } }, [254] = { .class_hid = BNXT_ULP_CLASS_HID_45fd, @@ -5112,14 +5365,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 24576, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } }, [255] = { .class_hid = BNXT_ULP_CLASS_HID_577d, @@ -5127,14 +5381,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } }, [256] = { .class_hid = BNXT_ULP_CLASS_HID_1cb1, @@ -5142,15 +5397,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 57344, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } }, [257] = { .class_hid = BNXT_ULP_CLASS_HID_3771, @@ -5158,14 +5414,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 81920, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [258] = { .class_hid = BNXT_ULP_CLASS_HID_65f9, @@ -5173,15 +5430,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 90112, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [259] = { .class_hid = BNXT_ULP_CLASS_HID_0e35, @@ -5189,15 +5447,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 114688, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [260] = { .class_hid = BNXT_ULP_CLASS_HID_3cbd, @@ -5205,16 +5464,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 122880, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } }, [261] = { .class_hid = BNXT_ULP_CLASS_HID_3fcb, @@ -5222,6 +5482,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32768, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5229,7 +5490,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [262] = { .class_hid = BNXT_ULP_CLASS_HID_2bd7, @@ -5237,6 +5498,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32832, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5244,8 +5506,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [263] = { .class_hid = BNXT_ULP_CLASS_HID_5707, @@ -5253,6 +5515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5260,8 +5523,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [264] = { .class_hid = BNXT_ULP_CLASS_HID_4313, @@ -5269,6 +5532,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5276,9 +5540,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } }, [265] = { .class_hid = BNXT_ULP_CLASS_HID_5fc7, @@ -5286,6 +5550,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98304, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5293,8 +5558,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [266] = { .class_hid = BNXT_ULP_CLASS_HID_4bd3, @@ -5302,6 +5567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98368, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5309,9 +5575,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [267] = { .class_hid = BNXT_ULP_CLASS_HID_0e4f, @@ -5319,6 +5585,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114688, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5326,9 +5593,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [268] = { .class_hid = BNXT_ULP_CLASS_HID_632f, @@ -5336,6 +5603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114752, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5343,10 +5611,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } }, [269] = { .class_hid = BNXT_ULP_CLASS_HID_1baf, @@ -5354,6 +5622,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163840, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5361,8 +5630,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [270] = { .class_hid = BNXT_ULP_CLASS_HID_07bb, @@ -5370,6 +5639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163904, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5377,9 +5647,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [271] = { .class_hid = BNXT_ULP_CLASS_HID_32eb, @@ -5387,6 +5657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180224, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5394,9 +5665,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [272] = { .class_hid = BNXT_ULP_CLASS_HID_1ef7, @@ -5404,6 +5675,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180288, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5411,10 +5683,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [273] = { .class_hid = BNXT_ULP_CLASS_HID_3bab, @@ -5422,6 +5694,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229376, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5429,9 +5702,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [274] = { .class_hid = BNXT_ULP_CLASS_HID_27b7, @@ -5439,6 +5712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229440, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5446,10 +5720,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [275] = { .class_hid = BNXT_ULP_CLASS_HID_52e7, @@ -5457,6 +5731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245760, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5464,10 +5739,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [276] = { .class_hid = BNXT_ULP_CLASS_HID_3ef3, @@ -5475,6 +5750,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245824, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5482,11 +5758,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } }, [277] = { .class_hid = BNXT_ULP_CLASS_HID_4473, @@ -5494,6 +5770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5501,7 +5778,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [278] = { .class_hid = BNXT_ULP_CLASS_HID_306f, @@ -5509,6 +5786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131136, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5516,8 +5794,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [279] = { .class_hid = BNXT_ULP_CLASS_HID_647f, @@ -5525,6 +5803,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196608, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5532,8 +5811,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [280] = { .class_hid = BNXT_ULP_CLASS_HID_506b, @@ -5541,6 +5820,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5548,9 +5828,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } }, [281] = { .class_hid = BNXT_ULP_CLASS_HID_66af, @@ -5558,6 +5838,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5565,8 +5846,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [282] = { .class_hid = BNXT_ULP_CLASS_HID_525b, @@ -5574,6 +5855,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393280, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5581,9 +5863,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [283] = { .class_hid = BNXT_ULP_CLASS_HID_1de7, @@ -5591,6 +5873,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458752, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5598,9 +5881,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [284] = { .class_hid = BNXT_ULP_CLASS_HID_0993, @@ -5608,6 +5891,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458816, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5615,10 +5899,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } }, [285] = { .class_hid = BNXT_ULP_CLASS_HID_213f, @@ -5626,6 +5910,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655360, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5633,8 +5918,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [286] = { .class_hid = BNXT_ULP_CLASS_HID_0d2b, @@ -5642,6 +5927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655424, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5649,9 +5935,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [287] = { .class_hid = BNXT_ULP_CLASS_HID_413b, @@ -5659,6 +5945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720896, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5666,9 +5953,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [288] = { .class_hid = BNXT_ULP_CLASS_HID_2cd7, @@ -5676,6 +5963,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720960, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5683,10 +5971,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [289] = { .class_hid = BNXT_ULP_CLASS_HID_436b, @@ -5694,6 +5982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917504, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5701,9 +5990,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [290] = { .class_hid = BNXT_ULP_CLASS_HID_2f07, @@ -5711,6 +6000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917568, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5718,10 +6008,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [291] = { .class_hid = BNXT_ULP_CLASS_HID_6317, @@ -5729,6 +6019,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983040, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5736,10 +6027,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [292] = { .class_hid = BNXT_ULP_CLASS_HID_4f03, @@ -5747,6 +6038,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983104, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5754,11 +6046,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } }, [293] = { .class_hid = BNXT_ULP_CLASS_HID_3fab, @@ -5766,6 +6058,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32768, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5773,7 +6066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [294] = { .class_hid = BNXT_ULP_CLASS_HID_2bb7, @@ -5781,6 +6074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32832, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5788,8 +6082,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [295] = { .class_hid = BNXT_ULP_CLASS_HID_5767, @@ -5797,6 +6091,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5804,8 +6099,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [296] = { .class_hid = BNXT_ULP_CLASS_HID_4373, @@ -5813,6 +6108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5820,9 +6116,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } }, [297] = { .class_hid = BNXT_ULP_CLASS_HID_5fa7, @@ -5830,6 +6126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98304, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5837,8 +6134,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [298] = { .class_hid = BNXT_ULP_CLASS_HID_4bb3, @@ -5846,6 +6143,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98368, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5853,9 +6151,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [299] = { .class_hid = BNXT_ULP_CLASS_HID_0e2f, @@ -5863,6 +6161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114688, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5870,9 +6169,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [300] = { .class_hid = BNXT_ULP_CLASS_HID_634f, @@ -5880,6 +6179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114752, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5887,10 +6187,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } }, [301] = { .class_hid = BNXT_ULP_CLASS_HID_1bcf, @@ -5898,6 +6198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163840, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5905,8 +6206,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [302] = { .class_hid = BNXT_ULP_CLASS_HID_07db, @@ -5914,6 +6215,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163904, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5921,9 +6223,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [303] = { .class_hid = BNXT_ULP_CLASS_HID_328b, @@ -5931,6 +6233,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180224, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5938,9 +6241,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [304] = { .class_hid = BNXT_ULP_CLASS_HID_1e97, @@ -5948,6 +6251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180288, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5955,10 +6259,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [305] = { .class_hid = BNXT_ULP_CLASS_HID_3bcb, @@ -5966,6 +6270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229376, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5973,9 +6278,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [306] = { .class_hid = BNXT_ULP_CLASS_HID_27d7, @@ -5983,6 +6288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229440, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -5990,10 +6296,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [307] = { .class_hid = BNXT_ULP_CLASS_HID_5287, @@ -6001,6 +6307,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245760, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6008,10 +6315,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [308] = { .class_hid = BNXT_ULP_CLASS_HID_3e93, @@ -6019,6 +6326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245824, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6026,11 +6334,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } }, [309] = { .class_hid = BNXT_ULP_CLASS_HID_4413, @@ -6038,6 +6346,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131072, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6045,7 +6354,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [310] = { .class_hid = BNXT_ULP_CLASS_HID_300f, @@ -6053,6 +6362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131136, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6060,8 +6370,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [311] = { .class_hid = BNXT_ULP_CLASS_HID_641f, @@ -6069,6 +6379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196608, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6076,8 +6387,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [312] = { .class_hid = BNXT_ULP_CLASS_HID_500b, @@ -6085,6 +6396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6092,9 +6404,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } }, [313] = { .class_hid = BNXT_ULP_CLASS_HID_66cf, @@ -6102,6 +6414,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6109,8 +6422,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [314] = { .class_hid = BNXT_ULP_CLASS_HID_523b, @@ -6118,6 +6431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393280, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6125,9 +6439,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [315] = { .class_hid = BNXT_ULP_CLASS_HID_1d87, @@ -6135,6 +6449,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458752, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6142,9 +6457,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [316] = { .class_hid = BNXT_ULP_CLASS_HID_09f3, @@ -6152,6 +6467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458816, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6159,10 +6475,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } }, [317] = { .class_hid = BNXT_ULP_CLASS_HID_215f, @@ -6170,6 +6486,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655360, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6177,8 +6494,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [318] = { .class_hid = BNXT_ULP_CLASS_HID_0d4b, @@ -6186,6 +6503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655424, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6193,9 +6511,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [319] = { .class_hid = BNXT_ULP_CLASS_HID_415b, @@ -6203,6 +6521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720896, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6210,9 +6529,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [320] = { .class_hid = BNXT_ULP_CLASS_HID_2cb7, @@ -6220,6 +6539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720960, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6227,10 +6547,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [321] = { .class_hid = BNXT_ULP_CLASS_HID_430b, @@ -6238,6 +6558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917504, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6245,9 +6566,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [322] = { .class_hid = BNXT_ULP_CLASS_HID_2f67, @@ -6255,6 +6576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917568, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6262,10 +6584,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [323] = { .class_hid = BNXT_ULP_CLASS_HID_6377, @@ -6273,6 +6595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983040, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6280,10 +6603,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [324] = { .class_hid = BNXT_ULP_CLASS_HID_4f63, @@ -6291,6 +6614,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983104, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6298,11 +6622,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } }, [325] = { .class_hid = BNXT_ULP_CLASS_HID_29b5, @@ -6310,13 +6634,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC } }, [326] = { .class_hid = BNXT_ULP_CLASS_HID_29ad, @@ -6324,13 +6649,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC } }, [327] = { .class_hid = BNXT_ULP_CLASS_HID_29b7, @@ -6338,14 +6664,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC } }, [328] = { .class_hid = BNXT_ULP_CLASS_HID_1583, @@ -6353,15 +6680,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 72, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID } }, [329] = { .class_hid = BNXT_ULP_CLASS_HID_29af, @@ -6369,14 +6697,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC } }, [330] = { .class_hid = BNXT_ULP_CLASS_HID_159b, @@ -6384,15 +6713,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 72, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID } }, [331] = { .class_hid = BNXT_ULP_CLASS_HID_2995, @@ -6400,14 +6730,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC } }, [332] = { .class_hid = BNXT_ULP_CLASS_HID_298d, @@ -6415,14 +6746,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC } }, [333] = { .class_hid = BNXT_ULP_CLASS_HID_29f5, @@ -6430,14 +6762,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC } }, [334] = { .class_hid = BNXT_ULP_CLASS_HID_29ed, @@ -6445,14 +6778,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC } }, [335] = { .class_hid = BNXT_ULP_CLASS_HID_2997, @@ -6460,6 +6794,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6467,8 +6802,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC } }, [336] = { .class_hid = BNXT_ULP_CLASS_HID_15a3, @@ -6476,6 +6811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 72, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6483,9 +6819,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID } }, [337] = { .class_hid = BNXT_ULP_CLASS_HID_298f, @@ -6493,6 +6829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6500,8 +6837,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC } }, [338] = { .class_hid = BNXT_ULP_CLASS_HID_15bb, @@ -6509,6 +6846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 72, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6516,9 +6854,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID } }, [339] = { .class_hid = BNXT_ULP_CLASS_HID_29f7, @@ -6526,6 +6864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6533,8 +6872,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC } }, [340] = { .class_hid = BNXT_ULP_CLASS_HID_15c3, @@ -6542,6 +6881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 72, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6549,9 +6889,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID } }, [341] = { .class_hid = BNXT_ULP_CLASS_HID_29ef, @@ -6559,6 +6899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 8, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6566,8 +6907,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC } }, [342] = { .class_hid = BNXT_ULP_CLASS_HID_15db, @@ -6575,6 +6916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 72, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -6582,9 +6924,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID } }, [343] = { .class_hid = BNXT_ULP_CLASS_HID_1151, @@ -6592,6 +6934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 12, .flow_sig_id = 16384, .flow_pattern_id = 3, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | @@ -6599,8 +6942,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_T_VXLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR } }, [344] = { .class_hid = BNXT_ULP_CLASS_HID_315d, @@ -6608,6 +6951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 12, .flow_sig_id = 81920, .flow_pattern_id = 3, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | @@ -6615,9 +6959,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_T_VXLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT } }, [345] = { .class_hid = BNXT_ULP_CLASS_HID_34c6, @@ -6625,13 +6969,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 4096, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } }, [346] = { .class_hid = BNXT_ULP_CLASS_HID_0c22, @@ -6639,14 +6984,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 4100, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } }, [347] = { .class_hid = BNXT_ULP_CLASS_HID_1cbe, @@ -6654,14 +7000,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 6144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } }, [348] = { .class_hid = BNXT_ULP_CLASS_HID_179a, @@ -6669,15 +7016,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 6148, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } }, [349] = { .class_hid = BNXT_ULP_CLASS_HID_59be, @@ -6685,13 +7033,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 16384, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } }, [350] = { .class_hid = BNXT_ULP_CLASS_HID_515a, @@ -6699,14 +7048,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 16388, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } }, [351] = { .class_hid = BNXT_ULP_CLASS_HID_1c72, @@ -6714,14 +7064,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 24576, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } }, [352] = { .class_hid = BNXT_ULP_CLASS_HID_171e, @@ -6729,15 +7080,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 24580, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } }, [353] = { .class_hid = BNXT_ULP_CLASS_HID_19c8, @@ -6745,14 +7097,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32768, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [354] = { .class_hid = BNXT_ULP_CLASS_HID_112c, @@ -6760,15 +7113,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32772, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [355] = { .class_hid = BNXT_ULP_CLASS_HID_4d68, @@ -6776,15 +7130,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32832, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [356] = { .class_hid = BNXT_ULP_CLASS_HID_444c, @@ -6792,16 +7147,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32836, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [357] = { .class_hid = BNXT_ULP_CLASS_HID_0e8c, @@ -6809,15 +7165,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [358] = { .class_hid = BNXT_ULP_CLASS_HID_09e0, @@ -6825,16 +7182,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49156, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [359] = { .class_hid = BNXT_ULP_CLASS_HID_1af0, @@ -6842,16 +7200,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [360] = { .class_hid = BNXT_ULP_CLASS_HID_15d4, @@ -6859,17 +7218,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49220, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [361] = { .class_hid = BNXT_ULP_CLASS_HID_1dd0, @@ -6877,14 +7237,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131072, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [362] = { .class_hid = BNXT_ULP_CLASS_HID_14f4, @@ -6892,15 +7253,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131076, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [363] = { .class_hid = BNXT_ULP_CLASS_HID_70b0, @@ -6908,15 +7270,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131136, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [364] = { .class_hid = BNXT_ULP_CLASS_HID_4854, @@ -6924,16 +7287,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131140, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [365] = { .class_hid = BNXT_ULP_CLASS_HID_3dd4, @@ -6941,15 +7305,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196608, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [366] = { .class_hid = BNXT_ULP_CLASS_HID_34f8, @@ -6957,16 +7322,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196612, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [367] = { .class_hid = BNXT_ULP_CLASS_HID_09e8, @@ -6974,16 +7340,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [368] = { .class_hid = BNXT_ULP_CLASS_HID_008c, @@ -6991,17 +7358,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196676, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [369] = { .class_hid = BNXT_ULP_CLASS_HID_34e6, @@ -7009,14 +7377,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 4096, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } }, [370] = { .class_hid = BNXT_ULP_CLASS_HID_0c02, @@ -7024,15 +7393,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 4100, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } }, [371] = { .class_hid = BNXT_ULP_CLASS_HID_1c9e, @@ -7040,15 +7410,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 6144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } }, [372] = { .class_hid = BNXT_ULP_CLASS_HID_17ba, @@ -7056,16 +7427,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 6148, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } }, [373] = { .class_hid = BNXT_ULP_CLASS_HID_429e, @@ -7073,15 +7445,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 12288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } }, [374] = { .class_hid = BNXT_ULP_CLASS_HID_5dba, @@ -7089,16 +7462,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 12292, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } }, [375] = { .class_hid = BNXT_ULP_CLASS_HID_2a16, @@ -7106,16 +7480,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 14336, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } }, [376] = { .class_hid = BNXT_ULP_CLASS_HID_2532, @@ -7123,17 +7498,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 14340, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } }, [377] = { .class_hid = BNXT_ULP_CLASS_HID_2da2, @@ -7141,15 +7517,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 20480, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [378] = { .class_hid = BNXT_ULP_CLASS_HID_24fe, @@ -7157,16 +7534,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 20484, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [379] = { .class_hid = BNXT_ULP_CLASS_HID_355a, @@ -7174,16 +7552,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 22528, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [380] = { .class_hid = BNXT_ULP_CLASS_HID_0c76, @@ -7191,17 +7570,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 22532, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [381] = { .class_hid = BNXT_ULP_CLASS_HID_13e6, @@ -7209,16 +7589,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 28672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [382] = { .class_hid = BNXT_ULP_CLASS_HID_7276, @@ -7226,17 +7607,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 28676, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [383] = { .class_hid = BNXT_ULP_CLASS_HID_42d2, @@ -7244,17 +7626,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 30720, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [384] = { .class_hid = BNXT_ULP_CLASS_HID_5dee, @@ -7262,18 +7645,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 30724, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [385] = { .class_hid = BNXT_ULP_CLASS_HID_59de, @@ -7281,14 +7665,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 16384, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } }, [386] = { .class_hid = BNXT_ULP_CLASS_HID_513a, @@ -7296,15 +7681,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 16388, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } }, [387] = { .class_hid = BNXT_ULP_CLASS_HID_1c12, @@ -7312,15 +7698,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 24576, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } }, [388] = { .class_hid = BNXT_ULP_CLASS_HID_177e, @@ -7328,16 +7715,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 24580, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } }, [389] = { .class_hid = BNXT_ULP_CLASS_HID_0e92, @@ -7345,15 +7733,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } }, [390] = { .class_hid = BNXT_ULP_CLASS_HID_09fe, @@ -7361,16 +7750,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 49156, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } }, [391] = { .class_hid = BNXT_ULP_CLASS_HID_5c1a, @@ -7378,16 +7768,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 57344, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } }, [392] = { .class_hid = BNXT_ULP_CLASS_HID_5746, @@ -7395,17 +7786,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 57348, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } }, [393] = { .class_hid = BNXT_ULP_CLASS_HID_79da, @@ -7413,15 +7805,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 81920, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [394] = { .class_hid = BNXT_ULP_CLASS_HID_7106, @@ -7429,16 +7822,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 81924, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [395] = { .class_hid = BNXT_ULP_CLASS_HID_3c1e, @@ -7446,16 +7840,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 90112, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [396] = { .class_hid = BNXT_ULP_CLASS_HID_377a, @@ -7463,17 +7858,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 90116, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [397] = { .class_hid = BNXT_ULP_CLASS_HID_2e9e, @@ -7481,16 +7877,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 114688, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [398] = { .class_hid = BNXT_ULP_CLASS_HID_29fa, @@ -7498,17 +7895,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 114692, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [399] = { .class_hid = BNXT_ULP_CLASS_HID_14d2, @@ -7516,17 +7914,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 122880, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [400] = { .class_hid = BNXT_ULP_CLASS_HID_7742, @@ -7534,18 +7933,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 122884, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [401] = { .class_hid = BNXT_ULP_CLASS_HID_3706, @@ -7553,14 +7953,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 4096, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } }, [402] = { .class_hid = BNXT_ULP_CLASS_HID_0fe2, @@ -7568,15 +7969,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 4100, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } }, [403] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e, @@ -7584,15 +7986,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 6144, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } }, [404] = { .class_hid = BNXT_ULP_CLASS_HID_145a, @@ -7600,16 +8003,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 6148, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } }, [405] = { .class_hid = BNXT_ULP_CLASS_HID_417e, @@ -7617,15 +8021,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 12288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } }, [406] = { .class_hid = BNXT_ULP_CLASS_HID_5e5a, @@ -7633,16 +8038,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 12292, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } }, [407] = { .class_hid = BNXT_ULP_CLASS_HID_29f6, @@ -7650,16 +8056,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 14336, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } }, [408] = { .class_hid = BNXT_ULP_CLASS_HID_26d2, @@ -7667,17 +8074,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 14340, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } }, [409] = { .class_hid = BNXT_ULP_CLASS_HID_2e42, @@ -7685,15 +8093,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 20480, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [410] = { .class_hid = BNXT_ULP_CLASS_HID_271e, @@ -7701,16 +8110,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 20484, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [411] = { .class_hid = BNXT_ULP_CLASS_HID_36ba, @@ -7718,16 +8128,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 22528, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [412] = { .class_hid = BNXT_ULP_CLASS_HID_0f96, @@ -7735,17 +8146,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 22532, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [413] = { .class_hid = BNXT_ULP_CLASS_HID_1006, @@ -7753,16 +8165,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 28672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [414] = { .class_hid = BNXT_ULP_CLASS_HID_7196, @@ -7770,17 +8183,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 28676, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [415] = { .class_hid = BNXT_ULP_CLASS_HID_4132, @@ -7788,17 +8202,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 30720, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [416] = { .class_hid = BNXT_ULP_CLASS_HID_5e0e, @@ -7806,18 +8221,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 30724, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [417] = { .class_hid = BNXT_ULP_CLASS_HID_59fe, @@ -7825,14 +8241,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 16384, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } }, [418] = { .class_hid = BNXT_ULP_CLASS_HID_511a, @@ -7840,15 +8257,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 16388, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } }, [419] = { .class_hid = BNXT_ULP_CLASS_HID_1c32, @@ -7856,15 +8274,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 24576, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } }, [420] = { .class_hid = BNXT_ULP_CLASS_HID_175e, @@ -7872,16 +8291,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 24580, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } }, [421] = { .class_hid = BNXT_ULP_CLASS_HID_0eb2, @@ -7889,15 +8309,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } }, [422] = { .class_hid = BNXT_ULP_CLASS_HID_09de, @@ -7905,16 +8326,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 49156, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } }, [423] = { .class_hid = BNXT_ULP_CLASS_HID_5c3a, @@ -7922,16 +8344,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 57344, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } }, [424] = { .class_hid = BNXT_ULP_CLASS_HID_5766, @@ -7939,17 +8362,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 57348, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } }, [425] = { .class_hid = BNXT_ULP_CLASS_HID_79fa, @@ -7957,15 +8381,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 81920, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [426] = { .class_hid = BNXT_ULP_CLASS_HID_7126, @@ -7973,16 +8398,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 81924, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [427] = { .class_hid = BNXT_ULP_CLASS_HID_3c3e, @@ -7990,16 +8416,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 90112, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [428] = { .class_hid = BNXT_ULP_CLASS_HID_375a, @@ -8007,17 +8434,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 90116, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [429] = { .class_hid = BNXT_ULP_CLASS_HID_2ebe, @@ -8025,16 +8453,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 114688, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [430] = { .class_hid = BNXT_ULP_CLASS_HID_29da, @@ -8042,17 +8471,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 114692, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [431] = { .class_hid = BNXT_ULP_CLASS_HID_14f2, @@ -8060,17 +8490,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 122880, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [432] = { .class_hid = BNXT_ULP_CLASS_HID_7762, @@ -8078,18 +8509,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 122884, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [433] = { .class_hid = BNXT_ULP_CLASS_HID_19e8, @@ -8097,6 +8529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32768, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8104,8 +8537,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [434] = { .class_hid = BNXT_ULP_CLASS_HID_110c, @@ -8113,6 +8546,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32772, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8120,9 +8554,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [435] = { .class_hid = BNXT_ULP_CLASS_HID_4d48, @@ -8130,6 +8564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32832, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8137,9 +8572,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [436] = { .class_hid = BNXT_ULP_CLASS_HID_446c, @@ -8147,6 +8582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32836, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8154,10 +8590,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [437] = { .class_hid = BNXT_ULP_CLASS_HID_0eac, @@ -8165,6 +8601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8172,9 +8609,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [438] = { .class_hid = BNXT_ULP_CLASS_HID_09c0, @@ -8182,6 +8619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49156, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8189,10 +8627,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [439] = { .class_hid = BNXT_ULP_CLASS_HID_1ad0, @@ -8200,6 +8638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8207,10 +8646,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [440] = { .class_hid = BNXT_ULP_CLASS_HID_15f4, @@ -8218,6 +8657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49220, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8225,11 +8665,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [441] = { .class_hid = BNXT_ULP_CLASS_HID_39ec, @@ -8237,6 +8677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98304, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8244,9 +8685,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [442] = { .class_hid = BNXT_ULP_CLASS_HID_3100, @@ -8254,6 +8695,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98308, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8261,10 +8703,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [443] = { .class_hid = BNXT_ULP_CLASS_HID_0210, @@ -8272,6 +8714,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98368, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8279,10 +8722,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [444] = { .class_hid = BNXT_ULP_CLASS_HID_1d34, @@ -8290,6 +8733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98372, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8297,11 +8741,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [445] = { .class_hid = BNXT_ULP_CLASS_HID_2ea0, @@ -8309,6 +8753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114688, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8316,10 +8761,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [446] = { .class_hid = BNXT_ULP_CLASS_HID_29c4, @@ -8327,6 +8772,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114692, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8334,11 +8780,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [447] = { .class_hid = BNXT_ULP_CLASS_HID_3ad4, @@ -8346,6 +8792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114752, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8353,11 +8800,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [448] = { .class_hid = BNXT_ULP_CLASS_HID_35e8, @@ -8365,6 +8812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114756, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8372,12 +8820,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [449] = { .class_hid = BNXT_ULP_CLASS_HID_5d80, @@ -8385,6 +8833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163840, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8392,9 +8841,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [450] = { .class_hid = BNXT_ULP_CLASS_HID_54a4, @@ -8402,6 +8851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163844, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8409,10 +8859,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [451] = { .class_hid = BNXT_ULP_CLASS_HID_29b4, @@ -8420,6 +8870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163904, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8427,10 +8878,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [452] = { .class_hid = BNXT_ULP_CLASS_HID_20c8, @@ -8438,6 +8889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163908, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8445,11 +8897,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [453] = { .class_hid = BNXT_ULP_CLASS_HID_7244, @@ -8457,6 +8909,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8464,10 +8917,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [454] = { .class_hid = BNXT_ULP_CLASS_HID_4d98, @@ -8475,6 +8928,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180228, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8482,11 +8936,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [455] = { .class_hid = BNXT_ULP_CLASS_HID_5e68, @@ -8494,6 +8948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8501,11 +8956,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [456] = { .class_hid = BNXT_ULP_CLASS_HID_598c, @@ -8513,6 +8968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180292, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8520,12 +8976,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [457] = { .class_hid = BNXT_ULP_CLASS_HID_1248, @@ -8533,6 +8989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229376, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8540,10 +8997,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [458] = { .class_hid = BNXT_ULP_CLASS_HID_74d8, @@ -8551,6 +9008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229380, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8558,11 +9016,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [459] = { .class_hid = BNXT_ULP_CLASS_HID_49a8, @@ -8570,6 +9028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229440, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8577,11 +9036,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [460] = { .class_hid = BNXT_ULP_CLASS_HID_40cc, @@ -8589,6 +9048,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229444, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8596,12 +9056,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [461] = { .class_hid = BNXT_ULP_CLASS_HID_0b0c, @@ -8609,6 +9069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245760, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8616,11 +9077,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [462] = { .class_hid = BNXT_ULP_CLASS_HID_0220, @@ -8628,6 +9089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245764, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8635,12 +9097,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [463] = { .class_hid = BNXT_ULP_CLASS_HID_1730, @@ -8648,6 +9110,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245824, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8655,12 +9118,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [464] = { .class_hid = BNXT_ULP_CLASS_HID_7980, @@ -8668,6 +9131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245828, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8675,13 +9139,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [465] = { .class_hid = BNXT_ULP_CLASS_HID_1db0, @@ -8689,6 +9153,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8696,8 +9161,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [466] = { .class_hid = BNXT_ULP_CLASS_HID_1494, @@ -8705,6 +9170,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131076, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8712,9 +9178,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [467] = { .class_hid = BNXT_ULP_CLASS_HID_70d0, @@ -8722,6 +9188,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131136, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8729,9 +9196,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [468] = { .class_hid = BNXT_ULP_CLASS_HID_4834, @@ -8739,6 +9206,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131140, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8746,10 +9214,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [469] = { .class_hid = BNXT_ULP_CLASS_HID_3db4, @@ -8757,6 +9225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196608, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8764,9 +9233,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [470] = { .class_hid = BNXT_ULP_CLASS_HID_3498, @@ -8774,6 +9243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196612, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8781,10 +9251,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [471] = { .class_hid = BNXT_ULP_CLASS_HID_0988, @@ -8792,6 +9262,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8799,10 +9270,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [472] = { .class_hid = BNXT_ULP_CLASS_HID_00ec, @@ -8810,6 +9281,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196676, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8817,11 +9289,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [473] = { .class_hid = BNXT_ULP_CLASS_HID_3f44, @@ -8829,6 +9301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8836,9 +9309,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [474] = { .class_hid = BNXT_ULP_CLASS_HID_36a8, @@ -8846,6 +9319,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393220, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8853,10 +9327,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [475] = { .class_hid = BNXT_ULP_CLASS_HID_0b58, @@ -8864,6 +9338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393280, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8871,10 +9346,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [476] = { .class_hid = BNXT_ULP_CLASS_HID_02bc, @@ -8882,6 +9357,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393284, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8889,11 +9365,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [477] = { .class_hid = BNXT_ULP_CLASS_HID_5f48, @@ -8901,6 +9377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458752, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8908,10 +9385,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [478] = { .class_hid = BNXT_ULP_CLASS_HID_56ac, @@ -8919,6 +9396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458756, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8926,11 +9404,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [479] = { .class_hid = BNXT_ULP_CLASS_HID_2b5c, @@ -8938,6 +9416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458816, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8945,11 +9424,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [480] = { .class_hid = BNXT_ULP_CLASS_HID_2280, @@ -8957,6 +9436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458820, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8964,12 +9444,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [481] = { .class_hid = BNXT_ULP_CLASS_HID_4000, @@ -8977,6 +9457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655360, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -8984,9 +9465,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [482] = { .class_hid = BNXT_ULP_CLASS_HID_5b64, @@ -8994,6 +9475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655364, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9001,10 +9483,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [483] = { .class_hid = BNXT_ULP_CLASS_HID_2c14, @@ -9012,6 +9494,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655424, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9019,10 +9502,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [484] = { .class_hid = BNXT_ULP_CLASS_HID_2778, @@ -9030,6 +9513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655428, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9037,11 +9521,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [485] = { .class_hid = BNXT_ULP_CLASS_HID_18f8, @@ -9049,6 +9533,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720896, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9056,10 +9541,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [486] = { .class_hid = BNXT_ULP_CLASS_HID_13dc, @@ -9067,6 +9552,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720900, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9074,11 +9560,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [487] = { .class_hid = BNXT_ULP_CLASS_HID_4c18, @@ -9086,6 +9572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720960, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9093,11 +9580,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [488] = { .class_hid = BNXT_ULP_CLASS_HID_477c, @@ -9105,6 +9592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720964, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9112,12 +9600,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [489] = { .class_hid = BNXT_ULP_CLASS_HID_1a88, @@ -9125,6 +9613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917504, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9132,10 +9621,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [490] = { .class_hid = BNXT_ULP_CLASS_HID_15ec, @@ -9143,6 +9632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917508, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9150,11 +9640,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [491] = { .class_hid = BNXT_ULP_CLASS_HID_4e28, @@ -9162,6 +9652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917568, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9169,11 +9660,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [492] = { .class_hid = BNXT_ULP_CLASS_HID_490c, @@ -9181,6 +9672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917572, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9188,12 +9680,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [493] = { .class_hid = BNXT_ULP_CLASS_HID_3a8c, @@ -9201,6 +9693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983040, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9208,11 +9701,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [494] = { .class_hid = BNXT_ULP_CLASS_HID_35f0, @@ -9220,6 +9713,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983044, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9227,12 +9721,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [495] = { .class_hid = BNXT_ULP_CLASS_HID_06e0, @@ -9240,6 +9734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983104, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9247,12 +9742,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [496] = { .class_hid = BNXT_ULP_CLASS_HID_01c4, @@ -9260,6 +9755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983108, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9267,13 +9763,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [497] = { .class_hid = BNXT_ULP_CLASS_HID_1a08, @@ -9281,6 +9777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32768, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9288,8 +9785,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [498] = { .class_hid = BNXT_ULP_CLASS_HID_12ec, @@ -9297,6 +9794,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32772, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9304,9 +9802,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [499] = { .class_hid = BNXT_ULP_CLASS_HID_4ea8, @@ -9314,6 +9812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32832, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9321,9 +9820,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [500] = { .class_hid = BNXT_ULP_CLASS_HID_478c, @@ -9331,6 +9830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32836, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9338,10 +9838,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [501] = { .class_hid = BNXT_ULP_CLASS_HID_0d4c, @@ -9349,6 +9849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49152, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9356,9 +9857,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [502] = { .class_hid = BNXT_ULP_CLASS_HID_0a20, @@ -9366,6 +9867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49156, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9373,10 +9875,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [503] = { .class_hid = BNXT_ULP_CLASS_HID_1930, @@ -9384,6 +9886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9391,10 +9894,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [504] = { .class_hid = BNXT_ULP_CLASS_HID_1614, @@ -9402,6 +9905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49220, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9409,11 +9913,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [505] = { .class_hid = BNXT_ULP_CLASS_HID_3a0c, @@ -9421,6 +9925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98304, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9428,9 +9933,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [506] = { .class_hid = BNXT_ULP_CLASS_HID_32e0, @@ -9438,6 +9943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98308, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9445,10 +9951,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [507] = { .class_hid = BNXT_ULP_CLASS_HID_01f0, @@ -9456,6 +9962,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98368, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9463,10 +9970,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [508] = { .class_hid = BNXT_ULP_CLASS_HID_1ed4, @@ -9474,6 +9981,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98372, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9481,11 +9989,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [509] = { .class_hid = BNXT_ULP_CLASS_HID_2d40, @@ -9493,6 +10001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114688, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9500,10 +10009,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [510] = { .class_hid = BNXT_ULP_CLASS_HID_2a24, @@ -9511,6 +10020,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114692, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9518,11 +10028,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [511] = { .class_hid = BNXT_ULP_CLASS_HID_3934, @@ -9530,6 +10040,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114752, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9537,11 +10048,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [512] = { .class_hid = BNXT_ULP_CLASS_HID_3608, @@ -9549,6 +10060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114756, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9556,12 +10068,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [513] = { .class_hid = BNXT_ULP_CLASS_HID_5e60, @@ -9569,6 +10081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163840, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9576,9 +10089,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [514] = { .class_hid = BNXT_ULP_CLASS_HID_5744, @@ -9586,6 +10099,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163844, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9593,10 +10107,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [515] = { .class_hid = BNXT_ULP_CLASS_HID_2a54, @@ -9604,6 +10118,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163904, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9611,10 +10126,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [516] = { .class_hid = BNXT_ULP_CLASS_HID_2328, @@ -9622,6 +10137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163908, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9629,11 +10145,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [517] = { .class_hid = BNXT_ULP_CLASS_HID_71a4, @@ -9641,6 +10157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180224, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9648,10 +10165,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [518] = { .class_hid = BNXT_ULP_CLASS_HID_4e78, @@ -9659,6 +10176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180228, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9666,11 +10184,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [519] = { .class_hid = BNXT_ULP_CLASS_HID_5d88, @@ -9678,6 +10196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180288, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9685,11 +10204,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [520] = { .class_hid = BNXT_ULP_CLASS_HID_5a6c, @@ -9697,6 +10216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180292, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9704,12 +10224,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [521] = { .class_hid = BNXT_ULP_CLASS_HID_11a8, @@ -9717,6 +10237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229376, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9724,10 +10245,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [522] = { .class_hid = BNXT_ULP_CLASS_HID_7738, @@ -9735,6 +10256,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229380, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9742,11 +10264,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [523] = { .class_hid = BNXT_ULP_CLASS_HID_4a48, @@ -9754,6 +10276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229440, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9761,11 +10284,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [524] = { .class_hid = BNXT_ULP_CLASS_HID_432c, @@ -9773,6 +10296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229444, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9780,12 +10304,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [525] = { .class_hid = BNXT_ULP_CLASS_HID_08ec, @@ -9793,6 +10317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245760, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9800,11 +10325,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [526] = { .class_hid = BNXT_ULP_CLASS_HID_01c0, @@ -9812,6 +10337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245764, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9819,12 +10345,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [527] = { .class_hid = BNXT_ULP_CLASS_HID_14d0, @@ -9832,6 +10358,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245824, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9839,12 +10366,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [528] = { .class_hid = BNXT_ULP_CLASS_HID_7a60, @@ -9852,6 +10379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245828, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9859,13 +10387,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [529] = { .class_hid = BNXT_ULP_CLASS_HID_1d90, @@ -9873,6 +10401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131072, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9880,8 +10409,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [530] = { .class_hid = BNXT_ULP_CLASS_HID_14b4, @@ -9889,6 +10418,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131076, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9896,9 +10426,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [531] = { .class_hid = BNXT_ULP_CLASS_HID_70f0, @@ -9906,6 +10436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131136, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9913,9 +10444,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [532] = { .class_hid = BNXT_ULP_CLASS_HID_4814, @@ -9923,6 +10454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131140, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9930,10 +10462,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [533] = { .class_hid = BNXT_ULP_CLASS_HID_3d94, @@ -9941,6 +10473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196608, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9948,9 +10481,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [534] = { .class_hid = BNXT_ULP_CLASS_HID_34b8, @@ -9958,6 +10491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196612, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9965,10 +10499,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [535] = { .class_hid = BNXT_ULP_CLASS_HID_09a8, @@ -9976,6 +10510,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196672, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -9983,10 +10518,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [536] = { .class_hid = BNXT_ULP_CLASS_HID_00cc, @@ -9994,6 +10529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196676, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10001,11 +10537,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [537] = { .class_hid = BNXT_ULP_CLASS_HID_3f64, @@ -10013,6 +10549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393216, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10020,9 +10557,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [538] = { .class_hid = BNXT_ULP_CLASS_HID_3688, @@ -10030,6 +10567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393220, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10037,10 +10575,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [539] = { .class_hid = BNXT_ULP_CLASS_HID_0b78, @@ -10048,6 +10586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393280, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10055,10 +10594,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [540] = { .class_hid = BNXT_ULP_CLASS_HID_029c, @@ -10066,6 +10605,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393284, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10073,11 +10613,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [541] = { .class_hid = BNXT_ULP_CLASS_HID_5f68, @@ -10085,6 +10625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458752, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10092,10 +10633,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [542] = { .class_hid = BNXT_ULP_CLASS_HID_568c, @@ -10103,6 +10644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458756, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10110,11 +10652,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [543] = { .class_hid = BNXT_ULP_CLASS_HID_2b7c, @@ -10122,6 +10664,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458816, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10129,11 +10672,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [544] = { .class_hid = BNXT_ULP_CLASS_HID_22a0, @@ -10141,6 +10684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458820, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10148,12 +10692,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [545] = { .class_hid = BNXT_ULP_CLASS_HID_4020, @@ -10161,6 +10705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655360, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10168,9 +10713,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [546] = { .class_hid = BNXT_ULP_CLASS_HID_5b44, @@ -10178,6 +10723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655364, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10185,10 +10731,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [547] = { .class_hid = BNXT_ULP_CLASS_HID_2c34, @@ -10196,6 +10742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655424, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10203,10 +10750,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [548] = { .class_hid = BNXT_ULP_CLASS_HID_2758, @@ -10214,6 +10761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655428, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10221,11 +10769,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [549] = { .class_hid = BNXT_ULP_CLASS_HID_18d8, @@ -10233,6 +10781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720896, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10240,10 +10789,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [550] = { .class_hid = BNXT_ULP_CLASS_HID_13fc, @@ -10251,6 +10800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720900, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10258,11 +10808,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [551] = { .class_hid = BNXT_ULP_CLASS_HID_4c38, @@ -10270,6 +10820,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720960, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10277,11 +10828,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [552] = { .class_hid = BNXT_ULP_CLASS_HID_475c, @@ -10289,6 +10840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720964, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10296,12 +10848,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [553] = { .class_hid = BNXT_ULP_CLASS_HID_1aa8, @@ -10309,6 +10861,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917504, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10316,10 +10869,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [554] = { .class_hid = BNXT_ULP_CLASS_HID_15cc, @@ -10327,6 +10880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917508, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10334,11 +10888,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [555] = { .class_hid = BNXT_ULP_CLASS_HID_4e08, @@ -10346,6 +10900,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917568, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10353,11 +10908,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [556] = { .class_hid = BNXT_ULP_CLASS_HID_492c, @@ -10365,6 +10920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917572, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10372,12 +10928,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [557] = { .class_hid = BNXT_ULP_CLASS_HID_3aac, @@ -10385,6 +10941,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983040, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10392,11 +10949,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [558] = { .class_hid = BNXT_ULP_CLASS_HID_35d0, @@ -10404,6 +10961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983044, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10411,12 +10969,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [559] = { .class_hid = BNXT_ULP_CLASS_HID_06c0, @@ -10424,6 +10982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983104, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10431,12 +10990,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [560] = { .class_hid = BNXT_ULP_CLASS_HID_01e4, @@ -10444,6 +11003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983108, .flow_pattern_id = 0, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -10451,13 +11011,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [561] = { .class_hid = BNXT_ULP_CLASS_HID_4d32, @@ -10465,12 +11025,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 4096, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } }, [562] = { .class_hid = BNXT_ULP_CLASS_HID_54aa, @@ -10478,13 +11039,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 6144, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } }, [563] = { .class_hid = BNXT_ULP_CLASS_HID_0686, @@ -10492,12 +11054,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 16384, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } }, [564] = { .class_hid = BNXT_ULP_CLASS_HID_540e, @@ -10505,13 +11068,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 24576, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } }, [565] = { .class_hid = BNXT_ULP_CLASS_HID_2e3c, @@ -10519,13 +11083,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32768, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [566] = { .class_hid = BNXT_ULP_CLASS_HID_3a20, @@ -10533,14 +11098,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 32832, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [567] = { .class_hid = BNXT_ULP_CLASS_HID_46f0, @@ -10548,14 +11114,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [568] = { .class_hid = BNXT_ULP_CLASS_HID_52e4, @@ -10563,15 +11130,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 49216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } }, [569] = { .class_hid = BNXT_ULP_CLASS_HID_55e4, @@ -10579,13 +11147,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131072, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [570] = { .class_hid = BNXT_ULP_CLASS_HID_21f8, @@ -10593,14 +11162,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 131136, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [571] = { .class_hid = BNXT_ULP_CLASS_HID_75e8, @@ -10608,14 +11178,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196608, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [572] = { .class_hid = BNXT_ULP_CLASS_HID_41fc, @@ -10623,15 +11194,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 196672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } }, [573] = { .class_hid = BNXT_ULP_CLASS_HID_4d12, @@ -10639,13 +11211,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 4096, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } }, [574] = { .class_hid = BNXT_ULP_CLASS_HID_548a, @@ -10653,14 +11226,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 6144, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } }, [575] = { .class_hid = BNXT_ULP_CLASS_HID_3356, @@ -10668,14 +11242,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 12288, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } }, [576] = { .class_hid = BNXT_ULP_CLASS_HID_1ace, @@ -10683,15 +11258,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 14336, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } }, [577] = { .class_hid = BNXT_ULP_CLASS_HID_1a9a, @@ -10699,14 +11275,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 20480, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [578] = { .class_hid = BNXT_ULP_CLASS_HID_4d46, @@ -10714,15 +11291,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 22528, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [579] = { .class_hid = BNXT_ULP_CLASS_HID_2812, @@ -10730,15 +11308,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 28672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [580] = { .class_hid = BNXT_ULP_CLASS_HID_338a, @@ -10746,16 +11325,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 30720, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } }, [581] = { .class_hid = BNXT_ULP_CLASS_HID_06e6, @@ -10763,13 +11343,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 16384, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } }, [582] = { .class_hid = BNXT_ULP_CLASS_HID_546e, @@ -10777,14 +11358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 24576, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } }, [583] = { .class_hid = BNXT_ULP_CLASS_HID_46ee, @@ -10792,14 +11374,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } }, [584] = { .class_hid = BNXT_ULP_CLASS_HID_0d22, @@ -10807,15 +11390,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 57344, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } }, [585] = { .class_hid = BNXT_ULP_CLASS_HID_26e2, @@ -10823,14 +11407,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 81920, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [586] = { .class_hid = BNXT_ULP_CLASS_HID_746a, @@ -10838,15 +11423,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 90112, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [587] = { .class_hid = BNXT_ULP_CLASS_HID_1fa6, @@ -10854,15 +11440,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 114688, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [588] = { .class_hid = BNXT_ULP_CLASS_HID_2d2e, @@ -10870,16 +11457,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 122880, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } }, [589] = { .class_hid = BNXT_ULP_CLASS_HID_4ef2, @@ -10887,13 +11475,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 4096, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } }, [590] = { .class_hid = BNXT_ULP_CLASS_HID_576a, @@ -10901,14 +11490,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 6144, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } }, [591] = { .class_hid = BNXT_ULP_CLASS_HID_30b6, @@ -10916,14 +11506,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 12288, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } }, [592] = { .class_hid = BNXT_ULP_CLASS_HID_192e, @@ -10931,15 +11522,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 14336, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } }, [593] = { .class_hid = BNXT_ULP_CLASS_HID_197a, @@ -10947,14 +11539,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 20480, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [594] = { .class_hid = BNXT_ULP_CLASS_HID_4ea6, @@ -10962,15 +11555,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 22528, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [595] = { .class_hid = BNXT_ULP_CLASS_HID_2bf2, @@ -10978,15 +11572,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 28672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [596] = { .class_hid = BNXT_ULP_CLASS_HID_306a, @@ -10994,16 +11589,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 30720, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } }, [597] = { .class_hid = BNXT_ULP_CLASS_HID_06c6, @@ -11011,13 +11607,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 16384, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } }, [598] = { .class_hid = BNXT_ULP_CLASS_HID_544e, @@ -11025,14 +11622,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 24576, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } }, [599] = { .class_hid = BNXT_ULP_CLASS_HID_46ce, @@ -11040,14 +11638,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } }, [600] = { .class_hid = BNXT_ULP_CLASS_HID_0d02, @@ -11055,15 +11654,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 57344, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } }, [601] = { .class_hid = BNXT_ULP_CLASS_HID_26c2, @@ -11071,14 +11671,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 81920, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [602] = { .class_hid = BNXT_ULP_CLASS_HID_744a, @@ -11086,15 +11687,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 90112, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [603] = { .class_hid = BNXT_ULP_CLASS_HID_1f86, @@ -11102,15 +11704,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 114688, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [604] = { .class_hid = BNXT_ULP_CLASS_HID_2d0e, @@ -11118,16 +11721,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 122880, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } }, [605] = { .class_hid = BNXT_ULP_CLASS_HID_2e1c, @@ -11135,6 +11739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32768, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11142,7 +11747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [606] = { .class_hid = BNXT_ULP_CLASS_HID_3a00, @@ -11150,6 +11755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 32832, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11157,8 +11763,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [607] = { .class_hid = BNXT_ULP_CLASS_HID_46d0, @@ -11166,6 +11772,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11173,8 +11780,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [608] = { .class_hid = BNXT_ULP_CLASS_HID_52c4, @@ -11182,6 +11789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11189,9 +11797,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } }, [609] = { .class_hid = BNXT_ULP_CLASS_HID_4e10, @@ -11199,6 +11807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98304, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11206,8 +11815,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [610] = { .class_hid = BNXT_ULP_CLASS_HID_5a04, @@ -11215,6 +11824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 98368, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11222,9 +11832,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [611] = { .class_hid = BNXT_ULP_CLASS_HID_1f98, @@ -11232,6 +11842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114688, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11239,9 +11850,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [612] = { .class_hid = BNXT_ULP_CLASS_HID_72f8, @@ -11249,6 +11860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 114752, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11256,10 +11868,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } }, [613] = { .class_hid = BNXT_ULP_CLASS_HID_0a78, @@ -11267,6 +11879,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163840, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11274,8 +11887,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [614] = { .class_hid = BNXT_ULP_CLASS_HID_166c, @@ -11283,6 +11896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 163904, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11290,9 +11904,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [615] = { .class_hid = BNXT_ULP_CLASS_HID_233c, @@ -11300,6 +11914,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180224, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11307,9 +11922,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [616] = { .class_hid = BNXT_ULP_CLASS_HID_0f20, @@ -11317,6 +11932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 180288, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11324,10 +11940,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [617] = { .class_hid = BNXT_ULP_CLASS_HID_2a7c, @@ -11335,6 +11951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229376, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11342,9 +11959,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [618] = { .class_hid = BNXT_ULP_CLASS_HID_3660, @@ -11352,6 +11969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 229440, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11359,10 +11977,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [619] = { .class_hid = BNXT_ULP_CLASS_HID_4330, @@ -11370,6 +11988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245760, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11377,10 +11996,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [620] = { .class_hid = BNXT_ULP_CLASS_HID_2f24, @@ -11388,6 +12007,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 245824, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11395,11 +12015,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } }, [621] = { .class_hid = BNXT_ULP_CLASS_HID_5584, @@ -11407,6 +12027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11414,7 +12035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [622] = { .class_hid = BNXT_ULP_CLASS_HID_2198, @@ -11422,6 +12043,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 131136, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11429,8 +12051,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [623] = { .class_hid = BNXT_ULP_CLASS_HID_7588, @@ -11438,6 +12060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196608, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11445,8 +12068,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [624] = { .class_hid = BNXT_ULP_CLASS_HID_419c, @@ -11454,6 +12077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 196672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11461,9 +12085,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } }, [625] = { .class_hid = BNXT_ULP_CLASS_HID_7758, @@ -11471,6 +12095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11478,8 +12103,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [626] = { .class_hid = BNXT_ULP_CLASS_HID_43ac, @@ -11487,6 +12112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 393280, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11494,9 +12120,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [627] = { .class_hid = BNXT_ULP_CLASS_HID_0c10, @@ -11504,6 +12130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458752, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11511,9 +12138,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [628] = { .class_hid = BNXT_ULP_CLASS_HID_1864, @@ -11521,6 +12148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 458816, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11528,10 +12156,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } }, [629] = { .class_hid = BNXT_ULP_CLASS_HID_30c8, @@ -11539,6 +12167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655360, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11546,8 +12175,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [630] = { .class_hid = BNXT_ULP_CLASS_HID_1cdc, @@ -11555,6 +12184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 655424, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11562,9 +12192,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [631] = { .class_hid = BNXT_ULP_CLASS_HID_50cc, @@ -11572,6 +12202,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720896, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11579,9 +12210,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [632] = { .class_hid = BNXT_ULP_CLASS_HID_3d20, @@ -11589,6 +12220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 720960, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11596,10 +12228,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [633] = { .class_hid = BNXT_ULP_CLASS_HID_529c, @@ -11607,6 +12239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917504, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11614,9 +12247,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [634] = { .class_hid = BNXT_ULP_CLASS_HID_3ef0, @@ -11624,6 +12257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 917568, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11631,10 +12265,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [635] = { .class_hid = BNXT_ULP_CLASS_HID_72e0, @@ -11642,6 +12276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983040, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11649,10 +12284,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [636] = { .class_hid = BNXT_ULP_CLASS_HID_5ef4, @@ -11660,6 +12295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 983104, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11667,11 +12303,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } }, [637] = { .class_hid = BNXT_ULP_CLASS_HID_2dfc, @@ -11679,6 +12315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32768, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11686,7 +12323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [638] = { .class_hid = BNXT_ULP_CLASS_HID_39e0, @@ -11694,6 +12331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 32832, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11701,8 +12339,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [639] = { .class_hid = BNXT_ULP_CLASS_HID_4530, @@ -11710,6 +12348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49152, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11717,8 +12356,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [640] = { .class_hid = BNXT_ULP_CLASS_HID_5124, @@ -11726,6 +12365,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 49216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11733,9 +12373,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } }, [641] = { .class_hid = BNXT_ULP_CLASS_HID_4df0, @@ -11743,6 +12383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98304, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11750,8 +12391,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [642] = { .class_hid = BNXT_ULP_CLASS_HID_59e4, @@ -11759,6 +12400,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 98368, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11766,9 +12408,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [643] = { .class_hid = BNXT_ULP_CLASS_HID_1c78, @@ -11776,6 +12418,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114688, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11783,9 +12426,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [644] = { .class_hid = BNXT_ULP_CLASS_HID_7118, @@ -11793,6 +12436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 114752, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11800,10 +12444,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } }, [645] = { .class_hid = BNXT_ULP_CLASS_HID_0998, @@ -11811,6 +12455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163840, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11818,8 +12463,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [646] = { .class_hid = BNXT_ULP_CLASS_HID_158c, @@ -11827,6 +12472,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 163904, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11834,9 +12480,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [647] = { .class_hid = BNXT_ULP_CLASS_HID_20dc, @@ -11844,6 +12490,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180224, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11851,9 +12498,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [648] = { .class_hid = BNXT_ULP_CLASS_HID_0cc0, @@ -11861,6 +12508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 180288, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11868,10 +12516,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [649] = { .class_hid = BNXT_ULP_CLASS_HID_299c, @@ -11879,6 +12527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229376, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11886,9 +12535,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [650] = { .class_hid = BNXT_ULP_CLASS_HID_3580, @@ -11896,6 +12545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 229440, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11903,10 +12553,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [651] = { .class_hid = BNXT_ULP_CLASS_HID_40d0, @@ -11914,6 +12564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245760, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11921,10 +12572,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [652] = { .class_hid = BNXT_ULP_CLASS_HID_2cc4, @@ -11932,6 +12583,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 245824, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11939,11 +12591,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } }, [653] = { .class_hid = BNXT_ULP_CLASS_HID_55a4, @@ -11951,6 +12603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131072, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11958,7 +12611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [654] = { .class_hid = BNXT_ULP_CLASS_HID_21b8, @@ -11966,6 +12619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 131136, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11973,8 +12627,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [655] = { .class_hid = BNXT_ULP_CLASS_HID_75a8, @@ -11982,6 +12636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196608, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -11989,8 +12644,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [656] = { .class_hid = BNXT_ULP_CLASS_HID_41bc, @@ -11998,6 +12653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 196672, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12005,9 +12661,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } }, [657] = { .class_hid = BNXT_ULP_CLASS_HID_7778, @@ -12015,6 +12671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393216, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12022,8 +12679,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [658] = { .class_hid = BNXT_ULP_CLASS_HID_438c, @@ -12031,6 +12688,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 393280, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12038,9 +12696,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [659] = { .class_hid = BNXT_ULP_CLASS_HID_0c30, @@ -12048,6 +12706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458752, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12055,9 +12714,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [660] = { .class_hid = BNXT_ULP_CLASS_HID_1844, @@ -12065,6 +12724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 458816, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12072,10 +12732,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } }, [661] = { .class_hid = BNXT_ULP_CLASS_HID_30e8, @@ -12083,6 +12743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655360, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12090,8 +12751,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [662] = { .class_hid = BNXT_ULP_CLASS_HID_1cfc, @@ -12099,6 +12760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 655424, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12106,9 +12768,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [663] = { .class_hid = BNXT_ULP_CLASS_HID_50ec, @@ -12116,6 +12778,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720896, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12123,9 +12786,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [664] = { .class_hid = BNXT_ULP_CLASS_HID_3d00, @@ -12133,6 +12796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 720960, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12140,10 +12804,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [665] = { .class_hid = BNXT_ULP_CLASS_HID_52bc, @@ -12151,6 +12815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917504, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12158,9 +12823,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [666] = { .class_hid = BNXT_ULP_CLASS_HID_3ed0, @@ -12168,6 +12833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 917568, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12175,10 +12841,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [667] = { .class_hid = BNXT_ULP_CLASS_HID_72c0, @@ -12186,6 +12852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983040, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12193,10 +12860,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [668] = { .class_hid = BNXT_ULP_CLASS_HID_5ed4, @@ -12204,6 +12871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 983104, .flow_pattern_id = 1, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12211,11 +12879,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } }, [669] = { .class_hid = BNXT_ULP_CLASS_HID_3866, @@ -12223,13 +12891,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 0, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC } }, [670] = { .class_hid = BNXT_ULP_CLASS_HID_381e, @@ -12237,13 +12906,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 1, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC } }, [671] = { .class_hid = BNXT_ULP_CLASS_HID_3860, @@ -12251,14 +12921,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC } }, [672] = { .class_hid = BNXT_ULP_CLASS_HID_0454, @@ -12266,15 +12937,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 2, .flow_sig_id = 68, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID } }, [673] = { .class_hid = BNXT_ULP_CLASS_HID_3818, @@ -12282,14 +12954,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC } }, [674] = { .class_hid = BNXT_ULP_CLASS_HID_042c, @@ -12297,15 +12970,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 3, .flow_sig_id = 68, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID } }, [675] = { .class_hid = BNXT_ULP_CLASS_HID_3846, @@ -12313,14 +12987,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 4, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC } }, [676] = { .class_hid = BNXT_ULP_CLASS_HID_387e, @@ -12328,14 +13003,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 5, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC } }, [677] = { .class_hid = BNXT_ULP_CLASS_HID_3ba6, @@ -12343,14 +13019,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 6, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC } }, [678] = { .class_hid = BNXT_ULP_CLASS_HID_385e, @@ -12358,14 +13035,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 7, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC } }, [679] = { .class_hid = BNXT_ULP_CLASS_HID_3840, @@ -12373,6 +13051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12380,8 +13059,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC } }, [680] = { .class_hid = BNXT_ULP_CLASS_HID_0474, @@ -12389,6 +13068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 8, .flow_sig_id = 68, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12396,9 +13076,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID } }, [681] = { .class_hid = BNXT_ULP_CLASS_HID_3878, @@ -12406,6 +13086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12413,8 +13094,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC } }, [682] = { .class_hid = BNXT_ULP_CLASS_HID_044c, @@ -12422,6 +13103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 9, .flow_sig_id = 68, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12429,9 +13111,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID } }, [683] = { .class_hid = BNXT_ULP_CLASS_HID_3ba0, @@ -12439,6 +13121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12446,8 +13129,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC } }, [684] = { .class_hid = BNXT_ULP_CLASS_HID_0794, @@ -12455,6 +13138,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 10, .flow_sig_id = 68, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12462,9 +13146,9 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID } }, [685] = { .class_hid = BNXT_ULP_CLASS_HID_3858, @@ -12472,6 +13156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 4, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12479,8 +13164,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC } }, [686] = { .class_hid = BNXT_ULP_CLASS_HID_046c, @@ -12488,6 +13173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .hdr_sig_id = 11, .flow_sig_id = 68, .flow_pattern_id = 2, + .app_sig = 0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | @@ -12495,8 +13181,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID } } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 0058908c70..4a2f7337be 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Sun Mar 14 12:41:59 2021 */ +/* date: Wed Mar 17 11:31:19 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -34,6 +34,7 @@ #define BNXT_ULP_COND_GOTO_RF 0x10000 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 +#define BNXT_ULP_APP_ID_SHIFT 4 #define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595 #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5 #define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74 @@ -111,7 +112,8 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000, BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000 + BNXT_ULP_HDR_BIT_ANY = 0x0000000000080000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000 }; enum bnxt_ulp_accept_opc { @@ -343,10 +345,14 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 7, BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 8, BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 9, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 10, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 11, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 12, - BNXT_ULP_GLB_RF_IDX_LAST = 13 + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 10, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 11, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 12, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 13, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 14, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 15, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 16, + BNXT_ULP_GLB_RF_IDX_LAST = 17 }; enum bnxt_ulp_hdr_type { @@ -477,7 +483,8 @@ enum bnxt_ulp_template_type { }; enum bnxt_ulp_app_cap { - BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001 + BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001, + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002 }; enum bnxt_ulp_fdb_resource_flags { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h index 3a3b609941..115bdc644c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 3 12:15:37 2021 */ +/* date: Wed Mar 17 11:31:19 2021 */ #ifndef ULP_HDR_FIELD_ENUMS_H_ #define ULP_HDR_FIELD_ENUMS_H_ @@ -109,578 +109,578 @@ enum bnxt_ulp_glb_hf { BNXT_ULP_GLB_HF_ID_T_VXLAN_RSVD1 }; -enum bnxt_ulp_hf1_0_bitmask { - BNXT_ULP_HF1_0_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_0_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 +enum bnxt_ulp_hf_0_1_0_bitmask { + BNXT_ULP_HF_0_1_0_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 }; -enum bnxt_ulp_hf1_1_bitmask { - BNXT_ULP_HF1_1_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_1_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 +enum bnxt_ulp_hf_0_1_1_bitmask { + BNXT_ULP_HF_0_1_1_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 }; -enum bnxt_ulp_hf1_2_bitmask { - BNXT_ULP_HF1_2_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_2_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 +enum bnxt_ulp_hf_0_1_2_bitmask { + BNXT_ULP_HF_0_1_2_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 }; -enum bnxt_ulp_hf1_3_bitmask { - BNXT_ULP_HF1_3_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_3_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 +enum bnxt_ulp_hf_0_1_3_bitmask { + BNXT_ULP_HF_0_1_3_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 }; -enum bnxt_ulp_hf1_4_bitmask { - BNXT_ULP_HF1_4_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_4_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, - BNXT_ULP_HF1_4_BITMASK_O_TCP_URP = 0x0000040000000000 +enum bnxt_ulp_hf_0_1_4_bitmask { + BNXT_ULP_HF_0_1_4_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, + BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_URP = 0x0000040000000000 }; -enum bnxt_ulp_hf1_5_bitmask { - BNXT_ULP_HF1_5_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_5_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF1_5_BITMASK_O_TCP_URP = 0x0000010000000000 +enum bnxt_ulp_hf_0_1_5_bitmask { + BNXT_ULP_HF_0_1_5_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_URP = 0x0000010000000000 }; -enum bnxt_ulp_hf1_6_bitmask { - BNXT_ULP_HF1_6_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_6_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF1_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF1_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 +enum bnxt_ulp_hf_0_1_6_bitmask { + BNXT_ULP_HF_0_1_6_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 }; -enum bnxt_ulp_hf1_7_bitmask { - BNXT_ULP_HF1_7_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_7_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 +enum bnxt_ulp_hf_0_1_7_bitmask { + BNXT_ULP_HF_0_1_7_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 }; -enum bnxt_ulp_hf1_8_bitmask { - BNXT_ULP_HF1_8_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_8_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF1_8_BITMASK_O_TCP_URP = 0x0000008000000000 +enum bnxt_ulp_hf_0_1_8_bitmask { + BNXT_ULP_HF_0_1_8_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_URP = 0x0000008000000000 }; -enum bnxt_ulp_hf1_9_bitmask { - BNXT_ULP_HF1_9_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_9_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF1_9_BITMASK_O_TCP_URP = 0x0000002000000000 +enum bnxt_ulp_hf_0_1_9_bitmask { + BNXT_ULP_HF_0_1_9_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_URP = 0x0000002000000000 }; -enum bnxt_ulp_hf1_10_bitmask { - BNXT_ULP_HF1_10_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_10_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_10_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF1_10_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF1_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF1_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF1_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF1_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 +enum bnxt_ulp_hf_0_1_10_bitmask { + BNXT_ULP_HF_0_1_10_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 }; -enum bnxt_ulp_hf1_11_bitmask { - BNXT_ULP_HF1_11_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_11_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF1_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF1_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 +enum bnxt_ulp_hf_0_1_11_bitmask { + BNXT_ULP_HF_0_1_11_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 }; -enum bnxt_ulp_hf1_12_bitmask { - BNXT_ULP_HF1_12_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF1_12_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF1_12_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF1_12_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF1_12_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF1_12_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF1_12_BITMASK_O_UDP_CSUM = 0x0000200000000000, - BNXT_ULP_HF1_12_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000, - BNXT_ULP_HF1_12_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000, - BNXT_ULP_HF1_12_BITMASK_T_VXLAN_VNI = 0x0000040000000000, - BNXT_ULP_HF1_12_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000 +enum bnxt_ulp_hf_0_1_12_bitmask { + BNXT_ULP_HF_0_1_12_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_CSUM = 0x0000200000000000, + BNXT_ULP_HF_0_1_12_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000, + BNXT_ULP_HF_0_1_12_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000, + BNXT_ULP_HF_0_1_12_BITMASK_T_VXLAN_VNI = 0x0000040000000000, + BNXT_ULP_HF_0_1_12_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000 }; -enum bnxt_ulp_hf2_0_bitmask { - BNXT_ULP_HF2_0_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_0_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 +enum bnxt_ulp_hf_0_2_0_bitmask { + BNXT_ULP_HF_0_2_0_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 }; -enum bnxt_ulp_hf2_1_bitmask { - BNXT_ULP_HF2_1_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_1_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 +enum bnxt_ulp_hf_0_2_1_bitmask { + BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 }; -enum bnxt_ulp_hf2_2_bitmask { - BNXT_ULP_HF2_2_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_2_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 +enum bnxt_ulp_hf_0_2_2_bitmask { + BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 }; -enum bnxt_ulp_hf2_3_bitmask { - BNXT_ULP_HF2_3_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_3_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 +enum bnxt_ulp_hf_0_2_3_bitmask { + BNXT_ULP_HF_0_2_3_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 }; -enum bnxt_ulp_hf2_4_bitmask { - BNXT_ULP_HF2_4_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_4_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_4_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF2_4_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, - BNXT_ULP_HF2_4_BITMASK_O_TCP_URP = 0x0000040000000000 +enum bnxt_ulp_hf_0_2_4_bitmask { + BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP = 0x0000040000000000 }; -enum bnxt_ulp_hf2_5_bitmask { - BNXT_ULP_HF2_5_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_5_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF2_5_BITMASK_O_TCP_URP = 0x0000010000000000 +enum bnxt_ulp_hf_0_2_5_bitmask { + BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP = 0x0000010000000000 }; -enum bnxt_ulp_hf2_6_bitmask { - BNXT_ULP_HF2_6_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_6_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 +enum bnxt_ulp_hf_0_2_6_bitmask { + BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 }; -enum bnxt_ulp_hf2_7_bitmask { - BNXT_ULP_HF2_7_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_7_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 +enum bnxt_ulp_hf_0_2_7_bitmask { + BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 }; -enum bnxt_ulp_hf2_8_bitmask { - BNXT_ULP_HF2_8_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_8_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF2_8_BITMASK_O_TCP_URP = 0x0000008000000000 +enum bnxt_ulp_hf_0_2_8_bitmask { + BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP = 0x0000008000000000 }; -enum bnxt_ulp_hf2_9_bitmask { - BNXT_ULP_HF2_9_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_9_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF2_9_BITMASK_O_TCP_URP = 0x0000002000000000 +enum bnxt_ulp_hf_0_2_9_bitmask { + BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP = 0x0000002000000000 }; -enum bnxt_ulp_hf2_10_bitmask { - BNXT_ULP_HF2_10_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_10_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_10_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF2_10_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 +enum bnxt_ulp_hf_0_2_10_bitmask { + BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 }; -enum bnxt_ulp_hf2_11_bitmask { - BNXT_ULP_HF2_11_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF2_11_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 +enum bnxt_ulp_hf_0_2_11_bitmask { + BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 67bb8b116b..f3146cc1a3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Mar 15 10:26:20 2021 */ +/* date: Wed Mar 17 11:31:19 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -814,7 +814,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 16384 + .count = 8192 }, { .app_id = 0, @@ -958,7 +958,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 16384 + .count = 8192 }, { .app_id = 0, @@ -1398,7 +1398,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 16384 + .count = 8192 }, { .app_id = 1, @@ -1542,7 +1542,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 16384 + .count = 8192 }, { .app_id = 1, @@ -1982,7 +1982,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 16384 + .count = 8192 }, { .app_id = 2, @@ -2126,7 +2126,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 16384 + .count = 8192 }, { .app_id = 2, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 938bcbfe56..09bd179781 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -88,6 +88,7 @@ struct ulp_rte_parser_params { uint32_t flow_sig_id; uint32_t flow_pattern_id; uint32_t act_pattern_id; + uint8_t app_id; }; /* Flow Parser Header Information Structure */ @@ -133,6 +134,7 @@ struct bnxt_ulp_class_match_info { uint32_t class_tid; uint8_t act_vnic; uint8_t wc_pri; + uint8_t app_sig; uint32_t hdr_sig_id; uint32_t flow_sig_id; uint32_t flow_pattern_id; @@ -153,6 +155,7 @@ struct bnxt_ulp_act_match_info { uint32_t act_hid; uint32_t act_tid; uint32_t act_pattern_id; + uint8_t app_sig; }; /* Flow Matcher templates Structure for action entries */ From patchwork Sun May 30 08:59:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93592 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A59A0A0524; Sun, 30 May 2021 11:07:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B5FCB411E0; Sun, 30 May 2021 11:02:03 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 6FB9E4003E for ; Sun, 30 May 2021 11:02:00 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 0E2487DAF; Sun, 30 May 2021 02:01:58 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 0E2487DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365320; bh=zDeUOKj0KVcibhs3dxPo1LWVwspCTnCxVezbVQqC2lA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YYvTRPmz33TC9kFzkwsl7hRUsAz9eaWsm4qDU6cY/BKG3ikmpJrQ596xVnZeKVLRq Lvdg57l6Akkr2TTJV/ywmTQwZ5xcoKpbM2JC1tc/ZJgGBuXDomxQxedzwHaQ62zdKk OtfKSxZOKMCgSm7ozzEK/SkmThl6pX610i+BgKnk= From: Venkat Duvvuru To: dev@dpdk.org Cc: Mike Baucom , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:22 +0530 Message-Id: <20210530085929.29695-52-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 51/58] net/bnxt: process resource lists before session open X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Mike Baucom Shared sessions require both named and unnamed resources to be requested during a tf_open_session. ULP uses named resources for global resources that are pre-allocated and remain through the life of the application. Unnamed resources are generally per flow resources and allocated on demand. The sum of both named and unnamed resources must be requested when initializing the session. The ulp_init now processes both lists prior to calling tf_open_session for both shared and regular sessions. Signed-off-by: Mike Baucom Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 177 ++++++++++++------ drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 4 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 37 ++-- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 1 + drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 36 ++++ drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 6 + 6 files changed, 183 insertions(+), 78 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 632334674c..98b86f2c52 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -77,6 +77,15 @@ bnxt_ulp_app_cap_list_get(uint32_t *num_entries) return ulp_app_cap_info_list; } +static struct bnxt_ulp_resource_resv_info * +bnxt_ulp_app_resource_resv_list_get(uint32_t *num_entries) +{ + if (num_entries == NULL) + return NULL; + *num_entries = BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ; + return ulp_app_resource_resv_list; +} + struct bnxt_ulp_resource_resv_info * bnxt_ulp_resource_resv_list_get(uint32_t *num_entries) { @@ -96,23 +105,18 @@ bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries) } static int32_t -bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, - struct tf_session_resources *res) +bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx, + struct bnxt_ulp_glb_resource_info *info, + uint32_t num, + struct tf_session_resources *res) { - struct bnxt_ulp_resource_resv_info *info = NULL; - uint32_t dev_id, res_type, i, num; + uint32_t dev_id, res_type, i; enum tf_dir dir; uint8_t app_id; int32_t rc = 0; - if (!ulp_ctx || !res) { - BNXT_TF_DBG(ERR, "Invalid arguments to get resources.\n"); - return -EINVAL; - } - - info = bnxt_ulp_resource_resv_list_get(&num); - if (!info) { - BNXT_TF_DBG(ERR, "Unable to get resource reservation list.\n"); + if (ulp_ctx == NULL || info == NULL || res == NULL || num == 0) { + BNXT_TF_DBG(ERR, "Invalid parms to named resources calc.\n"); return -EINVAL; } @@ -124,31 +128,33 @@ bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); if (rc) { - BNXT_TF_DBG(ERR, "Unable to get the device id from ulp.\n"); + BNXT_TF_DBG(ERR, "Unable to get the dev id from ulp.\n"); return -EINVAL; } for (i = 0; i < num; i++) { - if (app_id != info[i].app_id || dev_id != info[i].device_id) + if (dev_id != info[i].device_id || app_id != info[i].app_id) continue; dir = info[i].direction; res_type = info[i].resource_type; switch (info[i].resource_func) { case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: - res->ident_cnt[dir].cnt[res_type] = info[i].count; + res->ident_cnt[dir].cnt[res_type]++; break; case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: - res->tbl_cnt[dir].cnt[res_type] = info[i].count; + res->tbl_cnt[dir].cnt[res_type]++; break; case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: - res->tcam_cnt[dir].cnt[res_type] = info[i].count; + res->tcam_cnt[dir].cnt[res_type]++; break; case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: - res->em_cnt[dir].cnt[res_type] = info[i].count; + res->em_cnt[dir].cnt[res_type]++; break; default: - break; + BNXT_TF_DBG(ERR, "Unknown resource func (0x%x)\n,", + info[i].resource_func); + continue; } } @@ -156,14 +162,20 @@ bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, } static int32_t -bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, - struct tf_session_resources *res) +bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx, + struct bnxt_ulp_resource_resv_info *info, + uint32_t num, + struct tf_session_resources *res) { - struct bnxt_ulp_glb_resource_info *info; - uint32_t dev_id, res_type, i, num; + uint32_t dev_id, res_type, i; enum tf_dir dir; uint8_t app_id; - int32_t rc; + int32_t rc = 0; + + if (ulp_ctx == NULL || res == NULL || info == NULL || num == 0) { + BNXT_TF_DBG(ERR, "Invalid arguments to get resources.\n"); + return -EINVAL; + } rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); if (rc) { @@ -173,48 +185,108 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); if (rc) { - BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n"); + BNXT_TF_DBG(ERR, "Unable to get the dev id from ulp.\n"); return -EINVAL; } - /* Make sure the resources are zero before accumulating. */ - memset(res, 0, sizeof(struct tf_session_resources)); - - /* Get the list and tally the resources. */ - info = bnxt_ulp_app_glb_resource_info_list_get(&num); - if (!info) { - BNXT_TF_DBG(ERR, "Unable to get app global resource list\n"); - return -EINVAL; - } for (i = 0; i < num; i++) { - if (dev_id != info[i].device_id || app_id != info[i].app_id) + if (app_id != info[i].app_id || dev_id != info[i].device_id) continue; dir = info[i].direction; res_type = info[i].resource_type; switch (info[i].resource_func) { case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: - res->ident_cnt[dir].cnt[res_type]++; + res->ident_cnt[dir].cnt[res_type] = info[i].count; break; case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: - res->tbl_cnt[dir].cnt[res_type]++; + res->tbl_cnt[dir].cnt[res_type] = info[i].count; break; case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: - res->tcam_cnt[dir].cnt[res_type]++; + res->tcam_cnt[dir].cnt[res_type] = info[i].count; break; case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: - res->em_cnt[dir].cnt[res_type]++; + res->em_cnt[dir].cnt[res_type] = info[i].count; break; default: - BNXT_TF_DBG(ERR, "Unknown resource func (0x%x)\n,", - info[i].resource_func); - continue; + break; } } - return 0; } +static int32_t +bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, + struct tf_session_resources *res) +{ + struct bnxt_ulp_resource_resv_info *unnamed = NULL; + uint32_t unum; + int32_t rc = 0; + + if (ulp_ctx == NULL || res == NULL) { + BNXT_TF_DBG(ERR, "Invalid arguments to get resources.\n"); + return -EINVAL; + } + + unnamed = bnxt_ulp_resource_resv_list_get(&unum); + if (unnamed == NULL) { + BNXT_TF_DBG(ERR, "Unable to get resource resv list.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res); + if (rc) + BNXT_TF_DBG(ERR, "Unable to calc resources for session.\n"); + + return rc; +} + +static int32_t +bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, + struct tf_session_resources *res) +{ + struct bnxt_ulp_resource_resv_info *unnamed; + struct bnxt_ulp_glb_resource_info *named; + uint32_t unum, nnum; + int32_t rc; + + if (ulp_ctx == NULL || res == NULL) { + BNXT_TF_DBG(ERR, "Invalid arguments to get resources.\n"); + return -EINVAL; + } + + /* Make sure the resources are zero before accumulating. */ + memset(res, 0, sizeof(struct tf_session_resources)); + + /* + * Shared resources are comprised of both named and unnamed resources. + * First get the unnamed counts, and then add the named to the result. + */ + /* Get the baseline counts */ + unnamed = bnxt_ulp_app_resource_resv_list_get(&unum); + if (unnamed == NULL) { + BNXT_TF_DBG(ERR, "Unable to get shared resource resv list.\n"); + return -EINVAL; + } + rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to calc resources for shared session.\n"); + return -EINVAL; + } + + /* Get the named list and add the totals */ + named = bnxt_ulp_app_glb_resource_info_list_get(&nnum); + if (named == NULL) { + BNXT_TF_DBG(ERR, "Unable to get app global resource list\n"); + return -EINVAL; + } + rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, res); + if (rc) + BNXT_TF_DBG(ERR, "Unable to calc named resources\n"); + + return rc; +} + int32_t bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, uint8_t app_id, uint32_t dev_id) @@ -320,10 +392,8 @@ ulp_ctx_shared_session_open(struct bnxt *bp, strncat(parms.ctrl_chan_name, "-tf_shared", copy_num_bytes); rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, resources); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get shared resource count.\n"); + if (rc) return rc; - } rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); if (rc) { @@ -342,8 +412,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp, parms.device_type = TF_DEVICE_TYPE_THOR; break; default: - BNXT_TF_DBG(ERR, "Unable to determine device for " - "opening session.\n"); + BNXT_TF_DBG(ERR, "Unable to determine dev for opening session.\n"); return rc; } @@ -450,18 +519,14 @@ ulp_ctx_session_open(struct bnxt *bp, params.device_type = TF_DEVICE_TYPE_THOR; break; default: - BNXT_TF_DBG(ERR, "Unable to determine device for " - "opening session.\n"); + BNXT_TF_DBG(ERR, "Unable to determine device for opening session.\n"); return rc; } resources = ¶ms.resources; rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx, resources); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to determine tf resources for " - "session open.\n"); + if (rc) return rc; - } params.bp = bp; rc = tf_open_session(&bp->tfp, ¶ms); @@ -708,8 +773,8 @@ ulp_ctx_init(struct bnxt *bp, rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid); if (rc) { - BNXT_TF_DBG(ERR, "Unable to set capabilities for " - " app(%x)/dev(%x)\n", bp->app_id, devid); + BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", + bp->app_id, devid); goto error_deinit; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index b688288a62..483030edbf 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -321,8 +321,8 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (!ulp_ctx) { - BNXT_TF_DBG(ERR, "ULP context is not initialized. " - "Failed to create default flow.\n"); + BNXT_TF_DBG(ERR, + "ULP context is not initialized. Failed to create dflt flow.\n"); return -EINVAL; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 8fd8a329bf..b5cefbeb08 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -2296,8 +2296,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, tbl->tbl_operand, ®val, &shared)) { BNXT_TF_DBG(ERR, - "Failed to get tbl idx from Global " - "regfile[%d].\n", + "Failed to get tbl idx from Glb RF[%d].\n", tbl->tbl_operand); return -EINVAL; } @@ -2347,8 +2346,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, gparms.data_sz_in_bytes, data.byte_order); if (rc) { - BNXT_TF_DBG(ERR, "Failed to read fields on tbl read " - "rc=%d\n", rc); + BNXT_TF_DBG(ERR, + "Failed to get flds on tbl read rc=%d\n", + rc); return rc; } return 0; @@ -2433,8 +2433,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_set_tbl_entry(tfp, &sparms); if (rc) { BNXT_TF_DBG(ERR, - "Index table[%s][%s][%x] write failed " - "rc=%d\n", + "Index table[%s][%s][%x] write fail rc=%d\n", tf_tbl_type_2_str(sparms.type), tf_dir_2_str(sparms.dir), sparms.idx, rc); @@ -2833,15 +2832,15 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); if (rc) { - BNXT_TF_DBG(ERR, "Failed to get device id for " - "global init (%d)\n", rc); + BNXT_TF_DBG(ERR, "Failed to get device id for glb init (%d)\n", + rc); return rc; } rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); if (rc) { - BNXT_TF_DBG(ERR, "Failed to get app id for " - "global init (%d)\n", rc); + BNXT_TF_DBG(ERR, "Failed to get app id for glb init (%d)\n", + rc); return rc; } @@ -2916,15 +2915,15 @@ ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); if (rc) { - BNXT_TF_DBG(ERR, "Failed to get the app id in global init " - "(%d).\n", rc); + BNXT_TF_DBG(ERR, "Failed to get the app id in glb init (%d).\n", + rc); return rc; } rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); if (rc) { - BNXT_TF_DBG(ERR, "Failed to get device id for app " - "global init (%d)\n", rc); + BNXT_TF_DBG(ERR, "Failed to get dev id for app glb init (%d)\n", + rc); return rc; } @@ -3413,8 +3412,8 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) cond_tbls, num_cond_tbls, &cond_rc); if (rc) { - BNXT_TF_DBG(ERR, "Failed to process cond opc list " - "(%d)\n", rc); + BNXT_TF_DBG(ERR, "Failed to proc cond opc list (%d)\n", + rc); goto error; } /* Skip the table if False */ @@ -3812,8 +3811,7 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx) if (bnxt_ulp_cntxt_shared_session_enabled(ulp_ctx)) { rc = ulp_mapper_app_glb_resource_info_init(ulp_ctx, data); if (rc) { - BNXT_TF_DBG(ERR, "Failed to initialize app " - "global resources\n"); + BNXT_TF_DBG(ERR, "Failed to init app glb resources\n"); goto error; } } @@ -3840,8 +3838,7 @@ ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx) if (!ulp_ctx) { BNXT_TF_DBG(ERR, - "Failed to acquire ulp context, so data may " - "not be released.\n"); + "Failed to acquire ulp context, so data may not be released.\n"); return; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 4a2f7337be..bc701aa8a5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -29,6 +29,7 @@ #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 33 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 27 #define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 219 +#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 4 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index f3146cc1a3..ffa42ffa8b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -270,6 +270,42 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { } }; +/* List of unnamed app tf resources required to be reserved per app/device */ +struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 256 + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 256 + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 256 + } +}; + /* List of device specific parameters */ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 09bd179781..72d0df98a8 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -391,6 +391,12 @@ extern struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[]; */ extern struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[]; +/* + * The ulp_app_resource_resv_list provides the list of tf resources required + * when calling tf_open. + */ +extern struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[]; + /* * The_app_cap_info_list provides the list of ULP capabilities per app/device. */ From patchwork Sun May 30 08:59:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93593 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5047BA0524; Sun, 30 May 2021 11:07:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 474C541205; Sun, 30 May 2021 11:02:05 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id EE461411F6 for ; Sun, 30 May 2021 11:02:01 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 8B4C87DC0; Sun, 30 May 2021 02:02:00 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 8B4C87DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365321; bh=ofWgOak0CFKJn7JunqgcBy3mVl5e5yoyY6Sx+cyZdjg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rbiUDmqDQmag5/2BnRaK50PRkaBBfttw9Ihnzv6ibVx7aSPFdyD7h8Vg94eh4mPAT na69BtGy2TjU5j8cm9BSPKPUofavFBqxThhq4fBIwwTS7f+etnQllzOpySBM2fIhh3 g5N/QqzGjrCcbrE7MXB61vDeI1sem/j9g8++5cFA= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:23 +0530 Message-Id: <20210530085929.29695-53-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 52/58] net/bnxt: add support for shared sessions in ULP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha 1. Add template support for shared sessions. 2. Store the shared session flag in flow data base. 3. Store WC tcam region in the computational field. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 5 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 11 + drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 19 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 18 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 57 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 1 - .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 21 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 444 ++-- .../bnxt/tf_ulp/ulp_template_db_thor_class.c | 68 +- .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c | 1100 +++++----- .../tf_ulp/ulp_template_db_wh_plus_class.c | 1838 +++++++++-------- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 3 + 14 files changed, 1805 insertions(+), 1792 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 98b86f2c52..0daa8e4c29 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -671,7 +671,7 @@ ulp_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) if (!ulp_ctx || !ulp_ctx->cfg_data) return -EINVAL; - tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n"); return -EINVAL; @@ -1632,13 +1632,17 @@ bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp) /* Function to get the tfp session details from the ulp context. */ struct tf * -bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp) +bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp, + enum bnxt_ulp_shared_session shared) { if (!ulp) { BNXT_TF_DBG(ERR, "Invalid arguments\n"); return NULL; } - return ulp->g_tfp; + if (shared) + return ulp->g_shared_tfp; + else + return ulp->g_tfp; } /* diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 648fb2ab37..1ba67ed9f6 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -31,11 +31,13 @@ #define BNXT_ULP_VF_REP_ENABLED 0x1 #define BNXT_ULP_SHARED_SESSION_ENABLED 0x2 #define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 +#define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ BNXT_ULP_SHARED_SESSION_ENABLED) #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag) ((flag) &\ BNXT_ULP_APP_DEV_UNSUPPORTED) +#define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -158,7 +160,8 @@ bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp); /* Function to get the tfp session details from ulp context. */ struct tf * -bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp); +bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp, + enum bnxt_ulp_shared_session shared); /* Get the device table entry based on the device id. */ struct bnxt_ulp_device_params * diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 42dc9bef71..9c27217573 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -81,6 +81,8 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, struct ulp_rte_parser_params *params, enum bnxt_ulp_fdb_type flow_type) { + uint32_t ulp_flags = 0; + memset(mapper_cparms, 0, sizeof(*mapper_cparms)); mapper_cparms->flow_type = flow_type; mapper_cparms->app_priority = params->priority; @@ -106,6 +108,15 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, params->hdr_sig_id); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, params->flow_sig_id); + + /* update the WC Priority flag */ + if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) && + ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { + /* TBD: read the state and Set the WC priority */ + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, 1); + } + } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index a25893c63c..7c83cb2054 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -389,7 +389,7 @@ ulp_fc_mgr_alarm_cb(void *arg) return; } - tfp = bnxt_ulp_cntxt_tfp_get(ctxt); + tfp = bnxt_ulp_cntxt_tfp_get(ctxt, BNXT_ULP_SHARED_SESSION_NO); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n"); return; diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 8a6a925559..e7e8335dbe 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -156,7 +156,7 @@ ulp_flow_db_res_params_to_info(struct ulp_fdb_resource_info *resource_info, resource_info->resource_hndl = (uint32_t)params->resource_hndl; resource_info->resource_type = params->resource_type; resource_info->resource_sub_type = params->resource_sub_type; - resource_info->reserved = params->reserved; + resource_info->fdb_flags = params->fdb_flags; } else { resource_info->resource_em_handle = params->resource_hndl; } @@ -187,7 +187,7 @@ ulp_flow_db_res_info_to_params(struct ulp_fdb_resource_info *resource_info, params->resource_hndl = resource_info->resource_hndl; params->resource_type = resource_info->resource_type; params->resource_sub_type = resource_info->resource_sub_type; - params->reserved = resource_info->reserved; + params->fdb_flags = resource_info->fdb_flags; } } @@ -1900,3 +1900,18 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt) } } } + +/* + * Set the shared bit for the flow db entry + * + * res [in] Ptr to fdb entry + * shared [in] shared flag + * + * returns none + */ +void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res, + enum bnxt_ulp_shared_session shared) +{ + if (res && (shared & BNXT_ULP_SHARED_SESSION_YES)) + res->fdb_flags |= ULP_FDB_FLAG_SHARED_SESSION; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h index 62c914833b..d84715e59c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h @@ -13,6 +13,9 @@ #define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS 512 #define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES 8 +/* Defines for the fdb flag */ +#define ULP_FDB_FLAG_SHARED_SESSION 0x1 + /* * Structure for the flow database resource information * The below structure is based on the below paritions @@ -30,7 +33,7 @@ struct ulp_fdb_resource_info { uint8_t resource_func_lower; uint8_t resource_type; uint8_t resource_sub_type; - uint8_t reserved; + uint8_t fdb_flags; uint32_t resource_hndl; }; }; @@ -86,7 +89,7 @@ struct ulp_flow_db_res_params { enum bnxt_ulp_resource_func resource_func; uint8_t resource_type; uint8_t resource_sub_type; - uint8_t reserved; + uint8_t fdb_flags; uint8_t critical_resource; uint64_t resource_hndl; }; @@ -403,4 +406,15 @@ ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, void ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt); +/* + * Set the shared bit for the flow db entry + * + * res [in] Ptr to fdb entry + * shared [in] shared flag + * + * returns none + */ +void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res, + enum bnxt_ulp_shared_session shared); + #endif /* _ULP_FLOW_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index b5cefbeb08..e2404c392b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -121,7 +121,7 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx, struct tf *tfp; int32_t rc = 0; - tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); if (!tfp) return -EINVAL; @@ -174,7 +174,7 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, uint32_t tbl_scope_id; int32_t rc = 0; - tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); if (!tfp) return -EINVAL; @@ -741,7 +741,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, struct tf *tfp; int rc; - tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get tf pointer\n"); return -EINVAL; @@ -776,6 +776,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_type = ident->ident_type; fid_parms.resource_hndl = iparms.id; fid_parms.critical_resource = tbl->critical_resource; + ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session); rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { @@ -822,7 +823,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, int rc; /* Get the tfp from ulp context */ - tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get tf pointer\n"); return -EINVAL; @@ -868,6 +869,8 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_type = ident->ident_type; fid_parms.resource_hndl = sparms.search_id; fid_parms.critical_resource = tbl->critical_resource; + ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to link res to flow rc = %d\n", @@ -1513,6 +1516,8 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = gfid; + ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc); @@ -1559,6 +1564,8 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = act_idx; + ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc); @@ -1605,6 +1612,8 @@ ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_type = mark_flag; fid_parms.resource_hndl = act_idx; + ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc); @@ -1671,7 +1680,7 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, uint16_t tmplen; int32_t rc; - tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get truflow pointer\n"); return -EINVAL; @@ -1838,7 +1847,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, return 0; } - tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get truflow pointer\n"); return -EINVAL; @@ -1887,7 +1896,9 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, } /* For wild card tcam perform the post process to swap the blob */ - if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) { + if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM || + tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH || + tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW) { if (dparms->dynamic_pad_en) { /* Sets up the slices for writing to the WC TCAM */ rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms, @@ -2004,6 +2015,8 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_type = tbl->resource_type; fid_parms.critical_resource = tbl->critical_resource; fid_parms.resource_hndl = idx; + ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n", @@ -2032,7 +2045,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct ulp_blob key, data; uint32_t i, num_kflds; uint16_t tmplen; - struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); + struct tf *tfp; struct ulp_flow_db_res_params fid_parms = { 0 }; struct tf_insert_em_entry_parms iparms = { 0 }; struct tf_delete_em_entry_parms free_parms = { 0 }; @@ -2042,6 +2055,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, int32_t rc = 0; int32_t pad = 0; + tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session); rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype); if (rc) { BNXT_TF_DBG(ERR, "Failed to get the mem type for EM\n"); @@ -2208,7 +2222,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct tf_get_tbl_entry_parms gparms = { 0 }; struct tf_free_tbl_entry_parms free_parms = { 0 }; uint32_t tbl_scope_id; - struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); + struct tf *tfp; struct bnxt_ulp_glb_resource_info glb_res; uint16_t bit_size; bool alloc = false; @@ -2217,6 +2231,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, uint64_t act_rec_size; bool shared = false; + tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session); /* use the max size if encap is enabled */ if (tbl->encap_num_fields) bit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS; @@ -2460,6 +2475,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_sub_type = tbl->resource_sub_type; fid_parms.resource_hndl = index; fid_parms.critical_resource = tbl->critical_resource; + ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session); rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) { @@ -2505,10 +2521,11 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, int32_t rc = 0; struct tf_set_if_tbl_entry_parms iftbl_params = { 0 }; struct tf_get_if_tbl_entry_parms get_parms = { 0 }; - struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx); + struct tf *tfp; enum bnxt_ulp_if_tbl_opc if_opc = tbl->tbl_opcode; uint32_t res_size; + tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session); /* Initialize the blob data */ if (!ulp_blob_init(&data, tbl->result_bit_size, parms->device_params->byte_order)) { @@ -2610,7 +2627,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, struct ulp_flow_db_res_params fid_parms; struct ulp_mapper_gen_tbl_entry gen_tbl_ent, *g; struct ulp_gen_hash_entry_params hash_entry; - uint16_t tmplen; + uint16_t tmplen = 0; struct ulp_blob key, data; uint8_t *cache_key; int32_t tbl_idx; @@ -2687,6 +2704,11 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, } } else { /* convert key to index directly */ + if (ULP_BITS_2_BYTE(tmplen) > (int32_t)sizeof(key_index)) { + BNXT_TF_DBG(ERR, "%s: keysize is bigger then 4 bytes\n", + gen_tbl_list->gen_tbl_name); + return -EINVAL; + } memcpy(&key_index, cache_key, ULP_BITS_2_BYTE(tmplen)); /* Get the generic table entry */ if (ulp_mapper_gen_tbl_entry_get(gen_tbl_list, key_index, @@ -2791,6 +2813,8 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, fid_parms.resource_sub_type = tbl->resource_sub_type; fid_parms.resource_hndl = key_index; fid_parms.critical_resource = tbl->critical_resource; + ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session); + rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms); if (rc) BNXT_TF_DBG(ERR, "Fail to add gen ent flowdb %d\n", rc); @@ -3514,8 +3538,10 @@ ulp_mapper_resource_free(struct bnxt_ulp_context *ulp, BNXT_TF_DBG(ERR, "Unable to free resource\n "); return -EINVAL; } - - tfp = bnxt_ulp_cntxt_tfp_get(ulp); + if (res->fdb_flags & ULP_FDB_FLAG_SHARED_SESSION) + tfp = bnxt_ulp_cntxt_tfp_get(ulp, BNXT_ULP_SHARED_SESSION_YES); + else + tfp = bnxt_ulp_cntxt_tfp_get(ulp, BNXT_ULP_SHARED_SESSION_NO); if (!tfp) { BNXT_TF_DBG(ERR, "Unable to free resource failed to get tfp\n"); return -EINVAL; @@ -3680,7 +3706,6 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, parms.hdr_field = cparms->hdr_field; parms.fld_bitmap = cparms->fld_bitmap; parms.comp_fld = cparms->comp_fld; - parms.tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); parms.ulp_ctx = ulp_ctx; parms.act_tid = cparms->act_tid; parms.class_tid = cparms->class_tid; @@ -3779,7 +3804,7 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx) if (!ulp_ctx) return -EINVAL; - tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); if (!tfp) return -EINVAL; @@ -3850,7 +3875,7 @@ ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx) return; } - tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to acquire tfp.\n"); /* Free the mapper data regardless of errors. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index edd5978ac6..4c5dd4b836 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -48,7 +48,6 @@ struct bnxt_ulp_mapper_parms { struct ulp_rte_field_bitmap *fld_bitmap; uint32_t *comp_fld; struct ulp_regfile *regfile; - struct tf *tfp; struct bnxt_ulp_context *ulp_ctx; uint32_t fid; enum bnxt_ulp_fdb_type flow_type; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index bc701aa8a5..8cbbe203a8 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 17 11:31:19 2021 */ +/* date: Sun Mar 21 13:04:51 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -26,10 +26,10 @@ #define BNXT_ULP_ACT_HID_SHFTR 27 #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 33 -#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 27 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 219 #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 4 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 33 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 26 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 205 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 @@ -218,7 +218,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_HDR_SIG_ID = 59, BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60, BNXT_ULP_CF_IDX_WC_MATCH = 61, - BNXT_ULP_CF_IDX_LAST = 62 + BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62, + BNXT_ULP_CF_IDX_LAST = 63 }; enum bnxt_ulp_cond_list_opc { @@ -468,6 +469,12 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_LAST = 40 }; +enum bnxt_ulp_shared_session { + BNXT_ULP_SHARED_SESSION_NO = 0, + BNXT_ULP_SHARED_SESSION_YES = 1, + BNXT_ULP_SHARED_SESSION_LAST = 2 +}; + enum bnxt_ulp_tcam_tbl_opc { BNXT_ULP_TCAM_TBL_OPC_NOT_USED = 0, BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE = 1, @@ -571,6 +578,7 @@ enum bnxt_ulp_act_prop_sz { BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32, BNXT_ULP_ACT_PROP_SZ_JUMP = 4, BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE = 8, + BNXT_ULP_ACT_PROP_SZ_RSS = 64, BNXT_ULP_ACT_PROP_SZ_LAST = 4 }; @@ -617,7 +625,8 @@ enum bnxt_ulp_act_prop_idx { BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225, BNXT_ULP_ACT_PROP_IDX_JUMP = 257, BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 261, - BNXT_ULP_ACT_PROP_IDX_LAST = 269 + BNXT_ULP_ACT_PROP_IDX_RSS = 269, + BNXT_ULP_ACT_PROP_IDX_LAST = 333 }; enum ulp_wp_sym { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index ffa42ffa8b..be7914a5cd 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 17 11:31:19 2021 */ +/* date: Sun Mar 21 13:04:51 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -278,7 +278,7 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 256 + .count = 512 }, { .app_id = 1, @@ -286,7 +286,7 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 256 + .count = 512 }, { .app_id = 2, @@ -294,7 +294,7 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 256 + .count = 512 }, { .app_id = 2, @@ -302,12 +302,12 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 256 + .count = 512 } }; -/* List of device specific parameters */ -struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { +/* List of global app tf resources required to be reserved per app/device */ +struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, @@ -368,6 +368,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX @@ -401,31 +409,23 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, - .direction = TF_DIR_TX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, + .direction = TF_DIR_RX }, { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { @@ -433,7 +433,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { @@ -472,6 +472,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX @@ -505,28 +513,12 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, - .direction = TF_DIR_TX - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, - .direction = TF_DIR_TX - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX } }; -/* List of device specific parameters */ +/* List of global tf resources required to be reserved per app/device */ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { { .app_id = 0, @@ -818,7 +810,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 192 + .count = 191 }, { .app_id = 0, @@ -962,7 +954,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 192 + .count = 191 }, { .app_id = 0, @@ -1386,7 +1378,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { .app_id = 1, @@ -1394,7 +1386,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { .app_id = 1, @@ -1402,7 +1394,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 192 + .count = 4 }, { .app_id = 1, @@ -1410,7 +1402,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 64 + .count = 4 }, { .app_id = 1, @@ -1418,7 +1410,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { .app_id = 1, @@ -1426,7 +1418,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 512 }, { .app_id = 1, @@ -1434,7 +1426,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 + .count = 1024 }, { .app_id = 1, @@ -1442,7 +1434,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { .app_id = 1, @@ -1450,7 +1442,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { .app_id = 1, @@ -1458,7 +1450,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 63 + .count = 4 }, { .app_id = 1, @@ -1466,15 +1458,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { .app_id = 1, @@ -1482,7 +1466,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { .app_id = 1, @@ -1490,7 +1474,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { .app_id = 1, @@ -1498,7 +1482,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { .app_id = 1, @@ -1506,7 +1490,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 4 }, { .app_id = 1, @@ -1514,15 +1498,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { .app_id = 1, @@ -1530,7 +1506,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { .app_id = 1, @@ -1538,7 +1514,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { .app_id = 1, @@ -1546,7 +1522,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 192 + .count = 4 }, { .app_id = 1, @@ -1554,7 +1530,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 64 + .count = 4 }, { .app_id = 1, @@ -1562,7 +1538,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { .app_id = 1, @@ -1570,7 +1546,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 512 }, { .app_id = 1, @@ -1578,7 +1554,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 + .count = 1024 }, { .app_id = 1, @@ -1586,7 +1562,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { .app_id = 1, @@ -1594,7 +1570,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { .app_id = 1, @@ -1602,7 +1578,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { .app_id = 1, @@ -1610,7 +1586,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { .app_id = 1, @@ -1618,7 +1594,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { .app_id = 1, @@ -1626,15 +1602,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { .app_id = 1, @@ -1642,7 +1610,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { .app_id = 1, @@ -1650,7 +1618,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { .app_id = 1, @@ -1658,7 +1626,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { .app_id = 1, @@ -1666,7 +1634,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { .app_id = 1, @@ -1674,15 +1642,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { .app_id = 1, @@ -1690,7 +1650,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 26 + .count = 32 }, { .app_id = 1, @@ -1698,7 +1658,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { .app_id = 1, @@ -1730,14 +1690,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 1024 - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, { @@ -1745,8 +1697,8 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 14 + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 1024 }, { .app_id = 1, @@ -1754,7 +1706,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { .app_id = 1, @@ -1762,7 +1714,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { .app_id = 1, @@ -1770,7 +1722,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 4 }, { .app_id = 1, @@ -1778,7 +1730,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 64 + .count = 4 }, { .app_id = 1, @@ -1786,7 +1738,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 300 + .count = 32 }, { .app_id = 1, @@ -1794,7 +1746,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { .app_id = 1, @@ -1802,7 +1754,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { .app_id = 1, @@ -1810,7 +1762,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 112 + .count = 4 }, { .app_id = 1, @@ -1818,7 +1770,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13200 + .count = 1024 }, { .app_id = 1, @@ -1834,7 +1786,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 26 + .count = 2 }, { .app_id = 1, @@ -1842,7 +1794,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 4 }, { .app_id = 1, @@ -1850,7 +1802,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { .app_id = 1, @@ -1858,7 +1810,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 4 }, { .app_id = 1, @@ -1866,14 +1818,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 1024 - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, { @@ -1881,8 +1825,8 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 14 + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 1024 }, { .app_id = 1, @@ -1890,7 +1834,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { .app_id = 1, @@ -1898,7 +1842,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { .app_id = 1, @@ -1906,7 +1850,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 4 }, { .app_id = 1, @@ -1914,15 +1858,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 100 - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { .app_id = 1, @@ -1930,7 +1866,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 200 + .count = 32 }, { .app_id = 1, @@ -1938,7 +1874,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 110 + .count = 2 }, { .app_id = 1, @@ -1946,7 +1882,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { .app_id = 1, @@ -1954,7 +1890,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 128 + .count = 4 }, { .app_id = 1, @@ -1962,7 +1898,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 + .count = 1024 }, { .app_id = 2, @@ -1970,7 +1906,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { .app_id = 2, @@ -1978,7 +1914,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { .app_id = 2, @@ -1986,7 +1922,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 192 + .count = 4 }, { .app_id = 2, @@ -1994,7 +1930,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 64 + .count = 4 }, { .app_id = 2, @@ -2002,7 +1938,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { .app_id = 2, @@ -2010,7 +1946,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 512 }, { .app_id = 2, @@ -2018,7 +1954,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 + .count = 1024 }, { .app_id = 2, @@ -2026,7 +1962,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { .app_id = 2, @@ -2034,7 +1970,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { .app_id = 2, @@ -2042,7 +1978,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 63 + .count = 4 }, { .app_id = 2, @@ -2050,15 +1986,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { .app_id = 2, @@ -2066,7 +1994,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { .app_id = 2, @@ -2074,7 +2002,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { .app_id = 2, @@ -2082,7 +2010,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { .app_id = 2, @@ -2090,7 +2018,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 128 }, { .app_id = 2, @@ -2098,15 +2026,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { .app_id = 2, @@ -2114,7 +2034,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { .app_id = 2, @@ -2122,7 +2042,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { .app_id = 2, @@ -2130,7 +2050,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 192 + .count = 4 }, { .app_id = 2, @@ -2138,7 +2058,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 64 + .count = 4 }, { .app_id = 2, @@ -2146,7 +2066,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { .app_id = 2, @@ -2154,7 +2074,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 512 }, { .app_id = 2, @@ -2162,7 +2082,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 + .count = 1024 }, { .app_id = 2, @@ -2170,7 +2090,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { .app_id = 2, @@ -2178,7 +2098,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { .app_id = 2, @@ -2186,7 +2106,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { .app_id = 2, @@ -2194,7 +2114,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { .app_id = 2, @@ -2202,7 +2122,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { .app_id = 2, @@ -2210,15 +2130,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { .app_id = 2, @@ -2226,7 +2138,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { .app_id = 2, @@ -2234,7 +2146,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { .app_id = 2, @@ -2242,7 +2154,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { .app_id = 2, @@ -2250,7 +2162,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { .app_id = 2, @@ -2258,15 +2170,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { .app_id = 2, @@ -2274,7 +2178,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 26 + .count = 32 }, { .app_id = 2, @@ -2282,7 +2186,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { .app_id = 2, @@ -2314,14 +2218,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 1024 - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, { @@ -2329,8 +2225,8 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 14 + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 1024 }, { .app_id = 2, @@ -2338,7 +2234,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { .app_id = 2, @@ -2346,7 +2242,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { .app_id = 2, @@ -2354,7 +2250,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 4 }, { .app_id = 2, @@ -2362,7 +2258,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 64 + .count = 4 }, { .app_id = 2, @@ -2370,7 +2266,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 300 + .count = 32 }, { .app_id = 2, @@ -2378,7 +2274,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { .app_id = 2, @@ -2386,7 +2282,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { .app_id = 2, @@ -2394,7 +2290,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 112 + .count = 128 }, { .app_id = 2, @@ -2402,7 +2298,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13200 + .count = 1024 }, { .app_id = 2, @@ -2418,7 +2314,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 26 + .count = 2 }, { .app_id = 2, @@ -2426,7 +2322,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 4 }, { .app_id = 2, @@ -2434,7 +2330,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { .app_id = 2, @@ -2442,7 +2338,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 4 }, { .app_id = 2, @@ -2450,14 +2346,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 1024 - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, .count = 512 }, { @@ -2465,8 +2353,8 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 14 + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 1024 }, { .app_id = 2, @@ -2474,7 +2362,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { .app_id = 2, @@ -2482,7 +2370,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { .app_id = 2, @@ -2490,7 +2378,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 4 }, { .app_id = 2, @@ -2498,15 +2386,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 100 - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { .app_id = 2, @@ -2514,7 +2394,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 200 + .count = 32 }, { .app_id = 2, @@ -2522,7 +2402,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 110 + .count = 2 }, { .app_id = 2, @@ -2530,7 +2410,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { .app_id = 2, @@ -2538,7 +2418,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 128 + .count = 4 }, { .app_id = 2, @@ -2546,7 +2426,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 + .count = 1024 } }; @@ -2635,6 +2515,8 @@ uint32_t ulp_act_prop_map_table[] = { BNXT_ULP_ACT_PROP_SZ_JUMP, [BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE] = BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE, + [BNXT_ULP_ACT_PROP_IDX_RSS] = + BNXT_ULP_ACT_PROP_SZ_RSS, [BNXT_ULP_ACT_PROP_IDX_LAST] = BNXT_ULP_ACT_PROP_SZ_LAST }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c index d20e630980..5e7ba75c62 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c @@ -357,8 +357,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "use_default", @@ -402,7 +402,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 3, thor, table: parif_def_arec_ptr.ing_0 */ { @@ -411,8 +411,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 3, thor, table: parif_def_err_arec_ptr.ing_0 */ { @@ -421,8 +421,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 3, thor, table: int_full_act_record.egr_vfr */ { @@ -485,8 +485,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} }, { .description = "use_default", @@ -530,7 +530,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 3, thor, table: parif_def_arec_ptr.egr_0 */ { @@ -539,8 +539,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 3, thor, table: parif_def_err_arec_ptr.egr_0 */ { @@ -549,8 +549,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 4, thor, table: int_full_act_record.loopback */ { @@ -613,8 +613,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_THOR_SYM_LOOPBACK_PORT & 0xff} + (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_THOR_SYM_LOOPBACK_PORT & 0xff} }, { .description = "use_default", @@ -658,7 +658,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 4, thor, table: parif_def_arec_ptr.vf_egr */ { @@ -667,8 +667,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, /* class_tid: 4, thor, table: parif_def_err_arec_ptr.vf_egr */ { @@ -677,8 +677,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, /* class_tid: 4, thor, table: int_full_act_record.vf_ing */ { @@ -741,8 +741,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "use_default", @@ -786,7 +786,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 4, thor, table: vtag_encap_record.vfr_egr0 */ { @@ -819,7 +819,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "rsrvd", @@ -833,7 +833,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "vtag_tpid", @@ -850,8 +850,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} }, { .description = "vtag_de", @@ -865,8 +865,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, /* class_tid: 4, thor, table: int_full_act_record.vfr_egr0 */ { @@ -881,8 +881,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "mod_rec_ptr", @@ -932,8 +932,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_THOR_SYM_LOOPBACK_PORT & 0xff} + (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_THOR_SYM_LOOPBACK_PORT & 0xff} }, { .description = "use_default", diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c index 1d21cd3e38..9e0a6b5c18 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Sun Mar 14 12:41:59 2021 */ +/* date: Sun Mar 21 13:04:51 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -997,8 +997,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} } }, /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ @@ -1017,8 +1017,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} } } }; @@ -1062,7 +1062,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "ecv_custom_en", @@ -1076,7 +1076,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "vtag_tpid", @@ -1084,8 +1084,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} }, { .description = "vtag_vid", @@ -1093,8 +1093,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} }, { .description = "vtag_de", @@ -1108,8 +1108,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, { .description = "spare", @@ -1124,8 +1124,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -1151,14 +1151,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "tcpflags_key", @@ -1184,8 +1184,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", @@ -1193,8 +1193,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", @@ -1202,14 +1202,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, @@ -1222,8 +1222,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", @@ -1231,14 +1231,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, @@ -1269,8 +1269,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -1278,8 +1278,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -1287,20 +1287,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_DECAP_FUNC_NONE} + ULP_WP_SYM_DECAP_FUNC_NONE} }, { .description = "vnic_or_vport", @@ -1308,8 +1308,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", @@ -1317,14 +1317,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} }, { .description = "meter", @@ -1338,14 +1338,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, @@ -1358,14 +1358,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} }, { .description = "hit", @@ -1386,8 +1386,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -1413,14 +1413,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", @@ -1464,8 +1464,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", @@ -1473,14 +1473,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, @@ -1493,8 +1493,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", @@ -1502,14 +1502,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, @@ -1540,8 +1540,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -1549,8 +1549,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -1558,20 +1558,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_DECAP_FUNC_NONE} + ULP_WP_SYM_DECAP_FUNC_NONE} }, { .description = "vnic_or_vport", @@ -1579,8 +1579,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", @@ -1588,14 +1588,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} }, { .description = "meter", @@ -1609,8 +1609,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff} }, { .description = "drop", @@ -1618,14 +1618,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} }, { .description = "ecv_tun_type", @@ -1651,7 +1651,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L2_EN_YES} + ULP_WP_SYM_ECV_L2_EN_YES} }, { .description = "ecv_vtag_type", @@ -1714,7 +1714,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "copy", @@ -1754,8 +1754,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -1781,14 +1781,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "tcpflags_key", @@ -1880,8 +1880,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", @@ -1928,8 +1928,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -1955,14 +1955,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", @@ -2066,8 +2066,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", @@ -2075,14 +2075,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} }, { .description = "meter", @@ -2128,7 +2128,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L2_EN_YES} + ULP_WP_SYM_ECV_L2_EN_YES} }, { .description = "ecv_vtag_type", @@ -2185,8 +2185,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "enable", @@ -2194,7 +2194,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "copy", @@ -2227,8 +2227,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "mirror_id", @@ -2253,8 +2253,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff} }, /* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */ { @@ -2263,8 +2263,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} }, /* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */ { @@ -2291,7 +2291,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L2_EN_YES} + ULP_WP_SYM_ECV_L2_EN_YES} }, { .description = "ecv_vtag_type", @@ -2311,7 +2311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "vtag_tpid", @@ -2350,8 +2350,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -2377,14 +2377,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "tcpflags_key", @@ -2410,8 +2410,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} }, { .description = "dst_ip_ptr", @@ -2419,8 +2419,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", @@ -2428,14 +2428,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, @@ -2448,8 +2448,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", @@ -2457,14 +2457,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, @@ -2495,8 +2495,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -2504,8 +2504,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -2513,20 +2513,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_DECAP_FUNC_THRU_L2} + ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", @@ -2534,8 +2534,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", @@ -2580,8 +2580,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -2607,14 +2607,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", @@ -2646,8 +2646,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} }, { .description = "encap_rec_int", @@ -2655,7 +2655,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "dst_ip_ptr", @@ -2663,8 +2663,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", @@ -2672,14 +2672,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, @@ -2692,8 +2692,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", @@ -2701,14 +2701,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, @@ -2739,8 +2739,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -2748,8 +2748,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -2757,20 +2757,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_DECAP_FUNC_THRU_L2} + ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", @@ -2778,8 +2778,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} }, { .description = "pop_vlan", @@ -2829,7 +2829,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L2_EN_YES} + ULP_WP_SYM_ECV_L2_EN_YES} }, { .description = "ecv_vtag_type", @@ -2917,7 +2917,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "ecv_custom_en", @@ -2931,7 +2931,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "vtag_tpid", @@ -2939,8 +2939,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} }, { .description = "vtag_vid", @@ -2948,8 +2948,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} }, { .description = "vtag_de", @@ -2963,8 +2963,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, { .description = "spare", @@ -2979,8 +2979,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -3006,14 +3006,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "tcpflags_key", @@ -3039,8 +3039,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", @@ -3090,8 +3090,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -3099,8 +3099,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -3114,8 +3114,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", @@ -3141,14 +3141,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} }, { .description = "hit", @@ -3169,8 +3169,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -3196,14 +3196,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", @@ -3289,8 +3289,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -3298,8 +3298,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -3313,8 +3313,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", @@ -3340,14 +3340,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} }, { .description = "ecv_tun_type", @@ -3373,7 +3373,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L2_EN_YES} + ULP_WP_SYM_ECV_L2_EN_YES} }, { .description = "ecv_vtag_type", @@ -3430,8 +3430,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -3457,14 +3457,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", @@ -3550,8 +3550,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -3559,8 +3559,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -3574,8 +3574,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", @@ -3583,14 +3583,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff} }, { .description = "meter", @@ -3610,14 +3610,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} }, { .description = "ecv_tun_type", @@ -3649,7 +3649,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "ecv_custom_en", @@ -3663,7 +3663,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "vtag_tpid", @@ -3671,8 +3671,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff} }, { .description = "vtag_vid", @@ -3680,8 +3680,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff} }, { .description = "vtag_de", @@ -3695,8 +3695,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, { .description = "spare", @@ -3718,8 +3718,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff} }, /* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */ { @@ -3728,8 +3728,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} }, /* act_tid: 5, wh_plus, table: int_encap_mac_record.dummy */ { @@ -3756,7 +3756,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L2_EN_YES} + ULP_WP_SYM_ECV_L2_EN_YES} }, { .description = "ecv_vtag_type", @@ -3776,7 +3776,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "vtag_tpid", @@ -3815,8 +3815,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -3842,14 +3842,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "tcpflags_key", @@ -3875,8 +3875,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} }, { .description = "dst_ip_ptr", @@ -3884,8 +3884,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", @@ -3893,14 +3893,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, @@ -3913,8 +3913,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", @@ -3922,14 +3922,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, @@ -3960,8 +3960,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -3969,8 +3969,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -3978,20 +3978,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_DECAP_FUNC_THRU_L2} + ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", @@ -3999,8 +3999,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", @@ -4045,8 +4045,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -4072,14 +4072,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", @@ -4111,8 +4111,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff} }, { .description = "encap_rec_int", @@ -4120,7 +4120,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "dst_ip_ptr", @@ -4128,8 +4128,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff} }, { .description = "tcp_dst_port", @@ -4137,14 +4137,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, @@ -4157,8 +4157,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff} }, { .description = "tcp_src_port", @@ -4166,14 +4166,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, @@ -4204,8 +4204,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "tl3_ttl_dec", @@ -4213,8 +4213,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "decap_func", @@ -4222,20 +4222,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_DECAP_FUNC_THRU_L2} + ULP_WP_SYM_DECAP_FUNC_THRU_L2} }, { .description = "vnic_or_vport", @@ -4243,8 +4243,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", @@ -4294,7 +4294,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L2_EN_YES} + ULP_WP_SYM_ECV_L2_EN_YES} }, { .description = "ecv_vtag_type", @@ -4358,8 +4358,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff} }, { .description = "ipv4_src_addr", @@ -4367,8 +4367,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff} }, { .description = "reserved", @@ -4383,8 +4383,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff} }, { .description = "ipv6_src_addr", @@ -4392,8 +4392,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff} }, { .description = "reserved", @@ -4408,7 +4408,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_TUN_TYPE_VXLAN} + ULP_WP_SYM_ECV_TUN_TYPE_VXLAN} }, { .description = "ecv_l4_type", @@ -4416,7 +4416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM} + ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM} }, { .description = "ecv_l3_type", @@ -4424,8 +4424,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} }, { .description = "ecv_l2_en", @@ -4433,7 +4433,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "ecv_vtag_type", @@ -4441,8 +4441,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} }, { .description = "ecv_custom_en", @@ -4456,7 +4456,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "encap_l2_dmac", @@ -4464,8 +4464,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff} }, { .description = "encap_vtag", @@ -4495,8 +4495,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff} }, { .description = "encap_tun", @@ -4516,8 +4516,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -4543,14 +4543,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "tcpflags_key", @@ -4576,8 +4576,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", @@ -4645,8 +4645,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", @@ -4691,8 +4691,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} }, { .description = "age_enable", @@ -4718,14 +4718,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff} }, { .description = "flow_cntr_ext", @@ -4829,8 +4829,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} }, { .description = "pop_vlan", @@ -4862,7 +4862,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_TUN_TYPE_VXLAN} + ULP_WP_SYM_ECV_TUN_TYPE_VXLAN} }, { .description = "ecv_l4_type", @@ -4870,7 +4870,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM} + ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM} }, { .description = "ecv_l3_type", @@ -4878,8 +4878,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} }, { .description = "ecv_l2_en", @@ -4887,7 +4887,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "ecv_vtag_type", @@ -4895,8 +4895,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} }, { .description = "ecv_custom_en", @@ -4910,7 +4910,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "encap_l2_dmac", @@ -4918,8 +4918,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff} }, { .description = "encap_vtag", @@ -4949,8 +4949,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff} }, { .description = "encap_tun", @@ -4958,8 +4958,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff} + (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff} } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index 4e0cd66126..ca385b66f9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Mar 15 10:26:20 2021 */ +/* date: Sun Mar 21 13:04:51 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1846,8 +1846,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", @@ -1855,8 +1855,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ @@ -1867,8 +1867,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", @@ -1876,8 +1876,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { @@ -1885,13 +1885,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -1909,8 +1913,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { @@ -1920,14 +1924,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -1940,14 +1944,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -1962,8 +1966,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "mac_addr", @@ -1971,8 +1975,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ @@ -1983,14 +1987,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -2003,14 +2007,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -2039,8 +2043,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "mac0_addr", @@ -2048,8 +2052,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { @@ -2059,8 +2063,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", @@ -2068,8 +2072,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { @@ -2143,8 +2147,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} } }, { @@ -2166,13 +2170,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -2196,7 +2204,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -2204,7 +2212,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ @@ -2215,8 +2223,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", @@ -2224,8 +2232,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { @@ -2233,13 +2241,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -2257,8 +2269,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { @@ -2268,14 +2280,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -2288,14 +2300,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -2310,8 +2322,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "mac_addr", @@ -2319,8 +2331,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ @@ -2355,16 +2367,16 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { @@ -2382,8 +2394,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ @@ -2408,8 +2420,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ONES, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -2419,20 +2431,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { @@ -2442,8 +2454,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { .description = "l4_hdr_error", @@ -2459,8 +2471,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { .description = "l4_hdr_valid", @@ -2468,8 +2480,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} } }, { @@ -2561,7 +2573,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { @@ -2595,8 +2607,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { @@ -2662,7 +2674,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + ULP_WP_SYM_L2_HDR_VALID_YES} } }, { @@ -2982,16 +2994,16 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { @@ -3057,7 +3069,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -3065,7 +3077,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ @@ -3090,8 +3102,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ONES, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -3101,20 +3113,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { @@ -3124,8 +3136,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { .description = "l4_hdr_error", @@ -3141,8 +3153,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { .description = "l4_hdr_valid", @@ -3150,8 +3162,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} } }, { @@ -3211,7 +3223,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV6} + ULP_WP_SYM_L3_HDR_TYPE_IPV6} } }, { @@ -3245,7 +3257,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { @@ -3279,8 +3291,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { @@ -3346,7 +3358,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + ULP_WP_SYM_L2_HDR_VALID_YES} } }, { @@ -3666,16 +3678,16 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { @@ -3741,7 +3753,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -3749,7 +3761,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ @@ -3782,7 +3794,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { @@ -4044,7 +4056,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_TUN_HDR_VALID_YES} + ULP_WP_SYM_TUN_HDR_VALID_YES} } }, { @@ -4104,7 +4116,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_TL4_HDR_VALID_YES} + ULP_WP_SYM_TL4_HDR_VALID_YES} } }, { @@ -4194,7 +4206,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_TL3_HDR_VALID_YES} + ULP_WP_SYM_TL3_HDR_VALID_YES} } }, { @@ -4270,7 +4282,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_TL2_HDR_VALID_YES} + ULP_WP_SYM_TL2_HDR_VALID_YES} } }, { @@ -4316,8 +4328,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} } }, { @@ -4383,7 +4395,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -4391,7 +4403,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ @@ -4426,16 +4438,16 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { @@ -4453,8 +4465,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, /* class_tid: 1, wh_plus, table: em.ipv4 */ @@ -4502,8 +4514,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, @@ -4527,8 +4539,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, @@ -4551,8 +4563,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, @@ -4567,8 +4579,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", @@ -4576,8 +4588,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { @@ -4587,8 +4599,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", @@ -4596,8 +4608,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { @@ -4607,8 +4619,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "l2.smac", @@ -4616,8 +4628,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { @@ -4636,8 +4648,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -4655,8 +4667,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 1, wh_plus, table: eem.ipv4 */ @@ -4704,8 +4716,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, @@ -4729,8 +4741,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, @@ -4753,8 +4765,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, @@ -4769,8 +4781,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", @@ -4778,8 +4790,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { @@ -4789,8 +4801,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", @@ -4798,8 +4810,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { @@ -4809,8 +4821,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "l2.smac", @@ -4818,8 +4830,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { @@ -4838,8 +4850,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -4857,8 +4869,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 1, wh_plus, table: em.ipv6 */ @@ -4906,8 +4918,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, @@ -4931,8 +4943,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, @@ -4955,8 +4967,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, @@ -4971,8 +4983,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", @@ -4980,8 +4992,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { @@ -4991,8 +5003,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", @@ -5000,8 +5012,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { @@ -5011,8 +5023,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "l2.smac", @@ -5020,8 +5032,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { @@ -5054,8 +5066,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -5073,8 +5085,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 1, wh_plus, table: eem.ipv6 */ @@ -5122,8 +5134,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, @@ -5147,8 +5159,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, @@ -5171,8 +5183,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, @@ -5187,8 +5199,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", @@ -5196,8 +5208,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { @@ -5207,8 +5219,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", @@ -5216,8 +5228,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { @@ -5227,8 +5239,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "l2.smac", @@ -5236,8 +5248,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { @@ -5270,8 +5282,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -5289,8 +5301,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 1, wh_plus, table: em.vxlan */ @@ -5352,8 +5364,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (4789 >> 8) & 0xff, - 4789 & 0xff} + (4789 >> 8) & 0xff, + 4789 & 0xff} } }, { @@ -5371,7 +5383,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 17} + 17} } }, { @@ -5381,8 +5393,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "tl3.dst", @@ -5390,8 +5402,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { @@ -5452,8 +5464,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -5471,8 +5483,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 1, wh_plus, table: eem.vxlan */ @@ -5520,8 +5532,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (4789 >> 8) & 0xff, - 4789 & 0xff} + (4789 >> 8) & 0xff, + 4789 & 0xff} } }, { @@ -5553,7 +5565,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 17} + 17} } }, { @@ -5563,8 +5575,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "tl3.dst", @@ -5572,8 +5584,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { @@ -5634,8 +5646,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -5653,8 +5665,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ @@ -5665,8 +5677,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", @@ -5674,8 +5686,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ @@ -5686,8 +5698,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", @@ -5695,8 +5707,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { @@ -5704,13 +5716,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -5728,8 +5744,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { @@ -5739,14 +5755,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -5759,14 +5775,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -5781,8 +5797,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "mac_addr", @@ -5790,8 +5806,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ @@ -5802,14 +5818,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -5822,14 +5838,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -5858,8 +5874,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "mac0_addr", @@ -5867,8 +5883,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, { @@ -5878,8 +5894,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", @@ -5887,8 +5903,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { @@ -5962,8 +5978,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} } }, { @@ -5985,13 +6001,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -6015,7 +6035,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -6023,7 +6043,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ @@ -6034,8 +6054,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { .description = "svif", @@ -6043,8 +6063,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { @@ -6052,13 +6072,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -6076,8 +6100,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { @@ -6087,14 +6111,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -6107,14 +6131,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, @@ -6129,8 +6153,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { .description = "mac_addr", @@ -6138,8 +6162,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ @@ -6174,16 +6198,16 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { @@ -6201,8 +6225,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ @@ -6227,8 +6251,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ONES, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6238,20 +6262,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { @@ -6261,8 +6285,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { .description = "l4_hdr_error", @@ -6278,8 +6302,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { .description = "l4_hdr_valid", @@ -6287,8 +6311,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} } }, { @@ -6380,7 +6404,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { @@ -6414,8 +6438,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { @@ -6481,7 +6505,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + ULP_WP_SYM_L2_HDR_VALID_YES} } }, { @@ -6801,16 +6825,16 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { @@ -6876,7 +6900,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -6884,7 +6908,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ @@ -6909,8 +6933,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ONES, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, @@ -6920,20 +6944,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { @@ -6943,8 +6967,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { .description = "l4_hdr_error", @@ -6960,8 +6984,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { .description = "l4_hdr_valid", @@ -6969,8 +6993,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} } }, { @@ -7030,7 +7054,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV6} + ULP_WP_SYM_L3_HDR_TYPE_IPV6} } }, { @@ -7064,7 +7088,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { @@ -7098,8 +7122,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { @@ -7165,7 +7189,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + ULP_WP_SYM_L2_HDR_VALID_YES} } }, { @@ -7485,16 +7509,16 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { @@ -7560,7 +7584,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -7568,7 +7592,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ @@ -7603,16 +7627,16 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { @@ -7630,8 +7654,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, /* class_tid: 2, wh_plus, table: em.ipv4 */ @@ -7679,8 +7703,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, @@ -7704,8 +7728,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, @@ -7728,8 +7752,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, @@ -7744,8 +7768,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", @@ -7753,8 +7777,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { @@ -7764,8 +7788,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", @@ -7773,8 +7797,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { @@ -7784,8 +7808,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "l2.dmac", @@ -7793,8 +7817,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { @@ -7813,8 +7837,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -7832,8 +7856,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 2, wh_plus, table: eem.ipv4 */ @@ -7881,8 +7905,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, @@ -7906,8 +7930,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, @@ -7930,8 +7954,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, @@ -7946,8 +7970,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", @@ -7955,8 +7979,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { @@ -7966,8 +7990,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", @@ -7975,8 +7999,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { @@ -7986,8 +8010,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "l2.dmac", @@ -7995,8 +8019,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { @@ -8015,8 +8039,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -8034,8 +8058,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 2, wh_plus, table: em.ipv6 */ @@ -8083,8 +8107,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, @@ -8108,8 +8132,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, @@ -8132,8 +8156,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, @@ -8148,8 +8172,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", @@ -8157,8 +8181,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { @@ -8168,8 +8192,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", @@ -8177,8 +8201,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { @@ -8202,8 +8226,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "l2.dmac", @@ -8211,8 +8235,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { @@ -8231,8 +8255,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -8250,8 +8274,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 2, wh_plus, table: eem.ipv6 */ @@ -8299,8 +8323,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, @@ -8324,8 +8348,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, @@ -8348,8 +8372,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, @@ -8364,8 +8388,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { .description = "l3.dst", @@ -8373,8 +8397,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { @@ -8384,8 +8408,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { .description = "l3.src", @@ -8393,8 +8417,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { @@ -8418,8 +8442,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "l2.dmac", @@ -8427,8 +8451,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { @@ -8447,8 +8471,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { @@ -8466,8 +8490,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_rd */ @@ -8486,8 +8510,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ @@ -8548,8 +8572,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, { @@ -8641,13 +8665,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -8671,7 +8699,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -8679,7 +8707,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_wr */ @@ -8698,8 +8726,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_rd_vfr */ @@ -8718,8 +8746,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.egr_vfr */ @@ -8780,8 +8808,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { @@ -8873,13 +8901,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -8903,7 +8935,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -8911,7 +8943,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr_vfr */ @@ -8930,8 +8962,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ @@ -8950,8 +8982,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ @@ -9012,8 +9044,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { @@ -9105,13 +9137,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -9135,7 +9171,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -9143,7 +9179,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ @@ -9162,8 +9198,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_rd_egr */ @@ -9182,8 +9218,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ @@ -9244,8 +9280,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { @@ -9337,13 +9373,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -9367,7 +9407,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -9375,7 +9415,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_egr_wr */ @@ -9394,8 +9434,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vf_ing */ @@ -9456,8 +9496,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, { @@ -9549,13 +9589,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -9579,7 +9623,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -9587,7 +9631,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ @@ -9606,8 +9650,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_egr0 */ @@ -9668,8 +9712,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { @@ -9761,13 +9805,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -9791,7 +9839,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -9799,7 +9847,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ @@ -9818,8 +9866,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ @@ -9853,8 +9901,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { @@ -9886,8 +9934,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { @@ -9961,7 +10009,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 2} + 2} } }, { @@ -9993,7 +10041,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -10017,7 +10065,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -10025,7 +10073,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ @@ -10045,8 +10093,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, { @@ -10092,8 +10140,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, { @@ -10167,7 +10215,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } }, { @@ -10199,7 +10247,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { @@ -10223,7 +10271,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, .field_info_spec = { .description = "valid", @@ -10231,7 +10279,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} } } }; @@ -10244,8 +10292,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", @@ -10253,8 +10301,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", @@ -10268,8 +10316,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, { .description = "allowed_pri", @@ -10313,7 +10361,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -10334,8 +10382,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", @@ -10349,8 +10397,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", @@ -10383,7 +10431,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "em_key_mask.1", @@ -10391,8 +10439,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, { .description = "em_key_mask.2", @@ -10400,8 +10448,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, { .description = "em_key_mask.3", @@ -10409,8 +10457,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, { .description = "em_key_mask.4", @@ -10418,8 +10466,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} }, { .description = "em_key_mask.5", @@ -10427,16 +10475,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} }, { .description = "em_key_mask.6", @@ -10444,16 +10492,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} }, { .description = "em_key_mask.7", @@ -10479,7 +10527,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "em_profile_id", @@ -10487,8 +10535,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "em_search_en", @@ -10496,7 +10544,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pl_byp_lkup_en", @@ -10529,7 +10577,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "em_key_mask.1", @@ -10543,8 +10591,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, { .description = "em_key_mask.3", @@ -10552,8 +10600,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, { .description = "em_key_mask.4", @@ -10561,8 +10609,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, { .description = "em_key_mask.5", @@ -10570,8 +10618,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} }, { .description = "em_key_mask.6", @@ -10579,16 +10627,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} }, { .description = "em_key_mask.7", @@ -10596,16 +10644,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} }, { .description = "em_key_mask.8", @@ -10625,7 +10673,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 7} + 7} }, { .description = "em_profile_id", @@ -10633,8 +10681,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "em_search_en", @@ -10642,7 +10690,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pl_byp_lkup_en", @@ -10675,7 +10723,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "em_key_mask.1", @@ -10701,7 +10749,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "em_key_mask.5", @@ -10709,7 +10757,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "em_key_mask.6", @@ -10717,7 +10765,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "em_key_mask.7", @@ -10743,7 +10791,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 20} + 20} }, { .description = "em_profile_id", @@ -10751,8 +10799,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "em_search_en", @@ -10760,7 +10808,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pl_byp_lkup_en", @@ -10775,8 +10823,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "profile_tcam_index", @@ -10784,8 +10832,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} }, { .description = "em_profile_id", @@ -10793,8 +10841,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "wc_profile_id", @@ -10808,8 +10856,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, /* class_tid: 1, wh_plus, table: em.ipv4 */ { @@ -10818,8 +10866,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -10857,7 +10905,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -10871,7 +10919,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 1, wh_plus, table: eem.ipv4 */ { @@ -10880,8 +10928,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -10901,8 +10949,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { .description = "key_size", @@ -10910,8 +10958,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (173 >> 8) & 0xff, - 173 & 0xff} + (173 >> 8) & 0xff, + 173 & 0xff} }, { .description = "reserved", @@ -10925,7 +10973,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -10939,7 +10987,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 1, wh_plus, table: em.ipv6 */ { @@ -10948,8 +10996,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -10987,7 +11035,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -11001,7 +11049,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 1, wh_plus, table: eem.ipv6 */ { @@ -11010,8 +11058,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -11031,8 +11079,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { .description = "key_size", @@ -11040,8 +11088,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (413 >> 8) & 0xff, - 413 & 0xff} + (413 >> 8) & 0xff, + 413 & 0xff} }, { .description = "reserved", @@ -11055,7 +11103,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -11069,7 +11117,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 1, wh_plus, table: em.vxlan */ { @@ -11078,8 +11126,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -11117,7 +11165,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -11131,7 +11179,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 1, wh_plus, table: eem.vxlan */ { @@ -11140,8 +11188,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -11161,8 +11209,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { .description = "key_size", @@ -11170,8 +11218,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (197 >> 8) & 0xff, - 197 & 0xff} + (197 >> 8) & 0xff, + 197 & 0xff} }, { .description = "reserved", @@ -11185,7 +11233,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -11199,7 +11247,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ { @@ -11208,8 +11256,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", @@ -11217,8 +11265,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", @@ -11232,15 +11280,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff}, + (BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff, + BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_WP_SYM_LOOPBACK_PARIF}, .field_src3 = BNXT_ULP_FIELD_SRC_CF, .field_opr3 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", @@ -11278,8 +11326,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff} }, { .description = "byp_sp_lkup", @@ -11287,7 +11335,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -11308,8 +11356,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", @@ -11317,8 +11365,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", @@ -11326,8 +11374,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", @@ -11360,7 +11408,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "em_key_mask.1", @@ -11368,8 +11416,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, { .description = "em_key_mask.2", @@ -11377,8 +11425,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, { .description = "em_key_mask.3", @@ -11386,8 +11434,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, { .description = "em_key_mask.4", @@ -11395,8 +11443,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} }, { .description = "em_key_mask.5", @@ -11404,16 +11452,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} }, { .description = "em_key_mask.6", @@ -11421,16 +11469,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} }, { .description = "em_key_mask.7", @@ -11456,7 +11504,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 4} + 4} }, { .description = "em_profile_id", @@ -11464,8 +11512,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "em_search_en", @@ -11473,7 +11521,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pl_byp_lkup_en", @@ -11506,7 +11554,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "em_key_mask.1", @@ -11514,8 +11562,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, { .description = "em_key_mask.2", @@ -11529,8 +11577,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, { .description = "em_key_mask.4", @@ -11538,8 +11586,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, { .description = "em_key_mask.5", @@ -11547,8 +11595,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} }, { .description = "em_key_mask.6", @@ -11556,16 +11604,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} }, { .description = "em_key_mask.7", @@ -11573,16 +11621,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} }, { .description = "em_key_mask.8", @@ -11602,7 +11650,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 7} + 7} }, { .description = "em_profile_id", @@ -11610,8 +11658,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "em_search_en", @@ -11619,7 +11667,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pl_byp_lkup_en", @@ -11634,8 +11682,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "profile_tcam_index", @@ -11643,8 +11691,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} }, { .description = "em_profile_id", @@ -11652,8 +11700,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { .description = "wc_profile_id", @@ -11667,8 +11715,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, /* class_tid: 2, wh_plus, table: em.ipv4 */ { @@ -11677,8 +11725,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -11716,7 +11764,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -11730,7 +11778,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 2, wh_plus, table: eem.ipv4 */ { @@ -11739,8 +11787,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -11760,8 +11808,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { .description = "key_size", @@ -11769,8 +11817,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (173 >> 8) & 0xff, - 173 & 0xff} + (173 >> 8) & 0xff, + 173 & 0xff} }, { .description = "reserved", @@ -11784,7 +11832,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -11798,7 +11846,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 2, wh_plus, table: em.ipv6 */ { @@ -11807,8 +11855,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -11846,7 +11894,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -11860,7 +11908,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 2, wh_plus, table: eem.ipv6 */ { @@ -11869,8 +11917,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "ext_flow_cntr", @@ -11890,8 +11938,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { .description = "key_size", @@ -11899,8 +11947,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (413 >> 8) & 0xff, - 413 & 0xff} + (413 >> 8) & 0xff, + 413 & 0xff} }, { .description = "reserved", @@ -11914,7 +11962,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 3} + 3} }, { .description = "l1_cacheable", @@ -11928,7 +11976,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, /* class_tid: 3, wh_plus, table: int_full_act_record.ing_0 */ { @@ -12051,8 +12099,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", @@ -12097,8 +12145,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", @@ -12106,8 +12154,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", @@ -12121,8 +12169,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, { .description = "allowed_pri", @@ -12166,7 +12214,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -12187,8 +12235,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", @@ -12196,8 +12244,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", @@ -12205,8 +12253,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", @@ -12221,8 +12269,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.ing_0 */ { @@ -12231,8 +12279,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.ing_0 */ { @@ -12241,8 +12289,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 3, wh_plus, table: int_full_act_record.egr_vfr */ { @@ -12365,8 +12413,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} }, { .description = "pop_vlan", @@ -12423,7 +12471,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "parif", @@ -12431,8 +12479,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", @@ -12464,7 +12512,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "sp_rec_ptr", @@ -12478,7 +12526,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -12499,8 +12547,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", @@ -12508,8 +12556,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", @@ -12530,8 +12578,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", @@ -12539,8 +12587,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", @@ -12554,8 +12602,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, { .description = "allowed_pri", @@ -12599,7 +12647,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -12620,8 +12668,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", @@ -12629,8 +12677,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", @@ -12638,8 +12686,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", @@ -12768,8 +12816,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} }, { .description = "pop_vlan", @@ -12814,8 +12862,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.egr_0 */ { @@ -12824,8 +12872,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.egr_0 */ { @@ -12834,8 +12882,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, /* class_tid: 4, wh_plus, table: int_full_act_record.loopback */ { @@ -12958,8 +13006,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_WP_SYM_LOOPBACK_PORT & 0xff} + (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_WP_SYM_LOOPBACK_PORT & 0xff} }, { .description = "pop_vlan", @@ -13004,8 +13052,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "prof_func_id", @@ -13013,8 +13061,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { .description = "l2_byp_lkup_en", @@ -13028,7 +13076,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_LOOPBACK_PARIF} + ULP_WP_SYM_LOOPBACK_PARIF} }, { .description = "allowed_pri", @@ -13072,7 +13120,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -13093,8 +13141,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", @@ -13102,8 +13150,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", @@ -13111,8 +13159,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { .description = "src_property_ptr", @@ -13127,8 +13175,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.vf_egr */ { @@ -13137,8 +13185,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.vf_egr */ { @@ -13147,8 +13195,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, /* class_tid: 4, wh_plus, table: int_full_act_record.vf_ing */ { @@ -13271,8 +13319,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", @@ -13317,8 +13365,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", @@ -13332,7 +13380,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "parif", @@ -13382,7 +13430,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -13415,7 +13463,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "parif", @@ -13453,7 +13501,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "sp_rec_ptr", @@ -13467,7 +13515,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -13488,8 +13536,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { .description = "l2_cntxt_tcam_index", @@ -13497,8 +13545,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { .description = "l2_cntxt_id", @@ -13543,7 +13591,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} + ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { .description = "ecv_custom_en", @@ -13557,7 +13605,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "vtag_tpid", @@ -13574,8 +13622,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} }, { .description = "vtag_de", @@ -13650,8 +13698,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "dst_ip_ptr", @@ -13719,8 +13767,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_WP_SYM_LOOPBACK_PORT & 0xff} + (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_WP_SYM_LOOPBACK_PORT & 0xff} }, { .description = "pop_vlan", @@ -13879,8 +13927,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff} + (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff} }, { .description = "pop_vlan", @@ -13888,7 +13936,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "meter", @@ -13927,8 +13975,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", @@ -13942,7 +13990,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "parif", @@ -13992,7 +14040,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", @@ -14013,8 +14061,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { .description = "reserved", @@ -14028,7 +14076,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "parif", @@ -14078,7 +14126,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 1} }, { .description = "pri_anti_spoof_ctl", diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 72d0df98a8..2d03ea4fdb 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -284,6 +284,9 @@ struct bnxt_ulp_mapper_tbl_info { /* FDB table opcode */ enum bnxt_ulp_fdb_opc fdb_opcode; uint32_t fdb_operand; + + /* Shared session */ + enum bnxt_ulp_shared_session shared_session; }; struct bnxt_ulp_mapper_field_info { From patchwork Sun May 30 08:59:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93594 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7FE3A0524; Sun, 30 May 2021 11:07:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 963A441187; Sun, 30 May 2021 11:02:08 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 7653B41104 for ; Sun, 30 May 2021 11:02:03 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 14CCD7DC2; Sun, 30 May 2021 02:02:01 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 14CCD7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365323; bh=ZxkNxdvaPiIN3EIl57AucD8p42zteKivMfUKrzWc2zE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AFSe/wyJ4kEhyOYHtM4GkVvmIMSaMm5c0lul+pMRqn5SzU80Lx/wE7FgwdtZ9dqgE 8SDCYiDNjsF1KEYLdMqtsykrLE4QWX7mZsyxsvvPsKOWXzAJ0c2c+jrHjI/0SCDGHJ x8zp8KpuOBIGd8MJOJ3Vhxs1v+EvOysmQ7+/W+tA= From: Venkat Duvvuru To: dev@dpdk.org Cc: Mike Baucom , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:24 +0530 Message-Id: <20210530085929.29695-54-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 53/58] net/bnxt: add HA support in ULP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Mike Baucom Added the ability for cooperative applications to share resources and perform some high availability functions. Signed-off-by: Mike Baucom Signed-off-by: Venkat Duvvuru Reviewed-by: Shahaji Bhosle Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 59 +++ drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 10 + drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 15 +- drivers/net/bnxt/tf_ulp/meson.build | 1 + drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 551 ++++++++++++++++++++++++ drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 67 +++ drivers/net/bnxt/tf_ulp/ulp_mapper.c | 52 ++- 7 files changed, 745 insertions(+), 10 deletions(-) create mode 100644 drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 0daa8e4c29..972bf8b992 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -23,6 +23,7 @@ #include "ulp_mapper.h" #include "ulp_port_db.h" #include "ulp_tun.h" +#include "ulp_ha_mgr.h" /* Linked list of all TF sessions. */ STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list = @@ -315,6 +316,9 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, if (info[i].flags & BNXT_ULP_APP_CAP_SHARED_EN) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_SHARED_SESSION_ENABLED; + if (info[i].flags & BNXT_ULP_APP_CAP_HOT_UPGRADE_EN) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_HIGH_AVAIL_ENABLED; } if (!found) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -1137,9 +1141,18 @@ static void bnxt_ulp_deinit(struct bnxt *bp, struct bnxt_ulp_session_state *session) { + bool ha_enabled; + if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data) return; + ha_enabled = bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx); + if (ha_enabled && session->session_opened) { + int32_t rc = ulp_ha_mgr_close(bp->ulp_ctx); + if (rc) + BNXT_TF_DBG(ERR, "Failed to close HA (%d)\n", rc); + } + /* clean up default flows */ bnxt_ulp_destroy_df_rules(bp, true); @@ -1179,6 +1192,9 @@ bnxt_ulp_deinit(struct bnxt *bp, /* free the flow db lock */ pthread_mutex_destroy(&bp->ulp_ctx->cfg_data->flow_db_lock); + if (ha_enabled) + ulp_ha_mgr_deinit(bp->ulp_ctx); + /* Delete the ulp context and tf session and free the ulp context */ ulp_ctx_deinit(bp, session); BNXT_TF_DBG(DEBUG, "ulp ctx has been deinitialized\n"); @@ -1275,6 +1291,19 @@ bnxt_ulp_init(struct bnxt *bp, BNXT_TF_DBG(ERR, "Failed to set tx global configuration\n"); goto jump_to_error; } + + if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx)) { + rc = ulp_ha_mgr_init(bp->ulp_ctx); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to initialize HA %d\n", rc); + goto jump_to_error; + } + rc = ulp_ha_mgr_open(bp->ulp_ctx); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to Process HA Open %d\n", rc); + goto jump_to_error; + } + } BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n"); return rc; @@ -1828,3 +1857,33 @@ bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx) pthread_mutex_unlock(&ulp_ctx->cfg_data->flow_db_lock); } + +/* Function to set the ha info into the context */ +int32_t +bnxt_ulp_cntxt_ptr2_ha_info_set(struct bnxt_ulp_context *ulp_ctx, + struct bnxt_ulp_ha_mgr_info *ulp_ha_info) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) { + BNXT_TF_DBG(ERR, "Invalid ulp context data\n"); + return -EINVAL; + } + ulp_ctx->cfg_data->ha_info = ulp_ha_info; + return 0; +} + +/* Function to retrieve the ha info from the context. */ +struct bnxt_ulp_ha_mgr_info * +bnxt_ulp_cntxt_ptr2_ha_info_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return NULL; + return ulp_ctx->cfg_data->ha_info; +} + +bool +bnxt_ulp_cntxt_ha_enabled(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return false; + return !!ULP_HIGH_AVAIL_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags); +} diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 1ba67ed9f6..b1f090a5cb 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -67,6 +67,7 @@ struct bnxt_ulp_data { void *mapper_data; struct bnxt_ulp_port_db *port_db; struct bnxt_ulp_fc_info *fc_info; + struct bnxt_ulp_ha_mgr_info *ha_info; uint32_t ulp_flags; struct bnxt_ulp_df_rule_info df_rule_info[RTE_MAX_ETHPORTS]; struct bnxt_ulp_vfr_rule_info vfr_rule_info[RTE_MAX_ETHPORTS]; @@ -275,4 +276,13 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_resource_resv_info * bnxt_ulp_resource_resv_list_get(uint32_t *num_entries); +int32_t +bnxt_ulp_cntxt_ptr2_ha_info_set(struct bnxt_ulp_context *ulp_ctx, + struct bnxt_ulp_ha_mgr_info *ulp_ha_info); + +struct bnxt_ulp_ha_mgr_info * +bnxt_ulp_cntxt_ptr2_ha_info_get(struct bnxt_ulp_context *ulp_ctx); + +bool +bnxt_ulp_cntxt_ha_enabled(struct bnxt_ulp_context *ulp_ctx); #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 9c27217573..96e6a76270 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -11,6 +11,7 @@ #include "ulp_mapper.h" #include "ulp_fc_mgr.h" #include "ulp_port_db.h" +#include "ulp_ha_mgr.h" #include static int32_t @@ -112,11 +113,17 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, /* update the WC Priority flag */ if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) && ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { - /* TBD: read the state and Set the WC priority */ - ULP_COMP_FLD_IDX_WR(params, - BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, 1); + enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW; + int32_t rc; + + rc = ulp_ha_mgr_region_get(params->ulp_ctx, ®ion); + if (rc) + BNXT_TF_DBG(ERR, "Unable to get WC region\n"); + if (region == ULP_HA_REGION_HI) + ULP_COMP_FLD_IDX_WR(params, + BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, + 1); } - } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build index 1bb93d4938..40479c5936 100644 --- a/drivers/net/bnxt/tf_ulp/meson.build +++ b/drivers/net/bnxt/tf_ulp/meson.build @@ -24,6 +24,7 @@ sources += files( 'ulp_tun.c', 'ulp_gen_tbl.c', 'ulp_gen_hash.c', + 'ulp_ha_mgr.c', 'ulp_rte_handler_tbl.c', 'ulp_template_db_wh_plus_act.c', 'ulp_template_db_wh_plus_class.c', diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c new file mode 100644 index 0000000000..dc71054f46 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c @@ -0,0 +1,551 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "bnxt.h" +#include "bnxt_ulp.h" +#include "bnxt_tf_common.h" +#include "ulp_ha_mgr.h" +#include "ulp_flow_db.h" + +/* Local only MACROs and defines that aren't exported */ +#define ULP_HA_TIMER_THREAD (1 << 0) +#define ULP_HA_TIMER_IS_RUNNING(info) (!!((info)->flags & ULP_HA_TIMER_THREAD)) +#define ULP_HA_TIMER_SEC 1 +#define ULP_HA_WAIT_TIME (MS_PER_S / 10) +#define ULP_HA_WAIT_TIMEOUT (MS_PER_S * 2) + +#define ULP_HA_IF_TBL_DIR TF_DIR_RX +#define ULP_HA_IF_TBL_TYPE TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR +#define ULP_HA_IF_TBL_IDX 10 + +static void ulp_ha_mgr_timer_cancel(struct bnxt_ulp_context *ulp_ctx); +static int32_t ulp_ha_mgr_timer_start(struct bnxt_ulp_context *ulp_ctx); +static void ulp_ha_mgr_timer_cb(void *arg); +static int32_t ulp_ha_mgr_app_type_set(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_app_type app_type); +static int32_t +ulp_ha_mgr_region_set(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_region region); +static int32_t +ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_state state); + +static int32_t +ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_state state) +{ + struct tf_set_if_tbl_entry_parms set_parms = { 0 }; + struct tf *tfp; + uint32_t val = 0; + int32_t rc = 0; + + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "Invalid parms in state get.\n"); + return -EINVAL; + } + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); + if (tfp == NULL) { + BNXT_TF_DBG(ERR, "Unable to get the TFP.\n"); + return -EINVAL; + } + + val = (uint32_t)state; + + set_parms.dir = ULP_HA_IF_TBL_DIR; + set_parms.type = ULP_HA_IF_TBL_TYPE; + set_parms.data = (uint8_t *)&val; + set_parms.data_sz_in_bytes = sizeof(val); + set_parms.idx = ULP_HA_IF_TBL_IDX; + + rc = tf_set_if_tbl_entry(tfp, &set_parms); + if (rc) + BNXT_TF_DBG(ERR, "Failed to write the HA state\n"); + + return rc; +} + +static int32_t +ulp_ha_mgr_region_set(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_region region) +{ + struct bnxt_ulp_ha_mgr_info *ha_info; + + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "Invalid params in ha region get.\n"); + return -EINVAL; + } + + ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); + if (ha_info == NULL) { + BNXT_TF_DBG(ERR, "Unable to get ha info\n"); + return -EINVAL; + } + ha_info->region = region; + + return 0; +} + +static int32_t +ulp_ha_mgr_app_type_set(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_app_type app_type) +{ + struct bnxt_ulp_ha_mgr_info *ha_info; + + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "Invalid Parms.\n"); + return -EINVAL; + } + + ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); + if (ha_info == NULL) { + BNXT_TF_DBG(ERR, "Unable to get the ha info.\n"); + return -EINVAL; + } + ha_info->app_type = app_type; + + return 0; +} + +/* + * When a secondary opens, the timer is started and periodically checks for a + * close of the primary (state moved to SEC_TIMER_COPY). + * In SEC_TIMER_COPY: + * - The flow db must be locked to prevent flows from being added to the high + * region during a move. + * - Move the high entries to low + * - Set the region to low for subsequent flows + * - Switch our persona to Primary + * - Set the state to Primary Run + * - Release the flow db lock for flows to continue + */ +static void +ulp_ha_mgr_timer_cb(void *arg) +{ + struct tf_move_tcam_shared_entries_parms mparms = { 0 }; + struct bnxt_ulp_context *ulp_ctx; + enum ulp_ha_mgr_state curr_state; + struct tf *tfp; + int32_t rc; + + ulp_ctx = (struct bnxt_ulp_context *)arg; + rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state); + if (rc) { + /* + * This shouldn't happen, if it does, resetart the timer + * and try again next time. + */ + BNXT_TF_DBG(ERR, "On HA CB:Failed(%d) to get state.\n", rc); + goto cb_restart; + } + if (curr_state != ULP_HA_STATE_SEC_TIMER_COPY) + goto cb_restart; + + /* Protect the flow database during the copy */ + if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { + /* Should not fail, if we do, restart timer and try again */ + BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + goto cb_restart; + } + /* All paths after this point must release the fdb lock */ + + /* The Primary has issued a close and we are in the timer copy + * phase. Become the new Primary, Set state to Primary Run and + * move WC entries to Low Region. + */ + BNXT_TF_DBG(INFO, "On HA CB: Moving entries HI to LOW\n"); + mparms.dir = TF_DIR_RX; + mparms.tcam_tbl_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH; + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_YES); + if (tfp == NULL) { + BNXT_TF_DBG(ERR, "On HA CB: Unable to get the TFP.\n"); + goto unlock; + } + + rc = tf_move_tcam_shared_entries(tfp, &mparms); + if (rc) { + BNXT_TF_DBG(ERR, "On HA_CB: Failed to move entries\n"); + goto unlock; + } + + ulp_ha_mgr_region_set(ulp_ctx, ULP_HA_REGION_LOW); + ulp_ha_mgr_app_type_set(ulp_ctx, ULP_HA_APP_TYPE_PRIM); + ulp_ha_mgr_state_set(ulp_ctx, ULP_HA_STATE_PRIM_RUN); + BNXT_TF_DBG(INFO, "On HA CB: SEC[SEC_TIMER_COPY] => PRIM[PRIM_RUN]\n"); +unlock: + bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); + return; +cb_restart: + ulp_ha_mgr_timer_start(ulp_ctx); +} + +static int32_t +ulp_ha_mgr_timer_start(struct bnxt_ulp_context *ulp_ctx) +{ + struct bnxt_ulp_ha_mgr_info *ha_info; + + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "Invalid parmsi for ha timer start.\n"); + return -EINVAL; + } + + ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); + + if (ha_info == NULL) { + BNXT_TF_DBG(ERR, "Unable to get HA Info in timer start.\n"); + return -EINVAL; + } + ha_info->flags |= ULP_HA_TIMER_THREAD; + rte_eal_alarm_set(US_PER_S * ULP_HA_TIMER_SEC, + ulp_ha_mgr_timer_cb, + (void *)ulp_ctx); + return 0; +} + +static void +ulp_ha_mgr_timer_cancel(struct bnxt_ulp_context *ulp_ctx) +{ + struct bnxt_ulp_ha_mgr_info *ha_info; + + ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); + if (ha_info == NULL) { + BNXT_TF_DBG(ERR, "Unable to get ha info\n"); + return; + } + + ha_info->flags &= ~ULP_HA_TIMER_THREAD; + rte_eal_alarm_cancel(ulp_ha_mgr_timer_cb, (void *)ulp_ctx); +} + +int32_t +ulp_ha_mgr_init(struct bnxt_ulp_context *ulp_ctx) +{ + struct bnxt_ulp_ha_mgr_info *ha_info; + int32_t rc; + ha_info = rte_zmalloc("ulp_ha_mgr_info", sizeof(*ha_info), 0); + if (!ha_info) + return -ENOMEM; + + /* Add the HA info tbl to the ulp context. */ + bnxt_ulp_cntxt_ptr2_ha_info_set(ulp_ctx, ha_info); + + rc = pthread_mutex_init(&ha_info->ha_lock, NULL); + if (rc) { + PMD_DRV_LOG(ERR, "Failed to initialize ha mutex\n"); + goto cleanup; + } + + return 0; +cleanup: + if (ha_info != NULL) + ulp_ha_mgr_deinit(ulp_ctx); + return -ENOMEM; +} + +void +ulp_ha_mgr_deinit(struct bnxt_ulp_context *ulp_ctx) +{ + struct bnxt_ulp_ha_mgr_info *ha_info; + + ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); + if (ha_info == NULL) { + BNXT_TF_DBG(ERR, "Unable to get HA Info for deinit.\n"); + return; + } + + pthread_mutex_destroy(&ha_info->ha_lock); + rte_free(ha_info); + + bnxt_ulp_cntxt_ptr2_ha_info_set(ulp_ctx, NULL); +} + +int32_t +ulp_ha_mgr_app_type_get(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_app_type *app_type) +{ + struct bnxt_ulp_ha_mgr_info *ha_info; + + if (ulp_ctx == NULL || app_type == NULL) { + BNXT_TF_DBG(ERR, "Invalid Parms.\n"); + return -EINVAL; + } + + ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); + if (ha_info == NULL) { + BNXT_TF_DBG(ERR, "Unable to get the HA info.\n"); + return -EINVAL; + } + *app_type = ha_info->app_type; + + return 0; +} + +int32_t +ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_state *state) +{ + struct tf_get_if_tbl_entry_parms get_parms = { 0 }; + struct tf *tfp; + uint32_t val = 0; + int32_t rc = 0; + + if (ulp_ctx == NULL || state == NULL) { + BNXT_TF_DBG(ERR, "Invalid parms in state get.\n"); + return -EINVAL; + } + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); + if (tfp == NULL) { + BNXT_TF_DBG(ERR, "Unable to get the TFP.\n"); + return -EINVAL; + } + + get_parms.dir = ULP_HA_IF_TBL_DIR; + get_parms.type = ULP_HA_IF_TBL_TYPE; + get_parms.idx = ULP_HA_IF_TBL_IDX; + get_parms.data = (uint8_t *)&val; + get_parms.data_sz_in_bytes = sizeof(val); + + rc = tf_get_if_tbl_entry(tfp, &get_parms); + if (rc) + BNXT_TF_DBG(ERR, "Failed to read the HA state\n"); + + *state = val; + return rc; +} + +int32_t +ulp_ha_mgr_open(struct bnxt_ulp_context *ulp_ctx) +{ + enum ulp_ha_mgr_state curr_state; + int32_t rc; + + rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to get HA state on Open (%d)\n", rc); + return -EINVAL; + } + + /* + * An Open can only occur during the Init and Primary Run states. During + * Init, the system attempting to Open will become the only system + * running. During Primary Run, the system attempting to Open will + * become the secondary system temporarily, and should eventually be + * transitioned to the primary system. + */ + switch (curr_state) { + case ULP_HA_STATE_INIT: + /* + * No system is running, as we are the primary. Since no other + * system is running, we start writing into the low region. By + * writing into the low region, we save room for the secondary + * system to override our entries by using the high region. + */ + ulp_ha_mgr_app_type_set(ulp_ctx, ULP_HA_APP_TYPE_PRIM); + ulp_ha_mgr_region_set(ulp_ctx, ULP_HA_REGION_LOW); + rc = ulp_ha_mgr_state_set(ulp_ctx, ULP_HA_STATE_PRIM_RUN); + if (rc) { + BNXT_TF_DBG(ERR, "On Open: Failed to set PRIM_RUN.\n"); + return -EINVAL; + } + + BNXT_TF_DBG(INFO, "On Open: [INIT] => PRIM[PRIM_RUN]\n"); + break; + case ULP_HA_STATE_PRIM_RUN: + /* + * The secondary system is starting in order to take over. + * The current primary is expected to eventually close and pass + * full control to this system;however, until the primary closes + * both are operational. + * + * The timer is started in order to determine when the + * primary has closed. + */ + ulp_ha_mgr_app_type_set(ulp_ctx, ULP_HA_APP_TYPE_SEC); + ulp_ha_mgr_region_set(ulp_ctx, ULP_HA_REGION_HI); + + /* + * TODO: + * Clear the high region so the secondary can begin overriding + * the current entries. + */ + rc = ulp_ha_mgr_timer_start(ulp_ctx); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to start timer on HA Open.\n"); + return -EINVAL; + } + + rc = ulp_ha_mgr_state_set(ulp_ctx, ULP_HA_STATE_PRIM_SEC_RUN); + if (rc) { + BNXT_TF_DBG(ERR, "On Open: Failed to set PRIM_SEC_RUN\n"); + return -EINVAL; + } + BNXT_TF_DBG(INFO, "On Open: [PRIM_RUN] => [PRIM_SEC_RUN]\n"); + break; + default: + BNXT_TF_DBG(ERR, "On Open: Unknown state 0x%x\n", curr_state); + return -EINVAL; + } + + return 0; +} + +int32_t +ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx) +{ + enum ulp_ha_mgr_state curr_state, next_state, poll_state; + enum ulp_ha_mgr_app_type app_type; + int32_t timeout; + int32_t rc; + + rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state); + if (rc) { + BNXT_TF_DBG(ERR, "On Close: Failed(%d) to get HA state\n", rc); + return -EINVAL; + } + + rc = ulp_ha_mgr_app_type_get(ulp_ctx, &app_type); + if (rc) { + BNXT_TF_DBG(ERR, "On Close: Failed to get the app type.\n"); + return -EINVAL; + } + + if (curr_state == ULP_HA_STATE_PRIM_RUN && + app_type == ULP_HA_APP_TYPE_PRIM) { + /* + * Only the primary is running, so a close effectively moves the + * system back to INIT. + */ + next_state = ULP_HA_STATE_INIT; + ulp_ha_mgr_state_set(ulp_ctx, next_state); + BNXT_TF_DBG(INFO, "On Close: PRIM[PRIM_RUN] => [INIT]\n"); + } else if (curr_state == ULP_HA_STATE_PRIM_SEC_RUN && + app_type == ULP_HA_APP_TYPE_PRIM) { + /* + * While both are running, the primary received a close. + * Cleanup the flows, set the COPY state, and wait for the + * secondary to become the Primary. + */ + BNXT_TF_DBG(INFO, + "On Close: PRIM[PRIM_SEC_RUN] flushing flows.\n"); + + ulp_flow_db_flush_flows(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR); + ulp_ha_mgr_state_set(ulp_ctx, ULP_HA_STATE_SEC_TIMER_COPY); + + /* + * TODO: This needs to be bounded in case the other system does + * not move to PRIM_RUN. + */ + BNXT_TF_DBG(INFO, + "On Close: PRIM[PRIM_SEC_RUN] => [Copy], enter wait.\n"); + timeout = ULP_HA_WAIT_TIMEOUT; + do { + rte_delay_ms(ULP_HA_WAIT_TIME); + rc = ulp_ha_mgr_state_get(ulp_ctx, &poll_state); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed to get HA state on Close (%d)\n", + rc); + goto cleanup; + } + timeout -= ULP_HA_WAIT_TIME; + BNXT_TF_DBG(INFO, + "On Close: Waiting %d ms for PRIM_RUN\n", + timeout); + } while (poll_state != ULP_HA_STATE_PRIM_RUN && timeout > 0); + + if (timeout <= 0) { + BNXT_TF_DBG(ERR, "On Close: SEC[COPY] Timed out\n"); + goto cleanup; + } + + BNXT_TF_DBG(INFO, "On Close: PRIM[PRIM_SEC_RUN] => [COPY]\n"); + } else if (curr_state == ULP_HA_STATE_PRIM_SEC_RUN && + app_type == ULP_HA_APP_TYPE_SEC) { + /* + * While both are running, the secondary unexpectedly received a + * close. Cancel the timer, set the state to Primary RUN since + * it is the only one running. + */ + ulp_ha_mgr_timer_cancel(ulp_ctx); + ulp_ha_mgr_state_set(ulp_ctx, ULP_HA_STATE_PRIM_RUN); + + BNXT_TF_DBG(INFO, "On Close: SEC[PRIM_SEC_RUN] => [PRIM_RUN]\n"); + } else if (curr_state == ULP_HA_STATE_SEC_TIMER_COPY && + app_type == ULP_HA_APP_TYPE_SEC) { + /* + * While both were running and the Secondary went into copy, + * secondary received a close. Wait until the former Primary + * clears the copy stage, close, and set to INIT. + */ + BNXT_TF_DBG(INFO, "On Close: SEC[COPY] wait for PRIM_RUN\n"); + + timeout = ULP_HA_WAIT_TIMEOUT; + do { + rte_delay_ms(ULP_HA_WAIT_TIME); + rc = ulp_ha_mgr_state_get(ulp_ctx, &poll_state); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed to get HA state on Close (%d)\n", + rc); + goto cleanup; + } + + timeout -= ULP_HA_WAIT_TIME; + BNXT_TF_DBG(INFO, + "On Close: Waiting %d ms for PRIM_RUN\n", + timeout); + } while (poll_state != ULP_HA_STATE_PRIM_RUN && + timeout >= 0); + + if (timeout <= 0) { + BNXT_TF_DBG(ERR, + "On Close: SEC[COPY] Timed out\n"); + goto cleanup; + } + + next_state = ULP_HA_STATE_INIT; + rc = ulp_ha_mgr_state_set(ulp_ctx, next_state); + if (rc) { + BNXT_TF_DBG(ERR, + "On Close: Failed to set state to INIT(%x)\n", + rc); + goto cleanup; + } + + BNXT_TF_DBG(INFO, + "On Close: SEC[COPY] => [INIT] after %d ms\n", + ULP_HA_WAIT_TIMEOUT - timeout); + } else { + BNXT_TF_DBG(ERR, "On Close: Invalid type/state %d/%d\n", + curr_state, app_type); + } +cleanup: + return rc; +} + +int32_t +ulp_ha_mgr_region_get(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_region *region) +{ + struct bnxt_ulp_ha_mgr_info *ha_info; + + if (ulp_ctx == NULL || region == NULL) { + BNXT_TF_DBG(ERR, "Invalid params in ha region get.\n"); + return -EINVAL; + } + + ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); + if (ha_info == NULL) { + BNXT_TF_DBG(ERR, "Unable to get ha info\n"); + return -EINVAL; + } + *region = ha_info->region; + + return 0; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h new file mode 100644 index 0000000000..793511564a --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2021 Broadcom + * All rights reserved. + */ + +#ifndef _ULP_HA_MGR_H_ +#define _ULP_HA_MGR_H_ + +#include "bnxt_ulp.h" + +enum ulp_ha_mgr_state { + ULP_HA_STATE_INIT, + ULP_HA_STATE_PRIM_RUN, + ULP_HA_STATE_PRIM_SEC_RUN, + ULP_HA_STATE_SEC_TIMER_COPY, + ULP_HA_PRIM_CLOSE +}; + +enum ulp_ha_mgr_app_type { + ULP_HA_APP_TYPE_NONE, + ULP_HA_APP_TYPE_PRIM, + ULP_HA_APP_TYPE_SEC +}; + +enum ulp_ha_mgr_region { + ULP_HA_REGION_LOW, + ULP_HA_REGION_HI +}; + +struct bnxt_ulp_ha_mgr_info { + enum ulp_ha_mgr_app_type app_type; + enum ulp_ha_mgr_region region; + uint32_t flags; + pthread_mutex_t ha_lock; +}; + +bool +ulp_ha_mgr_is_enabled(struct bnxt_ulp_context *ulp_ctx); + +int32_t +ulp_ha_mgr_enable(struct bnxt_ulp_context *ulp_ctx); + +int32_t +ulp_ha_mgr_init(struct bnxt_ulp_context *ulp_ctx); + +void +ulp_ha_mgr_deinit(struct bnxt_ulp_context *ulp_ctx); + +int32_t +ulp_ha_mgr_app_type_get(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_app_type *app_type); + +int32_t +ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_state *state); + +int32_t +ulp_ha_mgr_open(struct bnxt_ulp_context *ulp_ctx); + +int32_t +ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx); + +int32_t +ulp_ha_mgr_region_get(struct bnxt_ulp_context *ulp_ctx, + enum ulp_ha_mgr_region *region); + +#endif /* _ULP_HA_MGR_H_*/ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index e2404c392b..05a43b6dc5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -19,6 +19,7 @@ #include "tf_util.h" #include "ulp_template_db_tbl.h" #include "ulp_port_db.h" +#include "ulp_ha_mgr.h" static uint8_t mapper_fld_zeros[16] = { 0 }; @@ -419,7 +420,7 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_parms *mparms, } static inline int32_t -ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp __rte_unused, +ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp, struct tf *tfp, struct ulp_flow_db_res_params *res) { @@ -429,6 +430,30 @@ ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp __rte_unused, .idx = (uint16_t)res->resource_hndl }; + /* If HA is enabled, we may have to remap the TF Type */ + if (bnxt_ulp_cntxt_ha_enabled(ulp)) { + enum ulp_ha_mgr_region region; + int32_t rc; + + switch (res->resource_type) { + case TF_TCAM_TBL_TYPE_WC_TCAM_HIGH: + case TF_TCAM_TBL_TYPE_WC_TCAM_LOW: + rc = ulp_ha_mgr_region_get(ulp, ®ion); + if (rc) + /* Log this, but assume region is correct */ + BNXT_TF_DBG(ERR, + "Unable to get HA region (%d)\n", + rc); + else + fparms.tcam_tbl_type = + (region == ULP_HA_REGION_LOW) ? + TF_TCAM_TBL_TYPE_WC_TCAM_LOW : + TF_TCAM_TBL_TYPE_WC_TCAM_HIGH; + break; + default: + break; + } + } return tf_free_tcam_entry(tfp, &fparms); } @@ -2904,10 +2929,12 @@ static int32_t ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_mapper_data *mapper_data) { + struct tf_get_shared_tbl_increment_parms iparms; struct bnxt_ulp_glb_resource_info *glb_res; struct tf_get_session_info_parms sparms; uint32_t num_entries, i, dev_id, res; struct tf_resource_info *res_info; + uint32_t addend; uint64_t regval; enum tf_dir dir; int32_t rc = 0; @@ -2915,13 +2942,11 @@ ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, uint8_t app_id; memset(&sparms, 0, sizeof(sparms)); - glb_res = bnxt_ulp_app_glb_resource_info_list_get(&num_entries); if (!glb_res || !num_entries) { BNXT_TF_DBG(ERR, "Invalid Arguments\n"); return -EINVAL; } - tfp = bnxt_ulp_cntxt_shared_tfp_get(ulp_ctx); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get tfp for app global init"); @@ -2958,12 +2983,29 @@ ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, continue; dir = glb_res[i].direction; res = glb_res[i].resource_type; + addend = 1; switch (glb_res[i].resource_func) { case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: res_info = &sparms.session_info.ident[dir].info[res]; break; case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: + /* + * Tables may have various strides for the allocations. + * Need to account. + */ + memset(&iparms, 0, sizeof(iparms)); + iparms.dir = dir; + iparms.type = res; + rc = tf_get_shared_tbl_increment(tfp, &iparms); + if (rc) { + BNXT_TF_DBG(ERR, + "Failed to get addend for %s[%s] rc=(%d)\n", + tf_tbl_type_2_str(res), + tf_dir_2_str(dir), rc); + return rc; + } + addend = iparms.increment_cnt; res_info = &sparms.session_info.tbl[dir].info[res]; break; case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: @@ -2977,10 +3019,8 @@ ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx, glb_res[i].resource_func); continue; } - regval = tfp_cpu_to_be_64((uint64_t)res_info->start); - res_info->start++; - + res_info->start += addend; /* * All resources written to the global regfile are shared for * this function. From patchwork Sun May 30 08:59:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93595 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9D1BA0524; Sun, 30 May 2021 11:07:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AAB3A41210; Sun, 30 May 2021 11:02:09 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id F252241184 for ; Sun, 30 May 2021 11:02:04 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 90BEC7DAF; Sun, 30 May 2021 02:02:03 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 90BEC7DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365324; bh=GcdCSIzeBhkYep7IYzID0Kdx56zbah7m/uw6C+HxCfg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IyM+sAzNYObZnONFW9zGKRoH/OX1BUPijRX0Rr0Ep9rxPTG/ynQjbNu4J0vgZfN8V 8fKhmQ+lXg8X73jL4Tpa3nep5gbnhqXkSW21sn9zm723EZKr68reJLvdN1yHeAKqs7 JWNY8L1yof4YOHgN1DVhGMY3h0T/gJfxGF+C0Iuk= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:25 +0530 Message-Id: <20210530085929.29695-55-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 54/58] net/bnxt: add support for icmp6 ULP parsing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha This patch adds support for parsing rte_flow items for icmp6 flows. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 4 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 48 +++++++++++++++++++ drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 5 ++ 3 files changed, 55 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c index 7bd499faa6..35e9858727 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c @@ -346,8 +346,8 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ICMP6] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_icmp6_hdr_handler }, [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = { .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 0d52c0b93b..a55655a5bd 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1599,6 +1599,54 @@ ulp_rte_icmp_hdr_handler(const struct rte_flow_item *item, return BNXT_TF_RC_SUCCESS; } +/* Function to handle the parsing of RTE Flow item ICMP6 Header. */ +int32_t +ulp_rte_icmp6_hdr_handler(const struct rte_flow_item *item, + struct ulp_rte_parser_params *params) +{ + const struct rte_flow_item_icmp6 *icmp_spec = item->spec; + const struct rte_flow_item_icmp6 *icmp_mask = item->mask; + struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; + uint32_t idx = 0; + uint32_t size; + + if (ulp_rte_prsr_fld_size_validate(params, &idx, + BNXT_ULP_PROTO_HDR_ICMP_NUM)) { + BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); + return BNXT_TF_RC_ERROR; + } + + size = sizeof(((struct rte_flow_item_icmp6 *)NULL)->type); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(icmp_spec, type), + ulp_deference_struct(icmp_mask, type), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_icmp6 *)NULL)->code); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(icmp_spec, code), + ulp_deference_struct(icmp_mask, code), + ULP_PRSR_ACT_DEFAULT); + + size = sizeof(((struct rte_flow_item_icmp6 *)NULL)->checksum); + ulp_rte_prsr_fld_mask(params, &idx, size, + ulp_deference_struct(icmp_spec, checksum), + ulp_deference_struct(icmp_mask, checksum), + ULP_PRSR_ACT_DEFAULT); + + if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4)) { + BNXT_TF_DBG(ERR, "Error: incorrect icmp version\n"); + return BNXT_TF_RC_ERROR; + } + + /* Update the hdr_bitmap with ICMP */ + if (ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) + ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_ICMP); + else + ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ICMP); + return BNXT_TF_RC_SUCCESS; +} + /* Function to handle the parsing of RTE Flow item void Header */ int32_t ulp_rte_void_hdr_handler(const struct rte_flow_item *item __rte_unused, diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index 66abe8e656..bbba10108c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -147,6 +147,11 @@ int32_t ulp_rte_icmp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_parser_params *params); +/* Function to handle the parsing of RTE Flow item ICMP6 Header. */ +int32_t +ulp_rte_icmp6_hdr_handler(const struct rte_flow_item *item, + struct ulp_rte_parser_params *params); + /* Function to handle the parsing of RTE Flow item void Header. */ int32_t ulp_rte_void_hdr_handler(const struct rte_flow_item *item, From patchwork Sun May 30 08:59:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93596 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AA62EA0524; Sun, 30 May 2021 11:07:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 621EE41218; Sun, 30 May 2021 11:02:11 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 79F4541203 for ; Sun, 30 May 2021 11:02:06 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 18BF17DC2; Sun, 30 May 2021 02:02:04 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 18BF17DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365326; bh=r2uUku8hndliCs8+Fvh7+fhtUr8rpG0eDx92n3WNLx8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i1V2ikJ8yFY6Lkj5FmkhWMrnuNjscIS2hSuzss+LOvxMUj1DF8W1NBpAEMuaANT54 HrXwM9m1CeR4gByyU+uhf5ZiTUAWyn1i1NTZgUTIXYKnyr0XsIdaSFLUIUpXsWEMUp WPz4Wp1AmL/Qg88433N2SpcRtTmmt5y4jsb8b8vw= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:26 +0530 Message-Id: <20210530085929.29695-56-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 55/58] net/bnxt: add support for ULP context list for timers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The alarm callback needs to have a valid context pointer when it is invoked, the context could become invalid if the port goes down and the callback is invoked before it is cancelled. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 95 ++++++++++++++++++++++++++++ drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 12 ++++ drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 30 ++++++--- drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 37 +++++------ 4 files changed, 144 insertions(+), 30 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 972bf8b992..5f1540027c 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "bnxt.h" #include "bnxt_ulp.h" @@ -32,6 +33,17 @@ STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list = /* Mutex to synchronize bnxt_ulp_session_list operations. */ static pthread_mutex_t bnxt_ulp_global_mutex = PTHREAD_MUTEX_INITIALIZER; +/* Spin lock to protect context global list */ +rte_spinlock_t bnxt_ulp_ctxt_lock; +TAILQ_HEAD(cntx_list_entry_list, ulp_context_list_entry); +static struct cntx_list_entry_list ulp_cntx_list = + TAILQ_HEAD_INITIALIZER(ulp_cntx_list); + +/* Static function declarations */ +static int32_t bnxt_ulp_cntxt_list_init(void); +static int32_t bnxt_ulp_cntxt_list_add(struct bnxt_ulp_context *ulp_ctx); +static void bnxt_ulp_cntxt_list_del(struct bnxt_ulp_context *ulp_ctx); + /* * Allow the deletion of context only for the bnxt device that * created the session. @@ -743,6 +755,16 @@ ulp_ctx_init(struct bnxt *bp, int32_t rc = 0; enum bnxt_ulp_device_id devid; + /* Initialize the context entries list */ + bnxt_ulp_cntxt_list_init(); + + /* Add the context to the context entries list */ + rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to add the context list entry\n"); + return -ENOMEM; + } + /* Allocate memory to hold ulp context data. */ ulp_data = rte_zmalloc("bnxt_ulp_data", sizeof(struct bnxt_ulp_data), 0); @@ -878,6 +900,13 @@ ulp_ctx_attach(struct bnxt *bp, /* update the session details in bnxt tfp */ bp->tfp.session = session->g_tfp->session; + /* Add the context to the context entries list */ + rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to add the context list entry\n"); + return -EINVAL; + } + /* * The supported flag will be set during the init. Use it now to * know if we should go through the attach. @@ -1448,6 +1477,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp) BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port deinit\n", bp->eth_dev->data->port_id); + /* Free the ulp context in the context entry list */ + bnxt_ulp_cntxt_list_del(bp->ulp_ctx); + /* Get the session details */ pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device); pci_addr = &pci_dev->addr; @@ -1887,3 +1919,66 @@ bnxt_ulp_cntxt_ha_enabled(struct bnxt_ulp_context *ulp_ctx) return false; return !!ULP_HIGH_AVAIL_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags); } + +static int32_t +bnxt_ulp_cntxt_list_init(void) +{ + /* Create the cntxt spin lock */ + rte_spinlock_init(&bnxt_ulp_ctxt_lock); + + return 0; +} + +static int32_t +bnxt_ulp_cntxt_list_add(struct bnxt_ulp_context *ulp_ctx) +{ + struct ulp_context_list_entry *entry; + + entry = rte_zmalloc(NULL, sizeof(struct ulp_context_list_entry), 0); + if (entry == NULL) { + BNXT_TF_DBG(ERR, "unable to allocate memory\n"); + return -ENOMEM; + } + + rte_spinlock_lock(&bnxt_ulp_ctxt_lock); + entry->ulp_ctx = ulp_ctx; + TAILQ_INSERT_TAIL(&ulp_cntx_list, entry, next); + rte_spinlock_unlock(&bnxt_ulp_ctxt_lock); + return 0; +} + +static void +bnxt_ulp_cntxt_list_del(struct bnxt_ulp_context *ulp_ctx) +{ + struct ulp_context_list_entry *entry, *temp; + + rte_spinlock_lock(&bnxt_ulp_ctxt_lock); + TAILQ_FOREACH_SAFE(entry, &ulp_cntx_list, next, temp) { + if (entry->ulp_ctx == ulp_ctx) { + TAILQ_REMOVE(&ulp_cntx_list, entry, next); + rte_free(entry); + break; + } + } + rte_spinlock_unlock(&bnxt_ulp_ctxt_lock); +} + +struct bnxt_ulp_context * +bnxt_ulp_cntxt_entry_acquire(void) +{ + struct ulp_context_list_entry *entry; + + /* take a lock and get the first ulp context available */ + if (rte_spinlock_trylock(&bnxt_ulp_ctxt_lock)) { + TAILQ_FOREACH(entry, &ulp_cntx_list, next) + if (entry->ulp_ctx) + return entry->ulp_ctx; + } + return NULL; +} + +void +bnxt_ulp_cntxt_entry_release(void) +{ + rte_spinlock_unlock(&bnxt_ulp_ctxt_lock); +} diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index b1f090a5cb..ea38dc0d9f 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -112,6 +112,11 @@ struct ulp_tlv_param { uint8_t value[16]; }; +struct ulp_context_list_entry { + TAILQ_ENTRY(ulp_context_list_entry) next; + struct bnxt_ulp_context *ulp_ctx; +}; + /* * Allow the deletion of context only for the bnxt device that * created the session @@ -285,4 +290,11 @@ bnxt_ulp_cntxt_ptr2_ha_info_get(struct bnxt_ulp_context *ulp_ctx); bool bnxt_ulp_cntxt_ha_enabled(struct bnxt_ulp_context *ulp_ctx); + +struct bnxt_ulp_context * +bnxt_ulp_cntxt_entry_acquire(void); + +void +bnxt_ulp_cntxt_entry_release(void); + #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 7c83cb2054..9a77132385 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -197,8 +197,7 @@ ulp_fc_mgr_thread_start(struct bnxt_ulp_context *ctxt) if (ulp_fc_info && !(ulp_fc_info->flags & ULP_FLAG_FC_THREAD)) { rte_eal_alarm_set(US_PER_S * ULP_FC_TIMER, - ulp_fc_mgr_alarm_cb, - (void *)ctxt); + ulp_fc_mgr_alarm_cb, NULL); ulp_fc_info->flags |= ULP_FLAG_FC_THREAD; } @@ -220,7 +219,7 @@ void ulp_fc_mgr_thread_cancel(struct bnxt_ulp_context *ctxt) return; ulp_fc_info->flags &= ~ULP_FLAG_FC_THREAD; - rte_eal_alarm_cancel(ulp_fc_mgr_alarm_cb, (void *)ctxt); + rte_eal_alarm_cancel(ulp_fc_mgr_alarm_cb, NULL); } /* @@ -363,35 +362,48 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, */ void -ulp_fc_mgr_alarm_cb(void *arg) +ulp_fc_mgr_alarm_cb(void *arg __rte_unused) { int rc = 0; unsigned int j; enum tf_dir i; - struct bnxt_ulp_context *ctxt = arg; + struct bnxt_ulp_context *ctxt; struct bnxt_ulp_fc_info *ulp_fc_info; struct bnxt_ulp_device_params *dparms; struct tf *tfp; uint32_t dev_id, hw_cntr_id = 0, num_entries = 0; + ctxt = bnxt_ulp_cntxt_entry_acquire(); + if (ctxt == NULL) { + BNXT_TF_DBG(INFO, "could not get the ulp context lock\n"); + rte_eal_alarm_set(US_PER_S * ULP_FC_TIMER, + ulp_fc_mgr_alarm_cb, NULL); + return; + } + ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt); - if (!ulp_fc_info) + if (!ulp_fc_info) { + bnxt_ulp_cntxt_entry_release(); return; + } if (bnxt_ulp_cntxt_dev_id_get(ctxt, &dev_id)) { BNXT_TF_DBG(DEBUG, "Failed to get device id\n"); + bnxt_ulp_cntxt_entry_release(); return; } dparms = bnxt_ulp_device_params_get(dev_id); if (!dparms) { BNXT_TF_DBG(DEBUG, "Failed to device parms\n"); + bnxt_ulp_cntxt_entry_release(); return; } tfp = bnxt_ulp_cntxt_tfp_get(ctxt, BNXT_ULP_SHARED_SESSION_NO); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n"); + bnxt_ulp_cntxt_entry_release(); return; } @@ -405,6 +417,7 @@ ulp_fc_mgr_alarm_cb(void *arg) if (!ulp_fc_info->num_entries) { pthread_mutex_unlock(&ulp_fc_info->fc_lock); ulp_fc_mgr_thread_cancel(ctxt); + bnxt_ulp_cntxt_entry_release(); return; } /* @@ -443,12 +456,13 @@ ulp_fc_mgr_alarm_cb(void *arg) if (rc) { ulp_fc_mgr_thread_cancel(ctxt); + bnxt_ulp_cntxt_entry_release(); return; } out: + bnxt_ulp_cntxt_entry_release(); rte_eal_alarm_set(US_PER_S * ULP_FC_TIMER, - ulp_fc_mgr_alarm_cb, - (void *)ctxt); + ulp_fc_mgr_alarm_cb, NULL); } /* diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c index dc71054f46..1cfe5cd0a7 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c @@ -26,7 +26,7 @@ #define ULP_HA_IF_TBL_IDX 10 static void ulp_ha_mgr_timer_cancel(struct bnxt_ulp_context *ulp_ctx); -static int32_t ulp_ha_mgr_timer_start(struct bnxt_ulp_context *ulp_ctx); +static int32_t ulp_ha_mgr_timer_start(void); static void ulp_ha_mgr_timer_cb(void *arg); static int32_t ulp_ha_mgr_app_type_set(struct bnxt_ulp_context *ulp_ctx, enum ulp_ha_mgr_app_type app_type); @@ -126,7 +126,7 @@ ulp_ha_mgr_app_type_set(struct bnxt_ulp_context *ulp_ctx, * - Release the flow db lock for flows to continue */ static void -ulp_ha_mgr_timer_cb(void *arg) +ulp_ha_mgr_timer_cb(void *arg __rte_unused) { struct tf_move_tcam_shared_entries_parms mparms = { 0 }; struct bnxt_ulp_context *ulp_ctx; @@ -134,7 +134,13 @@ ulp_ha_mgr_timer_cb(void *arg) struct tf *tfp; int32_t rc; - ulp_ctx = (struct bnxt_ulp_context *)arg; + ulp_ctx = bnxt_ulp_cntxt_entry_acquire(); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(INFO, "could not get the ulp context lock\n"); + ulp_ha_mgr_timer_start(); + return; + } + rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state); if (rc) { /* @@ -180,31 +186,18 @@ ulp_ha_mgr_timer_cb(void *arg) BNXT_TF_DBG(INFO, "On HA CB: SEC[SEC_TIMER_COPY] => PRIM[PRIM_RUN]\n"); unlock: bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); + bnxt_ulp_cntxt_entry_release(); return; cb_restart: - ulp_ha_mgr_timer_start(ulp_ctx); + bnxt_ulp_cntxt_entry_release(); + ulp_ha_mgr_timer_start(); } static int32_t -ulp_ha_mgr_timer_start(struct bnxt_ulp_context *ulp_ctx) +ulp_ha_mgr_timer_start(void) { - struct bnxt_ulp_ha_mgr_info *ha_info; - - if (ulp_ctx == NULL) { - BNXT_TF_DBG(ERR, "Invalid parmsi for ha timer start.\n"); - return -EINVAL; - } - - ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); - - if (ha_info == NULL) { - BNXT_TF_DBG(ERR, "Unable to get HA Info in timer start.\n"); - return -EINVAL; - } - ha_info->flags |= ULP_HA_TIMER_THREAD; rte_eal_alarm_set(US_PER_S * ULP_HA_TIMER_SEC, - ulp_ha_mgr_timer_cb, - (void *)ulp_ctx); + ulp_ha_mgr_timer_cb, NULL); return 0; } @@ -374,7 +367,7 @@ ulp_ha_mgr_open(struct bnxt_ulp_context *ulp_ctx) * Clear the high region so the secondary can begin overriding * the current entries. */ - rc = ulp_ha_mgr_timer_start(ulp_ctx); + rc = ulp_ha_mgr_timer_start(); if (rc) { BNXT_TF_DBG(ERR, "Unable to start timer on HA Open.\n"); return -EINVAL; From patchwork Sun May 30 08:59:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93699 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D397EA0524; Tue, 1 Jun 2021 09:43:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 35C7341151; Tue, 1 Jun 2021 09:40:14 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id D30864120C for ; Sun, 30 May 2021 11:02:08 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 96DE37DC0; Sun, 30 May 2021 02:02:06 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 96DE37DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365328; bh=eQ3niflWRHrn+wiTFXlZZhL46Hus4F/PtzDRKZSb7sM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ExhDYQ3CJuDGd2TdhOrmVLQkC/tuY07AZVL3adUHdCWSvx/RaLPnNRBRdEQTrebXY bkocS6Mj3bRmTfIKHh0clYXTaF5c6R4lbBjMqigafgQPfkcKDCN+eFX3Tyk/yYYqCv +ge2rwbToymOpyu80/KDBO27wNe8rnVI7353pP70= From: Venkat Duvvuru To: dev@dpdk.org Cc: Shahaji Bhosle , Mike Baucom , Kishore Padmanabha , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:27 +0530 Message-Id: <20210530085929.29695-57-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:54 +0200 Subject: [dpdk-dev] [PATCH 56/58] net/bnxt: cleanup ULP parser and mapper X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shahaji Bhosle 1. disable accum_stats for thor 2. delete the generic port table for default flow 3. The packet mask to calculate the number of packets must be 28 bits. 4. Increase the wc tcam entries to 512 per application and add 2 shared l2 context tcam entries to match identifiers for flow scaling 5. ignore multiple critical resources in ulp flow database 6. Renamed conditional code update to function opcode. 7. Updated tf debug logs to support the above changes. 8. As part of the HA cleanup, the shared session name now allows the user to designate that the session uses the wc_tcam regions within the shared session. 9. The CFA action pointer does not exist if there is no support for VF representor, so no need to display the message for use case where there is no support for VF representors. 10. Cleanup flow counter software accumulation. 11. When an ungraceful exit of testpmd happens, the HA code now clears the appropriate shared WC region and sets the HA state. 12. Removal of unnecessary INFO message. The message is an indicator that the ports are being removed from dpdk, but all cleanup has not completed. Once the cleanup is completed, the timer will be stopped. Signed-off-by: Shahaji Bhosle Signed-off-by: Mike Baucom Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h | 4 +- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h | 8 +- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c | 2 +- drivers/net/bnxt/tf_core/bitalloc.h | 2 +- drivers/net/bnxt/tf_core/cfa_resource_types.h | 2 +- drivers/net/bnxt/tf_core/dpool.h | 10 +- drivers/net/bnxt/tf_core/tf_core.h | 8 +- drivers/net/bnxt/tf_core/tf_em.h | 2 +- drivers/net/bnxt/tf_core/tf_session.h | 2 +- drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 2 +- drivers/net/bnxt/tf_core/tfp.h | 6 +- drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 378 + drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 29 + drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 102 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 4 + drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 1 + drivers/net/bnxt/tf_ulp/meson.build | 1 + drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 3 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 103 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 1 + drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 14 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 14 +- drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 197 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 153 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 6 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 43 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 38 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 92 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 158 +- .../bnxt/tf_ulp/ulp_template_db_thor_act.c | 185 +- .../bnxt/tf_ulp/ulp_template_db_thor_class.c | 29120 +++++++++++++++- .../tf_ulp/ulp_template_db_wh_plus_class.c | 76 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 20 +- drivers/net/bnxt/tf_ulp/ulp_utils.c | 8 +- drivers/net/bnxt/tf_ulp/ulp_utils.h | 4 +- 37 files changed, 30000 insertions(+), 802 deletions(-) create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h index c67aa29ad0..2f23c4a7fc 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h @@ -44,7 +44,7 @@ struct hcapi_cfa_devinfo { /** CFA device specific function hooks structure * * The following device hooks can be defined; unless noted otherwise, they are - * optional and can be filled with a null pointer. The pupose of these hooks + * optional and can be filled with a null pointer. The purpose of these hooks * to support CFA device operations for different device variants. */ struct hcapi_cfa_devops { @@ -93,7 +93,7 @@ struct hcapi_cfa_devops { * is stored. It holds the bucket index and the data pointer of * a dynamic bucket that is chained to static bucket * When using the HWOP GET, this is a pointer to the key location - * which should be retreved. + * which should be retrieved. * * (valid for SR2 only). * @return diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h index 5135a857e1..e1d6f6ee6b 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h @@ -100,7 +100,7 @@ enum hcapi_cfa_hwops { * operation is also undo the add operation * performed by the HCAPI_CFA_HWOPS_ADD op. */ - HCAPI_CFA_HWOPS_EVICT, /*< This operaton is used to evit entries from + HCAPI_CFA_HWOPS_EVICT, /*< This operation is used to edit entries from * CFA cache memories. This operation is only * applicable to tables that use CFA caches. */ @@ -231,7 +231,7 @@ struct hcapi_cfa_key_tbl { uint32_t size; /** [in] number of key buckets, applicable for newer chips */ uint32_t num_buckets; - /** [in] For EEM, this is KEY1 base mem pointer. Fo off-chip EM, + /** [in] For EEM, this is KEY1 base mem pointer. For off-chip EM, * this is the key record memory base pointer within the key table, * applicable for newer chip */ @@ -273,8 +273,8 @@ struct hcapi_cfa_key_data { uint8_t tbl_scope; /** [in] the fid owner of the key */ uint64_t metadata; - /** [in] stored with the bucket which can be used to by - * the caller to retreved later via the GET HW OP. + /** [in] stored with the bucket which can be used by + * the caller to retrieve later via the GET HW OP. */ }; diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c index 79bc569989..85e8052e0b 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c @@ -230,7 +230,7 @@ static int hcapi_cfa_p4_key_hw_op_del(struct hcapi_cfa_hwop *op, return rc; } -/** Apporiximation of hcapi_cfa_key_hw_op() +/** Approximation of hcapi_cfa_key_hw_op() * * */ diff --git a/drivers/net/bnxt/tf_core/bitalloc.h b/drivers/net/bnxt/tf_core/bitalloc.h index e3b389e68d..db8a09abdd 100644 --- a/drivers/net/bnxt/tf_core/bitalloc.h +++ b/drivers/net/bnxt/tf_core/bitalloc.h @@ -60,7 +60,7 @@ struct bitalloc { #define BA_NO_ENTRY_FOUND -1 /** - * Initializates the bitallocator + * Initializes the bitallocator * * Returns 0 on success, -1 on failure. Size is arbitrary up to * BITALLOC_MAX_SIZE diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h index b63b87bcf3..0d7df2920b 100644 --- a/drivers/net/bnxt/tf_core/cfa_resource_types.h +++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h @@ -57,7 +57,7 @@ #define CFA_RESOURCE_TYPE_P59_RANGE_PROF 0x15UL /* Range */ #define CFA_RESOURCE_TYPE_P59_RANGE 0x16UL -/* Link Aggrigation */ +/* Link Aggregation */ #define CFA_RESOURCE_TYPE_P59_LAG 0x17UL /* VEB TCAM */ #define CFA_RESOURCE_TYPE_P59_VEB_TCAM 0x18UL diff --git a/drivers/net/bnxt/tf_core/dpool.h b/drivers/net/bnxt/tf_core/dpool.h index db9d53f01f..fb79c7be4b 100644 --- a/drivers/net/bnxt/tf_core/dpool.h +++ b/drivers/net/bnxt/tf_core/dpool.h @@ -49,7 +49,7 @@ struct dpool_free_list_entry { * Free list * * Used internally to record free entries in the dpool entry array. - * Each entry represents a single or multiple contiguious entries + * Each entry represents a single or multiple contiguous entries * in the dpool entry array. * * Used only during the defrag operation. @@ -98,7 +98,7 @@ struct dpool_adj_list_entry { * * A list of references to entries in the dpool entry array that * have free entries to the left and right. Since we pack to the - * left entries will always have a non zero left cout. + * left entries will always have a non zero left out. * * Used only during the defrag operation. */ @@ -281,17 +281,17 @@ void dpool_dump(struct dpool *dpool); /** * dpool_defrag * - * De-fragment the dpool array and apply the specified defrag stratagy. + * De-fragment the dpool array and apply the specified defrag strategy. * * [in] dpool * The dpool * * [in] entry_size - * If using the DP_DEFRAG_TO_FIT stratagy defrag will stop when there's + * If using the DP_DEFRAG_TO_FIT strategy defrag will stop when there's * at least entry_size space available. * * [i] defrag - * Defrag stratagy: + * Defrag strategy: * * DP_DEFRAG_ALL (0x1) - Defrag until there is nothing left * to defrag. diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index be5725a66a..84b234f0e3 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -396,7 +396,7 @@ enum tf_search_status { enum tf_em_tbl_type { /** The number of internal EM records for the session */ TF_EM_TBL_TYPE_EM_RECORD, - /** The number of table scopes reequested */ + /** The number of table scopes requested */ TF_EM_TBL_TYPE_TBL_SCOPE, TF_EM_TBL_TYPE_MAX }; @@ -415,7 +415,7 @@ enum tf_em_tbl_type { */ struct tf_session_info { /** - * TrueFlow Version. Used to control the structure layout when + * TruFlow Version. Used to control the structure layout when * sharing sessions. No guarantee that a secondary process * would come from the same version of an executable. * TruFlow initializes this variable on tf_open_session(). @@ -520,7 +520,7 @@ struct tf_identifier_resources { struct tf_tbl_resources { /** * Array of TF Table types where each entry is expected to be - * set to the requeste resource number of that specific + * set to the requested resource number of that specific * type. The index used is tf_tbl_type. */ uint16_t cnt[TF_TBL_TYPE_MAX]; @@ -1677,7 +1677,7 @@ struct tf_search_tbl_entry_parms { * * Implementation: * - * A hash is performed on the result data and mappe3d to a shadow copy entry + * A hash is performed on the result data and mapped to a shadow copy entry * where the result is populated. If the result matches the entry, hit is set, * ref_cnt is incremented (if alloc), and the search status indicates what * action the caller can take regarding setting the entry. diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 9d168c3c7f..568071ad8c 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -95,7 +95,7 @@ * | Index |E | * +--------------+--+ * - * E = Entry (bucket inndex) + * E = Entry (bucket index) */ #define TF_EM_INTERNAL_INDEX_SHIFT 2 #define TF_EM_INTERNAL_INDEX_MASK 0xFFFC diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index c2875f9fa1..d68421cd13 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -59,7 +59,7 @@ * tf_session_info. */ struct tf_session { - /** TrueFlow Version. Used to control the structure layout + /** TruFlow Version. Used to control the structure layout * when sharing sessions. No guarantee that a secondary * process would come from the same version of an executable. */ diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c b/drivers/net/bnxt/tf_core/tf_shadow_tcam.c index 523261f189..5fcd1f9107 100644 --- a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_shadow_tcam.c @@ -25,7 +25,7 @@ * - the result table is stored separately since it only needs to be accessed * when the key matches. * - the result has a back pointer to the hash table via the hb handle. The - * hb handle is a 32 bit represention of the hash with a valid bit, bucket + * hb handle is a 32 bit representation of the hash with a valid bit, bucket * element index, and the hash index. It is necessary to store the hb handle * with the result since subsequent removes only provide the tcam index. * diff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h index 58f34bbcab..dd0a347058 100644 --- a/drivers/net/bnxt/tf_core/tfp.h +++ b/drivers/net/bnxt/tf_core/tfp.h @@ -38,7 +38,7 @@ struct tfp_spinlock_parms { /** * @file * - * TrueFlow Portability API Header File + * TruFlow Portability API Header File */ /** @@ -119,8 +119,8 @@ struct tfp_calloc_parms { */ /** - * Provides communication capability from the TrueFlow API layer to - * the TrueFlow firmware. The portability layer internally provides + * Provides communication capability from the TruFlow API layer to + * the TruFlow firmware. The portability layer internally provides * the transport to the firmware. * * [in] session, pointer to session handle diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c new file mode 100644 index 0000000000..b09cccedf5 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c @@ -0,0 +1,378 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2021 Broadcom + * All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "bnxt.h" +#include "bnxt_vnic.h" +#include "bnxt_hwrm.h" +#include "bnxt_tf_common.h" +#include "bnxt_tf_pmd_shim.h" + +struct bnxt * +bnxt_pmd_get_bp(uint16_t port) +{ + struct bnxt *bp; + struct rte_eth_dev *dev; + + if (!rte_eth_dev_is_valid_port(port)) { + PMD_DRV_LOG(ERR, "Invalid port %d\n", port); + return NULL; + } + + dev = &rte_eth_devices[port]; + if (!is_bnxt_supported(dev)) { + PMD_DRV_LOG(ERR, "Device %d not supported\n", port); + return NULL; + } + + bp = (struct bnxt *)dev->data->dev_private; + if (!BNXT_TRUFLOW_EN(bp)) { + PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); + return NULL; + } + + return bp; +} + +int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms) +{ + struct bnxt_vnic_info *vnic = NULL; + struct bnxt *bp = NULL; + uint64_t rss_types; + uint16_t hwrm_type; + uint32_t rss_level, key_len; + uint8_t *rss_key; + struct ulp_rte_act_prop *ap = parms->act_prop; + int32_t rc = -EINVAL; + + bp = bnxt_pmd_get_bp(parms->port_id); + if (bp == NULL) { + BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id); + return rc; + } + vnic = BNXT_GET_DEFAULT_VNIC(bp); + if (vnic == NULL) { + BNXT_TF_DBG(ERR, "default vnic not available for %u\n", + parms->port_id); + return rc; + } + + /* get the details */ + memcpy(&rss_types, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_TYPES], + BNXT_ULP_ACT_PROP_SZ_RSS_TYPES); + memcpy(&rss_level, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL], + BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL); + memcpy(&key_len, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN], + BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN); + rss_key = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY]; + + hwrm_type = bnxt_rte_to_hwrm_hash_types(rss_types); + if (!hwrm_type) { + BNXT_TF_DBG(ERR, "Error unsupported rss config type\n"); + return rc; + } + /* Configure RSS only if the queue count is > 1 */ + if (vnic->rx_queue_cnt > 1) { + vnic->hash_type = hwrm_type; + vnic->hash_mode = + bnxt_rte_to_hwrm_hash_level(bp, rss_types, rss_level); + memcpy(vnic->rss_hash_key, rss_key, + BNXT_ULP_ACT_PROP_SZ_RSS_KEY); + rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); + if (rc) { + BNXT_TF_DBG(ERR, "Error configuring vnic RSS config\n"); + return rc; + } + BNXT_TF_DBG(INFO, "Rss config successfully applied\n"); + } + return 0; +} + +#define PARENT_PHY_INTF_PATH "/sys/bus/pci/devices/%s/physfn/net/*" +#define ULP_PRT_MAC_PATH "/sys/bus/pci/devices/%s/physfn/net/%s/address" + +#define ULP_FILE_PATH_SIZE 256 + +static int32_t glob_error_fn(const char *epath, int32_t eerrno) +{ + BNXT_TF_DBG(ERR, "path %s error %d\n", epath, eerrno); + return 0; +} + + +static int32_t ulp_pmd_get_mac_by_pci(const char *pci_name, uint8_t *mac) +{ + char path[ULP_FILE_PATH_SIZE], dev_str[ULP_FILE_PATH_SIZE]; + char *intf_name; + glob_t gres; + FILE *fp; + int32_t rc = -EINVAL; + + memset(path, 0, sizeof(path)); + sprintf(path, PARENT_PHY_INTF_PATH, pci_name); + + /* There can be only one, no more, no less */ + if (glob(path, 0, glob_error_fn, &gres) == 0) { + if (gres.gl_pathc != 1) + return rc; + + /* Replace the PCI address with interface name and get index */ + intf_name = basename(gres.gl_pathv[0]); + sprintf(path, ULP_PRT_MAC_PATH, pci_name, intf_name); + + fp = fopen(path, "r"); + if (!fp) { + BNXT_TF_DBG(ERR, "Error in getting bond mac address\n"); + return rc; + } + + memset(dev_str, 0, sizeof(dev_str)); + if (fgets(dev_str, sizeof(dev_str), fp) == NULL) { + BNXT_TF_DBG(ERR, "Error in reading %s\n", path); + fclose(fp); + return rc; + } + + if (sscanf(dev_str, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx\n", + &mac[0], &mac[1], &mac[2], + &mac[3], &mac[4], &mac[5]) == 6) + rc = 0; + fclose(fp); + } + return rc; +} + +int32_t bnxt_pmd_get_parent_mac_addr(struct bnxt_ulp_mapper_parms *parms, + uint8_t *mac) +{ + struct bnxt *bp = NULL; + int32_t rc = -EINVAL; + + bp = bnxt_pmd_get_bp(parms->port_id); + if (bp == NULL) { + BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id); + return rc; + } + return ulp_pmd_get_mac_by_pci(bp->pdev->name, &mac[2]); +} + +uint16_t +bnxt_pmd_get_svif(uint16_t port_id, bool func_svif, + enum bnxt_ulp_intf_type type) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + eth_dev = &rte_eth_devices[port_id]; + if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { + struct bnxt_representor *vfr = eth_dev->data->dev_private; + if (!vfr) + return 0; + + if (type == BNXT_ULP_INTF_TYPE_VF_REP) + return vfr->svif; + + eth_dev = vfr->parent_dev; + } + + bp = eth_dev->data->dev_private; + + return func_svif ? bp->func_svif : bp->port_svif; +} + +void +bnxt_pmd_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, + uint8_t *mac, uint8_t *parent_mac) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && + type != BNXT_ULP_INTF_TYPE_PF) + return; + + eth_dev = &rte_eth_devices[port]; + bp = eth_dev->data->dev_private; + memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); + + if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) + memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); +} + +uint16_t +bnxt_pmd_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) + return 0; + + eth_dev = &rte_eth_devices[port]; + bp = eth_dev->data->dev_private; + + return bp->parent->vnic; +} + +uint16_t +bnxt_pmd_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) +{ + struct rte_eth_dev *eth_dev; + struct bnxt_vnic_info *vnic; + struct bnxt *bp; + + eth_dev = &rte_eth_devices[port]; + if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { + struct bnxt_representor *vfr = eth_dev->data->dev_private; + if (!vfr) + return 0; + + if (type == BNXT_ULP_INTF_TYPE_VF_REP) + return vfr->dflt_vnic_id; + + eth_dev = vfr->parent_dev; + } + + bp = eth_dev->data->dev_private; + + vnic = BNXT_GET_DEFAULT_VNIC(bp); + + return vnic->fw_vnic_id; +} + +uint16_t +bnxt_pmd_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + eth_dev = &rte_eth_devices[port]; + if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { + struct bnxt_representor *vfr = eth_dev->data->dev_private; + if (!vfr) + return 0; + + if (type == BNXT_ULP_INTF_TYPE_VF_REP) + return vfr->fw_fid; + + eth_dev = vfr->parent_dev; + } + + bp = eth_dev->data->dev_private; + + return bp->fw_fid; +} + +enum bnxt_ulp_intf_type +bnxt_pmd_get_interface_type(uint16_t port) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + eth_dev = &rte_eth_devices[port]; + if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) + return BNXT_ULP_INTF_TYPE_VF_REP; + + bp = eth_dev->data->dev_private; + if (BNXT_PF(bp)) + return BNXT_ULP_INTF_TYPE_PF; + else if (BNXT_VF_IS_TRUSTED(bp)) + return BNXT_ULP_INTF_TYPE_TRUSTED_VF; + else if (BNXT_VF(bp)) + return BNXT_ULP_INTF_TYPE_VF; + + return BNXT_ULP_INTF_TYPE_INVALID; +} + +uint16_t +bnxt_pmd_get_phy_port_id(uint16_t port_id) +{ + struct bnxt_representor *vfr; + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + eth_dev = &rte_eth_devices[port_id]; + if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { + vfr = eth_dev->data->dev_private; + if (!vfr) + return 0; + + eth_dev = vfr->parent_dev; + } + + bp = eth_dev->data->dev_private; + + return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; +} + +uint16_t +bnxt_pmd_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + eth_dev = &rte_eth_devices[port_id]; + if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { + struct bnxt_representor *vfr = eth_dev->data->dev_private; + if (!vfr) + return 0; + + if (type == BNXT_ULP_INTF_TYPE_VF_REP) + return vfr->fw_fid - 1; + + eth_dev = vfr->parent_dev; + } + + bp = eth_dev->data->dev_private; + + return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; +} + +uint16_t +bnxt_pmd_get_vport(uint16_t port_id) +{ + return (1 << bnxt_pmd_get_phy_port_id(port_id)); +} + + +int32_t +bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev) +{ + struct bnxt *bp = eth_dev->data->dev_private; + struct bnxt_vnic_info *vnic; + uint32_t old_flags; + int32_t rc; + + rc = is_bnxt_in_error(bp); + if (rc) + return rc; + + /* Filter settings will get applied when port is started */ + if (!eth_dev->data->dev_started) + return 0; + + if (bp->vnic_info == NULL) + return 0; + + vnic = BNXT_GET_DEFAULT_VNIC(bp); + + old_flags = vnic->flags; + vnic->flags |= BNXT_VNIC_INFO_UCAST; + vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; + vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; + vnic->flags &= ~BNXT_VNIC_INFO_BCAST; + rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); + if (rc != 0) + vnic->flags = old_flags; + + return rc; +} diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h new file mode 100644 index 0000000000..229e21814b --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2021 Broadcom + * All rights reserved. + */ + +#ifndef _BNXT_TF_PMD_ABSTRACT_H_ +#define _BNXT_TF_PMD_ABSTRACT_H_ + +#include "bnxt_tf_common.h" +#include "ulp_mapper.h" + +int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms); +int32_t bnxt_pmd_get_parent_mac_addr(struct bnxt_ulp_mapper_parms *parms, + uint8_t *mac); +void bnxt_pmd_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, + uint8_t *mac, uint8_t *parent_mac); +uint16_t bnxt_pmd_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); +uint16_t bnxt_pmd_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); +struct bnxt *bnxt_pmd_get_bp(uint16_t port); +uint16_t bnxt_pmd_get_svif(uint16_t port_id, bool func_svif, + enum bnxt_ulp_intf_type type); +uint16_t bnxt_pmd_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); +uint16_t bnxt_pmd_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); +uint16_t bnxt_pmd_get_phy_port_id(uint16_t port); +uint16_t bnxt_pmd_get_vport(uint16_t port); +enum bnxt_ulp_intf_type bnxt_pmd_get_interface_type(uint16_t port); +int32_t bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev); + +#endif /* _BNXT_TF_PMD_ABSTRACT_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 5f1540027c..eb95afc653 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -25,6 +25,7 @@ #include "ulp_port_db.h" #include "ulp_tun.h" #include "ulp_ha_mgr.h" +#include "bnxt_tf_pmd_shim.h" /* Linked list of all TF sessions. */ STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list = @@ -67,7 +68,6 @@ bnxt_ulp_devid_get(struct bnxt *bp, enum bnxt_ulp_device_id *ulp_dev_id) { if (BNXT_CHIP_P5(bp)) { - /* TBD: needs to accommodate even SR2 */ *ulp_dev_id = BNXT_ULP_DEVICE_ID_THOR; return 0; } @@ -123,7 +123,7 @@ bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx, uint32_t num, struct tf_session_resources *res) { - uint32_t dev_id, res_type, i; + uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST, res_type, i; enum tf_dir dir; uint8_t app_id; int32_t rc = 0; @@ -331,6 +331,9 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, if (info[i].flags & BNXT_ULP_APP_CAP_HOT_UPGRADE_EN) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_HIGH_AVAIL_ENABLED; + if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_UNICAST_ONLY; } if (!found) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -378,8 +381,8 @@ ulp_ctx_shared_session_open(struct bnxt *bp, struct rte_eth_dev *ethdev = bp->eth_dev; struct tf_session_resources *resources; struct tf_open_session_parms parms; - size_t copy_num_bytes; - uint32_t ulp_dev_id; + size_t copy_nbytes; + uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; int32_t rc = 0; /* only perform this if shared session is enabled. */ @@ -401,11 +404,19 @@ ulp_ctx_shared_session_open(struct bnxt *bp, * Need to account for size of ctrl_chan_name and 1 extra for Null * terminator */ - copy_num_bytes = sizeof(parms.ctrl_chan_name) - + copy_nbytes = sizeof(parms.ctrl_chan_name) - strlen(parms.ctrl_chan_name) - 1; - /* Build the ctrl_chan_name with shared token */ - strncat(parms.ctrl_chan_name, "-tf_shared", copy_num_bytes); + /* + * Build the ctrl_chan_name with shared token. + * When HA is enabled, the WC TCAM needs extra management by the core, + * so add the wc_tcam string to the control channel. + */ + if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx)) + strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam", + copy_nbytes); + else + strncat(parms.ctrl_chan_name, "-tf_shared", copy_nbytes); rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, resources); if (rc) @@ -504,7 +515,7 @@ ulp_ctx_session_open(struct bnxt *bp, int32_t rc = 0; struct tf_open_session_parms params; struct tf_session_resources *resources; - uint32_t ulp_dev_id; + uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; memset(¶ms, 0, sizeof(params)); @@ -835,7 +846,7 @@ static int32_t ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) { struct bnxt_ulp_device_params *dparms; - uint32_t dev_id; + uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST; if (!bp->max_num_kflows) { /* Defaults to Internal */ @@ -890,7 +901,7 @@ ulp_ctx_attach(struct bnxt *bp, struct bnxt_ulp_session_state *session) { int32_t rc = 0; - uint32_t flags, dev_id; + uint32_t flags, dev_id = BNXT_ULP_DEVICE_ID_LAST; uint8_t app_id; /* Increment the ulp context data reference count usage. */ @@ -1350,15 +1361,21 @@ bnxt_ulp_port_init(struct bnxt *bp) { struct bnxt_ulp_session_state *session; bool initialized; + enum bnxt_ulp_device_id devid = BNXT_ULP_DEVICE_ID_LAST; + uint32_t ulp_flags; int32_t rc = 0; - if (!bp || !BNXT_TRUFLOW_EN(bp)) - return rc; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { BNXT_TF_DBG(ERR, "Skip ulp init for port: %d, not a TVF or PF\n", - bp->eth_dev->data->port_id); + bp->eth_dev->data->port_id); + return rc; + } + + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(ERR, + "Skip ulp init for port: %d, truflow is not enabled\n", + bp->eth_dev->data->port_id); return rc; } @@ -1436,11 +1453,31 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - if (BNXT_ACCUM_STATS_EN(bp)) + rc = bnxt_ulp_devid_get(bp, &devid); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to determine device for ULP port init.\n"); + goto jump_to_error; + } + + if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp)) bp->ulp_ctx->cfg_data->accum_stats = true; - BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init\n", - bp->eth_dev->data->port_id); + BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", + bp->eth_dev->data->port_id, + bp->ulp_ctx->cfg_data->accum_stats); + + /* set the unicast mode */ + if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(bp->ulp_ctx, &ulp_flags)) { + BNXT_TF_DBG(ERR, "Error in getting ULP context flags\n"); + goto jump_to_error; + } + if (ulp_flags & BNXT_ULP_APP_UNICAST_ONLY) { + if (bnxt_pmd_set_unicast_rxmask(bp->eth_dev)) { + BNXT_TF_DBG(ERR, "Error in setting unicast rxmode\n"); + goto jump_to_error; + } + } + return rc; jump_to_error: @@ -1459,9 +1496,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp) struct rte_pci_device *pci_dev; struct rte_pci_addr *pci_addr; - if (!BNXT_TRUFLOW_EN(bp)) - return; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { BNXT_TF_DBG(ERR, "Skip ULP deinit port:%d, not a TVF or PF\n", @@ -1469,6 +1503,13 @@ bnxt_ulp_port_deinit(struct bnxt *bp) return; } + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(ERR, + "Skip ULP deinit for port:%d, truflow is not enabled\n", + bp->eth_dev->data->port_id); + return; + } + if (!bp->ulp_ctx) { BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n"); return; @@ -1599,7 +1640,7 @@ bnxt_ulp_cntxt_dev_id_get(struct bnxt_ulp_context *ulp_ctx, *dev_id = ulp_ctx->cfg_data->dev_id; return 0; } - + *dev_id = BNXT_ULP_DEVICE_ID_LAST; BNXT_TF_DBG(ERR, "Failed to read dev_id from ulp ctxt\n"); return -EINVAL; } @@ -1624,6 +1665,7 @@ bnxt_ulp_cntxt_mem_type_get(struct bnxt_ulp_context *ulp_ctx, *mem_type = ulp_ctx->cfg_data->mem_type; return 0; } + *mem_type = BNXT_ULP_FLOW_MEM_TYPE_LAST; BNXT_TF_DBG(ERR, "Failed to read mem_type in ulp ctxt\n"); return -EINVAL; } @@ -1663,6 +1705,13 @@ bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp) return -EINVAL; } + if (tfp == NULL) { + if (ulp->cfg_data->num_shared_clients > 0) + ulp->cfg_data->num_shared_clients--; + } else { + ulp->cfg_data->num_shared_clients++; + } + ulp->g_shared_tfp = tfp; return 0; } @@ -1678,6 +1727,17 @@ bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp) return ulp->g_shared_tfp; } +/* Function to get the number of shared clients attached */ +uint8_t +bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp) +{ + if (ulp == NULL || ulp->cfg_data == NULL) { + BNXT_TF_DBG(ERR, "Invalid arguments\n"); + return 0; + } + return ulp->cfg_data->num_shared_clients; +} + /* Function to set the tfp session details from the ulp context. */ int32_t bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index ea38dc0d9f..082ca501b6 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -32,6 +32,7 @@ #define BNXT_ULP_SHARED_SESSION_ENABLED 0x2 #define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 #define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 +#define BNXT_ULP_APP_UNICAST_ONLY 0x10 #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ BNXT_ULP_SHARED_SESSION_ENABLED) @@ -77,6 +78,7 @@ struct bnxt_ulp_data { struct bnxt_tun_cache_entry tun_tbl[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; bool accum_stats; uint8_t app_id; + uint8_t num_shared_clients; }; struct bnxt_ulp_context { @@ -297,4 +299,6 @@ bnxt_ulp_cntxt_entry_acquire(void); void bnxt_ulp_cntxt_entry_release(void); +uint8_t +bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx); #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 96e6a76270..19e9dba356 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -103,6 +103,7 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, mapper_cparms->flow_pattern_id = params->flow_pattern_id; mapper_cparms->act_pattern_id = params->act_pattern_id; mapper_cparms->app_id = params->app_id; + mapper_cparms->port_id = params->port_id; /* update the signature fields into the computed field list */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID, diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build index 40479c5936..456d8ca7b6 100644 --- a/drivers/net/bnxt/tf_ulp/meson.build +++ b/drivers/net/bnxt/tf_ulp/meson.build @@ -22,6 +22,7 @@ sources += files( 'ulp_def_rules.c', 'ulp_fc_mgr.c', 'ulp_tun.c', + 'bnxt_tf_pmd_shim.c', 'ulp_gen_tbl.c', 'ulp_gen_hash.c', 'ulp_ha_mgr.c', diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index 483030edbf..d8336d164e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -299,7 +299,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, uint32_t *flow_id) { struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX]; - uint32_t comp_fld[BNXT_ULP_CF_IDX_LAST]; + uint64_t comp_fld[BNXT_ULP_CF_IDX_LAST]; struct bnxt_ulp_mapper_create_parms mapper_params = { 0 }; struct ulp_rte_act_prop act_prop; struct ulp_rte_act_bitmap act = { 0 }; @@ -318,6 +318,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, mapper_params.comp_fld = comp_fld; mapper_params.class_tid = ulp_class_tid; mapper_params.flow_type = BNXT_ULP_FDB_TYPE_DEFAULT; + mapper_params.port_id = eth_dev->data->port_id; ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (!ulp_ctx) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 9a77132385..13f71ed83b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -80,12 +80,6 @@ ulp_fc_mgr_init(struct bnxt_ulp_context *ctxt) return -EINVAL; } - if (!dparms->flow_count_db_entries) { - BNXT_TF_DBG(DEBUG, "flow counter support is not enabled\n"); - bnxt_ulp_cntxt_ptr2_fc_info_set(ctxt, NULL); - return 0; - } - ulp_fc_info = rte_zmalloc("ulp_fc_info", sizeof(*ulp_fc_info), 0); if (!ulp_fc_info) goto error; @@ -99,6 +93,13 @@ ulp_fc_mgr_init(struct bnxt_ulp_context *ctxt) /* Add the FC info tbl to the ulp context. */ bnxt_ulp_cntxt_ptr2_fc_info_set(ctxt, ulp_fc_info); + ulp_fc_info->num_counters = dparms->flow_count_db_entries; + if (!ulp_fc_info->num_counters) { + /* No need for software counters, call fw directly */ + BNXT_TF_DBG(DEBUG, "Sw flow counter support not enabled\n"); + return 0; + } + sw_acc_cntr_tbl_sz = sizeof(struct sw_acc_counter) * dparms->flow_count_db_entries; @@ -138,6 +139,7 @@ int32_t ulp_fc_mgr_deinit(struct bnxt_ulp_context *ctxt) { struct bnxt_ulp_fc_info *ulp_fc_info; + struct hw_fc_mem_info *shd_info; int i; ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt); @@ -149,11 +151,15 @@ ulp_fc_mgr_deinit(struct bnxt_ulp_context *ctxt) pthread_mutex_destroy(&ulp_fc_info->fc_lock); - for (i = 0; i < TF_DIR_MAX; i++) - rte_free(ulp_fc_info->sw_acc_tbl[i]); + if (ulp_fc_info->num_counters) { + for (i = 0; i < TF_DIR_MAX; i++) + rte_free(ulp_fc_info->sw_acc_tbl[i]); - for (i = 0; i < TF_DIR_MAX; i++) - ulp_fc_mgr_shadow_mem_free(&ulp_fc_info->shadow_hw_tbl[i]); + for (i = 0; i < TF_DIR_MAX; i++) { + shd_info = &ulp_fc_info->shadow_hw_tbl[i]; + ulp_fc_mgr_shadow_mem_free(shd_info); + } + } rte_free(ulp_fc_info); @@ -291,6 +297,74 @@ ulp_bulk_get_flow_stats(struct tf *tfp, return rc; } +static int32_t +ulp_fc_tf_flow_stat_get(struct bnxt_ulp_context *ctxt, + struct ulp_flow_db_res_params *res, + struct rte_flow_query_count *qcount) +{ + struct tf *tfp; + struct bnxt_ulp_device_params *dparms; + struct tf_get_tbl_entry_parms parms = { 0 }; + struct tf_set_tbl_entry_parms sparms = { 0 }; + enum tf_tbl_type stype = TF_TBL_TYPE_ACT_STATS_64; + uint64_t stats = 0; + uint32_t dev_id = 0; + int32_t rc = 0; + + tfp = bnxt_ulp_cntxt_tfp_get(ctxt, BNXT_ULP_SHARED_SESSION_NO); + if (!tfp) { + BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n"); + return -EINVAL; + } + + if (bnxt_ulp_cntxt_dev_id_get(ctxt, &dev_id)) { + BNXT_TF_DBG(DEBUG, "Failed to get device id\n"); + bnxt_ulp_cntxt_entry_release(); + return -EINVAL; + } + + dparms = bnxt_ulp_device_params_get(dev_id); + if (!dparms) { + BNXT_TF_DBG(DEBUG, "Failed to device parms\n"); + bnxt_ulp_cntxt_entry_release(); + return -EINVAL; + } + parms.dir = res->direction; + parms.type = stype; + parms.idx = res->resource_hndl; + parms.data_sz_in_bytes = sizeof(uint64_t); + parms.data = (uint8_t *)&stats; + rc = tf_get_tbl_entry(tfp, &parms); + if (rc) { + PMD_DRV_LOG(ERR, + "Get failed for id:0x%x rc:%d\n", + parms.idx, rc); + return rc; + } + qcount->hits = FLOW_CNTR_PKTS(stats, dparms); + if (qcount->hits) + qcount->hits_set = 1; + qcount->bytes = FLOW_CNTR_BYTES(stats, dparms); + if (qcount->bytes) + qcount->bytes_set = 1; + + if (qcount->reset) { + stats = 0; + sparms.dir = res->direction; + sparms.type = stype; + sparms.idx = res->resource_hndl; + sparms.data = (uint8_t *)&stats; + sparms.data_sz_in_bytes = sizeof(uint64_t); + rc = tf_set_tbl_entry(tfp, &sparms); + if (rc) { + PMD_DRV_LOG(ERR, "Set failed for id:0x%x rc:%d\n", + sparms.idx, rc); + return rc; + } + } + return rc; +} + static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, struct tf *tfp, struct bnxt_ulp_fc_info *fc_info, @@ -540,6 +614,9 @@ int32_t ulp_fc_mgr_cntr_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir, if (!ulp_fc_info) return -EIO; + if (!ulp_fc_info->num_counters) + return 0; + pthread_mutex_lock(&ulp_fc_info->fc_lock); sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx; ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid = true; @@ -572,6 +649,9 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir, if (!ulp_fc_info) return -EIO; + if (!ulp_fc_info->num_counters) + return 0; + pthread_mutex_lock(&ulp_fc_info->fc_lock); sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx; ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid = false; @@ -644,6 +724,9 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, hw_cntr_id = params.resource_hndl; if (params.resource_sub_type == BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { + if (!ulp_fc_info->num_counters) + return ulp_fc_tf_flow_stat_get(ctxt, ¶ms, count); + /* TODO: * Think about optimizing with try_lock later */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h index 04cb86bea2..448d05c118 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h @@ -48,6 +48,7 @@ struct bnxt_ulp_fc_info { uint32_t flags; uint32_t num_entries; pthread_mutex_t fc_lock; + uint32_t num_counters; }; int32_t diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index e7e8335dbe..ab6013f0e3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info) func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >> ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER); - /* The reource func is split into upper and lower */ + /* The resource func is split into upper and lower */ if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER) return (func | res_info->resource_func_lower); return func; @@ -712,6 +712,12 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, } fid_resource = &flow_tbl->flow_resources[fid]; + if (params->critical_resource && fid_resource->resource_em_handle) { + BNXT_TF_DBG(DEBUG, "Ignore multiple critical resources\n"); + /* Ignore the multiple critical resources */ + params->critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; + } + if (!params->critical_resource) { /* Not the critical_resource so allocate a resource */ idx = flow_tbl->flow_tbl_stack[flow_tbl->tail_index]; @@ -735,7 +741,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, if (params->resource_type == TF_TBL_TYPE_ACT_STATS_64 && params->resource_sub_type == BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT && - ulp_fc_info) { + ulp_fc_info && ulp_fc_info->num_counters) { /* Store the first HW counter ID for this table */ if (!ulp_fc_mgr_start_idx_isset(ulp_ctxt, params->direction)) ulp_fc_mgr_start_idx_set(ulp_ctxt, params->direction, @@ -760,7 +766,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, * flow_type [in] Specify it is regular or default flow * fid [in] The index to the flow entry * params [in/out] The contents to be copied into params. - * Onlythe critical_resource needs to be set by the caller. + * Only the critical_resource needs to be set by the caller. * * Returns 0 on success and negative on failure. */ @@ -1287,7 +1293,7 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx, BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, sub_typ, ¶ms); if (rc) { - BNXT_TF_DBG(ERR, "CFA Action ptr not found for flow id %u\n", + BNXT_TF_DBG(INFO, "CFA Action ptr not found for flow id %u\n", flow_id); return -ENOENT; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h index d84715e59c..67afca8872 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h @@ -18,7 +18,7 @@ /* * Structure for the flow database resource information - * The below structure is based on the below paritions + * The below structure is based on the below partitions * nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0] * If resource_func is EM_TBL then use resource_em_handle. * Else the other part of the union is used and diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c index 5c94e2f5d0..3c1af0b007 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c @@ -346,11 +346,15 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } fid = tfp_be_to_cpu_32(fid); - - /* Destroy the flow associated with the shared flow id */ - if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_RID, - fid)) - BNXT_TF_DBG(ERR, "Error in deleting shared flow id %x\n", fid); + /* no need to del if fid is 0 since there is no associated resource */ + if (fid) { + /* Destroy the flow associated with the shared flow id */ + if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_RID, + fid)) + BNXT_TF_DBG(ERR, + "Error in deleting shared flow id %x\n", + fid); + } /* Delete the entry from the hash table */ if (gen_tbl_list->hash_tbl) diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c index 1cfe5cd0a7..5f5b5d639e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c @@ -24,8 +24,9 @@ #define ULP_HA_IF_TBL_DIR TF_DIR_RX #define ULP_HA_IF_TBL_TYPE TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR #define ULP_HA_IF_TBL_IDX 10 +#define ULP_HA_CLIENT_CNT_IF_TBL_IDX 9 -static void ulp_ha_mgr_timer_cancel(struct bnxt_ulp_context *ulp_ctx); +static void ulp_ha_mgr_timer_cancel(void); static int32_t ulp_ha_mgr_timer_start(void); static void ulp_ha_mgr_timer_cb(void *arg); static int32_t ulp_ha_mgr_app_type_set(struct bnxt_ulp_context *ulp_ctx, @@ -37,6 +38,9 @@ static int32_t ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx, enum ulp_ha_mgr_state state); +static int32_t +ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *cnt); + static int32_t ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx, enum ulp_ha_mgr_state state) @@ -71,6 +75,39 @@ ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx, return rc; } +static int32_t +ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx, + uint32_t *cnt) +{ + struct tf_get_if_tbl_entry_parms get_parms = { 0 }; + struct tf *tfp; + uint32_t val = 0; + int32_t rc = 0; + + if (ulp_ctx == NULL || cnt == NULL) { + BNXT_TF_DBG(ERR, "Invalid parms in client num get.\n"); + return -EINVAL; + } + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); + if (tfp == NULL) { + BNXT_TF_DBG(ERR, "Unable to get the TFP.\n"); + return -EINVAL; + } + + get_parms.dir = ULP_HA_IF_TBL_DIR; + get_parms.type = ULP_HA_IF_TBL_TYPE; + get_parms.idx = ULP_HA_CLIENT_CNT_IF_TBL_IDX; + get_parms.data = (uint8_t *)&val; + get_parms.data_sz_in_bytes = sizeof(val); + + rc = tf_get_if_tbl_entry(tfp, &get_parms); + if (rc) + BNXT_TF_DBG(ERR, "Failed to read the number of HA clients\n"); + + *cnt = val; + return rc; +} + static int32_t ulp_ha_mgr_region_set(struct bnxt_ulp_context *ulp_ctx, enum ulp_ha_mgr_region region) @@ -113,44 +150,113 @@ ulp_ha_mgr_app_type_set(struct bnxt_ulp_context *ulp_ctx, return 0; } -/* - * When a secondary opens, the timer is started and periodically checks for a - * close of the primary (state moved to SEC_TIMER_COPY). - * In SEC_TIMER_COPY: - * - The flow db must be locked to prevent flows from being added to the high - * region during a move. - * - Move the high entries to low - * - Set the region to low for subsequent flows - * - Switch our persona to Primary - * - Set the state to Primary Run - * - Release the flow db lock for flows to continue - */ static void ulp_ha_mgr_timer_cb(void *arg __rte_unused) { struct tf_move_tcam_shared_entries_parms mparms = { 0 }; + struct tf_clear_tcam_shared_entries_parms cparms = { 0 }; struct bnxt_ulp_context *ulp_ctx; enum ulp_ha_mgr_state curr_state; + enum ulp_ha_mgr_app_type app_type; + uint8_t myclient_cnt = 0; + uint32_t client_cnt = 0; struct tf *tfp; int32_t rc; ulp_ctx = bnxt_ulp_cntxt_entry_acquire(); if (ulp_ctx == NULL) { - BNXT_TF_DBG(INFO, "could not get the ulp context lock\n"); ulp_ha_mgr_timer_start(); return; } + myclient_cnt = bnxt_ulp_cntxt_num_shared_clients_get(ulp_ctx); + if (myclient_cnt == 0) { + BNXT_TF_DBG(ERR, + "PANIC Client Count is zero kill timer\n."); + return; + } + + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_YES); + if (tfp == NULL) { + BNXT_TF_DBG(ERR, "Unable to get the TFP.\n"); + goto cb_restart; + } + rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state); if (rc) { /* - * This shouldn't happen, if it does, resetart the timer + * This shouldn't happen, if it does, reset the timer * and try again next time. */ - BNXT_TF_DBG(ERR, "On HA CB:Failed(%d) to get state.\n", rc); + BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n", + rc); goto cb_restart; } - if (curr_state != ULP_HA_STATE_SEC_TIMER_COPY) + + rc = ulp_ha_mgr_tf_client_num_get(ulp_ctx, &client_cnt); + if (rc) { + BNXT_TF_DBG(ERR, "Failed(%d) to get cnt.\n", + rc); + goto cb_restart; + } + + rc = ulp_ha_mgr_app_type_get(ulp_ctx, &app_type); + if (rc) { + BNXT_TF_DBG(ERR, "Failed(%d) to get type.\n", + rc); + goto cb_restart; + } + + /* Handle the Cleanup if an app went away */ + if (client_cnt == myclient_cnt) { + if (curr_state == ULP_HA_STATE_PRIM_SEC_RUN && + app_type == ULP_HA_APP_TYPE_PRIM) { + /* + * The SECONDARY went away: + * 1. Set the state to PRIM_RUN + * 2. Clear the High region so our TCAM will hit. + */ + rc = ulp_ha_mgr_state_set(ulp_ctx, + ULP_HA_STATE_PRIM_RUN); + if (rc) { + BNXT_TF_DBG(ERR, + "On HA CB:Failed(%d) to set state\n", + rc); + goto cb_restart; + } + + cparms.dir = TF_DIR_RX; + cparms.tcam_tbl_type = + TF_TCAM_TBL_TYPE_WC_TCAM_HIGH; + rc = tf_clear_tcam_shared_entries(tfp, &cparms); + if (rc) { + BNXT_TF_DBG(ERR, + "On HA CB:Failed(%d) clear tcam\n", + rc); + goto cb_restart; + } + } else if (curr_state == ULP_HA_STATE_PRIM_SEC_RUN && + app_type == ULP_HA_APP_TYPE_SEC) { + /* + * The PRIMARY went away: + * 1. Set the state to SEC_COPY + * 2. Clear the Low Region for the next copy + */ + rc = ulp_ha_mgr_state_set(ulp_ctx, + ULP_HA_STATE_SEC_TIMER_COPY); + if (rc) { + BNXT_TF_DBG(ERR, + "On HA CB:Failed(%d) to set state\n", + rc); + goto cb_restart; + } + curr_state = ULP_HA_STATE_SEC_TIMER_COPY; + } + } + + /* Only the Secondary has work to on SEC_TIMER_COPY */ + if (curr_state != ULP_HA_STATE_SEC_TIMER_COPY || + app_type != ULP_HA_APP_TYPE_SEC) goto cb_restart; /* Protect the flow database during the copy */ @@ -166,14 +272,19 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused) * move WC entries to Low Region. */ BNXT_TF_DBG(INFO, "On HA CB: Moving entries HI to LOW\n"); - mparms.dir = TF_DIR_RX; - mparms.tcam_tbl_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH; - tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_YES); - if (tfp == NULL) { - BNXT_TF_DBG(ERR, "On HA CB: Unable to get the TFP.\n"); + + cparms.dir = TF_DIR_RX; + cparms.tcam_tbl_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW; + rc = tf_clear_tcam_shared_entries(tfp, &cparms); + if (rc) { + BNXT_TF_DBG(ERR, + "On HA CB:Failed(%d) clear tcam low\n", + rc); goto unlock; } + mparms.dir = TF_DIR_RX; + mparms.tcam_tbl_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH; rc = tf_move_tcam_shared_entries(tfp, &mparms); if (rc) { BNXT_TF_DBG(ERR, "On HA_CB: Failed to move entries\n"); @@ -186,8 +297,6 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused) BNXT_TF_DBG(INFO, "On HA CB: SEC[SEC_TIMER_COPY] => PRIM[PRIM_RUN]\n"); unlock: bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); - bnxt_ulp_cntxt_entry_release(); - return; cb_restart: bnxt_ulp_cntxt_entry_release(); ulp_ha_mgr_timer_start(); @@ -202,18 +311,9 @@ ulp_ha_mgr_timer_start(void) } static void -ulp_ha_mgr_timer_cancel(struct bnxt_ulp_context *ulp_ctx) +ulp_ha_mgr_timer_cancel(void) { - struct bnxt_ulp_ha_mgr_info *ha_info; - - ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); - if (ha_info == NULL) { - BNXT_TF_DBG(ERR, "Unable to get ha info\n"); - return; - } - - ha_info->flags &= ~ULP_HA_TIMER_THREAD; - rte_eal_alarm_cancel(ulp_ha_mgr_timer_cb, (void *)ulp_ctx); + rte_eal_alarm_cancel(ulp_ha_mgr_timer_cb, (void *)NULL); } int32_t @@ -233,6 +333,11 @@ ulp_ha_mgr_init(struct bnxt_ulp_context *ulp_ctx) PMD_DRV_LOG(ERR, "Failed to initialize ha mutex\n"); goto cleanup; } + rc = ulp_ha_mgr_timer_start(); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to start timer CB.\n"); + goto cleanup; + } return 0; cleanup: @@ -246,6 +351,8 @@ ulp_ha_mgr_deinit(struct bnxt_ulp_context *ulp_ctx) { struct bnxt_ulp_ha_mgr_info *ha_info; + ulp_ha_mgr_timer_cancel(); + ha_info = bnxt_ulp_cntxt_ptr2_ha_info_get(ulp_ctx); if (ha_info == NULL) { BNXT_TF_DBG(ERR, "Unable to get HA Info for deinit.\n"); @@ -355,24 +462,10 @@ ulp_ha_mgr_open(struct bnxt_ulp_context *ulp_ctx) * The current primary is expected to eventually close and pass * full control to this system;however, until the primary closes * both are operational. - * - * The timer is started in order to determine when the - * primary has closed. */ ulp_ha_mgr_app_type_set(ulp_ctx, ULP_HA_APP_TYPE_SEC); ulp_ha_mgr_region_set(ulp_ctx, ULP_HA_REGION_HI); - /* - * TODO: - * Clear the high region so the secondary can begin overriding - * the current entries. - */ - rc = ulp_ha_mgr_timer_start(); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to start timer on HA Open.\n"); - return -EINVAL; - } - rc = ulp_ha_mgr_state_set(ulp_ctx, ULP_HA_STATE_PRIM_SEC_RUN); if (rc) { BNXT_TF_DBG(ERR, "On Open: Failed to set PRIM_SEC_RUN\n"); @@ -396,6 +489,8 @@ ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx) int32_t timeout; int32_t rc; + curr_state = ULP_HA_STATE_INIT; + app_type = ULP_HA_APP_TYPE_NONE; rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state); if (rc) { BNXT_TF_DBG(ERR, "On Close: Failed(%d) to get HA state\n", rc); @@ -462,10 +557,8 @@ ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx) app_type == ULP_HA_APP_TYPE_SEC) { /* * While both are running, the secondary unexpectedly received a - * close. Cancel the timer, set the state to Primary RUN since - * it is the only one running. + * close. */ - ulp_ha_mgr_timer_cancel(ulp_ctx); ulp_ha_mgr_state_set(ulp_ctx, ULP_HA_STATE_PRIM_RUN); BNXT_TF_DBG(INFO, "On Close: SEC[PRIM_SEC_RUN] => [PRIM_RUN]\n"); diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 05a43b6dc5..acd9f996e8 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -20,6 +20,7 @@ #include "ulp_template_db_tbl.h" #include "ulp_port_db.h" #include "ulp_ha_mgr.h" +#include "bnxt_tf_pmd_shim.h" static uint8_t mapper_fld_zeros[16] = { 0 }; @@ -996,13 +997,13 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } idx = tfp_be_to_cpu_16(idx); - if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) { + if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) { BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx, bytelen); return -EINVAL; } buffer = (uint8_t *)&parms->comp_fld[idx]; - *val = &buffer[sizeof(uint32_t) - bytelen]; + *val = &buffer[sizeof(uint64_t) - bytelen]; *value = ULP_COMP_FLD_IDX_RD(parms, idx); break; case BNXT_ULP_FIELD_SRC_RF: @@ -3177,109 +3178,141 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms, } static int32_t -ulp_mapper_cc_upd_opr_compute(struct bnxt_ulp_mapper_parms *parms, - enum tf_dir dir, - enum bnxt_ulp_cc_upd_src cc_src, - uint16_t cc_opr, - uint64_t *result) +ulp_mapper_func_opr_compute(struct bnxt_ulp_mapper_parms *parms, + enum tf_dir dir, + enum bnxt_ulp_func_src func_src, + uint16_t func_opr, + uint64_t *result) { uint64_t regval; bool shared; *result = false; - switch (cc_src) { - case BNXT_ULP_CC_UPD_SRC_COMP_FIELD: - if (cc_opr >= BNXT_ULP_CF_IDX_LAST) { - BNXT_TF_DBG(ERR, "invalid index %u\n", cc_opr); + switch (func_src) { + case BNXT_ULP_FUNC_SRC_COMP_FIELD: + if (func_opr >= BNXT_ULP_CF_IDX_LAST) { + BNXT_TF_DBG(ERR, "invalid index %u\n", func_opr); return -EINVAL; } - *result = (uint64_t)ULP_COMP_FLD_IDX_RD(parms, cc_opr); + *result = ULP_COMP_FLD_IDX_RD(parms, func_opr); break; - case BNXT_ULP_CC_UPD_SRC_REGFILE: - if (!ulp_regfile_read(parms->regfile, cc_opr, ®val)) { - BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", cc_opr); + case BNXT_ULP_FUNC_SRC_REGFILE: + if (!ulp_regfile_read(parms->regfile, func_opr, ®val)) { + BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", func_opr); return -EINVAL; } *result = tfp_be_to_cpu_64(regval); break; - case BNXT_ULP_CC_UPD_SRC_GLB_REGFILE: + case BNXT_ULP_FUNC_SRC_GLB_REGFILE: if (ulp_mapper_glb_resource_read(parms->mapper_data, dir, - cc_opr, ®val, &shared)) { + func_opr, ®val, &shared)) { BNXT_TF_DBG(ERR, "global regfile[%d] read failed.\n", - cc_opr); + func_opr); return -EINVAL; } *result = tfp_be_to_cpu_64(regval); break; - case BNXT_ULP_CC_UPD_SRC_CONST: - *result = cc_opr; + case BNXT_ULP_FUNC_SRC_CONST: + *result = func_opr; break; default: - BNXT_TF_DBG(ERR, "invalid src code %u\n", cc_src); + BNXT_TF_DBG(ERR, "invalid src code %u\n", func_src); return -EINVAL; } return 0; } static int32_t -ulp_mapper_cc_upd_info_process(struct bnxt_ulp_mapper_parms *parms, - struct bnxt_ulp_mapper_tbl_info *tbl) +ulp_mapper_func_info_process(struct bnxt_ulp_mapper_parms *parms, + struct bnxt_ulp_mapper_tbl_info *tbl) { - struct bnxt_ulp_mapper_cc_upd_info *cc_upd = &tbl->cc_upd_info; - uint64_t res = 0, res1, res2; + struct bnxt_ulp_mapper_func_info *func_info = &tbl->func_info; + uint64_t res = 0, res1 = 0, res2 = 0; int32_t rc = 0; + uint32_t process_src1 = 0, process_src2 = 0; - if (cc_upd->cc_opc == BNXT_ULP_CC_UPD_OPC_NOP) + /* determine which functional operands to compute */ + switch (func_info->func_opc) { + case BNXT_ULP_FUNC_OPC_NOP: return rc; + case BNXT_ULP_FUNC_OPC_EQ: + case BNXT_ULP_FUNC_OPC_NE: + case BNXT_ULP_FUNC_OPC_GE: + case BNXT_ULP_FUNC_OPC_GT: + case BNXT_ULP_FUNC_OPC_LE: + case BNXT_ULP_FUNC_OPC_LT: + process_src1 = 1; + process_src2 = 1; + break; + case BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF: + process_src1 = 1; + break; + default: + break; + } - rc = ulp_mapper_cc_upd_opr_compute(parms, tbl->direction, - cc_upd->cc_src1, - cc_upd->cc_opr1, &res1); - if (rc) - return rc; + if (process_src1) { + rc = ulp_mapper_func_opr_compute(parms, tbl->direction, + func_info->func_src1, + func_info->func_opr1, &res1); + if (rc) + return rc; + } - rc = ulp_mapper_cc_upd_opr_compute(parms, tbl->direction, - cc_upd->cc_src2, - cc_upd->cc_opr2, &res2); - if (rc) - return rc; + if (process_src2) { + rc = ulp_mapper_func_opr_compute(parms, tbl->direction, + func_info->func_src2, + func_info->func_opr2, &res2); + if (rc) + return rc; + } - switch (cc_upd->cc_opc) { - case BNXT_ULP_CC_UPD_OPC_NOP: - res = 1; - break; - case BNXT_ULP_CC_UPD_OPC_EQ: + /* perform the functional opcode operations */ + switch (func_info->func_opc) { + case BNXT_ULP_FUNC_OPC_EQ: if (res1 == res2) res = 1; break; - case BNXT_ULP_CC_UPD_OPC_NE: + case BNXT_ULP_FUNC_OPC_NE: if (res1 != res2) res = 1; break; - case BNXT_ULP_CC_UPD_OPC_GE: + case BNXT_ULP_FUNC_OPC_GE: if (res1 >= res2) res = 1; break; - case BNXT_ULP_CC_UPD_OPC_GT: + case BNXT_ULP_FUNC_OPC_GT: if (res1 > res2) res = 1; break; - case BNXT_ULP_CC_UPD_OPC_LE: + case BNXT_ULP_FUNC_OPC_LE: if (res1 <= res2) res = 1; break; - case BNXT_ULP_CC_UPD_OPC_LT: + case BNXT_ULP_FUNC_OPC_LT: if (res1 < res2) res = 1; break; - case BNXT_ULP_CC_UPD_OPC_LAST: - BNXT_TF_DBG(ERR, "invalid code %u\n", cc_upd->cc_opc); + case BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF: + res = res1; + break; + case BNXT_ULP_FUNC_OPC_RSS_CONFIG: + /* apply the rss config using pmd method */ + return bnxt_rss_config_action_apply(parms); + case BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR: + rc = bnxt_pmd_get_parent_mac_addr(parms, (uint8_t *)&res); + if (rc) + return -EINVAL; + res = tfp_be_to_cpu_64(res); + break; + default: + BNXT_TF_DBG(ERR, "invalid func code %u\n", func_info->func_opc); return -EINVAL; } - if (ulp_regfile_write(parms->regfile, cc_upd->cc_dst_opr, + if (ulp_regfile_write(parms->regfile, func_info->func_dst_opr, tfp_cpu_to_be_64(res))) { - BNXT_TF_DBG(ERR, "Failed write the cc_opc %u\n", - cc_upd->cc_dst_opr); + BNXT_TF_DBG(ERR, "Failed write the func_opc %u\n", + func_info->func_dst_opr); return -EINVAL; } @@ -3366,7 +3399,7 @@ ulp_mapper_conflict_resolution_process(struct bnxt_ulp_mapper_parms *parms, { int32_t rc = 0; uint64_t regval; - uint64_t comp_sig_id; + uint64_t comp_sig; *res = 0; switch (tbl->accept_opcode) { @@ -3399,14 +3432,14 @@ ulp_mapper_conflict_resolution_process(struct bnxt_ulp_mapper_parms *parms, BNXT_ULP_RF_IDX_FLOW_SIG_ID); return -EINVAL; } - comp_sig_id = ULP_COMP_FLD_IDX_RD(parms, - BNXT_ULP_CF_IDX_FLOW_SIG_ID); + comp_sig = ULP_COMP_FLD_IDX_RD(parms, + BNXT_ULP_CF_IDX_FLOW_SIG_ID); regval = tfp_be_to_cpu_64(regval); - if (comp_sig_id == regval) + if (comp_sig == regval) *res = 1; else - BNXT_TF_DBG(ERR, "failed signature match %x:%x\n", - (uint32_t)comp_sig_id, (uint32_t)regval); + BNXT_TF_DBG(ERR, "failed signature match 0x%016" + PRIX64 ":%x\n", comp_sig, (uint32_t)regval); break; default: BNXT_TF_DBG(ERR, "Invalid accept opcode %d\n", @@ -3462,8 +3495,9 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) { tbl = &tbls[tbl_idx]; - /* Process the conditional code update opcodes */ - if (ulp_mapper_cc_upd_info_process(parms, tbl)) { + cond_goto = tbl->execute_info.cond_true_goto; + /* Process the conditional func code opcodes */ + if (ulp_mapper_func_info_process(parms, tbl)) { BNXT_TF_DBG(ERR, "Failed to process cond update\n"); rc = -EINVAL; goto error; @@ -3758,6 +3792,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, parms.flow_pattern_id = cparms->flow_pattern_id; parms.act_pattern_id = cparms->act_pattern_id; parms.app_id = cparms->app_id; + parms.port_id = cparms->port_id; /* Get the device id from the ulp context */ if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 4c5dd4b836..004e89ac2b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -46,7 +46,7 @@ struct bnxt_ulp_mapper_parms { struct ulp_rte_hdr_bitmap *hdr_bitmap; struct ulp_rte_hdr_field *hdr_field; struct ulp_rte_field_bitmap *fld_bitmap; - uint32_t *comp_fld; + uint64_t *comp_fld; struct ulp_regfile *regfile; struct bnxt_ulp_context *ulp_ctx; uint32_t fid; @@ -61,13 +61,14 @@ struct bnxt_ulp_mapper_parms { uint32_t flow_pattern_id; uint32_t act_pattern_id; uint8_t app_id; + uint16_t port_id; }; struct bnxt_ulp_mapper_create_parms { uint32_t app_priority; struct ulp_rte_hdr_bitmap *hdr_bitmap; struct ulp_rte_hdr_field *hdr_field; - uint32_t *comp_fld; + uint64_t *comp_fld; struct ulp_rte_act_bitmap *act; struct ulp_rte_act_prop *act_prop; struct ulp_rte_field_bitmap *fld_bitmap; @@ -89,6 +90,7 @@ struct bnxt_ulp_mapper_create_parms { uint32_t flow_pattern_id; uint32_t act_pattern_id; uint8_t app_id; + uint16_t port_id; }; /* Function to initialize any dynamic mapper data. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 96fc456d4c..4045473097 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -9,6 +9,7 @@ #include "bnxt_tf_common.h" #include "ulp_port_db.h" #include "tfp.h" +#include "bnxt_tf_pmd_shim.h" static uint32_t ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db) @@ -148,57 +149,57 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt, /* update the interface details */ intf = &port_db->ulp_intf_list[ifindex]; - intf->type = bnxt_get_interface_type(port_id); - intf->drv_func_id = bnxt_get_fw_func_id(port_id, - BNXT_ULP_INTF_TYPE_INVALID); + intf->type = bnxt_pmd_get_interface_type(port_id); + intf->drv_func_id = bnxt_pmd_get_fw_func_id(port_id, + BNXT_ULP_INTF_TYPE_INVALID); func = &port_db->ulp_func_id_tbl[intf->drv_func_id]; if (!func->func_valid) { - func->func_svif = bnxt_get_svif(port_id, true, - BNXT_ULP_INTF_TYPE_INVALID); - func->func_spif = bnxt_get_phy_port_id(port_id); + func->func_svif = bnxt_pmd_get_svif(port_id, true, + BNXT_ULP_INTF_TYPE_INVALID); + func->func_spif = bnxt_pmd_get_phy_port_id(port_id); func->func_parif = - bnxt_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID); + bnxt_pmd_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID); func->func_vnic = - bnxt_get_vnic_id(port_id, BNXT_ULP_INTF_TYPE_INVALID); - func->phy_port_id = bnxt_get_phy_port_id(port_id); + bnxt_pmd_get_vnic_id(port_id, BNXT_ULP_INTF_TYPE_INVALID); + func->phy_port_id = bnxt_pmd_get_phy_port_id(port_id); func->func_valid = true; func->ifindex = ifindex; } if (intf->type == BNXT_ULP_INTF_TYPE_VF_REP) { intf->vf_func_id = - bnxt_get_fw_func_id(port_id, BNXT_ULP_INTF_TYPE_VF_REP); + bnxt_pmd_get_fw_func_id(port_id, BNXT_ULP_INTF_TYPE_VF_REP); func = &port_db->ulp_func_id_tbl[intf->vf_func_id]; func->func_svif = - bnxt_get_svif(port_id, true, BNXT_ULP_INTF_TYPE_VF_REP); + bnxt_pmd_get_svif(port_id, true, BNXT_ULP_INTF_TYPE_VF_REP); func->func_spif = - bnxt_get_phy_port_id(port_id); + bnxt_pmd_get_phy_port_id(port_id); func->func_parif = - bnxt_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID); + bnxt_pmd_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID); func->func_vnic = - bnxt_get_vnic_id(port_id, BNXT_ULP_INTF_TYPE_VF_REP); - func->phy_port_id = bnxt_get_phy_port_id(port_id); + bnxt_pmd_get_vnic_id(port_id, BNXT_ULP_INTF_TYPE_VF_REP); + func->phy_port_id = bnxt_pmd_get_phy_port_id(port_id); func->ifindex = ifindex; } /* When there is no match, the default action is to send the packet to * the kernel. And to send it to the kernel, we need the PF's vnic id. */ - func->func_parent_vnic = bnxt_get_parent_vnic_id(port_id, intf->type); + func->func_parent_vnic = bnxt_pmd_get_parent_vnic_id(port_id, intf->type); func->func_parent_vnic = tfp_cpu_to_be_16(func->func_parent_vnic); - bnxt_get_iface_mac(port_id, intf->type, func->func_mac, + bnxt_pmd_get_iface_mac(port_id, intf->type, func->func_mac, func->func_parent_mac); port_data = &port_db->phy_port_list[func->phy_port_id]; if (!port_data->port_valid) { port_data->port_svif = - bnxt_get_svif(port_id, false, BNXT_ULP_INTF_TYPE_INVALID); - port_data->port_spif = bnxt_get_phy_port_id(port_id); + bnxt_pmd_get_svif(port_id, false, BNXT_ULP_INTF_TYPE_INVALID); + port_data->port_spif = bnxt_pmd_get_phy_port_id(port_id); port_data->port_parif = - bnxt_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID); - port_data->port_vport = bnxt_get_vport(port_id); + bnxt_pmd_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID); + port_data->port_vport = bnxt_pmd_get_vport(port_id); port_data->port_valid = true; } return 0; diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index a55655a5bd..b8802bdf8e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -201,8 +201,7 @@ bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params) dir = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_DIRECTION); /* read the port id details */ - port_id = ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_INCOMING_IF); + port_id = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_INCOMING_IF); if (ulp_port_db_dev_port_to_ulp_index(params->ulp_ctx, port_id, &ifindex)) { @@ -856,7 +855,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, BNXT_ULP_HDR_BIT_II_VLAN); inner_flag = 1; } else { - BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n"); + BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n"); return BNXT_TF_RC_ERROR; } /* Update the field protocol hdr bitmap */ @@ -1691,15 +1690,34 @@ int32_t ulp_rte_rss_act_handler(const struct rte_flow_action *action_item, struct ulp_rte_parser_params *param) { - const struct rte_flow_action_rss *rss = action_item->conf; + const struct rte_flow_action_rss *rss; + struct ulp_rte_act_prop *ap = ¶m->act_prop; - if (rss) { - /* Update the hdr_bitmap with vxlan */ - ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_RSS); - return BNXT_TF_RC_SUCCESS; + if (action_item == NULL || action_item->conf == NULL) { + BNXT_TF_DBG(ERR, "Parse Err: invalid rss configuration\n"); + return BNXT_TF_RC_ERROR; } - BNXT_TF_DBG(ERR, "Parse Error: RSS arg is invalid\n"); - return BNXT_TF_RC_ERROR; + + rss = action_item->conf; + /* Copy the rss into the specific action properties */ + memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_TYPES], &rss->types, + BNXT_ULP_ACT_PROP_SZ_RSS_TYPES); + memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL], &rss->level, + BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL); + memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN], + &rss->key_len, BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN); + + if (rss->key_len > BNXT_ULP_ACT_PROP_SZ_RSS_KEY) { + BNXT_TF_DBG(ERR, "Parse Err: RSS key too big\n"); + return BNXT_TF_RC_ERROR; + } + memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY], rss->key, + rss->key_len); + + /* set the RSS action header bit */ + ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_RSS); + + return BNXT_TF_RC_SUCCESS; } /* Function to handle the parsing of RTE Flow action vxlan_encap Header. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index bbba10108c..4431f1bbd0 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -24,7 +24,7 @@ #define BNXT_ULP_ENCAP_IPV6_DO 2 #define BNXT_ULP_ENCAP_IPV6_SIZE 24 #define BNXT_ULP_ENCAP_UDP_SIZE 4 -#define BNXT_ULP_INVALID_SVIF_VAL -1U +#define BNXT_ULP_INVALID_SVIF_VAL -1UL #define BNXT_ULP_GET_IPV6_VER(vtcf) \ (((vtcf) & BNXT_ULP_PARSER_IPV6_VER_MASK) >> 28) diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 8cbbe203a8..a38fddafdb 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Sun Mar 21 13:04:51 2021 */ +/* date: Wed Apr 14 09:56:27 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -28,7 +28,7 @@ #define BNXT_ULP_ACT_HID_MASK 2047 #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 4 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 33 -#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 26 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 38 #define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 205 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6 #define BNXT_ULP_COND_GOTO_REJECT 1023 @@ -113,8 +113,7 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000, BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, - BNXT_ULP_HDR_BIT_ANY = 0x0000000000080000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000 + BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000 }; enum bnxt_ulp_accept_opc { @@ -136,25 +135,6 @@ enum bnxt_ulp_byte_order { BNXT_ULP_BYTE_ORDER_LAST = 2 }; -enum bnxt_ulp_cc_upd_opc { - BNXT_ULP_CC_UPD_OPC_NOP = 0, - BNXT_ULP_CC_UPD_OPC_EQ = 1, - BNXT_ULP_CC_UPD_OPC_NE = 2, - BNXT_ULP_CC_UPD_OPC_GT = 3, - BNXT_ULP_CC_UPD_OPC_GE = 4, - BNXT_ULP_CC_UPD_OPC_LT = 5, - BNXT_ULP_CC_UPD_OPC_LE = 6, - BNXT_ULP_CC_UPD_OPC_LAST = 7 -}; - -enum bnxt_ulp_cc_upd_src { - BNXT_ULP_CC_UPD_SRC_REGFILE = 0, - BNXT_ULP_CC_UPD_SRC_GLB_REGFILE = 1, - BNXT_ULP_CC_UPD_SRC_COMP_FIELD = 2, - BNXT_ULP_CC_UPD_SRC_CONST = 3, - BNXT_ULP_CC_UPD_SRC_LAST = 4 -}; - enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_NOT_USED = 0, BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1, @@ -323,6 +303,28 @@ enum bnxt_ulp_field_src { BNXT_ULP_FIELD_SRC_LAST = 16 }; +enum bnxt_ulp_func_opc { + BNXT_ULP_FUNC_OPC_NOP = 0, + BNXT_ULP_FUNC_OPC_EQ = 1, + BNXT_ULP_FUNC_OPC_NE = 2, + BNXT_ULP_FUNC_OPC_GT = 3, + BNXT_ULP_FUNC_OPC_GE = 4, + BNXT_ULP_FUNC_OPC_LT = 5, + BNXT_ULP_FUNC_OPC_LE = 6, + BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7, + BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8, + BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9, + BNXT_ULP_FUNC_OPC_LAST = 10 +}; + +enum bnxt_ulp_func_src { + BNXT_ULP_FUNC_SRC_REGFILE = 0, + BNXT_ULP_FUNC_SRC_GLB_REGFILE = 1, + BNXT_ULP_FUNC_SRC_COMP_FIELD = 2, + BNXT_ULP_FUNC_SRC_CONST = 3, + BNXT_ULP_FUNC_SRC_LAST = 4 +}; + enum bnxt_ulp_generic_tbl_lkup_type { BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX = 0, BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH = 1, @@ -344,17 +346,22 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4, BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 6, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 7, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 8, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 9, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 10, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 11, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 12, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 13, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 14, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 15, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 16, - BNXT_ULP_GLB_RF_IDX_LAST = 17 + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 7, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 8, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 9, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 10, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 11, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 12, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 13, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 14, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 15, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 16, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 17, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 18, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 19, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 20, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 21, + BNXT_ULP_GLB_RF_IDX_LAST = 22 }; enum bnxt_ulp_hdr_type { @@ -465,7 +472,7 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR = 36, BNXT_ULP_RF_IDX_CC = 37, BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 38, - BNXT_ULP_RF_IDX_PHY_PORT_VPORT = 39, + BNXT_ULP_RF_IDX_PHY_PORT = 39, BNXT_ULP_RF_IDX_LAST = 40 }; @@ -492,7 +499,8 @@ enum bnxt_ulp_template_type { enum bnxt_ulp_app_cap { BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001, - BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002 + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002, + BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004 }; enum bnxt_ulp_fdb_resource_flags { @@ -578,7 +586,10 @@ enum bnxt_ulp_act_prop_sz { BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32, BNXT_ULP_ACT_PROP_SZ_JUMP = 4, BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE = 8, - BNXT_ULP_ACT_PROP_SZ_RSS = 64, + BNXT_ULP_ACT_PROP_SZ_RSS_TYPES = 8, + BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL = 4, + BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN = 4, + BNXT_ULP_ACT_PROP_SZ_RSS_KEY = 40, BNXT_ULP_ACT_PROP_SZ_LAST = 4 }; @@ -625,8 +636,11 @@ enum bnxt_ulp_act_prop_idx { BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225, BNXT_ULP_ACT_PROP_IDX_JUMP = 257, BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 261, - BNXT_ULP_ACT_PROP_IDX_RSS = 269, - BNXT_ULP_ACT_PROP_IDX_LAST = 333 + BNXT_ULP_ACT_PROP_IDX_RSS_TYPES = 269, + BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL = 277, + BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN = 281, + BNXT_ULP_ACT_PROP_IDX_RSS_KEY = 285, + BNXT_ULP_ACT_PROP_IDX_LAST = 325 }; enum ulp_wp_sym { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index be7914a5cd..7573cf6074 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Sun Mar 21 13:04:51 2021 */ +/* date: Wed Apr 14 09:56:27 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -77,7 +77,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE", .result_num_entries = 256, .result_num_bytes = 8, - .key_num_bytes = 9, + .key_num_bytes = 10, .num_buckets = 8, .hash_tbl_entries = 1024, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -87,7 +87,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE", .result_num_entries = 256, .result_num_bytes = 8, - .key_num_bytes = 9, + .key_num_bytes = 10, .num_buckets = 8, .hash_tbl_entries = 1024, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE @@ -202,7 +202,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { .ext_flow_db_num_entries = 32768, .mark_db_lfid_entries = 0, .mark_db_gfid_entries = 0, - .flow_count_db_entries = 0, + .flow_count_db_entries = 16384, .fdb_parent_flow_entries = 2, .num_resources_per_flow = 8, .num_phy_ports = 2, @@ -217,7 +217,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { .em_key_align_bytes = 80, .wc_slice_width = 160, .wc_max_slices = 4, - .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f}, + .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f}, .wc_mod_list_max_size = 4, .wc_ctl_size_bits = 32, .dev_tbls = ulp_template_thor_tbls @@ -251,12 +251,14 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .flags = BNXT_ULP_APP_CAP_SHARED_EN + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN }, { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .flags = BNXT_ULP_APP_CAP_SHARED_EN + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN }, { .app_id = 2, @@ -278,7 +280,7 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 512 + .count = 128 }, { .app_id = 1, @@ -294,7 +296,7 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 512 + .count = 128 }, { .app_id = 2, @@ -350,6 +352,30 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { }, { .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -391,6 +417,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, @@ -413,6 +447,22 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + }, + { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -454,6 +504,30 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { }, { .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -495,6 +569,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, @@ -515,6 +597,22 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .resource_type = TF_TBL_TYPE_WC_FKB, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX } }; @@ -818,7 +916,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 64 + .count = 63 }, { .app_id = 0, @@ -962,7 +1060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 64 + .count = 63 }, { .app_id = 0, @@ -1418,7 +1516,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 128 }, { .app_id = 1, @@ -1426,7 +1524,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 + .count = 128 }, { .app_id = 1, @@ -1546,7 +1644,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 128 }, { .app_id = 1, @@ -1554,7 +1652,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 + .count = 128 }, { .app_id = 1, @@ -1698,7 +1796,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 + .count = 256 }, { .app_id = 1, @@ -1826,7 +1924,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 + .count = 256 }, { .app_id = 1, @@ -1946,7 +2044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 128 }, { .app_id = 2, @@ -1954,7 +2052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 + .count = 128 }, { .app_id = 2, @@ -2018,7 +2116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 128 + .count = 64 }, { .app_id = 2, @@ -2074,7 +2172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 128 }, { .app_id = 2, @@ -2082,7 +2180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 + .count = 128 }, { .app_id = 2, @@ -2226,7 +2324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 + .count = 256 }, { .app_id = 2, @@ -2290,7 +2388,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 128 + .count = 256 }, { .app_id = 2, @@ -2354,7 +2452,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 + .count = 256 }, { .app_id = 2, @@ -2515,8 +2613,14 @@ uint32_t ulp_act_prop_map_table[] = { BNXT_ULP_ACT_PROP_SZ_JUMP, [BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE] = BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE, - [BNXT_ULP_ACT_PROP_IDX_RSS] = - BNXT_ULP_ACT_PROP_SZ_RSS, + [BNXT_ULP_ACT_PROP_IDX_RSS_TYPES] = + BNXT_ULP_ACT_PROP_SZ_RSS_TYPES, + [BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL] = + BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL, + [BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN] = + BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN, + [BNXT_ULP_ACT_PROP_IDX_RSS_KEY] = + BNXT_ULP_ACT_PROP_SZ_RSS_KEY, [BNXT_ULP_ACT_PROP_IDX_LAST] = BNXT_ULP_ACT_PROP_SZ_LAST }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c index 73df10a575..a60dfae104 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Feb 8 09:17:37 2021 */ +/* date: Mon Apr 5 11:35:38 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -12,21 +12,188 @@ /* Mapper templates for header act list */ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { + /* act_tid: 1, thor, ingress */ + [1] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR, + .num_tbls = 2, + .start_tbl_idx = 0, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 0, + .cond_nums = 0 } + } }; struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { + { /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 0, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 0, + .result_bit_size = 64, + .result_num_fields = 1 + }, + { /* act_tid: 1, thor, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 1, + .result_bit_size = 128, + .result_num_fields = 17 + } }; struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { + /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + } }; struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { -}; - -struct -bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = { -}; - -struct -bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { + /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 1, thor, table: int_full_act_record.0 */ + { + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd1", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stats_op", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stats_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "use_default", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "cond_copy", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "hit", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c index 5e7ba75c62..45025733fc 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Sun Mar 14 12:41:59 2021 */ +/* date: Mon Apr 5 11:35:38 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -12,34 +12,53 @@ /* Mapper templates for header class list */ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { - /* class_tid: 3, thor, ingress */ - [3] = { + /* class_tid: 1, thor, ingress */ + [1] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 7, + .num_tbls = 47, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, .cond_nums = 0 } }, - /* class_tid: 4, thor, egress */ + /* class_tid: 2, thor, ingress */ + [2] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR, + .num_tbls = 13, + .start_tbl_idx = 47, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 17, + .cond_nums = 0 } + }, + /* class_tid: 3, thor, ingress */ + [3] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR, + .num_tbls = 1, + .start_tbl_idx = 60, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 20, + .cond_nums = 0 } + }, + /* class_tid: 4, thor, ingress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 6, - .start_tbl_idx = 7, + .num_tbls = 9, + .start_tbl_idx = 61, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 1, + .cond_start_idx = 20, .cond_nums = 0 } } }; struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { - { /* class_tid: 3, thor, table: int_full_act_record.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + { /* class_tid: 1, thor, table: port_table.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, @@ -47,512 +66,28726 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 0, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 0, - .result_bit_size = 128, - .result_num_fields = 17 + .key_start_idx = 0, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .ident_start_idx = 0, + .ident_nums = 3 }, - { /* class_tid: 3, thor, table: parif_def_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + { /* class_tid: 1, thor, table: control.check_gre */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_false_goto = 17, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 0, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 17, - .result_bit_size = 32, - .result_num_fields = 1 + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, thor, table: parif_def_err_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + { /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 18, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 1, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 3, + .ident_nums = 0 }, - { /* class_tid: 3, thor, table: control.egr_1 */ + { /* class_tid: 1, thor, table: control.gre_hit */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 0, + .cond_false_goto = 42, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 0, + .cond_start_idx = 1, .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, thor, table: int_full_act_record.egr_vfr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + { /* class_tid: 1, thor, table: l2_cntxt_tcam.gre */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 2, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 0, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 3, + .ident_nums = 1 + }, + { /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 19, - .result_bit_size = 128, - .result_num_fields = 17, - .encap_num_fields = 0 + .key_start_idx = 23, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 6, + .result_bit_size = 62, + .result_num_fields = 4 }, - { /* class_tid: 3, thor, table: parif_def_arec_ptr.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, + { /* class_tid: 1, thor, table: fkb_select.gre */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 36, - .result_bit_size = 32, - .result_num_fields = 1 + .result_start_idx = 10, + .result_bit_size = 106, + .result_num_fields = 106 }, - { /* class_tid: 3, thor, table: parif_def_err_arec_ptr.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, + { /* class_tid: 1, thor, table: profile_tcam.gre */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 37, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 24, + .blob_key_bit_size = 94, + .key_bit_size = 94, + .key_num_fields = 43, + .result_start_idx = 116, + .result_bit_size = 33, + .result_num_fields = 8, + .ident_start_idx = 4, + .ident_nums = 0 }, - { /* class_tid: 4, thor, table: int_full_act_record.loopback */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, + { /* class_tid: 1, thor, table: wm.gre */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 2, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 2, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 67, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 124, + .result_bit_size = 38, + .result_num_fields = 5 + }, + { /* class_tid: 1, thor, table: wm.gre_low */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 3, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 38, - .result_bit_size = 128, - .result_num_fields = 17, - .encap_num_fields = 0 + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 181, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 129, + .result_bit_size = 38, + .result_num_fields = 5 }, - { /* class_tid: 4, thor, table: parif_def_arec_ptr.vf_egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, + { /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 3, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 55, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 295, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .ident_start_idx = 4, + .ident_nums = 0 }, - { /* class_tid: 4, thor, table: parif_def_err_arec_ptr.vf_egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, + { /* class_tid: 1, thor, table: control.gre_frag_mac_hit */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 4, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 56, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 300, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 134, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 4, + .ident_nums = 0 }, - { /* class_tid: 4, thor, table: int_full_act_record.vf_ing */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + { /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 4, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 57, - .result_bit_size = 128, - .result_num_fields = 17, - .encap_num_fields = 0 + .key_start_idx = 321, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .result_start_idx = 140, + .result_bit_size = 62, + .result_num_fields = 4 }, - { /* class_tid: 4, thor, table: vtag_encap_record.vfr_egr0 */ + { /* class_tid: 1, thor, table: fkb_select.gre_frag */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_TX, + .resource_type = TF_TBL_TYPE_WC_FKB, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 4, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 74, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 11 + .result_start_idx = 144, + .result_bit_size = 106, + .result_num_fields = 106 }, - { /* class_tid: 4, thor, table: int_full_act_record.vfr_egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, + { /* class_tid: 1, thor, table: profile_tcam.gre_frag */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 4, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 85, - .result_bit_size = 128, - .result_num_fields = 17 - } -}; - -struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_execute: class_tid: 3, control.egr_1 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE - } -}; - -struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { - /* class_tid: 3, thor, table: int_full_act_record.ing_0 */ - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .key_start_idx = 326, + .blob_key_bit_size = 94, + .key_bit_size = 94, + .key_num_fields = 43, + .result_start_idx = 250, + .result_bit_size = 33, + .result_num_fields = 8, + .ident_start_idx = 4, + .ident_nums = 0 }, - { - .description = "encap_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + { /* class_tid: 1, thor, table: wm.gre_frag */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 29, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 4, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 369, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 258, + .result_bit_size = 38, + .result_num_fields = 5 }, - { - .description = "mod_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + { /* class_tid: 1, thor, table: wm.gre_frag_low */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 28, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 5, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 483, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 263, + .result_bit_size = 38, + .result_num_fields = 5 }, - { - .description = "rsvd1", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + { /* class_tid: 1, thor, table: mac_addr_cache.non_gre_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 5, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 597, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .ident_start_idx = 4, + .ident_nums = 0 }, - { - .description = "rsvd0", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + { /* class_tid: 1, thor, table: control.non_gre_mac */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 5, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { - .description = "decap_func", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + { /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 6, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 602, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 268, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 4, + .ident_nums = 0 }, - { - .description = "meter", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + { /* class_tid: 1, thor, table: mac_addr_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 6, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 623, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .result_start_idx = 274, + .result_bit_size = 62, + .result_num_fields = 4 }, - { - .description = "stats_op", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + { /* class_tid: 1, thor, table: control.icmpv4_test */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 8, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 6, + .cond_nums = 2 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { - .description = "stats_ptr", + { /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 8, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 628, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 4, + .ident_nums = 0 + }, + { /* class_tid: 1, thor, table: control.icmpv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 8, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 1, thor, table: fkb_select.icmpv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 9, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 278, + .result_bit_size = 106, + .result_num_fields = 106 + }, + { /* class_tid: 1, thor, table: profile_tcam.icmpv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 9, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 631, + .blob_key_bit_size = 94, + .key_bit_size = 94, + .key_num_fields = 43, + .result_start_idx = 384, + .result_bit_size = 33, + .result_num_fields = 8, + .ident_start_idx = 4, + .ident_nums = 1 + }, + { /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 9, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 674, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 392, + .result_bit_size = 82, + .result_num_fields = 7 + }, + { /* class_tid: 1, thor, table: wm.icmpv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 17, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 9, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 677, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 399, + .result_bit_size = 38, + .result_num_fields = 5 + }, + { /* class_tid: 1, thor, table: wm.icmpv4_low */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 16, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 10, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 791, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 404, + .result_bit_size = 38, + .result_num_fields = 5 + }, + { /* class_tid: 1, thor, table: control.icmpv6_test */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 8, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 10, + .cond_nums = 2 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 12, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 905, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 5, + .ident_nums = 0 + }, + { /* class_tid: 1, thor, table: control.icmpv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 12, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 1, thor, table: fkb_select.icmpv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 409, + .result_bit_size = 106, + .result_num_fields = 106 + }, + { /* class_tid: 1, thor, table: profile_tcam.icmpv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 908, + .blob_key_bit_size = 94, + .key_bit_size = 94, + .key_num_fields = 43, + .result_start_idx = 515, + .result_bit_size = 33, + .result_num_fields = 8, + .ident_start_idx = 5, + .ident_nums = 1 + }, + { /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 951, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 523, + .result_bit_size = 82, + .result_num_fields = 7 + }, + { /* class_tid: 1, thor, table: wm.icmpv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 9, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 13, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 954, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 530, + .result_bit_size = 38, + .result_num_fields = 5 + }, + { /* class_tid: 1, thor, table: wm.icmpv6_low */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 8, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 14, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 1068, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 535, + .result_bit_size = 38, + .result_num_fields = 5 + }, + { /* class_tid: 1, thor, table: profile_tcam_cache.l3_l4_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 14, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1182, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 6, + .ident_nums = 0 + }, + { /* class_tid: 1, thor, table: control.l3_l4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 14, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 1, thor, table: fkb_select.l3_l4_wm */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 540, + .result_bit_size = 106, + .result_num_fields = 106 + }, + { /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1185, + .blob_key_bit_size = 94, + .key_bit_size = 94, + .key_num_fields = 43, + .result_start_idx = 646, + .result_bit_size = 33, + .result_num_fields = 8, + .ident_start_idx = 6, + .ident_nums = 0 + }, + { /* class_tid: 1, thor, table: profile_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1228, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 654, + .result_bit_size = 82, + .result_num_fields = 7 + }, + { /* class_tid: 1, thor, table: wm.l4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 2, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 1231, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 661, + .result_bit_size = 38, + .result_num_fields = 5 + }, + { /* class_tid: 1, thor, table: wm.l4_low */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 1345, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 666, + .result_bit_size = 38, + .result_num_fields = 5 + }, + { /* class_tid: 1, thor, table: control.check_rss_action */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 16, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 1, thor, table: control.rss_config */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_RSS_CONFIG, + .func_dst_opr = BNXT_ULP_RF_IDX_CC }, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 2, thor, table: port_table.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1459, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .ident_start_idx = 6, + .ident_nums = 3 + }, + { /* class_tid: 2, thor, table: mac_addr_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1460, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .ident_start_idx = 9, + .ident_nums = 0 + }, + { /* class_tid: 2, thor, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 17, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 2, thor, table: l2_cntxt_tcam.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 18, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1465, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 671, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 9, + .ident_nums = 1 + }, + { /* class_tid: 2, thor, table: mac_addr_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 18, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1486, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .result_start_idx = 677, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 2, thor, table: profile_tcam_cache.l3_l4_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 18, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1491, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 10, + .ident_nums = 0 + }, + { /* class_tid: 2, thor, table: control.l3_l4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 18, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 2, thor, table: fkb_select.l3_l4_wm */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 19, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 681, + .result_bit_size = 106, + .result_num_fields = 106 + }, + { /* class_tid: 2, thor, table: profile_tcam.l3_l4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 19, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1494, + .blob_key_bit_size = 94, + .key_bit_size = 94, + .key_num_fields = 43, + .result_start_idx = 787, + .result_bit_size = 33, + .result_num_fields = 8, + .ident_start_idx = 10, + .ident_nums = 0 + }, + { /* class_tid: 2, thor, table: profile_tcam_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 19, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1537, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 795, + .result_bit_size = 82, + .result_num_fields = 7 + }, + { /* class_tid: 2, thor, table: wm.l4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 19, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_BE, + .key_start_idx = 1540, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 114, + .result_start_idx = 802, + .result_bit_size = 38, + .result_num_fields = 5 + }, + { /* class_tid: 2, thor, table: control.check_rss_action */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 19, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 2, thor, table: control.rss_config */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 20, + .cond_nums = 0 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_RSS_CONFIG, + .func_dst_opr = BNXT_ULP_RF_IDX_CC }, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 3, thor, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 20, + .cond_nums = 0 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 4, thor, table: control.get_parent_mac_addr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 20, + .cond_nums = 0 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR, + .func_dst_opr = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC }, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 4, thor, table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 20, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr1 = BNXT_ULP_CF_IDX_PHY_PORT_VPORT, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 1, + .func_dst_opr = BNXT_ULP_RF_IDX_CC }, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 4, thor, table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 21, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 807, + .result_bit_size = 128, + .result_num_fields = 17 + }, + { /* class_tid: 4, thor, table: port_table.wr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 3, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 21, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1654, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .result_start_idx = 824, + .result_bit_size = 152, + .result_num_fields = 5 + }, + { /* class_tid: 4, thor, table: int_full_act_record.1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 21, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 829, + .result_bit_size = 128, + .result_num_fields = 17 + }, + { /* class_tid: 4, thor, table: port_table.wr_1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 21, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1655, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .result_start_idx = 846, + .result_bit_size = 152, + .result_num_fields = 5 + }, + { /* class_tid: 4, thor, table: port_table.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 21, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1656, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .ident_start_idx = 10, + .ident_nums = 1 + }, + { /* class_tid: 4, thor, table: parif_def_arec_ptr.ing_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 21, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 851, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 4, thor, table: parif_def_err_arec_ptr.ing_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 21, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 852, + .result_bit_size = 32, + .result_num_fields = 1 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { + /* cond_execute: class_tid: 1, control.check_gre */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GRE + }, + /* cond_execute: class_tid: 1, control.gre_hit */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, wm.gre */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG + }, + /* cond_execute: class_tid: 1, control.gre_frag_mac_hit */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, wm.gre_frag */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG + }, + /* cond_execute: class_tid: 1, control.non_gre_mac */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, control.icmpv4_test */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ICMP + }, + /* cond_execute: class_tid: 1, control.icmpv4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, wm.icmpv4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG + }, + /* cond_execute: class_tid: 1, control.icmpv6_test */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ICMP + }, + /* cond_execute: class_tid: 1, control.icmpv6 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, wm.icmpv6 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG + }, + /* cond_execute: class_tid: 1, control.l3_l4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, wm.l4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG + }, + /* cond_execute: class_tid: 1, control.check_rss_action */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_RSS + }, + /* cond_execute: class_tid: 2, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, control.l3_l4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, control.check_rss_action */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_RSS + }, + /* cond_execute: class_tid: 4, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_CC + } +}; + +struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { + /* class_tid: 1, thor, table: port_table.rd */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + /* class_tid: 1, thor, table: l2_cntxt_tcam.gre */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_GRE} + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + /* class_tid: 1, thor, table: profile_tcam.gre */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, thor, table: wm.gre */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 47} + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: wm.gre_low */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 47} + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + /* class_tid: 1, thor, table: profile_tcam.gre_frag */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 16} + }, + .field_info_spec = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 16} + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, thor, table: wm.gre_frag */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 47} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: wm.gre_frag_low */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 47} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: mac_addr_cache.non_gre_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, thor, table: mac_addr_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, thor, table: profile_tcam.icmpv4 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L4_HDR_TYPE_ICMP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L4_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, thor, table: wm.icmpv4 */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + 58} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: wm.icmpv4_low */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + 58} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, thor, table: profile_tcam.icmpv6 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L4_HDR_TYPE_ICMP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L4_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L3_HDR_TYPE_IPV6} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, thor, table: wm.icmpv6 */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + 58} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: wm.icmpv6_low */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + 58} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: profile_tcam_cache.l3_l4_rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L4_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR_SYM_L3_HDR_TYPE_IPV6} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, thor, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 1, thor, table: wm.l4 */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_IP_PROTO_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR_SYM_IP_PROTO_UDP} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 1, thor, table: wm.l4_low */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_IP_PROTO_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR_SYM_IP_PROTO_UDP} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 2, thor, table: port_table.rd */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 2, thor, table: mac_addr_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + /* class_tid: 2, thor, table: l2_cntxt_tcam.0 */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 2, thor, table: mac_addr_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_RF, + .field_opr3 = { + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + } + }, + /* class_tid: 2, thor, table: profile_tcam_cache.l3_l4_rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 2, thor, table: profile_tcam.l3_l4 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L4_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR_SYM_L3_HDR_TYPE_IPV6} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L3_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L2_HDR_VALID_YES} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 2, thor, table: profile_tcam_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 2, thor, table: wm.l4 */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_IP_PROTO_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR_SYM_IP_PROTO_UDP} + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + { + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } + }, + /* class_tid: 4, thor, table: port_table.wr_0 */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 4, thor, table: port_table.wr_1 */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 4, thor, table: port_table.rd */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { + /* class_tid: 1, thor, table: l2_cntxt_tcam.gre */ + { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 & 0xff} + }, + { + .description = "ctxt_meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "def_ctxt_data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "ctxt_opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: fkb_select.gre */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: profile_tcam.gre */ + { + .description = "wc_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 & 0xff} + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: wm.gre */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: wm.gre_low */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "ctxt_meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "def_ctxt_data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "ctxt_opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: fkb_select.gre_frag */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: profile_tcam.gre_frag */ + { + .description = "wc_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: wm.gre_frag */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: wm.gre_frag_low */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "ctxt_meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "def_ctxt_data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "ctxt_opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + /* class_tid: 1, thor, table: mac_addr_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: fkb_select.icmpv4 */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: profile_tcam.icmpv4 */ + { + .description = "wc_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_sig_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: wm.icmpv4 */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: wm.icmpv4_low */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: fkb_select.icmpv6 */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: profile_tcam.icmpv6 */ + { + .description = "wc_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_sig_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: wm.icmpv6 */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: wm.icmpv6_low */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: fkb_select.l3_l4_wm */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ + { + .description = "wc_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: profile_tcam_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_sig_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, thor, table: wm.l4 */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 1, thor, table: wm.l4_low */ + { + .description = "ctxt_data", + .field_bit_size = 14, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "data", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 2, thor, table: l2_cntxt_tcam.0 */ + { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "ctxt_meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "def_ctxt_data", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "ctxt_opcode", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, + BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + /* class_tid: 2, thor, table: mac_addr_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, thor, table: fkb_select.l3_l4_wm */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_selcmp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vnic_or_vport", - .field_bit_size = 11, + .description = "l4_win.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "use_default", + .description = "l4_pa.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "mirror", - .field_bit_size = 4, + .description = "l4_opt.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "cond_copy", + .description = "l4_tcpts.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vlan_del_rpt", - .field_bit_size = 2, + .description = "l4_tsval.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drop", + .description = "l4_txecr.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "hit", + .description = "l4_err.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, thor, table: profile_tcam.l3_l4 */ { - .description = "type", - .field_bit_size = 3, + .description = "wc_key_id", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} }, - /* class_tid: 3, thor, table: parif_def_arec_ptr.ing_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} }, - /* class_tid: 3, thor, table: parif_def_err_arec_ptr.ing_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "wc_search_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + 1} }, - /* class_tid: 3, thor, table: int_full_act_record.egr_vfr */ { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "em_key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "encap_ptr", - .field_bit_size = 16, + .description = "em_key_id", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "mod_rec_ptr", - .field_bit_size = 16, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rsvd1", - .field_bit_size = 16, + .description = "em_search_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rsvd0", - .field_bit_size = 8, + .description = "pl_byp_lkup_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, thor, table: profile_tcam_cache.wr */ { - .description = "decap_func", - .field_bit_size = 5, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "meter", + .description = "profile_tcam_index", .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "stats_op", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "stats_ptr", - .field_bit_size = 16, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vnic_or_vport", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} - }, - { - .description = "use_default", - .field_bit_size = 1, + .description = "em_key_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "mirror", - .field_bit_size = 4, + .description = "wc_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "cond_copy", - .field_bit_size = 1, + .description = "wc_key_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "vlan_del_rpt", - .field_bit_size = 2, + .description = "flow_sig_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, thor, table: wm.l4 */ { - .description = "drop", - .field_bit_size = 1, + .description = "ctxt_data", + .field_bit_size = 14, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "hit", - .field_bit_size = 1, + .description = "meta_prof", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "type", + .description = "opcode", .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, thor, table: parif_def_arec_ptr.egr_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "data", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, thor, table: parif_def_err_arec_ptr.egr_0 */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + 1} }, - /* class_tid: 4, thor, table: int_full_act_record.loopback */ + /* class_tid: 4, thor, table: int_full_act_record.0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -611,10 +28844,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .description = "vnic_or_vport", .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, .field_opr1 = { - (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_THOR_SYM_LOOPBACK_PORT & 0xff} + (BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC & 0xff} }, { .description = "use_default", @@ -660,27 +28893,44 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 4, thor, table: parif_def_arec_ptr.vf_egr */ + /* class_tid: 4, thor, table: port_table.wr_0 */ { - .description = "act_rec_ptr", + .description = "rid", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.parent.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} }, - /* class_tid: 4, thor, table: parif_def_err_arec_ptr.vf_egr */ { - .description = "act_rec_ptr", - .field_bit_size = 32, + .description = "phy_port", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_arec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 & 0xff} }, - /* class_tid: 4, thor, table: int_full_act_record.vf_ing */ + /* class_tid: 4, thor, table: int_full_act_record.1 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -739,10 +28989,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .description = "vnic_or_vport", .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + (BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC & 0xff} }, { .description = "use_default", @@ -788,202 +29038,148 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 4, thor, table: vtag_encap_record.vfr_egr0 */ - { - .description = "ecv_tun_type", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "ecv_l4_type", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, + /* class_tid: 4, thor, table: port_table.wr_1 */ { - .description = "ecv_l3_type", - .field_bit_size = 3, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_l2_en", - .field_bit_size = 1, + .description = "drv_func.mac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ecv_vtag_type", - .field_bit_size = 4, + .description = "drv_func.parent.mac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} - }, - { - .description = "rsrvd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} }, { - .description = "ecv_valid", - .field_bit_size = 1, + .description = "phy_port", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, { - .description = "vtag_tpid", + .description = "default_arec_ptr", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 0x81, - 0x00} - }, - { - .description = "vtag_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - }, - { - .description = "vtag_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 & 0xff} }, + /* class_tid: 4, thor, table: parif_def_arec_ptr.ing_0 */ { - .description = "vtag_pcp", - .field_bit_size = 3, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} - }, - /* class_tid: 4, thor, table: int_full_act_record.vfr_egr0 */ - { - .description = "sp_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, + /* class_tid: 4, thor, table: parif_def_err_arec_ptr.ing_0 */ { - .description = "encap_ptr", - .field_bit_size = 16, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} - }, - { - .description = "mod_rec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rsvd1", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rsvd0", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "decap_func", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + } +}; + +struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { + /* class_tid: 1, thor, table: port_table.rd */ { - .description = "meter", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "default_arec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .ident_bit_size = 16, + .ident_bit_pos = 136 }, { - .description = "stats_op", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "drv_func.parent.mac", + .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC, + .ident_bit_size = 48, + .ident_bit_pos = 80 }, { - .description = "stats_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "phy_port", + .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT, + .ident_bit_size = 8, + .ident_bit_pos = 128 }, + /* class_tid: 1, thor, table: l2_cntxt_tcam.gre */ { - .description = "vnic_or_vport", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, - ULP_THOR_SYM_LOOPBACK_PORT & 0xff} + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 29 }, + /* class_tid: 1, thor, table: profile_tcam.icmpv4 */ { - .description = "use_default", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "em_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 23 }, + /* class_tid: 1, thor, table: profile_tcam.icmpv6 */ { - .description = "mirror", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "em_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 23 }, + /* class_tid: 2, thor, table: port_table.rd */ { - .description = "cond_copy", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "default_arec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .ident_bit_size = 16, + .ident_bit_pos = 136 }, { - .description = "vlan_del_rpt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "drv_func.parent.mac", + .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC, + .ident_bit_size = 48, + .ident_bit_pos = 80 }, { - .description = "drop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "phy_port", + .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT, + .ident_bit_size = 8, + .ident_bit_pos = 128 }, + /* class_tid: 2, thor, table: l2_cntxt_tcam.0 */ { - .description = "hit", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 29 }, + /* class_tid: 4, thor, table: port_table.rd */ { - .description = "type", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .description = "default_arec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .ident_bit_size = 16, + .ident_bit_pos = 136 } }; -struct -bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { -}; - -struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { -}; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c index ca385b66f9..fa3c3507b6 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Sun Mar 21 13:04:51 2021 */ +/* date: Wed Apr 14 09:56:27 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -94,8 +94,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 1, - .blob_key_bit_size = 70, - .key_bit_size = 70, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 5, .ident_start_idx = 1, .ident_nums = 1 @@ -156,8 +156,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 19, - .blob_key_bit_size = 70, - .key_bit_size = 70, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 5, .result_start_idx = 13, .result_bit_size = 62, @@ -209,13 +209,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_start_idx = 4, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .cc_upd_info = { - .cc_opc = BNXT_ULP_CC_UPD_OPC_EQ, - .cc_src1 = BNXT_ULP_CC_UPD_SRC_REGFILE, - .cc_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .cc_src2 = BNXT_ULP_CC_UPD_SRC_REGFILE, - .cc_opr2 = BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID, - .cc_dst_opr = BNXT_ULP_RF_IDX_CC }, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC }, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ @@ -320,7 +320,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_bit_size = 14, .key_num_fields = 3, .result_start_idx = 68, - .result_bit_size = 74, + .result_bit_size = 90, .result_num_fields = 5 }, { /* class_tid: 1, wh_plus, table: em.ipv4 */ @@ -493,8 +493,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 224, - .blob_key_bit_size = 70, - .key_bit_size = 70, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 5, .ident_start_idx = 10, .ident_nums = 1 @@ -555,8 +555,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 242, - .blob_key_bit_size = 70, - .key_bit_size = 70, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 5, .result_start_idx = 140, .result_bit_size = 62, @@ -607,13 +607,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .cc_upd_info = { - .cc_opc = BNXT_ULP_CC_UPD_OPC_EQ, - .cc_src1 = BNXT_ULP_CC_UPD_SRC_REGFILE, - .cc_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .cc_src2 = BNXT_ULP_CC_UPD_SRC_COMP_FIELD, - .cc_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, - .cc_dst_opr = BNXT_ULP_RF_IDX_CC }, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC }, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, { /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ @@ -690,7 +690,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_bit_size = 14, .key_num_fields = 3, .result_start_idx = 178, - .result_bit_size = 74, + .result_bit_size = 90, .result_num_fields = 5 }, { /* class_tid: 2, wh_plus, table: em.ipv4 */ @@ -1883,7 +1883,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { { .field_info_mask = { .description = "tun_hdr", - .field_bit_size = 1, + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -1891,7 +1891,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, .field_info_spec = { .description = "tun_hdr", - .field_bit_size = 1, + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2239,7 +2239,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { { .field_info_mask = { .description = "tun_hdr", - .field_bit_size = 1, + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -2247,7 +2247,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, .field_info_spec = { .description = "tun_hdr", - .field_bit_size = 1, + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5714,7 +5714,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { { .field_info_mask = { .description = "tun_hdr", - .field_bit_size = 1, + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -5722,7 +5722,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, .field_info_spec = { .description = "tun_hdr", - .field_bit_size = 1, + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6070,7 +6070,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { { .field_info_mask = { .description = "tun_hdr", - .field_bit_size = 1, + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -6078,7 +6078,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, .field_info_spec = { .description = "tun_hdr", - .field_bit_size = 1, + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { @@ -10076,7 +10076,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -10852,7 +10852,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }, { .description = "flow_sig_id", - .field_bit_size = 16, + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -11711,7 +11711,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }, { .description = "flow_sig_id", - .field_bit_size = 16, + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { @@ -14176,7 +14176,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 16, + .ident_bit_size = 32, .ident_bit_pos = 58 }, { @@ -14245,7 +14245,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 16, + .ident_bit_size = 32, .ident_bit_pos = 58 }, { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 2d03ea4fdb..0cbac66237 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -70,7 +70,7 @@ struct ulp_rte_parser_params { struct ulp_rte_field_bitmap fld_bitmap; struct ulp_rte_field_bitmap fld_s_bitmap; struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX]; - uint32_t comp_fld[BNXT_ULP_CF_IDX_LAST]; + uint64_t comp_fld[BNXT_ULP_CF_IDX_LAST]; uint32_t field_idx; struct ulp_rte_act_bitmap act_bitmap; struct ulp_rte_act_prop act_prop; @@ -176,13 +176,13 @@ struct bnxt_ulp_mapper_cond_list_info { int32_t cond_false_goto; }; -struct bnxt_ulp_mapper_cc_upd_info { - enum bnxt_ulp_cc_upd_opc cc_opc; - enum bnxt_ulp_cc_upd_src cc_src1; - enum bnxt_ulp_cc_upd_src cc_src2; - uint16_t cc_opr1; - uint16_t cc_opr2; - uint16_t cc_dst_opr; +struct bnxt_ulp_mapper_func_info { + enum bnxt_ulp_func_opc func_opc; + enum bnxt_ulp_func_src func_src1; + enum bnxt_ulp_func_src func_src2; + uint16_t func_opr1; + uint16_t func_opr2; + uint16_t func_dst_opr; }; struct bnxt_ulp_template_device_tbls { @@ -244,7 +244,7 @@ struct bnxt_ulp_mapper_tbl_info { uint32_t resource_type; /* TF_ enum type */ enum bnxt_ulp_resource_sub_type resource_sub_type; struct bnxt_ulp_mapper_cond_list_info execute_info; - struct bnxt_ulp_mapper_cc_upd_info cc_upd_info; + struct bnxt_ulp_mapper_func_info func_info; enum bnxt_ulp_cond_opc cond_opcode; uint32_t cond_operand; uint8_t direction; @@ -252,7 +252,7 @@ struct bnxt_ulp_mapper_tbl_info { uint32_t pri_operand; enum bnxt_ulp_byte_order byte_order; - /* conflict resoution opcode */ + /* conflict resolution opcode */ enum bnxt_ulp_accept_opc accept_opcode; enum bnxt_ulp_critical_resource critical_resource; diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index 1649e157f2..bafb539c8d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile, * data [in] The value is written into this variable. It is going to be in the * same byte order as it was written. * - * size [in] The size in bytes of the value beingritten into this + * size [in] The size in bytes of the value being written into this * variable. * * returns 0 on success @@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob, datalen, data); if (!rc) { - BNXT_TF_DBG(ERR, "Failed ro write blob\n"); + BNXT_TF_DBG(ERR, "Failed to write blob\n"); return 0; } blob->write_idx += datalen; @@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset, datalen, data); if (!rc) { - BNXT_TF_DBG(ERR, "Failed ro write blob\n"); + BNXT_TF_DBG(ERR, "Failed to write blob\n"); return 0; } /* copy the previously stored data */ @@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob, * * data [in] 32-bit value to be added to the blob. * - * datalen [in] The number of bits to be added ot the blob. + * datalen [in] The number of bits to be added to the blob. * * The offset of the data is updated after each push of data. * NULL returned on error, pointer pushed value otherwise. diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h index 209c8fa6a4..e1b0e773f3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.h +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h @@ -64,10 +64,10 @@ /* Macros to read the computed fields */ #define ULP_COMP_FLD_IDX_RD(params, idx) \ - rte_be_to_cpu_32((params)->comp_fld[(idx)]) + rte_be_to_cpu_64((params)->comp_fld[(idx)]) #define ULP_COMP_FLD_IDX_WR(params, idx, val) \ - ((params)->comp_fld[(idx)] = rte_cpu_to_be_32((val))) + ((params)->comp_fld[(idx)] = rte_cpu_to_be_64((uint64_t)(val))) /* * Making the blob statically sized to 128 bytes for now. * The blob must be initialized with ulp_blob_init prior to using. From patchwork Sun May 30 08:59:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93597 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A2689A0524; Sun, 30 May 2021 11:08:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 91FEC411FD; Sun, 30 May 2021 11:02:12 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 326CB41124 for ; Sun, 30 May 2021 11:02:10 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id EEABC7DAF; Sun, 30 May 2021 02:02:08 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com EEABC7DAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365329; bh=ra+QzUdcbwSyOcUKmh+NVfBarHxbCKWjV7NWHx0r7/s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ojkjUee51isyfbboEJY2YG8H/Xw00vOSFB8NlEHhkuYHp6JRLol9xSWMWV05geb12 Spd6foZSGf+i19IsxlCZVFyAysQuReMOZj0Z3c/I9hzPAMyF5o0Zl6mR0rmtqv9sXt KT8HroatFYguVQtO0gB/7AUvbxx4Zr1tharxfvjQ= From: Venkat Duvvuru To: dev@dpdk.org Cc: Venkat Duvvuru Date: Sun, 30 May 2021 14:29:28 +0530 Message-Id: <20210530085929.29695-58-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 57/58] net/bnxt: reorganize ULP template directory structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reorganize ulp template directory structure and add meson.build file to the respective directories. Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher --- .../bnxt/tf_ulp/generic_templates/meson.build | 13 + .../ulp_template_db_act.c | 0 .../ulp_template_db_class.c | 0 .../ulp_template_db_enum.h | 0 .../ulp_template_db_field.h | 0 .../ulp_template_db_tbl.c | 0 .../ulp_template_db_tbl.h | 0 .../ulp_template_db_thor_act.c | 0 .../ulp_template_db_thor_class.c | 0 .../ulp_template_db_wh_plus_act.c | 0 .../ulp_template_db_wh_plus_class.c | 0 drivers/net/bnxt/tf_ulp/meson.build | 11 +- drivers/net/bnxt/tf_ulp/ulp_template_db.c | 4622 ----------------- drivers/net/bnxt/tf_ulp/ulp_template_db.h | 614 --- .../net/bnxt/tf_ulp/ulp_template_field_db.h | 224 - 15 files changed, 16 insertions(+), 5468 deletions(-) create mode 100644 drivers/net/bnxt/tf_ulp/generic_templates/meson.build rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_act.c (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_class.c (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_enum.h (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_field.h (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_tbl.c (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_tbl.h (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_thor_act.c (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_thor_class.c (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_wh_plus_act.c (100%) rename drivers/net/bnxt/tf_ulp/{ => generic_templates}/ulp_template_db_wh_plus_class.c (100%) delete mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db.c delete mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db.h delete mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_field_db.h diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build new file mode 100644 index 0000000000..e80dc3fb3f --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Intel Corporation +# Copyright(c) 2020 Broadcom + +includes += include_directories('.') +sources += files( + 'ulp_template_db_class.c', + 'ulp_template_db_act.c', + 'ulp_template_db_tbl.c', + 'ulp_template_db_wh_plus_act.c', + 'ulp_template_db_wh_plus_class.c', + 'ulp_template_db_thor_act.c', + 'ulp_template_db_thor_class.c') diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_act.c rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_class.c rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_field.h rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.h similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.h diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c similarity index 100% rename from drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c rename to drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build index 456d8ca7b6..25de7f3f3f 100644 --- a/drivers/net/bnxt/tf_ulp/meson.build +++ b/drivers/net/bnxt/tf_ulp/meson.build @@ -10,9 +10,6 @@ sources += files( 'bnxt_ulp.c', 'ulp_mark_mgr.c', 'ulp_flow_db.c', - 'ulp_template_db_tbl.c', - 'ulp_template_db_class.c', - 'ulp_template_db_act.c', 'ulp_utils.c', 'ulp_mapper.c', 'ulp_matcher.c', @@ -26,8 +23,6 @@ sources += files( 'ulp_gen_tbl.c', 'ulp_gen_hash.c', 'ulp_ha_mgr.c', - 'ulp_rte_handler_tbl.c', - 'ulp_template_db_wh_plus_act.c', - 'ulp_template_db_wh_plus_class.c', - 'ulp_template_db_thor_act.c', - 'ulp_template_db_thor_class.c') + 'ulp_rte_handler_tbl.c') + +subdir('generic_templates') diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c deleted file mode 100644 index c7277938ef..0000000000 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c +++ /dev/null @@ -1,4622 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom - * All rights reserved. - */ - - -#include "ulp_template_db.h" -#include "ulp_template_field_db.h" -#include "ulp_template_struct.h" -#include "ulp_rte_parser.h" - -uint32_t ulp_act_prop_map_table[] = { - [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE, - [BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM] = - BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM, - [BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] = - BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM, - [BNXT_ULP_ACT_PROP_IDX_PORT_ID] = - BNXT_ULP_ACT_PROP_SZ_PORT_ID, - [BNXT_ULP_ACT_PROP_IDX_VNIC] = - BNXT_ULP_ACT_PROP_SZ_VNIC, - [BNXT_ULP_ACT_PROP_IDX_VPORT] = - BNXT_ULP_ACT_PROP_SZ_VPORT, - [BNXT_ULP_ACT_PROP_IDX_MARK] = - BNXT_ULP_ACT_PROP_SZ_MARK, - [BNXT_ULP_ACT_PROP_IDX_COUNT] = - BNXT_ULP_ACT_PROP_SZ_COUNT, - [BNXT_ULP_ACT_PROP_IDX_METER] = - BNXT_ULP_ACT_PROP_SZ_METER, - [BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC] = - BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC, - [BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST] = - BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN, - [BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP] = - BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP, - [BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID] = - BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID, - [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC] = - BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC, - [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST] = - BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST, - [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC] = - BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC, - [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST] = - BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST, - [BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC] = - BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC, - [BNXT_ULP_ACT_PROP_IDX_SET_TP_DST] = - BNXT_ULP_ACT_PROP_SZ_SET_TP_DST, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6, - [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7] = - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP, - [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] = - BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN, - [BNXT_ULP_ACT_PROP_IDX_LAST] = - BNXT_ULP_ACT_PROP_SZ_LAST -}; - -struct bnxt_ulp_rte_act_info ulp_act_info[] = { - [RTE_FLOW_ACTION_TYPE_END] = { - .act_type = BNXT_ULP_ACT_TYPE_END, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_VOID] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_void_act_handler - }, - [RTE_FLOW_ACTION_TYPE_PASSTHRU] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_JUMP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_MARK] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_mark_act_handler - }, - [RTE_FLOW_ACTION_TYPE_FLAG] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_QUEUE] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_DROP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_drop_act_handler - }, - [RTE_FLOW_ACTION_TYPE_COUNT] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_count_act_handler - }, - [RTE_FLOW_ACTION_TYPE_RSS] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_rss_act_handler - }, - [RTE_FLOW_ACTION_TYPE_PF] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_pf_act_handler - }, - [RTE_FLOW_ACTION_TYPE_VF] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vf_act_handler - }, - [RTE_FLOW_ACTION_TYPE_PHY_PORT] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_phy_port_act_handler - }, - [RTE_FLOW_ACTION_TYPE_PORT_ID] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_port_id_act_handler - }, - [RTE_FLOW_ACTION_TYPE_METER] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SECURITY] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vxlan_encap_act_handler - }, - [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vxlan_decap_act_handler - }, - [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_RAW_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_TP_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_MAC_SWAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_DEC_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - }, - [RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL - } -}; - -struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = { -}; - -struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { - [BNXT_ULP_DEVICE_ID_WH_PLUS] = { - .global_fid_enable = BNXT_ULP_SYM_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .encap_byte_swap = 1, - .lfid_entries = 16384, - .lfid_entry_size = 4, - .gfid_entries = 65536, - .gfid_entry_size = 4, - .num_flows = 32768, - .num_resources_per_flow = 8 - } -}; - -struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { - [0] = { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_RX - }, - [1] = { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX - } -}; - -struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { - [RTE_FLOW_ITEM_TYPE_END] = { - .hdr_type = BNXT_ULP_HDR_TYPE_END, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_VOID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_void_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_INVERT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ANY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_PF] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_pf_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_VF] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vf_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_PHY_PORT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_phy_port_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_PORT_ID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_port_id_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_RAW] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_eth_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_VLAN] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vlan_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_IPV4] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_ipv4_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_IPV6] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_ipv6_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_ICMP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_UDP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_udp_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_TCP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_tcp_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_SCTP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_VXLAN] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vxlan_hdr_handler - }, - [RTE_FLOW_ITEM_TYPE_E_TAG] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_NVGRE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_MPLS] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GRE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_FUZZY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GTP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GTPC] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GTPU] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ESP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GENEVE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_IPV6_EXT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_MARK] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_META] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GRE_KEY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_GTP_PSC] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_PPPOES] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_PPPOED] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_NSH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_IGMP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_AH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - }, - [RTE_FLOW_ITEM_TYPE_HIGIG2] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL - } -}; - -uint32_t bnxt_ulp_encap_vtag_map[] = { - [0] = BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP, - [1] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - [2] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI -}; - -uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_0080] = 1, - [BNXT_ULP_CLASS_HID_0000] = 2, - [BNXT_ULP_CLASS_HID_0087] = 3 -}; - -struct bnxt_ulp_class_match_info ulp_class_match_list[] = { - [1] = { - .class_hid = BNXT_ULP_CLASS_HID_0080, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 0, - .act_vnic = 0, - .wc_pri = 0 - }, - [2] = { - .class_hid = BNXT_ULP_CLASS_HID_0000, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 1, - .act_vnic = 0, - .wc_pri = 0 - }, - [3] = { - .class_hid = BNXT_ULP_CLASS_HID_0087, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT | - BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 2, - .act_vnic = 0, - .wc_pri = 0 - } -}; - -uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_ACT_HID_00a1] = 1, - [BNXT_ULP_ACT_HID_0040] = 2, - [BNXT_ULP_ACT_HID_0029] = 3 -}; - -struct bnxt_ulp_act_match_info ulp_act_match_list[] = { - [1] = { - .act_hid = BNXT_ULP_ACT_HID_00a1, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 0 - }, - [2] = { - .act_hid = BNXT_ULP_ACT_HID_0040, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VPORT | - BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 1 - }, - [3] = { - .act_hid = BNXT_ULP_ACT_HID_0029, - .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - } -}; - -struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = { - [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 0 - }, - [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 5 - }, - [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 10 - } -}; - -struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 0, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 2, - .result_start_idx = 0, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 1, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - .vfr_flag = BNXT_ULP_VFR_FLAG_NO, - .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 2, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 1, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 1, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - .vfr_flag = BNXT_ULP_VFR_FLAG_NO, - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 15, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 14, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 1, - .ident_nums = 1, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - .vfr_flag = BNXT_ULP_VFR_FLAG_NO, - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 18, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 42, - .result_start_idx = 15, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - .vfr_flag = BNXT_ULP_VFR_FLAG_NO, - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 60, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 23, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_YES, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 71, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 2, - .result_start_idx = 32, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 1, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 73, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 33, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 86, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 46, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 1, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 89, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 42, - .result_start_idx = 47, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 4, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 131, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 55, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 4, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_YES, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 142, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 2, - .result_start_idx = 64, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 4, - .ident_nums = 1, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 144, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 65, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 157, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 78, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 1, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 160, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 42, - .result_start_idx = 79, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 6, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_NO, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_NOT_USED, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 202, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 87, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 6, - .ident_nums = 0, - .mark_enable = BNXT_ULP_MARK_ENABLE_YES, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED - } -}; - -struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = { - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV4, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_TYPE_DIX, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_HREC_NEXT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff, - BNXT_ULP_SYM_RESERVED_IGNORE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_AGG_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_RECYCLE_CNT_ZERO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_PKT_TYPE_L2, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV4, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_TYPE_DIX, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_HREC_NEXT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff, - BNXT_ULP_SYM_RESERVED_IGNORE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_AGG_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_RECYCLE_CNT_ZERO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_PKT_TYPE_L2, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF1_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF1_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_TYPE_IPV4, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_TYPE_DIX, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_ERROR_NO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_TYPE_DIX, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_HREC_NEXT_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff, - BNXT_ULP_SYM_RESERVED_IGNORE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_AGG_ERROR_IGNORE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_RECYCLE_CNT_ZERO, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_PKT_TYPE_L2, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF2_IDX_I_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF2_IDX_I_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT, - .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT, - .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } -}; - -struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 6, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 5, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 33, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 5, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 9, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 6, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 5, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 33, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 5, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 9, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 7, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 6, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 5, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 33, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 5, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 9, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } -}; - -struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, - .ident_bit_size = 10, - .ident_bit_pos = 0 - } -}; - -struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = { - [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 1, - .start_tbl_idx = 0 - }, - [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 1, - .start_tbl_idx = 1 - }, - [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 1, - .start_tbl_idx = 2 - } -}; - -struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = { - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 0, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 26, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 12, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 64, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR - } -}; - -struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { - { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_DECAP_FUNC_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 0, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 0, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 0, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_DECAP_FUNC_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT, - .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } -}; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h deleted file mode 100644 index ca0910ebf4..0000000000 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h +++ /dev/null @@ -1,614 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom - * All rights reserved. - */ - - -#ifndef ULP_TEMPLATE_DB_H_ -#define ULP_TEMPLATE_DB_H_ - -#define BNXT_ULP_REGFILE_MAX_SZ 15 -#define BNXT_ULP_MAX_NUM_DEVICES 4 -#define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_CACHE_TBL_MAX_SZ 4 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4 -#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919 -#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907 -#define BNXT_ULP_CLASS_HID_SHFTR 16 -#define BNXT_ULP_CLASS_HID_SHFTL 23 -#define BNXT_ULP_CLASS_HID_MASK 255 -#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4 -#define BNXT_ULP_ACT_HID_LOW_PRIME 7919 -#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919 -#define BNXT_ULP_ACT_HID_SHFTR 0 -#define BNXT_ULP_ACT_HID_SHFTL 23 -#define BNXT_ULP_ACT_HID_MASK 255 -#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2 -#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2 - -enum bnxt_ulp_action_bit { - BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001, - BNXT_ULP_ACTION_BIT_DROP = 0x0000000000000002, - BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004, - BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008, - BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010, - BNXT_ULP_ACTION_BIT_VNIC = 0x0000000000000020, - BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040, - BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080, - BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100, - BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200, - BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400, - BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800, - BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000, - BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000, - BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000, - BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000, - BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000, - BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000, - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000, - BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000, - BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000, - BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000200000, - BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000400000, - BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000800000, - BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000001000000, - BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000002000000, - BNXT_ULP_ACTION_BIT_NVGRE_ENCAP = 0x0000000004000000, - BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000 -}; - -enum bnxt_ulp_hdr_bit { - BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001, - BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002, - BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004, - BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008, - BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010, - BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020, - BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040, - BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080, - BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100, - BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200, - BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400, - BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000 -}; - -enum bnxt_ulp_act_type { - BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0, - BNXT_ULP_ACT_TYPE_SUPPORTED = 1, - BNXT_ULP_ACT_TYPE_END = 2, - BNXT_ULP_ACT_TYPE_LAST = 3 -}; - -enum bnxt_ulp_byte_order { - BNXT_ULP_BYTE_ORDER_BE = 0, - BNXT_ULP_BYTE_ORDER_LE = 1, - BNXT_ULP_BYTE_ORDER_LAST = 2 -}; - -enum bnxt_ulp_cf_idx { - BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0, - BNXT_ULP_CF_IDX_O_VTAG_NUM = 1, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2, - BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3, - BNXT_ULP_CF_IDX_I_VTAG_NUM = 4, - BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5, - BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6, - BNXT_ULP_CF_IDX_INCOMING_IF = 7, - BNXT_ULP_CF_IDX_DIRECTION = 8, - BNXT_ULP_CF_IDX_SVIF_FLAG = 9, - BNXT_ULP_CF_IDX_O_L3 = 10, - BNXT_ULP_CF_IDX_I_L3 = 11, - BNXT_ULP_CF_IDX_O_L4 = 12, - BNXT_ULP_CF_IDX_I_L4 = 13, - BNXT_ULP_CF_IDX_DEV_PORT_ID = 14, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15, - BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18, - BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20, - BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24, - BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27, - BNXT_ULP_CF_IDX_LAST = 28 -}; - -enum bnxt_ulp_critical_resource { - BNXT_ULP_CRITICAL_RESOURCE_NO = 0, - BNXT_ULP_CRITICAL_RESOURCE_YES = 1, - BNXT_ULP_CRITICAL_RESOURCE_LAST = 2 -}; - -enum bnxt_ulp_device_id { - BNXT_ULP_DEVICE_ID_WH_PLUS = 0, - BNXT_ULP_DEVICE_ID_THOR = 1, - BNXT_ULP_DEVICE_ID_STINGRAY = 2, - BNXT_ULP_DEVICE_ID_STINGRAY2 = 3, - BNXT_ULP_DEVICE_ID_LAST = 4 -}; - -enum bnxt_ulp_direction { - BNXT_ULP_DIRECTION_INGRESS = 0, - BNXT_ULP_DIRECTION_EGRESS = 1, - BNXT_ULP_DIRECTION_LAST = 2 -}; - -enum bnxt_ulp_glb_regfile_index { - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0, - BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1 -}; - -enum bnxt_ulp_hdr_type { - BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0, - BNXT_ULP_HDR_TYPE_SUPPORTED = 1, - BNXT_ULP_HDR_TYPE_END = 2, - BNXT_ULP_HDR_TYPE_LAST = 3 -}; - -enum bnxt_ulp_mark_enable { - BNXT_ULP_MARK_ENABLE_NO = 0, - BNXT_ULP_MARK_ENABLE_YES = 1, - BNXT_ULP_MARK_ENABLE_LAST = 2 -}; - -enum bnxt_ulp_mask_opc { - BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0, - BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1, - BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2, - BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3, - BNXT_ULP_MASK_OPC_ADD_PAD = 4, - BNXT_ULP_MASK_OPC_LAST = 5 -}; - -enum bnxt_ulp_match_type { - BNXT_ULP_MATCH_TYPE_EM = 0, - BNXT_ULP_MATCH_TYPE_WC = 1, - BNXT_ULP_MATCH_TYPE_LAST = 2 -}; - -enum bnxt_ulp_priority { - BNXT_ULP_PRIORITY_LEVEL_0 = 0, - BNXT_ULP_PRIORITY_LEVEL_1 = 1, - BNXT_ULP_PRIORITY_LEVEL_2 = 2, - BNXT_ULP_PRIORITY_LEVEL_3 = 3, - BNXT_ULP_PRIORITY_LEVEL_4 = 4, - BNXT_ULP_PRIORITY_LEVEL_5 = 5, - BNXT_ULP_PRIORITY_LEVEL_6 = 6, - BNXT_ULP_PRIORITY_LEVEL_7 = 7, - BNXT_ULP_PRIORITY_NOT_USED = 8, - BNXT_ULP_PRIORITY_LAST = 9 -}; - -enum bnxt_ulp_regfile_index { - BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2, - BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3, - BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7, - BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9, - BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12, - BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13, - BNXT_ULP_REGFILE_INDEX_NOT_USED = 14, - BNXT_ULP_REGFILE_INDEX_LAST = 15 -}; - -enum bnxt_ulp_result_opc { - BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0, - BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1, - BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2, - BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3, - BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4, - BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5, - BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6, - BNXT_ULP_RESULT_OPC_LAST = 7 -}; - -enum bnxt_ulp_search_before_alloc { - BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0, - BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1, - BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2 -}; - -enum bnxt_ulp_spec_opc { - BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0, - BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1, - BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2, - BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3, - BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4, - BNXT_ULP_SPEC_OPC_ADD_PAD = 5, - BNXT_ULP_SPEC_OPC_LAST = 6 -}; - -enum bnxt_ulp_vfr_flag { - BNXT_ULP_VFR_FLAG_NO = 0, - BNXT_ULP_VFR_FLAG_YES = 1, - BNXT_ULP_VFR_FLAG_LAST = 2 -}; - -enum bnxt_ulp_encap_vtag_encoding { - BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI = 4, - BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_REMAP_DIFFSERV = 5, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_ECAP_PRI = 6, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_DIFFSERV = 7, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_0 = 8, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_1 = 9, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_2 = 10, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_3 = 11, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_4 = 12, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_5 = 13, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_6 = 14, - BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_7 = 15, - BNXT_ULP_ENCAP_VTAG_ENCODING_NOP = 0, - BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI = 1, - BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_IVLAN_PRI = 2, - BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3 -}; - -enum bnxt_ulp_vfr_flag { - BNXT_ULP_VFR_FLAG_NO = 0, - BNXT_ULP_VFR_FLAG_YES = 1, - BNXT_ULP_VFR_FLAG_LAST = 2 -}; - -enum bnxt_ulp_fdb_resource_flags { - BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01, - BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00 -}; - -enum bnxt_ulp_fdb_type { - BNXT_ULP_FDB_TYPE_DEFAULT = 1, - BNXT_ULP_FDB_TYPE_REGULAR = 0 -}; - -enum bnxt_ulp_flow_dir_bitmask { - BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000, - BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000 -}; - -enum bnxt_ulp_match_type_bitmask { - BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000, - BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001 -}; - -enum bnxt_ulp_resource_func { - BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00, - BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20, - BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40, - BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60, - BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80, - BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81, - BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82, - BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83, - BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84, - BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85 -}; - -enum bnxt_ulp_resource_sub_type { - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0, - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0, - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1, - BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0 -}; - -enum bnxt_ulp_sym { - BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0, - BNXT_ULP_SYM_AGG_ERROR_NO = 0, - BNXT_ULP_SYM_AGG_ERROR_YES = 1, - BNXT_ULP_SYM_BIG_ENDIAN = 0, - BNXT_ULP_SYM_DECAP_FUNC_NONE = 0, - BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11, - BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12, - BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13, - BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3, - BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8, - BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9, - BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10, - BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0, - BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1, - BNXT_ULP_SYM_ECV_L2_EN_NO = 0, - BNXT_ULP_SYM_ECV_L2_EN_YES = 1, - BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4, - BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5, - BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6, - BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7, - BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0, - BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0, - BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4, - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5, - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, - BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1, - BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5, - BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3, - BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0, - BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4, - BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2, - BNXT_ULP_SYM_ECV_VALID_NO = 0, - BNXT_ULP_SYM_ECV_VALID_YES = 1, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, - BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0, - BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0, - BNXT_ULP_SYM_HREC_NEXT_NO = 0, - BNXT_ULP_SYM_HREC_NEXT_YES = 1, - BNXT_ULP_SYM_IP_PROTO_ICMP = 1, - BNXT_ULP_SYM_IP_PROTO_IGMP = 2, - BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4, - BNXT_ULP_SYM_IP_PROTO_TCP = 6, - BNXT_ULP_SYM_IP_PROTO_UDP = 17, - BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0, - BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2, - BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1, - BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_L2_HDR_VALID_NO = 0, - BNXT_ULP_SYM_L2_HDR_VALID_YES = 1, - BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0, - BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0, - BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1, - BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3, - BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0, - BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2, - BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0, - BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0, - BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0, - BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1, - BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0, - BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0, - BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1, - BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2, - BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4, - BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6, - BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0, - BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1, - BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3, - BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5, - BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7, - BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8, - BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_L3_HDR_VALID_NO = 0, - BNXT_ULP_SYM_L3_HDR_VALID_YES = 1, - BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0, - BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0, - BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1, - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0, - BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1, - BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0, - BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1, - BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5, - BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2, - BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0, - BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1, - BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3, - BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4, - BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_L4_HDR_VALID_NO = 0, - BNXT_ULP_SYM_L4_HDR_VALID_YES = 1, - BNXT_ULP_SYM_LITTLE_ENDIAN = 1, - BNXT_ULP_SYM_MATCH_TYPE_EM = 0, - BNXT_ULP_SYM_MATCH_TYPE_WM = 1, - BNXT_ULP_SYM_NO = 0, - BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0, - BNXT_ULP_SYM_PKT_TYPE_L2 = 0, - BNXT_ULP_SYM_POP_VLAN_NO = 0, - BNXT_ULP_SYM_POP_VLAN_YES = 1, - BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0, - BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1, - BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3, - BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2, - BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0, - BNXT_ULP_SYM_RESERVED_IGNORE = 0, - BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3, - BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3, - BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3, - BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0, - BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0, - BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1, - BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0, - BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0, - BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1, - BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3, - BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0, - BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2, - BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0, - BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0, - BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0, - BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1, - BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0, - BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0, - BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1, - BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0, - BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1, - BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0, - BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1, - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0, - BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1, - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0, - BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1, - BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, - BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, - BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0, - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1, - BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0, - BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1, - BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0, - BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0, - BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1, - BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0, - BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1, - BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3, - BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0, - BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4, - BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5, - BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7, - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15, - BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2, - BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6, - BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8, - BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9, - BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0, - BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0, - BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0, - BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1, - BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3, - BNXT_ULP_SYM_YES = 1 -}; - -enum bnxt_ulp_act_prop_sz { - BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4, - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4, - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4, - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4, - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4, - BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4, - BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4, - BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4, - BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4, - BNXT_ULP_ACT_PROP_SZ_VNIC = 4, - BNXT_ULP_ACT_PROP_SZ_VPORT = 4, - BNXT_ULP_ACT_PROP_SZ_MARK = 4, - BNXT_ULP_ACT_PROP_SZ_COUNT = 4, - BNXT_ULP_ACT_PROP_SZ_METER = 4, - BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8, - BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4, - BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4, - BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4, - BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4, - BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4, - BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16, - BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16, - BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4, - BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4, - BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4, - BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6, - BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6, - BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8, - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32, - BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16, - BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4, - BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32, - BNXT_ULP_ACT_PROP_SZ_LAST = 4 -}; - -enum bnxt_ulp_act_prop_idx { - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20, - BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24, - BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28, - BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32, - BNXT_ULP_ACT_PROP_IDX_VNIC = 36, - BNXT_ULP_ACT_PROP_IDX_VPORT = 40, - BNXT_ULP_ACT_PROP_IDX_MARK = 44, - BNXT_ULP_ACT_PROP_IDX_COUNT = 48, - BNXT_ULP_ACT_PROP_IDX_METER = 52, - BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56, - BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72, - BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76, - BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88, - BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92, - BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156, - BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236, - BNXT_ULP_ACT_PROP_IDX_LAST = 268 -}; - -enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_0080 = 0x0080, - BNXT_ULP_CLASS_HID_0000 = 0x0000, - BNXT_ULP_CLASS_HID_0087 = 0x0087 -}; - -enum bnxt_ulp_act_hid { - BNXT_ULP_ACT_HID_00a1 = 0x00a1, - BNXT_ULP_ACT_HID_0040 = 0x0040, - BNXT_ULP_ACT_HID_0029 = 0x0029 -}; - -#endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h deleted file mode 100644 index b05d223db8..0000000000 --- a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h +++ /dev/null @@ -1,224 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom - * All rights reserved. - */ - -#ifndef ULP_HDR_FIELD_ENUMS_H_ -#define ULP_HDR_FIELD_ENUMS_H_ - -enum bnxt_ulp_hf0 { - BNXT_ULP_HF0_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF0_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF0_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF0_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF0_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF0_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF0_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF0_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF0_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF0_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF0_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF0_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF0_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF0_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF0_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF0_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF0_IDX_O_IPV4_NEXT_PID = 16, - BNXT_ULP_HF0_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF0_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF0_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF0_IDX_O_UDP_CSUM = 23 -}; - -enum bnxt_ulp_hf1 { - BNXT_ULP_HF1_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF1_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF1_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF1_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF1_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF1_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF1_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF1_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF1_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF1_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF1_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF1_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF1_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF1_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF1_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF1_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF1_IDX_O_IPV4_NEXT_PID = 16, - BNXT_ULP_HF1_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF1_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF1_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF1_IDX_O_UDP_CSUM = 23 -}; - -enum bnxt_ulp_hf2 { - BNXT_ULP_HF2_IDX_SVIF_INDEX = 0, - BNXT_ULP_HF2_IDX_O_ETH_DMAC = 1, - BNXT_ULP_HF2_IDX_O_ETH_SMAC = 2, - BNXT_ULP_HF2_IDX_O_ETH_TYPE = 3, - BNXT_ULP_HF2_IDX_OO_VLAN_CFI_PRI = 4, - BNXT_ULP_HF2_IDX_OO_VLAN_VID = 5, - BNXT_ULP_HF2_IDX_OO_VLAN_TYPE = 6, - BNXT_ULP_HF2_IDX_OI_VLAN_CFI_PRI = 7, - BNXT_ULP_HF2_IDX_OI_VLAN_VID = 8, - BNXT_ULP_HF2_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF2_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF2_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF2_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF2_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF2_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF2_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF2_IDX_O_IPV4_NEXT_PID = 16, - BNXT_ULP_HF2_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF2_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF2_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF2_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF2_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF2_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF2_IDX_O_UDP_CSUM = 23, - BNXT_ULP_HF2_IDX_T_VXLAN_FLAGS = 24, - BNXT_ULP_HF2_IDX_T_VXLAN_RSVD0 = 25, - BNXT_ULP_HF2_IDX_T_VXLAN_VNI = 26, - BNXT_ULP_HF2_IDX_T_VXLAN_RSVD1 = 27, - BNXT_ULP_HF2_IDX_I_ETH_DMAC = 28, - BNXT_ULP_HF2_IDX_I_ETH_SMAC = 29, - BNXT_ULP_HF2_IDX_I_ETH_TYPE = 30, - BNXT_ULP_HF2_IDX_IO_VLAN_CFI_PRI = 31, - BNXT_ULP_HF2_IDX_IO_VLAN_VID = 32, - BNXT_ULP_HF2_IDX_IO_VLAN_TYPE = 33, - BNXT_ULP_HF2_IDX_II_VLAN_CFI_PRI = 34, - BNXT_ULP_HF2_IDX_II_VLAN_VID = 35, - BNXT_ULP_HF2_IDX_II_VLAN_TYPE = 36, - BNXT_ULP_HF2_IDX_I_IPV4_VER = 37, - BNXT_ULP_HF2_IDX_I_IPV4_TOS = 38, - BNXT_ULP_HF2_IDX_I_IPV4_LEN = 39, - BNXT_ULP_HF2_IDX_I_IPV4_FRAG_ID = 40, - BNXT_ULP_HF2_IDX_I_IPV4_FRAG_OFF = 41, - BNXT_ULP_HF2_IDX_I_IPV4_TTL = 42, - BNXT_ULP_HF2_IDX_I_IPV4_NEXT_PID = 43, - BNXT_ULP_HF2_IDX_I_IPV4_CSUM = 44, - BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR = 45, - BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR = 46, - BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT = 47, - BNXT_ULP_HF2_IDX_I_UDP_DST_PORT = 48, - BNXT_ULP_HF2_IDX_I_UDP_LENGTH = 49, - BNXT_ULP_HF2_IDX_I_UDP_CSUM = 50 -}; - -enum bnxt_ulp_hf_bitmask0 { - BNXT_ULP_HF0_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF0_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF0_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF0_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF0_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF0_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF0_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF0_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF0_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF0_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF0_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF0_BITMASK_O_UDP_CSUM = 0x0000010000000000 -}; -enum bnxt_ulp_hf_bitmask1 { - BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF1_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF1_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF1_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF1_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF1_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF1_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF1_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF1_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF1_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF1_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF1_BITMASK_O_UDP_CSUM = 0x0000010000000000 -}; - -enum bnxt_ulp_hf_bitmask2 { - BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000, - BNXT_ULP_HF2_BITMASK_O_ETH_DMAC = 0x4000000000000000, - BNXT_ULP_HF2_BITMASK_O_ETH_SMAC = 0x2000000000000000, - BNXT_ULP_HF2_BITMASK_O_ETH_TYPE = 0x1000000000000000, - BNXT_ULP_HF2_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, - BNXT_ULP_HF2_BITMASK_OO_VLAN_VID = 0x0400000000000000, - BNXT_ULP_HF2_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, - BNXT_ULP_HF2_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, - BNXT_ULP_HF2_BITMASK_OI_VLAN_VID = 0x0080000000000000, - BNXT_ULP_HF2_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF2_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF2_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF2_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF2_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF2_BITMASK_O_UDP_CSUM = 0x0000010000000000, - BNXT_ULP_HF2_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000, - BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000, - BNXT_ULP_HF2_BITMASK_T_VXLAN_VNI = 0x0000002000000000, - BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000, - BNXT_ULP_HF2_BITMASK_I_ETH_DMAC = 0x0000000800000000, - BNXT_ULP_HF2_BITMASK_I_ETH_SMAC = 0x0000000400000000, - BNXT_ULP_HF2_BITMASK_I_ETH_TYPE = 0x0000000200000000, - BNXT_ULP_HF2_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000, - BNXT_ULP_HF2_BITMASK_IO_VLAN_VID = 0x0000000080000000, - BNXT_ULP_HF2_BITMASK_IO_VLAN_TYPE = 0x0000000040000000, - BNXT_ULP_HF2_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000, - BNXT_ULP_HF2_BITMASK_II_VLAN_VID = 0x0000000010000000, - BNXT_ULP_HF2_BITMASK_II_VLAN_TYPE = 0x0000000008000000, - BNXT_ULP_HF2_BITMASK_I_IPV4_VER = 0x0000000004000000, - BNXT_ULP_HF2_BITMASK_I_IPV4_TOS = 0x0000000002000000, - BNXT_ULP_HF2_BITMASK_I_IPV4_LEN = 0x0000000001000000, - BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000, - BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000, - BNXT_ULP_HF2_BITMASK_I_IPV4_TTL = 0x0000000000200000, - BNXT_ULP_HF2_BITMASK_I_IPV4_NEXT_PID = 0x0000000000100000, - BNXT_ULP_HF2_BITMASK_I_IPV4_CSUM = 0x0000000000080000, - BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000, - BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000, - BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000, - BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT = 0x0000000000008000, - BNXT_ULP_HF2_BITMASK_I_UDP_LENGTH = 0x0000000000004000, - BNXT_ULP_HF2_BITMASK_I_UDP_CSUM = 0x0000000000002000 -}; - -#endif From patchwork Sun May 30 08:59:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 93700 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F670A0524; Tue, 1 Jun 2021 09:44:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B774841157; Tue, 1 Jun 2021 09:40:15 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 514B241148 for ; Sun, 30 May 2021 11:02:12 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 4795F7DC2; Sun, 30 May 2021 02:02:10 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 4795F7DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1622365331; bh=wpXVFHKgUuFC5EWkyZIIGypKR+NMPPIXxE5PIKf6mAM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wKe1GpJJTZmjBfwEyAn42IUAJCvrNdT3XomnTfudHo6iD8akwChct01/8m/pDESX3 sJiGl8ds5di+RJMxNl4ATBx6H619GeFDtnxnB9RSqjHWiyy6bYJeeeY9fzmFf6AQr/ fqBvVaf4LNIqZVZKvzngruDeWDa+Au1DRIzpruKU= From: Venkat Duvvuru To: dev@dpdk.org Cc: Mike Baucom , Venkat Duvvuru Date: Sun, 30 May 2021 14:29:29 +0530 Message-Id: <20210530085929.29695-59-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Tue, 01 Jun 2021 09:39:54 +0200 Subject: [dpdk-dev] [PATCH 58/58] net/bnxt: add Thor template support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Mike Baucom Template adds non-VFR based support for testpmd with: matches to include - DMAC, SIP, DIP, Proto, Sport, Dport - SIP, DIP, Proto, Sport, Dport actions: - count, drop Signed-off-by: Mike Baucom Signed-off-by: Venkat Duvvuru Reviewed-by: Kishore Padmanabha --- .../generic_templates/ulp_template_db_enum.h | 71 +- .../generic_templates/ulp_template_db_tbl.c | 278 +- .../ulp_template_db_thor_act.c | 48 +- .../ulp_template_db_thor_class.c | 31252 ++-------------- .../ulp_template_db_wh_plus_act.c | 156 +- .../ulp_template_db_wh_plus_class.c | 458 +- 6 files changed, 4697 insertions(+), 27566 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index a38fddafdb..b6db49cc5d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Apr 14 09:56:27 2021 */ +/* date: Thu May 13 18:15:56 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -26,10 +26,10 @@ #define BNXT_ULP_ACT_HID_SHFTR 27 #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 -#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 4 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 33 -#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 38 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 205 +#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 43 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 204 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 @@ -44,11 +44,11 @@ #define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546 #define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43 #define ULP_THOR_CLASS_TMPL_LIST_SIZE 5 -#define ULP_THOR_CLASS_TBL_LIST_SIZE 13 -#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 0 -#define ULP_THOR_CLASS_IDENT_LIST_SIZE 0 -#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 102 -#define ULP_THOR_CLASS_COND_LIST_SIZE 1 +#define ULP_THOR_CLASS_TBL_LIST_SIZE 33 +#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242 +#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8 +#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 259 +#define ULP_THOR_CLASS_COND_LIST_SIZE 13 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 @@ -56,11 +56,11 @@ #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512 #define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7 -#define ULP_THOR_ACT_TBL_LIST_SIZE 0 +#define ULP_THOR_ACT_TBL_LIST_SIZE 2 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 0 #define ULP_THOR_ACT_IDENT_LIST_SIZE 0 -#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 0 -#define ULP_THOR_ACT_COND_LIST_SIZE 0 +#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 18 +#define ULP_THOR_ACT_COND_LIST_SIZE 5 enum bnxt_ulp_act_bit { BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001, @@ -199,7 +199,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60, BNXT_ULP_CF_IDX_WC_MATCH = 61, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62, - BNXT_ULP_CF_IDX_LAST = 63 + BNXT_ULP_CF_IDX_F1_DMAC = 63, + BNXT_ULP_CF_IDX_LAST = 64 }; enum bnxt_ulp_cond_list_opc { @@ -345,23 +346,31 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 3, BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4, BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 6, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 7, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 8, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 9, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 10, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 11, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 12, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 13, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 14, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 15, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 16, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 17, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 18, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 19, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 20, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 21, - BNXT_ULP_GLB_RF_IDX_LAST = 22 + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 6, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 7, + BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 8, + BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 9, + BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 10, + BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 11, + BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 12, + BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 13, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 14, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 15, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 16, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 17, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 18, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 19, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 20, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 21, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 22, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 23, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 24, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 25, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 26, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 27, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 28, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 29, + BNXT_ULP_GLB_RF_IDX_LAST = 30 }; enum bnxt_ulp_hdr_type { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 7573cf6074..6664353764 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Apr 14 09:56:27 2021 */ +/* date: Thu May 13 18:15:56 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -36,7 +36,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { BNXT_ULP_DIRECTION_INGRESS] = { .name = "INGRESS GENERIC_TABLE_PROFILE_TCAM", .result_num_entries = 16384, - .result_num_bytes = 16, + .result_num_bytes = 18, .key_num_bytes = 0, .num_buckets = 0, .hash_tbl_entries = 0, @@ -46,7 +46,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { BNXT_ULP_DIRECTION_EGRESS] = { .name = "EGRESS GENERIC_TABLE_PROFILE_TCAM", .result_num_entries = 16384, - .result_num_bytes = 16, + .result_num_bytes = 18, .key_num_bytes = 0, .num_buckets = 0, .hash_tbl_entries = 0, @@ -167,6 +167,8 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = { .tmpl_list_size = ULP_THOR_ACT_TMPL_LIST_SIZE, .tbl_list = ulp_thor_act_tbl_list, .tbl_list_size = ULP_THOR_ACT_TBL_LIST_SIZE, + .cond_list = ulp_thor_act_cond_list, + .cond_list_size = ULP_THOR_ACT_COND_LIST_SIZE, .result_field_list = ulp_thor_act_result_field_list, .result_field_list_size = ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE } @@ -188,7 +190,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { .num_phy_ports = 2, .ext_cntr_table_type = 0, .byte_count_mask = 0x0000000fffffffff, - .packet_count_mask = 0xffffffff00000000, + .packet_count_mask = 0xfffffff000000000, .byte_count_shift = 0, .packet_count_shift = 36, .dynamic_pad_en = 0, @@ -207,17 +209,17 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { .num_resources_per_flow = 8, .num_phy_ports = 2, .ext_cntr_table_type = 0, - .byte_count_mask = 0x0000000fffffffff, - .packet_count_mask = 0xffffffff00000000, + .byte_count_mask = 0x00000007ffffffff, + .packet_count_mask = 0xfffffff800000000, .byte_count_shift = 0, - .packet_count_shift = 36, + .packet_count_shift = 35, .dynamic_pad_en = 1, .em_blk_size_bits = 100, .em_blk_align_bits = 128, .em_key_align_bytes = 80, .wc_slice_width = 160, .wc_max_slices = 4, - .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f}, + .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f}, .wc_mod_list_max_size = 4, .wc_ctl_size_bits = 32, .dev_tbls = ulp_template_thor_tbls @@ -252,28 +254,40 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .flags = BNXT_ULP_APP_CAP_SHARED_EN | - BNXT_ULP_APP_CAP_HOT_UPGRADE_EN + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY }, { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_SHARED_EN | - BNXT_ULP_APP_CAP_HOT_UPGRADE_EN + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY }, { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .flags = BNXT_ULP_APP_CAP_SHARED_EN + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY }, { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .flags = BNXT_ULP_APP_CAP_SHARED_EN + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY } }; /* List of unnamed app tf resources required to be reserved per app/device */ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, @@ -287,8 +301,24 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 512 + .count = 1024 + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 }, { .app_id = 2, @@ -303,8 +333,16 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 512 + .count = 1024 } }; @@ -322,6 +360,22 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -361,6 +415,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, @@ -386,6 +448,22 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -425,6 +503,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, @@ -474,6 +560,22 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -513,6 +615,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, @@ -538,6 +648,22 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -577,6 +703,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, @@ -684,6 +818,22 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { }, { .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -707,6 +857,70 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -1196,7 +1410,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 26 + .count = 422 }, { .app_id = 0, @@ -1252,7 +1466,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 14 + .count = 5 }, { .app_id = 0, @@ -1268,7 +1482,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 31 }, { .app_id = 0, @@ -1316,7 +1530,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 112 + .count = 2048 }, { .app_id = 0, @@ -1372,7 +1586,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 1024 + .count = 1023 }, { .app_id = 0, @@ -1388,7 +1602,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 14 + .count = 5 }, { .app_id = 0, @@ -1426,14 +1640,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .count = 200 @@ -1460,7 +1666,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 128 + .count = 2048 }, { .app_id = 0, @@ -1772,7 +1978,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 32 + .count = 16 }, { .app_id = 1, @@ -1788,7 +1994,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 528 }, { .app_id = 1, @@ -1876,7 +2082,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 26 + .count = 32 }, { .app_id = 1, @@ -2300,7 +2506,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 32 + .count = 16 }, { .app_id = 2, @@ -2316,7 +2522,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 528 }, { .app_id = 2, @@ -2388,7 +2594,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 256 + .count = 512 }, { .app_id = 2, @@ -2404,7 +2610,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 26 + .count = 32 }, { .app_id = 2, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c index a60dfae104..ce5a70b0c5 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Apr 5 11:35:38 2021 */ +/* date: Thu May 13 18:15:56 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -12,20 +12,20 @@ /* Mapper templates for header act list */ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { - /* act_tid: 1, thor, ingress */ + /* act_tid: 1, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, .num_tbls = 2, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, - .cond_nums = 0 } + .cond_nums = 4 } } }; struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { - { /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */ + { /* act_tid: 1, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 0, + .cond_start_idx = 4, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -46,7 +46,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 1 }, - { /* act_tid: 1, thor, table: int_full_act_record.0 */ + { /* act_tid: 1, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -56,7 +56,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 5, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -70,6 +70,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { + /* cond_reject: thor, act_tid: 1 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_POP_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_VXLAN_DECAP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -78,14 +95,14 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { }; struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { - /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */ + /* act_tid: 1, , table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 1, thor, table: int_full_act_record.0 */ + /* act_tid: 1, , table: int_full_act_record.0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -180,7 +197,16 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .description = "drop", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} }, { .description = "hit", diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 45025733fc..83f6152700 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon Apr 5 11:35:38 2021 */ +/* date: Thu May 13 18:15:56 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -12,50 +12,40 @@ /* Mapper templates for header class list */ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { - /* class_tid: 1, thor, ingress */ + /* class_tid: 1, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 47, + .num_tbls = 12, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, .cond_start_idx = 0, - .cond_nums = 0 } + .cond_nums = 4 } }, - /* class_tid: 2, thor, ingress */ - [2] = { - .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 13, - .start_tbl_idx = 47, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 17, - .cond_nums = 0 } - }, - /* class_tid: 3, thor, ingress */ + /* class_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 1, - .start_tbl_idx = 60, + .num_tbls = 15, + .start_tbl_idx = 12, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, - .cond_nums = 0 } + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 8, + .cond_nums = 1 } }, - /* class_tid: 4, thor, ingress */ + /* class_tid: 4, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 9, - .start_tbl_idx = 61, + .num_tbls = 6, + .start_tbl_idx = 27, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, - .cond_nums = 0 } + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 12, + .cond_nums = 1 } } }; struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { - { /* class_tid: 1, thor, table: port_table.rd */ + { /* class_tid: 1, , table: port_table.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, @@ -64,7 +54,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 0, + .cond_start_idx = 4, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -77,54 +67,65 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 0, .ident_nums = 3 }, - { /* class_tid: 1, thor, table: control.check_gre */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + { /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 17, + .cond_true_goto = 5, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 0, + .cond_start_idx = 4, .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 1, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 3, + .ident_nums = 1 }, - { /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_rd */ + { /* class_tid: 1, , table: mac_addr_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 5, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 3, - .ident_nums = 0 + .key_start_idx = 2, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .ident_start_idx = 4, + .ident_nums = 1 }, - { /* class_tid: 1, thor, table: control.gre_hit */ + { /* class_tid: 1, , table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 42, + .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 1, + .cond_start_idx = 5, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 1, thor, table: l2_cntxt_tcam.gre */ + { /* class_tid: 1, , table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -132,7 +133,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -141,40 +142,75 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 2, + .key_start_idx = 7, .blob_key_bit_size = 213, .key_bit_size = 213, .key_num_fields = 21, .result_start_idx = 0, .result_bit_size = 43, .result_num_fields = 6, - .ident_start_idx = 3, + .ident_start_idx = 5, .ident_nums = 1 }, - { /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_wr */ + { /* class_tid: 1, , table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 23, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, + .key_start_idx = 28, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, .result_start_idx = 6, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 1, thor, table: fkb_select.gre */ + { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 6, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 33, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 6, + .ident_nums = 0 + }, + { /* class_tid: 1, , table: control.l3_l4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 6, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 1, , table: fkb_select.l3_l4_wm */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, .direction = TF_DIR_RX, @@ -182,17 +218,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .result_start_idx = 10, .result_bit_size = 106, .result_num_fields = 106 }, - { /* class_tid: 1, thor, table: profile_tcam.gre */ + { /* class_tid: 1, , table: profile_tcam.l3_l4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -200,120 +236,164 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 24, + .key_start_idx = 36, .blob_key_bit_size = 94, .key_bit_size = 94, .key_num_fields = 43, .result_start_idx = 116, .result_bit_size = 33, .result_num_fields = 8, - .ident_start_idx = 4, + .ident_start_idx = 6, .ident_nums = 0 }, - { /* class_tid: 1, thor, table: wm.gre */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 2, + .cond_true_goto = 1, .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 7, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 79, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 124, + .result_bit_size = 138, + .result_num_fields = 7 + }, + { /* class_tid: 1, , table: wm.l3_l4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 2, + .cond_start_idx = 7, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 67, + .key_start_idx = 82, .blob_key_bit_size = 0, .key_bit_size = 0, .key_num_fields = 114, - .result_start_idx = 124, + .result_start_idx = 131, .result_bit_size = 38, .result_num_fields = 5 }, - { /* class_tid: 1, thor, table: wm.gre_low */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, + { /* class_tid: 3, , table: int_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 9, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 181, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 129, - .result_bit_size = 38, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 136, + .result_bit_size = 128, + .result_num_fields = 17 + }, + { /* class_tid: 3, , table: port_table.wr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 9, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 196, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .result_start_idx = 153, + .result_bit_size = 152, .result_num_fields = 5 }, - { /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_rd */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 9, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 295, - .blob_key_bit_size = 73, - .key_bit_size = 73, - .key_num_fields = 5, - .ident_start_idx = 4, + .key_start_idx = 197, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 6, .ident_nums = 0 }, - { /* class_tid: 1, thor, table: control.gre_frag_mac_hit */ + { /* class_tid: 3, , table: control.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 4, + .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 3, + .cond_start_idx = 9, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -321,27675 +401,4470 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 300, + .key_start_idx = 198, .blob_key_bit_size = 213, .key_bit_size = 213, .key_num_fields = 21, - .result_start_idx = 134, + .result_start_idx = 158, .result_bit_size = 43, .result_num_fields = 6, - .ident_start_idx = 4, - .ident_nums = 0 + .ident_start_idx = 6, + .ident_nums = 1 }, - { /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_wr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 10, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 321, - .blob_key_bit_size = 73, - .key_bit_size = 73, - .key_num_fields = 5, - .result_start_idx = 140, + .key_start_idx = 219, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 164, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 1, thor, table: fkb_select.gre_frag */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, + { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 10, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 144, - .result_bit_size = 106, - .result_num_fields = 106 + .result_start_idx = 168, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: profile_tcam.gre_frag */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 4, + .cond_start_idx = 10, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 326, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 250, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 4, - .ident_nums = 0 + .result_start_idx = 169, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: wm.gre_frag */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + { /* class_tid: 3, , table: control.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 29, - .cond_false_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 10, .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 369, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 258, - .result_bit_size = 38, - .result_num_fields = 5 + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 1, thor, table: wm.gre_frag_low */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, - .direction = TF_DIR_RX, + { /* class_tid: 3, , table: int_full_act_record.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 28, + .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 5, + .cond_start_idx = 11, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 483, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 263, - .result_bit_size = 38, - .result_num_fields = 5 + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 170, + .result_bit_size = 128, + .result_num_fields = 17, + .encap_num_fields = 0 }, - { /* class_tid: 1, thor, table: mac_addr_cache.non_gre_rd */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 5, + .cond_start_idx = 11, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 597, - .blob_key_bit_size = 73, - .key_bit_size = 73, - .key_num_fields = 5, - .ident_start_idx = 4, + .key_start_idx = 220, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 7, .ident_nums = 0 }, - { /* class_tid: 1, thor, table: control.non_gre_mac */ + { /* class_tid: 3, , table: control.egr_1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 3, + .cond_false_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 5, + .cond_start_idx = 11, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ + { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 602, + .key_start_idx = 221, .blob_key_bit_size = 213, .key_bit_size = 213, .key_num_fields = 21, - .result_start_idx = 268, + .result_start_idx = 187, .result_bit_size = 43, .result_num_fields = 6, - .ident_start_idx = 4, - .ident_nums = 0 + .ident_start_idx = 7, + .ident_nums = 1 }, - { /* class_tid: 1, thor, table: mac_addr_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_RX, + { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, + .cond_start_idx = 12, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 623, - .blob_key_bit_size = 73, - .key_bit_size = 73, - .key_num_fields = 5, - .result_start_idx = 274, - .result_bit_size = 62, - .result_num_fields = 4 - }, - { /* class_tid: 1, thor, table: control.icmpv4_test */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 8, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, - .cond_nums = 2 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .result_start_idx = 193, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, + { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 12, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 628, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .ident_start_idx = 4, - .ident_nums = 0 - }, - { /* class_tid: 1, thor, table: control.icmpv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 4, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .result_start_idx = 194, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: fkb_select.icmpv4 */ + { /* class_tid: 4, , table: int_full_act_record.loopback */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .direction = TF_DIR_RX, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, + .cond_start_idx = 13, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 278, - .result_bit_size = 106, - .result_num_fields = 106 - }, - { /* class_tid: 1, thor, table: profile_tcam.icmpv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 631, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 384, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 4, - .ident_nums = 1 + .result_start_idx = 195, + .result_bit_size = 128, + .result_num_fields = 17, + .encap_num_fields = 0 }, - { /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, + { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 9, + .cond_start_idx = 13, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 674, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .result_start_idx = 392, - .result_bit_size = 82, - .result_num_fields = 7 - }, - { /* class_tid: 1, thor, table: wm.icmpv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 17, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 677, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 399, - .result_bit_size = 38, - .result_num_fields = 5 + .result_start_idx = 212, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: wm.icmpv4_low */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, - .direction = TF_DIR_RX, + { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 16, + .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 13, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 791, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 404, - .result_bit_size = 38, - .result_num_fields = 5 - }, - { /* class_tid: 1, thor, table: control.icmpv6_test */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 8, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, - .cond_nums = 2 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 213, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + { /* class_tid: 4, , table: int_full_act_record.vf_ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 12, + .cond_start_idx = 13, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 905, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .ident_start_idx = 5, - .ident_nums = 0 - }, - { /* class_tid: 1, thor, table: control.icmpv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 4, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 12, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .result_start_idx = 214, + .result_bit_size = 128, + .result_num_fields = 17, + .encap_num_fields = 0 }, - { /* class_tid: 1, thor, table: fkb_select.icmpv6 */ + { /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .direction = TF_DIR_RX, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 13, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 409, - .result_bit_size = 106, - .result_num_fields = 106 + .result_start_idx = 231, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 11 }, - { /* class_tid: 1, thor, table: profile_tcam.icmpv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, + { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, + .cond_true_goto = 0, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 13, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 908, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 515, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 5, - .ident_nums = 1 - }, - { /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 951, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .result_start_idx = 523, - .result_bit_size = 82, - .result_num_fields = 7 - }, - { /* class_tid: 1, thor, table: wm.icmpv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 9, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 954, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 530, - .result_bit_size = 38, - .result_num_fields = 5 - }, - { /* class_tid: 1, thor, table: wm.icmpv6_low */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 8, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 1068, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 535, - .result_bit_size = 38, - .result_num_fields = 5 - }, - { /* class_tid: 1, thor, table: profile_tcam_cache.l3_l4_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1182, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .ident_start_idx = 6, - .ident_nums = 0 - }, - { /* class_tid: 1, thor, table: control.l3_l4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 4, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 1, thor, table: fkb_select.l3_l4_wm */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 540, - .result_bit_size = 106, - .result_num_fields = 106 - }, - { /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1185, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 646, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 6, - .ident_nums = 0 - }, - { /* class_tid: 1, thor, table: profile_tcam_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 15, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1228, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .result_start_idx = 654, - .result_bit_size = 82, - .result_num_fields = 7 - }, - { /* class_tid: 1, thor, table: wm.l4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 1231, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 661, - .result_bit_size = 38, - .result_num_fields = 5 - }, - { /* class_tid: 1, thor, table: wm.l4_low */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 16, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 1345, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 666, - .result_bit_size = 38, - .result_num_fields = 5 - }, - { /* class_tid: 1, thor, table: control.check_rss_action */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 1, thor, table: control.rss_config */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, - .cond_nums = 0 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_RSS_CONFIG, - .func_dst_opr = BNXT_ULP_RF_IDX_CC }, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 2, thor, table: port_table.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1459, - .blob_key_bit_size = 10, - .key_bit_size = 10, - .key_num_fields = 1, - .ident_start_idx = 6, - .ident_nums = 3 - }, - { /* class_tid: 2, thor, table: mac_addr_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 17, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1460, - .blob_key_bit_size = 73, - .key_bit_size = 73, - .key_num_fields = 5, - .ident_start_idx = 9, - .ident_nums = 0 - }, - { /* class_tid: 2, thor, table: control.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 2, thor, table: l2_cntxt_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1465, - .blob_key_bit_size = 213, - .key_bit_size = 213, - .key_num_fields = 21, - .result_start_idx = 671, - .result_bit_size = 43, - .result_num_fields = 6, - .ident_start_idx = 9, - .ident_nums = 1 - }, - { /* class_tid: 2, thor, table: mac_addr_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1486, - .blob_key_bit_size = 73, - .key_bit_size = 73, - .key_num_fields = 5, - .result_start_idx = 677, - .result_bit_size = 62, - .result_num_fields = 4 - }, - { /* class_tid: 2, thor, table: profile_tcam_cache.l3_l4_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1491, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .ident_start_idx = 10, - .ident_nums = 0 - }, - { /* class_tid: 2, thor, table: control.l3_l4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 4, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 2, thor, table: fkb_select.l3_l4_wm */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 681, - .result_bit_size = 106, - .result_num_fields = 106 - }, - { /* class_tid: 2, thor, table: profile_tcam.l3_l4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1494, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 787, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 10, - .ident_nums = 0 - }, - { /* class_tid: 2, thor, table: profile_tcam_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1537, - .blob_key_bit_size = 14, - .key_bit_size = 14, - .key_num_fields = 3, - .result_start_idx = 795, - .result_bit_size = 82, - .result_num_fields = 7 - }, - { /* class_tid: 2, thor, table: wm.l4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 19, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_BE, - .key_start_idx = 1540, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 802, - .result_bit_size = 38, - .result_num_fields = 5 - }, - { /* class_tid: 2, thor, table: control.check_rss_action */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 2, thor, table: control.rss_config */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, - .cond_nums = 0 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_RSS_CONFIG, - .func_dst_opr = BNXT_ULP_RF_IDX_CC }, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 3, thor, table: control.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, - .cond_nums = 0 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 4, thor, table: control.get_parent_mac_addr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, - .cond_nums = 0 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR, - .func_dst_opr = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC }, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 4, thor, table: control.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_EQ, - .func_src1 = BNXT_ULP_FUNC_SRC_COMP_FIELD, - .func_opr1 = BNXT_ULP_CF_IDX_PHY_PORT_VPORT, - .func_src2 = BNXT_ULP_FUNC_SRC_CONST, - .func_opr2 = 1, - .func_dst_opr = BNXT_ULP_RF_IDX_CC }, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 4, thor, table: int_full_act_record.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 21, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 807, - .result_bit_size = 128, - .result_num_fields = 17 - }, - { /* class_tid: 4, thor, table: port_table.wr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 3, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 21, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1654, - .blob_key_bit_size = 10, - .key_bit_size = 10, - .key_num_fields = 1, - .result_start_idx = 824, - .result_bit_size = 152, - .result_num_fields = 5 - }, - { /* class_tid: 4, thor, table: int_full_act_record.1 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 21, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .shared_session = BNXT_ULP_SHARED_SESSION_YES, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 829, - .result_bit_size = 128, - .result_num_fields = 17 - }, - { /* class_tid: 4, thor, table: port_table.wr_1 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 21, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1655, - .blob_key_bit_size = 10, - .key_bit_size = 10, - .key_num_fields = 1, - .result_start_idx = 846, - .result_bit_size = 152, - .result_num_fields = 5 - }, - { /* class_tid: 4, thor, table: port_table.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 21, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 1656, - .blob_key_bit_size = 10, - .key_bit_size = 10, - .key_num_fields = 1, - .ident_start_idx = 10, - .ident_nums = 1 - }, - { /* class_tid: 4, thor, table: parif_def_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 21, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 851, - .result_bit_size = 32, - .result_num_fields = 1 - }, - { /* class_tid: 4, thor, table: parif_def_err_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 21, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 852, - .result_bit_size = 32, - .result_num_fields = 1 - } -}; - -struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_execute: class_tid: 1, control.check_gre */ - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_GRE - }, - /* cond_execute: class_tid: 1, control.gre_hit */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 1, wm.gre */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG - }, - /* cond_execute: class_tid: 1, control.gre_frag_mac_hit */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 1, wm.gre_frag */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG - }, - /* cond_execute: class_tid: 1, control.non_gre_mac */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 1, control.icmpv4_test */ - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_ICMP - }, - /* cond_execute: class_tid: 1, control.icmpv4 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 1, wm.icmpv4 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG - }, - /* cond_execute: class_tid: 1, control.icmpv6_test */ - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 - }, - { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_ICMP - }, - /* cond_execute: class_tid: 1, control.icmpv6 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 1, wm.icmpv6 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG - }, - /* cond_execute: class_tid: 1, control.l3_l4 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 1, wm.l4 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG - }, - /* cond_execute: class_tid: 1, control.check_rss_action */ - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_RSS - }, - /* cond_execute: class_tid: 2, control.0 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 2, control.l3_l4 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - }, - /* cond_execute: class_tid: 2, control.check_rss_action */ - { - .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACT_BIT_RSS - }, - /* cond_execute: class_tid: 4, control.0 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_CC - } -}; - -struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { - /* class_tid: 1, thor, table: port_table.rd */ - { - .field_info_mask = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_rd */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam.gre */ - { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_GRE} - } - }, - { - .field_info_mask = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_wr */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - /* class_tid: 1, thor, table: profile_tcam.gre */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 & 0xff} - } - }, - { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: wm.gre */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 47} - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: wm.gre_low */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 47} - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_rd */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ - { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 2} - }, - .field_info_spec = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_wr */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - /* class_tid: 1, thor, table: profile_tcam.gre_frag */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 16} - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 16} - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: wm.gre_frag */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 47} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: wm.gre_frag_low */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 47} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: mac_addr_cache.non_gre_rd */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ - { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 2} - }, - .field_info_spec = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: mac_addr_cache.wr */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_rd */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 1, thor, table: profile_tcam.icmpv4 */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L4_HDR_TYPE_ICMP} - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L4_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_wr */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 1, thor, table: wm.icmpv4 */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - 1}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - 58} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: wm.icmpv4_low */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - 1}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - 58} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_rd */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 1, thor, table: profile_tcam.icmpv6 */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L4_HDR_TYPE_ICMP} - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L4_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_wr */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 1, thor, table: wm.icmpv6 */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - 1}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - 58} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: wm.icmpv6_low */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - 1}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - 58} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: profile_tcam_cache.l3_l4_rd */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L4_HDR_TYPE_UDP} - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L4_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 1, thor, table: profile_tcam_cache.wr */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 1, thor, table: wm.l4 */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_IP_PROTO_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_IP_PROTO_UDP} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_HF, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_HF, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 1, thor, table: wm.l4_low */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_IP_PROTO_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_IP_PROTO_UDP} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_HF, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_HF, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 2, thor, table: port_table.rd */ - { - .field_info_mask = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } - }, - /* class_tid: 2, thor, table: mac_addr_cache.rd */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - /* class_tid: 2, thor, table: l2_cntxt_tcam.0 */ - { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 2} - }, - .field_info_spec = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 2, thor, table: mac_addr_cache.wr */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } - }, - { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } - }, - { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_RF, - .field_opr3 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - } - }, - /* class_tid: 2, thor, table: profile_tcam_cache.l3_l4_rd */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 2, thor, table: profile_tcam.l3_l4 */ - { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L4_HDR_TYPE_UDP} - } - }, - { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L4_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } - }, - { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } - }, - { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 2, thor, table: profile_tcam_cache.wr */ - { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } - }, - /* class_tid: 2, thor, table: wm.l4 */ - { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} - } - }, - { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - } - }, - { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_IP_PROTO_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_IP_PROTO_UDP} - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_HF, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_HF, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} - } - }, - { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } - }, - /* class_tid: 4, thor, table: port_table.wr_0 */ - { - .field_info_mask = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } - }, - /* class_tid: 4, thor, table: port_table.wr_1 */ - { - .field_info_mask = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } - }, - /* class_tid: 4, thor, table: port_table.rd */ - { - .field_info_mask = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } - } -}; - -struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { - /* class_tid: 1, thor, table: l2_cntxt_tcam.gre */ - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 & 0xff} - }, - { - .description = "ctxt_meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "def_ctxt_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} - }, - { - .description = "ctxt_opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam_cache.gre_wr */ - { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} - }, - { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "src_property_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: fkb_select.gre */ - { - .description = "l2_cntxt_id.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "parif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "spif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "svif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "lcos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rcyc_cnt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "loopback.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "tl3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tuntype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tflags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tids.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tqos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "terr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_ack.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_win.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_tsval.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_txecr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: profile_tcam.gre */ - { - .description = "wc_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 & 0xff} - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "em_key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "em_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: wm.gre */ - { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - /* class_tid: 1, thor, table: wm.gre_low */ - { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - }, - { - .description = "ctxt_meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "def_ctxt_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} - }, - { - .description = "ctxt_opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} - }, - /* class_tid: 1, thor, table: mac_addr_cache.gre_frag_wr */ - { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} - }, - { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "src_property_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: fkb_select.gre_frag */ - { - .description = "l2_cntxt_id.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "parif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "spif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "svif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "lcos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rcyc_cnt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "loopback.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "tl3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tuntype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tflags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tids.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tqos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "terr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "l4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_ack.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_win.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_tsval.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_txecr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: profile_tcam.gre_frag */ - { - .description = "wc_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} - }, - { - .description = "wc_search_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "em_key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "em_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "em_search_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: wm.gre_frag */ - { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - /* class_tid: 1, thor, table: wm.gre_frag_low */ - { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} - }, - { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - /* class_tid: 1, thor, table: l2_cntxt_tcam.0 */ - { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} - }, - { - .description = "ctxt_meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "def_ctxt_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} - }, - { - .description = "ctxt_opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} - }, - { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} - }, - /* class_tid: 1, thor, table: mac_addr_cache.wr */ - { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} - }, - { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "src_property_ptr", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - /* class_tid: 1, thor, table: fkb_select.icmpv4 */ - { - .description = "l2_cntxt_id.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "parif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "spif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "svif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "lcos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "meta.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "rcyc_cnt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "loopback.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "tl3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tl4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tuntype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tflags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tids.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tctxt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "tqos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "terr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 242, + .result_bit_size = 128, + .result_num_fields = 17 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { + /* cond_reject: thor, class_tid: 1 */ { - .description = "l2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .description = "l2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, { - .description = "l2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH, + .cond_operand = 2 }, { - .description = "l2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH, + .cond_operand = 3 }, + /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ { - .description = "l2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* cond_execute: class_tid: 1, control.0 */ { - .description = "l2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* cond_execute: class_tid: 1, control.l3_l4 */ { - .description = "l2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* cond_execute: class_tid: 1, wm.l3_l4 */ { - .description = "l2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_L4 }, + /* cond_reject: thor, class_tid: 3 */ { - .description = "l2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, + /* cond_execute: class_tid: 3, control.ing_0 */ { - .description = "l2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* cond_execute: class_tid: 3, control.egr_0 */ { - .description = "l3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, + /* cond_execute: class_tid: 3, control.egr_1 */ { - .description = "l3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* cond_reject: thor, class_tid: 4 */ { - .description = "l3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + } +}; + +struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { + /* class_tid: 1, , table: port_table.rd */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } }, + /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */ { - .description = "l3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } }, + /* class_tid: 1, , table: mac_addr_cache.rd */ { - .description = "l3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } }, { - .description = "l3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } }, { - .description = "l3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } }, + /* class_tid: 1, , table: l2_cntxt_tcam.0 */ { - .description = "l3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } }, { - .description = "l3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } }, { - .description = "l4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } }, { - .description = "l4_ack.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_win.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "l4_tsval.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } }, + /* class_tid: 1, , table: mac_addr_cache.wr */ { - .description = "l4_txecr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } }, { - .description = "l4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_TUN_HDR_TYPE_NONE} + } }, - /* class_tid: 1, thor, table: profile_tcam.icmpv4 */ { - .description = "wc_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "wc_search_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } }, + /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */ { - .description = "em_key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "em_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } }, { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } }, + /* class_tid: 1, , table: profile_tcam.l3_l4 */ { - .description = "em_search_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, - /* class_tid: 1, thor, table: profile_tcam_cache.icmpv4_wr */ { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} + } }, { - .description = "profile_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ieh", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "em_key_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "wc_key_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "flow_sig_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, - /* class_tid: 1, thor, table: wm.icmpv4 */ { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L3_HDR_VALID_YES} + } }, { - .description = "meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, - /* class_tid: 1, thor, table: wm.icmpv4_low */ { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_L2_HDR_VALID_YES} + } }, { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, - /* class_tid: 1, thor, table: fkb_select.icmpv6 */ { - .description = "l2_cntxt_id.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "parif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "spif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "svif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "lcos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "meta.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "rcyc_cnt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "loopback.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } }, { - .description = "tl2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_0", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type_1", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } }, + /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */ { - .description = "tl3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + } }, { - .description = "tl3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } }, + /* class_tid: 1, , table: wm.l3_l4 */ { - .description = "tl3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff} + } }, { - .description = "tl3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } }, { - .description = "tl3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "lcos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tl4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tuntype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tflags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tids.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tctxts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tctxt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "tqos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "terr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl3.l3err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tl4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tuntype", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tflags", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxts", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tctxt", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "tqos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "terr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_l2type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_dt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_sa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_nvt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_ack.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ovt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_win.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivd", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_ivt", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_tsval.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_txecr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "l4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + } }, - /* class_tid: 1, thor, table: profile_tcam.icmpv6 */ { - .description = "wc_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff} + .field_info_mask = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.sip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "wc_search_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + } }, { - .description = "em_key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "em_key_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.dip_selcmp.ipv6", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "em_search_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff} + } }, { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv4", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, - /* class_tid: 1, thor, table: profile_tcam_cache.icmpv6_wr */ { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + .field_info_mask = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.fid.ipv6", + .field_bit_size = 20, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "profile_tcam_index", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_nonext", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "em_key_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_esp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_auth", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "wc_key_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "flow_sig_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, - /* class_tid: 1, thor, table: wm.icmpv6 */ { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_rthdr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_hop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.ieh_1frag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_info_mask = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.df", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv4", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, - /* class_tid: 1, thor, table: wm.icmpv6_low */ { - .description = "ctxt_data", - .field_bit_size = 14, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l3.l3err.ipv6", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "meta_prof", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.l4type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "opcode", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_HF, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff} + } }, { - .description = "data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_info_mask = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "strength", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.seq", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, - /* class_tid: 1, thor, table: fkb_select.l3_l4_wm */ { - .description = "l2_cntxt_id.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.ack", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "parif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.win", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "spif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.pa", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "svif.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.opt", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "lcos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tcpts", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "meta.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.tsval", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "rcyc_cnt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.txecr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, { - .description = "loopback.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + }, + .field_info_spec = { + .description = "l4.err", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SKIP + } }, + /* class_tid: 3, , table: port_table.wr_0 */ { - .description = "tl2_l2type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ { - .description = "tl2_dmac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } }, + /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ { - .description = "tl2_smac.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_dt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_sa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_nvt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ovp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ovd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ovv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ovt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ivp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ivd.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ivv.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_ivt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl2_etype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_l3type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_sip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } }, { - .description = "tl3_sip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_dip.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_dip_selcmp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_ttl.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_prot.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_fid.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ { - .description = "tl3_qos.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */ { - .description = "tl3_ieh_nonext.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } }, + /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ { - .description = "tl3_ieh_esp.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_ieh_auth.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_ieh_dest.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_ieh_frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_ieh_rthdr.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_ieh_hop.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_ieh_1frag.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_df.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl3_l3err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl4_l4type.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl4_src.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl4_dst.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl4_flags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl4_seq.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl4_pa.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } }, { - .description = "tl4_opt.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl4_tcpts.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tl4_err.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tuntype.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tflags.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } }, { - .description = "tids.en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { + /* class_tid: 1, , table: l2_cntxt_tcam.0 */ + { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { - .description = "tid.en", - .field_bit_size = 1, + .description = "ctxt_meta_prof", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tctxts.en", - .field_bit_size = 1, + .description = "def_ctxt_data", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, { - .description = "tctxt.en", - .field_bit_size = 1, + .description = "ctxt_opcode", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} }, { - .description = "tqos.en", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "terr.en", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, + /* class_tid: 1, , table: mac_addr_cache.wr */ { - .description = "l2_l2type.en", - .field_bit_size = 1, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "l2_dmac.en", - .field_bit_size = 1, + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_smac.en", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "l2_dt.en", - .field_bit_size = 1, + .description = "src_property_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, , table: fkb_select.l3_l4_wm */ { - .description = "l2_sa.en", + .description = "l2_cntxt_id.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "l2_nvt.en", + .description = "parif.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovp.en", + .description = "spif.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovd.en", + .description = "svif.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovv.en", + .description = "lcos.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovt.en", + .description = "meta.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivp.en", + .description = "rcyc_cnt.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivd.en", + .description = "loopback.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivv.en", + .description = "tl2_l2type.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivt.en", + .description = "tl2_dmac.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_etype.en", + .description = "tl2_smac.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_l3type.en", + .description = "tl2_dt.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_sip.en", + .description = "tl2_sa.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_sip_selcmp.en", + .description = "tl2_nvt.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_dip.en", + .description = "tl2_ovp.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_dip_selcmp.en", + .description = "tl2_ovd.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ttl.en", + .description = "tl2_ovv.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_prot.en", + .description = "tl2_ovt.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_fid.en", + .description = "tl2_ivp.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_qos.en", + .description = "tl2_ivd.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_nonext.en", + .description = "tl2_ivv.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_esp.en", + .description = "tl2_ivt.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_auth.en", + .description = "tl2_etype.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_dest.en", + .description = "tl3_l3type.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_frag.en", + .description = "tl3_sip.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_rthdr.en", + .description = "tl3_sip_selcmp.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_hop.en", + .description = "tl3_dip.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_1frag.en", + .description = "tl3_dip_selcmp.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_df.en", + .description = "tl3_ttl.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_l3err.en", + .description = "tl3_prot.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_l4type.en", + .description = "tl3_fid.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_src.en", + .description = "tl3_qos.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_dst.en", + .description = "tl3_ieh_nonext.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_flags.en", + .description = "tl3_ieh_esp.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_seq.en", + .description = "tl3_ieh_auth.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_ack.en", + .description = "tl3_ieh_dest.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_win.en", + .description = "tl3_ieh_frag.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_pa.en", + .description = "tl3_ieh_rthdr.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_opt.en", + .description = "tl3_ieh_hop.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_tcpts.en", + .description = "tl3_ieh_1frag.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_tsval.en", + .description = "tl3_df.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_txecr.en", + .description = "tl3_l3err.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_err.en", + .description = "tl4_l4type.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: profile_tcam.l3_l4 */ { - .description = "wc_key_id", - .field_bit_size = 6, + .description = "tl4_src.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_search_en", + .description = "tl4_dst.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_type", - .field_bit_size = 2, + .description = "tl4_flags.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 6, + .description = "tl4_seq.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl4_pa.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_search_en", + .description = "tl4_opt.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pl_byp_lkup_en", + .description = "tl4_tcpts.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: profile_tcam_cache.wr */ { - .description = "rid", - .field_bit_size = 32, + .description = "tl4_err.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "profile_tcam_index", - .field_bit_size = 10, + .description = "tuntype.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tflags.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 8, + .description = "tids.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "tid.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_key_id", - .field_bit_size = 8, + .description = "tctxts.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "flow_sig_id", - .field_bit_size = 8, + .description = "tctxt.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: wm.l4 */ { - .description = "ctxt_data", - .field_bit_size = 14, + .description = "tqos.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meta_prof", - .field_bit_size = 3, + .description = "terr.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "opcode", - .field_bit_size = 3, + .description = "l2_l2type.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "data", - .field_bit_size = 16, + .description = "l2_dmac.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "l2_smac.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, thor, table: wm.l4_low */ { - .description = "ctxt_data", - .field_bit_size = 14, + .description = "l2_dt.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meta_prof", - .field_bit_size = 3, + .description = "l2_sa.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "opcode", - .field_bit_size = 3, + .description = "l2_nvt.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "data", - .field_bit_size = 16, + .description = "l2_ovp.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "l2_ovd.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, thor, table: l2_cntxt_tcam.0 */ { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l2_ovv.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ctxt_meta_prof", - .field_bit_size = 3, + .description = "l2_ovt.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "def_ctxt_data", - .field_bit_size = 16, + .description = "l2_ivp.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ctxt_opcode", - .field_bit_size = 3, + .description = "l2_ivd.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} - }, - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PHY_PORT >> 8) & 0xff, - BNXT_ULP_RF_IDX_PHY_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "parif", - .field_bit_size = 4, + .description = "l2_ivv.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, thor, table: mac_addr_cache.wr */ { - .description = "rid", - .field_bit_size = 32, + .description = "l2_ivt.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "l2_etype.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l3_l3type.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "l3_sip.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l3_sip_selcmp.en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, thor, table: fkb_select.l3_l4_wm */ { - .description = "l2_cntxt_id.en", + .description = "l3_dip.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -27997,795 +4872,876 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { 1} }, { - .description = "parif.en", + .description = "l3_dip_selcmp.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "spif.en", + .description = "l3_ttl.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "svif.en", + .description = "l3_prot.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "lcos.en", + .description = "l3_fid.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meta.en", + .description = "l3_qos.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "rcyc_cnt.en", + .description = "l3_ieh_nonext.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "loopback.en", + .description = "l3_ieh_esp.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_l2type.en", + .description = "l3_ieh_auth.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_dmac.en", + .description = "l3_ieh_dest.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_smac.en", + .description = "l3_ieh_frag.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_dt.en", + .description = "l3_ieh_rthdr.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_sa.en", + .description = "l3_ieh_hop.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_nvt.en", + .description = "l3_ieh_1frag.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_ovp.en", + .description = "l3_df.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_ovd.en", + .description = "l3_l3err.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_ovv.en", + .description = "l4_l4type.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_ovt.en", + .description = "l4_src.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tl2_ivp.en", + .description = "l4_dst.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tl2_ivd.en", + .description = "l4_flags.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_ivv.en", + .description = "l4_seq.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_ivt.en", + .description = "l4_ack.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl2_etype.en", + .description = "l4_win.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_l3type.en", + .description = "l4_pa.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_sip.en", + .description = "l4_opt.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_sip_selcmp.en", + .description = "l4_tcpts.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_dip.en", + .description = "l4_tsval.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_dip_selcmp.en", + .description = "l4_txecr.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ttl.en", + .description = "l4_err.en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, , table: profile_tcam.l3_l4 */ { - .description = "tl3_prot.en", - .field_bit_size = 1, + .description = "wc_key_id", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff} }, { - .description = "tl3_fid.en", - .field_bit_size = 1, + .description = "wc_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff} }, { - .description = "tl3_qos.en", + .description = "wc_search_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "tl3_ieh_nonext.en", - .field_bit_size = 1, + .description = "em_key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ieh_esp.en", - .field_bit_size = 1, + .description = "em_key_id", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ieh_auth.en", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ieh_dest.en", + .description = "em_search_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ieh_frag.en", + .description = "pl_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */ { - .description = "tl3_ieh_rthdr.en", - .field_bit_size = 1, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "tl3_ieh_hop.en", - .field_bit_size = 1, + .description = "profile_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_ieh_1frag.en", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_df.en", - .field_bit_size = 1, + .description = "em_key_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl3_l3err.en", - .field_bit_size = 1, + .description = "wc_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl4_l4type.en", - .field_bit_size = 1, + .description = "wc_key_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl4_src.en", - .field_bit_size = 1, + .description = "flow_sig_id", + .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, + /* class_tid: 1, , table: wm.l3_l4 */ { - .description = "tl4_dst.en", - .field_bit_size = 1, + .description = "ctxt_data", + .field_bit_size = 14, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl4_flags.en", - .field_bit_size = 1, + .description = "meta_prof", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl4_seq.en", - .field_bit_size = 1, + .description = "opcode", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl4_pa.en", - .field_bit_size = 1, + .description = "data", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "tl4_opt.en", - .field_bit_size = 1, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 3, , table: int_full_act_record.0 */ { - .description = "tl4_tcpts.en", - .field_bit_size = 1, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tl4_err.en", - .field_bit_size = 1, + .description = "encap_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tuntype.en", - .field_bit_size = 1, + .description = "mod_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tflags.en", - .field_bit_size = 1, + .description = "rsvd1", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tids.en", - .field_bit_size = 1, + .description = "rsvd0", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tid.en", - .field_bit_size = 1, + .description = "decap_func", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tctxts.en", - .field_bit_size = 1, + .description = "meter", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tctxt.en", + .description = "stats_op", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tqos.en", - .field_bit_size = 1, + .description = "stats_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "terr.en", + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + }, + { + .description = "use_default", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_l2type.en", - .field_bit_size = 1, + .description = "mirror", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_dmac.en", + .description = "cond_copy", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_smac.en", - .field_bit_size = 1, + .description = "vlan_del_rpt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_dt.en", + .description = "drop", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_sa.en", + .description = "hit", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_nvt.en", - .field_bit_size = 1, + .description = "type", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 3, , table: port_table.wr_0 */ { - .description = "l2_ovp.en", - .field_bit_size = 1, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovd.en", - .field_bit_size = 1, + .description = "drv_func.mac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovv.en", - .field_bit_size = 1, + .description = "drv_func.parent.mac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ovt.en", - .field_bit_size = 1, + .description = "phy_port", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivp.en", - .field_bit_size = 1, + .description = "default_arec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, + /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ { - .description = "l2_ivd.en", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { - .description = "l2_ivv.en", - .field_bit_size = 1, + .description = "ctxt_meta_prof", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_ivt.en", - .field_bit_size = 1, + .description = "def_ctxt_data", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, { - .description = "l2_etype.en", - .field_bit_size = 1, + .description = "ctxt_opcode", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} }, { - .description = "l3_l3type.en", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "l3_sip.en", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ { - .description = "l3_sip_selcmp.en", - .field_bit_size = 1, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "l3_dip.en", - .field_bit_size = 1, + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} }, { - .description = "l3_dip_selcmp.en", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "l3_ttl.en", - .field_bit_size = 1, + .description = "src_property_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ { - .description = "l3_prot.en", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 1} + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, + /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ { - .description = "l3_fid.en", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, + /* class_tid: 3, , table: int_full_act_record.egr_0 */ { - .description = "l3_qos.en", - .field_bit_size = 1, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_nonext.en", - .field_bit_size = 1, + .description = "encap_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_esp.en", - .field_bit_size = 1, + .description = "mod_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_auth.en", - .field_bit_size = 1, + .description = "rsvd1", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_dest.en", - .field_bit_size = 1, + .description = "rsvd0", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_frag.en", - .field_bit_size = 1, + .description = "decap_func", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_rthdr.en", - .field_bit_size = 1, + .description = "meter", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_hop.en", + .description = "stats_op", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_ieh_1frag.en", - .field_bit_size = 1, + .description = "stats_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_df.en", - .field_bit_size = 1, + .description = "vnic_or_vport", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} }, { - .description = "l3_l3err.en", + .description = "use_default", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_l4type.en", - .field_bit_size = 1, + .description = "mirror", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_src.en", + .description = "cond_copy", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_dst.en", - .field_bit_size = 1, + .description = "vlan_del_rpt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_flags.en", + .description = "drop", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_seq.en", + .description = "hit", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_ack.en", - .field_bit_size = 1, + .description = "type", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ { - .description = "l4_win.en", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} }, { - .description = "l4_pa.en", - .field_bit_size = 1, + .description = "ctxt_meta_prof", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l4_opt.en", - .field_bit_size = 1, + .description = "def_ctxt_data", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "l4_tcpts.en", - .field_bit_size = 1, + .description = "ctxt_opcode", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW} }, { - .description = "l4_tsval.en", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "l4_txecr.en", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, + /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ { - .description = "l4_err.en", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 2, thor, table: profile_tcam.l3_l4 */ + /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ { - .description = "wc_key_id", - .field_bit_size = 6, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, + /* class_tid: 4, , table: int_full_act_record.loopback */ { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 & 0xff} + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_search_en", - .field_bit_size = 1, + .description = "encap_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_type", - .field_bit_size = 2, + .description = "mod_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 6, + .description = "rsvd1", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", + .description = "rsvd0", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_search_en", - .field_bit_size = 1, + .description = "decap_func", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, + .description = "meter", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, thor, table: profile_tcam_cache.wr */ { - .description = "rid", - .field_bit_size = 32, + .description = "stats_op", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "profile_tcam_index", - .field_bit_size = 10, + .description = "stats_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "vnic_or_vport", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_THOR_SYM_LOOPBACK_PORT & 0xff} }, { - .description = "em_key_id", - .field_bit_size = 8, + .description = "use_default", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "mirror", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_key_id", - .field_bit_size = 8, + .description = "cond_copy", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "flow_sig_id", - .field_bit_size = 8, + .description = "vlan_del_rpt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, thor, table: wm.l4 */ { - .description = "ctxt_data", - .field_bit_size = 14, + .description = "drop", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "meta_prof", - .field_bit_size = 3, + .description = "hit", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "opcode", + .description = "type", .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ { - .description = "data", - .field_bit_size = 16, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, + /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ { - .description = "strength", - .field_bit_size = 2, + .description = "act_rec_ptr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, thor, table: int_full_act_record.0 */ + /* class_tid: 4, , table: int_full_act_record.vf_ing */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -28844,10 +5800,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .description = "vnic_or_vport", .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC >> 8) & 0xff, - BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC & 0xff} + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} }, { .description = "use_default", @@ -28893,44 +5849,87 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 4, thor, table: port_table.wr_0 */ + /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */ { - .description = "rid", - .field_bit_size = 32, + .description = "ecv_tun_type", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drv_func.mac", - .field_bit_size = 48, + .description = "ecv_l4_type", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "drv_func.parent.mac", - .field_bit_size = 48, + .description = "ecv_l3_type", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} + ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI} }, { - .description = "phy_port", - .field_bit_size = 8, + .description = "rsrvd", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_arec_ptr", + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vtag_tpid", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 0x81, + 0x00} + }, + { + .description = "vtag_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + }, + { + .description = "vtag_de", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vtag_pcp", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 & 0xff} + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, - /* class_tid: 4, thor, table: int_full_act_record.1 */ + /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -28941,7 +5940,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .description = "encap_ptr", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, { .description = "mod_rec_ptr", @@ -28989,10 +5991,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .description = "vnic_or_vport", .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC >> 8) & 0xff, - BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC & 0xff} + (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_THOR_SYM_LOOPBACK_PORT & 0xff} }, { .description = "use_default", @@ -29037,70 +6039,11 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} - }, - /* class_tid: 4, thor, table: port_table.wr_1 */ - { - .description = "rid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "drv_func.mac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "drv_func.parent.mac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff} - }, - { - .description = "phy_port", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - { - .description = "default_arec_ptr", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 & 0xff} - }, - /* class_tid: 4, thor, table: parif_def_arec_ptr.ing_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} - }, - /* class_tid: 4, thor, table: parif_def_err_arec_ptr.ing_0 */ - { - .description = "act_rec_ptr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} } }; struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { - /* class_tid: 1, thor, table: port_table.rd */ + /* class_tid: 1, , table: port_table.rd */ { .description = "default_arec_ptr", .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, @@ -29119,53 +6062,30 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 128 }, - /* class_tid: 1, thor, table: l2_cntxt_tcam.gre */ + /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */ { .description = "l2_cntxt_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 29 + .ident_bit_pos = 42 }, - /* class_tid: 1, thor, table: profile_tcam.icmpv4 */ + /* class_tid: 1, , table: mac_addr_cache.rd */ { - .description = "em_profile_id", - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 23 + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 }, - /* class_tid: 1, thor, table: profile_tcam.icmpv6 */ + /* class_tid: 1, , table: l2_cntxt_tcam.0 */ { - .description = "em_profile_id", + .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_EM_PROF, - .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, - .ident_bit_size = 8, - .ident_bit_pos = 23 - }, - /* class_tid: 2, thor, table: port_table.rd */ - { - .description = "default_arec_ptr", - .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, - .ident_bit_size = 16, - .ident_bit_pos = 136 - }, - { - .description = "drv_func.parent.mac", - .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC, - .ident_bit_size = 48, - .ident_bit_pos = 80 - }, - { - .description = "phy_port", - .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT, - .ident_bit_size = 8, - .ident_bit_pos = 128 + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 29 }, - /* class_tid: 2, thor, table: l2_cntxt_tcam.0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -29174,12 +6094,14 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 29 }, - /* class_tid: 4, thor, table: port_table.rd */ + /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ { - .description = "default_arec_ptr", - .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, - .ident_bit_size = 16, - .ident_bit_pos = 136 + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 29 } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 9e0a6b5c18..b6d2afd55b 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Sun Mar 21 13:04:51 2021 */ +/* date: Thu May 13 18:15:56 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -12,7 +12,7 @@ /* Mapper templates for header act list */ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { - /* act_tid: 1, wh_plus, ingress */ + /* act_tid: 1, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, @@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .cond_start_idx = 0, .cond_nums = 9 } }, - /* act_tid: 2, wh_plus, ingress */ + /* act_tid: 2, ingress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 7, @@ -32,7 +32,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .cond_start_idx = 14, .cond_nums = 0 } }, - /* act_tid: 3, wh_plus, ingress */ + /* act_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, @@ -42,7 +42,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .cond_start_idx = 15, .cond_nums = 0 } }, - /* act_tid: 4, wh_plus, egress */ + /* act_tid: 4, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, @@ -52,7 +52,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .cond_start_idx = 20, .cond_nums = 0 } }, - /* act_tid: 5, wh_plus, egress */ + /* act_tid: 5, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, @@ -62,7 +62,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { .cond_start_idx = 28, .cond_nums = 0 } }, - /* act_tid: 6, wh_plus, egress */ + /* act_tid: 6, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, @@ -75,7 +75,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { - { /* act_tid: 1, wh_plus, table: shared_mirror_record.rd */ + { /* act_tid: 1, , table: shared_mirror_record.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .resource_sub_type = @@ -98,7 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .ident_start_idx = 0, .ident_nums = 1 }, - { /* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */ + { /* act_tid: 1, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -119,7 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 1 }, - { /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ + { /* act_tid: 1, , table: int_vtag_encap_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = @@ -141,7 +141,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12 }, - { /* act_tid: 1, wh_plus, table: int_full_act_record.0 */ + { /* act_tid: 1, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -163,7 +163,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0 }, - { /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */ + { /* act_tid: 1, , table: ext_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = @@ -185,7 +185,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 12 }, - { /* act_tid: 2, wh_plus, table: control.0 */ + { /* act_tid: 2, , table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -198,7 +198,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ + { /* act_tid: 2, , table: mirror_tbl.alloc */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .resource_sub_type = @@ -220,7 +220,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 6 }, - { /* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */ + { /* act_tid: 2, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -242,7 +242,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 1 }, - { /* act_tid: 2, wh_plus, table: int_full_act_record.0 */ + { /* act_tid: 2, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -265,7 +265,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0 }, - { /* act_tid: 2, wh_plus, table: ext_full_act_record.0 */ + { /* act_tid: 2, , table: ext_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = @@ -288,7 +288,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 12 }, - { /* act_tid: 2, wh_plus, table: mirror_tbl.wr */ + { /* act_tid: 2, , table: mirror_tbl.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .resource_sub_type = @@ -309,7 +309,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 6 }, - { /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ + { /* act_tid: 2, , table: shared_mirror_record.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, .resource_sub_type = @@ -333,7 +333,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 34, .result_num_fields = 2 }, - { /* act_tid: 3, wh_plus, table: int_flow_counter_tbl.0 */ + { /* act_tid: 3, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -353,7 +353,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 1 }, - { /* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */ + { /* act_tid: 3, , table: act_modify_ipv4_src.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = @@ -373,7 +373,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */ + { /* act_tid: 3, , table: act_modify_ipv4_dst.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = @@ -393,7 +393,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */ + { /* act_tid: 3, , table: int_encap_mac_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = @@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12 }, - { /* act_tid: 3, wh_plus, table: int_full_act_record.0 */ + { /* act_tid: 3, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -434,7 +434,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 26 }, - { /* act_tid: 3, wh_plus, table: ext_full_act_record.0 */ + { /* act_tid: 3, , table: ext_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = @@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 12 }, - { /* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */ + { /* act_tid: 4, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -475,7 +475,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 1 }, - { /* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */ + { /* act_tid: 4, , table: int_vtag_encap_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = @@ -496,7 +496,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12 }, - { /* act_tid: 4, wh_plus, table: int_full_act_record.0 */ + { /* act_tid: 4, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -516,7 +516,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 26 }, - { /* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */ + { /* act_tid: 4, , table: ext_full_act_record.no_tag */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = @@ -537,7 +537,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 12 }, - { /* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */ + { /* act_tid: 4, , table: ext_full_act_record.one_tag */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = @@ -558,7 +558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 12 }, - { /* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */ + { /* act_tid: 5, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -578,7 +578,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 1 }, - { /* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */ + { /* act_tid: 5, , table: act_modify_ipv4_src.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = @@ -598,7 +598,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */ + { /* act_tid: 5, , table: act_modify_ipv4_dst.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, .resource_sub_type = @@ -618,7 +618,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* act_tid: 5, wh_plus, table: int_encap_mac_record.dummy */ + { /* act_tid: 5, , table: int_encap_mac_record.dummy */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, .resource_sub_type = @@ -639,7 +639,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12 }, - { /* act_tid: 5, wh_plus, table: int_full_act_record.0 */ + { /* act_tid: 5, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -659,7 +659,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 26 }, - { /* act_tid: 5, wh_plus, table: ext_full_act_record.0 */ + { /* act_tid: 5, , table: ext_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = @@ -680,7 +680,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 12 }, - { /* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */ + { /* act_tid: 6, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, .resource_sub_type = @@ -700,7 +700,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 1 }, - { /* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */ + { /* act_tid: 6, , table: sp_smac_ipv4.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, .resource_sub_type = @@ -721,7 +721,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 3 }, - { /* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */ + { /* act_tid: 6, , table: sp_smac_ipv6.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, .resource_sub_type = @@ -742,7 +742,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 3 }, - { /* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */ + { /* act_tid: 6, , table: int_tun_encap_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, .resource_sub_type = @@ -763,7 +763,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12 }, - { /* act_tid: 6, wh_plus, table: int_full_act_record.0 */ + { /* act_tid: 6, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -783,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 26 }, - { /* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */ + { /* act_tid: 6, , table: ext_full_act_record_vxlan.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EXT, .resource_sub_type = @@ -981,7 +981,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { }; struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { - /* act_tid: 1, wh_plus, table: shared_mirror_record.rd */ + /* act_tid: 1, , table: shared_mirror_record.rd */ { .field_info_mask = { .description = "shared_index", @@ -1001,7 +1001,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} } }, - /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ + /* act_tid: 2, , table: shared_mirror_record.wr */ { .field_info_mask = { .description = "shared_index", @@ -1024,14 +1024,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = { }; struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { - /* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */ + /* act_tid: 1, , table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */ + /* act_tid: 1, , table: int_vtag_encap_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -1117,7 +1117,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 1, wh_plus, table: int_full_act_record.0 */ + /* act_tid: 1, , table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -1379,7 +1379,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */ + /* act_tid: 1, , table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -1701,7 +1701,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */ + /* act_tid: 2, , table: mirror_tbl.alloc */ { .description = "act_rec_ptr", .field_bit_size = 16, @@ -1740,14 +1740,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */ + /* act_tid: 2, , table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 2, wh_plus, table: int_full_act_record.0 */ + /* act_tid: 2, , table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -1921,7 +1921,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 2, wh_plus, table: ext_full_act_record.0 */ + /* act_tid: 2, , table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -2178,7 +2178,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 2, wh_plus, table: mirror_tbl.wr */ + /* act_tid: 2, , table: mirror_tbl.wr */ { .description = "act_rec_ptr", .field_bit_size = 16, @@ -2220,7 +2220,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 2, wh_plus, table: shared_mirror_record.wr */ + /* act_tid: 2, , table: shared_mirror_record.wr */ { .description = "rid", .field_bit_size = 32, @@ -2239,14 +2239,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (1 >> 8) & 0xff, 1 & 0xff} }, - /* act_tid: 3, wh_plus, table: int_flow_counter_tbl.0 */ + /* act_tid: 3, , table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */ + /* act_tid: 3, , table: act_modify_ipv4_src.0 */ { .description = "ipv4_addr", .field_bit_size = 32, @@ -2256,7 +2256,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff} }, - /* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */ + /* act_tid: 3, , table: act_modify_ipv4_dst.0 */ { .description = "ipv4_addr", .field_bit_size = 32, @@ -2266,7 +2266,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} }, - /* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */ + /* act_tid: 3, , table: int_encap_mac_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -2343,7 +2343,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 3, wh_plus, table: int_full_act_record.0 */ + /* act_tid: 3, , table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -2573,7 +2573,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 3, wh_plus, table: ext_full_act_record.0 */ + /* act_tid: 3, , table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -2879,14 +2879,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */ + /* act_tid: 4, , table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */ + /* act_tid: 4, , table: int_vtag_encap_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -2972,7 +2972,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 4, wh_plus, table: int_full_act_record.0 */ + /* act_tid: 4, , table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -3162,7 +3162,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */ + /* act_tid: 4, , table: ext_full_act_record.no_tag */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -3423,7 +3423,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */ + /* act_tid: 4, , table: ext_full_act_record.one_tag */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -3704,14 +3704,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */ + /* act_tid: 5, , table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */ + /* act_tid: 5, , table: act_modify_ipv4_src.0 */ { .description = "ipv4_addr", .field_bit_size = 32, @@ -3721,7 +3721,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff} }, - /* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */ + /* act_tid: 5, , table: act_modify_ipv4_dst.0 */ { .description = "ipv4_addr", .field_bit_size = 32, @@ -3731,7 +3731,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff} }, - /* act_tid: 5, wh_plus, table: int_encap_mac_record.dummy */ + /* act_tid: 5, , table: int_encap_mac_record.dummy */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -3808,7 +3808,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 5, wh_plus, table: int_full_act_record.0 */ + /* act_tid: 5, , table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -4038,7 +4038,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 5, wh_plus, table: ext_full_act_record.0 */ + /* act_tid: 5, , table: ext_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -4344,14 +4344,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */ + /* act_tid: 6, , table: int_flow_counter_tbl.0 */ { .description = "count", .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */ + /* act_tid: 6, , table: sp_smac_ipv4.0 */ { .description = "smac", .field_bit_size = 48, @@ -4376,7 +4376,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */ + /* act_tid: 6, , table: sp_smac_ipv6.0 */ { .description = "smac", .field_bit_size = 48, @@ -4401,7 +4401,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */ + /* act_tid: 6, , table: int_tun_encap_record.0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -4509,7 +4509,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff} }, - /* act_tid: 6, wh_plus, table: int_full_act_record.0 */ + /* act_tid: 6, , table: int_full_act_record.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -4684,7 +4684,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */ + /* act_tid: 6, , table: ext_full_act_record_vxlan.0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -4964,7 +4964,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { }; struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[] = { - /* act_tid: 1, wh_plus, table: shared_mirror_record.rd */ + /* act_tid: 1, , table: shared_mirror_record.rd */ { .description = "mirror_id", .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c index fa3c3507b6..85b8950e49 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Apr 14 09:56:27 2021 */ +/* date: Fri May 14 10:26:31 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -12,7 +12,7 @@ /* Mapper templates for header class list */ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { - /* class_tid: 1, wh_plus, ingress */ + /* class_tid: 1, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 18, @@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .cond_start_idx = 0, .cond_nums = 1 } }, - /* class_tid: 2, wh_plus, egress */ + /* class_tid: 2, egress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 15, @@ -32,7 +32,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .cond_start_idx = 24, .cond_nums = 1 } }, - /* class_tid: 3, wh_plus, ingress */ + /* class_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 22, @@ -42,7 +42,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .cond_start_idx = 35, .cond_nums = 0 } }, - /* class_tid: 4, wh_plus, egress */ + /* class_tid: 4, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 19, @@ -55,7 +55,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { }; struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { - { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = @@ -78,7 +78,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 0, .ident_nums = 1 }, - { /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ + { /* class_tid: 1, , table: mac_addr_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, @@ -100,7 +100,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 1, .ident_nums = 1 }, - { /* class_tid: 1, wh_plus, table: control.0 */ + { /* class_tid: 1, , table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -113,7 +113,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ + { /* class_tid: 1, , table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -140,7 +140,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 2, .ident_nums = 1 }, - { /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ + { /* class_tid: 1, , table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, @@ -163,7 +163,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ + { /* class_tid: 1, , table: profile_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = @@ -186,7 +186,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 3, .ident_nums = 3 }, - { /* class_tid: 1, wh_plus, table: control.1 */ + { /* class_tid: 1, , table: control.1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -199,7 +199,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 1, wh_plus, table: control.2 */ + { /* class_tid: 1, , table: control.2 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -218,7 +218,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .func_dst_opr = BNXT_ULP_RF_IDX_CC }, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ + { /* class_tid: 1, , table: profile_tcam.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -245,7 +245,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 6, .ident_nums = 1 }, - { /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ + { /* class_tid: 1, , table: profile_tcam.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -272,7 +272,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 7, .ident_nums = 1 }, - { /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ + { /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -299,7 +299,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 8, .ident_nums = 1 }, - { /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + { /* class_tid: 1, , table: profile_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = @@ -320,10 +320,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_bit_size = 14, .key_num_fields = 3, .result_start_idx = 68, - .result_bit_size = 90, + .result_bit_size = 122, .result_num_fields = 5 }, - { /* class_tid: 1, wh_plus, table: em.ipv4 */ + { /* class_tid: 1, , table: em.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, @@ -345,7 +345,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: eem.ipv4 */ + { /* class_tid: 1, , table: eem.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, @@ -367,7 +367,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: em.ipv6 */ + { /* class_tid: 1, , table: em.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, @@ -389,7 +389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: eem.ipv6 */ + { /* class_tid: 1, , table: eem.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, @@ -411,7 +411,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: em.vxlan */ + { /* class_tid: 1, , table: em.vxlan */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, @@ -433,7 +433,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 1, wh_plus, table: eem.vxlan */ + { /* class_tid: 1, , table: eem.vxlan */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_RX, @@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -477,7 +477,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 9, .ident_nums = 1 }, - { /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ + { /* class_tid: 2, , table: mac_addr_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, @@ -499,7 +499,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 10, .ident_nums = 1 }, - { /* class_tid: 2, wh_plus, table: control.0 */ + { /* class_tid: 2, , table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { @@ -512,7 +512,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + { /* class_tid: 2, , table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, @@ -539,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 11, .ident_nums = 1 }, - { /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ + { /* class_tid: 2, , table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, @@ -562,7 +562,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ + { /* class_tid: 2, , table: profile_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, @@ -584,7 +584,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 12, .ident_nums = 3 }, - { /* class_tid: 2, wh_plus, table: control.gen_tbl_miss */ + { /* class_tid: 2, , table: control.gen_tbl_miss */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { @@ -597,7 +597,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 2, wh_plus, table: control.conflict_check */ + { /* class_tid: 2, , table: control.conflict_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { @@ -616,7 +616,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .func_dst_opr = BNXT_ULP_RF_IDX_CC }, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ + { /* class_tid: 2, , table: profile_tcam.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -643,7 +643,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 15, .ident_nums = 1 }, - { /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ + { /* class_tid: 2, , table: profile_tcam.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -670,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 16, .ident_nums = 1 }, - { /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ + { /* class_tid: 2, , table: profile_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, @@ -690,10 +690,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .key_bit_size = 14, .key_num_fields = 3, .result_start_idx = 178, - .result_bit_size = 90, + .result_bit_size = 122, .result_num_fields = 5 }, - { /* class_tid: 2, wh_plus, table: em.ipv4 */ + { /* class_tid: 2, , table: em.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, @@ -715,7 +715,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, wh_plus, table: eem.ipv4 */ + { /* class_tid: 2, , table: eem.ipv4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, @@ -737,7 +737,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, wh_plus, table: em.ipv6 */ + { /* class_tid: 2, , table: em.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, @@ -759,7 +759,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, wh_plus, table: eem.ipv6 */ + { /* class_tid: 2, , table: eem.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, @@ -781,7 +781,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 3, wh_plus, table: int_full_act_record.ing_0 */ + { /* class_tid: 3, , table: int_full_act_record.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -802,7 +802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 26 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_rd */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -824,7 +824,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 17, .ident_nums = 0 }, - { /* class_tid: 3, wh_plus, table: control.ing_0 */ + { /* class_tid: 3, , table: control.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -837,7 +837,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ + { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -866,7 +866,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 17, .ident_nums = 1 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_wr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -889,7 +889,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.ing_0 */ + { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -907,7 +907,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.ing_0 */ + { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -925,7 +925,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.ing_0 */ + { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -943,7 +943,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, wh_plus, table: control.egr_0 */ + { /* class_tid: 3, , table: control.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -955,7 +955,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, wh_plus, table: int_full_act_record.egr_vfr */ + { /* class_tid: 3, , table: int_full_act_record.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -977,7 +977,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_rd_vfr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -999,7 +999,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 18, .ident_nums = 0 }, - { /* class_tid: 3, wh_plus, table: control.egr_1 */ + { /* class_tid: 3, , table: control.egr_1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -1012,7 +1012,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.egr_vfr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1039,7 +1039,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 18, .ident_nums = 0 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr_vfr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1062,7 +1062,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1084,7 +1084,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 18, .ident_nums = 0 }, - { /* class_tid: 3, wh_plus, table: control.egr_2 */ + { /* class_tid: 3, , table: control.egr_2 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -1097,7 +1097,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ + { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1124,7 +1124,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 18, .ident_nums = 1 }, - { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1147,7 +1147,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 3, wh_plus, table: int_full_act_record.egr_0 */ + { /* class_tid: 3, , table: int_full_act_record.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1169,7 +1169,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.egr_0 */ + { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1187,7 +1187,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.egr_0 */ + { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1205,7 +1205,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.egr_0 */ + { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1223,7 +1223,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.loopback */ + { /* class_tid: 4, , table: int_full_act_record.loopback */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1245,7 +1245,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_rd_egr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1267,7 +1267,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 19, .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: control.vf_0 */ + { /* class_tid: 4, , table: control.vf_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { @@ -1280,7 +1280,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ + { /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1307,7 +1307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 19, .ident_nums = 1 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_egr_wr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1330,7 +1330,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1348,7 +1348,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1366,7 +1366,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1384,7 +1384,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.vf_ing */ + { /* class_tid: 4, , table: int_full_act_record.vf_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1406,7 +1406,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vf_ing */ + { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1434,7 +1434,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 20, .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1456,7 +1456,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 20, .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: control.vfr_0 */ + { /* class_tid: 4, , table: control.vfr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { @@ -1469,7 +1469,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1496,7 +1496,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 20, .ident_nums = 0 }, - { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1519,7 +1519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 4, wh_plus, table: int_vtag_encap_record.vfr_egr0 */ + { /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = @@ -1541,7 +1541,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 12 }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_egr0 */ + { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1562,7 +1562,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 26 }, - { /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_ing0 */ + { /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1583,7 +1583,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 26 }, - { /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1611,7 +1611,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .ident_start_idx = 20, .ident_nums = 0 }, - { /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -1838,7 +1838,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { }; struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { .description = "svif", @@ -1859,7 +1859,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, - /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ + /* class_tid: 1, , table: mac_addr_cache.rd */ { .field_info_mask = { .description = "svif", @@ -1979,7 +1979,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 1, , table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -2215,7 +2215,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ + /* class_tid: 1, , table: mac_addr_cache.wr */ { .field_info_mask = { .description = "svif", @@ -2335,7 +2335,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ + /* class_tid: 1, , table: profile_tcam_cache.rd */ { .field_info_mask = { .description = "recycle_cnt", @@ -2398,7 +2398,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ + /* class_tid: 1, , table: profile_tcam.ipv4 */ { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", @@ -3080,7 +3080,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ + /* class_tid: 1, , table: profile_tcam.ipv6 */ { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", @@ -3764,7 +3764,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ + /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */ { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", @@ -4406,7 +4406,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + /* class_tid: 1, , table: profile_tcam_cache.wr */ { .field_info_mask = { .description = "recycle_cnt", @@ -4469,7 +4469,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 1, wh_plus, table: em.ipv4 */ + /* class_tid: 1, , table: em.ipv4 */ { .field_info_mask = { .description = "spare", @@ -4671,7 +4671,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: eem.ipv4 */ + /* class_tid: 1, , table: eem.ipv4 */ { .field_info_mask = { .description = "spare", @@ -4873,7 +4873,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: em.ipv6 */ + /* class_tid: 1, , table: em.ipv6 */ { .field_info_mask = { .description = "spare", @@ -5089,7 +5089,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: eem.ipv6 */ + /* class_tid: 1, , table: eem.ipv6 */ { .field_info_mask = { .description = "spare", @@ -5305,7 +5305,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: em.vxlan */ + /* class_tid: 1, , table: em.vxlan */ { .field_info_mask = { .description = "spare", @@ -5487,7 +5487,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 1, wh_plus, table: eem.vxlan */ + /* class_tid: 1, , table: eem.vxlan */ { .field_info_mask = { .description = "spare", @@ -5669,7 +5669,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { .description = "svif", @@ -5690,7 +5690,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, - /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ + /* class_tid: 2, , table: mac_addr_cache.rd */ { .field_info_mask = { .description = "svif", @@ -5810,7 +5810,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, , table: l2_cntxt_tcam.0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -6046,7 +6046,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ + /* class_tid: 2, , table: mac_addr_cache.wr */ { .field_info_mask = { .description = "svif", @@ -6166,7 +6166,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, - /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ + /* class_tid: 2, , table: profile_tcam_cache.rd */ { .field_info_mask = { .description = "recycle_cnt", @@ -6229,7 +6229,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ + /* class_tid: 2, , table: profile_tcam.ipv4 */ { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", @@ -6911,7 +6911,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ + /* class_tid: 2, , table: profile_tcam.ipv6 */ { .field_info_mask = { .description = "l4_hdr_is_udp_tcp", @@ -7595,7 +7595,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ + /* class_tid: 2, , table: profile_tcam_cache.wr */ { .field_info_mask = { .description = "recycle_cnt", @@ -7658,7 +7658,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, - /* class_tid: 2, wh_plus, table: em.ipv4 */ + /* class_tid: 2, , table: em.ipv4 */ { .field_info_mask = { .description = "spare", @@ -7860,7 +7860,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 2, wh_plus, table: eem.ipv4 */ + /* class_tid: 2, , table: eem.ipv4 */ { .field_info_mask = { .description = "spare", @@ -8062,7 +8062,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 2, wh_plus, table: em.ipv6 */ + /* class_tid: 2, , table: em.ipv6 */ { .field_info_mask = { .description = "spare", @@ -8278,7 +8278,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 2, wh_plus, table: eem.ipv6 */ + /* class_tid: 2, , table: eem.ipv6 */ { .field_info_mask = { .description = "spare", @@ -8494,7 +8494,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_rd */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ { .field_info_mask = { .description = "svif", @@ -8514,7 +8514,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -8665,17 +8665,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -8710,7 +8706,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_wr */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ { .field_info_mask = { .description = "svif", @@ -8730,7 +8726,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_rd_vfr */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ { .field_info_mask = { .description = "svif", @@ -8750,7 +8746,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.egr_vfr */ + /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -8901,17 +8897,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -8946,7 +8938,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr_vfr */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .field_info_mask = { .description = "svif", @@ -8966,7 +8958,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { .description = "svif", @@ -8986,7 +8978,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -9137,17 +9129,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9182,7 +9170,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ { .field_info_mask = { .description = "svif", @@ -9202,7 +9190,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_rd_egr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */ { .field_info_mask = { .description = "svif", @@ -9222,7 +9210,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ + /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -9373,17 +9361,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9418,7 +9402,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_egr_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ { .field_info_mask = { .description = "svif", @@ -9438,7 +9422,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vf_ing */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -9589,17 +9573,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9634,7 +9614,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ { .field_info_mask = { .description = "svif", @@ -9654,7 +9634,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_egr0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -9805,17 +9785,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -9850,7 +9826,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { .field_info_mask = { .description = "svif", @@ -9870,7 +9846,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -10031,17 +10007,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -10076,7 +10048,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .field_info_mask = { .description = "l2_ivlan_vid", @@ -10237,17 +10209,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -10285,7 +10253,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }; struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 1, , table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -10375,7 +10343,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: mac_addr_cache.wr */ + /* class_tid: 1, , table: mac_addr_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -10406,7 +10374,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ + /* class_tid: 1, , table: profile_tcam.ipv4 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -10552,7 +10520,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ + /* class_tid: 1, , table: profile_tcam.ipv6 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -10698,7 +10666,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ + /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */ { .description = "wc_key_id", .field_bit_size = 4, @@ -10816,7 +10784,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */ + /* class_tid: 1, , table: profile_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -10852,14 +10820,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }, { .description = "flow_sig_id", - .field_bit_size = 32, + .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, - /* class_tid: 1, wh_plus, table: em.ipv4 */ + /* class_tid: 1, , table: em.ipv4 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -10921,7 +10889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, wh_plus, table: eem.ipv4 */ + /* class_tid: 1, , table: eem.ipv4 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -10989,7 +10957,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, wh_plus, table: em.ipv6 */ + /* class_tid: 1, , table: em.ipv6 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11051,7 +11019,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, wh_plus, table: eem.ipv6 */ + /* class_tid: 1, , table: eem.ipv6 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11119,7 +11087,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, wh_plus, table: em.vxlan */ + /* class_tid: 1, , table: em.vxlan */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11181,7 +11149,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, wh_plus, table: eem.vxlan */ + /* class_tid: 1, , table: eem.vxlan */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11249,7 +11217,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, , table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -11349,7 +11317,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: mac_addr_cache.wr */ + /* class_tid: 2, , table: mac_addr_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -11383,7 +11351,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ + /* class_tid: 2, , table: profile_tcam.ipv4 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -11529,7 +11497,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ + /* class_tid: 2, , table: profile_tcam.ipv6 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -11675,7 +11643,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */ + /* class_tid: 2, , table: profile_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -11711,14 +11679,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }, { .description = "flow_sig_id", - .field_bit_size = 32, + .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, - /* class_tid: 2, wh_plus, table: em.ipv4 */ + /* class_tid: 2, , table: em.ipv4 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11780,7 +11748,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, wh_plus, table: eem.ipv4 */ + /* class_tid: 2, , table: eem.ipv4 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11848,7 +11816,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, wh_plus, table: em.ipv6 */ + /* class_tid: 2, , table: em.ipv6 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11910,7 +11878,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, wh_plus, table: eem.ipv6 */ + /* class_tid: 2, , table: eem.ipv6 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11978,7 +11946,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, wh_plus, table: int_full_act_record.ing_0 */ + /* class_tid: 3, , table: int_full_act_record.ing_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12138,7 +12106,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -12228,7 +12196,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.ing_wr */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ { .description = "rid", .field_bit_size = 32, @@ -12262,7 +12230,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.ing_0 */ + /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12272,7 +12240,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.ing_0 */ + /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12282,7 +12250,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.ing_0 */ + /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12292,7 +12260,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: int_full_act_record.egr_vfr */ + /* class_tid: 3, , table: int_full_act_record.egr_vfr */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12452,7 +12420,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.egr_vfr */ + /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -12540,7 +12508,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr_vfr */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .description = "rid", .field_bit_size = 32, @@ -12571,7 +12539,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -12661,7 +12629,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ { .description = "rid", .field_bit_size = 32, @@ -12695,7 +12663,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: int_full_act_record.egr_0 */ + /* class_tid: 3, , table: int_full_act_record.egr_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12855,7 +12823,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.egr_0 */ + /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12865,7 +12833,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.egr_0 */ + /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12875,7 +12843,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.egr_0 */ + /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12885,7 +12853,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: int_full_act_record.loopback */ + /* class_tid: 4, , table: int_full_act_record.loopback */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13045,7 +13013,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ + /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -13134,7 +13102,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vf_egr_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ { .description = "rid", .field_bit_size = 32, @@ -13168,7 +13136,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.vf_egr */ + /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13178,7 +13146,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.vf_egr */ + /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13188,7 +13156,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.vf_egr */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13198,7 +13166,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, wh_plus, table: int_full_act_record.vf_ing */ + /* class_tid: 4, , table: int_full_act_record.vf_ing */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13358,7 +13326,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vf_ing */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -13444,7 +13412,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_egr0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -13529,7 +13497,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { .description = "rid", .field_bit_size = 32, @@ -13560,7 +13528,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: int_vtag_encap_record.vfr_egr0 */ + /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -13643,7 +13611,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_egr0 */ + /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13806,7 +13774,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, wh_plus, table: int_full_act_record.vfr_ing0 */ + /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13968,7 +13936,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -14054,7 +14022,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -14143,21 +14111,21 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { }; struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */ { .description = "l2_cntxt_id", .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 42 }, - /* class_tid: 1, wh_plus, table: mac_addr_cache.rd */ + /* class_tid: 1, , table: mac_addr_cache.rd */ { .description = "l2_cntxt_id", .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 42 }, - /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 1, , table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14166,7 +14134,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */ + /* class_tid: 1, , table: profile_tcam_cache.rd */ { .description = "em_profile_id", .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, @@ -14176,7 +14144,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 32, + .ident_bit_size = 64, .ident_bit_pos = 58 }, { @@ -14185,7 +14153,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 32 }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */ + /* class_tid: 1, , table: profile_tcam.ipv4 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14194,7 +14162,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */ + /* class_tid: 1, , table: profile_tcam.ipv6 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14203,7 +14171,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_vxlan */ + /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14212,21 +14180,21 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ { .description = "l2_cntxt_id", .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 42 }, - /* class_tid: 2, wh_plus, table: mac_addr_cache.rd */ + /* class_tid: 2, , table: mac_addr_cache.rd */ { .description = "l2_cntxt_id", .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 42 }, - /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */ + /* class_tid: 2, , table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14235,7 +14203,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */ + /* class_tid: 2, , table: profile_tcam_cache.rd */ { .description = "em_profile_id", .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, @@ -14245,7 +14213,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { { .description = "flow_sig_id", .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .ident_bit_size = 32, + .ident_bit_size = 64, .ident_bit_pos = 58 }, { @@ -14254,7 +14222,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 32 }, - /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */ + /* class_tid: 2, , table: profile_tcam.ipv4 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14263,7 +14231,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */ + /* class_tid: 2, , table: profile_tcam.ipv6 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14272,7 +14240,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14281,7 +14249,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14290,7 +14258,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.vf_egr */ + /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,